1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used;
136 static arm_feature_set thumb_arch_used;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26 = FALSE;
140 static int atpcs = FALSE;
141 static int support_interwork = FALSE;
142 static int uses_apcs_float = FALSE;
143 static int pic_code = FALSE;
144 static int fix_v4bx = FALSE;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated = TRUE;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax = FALSE;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set *legacy_cpu = NULL;
158 static const arm_feature_set *legacy_fpu = NULL;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set *mcpu_cpu_opt = NULL;
162 static arm_feature_set *mcpu_ext_opt = NULL;
163 static const arm_feature_set *mcpu_fpu_opt = NULL;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set *march_cpu_opt = NULL;
167 static arm_feature_set *march_ext_opt = NULL;
168 static const arm_feature_set *march_fpu_opt = NULL;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set *mfpu_opt = NULL;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default = FPU_DEFAULT;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
176 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
179 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
182 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
184 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
187 static const arm_feature_set cpu_default = CPU_DEFAULT;
190 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
191 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
192 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
198 static const arm_feature_set arm_ext_v4t_5 =
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
210 static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212 static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214 static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216 static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
225 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
226 static const arm_feature_set arm_ext_m =
227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
229 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
234 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
235 static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
236 static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
238 static const arm_feature_set arm_ext_v8_1m_main =
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
243 static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
253 static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
258 static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
260 static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
262 static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
264 static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
266 static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
269 static const arm_feature_set arm_arch_any = ARM_ANY;
271 static const arm_feature_set fpu_any = FPU_ANY;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
277 static const arm_feature_set arm_cext_iwmmxt2 =
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
279 static const arm_feature_set arm_cext_iwmmxt =
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
281 static const arm_feature_set arm_cext_xscale =
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
283 static const arm_feature_set arm_cext_maverick =
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285 static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287 static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
289 static const arm_feature_set fpu_vfp_ext_v1xd =
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291 static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293 static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295 static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297 static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
299 static const arm_feature_set fpu_vfp_ext_d32 =
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301 static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
305 static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307 static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
310 static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312 static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
315 static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
317 static const arm_feature_set fpu_vfp_ext_armv8 =
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
319 static const arm_feature_set fpu_vfp_ext_armv8xd =
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
321 static const arm_feature_set fpu_neon_ext_armv8 =
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
323 static const arm_feature_set fpu_crypto_ext_armv8 =
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
325 static const arm_feature_set crc_ext_armv8 =
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
327 static const arm_feature_set fpu_neon_ext_v8_1 =
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
329 static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
332 static int mfloat_abi_opt = -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch = ARM_ARCH_NONE;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext = ARM_ARCH_NONE;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu = FPU_NONE;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name[20];
350 extern FLONUM_TYPE generic_floating_point_number;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
361 static int meabi_flags = EABI_DEFAULT;
363 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
366 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS * GOT_symbol;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode = 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
398 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax = FALSE;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars[] = "#[]{}";
444 enum neon_el_type type;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type;
500 } relocs[ARM_IT_MAX_RELOCS];
502 enum pred_instruction_type pred_insn_type;
508 struct neon_type_el vectype;
509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad : 1; /* Operand is SIMD quad register. */
524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
525 unsigned iszr : 1; /* Operand is ZR register. */
526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
533 } operands[ARM_IT_MAX_OPERANDS];
536 static struct arm_it inst;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name;
569 #define COND_ALWAYS 0xE
573 const char * template_name;
577 struct asm_barrier_opt
579 const char * template_name;
581 const arm_feature_set arch;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc;
601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined;
618 struct neon_type_el eltype;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs[] =
669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name;
711 /* Parameters to instruction. */
712 unsigned int operands[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control * arm_ops_hsh;
906 static struct hash_control * arm_cond_hsh;
907 static struct hash_control * arm_vcond_hsh;
908 static struct hash_control * arm_shift_hsh;
909 static struct hash_control * arm_psr_hsh;
910 static struct hash_control * arm_v7m_psr_hsh;
911 static struct hash_control * arm_reg_hsh;
912 static struct hash_control * arm_reloc_hsh;
913 static struct hash_control * arm_barrier_opt_hsh;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS * last_label_seen;
925 static int label_is_thumb_function_name = FALSE;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
942 struct literal_pool * next;
943 unsigned int alignment;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool * list_of_pools = NULL;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME,
956 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred;
965 now_pred_compatible (int cond)
967 return (cond & ~1) == (now_pred.cc & ~1);
971 conditional_insn (void)
973 return inst.cond != COND_ALWAYS;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars[] = "#";
1027 char arm_line_separator_chars[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str, char c)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS * sp)
1071 if (symbol_get_value_expression (sp)->X_op == O_big)
1074 if (symbol_get_value_expression (sp)->X_add_symbol)
1076 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1077 || (symbol_get_value_expression (sp)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1084 static bfd_boolean in_my_get_expression = FALSE;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1104 switch (prefix_mode)
1106 case GE_NO_PREFIX: break;
1108 if (!is_immediate_prefix (**str))
1110 inst.error = _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG:
1117 if (is_immediate_prefix (**str))
1124 memset (ep, 0, sizeof (expressionS));
1126 save_in = input_line_pointer;
1127 input_line_pointer = *str;
1128 in_my_get_expression = TRUE;
1130 in_my_get_expression = FALSE;
1132 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str = input_line_pointer;
1136 input_line_pointer = save_in;
1137 if (inst.error == NULL)
1138 inst.error = (ep->X_op == O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode != GE_OPT_PREFIX_BIG
1147 && (ep->X_op == O_big
1148 || (ep->X_add_symbol
1149 && (walk_no_bignums (ep->X_add_symbol)
1151 && walk_no_bignums (ep->X_op_symbol))))))
1153 inst.error = _("invalid constant");
1154 *str = input_line_pointer;
1155 input_line_pointer = save_in;
1159 *str = input_line_pointer;
1160 input_line_pointer = save_in;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type, char * litP, int * sizeP)
1182 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t = atof_ieee (input_line_pointer, type, words);
1219 input_line_pointer = t;
1220 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1222 if (target_big_endian)
1224 for (i = 0; i < prec; i++)
1226 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1227 litP += sizeof (LITTLENUM_TYPE);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1233 for (i = prec - 1; i >= 0; i--)
1235 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1236 litP += sizeof (LITTLENUM_TYPE);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i = 0; i < prec; i += 2)
1243 md_number_to_chars (litP, (valueT) words[i + 1],
1244 sizeof (LITTLENUM_TYPE));
1245 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1246 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1247 litP += 2 * sizeof (LITTLENUM_TYPE);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS * exp)
1260 if (in_my_get_expression)
1261 exp->X_op = O_illegal;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val)
1275 exp.X_op = O_illegal;
1277 if (is_immediate_prefix (*input_line_pointer))
1279 input_line_pointer++;
1283 if (exp.X_op != O_constant)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val = exp.X_add_number;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry *
1302 arm_reg_parse_multi (char **ccp)
1306 struct reg_entry *reg;
1308 skip_whitespace (start);
1310 #ifdef REGISTER_PREFIX
1311 if (*start != REGISTER_PREFIX)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start == OPTIONAL_REGISTER_PREFIX)
1321 if (!ISALPHA (*p) || !is_name_beginner (*p))
1326 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1328 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1338 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1339 enum arm_reg_type type)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg && reg->type == REG_TYPE_CN)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor = strtoul (start, ccp, 10);
1357 if (*ccp != start && processor <= 15)
1362 case REG_TYPE_MMXWC:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg && reg->type == REG_TYPE_MMXWCG)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp, enum arm_reg_type type)
1383 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1390 if (reg && reg->type == type)
1393 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type *type, char **str)
1422 while (type->elems < NEON_MAX_TYPE_ELS)
1424 enum neon_el_type thistype = NT_untyped;
1425 unsigned thissize = -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr))
1438 case 'i': thistype = NT_integer; break;
1439 case 'f': thistype = NT_float; break;
1440 case 'p': thistype = NT_poly; break;
1441 case 's': thistype = NT_signed; break;
1442 case 'u': thistype = NT_unsigned; break;
1444 thistype = NT_float;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype == NT_float && !ISDIGIT (*ptr))
1461 thissize = strtoul (ptr, &ptr, 10);
1463 if (thissize != 8 && thissize != 16 && thissize != 32
1466 as_bad (_("bad size %d in type specifier"), thissize);
1474 type->el[type->elems].type = thistype;
1475 type->el[type->elems].size = thissize;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type->elems == 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1506 struct neon_type optype;
1510 if (parse_neon_type (&optype, &str) == SUCCESS)
1512 if (optype.elems == 1)
1513 *vectype = optype.el[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set *feature)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set *feature)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1559 && ARM_CPU_IS_ANY (cpu_variant))
1561 first_error (BAD_MVE_AUTO);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1582 enum arm_reg_type *rtype,
1583 struct neon_typed_alias *typeinfo)
1586 struct reg_entry *reg = arm_reg_parse_multi (&str);
1587 struct neon_typed_alias atype;
1588 struct neon_type_el parsetype;
1592 atype.eltype.type = NT_invtype;
1593 atype.eltype.size = -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type == REG_TYPE_NDQ
1609 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1610 || (type == REG_TYPE_VFSD
1611 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1612 || (type == REG_TYPE_NSDQ
1613 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1614 || reg->type == REG_TYPE_NQ))
1615 || (type == REG_TYPE_NSD
1616 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1617 || (type == REG_TYPE_MMXWC
1618 && (reg->type == REG_TYPE_MMXWCG)))
1619 type = (enum arm_reg_type) reg->type;
1621 if (type == REG_TYPE_MQ)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1626 if (!reg || reg->type != REG_TYPE_NQ)
1629 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1637 && (type == REG_TYPE_NQ))
1641 if (type != reg->type)
1647 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1649 if ((atype.defined & NTA_HASTYPE) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype.defined |= NTA_HASTYPE;
1655 atype.eltype = parsetype;
1658 if (skip_past_char (&str, '[') == SUCCESS)
1660 if (type != REG_TYPE_VFD
1661 && !(type == REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1663 && !(type == REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype.defined & NTA_HASINDEX) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype.defined |= NTA_HASINDEX;
1681 if (skip_past_char (&str, ']') == SUCCESS)
1682 atype.index = NEON_ALL_LANES;
1687 my_get_expression (&exp, &str, GE_NO_PREFIX);
1689 if (exp.X_op != O_constant)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str, ']') == FAIL)
1698 atype.index = exp.X_add_number;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1722 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1724 struct neon_typed_alias atype;
1726 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype.defined & NTA_HASINDEX) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype = atype.eltype;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1759 arm_reg_type reg_type)
1763 struct neon_typed_alias atype;
1766 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1784 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1787 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
1789 first_error (_("scalar must have an index"));
1792 else if (atype.index >= reg_size / elsize)
1794 first_error (_("scalar index out of range"));
1799 *type = atype.eltype;
1803 return reg * 16 + atype.index;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp, enum reg_list_els etype)
1828 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str);
1846 const char apsr_str[] = "apsr";
1847 int apsr_str_len = strlen (apsr_str);
1849 reg = arm_reg_parse (&str, REGLIST_RN);
1850 if (etype == REGLIST_CLRM)
1852 if (reg == REG_SP || reg == REG_PC)
1854 else if (reg == FAIL
1855 && !strncasecmp (str, apsr_str, apsr_str_len)
1856 && !ISALPHA (*(str + apsr_str_len)))
1859 str += apsr_str_len;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs[REGLIST_RN]));
1883 first_error (_("bad range in register list"));
1887 for (i = cur_reg + 1; i < reg; i++)
1889 if (range & (1 << i))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range & (1 << reg))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg <= cur_reg)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str) != FAIL
1909 || (in_range = 1, *str++ == '-'));
1912 if (skip_past_char (&str, '}') == FAIL)
1914 first_error (_("missing `}'"));
1918 else if (etype == REGLIST_RN)
1922 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1925 if (exp.X_op == O_constant)
1927 if (exp.X_add_number
1928 != (exp.X_add_number & 0x0000ffff))
1930 inst.error = _("invalid register mask");
1934 if ((range & exp.X_add_number) != 0)
1936 int regno = range & exp.X_add_number;
1939 regno = (1 << regno) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range |= exp.X_add_number;
1949 if (inst.relocs[0].type != 0)
1951 inst.error = _("expression too complex");
1955 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1956 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1957 inst.relocs[0].pc_rel = 0;
1961 if (*str == '|' || *str == '+')
1967 while (another_range);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
1990 bfd_boolean *partial_match)
1995 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1999 unsigned long mask = 0;
2001 bfd_boolean vpr_seen = FALSE;
2002 bfd_boolean expect_vpr =
2003 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
2005 if (skip_past_char (&str, '{') == FAIL)
2007 inst.error = _("expecting {");
2014 case REGLIST_VFP_S_VPR:
2015 regtype = REG_TYPE_VFS;
2020 case REGLIST_VFP_D_VPR:
2021 regtype = REG_TYPE_VFD;
2024 case REGLIST_NEON_D:
2025 regtype = REG_TYPE_NDQ;
2032 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2049 base_reg = max_regs;
2050 *partial_match = FALSE;
2054 int setmask = 1, addregs = 1;
2055 const char vpr_str[] = "vpr";
2056 int vpr_str_len = strlen (vpr_str);
2058 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
2062 if (new_base == FAIL
2063 && !strncasecmp (str, vpr_str, vpr_str_len)
2064 && !ISALPHA (*(str + vpr_str_len))
2070 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base == FAIL)
2079 if (regtype == REG_TYPE_VFS)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base == FAIL)
2090 first_error (_(reg_expected_msgs[regtype]));
2094 *partial_match = TRUE;
2098 if (new_base >= max_regs)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype == REG_TYPE_NQ)
2111 if (new_base < base_reg)
2112 base_reg = new_base;
2114 if (mask & (setmask << new_base))
2116 first_error (_("invalid register list"));
2120 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask |= setmask << new_base;
2129 if (*str == '-') /* We have the start of a range expression */
2135 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
2138 inst.error = gettext (reg_expected_msgs[regtype]);
2142 if (high_range >= max_regs)
2144 first_error (_("register out of range in list"));
2148 if (regtype == REG_TYPE_NQ)
2149 high_range = high_range + 1;
2151 if (high_range <= new_base)
2153 inst.error = _("register range not in ascending order");
2157 for (new_base += addregs; new_base <= high_range; new_base += addregs)
2159 if (mask & (setmask << new_base))
2161 inst.error = _("invalid register list");
2165 mask |= setmask << new_base;
2170 while (skip_past_comma (&str) != FAIL);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen && count == 0) || count > max_regs)
2180 if (expect_vpr && !vpr_seen)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i = 0; i < count; i++)
2190 if ((mask & (1u << i)) == 0)
2192 inst.error = _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2213 if (a->defined != b->defined)
2216 if ((a->defined & NTA_HASTYPE) != 0
2217 && (a->eltype.type != b->eltype.type
2218 || a->eltype.size != b->eltype.size))
2221 if ((a->defined & NTA_HASINDEX) != 0
2222 && (a->index != b->index))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str, unsigned *pbase,
2243 struct neon_type_el *eltype)
2250 int leading_brace = 0;
2251 enum arm_reg_type rtype = REG_TYPE_NDQ;
2252 const char *const incr_error = mve ? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error = _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype;
2256 firsttype.defined = 0;
2257 firsttype.eltype.type = NT_invtype;
2258 firsttype.eltype.size = -1;
2259 firsttype.index = -1;
2261 if (skip_past_char (&ptr, '{') == SUCCESS)
2266 struct neon_typed_alias atype;
2268 rtype = REG_TYPE_MQ;
2269 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2273 first_error (_(reg_expected_msgs[rtype]));
2280 if (rtype == REG_TYPE_NQ)
2286 else if (reg_incr == -1)
2288 reg_incr = getreg - base_reg;
2289 if (reg_incr < 1 || reg_incr > 2)
2291 first_error (_(incr_error));
2295 else if (getreg != base_reg + reg_incr * count)
2297 first_error (_(incr_error));
2301 if (! neon_alias_types_same (&atype, &firsttype))
2303 first_error (_(type_error));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype;
2312 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2314 lane = NEON_INTERLEAVE_LANES;
2315 else if (lane != NEON_INTERLEAVE_LANES)
2317 first_error (_(type_error));
2322 else if (reg_incr != 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2331 first_error (_(reg_expected_msgs[rtype]));
2334 if (! neon_alias_types_same (&htype, &firsttype))
2336 first_error (_(type_error));
2339 count += hireg + dregs - getreg;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype == REG_TYPE_NQ)
2350 if ((atype.defined & NTA_HASINDEX) != 0)
2354 else if (lane != atype.index)
2356 first_error (_(type_error));
2360 else if (lane == -1)
2361 lane = NEON_INTERLEAVE_LANES;
2362 else if (lane != NEON_INTERLEAVE_LANES)
2364 first_error (_(type_error));
2369 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane = NEON_INTERLEAVE_LANES;
2376 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
2377 || (count > 1 && reg_incr == -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2385 first_error (_("expected }"));
2393 *eltype = firsttype.eltype;
2398 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str)
2410 struct reloc_entry *r;
2414 return BFD_RELOC_UNUSED;
2419 while (*q && *q != ')' && *q != ',')
2424 if ((r = (struct reloc_entry *)
2425 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2432 /* Directives: register aliases. */
2434 static struct reg_entry *
2435 insert_reg_alias (char *str, unsigned number, int type)
2437 struct reg_entry *new_reg;
2440 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2442 if (new_reg->builtin)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg->number != number || new_reg->type != type)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2453 name = xstrdup (str);
2454 new_reg = XNEW (struct reg_entry);
2456 new_reg->name = name;
2457 new_reg->number = number;
2458 new_reg->type = type;
2459 new_reg->builtin = FALSE;
2460 new_reg->neon = NULL;
2462 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2469 insert_neon_reg_alias (char *str, int number, int type,
2470 struct neon_typed_alias *atype)
2472 struct reg_entry *reg = insert_reg_alias (str, number, type);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg->neon = XNEW (struct neon_typed_alias);
2483 *reg->neon = *atype;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname, char *p)
2497 struct reg_entry *old;
2498 char *oldname, *nbuf;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname, " .req ", 6) != 0)
2508 if (*oldname == '\0')
2511 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname = original_case_string;
2525 nlen = strlen (newname);
2528 nbuf = xmemdup0 (newname, nlen);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2535 for (p = nbuf; *p; p++)
2538 if (strncmp (nbuf, newname, nlen))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2556 for (p = nbuf; *p; p++)
2559 if (strncmp (nbuf, newname, nlen))
2560 insert_reg_alias (nbuf, old->number, old->type);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname, char *p)
2580 enum arm_reg_type basetype;
2581 struct reg_entry *basereg;
2582 struct reg_entry mybasereg;
2583 struct neon_type ntype;
2584 struct neon_typed_alias typeinfo;
2585 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2588 typeinfo.defined = 0;
2589 typeinfo.eltype.type = NT_invtype;
2590 typeinfo.eltype.size = -1;
2591 typeinfo.index = -1;
2595 if (strncmp (p, " .dn ", 5) == 0)
2596 basetype = REG_TYPE_VFD;
2597 else if (strncmp (p, " .qn ", 5) == 0)
2598 basetype = REG_TYPE_NQ;
2607 basereg = arm_reg_parse_multi (&p);
2609 if (basereg && basereg->type != basetype)
2611 as_bad (_("bad type for register"));
2615 if (basereg == NULL)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp, &p, GE_NO_PREFIX);
2620 if (exp.X_op != O_constant)
2622 as_bad (_("expression must be constant"));
2625 basereg = &mybasereg;
2626 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2632 typeinfo = *basereg->neon;
2634 if (parse_neon_type (&ntype, &p) == SUCCESS)
2636 /* We got a type. */
2637 if (typeinfo.defined & NTA_HASTYPE)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo.defined |= NTA_HASTYPE;
2644 if (ntype.elems != 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo.eltype = ntype.el[0];
2652 if (skip_past_char (&p, '[') == SUCCESS)
2655 /* We got a scalar index. */
2657 if (typeinfo.defined & NTA_HASINDEX)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp, &p, GE_NO_PREFIX);
2665 if (exp.X_op != O_constant)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo.defined |= NTA_HASINDEX;
2672 typeinfo.index = exp.X_add_number;
2674 if (skip_past_char (&p, ']') == FAIL)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen = nameend - newname;
2687 newname = original_case_string;
2688 namelen = strlen (newname);
2691 namebuf = xmemdup0 (newname, namelen);
2693 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2694 typeinfo.defined != 0 ? &typeinfo : NULL);
2696 /* Insert name in all uppercase. */
2697 for (p = namebuf; *p; p++)
2700 if (strncmp (namebuf, newname, namelen))
2701 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2702 typeinfo.defined != 0 ? &typeinfo : NULL);
2704 /* Insert name in all lowercase. */
2705 for (p = namebuf; *p; p++)
2708 if (strncmp (namebuf, newname, namelen))
2709 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2710 typeinfo.defined != 0 ? &typeinfo : NULL);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED)
2749 name = input_line_pointer;
2751 while (*input_line_pointer != 0
2752 && *input_line_pointer != ' '
2753 && *input_line_pointer != '\n')
2754 ++input_line_pointer;
2756 saved_char = *input_line_pointer;
2757 *input_line_pointer = 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2767 as_bad (_("unknown register alias '%s'"), name);
2768 else if (reg->builtin)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh, name, FALSE);
2777 free ((char *) reg->name);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf = strdup (name);
2787 for (p = nbuf; *p; p++)
2789 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2792 hash_delete (arm_reg_hsh, nbuf, FALSE);
2793 free ((char *) reg->name);
2799 for (p = nbuf; *p; p++)
2801 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2804 hash_delete (arm_reg_hsh, nbuf, FALSE);
2805 free ((char *) reg->name);
2815 *input_line_pointer = saved_char;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2833 const char * symname;
2840 type = BSF_NO_FLAGS;
2844 type = BSF_NO_FLAGS;
2848 type = BSF_NO_FLAGS;
2854 symbolP = symbol_new (symname, now_seg, value, frag);
2855 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2860 THUMB_SET_FUNC (symbolP, 0);
2861 ARM_SET_THUMB (symbolP, 0);
2862 ARM_SET_INTERWORK (symbolP, support_interwork);
2866 THUMB_SET_FUNC (symbolP, 1);
2867 ARM_SET_THUMB (symbolP, 1);
2868 ARM_SET_INTERWORK (symbolP, support_interwork);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag->tc_frag_data.first_map != NULL)
2889 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2890 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2892 frag->tc_frag_data.first_map = symbolP;
2894 if (frag->tc_frag_data.last_map != NULL)
2896 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2897 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2898 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2900 frag->tc_frag_data.last_map = symbolP;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state,
2909 valueT value, fragS *frag, offsetT bytes)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag->tc_frag_data.last_map != NULL
2913 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2915 symbolS *symp = frag->tc_frag_data.last_map;
2919 know (frag->tc_frag_data.first_map == symp);
2920 frag->tc_frag_data.first_map = NULL;
2922 frag->tc_frag_data.last_map = NULL;
2923 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2926 make_mapping_symbol (MAP_DATA, value, frag);
2927 make_mapping_symbol (state, value + bytes, frag);
2930 static void mapping_state_2 (enum mstate state, int max_chars);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state)
2939 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2941 if (mapstate == state)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state == MAP_ARM || state == MAP_THUMB)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state, int max_chars)
2975 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2977 if (!SEG_NORMAL (now_seg))
2980 if (mapstate == state)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2986 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2988 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2989 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2995 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2996 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS * symbolP)
3011 const char * name = S_GET_NAME (symbolP);
3012 symbolS * new_target;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP) || name[0] == '.')
3028 real_start = concat (STUB_NAME, name, NULL);
3029 new_target = symbol_find (real_start);
3032 if (new_target == NULL)
3034 as_warn (_("Failed to find real start of function: %s\n"), name);
3035 new_target = symbolP;
3043 opcode_select (int width)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width);
3081 s_arm (int ignore ATTRIBUTE_UNUSED)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED)
3099 temp = get_absolute_expression ();
3104 opcode_select (temp);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name = TRUE;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim = get_symbol_name (& name);
3157 end_name = input_line_pointer;
3158 (void) restore_line_pointer (delim);
3160 if (*input_line_pointer != ',')
3163 as_bad (_("expected comma after name \"%s\""), name);
3165 ignore_rest_of_line ();
3169 input_line_pointer++;
3172 if (name[0] == '.' && name[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP = symbol_find (name)) == NULL
3179 && (symbolP = md_undefined_symbol (name)) == NULL)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing & LISTING_SYMBOLS)
3187 extern struct list_info_struct * listing_tail;
3188 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
3190 memset (dummy_frag, 0, sizeof (fragS));
3191 dummy_frag->fr_type = rs_fill;
3192 dummy_frag->line = listing_tail;
3193 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3194 dummy_frag->fr_symbol = symbolP;
3198 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP);
3211 && S_IS_DEFINED (symbolP)
3212 && S_GET_SEGMENT (symbolP) != reg_section)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3215 pseudo_set (symbolP);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP, 1);
3222 ARM_SET_THUMB (symbolP, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP, support_interwork);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED)
3238 delim = get_symbol_name (& name);
3240 if (!strcasecmp (name, "unified"))
3241 unified_syntax = TRUE;
3242 else if (!strcasecmp (name, "divided"))
3243 unified_syntax = FALSE;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name);
3249 (void) restore_line_pointer (delim);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3286 if (codecomposer_syntax)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name)
3297 static const char * last_name = NULL;
3301 gas_assert (last_name == NULL);
3304 if (debug_type == DEBUG_STABS)
3305 stabs_generate_asm_func (name, name);
3309 gas_assert (last_name != NULL);
3311 if (debug_type == DEBUG_STABS)
3312 stabs_generate_asm_endfunc (last_name, last_name);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3321 if (codecomposer_syntax)
3323 switch (asmfunc_state)
3325 case OUTSIDE_ASMFUNC:
3326 asmfunc_state = WAITING_ASMFUNC_NAME;
3329 case WAITING_ASMFUNC_NAME:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3346 if (codecomposer_syntax)
3348 switch (asmfunc_state)
3350 case OUTSIDE_ASMFUNC:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC:
3359 asmfunc_state = OUTSIDE_ASMFUNC;
3360 asmfunc_debug (NULL);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name)
3372 if (codecomposer_syntax)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool *
3381 find_literal_pool (void)
3383 literal_pool * pool;
3385 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3387 if (pool->section == now_seg
3388 && pool->sub_section == now_subseg)
3395 static literal_pool *
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num = 1;
3400 literal_pool * pool;
3402 pool = find_literal_pool ();
3406 /* Create a new pool. */
3407 pool = XNEW (literal_pool);
3411 pool->next_free_entry = 0;
3412 pool->section = now_seg;
3413 pool->sub_section = now_subseg;
3414 pool->next = list_of_pools;
3415 pool->symbol = NULL;
3416 pool->alignment = 2;
3418 /* Add it to the list. */
3419 list_of_pools = pool;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool->symbol == NULL)
3425 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3426 (valueT) 0, &zero_address_frag);
3427 pool->id = latest_pool_num ++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool * pool;
3443 unsigned int entry, pool_size = 0;
3444 bfd_boolean padding_slot_p = FALSE;
3450 imm1 = inst.operands[1].imm;
3451 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3452 : inst.relocs[0].exp.X_unsigned ? 0
3453 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3454 if (target_big_endian)
3457 imm2 = inst.operands[1].imm;
3461 pool = find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry = 0; entry < pool->next_free_entry; entry ++)
3468 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3469 && (inst.relocs[0].exp.X_op == O_constant)
3470 && (pool->literals[entry].X_add_number
3471 == inst.relocs[0].exp.X_add_number)
3472 && (pool->literals[entry].X_md == nbytes)
3473 && (pool->literals[entry].X_unsigned
3474 == inst.relocs[0].exp.X_unsigned))
3477 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3478 && (inst.relocs[0].exp.X_op == O_symbol)
3479 && (pool->literals[entry].X_add_number
3480 == inst.relocs[0].exp.X_add_number)
3481 && (pool->literals[entry].X_add_symbol
3482 == inst.relocs[0].exp.X_add_symbol)
3483 && (pool->literals[entry].X_op_symbol
3484 == inst.relocs[0].exp.X_op_symbol)
3485 && (pool->literals[entry].X_md == nbytes))
3488 else if ((nbytes == 8)
3489 && !(pool_size & 0x7)
3490 && ((entry + 1) != pool->next_free_entry)
3491 && (pool->literals[entry].X_op == O_constant)
3492 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3493 && (pool->literals[entry].X_unsigned
3494 == inst.relocs[0].exp.X_unsigned)
3495 && (pool->literals[entry + 1].X_op == O_constant)
3496 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3497 && (pool->literals[entry + 1].X_unsigned
3498 == inst.relocs[0].exp.X_unsigned))
3501 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3502 if (padding_slot_p && (nbytes == 4))
3508 /* Do we need to create a new entry? */
3509 if (entry == pool->next_free_entry)
3511 if (entry >= MAX_LITERAL_POOL_SIZE)
3513 inst.error = _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst.relocs[0].exp.X_op == O_constant
3531 || inst.relocs[0].exp.X_op == O_big))
3533 inst.error = _("invalid type for literal pool");
3536 else if (pool_size & 0x7)
3538 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3540 inst.error = _("literal pool overflow");
3544 pool->literals[entry] = inst.relocs[0].exp;
3545 pool->literals[entry].X_op = O_constant;
3546 pool->literals[entry].X_add_number = 0;
3547 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3548 pool->next_free_entry += 1;
3551 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3553 inst.error = _("literal pool overflow");
3557 pool->literals[entry] = inst.relocs[0].exp;
3558 pool->literals[entry].X_op = O_constant;
3559 pool->literals[entry].X_add_number = imm1;
3560 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3561 pool->literals[entry++].X_md = 4;
3562 pool->literals[entry] = inst.relocs[0].exp;
3563 pool->literals[entry].X_op = O_constant;
3564 pool->literals[entry].X_add_number = imm2;
3565 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3566 pool->literals[entry].X_md = 4;
3567 pool->alignment = 3;
3568 pool->next_free_entry += 1;
3572 pool->literals[entry] = inst.relocs[0].exp;
3573 pool->literals[entry].X_md = 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type == DEBUG_DWARF2)
3582 dwarf2_where (pool->locs + entry);
3584 pool->next_free_entry += 1;
3586 else if (padding_slot_p)
3588 pool->literals[entry] = inst.relocs[0].exp;
3589 pool->literals[entry].X_md = nbytes;
3592 inst.relocs[0].exp.X_op = O_symbol;
3593 inst.relocs[0].exp.X_add_number = pool_size;
3594 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret = TRUE;
3604 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3606 const char *label = input_line_pointer;
3608 while (!is_end_of_line[(int) label[-1]])
3613 as_bad (_("Invalid label '%s'"), label);
3617 asmfunc_debug (label);
3619 asmfunc_state = WAITING_ENDASMFUNC;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS * symbolP,
3630 const char * name, /* It is copied, the caller can modify. */
3631 segT segment, /* Segment identifier (SEG_<something>). */
3632 valueT valu, /* Symbol value. */
3633 fragS * frag) /* Associated fragment. */
3636 char * preserved_copy_of_name;
3638 name_length = strlen (name) + 1; /* +1 for \0. */
3639 obstack_grow (¬es, name, name_length);
3640 preserved_copy_of_name = (char *) obstack_finish (¬es);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name =
3644 tc_canonicalize_symbol_name (preserved_copy_of_name);
3647 S_SET_NAME (symbolP, preserved_copy_of_name);
3649 S_SET_SEGMENT (symbolP, segment);
3650 S_SET_VALUE (symbolP, valu);
3651 symbol_clear_list_pointers (symbolP);
3653 symbol_set_frag (symbolP, frag);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen;
3659 if (symbol_table_frozen)
3663 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3665 obj_symbol_new_hook (symbolP);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP);
3672 verify_symbol_chain (symbol_rootP, symbol_lastP);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3680 literal_pool * pool;
3683 pool = find_literal_pool ();
3685 || pool->symbol == NULL
3686 || pool->next_free_entry == 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool->alignment, 0, 0);
3694 record_alignment (now_seg, 2);
3697 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3698 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3700 sprintf (sym_name, "$$lit_\002%x", pool->id);
3702 symbol_locate (pool->symbol, sym_name, now_seg,
3703 (valueT) frag_now_fix (), frag_now);
3704 symbol_table_insert (pool->symbol);
3706 ARM_SET_THUMB (pool->symbol, thumb_mode);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3712 for (entry = 0; entry < pool->next_free_entry; entry ++)
3715 if (debug_type == DEBUG_DWARF2)
3716 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool->literals[entry]),
3720 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3723 /* Mark the pool as empty. */
3724 pool->next_free_entry = 0;
3725 pool->symbol = NULL;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3732 static valueT create_unwind_entry (int);
3733 static void start_unwind_section (const segT, int);
3734 static void add_unwind_opcode (valueT, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes);
3758 mapping_state (MAP_DATA);
3762 char *base = input_line_pointer;
3766 if (exp.X_op != O_symbol)
3767 emit_expr (&exp, (unsigned int) nbytes);
3770 char *before_reloc = input_line_pointer;
3771 reloc = parse_reloc (&input_line_pointer);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc == BFD_RELOC_UNUSED)
3779 emit_expr (&exp, (unsigned int) nbytes);
3782 reloc_howto_type *howto = (reloc_howto_type *)
3783 bfd_reloc_type_lookup (stdoutput,
3784 (bfd_reloc_code_real_type) reloc);
3785 int size = bfd_get_reloc_size (howto);
3787 if (reloc == BFD_RELOC_ARM_PLT32)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc = BFD_RELOC_UNUSED;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto->name, nbytes);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p = input_line_pointer;
3807 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3809 memcpy (save_buf, base, input_line_pointer - base);
3810 memmove (base + (input_line_pointer - before_reloc),
3811 base, before_reloc - base);
3813 input_line_pointer = base + (input_line_pointer-before_reloc);
3815 memcpy (base, save_buf, p - base);
3817 offset = nbytes - size;
3818 p = frag_more (nbytes);
3819 memset (p, 0, nbytes);
3820 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3821 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3827 while (*input_line_pointer++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer --;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS * exp)
3840 expressionS exp_high = *exp;
3842 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3843 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3844 exp->X_add_number &= 0xffff;
3845 emit_expr (exp, (unsigned int) THUMB_SIZE);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode)
3853 if ((unsigned int) opcode < 0xe800u)
3855 else if ((unsigned int) opcode >= 0xe8000000u)
3862 emit_insn (expressionS *exp, int nbytes)
3866 if (exp->X_op == O_constant)
3871 size = thumb_insn_size (exp->X_add_number);
3875 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3888 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3889 emit_thumb32_expr (exp);
3891 emit_expr (exp, (unsigned int) size);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM);
3943 if (! emit_insn (& exp, nbytes))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer --;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3966 if (*input_line_pointer == '1')
3967 highbit = 0x80000000;
3968 else if (*input_line_pointer != '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer++;
3972 if (*input_line_pointer != ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA);
3989 md_number_to_chars (p, highbit, 4);
3990 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3991 BFD_RELOC_ARM_PREL31);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4003 demand_empty_rest_of_line ();
4004 if (unwind.proc_start)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind.proc_start = expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind.opcode_count = 0;
4015 unwind.table_entry = NULL;
4016 unwind.personality_routine = NULL;
4017 unwind.personality_index = -1;
4018 unwind.frame_size = 0;
4019 unwind.fp_offset = 0;
4020 unwind.fp_reg = REG_SP;
4022 unwind.sp_restored = 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4032 demand_empty_rest_of_line ();
4033 if (!unwind.proc_start)
4034 as_bad (MISSING_FNSTART);
4036 if (unwind.table_entry)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4050 unsigned int marked_pr_dependency;
4052 demand_empty_rest_of_line ();
4054 if (!unwind.proc_start)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind.table_entry == NULL)
4062 val = create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind.saved_seg, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg, 2);
4071 ptr = frag_more (8);
4073 where = frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4077 BFD_RELOC_ARM_PREL31);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
4083 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4084 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4086 static const char *const name[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4093 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
4094 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
4095 |= 1 << unwind.personality_index;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr + 4, val, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4104 BFD_RELOC_ARM_PREL31);
4106 /* Restore the original section. */
4107 subseg_set (unwind.saved_seg, unwind.saved_subseg);
4109 unwind.proc_start = NULL;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4118 demand_empty_rest_of_line ();
4119 if (!unwind.proc_start)
4120 as_bad (MISSING_FNSTART);
4122 if (unwind.personality_routine || unwind.personality_index != -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind.personality_index = -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4136 if (!unwind.proc_start)
4137 as_bad (MISSING_FNSTART);
4139 if (unwind.personality_routine || unwind.personality_index != -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp.X_op != O_constant
4145 || exp.X_add_number < 0 || exp.X_add_number > 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind.personality_index = exp.X_add_number;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4165 if (!unwind.proc_start)
4166 as_bad (MISSING_FNSTART);
4168 if (unwind.personality_routine || unwind.personality_index != -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c = get_symbol_name (& name);
4172 p = input_line_pointer;
4174 ++ input_line_pointer;
4175 unwind.personality_routine = symbol_find_or_make (name);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind.sp_restored && unwind.fp_reg == 12
4204 && (range & 0x3000) == 0x1000)
4206 unwind.opcode_count--;
4207 unwind.sp_restored = 0;
4208 range = (range | 0x2000) & ~0x1000;
4209 unwind.pending_offset = 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n = 0; n < 8; n++)
4219 /* Break at the first non-saved register. */
4220 if ((range & (1 << (n + 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op = 0x8000 | ((range >> 4) & 0xfff);
4228 add_unwind_opcode (op, 2);
4232 /* Use the short form. */
4234 op = 0xa8; /* Pop r14. */
4236 op = 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op, 1);
4245 op = 0xb100 | (range & 0xf);
4246 add_unwind_opcode (op, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n = 0; n < 16; n++)
4252 if (range & (1 << n))
4253 unwind.frame_size += 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer) != FAIL)
4271 exp.X_op = O_illegal;
4273 if (exp.X_op != O_constant)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs = exp.X_add_number;
4282 if (num_regs < 1 || num_regs > 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op = 0xb4 | (num_regs - 1);
4295 add_unwind_opcode (op, 1);
4300 op = 0xc800 | (reg << 4) | (num_regs - 1);
4301 add_unwind_opcode (op, 2);
4303 unwind.frame_size += num_regs * 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs = 0;
4316 int num_regs_below_16;
4317 bfd_boolean partial_match;
4319 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs = count;
4336 else if (start + count > 16)
4337 num_vfpv3_regs = start + count - 16;
4339 if (num_vfpv3_regs > 0)
4341 int start_offset = start > 16 ? start - 16 : 0;
4342 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4343 add_unwind_opcode (op, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4348 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4349 if (num_regs_below_16 > 0)
4351 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4352 add_unwind_opcode (op, 2);
4355 unwind.frame_size += count * 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match;
4369 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op = 0xb8 | (count - 1);
4384 add_unwind_opcode (op, 1);
4389 op = 0xb300 | (reg << 4) | (count - 1);
4390 add_unwind_opcode (op, 2);
4392 unwind.frame_size += count * 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer == '{')
4408 input_line_pointer++;
4412 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4416 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer == '-')
4426 input_line_pointer++;
4427 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4430 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4433 else if (reg >= hi_reg)
4435 as_bad (_("bad register range"));
4438 for (; reg < hi_reg; reg++)
4442 while (skip_past_comma (&input_line_pointer) != FAIL);
4444 skip_past_char (&input_line_pointer, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i = 0; i < 16; i++)
4454 if (mask & (1 << i))
4455 unwind.frame_size += 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind.opcode_count > 0)
4463 i = unwind.opcodes[unwind.opcode_count - 1];
4464 if ((i & 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask & 0xfe00) == (1 << 9))
4472 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4473 unwind.opcode_count--;
4476 else if (i == 6 && unwind.opcode_count >= 2)
4478 i = unwind.opcodes[unwind.opcode_count - 2];
4482 op = 0xffff << (reg - 1);
4484 && ((mask & op) == (1u << (reg - 1))))
4486 op = (1 << (reg + i + 1)) - 1;
4487 op &= ~((1 << reg) - 1);
4489 unwind.opcode_count -= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg = 15; reg >= -1; reg--)
4500 /* Save registers in blocks. */
4502 || !(mask & (1 << reg)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op = 0xc0 | (hi_reg - 10);
4512 add_unwind_opcode (op, 1);
4517 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4518 add_unwind_opcode (op, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer == '{')
4539 input_line_pointer++;
4541 skip_whitespace (input_line_pointer);
4545 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4549 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer == '-')
4560 input_line_pointer++;
4561 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4564 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4567 else if (reg >= hi_reg)
4569 as_bad (_("bad register range"));
4572 for (; reg < hi_reg; reg++)
4576 while (skip_past_comma (&input_line_pointer) != FAIL);
4578 skip_past_char (&input_line_pointer, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg = 0; reg < 16; reg++)
4588 if (mask & (1 << reg))
4589 unwind.frame_size += 4;
4592 add_unwind_opcode (op, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6)
4606 struct reg_entry *reg;
4607 bfd_boolean had_brace = FALSE;
4609 if (!unwind.proc_start)
4610 as_bad (MISSING_FNSTART);
4612 /* Figure out what sort of save we have. */
4613 peek = input_line_pointer;
4621 reg = arm_reg_parse_multi (&peek);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer = peek;
4640 s_arm_unwind_save_fpa (reg->number);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4678 if (!unwind.proc_start)
4679 as_bad (MISSING_FNSTART);
4681 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4684 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer) != FAIL)
4692 if (immediate_for_directive (&offset) == FAIL)
4698 demand_empty_rest_of_line ();
4700 if (reg == REG_SP || reg == REG_PC)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind.fp_reg != REG_SP)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op, 1);
4713 /* Record the information for later. */
4714 unwind.fp_reg = reg;
4715 unwind.fp_offset = unwind.frame_size - offset;
4716 unwind.sp_restored = 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4726 if (!unwind.proc_start)
4727 as_bad (MISSING_FNSTART);
4729 if (immediate_for_directive (&offset) == FAIL)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind.frame_size += offset;
4741 unwind.pending_offset += offset;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4755 if (!unwind.proc_start)
4756 as_bad (MISSING_FNSTART);
4758 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4759 if (skip_past_comma (&input_line_pointer) == FAIL)
4762 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4764 if (fp_reg == FAIL || sp_reg == FAIL)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer) != FAIL)
4774 if (immediate_for_directive (&offset) == FAIL)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind.fp_reg = fp_reg;
4792 if (sp_reg == REG_SP)
4793 unwind.fp_offset = unwind.frame_size - offset;
4795 unwind.fp_offset -= offset;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4804 /* This is an arbitrary limit. */
4805 unsigned char op[16];
4808 if (!unwind.proc_start)
4809 as_bad (MISSING_FNSTART);
4812 if (exp.X_op == O_constant
4813 && skip_past_comma (&input_line_pointer) != FAIL)
4815 unwind.frame_size += exp.X_add_number;
4819 exp.X_op = O_illegal;
4821 if (exp.X_op != O_constant)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op[count++] = exp.X_add_number;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer) == FAIL)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op[count], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4866 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4868 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4869 attributes_set_explicitly[tag] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p = obstack_next_free (&frchain_now->frch_obstack);
4891 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4892 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4913 if (exp.X_op == O_symbol)
4914 exp.X_op = O_secrel;
4916 emit_expr (&exp, 4);
4918 while (*input_line_pointer++ == ',');
4920 input_line_pointer--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq, 0 },
4939 { "bss", s_bss, 0 },
4940 { "align", s_align_ptwo, 2 },
4941 { "arm", s_arm, 0 },
4942 { "thumb", s_thumb, 0 },
4943 { "code", s_code, 0 },
4944 { "force_thumb", s_force_thumb, 0 },
4945 { "thumb_func", s_thumb_func, 0 },
4946 { "thumb_set", s_thumb_set, 0 },
4947 { "even", s_even, 0 },
4948 { "ltorg", s_ltorg, 0 },
4949 { "pool", s_ltorg, 0 },
4950 { "syntax", s_syntax, 0 },
4951 { "cpu", s_arm_cpu, 0 },
4952 { "arch", s_arm_arch, 0 },
4953 { "object_arch", s_arm_object_arch, 0 },
4954 { "fpu", s_arm_fpu, 0 },
4955 { "arch_extension", s_arm_arch_extension, 0 },
4957 { "word", s_arm_elf_cons, 4 },
4958 { "long", s_arm_elf_cons, 4 },
4959 { "inst.n", s_arm_elf_inst, 2 },
4960 { "inst.w", s_arm_elf_inst, 4 },
4961 { "inst", s_arm_elf_inst, 0 },
4962 { "rel31", s_arm_rel31, 0 },
4963 { "fnstart", s_arm_unwind_fnstart, 0 },
4964 { "fnend", s_arm_unwind_fnend, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4966 { "personality", s_arm_unwind_personality, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4969 { "save", s_arm_unwind_save, 0 },
4970 { "vsave", s_arm_unwind_save, 1 },
4971 { "movsp", s_arm_unwind_movsp, 0 },
4972 { "pad", s_arm_unwind_pad, 0 },
4973 { "setfp", s_arm_unwind_setfp, 0 },
4974 { "unwind_raw", s_arm_unwind_raw, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file, 0 },
4986 { "loc", dwarf2_directive_loc, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4989 { "extend", float_cons, 'x' },
4990 { "ldouble", float_cons, 'x' },
4991 { "packed", float_cons, 'p' },
4993 {"secrel32", pe_directive_secrel, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref, 0},
4998 {"def", s_ccs_def, 0},
4999 {"asmfunc", s_ccs_asmfunc, 0},
5000 {"endasmfunc", s_ccs_endasmfunc, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str, int *val, int min, int max,
5015 bfd_boolean prefix_opt)
5019 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5020 if (exp.X_op != O_constant)
5022 inst.error = _("constant expression required");
5026 if (exp.X_add_number < min || exp.X_add_number > max)
5028 inst.error = _("immediate value out of range");
5032 *val = exp.X_add_number;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str, int i, expressionS *in_exp,
5042 bfd_boolean allow_symbol_p)
5045 expressionS *exp_p = in_exp ? in_exp : &exp;
5048 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5050 if (exp_p->X_op == O_constant)
5052 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5061 inst.operands[i].regisimm = 1;
5064 else if (exp_p->X_op == O_big
5065 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5067 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts != 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
5080 LITTLENUM_TYPE m = -1;
5082 if (generic_bignum[parts * 2] != 0
5083 && generic_bignum[parts * 2] != m)
5086 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
5087 if (generic_bignum[j] != generic_bignum[j-1])
5091 inst.operands[i].imm = 0;
5092 for (j = 0; j < parts; j++, idx++)
5093 inst.operands[i].imm |= generic_bignum[idx]
5094 << (LITTLENUM_NUMBER_OF_BITS * j);
5095 inst.operands[i].reg = 0;
5096 for (j = 0; j < parts; j++, idx++)
5097 inst.operands[i].reg |= generic_bignum[idx]
5098 << (LITTLENUM_NUMBER_OF_BITS * j);
5099 inst.operands[i].regisimm = 1;
5101 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str)
5115 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i = 0; fp_const[i]; i++)
5126 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
5130 *str += strlen (fp_const[i]);
5131 if (is_end_of_line[(unsigned char) **str])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
5144 /* Look for a raw floating point number. */
5145 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5146 && is_end_of_line[(unsigned char) *save_in])
5148 for (i = 0; i < NUM_FLOAT_VALS; i++)
5150 for (j = 0; j < MAX_LITTLENUMS; j++)
5152 if (words[j] != fp_values[i][j])
5156 if (j == MAX_LITTLENUMS)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in = input_line_pointer;
5167 input_line_pointer = *str;
5168 if (expression (&exp) == absolute_section
5169 && exp.X_op == O_big
5170 && exp.X_add_number < 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
5178 for (i = 0; i < NUM_FLOAT_VALS; i++)
5180 for (j = 0; j < MAX_LITTLENUMS; j++)
5182 if (words[j] != fp_values[i][j])
5186 if (j == MAX_LITTLENUMS)
5188 *str = input_line_pointer;
5189 input_line_pointer = save_in;
5196 *str = input_line_pointer;
5197 input_line_pointer = save_in;
5198 inst.error = _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm)
5208 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in)
5221 if (!is_immediate_prefix (**in))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in, "0x", 2) == 0)
5234 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5239 error_code = atof_generic (in, ".", EXP_CHARS,
5240 &generic_floating_point_number);
5243 && generic_floating_point_number.sign == '+'
5244 && (generic_floating_point_number.low
5245 > generic_floating_point_number.leader))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp, int *immed)
5262 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5263 int found_fpchar = 0;
5265 skip_past_char (&str, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum);
5275 if (strncmp (fpnum, "0x", 2) == 0)
5279 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5280 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5290 if ((str = atof_ieee (str, 's', words)) != NULL)
5292 unsigned fpword = 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5298 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5302 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str, int i, enum parse_shift_mode mode)
5351 const struct asm_shift_name *shift_name;
5352 enum shift_kind shift;
5357 for (p = *str; ISALPHA (*p); p++)
5362 inst.error = _("shift expression expected");
5366 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5369 if (shift_name == NULL)
5371 inst.error = _("shift expression expected");
5375 shift = shift_name->kind;
5379 case NO_SHIFT_RESTRICT:
5380 case SHIFT_IMMEDIATE:
5381 if (shift == SHIFT_UXTW)
5383 inst.error = _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5389 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5391 inst.error = _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE:
5397 if (shift != SHIFT_LSL)
5399 inst.error = _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE:
5405 if (shift != SHIFT_ASR)
5407 inst.error = _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE:
5412 if (shift != SHIFT_UXTW)
5414 inst.error = _("'UXTW' required");
5422 if (shift != SHIFT_RRX)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p);
5427 if (mode == NO_SHIFT_RESTRICT
5428 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5430 inst.operands[i].imm = reg;
5431 inst.operands[i].immisreg = 1;
5433 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5436 inst.operands[i].shift_kind = shift;
5437 inst.operands[i].shifted = 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str, int i)
5459 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5461 inst.operands[i].reg = value;
5462 inst.operands[i].isreg = 1;
5464 /* parse_shift will override this if appropriate */
5465 inst.relocs[0].exp.X_op = O_constant;
5466 inst.relocs[0].exp.X_add_number = 0;
5468 if (skip_past_comma (str) == FAIL)
5471 /* Shift operation on register. */
5472 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5475 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5478 if (skip_past_comma (str) == SUCCESS)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5484 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5486 inst.error = _("constant expression expected");
5490 value = exp.X_add_number;
5491 if (value < 0 || value > 30 || value % 2 != 0)
5493 inst.error = _("invalid rotation");
5496 if (inst.relocs[0].exp.X_add_number < 0
5497 || inst.relocs[0].exp.X_add_number > 255)
5499 inst.error = _("invalid constant");
5503 /* Encode as specified. */
5504 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5508 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5509 inst.relocs[0].pc_rel = 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5625 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5627 int length = strlen (group_reloc_table[i].name);
5629 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5630 && (*str)[length] == ':')
5632 *out = &group_reloc_table[i];
5633 *str += (length + 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str, int i)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str)[0] == '#' && (*str)[1] == ':')
5663 || (*str)[0] == ':')
5665 struct group_reloc_table_entry *entry;
5667 if ((*str)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5675 inst.error = _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5686 gas_assert (inst.relocs[0].type != 0);
5688 return PARSE_OPERAND_SUCCESS;
5691 return parse_shifter_operand (str, i) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str, int i)
5707 my_get_expression (&exp, &p, GE_NO_PREFIX);
5709 if (exp.X_op != O_constant)
5711 inst.error = _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL;
5715 inst.operands[i].imm = exp.X_add_number << 8;
5716 inst.operands[i].immisalign = 1;
5717 /* Alignments are not pre-indexes. */
5718 inst.operands[i].preind = 0;
5721 return PARSE_OPERAND_SUCCESS;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str, int i, int group_relocations,
5758 group_reloc_type group_type)
5763 if (skip_past_char (&p, '[') == FAIL)
5765 if (skip_past_char (&p, '=') == FAIL)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst.relocs[0].pc_rel = 1;
5769 inst.operands[i].reg = REG_PC;
5770 inst.operands[i].isreg = 1;
5771 inst.operands[i].preind = 1;
5773 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5774 return PARSE_OPERAND_FAIL;
5776 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5777 /*allow_symbol_p=*/TRUE))
5778 return PARSE_OPERAND_FAIL;
5781 return PARSE_OPERAND_SUCCESS;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p);
5787 if (group_type == GROUP_MVE)
5789 enum arm_reg_type rtype = REG_TYPE_MQ;
5790 struct neon_type_el et;
5791 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5793 inst.operands[i].isquad = 1;
5795 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5797 inst.error = BAD_ADDR_MODE;
5798 return PARSE_OPERAND_FAIL;
5801 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5803 if (group_type == GROUP_MVE)
5804 inst.error = BAD_ADDR_MODE;
5806 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5807 return PARSE_OPERAND_FAIL;
5809 inst.operands[i].reg = reg;
5810 inst.operands[i].isreg = 1;
5812 if (skip_past_comma (&p) == SUCCESS)
5814 inst.operands[i].preind = 1;
5817 else if (*p == '-') p++, inst.operands[i].negative = 1;
5819 enum arm_reg_type rtype = REG_TYPE_MQ;
5820 struct neon_type_el et;
5821 if (group_type == GROUP_MVE
5822 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5824 inst.operands[i].immisreg = 2;
5825 inst.operands[i].imm = reg;
5827 if (skip_past_comma (&p) == SUCCESS)
5829 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5831 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5832 inst.relocs[0].exp.X_add_number = 0;
5835 return PARSE_OPERAND_FAIL;
5838 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5840 inst.operands[i].imm = reg;
5841 inst.operands[i].immisreg = 1;
5843 if (skip_past_comma (&p) == SUCCESS)
5844 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5845 return PARSE_OPERAND_FAIL;
5847 else if (skip_past_char (&p, ':') == SUCCESS)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result = parse_neon_alignment (&p, i);
5854 if (result != PARSE_OPERAND_SUCCESS)
5859 if (inst.operands[i].negative)
5861 inst.operands[i].negative = 0;
5865 if (group_relocations
5866 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5868 struct group_reloc_table_entry *entry;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5880 inst.error = _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type) entry->ldr_code;
5900 = (bfd_reloc_code_real_type) entry->ldrs_code;
5905 = (bfd_reloc_code_real_type) entry->ldc_code;
5912 if (inst.relocs[0].type == 0)
5914 inst.error = _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5922 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5923 return PARSE_OPERAND_FAIL;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst.relocs[0].exp.X_op == O_constant
5926 && inst.relocs[0].exp.X_add_number == 0)
5928 skip_whitespace (q);
5932 skip_whitespace (q);
5935 inst.operands[i].negative = 1;
5940 else if (skip_past_char (&p, ':') == SUCCESS)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result = parse_neon_alignment (&p, i);
5946 if (result != PARSE_OPERAND_SUCCESS)
5950 if (skip_past_char (&p, ']') == FAIL)
5952 inst.error = _("']' expected");
5953 return PARSE_OPERAND_FAIL;
5956 if (skip_past_char (&p, '!') == SUCCESS)
5957 inst.operands[i].writeback = 1;
5959 else if (skip_past_comma (&p) == SUCCESS)
5961 if (skip_past_char (&p, '{') == SUCCESS)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p, &inst.operands[i].imm,
5965 0, 255, TRUE) == FAIL)
5966 return PARSE_OPERAND_FAIL;
5968 if (skip_past_char (&p, '}') == FAIL)
5970 inst.error = _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL;
5973 if (inst.operands[i].preind)
5975 inst.error = _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL;
5979 return PARSE_OPERAND_SUCCESS;
5983 inst.operands[i].postind = 1;
5984 inst.operands[i].writeback = 1;
5986 if (inst.operands[i].preind)
5988 inst.error = _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL;
5993 else if (*p == '-') p++, inst.operands[i].negative = 1;
5995 enum arm_reg_type rtype = REG_TYPE_MQ;
5996 struct neon_type_el et;
5997 if (group_type == GROUP_MVE
5998 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6000 inst.operands[i].immisreg = 2;
6001 inst.operands[i].imm = reg;
6003 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst.operands[i].immisalign)
6008 inst.operands[i].imm |= reg;
6010 inst.operands[i].imm = reg;
6011 inst.operands[i].immisreg = 1;
6013 if (skip_past_comma (&p) == SUCCESS)
6014 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6015 return PARSE_OPERAND_FAIL;
6021 if (inst.operands[i].negative)
6023 inst.operands[i].negative = 0;
6026 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6027 return PARSE_OPERAND_FAIL;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst.relocs[0].exp.X_op == O_constant
6030 && inst.relocs[0].exp.X_add_number == 0)
6032 skip_whitespace (q);
6036 skip_whitespace (q);
6039 inst.operands[i].negative = 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6049 inst.operands[i].preind = 1;
6050 inst.relocs[0].exp.X_op = O_constant;
6051 inst.relocs[0].exp.X_add_number = 0;
6054 return PARSE_OPERAND_SUCCESS;
6058 parse_address (char **str, int i)
6060 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str, int i, group_reloc_type type)
6067 return parse_address_main (str, i, 1, type);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str)
6077 skip_past_char (&p, '#');
6078 if (strncasecmp (p, ":lower16:", 9) == 0)
6079 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6080 else if (strncasecmp (p, ":upper16:", 9) == 0)
6081 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6083 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6086 skip_whitespace (p);
6089 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6092 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6094 if (inst.relocs[0].exp.X_op != O_constant)
6096 inst.error = _("constant expression expected");
6099 if (inst.relocs[0].exp.X_add_number < 0
6100 || inst.relocs[0].exp.X_add_number > 0xffff)
6102 inst.error = _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str, bfd_boolean lhs)
6118 unsigned long psr_field;
6119 const struct asm_psr *psr;
6121 bfd_boolean is_apsr = FALSE;
6122 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p, "SPSR", 4) == 0)
6136 goto unsupported_psr;
6138 psr_field = SPSR_BIT;
6140 else if (strncasecmp (p, "CPSR", 4) == 0)
6143 goto unsupported_psr;
6147 else if (strncasecmp (p, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p) || *p == '_');
6161 if (strncasecmp (start, "iapsr", 5) == 0
6162 || strncasecmp (start, "eapsr", 5) == 0
6163 || strncasecmp (start, "xpsr", 4) == 0
6164 || strncasecmp (start, "psr", 3) == 0)
6165 p = start + strcspn (start, "rR") + 1;
6167 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr->field <= 3)
6177 psr_field = psr->field;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr->field | (lhs ? PSR_f : 0);
6190 goto unsupported_psr;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p) || *p == '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits = 0;
6208 unsigned int g_bit = 0;
6211 for (bit = start; bit != p; bit++)
6213 switch (TOLOWER (*bit))
6216 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6236 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6240 inst.error = _("unexpected bit specified after APSR");
6245 if (nzcvq_bits == 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
6252 inst.error = _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits & 0x20) != 0
6261 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6262 || (g_bit & 0x2) != 0)
6264 inst.error = _("bad bitmask specified after APSR");
6270 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
6275 psr_field |= psr->field;
6281 goto error; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field |= (PSR_c | PSR_f);
6300 inst.error = _("selected processor does not support requested special "
6301 "purpose register");
6305 inst.error = _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end = strchr (*str, ',');
6327 size_t op_strlen = op_end - *str;
6329 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6331 if (!strncmp (*str, sysregs[i].name, op_strlen))
6333 val = sysregs[i].regl | (sysregs[i].regh << 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6359 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6360 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6363 inst.error = _("unrecognized CPS flag");
6368 if (saw_a_flag == 0)
6370 inst.error = _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str)
6387 if (strncasecmp (s, "BE", 2))
6389 else if (strncasecmp (s, "LE", 2))
6393 inst.error = _("valid endian specifiers are be or le");
6397 if (ISALNUM (s[2]) || s[2] == '_')
6399 inst.error = _("valid endian specifiers are be or le");
6404 return little_endian;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str)
6417 if (strncasecmp (s, "ROR", 3) == 0)
6421 inst.error = _("missing rotation field after comma");
6425 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6430 case 0: *str = s; return 0x0;
6431 case 8: *str = s; return 0x1;
6432 case 16: *str = s; return 0x2;
6433 case 24: *str = s; return 0x3;
6436 inst.error = _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str)
6447 const struct asm_cond *c;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q) && n < 3)
6457 cond[n] = TOLOWER (*q);
6462 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6465 inst.error = _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str)
6479 const struct asm_barrier_opt *o;
6482 while (ISALPHA (*q))
6485 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6490 if (!mark_feature_used (&o->arch))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str)
6505 if (skip_past_char (&p, '[') == FAIL)
6507 inst.error = _("'[' expected");
6511 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6513 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6516 inst.operands[0].reg = reg;
6518 if (skip_past_comma (&p) == FAIL)
6520 inst.error = _("',' expected");
6524 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6526 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6529 inst.operands[0].imm = reg;
6531 if (skip_past_comma (&p) == SUCCESS)
6533 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6535 if (inst.relocs[0].exp.X_add_number != 1)
6537 inst.error = _("invalid shift");
6540 inst.operands[0].shifted = 1;
6543 if (skip_past_char (&p, ']') == FAIL)
6545 inst.error = _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str, int *which_operand)
6562 int i = *which_operand, val;
6563 enum arm_reg_type rtype;
6565 struct neon_type_el optype;
6567 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6569 /* Cases 17 or 19. */
6570 inst.operands[i].reg = val;
6571 inst.operands[i].isvec = 1;
6572 inst.operands[i].isscalar = 2;
6573 inst.operands[i].vectype = optype;
6574 inst.operands[i++].present = 1;
6576 if (skip_past_comma (&ptr) == FAIL)
6579 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst.operands[i].reg = val;
6583 inst.operands[i].isreg = 1;
6584 inst.operands[i].present = 1;
6586 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst.operands[i].reg = val;
6590 inst.operands[i].isvec = 1;
6591 inst.operands[i].isscalar = 2;
6592 inst.operands[i].vectype = optype;
6593 inst.operands[i++].present = 1;
6595 if (skip_past_comma (&ptr) == FAIL)
6598 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6601 inst.operands[i].reg = val;
6602 inst.operands[i].isreg = 1;
6603 inst.operands[i++].present = 1;
6605 if (skip_past_comma (&ptr) == FAIL)
6608 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6611 inst.operands[i].reg = val;
6612 inst.operands[i].isreg = 1;
6613 inst.operands[i].present = 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst.operands[i].reg = val;
6625 inst.operands[i].isscalar = 1;
6626 inst.operands[i].vectype = optype;
6627 inst.operands[i++].present = 1;
6629 if (skip_past_comma (&ptr) == FAIL)
6632 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6635 inst.operands[i].reg = val;
6636 inst.operands[i].isreg = 1;
6637 inst.operands[i].present = 1;
6639 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6641 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr) == FAIL)
6648 inst.operands[i].reg = val;
6649 inst.operands[i].isreg = 1;
6650 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6651 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6652 inst.operands[i].isvec = 1;
6653 inst.operands[i].vectype = optype;
6654 inst.operands[i++].present = 1;
6656 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst.operands[i].reg = val;
6661 inst.operands[i].isreg = 1;
6662 inst.operands[i].present = 1;
6664 if (rtype == REG_TYPE_NQ)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype != REG_TYPE_VFS)
6672 if (skip_past_comma (&ptr) == FAIL)
6674 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6681 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst.operands[i].reg = val;
6690 inst.operands[i].isreg = 1;
6691 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6692 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6693 inst.operands[i].isvec = 1;
6694 inst.operands[i].vectype = optype;
6695 inst.operands[i].present = 1;
6697 if (skip_past_comma (&ptr) == SUCCESS)
6702 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6705 inst.operands[i].reg = val;
6706 inst.operands[i].isreg = 1;
6707 inst.operands[i++].present = 1;
6709 if (skip_past_comma (&ptr) == FAIL)
6712 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6715 inst.operands[i].reg = val;
6716 inst.operands[i].isreg = 1;
6717 inst.operands[i].present = 1;
6720 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst.operands[i].immisfloat = 1;
6726 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6739 /* Cases 6, 7, 16, 18. */
6740 inst.operands[i].reg = val;
6741 inst.operands[i].isreg = 1;
6742 inst.operands[i++].present = 1;
6744 if (skip_past_comma (&ptr) == FAIL)
6747 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst.operands[i].reg = val;
6751 inst.operands[i].isscalar = 2;
6752 inst.operands[i].present = 1;
6753 inst.operands[i].vectype = optype;
6755 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst.operands[i].reg = val;
6759 inst.operands[i].isscalar = 1;
6760 inst.operands[i].present = 1;
6761 inst.operands[i].vectype = optype;
6763 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6765 inst.operands[i].reg = val;
6766 inst.operands[i].isreg = 1;
6767 inst.operands[i++].present = 1;
6769 if (skip_past_comma (&ptr) == FAIL)
6772 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst.operands[i].reg = val;
6778 inst.operands[i].isreg = 1;
6779 inst.operands[i].isvec = 1;
6780 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6781 inst.operands[i].vectype = optype;
6782 inst.operands[i].present = 1;
6784 if (rtype == REG_TYPE_VFS)
6788 if (skip_past_comma (&ptr) == FAIL)
6790 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6793 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6796 inst.operands[i].reg = val;
6797 inst.operands[i].isreg = 1;
6798 inst.operands[i].isvec = 1;
6799 inst.operands[i].issingle = 1;
6800 inst.operands[i].vectype = optype;
6801 inst.operands[i].present = 1;
6806 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst.operands[i].reg = val;
6811 inst.operands[i].isvec = 1;
6812 inst.operands[i].isscalar = 2;
6813 inst.operands[i].vectype = optype;
6814 inst.operands[i++].present = 1;
6816 if (skip_past_comma (&ptr) == FAIL)
6819 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6822 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6825 inst.operands[i].reg = val;
6826 inst.operands[i].isvec = 1;
6827 inst.operands[i].isscalar = 2;
6828 inst.operands[i].vectype = optype;
6829 inst.operands[i].present = 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6843 inst.operands[i].reg = val;
6844 inst.operands[i].isreg = 1;
6845 inst.operands[i].isvec = 1;
6846 inst.operands[i].issingle = 1;
6847 inst.operands[i].vectype = optype;
6848 inst.operands[i].present = 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop, /* end of line */
6881 OP_RR, /* ARM register */
6882 OP_RRnpc, /* ARM register, not r15 */
6883 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP, /* Coprocessor number */
6889 OP_RCN, /* Coprocessor register */
6890 OP_RF, /* FPA register */
6891 OP_RVS, /* VFP single precision register */
6892 OP_RVD, /* VFP double precision register (0..15) */
6893 OP_RND, /* Neon double precision register (0..31) */
6894 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ, /* Neon quad precision register */
6898 OP_RNQMQ, /* Neon quad or MVE vector register. */
6899 OP_RVSD, /* VFP single or double precision register */
6900 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD, /* Neon single or double precision register */
6903 OP_RNDQ, /* Neon double or quad precision register */
6904 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ, /* Neon single, double or quad precision register */
6907 OP_RNSC, /* Neon scalar D[X] */
6908 OP_RVC, /* VFP control register */
6909 OP_RMF, /* Maverick F register */
6910 OP_RMD, /* Maverick D register */
6911 OP_RMFX, /* Maverick FX register */
6912 OP_RMDX, /* Maverick DX register */
6913 OP_RMAX, /* Maverick AX register */
6914 OP_RMDS, /* Maverick DSPSC register */
6915 OP_RIWR, /* iWMMXt wR register */
6916 OP_RIWC, /* iWMMXt wC register */
6917 OP_RIWG, /* iWMMXt wCG register */
6918 OP_RXA, /* XScale accumulator register */
6920 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ, /* MVE vector register. */
6925 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
6927 /* New operands for Armv8.1-M Mainline. */
6928 OP_LR, /* ARM LR register */
6929 OP_RRe, /* ARM register, only even numbered. */
6930 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
6931 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
6933 OP_REGLST, /* ARM register list */
6934 OP_CLRMLST, /* CLRM register list */
6935 OP_VRSLST, /* VFP single-precision register list */
6936 OP_VRDLST, /* VFP double-precision register list */
6937 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6938 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6939 OP_NSTRLST, /* Neon element/structure list */
6940 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
6941 OP_MSTRLST2, /* MVE vector list with two elements. */
6942 OP_MSTRLST4, /* MVE vector list with four elements. */
6944 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6945 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6946 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6947 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
6949 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6950 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6954 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6955 scalar, or ARM register. */
6956 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6957 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6958 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6959 OP_VMOV, /* Neon VMOV operands. */
6960 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6961 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6963 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6964 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6965 OP_VLDR, /* VLDR operand. */
6967 OP_I0, /* immediate zero */
6968 OP_I7, /* immediate value 0 .. 7 */
6969 OP_I15, /* 0 .. 15 */
6970 OP_I16, /* 1 .. 16 */
6971 OP_I16z, /* 0 .. 16 */
6972 OP_I31, /* 0 .. 31 */
6973 OP_I31w, /* 0 .. 31, optional trailing ! */
6974 OP_I32, /* 1 .. 32 */
6975 OP_I32z, /* 0 .. 32 */
6976 OP_I63, /* 0 .. 63 */
6977 OP_I63s, /* -64 .. 63 */
6978 OP_I64, /* 1 .. 64 */
6979 OP_I64z, /* 0 .. 64 */
6980 OP_I255, /* 0 .. 255 */
6982 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6983 OP_I7b, /* 0 .. 7 */
6984 OP_I15b, /* 0 .. 15 */
6985 OP_I31b, /* 0 .. 31 */
6987 OP_SH, /* shifter operand */
6988 OP_SHG, /* shifter operand with possible group relocation */
6989 OP_ADDR, /* Memory address expression (any mode) */
6990 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
6991 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6992 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6993 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6994 OP_EXP, /* arbitrary expression */
6995 OP_EXPi, /* same, with optional immediate prefix */
6996 OP_EXPr, /* same, with optional relocation suffix */
6997 OP_EXPs, /* same, with optional non-first operand relocation suffix */
6998 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6999 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7000 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7002 OP_CPSF, /* CPS flags */
7003 OP_ENDI, /* Endianness specifier */
7004 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7005 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
7006 OP_COND, /* conditional code */
7007 OP_TB, /* Table branch. */
7009 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7011 OP_RRnpc_I0, /* ARM register or literal 0 */
7012 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
7013 OP_RR_EXi, /* ARM register or expression with imm prefix */
7014 OP_RF_IF, /* FPA register or immediate */
7015 OP_RIWR_RIWC, /* iWMMXt R or C reg */
7016 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
7018 /* Optional operands. */
7019 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7020 OP_oI31b, /* 0 .. 31 */
7021 OP_oI32b, /* 1 .. 32 */
7022 OP_oI32z, /* 0 .. 32 */
7023 OP_oIffffb, /* 0 .. 65535 */
7024 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7026 OP_oRR, /* ARM register */
7027 OP_oLR, /* ARM LR register */
7028 OP_oRRnpc, /* ARM register, not the PC */
7029 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7030 OP_oRRw, /* ARM register, not r15, optional trailing ! */
7031 OP_oRND, /* Optional Neon double precision register */
7032 OP_oRNQ, /* Optional Neon quad precision register */
7033 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
7034 OP_oRNDQ, /* Optional Neon double or quad precision register */
7035 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
7036 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7038 OP_oSHll, /* LSL immediate */
7039 OP_oSHar, /* ASR immediate */
7040 OP_oSHllar, /* LSL or ASR immediate */
7041 OP_oROR, /* ROR 0/8/16/24 */
7042 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
7044 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7046 /* Some pre-defined mixed (ARM/THUMB) operands. */
7047 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7048 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7049 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7051 OP_FIRST_OPTIONAL = OP_oI7b
7054 /* Generic instruction operand parser. This does no encoding and no
7055 semantic validation; it merely squirrels values away in the inst
7056 structure. Returns SUCCESS or FAIL depending on whether the
7057 specified grammar matched. */
7059 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
7061 unsigned const int *upat = pattern;
7062 char *backtrack_pos = 0;
7063 const char *backtrack_error = 0;
7064 int i, val = 0, backtrack_index = 0;
7065 enum arm_reg_type rtype;
7066 parse_operand_result result;
7067 unsigned int op_parse_code;
7068 bfd_boolean partial_match;
7070 #define po_char_or_fail(chr) \
7073 if (skip_past_char (&str, chr) == FAIL) \
7078 #define po_reg_or_fail(regtype) \
7081 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7082 & inst.operands[i].vectype); \
7085 first_error (_(reg_expected_msgs[regtype])); \
7088 inst.operands[i].reg = val; \
7089 inst.operands[i].isreg = 1; \
7090 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7091 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7092 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7093 || rtype == REG_TYPE_VFD \
7094 || rtype == REG_TYPE_NQ); \
7095 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7099 #define po_reg_or_goto(regtype, label) \
7102 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7103 & inst.operands[i].vectype); \
7107 inst.operands[i].reg = val; \
7108 inst.operands[i].isreg = 1; \
7109 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7110 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7111 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7112 || rtype == REG_TYPE_VFD \
7113 || rtype == REG_TYPE_NQ); \
7114 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7118 #define po_imm_or_fail(min, max, popt) \
7121 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7123 inst.operands[i].imm = val; \
7127 #define po_scalar_or_goto(elsz, label, reg_type) \
7130 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7134 inst.operands[i].reg = val; \
7135 inst.operands[i].isscalar = 1; \
7139 #define po_misc_or_fail(expr) \
7147 #define po_misc_or_fail_no_backtrack(expr) \
7151 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7152 backtrack_pos = 0; \
7153 if (result != PARSE_OPERAND_SUCCESS) \
7158 #define po_barrier_or_imm(str) \
7161 val = parse_barrier (&str); \
7162 if (val == FAIL && ! ISALPHA (*str)) \
7165 /* ISB can only take SY as an option. */ \
7166 || ((inst.instruction & 0xf0) == 0x60 \
7169 inst.error = _("invalid barrier type"); \
7170 backtrack_pos = 0; \
7176 skip_whitespace (str);
7178 for (i = 0; upat[i] != OP_stop; i++)
7180 op_parse_code = upat[i];
7181 if (op_parse_code >= 1<<16)
7182 op_parse_code = thumb ? (op_parse_code >> 16)
7183 : (op_parse_code & ((1<<16)-1));
7185 if (op_parse_code >= OP_FIRST_OPTIONAL)
7187 /* Remember where we are in case we need to backtrack. */
7188 backtrack_pos = str;
7189 backtrack_error = inst.error;
7190 backtrack_index = i;
7193 if (i > 0 && (i > 1 || inst.operands[0].present))
7194 po_char_or_fail (',');
7196 switch (op_parse_code)
7208 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7209 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7210 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7211 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7212 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7213 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
7216 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7220 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7223 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
7225 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7227 /* Also accept generic coprocessor regs for unknown registers. */
7229 po_reg_or_fail (REG_TYPE_CN);
7231 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7232 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7233 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7234 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7235 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7236 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7237 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7238 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7239 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7240 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
7243 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7246 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
7247 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7249 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7254 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7258 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
7260 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7263 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
7265 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7268 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
7270 po_reg_or_goto (REG_TYPE_RN, try_mq);
7275 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7278 po_reg_or_fail (REG_TYPE_NSDQ);
7282 po_reg_or_fail (REG_TYPE_MQ);
7284 /* Neon scalar. Using an element size of 8 means that some invalid
7285 scalars are accepted here, so deal with those in later code. */
7286 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
7290 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7293 po_imm_or_fail (0, 0, TRUE);
7298 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7302 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7307 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7310 if (parse_ifimm_zero (&str))
7311 inst.operands[i].imm = 0;
7315 = _("only floating point zero is allowed as immediate value");
7323 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
7326 po_reg_or_fail (REG_TYPE_RN);
7330 case OP_RNSDQ_RNSC_MQ_RR:
7331 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7334 case OP_RNSDQ_RNSC_MQ:
7335 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7340 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7344 po_reg_or_fail (REG_TYPE_NSDQ);
7351 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
7354 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
7357 po_reg_or_fail (REG_TYPE_NSD);
7361 case OP_RNDQMQ_RNSC:
7362 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7367 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
7370 po_reg_or_fail (REG_TYPE_NDQ);
7376 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
7379 po_reg_or_fail (REG_TYPE_VFD);
7384 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7385 not careful then bad things might happen. */
7386 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7389 case OP_RNDQMQ_Ibig:
7390 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7395 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7398 /* There's a possibility of getting a 64-bit immediate here, so
7399 we need special handling. */
7400 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7403 inst.error = _("immediate value is out of range");
7411 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7414 po_imm_or_fail (0, 63, TRUE);
7419 po_char_or_fail ('[');
7420 po_reg_or_fail (REG_TYPE_RN);
7421 po_char_or_fail (']');
7427 po_reg_or_fail (REG_TYPE_RN);
7428 if (skip_past_char (&str, '!') == SUCCESS)
7429 inst.operands[i].writeback = 1;
7433 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7434 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7435 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
7436 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
7437 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7438 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
7439 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
7440 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
7441 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7442 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7443 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
7444 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
7446 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7448 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7449 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7451 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
7452 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7453 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
7454 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7456 /* Immediate variants */
7458 po_char_or_fail ('{');
7459 po_imm_or_fail (0, 255, TRUE);
7460 po_char_or_fail ('}');
7464 /* The expression parser chokes on a trailing !, so we have
7465 to find it first and zap it. */
7468 while (*s && *s != ',')
7473 inst.operands[i].writeback = 1;
7475 po_imm_or_fail (0, 31, TRUE);
7483 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7488 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7493 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7495 if (inst.relocs[0].exp.X_op == O_symbol)
7497 val = parse_reloc (&str);
7500 inst.error = _("unrecognized relocation suffix");
7503 else if (val != BFD_RELOC_UNUSED)
7505 inst.operands[i].imm = val;
7506 inst.operands[i].hasreloc = 1;
7512 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7514 if (inst.relocs[i].exp.X_op == O_symbol)
7516 inst.operands[i].hasreloc = 1;
7518 else if (inst.relocs[i].exp.X_op == O_constant)
7520 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7521 inst.operands[i].hasreloc = 0;
7525 /* Operand for MOVW or MOVT. */
7527 po_misc_or_fail (parse_half (&str));
7530 /* Register or expression. */
7531 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7532 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7534 /* Register or immediate. */
7535 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7536 I0: po_imm_or_fail (0, 0, FALSE); break;
7538 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7540 if (!is_immediate_prefix (*str))
7543 val = parse_fpa_immediate (&str);
7546 /* FPA immediates are encoded as registers 8-15.
7547 parse_fpa_immediate has already applied the offset. */
7548 inst.operands[i].reg = val;
7549 inst.operands[i].isreg = 1;
7552 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7553 I32z: po_imm_or_fail (0, 32, FALSE); break;
7555 /* Two kinds of register. */
7558 struct reg_entry *rege = arm_reg_parse_multi (&str);
7560 || (rege->type != REG_TYPE_MMXWR
7561 && rege->type != REG_TYPE_MMXWC
7562 && rege->type != REG_TYPE_MMXWCG))
7564 inst.error = _("iWMMXt data or control register expected");
7567 inst.operands[i].reg = rege->number;
7568 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7574 struct reg_entry *rege = arm_reg_parse_multi (&str);
7576 || (rege->type != REG_TYPE_MMXWC
7577 && rege->type != REG_TYPE_MMXWCG))
7579 inst.error = _("iWMMXt control register expected");
7582 inst.operands[i].reg = rege->number;
7583 inst.operands[i].isreg = 1;
7588 case OP_CPSF: val = parse_cps_flags (&str); break;
7589 case OP_ENDI: val = parse_endian_specifier (&str); break;
7590 case OP_oROR: val = parse_ror (&str); break;
7592 case OP_COND: val = parse_cond (&str); break;
7593 case OP_oBARRIER_I15:
7594 po_barrier_or_imm (str); break;
7596 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7602 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7603 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7605 inst.error = _("Banked registers are not available with this "
7611 val = parse_psr (&str, op_parse_code == OP_wPSR);
7615 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7618 val = parse_sys_vldr_vstr (&str);
7622 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7625 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7627 if (strncasecmp (str, "APSR_", 5) == 0)
7634 case 'c': found = (found & 1) ? 16 : found | 1; break;
7635 case 'n': found = (found & 2) ? 16 : found | 2; break;
7636 case 'z': found = (found & 4) ? 16 : found | 4; break;
7637 case 'v': found = (found & 8) ? 16 : found | 8; break;
7638 default: found = 16;
7642 inst.operands[i].isvec = 1;
7643 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7644 inst.operands[i].reg = REG_PC;
7651 po_misc_or_fail (parse_tb (&str));
7654 /* Register lists. */
7656 val = parse_reg_list (&str, REGLIST_RN);
7659 inst.operands[i].writeback = 1;
7665 val = parse_reg_list (&str, REGLIST_CLRM);
7669 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7674 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7679 /* Allow Q registers too. */
7680 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7681 REGLIST_NEON_D, &partial_match);
7685 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7686 REGLIST_VFP_S, &partial_match);
7687 inst.operands[i].issingle = 1;
7692 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7693 REGLIST_VFP_D_VPR, &partial_match);
7694 if (val == FAIL && !partial_match)
7697 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7698 REGLIST_VFP_S_VPR, &partial_match);
7699 inst.operands[i].issingle = 1;
7704 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7705 REGLIST_NEON_D, &partial_match);
7710 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7711 1, &inst.operands[i].vectype);
7712 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7716 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7717 0, &inst.operands[i].vectype);
7720 /* Addressing modes */
7722 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7726 po_misc_or_fail (parse_address (&str, i));
7730 po_misc_or_fail_no_backtrack (
7731 parse_address_group_reloc (&str, i, GROUP_LDR));
7735 po_misc_or_fail_no_backtrack (
7736 parse_address_group_reloc (&str, i, GROUP_LDRS));
7740 po_misc_or_fail_no_backtrack (
7741 parse_address_group_reloc (&str, i, GROUP_LDC));
7745 po_misc_or_fail (parse_shifter_operand (&str, i));
7749 po_misc_or_fail_no_backtrack (
7750 parse_shifter_operand_group_reloc (&str, i));
7754 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7758 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7762 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7767 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7770 po_reg_or_goto (REG_TYPE_RN, ZR);
7773 po_reg_or_fail (REG_TYPE_ZR);
7777 as_fatal (_("unhandled operand code %d"), op_parse_code);
7780 /* Various value-based sanity checks and shared operations. We
7781 do not signal immediate failures for the register constraints;
7782 this allows a syntax error to take precedence. */
7783 switch (op_parse_code)
7791 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7792 inst.error = BAD_PC;
7797 if (inst.operands[i].isreg)
7799 if (inst.operands[i].reg == REG_PC)
7800 inst.error = BAD_PC;
7801 else if (inst.operands[i].reg == REG_SP
7802 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7803 relaxed since ARMv8-A. */
7804 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7807 inst.error = BAD_SP;
7813 if (inst.operands[i].isreg
7814 && inst.operands[i].reg == REG_PC
7815 && (inst.operands[i].writeback || thumb))
7816 inst.error = BAD_PC;
7821 if (inst.operands[i].isreg)
7831 case OP_oBARRIER_I15:
7844 inst.operands[i].imm = val;
7849 if (inst.operands[i].reg != REG_LR)
7850 inst.error = _("operand must be LR register");
7855 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7856 inst.error = BAD_PC;
7860 if (inst.operands[i].isreg
7861 && (inst.operands[i].reg & 0x00000001) != 0)
7862 inst.error = BAD_ODD;
7866 if (inst.operands[i].isreg)
7868 if ((inst.operands[i].reg & 0x00000001) != 1)
7869 inst.error = BAD_EVEN;
7870 else if (inst.operands[i].reg == REG_SP)
7871 as_tsktsk (MVE_BAD_SP);
7872 else if (inst.operands[i].reg == REG_PC)
7873 inst.error = BAD_PC;
7881 /* If we get here, this operand was successfully parsed. */
7882 inst.operands[i].present = 1;
7886 inst.error = BAD_ARGS;
7891 /* The parse routine should already have set inst.error, but set a
7892 default here just in case. */
7894 inst.error = BAD_SYNTAX;
7898 /* Do not backtrack over a trailing optional argument that
7899 absorbed some text. We will only fail again, with the
7900 'garbage following instruction' error message, which is
7901 probably less helpful than the current one. */
7902 if (backtrack_index == i && backtrack_pos != str
7903 && upat[i+1] == OP_stop)
7906 inst.error = BAD_SYNTAX;
7910 /* Try again, skipping the optional argument at backtrack_pos. */
7911 str = backtrack_pos;
7912 inst.error = backtrack_error;
7913 inst.operands[backtrack_index].present = 0;
7914 i = backtrack_index;
7918 /* Check that we have parsed all the arguments. */
7919 if (*str != '\0' && !inst.error)
7920 inst.error = _("garbage following instruction");
7922 return inst.error ? FAIL : SUCCESS;
7925 #undef po_char_or_fail
7926 #undef po_reg_or_fail
7927 #undef po_reg_or_goto
7928 #undef po_imm_or_fail
7929 #undef po_scalar_or_fail
7930 #undef po_barrier_or_imm
7932 /* Shorthand macro for instruction encoding functions issuing errors. */
7933 #define constraint(expr, err) \
7944 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7945 instructions are unpredictable if these registers are used. This
7946 is the BadReg predicate in ARM's Thumb-2 documentation.
7948 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7949 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7950 #define reject_bad_reg(reg) \
7952 if (reg == REG_PC) \
7954 inst.error = BAD_PC; \
7957 else if (reg == REG_SP \
7958 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7960 inst.error = BAD_SP; \
7965 /* If REG is R13 (the stack pointer), warn that its use is
7967 #define warn_deprecated_sp(reg) \
7969 if (warn_on_deprecated && reg == REG_SP) \
7970 as_tsktsk (_("use of r13 is deprecated")); \
7973 /* Functions for operand encoding. ARM, then Thumb. */
7975 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7977 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7979 The only binary encoding difference is the Coprocessor number. Coprocessor
7980 9 is used for half-precision calculations or conversions. The format of the
7981 instruction is the same as the equivalent Coprocessor 10 instruction that
7982 exists for Single-Precision operation. */
7985 do_scalar_fp16_v82_encode (void)
7987 if (inst.cond < COND_ALWAYS)
7988 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7989 " the behaviour is UNPREDICTABLE"));
7990 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
7993 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
7994 mark_feature_used (&arm_ext_fp16);
7997 /* If VAL can be encoded in the immediate field of an ARM instruction,
7998 return the encoded form. Otherwise, return FAIL. */
8001 encode_arm_immediate (unsigned int val)
8008 for (i = 2; i < 32; i += 2)
8009 if ((a = rotate_left (val, i)) <= 0xff)
8010 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8015 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8016 return the encoded form. Otherwise, return FAIL. */
8018 encode_thumb32_immediate (unsigned int val)
8025 for (i = 1; i <= 24; i++)
8028 if ((val & ~(0xff << i)) == 0)
8029 return ((val >> i) & 0x7f) | ((32 - i) << 7);
8033 if (val == ((a << 16) | a))
8035 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8039 if (val == ((a << 16) | a))
8040 return 0x200 | (a >> 8);
8044 /* Encode a VFP SP or DP register number into inst.instruction. */
8047 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8049 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8052 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
8055 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8058 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8063 first_error (_("D register out of range for selected VFP version"));
8071 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8075 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8079 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8083 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8087 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8091 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8099 /* Encode a <shift> in an ARM-format instruction. The immediate,
8100 if any, is handled by md_apply_fix. */
8102 encode_arm_shift (int i)
8104 /* register-shifted register. */
8105 if (inst.operands[i].immisreg)
8108 for (op_index = 0; op_index <= i; ++op_index)
8110 /* Check the operand only when it's presented. In pre-UAL syntax,
8111 if the destination register is the same as the first operand, two
8112 register form of the instruction can be used. */
8113 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8114 && inst.operands[op_index].reg == REG_PC)
8115 as_warn (UNPRED_REG ("r15"));
8118 if (inst.operands[i].imm == REG_PC)
8119 as_warn (UNPRED_REG ("r15"));
8122 if (inst.operands[i].shift_kind == SHIFT_RRX)
8123 inst.instruction |= SHIFT_ROR << 5;
8126 inst.instruction |= inst.operands[i].shift_kind << 5;
8127 if (inst.operands[i].immisreg)
8129 inst.instruction |= SHIFT_BY_REG;
8130 inst.instruction |= inst.operands[i].imm << 8;
8133 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8138 encode_arm_shifter_operand (int i)
8140 if (inst.operands[i].isreg)
8142 inst.instruction |= inst.operands[i].reg;
8143 encode_arm_shift (i);
8147 inst.instruction |= INST_IMMEDIATE;
8148 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8149 inst.instruction |= inst.operands[i].imm;
8153 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8155 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
8158 Generate an error if the operand is not a register. */
8159 constraint (!inst.operands[i].isreg,
8160 _("Instruction does not support =N addresses"));
8162 inst.instruction |= inst.operands[i].reg << 16;
8164 if (inst.operands[i].preind)
8168 inst.error = _("instruction does not accept preindexed addressing");
8171 inst.instruction |= PRE_INDEX;
8172 if (inst.operands[i].writeback)
8173 inst.instruction |= WRITE_BACK;
8176 else if (inst.operands[i].postind)
8178 gas_assert (inst.operands[i].writeback);
8180 inst.instruction |= WRITE_BACK;
8182 else /* unindexed - only for coprocessor */
8184 inst.error = _("instruction does not accept unindexed addressing");
8188 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8189 && (((inst.instruction & 0x000f0000) >> 16)
8190 == ((inst.instruction & 0x0000f000) >> 12)))
8191 as_warn ((inst.instruction & LOAD_BIT)
8192 ? _("destination register same as write-back base")
8193 : _("source register same as write-back base"));
8196 /* inst.operands[i] was set up by parse_address. Encode it into an
8197 ARM-format mode 2 load or store instruction. If is_t is true,
8198 reject forms that cannot be used with a T instruction (i.e. not
8201 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
8203 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8205 encode_arm_addr_mode_common (i, is_t);
8207 if (inst.operands[i].immisreg)
8209 constraint ((inst.operands[i].imm == REG_PC
8210 || (is_pc && inst.operands[i].writeback)),
8212 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8213 inst.instruction |= inst.operands[i].imm;
8214 if (!inst.operands[i].negative)
8215 inst.instruction |= INDEX_UP;
8216 if (inst.operands[i].shifted)
8218 if (inst.operands[i].shift_kind == SHIFT_RRX)
8219 inst.instruction |= SHIFT_ROR << 5;
8222 inst.instruction |= inst.operands[i].shift_kind << 5;
8223 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8227 else /* immediate offset in inst.relocs[0] */
8229 if (is_pc && !inst.relocs[0].pc_rel)
8231 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
8233 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8234 cannot use PC in addressing.
8235 PC cannot be used in writeback addressing, either. */
8236 constraint ((is_t || inst.operands[i].writeback),
8239 /* Use of PC in str is deprecated for ARMv7. */
8240 if (warn_on_deprecated
8242 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
8243 as_tsktsk (_("use of PC in this instruction is deprecated"));
8246 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8248 /* Prefer + for zero encoded value. */
8249 if (!inst.operands[i].negative)
8250 inst.instruction |= INDEX_UP;
8251 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8256 /* inst.operands[i] was set up by parse_address. Encode it into an
8257 ARM-format mode 3 load or store instruction. Reject forms that
8258 cannot be used with such instructions. If is_t is true, reject
8259 forms that cannot be used with a T instruction (i.e. not
8262 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
8264 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8266 inst.error = _("instruction does not accept scaled register index");
8270 encode_arm_addr_mode_common (i, is_t);
8272 if (inst.operands[i].immisreg)
8274 constraint ((inst.operands[i].imm == REG_PC
8275 || (is_t && inst.operands[i].reg == REG_PC)),
8277 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8279 inst.instruction |= inst.operands[i].imm;
8280 if (!inst.operands[i].negative)
8281 inst.instruction |= INDEX_UP;
8283 else /* immediate offset in inst.relocs[0] */
8285 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8286 && inst.operands[i].writeback),
8288 inst.instruction |= HWOFFSET_IMM;
8289 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8291 /* Prefer + for zero encoded value. */
8292 if (!inst.operands[i].negative)
8293 inst.instruction |= INDEX_UP;
8295 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8300 /* Write immediate bits [7:0] to the following locations:
8302 |28/24|23 19|18 16|15 4|3 0|
8303 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8305 This function is used by VMOV/VMVN/VORR/VBIC. */
8308 neon_write_immbits (unsigned immbits)
8310 inst.instruction |= immbits & 0xf;
8311 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8312 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8315 /* Invert low-order SIZE bits of XHI:XLO. */
8318 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8320 unsigned immlo = xlo ? *xlo : 0;
8321 unsigned immhi = xhi ? *xhi : 0;
8326 immlo = (~immlo) & 0xff;
8330 immlo = (~immlo) & 0xffff;
8334 immhi = (~immhi) & 0xffffffff;
8338 immlo = (~immlo) & 0xffffffff;
8352 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8356 neon_bits_same_in_bytes (unsigned imm)
8358 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8359 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8360 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8361 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8364 /* For immediate of above form, return 0bABCD. */
8367 neon_squash_bits (unsigned imm)
8369 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8370 | ((imm & 0x01000000) >> 21);
8373 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8376 neon_qfloat_bits (unsigned imm)
8378 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8381 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8382 the instruction. *OP is passed as the initial value of the op field, and
8383 may be set to a different value depending on the constant (i.e.
8384 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8385 MVN). If the immediate looks like a repeated pattern then also
8386 try smaller element sizes. */
8389 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8390 unsigned *immbits, int *op, int size,
8391 enum neon_el_type type)
8393 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8395 if (type == NT_float && !float_p)
8398 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
8400 if (size != 32 || *op == 1)
8402 *immbits = neon_qfloat_bits (immlo);
8408 if (neon_bits_same_in_bytes (immhi)
8409 && neon_bits_same_in_bytes (immlo))
8413 *immbits = (neon_squash_bits (immhi) << 4)
8414 | neon_squash_bits (immlo);
8425 if (immlo == (immlo & 0x000000ff))
8430 else if (immlo == (immlo & 0x0000ff00))
8432 *immbits = immlo >> 8;
8435 else if (immlo == (immlo & 0x00ff0000))
8437 *immbits = immlo >> 16;
8440 else if (immlo == (immlo & 0xff000000))
8442 *immbits = immlo >> 24;
8445 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8447 *immbits = (immlo >> 8) & 0xff;
8450 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8452 *immbits = (immlo >> 16) & 0xff;
8456 if ((immlo & 0xffff) != (immlo >> 16))
8463 if (immlo == (immlo & 0x000000ff))
8468 else if (immlo == (immlo & 0x0000ff00))
8470 *immbits = immlo >> 8;
8474 if ((immlo & 0xff) != (immlo >> 8))
8479 if (immlo == (immlo & 0x000000ff))
8481 /* Don't allow MVN with 8-bit immediate. */
8491 #if defined BFD_HOST_64_BIT
8492 /* Returns TRUE if double precision value V may be cast
8493 to single precision without loss of accuracy. */
8496 is_double_a_single (bfd_int64_t v)
8498 int exp = (int)((v >> 52) & 0x7FF);
8499 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8501 return (exp == 0 || exp == 0x7FF
8502 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8503 && (mantissa & 0x1FFFFFFFl) == 0;
8506 /* Returns a double precision value casted to single precision
8507 (ignoring the least significant bits in exponent and mantissa). */
8510 double_to_single (bfd_int64_t v)
8512 int sign = (int) ((v >> 63) & 1l);
8513 int exp = (int) ((v >> 52) & 0x7FF);
8514 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8520 exp = exp - 1023 + 127;
8529 /* No denormalized numbers. */
8535 return (sign << 31) | (exp << 23) | mantissa;
8537 #endif /* BFD_HOST_64_BIT */
8546 static void do_vfp_nsyn_opcode (const char *);
8548 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8549 Determine whether it can be performed with a move instruction; if
8550 it can, convert inst.instruction to that move instruction and
8551 return TRUE; if it can't, convert inst.instruction to a literal-pool
8552 load and return FALSE. If this is not a valid thing to do in the
8553 current context, set inst.error and return TRUE.
8555 inst.operands[i] describes the destination register. */
8558 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
8561 bfd_boolean thumb_p = (t == CONST_THUMB);
8562 bfd_boolean arm_p = (t == CONST_ARM);
8565 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8569 if ((inst.instruction & tbit) == 0)
8571 inst.error = _("invalid pseudo operation");
8575 if (inst.relocs[0].exp.X_op != O_constant
8576 && inst.relocs[0].exp.X_op != O_symbol
8577 && inst.relocs[0].exp.X_op != O_big)
8579 inst.error = _("constant expression expected");
8583 if (inst.relocs[0].exp.X_op == O_constant
8584 || inst.relocs[0].exp.X_op == O_big)
8586 #if defined BFD_HOST_64_BIT
8591 if (inst.relocs[0].exp.X_op == O_big)
8593 LITTLENUM_TYPE w[X_PRECISION];
8596 if (inst.relocs[0].exp.X_add_number == -1)
8598 gen_to_words (w, X_PRECISION, E_PRECISION);
8600 /* FIXME: Should we check words w[2..5] ? */
8605 #if defined BFD_HOST_64_BIT
8607 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8608 << LITTLENUM_NUMBER_OF_BITS)
8609 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8610 << LITTLENUM_NUMBER_OF_BITS)
8611 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8612 << LITTLENUM_NUMBER_OF_BITS)
8613 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8615 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8616 | (l[0] & LITTLENUM_MASK);
8620 v = inst.relocs[0].exp.X_add_number;
8622 if (!inst.operands[i].issingle)
8626 /* LDR should not use lead in a flag-setting instruction being
8627 chosen so we do not check whether movs can be used. */
8629 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8630 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8631 && inst.operands[i].reg != 13
8632 && inst.operands[i].reg != 15)
8634 /* Check if on thumb2 it can be done with a mov.w, mvn or
8635 movw instruction. */
8636 unsigned int newimm;
8637 bfd_boolean isNegated;
8639 newimm = encode_thumb32_immediate (v);
8640 if (newimm != (unsigned int) FAIL)
8644 newimm = encode_thumb32_immediate (~v);
8645 if (newimm != (unsigned int) FAIL)
8649 /* The number can be loaded with a mov.w or mvn
8651 if (newimm != (unsigned int) FAIL
8652 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8654 inst.instruction = (0xf04f0000 /* MOV.W. */
8655 | (inst.operands[i].reg << 8));
8656 /* Change to MOVN. */
8657 inst.instruction |= (isNegated ? 0x200000 : 0);
8658 inst.instruction |= (newimm & 0x800) << 15;
8659 inst.instruction |= (newimm & 0x700) << 4;
8660 inst.instruction |= (newimm & 0x0ff);
8663 /* The number can be loaded with a movw instruction. */
8664 else if ((v & ~0xFFFF) == 0
8665 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8667 int imm = v & 0xFFFF;
8669 inst.instruction = 0xf2400000; /* MOVW. */
8670 inst.instruction |= (inst.operands[i].reg << 8);
8671 inst.instruction |= (imm & 0xf000) << 4;
8672 inst.instruction |= (imm & 0x0800) << 15;
8673 inst.instruction |= (imm & 0x0700) << 4;
8674 inst.instruction |= (imm & 0x00ff);
8681 int value = encode_arm_immediate (v);
8685 /* This can be done with a mov instruction. */
8686 inst.instruction &= LITERAL_MASK;
8687 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8688 inst.instruction |= value & 0xfff;
8692 value = encode_arm_immediate (~ v);
8695 /* This can be done with a mvn instruction. */
8696 inst.instruction &= LITERAL_MASK;
8697 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8698 inst.instruction |= value & 0xfff;
8702 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8705 unsigned immbits = 0;
8706 unsigned immlo = inst.operands[1].imm;
8707 unsigned immhi = inst.operands[1].regisimm
8708 ? inst.operands[1].reg
8709 : inst.relocs[0].exp.X_unsigned
8711 : ((bfd_int64_t)((int) immlo)) >> 32;
8712 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8713 &op, 64, NT_invtype);
8717 neon_invert_size (&immlo, &immhi, 64);
8719 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8720 &op, 64, NT_invtype);
8725 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8731 /* Fill other bits in vmov encoding for both thumb and arm. */
8733 inst.instruction |= (0x7U << 29) | (0xF << 24);
8735 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8736 neon_write_immbits (immbits);
8744 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8745 if (inst.operands[i].issingle
8746 && is_quarter_float (inst.operands[1].imm)
8747 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8749 inst.operands[1].imm =
8750 neon_qfloat_bits (v);
8751 do_vfp_nsyn_opcode ("fconsts");
8755 /* If our host does not support a 64-bit type then we cannot perform
8756 the following optimization. This mean that there will be a
8757 discrepancy between the output produced by an assembler built for
8758 a 32-bit-only host and the output produced from a 64-bit host, but
8759 this cannot be helped. */
8760 #if defined BFD_HOST_64_BIT
8761 else if (!inst.operands[1].issingle
8762 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8764 if (is_double_a_single (v)
8765 && is_quarter_float (double_to_single (v)))
8767 inst.operands[1].imm =
8768 neon_qfloat_bits (double_to_single (v));
8769 do_vfp_nsyn_opcode ("fconstd");
8777 if (add_to_lit_pool ((!inst.operands[i].isvec
8778 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8781 inst.operands[1].reg = REG_PC;
8782 inst.operands[1].isreg = 1;
8783 inst.operands[1].preind = 1;
8784 inst.relocs[0].pc_rel = 1;
8785 inst.relocs[0].type = (thumb_p
8786 ? BFD_RELOC_ARM_THUMB_OFFSET
8788 ? BFD_RELOC_ARM_HWLITERAL
8789 : BFD_RELOC_ARM_LITERAL));
8793 /* inst.operands[i] was set up by parse_address. Encode it into an
8794 ARM-format instruction. Reject all forms which cannot be encoded
8795 into a coprocessor load/store instruction. If wb_ok is false,
8796 reject use of writeback; if unind_ok is false, reject use of
8797 unindexed addressing. If reloc_override is not 0, use it instead
8798 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8799 (in which case it is preserved). */
8802 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8804 if (!inst.operands[i].isreg)
8807 if (! inst.operands[0].isvec)
8809 inst.error = _("invalid co-processor operand");
8812 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8816 inst.instruction |= inst.operands[i].reg << 16;
8818 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8820 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8822 gas_assert (!inst.operands[i].writeback);
8825 inst.error = _("instruction does not support unindexed addressing");
8828 inst.instruction |= inst.operands[i].imm;
8829 inst.instruction |= INDEX_UP;
8833 if (inst.operands[i].preind)
8834 inst.instruction |= PRE_INDEX;
8836 if (inst.operands[i].writeback)
8838 if (inst.operands[i].reg == REG_PC)
8840 inst.error = _("pc may not be used with write-back");
8845 inst.error = _("instruction does not support writeback");
8848 inst.instruction |= WRITE_BACK;
8852 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8853 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8854 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8855 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
8858 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8860 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
8863 /* Prefer + for zero encoded value. */
8864 if (!inst.operands[i].negative)
8865 inst.instruction |= INDEX_UP;
8870 /* Functions for instruction encoding, sorted by sub-architecture.
8871 First some generics; their names are taken from the conventional
8872 bit positions for register arguments in ARM format instructions. */
8882 inst.instruction |= inst.operands[0].reg << 12;
8888 inst.instruction |= inst.operands[0].reg << 16;
8894 inst.instruction |= inst.operands[0].reg << 12;
8895 inst.instruction |= inst.operands[1].reg;
8901 inst.instruction |= inst.operands[0].reg;
8902 inst.instruction |= inst.operands[1].reg << 16;
8908 inst.instruction |= inst.operands[0].reg << 12;
8909 inst.instruction |= inst.operands[1].reg << 16;
8915 inst.instruction |= inst.operands[0].reg << 16;
8916 inst.instruction |= inst.operands[1].reg << 12;
8922 inst.instruction |= inst.operands[0].reg << 8;
8923 inst.instruction |= inst.operands[1].reg << 16;
8927 check_obsolete (const arm_feature_set *feature, const char *msg)
8929 if (ARM_CPU_IS_ANY (cpu_variant))
8931 as_tsktsk ("%s", msg);
8934 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8946 unsigned Rn = inst.operands[2].reg;
8947 /* Enforce restrictions on SWP instruction. */
8948 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8950 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8951 _("Rn must not overlap other operands"));
8953 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8955 if (!check_obsolete (&arm_ext_v8,
8956 _("swp{b} use is obsoleted for ARMv8 and later"))
8957 && warn_on_deprecated
8958 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8959 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8962 inst.instruction |= inst.operands[0].reg << 12;
8963 inst.instruction |= inst.operands[1].reg;
8964 inst.instruction |= Rn << 16;
8970 inst.instruction |= inst.operands[0].reg << 12;
8971 inst.instruction |= inst.operands[1].reg << 16;
8972 inst.instruction |= inst.operands[2].reg;
8978 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8979 constraint (((inst.relocs[0].exp.X_op != O_constant
8980 && inst.relocs[0].exp.X_op != O_illegal)
8981 || inst.relocs[0].exp.X_add_number != 0),
8983 inst.instruction |= inst.operands[0].reg;
8984 inst.instruction |= inst.operands[1].reg << 12;
8985 inst.instruction |= inst.operands[2].reg << 16;
8991 inst.instruction |= inst.operands[0].imm;
8997 inst.instruction |= inst.operands[0].reg << 12;
8998 encode_arm_cp_address (1, TRUE, TRUE, 0);
9001 /* ARM instructions, in alphabetical order by function name (except
9002 that wrapper functions appear immediately after the function they
9005 /* This is a pseudo-op of the form "adr rd, label" to be converted
9006 into a relative address of the form "add rd, pc, #label-.-8". */
9011 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9013 /* Frag hacking will turn this into a sub instruction if the offset turns
9014 out to be negative. */
9015 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9016 inst.relocs[0].pc_rel = 1;
9017 inst.relocs[0].exp.X_add_number -= 8;
9019 if (support_interwork
9020 && inst.relocs[0].exp.X_op == O_symbol
9021 && inst.relocs[0].exp.X_add_symbol != NULL
9022 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9023 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9024 inst.relocs[0].exp.X_add_number |= 1;
9027 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9028 into a relative address of the form:
9029 add rd, pc, #low(label-.-8)"
9030 add rd, rd, #high(label-.-8)" */
9035 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9037 /* Frag hacking will turn this into a sub instruction if the offset turns
9038 out to be negative. */
9039 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9040 inst.relocs[0].pc_rel = 1;
9041 inst.size = INSN_SIZE * 2;
9042 inst.relocs[0].exp.X_add_number -= 8;
9044 if (support_interwork
9045 && inst.relocs[0].exp.X_op == O_symbol
9046 && inst.relocs[0].exp.X_add_symbol != NULL
9047 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9048 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9049 inst.relocs[0].exp.X_add_number |= 1;
9055 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9056 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9058 if (!inst.operands[1].present)
9059 inst.operands[1].reg = inst.operands[0].reg;
9060 inst.instruction |= inst.operands[0].reg << 12;
9061 inst.instruction |= inst.operands[1].reg << 16;
9062 encode_arm_shifter_operand (2);
9068 if (inst.operands[0].present)
9069 inst.instruction |= inst.operands[0].imm;
9071 inst.instruction |= 0xf;
9077 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9078 constraint (msb > 32, _("bit-field extends past end of register"));
9079 /* The instruction encoding stores the LSB and MSB,
9080 not the LSB and width. */
9081 inst.instruction |= inst.operands[0].reg << 12;
9082 inst.instruction |= inst.operands[1].imm << 7;
9083 inst.instruction |= (msb - 1) << 16;
9091 /* #0 in second position is alternative syntax for bfc, which is
9092 the same instruction but with REG_PC in the Rm field. */
9093 if (!inst.operands[1].isreg)
9094 inst.operands[1].reg = REG_PC;
9096 msb = inst.operands[2].imm + inst.operands[3].imm;
9097 constraint (msb > 32, _("bit-field extends past end of register"));
9098 /* The instruction encoding stores the LSB and MSB,
9099 not the LSB and width. */
9100 inst.instruction |= inst.operands[0].reg << 12;
9101 inst.instruction |= inst.operands[1].reg;
9102 inst.instruction |= inst.operands[2].imm << 7;
9103 inst.instruction |= (msb - 1) << 16;
9109 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9110 _("bit-field extends past end of register"));
9111 inst.instruction |= inst.operands[0].reg << 12;
9112 inst.instruction |= inst.operands[1].reg;
9113 inst.instruction |= inst.operands[2].imm << 7;
9114 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9117 /* ARM V5 breakpoint instruction (argument parse)
9118 BKPT <16 bit unsigned immediate>
9119 Instruction is not conditional.
9120 The bit pattern given in insns[] has the COND_ALWAYS condition,
9121 and it is an error if the caller tried to override that. */
9126 /* Top 12 of 16 bits to bits 19:8. */
9127 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9129 /* Bottom 4 of 16 bits to bits 3:0. */
9130 inst.instruction |= inst.operands[0].imm & 0xf;
9134 encode_branch (int default_reloc)
9136 if (inst.operands[0].hasreloc)
9138 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9139 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9140 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9141 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9142 ? BFD_RELOC_ARM_PLT32
9143 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
9146 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9147 inst.relocs[0].pc_rel = 1;
9154 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9155 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9158 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9165 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9167 if (inst.cond == COND_ALWAYS)
9168 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9170 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9174 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9177 /* ARM V5 branch-link-exchange instruction (argument parse)
9178 BLX <target_addr> ie BLX(1)
9179 BLX{<condition>} <Rm> ie BLX(2)
9180 Unfortunately, there are two different opcodes for this mnemonic.
9181 So, the insns[].value is not used, and the code here zaps values
9182 into inst.instruction.
9183 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9188 if (inst.operands[0].isreg)
9190 /* Arg is a register; the opcode provided by insns[] is correct.
9191 It is not illegal to do "blx pc", just useless. */
9192 if (inst.operands[0].reg == REG_PC)
9193 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9195 inst.instruction |= inst.operands[0].reg;
9199 /* Arg is an address; this instruction cannot be executed
9200 conditionally, and the opcode must be adjusted.
9201 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9202 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9203 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9204 inst.instruction = 0xfa000000;
9205 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
9212 bfd_boolean want_reloc;
9214 if (inst.operands[0].reg == REG_PC)
9215 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9217 inst.instruction |= inst.operands[0].reg;
9218 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9219 it is for ARMv4t or earlier. */
9220 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
9221 if (!ARM_FEATURE_ZERO (selected_object_arch)
9222 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
9226 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
9231 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9235 /* ARM v5TEJ. Jump to Jazelle code. */
9240 if (inst.operands[0].reg == REG_PC)
9241 as_tsktsk (_("use of r15 in bxj is not really useful"));
9243 inst.instruction |= inst.operands[0].reg;
9246 /* Co-processor data operation:
9247 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9248 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9252 inst.instruction |= inst.operands[0].reg << 8;
9253 inst.instruction |= inst.operands[1].imm << 20;
9254 inst.instruction |= inst.operands[2].reg << 12;
9255 inst.instruction |= inst.operands[3].reg << 16;
9256 inst.instruction |= inst.operands[4].reg;
9257 inst.instruction |= inst.operands[5].imm << 5;
9263 inst.instruction |= inst.operands[0].reg << 16;
9264 encode_arm_shifter_operand (1);
9267 /* Transfer between coprocessor and ARM registers.
9268 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9273 No special properties. */
9275 struct deprecated_coproc_regs_s
9282 arm_feature_set deprecated;
9283 arm_feature_set obsoleted;
9284 const char *dep_msg;
9285 const char *obs_msg;
9288 #define DEPR_ACCESS_V8 \
9289 N_("This coprocessor register access is deprecated in ARMv8")
9291 /* Table of all deprecated coprocessor registers. */
9292 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9294 {15, 0, 7, 10, 5, /* CP15DMB. */
9295 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9296 DEPR_ACCESS_V8, NULL},
9297 {15, 0, 7, 10, 4, /* CP15DSB. */
9298 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9299 DEPR_ACCESS_V8, NULL},
9300 {15, 0, 7, 5, 4, /* CP15ISB. */
9301 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9302 DEPR_ACCESS_V8, NULL},
9303 {14, 6, 1, 0, 0, /* TEEHBR. */
9304 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9305 DEPR_ACCESS_V8, NULL},
9306 {14, 6, 0, 0, 0, /* TEECR. */
9307 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9308 DEPR_ACCESS_V8, NULL},
9311 #undef DEPR_ACCESS_V8
9313 static const size_t deprecated_coproc_reg_count =
9314 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9322 Rd = inst.operands[2].reg;
9325 if (inst.instruction == 0xee000010
9326 || inst.instruction == 0xfe000010)
9328 reject_bad_reg (Rd);
9329 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9331 constraint (Rd == REG_SP, BAD_SP);
9336 if (inst.instruction == 0xe000010)
9337 constraint (Rd == REG_PC, BAD_PC);
9340 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9342 const struct deprecated_coproc_regs_s *r =
9343 deprecated_coproc_regs + i;
9345 if (inst.operands[0].reg == r->cp
9346 && inst.operands[1].imm == r->opc1
9347 && inst.operands[3].reg == r->crn
9348 && inst.operands[4].reg == r->crm
9349 && inst.operands[5].imm == r->opc2)
9351 if (! ARM_CPU_IS_ANY (cpu_variant)
9352 && warn_on_deprecated
9353 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
9354 as_tsktsk ("%s", r->dep_msg);
9358 inst.instruction |= inst.operands[0].reg << 8;
9359 inst.instruction |= inst.operands[1].imm << 21;
9360 inst.instruction |= Rd << 12;
9361 inst.instruction |= inst.operands[3].reg << 16;
9362 inst.instruction |= inst.operands[4].reg;
9363 inst.instruction |= inst.operands[5].imm << 5;
9366 /* Transfer between coprocessor register and pair of ARM registers.
9367 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9372 Two XScale instructions are special cases of these:
9374 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9375 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9377 Result unpredictable if Rd or Rn is R15. */
9384 Rd = inst.operands[2].reg;
9385 Rn = inst.operands[3].reg;
9389 reject_bad_reg (Rd);
9390 reject_bad_reg (Rn);
9394 constraint (Rd == REG_PC, BAD_PC);
9395 constraint (Rn == REG_PC, BAD_PC);
9398 /* Only check the MRRC{2} variants. */
9399 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9401 /* If Rd == Rn, error that the operation is
9402 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9403 constraint (Rd == Rn, BAD_OVERLAP);
9406 inst.instruction |= inst.operands[0].reg << 8;
9407 inst.instruction |= inst.operands[1].imm << 4;
9408 inst.instruction |= Rd << 12;
9409 inst.instruction |= Rn << 16;
9410 inst.instruction |= inst.operands[4].reg;
9416 inst.instruction |= inst.operands[0].imm << 6;
9417 if (inst.operands[1].present)
9419 inst.instruction |= CPSI_MMOD;
9420 inst.instruction |= inst.operands[1].imm;
9427 inst.instruction |= inst.operands[0].imm;
9433 unsigned Rd, Rn, Rm;
9435 Rd = inst.operands[0].reg;
9436 Rn = (inst.operands[1].present
9437 ? inst.operands[1].reg : Rd);
9438 Rm = inst.operands[2].reg;
9440 constraint ((Rd == REG_PC), BAD_PC);
9441 constraint ((Rn == REG_PC), BAD_PC);
9442 constraint ((Rm == REG_PC), BAD_PC);
9444 inst.instruction |= Rd << 16;
9445 inst.instruction |= Rn << 0;
9446 inst.instruction |= Rm << 8;
9452 /* There is no IT instruction in ARM mode. We
9453 process it to do the validation as if in
9454 thumb mode, just in case the code gets
9455 assembled for thumb using the unified syntax. */
9460 set_pred_insn_type (IT_INSN);
9461 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9462 now_pred.cc = inst.operands[0].imm;
9466 /* If there is only one register in the register list,
9467 then return its register number. Otherwise return -1. */
9469 only_one_reg_in_list (int range)
9471 int i = ffs (range) - 1;
9472 return (i > 15 || range != (1 << i)) ? -1 : i;
9476 encode_ldmstm(int from_push_pop_mnem)
9478 int base_reg = inst.operands[0].reg;
9479 int range = inst.operands[1].imm;
9482 inst.instruction |= base_reg << 16;
9483 inst.instruction |= range;
9485 if (inst.operands[1].writeback)
9486 inst.instruction |= LDM_TYPE_2_OR_3;
9488 if (inst.operands[0].writeback)
9490 inst.instruction |= WRITE_BACK;
9491 /* Check for unpredictable uses of writeback. */
9492 if (inst.instruction & LOAD_BIT)
9494 /* Not allowed in LDM type 2. */
9495 if ((inst.instruction & LDM_TYPE_2_OR_3)
9496 && ((range & (1 << REG_PC)) == 0))
9497 as_warn (_("writeback of base register is UNPREDICTABLE"));
9498 /* Only allowed if base reg not in list for other types. */
9499 else if (range & (1 << base_reg))
9500 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9504 /* Not allowed for type 2. */
9505 if (inst.instruction & LDM_TYPE_2_OR_3)
9506 as_warn (_("writeback of base register is UNPREDICTABLE"));
9507 /* Only allowed if base reg not in list, or first in list. */
9508 else if ((range & (1 << base_reg))
9509 && (range & ((1 << base_reg) - 1)))
9510 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9514 /* If PUSH/POP has only one register, then use the A2 encoding. */
9515 one_reg = only_one_reg_in_list (range);
9516 if (from_push_pop_mnem && one_reg >= 0)
9518 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9520 if (is_push && one_reg == 13 /* SP */)
9521 /* PR 22483: The A2 encoding cannot be used when
9522 pushing the stack pointer as this is UNPREDICTABLE. */
9525 inst.instruction &= A_COND_MASK;
9526 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9527 inst.instruction |= one_reg << 12;
9534 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
9537 /* ARMv5TE load-consecutive (argument parse)
9546 constraint (inst.operands[0].reg % 2 != 0,
9547 _("first transfer register must be even"));
9548 constraint (inst.operands[1].present
9549 && inst.operands[1].reg != inst.operands[0].reg + 1,
9550 _("can only transfer two consecutive registers"));
9551 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9552 constraint (!inst.operands[2].isreg, _("'[' expected"));
9554 if (!inst.operands[1].present)
9555 inst.operands[1].reg = inst.operands[0].reg + 1;
9557 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9558 register and the first register written; we have to diagnose
9559 overlap between the base and the second register written here. */
9561 if (inst.operands[2].reg == inst.operands[1].reg
9562 && (inst.operands[2].writeback || inst.operands[2].postind))
9563 as_warn (_("base register written back, and overlaps "
9564 "second transfer register"));
9566 if (!(inst.instruction & V4_STR_BIT))
9568 /* For an index-register load, the index register must not overlap the
9569 destination (even if not write-back). */
9570 if (inst.operands[2].immisreg
9571 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9572 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9573 as_warn (_("index register overlaps transfer register"));
9575 inst.instruction |= inst.operands[0].reg << 12;
9576 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
9582 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9583 || inst.operands[1].postind || inst.operands[1].writeback
9584 || inst.operands[1].immisreg || inst.operands[1].shifted
9585 || inst.operands[1].negative
9586 /* This can arise if the programmer has written
9588 or if they have mistakenly used a register name as the last
9591 It is very difficult to distinguish between these two cases
9592 because "rX" might actually be a label. ie the register
9593 name has been occluded by a symbol of the same name. So we
9594 just generate a general 'bad addressing mode' type error
9595 message and leave it up to the programmer to discover the
9596 true cause and fix their mistake. */
9597 || (inst.operands[1].reg == REG_PC),
9600 constraint (inst.relocs[0].exp.X_op != O_constant
9601 || inst.relocs[0].exp.X_add_number != 0,
9602 _("offset must be zero in ARM encoding"));
9604 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9606 inst.instruction |= inst.operands[0].reg << 12;
9607 inst.instruction |= inst.operands[1].reg << 16;
9608 inst.relocs[0].type = BFD_RELOC_UNUSED;
9614 constraint (inst.operands[0].reg % 2 != 0,
9615 _("even register required"));
9616 constraint (inst.operands[1].present
9617 && inst.operands[1].reg != inst.operands[0].reg + 1,
9618 _("can only load two consecutive registers"));
9619 /* If op 1 were present and equal to PC, this function wouldn't
9620 have been called in the first place. */
9621 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9623 inst.instruction |= inst.operands[0].reg << 12;
9624 inst.instruction |= inst.operands[2].reg << 16;
9627 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9628 which is not a multiple of four is UNPREDICTABLE. */
9630 check_ldr_r15_aligned (void)
9632 constraint (!(inst.operands[1].immisreg)
9633 && (inst.operands[0].reg == REG_PC
9634 && inst.operands[1].reg == REG_PC
9635 && (inst.relocs[0].exp.X_add_number & 0x3)),
9636 _("ldr to register 15 must be 4-byte aligned"));
9642 inst.instruction |= inst.operands[0].reg << 12;
9643 if (!inst.operands[1].isreg)
9644 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
9646 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
9647 check_ldr_r15_aligned ();
9653 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9655 if (inst.operands[1].preind)
9657 constraint (inst.relocs[0].exp.X_op != O_constant
9658 || inst.relocs[0].exp.X_add_number != 0,
9659 _("this instruction requires a post-indexed address"));
9661 inst.operands[1].preind = 0;
9662 inst.operands[1].postind = 1;
9663 inst.operands[1].writeback = 1;
9665 inst.instruction |= inst.operands[0].reg << 12;
9666 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9669 /* Halfword and signed-byte load/store operations. */
9674 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9675 inst.instruction |= inst.operands[0].reg << 12;
9676 if (!inst.operands[1].isreg)
9677 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
9679 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
9685 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9687 if (inst.operands[1].preind)
9689 constraint (inst.relocs[0].exp.X_op != O_constant
9690 || inst.relocs[0].exp.X_add_number != 0,
9691 _("this instruction requires a post-indexed address"));
9693 inst.operands[1].preind = 0;
9694 inst.operands[1].postind = 1;
9695 inst.operands[1].writeback = 1;
9697 inst.instruction |= inst.operands[0].reg << 12;
9698 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9701 /* Co-processor register load/store.
9702 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9706 inst.instruction |= inst.operands[0].reg << 8;
9707 inst.instruction |= inst.operands[1].reg << 12;
9708 encode_arm_cp_address (2, TRUE, TRUE, 0);
9714 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9715 if (inst.operands[0].reg == inst.operands[1].reg
9716 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
9717 && !(inst.instruction & 0x00400000))
9718 as_tsktsk (_("Rd and Rm should be different in mla"));
9720 inst.instruction |= inst.operands[0].reg << 16;
9721 inst.instruction |= inst.operands[1].reg;
9722 inst.instruction |= inst.operands[2].reg << 8;
9723 inst.instruction |= inst.operands[3].reg << 12;
9729 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9730 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9732 inst.instruction |= inst.operands[0].reg << 12;
9733 encode_arm_shifter_operand (1);
9736 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9743 top = (inst.instruction & 0x00400000) != 0;
9744 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
9745 _(":lower16: not allowed in this instruction"));
9746 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
9747 _(":upper16: not allowed in this instruction"));
9748 inst.instruction |= inst.operands[0].reg << 12;
9749 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
9751 imm = inst.relocs[0].exp.X_add_number;
9752 /* The value is in two pieces: 0:11, 16:19. */
9753 inst.instruction |= (imm & 0x00000fff);
9754 inst.instruction |= (imm & 0x0000f000) << 4;
9759 do_vfp_nsyn_mrs (void)
9761 if (inst.operands[0].isvec)
9763 if (inst.operands[1].reg != 1)
9764 first_error (_("operand 1 must be FPSCR"));
9765 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9766 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9767 do_vfp_nsyn_opcode ("fmstat");
9769 else if (inst.operands[1].isvec)
9770 do_vfp_nsyn_opcode ("fmrx");
9778 do_vfp_nsyn_msr (void)
9780 if (inst.operands[0].isvec)
9781 do_vfp_nsyn_opcode ("fmxr");
9791 unsigned Rt = inst.operands[0].reg;
9793 if (thumb_mode && Rt == REG_SP)
9795 inst.error = BAD_SP;
9799 /* MVFR2 is only valid at ARMv8-A. */
9800 if (inst.operands[1].reg == 5)
9801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9804 /* APSR_ sets isvec. All other refs to PC are illegal. */
9805 if (!inst.operands[0].isvec && Rt == REG_PC)
9807 inst.error = BAD_PC;
9811 /* If we get through parsing the register name, we just insert the number
9812 generated into the instruction without further validation. */
9813 inst.instruction |= (inst.operands[1].reg << 16);
9814 inst.instruction |= (Rt << 12);
9820 unsigned Rt = inst.operands[1].reg;
9823 reject_bad_reg (Rt);
9824 else if (Rt == REG_PC)
9826 inst.error = BAD_PC;
9830 /* MVFR2 is only valid for ARMv8-A. */
9831 if (inst.operands[0].reg == 5)
9832 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9835 /* If we get through parsing the register name, we just insert the number
9836 generated into the instruction without further validation. */
9837 inst.instruction |= (inst.operands[0].reg << 16);
9838 inst.instruction |= (Rt << 12);
9846 if (do_vfp_nsyn_mrs () == SUCCESS)
9849 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9850 inst.instruction |= inst.operands[0].reg << 12;
9852 if (inst.operands[1].isreg)
9854 br = inst.operands[1].reg;
9855 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
9856 as_bad (_("bad register for mrs"));
9860 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9861 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9863 _("'APSR', 'CPSR' or 'SPSR' expected"));
9864 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9867 inst.instruction |= br;
9870 /* Two possible forms:
9871 "{C|S}PSR_<field>, Rm",
9872 "{C|S}PSR_f, #expression". */
9877 if (do_vfp_nsyn_msr () == SUCCESS)
9880 inst.instruction |= inst.operands[0].imm;
9881 if (inst.operands[1].isreg)
9882 inst.instruction |= inst.operands[1].reg;
9885 inst.instruction |= INST_IMMEDIATE;
9886 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9887 inst.relocs[0].pc_rel = 0;
9894 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9896 if (!inst.operands[2].present)
9897 inst.operands[2].reg = inst.operands[0].reg;
9898 inst.instruction |= inst.operands[0].reg << 16;
9899 inst.instruction |= inst.operands[1].reg;
9900 inst.instruction |= inst.operands[2].reg << 8;
9902 if (inst.operands[0].reg == inst.operands[1].reg
9903 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9904 as_tsktsk (_("Rd and Rm should be different in mul"));
9907 /* Long Multiply Parser
9908 UMULL RdLo, RdHi, Rm, Rs
9909 SMULL RdLo, RdHi, Rm, Rs
9910 UMLAL RdLo, RdHi, Rm, Rs
9911 SMLAL RdLo, RdHi, Rm, Rs. */
9916 inst.instruction |= inst.operands[0].reg << 12;
9917 inst.instruction |= inst.operands[1].reg << 16;
9918 inst.instruction |= inst.operands[2].reg;
9919 inst.instruction |= inst.operands[3].reg << 8;
9921 /* rdhi and rdlo must be different. */
9922 if (inst.operands[0].reg == inst.operands[1].reg)
9923 as_tsktsk (_("rdhi and rdlo must be different"));
9925 /* rdhi, rdlo and rm must all be different before armv6. */
9926 if ((inst.operands[0].reg == inst.operands[2].reg
9927 || inst.operands[1].reg == inst.operands[2].reg)
9928 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9929 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9935 if (inst.operands[0].present
9936 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9938 /* Architectural NOP hints are CPSR sets with no bits selected. */
9939 inst.instruction &= 0xf0000000;
9940 inst.instruction |= 0x0320f000;
9941 if (inst.operands[0].present)
9942 inst.instruction |= inst.operands[0].imm;
9946 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9947 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9948 Condition defaults to COND_ALWAYS.
9949 Error if Rd, Rn or Rm are R15. */
9954 inst.instruction |= inst.operands[0].reg << 12;
9955 inst.instruction |= inst.operands[1].reg << 16;
9956 inst.instruction |= inst.operands[2].reg;
9957 if (inst.operands[3].present)
9958 encode_arm_shift (3);
9961 /* ARM V6 PKHTB (Argument Parse). */
9966 if (!inst.operands[3].present)
9968 /* If the shift specifier is omitted, turn the instruction
9969 into pkhbt rd, rm, rn. */
9970 inst.instruction &= 0xfff00010;
9971 inst.instruction |= inst.operands[0].reg << 12;
9972 inst.instruction |= inst.operands[1].reg;
9973 inst.instruction |= inst.operands[2].reg << 16;
9977 inst.instruction |= inst.operands[0].reg << 12;
9978 inst.instruction |= inst.operands[1].reg << 16;
9979 inst.instruction |= inst.operands[2].reg;
9980 encode_arm_shift (3);
9984 /* ARMv5TE: Preload-Cache
9985 MP Extensions: Preload for write
9989 Syntactically, like LDR with B=1, W=0, L=1. */
9994 constraint (!inst.operands[0].isreg,
9995 _("'[' expected after PLD mnemonic"));
9996 constraint (inst.operands[0].postind,
9997 _("post-indexed expression used in preload instruction"));
9998 constraint (inst.operands[0].writeback,
9999 _("writeback used in preload instruction"));
10000 constraint (!inst.operands[0].preind,
10001 _("unindexed addressing used in preload instruction"));
10002 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10005 /* ARMv7: PLI <addr_mode> */
10009 constraint (!inst.operands[0].isreg,
10010 _("'[' expected after PLI mnemonic"));
10011 constraint (inst.operands[0].postind,
10012 _("post-indexed expression used in preload instruction"));
10013 constraint (inst.operands[0].writeback,
10014 _("writeback used in preload instruction"));
10015 constraint (!inst.operands[0].preind,
10016 _("unindexed addressing used in preload instruction"));
10017 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10018 inst.instruction &= ~PRE_INDEX;
10024 constraint (inst.operands[0].writeback,
10025 _("push/pop do not support {reglist}^"));
10026 inst.operands[1] = inst.operands[0];
10027 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10028 inst.operands[0].isreg = 1;
10029 inst.operands[0].writeback = 1;
10030 inst.operands[0].reg = REG_SP;
10031 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
10034 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10035 word at the specified address and the following word
10037 Unconditionally executed.
10038 Error if Rn is R15. */
10043 inst.instruction |= inst.operands[0].reg << 16;
10044 if (inst.operands[0].writeback)
10045 inst.instruction |= WRITE_BACK;
10048 /* ARM V6 ssat (argument parse). */
10053 inst.instruction |= inst.operands[0].reg << 12;
10054 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10055 inst.instruction |= inst.operands[2].reg;
10057 if (inst.operands[3].present)
10058 encode_arm_shift (3);
10061 /* ARM V6 usat (argument parse). */
10066 inst.instruction |= inst.operands[0].reg << 12;
10067 inst.instruction |= inst.operands[1].imm << 16;
10068 inst.instruction |= inst.operands[2].reg;
10070 if (inst.operands[3].present)
10071 encode_arm_shift (3);
10074 /* ARM V6 ssat16 (argument parse). */
10079 inst.instruction |= inst.operands[0].reg << 12;
10080 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10081 inst.instruction |= inst.operands[2].reg;
10087 inst.instruction |= inst.operands[0].reg << 12;
10088 inst.instruction |= inst.operands[1].imm << 16;
10089 inst.instruction |= inst.operands[2].reg;
10092 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10093 preserving the other bits.
10095 setend <endian_specifier>, where <endian_specifier> is either
10101 if (warn_on_deprecated
10102 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10103 as_tsktsk (_("setend use is deprecated for ARMv8"));
10105 if (inst.operands[0].imm)
10106 inst.instruction |= 0x200;
10112 unsigned int Rm = (inst.operands[1].present
10113 ? inst.operands[1].reg
10114 : inst.operands[0].reg);
10116 inst.instruction |= inst.operands[0].reg << 12;
10117 inst.instruction |= Rm;
10118 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10120 inst.instruction |= inst.operands[2].reg << 8;
10121 inst.instruction |= SHIFT_BY_REG;
10122 /* PR 12854: Error on extraneous shifts. */
10123 constraint (inst.operands[2].shifted,
10124 _("extraneous shift as part of operand to shift insn"));
10127 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10133 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10134 inst.relocs[0].pc_rel = 0;
10140 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10141 inst.relocs[0].pc_rel = 0;
10147 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10148 inst.relocs[0].pc_rel = 0;
10154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10155 _("selected processor does not support SETPAN instruction"));
10157 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10164 _("selected processor does not support SETPAN instruction"));
10166 inst.instruction |= (inst.operands[0].imm << 3);
10169 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10170 SMLAxy{cond} Rd,Rm,Rs,Rn
10171 SMLAWy{cond} Rd,Rm,Rs,Rn
10172 Error if any register is R15. */
10177 inst.instruction |= inst.operands[0].reg << 16;
10178 inst.instruction |= inst.operands[1].reg;
10179 inst.instruction |= inst.operands[2].reg << 8;
10180 inst.instruction |= inst.operands[3].reg << 12;
10183 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10184 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10185 Error if any register is R15.
10186 Warning if Rdlo == Rdhi. */
10191 inst.instruction |= inst.operands[0].reg << 12;
10192 inst.instruction |= inst.operands[1].reg << 16;
10193 inst.instruction |= inst.operands[2].reg;
10194 inst.instruction |= inst.operands[3].reg << 8;
10196 if (inst.operands[0].reg == inst.operands[1].reg)
10197 as_tsktsk (_("rdhi and rdlo must be different"));
10200 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10201 SMULxy{cond} Rd,Rm,Rs
10202 Error if any register is R15. */
10207 inst.instruction |= inst.operands[0].reg << 16;
10208 inst.instruction |= inst.operands[1].reg;
10209 inst.instruction |= inst.operands[2].reg << 8;
10212 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10213 the same for both ARM and Thumb-2. */
10220 if (inst.operands[0].present)
10222 reg = inst.operands[0].reg;
10223 constraint (reg != REG_SP, _("SRS base register must be r13"));
10228 inst.instruction |= reg << 16;
10229 inst.instruction |= inst.operands[1].imm;
10230 if (inst.operands[0].writeback || inst.operands[1].writeback)
10231 inst.instruction |= WRITE_BACK;
10234 /* ARM V6 strex (argument parse). */
10239 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10240 || inst.operands[2].postind || inst.operands[2].writeback
10241 || inst.operands[2].immisreg || inst.operands[2].shifted
10242 || inst.operands[2].negative
10243 /* See comment in do_ldrex(). */
10244 || (inst.operands[2].reg == REG_PC),
10247 constraint (inst.operands[0].reg == inst.operands[1].reg
10248 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10250 constraint (inst.relocs[0].exp.X_op != O_constant
10251 || inst.relocs[0].exp.X_add_number != 0,
10252 _("offset must be zero in ARM encoding"));
10254 inst.instruction |= inst.operands[0].reg << 12;
10255 inst.instruction |= inst.operands[1].reg;
10256 inst.instruction |= inst.operands[2].reg << 16;
10257 inst.relocs[0].type = BFD_RELOC_UNUSED;
10261 do_t_strexbh (void)
10263 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10264 || inst.operands[2].postind || inst.operands[2].writeback
10265 || inst.operands[2].immisreg || inst.operands[2].shifted
10266 || inst.operands[2].negative,
10269 constraint (inst.operands[0].reg == inst.operands[1].reg
10270 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10278 constraint (inst.operands[1].reg % 2 != 0,
10279 _("even register required"));
10280 constraint (inst.operands[2].present
10281 && inst.operands[2].reg != inst.operands[1].reg + 1,
10282 _("can only store two consecutive registers"));
10283 /* If op 2 were present and equal to PC, this function wouldn't
10284 have been called in the first place. */
10285 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10287 constraint (inst.operands[0].reg == inst.operands[1].reg
10288 || inst.operands[0].reg == inst.operands[1].reg + 1
10289 || inst.operands[0].reg == inst.operands[3].reg,
10292 inst.instruction |= inst.operands[0].reg << 12;
10293 inst.instruction |= inst.operands[1].reg;
10294 inst.instruction |= inst.operands[3].reg << 16;
10301 constraint (inst.operands[0].reg == inst.operands[1].reg
10302 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10310 constraint (inst.operands[0].reg == inst.operands[1].reg
10311 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10316 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10317 extends it to 32-bits, and adds the result to a value in another
10318 register. You can specify a rotation by 0, 8, 16, or 24 bits
10319 before extracting the 16-bit value.
10320 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10321 Condition defaults to COND_ALWAYS.
10322 Error if any register uses R15. */
10327 inst.instruction |= inst.operands[0].reg << 12;
10328 inst.instruction |= inst.operands[1].reg << 16;
10329 inst.instruction |= inst.operands[2].reg;
10330 inst.instruction |= inst.operands[3].imm << 10;
10335 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10336 Condition defaults to COND_ALWAYS.
10337 Error if any register uses R15. */
10342 inst.instruction |= inst.operands[0].reg << 12;
10343 inst.instruction |= inst.operands[1].reg;
10344 inst.instruction |= inst.operands[2].imm << 10;
10347 /* VFP instructions. In a logical order: SP variant first, monad
10348 before dyad, arithmetic then move then load/store. */
10351 do_vfp_sp_monadic (void)
10353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10354 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10357 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10358 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10362 do_vfp_sp_dyadic (void)
10364 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10365 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10366 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10370 do_vfp_sp_compare_z (void)
10372 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10376 do_vfp_dp_sp_cvt (void)
10378 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10379 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10383 do_vfp_sp_dp_cvt (void)
10385 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10386 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10390 do_vfp_reg_from_sp (void)
10392 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10393 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10396 inst.instruction |= inst.operands[0].reg << 12;
10397 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10401 do_vfp_reg2_from_sp2 (void)
10403 constraint (inst.operands[2].imm != 2,
10404 _("only two consecutive VFP SP registers allowed here"));
10405 inst.instruction |= inst.operands[0].reg << 12;
10406 inst.instruction |= inst.operands[1].reg << 16;
10407 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10411 do_vfp_sp_from_reg (void)
10413 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10414 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10417 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10418 inst.instruction |= inst.operands[1].reg << 12;
10422 do_vfp_sp2_from_reg2 (void)
10424 constraint (inst.operands[0].imm != 2,
10425 _("only two consecutive VFP SP registers allowed here"));
10426 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10427 inst.instruction |= inst.operands[1].reg << 12;
10428 inst.instruction |= inst.operands[2].reg << 16;
10432 do_vfp_sp_ldst (void)
10434 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10435 encode_arm_cp_address (1, FALSE, TRUE, 0);
10439 do_vfp_dp_ldst (void)
10441 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10442 encode_arm_cp_address (1, FALSE, TRUE, 0);
10447 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
10449 if (inst.operands[0].writeback)
10450 inst.instruction |= WRITE_BACK;
10452 constraint (ldstm_type != VFP_LDSTMIA,
10453 _("this addressing mode requires base-register writeback"));
10454 inst.instruction |= inst.operands[0].reg << 16;
10455 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10456 inst.instruction |= inst.operands[1].imm;
10460 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
10464 if (inst.operands[0].writeback)
10465 inst.instruction |= WRITE_BACK;
10467 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10468 _("this addressing mode requires base-register writeback"));
10470 inst.instruction |= inst.operands[0].reg << 16;
10471 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10473 count = inst.operands[1].imm << 1;
10474 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10477 inst.instruction |= count;
10481 do_vfp_sp_ldstmia (void)
10483 vfp_sp_ldstm (VFP_LDSTMIA);
10487 do_vfp_sp_ldstmdb (void)
10489 vfp_sp_ldstm (VFP_LDSTMDB);
10493 do_vfp_dp_ldstmia (void)
10495 vfp_dp_ldstm (VFP_LDSTMIA);
10499 do_vfp_dp_ldstmdb (void)
10501 vfp_dp_ldstm (VFP_LDSTMDB);
10505 do_vfp_xp_ldstmia (void)
10507 vfp_dp_ldstm (VFP_LDSTMIAX);
10511 do_vfp_xp_ldstmdb (void)
10513 vfp_dp_ldstm (VFP_LDSTMDBX);
10517 do_vfp_dp_rd_rm (void)
10519 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10520 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10523 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10524 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10528 do_vfp_dp_rn_rd (void)
10530 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10531 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10535 do_vfp_dp_rd_rn (void)
10537 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10538 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10542 do_vfp_dp_rd_rn_rm (void)
10544 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10545 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10548 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10549 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10550 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10554 do_vfp_dp_rd (void)
10556 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10560 do_vfp_dp_rm_rd_rn (void)
10562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10563 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10566 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10567 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10568 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10571 /* VFPv3 instructions. */
10573 do_vfp_sp_const (void)
10575 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10576 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10577 inst.instruction |= (inst.operands[1].imm & 0x0f);
10581 do_vfp_dp_const (void)
10583 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10584 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10585 inst.instruction |= (inst.operands[1].imm & 0x0f);
10589 vfp_conv (int srcsize)
10591 int immbits = srcsize - inst.operands[1].imm;
10593 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10595 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10596 i.e. immbits must be in range 0 - 16. */
10597 inst.error = _("immediate value out of range, expected range [0, 16]");
10600 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
10602 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10603 i.e. immbits must be in range 0 - 31. */
10604 inst.error = _("immediate value out of range, expected range [1, 32]");
10608 inst.instruction |= (immbits & 1) << 5;
10609 inst.instruction |= (immbits >> 1);
10613 do_vfp_sp_conv_16 (void)
10615 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10620 do_vfp_dp_conv_16 (void)
10622 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10627 do_vfp_sp_conv_32 (void)
10629 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10634 do_vfp_dp_conv_32 (void)
10636 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10640 /* FPA instructions. Also in a logical order. */
10645 inst.instruction |= inst.operands[0].reg << 16;
10646 inst.instruction |= inst.operands[1].reg;
10650 do_fpa_ldmstm (void)
10652 inst.instruction |= inst.operands[0].reg << 12;
10653 switch (inst.operands[1].imm)
10655 case 1: inst.instruction |= CP_T_X; break;
10656 case 2: inst.instruction |= CP_T_Y; break;
10657 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10662 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10664 /* The instruction specified "ea" or "fd", so we can only accept
10665 [Rn]{!}. The instruction does not really support stacking or
10666 unstacking, so we have to emulate these by setting appropriate
10667 bits and offsets. */
10668 constraint (inst.relocs[0].exp.X_op != O_constant
10669 || inst.relocs[0].exp.X_add_number != 0,
10670 _("this instruction does not support indexing"));
10672 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
10673 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
10675 if (!(inst.instruction & INDEX_UP))
10676 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
10678 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10680 inst.operands[2].preind = 0;
10681 inst.operands[2].postind = 1;
10685 encode_arm_cp_address (2, TRUE, TRUE, 0);
10688 /* iWMMXt instructions: strictly in alphabetical order. */
10691 do_iwmmxt_tandorc (void)
10693 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10697 do_iwmmxt_textrc (void)
10699 inst.instruction |= inst.operands[0].reg << 12;
10700 inst.instruction |= inst.operands[1].imm;
10704 do_iwmmxt_textrm (void)
10706 inst.instruction |= inst.operands[0].reg << 12;
10707 inst.instruction |= inst.operands[1].reg << 16;
10708 inst.instruction |= inst.operands[2].imm;
10712 do_iwmmxt_tinsr (void)
10714 inst.instruction |= inst.operands[0].reg << 16;
10715 inst.instruction |= inst.operands[1].reg << 12;
10716 inst.instruction |= inst.operands[2].imm;
10720 do_iwmmxt_tmia (void)
10722 inst.instruction |= inst.operands[0].reg << 5;
10723 inst.instruction |= inst.operands[1].reg;
10724 inst.instruction |= inst.operands[2].reg << 12;
10728 do_iwmmxt_waligni (void)
10730 inst.instruction |= inst.operands[0].reg << 12;
10731 inst.instruction |= inst.operands[1].reg << 16;
10732 inst.instruction |= inst.operands[2].reg;
10733 inst.instruction |= inst.operands[3].imm << 20;
10737 do_iwmmxt_wmerge (void)
10739 inst.instruction |= inst.operands[0].reg << 12;
10740 inst.instruction |= inst.operands[1].reg << 16;
10741 inst.instruction |= inst.operands[2].reg;
10742 inst.instruction |= inst.operands[3].imm << 21;
10746 do_iwmmxt_wmov (void)
10748 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10749 inst.instruction |= inst.operands[0].reg << 12;
10750 inst.instruction |= inst.operands[1].reg << 16;
10751 inst.instruction |= inst.operands[1].reg;
10755 do_iwmmxt_wldstbh (void)
10758 inst.instruction |= inst.operands[0].reg << 12;
10760 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10762 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10763 encode_arm_cp_address (1, TRUE, FALSE, reloc);
10767 do_iwmmxt_wldstw (void)
10769 /* RIWR_RIWC clears .isreg for a control register. */
10770 if (!inst.operands[0].isreg)
10772 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10773 inst.instruction |= 0xf0000000;
10776 inst.instruction |= inst.operands[0].reg << 12;
10777 encode_arm_cp_address (1, TRUE, TRUE, 0);
10781 do_iwmmxt_wldstd (void)
10783 inst.instruction |= inst.operands[0].reg << 12;
10784 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10785 && inst.operands[1].immisreg)
10787 inst.instruction &= ~0x1a000ff;
10788 inst.instruction |= (0xfU << 28);
10789 if (inst.operands[1].preind)
10790 inst.instruction |= PRE_INDEX;
10791 if (!inst.operands[1].negative)
10792 inst.instruction |= INDEX_UP;
10793 if (inst.operands[1].writeback)
10794 inst.instruction |= WRITE_BACK;
10795 inst.instruction |= inst.operands[1].reg << 16;
10796 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
10797 inst.instruction |= inst.operands[1].imm;
10800 encode_arm_cp_address (1, TRUE, FALSE, 0);
10804 do_iwmmxt_wshufh (void)
10806 inst.instruction |= inst.operands[0].reg << 12;
10807 inst.instruction |= inst.operands[1].reg << 16;
10808 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10809 inst.instruction |= (inst.operands[2].imm & 0x0f);
10813 do_iwmmxt_wzero (void)
10815 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10816 inst.instruction |= inst.operands[0].reg;
10817 inst.instruction |= inst.operands[0].reg << 12;
10818 inst.instruction |= inst.operands[0].reg << 16;
10822 do_iwmmxt_wrwrwr_or_imm5 (void)
10824 if (inst.operands[2].isreg)
10827 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10828 _("immediate operand requires iWMMXt2"));
10830 if (inst.operands[2].imm == 0)
10832 switch ((inst.instruction >> 20) & 0xf)
10838 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10839 inst.operands[2].imm = 16;
10840 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10846 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10847 inst.operands[2].imm = 32;
10848 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10855 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10857 wrn = (inst.instruction >> 16) & 0xf;
10858 inst.instruction &= 0xff0fff0f;
10859 inst.instruction |= wrn;
10860 /* Bail out here; the instruction is now assembled. */
10865 /* Map 32 -> 0, etc. */
10866 inst.operands[2].imm &= 0x1f;
10867 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10871 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10872 operations first, then control, shift, and load/store. */
10874 /* Insns like "foo X,Y,Z". */
10877 do_mav_triple (void)
10879 inst.instruction |= inst.operands[0].reg << 16;
10880 inst.instruction |= inst.operands[1].reg;
10881 inst.instruction |= inst.operands[2].reg << 12;
10884 /* Insns like "foo W,X,Y,Z".
10885 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10890 inst.instruction |= inst.operands[0].reg << 5;
10891 inst.instruction |= inst.operands[1].reg << 12;
10892 inst.instruction |= inst.operands[2].reg << 16;
10893 inst.instruction |= inst.operands[3].reg;
10896 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10898 do_mav_dspsc (void)
10900 inst.instruction |= inst.operands[1].reg << 12;
10903 /* Maverick shift immediate instructions.
10904 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10905 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10908 do_mav_shift (void)
10910 int imm = inst.operands[2].imm;
10912 inst.instruction |= inst.operands[0].reg << 12;
10913 inst.instruction |= inst.operands[1].reg << 16;
10915 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10916 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10917 Bit 4 should be 0. */
10918 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10920 inst.instruction |= imm;
10923 /* XScale instructions. Also sorted arithmetic before move. */
10925 /* Xscale multiply-accumulate (argument parse)
10928 MIAxycc acc0,Rm,Rs. */
10933 inst.instruction |= inst.operands[1].reg;
10934 inst.instruction |= inst.operands[2].reg << 12;
10937 /* Xscale move-accumulator-register (argument parse)
10939 MARcc acc0,RdLo,RdHi. */
10944 inst.instruction |= inst.operands[1].reg << 12;
10945 inst.instruction |= inst.operands[2].reg << 16;
10948 /* Xscale move-register-accumulator (argument parse)
10950 MRAcc RdLo,RdHi,acc0. */
10955 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10956 inst.instruction |= inst.operands[0].reg << 12;
10957 inst.instruction |= inst.operands[1].reg << 16;
10960 /* Encoding functions relevant only to Thumb. */
10962 /* inst.operands[i] is a shifted-register operand; encode
10963 it into inst.instruction in the format used by Thumb32. */
10966 encode_thumb32_shifted_operand (int i)
10968 unsigned int value = inst.relocs[0].exp.X_add_number;
10969 unsigned int shift = inst.operands[i].shift_kind;
10971 constraint (inst.operands[i].immisreg,
10972 _("shift by register not allowed in thumb mode"));
10973 inst.instruction |= inst.operands[i].reg;
10974 if (shift == SHIFT_RRX)
10975 inst.instruction |= SHIFT_ROR << 4;
10978 constraint (inst.relocs[0].exp.X_op != O_constant,
10979 _("expression too complex"));
10981 constraint (value > 32
10982 || (value == 32 && (shift == SHIFT_LSL
10983 || shift == SHIFT_ROR)),
10984 _("shift expression is too large"));
10988 else if (value == 32)
10991 inst.instruction |= shift << 4;
10992 inst.instruction |= (value & 0x1c) << 10;
10993 inst.instruction |= (value & 0x03) << 6;
10998 /* inst.operands[i] was set up by parse_address. Encode it into a
10999 Thumb32 format load or store instruction. Reject forms that cannot
11000 be used with such instructions. If is_t is true, reject forms that
11001 cannot be used with a T instruction; if is_d is true, reject forms
11002 that cannot be used with a D instruction. If it is a store insn,
11003 reject PC in Rn. */
11006 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11008 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
11010 constraint (!inst.operands[i].isreg,
11011 _("Instruction does not support =N addresses"));
11013 inst.instruction |= inst.operands[i].reg << 16;
11014 if (inst.operands[i].immisreg)
11016 constraint (is_pc, BAD_PC_ADDRESSING);
11017 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11018 constraint (inst.operands[i].negative,
11019 _("Thumb does not support negative register indexing"));
11020 constraint (inst.operands[i].postind,
11021 _("Thumb does not support register post-indexing"));
11022 constraint (inst.operands[i].writeback,
11023 _("Thumb does not support register indexing with writeback"));
11024 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11025 _("Thumb supports only LSL in shifted register indexing"));
11027 inst.instruction |= inst.operands[i].imm;
11028 if (inst.operands[i].shifted)
11030 constraint (inst.relocs[0].exp.X_op != O_constant,
11031 _("expression too complex"));
11032 constraint (inst.relocs[0].exp.X_add_number < 0
11033 || inst.relocs[0].exp.X_add_number > 3,
11034 _("shift out of range"));
11035 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11037 inst.relocs[0].type = BFD_RELOC_UNUSED;
11039 else if (inst.operands[i].preind)
11041 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11042 constraint (is_t && inst.operands[i].writeback,
11043 _("cannot use writeback with this instruction"));
11044 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11045 BAD_PC_ADDRESSING);
11049 inst.instruction |= 0x01000000;
11050 if (inst.operands[i].writeback)
11051 inst.instruction |= 0x00200000;
11055 inst.instruction |= 0x00000c00;
11056 if (inst.operands[i].writeback)
11057 inst.instruction |= 0x00000100;
11059 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11061 else if (inst.operands[i].postind)
11063 gas_assert (inst.operands[i].writeback);
11064 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11065 constraint (is_t, _("cannot use post-indexing with this instruction"));
11068 inst.instruction |= 0x00200000;
11070 inst.instruction |= 0x00000900;
11071 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11073 else /* unindexed - only for coprocessor */
11074 inst.error = _("instruction does not accept unindexed addressing");
11077 /* Table of Thumb instructions which exist in both 16- and 32-bit
11078 encodings (the latter only in post-V6T2 cores). The index is the
11079 value used in the insns table below. When there is more than one
11080 possible 16-bit encoding for the instruction, this table always
11082 Also contains several pseudo-instructions used during relaxation. */
11083 #define T16_32_TAB \
11084 X(_adc, 4140, eb400000), \
11085 X(_adcs, 4140, eb500000), \
11086 X(_add, 1c00, eb000000), \
11087 X(_adds, 1c00, eb100000), \
11088 X(_addi, 0000, f1000000), \
11089 X(_addis, 0000, f1100000), \
11090 X(_add_pc,000f, f20f0000), \
11091 X(_add_sp,000d, f10d0000), \
11092 X(_adr, 000f, f20f0000), \
11093 X(_and, 4000, ea000000), \
11094 X(_ands, 4000, ea100000), \
11095 X(_asr, 1000, fa40f000), \
11096 X(_asrs, 1000, fa50f000), \
11097 X(_b, e000, f000b000), \
11098 X(_bcond, d000, f0008000), \
11099 X(_bf, 0000, f040e001), \
11100 X(_bfcsel,0000, f000e001), \
11101 X(_bfx, 0000, f060e001), \
11102 X(_bfl, 0000, f000c001), \
11103 X(_bflx, 0000, f070e001), \
11104 X(_bic, 4380, ea200000), \
11105 X(_bics, 4380, ea300000), \
11106 X(_cmn, 42c0, eb100f00), \
11107 X(_cmp, 2800, ebb00f00), \
11108 X(_cpsie, b660, f3af8400), \
11109 X(_cpsid, b670, f3af8600), \
11110 X(_cpy, 4600, ea4f0000), \
11111 X(_dec_sp,80dd, f1ad0d00), \
11112 X(_dls, 0000, f040e001), \
11113 X(_eor, 4040, ea800000), \
11114 X(_eors, 4040, ea900000), \
11115 X(_inc_sp,00dd, f10d0d00), \
11116 X(_ldmia, c800, e8900000), \
11117 X(_ldr, 6800, f8500000), \
11118 X(_ldrb, 7800, f8100000), \
11119 X(_ldrh, 8800, f8300000), \
11120 X(_ldrsb, 5600, f9100000), \
11121 X(_ldrsh, 5e00, f9300000), \
11122 X(_ldr_pc,4800, f85f0000), \
11123 X(_ldr_pc2,4800, f85f0000), \
11124 X(_ldr_sp,9800, f85d0000), \
11125 X(_le, 0000, f00fc001), \
11126 X(_lsl, 0000, fa00f000), \
11127 X(_lsls, 0000, fa10f000), \
11128 X(_lsr, 0800, fa20f000), \
11129 X(_lsrs, 0800, fa30f000), \
11130 X(_mov, 2000, ea4f0000), \
11131 X(_movs, 2000, ea5f0000), \
11132 X(_mul, 4340, fb00f000), \
11133 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11134 X(_mvn, 43c0, ea6f0000), \
11135 X(_mvns, 43c0, ea7f0000), \
11136 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11137 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11138 X(_orr, 4300, ea400000), \
11139 X(_orrs, 4300, ea500000), \
11140 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11141 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11142 X(_rev, ba00, fa90f080), \
11143 X(_rev16, ba40, fa90f090), \
11144 X(_revsh, bac0, fa90f0b0), \
11145 X(_ror, 41c0, fa60f000), \
11146 X(_rors, 41c0, fa70f000), \
11147 X(_sbc, 4180, eb600000), \
11148 X(_sbcs, 4180, eb700000), \
11149 X(_stmia, c000, e8800000), \
11150 X(_str, 6000, f8400000), \
11151 X(_strb, 7000, f8000000), \
11152 X(_strh, 8000, f8200000), \
11153 X(_str_sp,9000, f84d0000), \
11154 X(_sub, 1e00, eba00000), \
11155 X(_subs, 1e00, ebb00000), \
11156 X(_subi, 8000, f1a00000), \
11157 X(_subis, 8000, f1b00000), \
11158 X(_sxtb, b240, fa4ff080), \
11159 X(_sxth, b200, fa0ff080), \
11160 X(_tst, 4200, ea100f00), \
11161 X(_uxtb, b2c0, fa5ff080), \
11162 X(_uxth, b280, fa1ff080), \
11163 X(_nop, bf00, f3af8000), \
11164 X(_yield, bf10, f3af8001), \
11165 X(_wfe, bf20, f3af8002), \
11166 X(_wfi, bf30, f3af8003), \
11167 X(_wls, 0000, f040c001), \
11168 X(_sev, bf40, f3af8004), \
11169 X(_sevl, bf50, f3af8005), \
11170 X(_udf, de00, f7f0a000)
11172 /* To catch errors in encoding functions, the codes are all offset by
11173 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11174 as 16-bit instructions. */
11175 #define X(a,b,c) T_MNEM##a
11176 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11179 #define X(a,b,c) 0x##b
11180 static const unsigned short thumb_op16[] = { T16_32_TAB };
11181 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11184 #define X(a,b,c) 0x##c
11185 static const unsigned int thumb_op32[] = { T16_32_TAB };
11186 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11187 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11191 /* Thumb instruction encoders, in alphabetical order. */
11193 /* ADDW or SUBW. */
11196 do_t_add_sub_w (void)
11200 Rd = inst.operands[0].reg;
11201 Rn = inst.operands[1].reg;
11203 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11204 is the SP-{plus,minus}-immediate form of the instruction. */
11206 constraint (Rd == REG_PC, BAD_PC);
11208 reject_bad_reg (Rd);
11210 inst.instruction |= (Rn << 16) | (Rd << 8);
11211 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11214 /* Parse an add or subtract instruction. We get here with inst.instruction
11215 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11218 do_t_add_sub (void)
11222 Rd = inst.operands[0].reg;
11223 Rs = (inst.operands[1].present
11224 ? inst.operands[1].reg /* Rd, Rs, foo */
11225 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11228 set_pred_insn_type_last ();
11230 if (unified_syntax)
11233 bfd_boolean narrow;
11236 flags = (inst.instruction == T_MNEM_adds
11237 || inst.instruction == T_MNEM_subs);
11239 narrow = !in_pred_block ();
11241 narrow = in_pred_block ();
11242 if (!inst.operands[2].isreg)
11246 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11247 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11249 add = (inst.instruction == T_MNEM_add
11250 || inst.instruction == T_MNEM_adds);
11252 if (inst.size_req != 4)
11254 /* Attempt to use a narrow opcode, with relaxation if
11256 if (Rd == REG_SP && Rs == REG_SP && !flags)
11257 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11258 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11259 opcode = T_MNEM_add_sp;
11260 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11261 opcode = T_MNEM_add_pc;
11262 else if (Rd <= 7 && Rs <= 7 && narrow)
11265 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11267 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11271 inst.instruction = THUMB_OP16(opcode);
11272 inst.instruction |= (Rd << 4) | Rs;
11273 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11274 || (inst.relocs[0].type
11275 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
11277 if (inst.size_req == 2)
11278 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11280 inst.relax = opcode;
11284 constraint (inst.size_req == 2, BAD_HIREG);
11286 if (inst.size_req == 4
11287 || (inst.size_req != 2 && !opcode))
11289 constraint ((inst.relocs[0].type
11290 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11291 && (inst.relocs[0].type
11292 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
11293 THUMB1_RELOC_ONLY);
11296 constraint (add, BAD_PC);
11297 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11298 _("only SUBS PC, LR, #const allowed"));
11299 constraint (inst.relocs[0].exp.X_op != O_constant,
11300 _("expression too complex"));
11301 constraint (inst.relocs[0].exp.X_add_number < 0
11302 || inst.relocs[0].exp.X_add_number > 0xff,
11303 _("immediate value out of range"));
11304 inst.instruction = T2_SUBS_PC_LR
11305 | inst.relocs[0].exp.X_add_number;
11306 inst.relocs[0].type = BFD_RELOC_UNUSED;
11309 else if (Rs == REG_PC)
11311 /* Always use addw/subw. */
11312 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11313 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11317 inst.instruction = THUMB_OP32 (inst.instruction);
11318 inst.instruction = (inst.instruction & 0xe1ffffff)
11321 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11323 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11325 inst.instruction |= Rd << 8;
11326 inst.instruction |= Rs << 16;
11331 unsigned int value = inst.relocs[0].exp.X_add_number;
11332 unsigned int shift = inst.operands[2].shift_kind;
11334 Rn = inst.operands[2].reg;
11335 /* See if we can do this with a 16-bit instruction. */
11336 if (!inst.operands[2].shifted && inst.size_req != 4)
11338 if (Rd > 7 || Rs > 7 || Rn > 7)
11343 inst.instruction = ((inst.instruction == T_MNEM_adds
11344 || inst.instruction == T_MNEM_add)
11346 : T_OPCODE_SUB_R3);
11347 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11351 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11353 /* Thumb-1 cores (except v6-M) require at least one high
11354 register in a narrow non flag setting add. */
11355 if (Rd > 7 || Rn > 7
11356 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11357 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
11364 inst.instruction = T_OPCODE_ADD_HI;
11365 inst.instruction |= (Rd & 8) << 4;
11366 inst.instruction |= (Rd & 7);
11367 inst.instruction |= Rn << 3;
11373 constraint (Rd == REG_PC, BAD_PC);
11374 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11375 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11376 constraint (Rs == REG_PC, BAD_PC);
11377 reject_bad_reg (Rn);
11379 /* If we get here, it can't be done in 16 bits. */
11380 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11381 _("shift must be constant"));
11382 inst.instruction = THUMB_OP32 (inst.instruction);
11383 inst.instruction |= Rd << 8;
11384 inst.instruction |= Rs << 16;
11385 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11386 _("shift value over 3 not allowed in thumb mode"));
11387 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11388 _("only LSL shift allowed in thumb mode"));
11389 encode_thumb32_shifted_operand (2);
11394 constraint (inst.instruction == T_MNEM_adds
11395 || inst.instruction == T_MNEM_subs,
11398 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11400 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11401 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11404 inst.instruction = (inst.instruction == T_MNEM_add
11405 ? 0x0000 : 0x8000);
11406 inst.instruction |= (Rd << 4) | Rs;
11407 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11411 Rn = inst.operands[2].reg;
11412 constraint (inst.operands[2].shifted, _("unshifted register required"));
11414 /* We now have Rd, Rs, and Rn set to registers. */
11415 if (Rd > 7 || Rs > 7 || Rn > 7)
11417 /* Can't do this for SUB. */
11418 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11419 inst.instruction = T_OPCODE_ADD_HI;
11420 inst.instruction |= (Rd & 8) << 4;
11421 inst.instruction |= (Rd & 7);
11423 inst.instruction |= Rn << 3;
11425 inst.instruction |= Rs << 3;
11427 constraint (1, _("dest must overlap one source register"));
11431 inst.instruction = (inst.instruction == T_MNEM_add
11432 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11433 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11443 Rd = inst.operands[0].reg;
11444 reject_bad_reg (Rd);
11446 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11448 /* Defer to section relaxation. */
11449 inst.relax = inst.instruction;
11450 inst.instruction = THUMB_OP16 (inst.instruction);
11451 inst.instruction |= Rd << 4;
11453 else if (unified_syntax && inst.size_req != 2)
11455 /* Generate a 32-bit opcode. */
11456 inst.instruction = THUMB_OP32 (inst.instruction);
11457 inst.instruction |= Rd << 8;
11458 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11459 inst.relocs[0].pc_rel = 1;
11463 /* Generate a 16-bit opcode. */
11464 inst.instruction = THUMB_OP16 (inst.instruction);
11465 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11466 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11467 inst.relocs[0].pc_rel = 1;
11468 inst.instruction |= Rd << 4;
11471 if (inst.relocs[0].exp.X_op == O_symbol
11472 && inst.relocs[0].exp.X_add_symbol != NULL
11473 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11474 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11475 inst.relocs[0].exp.X_add_number += 1;
11478 /* Arithmetic instructions for which there is just one 16-bit
11479 instruction encoding, and it allows only two low registers.
11480 For maximal compatibility with ARM syntax, we allow three register
11481 operands even when Thumb-32 instructions are not available, as long
11482 as the first two are identical. For instance, both "sbc r0,r1" and
11483 "sbc r0,r0,r1" are allowed. */
11489 Rd = inst.operands[0].reg;
11490 Rs = (inst.operands[1].present
11491 ? inst.operands[1].reg /* Rd, Rs, foo */
11492 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11493 Rn = inst.operands[2].reg;
11495 reject_bad_reg (Rd);
11496 reject_bad_reg (Rs);
11497 if (inst.operands[2].isreg)
11498 reject_bad_reg (Rn);
11500 if (unified_syntax)
11502 if (!inst.operands[2].isreg)
11504 /* For an immediate, we always generate a 32-bit opcode;
11505 section relaxation will shrink it later if possible. */
11506 inst.instruction = THUMB_OP32 (inst.instruction);
11507 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11508 inst.instruction |= Rd << 8;
11509 inst.instruction |= Rs << 16;
11510 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11514 bfd_boolean narrow;
11516 /* See if we can do this with a 16-bit instruction. */
11517 if (THUMB_SETS_FLAGS (inst.instruction))
11518 narrow = !in_pred_block ();
11520 narrow = in_pred_block ();
11522 if (Rd > 7 || Rn > 7 || Rs > 7)
11524 if (inst.operands[2].shifted)
11526 if (inst.size_req == 4)
11532 inst.instruction = THUMB_OP16 (inst.instruction);
11533 inst.instruction |= Rd;
11534 inst.instruction |= Rn << 3;
11538 /* If we get here, it can't be done in 16 bits. */
11539 constraint (inst.operands[2].shifted
11540 && inst.operands[2].immisreg,
11541 _("shift must be constant"));
11542 inst.instruction = THUMB_OP32 (inst.instruction);
11543 inst.instruction |= Rd << 8;
11544 inst.instruction |= Rs << 16;
11545 encode_thumb32_shifted_operand (2);
11550 /* On its face this is a lie - the instruction does set the
11551 flags. However, the only supported mnemonic in this mode
11552 says it doesn't. */
11553 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11555 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11556 _("unshifted register required"));
11557 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11558 constraint (Rd != Rs,
11559 _("dest and source1 must be the same register"));
11561 inst.instruction = THUMB_OP16 (inst.instruction);
11562 inst.instruction |= Rd;
11563 inst.instruction |= Rn << 3;
11567 /* Similarly, but for instructions where the arithmetic operation is
11568 commutative, so we can allow either of them to be different from
11569 the destination operand in a 16-bit instruction. For instance, all
11570 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11577 Rd = inst.operands[0].reg;
11578 Rs = (inst.operands[1].present
11579 ? inst.operands[1].reg /* Rd, Rs, foo */
11580 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11581 Rn = inst.operands[2].reg;
11583 reject_bad_reg (Rd);
11584 reject_bad_reg (Rs);
11585 if (inst.operands[2].isreg)
11586 reject_bad_reg (Rn);
11588 if (unified_syntax)
11590 if (!inst.operands[2].isreg)
11592 /* For an immediate, we always generate a 32-bit opcode;
11593 section relaxation will shrink it later if possible. */
11594 inst.instruction = THUMB_OP32 (inst.instruction);
11595 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11596 inst.instruction |= Rd << 8;
11597 inst.instruction |= Rs << 16;
11598 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11602 bfd_boolean narrow;
11604 /* See if we can do this with a 16-bit instruction. */
11605 if (THUMB_SETS_FLAGS (inst.instruction))
11606 narrow = !in_pred_block ();
11608 narrow = in_pred_block ();
11610 if (Rd > 7 || Rn > 7 || Rs > 7)
11612 if (inst.operands[2].shifted)
11614 if (inst.size_req == 4)
11621 inst.instruction = THUMB_OP16 (inst.instruction);
11622 inst.instruction |= Rd;
11623 inst.instruction |= Rn << 3;
11628 inst.instruction = THUMB_OP16 (inst.instruction);
11629 inst.instruction |= Rd;
11630 inst.instruction |= Rs << 3;
11635 /* If we get here, it can't be done in 16 bits. */
11636 constraint (inst.operands[2].shifted
11637 && inst.operands[2].immisreg,
11638 _("shift must be constant"));
11639 inst.instruction = THUMB_OP32 (inst.instruction);
11640 inst.instruction |= Rd << 8;
11641 inst.instruction |= Rs << 16;
11642 encode_thumb32_shifted_operand (2);
11647 /* On its face this is a lie - the instruction does set the
11648 flags. However, the only supported mnemonic in this mode
11649 says it doesn't. */
11650 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11652 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11653 _("unshifted register required"));
11654 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11656 inst.instruction = THUMB_OP16 (inst.instruction);
11657 inst.instruction |= Rd;
11660 inst.instruction |= Rn << 3;
11662 inst.instruction |= Rs << 3;
11664 constraint (1, _("dest must overlap one source register"));
11672 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11673 constraint (msb > 32, _("bit-field extends past end of register"));
11674 /* The instruction encoding stores the LSB and MSB,
11675 not the LSB and width. */
11676 Rd = inst.operands[0].reg;
11677 reject_bad_reg (Rd);
11678 inst.instruction |= Rd << 8;
11679 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11680 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11681 inst.instruction |= msb - 1;
11690 Rd = inst.operands[0].reg;
11691 reject_bad_reg (Rd);
11693 /* #0 in second position is alternative syntax for bfc, which is
11694 the same instruction but with REG_PC in the Rm field. */
11695 if (!inst.operands[1].isreg)
11699 Rn = inst.operands[1].reg;
11700 reject_bad_reg (Rn);
11703 msb = inst.operands[2].imm + inst.operands[3].imm;
11704 constraint (msb > 32, _("bit-field extends past end of register"));
11705 /* The instruction encoding stores the LSB and MSB,
11706 not the LSB and width. */
11707 inst.instruction |= Rd << 8;
11708 inst.instruction |= Rn << 16;
11709 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11710 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11711 inst.instruction |= msb - 1;
11719 Rd = inst.operands[0].reg;
11720 Rn = inst.operands[1].reg;
11722 reject_bad_reg (Rd);
11723 reject_bad_reg (Rn);
11725 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11726 _("bit-field extends past end of register"));
11727 inst.instruction |= Rd << 8;
11728 inst.instruction |= Rn << 16;
11729 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11730 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11731 inst.instruction |= inst.operands[3].imm - 1;
11734 /* ARM V5 Thumb BLX (argument parse)
11735 BLX <target_addr> which is BLX(1)
11736 BLX <Rm> which is BLX(2)
11737 Unfortunately, there are two different opcodes for this mnemonic.
11738 So, the insns[].value is not used, and the code here zaps values
11739 into inst.instruction.
11741 ??? How to take advantage of the additional two bits of displacement
11742 available in Thumb32 mode? Need new relocation? */
11747 set_pred_insn_type_last ();
11749 if (inst.operands[0].isreg)
11751 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11752 /* We have a register, so this is BLX(2). */
11753 inst.instruction |= inst.operands[0].reg << 3;
11757 /* No register. This must be BLX(1). */
11758 inst.instruction = 0xf000e800;
11759 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
11768 bfd_reloc_code_real_type reloc;
11771 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
11773 if (in_pred_block ())
11775 /* Conditional branches inside IT blocks are encoded as unconditional
11777 cond = COND_ALWAYS;
11782 if (cond != COND_ALWAYS)
11783 opcode = T_MNEM_bcond;
11785 opcode = inst.instruction;
11788 && (inst.size_req == 4
11789 || (inst.size_req != 2
11790 && (inst.operands[0].hasreloc
11791 || inst.relocs[0].exp.X_op == O_constant))))
11793 inst.instruction = THUMB_OP32(opcode);
11794 if (cond == COND_ALWAYS)
11795 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11799 _("selected architecture does not support "
11800 "wide conditional branch instruction"));
11802 gas_assert (cond != 0xF);
11803 inst.instruction |= cond << 22;
11804 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11809 inst.instruction = THUMB_OP16(opcode);
11810 if (cond == COND_ALWAYS)
11811 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11814 inst.instruction |= cond << 8;
11815 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11817 /* Allow section relaxation. */
11818 if (unified_syntax && inst.size_req != 2)
11819 inst.relax = opcode;
11821 inst.relocs[0].type = reloc;
11822 inst.relocs[0].pc_rel = 1;
11825 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11826 between the two is the maximum immediate allowed - which is passed in
11829 do_t_bkpt_hlt1 (int range)
11831 constraint (inst.cond != COND_ALWAYS,
11832 _("instruction is always unconditional"));
11833 if (inst.operands[0].present)
11835 constraint (inst.operands[0].imm > range,
11836 _("immediate value out of range"));
11837 inst.instruction |= inst.operands[0].imm;
11840 set_pred_insn_type (NEUTRAL_IT_INSN);
11846 do_t_bkpt_hlt1 (63);
11852 do_t_bkpt_hlt1 (255);
11856 do_t_branch23 (void)
11858 set_pred_insn_type_last ();
11859 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11861 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11862 this file. We used to simply ignore the PLT reloc type here --
11863 the branch encoding is now needed to deal with TLSCALL relocs.
11864 So if we see a PLT reloc now, put it back to how it used to be to
11865 keep the preexisting behaviour. */
11866 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
11867 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11869 #if defined(OBJ_COFF)
11870 /* If the destination of the branch is a defined symbol which does not have
11871 the THUMB_FUNC attribute, then we must be calling a function which has
11872 the (interfacearm) attribute. We look for the Thumb entry point to that
11873 function and change the branch to refer to that function instead. */
11874 if ( inst.relocs[0].exp.X_op == O_symbol
11875 && inst.relocs[0].exp.X_add_symbol != NULL
11876 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11877 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11878 inst.relocs[0].exp.X_add_symbol
11879 = find_real_start (inst.relocs[0].exp.X_add_symbol);
11886 set_pred_insn_type_last ();
11887 inst.instruction |= inst.operands[0].reg << 3;
11888 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11889 should cause the alignment to be checked once it is known. This is
11890 because BX PC only works if the instruction is word aligned. */
11898 set_pred_insn_type_last ();
11899 Rm = inst.operands[0].reg;
11900 reject_bad_reg (Rm);
11901 inst.instruction |= Rm << 16;
11910 Rd = inst.operands[0].reg;
11911 Rm = inst.operands[1].reg;
11913 reject_bad_reg (Rd);
11914 reject_bad_reg (Rm);
11916 inst.instruction |= Rd << 8;
11917 inst.instruction |= Rm << 16;
11918 inst.instruction |= Rm;
11924 set_pred_insn_type (OUTSIDE_PRED_INSN);
11930 set_pred_insn_type (OUTSIDE_PRED_INSN);
11931 inst.instruction |= inst.operands[0].imm;
11937 set_pred_insn_type (OUTSIDE_PRED_INSN);
11939 && (inst.operands[1].present || inst.size_req == 4)
11940 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11942 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11943 inst.instruction = 0xf3af8000;
11944 inst.instruction |= imod << 9;
11945 inst.instruction |= inst.operands[0].imm << 5;
11946 if (inst.operands[1].present)
11947 inst.instruction |= 0x100 | inst.operands[1].imm;
11951 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11952 && (inst.operands[0].imm & 4),
11953 _("selected processor does not support 'A' form "
11954 "of this instruction"));
11955 constraint (inst.operands[1].present || inst.size_req == 4,
11956 _("Thumb does not support the 2-argument "
11957 "form of this instruction"));
11958 inst.instruction |= inst.operands[0].imm;
11962 /* THUMB CPY instruction (argument parse). */
11967 if (inst.size_req == 4)
11969 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11970 inst.instruction |= inst.operands[0].reg << 8;
11971 inst.instruction |= inst.operands[1].reg;
11975 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11976 inst.instruction |= (inst.operands[0].reg & 0x7);
11977 inst.instruction |= inst.operands[1].reg << 3;
11984 set_pred_insn_type (OUTSIDE_PRED_INSN);
11985 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11986 inst.instruction |= inst.operands[0].reg;
11987 inst.relocs[0].pc_rel = 1;
11988 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11994 inst.instruction |= inst.operands[0].imm;
12000 unsigned Rd, Rn, Rm;
12002 Rd = inst.operands[0].reg;
12003 Rn = (inst.operands[1].present
12004 ? inst.operands[1].reg : Rd);
12005 Rm = inst.operands[2].reg;
12007 reject_bad_reg (Rd);
12008 reject_bad_reg (Rn);
12009 reject_bad_reg (Rm);
12011 inst.instruction |= Rd << 8;
12012 inst.instruction |= Rn << 16;
12013 inst.instruction |= Rm;
12019 if (unified_syntax && inst.size_req == 4)
12020 inst.instruction = THUMB_OP32 (inst.instruction);
12022 inst.instruction = THUMB_OP16 (inst.instruction);
12028 unsigned int cond = inst.operands[0].imm;
12030 set_pred_insn_type (IT_INSN);
12031 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12032 now_pred.cc = cond;
12033 now_pred.warn_deprecated = FALSE;
12034 now_pred.type = SCALAR_PRED;
12036 /* If the condition is a negative condition, invert the mask. */
12037 if ((cond & 0x1) == 0x0)
12039 unsigned int mask = inst.instruction & 0x000f;
12041 if ((mask & 0x7) == 0)
12043 /* No conversion needed. */
12044 now_pred.block_length = 1;
12046 else if ((mask & 0x3) == 0)
12049 now_pred.block_length = 2;
12051 else if ((mask & 0x1) == 0)
12054 now_pred.block_length = 3;
12059 now_pred.block_length = 4;
12062 inst.instruction &= 0xfff0;
12063 inst.instruction |= mask;
12066 inst.instruction |= cond << 4;
12069 /* Helper function used for both push/pop and ldm/stm. */
12071 encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12072 bfd_boolean writeback)
12074 bfd_boolean load, store;
12076 gas_assert (base != -1 || !do_io);
12077 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12078 store = do_io && !load;
12080 if (mask & (1 << 13))
12081 inst.error = _("SP not allowed in register list");
12083 if (do_io && (mask & (1 << base)) != 0
12085 inst.error = _("having the base register in the register list when "
12086 "using write back is UNPREDICTABLE");
12090 if (mask & (1 << 15))
12092 if (mask & (1 << 14))
12093 inst.error = _("LR and PC should not both be in register list");
12095 set_pred_insn_type_last ();
12100 if (mask & (1 << 15))
12101 inst.error = _("PC not allowed in register list");
12104 if (do_io && ((mask & (mask - 1)) == 0))
12106 /* Single register transfers implemented as str/ldr. */
12109 if (inst.instruction & (1 << 23))
12110 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12112 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12116 if (inst.instruction & (1 << 23))
12117 inst.instruction = 0x00800000; /* ia -> [base] */
12119 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12122 inst.instruction |= 0xf8400000;
12124 inst.instruction |= 0x00100000;
12126 mask = ffs (mask) - 1;
12129 else if (writeback)
12130 inst.instruction |= WRITE_BACK;
12132 inst.instruction |= mask;
12134 inst.instruction |= base << 16;
12140 /* This really doesn't seem worth it. */
12141 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12142 _("expression too complex"));
12143 constraint (inst.operands[1].writeback,
12144 _("Thumb load/store multiple does not support {reglist}^"));
12146 if (unified_syntax)
12148 bfd_boolean narrow;
12152 /* See if we can use a 16-bit instruction. */
12153 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12154 && inst.size_req != 4
12155 && !(inst.operands[1].imm & ~0xff))
12157 mask = 1 << inst.operands[0].reg;
12159 if (inst.operands[0].reg <= 7)
12161 if (inst.instruction == T_MNEM_stmia
12162 ? inst.operands[0].writeback
12163 : (inst.operands[0].writeback
12164 == !(inst.operands[1].imm & mask)))
12166 if (inst.instruction == T_MNEM_stmia
12167 && (inst.operands[1].imm & mask)
12168 && (inst.operands[1].imm & (mask - 1)))
12169 as_warn (_("value stored for r%d is UNKNOWN"),
12170 inst.operands[0].reg);
12172 inst.instruction = THUMB_OP16 (inst.instruction);
12173 inst.instruction |= inst.operands[0].reg << 8;
12174 inst.instruction |= inst.operands[1].imm;
12177 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12179 /* This means 1 register in reg list one of 3 situations:
12180 1. Instruction is stmia, but without writeback.
12181 2. lmdia without writeback, but with Rn not in
12183 3. ldmia with writeback, but with Rn in reglist.
12184 Case 3 is UNPREDICTABLE behaviour, so we handle
12185 case 1 and 2 which can be converted into a 16-bit
12186 str or ldr. The SP cases are handled below. */
12187 unsigned long opcode;
12188 /* First, record an error for Case 3. */
12189 if (inst.operands[1].imm & mask
12190 && inst.operands[0].writeback)
12192 _("having the base register in the register list when "
12193 "using write back is UNPREDICTABLE");
12195 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
12197 inst.instruction = THUMB_OP16 (opcode);
12198 inst.instruction |= inst.operands[0].reg << 3;
12199 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12203 else if (inst.operands[0] .reg == REG_SP)
12205 if (inst.operands[0].writeback)
12208 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12209 ? T_MNEM_push : T_MNEM_pop);
12210 inst.instruction |= inst.operands[1].imm;
12213 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12216 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12217 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
12218 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
12226 if (inst.instruction < 0xffff)
12227 inst.instruction = THUMB_OP32 (inst.instruction);
12229 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12230 inst.operands[1].imm,
12231 inst.operands[0].writeback);
12236 constraint (inst.operands[0].reg > 7
12237 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12238 constraint (inst.instruction != T_MNEM_ldmia
12239 && inst.instruction != T_MNEM_stmia,
12240 _("Thumb-2 instruction only valid in unified syntax"));
12241 if (inst.instruction == T_MNEM_stmia)
12243 if (!inst.operands[0].writeback)
12244 as_warn (_("this instruction will write back the base register"));
12245 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12246 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12247 as_warn (_("value stored for r%d is UNKNOWN"),
12248 inst.operands[0].reg);
12252 if (!inst.operands[0].writeback
12253 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12254 as_warn (_("this instruction will write back the base register"));
12255 else if (inst.operands[0].writeback
12256 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12257 as_warn (_("this instruction will not write back the base register"));
12260 inst.instruction = THUMB_OP16 (inst.instruction);
12261 inst.instruction |= inst.operands[0].reg << 8;
12262 inst.instruction |= inst.operands[1].imm;
12269 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12270 || inst.operands[1].postind || inst.operands[1].writeback
12271 || inst.operands[1].immisreg || inst.operands[1].shifted
12272 || inst.operands[1].negative,
12275 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12277 inst.instruction |= inst.operands[0].reg << 12;
12278 inst.instruction |= inst.operands[1].reg << 16;
12279 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12285 if (!inst.operands[1].present)
12287 constraint (inst.operands[0].reg == REG_LR,
12288 _("r14 not allowed as first register "
12289 "when second register is omitted"));
12290 inst.operands[1].reg = inst.operands[0].reg + 1;
12292 constraint (inst.operands[0].reg == inst.operands[1].reg,
12295 inst.instruction |= inst.operands[0].reg << 12;
12296 inst.instruction |= inst.operands[1].reg << 8;
12297 inst.instruction |= inst.operands[2].reg << 16;
12303 unsigned long opcode;
12306 if (inst.operands[0].isreg
12307 && !inst.operands[0].preind
12308 && inst.operands[0].reg == REG_PC)
12309 set_pred_insn_type_last ();
12311 opcode = inst.instruction;
12312 if (unified_syntax)
12314 if (!inst.operands[1].isreg)
12316 if (opcode <= 0xffff)
12317 inst.instruction = THUMB_OP32 (opcode);
12318 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12321 if (inst.operands[1].isreg
12322 && !inst.operands[1].writeback
12323 && !inst.operands[1].shifted && !inst.operands[1].postind
12324 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12325 && opcode <= 0xffff
12326 && inst.size_req != 4)
12328 /* Insn may have a 16-bit form. */
12329 Rn = inst.operands[1].reg;
12330 if (inst.operands[1].immisreg)
12332 inst.instruction = THUMB_OP16 (opcode);
12334 if (Rn <= 7 && inst.operands[1].imm <= 7)
12336 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12337 reject_bad_reg (inst.operands[1].imm);
12339 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12340 && opcode != T_MNEM_ldrsb)
12341 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12342 || (Rn == REG_SP && opcode == T_MNEM_str))
12349 if (inst.relocs[0].pc_rel)
12350 opcode = T_MNEM_ldr_pc2;
12352 opcode = T_MNEM_ldr_pc;
12356 if (opcode == T_MNEM_ldr)
12357 opcode = T_MNEM_ldr_sp;
12359 opcode = T_MNEM_str_sp;
12361 inst.instruction = inst.operands[0].reg << 8;
12365 inst.instruction = inst.operands[0].reg;
12366 inst.instruction |= inst.operands[1].reg << 3;
12368 inst.instruction |= THUMB_OP16 (opcode);
12369 if (inst.size_req == 2)
12370 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12372 inst.relax = opcode;
12376 /* Definitely a 32-bit variant. */
12378 /* Warning for Erratum 752419. */
12379 if (opcode == T_MNEM_ldr
12380 && inst.operands[0].reg == REG_SP
12381 && inst.operands[1].writeback == 1
12382 && !inst.operands[1].immisreg)
12384 if (no_cpu_selected ()
12385 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
12386 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12387 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
12388 as_warn (_("This instruction may be unpredictable "
12389 "if executed on M-profile cores "
12390 "with interrupts enabled."));
12393 /* Do some validations regarding addressing modes. */
12394 if (inst.operands[1].immisreg)
12395 reject_bad_reg (inst.operands[1].imm);
12397 constraint (inst.operands[1].writeback == 1
12398 && inst.operands[0].reg == inst.operands[1].reg,
12401 inst.instruction = THUMB_OP32 (opcode);
12402 inst.instruction |= inst.operands[0].reg << 12;
12403 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
12404 check_ldr_r15_aligned ();
12408 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12410 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12412 /* Only [Rn,Rm] is acceptable. */
12413 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12414 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12415 || inst.operands[1].postind || inst.operands[1].shifted
12416 || inst.operands[1].negative,
12417 _("Thumb does not support this addressing mode"));
12418 inst.instruction = THUMB_OP16 (inst.instruction);
12422 inst.instruction = THUMB_OP16 (inst.instruction);
12423 if (!inst.operands[1].isreg)
12424 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12427 constraint (!inst.operands[1].preind
12428 || inst.operands[1].shifted
12429 || inst.operands[1].writeback,
12430 _("Thumb does not support this addressing mode"));
12431 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12433 constraint (inst.instruction & 0x0600,
12434 _("byte or halfword not valid for base register"));
12435 constraint (inst.operands[1].reg == REG_PC
12436 && !(inst.instruction & THUMB_LOAD_BIT),
12437 _("r15 based store not allowed"));
12438 constraint (inst.operands[1].immisreg,
12439 _("invalid base register for register offset"));
12441 if (inst.operands[1].reg == REG_PC)
12442 inst.instruction = T_OPCODE_LDR_PC;
12443 else if (inst.instruction & THUMB_LOAD_BIT)
12444 inst.instruction = T_OPCODE_LDR_SP;
12446 inst.instruction = T_OPCODE_STR_SP;
12448 inst.instruction |= inst.operands[0].reg << 8;
12449 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12453 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12454 if (!inst.operands[1].immisreg)
12456 /* Immediate offset. */
12457 inst.instruction |= inst.operands[0].reg;
12458 inst.instruction |= inst.operands[1].reg << 3;
12459 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12463 /* Register offset. */
12464 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12465 constraint (inst.operands[1].negative,
12466 _("Thumb does not support this addressing mode"));
12469 switch (inst.instruction)
12471 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12472 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12473 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12474 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12475 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12476 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12477 case 0x5600 /* ldrsb */:
12478 case 0x5e00 /* ldrsh */: break;
12482 inst.instruction |= inst.operands[0].reg;
12483 inst.instruction |= inst.operands[1].reg << 3;
12484 inst.instruction |= inst.operands[1].imm << 6;
12490 if (!inst.operands[1].present)
12492 inst.operands[1].reg = inst.operands[0].reg + 1;
12493 constraint (inst.operands[0].reg == REG_LR,
12494 _("r14 not allowed here"));
12495 constraint (inst.operands[0].reg == REG_R12,
12496 _("r12 not allowed here"));
12499 if (inst.operands[2].writeback
12500 && (inst.operands[0].reg == inst.operands[2].reg
12501 || inst.operands[1].reg == inst.operands[2].reg))
12502 as_warn (_("base register written back, and overlaps "
12503 "one of transfer registers"));
12505 inst.instruction |= inst.operands[0].reg << 12;
12506 inst.instruction |= inst.operands[1].reg << 8;
12507 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
12513 inst.instruction |= inst.operands[0].reg << 12;
12514 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12520 unsigned Rd, Rn, Rm, Ra;
12522 Rd = inst.operands[0].reg;
12523 Rn = inst.operands[1].reg;
12524 Rm = inst.operands[2].reg;
12525 Ra = inst.operands[3].reg;
12527 reject_bad_reg (Rd);
12528 reject_bad_reg (Rn);
12529 reject_bad_reg (Rm);
12530 reject_bad_reg (Ra);
12532 inst.instruction |= Rd << 8;
12533 inst.instruction |= Rn << 16;
12534 inst.instruction |= Rm;
12535 inst.instruction |= Ra << 12;
12541 unsigned RdLo, RdHi, Rn, Rm;
12543 RdLo = inst.operands[0].reg;
12544 RdHi = inst.operands[1].reg;
12545 Rn = inst.operands[2].reg;
12546 Rm = inst.operands[3].reg;
12548 reject_bad_reg (RdLo);
12549 reject_bad_reg (RdHi);
12550 reject_bad_reg (Rn);
12551 reject_bad_reg (Rm);
12553 inst.instruction |= RdLo << 12;
12554 inst.instruction |= RdHi << 8;
12555 inst.instruction |= Rn << 16;
12556 inst.instruction |= Rm;
12560 do_t_mov_cmp (void)
12564 Rn = inst.operands[0].reg;
12565 Rm = inst.operands[1].reg;
12568 set_pred_insn_type_last ();
12570 if (unified_syntax)
12572 int r0off = (inst.instruction == T_MNEM_mov
12573 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12574 unsigned long opcode;
12575 bfd_boolean narrow;
12576 bfd_boolean low_regs;
12578 low_regs = (Rn <= 7 && Rm <= 7);
12579 opcode = inst.instruction;
12580 if (in_pred_block ())
12581 narrow = opcode != T_MNEM_movs;
12583 narrow = opcode != T_MNEM_movs || low_regs;
12584 if (inst.size_req == 4
12585 || inst.operands[1].shifted)
12588 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12589 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12590 && !inst.operands[1].shifted
12594 inst.instruction = T2_SUBS_PC_LR;
12598 if (opcode == T_MNEM_cmp)
12600 constraint (Rn == REG_PC, BAD_PC);
12603 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12605 warn_deprecated_sp (Rm);
12606 /* R15 was documented as a valid choice for Rm in ARMv6,
12607 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12608 tools reject R15, so we do too. */
12609 constraint (Rm == REG_PC, BAD_PC);
12612 reject_bad_reg (Rm);
12614 else if (opcode == T_MNEM_mov
12615 || opcode == T_MNEM_movs)
12617 if (inst.operands[1].isreg)
12619 if (opcode == T_MNEM_movs)
12621 reject_bad_reg (Rn);
12622 reject_bad_reg (Rm);
12626 /* This is mov.n. */
12627 if ((Rn == REG_SP || Rn == REG_PC)
12628 && (Rm == REG_SP || Rm == REG_PC))
12630 as_tsktsk (_("Use of r%u as a source register is "
12631 "deprecated when r%u is the destination "
12632 "register."), Rm, Rn);
12637 /* This is mov.w. */
12638 constraint (Rn == REG_PC, BAD_PC);
12639 constraint (Rm == REG_PC, BAD_PC);
12640 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12641 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12645 reject_bad_reg (Rn);
12648 if (!inst.operands[1].isreg)
12650 /* Immediate operand. */
12651 if (!in_pred_block () && opcode == T_MNEM_mov)
12653 if (low_regs && narrow)
12655 inst.instruction = THUMB_OP16 (opcode);
12656 inst.instruction |= Rn << 8;
12657 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12658 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12660 if (inst.size_req == 2)
12661 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12663 inst.relax = opcode;
12668 constraint ((inst.relocs[0].type
12669 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12670 && (inst.relocs[0].type
12671 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
12672 THUMB1_RELOC_ONLY);
12674 inst.instruction = THUMB_OP32 (inst.instruction);
12675 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12676 inst.instruction |= Rn << r0off;
12677 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12680 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12681 && (inst.instruction == T_MNEM_mov
12682 || inst.instruction == T_MNEM_movs))
12684 /* Register shifts are encoded as separate shift instructions. */
12685 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12687 if (in_pred_block ())
12692 if (inst.size_req == 4)
12695 if (!low_regs || inst.operands[1].imm > 7)
12701 switch (inst.operands[1].shift_kind)
12704 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12707 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12710 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12713 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12719 inst.instruction = opcode;
12722 inst.instruction |= Rn;
12723 inst.instruction |= inst.operands[1].imm << 3;
12728 inst.instruction |= CONDS_BIT;
12730 inst.instruction |= Rn << 8;
12731 inst.instruction |= Rm << 16;
12732 inst.instruction |= inst.operands[1].imm;
12737 /* Some mov with immediate shift have narrow variants.
12738 Register shifts are handled above. */
12739 if (low_regs && inst.operands[1].shifted
12740 && (inst.instruction == T_MNEM_mov
12741 || inst.instruction == T_MNEM_movs))
12743 if (in_pred_block ())
12744 narrow = (inst.instruction == T_MNEM_mov);
12746 narrow = (inst.instruction == T_MNEM_movs);
12751 switch (inst.operands[1].shift_kind)
12753 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12754 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12755 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12756 default: narrow = FALSE; break;
12762 inst.instruction |= Rn;
12763 inst.instruction |= Rm << 3;
12764 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
12768 inst.instruction = THUMB_OP32 (inst.instruction);
12769 inst.instruction |= Rn << r0off;
12770 encode_thumb32_shifted_operand (1);
12774 switch (inst.instruction)
12777 /* In v4t or v5t a move of two lowregs produces unpredictable
12778 results. Don't allow this. */
12781 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
12782 "MOV Rd, Rs with two low registers is not "
12783 "permitted on this architecture");
12784 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
12788 inst.instruction = T_OPCODE_MOV_HR;
12789 inst.instruction |= (Rn & 0x8) << 4;
12790 inst.instruction |= (Rn & 0x7);
12791 inst.instruction |= Rm << 3;
12795 /* We know we have low registers at this point.
12796 Generate LSLS Rd, Rs, #0. */
12797 inst.instruction = T_OPCODE_LSL_I;
12798 inst.instruction |= Rn;
12799 inst.instruction |= Rm << 3;
12805 inst.instruction = T_OPCODE_CMP_LR;
12806 inst.instruction |= Rn;
12807 inst.instruction |= Rm << 3;
12811 inst.instruction = T_OPCODE_CMP_HR;
12812 inst.instruction |= (Rn & 0x8) << 4;
12813 inst.instruction |= (Rn & 0x7);
12814 inst.instruction |= Rm << 3;
12821 inst.instruction = THUMB_OP16 (inst.instruction);
12823 /* PR 10443: Do not silently ignore shifted operands. */
12824 constraint (inst.operands[1].shifted,
12825 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12827 if (inst.operands[1].isreg)
12829 if (Rn < 8 && Rm < 8)
12831 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12832 since a MOV instruction produces unpredictable results. */
12833 if (inst.instruction == T_OPCODE_MOV_I8)
12834 inst.instruction = T_OPCODE_ADD_I3;
12836 inst.instruction = T_OPCODE_CMP_LR;
12838 inst.instruction |= Rn;
12839 inst.instruction |= Rm << 3;
12843 if (inst.instruction == T_OPCODE_MOV_I8)
12844 inst.instruction = T_OPCODE_MOV_HR;
12846 inst.instruction = T_OPCODE_CMP_HR;
12852 constraint (Rn > 7,
12853 _("only lo regs allowed with immediate"));
12854 inst.instruction |= Rn << 8;
12855 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12866 top = (inst.instruction & 0x00800000) != 0;
12867 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
12869 constraint (top, _(":lower16: not allowed in this instruction"));
12870 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
12872 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
12874 constraint (!top, _(":upper16: not allowed in this instruction"));
12875 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
12878 Rd = inst.operands[0].reg;
12879 reject_bad_reg (Rd);
12881 inst.instruction |= Rd << 8;
12882 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
12884 imm = inst.relocs[0].exp.X_add_number;
12885 inst.instruction |= (imm & 0xf000) << 4;
12886 inst.instruction |= (imm & 0x0800) << 15;
12887 inst.instruction |= (imm & 0x0700) << 4;
12888 inst.instruction |= (imm & 0x00ff);
12893 do_t_mvn_tst (void)
12897 Rn = inst.operands[0].reg;
12898 Rm = inst.operands[1].reg;
12900 if (inst.instruction == T_MNEM_cmp
12901 || inst.instruction == T_MNEM_cmn)
12902 constraint (Rn == REG_PC, BAD_PC);
12904 reject_bad_reg (Rn);
12905 reject_bad_reg (Rm);
12907 if (unified_syntax)
12909 int r0off = (inst.instruction == T_MNEM_mvn
12910 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12911 bfd_boolean narrow;
12913 if (inst.size_req == 4
12914 || inst.instruction > 0xffff
12915 || inst.operands[1].shifted
12916 || Rn > 7 || Rm > 7)
12918 else if (inst.instruction == T_MNEM_cmn
12919 || inst.instruction == T_MNEM_tst)
12921 else if (THUMB_SETS_FLAGS (inst.instruction))
12922 narrow = !in_pred_block ();
12924 narrow = in_pred_block ();
12926 if (!inst.operands[1].isreg)
12928 /* For an immediate, we always generate a 32-bit opcode;
12929 section relaxation will shrink it later if possible. */
12930 if (inst.instruction < 0xffff)
12931 inst.instruction = THUMB_OP32 (inst.instruction);
12932 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12933 inst.instruction |= Rn << r0off;
12934 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12938 /* See if we can do this with a 16-bit instruction. */
12941 inst.instruction = THUMB_OP16 (inst.instruction);
12942 inst.instruction |= Rn;
12943 inst.instruction |= Rm << 3;
12947 constraint (inst.operands[1].shifted
12948 && inst.operands[1].immisreg,
12949 _("shift must be constant"));
12950 if (inst.instruction < 0xffff)
12951 inst.instruction = THUMB_OP32 (inst.instruction);
12952 inst.instruction |= Rn << r0off;
12953 encode_thumb32_shifted_operand (1);
12959 constraint (inst.instruction > 0xffff
12960 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12961 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12962 _("unshifted register required"));
12963 constraint (Rn > 7 || Rm > 7,
12966 inst.instruction = THUMB_OP16 (inst.instruction);
12967 inst.instruction |= Rn;
12968 inst.instruction |= Rm << 3;
12977 if (do_vfp_nsyn_mrs () == SUCCESS)
12980 Rd = inst.operands[0].reg;
12981 reject_bad_reg (Rd);
12982 inst.instruction |= Rd << 8;
12984 if (inst.operands[1].isreg)
12986 unsigned br = inst.operands[1].reg;
12987 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12988 as_bad (_("bad register for mrs"));
12990 inst.instruction |= br & (0xf << 16);
12991 inst.instruction |= (br & 0x300) >> 4;
12992 inst.instruction |= (br & SPSR_BIT) >> 2;
12996 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12998 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13000 /* PR gas/12698: The constraint is only applied for m_profile.
13001 If the user has specified -march=all, we want to ignore it as
13002 we are building for any CPU type, including non-m variants. */
13003 bfd_boolean m_profile =
13004 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13005 constraint ((flags != 0) && m_profile, _("selected processor does "
13006 "not support requested special purpose register"));
13009 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13011 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13012 _("'APSR', 'CPSR' or 'SPSR' expected"));
13014 inst.instruction |= (flags & SPSR_BIT) >> 2;
13015 inst.instruction |= inst.operands[1].imm & 0xff;
13016 inst.instruction |= 0xf0000;
13026 if (do_vfp_nsyn_msr () == SUCCESS)
13029 constraint (!inst.operands[1].isreg,
13030 _("Thumb encoding does not support an immediate here"));
13032 if (inst.operands[0].isreg)
13033 flags = (int)(inst.operands[0].reg);
13035 flags = inst.operands[0].imm;
13037 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13039 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13041 /* PR gas/12698: The constraint is only applied for m_profile.
13042 If the user has specified -march=all, we want to ignore it as
13043 we are building for any CPU type, including non-m variants. */
13044 bfd_boolean m_profile =
13045 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13046 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13047 && (bits & ~(PSR_s | PSR_f)) != 0)
13048 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13049 && bits != PSR_f)) && m_profile,
13050 _("selected processor does not support requested special "
13051 "purpose register"));
13054 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13055 "requested special purpose register"));
13057 Rn = inst.operands[1].reg;
13058 reject_bad_reg (Rn);
13060 inst.instruction |= (flags & SPSR_BIT) >> 2;
13061 inst.instruction |= (flags & 0xf0000) >> 8;
13062 inst.instruction |= (flags & 0x300) >> 4;
13063 inst.instruction |= (flags & 0xff);
13064 inst.instruction |= Rn << 16;
13070 bfd_boolean narrow;
13071 unsigned Rd, Rn, Rm;
13073 if (!inst.operands[2].present)
13074 inst.operands[2].reg = inst.operands[0].reg;
13076 Rd = inst.operands[0].reg;
13077 Rn = inst.operands[1].reg;
13078 Rm = inst.operands[2].reg;
13080 if (unified_syntax)
13082 if (inst.size_req == 4
13088 else if (inst.instruction == T_MNEM_muls)
13089 narrow = !in_pred_block ();
13091 narrow = in_pred_block ();
13095 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13096 constraint (Rn > 7 || Rm > 7,
13103 /* 16-bit MULS/Conditional MUL. */
13104 inst.instruction = THUMB_OP16 (inst.instruction);
13105 inst.instruction |= Rd;
13108 inst.instruction |= Rm << 3;
13110 inst.instruction |= Rn << 3;
13112 constraint (1, _("dest must overlap one source register"));
13116 constraint (inst.instruction != T_MNEM_mul,
13117 _("Thumb-2 MUL must not set flags"));
13119 inst.instruction = THUMB_OP32 (inst.instruction);
13120 inst.instruction |= Rd << 8;
13121 inst.instruction |= Rn << 16;
13122 inst.instruction |= Rm << 0;
13124 reject_bad_reg (Rd);
13125 reject_bad_reg (Rn);
13126 reject_bad_reg (Rm);
13133 unsigned RdLo, RdHi, Rn, Rm;
13135 RdLo = inst.operands[0].reg;
13136 RdHi = inst.operands[1].reg;
13137 Rn = inst.operands[2].reg;
13138 Rm = inst.operands[3].reg;
13140 reject_bad_reg (RdLo);
13141 reject_bad_reg (RdHi);
13142 reject_bad_reg (Rn);
13143 reject_bad_reg (Rm);
13145 inst.instruction |= RdLo << 12;
13146 inst.instruction |= RdHi << 8;
13147 inst.instruction |= Rn << 16;
13148 inst.instruction |= Rm;
13151 as_tsktsk (_("rdhi and rdlo must be different"));
13157 set_pred_insn_type (NEUTRAL_IT_INSN);
13159 if (unified_syntax)
13161 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13163 inst.instruction = THUMB_OP32 (inst.instruction);
13164 inst.instruction |= inst.operands[0].imm;
13168 /* PR9722: Check for Thumb2 availability before
13169 generating a thumb2 nop instruction. */
13170 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
13172 inst.instruction = THUMB_OP16 (inst.instruction);
13173 inst.instruction |= inst.operands[0].imm << 4;
13176 inst.instruction = 0x46c0;
13181 constraint (inst.operands[0].present,
13182 _("Thumb does not support NOP with hints"));
13183 inst.instruction = 0x46c0;
13190 if (unified_syntax)
13192 bfd_boolean narrow;
13194 if (THUMB_SETS_FLAGS (inst.instruction))
13195 narrow = !in_pred_block ();
13197 narrow = in_pred_block ();
13198 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13200 if (inst.size_req == 4)
13205 inst.instruction = THUMB_OP32 (inst.instruction);
13206 inst.instruction |= inst.operands[0].reg << 8;
13207 inst.instruction |= inst.operands[1].reg << 16;
13211 inst.instruction = THUMB_OP16 (inst.instruction);
13212 inst.instruction |= inst.operands[0].reg;
13213 inst.instruction |= inst.operands[1].reg << 3;
13218 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13220 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13222 inst.instruction = THUMB_OP16 (inst.instruction);
13223 inst.instruction |= inst.operands[0].reg;
13224 inst.instruction |= inst.operands[1].reg << 3;
13233 Rd = inst.operands[0].reg;
13234 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13236 reject_bad_reg (Rd);
13237 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13238 reject_bad_reg (Rn);
13240 inst.instruction |= Rd << 8;
13241 inst.instruction |= Rn << 16;
13243 if (!inst.operands[2].isreg)
13245 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13246 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13252 Rm = inst.operands[2].reg;
13253 reject_bad_reg (Rm);
13255 constraint (inst.operands[2].shifted
13256 && inst.operands[2].immisreg,
13257 _("shift must be constant"));
13258 encode_thumb32_shifted_operand (2);
13265 unsigned Rd, Rn, Rm;
13267 Rd = inst.operands[0].reg;
13268 Rn = inst.operands[1].reg;
13269 Rm = inst.operands[2].reg;
13271 reject_bad_reg (Rd);
13272 reject_bad_reg (Rn);
13273 reject_bad_reg (Rm);
13275 inst.instruction |= Rd << 8;
13276 inst.instruction |= Rn << 16;
13277 inst.instruction |= Rm;
13278 if (inst.operands[3].present)
13280 unsigned int val = inst.relocs[0].exp.X_add_number;
13281 constraint (inst.relocs[0].exp.X_op != O_constant,
13282 _("expression too complex"));
13283 inst.instruction |= (val & 0x1c) << 10;
13284 inst.instruction |= (val & 0x03) << 6;
13291 if (!inst.operands[3].present)
13295 inst.instruction &= ~0x00000020;
13297 /* PR 10168. Swap the Rm and Rn registers. */
13298 Rtmp = inst.operands[1].reg;
13299 inst.operands[1].reg = inst.operands[2].reg;
13300 inst.operands[2].reg = Rtmp;
13308 if (inst.operands[0].immisreg)
13309 reject_bad_reg (inst.operands[0].imm);
13311 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13315 do_t_push_pop (void)
13319 constraint (inst.operands[0].writeback,
13320 _("push/pop do not support {reglist}^"));
13321 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13322 _("expression too complex"));
13324 mask = inst.operands[0].imm;
13325 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13326 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13327 else if (inst.size_req != 4
13328 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13329 ? REG_LR : REG_PC)))
13331 inst.instruction = THUMB_OP16 (inst.instruction);
13332 inst.instruction |= THUMB_PP_PC_LR;
13333 inst.instruction |= mask & 0xff;
13335 else if (unified_syntax)
13337 inst.instruction = THUMB_OP32 (inst.instruction);
13338 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13342 inst.error = _("invalid register list to push/pop instruction");
13350 if (unified_syntax)
13351 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
13354 inst.error = _("invalid register list to push/pop instruction");
13360 do_t_vscclrm (void)
13362 if (inst.operands[0].issingle)
13364 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13365 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13366 inst.instruction |= inst.operands[0].imm;
13370 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13371 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13372 inst.instruction |= 1 << 8;
13373 inst.instruction |= inst.operands[0].imm << 1;
13382 Rd = inst.operands[0].reg;
13383 Rm = inst.operands[1].reg;
13385 reject_bad_reg (Rd);
13386 reject_bad_reg (Rm);
13388 inst.instruction |= Rd << 8;
13389 inst.instruction |= Rm << 16;
13390 inst.instruction |= Rm;
13398 Rd = inst.operands[0].reg;
13399 Rm = inst.operands[1].reg;
13401 reject_bad_reg (Rd);
13402 reject_bad_reg (Rm);
13404 if (Rd <= 7 && Rm <= 7
13405 && inst.size_req != 4)
13407 inst.instruction = THUMB_OP16 (inst.instruction);
13408 inst.instruction |= Rd;
13409 inst.instruction |= Rm << 3;
13411 else if (unified_syntax)
13413 inst.instruction = THUMB_OP32 (inst.instruction);
13414 inst.instruction |= Rd << 8;
13415 inst.instruction |= Rm << 16;
13416 inst.instruction |= Rm;
13419 inst.error = BAD_HIREG;
13427 Rd = inst.operands[0].reg;
13428 Rm = inst.operands[1].reg;
13430 reject_bad_reg (Rd);
13431 reject_bad_reg (Rm);
13433 inst.instruction |= Rd << 8;
13434 inst.instruction |= Rm;
13442 Rd = inst.operands[0].reg;
13443 Rs = (inst.operands[1].present
13444 ? inst.operands[1].reg /* Rd, Rs, foo */
13445 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13447 reject_bad_reg (Rd);
13448 reject_bad_reg (Rs);
13449 if (inst.operands[2].isreg)
13450 reject_bad_reg (inst.operands[2].reg);
13452 inst.instruction |= Rd << 8;
13453 inst.instruction |= Rs << 16;
13454 if (!inst.operands[2].isreg)
13456 bfd_boolean narrow;
13458 if ((inst.instruction & 0x00100000) != 0)
13459 narrow = !in_pred_block ();
13461 narrow = in_pred_block ();
13463 if (Rd > 7 || Rs > 7)
13466 if (inst.size_req == 4 || !unified_syntax)
13469 if (inst.relocs[0].exp.X_op != O_constant
13470 || inst.relocs[0].exp.X_add_number != 0)
13473 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13474 relaxation, but it doesn't seem worth the hassle. */
13477 inst.relocs[0].type = BFD_RELOC_UNUSED;
13478 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13479 inst.instruction |= Rs << 3;
13480 inst.instruction |= Rd;
13484 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13485 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13489 encode_thumb32_shifted_operand (2);
13495 if (warn_on_deprecated
13496 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13497 as_tsktsk (_("setend use is deprecated for ARMv8"));
13499 set_pred_insn_type (OUTSIDE_PRED_INSN);
13500 if (inst.operands[0].imm)
13501 inst.instruction |= 0x8;
13507 if (!inst.operands[1].present)
13508 inst.operands[1].reg = inst.operands[0].reg;
13510 if (unified_syntax)
13512 bfd_boolean narrow;
13515 switch (inst.instruction)
13518 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13520 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13522 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13524 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13528 if (THUMB_SETS_FLAGS (inst.instruction))
13529 narrow = !in_pred_block ();
13531 narrow = in_pred_block ();
13532 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13534 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13536 if (inst.operands[2].isreg
13537 && (inst.operands[1].reg != inst.operands[0].reg
13538 || inst.operands[2].reg > 7))
13540 if (inst.size_req == 4)
13543 reject_bad_reg (inst.operands[0].reg);
13544 reject_bad_reg (inst.operands[1].reg);
13548 if (inst.operands[2].isreg)
13550 reject_bad_reg (inst.operands[2].reg);
13551 inst.instruction = THUMB_OP32 (inst.instruction);
13552 inst.instruction |= inst.operands[0].reg << 8;
13553 inst.instruction |= inst.operands[1].reg << 16;
13554 inst.instruction |= inst.operands[2].reg;
13556 /* PR 12854: Error on extraneous shifts. */
13557 constraint (inst.operands[2].shifted,
13558 _("extraneous shift as part of operand to shift insn"));
13562 inst.operands[1].shifted = 1;
13563 inst.operands[1].shift_kind = shift_kind;
13564 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13565 ? T_MNEM_movs : T_MNEM_mov);
13566 inst.instruction |= inst.operands[0].reg << 8;
13567 encode_thumb32_shifted_operand (1);
13568 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13569 inst.relocs[0].type = BFD_RELOC_UNUSED;
13574 if (inst.operands[2].isreg)
13576 switch (shift_kind)
13578 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13579 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13580 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13581 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13585 inst.instruction |= inst.operands[0].reg;
13586 inst.instruction |= inst.operands[2].reg << 3;
13588 /* PR 12854: Error on extraneous shifts. */
13589 constraint (inst.operands[2].shifted,
13590 _("extraneous shift as part of operand to shift insn"));
13594 switch (shift_kind)
13596 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13597 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13598 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13601 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13602 inst.instruction |= inst.operands[0].reg;
13603 inst.instruction |= inst.operands[1].reg << 3;
13609 constraint (inst.operands[0].reg > 7
13610 || inst.operands[1].reg > 7, BAD_HIREG);
13611 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13613 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13615 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13616 constraint (inst.operands[0].reg != inst.operands[1].reg,
13617 _("source1 and dest must be same register"));
13619 switch (inst.instruction)
13621 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13622 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13623 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13624 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13628 inst.instruction |= inst.operands[0].reg;
13629 inst.instruction |= inst.operands[2].reg << 3;
13631 /* PR 12854: Error on extraneous shifts. */
13632 constraint (inst.operands[2].shifted,
13633 _("extraneous shift as part of operand to shift insn"));
13637 switch (inst.instruction)
13639 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13640 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13641 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13642 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13645 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13646 inst.instruction |= inst.operands[0].reg;
13647 inst.instruction |= inst.operands[1].reg << 3;
13655 unsigned Rd, Rn, Rm;
13657 Rd = inst.operands[0].reg;
13658 Rn = inst.operands[1].reg;
13659 Rm = inst.operands[2].reg;
13661 reject_bad_reg (Rd);
13662 reject_bad_reg (Rn);
13663 reject_bad_reg (Rm);
13665 inst.instruction |= Rd << 8;
13666 inst.instruction |= Rn << 16;
13667 inst.instruction |= Rm;
13673 unsigned Rd, Rn, Rm;
13675 Rd = inst.operands[0].reg;
13676 Rm = inst.operands[1].reg;
13677 Rn = inst.operands[2].reg;
13679 reject_bad_reg (Rd);
13680 reject_bad_reg (Rn);
13681 reject_bad_reg (Rm);
13683 inst.instruction |= Rd << 8;
13684 inst.instruction |= Rn << 16;
13685 inst.instruction |= Rm;
13691 unsigned int value = inst.relocs[0].exp.X_add_number;
13692 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13693 _("SMC is not permitted on this architecture"));
13694 constraint (inst.relocs[0].exp.X_op != O_constant,
13695 _("expression too complex"));
13696 inst.relocs[0].type = BFD_RELOC_UNUSED;
13697 inst.instruction |= (value & 0xf000) >> 12;
13698 inst.instruction |= (value & 0x0ff0);
13699 inst.instruction |= (value & 0x000f) << 16;
13700 /* PR gas/15623: SMC instructions must be last in an IT block. */
13701 set_pred_insn_type_last ();
13707 unsigned int value = inst.relocs[0].exp.X_add_number;
13709 inst.relocs[0].type = BFD_RELOC_UNUSED;
13710 inst.instruction |= (value & 0x0fff);
13711 inst.instruction |= (value & 0xf000) << 4;
13715 do_t_ssat_usat (int bias)
13719 Rd = inst.operands[0].reg;
13720 Rn = inst.operands[2].reg;
13722 reject_bad_reg (Rd);
13723 reject_bad_reg (Rn);
13725 inst.instruction |= Rd << 8;
13726 inst.instruction |= inst.operands[1].imm - bias;
13727 inst.instruction |= Rn << 16;
13729 if (inst.operands[3].present)
13731 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
13733 inst.relocs[0].type = BFD_RELOC_UNUSED;
13735 constraint (inst.relocs[0].exp.X_op != O_constant,
13736 _("expression too complex"));
13738 if (shift_amount != 0)
13740 constraint (shift_amount > 31,
13741 _("shift expression is too large"));
13743 if (inst.operands[3].shift_kind == SHIFT_ASR)
13744 inst.instruction |= 0x00200000; /* sh bit. */
13746 inst.instruction |= (shift_amount & 0x1c) << 10;
13747 inst.instruction |= (shift_amount & 0x03) << 6;
13755 do_t_ssat_usat (1);
13763 Rd = inst.operands[0].reg;
13764 Rn = inst.operands[2].reg;
13766 reject_bad_reg (Rd);
13767 reject_bad_reg (Rn);
13769 inst.instruction |= Rd << 8;
13770 inst.instruction |= inst.operands[1].imm - 1;
13771 inst.instruction |= Rn << 16;
13777 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
13778 || inst.operands[2].postind || inst.operands[2].writeback
13779 || inst.operands[2].immisreg || inst.operands[2].shifted
13780 || inst.operands[2].negative,
13783 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
13785 inst.instruction |= inst.operands[0].reg << 8;
13786 inst.instruction |= inst.operands[1].reg << 12;
13787 inst.instruction |= inst.operands[2].reg << 16;
13788 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
13794 if (!inst.operands[2].present)
13795 inst.operands[2].reg = inst.operands[1].reg + 1;
13797 constraint (inst.operands[0].reg == inst.operands[1].reg
13798 || inst.operands[0].reg == inst.operands[2].reg
13799 || inst.operands[0].reg == inst.operands[3].reg,
13802 inst.instruction |= inst.operands[0].reg;
13803 inst.instruction |= inst.operands[1].reg << 12;
13804 inst.instruction |= inst.operands[2].reg << 8;
13805 inst.instruction |= inst.operands[3].reg << 16;
13811 unsigned Rd, Rn, Rm;
13813 Rd = inst.operands[0].reg;
13814 Rn = inst.operands[1].reg;
13815 Rm = inst.operands[2].reg;
13817 reject_bad_reg (Rd);
13818 reject_bad_reg (Rn);
13819 reject_bad_reg (Rm);
13821 inst.instruction |= Rd << 8;
13822 inst.instruction |= Rn << 16;
13823 inst.instruction |= Rm;
13824 inst.instruction |= inst.operands[3].imm << 4;
13832 Rd = inst.operands[0].reg;
13833 Rm = inst.operands[1].reg;
13835 reject_bad_reg (Rd);
13836 reject_bad_reg (Rm);
13838 if (inst.instruction <= 0xffff
13839 && inst.size_req != 4
13840 && Rd <= 7 && Rm <= 7
13841 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13843 inst.instruction = THUMB_OP16 (inst.instruction);
13844 inst.instruction |= Rd;
13845 inst.instruction |= Rm << 3;
13847 else if (unified_syntax)
13849 if (inst.instruction <= 0xffff)
13850 inst.instruction = THUMB_OP32 (inst.instruction);
13851 inst.instruction |= Rd << 8;
13852 inst.instruction |= Rm;
13853 inst.instruction |= inst.operands[2].imm << 4;
13857 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13858 _("Thumb encoding does not support rotation"));
13859 constraint (1, BAD_HIREG);
13866 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
13875 half = (inst.instruction & 0x10) != 0;
13876 set_pred_insn_type_last ();
13877 constraint (inst.operands[0].immisreg,
13878 _("instruction requires register index"));
13880 Rn = inst.operands[0].reg;
13881 Rm = inst.operands[0].imm;
13883 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13884 constraint (Rn == REG_SP, BAD_SP);
13885 reject_bad_reg (Rm);
13887 constraint (!half && inst.operands[0].shifted,
13888 _("instruction does not allow shifted index"));
13889 inst.instruction |= (Rn << 16) | Rm;
13895 if (!inst.operands[0].present)
13896 inst.operands[0].imm = 0;
13898 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13900 constraint (inst.size_req == 2,
13901 _("immediate value out of range"));
13902 inst.instruction = THUMB_OP32 (inst.instruction);
13903 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13904 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13908 inst.instruction = THUMB_OP16 (inst.instruction);
13909 inst.instruction |= inst.operands[0].imm;
13912 set_pred_insn_type (NEUTRAL_IT_INSN);
13919 do_t_ssat_usat (0);
13927 Rd = inst.operands[0].reg;
13928 Rn = inst.operands[2].reg;
13930 reject_bad_reg (Rd);
13931 reject_bad_reg (Rn);
13933 inst.instruction |= Rd << 8;
13934 inst.instruction |= inst.operands[1].imm;
13935 inst.instruction |= Rn << 16;
13938 /* Checking the range of the branch offset (VAL) with NBITS bits
13939 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13941 v8_1_branch_value_check (int val, int nbits, int is_signed)
13943 gas_assert (nbits > 0 && nbits <= 32);
13946 int cmp = (1 << (nbits - 1));
13947 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
13952 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
13958 /* For branches in Armv8.1-M Mainline. */
13960 do_t_branch_future (void)
13962 unsigned long insn = inst.instruction;
13964 inst.instruction = THUMB_OP32 (inst.instruction);
13965 if (inst.operands[0].hasreloc == 0)
13967 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
13968 as_bad (BAD_BRANCH_OFF);
13970 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
13974 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
13975 inst.relocs[0].pc_rel = 1;
13981 if (inst.operands[1].hasreloc == 0)
13983 int val = inst.operands[1].imm;
13984 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
13985 as_bad (BAD_BRANCH_OFF);
13987 int immA = (val & 0x0001f000) >> 12;
13988 int immB = (val & 0x00000ffc) >> 2;
13989 int immC = (val & 0x00000002) >> 1;
13990 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
13994 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
13995 inst.relocs[1].pc_rel = 1;
14000 if (inst.operands[1].hasreloc == 0)
14002 int val = inst.operands[1].imm;
14003 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14004 as_bad (BAD_BRANCH_OFF);
14006 int immA = (val & 0x0007f000) >> 12;
14007 int immB = (val & 0x00000ffc) >> 2;
14008 int immC = (val & 0x00000002) >> 1;
14009 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14013 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14014 inst.relocs[1].pc_rel = 1;
14018 case T_MNEM_bfcsel:
14020 if (inst.operands[1].hasreloc == 0)
14022 int val = inst.operands[1].imm;
14023 int immA = (val & 0x00001000) >> 12;
14024 int immB = (val & 0x00000ffc) >> 2;
14025 int immC = (val & 0x00000002) >> 1;
14026 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14030 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14031 inst.relocs[1].pc_rel = 1;
14035 if (inst.operands[2].hasreloc == 0)
14037 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14038 int val2 = inst.operands[2].imm;
14039 int val0 = inst.operands[0].imm & 0x1f;
14040 int diff = val2 - val0;
14042 inst.instruction |= 1 << 17; /* T bit. */
14043 else if (diff != 2)
14044 as_bad (_("out of range label-relative fixup value"));
14048 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14049 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14050 inst.relocs[2].pc_rel = 1;
14054 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14055 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14060 inst.instruction |= inst.operands[1].reg << 16;
14067 /* Helper function for do_t_loloop to handle relocations. */
14069 v8_1_loop_reloc (int is_le)
14071 if (inst.relocs[0].exp.X_op == O_constant)
14073 int value = inst.relocs[0].exp.X_add_number;
14074 value = (is_le) ? -value : value;
14076 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14077 as_bad (BAD_BRANCH_OFF);
14081 immh = (value & 0x00000ffc) >> 2;
14082 imml = (value & 0x00000002) >> 1;
14084 inst.instruction |= (imml << 11) | (immh << 1);
14088 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14089 inst.relocs[0].pc_rel = 1;
14093 /* To handle the Scalar Low Overhead Loop instructions
14094 in Armv8.1-M Mainline. */
14098 unsigned long insn = inst.instruction;
14100 set_pred_insn_type (OUTSIDE_PRED_INSN);
14101 inst.instruction = THUMB_OP32 (inst.instruction);
14107 if (!inst.operands[0].present)
14108 inst.instruction |= 1 << 21;
14110 v8_1_loop_reloc (TRUE);
14114 v8_1_loop_reloc (FALSE);
14115 /* Fall through. */
14117 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
14118 inst.instruction |= (inst.operands[1].reg << 16);
14125 /* MVE instruction encoder helpers. */
14126 #define M_MNEM_vabav 0xee800f01
14127 #define M_MNEM_vmladav 0xeef00e00
14128 #define M_MNEM_vmladava 0xeef00e20
14129 #define M_MNEM_vmladavx 0xeef01e00
14130 #define M_MNEM_vmladavax 0xeef01e20
14131 #define M_MNEM_vmlsdav 0xeef00e01
14132 #define M_MNEM_vmlsdava 0xeef00e21
14133 #define M_MNEM_vmlsdavx 0xeef01e01
14134 #define M_MNEM_vmlsdavax 0xeef01e21
14135 #define M_MNEM_vmullt 0xee011e00
14136 #define M_MNEM_vmullb 0xee010e00
14137 #define M_MNEM_vst20 0xfc801e00
14138 #define M_MNEM_vst21 0xfc801e20
14139 #define M_MNEM_vst40 0xfc801e01
14140 #define M_MNEM_vst41 0xfc801e21
14141 #define M_MNEM_vst42 0xfc801e41
14142 #define M_MNEM_vst43 0xfc801e61
14143 #define M_MNEM_vld20 0xfc901e00
14144 #define M_MNEM_vld21 0xfc901e20
14145 #define M_MNEM_vld40 0xfc901e01
14146 #define M_MNEM_vld41 0xfc901e21
14147 #define M_MNEM_vld42 0xfc901e41
14148 #define M_MNEM_vld43 0xfc901e61
14149 #define M_MNEM_vstrb 0xec000e00
14150 #define M_MNEM_vstrh 0xec000e10
14151 #define M_MNEM_vstrw 0xec000e40
14152 #define M_MNEM_vstrd 0xec000e50
14153 #define M_MNEM_vldrb 0xec100e00
14154 #define M_MNEM_vldrh 0xec100e10
14155 #define M_MNEM_vldrw 0xec100e40
14156 #define M_MNEM_vldrd 0xec100e50
14157 #define M_MNEM_vmovlt 0xeea01f40
14158 #define M_MNEM_vmovlb 0xeea00f40
14159 #define M_MNEM_vmovnt 0xfe311e81
14160 #define M_MNEM_vmovnb 0xfe310e81
14161 #define M_MNEM_vadc 0xee300f00
14162 #define M_MNEM_vadci 0xee301f00
14163 #define M_MNEM_vbrsr 0xfe011e60
14164 #define M_MNEM_vaddlv 0xee890f00
14165 #define M_MNEM_vaddlva 0xee890f20
14166 #define M_MNEM_vaddv 0xeef10f00
14167 #define M_MNEM_vaddva 0xeef10f20
14168 #define M_MNEM_vddup 0xee011f6e
14169 #define M_MNEM_vdwdup 0xee011f60
14170 #define M_MNEM_vidup 0xee010f6e
14171 #define M_MNEM_viwdup 0xee010f60
14172 #define M_MNEM_vmaxv 0xeee20f00
14173 #define M_MNEM_vmaxav 0xeee00f00
14174 #define M_MNEM_vminv 0xeee20f80
14175 #define M_MNEM_vminav 0xeee00f80
14176 #define M_MNEM_vmlaldav 0xee800e00
14177 #define M_MNEM_vmlaldava 0xee800e20
14178 #define M_MNEM_vmlaldavx 0xee801e00
14179 #define M_MNEM_vmlaldavax 0xee801e20
14180 #define M_MNEM_vmlsldav 0xee800e01
14181 #define M_MNEM_vmlsldava 0xee800e21
14182 #define M_MNEM_vmlsldavx 0xee801e01
14183 #define M_MNEM_vmlsldavax 0xee801e21
14184 #define M_MNEM_vrmlaldavhx 0xee801f00
14185 #define M_MNEM_vrmlaldavhax 0xee801f20
14186 #define M_MNEM_vrmlsldavh 0xfe800e01
14187 #define M_MNEM_vrmlsldavha 0xfe800e21
14188 #define M_MNEM_vrmlsldavhx 0xfe801e01
14189 #define M_MNEM_vrmlsldavhax 0xfe801e21
14191 /* Neon instruction encoder helpers. */
14193 /* Encodings for the different types for various Neon opcodes. */
14195 /* An "invalid" code for the following tables. */
14198 struct neon_tab_entry
14201 unsigned float_or_poly;
14202 unsigned scalar_or_imm;
14205 /* Map overloaded Neon opcodes to their respective encodings. */
14206 #define NEON_ENC_TAB \
14207 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14208 X(vabdl, 0x0800700, N_INV, N_INV), \
14209 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14210 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14211 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14212 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14213 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14214 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14215 X(vaddl, 0x0800000, N_INV, N_INV), \
14216 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14217 X(vsubl, 0x0800200, N_INV, N_INV), \
14218 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14219 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14220 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14221 /* Register variants of the following two instructions are encoded as
14222 vcge / vcgt with the operands reversed. */ \
14223 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14224 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14225 X(vfma, N_INV, 0x0000c10, N_INV), \
14226 X(vfms, N_INV, 0x0200c10, N_INV), \
14227 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14228 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14229 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14230 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14231 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14232 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14233 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14234 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14235 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14236 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14237 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14238 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14239 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14240 X(vshl, 0x0000400, N_INV, 0x0800510), \
14241 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14242 X(vand, 0x0000110, N_INV, 0x0800030), \
14243 X(vbic, 0x0100110, N_INV, 0x0800030), \
14244 X(veor, 0x1000110, N_INV, N_INV), \
14245 X(vorn, 0x0300110, N_INV, 0x0800010), \
14246 X(vorr, 0x0200110, N_INV, 0x0800010), \
14247 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14248 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14249 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14250 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14251 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14252 X(vst1, 0x0000000, 0x0800000, N_INV), \
14253 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14254 X(vst2, 0x0000100, 0x0800100, N_INV), \
14255 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14256 X(vst3, 0x0000200, 0x0800200, N_INV), \
14257 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14258 X(vst4, 0x0000300, 0x0800300, N_INV), \
14259 X(vmovn, 0x1b20200, N_INV, N_INV), \
14260 X(vtrn, 0x1b20080, N_INV, N_INV), \
14261 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14262 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14263 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14264 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14265 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14266 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14267 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14268 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14269 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14270 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14271 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14272 X(vseleq, 0xe000a00, N_INV, N_INV), \
14273 X(vselvs, 0xe100a00, N_INV, N_INV), \
14274 X(vselge, 0xe200a00, N_INV, N_INV), \
14275 X(vselgt, 0xe300a00, N_INV, N_INV), \
14276 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14277 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14278 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14279 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14280 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14281 X(aes, 0x3b00300, N_INV, N_INV), \
14282 X(sha3op, 0x2000c00, N_INV, N_INV), \
14283 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14284 X(sha2op, 0x3ba0380, N_INV, N_INV)
14288 #define X(OPC,I,F,S) N_MNEM_##OPC
14293 static const struct neon_tab_entry neon_enc_tab[] =
14295 #define X(OPC,I,F,S) { (I), (F), (S) }
14300 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14301 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14302 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14303 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14304 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14305 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14306 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14307 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14308 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14309 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14310 #define NEON_ENC_SINGLE_(X) \
14311 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14312 #define NEON_ENC_DOUBLE_(X) \
14313 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14314 #define NEON_ENC_FPV8_(X) \
14315 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14317 #define NEON_ENCODE(type, inst) \
14320 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14321 inst.is_neon = 1; \
14325 #define check_neon_suffixes \
14328 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14330 as_bad (_("invalid neon suffix for non neon instruction")); \
14336 /* Define shapes for instruction operands. The following mnemonic characters
14337 are used in this table:
14339 F - VFP S<n> register
14340 D - Neon D<n> register
14341 Q - Neon Q<n> register
14345 L - D<n> register list
14347 This table is used to generate various data:
14348 - enumerations of the form NS_DDR to be used as arguments to
14350 - a table classifying shapes into single, double, quad, mixed.
14351 - a table used to drive neon_select_shape. */
14353 #define NEON_SHAPE_DEF \
14354 X(4, (R, R, Q, Q), QUAD), \
14355 X(4, (Q, R, R, I), QUAD), \
14356 X(4, (R, R, S, S), QUAD), \
14357 X(4, (S, S, R, R), QUAD), \
14358 X(3, (Q, R, I), QUAD), \
14359 X(3, (I, Q, Q), QUAD), \
14360 X(3, (I, Q, R), QUAD), \
14361 X(3, (R, Q, Q), QUAD), \
14362 X(3, (D, D, D), DOUBLE), \
14363 X(3, (Q, Q, Q), QUAD), \
14364 X(3, (D, D, I), DOUBLE), \
14365 X(3, (Q, Q, I), QUAD), \
14366 X(3, (D, D, S), DOUBLE), \
14367 X(3, (Q, Q, S), QUAD), \
14368 X(3, (Q, Q, R), QUAD), \
14369 X(3, (R, R, Q), QUAD), \
14370 X(2, (R, Q), QUAD), \
14371 X(2, (D, D), DOUBLE), \
14372 X(2, (Q, Q), QUAD), \
14373 X(2, (D, S), DOUBLE), \
14374 X(2, (Q, S), QUAD), \
14375 X(2, (D, R), DOUBLE), \
14376 X(2, (Q, R), QUAD), \
14377 X(2, (D, I), DOUBLE), \
14378 X(2, (Q, I), QUAD), \
14379 X(3, (D, L, D), DOUBLE), \
14380 X(2, (D, Q), MIXED), \
14381 X(2, (Q, D), MIXED), \
14382 X(3, (D, Q, I), MIXED), \
14383 X(3, (Q, D, I), MIXED), \
14384 X(3, (Q, D, D), MIXED), \
14385 X(3, (D, Q, Q), MIXED), \
14386 X(3, (Q, Q, D), MIXED), \
14387 X(3, (Q, D, S), MIXED), \
14388 X(3, (D, Q, S), MIXED), \
14389 X(4, (D, D, D, I), DOUBLE), \
14390 X(4, (Q, Q, Q, I), QUAD), \
14391 X(4, (D, D, S, I), DOUBLE), \
14392 X(4, (Q, Q, S, I), QUAD), \
14393 X(2, (F, F), SINGLE), \
14394 X(3, (F, F, F), SINGLE), \
14395 X(2, (F, I), SINGLE), \
14396 X(2, (F, D), MIXED), \
14397 X(2, (D, F), MIXED), \
14398 X(3, (F, F, I), MIXED), \
14399 X(4, (R, R, F, F), SINGLE), \
14400 X(4, (F, F, R, R), SINGLE), \
14401 X(3, (D, R, R), DOUBLE), \
14402 X(3, (R, R, D), DOUBLE), \
14403 X(2, (S, R), SINGLE), \
14404 X(2, (R, S), SINGLE), \
14405 X(2, (F, R), SINGLE), \
14406 X(2, (R, F), SINGLE), \
14407 /* Half float shape supported so far. */\
14408 X (2, (H, D), MIXED), \
14409 X (2, (D, H), MIXED), \
14410 X (2, (H, F), MIXED), \
14411 X (2, (F, H), MIXED), \
14412 X (2, (H, H), HALF), \
14413 X (2, (H, R), HALF), \
14414 X (2, (R, H), HALF), \
14415 X (2, (H, I), HALF), \
14416 X (3, (H, H, H), HALF), \
14417 X (3, (H, F, I), MIXED), \
14418 X (3, (F, H, I), MIXED), \
14419 X (3, (D, H, H), MIXED), \
14420 X (3, (D, H, S), MIXED)
14422 #define S2(A,B) NS_##A##B
14423 #define S3(A,B,C) NS_##A##B##C
14424 #define S4(A,B,C,D) NS_##A##B##C##D
14426 #define X(N, L, C) S##N L
14439 enum neon_shape_class
14448 #define X(N, L, C) SC_##C
14450 static enum neon_shape_class neon_shape_class[] =
14469 /* Register widths of above. */
14470 static unsigned neon_shape_el_size[] =
14482 struct neon_shape_info
14485 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14488 #define S2(A,B) { SE_##A, SE_##B }
14489 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14490 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14492 #define X(N, L, C) { N, S##N L }
14494 static struct neon_shape_info neon_shape_tab[] =
14504 /* Bit masks used in type checking given instructions.
14505 'N_EQK' means the type must be the same as (or based on in some way) the key
14506 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14507 set, various other bits can be set as well in order to modify the meaning of
14508 the type constraint. */
14510 enum neon_type_mask
14534 N_KEY = 0x1000000, /* Key element (main type specifier). */
14535 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
14536 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
14537 N_UNT = 0x8000000, /* Must be explicitly untyped. */
14538 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14539 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14540 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14541 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14542 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14543 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14544 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14546 N_MAX_NONSPECIAL = N_P64
14549 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14551 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14552 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14553 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14554 #define N_S_32 (N_S8 | N_S16 | N_S32)
14555 #define N_F_16_32 (N_F16 | N_F32)
14556 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14557 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14558 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14559 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14560 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14561 #define N_F_MVE (N_F16 | N_F32)
14562 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14564 /* Pass this as the first type argument to neon_check_type to ignore types
14566 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14568 /* Select a "shape" for the current instruction (describing register types or
14569 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14570 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14571 function of operand parsing, so this function doesn't need to be called.
14572 Shapes should be listed in order of decreasing length. */
14574 static enum neon_shape
14575 neon_select_shape (enum neon_shape shape, ...)
14578 enum neon_shape first_shape = shape;
14580 /* Fix missing optional operands. FIXME: we don't know at this point how
14581 many arguments we should have, so this makes the assumption that we have
14582 > 1. This is true of all current Neon opcodes, I think, but may not be
14583 true in the future. */
14584 if (!inst.operands[1].present)
14585 inst.operands[1] = inst.operands[0];
14587 va_start (ap, shape);
14589 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
14594 for (j = 0; j < neon_shape_tab[shape].els; j++)
14596 if (!inst.operands[j].present)
14602 switch (neon_shape_tab[shape].el[j])
14604 /* If a .f16, .16, .u16, .s16 type specifier is given over
14605 a VFP single precision register operand, it's essentially
14606 means only half of the register is used.
14608 If the type specifier is given after the mnemonics, the
14609 information is stored in inst.vectype. If the type specifier
14610 is given after register operand, the information is stored
14611 in inst.operands[].vectype.
14613 When there is only one type specifier, and all the register
14614 operands are the same type of hardware register, the type
14615 specifier applies to all register operands.
14617 If no type specifier is given, the shape is inferred from
14618 operand information.
14621 vadd.f16 s0, s1, s2: NS_HHH
14622 vabs.f16 s0, s1: NS_HH
14623 vmov.f16 s0, r1: NS_HR
14624 vmov.f16 r0, s1: NS_RH
14625 vcvt.f16 r0, s1: NS_RH
14626 vcvt.f16.s32 s2, s2, #29: NS_HFI
14627 vcvt.f16.s32 s2, s2: NS_HF
14630 if (!(inst.operands[j].isreg
14631 && inst.operands[j].isvec
14632 && inst.operands[j].issingle
14633 && !inst.operands[j].isquad
14634 && ((inst.vectype.elems == 1
14635 && inst.vectype.el[0].size == 16)
14636 || (inst.vectype.elems > 1
14637 && inst.vectype.el[j].size == 16)
14638 || (inst.vectype.elems == 0
14639 && inst.operands[j].vectype.type != NT_invtype
14640 && inst.operands[j].vectype.size == 16))))
14645 if (!(inst.operands[j].isreg
14646 && inst.operands[j].isvec
14647 && inst.operands[j].issingle
14648 && !inst.operands[j].isquad
14649 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14650 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14651 || (inst.vectype.elems == 0
14652 && (inst.operands[j].vectype.size == 32
14653 || inst.operands[j].vectype.type == NT_invtype)))))
14658 if (!(inst.operands[j].isreg
14659 && inst.operands[j].isvec
14660 && !inst.operands[j].isquad
14661 && !inst.operands[j].issingle))
14666 if (!(inst.operands[j].isreg
14667 && !inst.operands[j].isvec))
14672 if (!(inst.operands[j].isreg
14673 && inst.operands[j].isvec
14674 && inst.operands[j].isquad
14675 && !inst.operands[j].issingle))
14680 if (!(!inst.operands[j].isreg
14681 && !inst.operands[j].isscalar))
14686 if (!(!inst.operands[j].isreg
14687 && inst.operands[j].isscalar))
14697 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
14698 /* We've matched all the entries in the shape table, and we don't
14699 have any left over operands which have not been matched. */
14705 if (shape == NS_NULL && first_shape != NS_NULL)
14706 first_error (_("invalid instruction shape"));
14711 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14712 means the Q bit should be set). */
14715 neon_quad (enum neon_shape shape)
14717 return neon_shape_class[shape] == SC_QUAD;
14721 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
14724 /* Allow modification to be made to types which are constrained to be
14725 based on the key element, based on bits set alongside N_EQK. */
14726 if ((typebits & N_EQK) != 0)
14728 if ((typebits & N_HLF) != 0)
14730 else if ((typebits & N_DBL) != 0)
14732 if ((typebits & N_SGN) != 0)
14733 *g_type = NT_signed;
14734 else if ((typebits & N_UNS) != 0)
14735 *g_type = NT_unsigned;
14736 else if ((typebits & N_INT) != 0)
14737 *g_type = NT_integer;
14738 else if ((typebits & N_FLT) != 0)
14739 *g_type = NT_float;
14740 else if ((typebits & N_SIZ) != 0)
14741 *g_type = NT_untyped;
14745 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14746 operand type, i.e. the single type specified in a Neon instruction when it
14747 is the only one given. */
14749 static struct neon_type_el
14750 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
14752 struct neon_type_el dest = *key;
14754 gas_assert ((thisarg & N_EQK) != 0);
14756 neon_modify_type_size (thisarg, &dest.type, &dest.size);
14761 /* Convert Neon type and size into compact bitmask representation. */
14763 static enum neon_type_mask
14764 type_chk_of_el_type (enum neon_el_type type, unsigned size)
14771 case 8: return N_8;
14772 case 16: return N_16;
14773 case 32: return N_32;
14774 case 64: return N_64;
14782 case 8: return N_I8;
14783 case 16: return N_I16;
14784 case 32: return N_I32;
14785 case 64: return N_I64;
14793 case 16: return N_F16;
14794 case 32: return N_F32;
14795 case 64: return N_F64;
14803 case 8: return N_P8;
14804 case 16: return N_P16;
14805 case 64: return N_P64;
14813 case 8: return N_S8;
14814 case 16: return N_S16;
14815 case 32: return N_S32;
14816 case 64: return N_S64;
14824 case 8: return N_U8;
14825 case 16: return N_U16;
14826 case 32: return N_U32;
14827 case 64: return N_U64;
14838 /* Convert compact Neon bitmask type representation to a type and size. Only
14839 handles the case where a single bit is set in the mask. */
14842 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
14843 enum neon_type_mask mask)
14845 if ((mask & N_EQK) != 0)
14848 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
14850 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
14852 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
14854 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
14859 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
14861 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
14862 *type = NT_unsigned;
14863 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
14864 *type = NT_integer;
14865 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
14866 *type = NT_untyped;
14867 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
14869 else if ((mask & (N_F_ALL)) != 0)
14877 /* Modify a bitmask of allowed types. This is only needed for type
14881 modify_types_allowed (unsigned allowed, unsigned mods)
14884 enum neon_el_type type;
14890 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
14892 if (el_type_of_type_chk (&type, &size,
14893 (enum neon_type_mask) (allowed & i)) == SUCCESS)
14895 neon_modify_type_size (mods, &type, &size);
14896 destmask |= type_chk_of_el_type (type, size);
14903 /* Check type and return type classification.
14904 The manual states (paraphrase): If one datatype is given, it indicates the
14906 - the second operand, if there is one
14907 - the operand, if there is no second operand
14908 - the result, if there are no operands.
14909 This isn't quite good enough though, so we use a concept of a "key" datatype
14910 which is set on a per-instruction basis, which is the one which matters when
14911 only one data type is written.
14912 Note: this function has side-effects (e.g. filling in missing operands). All
14913 Neon instructions should call it before performing bit encoding. */
14915 static struct neon_type_el
14916 neon_check_type (unsigned els, enum neon_shape ns, ...)
14919 unsigned i, pass, key_el = 0;
14920 unsigned types[NEON_MAX_TYPE_ELS];
14921 enum neon_el_type k_type = NT_invtype;
14922 unsigned k_size = -1u;
14923 struct neon_type_el badtype = {NT_invtype, -1};
14924 unsigned key_allowed = 0;
14926 /* Optional registers in Neon instructions are always (not) in operand 1.
14927 Fill in the missing operand here, if it was omitted. */
14928 if (els > 1 && !inst.operands[1].present)
14929 inst.operands[1] = inst.operands[0];
14931 /* Suck up all the varargs. */
14933 for (i = 0; i < els; i++)
14935 unsigned thisarg = va_arg (ap, unsigned);
14936 if (thisarg == N_IGNORE_TYPE)
14941 types[i] = thisarg;
14942 if ((thisarg & N_KEY) != 0)
14947 if (inst.vectype.elems > 0)
14948 for (i = 0; i < els; i++)
14949 if (inst.operands[i].vectype.type != NT_invtype)
14951 first_error (_("types specified in both the mnemonic and operands"));
14955 /* Duplicate inst.vectype elements here as necessary.
14956 FIXME: No idea if this is exactly the same as the ARM assembler,
14957 particularly when an insn takes one register and one non-register
14959 if (inst.vectype.elems == 1 && els > 1)
14962 inst.vectype.elems = els;
14963 inst.vectype.el[key_el] = inst.vectype.el[0];
14964 for (j = 0; j < els; j++)
14966 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14969 else if (inst.vectype.elems == 0 && els > 0)
14972 /* No types were given after the mnemonic, so look for types specified
14973 after each operand. We allow some flexibility here; as long as the
14974 "key" operand has a type, we can infer the others. */
14975 for (j = 0; j < els; j++)
14976 if (inst.operands[j].vectype.type != NT_invtype)
14977 inst.vectype.el[j] = inst.operands[j].vectype;
14979 if (inst.operands[key_el].vectype.type != NT_invtype)
14981 for (j = 0; j < els; j++)
14982 if (inst.operands[j].vectype.type == NT_invtype)
14983 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14988 first_error (_("operand types can't be inferred"));
14992 else if (inst.vectype.elems != els)
14994 first_error (_("type specifier has the wrong number of parts"));
14998 for (pass = 0; pass < 2; pass++)
15000 for (i = 0; i < els; i++)
15002 unsigned thisarg = types[i];
15003 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15004 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15005 enum neon_el_type g_type = inst.vectype.el[i].type;
15006 unsigned g_size = inst.vectype.el[i].size;
15008 /* Decay more-specific signed & unsigned types to sign-insensitive
15009 integer types if sign-specific variants are unavailable. */
15010 if ((g_type == NT_signed || g_type == NT_unsigned)
15011 && (types_allowed & N_SU_ALL) == 0)
15012 g_type = NT_integer;
15014 /* If only untyped args are allowed, decay any more specific types to
15015 them. Some instructions only care about signs for some element
15016 sizes, so handle that properly. */
15017 if (((types_allowed & N_UNT) == 0)
15018 && ((g_size == 8 && (types_allowed & N_8) != 0)
15019 || (g_size == 16 && (types_allowed & N_16) != 0)
15020 || (g_size == 32 && (types_allowed & N_32) != 0)
15021 || (g_size == 64 && (types_allowed & N_64) != 0)))
15022 g_type = NT_untyped;
15026 if ((thisarg & N_KEY) != 0)
15030 key_allowed = thisarg & ~N_KEY;
15032 /* Check architecture constraint on FP16 extension. */
15034 && k_type == NT_float
15035 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15037 inst.error = _(BAD_FP16);
15044 if ((thisarg & N_VFP) != 0)
15046 enum neon_shape_el regshape;
15047 unsigned regwidth, match;
15049 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15052 first_error (_("invalid instruction shape"));
15055 regshape = neon_shape_tab[ns].el[i];
15056 regwidth = neon_shape_el_size[regshape];
15058 /* In VFP mode, operands must match register widths. If we
15059 have a key operand, use its width, else use the width of
15060 the current operand. */
15066 /* FP16 will use a single precision register. */
15067 if (regwidth == 32 && match == 16)
15069 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15073 inst.error = _(BAD_FP16);
15078 if (regwidth != match)
15080 first_error (_("operand size must match register width"));
15085 if ((thisarg & N_EQK) == 0)
15087 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15089 if ((given_type & types_allowed) == 0)
15091 first_error (BAD_SIMD_TYPE);
15097 enum neon_el_type mod_k_type = k_type;
15098 unsigned mod_k_size = k_size;
15099 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15100 if (g_type != mod_k_type || g_size != mod_k_size)
15102 first_error (_("inconsistent types in Neon instruction"));
15110 return inst.vectype.el[key_el];
15113 /* Neon-style VFP instruction forwarding. */
15115 /* Thumb VFP instructions have 0xE in the condition field. */
15118 do_vfp_cond_or_thumb (void)
15123 inst.instruction |= 0xe0000000;
15125 inst.instruction |= inst.cond << 28;
15128 /* Look up and encode a simple mnemonic, for use as a helper function for the
15129 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15130 etc. It is assumed that operand parsing has already been done, and that the
15131 operands are in the form expected by the given opcode (this isn't necessarily
15132 the same as the form in which they were parsed, hence some massaging must
15133 take place before this function is called).
15134 Checks current arch version against that in the looked-up opcode. */
15137 do_vfp_nsyn_opcode (const char *opname)
15139 const struct asm_opcode *opcode;
15141 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
15146 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
15147 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15154 inst.instruction = opcode->tvalue;
15155 opcode->tencode ();
15159 inst.instruction = (inst.cond << 28) | opcode->avalue;
15160 opcode->aencode ();
15165 do_vfp_nsyn_add_sub (enum neon_shape rs)
15167 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15169 if (rs == NS_FFF || rs == NS_HHH)
15172 do_vfp_nsyn_opcode ("fadds");
15174 do_vfp_nsyn_opcode ("fsubs");
15176 /* ARMv8.2 fp16 instruction. */
15178 do_scalar_fp16_v82_encode ();
15183 do_vfp_nsyn_opcode ("faddd");
15185 do_vfp_nsyn_opcode ("fsubd");
15189 /* Check operand types to see if this is a VFP instruction, and if so call
15193 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15195 enum neon_shape rs;
15196 struct neon_type_el et;
15201 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15202 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15206 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15207 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15208 N_F_ALL | N_KEY | N_VFP);
15215 if (et.type != NT_invtype)
15226 do_vfp_nsyn_mla_mls (enum neon_shape rs)
15228 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15230 if (rs == NS_FFF || rs == NS_HHH)
15233 do_vfp_nsyn_opcode ("fmacs");
15235 do_vfp_nsyn_opcode ("fnmacs");
15237 /* ARMv8.2 fp16 instruction. */
15239 do_scalar_fp16_v82_encode ();
15244 do_vfp_nsyn_opcode ("fmacd");
15246 do_vfp_nsyn_opcode ("fnmacd");
15251 do_vfp_nsyn_fma_fms (enum neon_shape rs)
15253 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15255 if (rs == NS_FFF || rs == NS_HHH)
15258 do_vfp_nsyn_opcode ("ffmas");
15260 do_vfp_nsyn_opcode ("ffnmas");
15262 /* ARMv8.2 fp16 instruction. */
15264 do_scalar_fp16_v82_encode ();
15269 do_vfp_nsyn_opcode ("ffmad");
15271 do_vfp_nsyn_opcode ("ffnmad");
15276 do_vfp_nsyn_mul (enum neon_shape rs)
15278 if (rs == NS_FFF || rs == NS_HHH)
15280 do_vfp_nsyn_opcode ("fmuls");
15282 /* ARMv8.2 fp16 instruction. */
15284 do_scalar_fp16_v82_encode ();
15287 do_vfp_nsyn_opcode ("fmuld");
15291 do_vfp_nsyn_abs_neg (enum neon_shape rs)
15293 int is_neg = (inst.instruction & 0x80) != 0;
15294 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
15296 if (rs == NS_FF || rs == NS_HH)
15299 do_vfp_nsyn_opcode ("fnegs");
15301 do_vfp_nsyn_opcode ("fabss");
15303 /* ARMv8.2 fp16 instruction. */
15305 do_scalar_fp16_v82_encode ();
15310 do_vfp_nsyn_opcode ("fnegd");
15312 do_vfp_nsyn_opcode ("fabsd");
15316 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15317 insns belong to Neon, and are handled elsewhere. */
15320 do_vfp_nsyn_ldm_stm (int is_dbmode)
15322 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15326 do_vfp_nsyn_opcode ("fldmdbs");
15328 do_vfp_nsyn_opcode ("fldmias");
15333 do_vfp_nsyn_opcode ("fstmdbs");
15335 do_vfp_nsyn_opcode ("fstmias");
15340 do_vfp_nsyn_sqrt (void)
15342 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15343 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15345 if (rs == NS_FF || rs == NS_HH)
15347 do_vfp_nsyn_opcode ("fsqrts");
15349 /* ARMv8.2 fp16 instruction. */
15351 do_scalar_fp16_v82_encode ();
15354 do_vfp_nsyn_opcode ("fsqrtd");
15358 do_vfp_nsyn_div (void)
15360 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15361 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15362 N_F_ALL | N_KEY | N_VFP);
15364 if (rs == NS_FFF || rs == NS_HHH)
15366 do_vfp_nsyn_opcode ("fdivs");
15368 /* ARMv8.2 fp16 instruction. */
15370 do_scalar_fp16_v82_encode ();
15373 do_vfp_nsyn_opcode ("fdivd");
15377 do_vfp_nsyn_nmul (void)
15379 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15380 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15381 N_F_ALL | N_KEY | N_VFP);
15383 if (rs == NS_FFF || rs == NS_HHH)
15385 NEON_ENCODE (SINGLE, inst);
15386 do_vfp_sp_dyadic ();
15388 /* ARMv8.2 fp16 instruction. */
15390 do_scalar_fp16_v82_encode ();
15394 NEON_ENCODE (DOUBLE, inst);
15395 do_vfp_dp_rd_rn_rm ();
15397 do_vfp_cond_or_thumb ();
15401 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15405 neon_logbits (unsigned x)
15407 return ffs (x) - 4;
15410 #define LOW4(R) ((R) & 0xf)
15411 #define HI1(R) (((R) >> 4) & 1)
15414 mve_get_vcmp_vpt_cond (struct neon_type_el et)
15419 first_error (BAD_EL_TYPE);
15422 switch (inst.operands[0].imm)
15425 first_error (_("invalid condition"));
15447 /* only accept eq and ne. */
15448 if (inst.operands[0].imm > 1)
15450 first_error (_("invalid condition"));
15453 return inst.operands[0].imm;
15455 if (inst.operands[0].imm == 0x2)
15457 else if (inst.operands[0].imm == 0x8)
15461 first_error (_("invalid condition"));
15465 switch (inst.operands[0].imm)
15468 first_error (_("invalid condition"));
15484 /* Should be unreachable. */
15491 /* We are dealing with a vector predicated block. */
15492 if (inst.operands[0].present)
15494 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15495 struct neon_type_el et
15496 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15499 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15501 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15503 if (et.type == NT_invtype)
15506 if (et.type == NT_float)
15508 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15510 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15511 inst.instruction |= (et.size == 16) << 28;
15512 inst.instruction |= 0x3 << 20;
15516 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15518 inst.instruction |= 1 << 28;
15519 inst.instruction |= neon_logbits (et.size) << 20;
15522 if (inst.operands[2].isquad)
15524 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15525 inst.instruction |= LOW4 (inst.operands[2].reg);
15526 inst.instruction |= (fcond & 0x2) >> 1;
15530 if (inst.operands[2].reg == REG_SP)
15531 as_tsktsk (MVE_BAD_SP);
15532 inst.instruction |= 1 << 6;
15533 inst.instruction |= (fcond & 0x2) << 4;
15534 inst.instruction |= inst.operands[2].reg;
15536 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15537 inst.instruction |= (fcond & 0x4) << 10;
15538 inst.instruction |= (fcond & 0x1) << 7;
15541 set_pred_insn_type (VPT_INSN);
15543 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15544 | ((inst.instruction & 0xe000) >> 13);
15545 now_pred.warn_deprecated = FALSE;
15546 now_pred.type = VECTOR_PRED;
15553 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15554 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15555 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15556 if (!inst.operands[2].present)
15557 first_error (_("MVE vector or ARM register expected"));
15558 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15560 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15561 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15562 && inst.operands[1].isquad)
15564 inst.instruction = N_MNEM_vcmp;
15568 if (inst.cond > COND_ALWAYS)
15569 inst.pred_insn_type = INSIDE_VPT_INSN;
15571 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15573 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15574 struct neon_type_el et
15575 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15578 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15579 && !inst.operands[2].iszr, BAD_PC);
15581 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15583 inst.instruction = 0xee010f00;
15584 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15585 inst.instruction |= (fcond & 0x4) << 10;
15586 inst.instruction |= (fcond & 0x1) << 7;
15587 if (et.type == NT_float)
15589 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15591 inst.instruction |= (et.size == 16) << 28;
15592 inst.instruction |= 0x3 << 20;
15596 inst.instruction |= 1 << 28;
15597 inst.instruction |= neon_logbits (et.size) << 20;
15599 if (inst.operands[2].isquad)
15601 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15602 inst.instruction |= (fcond & 0x2) >> 1;
15603 inst.instruction |= LOW4 (inst.operands[2].reg);
15607 if (inst.operands[2].reg == REG_SP)
15608 as_tsktsk (MVE_BAD_SP);
15609 inst.instruction |= 1 << 6;
15610 inst.instruction |= (fcond & 0x2) << 4;
15611 inst.instruction |= inst.operands[2].reg;
15619 do_mve_vmaxa_vmina (void)
15621 if (inst.cond > COND_ALWAYS)
15622 inst.pred_insn_type = INSIDE_VPT_INSN;
15624 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15626 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15627 struct neon_type_el et
15628 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15630 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15631 inst.instruction |= neon_logbits (et.size) << 18;
15632 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15633 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15634 inst.instruction |= LOW4 (inst.operands[1].reg);
15639 do_mve_vfmas (void)
15641 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15642 struct neon_type_el et
15643 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15645 if (inst.cond > COND_ALWAYS)
15646 inst.pred_insn_type = INSIDE_VPT_INSN;
15648 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15650 if (inst.operands[2].reg == REG_SP)
15651 as_tsktsk (MVE_BAD_SP);
15652 else if (inst.operands[2].reg == REG_PC)
15653 as_tsktsk (MVE_BAD_PC);
15655 inst.instruction |= (et.size == 16) << 28;
15656 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15657 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15658 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15659 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15660 inst.instruction |= inst.operands[2].reg;
15665 do_mve_viddup (void)
15667 if (inst.cond > COND_ALWAYS)
15668 inst.pred_insn_type = INSIDE_VPT_INSN;
15670 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15672 unsigned imm = inst.relocs[0].exp.X_add_number;
15673 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
15674 _("immediate must be either 1, 2, 4 or 8"));
15676 enum neon_shape rs;
15677 struct neon_type_el et;
15679 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
15681 rs = neon_select_shape (NS_QRI, NS_NULL);
15682 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
15687 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
15688 if (inst.operands[2].reg == REG_SP)
15689 as_tsktsk (MVE_BAD_SP);
15690 else if (inst.operands[2].reg == REG_PC)
15691 first_error (BAD_PC);
15693 rs = neon_select_shape (NS_QRRI, NS_NULL);
15694 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
15695 Rm = inst.operands[2].reg >> 1;
15697 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15698 inst.instruction |= neon_logbits (et.size) << 20;
15699 inst.instruction |= inst.operands[1].reg << 16;
15700 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15701 inst.instruction |= (imm > 2) << 7;
15702 inst.instruction |= Rm << 1;
15703 inst.instruction |= (imm == 2 || imm == 8);
15708 do_mve_vmaxnma_vminnma (void)
15710 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15711 struct neon_type_el et
15712 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
15714 if (inst.cond > COND_ALWAYS)
15715 inst.pred_insn_type = INSIDE_VPT_INSN;
15717 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15719 inst.instruction |= (et.size == 16) << 28;
15720 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15721 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15722 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15723 inst.instruction |= LOW4 (inst.operands[1].reg);
15728 do_mve_vcmul (void)
15730 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
15731 struct neon_type_el et
15732 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
15734 if (inst.cond > COND_ALWAYS)
15735 inst.pred_insn_type = INSIDE_VPT_INSN;
15737 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15739 unsigned rot = inst.relocs[0].exp.X_add_number;
15740 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
15741 _("immediate out of range"));
15743 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
15744 || inst.operands[0].reg == inst.operands[2].reg))
15745 as_tsktsk (BAD_MVE_SRCDEST);
15747 inst.instruction |= (et.size == 32) << 28;
15748 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15749 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15750 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15751 inst.instruction |= (rot > 90) << 12;
15752 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15753 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15754 inst.instruction |= LOW4 (inst.operands[2].reg);
15755 inst.instruction |= (rot == 90 || rot == 270);
15760 do_vfp_nsyn_cmp (void)
15762 enum neon_shape rs;
15763 if (!inst.operands[0].isreg)
15770 constraint (inst.operands[2].present, BAD_SYNTAX);
15771 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
15775 if (inst.operands[1].isreg)
15777 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15778 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15780 if (rs == NS_FF || rs == NS_HH)
15782 NEON_ENCODE (SINGLE, inst);
15783 do_vfp_sp_monadic ();
15787 NEON_ENCODE (DOUBLE, inst);
15788 do_vfp_dp_rd_rm ();
15793 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
15794 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
15796 switch (inst.instruction & 0x0fffffff)
15799 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
15802 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
15808 if (rs == NS_FI || rs == NS_HI)
15810 NEON_ENCODE (SINGLE, inst);
15811 do_vfp_sp_compare_z ();
15815 NEON_ENCODE (DOUBLE, inst);
15819 do_vfp_cond_or_thumb ();
15821 /* ARMv8.2 fp16 instruction. */
15822 if (rs == NS_HI || rs == NS_HH)
15823 do_scalar_fp16_v82_encode ();
15827 nsyn_insert_sp (void)
15829 inst.operands[1] = inst.operands[0];
15830 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
15831 inst.operands[0].reg = REG_SP;
15832 inst.operands[0].isreg = 1;
15833 inst.operands[0].writeback = 1;
15834 inst.operands[0].present = 1;
15838 do_vfp_nsyn_push (void)
15842 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15843 _("register list must contain at least 1 and at most 16 "
15846 if (inst.operands[1].issingle)
15847 do_vfp_nsyn_opcode ("fstmdbs");
15849 do_vfp_nsyn_opcode ("fstmdbd");
15853 do_vfp_nsyn_pop (void)
15857 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15858 _("register list must contain at least 1 and at most 16 "
15861 if (inst.operands[1].issingle)
15862 do_vfp_nsyn_opcode ("fldmias");
15864 do_vfp_nsyn_opcode ("fldmiad");
15867 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15868 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15871 neon_dp_fixup (struct arm_it* insn)
15873 unsigned int i = insn->instruction;
15878 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15889 insn->instruction = i;
15893 mve_encode_qqr (int size, int U, int fp)
15895 if (inst.operands[2].reg == REG_SP)
15896 as_tsktsk (MVE_BAD_SP);
15897 else if (inst.operands[2].reg == REG_PC)
15898 as_tsktsk (MVE_BAD_PC);
15903 if (((unsigned)inst.instruction) == 0xd00)
15904 inst.instruction = 0xee300f40;
15906 else if (((unsigned)inst.instruction) == 0x200d00)
15907 inst.instruction = 0xee301f40;
15909 else if (((unsigned)inst.instruction) == 0x1000d10)
15910 inst.instruction = 0xee310e60;
15912 /* Setting size which is 1 for F16 and 0 for F32. */
15913 inst.instruction |= (size == 16) << 28;
15918 if (((unsigned)inst.instruction) == 0x800)
15919 inst.instruction = 0xee010f40;
15921 else if (((unsigned)inst.instruction) == 0x1000800)
15922 inst.instruction = 0xee011f40;
15924 else if (((unsigned)inst.instruction) == 0)
15925 inst.instruction = 0xee000f40;
15927 else if (((unsigned)inst.instruction) == 0x200)
15928 inst.instruction = 0xee001f40;
15930 else if (((unsigned)inst.instruction) == 0x900)
15931 inst.instruction = 0xee010e40;
15933 else if (((unsigned)inst.instruction) == 0x910)
15934 inst.instruction = 0xee011e60;
15936 else if (((unsigned)inst.instruction) == 0x10)
15937 inst.instruction = 0xee000f60;
15939 else if (((unsigned)inst.instruction) == 0x210)
15940 inst.instruction = 0xee001f60;
15943 inst.instruction |= U << 28;
15945 /* Setting bits for size. */
15946 inst.instruction |= neon_logbits (size) << 20;
15948 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15949 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15950 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15951 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15952 inst.instruction |= inst.operands[2].reg;
15957 mve_encode_rqq (unsigned bit28, unsigned size)
15959 inst.instruction |= bit28 << 28;
15960 inst.instruction |= neon_logbits (size) << 20;
15961 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15962 inst.instruction |= inst.operands[0].reg << 12;
15963 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15964 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15965 inst.instruction |= LOW4 (inst.operands[2].reg);
15970 mve_encode_qqq (int ubit, int size)
15973 inst.instruction |= (ubit != 0) << 28;
15974 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15975 inst.instruction |= neon_logbits (size) << 20;
15976 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15977 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15978 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15979 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15980 inst.instruction |= LOW4 (inst.operands[2].reg);
15986 mve_encode_rq (unsigned bit28, unsigned size)
15988 inst.instruction |= bit28 << 28;
15989 inst.instruction |= neon_logbits (size) << 18;
15990 inst.instruction |= inst.operands[0].reg << 12;
15991 inst.instruction |= LOW4 (inst.operands[1].reg);
15996 mve_encode_rrqq (unsigned U, unsigned size)
15998 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16000 inst.instruction |= U << 28;
16001 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16002 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16003 inst.instruction |= (size == 32) << 16;
16004 inst.instruction |= inst.operands[0].reg << 12;
16005 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16006 inst.instruction |= inst.operands[3].reg;
16010 /* Encode insns with bit pattern:
16012 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16013 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16015 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16016 different meaning for some instruction. */
16019 neon_three_same (int isquad, int ubit, int size)
16021 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16022 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16023 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16024 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16025 inst.instruction |= LOW4 (inst.operands[2].reg);
16026 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16027 inst.instruction |= (isquad != 0) << 6;
16028 inst.instruction |= (ubit != 0) << 24;
16030 inst.instruction |= neon_logbits (size) << 20;
16032 neon_dp_fixup (&inst);
16035 /* Encode instructions of the form:
16037 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16038 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16040 Don't write size if SIZE == -1. */
16043 neon_two_same (int qbit, int ubit, int size)
16045 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16046 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16047 inst.instruction |= LOW4 (inst.operands[1].reg);
16048 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16049 inst.instruction |= (qbit != 0) << 6;
16050 inst.instruction |= (ubit != 0) << 24;
16053 inst.instruction |= neon_logbits (size) << 18;
16055 neon_dp_fixup (&inst);
16058 enum vfp_or_neon_is_neon_bits
16061 NEON_CHECK_ARCH = 2,
16062 NEON_CHECK_ARCH8 = 4
16065 /* Call this function if an instruction which may have belonged to the VFP or
16066 Neon instruction sets, but turned out to be a Neon instruction (due to the
16067 operand types involved, etc.). We have to check and/or fix-up a couple of
16070 - Make sure the user hasn't attempted to make a Neon instruction
16072 - Alter the value in the condition code field if necessary.
16073 - Make sure that the arch supports Neon instructions.
16075 Which of these operations take place depends on bits from enum
16076 vfp_or_neon_is_neon_bits.
16078 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16079 current instruction's condition is COND_ALWAYS, the condition field is
16080 changed to inst.uncond_value. This is necessary because instructions shared
16081 between VFP and Neon may be conditional for the VFP variants only, and the
16082 unconditional Neon version must have, e.g., 0xF in the condition field. */
16085 vfp_or_neon_is_neon (unsigned check)
16087 /* Conditions are always legal in Thumb mode (IT blocks). */
16088 if (!thumb_mode && (check & NEON_CHECK_CC))
16090 if (inst.cond != COND_ALWAYS)
16092 first_error (_(BAD_COND));
16095 if (inst.uncond_value != -1)
16096 inst.instruction |= inst.uncond_value << 28;
16100 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16101 || ((check & NEON_CHECK_ARCH8)
16102 && !mark_feature_used (&fpu_neon_ext_armv8)))
16104 first_error (_(BAD_FPU));
16112 check_simd_pred_availability (int fp, unsigned check)
16114 if (inst.cond > COND_ALWAYS)
16116 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16118 inst.error = BAD_FPU;
16121 inst.pred_insn_type = INSIDE_VPT_INSN;
16123 else if (inst.cond < COND_ALWAYS)
16125 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16126 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16127 else if (vfp_or_neon_is_neon (check) == FAIL)
16132 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16133 && vfp_or_neon_is_neon (check) == FAIL)
16136 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16137 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16142 /* Neon instruction encoders, in approximate order of appearance. */
16145 do_neon_dyadic_i_su (void)
16147 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16150 enum neon_shape rs;
16151 struct neon_type_el et;
16152 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16153 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16155 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16157 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16161 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16163 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16167 do_neon_dyadic_i64_su (void)
16169 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
16171 enum neon_shape rs;
16172 struct neon_type_el et;
16173 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16175 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16176 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16180 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16181 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16184 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16186 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16190 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
16193 unsigned size = et.size >> 3;
16194 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16195 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16196 inst.instruction |= LOW4 (inst.operands[1].reg);
16197 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16198 inst.instruction |= (isquad != 0) << 6;
16199 inst.instruction |= immbits << 16;
16200 inst.instruction |= (size >> 3) << 7;
16201 inst.instruction |= (size & 0x7) << 19;
16203 inst.instruction |= (uval != 0) << 24;
16205 neon_dp_fixup (&inst);
16209 do_neon_shl_imm (void)
16211 if (!inst.operands[2].isreg)
16213 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16214 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16215 int imm = inst.operands[2].imm;
16217 constraint (imm < 0 || (unsigned)imm >= et.size,
16218 _("immediate out of range for shift"));
16219 NEON_ENCODE (IMMED, inst);
16220 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
16224 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16225 struct neon_type_el et = neon_check_type (3, rs,
16226 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16229 /* VSHL/VQSHL 3-register variants have syntax such as:
16231 whereas other 3-register operations encoded by neon_three_same have
16234 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
16236 tmp = inst.operands[2].reg;
16237 inst.operands[2].reg = inst.operands[1].reg;
16238 inst.operands[1].reg = tmp;
16239 NEON_ENCODE (INTEGER, inst);
16240 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16245 do_neon_qshl_imm (void)
16247 if (!inst.operands[2].isreg)
16249 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16250 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16251 int imm = inst.operands[2].imm;
16253 constraint (imm < 0 || (unsigned)imm >= et.size,
16254 _("immediate out of range for shift"));
16255 NEON_ENCODE (IMMED, inst);
16256 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
16260 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16261 struct neon_type_el et = neon_check_type (3, rs,
16262 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16265 /* See note in do_neon_shl_imm. */
16266 tmp = inst.operands[2].reg;
16267 inst.operands[2].reg = inst.operands[1].reg;
16268 inst.operands[1].reg = tmp;
16269 NEON_ENCODE (INTEGER, inst);
16270 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16275 do_neon_rshl (void)
16277 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16278 struct neon_type_el et = neon_check_type (3, rs,
16279 N_EQK, N_EQK, N_SU_ALL | N_KEY);
16282 tmp = inst.operands[2].reg;
16283 inst.operands[2].reg = inst.operands[1].reg;
16284 inst.operands[1].reg = tmp;
16285 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16289 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
16291 /* Handle .I8 pseudo-instructions. */
16294 /* Unfortunately, this will make everything apart from zero out-of-range.
16295 FIXME is this the intended semantics? There doesn't seem much point in
16296 accepting .I8 if so. */
16297 immediate |= immediate << 8;
16303 if (immediate == (immediate & 0x000000ff))
16305 *immbits = immediate;
16308 else if (immediate == (immediate & 0x0000ff00))
16310 *immbits = immediate >> 8;
16313 else if (immediate == (immediate & 0x00ff0000))
16315 *immbits = immediate >> 16;
16318 else if (immediate == (immediate & 0xff000000))
16320 *immbits = immediate >> 24;
16323 if ((immediate & 0xffff) != (immediate >> 16))
16324 goto bad_immediate;
16325 immediate &= 0xffff;
16328 if (immediate == (immediate & 0x000000ff))
16330 *immbits = immediate;
16333 else if (immediate == (immediate & 0x0000ff00))
16335 *immbits = immediate >> 8;
16340 first_error (_("immediate value out of range"));
16345 do_neon_logic (void)
16347 if (inst.operands[2].present && inst.operands[2].isreg)
16349 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16351 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16354 else if (rs != NS_QQQ
16355 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16356 first_error (BAD_FPU);
16358 neon_check_type (3, rs, N_IGNORE_TYPE);
16359 /* U bit and size field were set as part of the bitmask. */
16360 NEON_ENCODE (INTEGER, inst);
16361 neon_three_same (neon_quad (rs), 0, -1);
16365 const int three_ops_form = (inst.operands[2].present
16366 && !inst.operands[2].isreg);
16367 const int immoperand = (three_ops_form ? 2 : 1);
16368 enum neon_shape rs = (three_ops_form
16369 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
16370 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
16371 /* Because neon_select_shape makes the second operand a copy of the first
16372 if the second operand is not present. */
16374 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16377 else if (rs != NS_QQI
16378 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16379 first_error (BAD_FPU);
16381 struct neon_type_el et;
16382 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16383 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
16385 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
16388 if (et.type == NT_invtype)
16390 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
16395 if (three_ops_form)
16396 constraint (inst.operands[0].reg != inst.operands[1].reg,
16397 _("first and second operands shall be the same register"));
16399 NEON_ENCODE (IMMED, inst);
16401 immbits = inst.operands[immoperand].imm;
16404 /* .i64 is a pseudo-op, so the immediate must be a repeating
16406 if (immbits != (inst.operands[immoperand].regisimm ?
16407 inst.operands[immoperand].reg : 0))
16409 /* Set immbits to an invalid constant. */
16410 immbits = 0xdeadbeef;
16417 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16421 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16425 /* Pseudo-instruction for VBIC. */
16426 neon_invert_size (&immbits, 0, et.size);
16427 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16431 /* Pseudo-instruction for VORR. */
16432 neon_invert_size (&immbits, 0, et.size);
16433 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16443 inst.instruction |= neon_quad (rs) << 6;
16444 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16445 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16446 inst.instruction |= cmode << 8;
16447 neon_write_immbits (immbits);
16449 neon_dp_fixup (&inst);
16454 do_neon_bitfield (void)
16456 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16457 neon_check_type (3, rs, N_IGNORE_TYPE);
16458 neon_three_same (neon_quad (rs), 0, -1);
16462 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
16465 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16466 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
16468 if (et.type == NT_float)
16470 NEON_ENCODE (FLOAT, inst);
16472 mve_encode_qqr (et.size, 0, 1);
16474 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
16478 NEON_ENCODE (INTEGER, inst);
16480 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
16482 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
16488 do_neon_dyadic_if_su_d (void)
16490 /* This version only allow D registers, but that constraint is enforced during
16491 operand parsing so we don't need to do anything extra here. */
16492 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
16496 do_neon_dyadic_if_i_d (void)
16498 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16499 affected if we specify unsigned args. */
16500 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
16504 do_mve_vstr_vldr_QI (int size, int elsize, int load)
16506 constraint (size < 32, BAD_ADDR_MODE);
16507 constraint (size != elsize, BAD_EL_TYPE);
16508 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16509 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
16510 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
16511 _("destination register and offset register may not be the"
16514 int imm = inst.relocs[0].exp.X_add_number;
16521 constraint ((imm % (size / 8) != 0)
16522 || imm > (0x7f << neon_logbits (size)),
16523 (size == 32) ? _("immediate must be a multiple of 4 in the"
16524 " range of +/-[0,508]")
16525 : _("immediate must be a multiple of 8 in the"
16526 " range of +/-[0,1016]"));
16527 inst.instruction |= 0x11 << 24;
16528 inst.instruction |= add << 23;
16529 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16530 inst.instruction |= inst.operands[1].writeback << 21;
16531 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16532 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16533 inst.instruction |= 1 << 12;
16534 inst.instruction |= (size == 64) << 8;
16535 inst.instruction &= 0xffffff00;
16536 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16537 inst.instruction |= imm >> neon_logbits (size);
16541 do_mve_vstr_vldr_RQ (int size, int elsize, int load)
16543 unsigned os = inst.operands[1].imm >> 5;
16544 constraint (os != 0 && size == 8,
16545 _("can not shift offsets when accessing less than half-word"));
16546 constraint (os && os != neon_logbits (size),
16547 _("shift immediate must be 1, 2 or 3 for half-word, word"
16548 " or double-word accesses respectively"));
16549 if (inst.operands[1].reg == REG_PC)
16550 as_tsktsk (MVE_BAD_PC);
16555 constraint (elsize >= 64, BAD_EL_TYPE);
16558 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16562 constraint (elsize != size, BAD_EL_TYPE);
16567 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
16571 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
16572 _("destination register and offset register may not be"
16574 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
16576 constraint (inst.vectype.el[0].type != NT_unsigned
16577 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
16578 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
16582 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
16585 inst.instruction |= 1 << 23;
16586 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16587 inst.instruction |= inst.operands[1].reg << 16;
16588 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16589 inst.instruction |= neon_logbits (elsize) << 7;
16590 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
16591 inst.instruction |= LOW4 (inst.operands[1].imm);
16592 inst.instruction |= !!os;
16596 do_mve_vstr_vldr_RI (int size, int elsize, int load)
16598 enum neon_el_type type = inst.vectype.el[0].type;
16600 constraint (size >= 64, BAD_ADDR_MODE);
16604 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16607 constraint (elsize != size, BAD_EL_TYPE);
16614 constraint (elsize != size && type != NT_unsigned
16615 && type != NT_signed, BAD_EL_TYPE);
16619 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
16622 int imm = inst.relocs[0].exp.X_add_number;
16630 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
16635 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16638 constraint (1, _("immediate must be a multiple of 2 in the"
16639 " range of +/-[0,254]"));
16642 constraint (1, _("immediate must be a multiple of 4 in the"
16643 " range of +/-[0,508]"));
16648 if (size != elsize)
16650 constraint (inst.operands[1].reg > 7, BAD_HIREG);
16651 constraint (inst.operands[0].reg > 14,
16652 _("MVE vector register in the range [Q0..Q7] expected"));
16653 inst.instruction |= (load && type == NT_unsigned) << 28;
16654 inst.instruction |= (size == 16) << 19;
16655 inst.instruction |= neon_logbits (elsize) << 7;
16659 if (inst.operands[1].reg == REG_PC)
16660 as_tsktsk (MVE_BAD_PC);
16661 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
16662 as_tsktsk (MVE_BAD_SP);
16663 inst.instruction |= 1 << 12;
16664 inst.instruction |= neon_logbits (size) << 7;
16666 inst.instruction |= inst.operands[1].preind << 24;
16667 inst.instruction |= add << 23;
16668 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16669 inst.instruction |= inst.operands[1].writeback << 21;
16670 inst.instruction |= inst.operands[1].reg << 16;
16671 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16672 inst.instruction &= 0xffffff80;
16673 inst.instruction |= imm >> neon_logbits (size);
16678 do_mve_vstr_vldr (void)
16683 if (inst.cond > COND_ALWAYS)
16684 inst.pred_insn_type = INSIDE_VPT_INSN;
16686 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16688 switch (inst.instruction)
16695 /* fall through. */
16701 /* fall through. */
16707 /* fall through. */
16713 /* fall through. */
16718 unsigned elsize = inst.vectype.el[0].size;
16720 if (inst.operands[1].isquad)
16722 /* We are dealing with [Q, imm]{!} cases. */
16723 do_mve_vstr_vldr_QI (size, elsize, load);
16727 if (inst.operands[1].immisreg == 2)
16729 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16730 do_mve_vstr_vldr_RQ (size, elsize, load);
16732 else if (!inst.operands[1].immisreg)
16734 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16735 do_mve_vstr_vldr_RI (size, elsize, load);
16738 constraint (1, BAD_ADDR_MODE);
16745 do_mve_vst_vld (void)
16747 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16750 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
16751 || inst.relocs[0].exp.X_add_number != 0
16752 || inst.operands[1].immisreg != 0,
16754 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
16755 if (inst.operands[1].reg == REG_PC)
16756 as_tsktsk (MVE_BAD_PC);
16757 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
16758 as_tsktsk (MVE_BAD_SP);
16761 /* These instructions are one of the "exceptions" mentioned in
16762 handle_pred_state. They are MVE instructions that are not VPT compatible
16763 and do not accept a VPT code, thus appending such a code is a syntax
16765 if (inst.cond > COND_ALWAYS)
16766 first_error (BAD_SYNTAX);
16767 /* If we append a scalar condition code we can set this to
16768 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16769 else if (inst.cond < COND_ALWAYS)
16770 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16772 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
16774 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16775 inst.instruction |= inst.operands[1].writeback << 21;
16776 inst.instruction |= inst.operands[1].reg << 16;
16777 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16778 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
16783 do_mve_vaddlv (void)
16785 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
16786 struct neon_type_el et
16787 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
16789 if (et.type == NT_invtype)
16790 first_error (BAD_EL_TYPE);
16792 if (inst.cond > COND_ALWAYS)
16793 inst.pred_insn_type = INSIDE_VPT_INSN;
16795 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16797 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16799 inst.instruction |= (et.type == NT_unsigned) << 28;
16800 inst.instruction |= inst.operands[1].reg << 19;
16801 inst.instruction |= inst.operands[0].reg << 12;
16802 inst.instruction |= inst.operands[2].reg;
16807 do_neon_dyadic_if_su (void)
16809 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16810 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
16813 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
16814 || inst.instruction == ((unsigned) N_MNEM_vmin))
16815 && et.type == NT_float
16816 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
16818 if (check_simd_pred_availability (et.type == NT_float,
16819 NEON_CHECK_ARCH | NEON_CHECK_CC))
16822 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
16826 do_neon_addsub_if_i (void)
16828 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
16829 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
16832 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16833 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
16834 N_EQK, N_IF_32 | N_I64 | N_KEY);
16836 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
16837 /* If we are parsing Q registers and the element types match MVE, which NEON
16838 also supports, then we must check whether this is an instruction that can
16839 be used by both MVE/NEON. This distinction can be made based on whether
16840 they are predicated or not. */
16841 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
16843 if (check_simd_pred_availability (et.type == NT_float,
16844 NEON_CHECK_ARCH | NEON_CHECK_CC))
16849 /* If they are either in a D register or are using an unsupported. */
16851 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16855 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16856 affected if we specify unsigned args. */
16857 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
16860 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16862 V<op> A,B (A is operand 0, B is operand 2)
16867 so handle that case specially. */
16870 neon_exchange_operands (void)
16872 if (inst.operands[1].present)
16874 void *scratch = xmalloc (sizeof (inst.operands[0]));
16876 /* Swap operands[1] and operands[2]. */
16877 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
16878 inst.operands[1] = inst.operands[2];
16879 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
16884 inst.operands[1] = inst.operands[2];
16885 inst.operands[2] = inst.operands[0];
16890 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
16892 if (inst.operands[2].isreg)
16895 neon_exchange_operands ();
16896 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
16900 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16901 struct neon_type_el et = neon_check_type (2, rs,
16902 N_EQK | N_SIZ, immtypes | N_KEY);
16904 NEON_ENCODE (IMMED, inst);
16905 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16906 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16907 inst.instruction |= LOW4 (inst.operands[1].reg);
16908 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16909 inst.instruction |= neon_quad (rs) << 6;
16910 inst.instruction |= (et.type == NT_float) << 10;
16911 inst.instruction |= neon_logbits (et.size) << 18;
16913 neon_dp_fixup (&inst);
16920 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
16924 do_neon_cmp_inv (void)
16926 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
16932 neon_compare (N_IF_32, N_IF_32, FALSE);
16935 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16936 scalars, which are encoded in 5 bits, M : Rm.
16937 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16938 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16941 Dot Product instructions are similar to multiply instructions except elsize
16942 should always be 32.
16944 This function translates SCALAR, which is GAS's internal encoding of indexed
16945 scalar register, to raw encoding. There is also register and index range
16946 check based on ELSIZE. */
16949 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
16951 unsigned regno = NEON_SCALAR_REG (scalar);
16952 unsigned elno = NEON_SCALAR_INDEX (scalar);
16957 if (regno > 7 || elno > 3)
16959 return regno | (elno << 3);
16962 if (regno > 15 || elno > 1)
16964 return regno | (elno << 4);
16968 first_error (_("scalar out of range for multiply instruction"));
16974 /* Encode multiply / multiply-accumulate scalar instructions. */
16977 neon_mul_mac (struct neon_type_el et, int ubit)
16981 /* Give a more helpful error message if we have an invalid type. */
16982 if (et.type == NT_invtype)
16985 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
16986 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16987 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16988 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16989 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16990 inst.instruction |= LOW4 (scalar);
16991 inst.instruction |= HI1 (scalar) << 5;
16992 inst.instruction |= (et.type == NT_float) << 8;
16993 inst.instruction |= neon_logbits (et.size) << 20;
16994 inst.instruction |= (ubit != 0) << 24;
16996 neon_dp_fixup (&inst);
17000 do_neon_mac_maybe_scalar (void)
17002 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17005 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
17008 if (inst.operands[2].isscalar)
17010 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17011 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17012 struct neon_type_el et = neon_check_type (3, rs,
17013 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
17014 NEON_ENCODE (SCALAR, inst);
17015 neon_mul_mac (et, neon_quad (rs));
17017 else if (!inst.operands[2].isvec)
17019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17021 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17022 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17024 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17028 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17029 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17030 affected if we specify unsigned args. */
17031 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17036 do_neon_fmac (void)
17038 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17039 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
17042 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
17045 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17047 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17048 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17053 if (inst.operands[2].reg == REG_SP)
17054 as_tsktsk (MVE_BAD_SP);
17055 else if (inst.operands[2].reg == REG_PC)
17056 as_tsktsk (MVE_BAD_PC);
17058 inst.instruction = 0xee310e40;
17059 inst.instruction |= (et.size == 16) << 28;
17060 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17061 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17062 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17063 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17064 inst.instruction |= inst.operands[2].reg;
17071 constraint (!inst.operands[2].isvec, BAD_FPU);
17074 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17080 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17081 struct neon_type_el et = neon_check_type (3, rs,
17082 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17083 neon_three_same (neon_quad (rs), 0, et.size);
17086 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17087 same types as the MAC equivalents. The polynomial type for this instruction
17088 is encoded the same as the integer type. */
17093 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17096 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
17099 if (inst.operands[2].isscalar)
17101 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17102 do_neon_mac_maybe_scalar ();
17106 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17108 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17109 struct neon_type_el et
17110 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
17111 if (et.type == NT_float)
17112 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
17115 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
17119 constraint (!inst.operands[2].isvec, BAD_FPU);
17120 neon_dyadic_misc (NT_poly,
17121 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17127 do_neon_qdmulh (void)
17129 if (inst.operands[2].isscalar)
17131 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17132 struct neon_type_el et = neon_check_type (3, rs,
17133 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17134 NEON_ENCODE (SCALAR, inst);
17135 neon_mul_mac (et, neon_quad (rs));
17139 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17140 struct neon_type_el et = neon_check_type (3, rs,
17141 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17142 NEON_ENCODE (INTEGER, inst);
17143 /* The U bit (rounding) comes from bit mask. */
17144 neon_three_same (neon_quad (rs), 0, et.size);
17149 do_mve_vaddv (void)
17151 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17152 struct neon_type_el et
17153 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17155 if (et.type == NT_invtype)
17156 first_error (BAD_EL_TYPE);
17158 if (inst.cond > COND_ALWAYS)
17159 inst.pred_insn_type = INSIDE_VPT_INSN;
17161 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17163 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17165 mve_encode_rq (et.type == NT_unsigned, et.size);
17169 do_mve_vhcadd (void)
17171 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17172 struct neon_type_el et
17173 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17175 if (inst.cond > COND_ALWAYS)
17176 inst.pred_insn_type = INSIDE_VPT_INSN;
17178 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17180 unsigned rot = inst.relocs[0].exp.X_add_number;
17181 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17183 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17184 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17185 "operand makes instruction UNPREDICTABLE"));
17187 mve_encode_qqq (0, et.size);
17188 inst.instruction |= (rot == 270) << 12;
17195 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17196 struct neon_type_el et
17197 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17199 if (et.type == NT_invtype)
17200 first_error (BAD_EL_TYPE);
17202 if (inst.cond > COND_ALWAYS)
17203 inst.pred_insn_type = INSIDE_VPT_INSN;
17205 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17207 mve_encode_qqq (0, 64);
17211 do_mve_vbrsr (void)
17213 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17214 struct neon_type_el et
17215 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17217 if (inst.cond > COND_ALWAYS)
17218 inst.pred_insn_type = INSIDE_VPT_INSN;
17220 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17222 mve_encode_qqr (et.size, 0, 0);
17228 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
17230 if (inst.cond > COND_ALWAYS)
17231 inst.pred_insn_type = INSIDE_VPT_INSN;
17233 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17235 mve_encode_qqq (1, 64);
17239 do_mve_vmull (void)
17242 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
17243 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
17244 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
17245 && inst.cond == COND_ALWAYS
17246 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
17251 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17252 N_SUF_32 | N_F64 | N_P8
17253 | N_P16 | N_I_MVE | N_KEY);
17254 if (((et.type == NT_poly) && et.size == 8
17255 && ARM_CPU_IS_ANY (cpu_variant))
17256 || (et.type == NT_integer) || (et.type == NT_float))
17263 constraint (rs != NS_QQQ, BAD_FPU);
17264 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17265 N_SU_32 | N_P8 | N_P16 | N_KEY);
17267 /* We are dealing with MVE's vmullt. */
17269 && (inst.operands[0].reg == inst.operands[1].reg
17270 || inst.operands[0].reg == inst.operands[2].reg))
17271 as_tsktsk (BAD_MVE_SRCDEST);
17273 if (inst.cond > COND_ALWAYS)
17274 inst.pred_insn_type = INSIDE_VPT_INSN;
17276 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17278 if (et.type == NT_poly)
17279 mve_encode_qqq (neon_logbits (et.size), 64);
17281 mve_encode_qqq (et.type == NT_unsigned, et.size);
17286 inst.instruction = N_MNEM_vmul;
17289 inst.pred_insn_type = INSIDE_IT_INSN;
17294 do_mve_vabav (void)
17296 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17301 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17304 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
17305 | N_S16 | N_S32 | N_U8 | N_U16
17308 if (inst.cond > COND_ALWAYS)
17309 inst.pred_insn_type = INSIDE_VPT_INSN;
17311 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17313 mve_encode_rqq (et.type == NT_unsigned, et.size);
17317 do_mve_vmladav (void)
17319 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17320 struct neon_type_el et = neon_check_type (3, rs,
17321 N_EQK, N_EQK, N_SU_MVE | N_KEY);
17323 if (et.type == NT_unsigned
17324 && (inst.instruction == M_MNEM_vmladavx
17325 || inst.instruction == M_MNEM_vmladavax
17326 || inst.instruction == M_MNEM_vmlsdav
17327 || inst.instruction == M_MNEM_vmlsdava
17328 || inst.instruction == M_MNEM_vmlsdavx
17329 || inst.instruction == M_MNEM_vmlsdavax))
17330 first_error (BAD_SIMD_TYPE);
17332 constraint (inst.operands[2].reg > 14,
17333 _("MVE vector register in the range [Q0..Q7] expected"));
17335 if (inst.cond > COND_ALWAYS)
17336 inst.pred_insn_type = INSIDE_VPT_INSN;
17338 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17340 if (inst.instruction == M_MNEM_vmlsdav
17341 || inst.instruction == M_MNEM_vmlsdava
17342 || inst.instruction == M_MNEM_vmlsdavx
17343 || inst.instruction == M_MNEM_vmlsdavax)
17344 inst.instruction |= (et.size == 8) << 28;
17346 inst.instruction |= (et.size == 8) << 8;
17348 mve_encode_rqq (et.type == NT_unsigned, 64);
17349 inst.instruction |= (et.size == 32) << 16;
17353 do_mve_vmlaldav (void)
17355 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
17356 struct neon_type_el et
17357 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
17358 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
17360 if (et.type == NT_unsigned
17361 && (inst.instruction == M_MNEM_vmlsldav
17362 || inst.instruction == M_MNEM_vmlsldava
17363 || inst.instruction == M_MNEM_vmlsldavx
17364 || inst.instruction == M_MNEM_vmlsldavax))
17365 first_error (BAD_SIMD_TYPE);
17367 if (inst.cond > COND_ALWAYS)
17368 inst.pred_insn_type = INSIDE_VPT_INSN;
17370 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17372 mve_encode_rrqq (et.type == NT_unsigned, et.size);
17376 do_mve_vrmlaldavh (void)
17378 struct neon_type_el et;
17379 if (inst.instruction == M_MNEM_vrmlsldavh
17380 || inst.instruction == M_MNEM_vrmlsldavha
17381 || inst.instruction == M_MNEM_vrmlsldavhx
17382 || inst.instruction == M_MNEM_vrmlsldavhax)
17384 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17385 if (inst.operands[1].reg == REG_SP)
17386 as_tsktsk (MVE_BAD_SP);
17390 if (inst.instruction == M_MNEM_vrmlaldavhx
17391 || inst.instruction == M_MNEM_vrmlaldavhax)
17392 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17394 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
17395 N_U32 | N_S32 | N_KEY);
17396 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17397 with vmax/min instructions, making the use of SP in assembly really
17398 nonsensical, so instead of issuing a warning like we do for other uses
17399 of SP for the odd register operand we error out. */
17400 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
17403 /* Make sure we still check the second operand is an odd one and that PC is
17404 disallowed. This because we are parsing for any GPR operand, to be able
17405 to distinguish between giving a warning or an error for SP as described
17407 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
17408 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
17410 if (inst.cond > COND_ALWAYS)
17411 inst.pred_insn_type = INSIDE_VPT_INSN;
17413 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17415 mve_encode_rrqq (et.type == NT_unsigned, 0);
17420 do_mve_vmaxnmv (void)
17422 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17423 struct neon_type_el et
17424 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
17426 if (inst.cond > COND_ALWAYS)
17427 inst.pred_insn_type = INSIDE_VPT_INSN;
17429 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17431 if (inst.operands[0].reg == REG_SP)
17432 as_tsktsk (MVE_BAD_SP);
17433 else if (inst.operands[0].reg == REG_PC)
17434 as_tsktsk (MVE_BAD_PC);
17436 mve_encode_rq (et.size == 16, 64);
17440 do_mve_vmaxv (void)
17442 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17443 struct neon_type_el et;
17445 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
17446 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
17448 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17450 if (inst.cond > COND_ALWAYS)
17451 inst.pred_insn_type = INSIDE_VPT_INSN;
17453 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17455 if (inst.operands[0].reg == REG_SP)
17456 as_tsktsk (MVE_BAD_SP);
17457 else if (inst.operands[0].reg == REG_PC)
17458 as_tsktsk (MVE_BAD_PC);
17460 mve_encode_rq (et.type == NT_unsigned, et.size);
17465 do_neon_qrdmlah (void)
17467 /* Check we're on the correct architecture. */
17468 if (!mark_feature_used (&fpu_neon_ext_armv8))
17470 _("instruction form not available on this architecture.");
17471 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
17473 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17474 record_feature_use (&fpu_neon_ext_v8_1);
17477 if (inst.operands[2].isscalar)
17479 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17480 struct neon_type_el et = neon_check_type (3, rs,
17481 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17482 NEON_ENCODE (SCALAR, inst);
17483 neon_mul_mac (et, neon_quad (rs));
17487 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17488 struct neon_type_el et = neon_check_type (3, rs,
17489 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17490 NEON_ENCODE (INTEGER, inst);
17491 /* The U bit (rounding) comes from bit mask. */
17492 neon_three_same (neon_quad (rs), 0, et.size);
17497 do_neon_fcmp_absolute (void)
17499 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17500 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17501 N_F_16_32 | N_KEY);
17502 /* Size field comes from bit mask. */
17503 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
17507 do_neon_fcmp_absolute_inv (void)
17509 neon_exchange_operands ();
17510 do_neon_fcmp_absolute ();
17514 do_neon_step (void)
17516 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17517 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17518 N_F_16_32 | N_KEY);
17519 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
17523 do_neon_abs_neg (void)
17525 enum neon_shape rs;
17526 struct neon_type_el et;
17528 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
17531 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
17532 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
17534 if (check_simd_pred_availability (et.type == NT_float,
17535 NEON_CHECK_ARCH | NEON_CHECK_CC))
17538 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17539 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17540 inst.instruction |= LOW4 (inst.operands[1].reg);
17541 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17542 inst.instruction |= neon_quad (rs) << 6;
17543 inst.instruction |= (et.type == NT_float) << 10;
17544 inst.instruction |= neon_logbits (et.size) << 18;
17546 neon_dp_fixup (&inst);
17552 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17553 struct neon_type_el et = neon_check_type (2, rs,
17554 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
17555 int imm = inst.operands[2].imm;
17556 constraint (imm < 0 || (unsigned)imm >= et.size,
17557 _("immediate out of range for insert"));
17558 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
17564 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17565 struct neon_type_el et = neon_check_type (2, rs,
17566 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
17567 int imm = inst.operands[2].imm;
17568 constraint (imm < 1 || (unsigned)imm > et.size,
17569 _("immediate out of range for insert"));
17570 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
17574 do_neon_qshlu_imm (void)
17576 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17577 struct neon_type_el et = neon_check_type (2, rs,
17578 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
17579 int imm = inst.operands[2].imm;
17580 constraint (imm < 0 || (unsigned)imm >= et.size,
17581 _("immediate out of range for shift"));
17582 /* Only encodes the 'U present' variant of the instruction.
17583 In this case, signed types have OP (bit 8) set to 0.
17584 Unsigned types have OP set to 1. */
17585 inst.instruction |= (et.type == NT_unsigned) << 8;
17586 /* The rest of the bits are the same as other immediate shifts. */
17587 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
17591 do_neon_qmovn (void)
17593 struct neon_type_el et = neon_check_type (2, NS_DQ,
17594 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
17595 /* Saturating move where operands can be signed or unsigned, and the
17596 destination has the same signedness. */
17597 NEON_ENCODE (INTEGER, inst);
17598 if (et.type == NT_unsigned)
17599 inst.instruction |= 0xc0;
17601 inst.instruction |= 0x80;
17602 neon_two_same (0, 1, et.size / 2);
17606 do_neon_qmovun (void)
17608 struct neon_type_el et = neon_check_type (2, NS_DQ,
17609 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
17610 /* Saturating move with unsigned results. Operands must be signed. */
17611 NEON_ENCODE (INTEGER, inst);
17612 neon_two_same (0, 1, et.size / 2);
17616 do_neon_rshift_sat_narrow (void)
17618 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17619 or unsigned. If operands are unsigned, results must also be unsigned. */
17620 struct neon_type_el et = neon_check_type (2, NS_DQI,
17621 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
17622 int imm = inst.operands[2].imm;
17623 /* This gets the bounds check, size encoding and immediate bits calculation
17627 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17628 VQMOVN.I<size> <Dd>, <Qm>. */
17631 inst.operands[2].present = 0;
17632 inst.instruction = N_MNEM_vqmovn;
17637 constraint (imm < 1 || (unsigned)imm > et.size,
17638 _("immediate out of range"));
17639 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
17643 do_neon_rshift_sat_narrow_u (void)
17645 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17646 or unsigned. If operands are unsigned, results must also be unsigned. */
17647 struct neon_type_el et = neon_check_type (2, NS_DQI,
17648 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
17649 int imm = inst.operands[2].imm;
17650 /* This gets the bounds check, size encoding and immediate bits calculation
17654 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17655 VQMOVUN.I<size> <Dd>, <Qm>. */
17658 inst.operands[2].present = 0;
17659 inst.instruction = N_MNEM_vqmovun;
17664 constraint (imm < 1 || (unsigned)imm > et.size,
17665 _("immediate out of range"));
17666 /* FIXME: The manual is kind of unclear about what value U should have in
17667 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17669 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
17673 do_neon_movn (void)
17675 struct neon_type_el et = neon_check_type (2, NS_DQ,
17676 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
17677 NEON_ENCODE (INTEGER, inst);
17678 neon_two_same (0, 1, et.size / 2);
17682 do_neon_rshift_narrow (void)
17684 struct neon_type_el et = neon_check_type (2, NS_DQI,
17685 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
17686 int imm = inst.operands[2].imm;
17687 /* This gets the bounds check, size encoding and immediate bits calculation
17691 /* If immediate is zero then we are a pseudo-instruction for
17692 VMOVN.I<size> <Dd>, <Qm> */
17695 inst.operands[2].present = 0;
17696 inst.instruction = N_MNEM_vmovn;
17701 constraint (imm < 1 || (unsigned)imm > et.size,
17702 _("immediate out of range for narrowing operation"));
17703 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
17707 do_neon_shll (void)
17709 /* FIXME: Type checking when lengthening. */
17710 struct neon_type_el et = neon_check_type (2, NS_QDI,
17711 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
17712 unsigned imm = inst.operands[2].imm;
17714 if (imm == et.size)
17716 /* Maximum shift variant. */
17717 NEON_ENCODE (INTEGER, inst);
17718 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17719 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17720 inst.instruction |= LOW4 (inst.operands[1].reg);
17721 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17722 inst.instruction |= neon_logbits (et.size) << 18;
17724 neon_dp_fixup (&inst);
17728 /* A more-specific type check for non-max versions. */
17729 et = neon_check_type (2, NS_QDI,
17730 N_EQK | N_DBL, N_SU_32 | N_KEY);
17731 NEON_ENCODE (IMMED, inst);
17732 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
17736 /* Check the various types for the VCVT instruction, and return which version
17737 the current instruction is. */
17739 #define CVT_FLAVOUR_VAR \
17740 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17741 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17742 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17743 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17744 /* Half-precision conversions. */ \
17745 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17746 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17747 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17748 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17749 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17750 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17751 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17752 Compared with single/double precision variants, only the co-processor \
17753 field is different, so the encoding flow is reused here. */ \
17754 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17755 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17756 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17757 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17758 /* VFP instructions. */ \
17759 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17760 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17761 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17762 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17763 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17764 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17765 /* VFP instructions with bitshift. */ \
17766 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17767 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17768 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17769 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17770 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17771 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17772 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17773 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17775 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17776 neon_cvt_flavour_##C,
17778 /* The different types of conversions we can do. */
17779 enum neon_cvt_flavour
17782 neon_cvt_flavour_invalid,
17783 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
17788 static enum neon_cvt_flavour
17789 get_neon_cvt_flavour (enum neon_shape rs)
17791 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17792 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17793 if (et.type != NT_invtype) \
17795 inst.error = NULL; \
17796 return (neon_cvt_flavour_##C); \
17799 struct neon_type_el et;
17800 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
17801 || rs == NS_FF) ? N_VFP : 0;
17802 /* The instruction versions which take an immediate take one register
17803 argument, which is extended to the width of the full register. Thus the
17804 "source" and "destination" registers must have the same width. Hack that
17805 here by making the size equal to the key (wider, in this case) operand. */
17806 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
17810 return neon_cvt_flavour_invalid;
17825 /* Neon-syntax VFP conversions. */
17828 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
17830 const char *opname = 0;
17832 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
17833 || rs == NS_FHI || rs == NS_HFI)
17835 /* Conversions with immediate bitshift. */
17836 const char *enc[] =
17838 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17844 if (flavour < (int) ARRAY_SIZE (enc))
17846 opname = enc[flavour];
17847 constraint (inst.operands[0].reg != inst.operands[1].reg,
17848 _("operands 0 and 1 must be the same register"));
17849 inst.operands[1] = inst.operands[2];
17850 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
17855 /* Conversions without bitshift. */
17856 const char *enc[] =
17858 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17864 if (flavour < (int) ARRAY_SIZE (enc))
17865 opname = enc[flavour];
17869 do_vfp_nsyn_opcode (opname);
17871 /* ARMv8.2 fp16 VCVT instruction. */
17872 if (flavour == neon_cvt_flavour_s32_f16
17873 || flavour == neon_cvt_flavour_u32_f16
17874 || flavour == neon_cvt_flavour_f16_u32
17875 || flavour == neon_cvt_flavour_f16_s32)
17876 do_scalar_fp16_v82_encode ();
17880 do_vfp_nsyn_cvtz (void)
17882 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
17883 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
17884 const char *enc[] =
17886 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17892 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
17893 do_vfp_nsyn_opcode (enc[flavour]);
17897 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
17898 enum neon_cvt_mode mode)
17903 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17904 D register operands. */
17905 if (flavour == neon_cvt_flavour_s32_f64
17906 || flavour == neon_cvt_flavour_u32_f64)
17907 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17910 if (flavour == neon_cvt_flavour_s32_f16
17911 || flavour == neon_cvt_flavour_u32_f16)
17912 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
17915 set_pred_insn_type (OUTSIDE_PRED_INSN);
17919 case neon_cvt_flavour_s32_f64:
17923 case neon_cvt_flavour_s32_f32:
17927 case neon_cvt_flavour_s32_f16:
17931 case neon_cvt_flavour_u32_f64:
17935 case neon_cvt_flavour_u32_f32:
17939 case neon_cvt_flavour_u32_f16:
17944 first_error (_("invalid instruction shape"));
17950 case neon_cvt_mode_a: rm = 0; break;
17951 case neon_cvt_mode_n: rm = 1; break;
17952 case neon_cvt_mode_p: rm = 2; break;
17953 case neon_cvt_mode_m: rm = 3; break;
17954 default: first_error (_("invalid rounding mode")); return;
17957 NEON_ENCODE (FPV8, inst);
17958 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
17959 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
17960 inst.instruction |= sz << 8;
17962 /* ARMv8.2 fp16 VCVT instruction. */
17963 if (flavour == neon_cvt_flavour_s32_f16
17964 ||flavour == neon_cvt_flavour_u32_f16)
17965 do_scalar_fp16_v82_encode ();
17966 inst.instruction |= op << 7;
17967 inst.instruction |= rm << 16;
17968 inst.instruction |= 0xf0000000;
17969 inst.is_neon = TRUE;
17973 do_neon_cvt_1 (enum neon_cvt_mode mode)
17975 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
17976 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
17977 NS_FH, NS_HF, NS_FHI, NS_HFI,
17979 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
17981 if (flavour == neon_cvt_flavour_invalid)
17984 /* PR11109: Handle round-to-zero for VCVT conversions. */
17985 if (mode == neon_cvt_mode_z
17986 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
17987 && (flavour == neon_cvt_flavour_s16_f16
17988 || flavour == neon_cvt_flavour_u16_f16
17989 || flavour == neon_cvt_flavour_s32_f32
17990 || flavour == neon_cvt_flavour_u32_f32
17991 || flavour == neon_cvt_flavour_s32_f64
17992 || flavour == neon_cvt_flavour_u32_f64)
17993 && (rs == NS_FD || rs == NS_FF))
17995 do_vfp_nsyn_cvtz ();
17999 /* ARMv8.2 fp16 VCVT conversions. */
18000 if (mode == neon_cvt_mode_z
18001 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
18002 && (flavour == neon_cvt_flavour_s32_f16
18003 || flavour == neon_cvt_flavour_u32_f16)
18006 do_vfp_nsyn_cvtz ();
18007 do_scalar_fp16_v82_encode ();
18011 /* VFP rather than Neon conversions. */
18012 if (flavour >= neon_cvt_flavour_first_fp)
18014 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18015 do_vfp_nsyn_cvt (rs, flavour);
18017 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18025 if (mode == neon_cvt_mode_z
18026 && (flavour == neon_cvt_flavour_f16_s16
18027 || flavour == neon_cvt_flavour_f16_u16
18028 || flavour == neon_cvt_flavour_s16_f16
18029 || flavour == neon_cvt_flavour_u16_f16
18030 || flavour == neon_cvt_flavour_f32_u32
18031 || flavour == neon_cvt_flavour_f32_s32
18032 || flavour == neon_cvt_flavour_s32_f32
18033 || flavour == neon_cvt_flavour_u32_f32))
18035 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
18038 else if (mode == neon_cvt_mode_n)
18040 /* We are dealing with vcvt with the 'ne' condition. */
18042 inst.instruction = N_MNEM_vcvt;
18043 do_neon_cvt_1 (neon_cvt_mode_z);
18046 /* fall through. */
18050 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18051 0x0000100, 0x1000100, 0x0, 0x1000000};
18053 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18054 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18057 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18059 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18060 _("immediate value out of range"));
18063 case neon_cvt_flavour_f16_s16:
18064 case neon_cvt_flavour_f16_u16:
18065 case neon_cvt_flavour_s16_f16:
18066 case neon_cvt_flavour_u16_f16:
18067 constraint (inst.operands[2].imm > 16,
18068 _("immediate value out of range"));
18070 case neon_cvt_flavour_f32_u32:
18071 case neon_cvt_flavour_f32_s32:
18072 case neon_cvt_flavour_s32_f32:
18073 case neon_cvt_flavour_u32_f32:
18074 constraint (inst.operands[2].imm > 32,
18075 _("immediate value out of range"));
18078 inst.error = BAD_FPU;
18083 /* Fixed-point conversion with #0 immediate is encoded as an
18084 integer conversion. */
18085 if (inst.operands[2].present && inst.operands[2].imm == 0)
18087 NEON_ENCODE (IMMED, inst);
18088 if (flavour != neon_cvt_flavour_invalid)
18089 inst.instruction |= enctab[flavour];
18090 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18091 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18092 inst.instruction |= LOW4 (inst.operands[1].reg);
18093 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18094 inst.instruction |= neon_quad (rs) << 6;
18095 inst.instruction |= 1 << 21;
18096 if (flavour < neon_cvt_flavour_s16_f16)
18098 inst.instruction |= 1 << 21;
18099 immbits = 32 - inst.operands[2].imm;
18100 inst.instruction |= immbits << 16;
18104 inst.instruction |= 3 << 20;
18105 immbits = 16 - inst.operands[2].imm;
18106 inst.instruction |= immbits << 16;
18107 inst.instruction &= ~(1 << 9);
18110 neon_dp_fixup (&inst);
18115 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
18116 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
18117 && (flavour == neon_cvt_flavour_s16_f16
18118 || flavour == neon_cvt_flavour_u16_f16
18119 || flavour == neon_cvt_flavour_s32_f32
18120 || flavour == neon_cvt_flavour_u32_f32))
18122 if (check_simd_pred_availability (1,
18123 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18126 else if (mode == neon_cvt_mode_z
18127 && (flavour == neon_cvt_flavour_f16_s16
18128 || flavour == neon_cvt_flavour_f16_u16
18129 || flavour == neon_cvt_flavour_s16_f16
18130 || flavour == neon_cvt_flavour_u16_f16
18131 || flavour == neon_cvt_flavour_f32_u32
18132 || flavour == neon_cvt_flavour_f32_s32
18133 || flavour == neon_cvt_flavour_s32_f32
18134 || flavour == neon_cvt_flavour_u32_f32))
18136 if (check_simd_pred_availability (1,
18137 NEON_CHECK_CC | NEON_CHECK_ARCH))
18140 /* fall through. */
18142 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
18145 NEON_ENCODE (FLOAT, inst);
18146 if (check_simd_pred_availability (1,
18147 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18150 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18151 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18152 inst.instruction |= LOW4 (inst.operands[1].reg);
18153 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18154 inst.instruction |= neon_quad (rs) << 6;
18155 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
18156 || flavour == neon_cvt_flavour_u32_f32) << 7;
18157 inst.instruction |= mode << 8;
18158 if (flavour == neon_cvt_flavour_u16_f16
18159 || flavour == neon_cvt_flavour_s16_f16)
18160 /* Mask off the original size bits and reencode them. */
18161 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
18164 inst.instruction |= 0xfc000000;
18166 inst.instruction |= 0xf0000000;
18172 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
18173 0x100, 0x180, 0x0, 0x080};
18175 NEON_ENCODE (INTEGER, inst);
18177 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18179 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18183 if (flavour != neon_cvt_flavour_invalid)
18184 inst.instruction |= enctab[flavour];
18186 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18187 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18188 inst.instruction |= LOW4 (inst.operands[1].reg);
18189 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18190 inst.instruction |= neon_quad (rs) << 6;
18191 if (flavour >= neon_cvt_flavour_s16_f16
18192 && flavour <= neon_cvt_flavour_f16_u16)
18193 /* Half precision. */
18194 inst.instruction |= 1 << 18;
18196 inst.instruction |= 2 << 18;
18198 neon_dp_fixup (&inst);
18203 /* Half-precision conversions for Advanced SIMD -- neon. */
18206 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18210 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
18212 as_bad (_("operand size must match register width"));
18217 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
18219 as_bad (_("operand size must match register width"));
18224 inst.instruction = 0x3b60600;
18226 inst.instruction = 0x3b60700;
18228 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18229 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18230 inst.instruction |= LOW4 (inst.operands[1].reg);
18231 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18232 neon_dp_fixup (&inst);
18236 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18237 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18238 do_vfp_nsyn_cvt (rs, flavour);
18240 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18245 do_neon_cvtr (void)
18247 do_neon_cvt_1 (neon_cvt_mode_x);
18253 do_neon_cvt_1 (neon_cvt_mode_z);
18257 do_neon_cvta (void)
18259 do_neon_cvt_1 (neon_cvt_mode_a);
18263 do_neon_cvtn (void)
18265 do_neon_cvt_1 (neon_cvt_mode_n);
18269 do_neon_cvtp (void)
18271 do_neon_cvt_1 (neon_cvt_mode_p);
18275 do_neon_cvtm (void)
18277 do_neon_cvt_1 (neon_cvt_mode_m);
18281 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
18284 mark_feature_used (&fpu_vfp_ext_armv8);
18286 encode_arm_vfp_reg (inst.operands[0].reg,
18287 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
18288 encode_arm_vfp_reg (inst.operands[1].reg,
18289 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
18290 inst.instruction |= to ? 0x10000 : 0;
18291 inst.instruction |= t ? 0x80 : 0;
18292 inst.instruction |= is_double ? 0x100 : 0;
18293 do_vfp_cond_or_thumb ();
18297 do_neon_cvttb_1 (bfd_boolean t)
18299 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
18300 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
18304 else if (rs == NS_QQ || rs == NS_QQI)
18306 int single_to_half = 0;
18307 if (check_simd_pred_availability (1, NEON_CHECK_ARCH))
18310 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18312 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18313 && (flavour == neon_cvt_flavour_u16_f16
18314 || flavour == neon_cvt_flavour_s16_f16
18315 || flavour == neon_cvt_flavour_f16_s16
18316 || flavour == neon_cvt_flavour_f16_u16
18317 || flavour == neon_cvt_flavour_u32_f32
18318 || flavour == neon_cvt_flavour_s32_f32
18319 || flavour == neon_cvt_flavour_f32_s32
18320 || flavour == neon_cvt_flavour_f32_u32))
18323 inst.instruction = N_MNEM_vcvt;
18324 set_pred_insn_type (INSIDE_VPT_INSN);
18325 do_neon_cvt_1 (neon_cvt_mode_z);
18328 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
18329 single_to_half = 1;
18330 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
18332 first_error (BAD_FPU);
18336 inst.instruction = 0xee3f0e01;
18337 inst.instruction |= single_to_half << 28;
18338 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18339 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
18340 inst.instruction |= t << 12;
18341 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18342 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
18345 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
18348 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
18350 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
18353 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
18355 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
18357 /* The VCVTB and VCVTT instructions with D-register operands
18358 don't work for SP only targets. */
18359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18363 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
18365 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
18367 /* The VCVTB and VCVTT instructions with D-register operands
18368 don't work for SP only targets. */
18369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18373 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
18380 do_neon_cvtb (void)
18382 do_neon_cvttb_1 (FALSE);
18387 do_neon_cvtt (void)
18389 do_neon_cvttb_1 (TRUE);
18393 neon_move_immediate (void)
18395 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
18396 struct neon_type_el et = neon_check_type (2, rs,
18397 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
18398 unsigned immlo, immhi = 0, immbits;
18399 int op, cmode, float_p;
18401 constraint (et.type == NT_invtype,
18402 _("operand size must be specified for immediate VMOV"));
18404 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18405 op = (inst.instruction & (1 << 5)) != 0;
18407 immlo = inst.operands[1].imm;
18408 if (inst.operands[1].regisimm)
18409 immhi = inst.operands[1].reg;
18411 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
18412 _("immediate has bits set outside the operand size"));
18414 float_p = inst.operands[1].immisfloat;
18416 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
18417 et.size, et.type)) == FAIL)
18419 /* Invert relevant bits only. */
18420 neon_invert_size (&immlo, &immhi, et.size);
18421 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18422 with one or the other; those cases are caught by
18423 neon_cmode_for_move_imm. */
18425 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
18426 &op, et.size, et.type)) == FAIL)
18428 first_error (_("immediate out of range"));
18433 inst.instruction &= ~(1 << 5);
18434 inst.instruction |= op << 5;
18436 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18437 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18438 inst.instruction |= neon_quad (rs) << 6;
18439 inst.instruction |= cmode << 8;
18441 neon_write_immbits (immbits);
18447 if (inst.operands[1].isreg)
18449 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18451 NEON_ENCODE (INTEGER, inst);
18452 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18453 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18454 inst.instruction |= LOW4 (inst.operands[1].reg);
18455 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18456 inst.instruction |= neon_quad (rs) << 6;
18460 NEON_ENCODE (IMMED, inst);
18461 neon_move_immediate ();
18464 neon_dp_fixup (&inst);
18467 /* Encode instructions of form:
18469 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18470 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18473 neon_mixed_length (struct neon_type_el et, unsigned size)
18475 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18476 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18477 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18478 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18479 inst.instruction |= LOW4 (inst.operands[2].reg);
18480 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
18481 inst.instruction |= (et.type == NT_unsigned) << 24;
18482 inst.instruction |= neon_logbits (size) << 20;
18484 neon_dp_fixup (&inst);
18488 do_neon_dyadic_long (void)
18490 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
18493 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
18496 NEON_ENCODE (INTEGER, inst);
18497 /* FIXME: Type checking for lengthening op. */
18498 struct neon_type_el et = neon_check_type (3, NS_QDD,
18499 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
18500 neon_mixed_length (et, et.size);
18502 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18503 && (inst.cond == 0xf || inst.cond == 0x10))
18505 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18506 in an IT block with le/lt conditions. */
18508 if (inst.cond == 0xf)
18510 else if (inst.cond == 0x10)
18513 inst.pred_insn_type = INSIDE_IT_INSN;
18515 if (inst.instruction == N_MNEM_vaddl)
18517 inst.instruction = N_MNEM_vadd;
18518 do_neon_addsub_if_i ();
18520 else if (inst.instruction == N_MNEM_vsubl)
18522 inst.instruction = N_MNEM_vsub;
18523 do_neon_addsub_if_i ();
18525 else if (inst.instruction == N_MNEM_vabdl)
18527 inst.instruction = N_MNEM_vabd;
18528 do_neon_dyadic_if_su ();
18532 first_error (BAD_FPU);
18536 do_neon_abal (void)
18538 struct neon_type_el et = neon_check_type (3, NS_QDD,
18539 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
18540 neon_mixed_length (et, et.size);
18544 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
18546 if (inst.operands[2].isscalar)
18548 struct neon_type_el et = neon_check_type (3, NS_QDS,
18549 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
18550 NEON_ENCODE (SCALAR, inst);
18551 neon_mul_mac (et, et.type == NT_unsigned);
18555 struct neon_type_el et = neon_check_type (3, NS_QDD,
18556 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
18557 NEON_ENCODE (INTEGER, inst);
18558 neon_mixed_length (et, et.size);
18563 do_neon_mac_maybe_scalar_long (void)
18565 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
18568 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18569 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18572 neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
18574 unsigned regno = NEON_SCALAR_REG (scalar);
18575 unsigned elno = NEON_SCALAR_INDEX (scalar);
18579 if (regno > 7 || elno > 3)
18582 return ((regno & 0x7)
18583 | ((elno & 0x1) << 3)
18584 | (((elno >> 1) & 0x1) << 5));
18588 if (regno > 15 || elno > 1)
18591 return (((regno & 0x1) << 5)
18592 | ((regno >> 1) & 0x7)
18593 | ((elno & 0x1) << 3));
18597 first_error (_("scalar out of range for multiply instruction"));
18602 do_neon_fmac_maybe_scalar_long (int subtype)
18604 enum neon_shape rs;
18606 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18607 field (bits[21:20]) has different meaning. For scalar index variant, it's
18608 used to differentiate add and subtract, otherwise it's with fixed value
18612 if (inst.cond != COND_ALWAYS)
18613 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18614 "behaviour is UNPREDICTABLE"));
18616 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
18619 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
18622 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18623 be a scalar index register. */
18624 if (inst.operands[2].isscalar)
18626 high8 = 0xfe000000;
18629 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
18633 high8 = 0xfc000000;
18636 inst.instruction |= (0x1 << 23);
18637 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
18640 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
18642 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18643 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18644 so we simply pass -1 as size. */
18645 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
18646 neon_three_same (quad_p, 0, size);
18648 /* Undo neon_dp_fixup. Redo the high eight bits. */
18649 inst.instruction &= 0x00ffffff;
18650 inst.instruction |= high8;
18652 #define LOW1(R) ((R) & 0x1)
18653 #define HI4(R) (((R) >> 1) & 0xf)
18654 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18655 whether the instruction is in Q form and whether Vm is a scalar indexed
18657 if (inst.operands[2].isscalar)
18660 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
18661 inst.instruction &= 0xffffffd0;
18662 inst.instruction |= rm;
18666 /* Redo Rn as well. */
18667 inst.instruction &= 0xfff0ff7f;
18668 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
18669 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
18674 /* Redo Rn and Rm. */
18675 inst.instruction &= 0xfff0ff50;
18676 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
18677 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
18678 inst.instruction |= HI4 (inst.operands[2].reg);
18679 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
18684 do_neon_vfmal (void)
18686 return do_neon_fmac_maybe_scalar_long (0);
18690 do_neon_vfmsl (void)
18692 return do_neon_fmac_maybe_scalar_long (1);
18696 do_neon_dyadic_wide (void)
18698 struct neon_type_el et = neon_check_type (3, NS_QQD,
18699 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
18700 neon_mixed_length (et, et.size);
18704 do_neon_dyadic_narrow (void)
18706 struct neon_type_el et = neon_check_type (3, NS_QDD,
18707 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
18708 /* Operand sign is unimportant, and the U bit is part of the opcode,
18709 so force the operand type to integer. */
18710 et.type = NT_integer;
18711 neon_mixed_length (et, et.size / 2);
18715 do_neon_mul_sat_scalar_long (void)
18717 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
18721 do_neon_vmull (void)
18723 if (inst.operands[2].isscalar)
18724 do_neon_mac_maybe_scalar_long ();
18727 struct neon_type_el et = neon_check_type (3, NS_QDD,
18728 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
18730 if (et.type == NT_poly)
18731 NEON_ENCODE (POLY, inst);
18733 NEON_ENCODE (INTEGER, inst);
18735 /* For polynomial encoding the U bit must be zero, and the size must
18736 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18737 obviously, as 0b10). */
18740 /* Check we're on the correct architecture. */
18741 if (!mark_feature_used (&fpu_crypto_ext_armv8))
18743 _("Instruction form not available on this architecture.");
18748 neon_mixed_length (et, et.size);
18755 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
18756 struct neon_type_el et = neon_check_type (3, rs,
18757 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18758 unsigned imm = (inst.operands[3].imm * et.size) / 8;
18760 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
18761 _("shift out of range"));
18762 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18763 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18764 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18765 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18766 inst.instruction |= LOW4 (inst.operands[2].reg);
18767 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
18768 inst.instruction |= neon_quad (rs) << 6;
18769 inst.instruction |= imm << 8;
18771 neon_dp_fixup (&inst);
18777 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18778 struct neon_type_el et = neon_check_type (2, rs,
18779 N_EQK, N_8 | N_16 | N_32 | N_KEY);
18780 unsigned op = (inst.instruction >> 7) & 3;
18781 /* N (width of reversed regions) is encoded as part of the bitmask. We
18782 extract it here to check the elements to be reversed are smaller.
18783 Otherwise we'd get a reserved instruction. */
18784 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
18785 gas_assert (elsize != 0);
18786 constraint (et.size >= elsize,
18787 _("elements must be smaller than reversal region"));
18788 neon_two_same (neon_quad (rs), 1, et.size);
18794 if (inst.operands[1].isscalar)
18796 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
18798 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
18799 struct neon_type_el et = neon_check_type (2, rs,
18800 N_EQK, N_8 | N_16 | N_32 | N_KEY);
18801 unsigned sizebits = et.size >> 3;
18802 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
18803 int logsize = neon_logbits (et.size);
18804 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
18806 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
18809 NEON_ENCODE (SCALAR, inst);
18810 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18811 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18812 inst.instruction |= LOW4 (dm);
18813 inst.instruction |= HI1 (dm) << 5;
18814 inst.instruction |= neon_quad (rs) << 6;
18815 inst.instruction |= x << 17;
18816 inst.instruction |= sizebits << 16;
18818 neon_dp_fixup (&inst);
18822 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
18823 struct neon_type_el et = neon_check_type (2, rs,
18824 N_8 | N_16 | N_32 | N_KEY, N_EQK);
18827 if (check_simd_pred_availability (0, NEON_CHECK_ARCH))
18831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
18834 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18836 if (inst.operands[1].reg == REG_SP)
18837 as_tsktsk (MVE_BAD_SP);
18838 else if (inst.operands[1].reg == REG_PC)
18839 as_tsktsk (MVE_BAD_PC);
18842 /* Duplicate ARM register to lanes of vector. */
18843 NEON_ENCODE (ARMREG, inst);
18846 case 8: inst.instruction |= 0x400000; break;
18847 case 16: inst.instruction |= 0x000020; break;
18848 case 32: inst.instruction |= 0x000000; break;
18851 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
18852 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
18853 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
18854 inst.instruction |= neon_quad (rs) << 21;
18855 /* The encoding for this instruction is identical for the ARM and Thumb
18856 variants, except for the condition field. */
18857 do_vfp_cond_or_thumb ();
18862 do_mve_mov (int toQ)
18864 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18866 if (inst.cond > COND_ALWAYS)
18867 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
18869 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
18878 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
18879 _("Index one must be [2,3] and index two must be two less than"
18881 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
18882 _("General purpose registers may not be the same"));
18883 constraint (inst.operands[Rt].reg == REG_SP
18884 || inst.operands[Rt2].reg == REG_SP,
18886 constraint (inst.operands[Rt].reg == REG_PC
18887 || inst.operands[Rt2].reg == REG_PC,
18890 inst.instruction = 0xec000f00;
18891 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
18892 inst.instruction |= !!toQ << 20;
18893 inst.instruction |= inst.operands[Rt2].reg << 16;
18894 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
18895 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
18896 inst.instruction |= inst.operands[Rt].reg;
18902 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18905 if (inst.cond > COND_ALWAYS)
18906 inst.pred_insn_type = INSIDE_VPT_INSN;
18908 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18910 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
18913 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18914 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
18915 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18916 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18917 inst.instruction |= LOW4 (inst.operands[1].reg);
18922 /* VMOV has particularly many variations. It can be one of:
18923 0. VMOV<c><q> <Qd>, <Qm>
18924 1. VMOV<c><q> <Dd>, <Dm>
18925 (Register operations, which are VORR with Rm = Rn.)
18926 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18927 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18929 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18930 (ARM register to scalar.)
18931 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18932 (Two ARM registers to vector.)
18933 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18934 (Scalar to ARM register.)
18935 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18936 (Vector to two ARM registers.)
18937 8. VMOV.F32 <Sd>, <Sm>
18938 9. VMOV.F64 <Dd>, <Dm>
18939 (VFP register moves.)
18940 10. VMOV.F32 <Sd>, #imm
18941 11. VMOV.F64 <Dd>, #imm
18942 (VFP float immediate load.)
18943 12. VMOV <Rd>, <Sm>
18944 (VFP single to ARM reg.)
18945 13. VMOV <Sd>, <Rm>
18946 (ARM reg to VFP single.)
18947 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18948 (Two ARM regs to two VFP singles.)
18949 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18950 (Two VFP singles to two ARM regs.)
18951 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18952 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18953 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18954 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18956 These cases can be disambiguated using neon_select_shape, except cases 1/9
18957 and 3/11 which depend on the operand type too.
18959 All the encoded bits are hardcoded by this function.
18961 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18962 Cases 5, 7 may be used with VFPv2 and above.
18964 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18965 can specify a type where it doesn't make sense to, and is ignored). */
18970 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
18971 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
18972 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
18973 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
18975 struct neon_type_el et;
18976 const char *ldconst = 0;
18980 case NS_DD: /* case 1/9. */
18981 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
18982 /* It is not an error here if no type is given. */
18984 if (et.type == NT_float && et.size == 64)
18986 do_vfp_nsyn_opcode ("fcpyd");
18989 /* fall through. */
18991 case NS_QQ: /* case 0/1. */
18993 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
18995 /* The architecture manual I have doesn't explicitly state which
18996 value the U bit should have for register->register moves, but
18997 the equivalent VORR instruction has U = 0, so do that. */
18998 inst.instruction = 0x0200110;
18999 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19000 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19001 inst.instruction |= LOW4 (inst.operands[1].reg);
19002 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19003 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19004 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19005 inst.instruction |= neon_quad (rs) << 6;
19007 neon_dp_fixup (&inst);
19011 case NS_DI: /* case 3/11. */
19012 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19014 if (et.type == NT_float && et.size == 64)
19016 /* case 11 (fconstd). */
19017 ldconst = "fconstd";
19018 goto encode_fconstd;
19020 /* fall through. */
19022 case NS_QI: /* case 2/3. */
19023 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
19025 inst.instruction = 0x0800010;
19026 neon_move_immediate ();
19027 neon_dp_fixup (&inst);
19030 case NS_SR: /* case 4. */
19032 unsigned bcdebits = 0;
19034 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19035 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
19037 /* .<size> is optional here, defaulting to .32. */
19038 if (inst.vectype.elems == 0
19039 && inst.operands[0].vectype.type == NT_invtype
19040 && inst.operands[1].vectype.type == NT_invtype)
19042 inst.vectype.el[0].type = NT_untyped;
19043 inst.vectype.el[0].size = 32;
19044 inst.vectype.elems = 1;
19047 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
19048 logsize = neon_logbits (et.size);
19052 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19053 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
19058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19059 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19063 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19065 if (inst.operands[1].reg == REG_SP)
19066 as_tsktsk (MVE_BAD_SP);
19067 else if (inst.operands[1].reg == REG_PC)
19068 as_tsktsk (MVE_BAD_PC);
19070 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19072 constraint (et.type == NT_invtype, _("bad type for scalar"));
19073 constraint (x >= size / et.size, _("scalar index out of range"));
19078 case 8: bcdebits = 0x8; break;
19079 case 16: bcdebits = 0x1; break;
19080 case 32: bcdebits = 0x0; break;
19084 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19086 inst.instruction = 0xe000b10;
19087 do_vfp_cond_or_thumb ();
19088 inst.instruction |= LOW4 (dn) << 16;
19089 inst.instruction |= HI1 (dn) << 7;
19090 inst.instruction |= inst.operands[1].reg << 12;
19091 inst.instruction |= (bcdebits & 3) << 5;
19092 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
19093 inst.instruction |= (x >> (3-logsize)) << 16;
19097 case NS_DRR: /* case 5 (fmdrr). */
19098 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19099 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19102 inst.instruction = 0xc400b10;
19103 do_vfp_cond_or_thumb ();
19104 inst.instruction |= LOW4 (inst.operands[0].reg);
19105 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
19106 inst.instruction |= inst.operands[1].reg << 12;
19107 inst.instruction |= inst.operands[2].reg << 16;
19110 case NS_RS: /* case 6. */
19113 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
19114 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
19115 unsigned abcdebits = 0;
19117 /* .<dt> is optional here, defaulting to .32. */
19118 if (inst.vectype.elems == 0
19119 && inst.operands[0].vectype.type == NT_invtype
19120 && inst.operands[1].vectype.type == NT_invtype)
19122 inst.vectype.el[0].type = NT_untyped;
19123 inst.vectype.el[0].size = 32;
19124 inst.vectype.elems = 1;
19127 et = neon_check_type (2, NS_NULL,
19128 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
19129 logsize = neon_logbits (et.size);
19133 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19134 && vfp_or_neon_is_neon (NEON_CHECK_CC
19135 | NEON_CHECK_ARCH) == FAIL)
19140 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19141 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19145 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19147 if (inst.operands[0].reg == REG_SP)
19148 as_tsktsk (MVE_BAD_SP);
19149 else if (inst.operands[0].reg == REG_PC)
19150 as_tsktsk (MVE_BAD_PC);
19153 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
19155 constraint (et.type == NT_invtype, _("bad type for scalar"));
19156 constraint (x >= size / et.size, _("scalar index out of range"));
19160 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
19161 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
19162 case 32: abcdebits = 0x00; break;
19166 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19167 inst.instruction = 0xe100b10;
19168 do_vfp_cond_or_thumb ();
19169 inst.instruction |= LOW4 (dn) << 16;
19170 inst.instruction |= HI1 (dn) << 7;
19171 inst.instruction |= inst.operands[0].reg << 12;
19172 inst.instruction |= (abcdebits & 3) << 5;
19173 inst.instruction |= (abcdebits >> 2) << 21;
19174 inst.instruction |= (x >> (3-logsize)) << 16;
19178 case NS_RRD: /* case 7 (fmrrd). */
19179 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19180 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19183 inst.instruction = 0xc500b10;
19184 do_vfp_cond_or_thumb ();
19185 inst.instruction |= inst.operands[0].reg << 12;
19186 inst.instruction |= inst.operands[1].reg << 16;
19187 inst.instruction |= LOW4 (inst.operands[2].reg);
19188 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19191 case NS_FF: /* case 8 (fcpys). */
19192 do_vfp_nsyn_opcode ("fcpys");
19196 case NS_FI: /* case 10 (fconsts). */
19197 ldconst = "fconsts";
19199 if (!inst.operands[1].immisfloat)
19202 /* Immediate has to fit in 8 bits so float is enough. */
19203 float imm = (float) inst.operands[1].imm;
19204 memcpy (&new_imm, &imm, sizeof (float));
19205 /* But the assembly may have been written to provide an integer
19206 bit pattern that equates to a float, so check that the
19207 conversion has worked. */
19208 if (is_quarter_float (new_imm))
19210 if (is_quarter_float (inst.operands[1].imm))
19211 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19213 inst.operands[1].imm = new_imm;
19214 inst.operands[1].immisfloat = 1;
19218 if (is_quarter_float (inst.operands[1].imm))
19220 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
19221 do_vfp_nsyn_opcode (ldconst);
19223 /* ARMv8.2 fp16 vmov.f16 instruction. */
19225 do_scalar_fp16_v82_encode ();
19228 first_error (_("immediate out of range"));
19232 case NS_RF: /* case 12 (fmrs). */
19233 do_vfp_nsyn_opcode ("fmrs");
19234 /* ARMv8.2 fp16 vmov.f16 instruction. */
19236 do_scalar_fp16_v82_encode ();
19240 case NS_FR: /* case 13 (fmsr). */
19241 do_vfp_nsyn_opcode ("fmsr");
19242 /* ARMv8.2 fp16 vmov.f16 instruction. */
19244 do_scalar_fp16_v82_encode ();
19254 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19255 (one of which is a list), but we have parsed four. Do some fiddling to
19256 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19258 case NS_RRFF: /* case 14 (fmrrs). */
19259 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19260 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19262 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
19263 _("VFP registers must be adjacent"));
19264 inst.operands[2].imm = 2;
19265 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19266 do_vfp_nsyn_opcode ("fmrrs");
19269 case NS_FFRR: /* case 15 (fmsrr). */
19270 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19271 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19273 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
19274 _("VFP registers must be adjacent"));
19275 inst.operands[1] = inst.operands[2];
19276 inst.operands[2] = inst.operands[3];
19277 inst.operands[0].imm = 2;
19278 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19279 do_vfp_nsyn_opcode ("fmsrr");
19283 /* neon_select_shape has determined that the instruction
19284 shape is wrong and has already set the error message. */
19295 if (!(inst.operands[0].present && inst.operands[0].isquad
19296 && inst.operands[1].present && inst.operands[1].isquad
19297 && !inst.operands[2].present))
19299 inst.instruction = 0;
19302 set_pred_insn_type (INSIDE_IT_INSN);
19307 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19310 if (inst.cond != COND_ALWAYS)
19311 inst.pred_insn_type = INSIDE_VPT_INSN;
19313 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
19314 | N_S16 | N_U16 | N_KEY);
19316 inst.instruction |= (et.type == NT_unsigned) << 28;
19317 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19318 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
19319 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19320 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19321 inst.instruction |= LOW4 (inst.operands[1].reg);
19326 do_neon_rshift_round_imm (void)
19328 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
19329 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
19330 int imm = inst.operands[2].imm;
19332 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19335 inst.operands[2].present = 0;
19340 constraint (imm < 1 || (unsigned)imm > et.size,
19341 _("immediate out of range for shift"));
19342 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
19347 do_neon_movhf (void)
19349 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
19350 constraint (rs != NS_HH, _("invalid suffix"));
19352 if (inst.cond != COND_ALWAYS)
19356 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19357 " the behaviour is UNPREDICTABLE"));
19361 inst.error = BAD_COND;
19366 do_vfp_sp_monadic ();
19369 inst.instruction |= 0xf0000000;
19373 do_neon_movl (void)
19375 struct neon_type_el et = neon_check_type (2, NS_QD,
19376 N_EQK | N_DBL, N_SU_32 | N_KEY);
19377 unsigned sizebits = et.size >> 3;
19378 inst.instruction |= sizebits << 19;
19379 neon_two_same (0, et.type == NT_unsigned, -1);
19385 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19386 struct neon_type_el et = neon_check_type (2, rs,
19387 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19388 NEON_ENCODE (INTEGER, inst);
19389 neon_two_same (neon_quad (rs), 1, et.size);
19393 do_neon_zip_uzp (void)
19395 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19396 struct neon_type_el et = neon_check_type (2, rs,
19397 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19398 if (rs == NS_DD && et.size == 32)
19400 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19401 inst.instruction = N_MNEM_vtrn;
19405 neon_two_same (neon_quad (rs), 1, et.size);
19409 do_neon_sat_abs_neg (void)
19411 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19412 struct neon_type_el et = neon_check_type (2, rs,
19413 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19414 neon_two_same (neon_quad (rs), 1, et.size);
19418 do_neon_pair_long (void)
19420 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19421 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
19422 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19423 inst.instruction |= (et.type == NT_unsigned) << 7;
19424 neon_two_same (neon_quad (rs), 1, et.size);
19428 do_neon_recip_est (void)
19430 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19431 struct neon_type_el et = neon_check_type (2, rs,
19432 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
19433 inst.instruction |= (et.type == NT_float) << 8;
19434 neon_two_same (neon_quad (rs), 1, et.size);
19440 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19443 enum neon_shape rs;
19444 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19445 rs = neon_select_shape (NS_QQ, NS_NULL);
19447 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19449 struct neon_type_el et = neon_check_type (2, rs,
19450 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19451 neon_two_same (neon_quad (rs), 1, et.size);
19457 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19460 enum neon_shape rs;
19461 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19462 rs = neon_select_shape (NS_QQ, NS_NULL);
19464 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19466 struct neon_type_el et = neon_check_type (2, rs,
19467 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
19468 neon_two_same (neon_quad (rs), 1, et.size);
19474 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19475 struct neon_type_el et = neon_check_type (2, rs,
19476 N_EQK | N_INT, N_8 | N_KEY);
19477 neon_two_same (neon_quad (rs), 1, et.size);
19483 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19484 neon_two_same (neon_quad (rs), 1, -1);
19488 do_neon_tbl_tbx (void)
19490 unsigned listlenbits;
19491 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
19493 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
19495 first_error (_("bad list length for table lookup"));
19499 listlenbits = inst.operands[1].imm - 1;
19500 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19501 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19502 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19503 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19504 inst.instruction |= LOW4 (inst.operands[2].reg);
19505 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19506 inst.instruction |= listlenbits << 8;
19508 neon_dp_fixup (&inst);
19512 do_neon_ldm_stm (void)
19514 /* P, U and L bits are part of bitmask. */
19515 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
19516 unsigned offsetbits = inst.operands[1].imm * 2;
19518 if (inst.operands[1].issingle)
19520 do_vfp_nsyn_ldm_stm (is_dbmode);
19524 constraint (is_dbmode && !inst.operands[0].writeback,
19525 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19527 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
19528 _("register list must contain at least 1 and at most 16 "
19531 inst.instruction |= inst.operands[0].reg << 16;
19532 inst.instruction |= inst.operands[0].writeback << 21;
19533 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19534 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
19536 inst.instruction |= offsetbits;
19538 do_vfp_cond_or_thumb ();
19542 do_neon_ldr_str (void)
19544 int is_ldr = (inst.instruction & (1 << 20)) != 0;
19546 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19547 And is UNPREDICTABLE in thumb mode. */
19549 && inst.operands[1].reg == REG_PC
19550 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
19553 inst.error = _("Use of PC here is UNPREDICTABLE");
19554 else if (warn_on_deprecated)
19555 as_tsktsk (_("Use of PC here is deprecated"));
19558 if (inst.operands[0].issingle)
19561 do_vfp_nsyn_opcode ("flds");
19563 do_vfp_nsyn_opcode ("fsts");
19565 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19566 if (inst.vectype.el[0].size == 16)
19567 do_scalar_fp16_v82_encode ();
19572 do_vfp_nsyn_opcode ("fldd");
19574 do_vfp_nsyn_opcode ("fstd");
19579 do_t_vldr_vstr_sysreg (void)
19581 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
19582 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
19584 /* Use of PC is UNPREDICTABLE. */
19585 if (inst.operands[1].reg == REG_PC)
19586 inst.error = _("Use of PC here is UNPREDICTABLE");
19588 if (inst.operands[1].immisreg)
19589 inst.error = _("instruction does not accept register index");
19591 if (!inst.operands[1].isreg)
19592 inst.error = _("instruction does not accept PC-relative addressing");
19594 if (abs (inst.operands[1].imm) >= (1 << 7))
19595 inst.error = _("immediate value out of range");
19597 inst.instruction = 0xec000f80;
19599 inst.instruction |= 1 << sysreg_vldr_bitno;
19600 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
19601 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
19602 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
19606 do_vldr_vstr (void)
19608 bfd_boolean sysreg_op = !inst.operands[0].isreg;
19610 /* VLDR/VSTR (System Register). */
19613 if (!mark_feature_used (&arm_ext_v8_1m_main))
19614 as_bad (_("Instruction not permitted on this architecture"));
19616 do_t_vldr_vstr_sysreg ();
19621 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
19622 as_bad (_("Instruction not permitted on this architecture"));
19623 do_neon_ldr_str ();
19627 /* "interleave" version also handles non-interleaving register VLD1/VST1
19631 do_neon_ld_st_interleave (void)
19633 struct neon_type_el et = neon_check_type (1, NS_NULL,
19634 N_8 | N_16 | N_32 | N_64);
19635 unsigned alignbits = 0;
19637 /* The bits in this table go:
19638 0: register stride of one (0) or two (1)
19639 1,2: register list length, minus one (1, 2, 3, 4).
19640 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19641 We use -1 for invalid entries. */
19642 const int typetable[] =
19644 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19645 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19646 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19647 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19651 if (et.type == NT_invtype)
19654 if (inst.operands[1].immisalign)
19655 switch (inst.operands[1].imm >> 8)
19657 case 64: alignbits = 1; break;
19659 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
19660 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
19661 goto bad_alignment;
19665 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
19666 goto bad_alignment;
19671 first_error (_("bad alignment"));
19675 inst.instruction |= alignbits << 4;
19676 inst.instruction |= neon_logbits (et.size) << 6;
19678 /* Bits [4:6] of the immediate in a list specifier encode register stride
19679 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19680 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19681 up the right value for "type" in a table based on this value and the given
19682 list style, then stick it back. */
19683 idx = ((inst.operands[0].imm >> 4) & 7)
19684 | (((inst.instruction >> 8) & 3) << 3);
19686 typebits = typetable[idx];
19688 constraint (typebits == -1, _("bad list type for instruction"));
19689 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
19692 inst.instruction &= ~0xf00;
19693 inst.instruction |= typebits << 8;
19696 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19697 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19698 otherwise. The variable arguments are a list of pairs of legal (size, align)
19699 values, terminated with -1. */
19702 neon_alignment_bit (int size, int align, int *do_alignment, ...)
19705 int result = FAIL, thissize, thisalign;
19707 if (!inst.operands[1].immisalign)
19713 va_start (ap, do_alignment);
19717 thissize = va_arg (ap, int);
19718 if (thissize == -1)
19720 thisalign = va_arg (ap, int);
19722 if (size == thissize && align == thisalign)
19725 while (result != SUCCESS);
19729 if (result == SUCCESS)
19732 first_error (_("unsupported alignment for instruction"));
19738 do_neon_ld_st_lane (void)
19740 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
19741 int align_good, do_alignment = 0;
19742 int logsize = neon_logbits (et.size);
19743 int align = inst.operands[1].imm >> 8;
19744 int n = (inst.instruction >> 8) & 3;
19745 int max_el = 64 / et.size;
19747 if (et.type == NT_invtype)
19750 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
19751 _("bad list length"));
19752 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
19753 _("scalar index out of range"));
19754 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
19756 _("stride of 2 unavailable when element size is 8"));
19760 case 0: /* VLD1 / VST1. */
19761 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
19763 if (align_good == FAIL)
19767 unsigned alignbits = 0;
19770 case 16: alignbits = 0x1; break;
19771 case 32: alignbits = 0x3; break;
19774 inst.instruction |= alignbits << 4;
19778 case 1: /* VLD2 / VST2. */
19779 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
19780 16, 32, 32, 64, -1);
19781 if (align_good == FAIL)
19784 inst.instruction |= 1 << 4;
19787 case 2: /* VLD3 / VST3. */
19788 constraint (inst.operands[1].immisalign,
19789 _("can't use alignment with this instruction"));
19792 case 3: /* VLD4 / VST4. */
19793 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
19794 16, 64, 32, 64, 32, 128, -1);
19795 if (align_good == FAIL)
19799 unsigned alignbits = 0;
19802 case 8: alignbits = 0x1; break;
19803 case 16: alignbits = 0x1; break;
19804 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
19807 inst.instruction |= alignbits << 4;
19814 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19815 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19816 inst.instruction |= 1 << (4 + logsize);
19818 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
19819 inst.instruction |= logsize << 10;
19822 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19825 do_neon_ld_dup (void)
19827 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
19828 int align_good, do_alignment = 0;
19830 if (et.type == NT_invtype)
19833 switch ((inst.instruction >> 8) & 3)
19835 case 0: /* VLD1. */
19836 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
19837 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
19838 &do_alignment, 16, 16, 32, 32, -1);
19839 if (align_good == FAIL)
19841 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
19844 case 2: inst.instruction |= 1 << 5; break;
19845 default: first_error (_("bad list length")); return;
19847 inst.instruction |= neon_logbits (et.size) << 6;
19850 case 1: /* VLD2. */
19851 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
19852 &do_alignment, 8, 16, 16, 32, 32, 64,
19854 if (align_good == FAIL)
19856 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
19857 _("bad list length"));
19858 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19859 inst.instruction |= 1 << 5;
19860 inst.instruction |= neon_logbits (et.size) << 6;
19863 case 2: /* VLD3. */
19864 constraint (inst.operands[1].immisalign,
19865 _("can't use alignment with this instruction"));
19866 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
19867 _("bad list length"));
19868 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19869 inst.instruction |= 1 << 5;
19870 inst.instruction |= neon_logbits (et.size) << 6;
19873 case 3: /* VLD4. */
19875 int align = inst.operands[1].imm >> 8;
19876 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
19877 16, 64, 32, 64, 32, 128, -1);
19878 if (align_good == FAIL)
19880 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
19881 _("bad list length"));
19882 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19883 inst.instruction |= 1 << 5;
19884 if (et.size == 32 && align == 128)
19885 inst.instruction |= 0x3 << 6;
19887 inst.instruction |= neon_logbits (et.size) << 6;
19894 inst.instruction |= do_alignment << 4;
19897 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19898 apart from bits [11:4]. */
19901 do_neon_ldx_stx (void)
19903 if (inst.operands[1].isreg)
19904 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
19906 switch (NEON_LANE (inst.operands[0].imm))
19908 case NEON_INTERLEAVE_LANES:
19909 NEON_ENCODE (INTERLV, inst);
19910 do_neon_ld_st_interleave ();
19913 case NEON_ALL_LANES:
19914 NEON_ENCODE (DUP, inst);
19915 if (inst.instruction == N_INV)
19917 first_error ("only loads support such operands");
19924 NEON_ENCODE (LANE, inst);
19925 do_neon_ld_st_lane ();
19928 /* L bit comes from bit mask. */
19929 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19930 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19931 inst.instruction |= inst.operands[1].reg << 16;
19933 if (inst.operands[1].postind)
19935 int postreg = inst.operands[1].imm & 0xf;
19936 constraint (!inst.operands[1].immisreg,
19937 _("post-index must be a register"));
19938 constraint (postreg == 0xd || postreg == 0xf,
19939 _("bad register for post-index"));
19940 inst.instruction |= postreg;
19944 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
19945 constraint (inst.relocs[0].exp.X_op != O_constant
19946 || inst.relocs[0].exp.X_add_number != 0,
19949 if (inst.operands[1].writeback)
19951 inst.instruction |= 0xd;
19954 inst.instruction |= 0xf;
19958 inst.instruction |= 0xf9000000;
19960 inst.instruction |= 0xf4000000;
19965 do_vfp_nsyn_fpv8 (enum neon_shape rs)
19967 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19968 D register operands. */
19969 if (neon_shape_class[rs] == SC_DOUBLE)
19970 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19973 NEON_ENCODE (FPV8, inst);
19975 if (rs == NS_FFF || rs == NS_HHH)
19977 do_vfp_sp_dyadic ();
19979 /* ARMv8.2 fp16 instruction. */
19981 do_scalar_fp16_v82_encode ();
19984 do_vfp_dp_rd_rn_rm ();
19987 inst.instruction |= 0x100;
19989 inst.instruction |= 0xf0000000;
19995 set_pred_insn_type (OUTSIDE_PRED_INSN);
19997 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
19998 first_error (_("invalid instruction shape"));
20004 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20005 set_pred_insn_type (OUTSIDE_PRED_INSN);
20007 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
20010 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
20013 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
20017 do_vrint_1 (enum neon_cvt_mode mode)
20019 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
20020 struct neon_type_el et;
20025 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20026 D register operands. */
20027 if (neon_shape_class[rs] == SC_DOUBLE)
20028 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20031 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
20033 if (et.type != NT_invtype)
20035 /* VFP encodings. */
20036 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
20037 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
20038 set_pred_insn_type (OUTSIDE_PRED_INSN);
20040 NEON_ENCODE (FPV8, inst);
20041 if (rs == NS_FF || rs == NS_HH)
20042 do_vfp_sp_monadic ();
20044 do_vfp_dp_rd_rm ();
20048 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
20049 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
20050 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
20051 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
20052 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
20053 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
20054 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
20058 inst.instruction |= (rs == NS_DD) << 8;
20059 do_vfp_cond_or_thumb ();
20061 /* ARMv8.2 fp16 vrint instruction. */
20063 do_scalar_fp16_v82_encode ();
20067 /* Neon encodings (or something broken...). */
20069 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
20071 if (et.type == NT_invtype)
20074 set_pred_insn_type (OUTSIDE_PRED_INSN);
20075 NEON_ENCODE (FLOAT, inst);
20077 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
20080 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20081 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20082 inst.instruction |= LOW4 (inst.operands[1].reg);
20083 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20084 inst.instruction |= neon_quad (rs) << 6;
20085 /* Mask off the original size bits and reencode them. */
20086 inst.instruction = ((inst.instruction & 0xfff3ffff)
20087 | neon_logbits (et.size) << 18);
20091 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
20092 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
20093 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
20094 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
20095 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
20096 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
20097 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
20102 inst.instruction |= 0xfc000000;
20104 inst.instruction |= 0xf0000000;
20111 do_vrint_1 (neon_cvt_mode_x);
20117 do_vrint_1 (neon_cvt_mode_z);
20123 do_vrint_1 (neon_cvt_mode_r);
20129 do_vrint_1 (neon_cvt_mode_a);
20135 do_vrint_1 (neon_cvt_mode_n);
20141 do_vrint_1 (neon_cvt_mode_p);
20147 do_vrint_1 (neon_cvt_mode_m);
20151 neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
20153 unsigned regno = NEON_SCALAR_REG (opnd);
20154 unsigned elno = NEON_SCALAR_INDEX (opnd);
20156 if (elsize == 16 && elno < 2 && regno < 16)
20157 return regno | (elno << 4);
20158 else if (elsize == 32 && elno == 0)
20161 first_error (_("scalar out of range"));
20168 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
20169 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20170 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20171 constraint (inst.relocs[0].exp.X_op != O_constant,
20172 _("expression too complex"));
20173 unsigned rot = inst.relocs[0].exp.X_add_number;
20174 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
20175 _("immediate out of range"));
20178 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC))
20181 if (inst.operands[2].isscalar)
20183 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20184 first_error (_("invalid instruction shape"));
20185 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
20186 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20187 N_KEY | N_F16 | N_F32).size;
20188 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
20190 inst.instruction = 0xfe000800;
20191 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20192 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20193 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20194 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20195 inst.instruction |= LOW4 (m);
20196 inst.instruction |= HI1 (m) << 5;
20197 inst.instruction |= neon_quad (rs) << 6;
20198 inst.instruction |= rot << 20;
20199 inst.instruction |= (size == 32) << 23;
20203 enum neon_shape rs;
20204 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20205 rs = neon_select_shape (NS_QQQI, NS_NULL);
20207 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20209 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20210 N_KEY | N_F16 | N_F32).size;
20211 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
20212 && (inst.operands[0].reg == inst.operands[1].reg
20213 || inst.operands[0].reg == inst.operands[2].reg))
20214 as_tsktsk (BAD_MVE_SRCDEST);
20216 neon_three_same (neon_quad (rs), 0, -1);
20217 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20218 inst.instruction |= 0xfc200800;
20219 inst.instruction |= rot << 23;
20220 inst.instruction |= (size == 32) << 20;
20227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20228 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20229 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20230 constraint (inst.relocs[0].exp.X_op != O_constant,
20231 _("expression too complex"));
20233 unsigned rot = inst.relocs[0].exp.X_add_number;
20234 constraint (rot != 90 && rot != 270, _("immediate out of range"));
20235 enum neon_shape rs;
20236 struct neon_type_el et;
20237 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20239 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20240 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
20244 rs = neon_select_shape (NS_QQQI, NS_NULL);
20245 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
20247 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
20248 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20249 "operand makes instruction UNPREDICTABLE"));
20252 if (et.type == NT_invtype)
20255 if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8
20259 if (et.type == NT_float)
20261 neon_three_same (neon_quad (rs), 0, -1);
20262 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20263 inst.instruction |= 0xfc800800;
20264 inst.instruction |= (rot == 270) << 24;
20265 inst.instruction |= (et.size == 32) << 20;
20269 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
20270 inst.instruction = 0xfe000f00;
20271 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20272 inst.instruction |= neon_logbits (et.size) << 20;
20273 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20274 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20275 inst.instruction |= (rot == 270) << 12;
20276 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20277 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20278 inst.instruction |= LOW4 (inst.operands[2].reg);
20283 /* Dot Product instructions encoding support. */
20286 do_neon_dotproduct (int unsigned_p)
20288 enum neon_shape rs;
20289 unsigned scalar_oprd2 = 0;
20292 if (inst.cond != COND_ALWAYS)
20293 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20294 "is UNPREDICTABLE"));
20296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
20299 /* Dot Product instructions are in three-same D/Q register format or the third
20300 operand can be a scalar index register. */
20301 if (inst.operands[2].isscalar)
20303 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
20304 high8 = 0xfe000000;
20305 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
20309 high8 = 0xfc000000;
20310 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
20314 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
20316 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
20318 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20319 Product instruction, so we pass 0 as the "ubit" parameter. And the
20320 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20321 neon_three_same (neon_quad (rs), 0, 32);
20323 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20324 different NEON three-same encoding. */
20325 inst.instruction &= 0x00ffffff;
20326 inst.instruction |= high8;
20327 /* Encode 'U' bit which indicates signedness. */
20328 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
20329 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20330 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20331 the instruction encoding. */
20332 if (inst.operands[2].isscalar)
20334 inst.instruction &= 0xffffffd0;
20335 inst.instruction |= LOW4 (scalar_oprd2);
20336 inst.instruction |= HI1 (scalar_oprd2) << 5;
20340 /* Dot Product instructions for signed integer. */
20343 do_neon_dotproduct_s (void)
20345 return do_neon_dotproduct (0);
20348 /* Dot Product instructions for unsigned integer. */
20351 do_neon_dotproduct_u (void)
20353 return do_neon_dotproduct (1);
20356 /* Crypto v1 instructions. */
20358 do_crypto_2op_1 (unsigned elttype, int op)
20360 set_pred_insn_type (OUTSIDE_PRED_INSN);
20362 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
20368 NEON_ENCODE (INTEGER, inst);
20369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20370 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20371 inst.instruction |= LOW4 (inst.operands[1].reg);
20372 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20374 inst.instruction |= op << 6;
20377 inst.instruction |= 0xfc000000;
20379 inst.instruction |= 0xf0000000;
20383 do_crypto_3op_1 (int u, int op)
20385 set_pred_insn_type (OUTSIDE_PRED_INSN);
20387 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
20388 N_32 | N_UNT | N_KEY).type == NT_invtype)
20393 NEON_ENCODE (INTEGER, inst);
20394 neon_three_same (1, u, 8 << op);
20400 do_crypto_2op_1 (N_8, 0);
20406 do_crypto_2op_1 (N_8, 1);
20412 do_crypto_2op_1 (N_8, 2);
20418 do_crypto_2op_1 (N_8, 3);
20424 do_crypto_3op_1 (0, 0);
20430 do_crypto_3op_1 (0, 1);
20436 do_crypto_3op_1 (0, 2);
20442 do_crypto_3op_1 (0, 3);
20448 do_crypto_3op_1 (1, 0);
20454 do_crypto_3op_1 (1, 1);
20458 do_sha256su1 (void)
20460 do_crypto_3op_1 (1, 2);
20466 do_crypto_2op_1 (N_32, -1);
20472 do_crypto_2op_1 (N_32, 0);
20476 do_sha256su0 (void)
20478 do_crypto_2op_1 (N_32, 1);
20482 do_crc32_1 (unsigned int poly, unsigned int sz)
20484 unsigned int Rd = inst.operands[0].reg;
20485 unsigned int Rn = inst.operands[1].reg;
20486 unsigned int Rm = inst.operands[2].reg;
20488 set_pred_insn_type (OUTSIDE_PRED_INSN);
20489 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
20490 inst.instruction |= LOW4 (Rn) << 16;
20491 inst.instruction |= LOW4 (Rm);
20492 inst.instruction |= sz << (thumb_mode ? 4 : 21);
20493 inst.instruction |= poly << (thumb_mode ? 20 : 9);
20495 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
20496 as_warn (UNPRED_REG ("r15"));
20538 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20540 neon_check_type (2, NS_FD, N_S32, N_F64);
20541 do_vfp_sp_dp_cvt ();
20542 do_vfp_cond_or_thumb ();
20546 /* Overall per-instruction processing. */
20548 /* We need to be able to fix up arbitrary expressions in some statements.
20549 This is so that we can handle symbols that are an arbitrary distance from
20550 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20551 which returns part of an address in a form which will be valid for
20552 a data instruction. We do this by pushing the expression into a symbol
20553 in the expr_section, and creating a fix for that. */
20556 fix_new_arm (fragS * frag,
20570 /* Create an absolute valued symbol, so we have something to
20571 refer to in the object file. Unfortunately for us, gas's
20572 generic expression parsing will already have folded out
20573 any use of .set foo/.type foo %function that may have
20574 been used to set type information of the target location,
20575 that's being specified symbolically. We have to presume
20576 the user knows what they are doing. */
20580 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
20582 symbol = symbol_find_or_make (name);
20583 S_SET_SEGMENT (symbol, absolute_section);
20584 symbol_set_frag (symbol, &zero_address_frag);
20585 S_SET_VALUE (symbol, exp->X_add_number);
20586 exp->X_op = O_symbol;
20587 exp->X_add_symbol = symbol;
20588 exp->X_add_number = 0;
20594 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
20595 (enum bfd_reloc_code_real) reloc);
20599 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
20600 pc_rel, (enum bfd_reloc_code_real) reloc);
20604 /* Mark whether the fix is to a THUMB instruction, or an ARM
20606 new_fix->tc_fix_data = thumb_mode;
20609 /* Create a frg for an instruction requiring relaxation. */
20611 output_relax_insn (void)
20617 /* The size of the instruction is unknown, so tie the debug info to the
20618 start of the instruction. */
20619 dwarf2_emit_insn (0);
20621 switch (inst.relocs[0].exp.X_op)
20624 sym = inst.relocs[0].exp.X_add_symbol;
20625 offset = inst.relocs[0].exp.X_add_number;
20629 offset = inst.relocs[0].exp.X_add_number;
20632 sym = make_expr_symbol (&inst.relocs[0].exp);
20636 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
20637 inst.relax, sym, offset, NULL/*offset, opcode*/);
20638 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
20641 /* Write a 32-bit thumb instruction to buf. */
20643 put_thumb32_insn (char * buf, unsigned long insn)
20645 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
20646 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
20650 output_inst (const char * str)
20656 as_bad ("%s -- `%s'", inst.error, str);
20661 output_relax_insn ();
20664 if (inst.size == 0)
20667 to = frag_more (inst.size);
20668 /* PR 9814: Record the thumb mode into the current frag so that we know
20669 what type of NOP padding to use, if necessary. We override any previous
20670 setting so that if the mode has changed then the NOPS that we use will
20671 match the encoding of the last instruction in the frag. */
20672 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20674 if (thumb_mode && (inst.size > THUMB_SIZE))
20676 gas_assert (inst.size == (2 * THUMB_SIZE));
20677 put_thumb32_insn (to, inst.instruction);
20679 else if (inst.size > INSN_SIZE)
20681 gas_assert (inst.size == (2 * INSN_SIZE));
20682 md_number_to_chars (to, inst.instruction, INSN_SIZE);
20683 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
20686 md_number_to_chars (to, inst.instruction, inst.size);
20689 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
20691 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
20692 fix_new_arm (frag_now, to - frag_now->fr_literal,
20693 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
20694 inst.relocs[r].type);
20697 dwarf2_emit_insn (inst.size);
20701 output_it_inst (int cond, int mask, char * to)
20703 unsigned long instruction = 0xbf00;
20706 instruction |= mask;
20707 instruction |= cond << 4;
20711 to = frag_more (2);
20713 dwarf2_emit_insn (2);
20717 md_number_to_chars (to, instruction, 2);
20722 /* Tag values used in struct asm_opcode's tag field. */
20725 OT_unconditional, /* Instruction cannot be conditionalized.
20726 The ARM condition field is still 0xE. */
20727 OT_unconditionalF, /* Instruction cannot be conditionalized
20728 and carries 0xF in its ARM condition field. */
20729 OT_csuffix, /* Instruction takes a conditional suffix. */
20730 OT_csuffixF, /* Some forms of the instruction take a scalar
20731 conditional suffix, others place 0xF where the
20732 condition field would be, others take a vector
20733 conditional suffix. */
20734 OT_cinfix3, /* Instruction takes a conditional infix,
20735 beginning at character index 3. (In
20736 unified mode, it becomes a suffix.) */
20737 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
20738 tsts, cmps, cmns, and teqs. */
20739 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
20740 character index 3, even in unified mode. Used for
20741 legacy instructions where suffix and infix forms
20742 may be ambiguous. */
20743 OT_csuf_or_in3, /* Instruction takes either a conditional
20744 suffix or an infix at character index 3. */
20745 OT_odd_infix_unc, /* This is the unconditional variant of an
20746 instruction that takes a conditional infix
20747 at an unusual position. In unified mode,
20748 this variant will accept a suffix. */
20749 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
20750 are the conditional variants of instructions that
20751 take conditional infixes in unusual positions.
20752 The infix appears at character index
20753 (tag - OT_odd_infix_0). These are not accepted
20754 in unified mode. */
20757 /* Subroutine of md_assemble, responsible for looking up the primary
20758 opcode from the mnemonic the user wrote. STR points to the
20759 beginning of the mnemonic.
20761 This is not simply a hash table lookup, because of conditional
20762 variants. Most instructions have conditional variants, which are
20763 expressed with a _conditional affix_ to the mnemonic. If we were
20764 to encode each conditional variant as a literal string in the opcode
20765 table, it would have approximately 20,000 entries.
20767 Most mnemonics take this affix as a suffix, and in unified syntax,
20768 'most' is upgraded to 'all'. However, in the divided syntax, some
20769 instructions take the affix as an infix, notably the s-variants of
20770 the arithmetic instructions. Of those instructions, all but six
20771 have the infix appear after the third character of the mnemonic.
20773 Accordingly, the algorithm for looking up primary opcodes given
20776 1. Look up the identifier in the opcode table.
20777 If we find a match, go to step U.
20779 2. Look up the last two characters of the identifier in the
20780 conditions table. If we find a match, look up the first N-2
20781 characters of the identifier in the opcode table. If we
20782 find a match, go to step CE.
20784 3. Look up the fourth and fifth characters of the identifier in
20785 the conditions table. If we find a match, extract those
20786 characters from the identifier, and look up the remaining
20787 characters in the opcode table. If we find a match, go
20792 U. Examine the tag field of the opcode structure, in case this is
20793 one of the six instructions with its conditional infix in an
20794 unusual place. If it is, the tag tells us where to find the
20795 infix; look it up in the conditions table and set inst.cond
20796 accordingly. Otherwise, this is an unconditional instruction.
20797 Again set inst.cond accordingly. Return the opcode structure.
20799 CE. Examine the tag field to make sure this is an instruction that
20800 should receive a conditional suffix. If it is not, fail.
20801 Otherwise, set inst.cond from the suffix we already looked up,
20802 and return the opcode structure.
20804 CM. Examine the tag field to make sure this is an instruction that
20805 should receive a conditional infix after the third character.
20806 If it is not, fail. Otherwise, undo the edits to the current
20807 line of input and proceed as for case CE. */
20809 static const struct asm_opcode *
20810 opcode_lookup (char **str)
20814 const struct asm_opcode *opcode;
20815 const struct asm_cond *cond;
20818 /* Scan up to the end of the mnemonic, which must end in white space,
20819 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20820 for (base = end = *str; *end != '\0'; end++)
20821 if (*end == ' ' || *end == '.')
20827 /* Handle a possible width suffix and/or Neon type suffix. */
20832 /* The .w and .n suffixes are only valid if the unified syntax is in
20834 if (unified_syntax && end[1] == 'w')
20836 else if (unified_syntax && end[1] == 'n')
20841 inst.vectype.elems = 0;
20843 *str = end + offset;
20845 if (end[offset] == '.')
20847 /* See if we have a Neon type suffix (possible in either unified or
20848 non-unified ARM syntax mode). */
20849 if (parse_neon_type (&inst.vectype, str) == FAIL)
20852 else if (end[offset] != '\0' && end[offset] != ' ')
20858 /* Look for unaffixed or special-case affixed mnemonic. */
20859 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20864 if (opcode->tag < OT_odd_infix_0)
20866 inst.cond = COND_ALWAYS;
20870 if (warn_on_deprecated && unified_syntax)
20871 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20872 affix = base + (opcode->tag - OT_odd_infix_0);
20873 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20876 inst.cond = cond->value;
20879 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20881 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20883 if (end - base < 2)
20886 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
20887 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20889 /* If this opcode can not be vector predicated then don't accept it with a
20890 vector predication code. */
20891 if (opcode && !opcode->mayBeVecPred)
20894 if (!opcode || !cond)
20896 /* Cannot have a conditional suffix on a mnemonic of less than two
20898 if (end - base < 3)
20901 /* Look for suffixed mnemonic. */
20903 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20904 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20908 if (opcode && cond)
20911 switch (opcode->tag)
20913 case OT_cinfix3_legacy:
20914 /* Ignore conditional suffixes matched on infix only mnemonics. */
20918 case OT_cinfix3_deprecated:
20919 case OT_odd_infix_unc:
20920 if (!unified_syntax)
20922 /* Fall through. */
20926 case OT_csuf_or_in3:
20927 inst.cond = cond->value;
20930 case OT_unconditional:
20931 case OT_unconditionalF:
20933 inst.cond = cond->value;
20936 /* Delayed diagnostic. */
20937 inst.error = BAD_COND;
20938 inst.cond = COND_ALWAYS;
20947 /* Cannot have a usual-position infix on a mnemonic of less than
20948 six characters (five would be a suffix). */
20949 if (end - base < 6)
20952 /* Look for infixed mnemonic in the usual position. */
20954 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20958 memcpy (save, affix, 2);
20959 memmove (affix, affix + 2, (end - affix) - 2);
20960 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20962 memmove (affix + 2, affix, (end - affix) - 2);
20963 memcpy (affix, save, 2);
20966 && (opcode->tag == OT_cinfix3
20967 || opcode->tag == OT_cinfix3_deprecated
20968 || opcode->tag == OT_csuf_or_in3
20969 || opcode->tag == OT_cinfix3_legacy))
20972 if (warn_on_deprecated && unified_syntax
20973 && (opcode->tag == OT_cinfix3
20974 || opcode->tag == OT_cinfix3_deprecated))
20975 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20977 inst.cond = cond->value;
20984 /* This function generates an initial IT instruction, leaving its block
20985 virtually open for the new instructions. Eventually,
20986 the mask will be updated by now_pred_add_mask () each time
20987 a new instruction needs to be included in the IT block.
20988 Finally, the block is closed with close_automatic_it_block ().
20989 The block closure can be requested either from md_assemble (),
20990 a tencode (), or due to a label hook. */
20993 new_automatic_it_block (int cond)
20995 now_pred.state = AUTOMATIC_PRED_BLOCK;
20996 now_pred.mask = 0x18;
20997 now_pred.cc = cond;
20998 now_pred.block_length = 1;
20999 mapping_state (MAP_THUMB);
21000 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
21001 now_pred.warn_deprecated = FALSE;
21002 now_pred.insn_cond = TRUE;
21005 /* Close an automatic IT block.
21006 See comments in new_automatic_it_block (). */
21009 close_automatic_it_block (void)
21011 now_pred.mask = 0x10;
21012 now_pred.block_length = 0;
21015 /* Update the mask of the current automatically-generated IT
21016 instruction. See comments in new_automatic_it_block (). */
21019 now_pred_add_mask (int cond)
21021 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21022 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21023 | ((bitvalue) << (nbit)))
21024 const int resulting_bit = (cond & 1);
21026 now_pred.mask &= 0xf;
21027 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
21029 (5 - now_pred.block_length));
21030 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
21032 ((5 - now_pred.block_length) - 1));
21033 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
21036 #undef SET_BIT_VALUE
21039 /* The IT blocks handling machinery is accessed through the these functions:
21040 it_fsm_pre_encode () from md_assemble ()
21041 set_pred_insn_type () optional, from the tencode functions
21042 set_pred_insn_type_last () ditto
21043 in_pred_block () ditto
21044 it_fsm_post_encode () from md_assemble ()
21045 force_automatic_it_block_close () from label handling functions
21048 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21049 initializing the IT insn type with a generic initial value depending
21050 on the inst.condition.
21051 2) During the tencode function, two things may happen:
21052 a) The tencode function overrides the IT insn type by
21053 calling either set_pred_insn_type (type) or
21054 set_pred_insn_type_last ().
21055 b) The tencode function queries the IT block state by
21056 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21058 Both set_pred_insn_type and in_pred_block run the internal FSM state
21059 handling function (handle_pred_state), because: a) setting the IT insn
21060 type may incur in an invalid state (exiting the function),
21061 and b) querying the state requires the FSM to be updated.
21062 Specifically we want to avoid creating an IT block for conditional
21063 branches, so it_fsm_pre_encode is actually a guess and we can't
21064 determine whether an IT block is required until the tencode () routine
21065 has decided what type of instruction this actually it.
21066 Because of this, if set_pred_insn_type and in_pred_block have to be
21067 used, set_pred_insn_type has to be called first.
21069 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21070 that determines the insn IT type depending on the inst.cond code.
21071 When a tencode () routine encodes an instruction that can be
21072 either outside an IT block, or, in the case of being inside, has to be
21073 the last one, set_pred_insn_type_last () will determine the proper
21074 IT instruction type based on the inst.cond code. Otherwise,
21075 set_pred_insn_type can be called for overriding that logic or
21076 for covering other cases.
21078 Calling handle_pred_state () may not transition the IT block state to
21079 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21080 still queried. Instead, if the FSM determines that the state should
21081 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21082 after the tencode () function: that's what it_fsm_post_encode () does.
21084 Since in_pred_block () calls the state handling function to get an
21085 updated state, an error may occur (due to invalid insns combination).
21086 In that case, inst.error is set.
21087 Therefore, inst.error has to be checked after the execution of
21088 the tencode () routine.
21090 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21091 any pending state change (if any) that didn't take place in
21092 handle_pred_state () as explained above. */
21095 it_fsm_pre_encode (void)
21097 if (inst.cond != COND_ALWAYS)
21098 inst.pred_insn_type = INSIDE_IT_INSN;
21100 inst.pred_insn_type = OUTSIDE_PRED_INSN;
21102 now_pred.state_handled = 0;
21105 /* IT state FSM handling function. */
21106 /* MVE instructions and non-MVE instructions are handled differently because of
21107 the introduction of VPT blocks.
21108 Specifications say that any non-MVE instruction inside a VPT block is
21109 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21110 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21111 few exceptions we have MVE_UNPREDICABLE_INSN.
21112 The error messages provided depending on the different combinations possible
21113 are described in the cases below:
21114 For 'most' MVE instructions:
21115 1) In an IT block, with an IT code: syntax error
21116 2) In an IT block, with a VPT code: error: must be in a VPT block
21117 3) In an IT block, with no code: warning: UNPREDICTABLE
21118 4) In a VPT block, with an IT code: syntax error
21119 5) In a VPT block, with a VPT code: OK!
21120 6) In a VPT block, with no code: error: missing code
21121 7) Outside a pred block, with an IT code: error: syntax error
21122 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21123 9) Outside a pred block, with no code: OK!
21124 For non-MVE instructions:
21125 10) In an IT block, with an IT code: OK!
21126 11) In an IT block, with a VPT code: syntax error
21127 12) In an IT block, with no code: error: missing code
21128 13) In a VPT block, with an IT code: error: should be in an IT block
21129 14) In a VPT block, with a VPT code: syntax error
21130 15) In a VPT block, with no code: UNPREDICTABLE
21131 16) Outside a pred block, with an IT code: error: should be in an IT block
21132 17) Outside a pred block, with a VPT code: syntax error
21133 18) Outside a pred block, with no code: OK!
21138 handle_pred_state (void)
21140 now_pred.state_handled = 1;
21141 now_pred.insn_cond = FALSE;
21143 switch (now_pred.state)
21145 case OUTSIDE_PRED_BLOCK:
21146 switch (inst.pred_insn_type)
21148 case MVE_UNPREDICABLE_INSN:
21149 case MVE_OUTSIDE_PRED_INSN:
21150 if (inst.cond < COND_ALWAYS)
21152 /* Case 7: Outside a pred block, with an IT code: error: syntax
21154 inst.error = BAD_SYNTAX;
21157 /* Case 9: Outside a pred block, with no code: OK! */
21159 case OUTSIDE_PRED_INSN:
21160 if (inst.cond > COND_ALWAYS)
21162 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21164 inst.error = BAD_SYNTAX;
21167 /* Case 18: Outside a pred block, with no code: OK! */
21170 case INSIDE_VPT_INSN:
21171 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21173 inst.error = BAD_OUT_VPT;
21176 case INSIDE_IT_INSN:
21177 case INSIDE_IT_LAST_INSN:
21178 if (inst.cond < COND_ALWAYS)
21180 /* Case 16: Outside a pred block, with an IT code: error: should
21181 be in an IT block. */
21182 if (thumb_mode == 0)
21185 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
21186 as_tsktsk (_("Warning: conditional outside an IT block"\
21191 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
21192 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
21194 /* Automatically generate the IT instruction. */
21195 new_automatic_it_block (inst.cond);
21196 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
21197 close_automatic_it_block ();
21201 inst.error = BAD_OUT_IT;
21207 else if (inst.cond > COND_ALWAYS)
21209 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21211 inst.error = BAD_SYNTAX;
21216 case IF_INSIDE_IT_LAST_INSN:
21217 case NEUTRAL_IT_INSN:
21221 if (inst.cond != COND_ALWAYS)
21222 first_error (BAD_SYNTAX);
21223 now_pred.state = MANUAL_PRED_BLOCK;
21224 now_pred.block_length = 0;
21225 now_pred.type = VECTOR_PRED;
21229 now_pred.state = MANUAL_PRED_BLOCK;
21230 now_pred.block_length = 0;
21231 now_pred.type = SCALAR_PRED;
21236 case AUTOMATIC_PRED_BLOCK:
21237 /* Three things may happen now:
21238 a) We should increment current it block size;
21239 b) We should close current it block (closing insn or 4 insns);
21240 c) We should close current it block and start a new one (due
21241 to incompatible conditions or
21242 4 insns-length block reached). */
21244 switch (inst.pred_insn_type)
21246 case INSIDE_VPT_INSN:
21248 case MVE_UNPREDICABLE_INSN:
21249 case MVE_OUTSIDE_PRED_INSN:
21251 case OUTSIDE_PRED_INSN:
21252 /* The closure of the block shall happen immediately,
21253 so any in_pred_block () call reports the block as closed. */
21254 force_automatic_it_block_close ();
21257 case INSIDE_IT_INSN:
21258 case INSIDE_IT_LAST_INSN:
21259 case IF_INSIDE_IT_LAST_INSN:
21260 now_pred.block_length++;
21262 if (now_pred.block_length > 4
21263 || !now_pred_compatible (inst.cond))
21265 force_automatic_it_block_close ();
21266 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
21267 new_automatic_it_block (inst.cond);
21271 now_pred.insn_cond = TRUE;
21272 now_pred_add_mask (inst.cond);
21275 if (now_pred.state == AUTOMATIC_PRED_BLOCK
21276 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
21277 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
21278 close_automatic_it_block ();
21281 case NEUTRAL_IT_INSN:
21282 now_pred.block_length++;
21283 now_pred.insn_cond = TRUE;
21285 if (now_pred.block_length > 4)
21286 force_automatic_it_block_close ();
21288 now_pred_add_mask (now_pred.cc & 1);
21292 close_automatic_it_block ();
21293 now_pred.state = MANUAL_PRED_BLOCK;
21298 case MANUAL_PRED_BLOCK:
21301 if (now_pred.type == SCALAR_PRED)
21303 /* Check conditional suffixes. */
21304 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
21305 now_pred.mask <<= 1;
21306 now_pred.mask &= 0x1f;
21307 is_last = (now_pred.mask == 0x10);
21311 now_pred.cc ^= (now_pred.mask >> 4);
21312 cond = now_pred.cc + 0xf;
21313 now_pred.mask <<= 1;
21314 now_pred.mask &= 0x1f;
21315 is_last = now_pred.mask == 0x10;
21317 now_pred.insn_cond = TRUE;
21319 switch (inst.pred_insn_type)
21321 case OUTSIDE_PRED_INSN:
21322 if (now_pred.type == SCALAR_PRED)
21324 if (inst.cond == COND_ALWAYS)
21326 /* Case 12: In an IT block, with no code: error: missing
21328 inst.error = BAD_NOT_IT;
21331 else if (inst.cond > COND_ALWAYS)
21333 /* Case 11: In an IT block, with a VPT code: syntax error.
21335 inst.error = BAD_SYNTAX;
21338 else if (thumb_mode)
21340 /* This is for some special cases where a non-MVE
21341 instruction is not allowed in an IT block, such as cbz,
21342 but are put into one with a condition code.
21343 You could argue this should be a syntax error, but we
21344 gave the 'not allowed in IT block' diagnostic in the
21345 past so we will keep doing so. */
21346 inst.error = BAD_NOT_IT;
21353 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21354 as_tsktsk (MVE_NOT_VPT);
21357 case MVE_OUTSIDE_PRED_INSN:
21358 if (now_pred.type == SCALAR_PRED)
21360 if (inst.cond == COND_ALWAYS)
21362 /* Case 3: In an IT block, with no code: warning:
21364 as_tsktsk (MVE_NOT_IT);
21367 else if (inst.cond < COND_ALWAYS)
21369 /* Case 1: In an IT block, with an IT code: syntax error.
21371 inst.error = BAD_SYNTAX;
21379 if (inst.cond < COND_ALWAYS)
21381 /* Case 4: In a VPT block, with an IT code: syntax error.
21383 inst.error = BAD_SYNTAX;
21386 else if (inst.cond == COND_ALWAYS)
21388 /* Case 6: In a VPT block, with no code: error: missing
21390 inst.error = BAD_NOT_VPT;
21398 case MVE_UNPREDICABLE_INSN:
21399 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
21401 case INSIDE_IT_INSN:
21402 if (inst.cond > COND_ALWAYS)
21404 /* Case 11: In an IT block, with a VPT code: syntax error. */
21405 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21406 inst.error = BAD_SYNTAX;
21409 else if (now_pred.type == SCALAR_PRED)
21411 /* Case 10: In an IT block, with an IT code: OK! */
21412 if (cond != inst.cond)
21414 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
21421 /* Case 13: In a VPT block, with an IT code: error: should be
21423 inst.error = BAD_OUT_IT;
21428 case INSIDE_VPT_INSN:
21429 if (now_pred.type == SCALAR_PRED)
21431 /* Case 2: In an IT block, with a VPT code: error: must be in a
21433 inst.error = BAD_OUT_VPT;
21436 /* Case 5: In a VPT block, with a VPT code: OK! */
21437 else if (cond != inst.cond)
21439 inst.error = BAD_VPT_COND;
21443 case INSIDE_IT_LAST_INSN:
21444 case IF_INSIDE_IT_LAST_INSN:
21445 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
21447 /* Case 4: In a VPT block, with an IT code: syntax error. */
21448 /* Case 11: In an IT block, with a VPT code: syntax error. */
21449 inst.error = BAD_SYNTAX;
21452 else if (cond != inst.cond)
21454 inst.error = BAD_IT_COND;
21459 inst.error = BAD_BRANCH;
21464 case NEUTRAL_IT_INSN:
21465 /* The BKPT instruction is unconditional even in a IT or VPT
21470 if (now_pred.type == SCALAR_PRED)
21472 inst.error = BAD_IT_IT;
21475 /* fall through. */
21477 if (inst.cond == COND_ALWAYS)
21479 /* Executing a VPT/VPST instruction inside an IT block or a
21480 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21482 if (now_pred.type == SCALAR_PRED)
21483 as_tsktsk (MVE_NOT_IT);
21485 as_tsktsk (MVE_NOT_VPT);
21490 /* VPT/VPST do not accept condition codes. */
21491 inst.error = BAD_SYNTAX;
21502 struct depr_insn_mask
21504 unsigned long pattern;
21505 unsigned long mask;
21506 const char* description;
21509 /* List of 16-bit instruction patterns deprecated in an IT block in
21511 static const struct depr_insn_mask depr_it_insns[] = {
21512 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21513 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21514 { 0xa000, 0xb800, N_("ADR") },
21515 { 0x4800, 0xf800, N_("Literal loads") },
21516 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21517 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21518 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21519 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21520 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21525 it_fsm_post_encode (void)
21529 if (!now_pred.state_handled)
21530 handle_pred_state ();
21532 if (now_pred.insn_cond
21533 && !now_pred.warn_deprecated
21534 && warn_on_deprecated
21535 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
21536 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
21538 if (inst.instruction >= 0x10000)
21540 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21541 "performance deprecated in ARMv8-A and ARMv8-R"));
21542 now_pred.warn_deprecated = TRUE;
21546 const struct depr_insn_mask *p = depr_it_insns;
21548 while (p->mask != 0)
21550 if ((inst.instruction & p->mask) == p->pattern)
21552 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21553 "instructions of the following class are "
21554 "performance deprecated in ARMv8-A and "
21555 "ARMv8-R: %s"), p->description);
21556 now_pred.warn_deprecated = TRUE;
21564 if (now_pred.block_length > 1)
21566 as_tsktsk (_("IT blocks containing more than one conditional "
21567 "instruction are performance deprecated in ARMv8-A and "
21569 now_pred.warn_deprecated = TRUE;
21573 is_last = (now_pred.mask == 0x10);
21576 now_pred.state = OUTSIDE_PRED_BLOCK;
21582 force_automatic_it_block_close (void)
21584 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
21586 close_automatic_it_block ();
21587 now_pred.state = OUTSIDE_PRED_BLOCK;
21593 in_pred_block (void)
21595 if (!now_pred.state_handled)
21596 handle_pred_state ();
21598 return now_pred.state != OUTSIDE_PRED_BLOCK;
21601 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21602 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21603 here, hence the "known" in the function name. */
21606 known_t32_only_insn (const struct asm_opcode *opcode)
21608 /* Original Thumb-1 wide instruction. */
21609 if (opcode->tencode == do_t_blx
21610 || opcode->tencode == do_t_branch23
21611 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
21612 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
21615 /* Wide-only instruction added to ARMv8-M Baseline. */
21616 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
21617 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
21618 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
21619 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
21625 /* Whether wide instruction variant can be used if available for a valid OPCODE
21629 t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
21631 if (known_t32_only_insn (opcode))
21634 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21635 of variant T3 of B.W is checked in do_t_branch. */
21636 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
21637 && opcode->tencode == do_t_branch)
21640 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21641 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
21642 && opcode->tencode == do_t_mov_cmp
21643 /* Make sure CMP instruction is not affected. */
21644 && opcode->aencode == do_mov)
21647 /* Wide instruction variants of all instructions with narrow *and* wide
21648 variants become available with ARMv6t2. Other opcodes are either
21649 narrow-only or wide-only and are thus available if OPCODE is valid. */
21650 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
21653 /* OPCODE with narrow only instruction variant or wide variant not
21659 md_assemble (char *str)
21662 const struct asm_opcode * opcode;
21664 /* Align the previous label if needed. */
21665 if (last_label_seen != NULL)
21667 symbol_set_frag (last_label_seen, frag_now);
21668 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
21669 S_SET_SEGMENT (last_label_seen, now_seg);
21672 memset (&inst, '\0', sizeof (inst));
21674 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21675 inst.relocs[r].type = BFD_RELOC_UNUSED;
21677 opcode = opcode_lookup (&p);
21680 /* It wasn't an instruction, but it might be a register alias of
21681 the form alias .req reg, or a Neon .dn/.qn directive. */
21682 if (! create_register_alias (str, p)
21683 && ! create_neon_reg_alias (str, p))
21684 as_bad (_("bad instruction `%s'"), str);
21689 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
21690 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21692 /* The value which unconditional instructions should have in place of the
21693 condition field. */
21694 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
21698 arm_feature_set variant;
21700 variant = cpu_variant;
21701 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21702 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
21703 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
21704 /* Check that this instruction is supported for this CPU. */
21705 if (!opcode->tvariant
21706 || (thumb_mode == 1
21707 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
21709 if (opcode->tencode == do_t_swi)
21710 as_bad (_("SVC is not permitted on this architecture"));
21712 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
21715 if (inst.cond != COND_ALWAYS && !unified_syntax
21716 && opcode->tencode != do_t_branch)
21718 as_bad (_("Thumb does not support conditional execution"));
21722 /* Two things are addressed here:
21723 1) Implicit require narrow instructions on Thumb-1.
21724 This avoids relaxation accidentally introducing Thumb-2
21726 2) Reject wide instructions in non Thumb-2 cores.
21728 Only instructions with narrow and wide variants need to be handled
21729 but selecting all non wide-only instructions is easier. */
21730 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
21731 && !t32_insn_ok (variant, opcode))
21733 if (inst.size_req == 0)
21735 else if (inst.size_req == 4)
21737 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
21738 as_bad (_("selected processor does not support 32bit wide "
21739 "variant of instruction `%s'"), str);
21741 as_bad (_("selected processor does not support `%s' in "
21742 "Thumb-2 mode"), str);
21747 inst.instruction = opcode->tvalue;
21749 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
21751 /* Prepare the pred_insn_type for those encodings that don't set
21753 it_fsm_pre_encode ();
21755 opcode->tencode ();
21757 it_fsm_post_encode ();
21760 if (!(inst.error || inst.relax))
21762 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
21763 inst.size = (inst.instruction > 0xffff ? 4 : 2);
21764 if (inst.size_req && inst.size_req != inst.size)
21766 as_bad (_("cannot honor width suffix -- `%s'"), str);
21771 /* Something has gone badly wrong if we try to relax a fixed size
21773 gas_assert (inst.size_req == 0 || !inst.relax);
21775 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
21776 *opcode->tvariant);
21777 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21778 set those bits when Thumb-2 32-bit instructions are seen. The impact
21779 of relaxable instructions will be considered later after we finish all
21781 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
21782 variant = arm_arch_none;
21784 variant = cpu_variant;
21785 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
21786 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
21789 check_neon_suffixes;
21793 mapping_state (MAP_THUMB);
21796 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
21800 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21801 is_bx = (opcode->aencode == do_bx);
21803 /* Check that this instruction is supported for this CPU. */
21804 if (!(is_bx && fix_v4bx)
21805 && !(opcode->avariant &&
21806 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
21808 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
21813 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
21817 inst.instruction = opcode->avalue;
21818 if (opcode->tag == OT_unconditionalF)
21819 inst.instruction |= 0xFU << 28;
21821 inst.instruction |= inst.cond << 28;
21822 inst.size = INSN_SIZE;
21823 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
21825 it_fsm_pre_encode ();
21826 opcode->aencode ();
21827 it_fsm_post_encode ();
21829 /* Arm mode bx is marked as both v4T and v5 because it's still required
21830 on a hypothetical non-thumb v5 core. */
21832 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
21834 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
21835 *opcode->avariant);
21837 check_neon_suffixes;
21841 mapping_state (MAP_ARM);
21846 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21854 check_pred_blocks_finished (void)
21859 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
21860 if (seg_info (sect)->tc_segment_info_data.current_pred.state
21861 == MANUAL_PRED_BLOCK)
21863 if (now_pred.type == SCALAR_PRED)
21864 as_warn (_("section '%s' finished with an open IT block."),
21867 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21871 if (now_pred.state == MANUAL_PRED_BLOCK)
21873 if (now_pred.type == SCALAR_PRED)
21874 as_warn (_("file finished with an open IT block."));
21876 as_warn (_("file finished with an open VPT/VPST block."));
21881 /* Various frobbings of labels and their addresses. */
21884 arm_start_line_hook (void)
21886 last_label_seen = NULL;
21890 arm_frob_label (symbolS * sym)
21892 last_label_seen = sym;
21894 ARM_SET_THUMB (sym, thumb_mode);
21896 #if defined OBJ_COFF || defined OBJ_ELF
21897 ARM_SET_INTERWORK (sym, support_interwork);
21900 force_automatic_it_block_close ();
21902 /* Note - do not allow local symbols (.Lxxx) to be labelled
21903 as Thumb functions. This is because these labels, whilst
21904 they exist inside Thumb code, are not the entry points for
21905 possible ARM->Thumb calls. Also, these labels can be used
21906 as part of a computed goto or switch statement. eg gcc
21907 can generate code that looks like this:
21909 ldr r2, [pc, .Laaa]
21919 The first instruction loads the address of the jump table.
21920 The second instruction converts a table index into a byte offset.
21921 The third instruction gets the jump address out of the table.
21922 The fourth instruction performs the jump.
21924 If the address stored at .Laaa is that of a symbol which has the
21925 Thumb_Func bit set, then the linker will arrange for this address
21926 to have the bottom bit set, which in turn would mean that the
21927 address computation performed by the third instruction would end
21928 up with the bottom bit set. Since the ARM is capable of unaligned
21929 word loads, the instruction would then load the incorrect address
21930 out of the jump table, and chaos would ensue. */
21931 if (label_is_thumb_function_name
21932 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
21933 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
21935 /* When the address of a Thumb function is taken the bottom
21936 bit of that address should be set. This will allow
21937 interworking between Arm and Thumb functions to work
21940 THUMB_SET_FUNC (sym, 1);
21942 label_is_thumb_function_name = FALSE;
21945 dwarf2_emit_label (sym);
21949 arm_data_in_code (void)
21951 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
21953 *input_line_pointer = '/';
21954 input_line_pointer += 5;
21955 *input_line_pointer = 0;
21963 arm_canonicalize_symbol_name (char * name)
21967 if (thumb_mode && (len = strlen (name)) > 5
21968 && streq (name + len - 5, "/data"))
21969 *(name + len - 5) = 0;
21974 /* Table of all register names defined by default. The user can
21975 define additional names with .req. Note that all register names
21976 should appear in both upper and lowercase variants. Some registers
21977 also have mixed-case names. */
21979 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21980 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21981 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21982 #define REGSET(p,t) \
21983 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21984 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21985 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21986 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21987 #define REGSETH(p,t) \
21988 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21989 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21990 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21991 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21992 #define REGSET2(p,t) \
21993 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21994 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21995 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21996 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21997 #define SPLRBANK(base,bank,t) \
21998 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21999 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22000 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22001 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22002 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22003 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22005 static const struct reg_entry reg_names[] =
22007 /* ARM integer registers. */
22008 REGSET(r, RN), REGSET(R, RN),
22010 /* ATPCS synonyms. */
22011 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
22012 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
22013 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
22015 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
22016 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
22017 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
22019 /* Well-known aliases. */
22020 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
22021 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
22023 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
22024 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
22026 /* Defining the new Zero register from ARMv8.1-M. */
22030 /* Coprocessor numbers. */
22031 REGSET(p, CP), REGSET(P, CP),
22033 /* Coprocessor register numbers. The "cr" variants are for backward
22035 REGSET(c, CN), REGSET(C, CN),
22036 REGSET(cr, CN), REGSET(CR, CN),
22038 /* ARM banked registers. */
22039 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
22040 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
22041 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
22042 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
22043 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
22044 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
22045 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
22047 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
22048 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
22049 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
22050 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
22051 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
22052 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
22053 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
22054 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
22056 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
22057 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
22058 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
22059 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
22060 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
22061 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
22062 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
22063 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
22064 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
22066 /* FPA registers. */
22067 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
22068 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
22070 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
22071 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
22073 /* VFP SP registers. */
22074 REGSET(s,VFS), REGSET(S,VFS),
22075 REGSETH(s,VFS), REGSETH(S,VFS),
22077 /* VFP DP Registers. */
22078 REGSET(d,VFD), REGSET(D,VFD),
22079 /* Extra Neon DP registers. */
22080 REGSETH(d,VFD), REGSETH(D,VFD),
22082 /* Neon QP registers. */
22083 REGSET2(q,NQ), REGSET2(Q,NQ),
22085 /* VFP control registers. */
22086 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
22087 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
22088 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
22089 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
22090 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
22091 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
22092 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
22094 /* Maverick DSP coprocessor registers. */
22095 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
22096 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
22098 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
22099 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
22100 REGDEF(dspsc,0,DSPSC),
22102 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
22103 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
22104 REGDEF(DSPSC,0,DSPSC),
22106 /* iWMMXt data registers - p0, c0-15. */
22107 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
22109 /* iWMMXt control registers - p1, c0-3. */
22110 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
22111 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
22112 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
22113 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
22115 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22116 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
22117 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
22118 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
22119 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
22121 /* XScale accumulator registers. */
22122 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
22128 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22129 within psr_required_here. */
22130 static const struct asm_psr psrs[] =
22132 /* Backward compatibility notation. Note that "all" is no longer
22133 truly all possible PSR bits. */
22134 {"all", PSR_c | PSR_f},
22138 /* Individual flags. */
22144 /* Combinations of flags. */
22145 {"fs", PSR_f | PSR_s},
22146 {"fx", PSR_f | PSR_x},
22147 {"fc", PSR_f | PSR_c},
22148 {"sf", PSR_s | PSR_f},
22149 {"sx", PSR_s | PSR_x},
22150 {"sc", PSR_s | PSR_c},
22151 {"xf", PSR_x | PSR_f},
22152 {"xs", PSR_x | PSR_s},
22153 {"xc", PSR_x | PSR_c},
22154 {"cf", PSR_c | PSR_f},
22155 {"cs", PSR_c | PSR_s},
22156 {"cx", PSR_c | PSR_x},
22157 {"fsx", PSR_f | PSR_s | PSR_x},
22158 {"fsc", PSR_f | PSR_s | PSR_c},
22159 {"fxs", PSR_f | PSR_x | PSR_s},
22160 {"fxc", PSR_f | PSR_x | PSR_c},
22161 {"fcs", PSR_f | PSR_c | PSR_s},
22162 {"fcx", PSR_f | PSR_c | PSR_x},
22163 {"sfx", PSR_s | PSR_f | PSR_x},
22164 {"sfc", PSR_s | PSR_f | PSR_c},
22165 {"sxf", PSR_s | PSR_x | PSR_f},
22166 {"sxc", PSR_s | PSR_x | PSR_c},
22167 {"scf", PSR_s | PSR_c | PSR_f},
22168 {"scx", PSR_s | PSR_c | PSR_x},
22169 {"xfs", PSR_x | PSR_f | PSR_s},
22170 {"xfc", PSR_x | PSR_f | PSR_c},
22171 {"xsf", PSR_x | PSR_s | PSR_f},
22172 {"xsc", PSR_x | PSR_s | PSR_c},
22173 {"xcf", PSR_x | PSR_c | PSR_f},
22174 {"xcs", PSR_x | PSR_c | PSR_s},
22175 {"cfs", PSR_c | PSR_f | PSR_s},
22176 {"cfx", PSR_c | PSR_f | PSR_x},
22177 {"csf", PSR_c | PSR_s | PSR_f},
22178 {"csx", PSR_c | PSR_s | PSR_x},
22179 {"cxf", PSR_c | PSR_x | PSR_f},
22180 {"cxs", PSR_c | PSR_x | PSR_s},
22181 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
22182 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
22183 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
22184 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
22185 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
22186 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
22187 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
22188 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
22189 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
22190 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
22191 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
22192 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
22193 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
22194 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
22195 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
22196 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
22197 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
22198 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
22199 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
22200 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
22201 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
22202 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
22203 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
22204 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
22207 /* Table of V7M psr names. */
22208 static const struct asm_psr v7m_psrs[] =
22210 {"apsr", 0x0 }, {"APSR", 0x0 },
22211 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22212 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22213 {"psr", 0x3 }, {"PSR", 0x3 },
22214 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22215 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22216 {"epsr", 0x6 }, {"EPSR", 0x6 },
22217 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22218 {"msp", 0x8 }, {"MSP", 0x8 },
22219 {"psp", 0x9 }, {"PSP", 0x9 },
22220 {"msplim", 0xa }, {"MSPLIM", 0xa },
22221 {"psplim", 0xb }, {"PSPLIM", 0xb },
22222 {"primask", 0x10}, {"PRIMASK", 0x10},
22223 {"basepri", 0x11}, {"BASEPRI", 0x11},
22224 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22225 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22226 {"control", 0x14}, {"CONTROL", 0x14},
22227 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22228 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22229 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22230 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22231 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22232 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22233 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22234 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22235 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22238 /* Table of all shift-in-operand names. */
22239 static const struct asm_shift_name shift_names [] =
22241 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
22242 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
22243 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
22244 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
22245 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
22246 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
22247 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
22250 /* Table of all explicit relocation names. */
22252 static struct reloc_entry reloc_names[] =
22254 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
22255 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
22256 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
22257 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
22258 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
22259 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
22260 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
22261 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
22262 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
22263 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
22264 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
22265 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
22266 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
22267 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
22268 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
22269 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
22270 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
22271 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
22272 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
22273 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
22274 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22275 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22276 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
22277 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
22278 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
22279 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
22280 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
22284 /* Table of all conditional affixes. */
22285 static const struct asm_cond conds[] =
22289 {"cs", 0x2}, {"hs", 0x2},
22290 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22303 static const struct asm_cond vconds[] =
22309 #define UL_BARRIER(L,U,CODE,FEAT) \
22310 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22311 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22313 static struct asm_barrier_opt barrier_opt_names[] =
22315 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
22316 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
22317 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
22318 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
22319 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
22320 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
22321 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
22322 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
22323 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
22324 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
22325 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
22326 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
22327 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
22328 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
22329 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
22330 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
22335 /* Table of ARM-format instructions. */
22337 /* Macros for gluing together operand strings. N.B. In all cases
22338 other than OPS0, the trailing OP_stop comes from default
22339 zero-initialization of the unspecified elements of the array. */
22340 #define OPS0() { OP_stop, }
22341 #define OPS1(a) { OP_##a, }
22342 #define OPS2(a,b) { OP_##a,OP_##b, }
22343 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22344 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22345 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22346 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22348 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22349 This is useful when mixing operands for ARM and THUMB, i.e. using the
22350 MIX_ARM_THUMB_OPERANDS macro.
22351 In order to use these macros, prefix the number of operands with _
22353 #define OPS_1(a) { a, }
22354 #define OPS_2(a,b) { a,b, }
22355 #define OPS_3(a,b,c) { a,b,c, }
22356 #define OPS_4(a,b,c,d) { a,b,c,d, }
22357 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22358 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22360 /* These macros abstract out the exact format of the mnemonic table and
22361 save some repeated characters. */
22363 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22364 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22365 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22366 THUMB_VARIANT, do_##ae, do_##te, 0 }
22368 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22369 a T_MNEM_xyz enumerator. */
22370 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22371 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22372 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22373 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22375 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22376 infix after the third character. */
22377 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22378 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22379 THUMB_VARIANT, do_##ae, do_##te, 0 }
22380 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22381 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22382 THUMB_VARIANT, do_##ae, do_##te, 0 }
22383 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22384 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22385 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22386 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22387 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22388 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22389 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22390 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22392 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22393 field is still 0xE. Many of the Thumb variants can be executed
22394 conditionally, so this is checked separately. */
22395 #define TUE(mnem, op, top, nops, ops, ae, te) \
22396 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22397 THUMB_VARIANT, do_##ae, do_##te, 0 }
22399 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22400 Used by mnemonics that have very minimal differences in the encoding for
22401 ARM and Thumb variants and can be handled in a common function. */
22402 #define TUEc(mnem, op, top, nops, ops, en) \
22403 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22404 THUMB_VARIANT, do_##en, do_##en, 0 }
22406 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22407 condition code field. */
22408 #define TUF(mnem, op, top, nops, ops, ae, te) \
22409 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22410 THUMB_VARIANT, do_##ae, do_##te, 0 }
22412 /* ARM-only variants of all the above. */
22413 #define CE(mnem, op, nops, ops, ae) \
22414 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22416 #define C3(mnem, op, nops, ops, ae) \
22417 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22419 /* Thumb-only variants of TCE and TUE. */
22420 #define ToC(mnem, top, nops, ops, te) \
22421 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22424 #define ToU(mnem, top, nops, ops, te) \
22425 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22428 /* T_MNEM_xyz enumerator variants of ToC. */
22429 #define toC(mnem, top, nops, ops, te) \
22430 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22433 /* T_MNEM_xyz enumerator variants of ToU. */
22434 #define toU(mnem, top, nops, ops, te) \
22435 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22438 /* Legacy mnemonics that always have conditional infix after the third
22440 #define CL(mnem, op, nops, ops, ae) \
22441 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22442 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22444 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22445 #define cCE(mnem, op, nops, ops, ae) \
22446 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22448 /* mov instructions that are shared between coprocessor and MVE. */
22449 #define mcCE(mnem, op, nops, ops, ae) \
22450 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22452 /* Legacy coprocessor instructions where conditional infix and conditional
22453 suffix are ambiguous. For consistency this includes all FPA instructions,
22454 not just the potentially ambiguous ones. */
22455 #define cCL(mnem, op, nops, ops, ae) \
22456 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22457 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22459 /* Coprocessor, takes either a suffix or a position-3 infix
22460 (for an FPA corner case). */
22461 #define C3E(mnem, op, nops, ops, ae) \
22462 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22463 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22465 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22466 { m1 #m2 m3, OPS##nops ops, \
22467 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22468 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22470 #define CM(m1, m2, op, nops, ops, ae) \
22471 xCM_ (m1, , m2, op, nops, ops, ae), \
22472 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22473 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22474 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22475 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22476 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22477 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22478 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22479 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22480 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22481 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22482 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22483 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22484 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22485 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22486 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22487 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22488 xCM_ (m1, le, m2, op, nops, ops, ae), \
22489 xCM_ (m1, al, m2, op, nops, ops, ae)
22491 #define UE(mnem, op, nops, ops, ae) \
22492 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22494 #define UF(mnem, op, nops, ops, ae) \
22495 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22497 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22498 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22499 use the same encoding function for each. */
22500 #define NUF(mnem, op, nops, ops, enc) \
22501 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22502 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22504 /* Neon data processing, version which indirects through neon_enc_tab for
22505 the various overloaded versions of opcodes. */
22506 #define nUF(mnem, op, nops, ops, enc) \
22507 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22508 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22510 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22512 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22513 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22514 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22516 #define NCE(mnem, op, nops, ops, enc) \
22517 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22519 #define NCEF(mnem, op, nops, ops, enc) \
22520 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22522 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22523 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22524 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22525 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22527 #define nCE(mnem, op, nops, ops, enc) \
22528 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22530 #define nCEF(mnem, op, nops, ops, enc) \
22531 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22534 #define mCEF(mnem, op, nops, ops, enc) \
22535 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22536 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22539 /* nCEF but for MVE predicated instructions. */
22540 #define mnCEF(mnem, op, nops, ops, enc) \
22541 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22543 /* nCE but for MVE predicated instructions. */
22544 #define mnCE(mnem, op, nops, ops, enc) \
22545 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22547 /* NUF but for potentially MVE predicated instructions. */
22548 #define MNUF(mnem, op, nops, ops, enc) \
22549 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22550 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22552 /* nUF but for potentially MVE predicated instructions. */
22553 #define mnUF(mnem, op, nops, ops, enc) \
22554 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22555 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22557 /* ToC but for potentially MVE predicated instructions. */
22558 #define mToC(mnem, top, nops, ops, te) \
22559 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22562 /* NCE but for MVE predicated instructions. */
22563 #define MNCE(mnem, op, nops, ops, enc) \
22564 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22566 /* NCEF but for MVE predicated instructions. */
22567 #define MNCEF(mnem, op, nops, ops, enc) \
22568 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22571 static const struct asm_opcode insns[] =
22573 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22574 #define THUMB_VARIANT & arm_ext_v4t
22575 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
22576 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
22577 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
22578 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
22579 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
22580 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
22581 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
22582 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
22583 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
22584 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
22585 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
22586 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
22587 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
22588 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
22589 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
22590 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
22592 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22593 for setting PSR flag bits. They are obsolete in V6 and do not
22594 have Thumb equivalents. */
22595 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
22596 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
22597 CL("tstp", 110f000, 2, (RR, SH), cmp),
22598 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
22599 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
22600 CL("cmpp", 150f000, 2, (RR, SH), cmp),
22601 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
22602 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
22603 CL("cmnp", 170f000, 2, (RR, SH), cmp),
22605 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
22606 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
22607 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
22608 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
22610 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
22611 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
22612 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
22614 OP_ADDRGLDR),ldst, t_ldst),
22615 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
22617 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22618 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22619 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22620 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22621 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22622 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22624 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
22625 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
22628 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
22629 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
22630 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
22631 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
22633 /* Thumb-compatibility pseudo ops. */
22634 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
22635 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
22636 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
22637 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
22638 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
22639 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
22640 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
22641 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
22642 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
22643 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
22644 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
22645 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
22647 /* These may simplify to neg. */
22648 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
22649 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
22651 #undef THUMB_VARIANT
22652 #define THUMB_VARIANT & arm_ext_os
22654 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
22655 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
22657 #undef THUMB_VARIANT
22658 #define THUMB_VARIANT & arm_ext_v6
22660 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
22662 /* V1 instructions with no Thumb analogue prior to V6T2. */
22663 #undef THUMB_VARIANT
22664 #define THUMB_VARIANT & arm_ext_v6t2
22666 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
22667 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
22668 CL("teqp", 130f000, 2, (RR, SH), cmp),
22670 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22671 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22672 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
22673 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22675 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22676 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22678 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22679 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22681 /* V1 instructions with no Thumb analogue at all. */
22682 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
22683 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
22685 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
22686 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
22687 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
22688 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
22689 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
22690 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
22691 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
22692 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
22695 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22696 #undef THUMB_VARIANT
22697 #define THUMB_VARIANT & arm_ext_v4t
22699 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
22700 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
22702 #undef THUMB_VARIANT
22703 #define THUMB_VARIANT & arm_ext_v6t2
22705 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
22706 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
22708 /* Generic coprocessor instructions. */
22709 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
22710 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22711 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22712 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22713 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22714 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22715 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
22718 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22720 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
22721 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
22724 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22725 #undef THUMB_VARIANT
22726 #define THUMB_VARIANT & arm_ext_msr
22728 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
22729 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
22732 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22733 #undef THUMB_VARIANT
22734 #define THUMB_VARIANT & arm_ext_v6t2
22736 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22737 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22738 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22739 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22740 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22741 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22742 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22743 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22746 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22747 #undef THUMB_VARIANT
22748 #define THUMB_VARIANT & arm_ext_v4t
22750 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22751 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22752 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22753 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22754 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22755 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22758 #define ARM_VARIANT & arm_ext_v4t_5
22760 /* ARM Architecture 4T. */
22761 /* Note: bx (and blx) are required on V5, even if the processor does
22762 not support Thumb. */
22763 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
22766 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22767 #undef THUMB_VARIANT
22768 #define THUMB_VARIANT & arm_ext_v5t
22770 /* Note: blx has 2 variants; the .value coded here is for
22771 BLX(2). Only this variant has conditional execution. */
22772 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
22773 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
22775 #undef THUMB_VARIANT
22776 #define THUMB_VARIANT & arm_ext_v6t2
22778 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
22779 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22780 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22781 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22782 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22783 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
22784 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22785 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22788 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22789 #undef THUMB_VARIANT
22790 #define THUMB_VARIANT & arm_ext_v5exp
22792 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22793 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22794 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22795 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22797 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22798 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22800 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22801 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22802 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22803 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22805 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22806 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22807 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22808 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22810 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22811 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22813 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22814 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22815 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22816 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22819 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22820 #undef THUMB_VARIANT
22821 #define THUMB_VARIANT & arm_ext_v6t2
22823 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
22824 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
22826 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
22827 ADDRGLDRS), ldrd, t_ldstd),
22829 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22830 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22833 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22835 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
22838 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22839 #undef THUMB_VARIANT
22840 #define THUMB_VARIANT & arm_ext_v6
22842 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
22843 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
22844 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22845 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22846 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22847 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22848 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22849 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22850 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22851 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
22853 #undef THUMB_VARIANT
22854 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22856 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
22857 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
22859 #undef THUMB_VARIANT
22860 #define THUMB_VARIANT & arm_ext_v6t2
22862 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22863 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22865 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
22866 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
22868 /* ARM V6 not included in V7M. */
22869 #undef THUMB_VARIANT
22870 #define THUMB_VARIANT & arm_ext_v6_notm
22871 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22872 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22873 UF(rfeib, 9900a00, 1, (RRw), rfe),
22874 UF(rfeda, 8100a00, 1, (RRw), rfe),
22875 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
22876 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22877 UF(rfefa, 8100a00, 1, (RRw), rfe),
22878 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
22879 UF(rfeed, 9900a00, 1, (RRw), rfe),
22880 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22881 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22882 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22883 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
22884 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
22885 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
22886 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
22887 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
22888 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
22889 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
22891 /* ARM V6 not included in V7M (eg. integer SIMD). */
22892 #undef THUMB_VARIANT
22893 #define THUMB_VARIANT & arm_ext_v6_dsp
22894 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
22895 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
22896 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22897 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22898 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22899 /* Old name for QASX. */
22900 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22901 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22902 /* Old name for QSAX. */
22903 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22904 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22905 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22906 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22907 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22908 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22909 /* Old name for SASX. */
22910 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22911 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22912 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22913 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22914 /* Old name for SHASX. */
22915 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22916 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22917 /* Old name for SHSAX. */
22918 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22919 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22920 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22921 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22922 /* Old name for SSAX. */
22923 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22924 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22925 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22926 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22927 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22928 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22929 /* Old name for UASX. */
22930 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22931 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22932 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22933 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22934 /* Old name for UHASX. */
22935 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22936 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22937 /* Old name for UHSAX. */
22938 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22939 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22940 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22941 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22942 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22943 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22944 /* Old name for UQASX. */
22945 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22946 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22947 /* Old name for UQSAX. */
22948 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22949 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22950 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22951 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22952 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22953 /* Old name for USAX. */
22954 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22955 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22956 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22957 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22958 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22959 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22960 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22961 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22962 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22963 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22964 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22965 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22966 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22967 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22968 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22969 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22970 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22971 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22972 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22973 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22974 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22975 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22976 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22977 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22978 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22979 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22980 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22981 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22982 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22983 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
22984 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
22985 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22986 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22987 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
22990 #define ARM_VARIANT & arm_ext_v6k_v6t2
22991 #undef THUMB_VARIANT
22992 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22994 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
22995 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
22996 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
22997 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
22999 #undef THUMB_VARIANT
23000 #define THUMB_VARIANT & arm_ext_v6_notm
23001 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
23003 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
23004 RRnpcb), strexd, t_strexd),
23006 #undef THUMB_VARIANT
23007 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23008 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
23010 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
23012 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23014 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23016 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
23019 #define ARM_VARIANT & arm_ext_sec
23020 #undef THUMB_VARIANT
23021 #define THUMB_VARIANT & arm_ext_sec
23023 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
23026 #define ARM_VARIANT & arm_ext_virt
23027 #undef THUMB_VARIANT
23028 #define THUMB_VARIANT & arm_ext_virt
23030 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
23031 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
23034 #define ARM_VARIANT & arm_ext_pan
23035 #undef THUMB_VARIANT
23036 #define THUMB_VARIANT & arm_ext_pan
23038 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
23041 #define ARM_VARIANT & arm_ext_v6t2
23042 #undef THUMB_VARIANT
23043 #define THUMB_VARIANT & arm_ext_v6t2
23045 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
23046 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
23047 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23048 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23050 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
23051 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
23053 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23054 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23055 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23056 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23059 #define ARM_VARIANT & arm_ext_v3
23060 #undef THUMB_VARIANT
23061 #define THUMB_VARIANT & arm_ext_v6t2
23063 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
23064 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
23065 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
23068 #define ARM_VARIANT & arm_ext_v6t2
23069 #undef THUMB_VARIANT
23070 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23071 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
23072 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
23074 /* Thumb-only instructions. */
23076 #define ARM_VARIANT NULL
23077 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
23078 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
23080 /* ARM does not really have an IT instruction, so always allow it.
23081 The opcode is copied from Thumb in order to allow warnings in
23082 -mimplicit-it=[never | arm] modes. */
23084 #define ARM_VARIANT & arm_ext_v1
23085 #undef THUMB_VARIANT
23086 #define THUMB_VARIANT & arm_ext_v6t2
23088 TUE("it", bf08, bf08, 1, (COND), it, t_it),
23089 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
23090 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
23091 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
23092 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
23093 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
23094 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
23095 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
23096 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
23097 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
23098 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
23099 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
23100 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
23101 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
23102 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
23103 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23104 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
23105 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
23107 /* Thumb2 only instructions. */
23109 #define ARM_VARIANT NULL
23111 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23112 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23113 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
23114 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
23115 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
23116 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
23118 /* Hardware division instructions. */
23120 #define ARM_VARIANT & arm_ext_adiv
23121 #undef THUMB_VARIANT
23122 #define THUMB_VARIANT & arm_ext_div
23124 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
23125 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
23127 /* ARM V6M/V7 instructions. */
23129 #define ARM_VARIANT & arm_ext_barrier
23130 #undef THUMB_VARIANT
23131 #define THUMB_VARIANT & arm_ext_barrier
23133 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
23134 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
23135 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
23137 /* ARM V7 instructions. */
23139 #define ARM_VARIANT & arm_ext_v7
23140 #undef THUMB_VARIANT
23141 #define THUMB_VARIANT & arm_ext_v7
23143 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
23144 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
23147 #define ARM_VARIANT & arm_ext_mp
23148 #undef THUMB_VARIANT
23149 #define THUMB_VARIANT & arm_ext_mp
23151 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
23153 /* AArchv8 instructions. */
23155 #define ARM_VARIANT & arm_ext_v8
23157 /* Instructions shared between armv8-a and armv8-m. */
23158 #undef THUMB_VARIANT
23159 #define THUMB_VARIANT & arm_ext_atomics
23161 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23162 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23163 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23164 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23165 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23166 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23167 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23168 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
23169 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23170 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
23172 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
23174 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
23176 #undef THUMB_VARIANT
23177 #define THUMB_VARIANT & arm_ext_v8
23179 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
23180 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
23182 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
23185 /* Defined in V8 but is in undefined encoding space for earlier
23186 architectures. However earlier architectures are required to treat
23187 this instuction as a semihosting trap as well. Hence while not explicitly
23188 defined as such, it is in fact correct to define the instruction for all
23190 #undef THUMB_VARIANT
23191 #define THUMB_VARIANT & arm_ext_v1
23193 #define ARM_VARIANT & arm_ext_v1
23194 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
23196 /* ARMv8 T32 only. */
23198 #define ARM_VARIANT NULL
23199 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
23200 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
23201 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
23203 /* FP for ARMv8. */
23205 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23206 #undef THUMB_VARIANT
23207 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23209 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
23210 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
23211 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
23212 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
23213 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
23214 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
23215 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
23216 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
23217 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
23218 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
23219 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
23221 /* Crypto v1 extensions. */
23223 #define ARM_VARIANT & fpu_crypto_ext_armv8
23224 #undef THUMB_VARIANT
23225 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23227 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
23228 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
23229 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
23230 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
23231 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
23232 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
23233 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
23234 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
23235 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
23236 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
23237 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
23238 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
23239 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
23240 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
23243 #define ARM_VARIANT & crc_ext_armv8
23244 #undef THUMB_VARIANT
23245 #define THUMB_VARIANT & crc_ext_armv8
23246 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
23247 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
23248 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
23249 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
23250 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
23251 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
23253 /* ARMv8.2 RAS extension. */
23255 #define ARM_VARIANT & arm_ext_ras
23256 #undef THUMB_VARIANT
23257 #define THUMB_VARIANT & arm_ext_ras
23258 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
23261 #define ARM_VARIANT & arm_ext_v8_3
23262 #undef THUMB_VARIANT
23263 #define THUMB_VARIANT & arm_ext_v8_3
23264 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
23267 #define ARM_VARIANT & fpu_neon_ext_dotprod
23268 #undef THUMB_VARIANT
23269 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23270 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
23271 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
23274 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23275 #undef THUMB_VARIANT
23276 #define THUMB_VARIANT NULL
23278 cCE("wfs", e200110, 1, (RR), rd),
23279 cCE("rfs", e300110, 1, (RR), rd),
23280 cCE("wfc", e400110, 1, (RR), rd),
23281 cCE("rfc", e500110, 1, (RR), rd),
23283 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
23284 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
23285 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
23286 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
23288 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
23289 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
23290 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
23291 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
23293 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
23294 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
23295 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
23296 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
23297 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
23298 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
23299 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
23300 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
23301 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
23302 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
23303 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
23304 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
23306 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
23307 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
23308 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
23309 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
23310 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
23311 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
23312 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
23313 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
23314 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
23315 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
23316 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
23317 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
23319 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
23320 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
23321 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
23322 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
23323 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
23324 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
23325 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
23326 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
23327 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
23328 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
23329 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
23330 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
23332 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
23333 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
23334 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
23335 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
23336 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
23337 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
23338 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
23339 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
23340 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
23341 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
23342 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
23343 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
23345 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
23346 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
23347 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
23348 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
23349 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
23350 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
23351 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
23352 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
23353 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
23354 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
23355 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
23356 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
23358 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
23359 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
23360 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
23361 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
23362 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
23363 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
23364 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
23365 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
23366 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
23367 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
23368 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
23369 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
23371 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
23372 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
23373 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
23374 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
23375 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
23376 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
23377 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
23378 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
23379 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
23380 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
23381 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
23382 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
23384 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
23385 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
23386 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
23387 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
23388 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
23389 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
23390 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
23391 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
23392 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
23393 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
23394 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
23395 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
23397 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
23398 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
23399 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
23400 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
23401 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
23402 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
23403 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
23404 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
23405 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
23406 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
23407 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
23408 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
23410 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
23411 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
23412 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
23413 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
23414 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
23415 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
23416 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
23417 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
23418 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
23419 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
23420 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
23421 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
23423 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
23424 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
23425 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
23426 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
23427 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
23428 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
23429 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
23430 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
23431 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
23432 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
23433 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
23434 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
23436 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
23437 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
23438 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
23439 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
23440 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
23441 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
23442 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
23443 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
23444 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
23445 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
23446 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
23447 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
23449 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
23450 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
23451 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
23452 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
23453 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
23454 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
23455 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
23456 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
23457 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
23458 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
23459 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
23460 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
23462 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
23463 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
23464 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
23465 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
23466 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
23467 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
23468 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
23469 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
23470 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
23471 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
23472 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
23473 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
23475 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
23476 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
23477 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
23478 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
23479 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
23480 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
23481 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
23482 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
23483 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
23484 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
23485 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
23486 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
23488 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
23489 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
23490 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
23491 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
23492 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
23493 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
23494 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
23495 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
23496 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
23497 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
23498 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
23499 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
23501 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
23502 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
23503 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
23504 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
23505 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
23506 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23507 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23508 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23509 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
23510 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
23511 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
23512 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
23514 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
23515 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
23516 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
23517 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
23518 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
23519 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23520 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23521 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23522 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
23523 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
23524 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
23525 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
23527 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
23528 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
23529 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
23530 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
23531 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
23532 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23533 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23534 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23535 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
23536 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
23537 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
23538 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
23540 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
23541 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
23542 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
23543 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
23544 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
23545 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23546 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23547 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23548 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
23549 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
23550 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
23551 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
23553 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
23554 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
23555 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
23556 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
23557 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
23558 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23559 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23560 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23561 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
23562 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
23563 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
23564 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
23566 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
23567 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
23568 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
23569 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
23570 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
23571 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23572 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23573 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23574 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
23575 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
23576 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
23577 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
23579 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
23580 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
23581 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
23582 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
23583 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
23584 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23585 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23586 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23587 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
23588 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
23589 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
23590 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
23592 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
23593 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
23594 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
23595 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
23596 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
23597 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23598 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23599 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23600 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
23601 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
23602 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
23603 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
23605 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
23606 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
23607 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
23608 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
23609 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
23610 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23611 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23612 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23613 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
23614 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
23615 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
23616 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
23618 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
23619 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
23620 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
23621 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
23622 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
23623 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23624 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23625 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23626 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
23627 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
23628 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
23629 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
23631 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23632 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23633 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23634 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23635 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23636 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23637 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23638 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23639 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23640 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23641 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23642 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23644 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23645 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23646 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23647 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23648 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23649 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23650 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23651 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23652 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23653 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23654 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23655 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23657 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23658 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23659 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23660 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23661 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23662 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23663 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23664 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23665 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23666 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23667 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23668 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23670 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
23671 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
23672 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
23673 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
23675 cCL("flts", e000110, 2, (RF, RR), rn_rd),
23676 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
23677 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
23678 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
23679 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
23680 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
23681 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
23682 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
23683 cCL("flte", e080110, 2, (RF, RR), rn_rd),
23684 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
23685 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
23686 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
23688 /* The implementation of the FIX instruction is broken on some
23689 assemblers, in that it accepts a precision specifier as well as a
23690 rounding specifier, despite the fact that this is meaningless.
23691 To be more compatible, we accept it as well, though of course it
23692 does not set any bits. */
23693 cCE("fix", e100110, 2, (RR, RF), rd_rm),
23694 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
23695 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
23696 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
23697 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
23698 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
23699 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
23700 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
23701 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
23702 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
23703 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
23704 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
23705 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
23707 /* Instructions that were new with the real FPA, call them V2. */
23709 #define ARM_VARIANT & fpu_fpa_ext_v2
23711 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23712 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23713 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23714 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23715 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23716 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23719 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23721 /* Moves and type conversions. */
23722 cCE("fmstat", ef1fa10, 0, (), noargs),
23723 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
23724 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
23725 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
23726 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
23727 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
23728 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
23729 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
23730 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
23731 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
23732 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
23734 /* Memory operations. */
23735 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
23736 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
23737 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23738 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23739 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23740 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23741 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23742 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23743 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23744 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23745 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23746 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23747 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23748 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23749 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23750 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23751 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23752 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23754 /* Monadic operations. */
23755 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
23756 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
23757 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
23759 /* Dyadic operations. */
23760 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23761 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23762 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23763 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23764 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23765 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23766 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23767 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23768 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23771 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
23772 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
23773 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
23774 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
23776 /* Double precision load/store are still present on single precision
23777 implementations. */
23778 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
23779 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
23780 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23781 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23782 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23783 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23784 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23785 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23786 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23787 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23790 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23792 /* Moves and type conversions. */
23793 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
23794 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23795 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
23796 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
23797 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
23798 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
23799 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
23800 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
23801 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
23802 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23803 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
23804 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23806 /* Monadic operations. */
23807 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23808 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
23809 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23811 /* Dyadic operations. */
23812 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23813 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23814 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23815 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23816 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23817 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23818 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23819 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23820 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23823 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
23824 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
23825 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23826 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
23828 /* Instructions which may belong to either the Neon or VFP instruction sets.
23829 Individual encoder functions perform additional architecture checks. */
23831 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23832 #undef THUMB_VARIANT
23833 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23835 /* These mnemonics are unique to VFP. */
23836 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
23837 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
23838 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23839 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23840 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23841 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
23842 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
23843 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
23845 /* Mnemonics shared by Neon and VFP. */
23846 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
23848 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23849 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23850 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23851 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23852 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23853 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23855 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
23856 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
23857 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
23858 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
23861 /* NOTE: All VMOV encoding is special-cased! */
23862 NCE(vmovq, 0, 1, (VMOV), neon_mov),
23864 #undef THUMB_VARIANT
23865 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23866 by different feature bits. Since we are setting the Thumb guard, we can
23867 require Thumb-1 which makes it a nop guard and set the right feature bit in
23868 do_vldr_vstr (). */
23869 #define THUMB_VARIANT & arm_ext_v4t
23870 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
23871 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
23874 #define ARM_VARIANT & arm_ext_fp16
23875 #undef THUMB_VARIANT
23876 #define THUMB_VARIANT & arm_ext_fp16
23877 /* New instructions added from v8.2, allowing the extraction and insertion of
23878 the upper 16 bits of a 32-bit vector register. */
23879 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
23880 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
23882 /* New backported fma/fms instructions optional in v8.2. */
23883 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
23884 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
23886 #undef THUMB_VARIANT
23887 #define THUMB_VARIANT & fpu_neon_ext_v1
23889 #define ARM_VARIANT & fpu_neon_ext_v1
23891 /* Data processing with three registers of the same length. */
23892 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23893 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
23894 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
23895 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23896 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23897 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23898 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23899 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
23900 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
23901 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
23902 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
23903 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
23904 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
23905 /* If not immediate, fall back to neon_dyadic_i64_su.
23906 shl_imm should accept I8 I16 I32 I64,
23907 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23908 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
23909 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
23910 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
23911 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
23912 /* Logic ops, types optional & ignored. */
23913 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23914 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23915 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23916 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23917 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
23918 /* Bitfield ops, untyped. */
23919 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23920 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23921 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23922 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23923 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23924 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23925 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23926 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23927 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23928 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23929 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23930 back to neon_dyadic_if_su. */
23931 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
23932 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
23933 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
23934 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
23935 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
23936 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
23937 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
23938 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
23939 /* Comparison. Type I8 I16 I32 F32. */
23940 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
23941 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
23942 /* As above, D registers only. */
23943 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
23944 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
23945 /* Int and float variants, signedness unimportant. */
23946 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
23947 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
23948 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
23949 /* Add/sub take types I8 I16 I32 I64 F32. */
23950 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
23951 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
23952 /* vtst takes sizes 8, 16, 32. */
23953 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
23954 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
23955 /* VMUL takes I8 I16 I32 F32 P8. */
23956 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
23957 /* VQD{R}MULH takes S16 S32. */
23958 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
23959 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
23960 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
23961 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
23962 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
23963 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
23964 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
23965 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
23966 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
23967 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
23968 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
23969 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
23970 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
23971 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
23972 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
23973 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
23974 /* ARM v8.1 extension. */
23975 nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
23976 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
23977 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
23978 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
23980 /* Two address, int/float. Types S8 S16 S32 F32. */
23981 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
23982 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
23984 /* Data processing with two registers and a shift amount. */
23985 /* Right shifts, and variants with rounding.
23986 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23987 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
23988 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
23989 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
23990 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
23991 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
23992 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
23993 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
23994 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
23995 /* Shift and insert. Sizes accepted 8 16 32 64. */
23996 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
23997 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
23998 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
23999 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
24000 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24001 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
24002 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
24003 /* Right shift immediate, saturating & narrowing, with rounding variants.
24004 Types accepted S16 S32 S64 U16 U32 U64. */
24005 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24006 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24007 /* As above, unsigned. Types accepted S16 S32 S64. */
24008 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24009 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24010 /* Right shift narrowing. Types accepted I16 I32 I64. */
24011 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24012 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24013 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24014 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
24015 /* CVT with optional immediate for fixed-point variant. */
24016 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
24018 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
24019 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
24021 /* Data processing, three registers of different lengths. */
24022 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24023 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
24024 /* If not scalar, fall back to neon_dyadic_long.
24025 Vector types as above, scalar types S16 S32 U16 U32. */
24026 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24027 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24028 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24029 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24030 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24031 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24032 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24033 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24034 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24035 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24036 /* Saturating doubling multiplies. Types S16 S32. */
24037 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24038 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24039 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24040 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24041 S16 S32 U16 U32. */
24042 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
24044 /* Extract. Size 8. */
24045 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
24046 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
24048 /* Two registers, miscellaneous. */
24049 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24050 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
24051 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
24052 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
24053 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
24054 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
24055 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
24056 /* Vector replicate. Sizes 8 16 32. */
24057 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
24058 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24059 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
24060 /* VMOVN. Types I16 I32 I64. */
24061 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
24062 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24063 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
24064 /* VQMOVUN. Types S16 S32 S64. */
24065 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
24066 /* VZIP / VUZP. Sizes 8 16 32. */
24067 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
24068 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
24069 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
24070 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
24071 /* VQABS / VQNEG. Types S8 S16 S32. */
24072 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
24073 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
24074 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
24075 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
24076 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24077 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
24078 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
24079 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
24080 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
24081 /* Reciprocal estimates. Types U32 F16 F32. */
24082 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
24083 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
24084 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
24085 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
24086 /* VCLS. Types S8 S16 S32. */
24087 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
24088 /* VCLZ. Types I8 I16 I32. */
24089 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
24090 /* VCNT. Size 8. */
24091 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
24092 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
24093 /* Two address, untyped. */
24094 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
24095 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
24096 /* VTRN. Sizes 8 16 32. */
24097 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
24098 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
24100 /* Table lookup. Size 8. */
24101 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24102 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24104 #undef THUMB_VARIANT
24105 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24107 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24109 /* Neon element/structure load/store. */
24110 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24111 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24112 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24113 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24114 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24115 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24116 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24117 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24119 #undef THUMB_VARIANT
24120 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24122 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24123 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
24124 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24125 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24126 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24127 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24128 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24129 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24130 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24131 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24133 #undef THUMB_VARIANT
24134 #define THUMB_VARIANT & fpu_vfp_ext_v3
24136 #define ARM_VARIANT & fpu_vfp_ext_v3
24138 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
24139 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24140 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24141 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24142 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24143 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24144 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24145 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24146 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24149 #define ARM_VARIANT & fpu_vfp_ext_fma
24150 #undef THUMB_VARIANT
24151 #define THUMB_VARIANT & fpu_vfp_ext_fma
24152 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24153 VFP FMA variant; NEON and VFP FMA always includes the NEON
24154 FMA instructions. */
24155 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
24156 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
24158 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24159 the v form should always be used. */
24160 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24161 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24162 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24163 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24164 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24165 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24167 #undef THUMB_VARIANT
24169 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24171 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24172 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24173 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24174 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24175 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24176 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24177 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
24178 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
24181 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24183 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
24184 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
24185 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
24186 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
24187 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
24188 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
24189 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
24190 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
24191 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
24192 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24193 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24194 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24195 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24196 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24197 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24198 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24199 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24200 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24201 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
24202 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
24203 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24204 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24205 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24206 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24207 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24208 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24209 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
24210 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
24211 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
24212 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
24213 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
24214 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
24215 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
24216 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
24217 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
24218 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
24219 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
24220 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24221 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24222 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24223 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24224 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24225 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24226 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24227 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24228 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24229 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
24230 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24231 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24232 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24233 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24234 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24235 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24236 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24237 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24238 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24239 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24240 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24241 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24242 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24243 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24244 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24245 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24246 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24247 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24248 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24249 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24250 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24251 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24252 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24253 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24254 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24255 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24256 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24257 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24258 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24259 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24260 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24261 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24262 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24263 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24264 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24265 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24266 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24267 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24268 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24269 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24270 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24271 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
24272 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24273 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24274 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24275 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24276 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24277 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24278 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24279 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24280 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24281 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24282 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24283 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24284 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24285 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24286 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24287 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24288 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24289 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24290 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24291 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24292 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24293 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
24294 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24295 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24296 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24297 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24298 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24299 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24300 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24301 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24302 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24303 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24304 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24305 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24306 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24307 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24308 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24309 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24310 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24311 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24312 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24313 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24314 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24315 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24316 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24317 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24318 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24319 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24320 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24321 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24322 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24323 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24324 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24325 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
24326 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
24327 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
24328 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
24329 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
24330 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
24331 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24332 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24333 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24334 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
24335 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
24336 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
24337 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
24338 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
24339 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
24340 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24341 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24342 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24343 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24344 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
24347 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24349 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
24350 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
24351 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
24352 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
24353 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
24354 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
24355 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24356 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24357 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24358 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24359 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24360 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24361 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24362 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24363 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24364 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24365 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24366 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24367 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24368 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24369 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
24370 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24371 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24372 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24373 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24374 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24375 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24376 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24377 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24378 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24379 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24380 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24381 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24382 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24383 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24384 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24385 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24386 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24387 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24388 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24389 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24390 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24391 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24392 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24393 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24394 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24395 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24396 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24397 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24398 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24399 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24400 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24401 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24402 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24403 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24404 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24405 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24408 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24410 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24411 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24412 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24413 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24414 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24415 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24416 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24417 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24418 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
24419 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
24420 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
24421 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
24422 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
24423 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
24424 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
24425 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
24426 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
24427 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
24428 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
24429 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
24430 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
24431 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
24432 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
24433 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
24434 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
24435 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
24436 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
24437 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
24438 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
24439 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
24440 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
24441 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
24442 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
24443 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
24444 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
24445 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
24446 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
24447 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
24448 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
24449 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
24450 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
24451 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
24452 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
24453 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
24454 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
24455 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
24456 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
24457 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
24458 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
24459 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
24460 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
24461 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
24462 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
24463 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
24464 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
24465 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
24466 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
24467 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
24468 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
24469 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
24470 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
24471 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
24472 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
24473 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
24474 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24475 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24476 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24477 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24478 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24479 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24480 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24481 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24482 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24483 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24484 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24485 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24487 /* ARMv8.5-A instructions. */
24489 #define ARM_VARIANT & arm_ext_sb
24490 #undef THUMB_VARIANT
24491 #define THUMB_VARIANT & arm_ext_sb
24492 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
24495 #define ARM_VARIANT & arm_ext_predres
24496 #undef THUMB_VARIANT
24497 #define THUMB_VARIANT & arm_ext_predres
24498 CE("cfprctx", e070f93, 1, (RRnpc), rd),
24499 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
24500 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
24502 /* ARMv8-M instructions. */
24504 #define ARM_VARIANT NULL
24505 #undef THUMB_VARIANT
24506 #define THUMB_VARIANT & arm_ext_v8m
24507 ToU("sg", e97fe97f, 0, (), noargs),
24508 ToC("blxns", 4784, 1, (RRnpc), t_blx),
24509 ToC("bxns", 4704, 1, (RRnpc), t_bx),
24510 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
24511 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
24512 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
24513 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
24515 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24516 instructions behave as nop if no VFP is present. */
24517 #undef THUMB_VARIANT
24518 #define THUMB_VARIANT & arm_ext_v8m_main
24519 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
24520 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
24522 /* Armv8.1-M Mainline instructions. */
24523 #undef THUMB_VARIANT
24524 #define THUMB_VARIANT & arm_ext_v8_1m_main
24525 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
24526 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
24527 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
24528 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
24529 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
24531 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
24532 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
24533 toU("le", _le, 2, (oLR, EXP), t_loloop),
24535 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
24536 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
24538 #undef THUMB_VARIANT
24539 #define THUMB_VARIANT & mve_ext
24541 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24542 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24543 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24544 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24545 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24546 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24547 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24548 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24549 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24550 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24551 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24552 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24553 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24554 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24555 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24557 ToC("vpst", fe710f4d, 0, (), mve_vpt),
24558 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
24559 ToC("vpste", fe718f4d, 0, (), mve_vpt),
24560 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
24561 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
24562 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
24563 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
24564 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
24565 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
24566 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
24567 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
24568 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
24569 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
24570 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
24571 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
24573 /* MVE and MVE FP only. */
24574 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
24575 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
24576 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
24577 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
24578 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
24579 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
24580 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
24581 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24582 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24583 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
24584 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
24585 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24586 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24587 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24588 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24589 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
24590 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
24592 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24593 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24594 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24595 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24596 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24597 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24598 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24599 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24600 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24601 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24602 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24603 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24604 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24605 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24606 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24607 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24608 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24609 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24610 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24611 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24613 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
24614 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
24615 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
24616 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
24617 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
24618 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
24619 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
24620 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
24621 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
24622 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
24623 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
24624 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
24625 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
24626 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
24627 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
24628 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
24629 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
24631 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24632 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24633 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24634 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24635 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24636 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24637 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24638 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24639 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24640 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24641 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24642 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24643 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24644 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24645 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24646 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24647 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24648 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24649 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24650 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24652 #undef THUMB_VARIANT
24653 #define THUMB_VARIANT & mve_fp_ext
24654 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
24655 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
24656 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
24657 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
24658 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
24659 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
24660 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
24661 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
24664 #define ARM_VARIANT & fpu_vfp_ext_v1
24665 #undef THUMB_VARIANT
24666 #define THUMB_VARIANT & arm_ext_v6t2
24667 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
24668 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
24670 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24673 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24675 MNCE(vmov, 0, 1, (VMOV), neon_mov),
24676 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
24677 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
24678 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
24680 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
24681 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
24682 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
24684 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
24685 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
24687 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
24688 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
24690 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
24691 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
24694 #define ARM_VARIANT & fpu_vfp_ext_v2
24696 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
24697 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
24698 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
24699 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
24702 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24703 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
24704 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
24705 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
24706 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
24707 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
24708 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
24711 #define ARM_VARIANT & fpu_neon_ext_v1
24712 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24713 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
24714 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
24715 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
24716 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24717 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24718 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24719 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24720 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
24721 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
24722 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
24723 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
24724 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
24725 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
24726 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
24727 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24728 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24729 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
24730 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
24733 #define ARM_VARIANT & arm_ext_v8_3
24734 #undef THUMB_VARIANT
24735 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24736 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
24737 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
24740 #undef THUMB_VARIANT
24772 /* MD interface: bits in the object file. */
24774 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24775 for use in the a.out file, and stores them in the array pointed to by buf.
24776 This knows about the endian-ness of the target machine and does
24777 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24778 2 (short) and 4 (long) Floating numbers are put out as a series of
24779 LITTLENUMS (shorts, here at least). */
24782 md_number_to_chars (char * buf, valueT val, int n)
24784 if (target_big_endian)
24785 number_to_chars_bigendian (buf, val, n);
24787 number_to_chars_littleendian (buf, val, n);
24791 md_chars_to_number (char * buf, int n)
24794 unsigned char * where = (unsigned char *) buf;
24796 if (target_big_endian)
24801 result |= (*where++ & 255);
24809 result |= (where[n] & 255);
24816 /* MD interface: Sections. */
24818 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24819 that an rs_machine_dependent frag may reach. */
24822 arm_frag_max_var (fragS *fragp)
24824 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24825 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24827 Note that we generate relaxable instructions even for cases that don't
24828 really need it, like an immediate that's a trivial constant. So we're
24829 overestimating the instruction size for some of those cases. Rather
24830 than putting more intelligence here, it would probably be better to
24831 avoid generating a relaxation frag in the first place when it can be
24832 determined up front that a short instruction will suffice. */
24834 gas_assert (fragp->fr_type == rs_machine_dependent);
24838 /* Estimate the size of a frag before relaxing. Assume everything fits in
24842 md_estimate_size_before_relax (fragS * fragp,
24843 segT segtype ATTRIBUTE_UNUSED)
24849 /* Convert a machine dependent frag. */
24852 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
24854 unsigned long insn;
24855 unsigned long old_op;
24863 buf = fragp->fr_literal + fragp->fr_fix;
24865 old_op = bfd_get_16(abfd, buf);
24866 if (fragp->fr_symbol)
24868 exp.X_op = O_symbol;
24869 exp.X_add_symbol = fragp->fr_symbol;
24873 exp.X_op = O_constant;
24875 exp.X_add_number = fragp->fr_offset;
24876 opcode = fragp->fr_subtype;
24879 case T_MNEM_ldr_pc:
24880 case T_MNEM_ldr_pc2:
24881 case T_MNEM_ldr_sp:
24882 case T_MNEM_str_sp:
24889 if (fragp->fr_var == 4)
24891 insn = THUMB_OP32 (opcode);
24892 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
24894 insn |= (old_op & 0x700) << 4;
24898 insn |= (old_op & 7) << 12;
24899 insn |= (old_op & 0x38) << 13;
24901 insn |= 0x00000c00;
24902 put_thumb32_insn (buf, insn);
24903 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
24907 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
24909 pc_rel = (opcode == T_MNEM_ldr_pc2);
24912 if (fragp->fr_var == 4)
24914 insn = THUMB_OP32 (opcode);
24915 insn |= (old_op & 0xf0) << 4;
24916 put_thumb32_insn (buf, insn);
24917 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
24921 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
24922 exp.X_add_number -= 4;
24930 if (fragp->fr_var == 4)
24932 int r0off = (opcode == T_MNEM_mov
24933 || opcode == T_MNEM_movs) ? 0 : 8;
24934 insn = THUMB_OP32 (opcode);
24935 insn = (insn & 0xe1ffffff) | 0x10000000;
24936 insn |= (old_op & 0x700) << r0off;
24937 put_thumb32_insn (buf, insn);
24938 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
24942 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
24947 if (fragp->fr_var == 4)
24949 insn = THUMB_OP32(opcode);
24950 put_thumb32_insn (buf, insn);
24951 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
24954 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
24958 if (fragp->fr_var == 4)
24960 insn = THUMB_OP32(opcode);
24961 insn |= (old_op & 0xf00) << 14;
24962 put_thumb32_insn (buf, insn);
24963 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
24966 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
24969 case T_MNEM_add_sp:
24970 case T_MNEM_add_pc:
24971 case T_MNEM_inc_sp:
24972 case T_MNEM_dec_sp:
24973 if (fragp->fr_var == 4)
24975 /* ??? Choose between add and addw. */
24976 insn = THUMB_OP32 (opcode);
24977 insn |= (old_op & 0xf0) << 4;
24978 put_thumb32_insn (buf, insn);
24979 if (opcode == T_MNEM_add_pc)
24980 reloc_type = BFD_RELOC_ARM_T32_IMM12;
24982 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
24985 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
24993 if (fragp->fr_var == 4)
24995 insn = THUMB_OP32 (opcode);
24996 insn |= (old_op & 0xf0) << 4;
24997 insn |= (old_op & 0xf) << 16;
24998 put_thumb32_insn (buf, insn);
24999 if (insn & (1 << 20))
25000 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
25002 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25005 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25011 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
25012 (enum bfd_reloc_code_real) reloc_type);
25013 fixp->fx_file = fragp->fr_file;
25014 fixp->fx_line = fragp->fr_line;
25015 fragp->fr_fix += fragp->fr_var;
25017 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25018 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
25019 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
25020 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
25023 /* Return the size of a relaxable immediate operand instruction.
25024 SHIFT and SIZE specify the form of the allowable immediate. */
25026 relax_immediate (fragS *fragp, int size, int shift)
25032 /* ??? Should be able to do better than this. */
25033 if (fragp->fr_symbol)
25036 low = (1 << shift) - 1;
25037 mask = (1 << (shift + size)) - (1 << shift);
25038 offset = fragp->fr_offset;
25039 /* Force misaligned offsets to 32-bit variant. */
25042 if (offset & ~mask)
25047 /* Get the address of a symbol during relaxation. */
25049 relaxed_symbol_addr (fragS *fragp, long stretch)
25055 sym = fragp->fr_symbol;
25056 sym_frag = symbol_get_frag (sym);
25057 know (S_GET_SEGMENT (sym) != absolute_section
25058 || sym_frag == &zero_address_frag);
25059 addr = S_GET_VALUE (sym) + fragp->fr_offset;
25061 /* If frag has yet to be reached on this pass, assume it will
25062 move by STRETCH just as we did. If this is not so, it will
25063 be because some frag between grows, and that will force
25067 && sym_frag->relax_marker != fragp->relax_marker)
25071 /* Adjust stretch for any alignment frag. Note that if have
25072 been expanding the earlier code, the symbol may be
25073 defined in what appears to be an earlier frag. FIXME:
25074 This doesn't handle the fr_subtype field, which specifies
25075 a maximum number of bytes to skip when doing an
25077 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
25079 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
25082 stretch = - ((- stretch)
25083 & ~ ((1 << (int) f->fr_offset) - 1));
25085 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
25097 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25100 relax_adr (fragS *fragp, asection *sec, long stretch)
25105 /* Assume worst case for symbols not known to be in the same section. */
25106 if (fragp->fr_symbol == NULL
25107 || !S_IS_DEFINED (fragp->fr_symbol)
25108 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25109 || S_IS_WEAK (fragp->fr_symbol))
25112 val = relaxed_symbol_addr (fragp, stretch);
25113 addr = fragp->fr_address + fragp->fr_fix;
25114 addr = (addr + 4) & ~3;
25115 /* Force misaligned targets to 32-bit variant. */
25119 if (val < 0 || val > 1020)
25124 /* Return the size of a relaxable add/sub immediate instruction. */
25126 relax_addsub (fragS *fragp, asection *sec)
25131 buf = fragp->fr_literal + fragp->fr_fix;
25132 op = bfd_get_16(sec->owner, buf);
25133 if ((op & 0xf) == ((op >> 4) & 0xf))
25134 return relax_immediate (fragp, 8, 0);
25136 return relax_immediate (fragp, 3, 0);
25139 /* Return TRUE iff the definition of symbol S could be pre-empted
25140 (overridden) at link or load time. */
25142 symbol_preemptible (symbolS *s)
25144 /* Weak symbols can always be pre-empted. */
25148 /* Non-global symbols cannot be pre-empted. */
25149 if (! S_IS_EXTERNAL (s))
25153 /* In ELF, a global symbol can be marked protected, or private. In that
25154 case it can't be pre-empted (other definitions in the same link unit
25155 would violate the ODR). */
25156 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
25160 /* Other global symbols might be pre-empted. */
25164 /* Return the size of a relaxable branch instruction. BITS is the
25165 size of the offset field in the narrow instruction. */
25168 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
25174 /* Assume worst case for symbols not known to be in the same section. */
25175 if (!S_IS_DEFINED (fragp->fr_symbol)
25176 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25177 || S_IS_WEAK (fragp->fr_symbol))
25181 /* A branch to a function in ARM state will require interworking. */
25182 if (S_IS_DEFINED (fragp->fr_symbol)
25183 && ARM_IS_FUNC (fragp->fr_symbol))
25187 if (symbol_preemptible (fragp->fr_symbol))
25190 val = relaxed_symbol_addr (fragp, stretch);
25191 addr = fragp->fr_address + fragp->fr_fix + 4;
25194 /* Offset is a signed value *2 */
25196 if (val >= limit || val < -limit)
25202 /* Relax a machine dependent frag. This returns the amount by which
25203 the current size of the frag should change. */
25206 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
25211 oldsize = fragp->fr_var;
25212 switch (fragp->fr_subtype)
25214 case T_MNEM_ldr_pc2:
25215 newsize = relax_adr (fragp, sec, stretch);
25217 case T_MNEM_ldr_pc:
25218 case T_MNEM_ldr_sp:
25219 case T_MNEM_str_sp:
25220 newsize = relax_immediate (fragp, 8, 2);
25224 newsize = relax_immediate (fragp, 5, 2);
25228 newsize = relax_immediate (fragp, 5, 1);
25232 newsize = relax_immediate (fragp, 5, 0);
25235 newsize = relax_adr (fragp, sec, stretch);
25241 newsize = relax_immediate (fragp, 8, 0);
25244 newsize = relax_branch (fragp, sec, 11, stretch);
25247 newsize = relax_branch (fragp, sec, 8, stretch);
25249 case T_MNEM_add_sp:
25250 case T_MNEM_add_pc:
25251 newsize = relax_immediate (fragp, 8, 2);
25253 case T_MNEM_inc_sp:
25254 case T_MNEM_dec_sp:
25255 newsize = relax_immediate (fragp, 7, 2);
25261 newsize = relax_addsub (fragp, sec);
25267 fragp->fr_var = newsize;
25268 /* Freeze wide instructions that are at or before the same location as
25269 in the previous pass. This avoids infinite loops.
25270 Don't freeze them unconditionally because targets may be artificially
25271 misaligned by the expansion of preceding frags. */
25272 if (stretch <= 0 && newsize > 2)
25274 md_convert_frag (sec->owner, sec, fragp);
25278 return newsize - oldsize;
25281 /* Round up a section size to the appropriate boundary. */
25284 md_section_align (segT segment ATTRIBUTE_UNUSED,
25290 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25291 of an rs_align_code fragment. */
25294 arm_handle_align (fragS * fragP)
25296 static unsigned char const arm_noop[2][2][4] =
25299 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25300 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25303 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25304 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25307 static unsigned char const thumb_noop[2][2][2] =
25310 {0xc0, 0x46}, /* LE */
25311 {0x46, 0xc0}, /* BE */
25314 {0x00, 0xbf}, /* LE */
25315 {0xbf, 0x00} /* BE */
25318 static unsigned char const wide_thumb_noop[2][4] =
25319 { /* Wide Thumb-2 */
25320 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25321 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25324 unsigned bytes, fix, noop_size;
25326 const unsigned char * noop;
25327 const unsigned char *narrow_noop = NULL;
25332 if (fragP->fr_type != rs_align_code)
25335 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
25336 p = fragP->fr_literal + fragP->fr_fix;
25339 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
25340 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
25342 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
25344 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
25346 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25347 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
25349 narrow_noop = thumb_noop[1][target_big_endian];
25350 noop = wide_thumb_noop[target_big_endian];
25353 noop = thumb_noop[0][target_big_endian];
25361 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25362 ? selected_cpu : arm_arch_none,
25364 [target_big_endian];
25371 fragP->fr_var = noop_size;
25373 if (bytes & (noop_size - 1))
25375 fix = bytes & (noop_size - 1);
25377 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
25379 memset (p, 0, fix);
25386 if (bytes & noop_size)
25388 /* Insert a narrow noop. */
25389 memcpy (p, narrow_noop, noop_size);
25391 bytes -= noop_size;
25395 /* Use wide noops for the remainder */
25399 while (bytes >= noop_size)
25401 memcpy (p, noop, noop_size);
25403 bytes -= noop_size;
25407 fragP->fr_fix += fix;
25410 /* Called from md_do_align. Used to create an alignment
25411 frag in a code section. */
25414 arm_frag_align_code (int n, int max)
25418 /* We assume that there will never be a requirement
25419 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25420 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
25425 _("alignments greater than %d bytes not supported in .text sections."),
25426 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
25427 as_fatal ("%s", err_msg);
25430 p = frag_var (rs_align_code,
25431 MAX_MEM_FOR_RS_ALIGN_CODE,
25433 (relax_substateT) max,
25440 /* Perform target specific initialisation of a frag.
25441 Note - despite the name this initialisation is not done when the frag
25442 is created, but only when its type is assigned. A frag can be created
25443 and used a long time before its type is set, so beware of assuming that
25444 this initialisation is performed first. */
25448 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
25450 /* Record whether this frag is in an ARM or a THUMB area. */
25451 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
25454 #else /* OBJ_ELF is defined. */
25456 arm_init_frag (fragS * fragP, int max_chars)
25458 bfd_boolean frag_thumb_mode;
25460 /* If the current ARM vs THUMB mode has not already
25461 been recorded into this frag then do so now. */
25462 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
25463 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
25465 /* PR 21809: Do not set a mapping state for debug sections
25466 - it just confuses other tools. */
25467 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
25470 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
25472 /* Record a mapping symbol for alignment frags. We will delete this
25473 later if the alignment ends up empty. */
25474 switch (fragP->fr_type)
25477 case rs_align_test:
25479 mapping_state_2 (MAP_DATA, max_chars);
25481 case rs_align_code:
25482 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
25489 /* When we change sections we need to issue a new mapping symbol. */
25492 arm_elf_change_section (void)
25494 /* Link an unlinked unwind index table section to the .text section. */
25495 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
25496 && elf_linked_to_section (now_seg) == NULL)
25497 elf_linked_to_section (now_seg) = text_section;
25501 arm_elf_section_type (const char * str, size_t len)
25503 if (len == 5 && strncmp (str, "exidx", 5) == 0)
25504 return SHT_ARM_EXIDX;
25509 /* Code to deal with unwinding tables. */
25511 static void add_unwind_adjustsp (offsetT);
25513 /* Generate any deferred unwind frame offset. */
25516 flush_pending_unwind (void)
25520 offset = unwind.pending_offset;
25521 unwind.pending_offset = 0;
25523 add_unwind_adjustsp (offset);
25526 /* Add an opcode to this list for this function. Two-byte opcodes should
25527 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25531 add_unwind_opcode (valueT op, int length)
25533 /* Add any deferred stack adjustment. */
25534 if (unwind.pending_offset)
25535 flush_pending_unwind ();
25537 unwind.sp_restored = 0;
25539 if (unwind.opcode_count + length > unwind.opcode_alloc)
25541 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
25542 if (unwind.opcodes)
25543 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
25544 unwind.opcode_alloc);
25546 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
25551 unwind.opcodes[unwind.opcode_count] = op & 0xff;
25553 unwind.opcode_count++;
25557 /* Add unwind opcodes to adjust the stack pointer. */
25560 add_unwind_adjustsp (offsetT offset)
25564 if (offset > 0x200)
25566 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
25571 /* Long form: 0xb2, uleb128. */
25572 /* This might not fit in a word so add the individual bytes,
25573 remembering the list is built in reverse order. */
25574 o = (valueT) ((offset - 0x204) >> 2);
25576 add_unwind_opcode (0, 1);
25578 /* Calculate the uleb128 encoding of the offset. */
25582 bytes[n] = o & 0x7f;
25588 /* Add the insn. */
25590 add_unwind_opcode (bytes[n - 1], 1);
25591 add_unwind_opcode (0xb2, 1);
25593 else if (offset > 0x100)
25595 /* Two short opcodes. */
25596 add_unwind_opcode (0x3f, 1);
25597 op = (offset - 0x104) >> 2;
25598 add_unwind_opcode (op, 1);
25600 else if (offset > 0)
25602 /* Short opcode. */
25603 op = (offset - 4) >> 2;
25604 add_unwind_opcode (op, 1);
25606 else if (offset < 0)
25609 while (offset > 0x100)
25611 add_unwind_opcode (0x7f, 1);
25614 op = ((offset - 4) >> 2) | 0x40;
25615 add_unwind_opcode (op, 1);
25619 /* Finish the list of unwind opcodes for this function. */
25622 finish_unwind_opcodes (void)
25626 if (unwind.fp_used)
25628 /* Adjust sp as necessary. */
25629 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
25630 flush_pending_unwind ();
25632 /* After restoring sp from the frame pointer. */
25633 op = 0x90 | unwind.fp_reg;
25634 add_unwind_opcode (op, 1);
25637 flush_pending_unwind ();
25641 /* Start an exception table entry. If idx is nonzero this is an index table
25645 start_unwind_section (const segT text_seg, int idx)
25647 const char * text_name;
25648 const char * prefix;
25649 const char * prefix_once;
25650 const char * group_name;
25658 prefix = ELF_STRING_ARM_unwind;
25659 prefix_once = ELF_STRING_ARM_unwind_once;
25660 type = SHT_ARM_EXIDX;
25664 prefix = ELF_STRING_ARM_unwind_info;
25665 prefix_once = ELF_STRING_ARM_unwind_info_once;
25666 type = SHT_PROGBITS;
25669 text_name = segment_name (text_seg);
25670 if (streq (text_name, ".text"))
25673 if (strncmp (text_name, ".gnu.linkonce.t.",
25674 strlen (".gnu.linkonce.t.")) == 0)
25676 prefix = prefix_once;
25677 text_name += strlen (".gnu.linkonce.t.");
25680 sec_name = concat (prefix, text_name, (char *) NULL);
25686 /* Handle COMDAT group. */
25687 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
25689 group_name = elf_group_name (text_seg);
25690 if (group_name == NULL)
25692 as_bad (_("Group section `%s' has no group signature"),
25693 segment_name (text_seg));
25694 ignore_rest_of_line ();
25697 flags |= SHF_GROUP;
25701 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
25704 /* Set the section link for index tables. */
25706 elf_linked_to_section (now_seg) = text_seg;
25710 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25711 personality routine data. Returns zero, or the index table value for
25712 an inline entry. */
25715 create_unwind_entry (int have_data)
25720 /* The current word of data. */
25722 /* The number of bytes left in this word. */
25725 finish_unwind_opcodes ();
25727 /* Remember the current text section. */
25728 unwind.saved_seg = now_seg;
25729 unwind.saved_subseg = now_subseg;
25731 start_unwind_section (now_seg, 0);
25733 if (unwind.personality_routine == NULL)
25735 if (unwind.personality_index == -2)
25738 as_bad (_("handlerdata in cantunwind frame"));
25739 return 1; /* EXIDX_CANTUNWIND. */
25742 /* Use a default personality routine if none is specified. */
25743 if (unwind.personality_index == -1)
25745 if (unwind.opcode_count > 3)
25746 unwind.personality_index = 1;
25748 unwind.personality_index = 0;
25751 /* Space for the personality routine entry. */
25752 if (unwind.personality_index == 0)
25754 if (unwind.opcode_count > 3)
25755 as_bad (_("too many unwind opcodes for personality routine 0"));
25759 /* All the data is inline in the index table. */
25762 while (unwind.opcode_count > 0)
25764 unwind.opcode_count--;
25765 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
25769 /* Pad with "finish" opcodes. */
25771 data = (data << 8) | 0xb0;
25778 /* We get two opcodes "free" in the first word. */
25779 size = unwind.opcode_count - 2;
25783 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25784 if (unwind.personality_index != -1)
25786 as_bad (_("attempt to recreate an unwind entry"));
25790 /* An extra byte is required for the opcode count. */
25791 size = unwind.opcode_count + 1;
25794 size = (size + 3) >> 2;
25796 as_bad (_("too many unwind opcodes"));
25798 frag_align (2, 0, 0);
25799 record_alignment (now_seg, 2);
25800 unwind.table_entry = expr_build_dot ();
25802 /* Allocate the table entry. */
25803 ptr = frag_more ((size << 2) + 4);
25804 /* PR 13449: Zero the table entries in case some of them are not used. */
25805 memset (ptr, 0, (size << 2) + 4);
25806 where = frag_now_fix () - ((size << 2) + 4);
25808 switch (unwind.personality_index)
25811 /* ??? Should this be a PLT generating relocation? */
25812 /* Custom personality routine. */
25813 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
25814 BFD_RELOC_ARM_PREL31);
25819 /* Set the first byte to the number of additional words. */
25820 data = size > 0 ? size - 1 : 0;
25824 /* ABI defined personality routines. */
25826 /* Three opcodes bytes are packed into the first word. */
25833 /* The size and first two opcode bytes go in the first word. */
25834 data = ((0x80 + unwind.personality_index) << 8) | size;
25839 /* Should never happen. */
25843 /* Pack the opcodes into words (MSB first), reversing the list at the same
25845 while (unwind.opcode_count > 0)
25849 md_number_to_chars (ptr, data, 4);
25854 unwind.opcode_count--;
25856 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
25859 /* Finish off the last word. */
25862 /* Pad with "finish" opcodes. */
25864 data = (data << 8) | 0xb0;
25866 md_number_to_chars (ptr, data, 4);
25871 /* Add an empty descriptor if there is no user-specified data. */
25872 ptr = frag_more (4);
25873 md_number_to_chars (ptr, 0, 4);
25880 /* Initialize the DWARF-2 unwind information for this procedure. */
25883 tc_arm_frame_initial_instructions (void)
25885 cfi_add_CFA_def_cfa (REG_SP, 0);
25887 #endif /* OBJ_ELF */
25889 /* Convert REGNAME to a DWARF-2 register number. */
25892 tc_arm_regname_to_dw2regnum (char *regname)
25894 int reg = arm_reg_parse (®name, REG_TYPE_RN);
25898 /* PR 16694: Allow VFP registers as well. */
25899 reg = arm_reg_parse (®name, REG_TYPE_VFS);
25903 reg = arm_reg_parse (®name, REG_TYPE_VFD);
25912 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
25916 exp.X_op = O_secrel;
25917 exp.X_add_symbol = symbol;
25918 exp.X_add_number = 0;
25919 emit_expr (&exp, size);
25923 /* MD interface: Symbol and relocation handling. */
25925 /* Return the address within the segment that a PC-relative fixup is
25926 relative to. For ARM, PC-relative fixups applied to instructions
25927 are generally relative to the location of the fixup plus 8 bytes.
25928 Thumb branches are offset by 4, and Thumb loads relative to PC
25929 require special handling. */
25932 md_pcrel_from_section (fixS * fixP, segT seg)
25934 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
25936 /* If this is pc-relative and we are going to emit a relocation
25937 then we just want to put out any pipeline compensation that the linker
25938 will need. Otherwise we want to use the calculated base.
25939 For WinCE we skip the bias for externals as well, since this
25940 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25942 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
25943 || (arm_force_relocation (fixP)
25945 && !S_IS_EXTERNAL (fixP->fx_addsy)
25951 switch (fixP->fx_r_type)
25953 /* PC relative addressing on the Thumb is slightly odd as the
25954 bottom two bits of the PC are forced to zero for the
25955 calculation. This happens *after* application of the
25956 pipeline offset. However, Thumb adrl already adjusts for
25957 this, so we need not do it again. */
25958 case BFD_RELOC_ARM_THUMB_ADD:
25961 case BFD_RELOC_ARM_THUMB_OFFSET:
25962 case BFD_RELOC_ARM_T32_OFFSET_IMM:
25963 case BFD_RELOC_ARM_T32_ADD_PC12:
25964 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
25965 return (base + 4) & ~3;
25967 /* Thumb branches are simply offset by +4. */
25968 case BFD_RELOC_THUMB_PCREL_BRANCH5:
25969 case BFD_RELOC_THUMB_PCREL_BRANCH7:
25970 case BFD_RELOC_THUMB_PCREL_BRANCH9:
25971 case BFD_RELOC_THUMB_PCREL_BRANCH12:
25972 case BFD_RELOC_THUMB_PCREL_BRANCH20:
25973 case BFD_RELOC_THUMB_PCREL_BRANCH25:
25974 case BFD_RELOC_THUMB_PCREL_BFCSEL:
25975 case BFD_RELOC_ARM_THUMB_BF17:
25976 case BFD_RELOC_ARM_THUMB_BF19:
25977 case BFD_RELOC_ARM_THUMB_BF13:
25978 case BFD_RELOC_ARM_THUMB_LOOP12:
25981 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25983 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25984 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25985 && ARM_IS_FUNC (fixP->fx_addsy)
25986 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25987 base = fixP->fx_where + fixP->fx_frag->fr_address;
25990 /* BLX is like branches above, but forces the low two bits of PC to
25992 case BFD_RELOC_THUMB_PCREL_BLX:
25994 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25995 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25996 && THUMB_IS_FUNC (fixP->fx_addsy)
25997 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25998 base = fixP->fx_where + fixP->fx_frag->fr_address;
25999 return (base + 4) & ~3;
26001 /* ARM mode branches are offset by +8. However, the Windows CE
26002 loader expects the relocation not to take this into account. */
26003 case BFD_RELOC_ARM_PCREL_BLX:
26005 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26006 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26007 && ARM_IS_FUNC (fixP->fx_addsy)
26008 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26009 base = fixP->fx_where + fixP->fx_frag->fr_address;
26012 case BFD_RELOC_ARM_PCREL_CALL:
26014 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26015 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26016 && THUMB_IS_FUNC (fixP->fx_addsy)
26017 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26018 base = fixP->fx_where + fixP->fx_frag->fr_address;
26021 case BFD_RELOC_ARM_PCREL_BRANCH:
26022 case BFD_RELOC_ARM_PCREL_JUMP:
26023 case BFD_RELOC_ARM_PLT32:
26025 /* When handling fixups immediately, because we have already
26026 discovered the value of a symbol, or the address of the frag involved
26027 we must account for the offset by +8, as the OS loader will never see the reloc.
26028 see fixup_segment() in write.c
26029 The S_IS_EXTERNAL test handles the case of global symbols.
26030 Those need the calculated base, not just the pipe compensation the linker will need. */
26032 && fixP->fx_addsy != NULL
26033 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26034 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
26042 /* ARM mode loads relative to PC are also offset by +8. Unlike
26043 branches, the Windows CE loader *does* expect the relocation
26044 to take this into account. */
26045 case BFD_RELOC_ARM_OFFSET_IMM:
26046 case BFD_RELOC_ARM_OFFSET_IMM8:
26047 case BFD_RELOC_ARM_HWLITERAL:
26048 case BFD_RELOC_ARM_LITERAL:
26049 case BFD_RELOC_ARM_CP_OFF_IMM:
26053 /* Other PC-relative relocations are un-offset. */
26059 static bfd_boolean flag_warn_syms = TRUE;
26062 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
26064 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26065 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26066 does mean that the resulting code might be very confusing to the reader.
26067 Also this warning can be triggered if the user omits an operand before
26068 an immediate address, eg:
26072 GAS treats this as an assignment of the value of the symbol foo to a
26073 symbol LDR, and so (without this code) it will not issue any kind of
26074 warning or error message.
26076 Note - ARM instructions are case-insensitive but the strings in the hash
26077 table are all stored in lower case, so we must first ensure that name is
26079 if (flag_warn_syms && arm_ops_hsh)
26081 char * nbuf = strdup (name);
26084 for (p = nbuf; *p; p++)
26086 if (hash_find (arm_ops_hsh, nbuf) != NULL)
26088 static struct hash_control * already_warned = NULL;
26090 if (already_warned == NULL)
26091 already_warned = hash_new ();
26092 /* Only warn about the symbol once. To keep the code
26093 simple we let hash_insert do the lookup for us. */
26094 if (hash_insert (already_warned, nbuf, NULL) == NULL)
26095 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
26104 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26105 Otherwise we have no need to default values of symbols. */
26108 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
26111 if (name[0] == '_' && name[1] == 'G'
26112 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
26116 if (symbol_find (name))
26117 as_bad (_("GOT already in the symbol table"));
26119 GOT_symbol = symbol_new (name, undefined_section,
26120 (valueT) 0, & zero_address_frag);
26130 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26131 computed as two separate immediate values, added together. We
26132 already know that this value cannot be computed by just one ARM
26135 static unsigned int
26136 validate_immediate_twopart (unsigned int val,
26137 unsigned int * highpart)
26142 for (i = 0; i < 32; i += 2)
26143 if (((a = rotate_left (val, i)) & 0xff) != 0)
26149 * highpart = (a >> 8) | ((i + 24) << 7);
26151 else if (a & 0xff0000)
26153 if (a & 0xff000000)
26155 * highpart = (a >> 16) | ((i + 16) << 7);
26159 gas_assert (a & 0xff000000);
26160 * highpart = (a >> 24) | ((i + 8) << 7);
26163 return (a & 0xff) | (i << 7);
26170 validate_offset_imm (unsigned int val, int hwse)
26172 if ((hwse && val > 255) || val > 4095)
26177 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26178 negative immediate constant by altering the instruction. A bit of
26183 by inverting the second operand, and
26186 by negating the second operand. */
26189 negate_data_op (unsigned long * instruction,
26190 unsigned long value)
26193 unsigned long negated, inverted;
26195 negated = encode_arm_immediate (-value);
26196 inverted = encode_arm_immediate (~value);
26198 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
26201 /* First negates. */
26202 case OPCODE_SUB: /* ADD <-> SUB */
26203 new_inst = OPCODE_ADD;
26208 new_inst = OPCODE_SUB;
26212 case OPCODE_CMP: /* CMP <-> CMN */
26213 new_inst = OPCODE_CMN;
26218 new_inst = OPCODE_CMP;
26222 /* Now Inverted ops. */
26223 case OPCODE_MOV: /* MOV <-> MVN */
26224 new_inst = OPCODE_MVN;
26229 new_inst = OPCODE_MOV;
26233 case OPCODE_AND: /* AND <-> BIC */
26234 new_inst = OPCODE_BIC;
26239 new_inst = OPCODE_AND;
26243 case OPCODE_ADC: /* ADC <-> SBC */
26244 new_inst = OPCODE_SBC;
26249 new_inst = OPCODE_ADC;
26253 /* We cannot do anything. */
26258 if (value == (unsigned) FAIL)
26261 *instruction &= OPCODE_MASK;
26262 *instruction |= new_inst << DATA_OP_SHIFT;
26266 /* Like negate_data_op, but for Thumb-2. */
26268 static unsigned int
26269 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
26273 unsigned int negated, inverted;
26275 negated = encode_thumb32_immediate (-value);
26276 inverted = encode_thumb32_immediate (~value);
26278 rd = (*instruction >> 8) & 0xf;
26279 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
26282 /* ADD <-> SUB. Includes CMP <-> CMN. */
26283 case T2_OPCODE_SUB:
26284 new_inst = T2_OPCODE_ADD;
26288 case T2_OPCODE_ADD:
26289 new_inst = T2_OPCODE_SUB;
26293 /* ORR <-> ORN. Includes MOV <-> MVN. */
26294 case T2_OPCODE_ORR:
26295 new_inst = T2_OPCODE_ORN;
26299 case T2_OPCODE_ORN:
26300 new_inst = T2_OPCODE_ORR;
26304 /* AND <-> BIC. TST has no inverted equivalent. */
26305 case T2_OPCODE_AND:
26306 new_inst = T2_OPCODE_BIC;
26313 case T2_OPCODE_BIC:
26314 new_inst = T2_OPCODE_AND;
26319 case T2_OPCODE_ADC:
26320 new_inst = T2_OPCODE_SBC;
26324 case T2_OPCODE_SBC:
26325 new_inst = T2_OPCODE_ADC;
26329 /* We cannot do anything. */
26334 if (value == (unsigned int)FAIL)
26337 *instruction &= T2_OPCODE_MASK;
26338 *instruction |= new_inst << T2_DATA_OP_SHIFT;
26342 /* Read a 32-bit thumb instruction from buf. */
26344 static unsigned long
26345 get_thumb32_insn (char * buf)
26347 unsigned long insn;
26348 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
26349 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26354 /* We usually want to set the low bit on the address of thumb function
26355 symbols. In particular .word foo - . should have the low bit set.
26356 Generic code tries to fold the difference of two symbols to
26357 a constant. Prevent this and force a relocation when the first symbols
26358 is a thumb function. */
26361 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
26363 if (op == O_subtract
26364 && l->X_op == O_symbol
26365 && r->X_op == O_symbol
26366 && THUMB_IS_FUNC (l->X_add_symbol))
26368 l->X_op = O_subtract;
26369 l->X_op_symbol = r->X_add_symbol;
26370 l->X_add_number -= r->X_add_number;
26374 /* Process as normal. */
26378 /* Encode Thumb2 unconditional branches and calls. The encoding
26379 for the 2 are identical for the immediate values. */
26382 encode_thumb2_b_bl_offset (char * buf, offsetT value)
26384 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26387 addressT S, I1, I2, lo, hi;
26389 S = (value >> 24) & 0x01;
26390 I1 = (value >> 23) & 0x01;
26391 I2 = (value >> 22) & 0x01;
26392 hi = (value >> 12) & 0x3ff;
26393 lo = (value >> 1) & 0x7ff;
26394 newval = md_chars_to_number (buf, THUMB_SIZE);
26395 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26396 newval |= (S << 10) | hi;
26397 newval2 &= ~T2I1I2MASK;
26398 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
26399 md_number_to_chars (buf, newval, THUMB_SIZE);
26400 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
26404 md_apply_fix (fixS * fixP,
26408 offsetT value = * valP;
26410 unsigned int newimm;
26411 unsigned long temp;
26413 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
26415 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
26417 /* Note whether this will delete the relocation. */
26419 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
26422 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26423 consistency with the behaviour on 32-bit hosts. Remember value
26425 value &= 0xffffffff;
26426 value ^= 0x80000000;
26427 value -= 0x80000000;
26430 fixP->fx_addnumber = value;
26432 /* Same treatment for fixP->fx_offset. */
26433 fixP->fx_offset &= 0xffffffff;
26434 fixP->fx_offset ^= 0x80000000;
26435 fixP->fx_offset -= 0x80000000;
26437 switch (fixP->fx_r_type)
26439 case BFD_RELOC_NONE:
26440 /* This will need to go in the object file. */
26444 case BFD_RELOC_ARM_IMMEDIATE:
26445 /* We claim that this fixup has been processed here,
26446 even if in fact we generate an error because we do
26447 not have a reloc for it, so tc_gen_reloc will reject it. */
26450 if (fixP->fx_addsy)
26452 const char *msg = 0;
26454 if (! S_IS_DEFINED (fixP->fx_addsy))
26455 msg = _("undefined symbol %s used as an immediate value");
26456 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
26457 msg = _("symbol %s is in a different section");
26458 else if (S_IS_WEAK (fixP->fx_addsy))
26459 msg = _("symbol %s is weak and may be overridden later");
26463 as_bad_where (fixP->fx_file, fixP->fx_line,
26464 msg, S_GET_NAME (fixP->fx_addsy));
26469 temp = md_chars_to_number (buf, INSN_SIZE);
26471 /* If the offset is negative, we should use encoding A2 for ADR. */
26472 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
26473 newimm = negate_data_op (&temp, value);
26476 newimm = encode_arm_immediate (value);
26478 /* If the instruction will fail, see if we can fix things up by
26479 changing the opcode. */
26480 if (newimm == (unsigned int) FAIL)
26481 newimm = negate_data_op (&temp, value);
26482 /* MOV accepts both ARM modified immediate (A1 encoding) and
26483 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
26484 When disassembling, MOV is preferred when there is no encoding
26486 if (newimm == (unsigned int) FAIL
26487 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
26488 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
26489 && !((temp >> SBIT_SHIFT) & 0x1)
26490 && value >= 0 && value <= 0xffff)
26492 /* Clear bits[23:20] to change encoding from A1 to A2. */
26493 temp &= 0xff0fffff;
26494 /* Encoding high 4bits imm. Code below will encode the remaining
26496 temp |= (value & 0x0000f000) << 4;
26497 newimm = value & 0x00000fff;
26501 if (newimm == (unsigned int) FAIL)
26503 as_bad_where (fixP->fx_file, fixP->fx_line,
26504 _("invalid constant (%lx) after fixup"),
26505 (unsigned long) value);
26509 newimm |= (temp & 0xfffff000);
26510 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
26513 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
26515 unsigned int highpart = 0;
26516 unsigned int newinsn = 0xe1a00000; /* nop. */
26518 if (fixP->fx_addsy)
26520 const char *msg = 0;
26522 if (! S_IS_DEFINED (fixP->fx_addsy))
26523 msg = _("undefined symbol %s used as an immediate value");
26524 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
26525 msg = _("symbol %s is in a different section");
26526 else if (S_IS_WEAK (fixP->fx_addsy))
26527 msg = _("symbol %s is weak and may be overridden later");
26531 as_bad_where (fixP->fx_file, fixP->fx_line,
26532 msg, S_GET_NAME (fixP->fx_addsy));
26537 newimm = encode_arm_immediate (value);
26538 temp = md_chars_to_number (buf, INSN_SIZE);
26540 /* If the instruction will fail, see if we can fix things up by
26541 changing the opcode. */
26542 if (newimm == (unsigned int) FAIL
26543 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
26545 /* No ? OK - try using two ADD instructions to generate
26547 newimm = validate_immediate_twopart (value, & highpart);
26549 /* Yes - then make sure that the second instruction is
26551 if (newimm != (unsigned int) FAIL)
26553 /* Still No ? Try using a negated value. */
26554 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
26555 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
26556 /* Otherwise - give up. */
26559 as_bad_where (fixP->fx_file, fixP->fx_line,
26560 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
26565 /* Replace the first operand in the 2nd instruction (which
26566 is the PC) with the destination register. We have
26567 already added in the PC in the first instruction and we
26568 do not want to do it again. */
26569 newinsn &= ~ 0xf0000;
26570 newinsn |= ((newinsn & 0x0f000) << 4);
26573 newimm |= (temp & 0xfffff000);
26574 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
26576 highpart |= (newinsn & 0xfffff000);
26577 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
26581 case BFD_RELOC_ARM_OFFSET_IMM:
26582 if (!fixP->fx_done && seg->use_rela_p)
26584 /* Fall through. */
26586 case BFD_RELOC_ARM_LITERAL:
26592 if (validate_offset_imm (value, 0) == FAIL)
26594 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
26595 as_bad_where (fixP->fx_file, fixP->fx_line,
26596 _("invalid literal constant: pool needs to be closer"));
26598 as_bad_where (fixP->fx_file, fixP->fx_line,
26599 _("bad immediate value for offset (%ld)"),
26604 newval = md_chars_to_number (buf, INSN_SIZE);
26606 newval &= 0xfffff000;
26609 newval &= 0xff7ff000;
26610 newval |= value | (sign ? INDEX_UP : 0);
26612 md_number_to_chars (buf, newval, INSN_SIZE);
26615 case BFD_RELOC_ARM_OFFSET_IMM8:
26616 case BFD_RELOC_ARM_HWLITERAL:
26622 if (validate_offset_imm (value, 1) == FAIL)
26624 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
26625 as_bad_where (fixP->fx_file, fixP->fx_line,
26626 _("invalid literal constant: pool needs to be closer"));
26628 as_bad_where (fixP->fx_file, fixP->fx_line,
26629 _("bad immediate value for 8-bit offset (%ld)"),
26634 newval = md_chars_to_number (buf, INSN_SIZE);
26636 newval &= 0xfffff0f0;
26639 newval &= 0xff7ff0f0;
26640 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
26642 md_number_to_chars (buf, newval, INSN_SIZE);
26645 case BFD_RELOC_ARM_T32_OFFSET_U8:
26646 if (value < 0 || value > 1020 || value % 4 != 0)
26647 as_bad_where (fixP->fx_file, fixP->fx_line,
26648 _("bad immediate value for offset (%ld)"), (long) value);
26651 newval = md_chars_to_number (buf+2, THUMB_SIZE);
26653 md_number_to_chars (buf+2, newval, THUMB_SIZE);
26656 case BFD_RELOC_ARM_T32_OFFSET_IMM:
26657 /* This is a complicated relocation used for all varieties of Thumb32
26658 load/store instruction with immediate offset:
26660 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26661 *4, optional writeback(W)
26662 (doubleword load/store)
26664 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26665 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26666 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26667 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26668 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26670 Uppercase letters indicate bits that are already encoded at
26671 this point. Lowercase letters are our problem. For the
26672 second block of instructions, the secondary opcode nybble
26673 (bits 8..11) is present, and bit 23 is zero, even if this is
26674 a PC-relative operation. */
26675 newval = md_chars_to_number (buf, THUMB_SIZE);
26677 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
26679 if ((newval & 0xf0000000) == 0xe0000000)
26681 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26683 newval |= (1 << 23);
26686 if (value % 4 != 0)
26688 as_bad_where (fixP->fx_file, fixP->fx_line,
26689 _("offset not a multiple of 4"));
26695 as_bad_where (fixP->fx_file, fixP->fx_line,
26696 _("offset out of range"));
26701 else if ((newval & 0x000f0000) == 0x000f0000)
26703 /* PC-relative, 12-bit offset. */
26705 newval |= (1 << 23);
26710 as_bad_where (fixP->fx_file, fixP->fx_line,
26711 _("offset out of range"));
26716 else if ((newval & 0x00000100) == 0x00000100)
26718 /* Writeback: 8-bit, +/- offset. */
26720 newval |= (1 << 9);
26725 as_bad_where (fixP->fx_file, fixP->fx_line,
26726 _("offset out of range"));
26731 else if ((newval & 0x00000f00) == 0x00000e00)
26733 /* T-instruction: positive 8-bit offset. */
26734 if (value < 0 || value > 0xff)
26736 as_bad_where (fixP->fx_file, fixP->fx_line,
26737 _("offset out of range"));
26745 /* Positive 12-bit or negative 8-bit offset. */
26749 newval |= (1 << 23);
26759 as_bad_where (fixP->fx_file, fixP->fx_line,
26760 _("offset out of range"));
26767 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
26768 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
26771 case BFD_RELOC_ARM_SHIFT_IMM:
26772 newval = md_chars_to_number (buf, INSN_SIZE);
26773 if (((unsigned long) value) > 32
26775 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
26777 as_bad_where (fixP->fx_file, fixP->fx_line,
26778 _("shift expression is too large"));
26783 /* Shifts of zero must be done as lsl. */
26785 else if (value == 32)
26787 newval &= 0xfffff07f;
26788 newval |= (value & 0x1f) << 7;
26789 md_number_to_chars (buf, newval, INSN_SIZE);
26792 case BFD_RELOC_ARM_T32_IMMEDIATE:
26793 case BFD_RELOC_ARM_T32_ADD_IMM:
26794 case BFD_RELOC_ARM_T32_IMM12:
26795 case BFD_RELOC_ARM_T32_ADD_PC12:
26796 /* We claim that this fixup has been processed here,
26797 even if in fact we generate an error because we do
26798 not have a reloc for it, so tc_gen_reloc will reject it. */
26802 && ! S_IS_DEFINED (fixP->fx_addsy))
26804 as_bad_where (fixP->fx_file, fixP->fx_line,
26805 _("undefined symbol %s used as an immediate value"),
26806 S_GET_NAME (fixP->fx_addsy));
26810 newval = md_chars_to_number (buf, THUMB_SIZE);
26812 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
26815 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
26816 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26817 Thumb2 modified immediate encoding (T2). */
26818 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
26819 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
26821 newimm = encode_thumb32_immediate (value);
26822 if (newimm == (unsigned int) FAIL)
26823 newimm = thumb32_negate_data_op (&newval, value);
26825 if (newimm == (unsigned int) FAIL)
26827 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
26829 /* Turn add/sum into addw/subw. */
26830 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
26831 newval = (newval & 0xfeffffff) | 0x02000000;
26832 /* No flat 12-bit imm encoding for addsw/subsw. */
26833 if ((newval & 0x00100000) == 0)
26835 /* 12 bit immediate for addw/subw. */
26839 newval ^= 0x00a00000;
26842 newimm = (unsigned int) FAIL;
26849 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26850 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26851 disassembling, MOV is preferred when there is no encoding
26853 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
26854 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26855 but with the Rn field [19:16] set to 1111. */
26856 && (((newval >> 16) & 0xf) == 0xf)
26857 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
26858 && !((newval >> T2_SBIT_SHIFT) & 0x1)
26859 && value >= 0 && value <= 0xffff)
26861 /* Toggle bit[25] to change encoding from T2 to T3. */
26863 /* Clear bits[19:16]. */
26864 newval &= 0xfff0ffff;
26865 /* Encoding high 4bits imm. Code below will encode the
26866 remaining low 12bits. */
26867 newval |= (value & 0x0000f000) << 4;
26868 newimm = value & 0x00000fff;
26873 if (newimm == (unsigned int)FAIL)
26875 as_bad_where (fixP->fx_file, fixP->fx_line,
26876 _("invalid constant (%lx) after fixup"),
26877 (unsigned long) value);
26881 newval |= (newimm & 0x800) << 15;
26882 newval |= (newimm & 0x700) << 4;
26883 newval |= (newimm & 0x0ff);
26885 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
26886 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
26889 case BFD_RELOC_ARM_SMC:
26890 if (((unsigned long) value) > 0xffff)
26891 as_bad_where (fixP->fx_file, fixP->fx_line,
26892 _("invalid smc expression"));
26893 newval = md_chars_to_number (buf, INSN_SIZE);
26894 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
26895 md_number_to_chars (buf, newval, INSN_SIZE);
26898 case BFD_RELOC_ARM_HVC:
26899 if (((unsigned long) value) > 0xffff)
26900 as_bad_where (fixP->fx_file, fixP->fx_line,
26901 _("invalid hvc expression"));
26902 newval = md_chars_to_number (buf, INSN_SIZE);
26903 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
26904 md_number_to_chars (buf, newval, INSN_SIZE);
26907 case BFD_RELOC_ARM_SWI:
26908 if (fixP->tc_fix_data != 0)
26910 if (((unsigned long) value) > 0xff)
26911 as_bad_where (fixP->fx_file, fixP->fx_line,
26912 _("invalid swi expression"));
26913 newval = md_chars_to_number (buf, THUMB_SIZE);
26915 md_number_to_chars (buf, newval, THUMB_SIZE);
26919 if (((unsigned long) value) > 0x00ffffff)
26920 as_bad_where (fixP->fx_file, fixP->fx_line,
26921 _("invalid swi expression"));
26922 newval = md_chars_to_number (buf, INSN_SIZE);
26924 md_number_to_chars (buf, newval, INSN_SIZE);
26928 case BFD_RELOC_ARM_MULTI:
26929 if (((unsigned long) value) > 0xffff)
26930 as_bad_where (fixP->fx_file, fixP->fx_line,
26931 _("invalid expression in load/store multiple"));
26932 newval = value | md_chars_to_number (buf, INSN_SIZE);
26933 md_number_to_chars (buf, newval, INSN_SIZE);
26937 case BFD_RELOC_ARM_PCREL_CALL:
26939 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26941 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26942 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26943 && THUMB_IS_FUNC (fixP->fx_addsy))
26944 /* Flip the bl to blx. This is a simple flip
26945 bit here because we generate PCREL_CALL for
26946 unconditional bls. */
26948 newval = md_chars_to_number (buf, INSN_SIZE);
26949 newval = newval | 0x10000000;
26950 md_number_to_chars (buf, newval, INSN_SIZE);
26956 goto arm_branch_common;
26958 case BFD_RELOC_ARM_PCREL_JUMP:
26959 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26961 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26962 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26963 && THUMB_IS_FUNC (fixP->fx_addsy))
26965 /* This would map to a bl<cond>, b<cond>,
26966 b<always> to a Thumb function. We
26967 need to force a relocation for this particular
26969 newval = md_chars_to_number (buf, INSN_SIZE);
26972 /* Fall through. */
26974 case BFD_RELOC_ARM_PLT32:
26976 case BFD_RELOC_ARM_PCREL_BRANCH:
26978 goto arm_branch_common;
26980 case BFD_RELOC_ARM_PCREL_BLX:
26983 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26985 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26986 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26987 && ARM_IS_FUNC (fixP->fx_addsy))
26989 /* Flip the blx to a bl and warn. */
26990 const char *name = S_GET_NAME (fixP->fx_addsy);
26991 newval = 0xeb000000;
26992 as_warn_where (fixP->fx_file, fixP->fx_line,
26993 _("blx to '%s' an ARM ISA state function changed to bl"),
26995 md_number_to_chars (buf, newval, INSN_SIZE);
27001 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
27002 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
27006 /* We are going to store value (shifted right by two) in the
27007 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27008 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27011 as_bad_where (fixP->fx_file, fixP->fx_line,
27012 _("misaligned branch destination"));
27013 if ((value & (offsetT)0xfe000000) != (offsetT)0
27014 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
27015 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27017 if (fixP->fx_done || !seg->use_rela_p)
27019 newval = md_chars_to_number (buf, INSN_SIZE);
27020 newval |= (value >> 2) & 0x00ffffff;
27021 /* Set the H bit on BLX instructions. */
27025 newval |= 0x01000000;
27027 newval &= ~0x01000000;
27029 md_number_to_chars (buf, newval, INSN_SIZE);
27033 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
27034 /* CBZ can only branch forward. */
27036 /* Attempts to use CBZ to branch to the next instruction
27037 (which, strictly speaking, are prohibited) will be turned into
27040 FIXME: It may be better to remove the instruction completely and
27041 perform relaxation. */
27044 newval = md_chars_to_number (buf, THUMB_SIZE);
27045 newval = 0xbf00; /* NOP encoding T1 */
27046 md_number_to_chars (buf, newval, THUMB_SIZE);
27051 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27053 if (fixP->fx_done || !seg->use_rela_p)
27055 newval = md_chars_to_number (buf, THUMB_SIZE);
27056 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
27057 md_number_to_chars (buf, newval, THUMB_SIZE);
27062 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
27063 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
27064 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27066 if (fixP->fx_done || !seg->use_rela_p)
27068 newval = md_chars_to_number (buf, THUMB_SIZE);
27069 newval |= (value & 0x1ff) >> 1;
27070 md_number_to_chars (buf, newval, THUMB_SIZE);
27074 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
27075 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
27076 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27078 if (fixP->fx_done || !seg->use_rela_p)
27080 newval = md_chars_to_number (buf, THUMB_SIZE);
27081 newval |= (value & 0xfff) >> 1;
27082 md_number_to_chars (buf, newval, THUMB_SIZE);
27086 case BFD_RELOC_THUMB_PCREL_BRANCH20:
27088 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27089 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27090 && ARM_IS_FUNC (fixP->fx_addsy)
27091 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27093 /* Force a relocation for a branch 20 bits wide. */
27096 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
27097 as_bad_where (fixP->fx_file, fixP->fx_line,
27098 _("conditional branch out of range"));
27100 if (fixP->fx_done || !seg->use_rela_p)
27103 addressT S, J1, J2, lo, hi;
27105 S = (value & 0x00100000) >> 20;
27106 J2 = (value & 0x00080000) >> 19;
27107 J1 = (value & 0x00040000) >> 18;
27108 hi = (value & 0x0003f000) >> 12;
27109 lo = (value & 0x00000ffe) >> 1;
27111 newval = md_chars_to_number (buf, THUMB_SIZE);
27112 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27113 newval |= (S << 10) | hi;
27114 newval2 |= (J1 << 13) | (J2 << 11) | lo;
27115 md_number_to_chars (buf, newval, THUMB_SIZE);
27116 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27120 case BFD_RELOC_THUMB_PCREL_BLX:
27121 /* If there is a blx from a thumb state function to
27122 another thumb function flip this to a bl and warn
27126 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27127 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27128 && THUMB_IS_FUNC (fixP->fx_addsy))
27130 const char *name = S_GET_NAME (fixP->fx_addsy);
27131 as_warn_where (fixP->fx_file, fixP->fx_line,
27132 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27134 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27135 newval = newval | 0x1000;
27136 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27137 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27142 goto thumb_bl_common;
27144 case BFD_RELOC_THUMB_PCREL_BRANCH23:
27145 /* A bl from Thumb state ISA to an internal ARM state function
27146 is converted to a blx. */
27148 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27149 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27150 && ARM_IS_FUNC (fixP->fx_addsy)
27151 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27153 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27154 newval = newval & ~0x1000;
27155 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27156 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
27162 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27163 /* For a BLX instruction, make sure that the relocation is rounded up
27164 to a word boundary. This follows the semantics of the instruction
27165 which specifies that bit 1 of the target address will come from bit
27166 1 of the base address. */
27167 value = (value + 3) & ~ 3;
27170 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
27171 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27172 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27175 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
27177 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
27178 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27179 else if ((value & ~0x1ffffff)
27180 && ((value & ~0x1ffffff) != ~0x1ffffff))
27181 as_bad_where (fixP->fx_file, fixP->fx_line,
27182 _("Thumb2 branch out of range"));
27185 if (fixP->fx_done || !seg->use_rela_p)
27186 encode_thumb2_b_bl_offset (buf, value);
27190 case BFD_RELOC_THUMB_PCREL_BRANCH25:
27191 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
27192 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27194 if (fixP->fx_done || !seg->use_rela_p)
27195 encode_thumb2_b_bl_offset (buf, value);
27200 if (fixP->fx_done || !seg->use_rela_p)
27205 if (fixP->fx_done || !seg->use_rela_p)
27206 md_number_to_chars (buf, value, 2);
27210 case BFD_RELOC_ARM_TLS_CALL:
27211 case BFD_RELOC_ARM_THM_TLS_CALL:
27212 case BFD_RELOC_ARM_TLS_DESCSEQ:
27213 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
27214 case BFD_RELOC_ARM_TLS_GOTDESC:
27215 case BFD_RELOC_ARM_TLS_GD32:
27216 case BFD_RELOC_ARM_TLS_LE32:
27217 case BFD_RELOC_ARM_TLS_IE32:
27218 case BFD_RELOC_ARM_TLS_LDM32:
27219 case BFD_RELOC_ARM_TLS_LDO32:
27220 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27223 /* Same handling as above, but with the arm_fdpic guard. */
27224 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
27225 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
27226 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
27229 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27233 as_bad_where (fixP->fx_file, fixP->fx_line,
27234 _("Relocation supported only in FDPIC mode"));
27238 case BFD_RELOC_ARM_GOT32:
27239 case BFD_RELOC_ARM_GOTOFF:
27242 case BFD_RELOC_ARM_GOT_PREL:
27243 if (fixP->fx_done || !seg->use_rela_p)
27244 md_number_to_chars (buf, value, 4);
27247 case BFD_RELOC_ARM_TARGET2:
27248 /* TARGET2 is not partial-inplace, so we need to write the
27249 addend here for REL targets, because it won't be written out
27250 during reloc processing later. */
27251 if (fixP->fx_done || !seg->use_rela_p)
27252 md_number_to_chars (buf, fixP->fx_offset, 4);
27255 /* Relocations for FDPIC. */
27256 case BFD_RELOC_ARM_GOTFUNCDESC:
27257 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
27258 case BFD_RELOC_ARM_FUNCDESC:
27261 if (fixP->fx_done || !seg->use_rela_p)
27262 md_number_to_chars (buf, 0, 4);
27266 as_bad_where (fixP->fx_file, fixP->fx_line,
27267 _("Relocation supported only in FDPIC mode"));
27272 case BFD_RELOC_RVA:
27274 case BFD_RELOC_ARM_TARGET1:
27275 case BFD_RELOC_ARM_ROSEGREL32:
27276 case BFD_RELOC_ARM_SBREL32:
27277 case BFD_RELOC_32_PCREL:
27279 case BFD_RELOC_32_SECREL:
27281 if (fixP->fx_done || !seg->use_rela_p)
27283 /* For WinCE we only do this for pcrel fixups. */
27284 if (fixP->fx_done || fixP->fx_pcrel)
27286 md_number_to_chars (buf, value, 4);
27290 case BFD_RELOC_ARM_PREL31:
27291 if (fixP->fx_done || !seg->use_rela_p)
27293 newval = md_chars_to_number (buf, 4) & 0x80000000;
27294 if ((value ^ (value >> 1)) & 0x40000000)
27296 as_bad_where (fixP->fx_file, fixP->fx_line,
27297 _("rel31 relocation overflow"));
27299 newval |= value & 0x7fffffff;
27300 md_number_to_chars (buf, newval, 4);
27305 case BFD_RELOC_ARM_CP_OFF_IMM:
27306 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
27307 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
27308 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
27309 newval = md_chars_to_number (buf, INSN_SIZE);
27311 newval = get_thumb32_insn (buf);
27312 if ((newval & 0x0f200f00) == 0x0d000900)
27314 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27315 has permitted values that are multiples of 2, in the range 0
27317 if (value < -510 || value > 510 || (value & 1))
27318 as_bad_where (fixP->fx_file, fixP->fx_line,
27319 _("co-processor offset out of range"));
27321 else if ((newval & 0xfe001f80) == 0xec000f80)
27323 if (value < -511 || value > 512 || (value & 3))
27324 as_bad_where (fixP->fx_file, fixP->fx_line,
27325 _("co-processor offset out of range"));
27327 else if (value < -1023 || value > 1023 || (value & 3))
27328 as_bad_where (fixP->fx_file, fixP->fx_line,
27329 _("co-processor offset out of range"));
27334 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27335 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27336 newval = md_chars_to_number (buf, INSN_SIZE);
27338 newval = get_thumb32_insn (buf);
27341 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27342 newval &= 0xffffff80;
27344 newval &= 0xffffff00;
27348 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27349 newval &= 0xff7fff80;
27351 newval &= 0xff7fff00;
27352 if ((newval & 0x0f200f00) == 0x0d000900)
27354 /* This is a fp16 vstr/vldr.
27356 It requires the immediate offset in the instruction is shifted
27357 left by 1 to be a half-word offset.
27359 Here, left shift by 1 first, and later right shift by 2
27360 should get the right offset. */
27363 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
27365 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27366 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27367 md_number_to_chars (buf, newval, INSN_SIZE);
27369 put_thumb32_insn (buf, newval);
27372 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
27373 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
27374 if (value < -255 || value > 255)
27375 as_bad_where (fixP->fx_file, fixP->fx_line,
27376 _("co-processor offset out of range"));
27378 goto cp_off_common;
27380 case BFD_RELOC_ARM_THUMB_OFFSET:
27381 newval = md_chars_to_number (buf, THUMB_SIZE);
27382 /* Exactly what ranges, and where the offset is inserted depends
27383 on the type of instruction, we can establish this from the
27385 switch (newval >> 12)
27387 case 4: /* PC load. */
27388 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27389 forced to zero for these loads; md_pcrel_from has already
27390 compensated for this. */
27392 as_bad_where (fixP->fx_file, fixP->fx_line,
27393 _("invalid offset, target not word aligned (0x%08lX)"),
27394 (((unsigned long) fixP->fx_frag->fr_address
27395 + (unsigned long) fixP->fx_where) & ~3)
27396 + (unsigned long) value);
27398 if (value & ~0x3fc)
27399 as_bad_where (fixP->fx_file, fixP->fx_line,
27400 _("invalid offset, value too big (0x%08lX)"),
27403 newval |= value >> 2;
27406 case 9: /* SP load/store. */
27407 if (value & ~0x3fc)
27408 as_bad_where (fixP->fx_file, fixP->fx_line,
27409 _("invalid offset, value too big (0x%08lX)"),
27411 newval |= value >> 2;
27414 case 6: /* Word load/store. */
27416 as_bad_where (fixP->fx_file, fixP->fx_line,
27417 _("invalid offset, value too big (0x%08lX)"),
27419 newval |= value << 4; /* 6 - 2. */
27422 case 7: /* Byte load/store. */
27424 as_bad_where (fixP->fx_file, fixP->fx_line,
27425 _("invalid offset, value too big (0x%08lX)"),
27427 newval |= value << 6;
27430 case 8: /* Halfword load/store. */
27432 as_bad_where (fixP->fx_file, fixP->fx_line,
27433 _("invalid offset, value too big (0x%08lX)"),
27435 newval |= value << 5; /* 6 - 1. */
27439 as_bad_where (fixP->fx_file, fixP->fx_line,
27440 "Unable to process relocation for thumb opcode: %lx",
27441 (unsigned long) newval);
27444 md_number_to_chars (buf, newval, THUMB_SIZE);
27447 case BFD_RELOC_ARM_THUMB_ADD:
27448 /* This is a complicated relocation, since we use it for all of
27449 the following immediate relocations:
27453 9bit ADD/SUB SP word-aligned
27454 10bit ADD PC/SP word-aligned
27456 The type of instruction being processed is encoded in the
27463 newval = md_chars_to_number (buf, THUMB_SIZE);
27465 int rd = (newval >> 4) & 0xf;
27466 int rs = newval & 0xf;
27467 int subtract = !!(newval & 0x8000);
27469 /* Check for HI regs, only very restricted cases allowed:
27470 Adjusting SP, and using PC or SP to get an address. */
27471 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
27472 || (rs > 7 && rs != REG_SP && rs != REG_PC))
27473 as_bad_where (fixP->fx_file, fixP->fx_line,
27474 _("invalid Hi register with immediate"));
27476 /* If value is negative, choose the opposite instruction. */
27480 subtract = !subtract;
27482 as_bad_where (fixP->fx_file, fixP->fx_line,
27483 _("immediate value out of range"));
27488 if (value & ~0x1fc)
27489 as_bad_where (fixP->fx_file, fixP->fx_line,
27490 _("invalid immediate for stack address calculation"));
27491 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
27492 newval |= value >> 2;
27494 else if (rs == REG_PC || rs == REG_SP)
27496 /* PR gas/18541. If the addition is for a defined symbol
27497 within range of an ADR instruction then accept it. */
27500 && fixP->fx_addsy != NULL)
27504 if (! S_IS_DEFINED (fixP->fx_addsy)
27505 || S_GET_SEGMENT (fixP->fx_addsy) != seg
27506 || S_IS_WEAK (fixP->fx_addsy))
27508 as_bad_where (fixP->fx_file, fixP->fx_line,
27509 _("address calculation needs a strongly defined nearby symbol"));
27513 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
27515 /* Round up to the next 4-byte boundary. */
27520 v = S_GET_VALUE (fixP->fx_addsy) - v;
27524 as_bad_where (fixP->fx_file, fixP->fx_line,
27525 _("symbol too far away"));
27535 if (subtract || value & ~0x3fc)
27536 as_bad_where (fixP->fx_file, fixP->fx_line,
27537 _("invalid immediate for address calculation (value = 0x%08lX)"),
27538 (unsigned long) (subtract ? - value : value));
27539 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
27541 newval |= value >> 2;
27546 as_bad_where (fixP->fx_file, fixP->fx_line,
27547 _("immediate value out of range"));
27548 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
27549 newval |= (rd << 8) | value;
27554 as_bad_where (fixP->fx_file, fixP->fx_line,
27555 _("immediate value out of range"));
27556 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
27557 newval |= rd | (rs << 3) | (value << 6);
27560 md_number_to_chars (buf, newval, THUMB_SIZE);
27563 case BFD_RELOC_ARM_THUMB_IMM:
27564 newval = md_chars_to_number (buf, THUMB_SIZE);
27565 if (value < 0 || value > 255)
27566 as_bad_where (fixP->fx_file, fixP->fx_line,
27567 _("invalid immediate: %ld is out of range"),
27570 md_number_to_chars (buf, newval, THUMB_SIZE);
27573 case BFD_RELOC_ARM_THUMB_SHIFT:
27574 /* 5bit shift value (0..32). LSL cannot take 32. */
27575 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
27576 temp = newval & 0xf800;
27577 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
27578 as_bad_where (fixP->fx_file, fixP->fx_line,
27579 _("invalid shift value: %ld"), (long) value);
27580 /* Shifts of zero must be encoded as LSL. */
27582 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
27583 /* Shifts of 32 are encoded as zero. */
27584 else if (value == 32)
27586 newval |= value << 6;
27587 md_number_to_chars (buf, newval, THUMB_SIZE);
27590 case BFD_RELOC_VTABLE_INHERIT:
27591 case BFD_RELOC_VTABLE_ENTRY:
27595 case BFD_RELOC_ARM_MOVW:
27596 case BFD_RELOC_ARM_MOVT:
27597 case BFD_RELOC_ARM_THUMB_MOVW:
27598 case BFD_RELOC_ARM_THUMB_MOVT:
27599 if (fixP->fx_done || !seg->use_rela_p)
27601 /* REL format relocations are limited to a 16-bit addend. */
27602 if (!fixP->fx_done)
27604 if (value < -0x8000 || value > 0x7fff)
27605 as_bad_where (fixP->fx_file, fixP->fx_line,
27606 _("offset out of range"));
27608 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
27609 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
27614 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
27615 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
27617 newval = get_thumb32_insn (buf);
27618 newval &= 0xfbf08f00;
27619 newval |= (value & 0xf000) << 4;
27620 newval |= (value & 0x0800) << 15;
27621 newval |= (value & 0x0700) << 4;
27622 newval |= (value & 0x00ff);
27623 put_thumb32_insn (buf, newval);
27627 newval = md_chars_to_number (buf, 4);
27628 newval &= 0xfff0f000;
27629 newval |= value & 0x0fff;
27630 newval |= (value & 0xf000) << 4;
27631 md_number_to_chars (buf, newval, 4);
27636 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
27637 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
27638 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
27639 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
27640 gas_assert (!fixP->fx_done);
27643 bfd_boolean is_mov;
27644 bfd_vma encoded_addend = value;
27646 /* Check that addend can be encoded in instruction. */
27647 if (!seg->use_rela_p && (value < 0 || value > 255))
27648 as_bad_where (fixP->fx_file, fixP->fx_line,
27649 _("the offset 0x%08lX is not representable"),
27650 (unsigned long) encoded_addend);
27652 /* Extract the instruction. */
27653 insn = md_chars_to_number (buf, THUMB_SIZE);
27654 is_mov = (insn & 0xf800) == 0x2000;
27659 if (!seg->use_rela_p)
27660 insn |= encoded_addend;
27666 /* Extract the instruction. */
27667 /* Encoding is the following
27672 /* The following conditions must be true :
27677 rd = (insn >> 4) & 0xf;
27679 if ((insn & 0x8000) || (rd != rs) || rd > 7)
27680 as_bad_where (fixP->fx_file, fixP->fx_line,
27681 _("Unable to process relocation for thumb opcode: %lx"),
27682 (unsigned long) insn);
27684 /* Encode as ADD immediate8 thumb 1 code. */
27685 insn = 0x3000 | (rd << 8);
27687 /* Place the encoded addend into the first 8 bits of the
27689 if (!seg->use_rela_p)
27690 insn |= encoded_addend;
27693 /* Update the instruction. */
27694 md_number_to_chars (buf, insn, THUMB_SIZE);
27698 case BFD_RELOC_ARM_ALU_PC_G0_NC:
27699 case BFD_RELOC_ARM_ALU_PC_G0:
27700 case BFD_RELOC_ARM_ALU_PC_G1_NC:
27701 case BFD_RELOC_ARM_ALU_PC_G1:
27702 case BFD_RELOC_ARM_ALU_PC_G2:
27703 case BFD_RELOC_ARM_ALU_SB_G0_NC:
27704 case BFD_RELOC_ARM_ALU_SB_G0:
27705 case BFD_RELOC_ARM_ALU_SB_G1_NC:
27706 case BFD_RELOC_ARM_ALU_SB_G1:
27707 case BFD_RELOC_ARM_ALU_SB_G2:
27708 gas_assert (!fixP->fx_done);
27709 if (!seg->use_rela_p)
27712 bfd_vma encoded_addend;
27713 bfd_vma addend_abs = llabs (value);
27715 /* Check that the absolute value of the addend can be
27716 expressed as an 8-bit constant plus a rotation. */
27717 encoded_addend = encode_arm_immediate (addend_abs);
27718 if (encoded_addend == (unsigned int) FAIL)
27719 as_bad_where (fixP->fx_file, fixP->fx_line,
27720 _("the offset 0x%08lX is not representable"),
27721 (unsigned long) addend_abs);
27723 /* Extract the instruction. */
27724 insn = md_chars_to_number (buf, INSN_SIZE);
27726 /* If the addend is positive, use an ADD instruction.
27727 Otherwise use a SUB. Take care not to destroy the S bit. */
27728 insn &= 0xff1fffff;
27734 /* Place the encoded addend into the first 12 bits of the
27736 insn &= 0xfffff000;
27737 insn |= encoded_addend;
27739 /* Update the instruction. */
27740 md_number_to_chars (buf, insn, INSN_SIZE);
27744 case BFD_RELOC_ARM_LDR_PC_G0:
27745 case BFD_RELOC_ARM_LDR_PC_G1:
27746 case BFD_RELOC_ARM_LDR_PC_G2:
27747 case BFD_RELOC_ARM_LDR_SB_G0:
27748 case BFD_RELOC_ARM_LDR_SB_G1:
27749 case BFD_RELOC_ARM_LDR_SB_G2:
27750 gas_assert (!fixP->fx_done);
27751 if (!seg->use_rela_p)
27754 bfd_vma addend_abs = llabs (value);
27756 /* Check that the absolute value of the addend can be
27757 encoded in 12 bits. */
27758 if (addend_abs >= 0x1000)
27759 as_bad_where (fixP->fx_file, fixP->fx_line,
27760 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27761 (unsigned long) addend_abs);
27763 /* Extract the instruction. */
27764 insn = md_chars_to_number (buf, INSN_SIZE);
27766 /* If the addend is negative, clear bit 23 of the instruction.
27767 Otherwise set it. */
27769 insn &= ~(1 << 23);
27773 /* Place the absolute value of the addend into the first 12 bits
27774 of the instruction. */
27775 insn &= 0xfffff000;
27776 insn |= addend_abs;
27778 /* Update the instruction. */
27779 md_number_to_chars (buf, insn, INSN_SIZE);
27783 case BFD_RELOC_ARM_LDRS_PC_G0:
27784 case BFD_RELOC_ARM_LDRS_PC_G1:
27785 case BFD_RELOC_ARM_LDRS_PC_G2:
27786 case BFD_RELOC_ARM_LDRS_SB_G0:
27787 case BFD_RELOC_ARM_LDRS_SB_G1:
27788 case BFD_RELOC_ARM_LDRS_SB_G2:
27789 gas_assert (!fixP->fx_done);
27790 if (!seg->use_rela_p)
27793 bfd_vma addend_abs = llabs (value);
27795 /* Check that the absolute value of the addend can be
27796 encoded in 8 bits. */
27797 if (addend_abs >= 0x100)
27798 as_bad_where (fixP->fx_file, fixP->fx_line,
27799 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27800 (unsigned long) addend_abs);
27802 /* Extract the instruction. */
27803 insn = md_chars_to_number (buf, INSN_SIZE);
27805 /* If the addend is negative, clear bit 23 of the instruction.
27806 Otherwise set it. */
27808 insn &= ~(1 << 23);
27812 /* Place the first four bits of the absolute value of the addend
27813 into the first 4 bits of the instruction, and the remaining
27814 four into bits 8 .. 11. */
27815 insn &= 0xfffff0f0;
27816 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
27818 /* Update the instruction. */
27819 md_number_to_chars (buf, insn, INSN_SIZE);
27823 case BFD_RELOC_ARM_LDC_PC_G0:
27824 case BFD_RELOC_ARM_LDC_PC_G1:
27825 case BFD_RELOC_ARM_LDC_PC_G2:
27826 case BFD_RELOC_ARM_LDC_SB_G0:
27827 case BFD_RELOC_ARM_LDC_SB_G1:
27828 case BFD_RELOC_ARM_LDC_SB_G2:
27829 gas_assert (!fixP->fx_done);
27830 if (!seg->use_rela_p)
27833 bfd_vma addend_abs = llabs (value);
27835 /* Check that the absolute value of the addend is a multiple of
27836 four and, when divided by four, fits in 8 bits. */
27837 if (addend_abs & 0x3)
27838 as_bad_where (fixP->fx_file, fixP->fx_line,
27839 _("bad offset 0x%08lX (must be word-aligned)"),
27840 (unsigned long) addend_abs);
27842 if ((addend_abs >> 2) > 0xff)
27843 as_bad_where (fixP->fx_file, fixP->fx_line,
27844 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27845 (unsigned long) addend_abs);
27847 /* Extract the instruction. */
27848 insn = md_chars_to_number (buf, INSN_SIZE);
27850 /* If the addend is negative, clear bit 23 of the instruction.
27851 Otherwise set it. */
27853 insn &= ~(1 << 23);
27857 /* Place the addend (divided by four) into the first eight
27858 bits of the instruction. */
27859 insn &= 0xfffffff0;
27860 insn |= addend_abs >> 2;
27862 /* Update the instruction. */
27863 md_number_to_chars (buf, insn, INSN_SIZE);
27867 case BFD_RELOC_THUMB_PCREL_BRANCH5:
27869 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27870 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27871 && ARM_IS_FUNC (fixP->fx_addsy)
27872 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27874 /* Force a relocation for a branch 5 bits wide. */
27877 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
27878 as_bad_where (fixP->fx_file, fixP->fx_line,
27881 if (fixP->fx_done || !seg->use_rela_p)
27883 addressT boff = value >> 1;
27885 newval = md_chars_to_number (buf, THUMB_SIZE);
27886 newval |= (boff << 7);
27887 md_number_to_chars (buf, newval, THUMB_SIZE);
27891 case BFD_RELOC_THUMB_PCREL_BFCSEL:
27893 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27894 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27895 && ARM_IS_FUNC (fixP->fx_addsy)
27896 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27900 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
27901 as_bad_where (fixP->fx_file, fixP->fx_line,
27902 _("branch out of range"));
27904 if (fixP->fx_done || !seg->use_rela_p)
27906 newval = md_chars_to_number (buf, THUMB_SIZE);
27908 addressT boff = ((newval & 0x0780) >> 7) << 1;
27909 addressT diff = value - boff;
27913 newval |= 1 << 1; /* T bit. */
27915 else if (diff != 2)
27917 as_bad_where (fixP->fx_file, fixP->fx_line,
27918 _("out of range label-relative fixup value"));
27920 md_number_to_chars (buf, newval, THUMB_SIZE);
27924 case BFD_RELOC_ARM_THUMB_BF17:
27926 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27927 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27928 && ARM_IS_FUNC (fixP->fx_addsy)
27929 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27931 /* Force a relocation for a branch 17 bits wide. */
27935 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
27936 as_bad_where (fixP->fx_file, fixP->fx_line,
27939 if (fixP->fx_done || !seg->use_rela_p)
27942 addressT immA, immB, immC;
27944 immA = (value & 0x0001f000) >> 12;
27945 immB = (value & 0x00000ffc) >> 2;
27946 immC = (value & 0x00000002) >> 1;
27948 newval = md_chars_to_number (buf, THUMB_SIZE);
27949 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27951 newval2 |= (immC << 11) | (immB << 1);
27952 md_number_to_chars (buf, newval, THUMB_SIZE);
27953 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27957 case BFD_RELOC_ARM_THUMB_BF19:
27959 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27960 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27961 && ARM_IS_FUNC (fixP->fx_addsy)
27962 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27964 /* Force a relocation for a branch 19 bits wide. */
27968 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
27969 as_bad_where (fixP->fx_file, fixP->fx_line,
27972 if (fixP->fx_done || !seg->use_rela_p)
27975 addressT immA, immB, immC;
27977 immA = (value & 0x0007f000) >> 12;
27978 immB = (value & 0x00000ffc) >> 2;
27979 immC = (value & 0x00000002) >> 1;
27981 newval = md_chars_to_number (buf, THUMB_SIZE);
27982 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27984 newval2 |= (immC << 11) | (immB << 1);
27985 md_number_to_chars (buf, newval, THUMB_SIZE);
27986 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27990 case BFD_RELOC_ARM_THUMB_BF13:
27992 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27993 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27994 && ARM_IS_FUNC (fixP->fx_addsy)
27995 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27997 /* Force a relocation for a branch 13 bits wide. */
28001 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
28002 as_bad_where (fixP->fx_file, fixP->fx_line,
28005 if (fixP->fx_done || !seg->use_rela_p)
28008 addressT immA, immB, immC;
28010 immA = (value & 0x00001000) >> 12;
28011 immB = (value & 0x00000ffc) >> 2;
28012 immC = (value & 0x00000002) >> 1;
28014 newval = md_chars_to_number (buf, THUMB_SIZE);
28015 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28017 newval2 |= (immC << 11) | (immB << 1);
28018 md_number_to_chars (buf, newval, THUMB_SIZE);
28019 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28023 case BFD_RELOC_ARM_THUMB_LOOP12:
28025 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28026 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28027 && ARM_IS_FUNC (fixP->fx_addsy)
28028 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28030 /* Force a relocation for a branch 12 bits wide. */
28034 bfd_vma insn = get_thumb32_insn (buf);
28035 /* le lr, <label> or le <label> */
28036 if (((insn & 0xffffffff) == 0xf00fc001)
28037 || ((insn & 0xffffffff) == 0xf02fc001))
28040 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
28041 as_bad_where (fixP->fx_file, fixP->fx_line,
28043 if (fixP->fx_done || !seg->use_rela_p)
28045 addressT imml, immh;
28047 immh = (value & 0x00000ffc) >> 2;
28048 imml = (value & 0x00000002) >> 1;
28050 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28051 newval |= (imml << 11) | (immh << 1);
28052 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
28056 case BFD_RELOC_ARM_V4BX:
28057 /* This will need to go in the object file. */
28061 case BFD_RELOC_UNUSED:
28063 as_bad_where (fixP->fx_file, fixP->fx_line,
28064 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
28068 /* Translate internal representation of relocation info to BFD target
28072 tc_gen_reloc (asection *section, fixS *fixp)
28075 bfd_reloc_code_real_type code;
28077 reloc = XNEW (arelent);
28079 reloc->sym_ptr_ptr = XNEW (asymbol *);
28080 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
28081 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
28083 if (fixp->fx_pcrel)
28085 if (section->use_rela_p)
28086 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
28088 fixp->fx_offset = reloc->address;
28090 reloc->addend = fixp->fx_offset;
28092 switch (fixp->fx_r_type)
28095 if (fixp->fx_pcrel)
28097 code = BFD_RELOC_8_PCREL;
28100 /* Fall through. */
28103 if (fixp->fx_pcrel)
28105 code = BFD_RELOC_16_PCREL;
28108 /* Fall through. */
28111 if (fixp->fx_pcrel)
28113 code = BFD_RELOC_32_PCREL;
28116 /* Fall through. */
28118 case BFD_RELOC_ARM_MOVW:
28119 if (fixp->fx_pcrel)
28121 code = BFD_RELOC_ARM_MOVW_PCREL;
28124 /* Fall through. */
28126 case BFD_RELOC_ARM_MOVT:
28127 if (fixp->fx_pcrel)
28129 code = BFD_RELOC_ARM_MOVT_PCREL;
28132 /* Fall through. */
28134 case BFD_RELOC_ARM_THUMB_MOVW:
28135 if (fixp->fx_pcrel)
28137 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
28140 /* Fall through. */
28142 case BFD_RELOC_ARM_THUMB_MOVT:
28143 if (fixp->fx_pcrel)
28145 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
28148 /* Fall through. */
28150 case BFD_RELOC_NONE:
28151 case BFD_RELOC_ARM_PCREL_BRANCH:
28152 case BFD_RELOC_ARM_PCREL_BLX:
28153 case BFD_RELOC_RVA:
28154 case BFD_RELOC_THUMB_PCREL_BRANCH7:
28155 case BFD_RELOC_THUMB_PCREL_BRANCH9:
28156 case BFD_RELOC_THUMB_PCREL_BRANCH12:
28157 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28158 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28159 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28160 case BFD_RELOC_VTABLE_ENTRY:
28161 case BFD_RELOC_VTABLE_INHERIT:
28163 case BFD_RELOC_32_SECREL:
28165 code = fixp->fx_r_type;
28168 case BFD_RELOC_THUMB_PCREL_BLX:
28170 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
28171 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
28174 code = BFD_RELOC_THUMB_PCREL_BLX;
28177 case BFD_RELOC_ARM_LITERAL:
28178 case BFD_RELOC_ARM_HWLITERAL:
28179 /* If this is called then the a literal has
28180 been referenced across a section boundary. */
28181 as_bad_where (fixp->fx_file, fixp->fx_line,
28182 _("literal referenced across section boundary"));
28186 case BFD_RELOC_ARM_TLS_CALL:
28187 case BFD_RELOC_ARM_THM_TLS_CALL:
28188 case BFD_RELOC_ARM_TLS_DESCSEQ:
28189 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
28190 case BFD_RELOC_ARM_GOT32:
28191 case BFD_RELOC_ARM_GOTOFF:
28192 case BFD_RELOC_ARM_GOT_PREL:
28193 case BFD_RELOC_ARM_PLT32:
28194 case BFD_RELOC_ARM_TARGET1:
28195 case BFD_RELOC_ARM_ROSEGREL32:
28196 case BFD_RELOC_ARM_SBREL32:
28197 case BFD_RELOC_ARM_PREL31:
28198 case BFD_RELOC_ARM_TARGET2:
28199 case BFD_RELOC_ARM_TLS_LDO32:
28200 case BFD_RELOC_ARM_PCREL_CALL:
28201 case BFD_RELOC_ARM_PCREL_JUMP:
28202 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28203 case BFD_RELOC_ARM_ALU_PC_G0:
28204 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28205 case BFD_RELOC_ARM_ALU_PC_G1:
28206 case BFD_RELOC_ARM_ALU_PC_G2:
28207 case BFD_RELOC_ARM_LDR_PC_G0:
28208 case BFD_RELOC_ARM_LDR_PC_G1:
28209 case BFD_RELOC_ARM_LDR_PC_G2:
28210 case BFD_RELOC_ARM_LDRS_PC_G0:
28211 case BFD_RELOC_ARM_LDRS_PC_G1:
28212 case BFD_RELOC_ARM_LDRS_PC_G2:
28213 case BFD_RELOC_ARM_LDC_PC_G0:
28214 case BFD_RELOC_ARM_LDC_PC_G1:
28215 case BFD_RELOC_ARM_LDC_PC_G2:
28216 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28217 case BFD_RELOC_ARM_ALU_SB_G0:
28218 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28219 case BFD_RELOC_ARM_ALU_SB_G1:
28220 case BFD_RELOC_ARM_ALU_SB_G2:
28221 case BFD_RELOC_ARM_LDR_SB_G0:
28222 case BFD_RELOC_ARM_LDR_SB_G1:
28223 case BFD_RELOC_ARM_LDR_SB_G2:
28224 case BFD_RELOC_ARM_LDRS_SB_G0:
28225 case BFD_RELOC_ARM_LDRS_SB_G1:
28226 case BFD_RELOC_ARM_LDRS_SB_G2:
28227 case BFD_RELOC_ARM_LDC_SB_G0:
28228 case BFD_RELOC_ARM_LDC_SB_G1:
28229 case BFD_RELOC_ARM_LDC_SB_G2:
28230 case BFD_RELOC_ARM_V4BX:
28231 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28232 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28233 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28234 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28235 case BFD_RELOC_ARM_GOTFUNCDESC:
28236 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28237 case BFD_RELOC_ARM_FUNCDESC:
28238 case BFD_RELOC_ARM_THUMB_BF17:
28239 case BFD_RELOC_ARM_THUMB_BF19:
28240 case BFD_RELOC_ARM_THUMB_BF13:
28241 code = fixp->fx_r_type;
28244 case BFD_RELOC_ARM_TLS_GOTDESC:
28245 case BFD_RELOC_ARM_TLS_GD32:
28246 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28247 case BFD_RELOC_ARM_TLS_LE32:
28248 case BFD_RELOC_ARM_TLS_IE32:
28249 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28250 case BFD_RELOC_ARM_TLS_LDM32:
28251 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28252 /* BFD will include the symbol's address in the addend.
28253 But we don't want that, so subtract it out again here. */
28254 if (!S_IS_COMMON (fixp->fx_addsy))
28255 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
28256 code = fixp->fx_r_type;
28260 case BFD_RELOC_ARM_IMMEDIATE:
28261 as_bad_where (fixp->fx_file, fixp->fx_line,
28262 _("internal relocation (type: IMMEDIATE) not fixed up"));
28265 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28266 as_bad_where (fixp->fx_file, fixp->fx_line,
28267 _("ADRL used for a symbol not defined in the same file"));
28270 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28271 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28272 case BFD_RELOC_ARM_THUMB_LOOP12:
28273 as_bad_where (fixp->fx_file, fixp->fx_line,
28274 _("%s used for a symbol not defined in the same file"),
28275 bfd_get_reloc_code_name (fixp->fx_r_type));
28278 case BFD_RELOC_ARM_OFFSET_IMM:
28279 if (section->use_rela_p)
28281 code = fixp->fx_r_type;
28285 if (fixp->fx_addsy != NULL
28286 && !S_IS_DEFINED (fixp->fx_addsy)
28287 && S_IS_LOCAL (fixp->fx_addsy))
28289 as_bad_where (fixp->fx_file, fixp->fx_line,
28290 _("undefined local label `%s'"),
28291 S_GET_NAME (fixp->fx_addsy));
28295 as_bad_where (fixp->fx_file, fixp->fx_line,
28296 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28303 switch (fixp->fx_r_type)
28305 case BFD_RELOC_NONE: type = "NONE"; break;
28306 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
28307 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
28308 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
28309 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
28310 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
28311 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
28312 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
28313 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
28314 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
28315 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
28316 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
28317 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
28318 default: type = _("<unknown>"); break;
28320 as_bad_where (fixp->fx_file, fixp->fx_line,
28321 _("cannot represent %s relocation in this object file format"),
28328 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
28330 && fixp->fx_addsy == GOT_symbol)
28332 code = BFD_RELOC_ARM_GOTPC;
28333 reloc->addend = fixp->fx_offset = reloc->address;
28337 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
28339 if (reloc->howto == NULL)
28341 as_bad_where (fixp->fx_file, fixp->fx_line,
28342 _("cannot represent %s relocation in this object file format"),
28343 bfd_get_reloc_code_name (code));
28347 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28348 vtable entry to be used in the relocation's section offset. */
28349 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
28350 reloc->address = fixp->fx_offset;
28355 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28358 cons_fix_new_arm (fragS * frag,
28362 bfd_reloc_code_real_type reloc)
28367 FIXME: @@ Should look at CPU word size. */
28371 reloc = BFD_RELOC_8;
28374 reloc = BFD_RELOC_16;
28378 reloc = BFD_RELOC_32;
28381 reloc = BFD_RELOC_64;
28386 if (exp->X_op == O_secrel)
28388 exp->X_op = O_symbol;
28389 reloc = BFD_RELOC_32_SECREL;
28393 fix_new_exp (frag, where, size, exp, pcrel, reloc);
28396 #if defined (OBJ_COFF)
28398 arm_validate_fix (fixS * fixP)
28400 /* If the destination of the branch is a defined symbol which does not have
28401 the THUMB_FUNC attribute, then we must be calling a function which has
28402 the (interfacearm) attribute. We look for the Thumb entry point to that
28403 function and change the branch to refer to that function instead. */
28404 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
28405 && fixP->fx_addsy != NULL
28406 && S_IS_DEFINED (fixP->fx_addsy)
28407 && ! THUMB_IS_FUNC (fixP->fx_addsy))
28409 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
28416 arm_force_relocation (struct fix * fixp)
28418 #if defined (OBJ_COFF) && defined (TE_PE)
28419 if (fixp->fx_r_type == BFD_RELOC_RVA)
28423 /* In case we have a call or a branch to a function in ARM ISA mode from
28424 a thumb function or vice-versa force the relocation. These relocations
28425 are cleared off for some cores that might have blx and simple transformations
28429 switch (fixp->fx_r_type)
28431 case BFD_RELOC_ARM_PCREL_JUMP:
28432 case BFD_RELOC_ARM_PCREL_CALL:
28433 case BFD_RELOC_THUMB_PCREL_BLX:
28434 if (THUMB_IS_FUNC (fixp->fx_addsy))
28438 case BFD_RELOC_ARM_PCREL_BLX:
28439 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28440 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28441 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28442 if (ARM_IS_FUNC (fixp->fx_addsy))
28451 /* Resolve these relocations even if the symbol is extern or weak.
28452 Technically this is probably wrong due to symbol preemption.
28453 In practice these relocations do not have enough range to be useful
28454 at dynamic link time, and some code (e.g. in the Linux kernel)
28455 expects these references to be resolved. */
28456 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
28457 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
28458 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
28459 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
28460 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28461 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
28462 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
28463 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
28464 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
28465 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
28466 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
28467 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
28468 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
28469 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
28472 /* Always leave these relocations for the linker. */
28473 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
28474 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
28475 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
28478 /* Always generate relocations against function symbols. */
28479 if (fixp->fx_r_type == BFD_RELOC_32
28481 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
28484 return generic_force_reloc (fixp);
28487 #if defined (OBJ_ELF) || defined (OBJ_COFF)
28488 /* Relocations against function names must be left unadjusted,
28489 so that the linker can use this information to generate interworking
28490 stubs. The MIPS version of this function
28491 also prevents relocations that are mips-16 specific, but I do not
28492 know why it does this.
28495 There is one other problem that ought to be addressed here, but
28496 which currently is not: Taking the address of a label (rather
28497 than a function) and then later jumping to that address. Such
28498 addresses also ought to have their bottom bit set (assuming that
28499 they reside in Thumb code), but at the moment they will not. */
28502 arm_fix_adjustable (fixS * fixP)
28504 if (fixP->fx_addsy == NULL)
28507 /* Preserve relocations against symbols with function type. */
28508 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
28511 if (THUMB_IS_FUNC (fixP->fx_addsy)
28512 && fixP->fx_subsy == NULL)
28515 /* We need the symbol name for the VTABLE entries. */
28516 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
28517 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
28520 /* Don't allow symbols to be discarded on GOT related relocs. */
28521 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
28522 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
28523 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
28524 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
28525 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
28526 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
28527 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
28528 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
28529 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
28530 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
28531 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
28532 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
28533 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
28534 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
28535 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
28536 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
28537 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
28540 /* Similarly for group relocations. */
28541 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
28542 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
28543 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
28546 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28547 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
28548 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28549 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
28550 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
28551 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28552 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
28553 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
28554 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
28557 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28558 offsets, so keep these symbols. */
28559 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28560 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
28565 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
28569 elf32_arm_target_format (void)
28572 return (target_big_endian
28573 ? "elf32-bigarm-symbian"
28574 : "elf32-littlearm-symbian");
28575 #elif defined (TE_VXWORKS)
28576 return (target_big_endian
28577 ? "elf32-bigarm-vxworks"
28578 : "elf32-littlearm-vxworks");
28579 #elif defined (TE_NACL)
28580 return (target_big_endian
28581 ? "elf32-bigarm-nacl"
28582 : "elf32-littlearm-nacl");
28586 if (target_big_endian)
28587 return "elf32-bigarm-fdpic";
28589 return "elf32-littlearm-fdpic";
28593 if (target_big_endian)
28594 return "elf32-bigarm";
28596 return "elf32-littlearm";
28602 armelf_frob_symbol (symbolS * symp,
28605 elf_frob_symbol (symp, puntp);
28609 /* MD interface: Finalization. */
28614 literal_pool * pool;
28616 /* Ensure that all the predication blocks are properly closed. */
28617 check_pred_blocks_finished ();
28619 for (pool = list_of_pools; pool; pool = pool->next)
28621 /* Put it at the end of the relevant section. */
28622 subseg_set (pool->section, pool->sub_section);
28624 arm_elf_change_section ();
28631 /* Remove any excess mapping symbols generated for alignment frags in
28632 SEC. We may have created a mapping symbol before a zero byte
28633 alignment; remove it if there's a mapping symbol after the
28636 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
28637 void *dummy ATTRIBUTE_UNUSED)
28639 segment_info_type *seginfo = seg_info (sec);
28642 if (seginfo == NULL || seginfo->frchainP == NULL)
28645 for (fragp = seginfo->frchainP->frch_root;
28647 fragp = fragp->fr_next)
28649 symbolS *sym = fragp->tc_frag_data.last_map;
28650 fragS *next = fragp->fr_next;
28652 /* Variable-sized frags have been converted to fixed size by
28653 this point. But if this was variable-sized to start with,
28654 there will be a fixed-size frag after it. So don't handle
28656 if (sym == NULL || next == NULL)
28659 if (S_GET_VALUE (sym) < next->fr_address)
28660 /* Not at the end of this frag. */
28662 know (S_GET_VALUE (sym) == next->fr_address);
28666 if (next->tc_frag_data.first_map != NULL)
28668 /* Next frag starts with a mapping symbol. Discard this
28670 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
28674 if (next->fr_next == NULL)
28676 /* This mapping symbol is at the end of the section. Discard
28678 know (next->fr_fix == 0 && next->fr_var == 0);
28679 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
28683 /* As long as we have empty frags without any mapping symbols,
28685 /* If the next frag is non-empty and does not start with a
28686 mapping symbol, then this mapping symbol is required. */
28687 if (next->fr_address != next->fr_next->fr_address)
28690 next = next->fr_next;
28692 while (next != NULL);
28697 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28701 arm_adjust_symtab (void)
28706 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
28708 if (ARM_IS_THUMB (sym))
28710 if (THUMB_IS_FUNC (sym))
28712 /* Mark the symbol as a Thumb function. */
28713 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
28714 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
28715 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
28717 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
28718 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
28720 as_bad (_("%s: unexpected function type: %d"),
28721 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
28723 else switch (S_GET_STORAGE_CLASS (sym))
28726 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
28729 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
28732 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
28740 if (ARM_IS_INTERWORK (sym))
28741 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
28748 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
28750 if (ARM_IS_THUMB (sym))
28752 elf_symbol_type * elf_sym;
28754 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
28755 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
28757 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
28758 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
28760 /* If it's a .thumb_func, declare it as so,
28761 otherwise tag label as .code 16. */
28762 if (THUMB_IS_FUNC (sym))
28763 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
28764 ST_BRANCH_TO_THUMB);
28765 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
28766 elf_sym->internal_elf_sym.st_info =
28767 ELF_ST_INFO (bind, STT_ARM_16BIT);
28772 /* Remove any overlapping mapping symbols generated by alignment frags. */
28773 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
28774 /* Now do generic ELF adjustments. */
28775 elf_adjust_symtab ();
28779 /* MD interface: Initialization. */
28782 set_constant_flonums (void)
28786 for (i = 0; i < NUM_FLOAT_VALS; i++)
28787 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
28791 /* Auto-select Thumb mode if it's the only available instruction set for the
28792 given architecture. */
28795 autoselect_thumb_from_cpu_variant (void)
28797 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
28798 opcode_select (16);
28807 if ( (arm_ops_hsh = hash_new ()) == NULL
28808 || (arm_cond_hsh = hash_new ()) == NULL
28809 || (arm_vcond_hsh = hash_new ()) == NULL
28810 || (arm_shift_hsh = hash_new ()) == NULL
28811 || (arm_psr_hsh = hash_new ()) == NULL
28812 || (arm_v7m_psr_hsh = hash_new ()) == NULL
28813 || (arm_reg_hsh = hash_new ()) == NULL
28814 || (arm_reloc_hsh = hash_new ()) == NULL
28815 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
28816 as_fatal (_("virtual memory exhausted"));
28818 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
28819 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
28820 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
28821 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
28822 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
28823 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
28824 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
28825 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
28826 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
28827 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
28828 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
28829 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
28830 (void *) (v7m_psrs + i));
28831 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
28832 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
28834 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
28836 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
28837 (void *) (barrier_opt_names + i));
28839 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
28841 struct reloc_entry * entry = reloc_names + i;
28843 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
28844 /* This makes encode_branch() use the EABI versions of this relocation. */
28845 entry->reloc = BFD_RELOC_UNUSED;
28847 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
28851 set_constant_flonums ();
28853 /* Set the cpu variant based on the command-line options. We prefer
28854 -mcpu= over -march= if both are set (as for GCC); and we prefer
28855 -mfpu= over any other way of setting the floating point unit.
28856 Use of legacy options with new options are faulted. */
28859 if (mcpu_cpu_opt || march_cpu_opt)
28860 as_bad (_("use of old and new-style options to set CPU type"));
28862 selected_arch = *legacy_cpu;
28864 else if (mcpu_cpu_opt)
28866 selected_arch = *mcpu_cpu_opt;
28867 selected_ext = *mcpu_ext_opt;
28869 else if (march_cpu_opt)
28871 selected_arch = *march_cpu_opt;
28872 selected_ext = *march_ext_opt;
28874 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
28879 as_bad (_("use of old and new-style options to set FPU type"));
28881 selected_fpu = *legacy_fpu;
28884 selected_fpu = *mfpu_opt;
28887 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28888 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28889 /* Some environments specify a default FPU. If they don't, infer it
28890 from the processor. */
28892 selected_fpu = *mcpu_fpu_opt;
28893 else if (march_fpu_opt)
28894 selected_fpu = *march_fpu_opt;
28896 selected_fpu = fpu_default;
28900 if (ARM_FEATURE_ZERO (selected_fpu))
28902 if (!no_cpu_selected ())
28903 selected_fpu = fpu_default;
28905 selected_fpu = fpu_arch_fpa;
28909 if (ARM_FEATURE_ZERO (selected_arch))
28911 selected_arch = cpu_default;
28912 selected_cpu = selected_arch;
28914 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
28916 /* Autodection of feature mode: allow all features in cpu_variant but leave
28917 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28918 after all instruction have been processed and we can decide what CPU
28919 should be selected. */
28920 if (ARM_FEATURE_ZERO (selected_arch))
28921 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
28923 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
28926 autoselect_thumb_from_cpu_variant ();
28928 arm_arch_used = thumb_arch_used = arm_arch_none;
28930 #if defined OBJ_COFF || defined OBJ_ELF
28932 unsigned int flags = 0;
28934 #if defined OBJ_ELF
28935 flags = meabi_flags;
28937 switch (meabi_flags)
28939 case EF_ARM_EABI_UNKNOWN:
28941 /* Set the flags in the private structure. */
28942 if (uses_apcs_26) flags |= F_APCS26;
28943 if (support_interwork) flags |= F_INTERWORK;
28944 if (uses_apcs_float) flags |= F_APCS_FLOAT;
28945 if (pic_code) flags |= F_PIC;
28946 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
28947 flags |= F_SOFT_FLOAT;
28949 switch (mfloat_abi_opt)
28951 case ARM_FLOAT_ABI_SOFT:
28952 case ARM_FLOAT_ABI_SOFTFP:
28953 flags |= F_SOFT_FLOAT;
28956 case ARM_FLOAT_ABI_HARD:
28957 if (flags & F_SOFT_FLOAT)
28958 as_bad (_("hard-float conflicts with specified fpu"));
28962 /* Using pure-endian doubles (even if soft-float). */
28963 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
28964 flags |= F_VFP_FLOAT;
28966 #if defined OBJ_ELF
28967 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
28968 flags |= EF_ARM_MAVERICK_FLOAT;
28971 case EF_ARM_EABI_VER4:
28972 case EF_ARM_EABI_VER5:
28973 /* No additional flags to set. */
28980 bfd_set_private_flags (stdoutput, flags);
28982 /* We have run out flags in the COFF header to encode the
28983 status of ATPCS support, so instead we create a dummy,
28984 empty, debug section called .arm.atpcs. */
28989 sec = bfd_make_section (stdoutput, ".arm.atpcs");
28993 bfd_set_section_flags
28994 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
28995 bfd_set_section_size (stdoutput, sec, 0);
28996 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
29002 /* Record the CPU type as well. */
29003 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
29004 mach = bfd_mach_arm_iWMMXt2;
29005 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
29006 mach = bfd_mach_arm_iWMMXt;
29007 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
29008 mach = bfd_mach_arm_XScale;
29009 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
29010 mach = bfd_mach_arm_ep9312;
29011 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
29012 mach = bfd_mach_arm_5TE;
29013 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
29015 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
29016 mach = bfd_mach_arm_5T;
29018 mach = bfd_mach_arm_5;
29020 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
29022 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
29023 mach = bfd_mach_arm_4T;
29025 mach = bfd_mach_arm_4;
29027 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
29028 mach = bfd_mach_arm_3M;
29029 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
29030 mach = bfd_mach_arm_3;
29031 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
29032 mach = bfd_mach_arm_2a;
29033 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
29034 mach = bfd_mach_arm_2;
29036 mach = bfd_mach_arm_unknown;
29038 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
29041 /* Command line processing. */
29044 Invocation line includes a switch not recognized by the base assembler.
29045 See if it's a processor-specific option.
29047 This routine is somewhat complicated by the need for backwards
29048 compatibility (since older releases of gcc can't be changed).
29049 The new options try to make the interface as compatible as
29052 New options (supported) are:
29054 -mcpu=<cpu name> Assemble for selected processor
29055 -march=<architecture name> Assemble for selected architecture
29056 -mfpu=<fpu architecture> Assemble for selected FPU.
29057 -EB/-mbig-endian Big-endian
29058 -EL/-mlittle-endian Little-endian
29059 -k Generate PIC code
29060 -mthumb Start in Thumb mode
29061 -mthumb-interwork Code supports ARM/Thumb interworking
29063 -m[no-]warn-deprecated Warn about deprecated features
29064 -m[no-]warn-syms Warn when symbols match instructions
29066 For now we will also provide support for:
29068 -mapcs-32 32-bit Program counter
29069 -mapcs-26 26-bit Program counter
29070 -macps-float Floats passed in FP registers
29071 -mapcs-reentrant Reentrant code
29073 (sometime these will probably be replaced with -mapcs=<list of options>
29074 and -matpcs=<list of options>)
29076 The remaining options are only supported for back-wards compatibility.
29077 Cpu variants, the arm part is optional:
29078 -m[arm]1 Currently not supported.
29079 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29080 -m[arm]3 Arm 3 processor
29081 -m[arm]6[xx], Arm 6 processors
29082 -m[arm]7[xx][t][[d]m] Arm 7 processors
29083 -m[arm]8[10] Arm 8 processors
29084 -m[arm]9[20][tdmi] Arm 9 processors
29085 -mstrongarm[110[0]] StrongARM processors
29086 -mxscale XScale processors
29087 -m[arm]v[2345[t[e]]] Arm architectures
29088 -mall All (except the ARM1)
29090 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29091 -mfpe-old (No float load/store multiples)
29092 -mvfpxd VFP Single precision
29094 -mno-fpu Disable all floating point instructions
29096 The following CPU names are recognized:
29097 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29098 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29099 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29100 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29101 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29102 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29103 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29107 const char * md_shortopts = "m:k";
29109 #ifdef ARM_BI_ENDIAN
29110 #define OPTION_EB (OPTION_MD_BASE + 0)
29111 #define OPTION_EL (OPTION_MD_BASE + 1)
29113 #if TARGET_BYTES_BIG_ENDIAN
29114 #define OPTION_EB (OPTION_MD_BASE + 0)
29116 #define OPTION_EL (OPTION_MD_BASE + 1)
29119 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29120 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29122 struct option md_longopts[] =
29125 {"EB", no_argument, NULL, OPTION_EB},
29128 {"EL", no_argument, NULL, OPTION_EL},
29130 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
29132 {"fdpic", no_argument, NULL, OPTION_FDPIC},
29134 {NULL, no_argument, NULL, 0}
29137 size_t md_longopts_size = sizeof (md_longopts);
29139 struct arm_option_table
29141 const char * option; /* Option name to match. */
29142 const char * help; /* Help information. */
29143 int * var; /* Variable to change. */
29144 int value; /* What to change it to. */
29145 const char * deprecated; /* If non-null, print this message. */
29148 struct arm_option_table arm_opts[] =
29150 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
29151 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
29152 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29153 &support_interwork, 1, NULL},
29154 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
29155 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
29156 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
29158 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
29159 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
29160 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
29161 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
29164 /* These are recognized by the assembler, but have no affect on code. */
29165 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
29166 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
29168 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
29169 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29170 &warn_on_deprecated, 0, NULL},
29171 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
29172 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
29173 {NULL, NULL, NULL, 0, NULL}
29176 struct arm_legacy_option_table
29178 const char * option; /* Option name to match. */
29179 const arm_feature_set ** var; /* Variable to change. */
29180 const arm_feature_set value; /* What to change it to. */
29181 const char * deprecated; /* If non-null, print this message. */
29184 const struct arm_legacy_option_table arm_legacy_opts[] =
29186 /* DON'T add any new processors to this list -- we want the whole list
29187 to go away... Add them to the processors table instead. */
29188 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29189 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29190 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29191 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29192 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29193 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29194 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29195 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29196 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29197 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29198 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29199 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29200 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29201 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29202 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29203 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29204 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29205 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29206 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29207 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29208 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29209 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29210 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29211 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29212 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29213 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29214 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29215 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29216 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29217 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29218 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29219 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29220 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29221 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29222 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29223 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29224 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29225 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29226 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29227 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29228 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29229 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29230 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29231 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29232 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29233 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29234 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29235 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29236 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29237 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29238 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29239 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29240 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29241 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29242 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29243 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29244 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29245 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29246 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29247 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29248 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29249 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29250 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29251 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29252 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29253 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29254 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29255 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29256 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
29257 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
29258 N_("use -mcpu=strongarm110")},
29259 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
29260 N_("use -mcpu=strongarm1100")},
29261 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
29262 N_("use -mcpu=strongarm1110")},
29263 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
29264 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
29265 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
29267 /* Architecture variants -- don't add any more to this list either. */
29268 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29269 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29270 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29271 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29272 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29273 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29274 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29275 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29276 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29277 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29278 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29279 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29280 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29281 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29282 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29283 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29284 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29285 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29287 /* Floating point variants -- don't add any more to this list either. */
29288 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
29289 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
29290 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
29291 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
29292 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29294 {NULL, NULL, ARM_ARCH_NONE, NULL}
29297 struct arm_cpu_option_table
29301 const arm_feature_set value;
29302 const arm_feature_set ext;
29303 /* For some CPUs we assume an FPU unless the user explicitly sets
29305 const arm_feature_set default_fpu;
29306 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29308 const char * canonical_name;
29311 /* This list should, at a minimum, contain all the cpu names
29312 recognized by GCC. */
29313 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29315 static const struct arm_cpu_option_table arm_cpus[] =
29317 ARM_CPU_OPT ("all", NULL, ARM_ANY,
29320 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
29323 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
29326 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
29329 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
29332 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
29335 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
29338 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
29341 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
29344 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
29347 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
29350 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
29353 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
29356 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
29359 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
29362 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
29365 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
29368 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
29371 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
29374 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
29377 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
29380 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
29383 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
29386 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
29389 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
29392 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
29395 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
29398 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
29401 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
29404 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
29407 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
29410 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
29413 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
29416 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
29419 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
29422 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
29425 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
29428 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
29431 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
29434 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
29437 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
29440 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
29443 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
29446 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
29449 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
29452 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
29456 /* For V5 or later processors we default to using VFP; but the user
29457 should really set the FPU type explicitly. */
29458 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
29461 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
29464 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
29467 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
29470 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
29473 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
29476 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
29479 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
29482 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
29485 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
29488 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
29491 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
29494 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
29497 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
29500 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
29503 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
29506 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
29509 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
29512 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
29515 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
29518 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
29521 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
29524 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
29527 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
29530 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
29533 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
29536 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
29539 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
29542 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
29545 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
29548 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
29551 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
29554 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
29557 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
29560 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
29563 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
29566 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
29567 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29569 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
29571 FPU_ARCH_NEON_VFP_V4),
29572 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
29573 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
29574 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
29575 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
29576 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29577 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
29578 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
29580 FPU_ARCH_NEON_VFP_V4),
29581 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
29583 FPU_ARCH_NEON_VFP_V4),
29584 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
29586 FPU_ARCH_NEON_VFP_V4),
29587 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
29588 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29590 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
29591 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29593 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
29594 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29596 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
29597 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29598 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29599 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
29600 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29601 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29602 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
29603 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29604 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29605 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
29606 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29607 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29608 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
29609 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29610 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29611 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
29612 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29613 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29614 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
29615 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29616 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29617 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
29620 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
29622 FPU_ARCH_VFP_V3D16),
29623 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
29624 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29626 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
29627 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29628 FPU_ARCH_VFP_V3D16),
29629 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
29630 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29631 FPU_ARCH_VFP_V3D16),
29632 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
29633 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29634 FPU_ARCH_NEON_VFP_ARMV8),
29635 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
29636 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29638 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
29641 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
29644 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
29647 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
29650 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
29653 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
29656 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
29659 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
29660 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29661 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29662 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
29663 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29664 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29665 /* ??? XSCALE is really an architecture. */
29666 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
29670 /* ??? iwmmxt is not a processor. */
29671 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
29674 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
29677 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
29682 ARM_CPU_OPT ("ep9312", "ARM920T",
29683 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
29684 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
29686 /* Marvell processors. */
29687 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
29688 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29689 FPU_ARCH_VFP_V3D16),
29690 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
29691 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29692 FPU_ARCH_NEON_VFP_V4),
29694 /* APM X-Gene family. */
29695 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
29697 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29698 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
29699 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29700 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29702 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
29706 struct arm_ext_table
29710 const arm_feature_set merge;
29711 const arm_feature_set clear;
29714 struct arm_arch_option_table
29718 const arm_feature_set value;
29719 const arm_feature_set default_fpu;
29720 const struct arm_ext_table * ext_table;
29723 /* Used to add support for +E and +noE extension. */
29724 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29725 /* Used to add support for a +E extension. */
29726 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29727 /* Used to add support for a +noE extension. */
29728 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29730 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29731 ~0 & ~FPU_ENDIAN_PURE)
29733 static const struct arm_ext_table armv5te_ext_table[] =
29735 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
29736 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29739 static const struct arm_ext_table armv7_ext_table[] =
29741 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29742 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29745 static const struct arm_ext_table armv7ve_ext_table[] =
29747 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
29748 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
29749 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
29750 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29751 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
29752 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
29753 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
29755 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
29756 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
29758 /* Aliases for +simd. */
29759 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
29761 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29762 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29763 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
29765 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29768 static const struct arm_ext_table armv7a_ext_table[] =
29770 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29771 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
29772 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
29773 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29774 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
29775 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
29776 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
29778 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
29779 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
29781 /* Aliases for +simd. */
29782 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29783 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29785 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
29786 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
29788 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
29789 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
29790 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29793 static const struct arm_ext_table armv7r_ext_table[] =
29795 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
29796 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
29797 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29798 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
29799 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
29800 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29801 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
29802 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
29803 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29806 static const struct arm_ext_table armv7em_ext_table[] =
29808 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
29809 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29810 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
29811 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
29812 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
29813 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
29814 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29817 static const struct arm_ext_table armv8a_ext_table[] =
29819 ARM_ADD ("crc", ARCH_CRC_ARMV8),
29820 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
29821 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
29822 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29824 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29825 should use the +simd option to turn on FP. */
29826 ARM_REMOVE ("fp", ALL_FP),
29827 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29828 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29829 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29833 static const struct arm_ext_table armv81a_ext_table[] =
29835 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
29836 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
29837 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29839 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29840 should use the +simd option to turn on FP. */
29841 ARM_REMOVE ("fp", ALL_FP),
29842 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29843 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29844 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29847 static const struct arm_ext_table armv82a_ext_table[] =
29849 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
29850 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
29851 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
29852 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
29853 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29854 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29856 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29857 should use the +simd option to turn on FP. */
29858 ARM_REMOVE ("fp", ALL_FP),
29859 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29860 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29861 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29864 static const struct arm_ext_table armv84a_ext_table[] =
29866 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29867 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
29868 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
29869 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29871 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29872 should use the +simd option to turn on FP. */
29873 ARM_REMOVE ("fp", ALL_FP),
29874 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29875 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29876 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29879 static const struct arm_ext_table armv85a_ext_table[] =
29881 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29882 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
29883 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
29884 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29886 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29887 should use the +simd option to turn on FP. */
29888 ARM_REMOVE ("fp", ALL_FP),
29889 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29892 static const struct arm_ext_table armv8m_main_ext_table[] =
29894 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29895 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
29896 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
29897 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
29898 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29901 static const struct arm_ext_table armv8_1m_main_ext_table[] =
29903 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29904 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
29906 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29907 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
29910 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29911 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
29912 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
29913 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
29915 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29916 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
29917 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
29918 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29921 static const struct arm_ext_table armv8r_ext_table[] =
29923 ARM_ADD ("crc", ARCH_CRC_ARMV8),
29924 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
29925 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
29926 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29927 ARM_REMOVE ("fp", ALL_FP),
29928 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
29929 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29932 /* This list should, at a minimum, contain all the architecture names
29933 recognized by GCC. */
29934 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29935 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29936 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29938 static const struct arm_arch_option_table arm_archs[] =
29940 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
29941 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
29942 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
29943 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
29944 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
29945 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
29946 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
29947 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
29948 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
29949 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
29950 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
29951 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
29952 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
29953 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
29954 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
29955 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
29956 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
29957 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
29958 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
29959 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
29960 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
29961 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29962 kept to preserve existing behaviour. */
29963 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
29964 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
29965 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
29966 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
29967 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
29968 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29969 kept to preserve existing behaviour. */
29970 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
29971 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
29972 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
29973 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
29974 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
29975 /* The official spelling of the ARMv7 profile variants is the dashed form.
29976 Accept the non-dashed form for compatibility with old toolchains. */
29977 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
29978 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
29979 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
29980 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
29981 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
29982 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
29983 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
29984 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
29985 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
29986 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
29988 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
29990 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
29991 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
29992 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
29993 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
29994 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
29995 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
29996 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
29997 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
29998 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
29999 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
30000 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
30002 #undef ARM_ARCH_OPT
30004 /* ISA extensions in the co-processor and main instruction set space. */
30006 struct arm_option_extension_value_table
30010 const arm_feature_set merge_value;
30011 const arm_feature_set clear_value;
30012 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30013 indicates that an extension is available for all architectures while
30014 ARM_ANY marks an empty entry. */
30015 const arm_feature_set allowed_archs[2];
30018 /* The following table must be in alphabetical order with a NULL last entry. */
30020 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30021 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30023 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30024 use the context sensitive approach using arm_ext_table's. */
30025 static const struct arm_option_extension_value_table arm_extensions[] =
30027 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30028 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30029 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30030 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
30031 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30032 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
30033 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
30035 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30036 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30037 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
30038 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
30039 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30040 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30041 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30043 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30044 | ARM_EXT2_FP16_FML),
30045 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30046 | ARM_EXT2_FP16_FML),
30048 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30049 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30050 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30051 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
30052 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30053 Thumb divide instruction. Due to this having the same name as the
30054 previous entry, this will be ignored when doing command-line parsing and
30055 only considered by build attribute selection code. */
30056 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30057 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30058 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
30059 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
30060 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
30061 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
30062 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
30063 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
30064 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
30065 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
30066 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
30067 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30068 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
30069 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30070 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30071 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
30072 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
30073 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
30074 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30075 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30076 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30078 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
30079 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
30080 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30081 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
30082 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
30083 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30084 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30085 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30087 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30088 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30089 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
30090 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30091 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
30092 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
30093 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30094 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
30096 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
30097 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30098 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
30099 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
30100 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
30104 /* ISA floating-point and Advanced SIMD extensions. */
30105 struct arm_option_fpu_value_table
30108 const arm_feature_set value;
30111 /* This list should, at a minimum, contain all the fpu names
30112 recognized by GCC. */
30113 static const struct arm_option_fpu_value_table arm_fpus[] =
30115 {"softfpa", FPU_NONE},
30116 {"fpe", FPU_ARCH_FPE},
30117 {"fpe2", FPU_ARCH_FPE},
30118 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
30119 {"fpa", FPU_ARCH_FPA},
30120 {"fpa10", FPU_ARCH_FPA},
30121 {"fpa11", FPU_ARCH_FPA},
30122 {"arm7500fe", FPU_ARCH_FPA},
30123 {"softvfp", FPU_ARCH_VFP},
30124 {"softvfp+vfp", FPU_ARCH_VFP_V2},
30125 {"vfp", FPU_ARCH_VFP_V2},
30126 {"vfp9", FPU_ARCH_VFP_V2},
30127 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
30128 {"vfp10", FPU_ARCH_VFP_V2},
30129 {"vfp10-r0", FPU_ARCH_VFP_V1},
30130 {"vfpxd", FPU_ARCH_VFP_V1xD},
30131 {"vfpv2", FPU_ARCH_VFP_V2},
30132 {"vfpv3", FPU_ARCH_VFP_V3},
30133 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
30134 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
30135 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
30136 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
30137 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
30138 {"arm1020t", FPU_ARCH_VFP_V1},
30139 {"arm1020e", FPU_ARCH_VFP_V2},
30140 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
30141 {"arm1136jf-s", FPU_ARCH_VFP_V2},
30142 {"maverick", FPU_ARCH_MAVERICK},
30143 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30144 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30145 {"neon-fp16", FPU_ARCH_NEON_FP16},
30146 {"vfpv4", FPU_ARCH_VFP_V4},
30147 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
30148 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
30149 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
30150 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
30151 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
30152 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
30153 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
30154 {"crypto-neon-fp-armv8",
30155 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
30156 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
30157 {"crypto-neon-fp-armv8.1",
30158 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
30159 {NULL, ARM_ARCH_NONE}
30162 struct arm_option_value_table
30168 static const struct arm_option_value_table arm_float_abis[] =
30170 {"hard", ARM_FLOAT_ABI_HARD},
30171 {"softfp", ARM_FLOAT_ABI_SOFTFP},
30172 {"soft", ARM_FLOAT_ABI_SOFT},
30177 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30178 static const struct arm_option_value_table arm_eabis[] =
30180 {"gnu", EF_ARM_EABI_UNKNOWN},
30181 {"4", EF_ARM_EABI_VER4},
30182 {"5", EF_ARM_EABI_VER5},
30187 struct arm_long_option_table
30189 const char * option; /* Substring to match. */
30190 const char * help; /* Help information. */
30191 int (* func) (const char * subopt); /* Function to decode sub-option. */
30192 const char * deprecated; /* If non-null, print this message. */
30196 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
30197 arm_feature_set *ext_set,
30198 const struct arm_ext_table *ext_table)
30200 /* We insist on extensions being specified in alphabetical order, and with
30201 extensions being added before being removed. We achieve this by having
30202 the global ARM_EXTENSIONS table in alphabetical order, and using the
30203 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30204 or removing it (0) and only allowing it to change in the order
30206 const struct arm_option_extension_value_table * opt = NULL;
30207 const arm_feature_set arm_any = ARM_ANY;
30208 int adding_value = -1;
30210 while (str != NULL && *str != 0)
30217 as_bad (_("invalid architectural extension"));
30222 ext = strchr (str, '+');
30227 len = strlen (str);
30229 if (len >= 2 && strncmp (str, "no", 2) == 0)
30231 if (adding_value != 0)
30234 opt = arm_extensions;
30242 if (adding_value == -1)
30245 opt = arm_extensions;
30247 else if (adding_value != 1)
30249 as_bad (_("must specify extensions to add before specifying "
30250 "those to remove"));
30257 as_bad (_("missing architectural extension"));
30261 gas_assert (adding_value != -1);
30262 gas_assert (opt != NULL);
30264 if (ext_table != NULL)
30266 const struct arm_ext_table * ext_opt = ext_table;
30267 bfd_boolean found = FALSE;
30268 for (; ext_opt->name != NULL; ext_opt++)
30269 if (ext_opt->name_len == len
30270 && strncmp (ext_opt->name, str, len) == 0)
30274 if (ARM_FEATURE_ZERO (ext_opt->merge))
30275 /* TODO: Option not supported. When we remove the
30276 legacy table this case should error out. */
30279 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
30283 if (ARM_FEATURE_ZERO (ext_opt->clear))
30284 /* TODO: Option not supported. When we remove the
30285 legacy table this case should error out. */
30287 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
30299 /* Scan over the options table trying to find an exact match. */
30300 for (; opt->name != NULL; opt++)
30301 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30303 int i, nb_allowed_archs =
30304 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
30305 /* Check we can apply the extension to this architecture. */
30306 for (i = 0; i < nb_allowed_archs; i++)
30309 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
30311 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
30314 if (i == nb_allowed_archs)
30316 as_bad (_("extension does not apply to the base architecture"));
30320 /* Add or remove the extension. */
30322 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
30324 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
30326 /* Allowing Thumb division instructions for ARMv7 in autodetection
30327 rely on this break so that duplicate extensions (extensions
30328 with the same name as a previous extension in the list) are not
30329 considered for command-line parsing. */
30333 if (opt->name == NULL)
30335 /* Did we fail to find an extension because it wasn't specified in
30336 alphabetical order, or because it does not exist? */
30338 for (opt = arm_extensions; opt->name != NULL; opt++)
30339 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30342 if (opt->name == NULL)
30343 as_bad (_("unknown architectural extension `%s'"), str);
30345 as_bad (_("architectural extensions must be specified in "
30346 "alphabetical order"));
30352 /* We should skip the extension we've just matched the next time
30364 arm_parse_cpu (const char *str)
30366 const struct arm_cpu_option_table *opt;
30367 const char *ext = strchr (str, '+');
30373 len = strlen (str);
30377 as_bad (_("missing cpu name `%s'"), str);
30381 for (opt = arm_cpus; opt->name != NULL; opt++)
30382 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30384 mcpu_cpu_opt = &opt->value;
30385 if (mcpu_ext_opt == NULL)
30386 mcpu_ext_opt = XNEW (arm_feature_set);
30387 *mcpu_ext_opt = opt->ext;
30388 mcpu_fpu_opt = &opt->default_fpu;
30389 if (opt->canonical_name)
30391 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
30392 strcpy (selected_cpu_name, opt->canonical_name);
30398 if (len >= sizeof selected_cpu_name)
30399 len = (sizeof selected_cpu_name) - 1;
30401 for (i = 0; i < len; i++)
30402 selected_cpu_name[i] = TOUPPER (opt->name[i]);
30403 selected_cpu_name[i] = 0;
30407 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
30412 as_bad (_("unknown cpu `%s'"), str);
30417 arm_parse_arch (const char *str)
30419 const struct arm_arch_option_table *opt;
30420 const char *ext = strchr (str, '+');
30426 len = strlen (str);
30430 as_bad (_("missing architecture name `%s'"), str);
30434 for (opt = arm_archs; opt->name != NULL; opt++)
30435 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30437 march_cpu_opt = &opt->value;
30438 if (march_ext_opt == NULL)
30439 march_ext_opt = XNEW (arm_feature_set);
30440 *march_ext_opt = arm_arch_none;
30441 march_fpu_opt = &opt->default_fpu;
30442 strcpy (selected_cpu_name, opt->name);
30445 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
30451 as_bad (_("unknown architecture `%s'\n"), str);
30456 arm_parse_fpu (const char * str)
30458 const struct arm_option_fpu_value_table * opt;
30460 for (opt = arm_fpus; opt->name != NULL; opt++)
30461 if (streq (opt->name, str))
30463 mfpu_opt = &opt->value;
30467 as_bad (_("unknown floating point format `%s'\n"), str);
30472 arm_parse_float_abi (const char * str)
30474 const struct arm_option_value_table * opt;
30476 for (opt = arm_float_abis; opt->name != NULL; opt++)
30477 if (streq (opt->name, str))
30479 mfloat_abi_opt = opt->value;
30483 as_bad (_("unknown floating point abi `%s'\n"), str);
30489 arm_parse_eabi (const char * str)
30491 const struct arm_option_value_table *opt;
30493 for (opt = arm_eabis; opt->name != NULL; opt++)
30494 if (streq (opt->name, str))
30496 meabi_flags = opt->value;
30499 as_bad (_("unknown EABI `%s'\n"), str);
30505 arm_parse_it_mode (const char * str)
30507 bfd_boolean ret = TRUE;
30509 if (streq ("arm", str))
30510 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
30511 else if (streq ("thumb", str))
30512 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
30513 else if (streq ("always", str))
30514 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
30515 else if (streq ("never", str))
30516 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
30519 as_bad (_("unknown implicit IT mode `%s', should be "\
30520 "arm, thumb, always, or never."), str);
30528 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
30530 codecomposer_syntax = TRUE;
30531 arm_comment_chars[0] = ';';
30532 arm_line_separator_chars[0] = 0;
30536 struct arm_long_option_table arm_long_opts[] =
30538 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30539 arm_parse_cpu, NULL},
30540 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30541 arm_parse_arch, NULL},
30542 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30543 arm_parse_fpu, NULL},
30544 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30545 arm_parse_float_abi, NULL},
30547 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30548 arm_parse_eabi, NULL},
30550 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30551 arm_parse_it_mode, NULL},
30552 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30553 arm_ccs_mode, NULL},
30554 {NULL, NULL, 0, NULL}
30558 md_parse_option (int c, const char * arg)
30560 struct arm_option_table *opt;
30561 const struct arm_legacy_option_table *fopt;
30562 struct arm_long_option_table *lopt;
30568 target_big_endian = 1;
30574 target_big_endian = 0;
30578 case OPTION_FIX_V4BX:
30586 #endif /* OBJ_ELF */
30589 /* Listing option. Just ignore these, we don't support additional
30594 for (opt = arm_opts; opt->option != NULL; opt++)
30596 if (c == opt->option[0]
30597 && ((arg == NULL && opt->option[1] == 0)
30598 || streq (arg, opt->option + 1)))
30600 /* If the option is deprecated, tell the user. */
30601 if (warn_on_deprecated && opt->deprecated != NULL)
30602 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
30603 arg ? arg : "", _(opt->deprecated));
30605 if (opt->var != NULL)
30606 *opt->var = opt->value;
30612 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
30614 if (c == fopt->option[0]
30615 && ((arg == NULL && fopt->option[1] == 0)
30616 || streq (arg, fopt->option + 1)))
30618 /* If the option is deprecated, tell the user. */
30619 if (warn_on_deprecated && fopt->deprecated != NULL)
30620 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
30621 arg ? arg : "", _(fopt->deprecated));
30623 if (fopt->var != NULL)
30624 *fopt->var = &fopt->value;
30630 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
30632 /* These options are expected to have an argument. */
30633 if (c == lopt->option[0]
30635 && strncmp (arg, lopt->option + 1,
30636 strlen (lopt->option + 1)) == 0)
30638 /* If the option is deprecated, tell the user. */
30639 if (warn_on_deprecated && lopt->deprecated != NULL)
30640 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
30641 _(lopt->deprecated));
30643 /* Call the sup-option parser. */
30644 return lopt->func (arg + strlen (lopt->option) - 1);
30655 md_show_usage (FILE * fp)
30657 struct arm_option_table *opt;
30658 struct arm_long_option_table *lopt;
30660 fprintf (fp, _(" ARM-specific assembler options:\n"));
30662 for (opt = arm_opts; opt->option != NULL; opt++)
30663 if (opt->help != NULL)
30664 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
30666 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
30667 if (lopt->help != NULL)
30668 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
30672 -EB assemble code for a big-endian cpu\n"));
30677 -EL assemble code for a little-endian cpu\n"));
30681 --fix-v4bx Allow BX in ARMv4 code\n"));
30685 --fdpic generate an FDPIC object file\n"));
30686 #endif /* OBJ_ELF */
30694 arm_feature_set flags;
30695 } cpu_arch_ver_table;
30697 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30698 chronologically for architectures, with an exception for ARMv6-M and
30699 ARMv6S-M due to legacy reasons. No new architecture should have a
30700 special case. This allows for build attribute selection results to be
30701 stable when new architectures are added. */
30702 static const cpu_arch_ver_table cpu_arch_ver[] =
30704 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
30705 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
30706 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
30707 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
30708 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
30709 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
30710 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
30711 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
30712 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
30713 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
30714 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
30715 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
30716 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
30717 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
30718 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
30719 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
30720 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
30721 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
30722 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
30723 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
30724 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
30725 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
30726 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
30727 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
30729 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30730 always selected build attributes to match those of ARMv6-M
30731 (resp. ARMv6S-M). However, due to these architectures being a strict
30732 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30733 would be selected when fully respecting chronology of architectures.
30734 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30735 move them before ARMv7 architectures. */
30736 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
30737 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
30739 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
30740 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
30741 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
30742 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
30743 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
30744 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
30745 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
30746 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
30747 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
30748 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
30749 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
30750 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
30751 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
30752 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
30753 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
30754 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
30755 {-1, ARM_ARCH_NONE}
30758 /* Set an attribute if it has not already been set by the user. */
30761 aeabi_set_attribute_int (int tag, int value)
30764 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
30765 || !attributes_set_explicitly[tag])
30766 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
30770 aeabi_set_attribute_string (int tag, const char *value)
30773 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
30774 || !attributes_set_explicitly[tag])
30775 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
30778 /* Return whether features in the *NEEDED feature set are available via
30779 extensions for the architecture whose feature set is *ARCH_FSET. */
30782 have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
30783 const arm_feature_set *needed)
30785 int i, nb_allowed_archs;
30786 arm_feature_set ext_fset;
30787 const struct arm_option_extension_value_table *opt;
30789 ext_fset = arm_arch_none;
30790 for (opt = arm_extensions; opt->name != NULL; opt++)
30792 /* Extension does not provide any feature we need. */
30793 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
30797 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
30798 for (i = 0; i < nb_allowed_archs; i++)
30801 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
30804 /* Extension is available, add it. */
30805 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
30806 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
30810 /* Can we enable all features in *needed? */
30811 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
30814 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30815 a given architecture feature set *ARCH_EXT_FSET including extension feature
30816 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30817 - if true, check for an exact match of the architecture modulo extensions;
30818 - otherwise, select build attribute value of the first superset
30819 architecture released so that results remains stable when new architectures
30821 For -march/-mcpu=all the build attribute value of the most featureful
30822 architecture is returned. Tag_CPU_arch_profile result is returned in
30826 get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
30827 const arm_feature_set *ext_fset,
30828 char *profile, int exact_match)
30830 arm_feature_set arch_fset;
30831 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
30833 /* Select most featureful architecture with all its extensions if building
30834 for -march=all as the feature sets used to set build attributes. */
30835 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
30837 /* Force revisiting of decision for each new architecture. */
30838 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
30840 return TAG_CPU_ARCH_V8;
30843 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
30845 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
30847 arm_feature_set known_arch_fset;
30849 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
30852 /* Base architecture match user-specified architecture and
30853 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30854 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
30859 /* Base architecture match user-specified architecture only
30860 (eg. ARMv6-M in the same case as above). Record it in case we
30861 find a match with above condition. */
30862 else if (p_ver_ret == NULL
30863 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
30869 /* Architecture has all features wanted. */
30870 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
30872 arm_feature_set added_fset;
30874 /* Compute features added by this architecture over the one
30875 recorded in p_ver_ret. */
30876 if (p_ver_ret != NULL)
30877 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
30879 /* First architecture that match incl. with extensions, or the
30880 only difference in features over the recorded match is
30881 features that were optional and are now mandatory. */
30882 if (p_ver_ret == NULL
30883 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
30889 else if (p_ver_ret == NULL)
30891 arm_feature_set needed_ext_fset;
30893 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
30895 /* Architecture has all features needed when using some
30896 extensions. Record it and continue searching in case there
30897 exist an architecture providing all needed features without
30898 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30900 if (have_ext_for_needed_feat_p (&known_arch_fset,
30907 if (p_ver_ret == NULL)
30911 /* Tag_CPU_arch_profile. */
30912 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
30913 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
30914 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
30915 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
30917 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
30919 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
30923 return p_ver_ret->val;
30926 /* Set the public EABI object attributes. */
30929 aeabi_set_public_attributes (void)
30931 char profile = '\0';
30934 int fp16_optional = 0;
30935 int skip_exact_match = 0;
30936 arm_feature_set flags, flags_arch, flags_ext;
30938 /* Autodetection mode, choose the architecture based the instructions
30940 if (no_cpu_selected ())
30942 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
30944 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
30945 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
30947 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
30948 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
30950 /* Code run during relaxation relies on selected_cpu being set. */
30951 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
30952 flags_ext = arm_arch_none;
30953 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
30954 selected_ext = flags_ext;
30955 selected_cpu = flags;
30957 /* Otherwise, choose the architecture based on the capabilities of the
30961 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
30962 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
30963 flags_ext = selected_ext;
30964 flags = selected_cpu;
30966 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
30968 /* Allow the user to override the reported architecture. */
30969 if (!ARM_FEATURE_ZERO (selected_object_arch))
30971 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
30972 flags_ext = arm_arch_none;
30975 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
30977 /* When this function is run again after relaxation has happened there is no
30978 way to determine whether an architecture or CPU was specified by the user:
30979 - selected_cpu is set above for relaxation to work;
30980 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30981 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30982 Therefore, if not in -march=all case we first try an exact match and fall
30983 back to autodetection. */
30984 if (!skip_exact_match)
30985 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
30987 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
30989 as_bad (_("no architecture contains all the instructions used\n"));
30991 /* Tag_CPU_name. */
30992 if (selected_cpu_name[0])
30996 q = selected_cpu_name;
30997 if (strncmp (q, "armv", 4) == 0)
31002 for (i = 0; q[i]; i++)
31003 q[i] = TOUPPER (q[i]);
31005 aeabi_set_attribute_string (Tag_CPU_name, q);
31008 /* Tag_CPU_arch. */
31009 aeabi_set_attribute_int (Tag_CPU_arch, arch);
31011 /* Tag_CPU_arch_profile. */
31012 if (profile != '\0')
31013 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
31015 /* Tag_DSP_extension. */
31016 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
31017 aeabi_set_attribute_int (Tag_DSP_extension, 1);
31019 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
31020 /* Tag_ARM_ISA_use. */
31021 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
31022 || ARM_FEATURE_ZERO (flags_arch))
31023 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
31025 /* Tag_THUMB_ISA_use. */
31026 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
31027 || ARM_FEATURE_ZERO (flags_arch))
31031 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31032 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
31034 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
31038 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
31041 /* Tag_VFP_arch. */
31042 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
31043 aeabi_set_attribute_int (Tag_VFP_arch,
31044 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31046 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
31047 aeabi_set_attribute_int (Tag_VFP_arch,
31048 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31050 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
31053 aeabi_set_attribute_int (Tag_VFP_arch, 3);
31055 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
31057 aeabi_set_attribute_int (Tag_VFP_arch, 4);
31060 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
31061 aeabi_set_attribute_int (Tag_VFP_arch, 2);
31062 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
31063 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
31064 aeabi_set_attribute_int (Tag_VFP_arch, 1);
31066 /* Tag_ABI_HardFP_use. */
31067 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
31068 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
31069 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
31071 /* Tag_WMMX_arch. */
31072 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
31073 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
31074 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
31075 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
31077 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31078 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
31079 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
31080 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
31081 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
31082 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
31084 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
31086 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
31090 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
31095 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
31096 aeabi_set_attribute_int (Tag_MVE_arch, 2);
31097 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
31098 aeabi_set_attribute_int (Tag_MVE_arch, 1);
31100 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31101 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
31102 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
31106 We set Tag_DIV_use to two when integer divide instructions have been used
31107 in ARM state, or when Thumb integer divide instructions have been used,
31108 but we have no architecture profile set, nor have we any ARM instructions.
31110 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31111 by the base architecture.
31113 For new architectures we will have to check these tests. */
31114 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
31115 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31116 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
31117 aeabi_set_attribute_int (Tag_DIV_use, 0);
31118 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
31119 || (profile == '\0'
31120 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
31121 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
31122 aeabi_set_attribute_int (Tag_DIV_use, 2);
31124 /* Tag_MP_extension_use. */
31125 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
31126 aeabi_set_attribute_int (Tag_MPextension_use, 1);
31128 /* Tag Virtualization_use. */
31129 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
31131 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
31134 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
31137 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31138 finished and free extension feature bits which will not be used anymore. */
31141 arm_md_post_relax (void)
31143 aeabi_set_public_attributes ();
31144 XDELETE (mcpu_ext_opt);
31145 mcpu_ext_opt = NULL;
31146 XDELETE (march_ext_opt);
31147 march_ext_opt = NULL;
31150 /* Add the default contents for the .ARM.attributes section. */
31155 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
31158 aeabi_set_public_attributes ();
31160 #endif /* OBJ_ELF */
31162 /* Parse a .cpu directive. */
31165 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
31167 const struct arm_cpu_option_table *opt;
31171 name = input_line_pointer;
31172 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31173 input_line_pointer++;
31174 saved_char = *input_line_pointer;
31175 *input_line_pointer = 0;
31177 /* Skip the first "all" entry. */
31178 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
31179 if (streq (opt->name, name))
31181 selected_arch = opt->value;
31182 selected_ext = opt->ext;
31183 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31184 if (opt->canonical_name)
31185 strcpy (selected_cpu_name, opt->canonical_name);
31189 for (i = 0; opt->name[i]; i++)
31190 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31192 selected_cpu_name[i] = 0;
31194 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31196 *input_line_pointer = saved_char;
31197 demand_empty_rest_of_line ();
31200 as_bad (_("unknown cpu `%s'"), name);
31201 *input_line_pointer = saved_char;
31202 ignore_rest_of_line ();
31205 /* Parse a .arch directive. */
31208 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
31210 const struct arm_arch_option_table *opt;
31214 name = input_line_pointer;
31215 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31216 input_line_pointer++;
31217 saved_char = *input_line_pointer;
31218 *input_line_pointer = 0;
31220 /* Skip the first "all" entry. */
31221 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31222 if (streq (opt->name, name))
31224 selected_arch = opt->value;
31225 selected_ext = arm_arch_none;
31226 selected_cpu = selected_arch;
31227 strcpy (selected_cpu_name, opt->name);
31228 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31229 *input_line_pointer = saved_char;
31230 demand_empty_rest_of_line ();
31234 as_bad (_("unknown architecture `%s'\n"), name);
31235 *input_line_pointer = saved_char;
31236 ignore_rest_of_line ();
31239 /* Parse a .object_arch directive. */
31242 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
31244 const struct arm_arch_option_table *opt;
31248 name = input_line_pointer;
31249 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31250 input_line_pointer++;
31251 saved_char = *input_line_pointer;
31252 *input_line_pointer = 0;
31254 /* Skip the first "all" entry. */
31255 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31256 if (streq (opt->name, name))
31258 selected_object_arch = opt->value;
31259 *input_line_pointer = saved_char;
31260 demand_empty_rest_of_line ();
31264 as_bad (_("unknown architecture `%s'\n"), name);
31265 *input_line_pointer = saved_char;
31266 ignore_rest_of_line ();
31269 /* Parse a .arch_extension directive. */
31272 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
31274 const struct arm_option_extension_value_table *opt;
31277 int adding_value = 1;
31279 name = input_line_pointer;
31280 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31281 input_line_pointer++;
31282 saved_char = *input_line_pointer;
31283 *input_line_pointer = 0;
31285 if (strlen (name) >= 2
31286 && strncmp (name, "no", 2) == 0)
31292 for (opt = arm_extensions; opt->name != NULL; opt++)
31293 if (streq (opt->name, name))
31295 int i, nb_allowed_archs =
31296 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
31297 for (i = 0; i < nb_allowed_archs; i++)
31300 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
31302 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
31306 if (i == nb_allowed_archs)
31308 as_bad (_("architectural extension `%s' is not allowed for the "
31309 "current base architecture"), name);
31314 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
31317 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
31319 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31320 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31321 *input_line_pointer = saved_char;
31322 demand_empty_rest_of_line ();
31323 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31324 on this return so that duplicate extensions (extensions with the
31325 same name as a previous extension in the list) are not considered
31326 for command-line parsing. */
31330 if (opt->name == NULL)
31331 as_bad (_("unknown architecture extension `%s'\n"), name);
31333 *input_line_pointer = saved_char;
31334 ignore_rest_of_line ();
31337 /* Parse a .fpu directive. */
31340 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
31342 const struct arm_option_fpu_value_table *opt;
31346 name = input_line_pointer;
31347 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31348 input_line_pointer++;
31349 saved_char = *input_line_pointer;
31350 *input_line_pointer = 0;
31352 for (opt = arm_fpus; opt->name != NULL; opt++)
31353 if (streq (opt->name, name))
31355 selected_fpu = opt->value;
31356 #ifndef CPU_DEFAULT
31357 if (no_cpu_selected ())
31358 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
31361 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31362 *input_line_pointer = saved_char;
31363 demand_empty_rest_of_line ();
31367 as_bad (_("unknown floating point format `%s'\n"), name);
31368 *input_line_pointer = saved_char;
31369 ignore_rest_of_line ();
31372 /* Copy symbol information. */
31375 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
31377 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
31381 /* Given a symbolic attribute NAME, return the proper integer value.
31382 Returns -1 if the attribute is not known. */
31385 arm_convert_symbolic_attribute (const char *name)
31387 static const struct
31392 attribute_table[] =
31394 /* When you modify this table you should
31395 also modify the list in doc/c-arm.texi. */
31396 #define T(tag) {#tag, tag}
31397 T (Tag_CPU_raw_name),
31400 T (Tag_CPU_arch_profile),
31401 T (Tag_ARM_ISA_use),
31402 T (Tag_THUMB_ISA_use),
31406 T (Tag_Advanced_SIMD_arch),
31407 T (Tag_PCS_config),
31408 T (Tag_ABI_PCS_R9_use),
31409 T (Tag_ABI_PCS_RW_data),
31410 T (Tag_ABI_PCS_RO_data),
31411 T (Tag_ABI_PCS_GOT_use),
31412 T (Tag_ABI_PCS_wchar_t),
31413 T (Tag_ABI_FP_rounding),
31414 T (Tag_ABI_FP_denormal),
31415 T (Tag_ABI_FP_exceptions),
31416 T (Tag_ABI_FP_user_exceptions),
31417 T (Tag_ABI_FP_number_model),
31418 T (Tag_ABI_align_needed),
31419 T (Tag_ABI_align8_needed),
31420 T (Tag_ABI_align_preserved),
31421 T (Tag_ABI_align8_preserved),
31422 T (Tag_ABI_enum_size),
31423 T (Tag_ABI_HardFP_use),
31424 T (Tag_ABI_VFP_args),
31425 T (Tag_ABI_WMMX_args),
31426 T (Tag_ABI_optimization_goals),
31427 T (Tag_ABI_FP_optimization_goals),
31428 T (Tag_compatibility),
31429 T (Tag_CPU_unaligned_access),
31430 T (Tag_FP_HP_extension),
31431 T (Tag_VFP_HP_extension),
31432 T (Tag_ABI_FP_16bit_format),
31433 T (Tag_MPextension_use),
31435 T (Tag_nodefaults),
31436 T (Tag_also_compatible_with),
31437 T (Tag_conformance),
31439 T (Tag_Virtualization_use),
31440 T (Tag_DSP_extension),
31442 /* We deliberately do not include Tag_MPextension_use_legacy. */
31450 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
31451 if (streq (name, attribute_table[i].name))
31452 return attribute_table[i].tag;
31457 /* Apply sym value for relocations only in the case that they are for
31458 local symbols in the same segment as the fixup and you have the
31459 respective architectural feature for blx and simple switches. */
31462 arm_apply_sym_value (struct fix * fixP, segT this_seg)
31465 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
31466 /* PR 17444: If the local symbol is in a different section then a reloc
31467 will always be generated for it, so applying the symbol value now
31468 will result in a double offset being stored in the relocation. */
31469 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
31470 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
31472 switch (fixP->fx_r_type)
31474 case BFD_RELOC_ARM_PCREL_BLX:
31475 case BFD_RELOC_THUMB_PCREL_BRANCH23:
31476 if (ARM_IS_FUNC (fixP->fx_addsy))
31480 case BFD_RELOC_ARM_PCREL_CALL:
31481 case BFD_RELOC_THUMB_PCREL_BLX:
31482 if (THUMB_IS_FUNC (fixP->fx_addsy))
31493 #endif /* OBJ_ELF */