1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
727 #define BAD_RANGE _("branch out of range")
729 static struct hash_control * arm_ops_hsh;
730 static struct hash_control * arm_cond_hsh;
731 static struct hash_control * arm_shift_hsh;
732 static struct hash_control * arm_psr_hsh;
733 static struct hash_control * arm_v7m_psr_hsh;
734 static struct hash_control * arm_reg_hsh;
735 static struct hash_control * arm_reloc_hsh;
736 static struct hash_control * arm_barrier_opt_hsh;
738 /* Stuff needed to resolve the label ambiguity
747 symbolS * last_label_seen;
748 static int label_is_thumb_function_name = FALSE;
750 /* Literal pool structure. Held on a per-section
751 and per-sub-section basis. */
753 #define MAX_LITERAL_POOL_SIZE 1024
754 typedef struct literal_pool
756 expressionS literals [MAX_LITERAL_POOL_SIZE];
757 unsigned int next_free_entry;
763 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
765 struct literal_pool * next;
768 /* Pointer to a linked list of literal pools. */
769 literal_pool * list_of_pools = NULL;
772 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
774 static struct current_it now_it;
778 now_it_compatible (int cond)
780 return (cond & ~1) == (now_it.cc & ~1);
784 conditional_insn (void)
786 return inst.cond != COND_ALWAYS;
789 static int in_it_block (void);
791 static int handle_it_state (void);
793 static void force_automatic_it_block_close (void);
795 static void it_fsm_post_encode (void);
797 #define set_it_insn_type(type) \
800 inst.it_insn_type = type; \
801 if (handle_it_state () == FAIL) \
806 #define set_it_insn_type_nonvoid(type, failret) \
809 inst.it_insn_type = type; \
810 if (handle_it_state () == FAIL) \
815 #define set_it_insn_type_last() \
818 if (inst.cond == COND_ALWAYS) \
819 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
821 set_it_insn_type (INSIDE_IT_LAST_INSN); \
827 /* This array holds the chars that always start a comment. If the
828 pre-processor is disabled, these aren't very useful. */
829 const char comment_chars[] = "@";
831 /* This array holds the chars that only start a comment at the beginning of
832 a line. If the line seems to have the form '# 123 filename'
833 .line and .file directives will appear in the pre-processed output. */
834 /* Note that input_file.c hand checks for '#' at the beginning of the
835 first line of the input file. This is because the compiler outputs
836 #NO_APP at the beginning of its output. */
837 /* Also note that comments like this one will always work. */
838 const char line_comment_chars[] = "#";
840 const char line_separator_chars[] = ";";
842 /* Chars that can be used to separate mant
843 from exp in floating point numbers. */
844 const char EXP_CHARS[] = "eE";
846 /* Chars that mean this number is a floating point constant. */
850 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
852 /* Prefix characters that indicate the start of an immediate
854 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
856 /* Separator character handling. */
858 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
861 skip_past_char (char ** str, char c)
872 #define skip_past_comma(str) skip_past_char (str, ',')
874 /* Arithmetic expressions (possibly involving symbols). */
876 /* Return TRUE if anything in the expression is a bignum. */
879 walk_no_bignums (symbolS * sp)
881 if (symbol_get_value_expression (sp)->X_op == O_big)
884 if (symbol_get_value_expression (sp)->X_add_symbol)
886 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
887 || (symbol_get_value_expression (sp)->X_op_symbol
888 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
894 static int in_my_get_expression = 0;
896 /* Third argument to my_get_expression. */
897 #define GE_NO_PREFIX 0
898 #define GE_IMM_PREFIX 1
899 #define GE_OPT_PREFIX 2
900 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
901 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
902 #define GE_OPT_PREFIX_BIG 3
905 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
910 /* In unified syntax, all prefixes are optional. */
912 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
917 case GE_NO_PREFIX: break;
919 if (!is_immediate_prefix (**str))
921 inst.error = _("immediate expression requires a # prefix");
927 case GE_OPT_PREFIX_BIG:
928 if (is_immediate_prefix (**str))
934 memset (ep, 0, sizeof (expressionS));
936 save_in = input_line_pointer;
937 input_line_pointer = *str;
938 in_my_get_expression = 1;
939 seg = expression (ep);
940 in_my_get_expression = 0;
942 if (ep->X_op == O_illegal || ep->X_op == O_absent)
944 /* We found a bad or missing expression in md_operand(). */
945 *str = input_line_pointer;
946 input_line_pointer = save_in;
947 if (inst.error == NULL)
948 inst.error = (ep->X_op == O_absent
949 ? _("missing expression") :_("bad expression"));
954 if (seg != absolute_section
955 && seg != text_section
956 && seg != data_section
957 && seg != bss_section
958 && seg != undefined_section)
960 inst.error = _("bad segment");
961 *str = input_line_pointer;
962 input_line_pointer = save_in;
969 /* Get rid of any bignums now, so that we don't generate an error for which
970 we can't establish a line number later on. Big numbers are never valid
971 in instructions, which is where this routine is always called. */
972 if (prefix_mode != GE_OPT_PREFIX_BIG
973 && (ep->X_op == O_big
975 && (walk_no_bignums (ep->X_add_symbol)
977 && walk_no_bignums (ep->X_op_symbol))))))
979 inst.error = _("invalid constant");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
985 *str = input_line_pointer;
986 input_line_pointer = save_in;
990 /* Turn a string in input_line_pointer into a floating point constant
991 of type TYPE, and store the appropriate bytes in *LITP. The number
992 of LITTLENUMS emitted is stored in *SIZEP. An error message is
993 returned, or NULL on OK.
995 Note that fp constants aren't represent in the normal way on the ARM.
996 In big endian mode, things are as expected. However, in little endian
997 mode fp constants are big-endian word-wise, and little-endian byte-wise
998 within the words. For example, (double) 1.1 in big endian mode is
999 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1000 the byte sequence 99 99 f1 3f 9a 99 99 99.
1002 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1005 md_atof (int type, char * litP, int * sizeP)
1008 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1040 return _("Unrecognized or unsupported floating point constant");
1043 t = atof_ieee (input_line_pointer, type, words);
1045 input_line_pointer = t;
1046 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1048 if (target_big_endian)
1050 for (i = 0; i < prec; i++)
1052 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1053 litP += sizeof (LITTLENUM_TYPE);
1058 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1059 for (i = prec - 1; i >= 0; i--)
1061 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1062 litP += sizeof (LITTLENUM_TYPE);
1065 /* For a 4 byte float the order of elements in `words' is 1 0.
1066 For an 8 byte float the order is 1 0 3 2. */
1067 for (i = 0; i < prec; i += 2)
1069 md_number_to_chars (litP, (valueT) words[i + 1],
1070 sizeof (LITTLENUM_TYPE));
1071 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1072 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += 2 * sizeof (LITTLENUM_TYPE);
1080 /* We handle all bad expressions here, so that we can report the faulty
1081 instruction in the error message. */
1083 md_operand (expressionS * exp)
1085 if (in_my_get_expression)
1086 exp->X_op = O_illegal;
1089 /* Immediate values. */
1091 /* Generic immediate-value read function for use in directives.
1092 Accepts anything that 'expression' can fold to a constant.
1093 *val receives the number. */
1096 immediate_for_directive (int *val)
1099 exp.X_op = O_illegal;
1101 if (is_immediate_prefix (*input_line_pointer))
1103 input_line_pointer++;
1107 if (exp.X_op != O_constant)
1109 as_bad (_("expected #constant"));
1110 ignore_rest_of_line ();
1113 *val = exp.X_add_number;
1118 /* Register parsing. */
1120 /* Generic register parser. CCP points to what should be the
1121 beginning of a register name. If it is indeed a valid register
1122 name, advance CCP over it and return the reg_entry structure;
1123 otherwise return NULL. Does not issue diagnostics. */
1125 static struct reg_entry *
1126 arm_reg_parse_multi (char **ccp)
1130 struct reg_entry *reg;
1132 #ifdef REGISTER_PREFIX
1133 if (*start != REGISTER_PREFIX)
1137 #ifdef OPTIONAL_REGISTER_PREFIX
1138 if (*start == OPTIONAL_REGISTER_PREFIX)
1143 if (!ISALPHA (*p) || !is_name_beginner (*p))
1148 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1150 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1160 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1161 enum arm_reg_type type)
1163 /* Alternative syntaxes are accepted for a few register classes. */
1170 /* Generic coprocessor register names are allowed for these. */
1171 if (reg && reg->type == REG_TYPE_CN)
1176 /* For backward compatibility, a bare number is valid here. */
1178 unsigned long processor = strtoul (start, ccp, 10);
1179 if (*ccp != start && processor <= 15)
1183 case REG_TYPE_MMXWC:
1184 /* WC includes WCG. ??? I'm not sure this is true for all
1185 instructions that take WC registers. */
1186 if (reg && reg->type == REG_TYPE_MMXWCG)
1197 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1198 return value is the register number or FAIL. */
1201 arm_reg_parse (char **ccp, enum arm_reg_type type)
1204 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1207 /* Do not allow a scalar (reg+index) to parse as a register. */
1208 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1211 if (reg && reg->type == type)
1214 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1221 /* Parse a Neon type specifier. *STR should point at the leading '.'
1222 character. Does no verification at this stage that the type fits the opcode
1229 Can all be legally parsed by this function.
1231 Fills in neon_type struct pointer with parsed information, and updates STR
1232 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1233 type, FAIL if not. */
1236 parse_neon_type (struct neon_type *type, char **str)
1243 while (type->elems < NEON_MAX_TYPE_ELS)
1245 enum neon_el_type thistype = NT_untyped;
1246 unsigned thissize = -1u;
1253 /* Just a size without an explicit type. */
1257 switch (TOLOWER (*ptr))
1259 case 'i': thistype = NT_integer; break;
1260 case 'f': thistype = NT_float; break;
1261 case 'p': thistype = NT_poly; break;
1262 case 's': thistype = NT_signed; break;
1263 case 'u': thistype = NT_unsigned; break;
1265 thistype = NT_float;
1270 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1276 /* .f is an abbreviation for .f32. */
1277 if (thistype == NT_float && !ISDIGIT (*ptr))
1282 thissize = strtoul (ptr, &ptr, 10);
1284 if (thissize != 8 && thissize != 16 && thissize != 32
1287 as_bad (_("bad size %d in type specifier"), thissize);
1295 type->el[type->elems].type = thistype;
1296 type->el[type->elems].size = thissize;
1301 /* Empty/missing type is not a successful parse. */
1302 if (type->elems == 0)
1310 /* Errors may be set multiple times during parsing or bit encoding
1311 (particularly in the Neon bits), but usually the earliest error which is set
1312 will be the most meaningful. Avoid overwriting it with later (cascading)
1313 errors by calling this function. */
1316 first_error (const char *err)
1322 /* Parse a single type, e.g. ".s32", leading period included. */
1324 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1327 struct neon_type optype;
1331 if (parse_neon_type (&optype, &str) == SUCCESS)
1333 if (optype.elems == 1)
1334 *vectype = optype.el[0];
1337 first_error (_("only one type should be specified for operand"));
1343 first_error (_("vector type expected"));
1355 /* Special meanings for indices (which have a range of 0-7), which will fit into
1358 #define NEON_ALL_LANES 15
1359 #define NEON_INTERLEAVE_LANES 14
1361 /* Parse either a register or a scalar, with an optional type. Return the
1362 register number, and optionally fill in the actual type of the register
1363 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1364 type/index information in *TYPEINFO. */
1367 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1368 enum arm_reg_type *rtype,
1369 struct neon_typed_alias *typeinfo)
1372 struct reg_entry *reg = arm_reg_parse_multi (&str);
1373 struct neon_typed_alias atype;
1374 struct neon_type_el parsetype;
1378 atype.eltype.type = NT_invtype;
1379 atype.eltype.size = -1;
1381 /* Try alternate syntax for some types of register. Note these are mutually
1382 exclusive with the Neon syntax extensions. */
1385 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1393 /* Undo polymorphism when a set of register types may be accepted. */
1394 if ((type == REG_TYPE_NDQ
1395 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1396 || (type == REG_TYPE_VFSD
1397 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1398 || (type == REG_TYPE_NSDQ
1399 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1400 || reg->type == REG_TYPE_NQ))
1401 || (type == REG_TYPE_MMXWC
1402 && (reg->type == REG_TYPE_MMXWCG)))
1403 type = (enum arm_reg_type) reg->type;
1405 if (type != reg->type)
1411 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1413 if ((atype.defined & NTA_HASTYPE) != 0)
1415 first_error (_("can't redefine type for operand"));
1418 atype.defined |= NTA_HASTYPE;
1419 atype.eltype = parsetype;
1422 if (skip_past_char (&str, '[') == SUCCESS)
1424 if (type != REG_TYPE_VFD)
1426 first_error (_("only D registers may be indexed"));
1430 if ((atype.defined & NTA_HASINDEX) != 0)
1432 first_error (_("can't change index for operand"));
1436 atype.defined |= NTA_HASINDEX;
1438 if (skip_past_char (&str, ']') == SUCCESS)
1439 atype.index = NEON_ALL_LANES;
1444 my_get_expression (&exp, &str, GE_NO_PREFIX);
1446 if (exp.X_op != O_constant)
1448 first_error (_("constant expression required"));
1452 if (skip_past_char (&str, ']') == FAIL)
1455 atype.index = exp.X_add_number;
1470 /* Like arm_reg_parse, but allow allow the following extra features:
1471 - If RTYPE is non-zero, return the (possibly restricted) type of the
1472 register (e.g. Neon double or quad reg when either has been requested).
1473 - If this is a Neon vector type with additional type information, fill
1474 in the struct pointed to by VECTYPE (if non-NULL).
1475 This function will fault on encountering a scalar. */
1478 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1479 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1481 struct neon_typed_alias atype;
1483 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1488 /* Do not allow regname(... to parse as a register. */
1492 /* Do not allow a scalar (reg+index) to parse as a register. */
1493 if ((atype.defined & NTA_HASINDEX) != 0)
1495 first_error (_("register operand expected, but got scalar"));
1500 *vectype = atype.eltype;
1507 #define NEON_SCALAR_REG(X) ((X) >> 4)
1508 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1510 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1511 have enough information to be able to do a good job bounds-checking. So, we
1512 just do easy checks here, and do further checks later. */
1515 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1519 struct neon_typed_alias atype;
1521 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1523 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1526 if (atype.index == NEON_ALL_LANES)
1528 first_error (_("scalar must have an index"));
1531 else if (atype.index >= 64 / elsize)
1533 first_error (_("scalar index out of range"));
1538 *type = atype.eltype;
1542 return reg * 16 + atype.index;
1545 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1548 parse_reg_list (char ** strp)
1550 char * str = * strp;
1554 /* We come back here if we get ranges concatenated by '+' or '|'. */
1569 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1571 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1581 first_error (_("bad range in register list"));
1585 for (i = cur_reg + 1; i < reg; i++)
1587 if (range & (1 << i))
1589 (_("Warning: duplicated register (r%d) in register list"),
1597 if (range & (1 << reg))
1598 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1600 else if (reg <= cur_reg)
1601 as_tsktsk (_("Warning: register range not in ascending order"));
1606 while (skip_past_comma (&str) != FAIL
1607 || (in_range = 1, *str++ == '-'));
1612 first_error (_("missing `}'"));
1620 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1623 if (exp.X_op == O_constant)
1625 if (exp.X_add_number
1626 != (exp.X_add_number & 0x0000ffff))
1628 inst.error = _("invalid register mask");
1632 if ((range & exp.X_add_number) != 0)
1634 int regno = range & exp.X_add_number;
1637 regno = (1 << regno) - 1;
1639 (_("Warning: duplicated register (r%d) in register list"),
1643 range |= exp.X_add_number;
1647 if (inst.reloc.type != 0)
1649 inst.error = _("expression too complex");
1653 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1654 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1655 inst.reloc.pc_rel = 0;
1659 if (*str == '|' || *str == '+')
1665 while (another_range);
1671 /* Types of registers in a list. */
1680 /* Parse a VFP register list. If the string is invalid return FAIL.
1681 Otherwise return the number of registers, and set PBASE to the first
1682 register. Parses registers of type ETYPE.
1683 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1684 - Q registers can be used to specify pairs of D registers
1685 - { } can be omitted from around a singleton register list
1686 FIXME: This is not implemented, as it would require backtracking in
1689 This could be done (the meaning isn't really ambiguous), but doesn't
1690 fit in well with the current parsing framework.
1691 - 32 D registers may be used (also true for VFPv3).
1692 FIXME: Types are ignored in these register lists, which is probably a
1696 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1701 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1705 unsigned long mask = 0;
1710 inst.error = _("expecting {");
1719 regtype = REG_TYPE_VFS;
1724 regtype = REG_TYPE_VFD;
1727 case REGLIST_NEON_D:
1728 regtype = REG_TYPE_NDQ;
1732 if (etype != REGLIST_VFP_S)
1734 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1735 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1739 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1742 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1749 base_reg = max_regs;
1753 int setmask = 1, addregs = 1;
1755 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1757 if (new_base == FAIL)
1759 first_error (_(reg_expected_msgs[regtype]));
1763 if (new_base >= max_regs)
1765 first_error (_("register out of range in list"));
1769 /* Note: a value of 2 * n is returned for the register Q<n>. */
1770 if (regtype == REG_TYPE_NQ)
1776 if (new_base < base_reg)
1777 base_reg = new_base;
1779 if (mask & (setmask << new_base))
1781 first_error (_("invalid register list"));
1785 if ((mask >> new_base) != 0 && ! warned)
1787 as_tsktsk (_("register list not in ascending order"));
1791 mask |= setmask << new_base;
1794 if (*str == '-') /* We have the start of a range expression */
1800 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1803 inst.error = gettext (reg_expected_msgs[regtype]);
1807 if (high_range >= max_regs)
1809 first_error (_("register out of range in list"));
1813 if (regtype == REG_TYPE_NQ)
1814 high_range = high_range + 1;
1816 if (high_range <= new_base)
1818 inst.error = _("register range not in ascending order");
1822 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1824 if (mask & (setmask << new_base))
1826 inst.error = _("invalid register list");
1830 mask |= setmask << new_base;
1835 while (skip_past_comma (&str) != FAIL);
1839 /* Sanity check -- should have raised a parse error above. */
1840 if (count == 0 || count > max_regs)
1845 /* Final test -- the registers must be consecutive. */
1847 for (i = 0; i < count; i++)
1849 if ((mask & (1u << i)) == 0)
1851 inst.error = _("non-contiguous register range");
1861 /* True if two alias types are the same. */
1864 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1872 if (a->defined != b->defined)
1875 if ((a->defined & NTA_HASTYPE) != 0
1876 && (a->eltype.type != b->eltype.type
1877 || a->eltype.size != b->eltype.size))
1880 if ((a->defined & NTA_HASINDEX) != 0
1881 && (a->index != b->index))
1887 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1888 The base register is put in *PBASE.
1889 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1891 The register stride (minus one) is put in bit 4 of the return value.
1892 Bits [6:5] encode the list length (minus one).
1893 The type of the list elements is put in *ELTYPE, if non-NULL. */
1895 #define NEON_LANE(X) ((X) & 0xf)
1896 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1897 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1900 parse_neon_el_struct_list (char **str, unsigned *pbase,
1901 struct neon_type_el *eltype)
1908 int leading_brace = 0;
1909 enum arm_reg_type rtype = REG_TYPE_NDQ;
1910 const char *const incr_error = _("register stride must be 1 or 2");
1911 const char *const type_error = _("mismatched element/structure types in list");
1912 struct neon_typed_alias firsttype;
1914 if (skip_past_char (&ptr, '{') == SUCCESS)
1919 struct neon_typed_alias atype;
1920 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1924 first_error (_(reg_expected_msgs[rtype]));
1931 if (rtype == REG_TYPE_NQ)
1937 else if (reg_incr == -1)
1939 reg_incr = getreg - base_reg;
1940 if (reg_incr < 1 || reg_incr > 2)
1942 first_error (_(incr_error));
1946 else if (getreg != base_reg + reg_incr * count)
1948 first_error (_(incr_error));
1952 if (! neon_alias_types_same (&atype, &firsttype))
1954 first_error (_(type_error));
1958 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1962 struct neon_typed_alias htype;
1963 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1965 lane = NEON_INTERLEAVE_LANES;
1966 else if (lane != NEON_INTERLEAVE_LANES)
1968 first_error (_(type_error));
1973 else if (reg_incr != 1)
1975 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1979 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1982 first_error (_(reg_expected_msgs[rtype]));
1985 if (! neon_alias_types_same (&htype, &firsttype))
1987 first_error (_(type_error));
1990 count += hireg + dregs - getreg;
1994 /* If we're using Q registers, we can't use [] or [n] syntax. */
1995 if (rtype == REG_TYPE_NQ)
2001 if ((atype.defined & NTA_HASINDEX) != 0)
2005 else if (lane != atype.index)
2007 first_error (_(type_error));
2011 else if (lane == -1)
2012 lane = NEON_INTERLEAVE_LANES;
2013 else if (lane != NEON_INTERLEAVE_LANES)
2015 first_error (_(type_error));
2020 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2022 /* No lane set by [x]. We must be interleaving structures. */
2024 lane = NEON_INTERLEAVE_LANES;
2027 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2028 || (count > 1 && reg_incr == -1))
2030 first_error (_("error parsing element/structure list"));
2034 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2036 first_error (_("expected }"));
2044 *eltype = firsttype.eltype;
2049 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2052 /* Parse an explicit relocation suffix on an expression. This is
2053 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2054 arm_reloc_hsh contains no entries, so this function can only
2055 succeed if there is no () after the word. Returns -1 on error,
2056 BFD_RELOC_UNUSED if there wasn't any suffix. */
2058 parse_reloc (char **str)
2060 struct reloc_entry *r;
2064 return BFD_RELOC_UNUSED;
2069 while (*q && *q != ')' && *q != ',')
2074 if ((r = (struct reloc_entry *)
2075 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2082 /* Directives: register aliases. */
2084 static struct reg_entry *
2085 insert_reg_alias (char *str, unsigned number, int type)
2087 struct reg_entry *new_reg;
2090 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2092 if (new_reg->builtin)
2093 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2095 /* Only warn about a redefinition if it's not defined as the
2097 else if (new_reg->number != number || new_reg->type != type)
2098 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2103 name = xstrdup (str);
2104 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2106 new_reg->name = name;
2107 new_reg->number = number;
2108 new_reg->type = type;
2109 new_reg->builtin = FALSE;
2110 new_reg->neon = NULL;
2112 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2119 insert_neon_reg_alias (char *str, int number, int type,
2120 struct neon_typed_alias *atype)
2122 struct reg_entry *reg = insert_reg_alias (str, number, type);
2126 first_error (_("attempt to redefine typed alias"));
2132 reg->neon = (struct neon_typed_alias *)
2133 xmalloc (sizeof (struct neon_typed_alias));
2134 *reg->neon = *atype;
2138 /* Look for the .req directive. This is of the form:
2140 new_register_name .req existing_register_name
2142 If we find one, or if it looks sufficiently like one that we want to
2143 handle any error here, return TRUE. Otherwise return FALSE. */
2146 create_register_alias (char * newname, char *p)
2148 struct reg_entry *old;
2149 char *oldname, *nbuf;
2152 /* The input scrubber ensures that whitespace after the mnemonic is
2153 collapsed to single spaces. */
2155 if (strncmp (oldname, " .req ", 6) != 0)
2159 if (*oldname == '\0')
2162 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2165 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2169 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2170 the desired alias name, and p points to its end. If not, then
2171 the desired alias name is in the global original_case_string. */
2172 #ifdef TC_CASE_SENSITIVE
2175 newname = original_case_string;
2176 nlen = strlen (newname);
2179 nbuf = (char *) alloca (nlen + 1);
2180 memcpy (nbuf, newname, nlen);
2183 /* Create aliases under the new name as stated; an all-lowercase
2184 version of the new name; and an all-uppercase version of the new
2186 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2188 for (p = nbuf; *p; p++)
2191 if (strncmp (nbuf, newname, nlen))
2193 /* If this attempt to create an additional alias fails, do not bother
2194 trying to create the all-lower case alias. We will fail and issue
2195 a second, duplicate error message. This situation arises when the
2196 programmer does something like:
2199 The second .req creates the "Foo" alias but then fails to create
2200 the artificial FOO alias because it has already been created by the
2202 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2206 for (p = nbuf; *p; p++)
2209 if (strncmp (nbuf, newname, nlen))
2210 insert_reg_alias (nbuf, old->number, old->type);
2216 /* Create a Neon typed/indexed register alias using directives, e.g.:
2221 These typed registers can be used instead of the types specified after the
2222 Neon mnemonic, so long as all operands given have types. Types can also be
2223 specified directly, e.g.:
2224 vadd d0.s32, d1.s32, d2.s32 */
2227 create_neon_reg_alias (char *newname, char *p)
2229 enum arm_reg_type basetype;
2230 struct reg_entry *basereg;
2231 struct reg_entry mybasereg;
2232 struct neon_type ntype;
2233 struct neon_typed_alias typeinfo;
2234 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2237 typeinfo.defined = 0;
2238 typeinfo.eltype.type = NT_invtype;
2239 typeinfo.eltype.size = -1;
2240 typeinfo.index = -1;
2244 if (strncmp (p, " .dn ", 5) == 0)
2245 basetype = REG_TYPE_VFD;
2246 else if (strncmp (p, " .qn ", 5) == 0)
2247 basetype = REG_TYPE_NQ;
2256 basereg = arm_reg_parse_multi (&p);
2258 if (basereg && basereg->type != basetype)
2260 as_bad (_("bad type for register"));
2264 if (basereg == NULL)
2267 /* Try parsing as an integer. */
2268 my_get_expression (&exp, &p, GE_NO_PREFIX);
2269 if (exp.X_op != O_constant)
2271 as_bad (_("expression must be constant"));
2274 basereg = &mybasereg;
2275 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2281 typeinfo = *basereg->neon;
2283 if (parse_neon_type (&ntype, &p) == SUCCESS)
2285 /* We got a type. */
2286 if (typeinfo.defined & NTA_HASTYPE)
2288 as_bad (_("can't redefine the type of a register alias"));
2292 typeinfo.defined |= NTA_HASTYPE;
2293 if (ntype.elems != 1)
2295 as_bad (_("you must specify a single type only"));
2298 typeinfo.eltype = ntype.el[0];
2301 if (skip_past_char (&p, '[') == SUCCESS)
2304 /* We got a scalar index. */
2306 if (typeinfo.defined & NTA_HASINDEX)
2308 as_bad (_("can't redefine the index of a scalar alias"));
2312 my_get_expression (&exp, &p, GE_NO_PREFIX);
2314 if (exp.X_op != O_constant)
2316 as_bad (_("scalar index must be constant"));
2320 typeinfo.defined |= NTA_HASINDEX;
2321 typeinfo.index = exp.X_add_number;
2323 if (skip_past_char (&p, ']') == FAIL)
2325 as_bad (_("expecting ]"));
2330 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2331 the desired alias name, and p points to its end. If not, then
2332 the desired alias name is in the global original_case_string. */
2333 #ifdef TC_CASE_SENSITIVE
2334 namelen = nameend - newname;
2336 newname = original_case_string;
2337 namelen = strlen (newname);
2340 namebuf = (char *) alloca (namelen + 1);
2341 strncpy (namebuf, newname, namelen);
2342 namebuf[namelen] = '\0';
2344 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2345 typeinfo.defined != 0 ? &typeinfo : NULL);
2347 /* Insert name in all uppercase. */
2348 for (p = namebuf; *p; p++)
2351 if (strncmp (namebuf, newname, namelen))
2352 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2353 typeinfo.defined != 0 ? &typeinfo : NULL);
2355 /* Insert name in all lowercase. */
2356 for (p = namebuf; *p; p++)
2359 if (strncmp (namebuf, newname, namelen))
2360 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2361 typeinfo.defined != 0 ? &typeinfo : NULL);
2366 /* Should never be called, as .req goes between the alias and the
2367 register name, not at the beginning of the line. */
2370 s_req (int a ATTRIBUTE_UNUSED)
2372 as_bad (_("invalid syntax for .req directive"));
2376 s_dn (int a ATTRIBUTE_UNUSED)
2378 as_bad (_("invalid syntax for .dn directive"));
2382 s_qn (int a ATTRIBUTE_UNUSED)
2384 as_bad (_("invalid syntax for .qn directive"));
2387 /* The .unreq directive deletes an alias which was previously defined
2388 by .req. For example:
2394 s_unreq (int a ATTRIBUTE_UNUSED)
2399 name = input_line_pointer;
2401 while (*input_line_pointer != 0
2402 && *input_line_pointer != ' '
2403 && *input_line_pointer != '\n')
2404 ++input_line_pointer;
2406 saved_char = *input_line_pointer;
2407 *input_line_pointer = 0;
2410 as_bad (_("invalid syntax for .unreq directive"));
2413 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2417 as_bad (_("unknown register alias '%s'"), name);
2418 else if (reg->builtin)
2419 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2426 hash_delete (arm_reg_hsh, name, FALSE);
2427 free ((char *) reg->name);
2432 /* Also locate the all upper case and all lower case versions.
2433 Do not complain if we cannot find one or the other as it
2434 was probably deleted above. */
2436 nbuf = strdup (name);
2437 for (p = nbuf; *p; p++)
2439 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2442 hash_delete (arm_reg_hsh, nbuf, FALSE);
2443 free ((char *) reg->name);
2449 for (p = nbuf; *p; p++)
2451 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2454 hash_delete (arm_reg_hsh, nbuf, FALSE);
2455 free ((char *) reg->name);
2465 *input_line_pointer = saved_char;
2466 demand_empty_rest_of_line ();
2469 /* Directives: Instruction set selection. */
2472 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2473 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2474 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2475 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2477 /* Create a new mapping symbol for the transition to STATE. */
2480 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2483 const char * symname;
2490 type = BSF_NO_FLAGS;
2494 type = BSF_NO_FLAGS;
2498 type = BSF_NO_FLAGS;
2504 symbolP = symbol_new (symname, now_seg, value, frag);
2505 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2510 THUMB_SET_FUNC (symbolP, 0);
2511 ARM_SET_THUMB (symbolP, 0);
2512 ARM_SET_INTERWORK (symbolP, support_interwork);
2516 THUMB_SET_FUNC (symbolP, 1);
2517 ARM_SET_THUMB (symbolP, 1);
2518 ARM_SET_INTERWORK (symbolP, support_interwork);
2526 /* Save the mapping symbols for future reference. Also check that
2527 we do not place two mapping symbols at the same offset within a
2528 frag. We'll handle overlap between frags in
2529 check_mapping_symbols.
2531 If .fill or other data filling directive generates zero sized data,
2532 the mapping symbol for the following code will have the same value
2533 as the one generated for the data filling directive. In this case,
2534 we replace the old symbol with the new one at the same address. */
2537 if (frag->tc_frag_data.first_map != NULL)
2539 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2540 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2542 frag->tc_frag_data.first_map = symbolP;
2544 if (frag->tc_frag_data.last_map != NULL)
2546 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2547 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2548 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2550 frag->tc_frag_data.last_map = symbolP;
2553 /* We must sometimes convert a region marked as code to data during
2554 code alignment, if an odd number of bytes have to be padded. The
2555 code mapping symbol is pushed to an aligned address. */
2558 insert_data_mapping_symbol (enum mstate state,
2559 valueT value, fragS *frag, offsetT bytes)
2561 /* If there was already a mapping symbol, remove it. */
2562 if (frag->tc_frag_data.last_map != NULL
2563 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2565 symbolS *symp = frag->tc_frag_data.last_map;
2569 know (frag->tc_frag_data.first_map == symp);
2570 frag->tc_frag_data.first_map = NULL;
2572 frag->tc_frag_data.last_map = NULL;
2573 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2576 make_mapping_symbol (MAP_DATA, value, frag);
2577 make_mapping_symbol (state, value + bytes, frag);
2580 static void mapping_state_2 (enum mstate state, int max_chars);
2582 /* Set the mapping state to STATE. Only call this when about to
2583 emit some STATE bytes to the file. */
2586 mapping_state (enum mstate state)
2588 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2590 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2592 if (mapstate == state)
2593 /* The mapping symbol has already been emitted.
2594 There is nothing else to do. */
2597 if (state == MAP_ARM || state == MAP_THUMB)
2599 All ARM instructions require 4-byte alignment.
2600 (Almost) all Thumb instructions require 2-byte alignment.
2602 When emitting instructions into any section, mark the section
2605 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2606 but themselves require 2-byte alignment; this applies to some
2607 PC- relative forms. However, these cases will invovle implicit
2608 literal pool generation or an explicit .align >=2, both of
2609 which will cause the section to me marked with sufficient
2610 alignment. Thus, we don't handle those cases here. */
2611 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2613 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2614 /* This case will be evaluated later in the next else. */
2616 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2617 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2619 /* Only add the symbol if the offset is > 0:
2620 if we're at the first frag, check it's size > 0;
2621 if we're not at the first frag, then for sure
2622 the offset is > 0. */
2623 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2624 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2627 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2630 mapping_state_2 (state, 0);
2634 /* Same as mapping_state, but MAX_CHARS bytes have already been
2635 allocated. Put the mapping symbol that far back. */
2638 mapping_state_2 (enum mstate state, int max_chars)
2640 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2642 if (!SEG_NORMAL (now_seg))
2645 if (mapstate == state)
2646 /* The mapping symbol has already been emitted.
2647 There is nothing else to do. */
2650 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2651 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2654 #define mapping_state(x) ((void)0)
2655 #define mapping_state_2(x, y) ((void)0)
2658 /* Find the real, Thumb encoded start of a Thumb function. */
2662 find_real_start (symbolS * symbolP)
2665 const char * name = S_GET_NAME (symbolP);
2666 symbolS * new_target;
2668 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2669 #define STUB_NAME ".real_start_of"
2674 /* The compiler may generate BL instructions to local labels because
2675 it needs to perform a branch to a far away location. These labels
2676 do not have a corresponding ".real_start_of" label. We check
2677 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2678 the ".real_start_of" convention for nonlocal branches. */
2679 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2682 real_start = ACONCAT ((STUB_NAME, name, NULL));
2683 new_target = symbol_find (real_start);
2685 if (new_target == NULL)
2687 as_warn (_("Failed to find real start of function: %s\n"), name);
2688 new_target = symbolP;
2696 opcode_select (int width)
2703 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2704 as_bad (_("selected processor does not support THUMB opcodes"));
2707 /* No need to force the alignment, since we will have been
2708 coming from ARM mode, which is word-aligned. */
2709 record_alignment (now_seg, 1);
2716 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2717 as_bad (_("selected processor does not support ARM opcodes"));
2722 frag_align (2, 0, 0);
2724 record_alignment (now_seg, 1);
2729 as_bad (_("invalid instruction size selected (%d)"), width);
2734 s_arm (int ignore ATTRIBUTE_UNUSED)
2737 demand_empty_rest_of_line ();
2741 s_thumb (int ignore ATTRIBUTE_UNUSED)
2744 demand_empty_rest_of_line ();
2748 s_code (int unused ATTRIBUTE_UNUSED)
2752 temp = get_absolute_expression ();
2757 opcode_select (temp);
2761 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2766 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2768 /* If we are not already in thumb mode go into it, EVEN if
2769 the target processor does not support thumb instructions.
2770 This is used by gcc/config/arm/lib1funcs.asm for example
2771 to compile interworking support functions even if the
2772 target processor should not support interworking. */
2776 record_alignment (now_seg, 1);
2779 demand_empty_rest_of_line ();
2783 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2787 /* The following label is the name/address of the start of a Thumb function.
2788 We need to know this for the interworking support. */
2789 label_is_thumb_function_name = TRUE;
2792 /* Perform a .set directive, but also mark the alias as
2793 being a thumb function. */
2796 s_thumb_set (int equiv)
2798 /* XXX the following is a duplicate of the code for s_set() in read.c
2799 We cannot just call that code as we need to get at the symbol that
2806 /* Especial apologies for the random logic:
2807 This just grew, and could be parsed much more simply!
2809 name = input_line_pointer;
2810 delim = get_symbol_end ();
2811 end_name = input_line_pointer;
2814 if (*input_line_pointer != ',')
2817 as_bad (_("expected comma after name \"%s\""), name);
2819 ignore_rest_of_line ();
2823 input_line_pointer++;
2826 if (name[0] == '.' && name[1] == '\0')
2828 /* XXX - this should not happen to .thumb_set. */
2832 if ((symbolP = symbol_find (name)) == NULL
2833 && (symbolP = md_undefined_symbol (name)) == NULL)
2836 /* When doing symbol listings, play games with dummy fragments living
2837 outside the normal fragment chain to record the file and line info
2839 if (listing & LISTING_SYMBOLS)
2841 extern struct list_info_struct * listing_tail;
2842 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2844 memset (dummy_frag, 0, sizeof (fragS));
2845 dummy_frag->fr_type = rs_fill;
2846 dummy_frag->line = listing_tail;
2847 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2848 dummy_frag->fr_symbol = symbolP;
2852 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2855 /* "set" symbols are local unless otherwise specified. */
2856 SF_SET_LOCAL (symbolP);
2857 #endif /* OBJ_COFF */
2858 } /* Make a new symbol. */
2860 symbol_table_insert (symbolP);
2865 && S_IS_DEFINED (symbolP)
2866 && S_GET_SEGMENT (symbolP) != reg_section)
2867 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2869 pseudo_set (symbolP);
2871 demand_empty_rest_of_line ();
2873 /* XXX Now we come to the Thumb specific bit of code. */
2875 THUMB_SET_FUNC (symbolP, 1);
2876 ARM_SET_THUMB (symbolP, 1);
2877 #if defined OBJ_ELF || defined OBJ_COFF
2878 ARM_SET_INTERWORK (symbolP, support_interwork);
2882 /* Directives: Mode selection. */
2884 /* .syntax [unified|divided] - choose the new unified syntax
2885 (same for Arm and Thumb encoding, modulo slight differences in what
2886 can be represented) or the old divergent syntax for each mode. */
2888 s_syntax (int unused ATTRIBUTE_UNUSED)
2892 name = input_line_pointer;
2893 delim = get_symbol_end ();
2895 if (!strcasecmp (name, "unified"))
2896 unified_syntax = TRUE;
2897 else if (!strcasecmp (name, "divided"))
2898 unified_syntax = FALSE;
2901 as_bad (_("unrecognized syntax mode \"%s\""), name);
2904 *input_line_pointer = delim;
2905 demand_empty_rest_of_line ();
2908 /* Directives: sectioning and alignment. */
2910 /* Same as s_align_ptwo but align 0 => align 2. */
2913 s_align (int unused ATTRIBUTE_UNUSED)
2918 long max_alignment = 15;
2920 temp = get_absolute_expression ();
2921 if (temp > max_alignment)
2922 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2925 as_bad (_("alignment negative. 0 assumed."));
2929 if (*input_line_pointer == ',')
2931 input_line_pointer++;
2932 temp_fill = get_absolute_expression ();
2944 /* Only make a frag if we HAVE to. */
2945 if (temp && !need_pass_2)
2947 if (!fill_p && subseg_text_p (now_seg))
2948 frag_align_code (temp, 0);
2950 frag_align (temp, (int) temp_fill, 0);
2952 demand_empty_rest_of_line ();
2954 record_alignment (now_seg, temp);
2958 s_bss (int ignore ATTRIBUTE_UNUSED)
2960 /* We don't support putting frags in the BSS segment, we fake it by
2961 marking in_bss, then looking at s_skip for clues. */
2962 subseg_set (bss_section, 0);
2963 demand_empty_rest_of_line ();
2965 #ifdef md_elf_section_change_hook
2966 md_elf_section_change_hook ();
2971 s_even (int ignore ATTRIBUTE_UNUSED)
2973 /* Never make frag if expect extra pass. */
2975 frag_align (1, 0, 0);
2977 record_alignment (now_seg, 1);
2979 demand_empty_rest_of_line ();
2982 /* Directives: Literal pools. */
2984 static literal_pool *
2985 find_literal_pool (void)
2987 literal_pool * pool;
2989 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2991 if (pool->section == now_seg
2992 && pool->sub_section == now_subseg)
2999 static literal_pool *
3000 find_or_make_literal_pool (void)
3002 /* Next literal pool ID number. */
3003 static unsigned int latest_pool_num = 1;
3004 literal_pool * pool;
3006 pool = find_literal_pool ();
3010 /* Create a new pool. */
3011 pool = (literal_pool *) xmalloc (sizeof (* pool));
3015 pool->next_free_entry = 0;
3016 pool->section = now_seg;
3017 pool->sub_section = now_subseg;
3018 pool->next = list_of_pools;
3019 pool->symbol = NULL;
3021 /* Add it to the list. */
3022 list_of_pools = pool;
3025 /* New pools, and emptied pools, will have a NULL symbol. */
3026 if (pool->symbol == NULL)
3028 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3029 (valueT) 0, &zero_address_frag);
3030 pool->id = latest_pool_num ++;
3037 /* Add the literal in the global 'inst'
3038 structure to the relevant literal pool. */
3041 add_to_lit_pool (void)
3043 literal_pool * pool;
3046 pool = find_or_make_literal_pool ();
3048 /* Check if this literal value is already in the pool. */
3049 for (entry = 0; entry < pool->next_free_entry; entry ++)
3051 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3052 && (inst.reloc.exp.X_op == O_constant)
3053 && (pool->literals[entry].X_add_number
3054 == inst.reloc.exp.X_add_number)
3055 && (pool->literals[entry].X_unsigned
3056 == inst.reloc.exp.X_unsigned))
3059 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3060 && (inst.reloc.exp.X_op == O_symbol)
3061 && (pool->literals[entry].X_add_number
3062 == inst.reloc.exp.X_add_number)
3063 && (pool->literals[entry].X_add_symbol
3064 == inst.reloc.exp.X_add_symbol)
3065 && (pool->literals[entry].X_op_symbol
3066 == inst.reloc.exp.X_op_symbol))
3070 /* Do we need to create a new entry? */
3071 if (entry == pool->next_free_entry)
3073 if (entry >= MAX_LITERAL_POOL_SIZE)
3075 inst.error = _("literal pool overflow");
3079 pool->literals[entry] = inst.reloc.exp;
3081 /* PR ld/12974: Record the location of the first source line to reference
3082 this entry in the literal pool. If it turns out during linking that the
3083 symbol does not exist we will be able to give an accurate line number for
3084 the (first use of the) missing reference. */
3085 if (debug_type == DEBUG_DWARF2)
3086 dwarf2_where (pool->locs + entry);
3088 pool->next_free_entry += 1;
3091 inst.reloc.exp.X_op = O_symbol;
3092 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3093 inst.reloc.exp.X_add_symbol = pool->symbol;
3098 /* Can't use symbol_new here, so have to create a symbol and then at
3099 a later date assign it a value. Thats what these functions do. */
3102 symbol_locate (symbolS * symbolP,
3103 const char * name, /* It is copied, the caller can modify. */
3104 segT segment, /* Segment identifier (SEG_<something>). */
3105 valueT valu, /* Symbol value. */
3106 fragS * frag) /* Associated fragment. */
3108 unsigned int name_length;
3109 char * preserved_copy_of_name;
3111 name_length = strlen (name) + 1; /* +1 for \0. */
3112 obstack_grow (¬es, name, name_length);
3113 preserved_copy_of_name = (char *) obstack_finish (¬es);
3115 #ifdef tc_canonicalize_symbol_name
3116 preserved_copy_of_name =
3117 tc_canonicalize_symbol_name (preserved_copy_of_name);
3120 S_SET_NAME (symbolP, preserved_copy_of_name);
3122 S_SET_SEGMENT (symbolP, segment);
3123 S_SET_VALUE (symbolP, valu);
3124 symbol_clear_list_pointers (symbolP);
3126 symbol_set_frag (symbolP, frag);
3128 /* Link to end of symbol chain. */
3130 extern int symbol_table_frozen;
3132 if (symbol_table_frozen)
3136 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3138 obj_symbol_new_hook (symbolP);
3140 #ifdef tc_symbol_new_hook
3141 tc_symbol_new_hook (symbolP);
3145 verify_symbol_chain (symbol_rootP, symbol_lastP);
3146 #endif /* DEBUG_SYMS */
3151 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3154 literal_pool * pool;
3157 pool = find_literal_pool ();
3159 || pool->symbol == NULL
3160 || pool->next_free_entry == 0)
3163 mapping_state (MAP_DATA);
3165 /* Align pool as you have word accesses.
3166 Only make a frag if we have to. */
3168 frag_align (2, 0, 0);
3170 record_alignment (now_seg, 2);
3172 sprintf (sym_name, "$$lit_\002%x", pool->id);
3174 symbol_locate (pool->symbol, sym_name, now_seg,
3175 (valueT) frag_now_fix (), frag_now);
3176 symbol_table_insert (pool->symbol);
3178 ARM_SET_THUMB (pool->symbol, thumb_mode);
3180 #if defined OBJ_COFF || defined OBJ_ELF
3181 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3184 for (entry = 0; entry < pool->next_free_entry; entry ++)
3187 if (debug_type == DEBUG_DWARF2)
3188 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3190 /* First output the expression in the instruction to the pool. */
3191 emit_expr (&(pool->literals[entry]), 4); /* .word */
3194 /* Mark the pool as empty. */
3195 pool->next_free_entry = 0;
3196 pool->symbol = NULL;
3200 /* Forward declarations for functions below, in the MD interface
3202 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3203 static valueT create_unwind_entry (int);
3204 static void start_unwind_section (const segT, int);
3205 static void add_unwind_opcode (valueT, int);
3206 static void flush_pending_unwind (void);
3208 /* Directives: Data. */
3211 s_arm_elf_cons (int nbytes)
3215 #ifdef md_flush_pending_output
3216 md_flush_pending_output ();
3219 if (is_it_end_of_statement ())
3221 demand_empty_rest_of_line ();
3225 #ifdef md_cons_align
3226 md_cons_align (nbytes);
3229 mapping_state (MAP_DATA);
3233 char *base = input_line_pointer;
3237 if (exp.X_op != O_symbol)
3238 emit_expr (&exp, (unsigned int) nbytes);
3241 char *before_reloc = input_line_pointer;
3242 reloc = parse_reloc (&input_line_pointer);
3245 as_bad (_("unrecognized relocation suffix"));
3246 ignore_rest_of_line ();
3249 else if (reloc == BFD_RELOC_UNUSED)
3250 emit_expr (&exp, (unsigned int) nbytes);
3253 reloc_howto_type *howto = (reloc_howto_type *)
3254 bfd_reloc_type_lookup (stdoutput,
3255 (bfd_reloc_code_real_type) reloc);
3256 int size = bfd_get_reloc_size (howto);
3258 if (reloc == BFD_RELOC_ARM_PLT32)
3260 as_bad (_("(plt) is only valid on branch targets"));
3261 reloc = BFD_RELOC_UNUSED;
3266 as_bad (_("%s relocations do not fit in %d bytes"),
3267 howto->name, nbytes);
3270 /* We've parsed an expression stopping at O_symbol.
3271 But there may be more expression left now that we
3272 have parsed the relocation marker. Parse it again.
3273 XXX Surely there is a cleaner way to do this. */
3274 char *p = input_line_pointer;
3276 char *save_buf = (char *) alloca (input_line_pointer - base);
3277 memcpy (save_buf, base, input_line_pointer - base);
3278 memmove (base + (input_line_pointer - before_reloc),
3279 base, before_reloc - base);
3281 input_line_pointer = base + (input_line_pointer-before_reloc);
3283 memcpy (base, save_buf, p - base);
3285 offset = nbytes - size;
3286 p = frag_more ((int) nbytes);
3287 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3288 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3293 while (*input_line_pointer++ == ',');
3295 /* Put terminator back into stream. */
3296 input_line_pointer --;
3297 demand_empty_rest_of_line ();
3300 /* Emit an expression containing a 32-bit thumb instruction.
3301 Implementation based on put_thumb32_insn. */
3304 emit_thumb32_expr (expressionS * exp)
3306 expressionS exp_high = *exp;
3308 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3309 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3310 exp->X_add_number &= 0xffff;
3311 emit_expr (exp, (unsigned int) THUMB_SIZE);
3314 /* Guess the instruction size based on the opcode. */
3317 thumb_insn_size (int opcode)
3319 if ((unsigned int) opcode < 0xe800u)
3321 else if ((unsigned int) opcode >= 0xe8000000u)
3328 emit_insn (expressionS *exp, int nbytes)
3332 if (exp->X_op == O_constant)
3337 size = thumb_insn_size (exp->X_add_number);
3341 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3343 as_bad (_(".inst.n operand too big. "\
3344 "Use .inst.w instead"));
3349 if (now_it.state == AUTOMATIC_IT_BLOCK)
3350 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3352 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3354 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3355 emit_thumb32_expr (exp);
3357 emit_expr (exp, (unsigned int) size);
3359 it_fsm_post_encode ();
3363 as_bad (_("cannot determine Thumb instruction size. " \
3364 "Use .inst.n/.inst.w instead"));
3367 as_bad (_("constant expression required"));
3372 /* Like s_arm_elf_cons but do not use md_cons_align and
3373 set the mapping state to MAP_ARM/MAP_THUMB. */
3376 s_arm_elf_inst (int nbytes)
3378 if (is_it_end_of_statement ())
3380 demand_empty_rest_of_line ();
3384 /* Calling mapping_state () here will not change ARM/THUMB,
3385 but will ensure not to be in DATA state. */
3388 mapping_state (MAP_THUMB);
3393 as_bad (_("width suffixes are invalid in ARM mode"));
3394 ignore_rest_of_line ();
3400 mapping_state (MAP_ARM);
3409 if (! emit_insn (& exp, nbytes))
3411 ignore_rest_of_line ();
3415 while (*input_line_pointer++ == ',');
3417 /* Put terminator back into stream. */
3418 input_line_pointer --;
3419 demand_empty_rest_of_line ();
3422 /* Parse a .rel31 directive. */
3425 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3432 if (*input_line_pointer == '1')
3433 highbit = 0x80000000;
3434 else if (*input_line_pointer != '0')
3435 as_bad (_("expected 0 or 1"));
3437 input_line_pointer++;
3438 if (*input_line_pointer != ',')
3439 as_bad (_("missing comma"));
3440 input_line_pointer++;
3442 #ifdef md_flush_pending_output
3443 md_flush_pending_output ();
3446 #ifdef md_cons_align
3450 mapping_state (MAP_DATA);
3455 md_number_to_chars (p, highbit, 4);
3456 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3457 BFD_RELOC_ARM_PREL31);
3459 demand_empty_rest_of_line ();
3462 /* Directives: AEABI stack-unwind tables. */
3464 /* Parse an unwind_fnstart directive. Simply records the current location. */
3467 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3469 demand_empty_rest_of_line ();
3470 if (unwind.proc_start)
3472 as_bad (_("duplicate .fnstart directive"));
3476 /* Mark the start of the function. */
3477 unwind.proc_start = expr_build_dot ();
3479 /* Reset the rest of the unwind info. */
3480 unwind.opcode_count = 0;
3481 unwind.table_entry = NULL;
3482 unwind.personality_routine = NULL;
3483 unwind.personality_index = -1;
3484 unwind.frame_size = 0;
3485 unwind.fp_offset = 0;
3486 unwind.fp_reg = REG_SP;
3488 unwind.sp_restored = 0;
3492 /* Parse a handlerdata directive. Creates the exception handling table entry
3493 for the function. */
3496 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3498 demand_empty_rest_of_line ();
3499 if (!unwind.proc_start)
3500 as_bad (MISSING_FNSTART);
3502 if (unwind.table_entry)
3503 as_bad (_("duplicate .handlerdata directive"));
3505 create_unwind_entry (1);
3508 /* Parse an unwind_fnend directive. Generates the index table entry. */
3511 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3516 unsigned int marked_pr_dependency;
3518 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3522 as_bad (_(".fnend directive without .fnstart"));
3526 /* Add eh table entry. */
3527 if (unwind.table_entry == NULL)
3528 val = create_unwind_entry (0);
3532 /* Add index table entry. This is two words. */
3533 start_unwind_section (unwind.saved_seg, 1);
3534 frag_align (2, 0, 0);
3535 record_alignment (now_seg, 2);
3537 ptr = frag_more (8);
3538 where = frag_now_fix () - 8;
3540 /* Self relative offset of the function start. */
3541 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3542 BFD_RELOC_ARM_PREL31);
3544 /* Indicate dependency on EHABI-defined personality routines to the
3545 linker, if it hasn't been done already. */
3546 marked_pr_dependency
3547 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3548 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3549 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3551 static const char *const name[] =
3553 "__aeabi_unwind_cpp_pr0",
3554 "__aeabi_unwind_cpp_pr1",
3555 "__aeabi_unwind_cpp_pr2"
3557 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3558 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3559 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3560 |= 1 << unwind.personality_index;
3564 /* Inline exception table entry. */
3565 md_number_to_chars (ptr + 4, val, 4);
3567 /* Self relative offset of the table entry. */
3568 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3569 BFD_RELOC_ARM_PREL31);
3571 /* Restore the original section. */
3572 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3574 unwind.proc_start = NULL;
3578 /* Parse an unwind_cantunwind directive. */
3581 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3583 demand_empty_rest_of_line ();
3584 if (!unwind.proc_start)
3585 as_bad (MISSING_FNSTART);
3587 if (unwind.personality_routine || unwind.personality_index != -1)
3588 as_bad (_("personality routine specified for cantunwind frame"));
3590 unwind.personality_index = -2;
3594 /* Parse a personalityindex directive. */
3597 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3601 if (!unwind.proc_start)
3602 as_bad (MISSING_FNSTART);
3604 if (unwind.personality_routine || unwind.personality_index != -1)
3605 as_bad (_("duplicate .personalityindex directive"));
3609 if (exp.X_op != O_constant
3610 || exp.X_add_number < 0 || exp.X_add_number > 15)
3612 as_bad (_("bad personality routine number"));
3613 ignore_rest_of_line ();
3617 unwind.personality_index = exp.X_add_number;
3619 demand_empty_rest_of_line ();
3623 /* Parse a personality directive. */
3626 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3630 if (!unwind.proc_start)
3631 as_bad (MISSING_FNSTART);
3633 if (unwind.personality_routine || unwind.personality_index != -1)
3634 as_bad (_("duplicate .personality directive"));
3636 name = input_line_pointer;
3637 c = get_symbol_end ();
3638 p = input_line_pointer;
3639 unwind.personality_routine = symbol_find_or_make (name);
3641 demand_empty_rest_of_line ();
3645 /* Parse a directive saving core registers. */
3648 s_arm_unwind_save_core (void)
3654 range = parse_reg_list (&input_line_pointer);
3657 as_bad (_("expected register list"));
3658 ignore_rest_of_line ();
3662 demand_empty_rest_of_line ();
3664 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3665 into .unwind_save {..., sp...}. We aren't bothered about the value of
3666 ip because it is clobbered by calls. */
3667 if (unwind.sp_restored && unwind.fp_reg == 12
3668 && (range & 0x3000) == 0x1000)
3670 unwind.opcode_count--;
3671 unwind.sp_restored = 0;
3672 range = (range | 0x2000) & ~0x1000;
3673 unwind.pending_offset = 0;
3679 /* See if we can use the short opcodes. These pop a block of up to 8
3680 registers starting with r4, plus maybe r14. */
3681 for (n = 0; n < 8; n++)
3683 /* Break at the first non-saved register. */
3684 if ((range & (1 << (n + 4))) == 0)
3687 /* See if there are any other bits set. */
3688 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3690 /* Use the long form. */
3691 op = 0x8000 | ((range >> 4) & 0xfff);
3692 add_unwind_opcode (op, 2);
3696 /* Use the short form. */
3698 op = 0xa8; /* Pop r14. */
3700 op = 0xa0; /* Do not pop r14. */
3702 add_unwind_opcode (op, 1);
3709 op = 0xb100 | (range & 0xf);
3710 add_unwind_opcode (op, 2);
3713 /* Record the number of bytes pushed. */
3714 for (n = 0; n < 16; n++)
3716 if (range & (1 << n))
3717 unwind.frame_size += 4;
3722 /* Parse a directive saving FPA registers. */
3725 s_arm_unwind_save_fpa (int reg)
3731 /* Get Number of registers to transfer. */
3732 if (skip_past_comma (&input_line_pointer) != FAIL)
3735 exp.X_op = O_illegal;
3737 if (exp.X_op != O_constant)
3739 as_bad (_("expected , <constant>"));
3740 ignore_rest_of_line ();
3744 num_regs = exp.X_add_number;
3746 if (num_regs < 1 || num_regs > 4)
3748 as_bad (_("number of registers must be in the range [1:4]"));
3749 ignore_rest_of_line ();
3753 demand_empty_rest_of_line ();
3758 op = 0xb4 | (num_regs - 1);
3759 add_unwind_opcode (op, 1);
3764 op = 0xc800 | (reg << 4) | (num_regs - 1);
3765 add_unwind_opcode (op, 2);
3767 unwind.frame_size += num_regs * 12;
3771 /* Parse a directive saving VFP registers for ARMv6 and above. */
3774 s_arm_unwind_save_vfp_armv6 (void)
3779 int num_vfpv3_regs = 0;
3780 int num_regs_below_16;
3782 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3785 as_bad (_("expected register list"));
3786 ignore_rest_of_line ();
3790 demand_empty_rest_of_line ();
3792 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3793 than FSTMX/FLDMX-style ones). */
3795 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3797 num_vfpv3_regs = count;
3798 else if (start + count > 16)
3799 num_vfpv3_regs = start + count - 16;
3801 if (num_vfpv3_regs > 0)
3803 int start_offset = start > 16 ? start - 16 : 0;
3804 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3805 add_unwind_opcode (op, 2);
3808 /* Generate opcode for registers numbered in the range 0 .. 15. */
3809 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3810 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3811 if (num_regs_below_16 > 0)
3813 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3814 add_unwind_opcode (op, 2);
3817 unwind.frame_size += count * 8;
3821 /* Parse a directive saving VFP registers for pre-ARMv6. */
3824 s_arm_unwind_save_vfp (void)
3830 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3833 as_bad (_("expected register list"));
3834 ignore_rest_of_line ();
3838 demand_empty_rest_of_line ();
3843 op = 0xb8 | (count - 1);
3844 add_unwind_opcode (op, 1);
3849 op = 0xb300 | (reg << 4) | (count - 1);
3850 add_unwind_opcode (op, 2);
3852 unwind.frame_size += count * 8 + 4;
3856 /* Parse a directive saving iWMMXt data registers. */
3859 s_arm_unwind_save_mmxwr (void)
3867 if (*input_line_pointer == '{')
3868 input_line_pointer++;
3872 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3876 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3881 as_tsktsk (_("register list not in ascending order"));
3884 if (*input_line_pointer == '-')
3886 input_line_pointer++;
3887 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3890 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3893 else if (reg >= hi_reg)
3895 as_bad (_("bad register range"));
3898 for (; reg < hi_reg; reg++)
3902 while (skip_past_comma (&input_line_pointer) != FAIL);
3904 if (*input_line_pointer == '}')
3905 input_line_pointer++;
3907 demand_empty_rest_of_line ();
3909 /* Generate any deferred opcodes because we're going to be looking at
3911 flush_pending_unwind ();
3913 for (i = 0; i < 16; i++)
3915 if (mask & (1 << i))
3916 unwind.frame_size += 8;
3919 /* Attempt to combine with a previous opcode. We do this because gcc
3920 likes to output separate unwind directives for a single block of
3922 if (unwind.opcode_count > 0)
3924 i = unwind.opcodes[unwind.opcode_count - 1];
3925 if ((i & 0xf8) == 0xc0)
3928 /* Only merge if the blocks are contiguous. */
3931 if ((mask & 0xfe00) == (1 << 9))
3933 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3934 unwind.opcode_count--;
3937 else if (i == 6 && unwind.opcode_count >= 2)
3939 i = unwind.opcodes[unwind.opcode_count - 2];
3943 op = 0xffff << (reg - 1);
3945 && ((mask & op) == (1u << (reg - 1))))
3947 op = (1 << (reg + i + 1)) - 1;
3948 op &= ~((1 << reg) - 1);
3950 unwind.opcode_count -= 2;
3957 /* We want to generate opcodes in the order the registers have been
3958 saved, ie. descending order. */
3959 for (reg = 15; reg >= -1; reg--)
3961 /* Save registers in blocks. */
3963 || !(mask & (1 << reg)))
3965 /* We found an unsaved reg. Generate opcodes to save the
3972 op = 0xc0 | (hi_reg - 10);
3973 add_unwind_opcode (op, 1);
3978 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3979 add_unwind_opcode (op, 2);
3988 ignore_rest_of_line ();
3992 s_arm_unwind_save_mmxwcg (void)
3999 if (*input_line_pointer == '{')
4000 input_line_pointer++;
4004 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4008 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4014 as_tsktsk (_("register list not in ascending order"));
4017 if (*input_line_pointer == '-')
4019 input_line_pointer++;
4020 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4023 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4026 else if (reg >= hi_reg)
4028 as_bad (_("bad register range"));
4031 for (; reg < hi_reg; reg++)
4035 while (skip_past_comma (&input_line_pointer) != FAIL);
4037 if (*input_line_pointer == '}')
4038 input_line_pointer++;
4040 demand_empty_rest_of_line ();
4042 /* Generate any deferred opcodes because we're going to be looking at
4044 flush_pending_unwind ();
4046 for (reg = 0; reg < 16; reg++)
4048 if (mask & (1 << reg))
4049 unwind.frame_size += 4;
4052 add_unwind_opcode (op, 2);
4055 ignore_rest_of_line ();
4059 /* Parse an unwind_save directive.
4060 If the argument is non-zero, this is a .vsave directive. */
4063 s_arm_unwind_save (int arch_v6)
4066 struct reg_entry *reg;
4067 bfd_boolean had_brace = FALSE;
4069 if (!unwind.proc_start)
4070 as_bad (MISSING_FNSTART);
4072 /* Figure out what sort of save we have. */
4073 peek = input_line_pointer;
4081 reg = arm_reg_parse_multi (&peek);
4085 as_bad (_("register expected"));
4086 ignore_rest_of_line ();
4095 as_bad (_("FPA .unwind_save does not take a register list"));
4096 ignore_rest_of_line ();
4099 input_line_pointer = peek;
4100 s_arm_unwind_save_fpa (reg->number);
4103 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4106 s_arm_unwind_save_vfp_armv6 ();
4108 s_arm_unwind_save_vfp ();
4110 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4111 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4114 as_bad (_(".unwind_save does not support this kind of register"));
4115 ignore_rest_of_line ();
4120 /* Parse an unwind_movsp directive. */
4123 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4129 if (!unwind.proc_start)
4130 as_bad (MISSING_FNSTART);
4132 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4135 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4136 ignore_rest_of_line ();
4140 /* Optional constant. */
4141 if (skip_past_comma (&input_line_pointer) != FAIL)
4143 if (immediate_for_directive (&offset) == FAIL)
4149 demand_empty_rest_of_line ();
4151 if (reg == REG_SP || reg == REG_PC)
4153 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4157 if (unwind.fp_reg != REG_SP)
4158 as_bad (_("unexpected .unwind_movsp directive"));
4160 /* Generate opcode to restore the value. */
4162 add_unwind_opcode (op, 1);
4164 /* Record the information for later. */
4165 unwind.fp_reg = reg;
4166 unwind.fp_offset = unwind.frame_size - offset;
4167 unwind.sp_restored = 1;
4170 /* Parse an unwind_pad directive. */
4173 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4177 if (!unwind.proc_start)
4178 as_bad (MISSING_FNSTART);
4180 if (immediate_for_directive (&offset) == FAIL)
4185 as_bad (_("stack increment must be multiple of 4"));
4186 ignore_rest_of_line ();
4190 /* Don't generate any opcodes, just record the details for later. */
4191 unwind.frame_size += offset;
4192 unwind.pending_offset += offset;
4194 demand_empty_rest_of_line ();
4197 /* Parse an unwind_setfp directive. */
4200 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4206 if (!unwind.proc_start)
4207 as_bad (MISSING_FNSTART);
4209 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4210 if (skip_past_comma (&input_line_pointer) == FAIL)
4213 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4215 if (fp_reg == FAIL || sp_reg == FAIL)
4217 as_bad (_("expected <reg>, <reg>"));
4218 ignore_rest_of_line ();
4222 /* Optional constant. */
4223 if (skip_past_comma (&input_line_pointer) != FAIL)
4225 if (immediate_for_directive (&offset) == FAIL)
4231 demand_empty_rest_of_line ();
4233 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4235 as_bad (_("register must be either sp or set by a previous"
4236 "unwind_movsp directive"));
4240 /* Don't generate any opcodes, just record the information for later. */
4241 unwind.fp_reg = fp_reg;
4243 if (sp_reg == REG_SP)
4244 unwind.fp_offset = unwind.frame_size - offset;
4246 unwind.fp_offset -= offset;
4249 /* Parse an unwind_raw directive. */
4252 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4255 /* This is an arbitrary limit. */
4256 unsigned char op[16];
4259 if (!unwind.proc_start)
4260 as_bad (MISSING_FNSTART);
4263 if (exp.X_op == O_constant
4264 && skip_past_comma (&input_line_pointer) != FAIL)
4266 unwind.frame_size += exp.X_add_number;
4270 exp.X_op = O_illegal;
4272 if (exp.X_op != O_constant)
4274 as_bad (_("expected <offset>, <opcode>"));
4275 ignore_rest_of_line ();
4281 /* Parse the opcode. */
4286 as_bad (_("unwind opcode too long"));
4287 ignore_rest_of_line ();
4289 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4291 as_bad (_("invalid unwind opcode"));
4292 ignore_rest_of_line ();
4295 op[count++] = exp.X_add_number;
4297 /* Parse the next byte. */
4298 if (skip_past_comma (&input_line_pointer) == FAIL)
4304 /* Add the opcode bytes in reverse order. */
4306 add_unwind_opcode (op[count], 1);
4308 demand_empty_rest_of_line ();
4312 /* Parse a .eabi_attribute directive. */
4315 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4317 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4319 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4320 attributes_set_explicitly[tag] = 1;
4323 /* Emit a tls fix for the symbol. */
4326 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4330 #ifdef md_flush_pending_output
4331 md_flush_pending_output ();
4334 #ifdef md_cons_align
4338 /* Since we're just labelling the code, there's no need to define a
4341 p = obstack_next_free (&frchain_now->frch_obstack);
4342 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4343 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4344 : BFD_RELOC_ARM_TLS_DESCSEQ);
4346 #endif /* OBJ_ELF */
4348 static void s_arm_arch (int);
4349 static void s_arm_object_arch (int);
4350 static void s_arm_cpu (int);
4351 static void s_arm_fpu (int);
4352 static void s_arm_arch_extension (int);
4357 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4364 if (exp.X_op == O_symbol)
4365 exp.X_op = O_secrel;
4367 emit_expr (&exp, 4);
4369 while (*input_line_pointer++ == ',');
4371 input_line_pointer--;
4372 demand_empty_rest_of_line ();
4376 /* This table describes all the machine specific pseudo-ops the assembler
4377 has to support. The fields are:
4378 pseudo-op name without dot
4379 function to call to execute this pseudo-op
4380 Integer arg to pass to the function. */
4382 const pseudo_typeS md_pseudo_table[] =
4384 /* Never called because '.req' does not start a line. */
4385 { "req", s_req, 0 },
4386 /* Following two are likewise never called. */
4389 { "unreq", s_unreq, 0 },
4390 { "bss", s_bss, 0 },
4391 { "align", s_align, 0 },
4392 { "arm", s_arm, 0 },
4393 { "thumb", s_thumb, 0 },
4394 { "code", s_code, 0 },
4395 { "force_thumb", s_force_thumb, 0 },
4396 { "thumb_func", s_thumb_func, 0 },
4397 { "thumb_set", s_thumb_set, 0 },
4398 { "even", s_even, 0 },
4399 { "ltorg", s_ltorg, 0 },
4400 { "pool", s_ltorg, 0 },
4401 { "syntax", s_syntax, 0 },
4402 { "cpu", s_arm_cpu, 0 },
4403 { "arch", s_arm_arch, 0 },
4404 { "object_arch", s_arm_object_arch, 0 },
4405 { "fpu", s_arm_fpu, 0 },
4406 { "arch_extension", s_arm_arch_extension, 0 },
4408 { "word", s_arm_elf_cons, 4 },
4409 { "long", s_arm_elf_cons, 4 },
4410 { "inst.n", s_arm_elf_inst, 2 },
4411 { "inst.w", s_arm_elf_inst, 4 },
4412 { "inst", s_arm_elf_inst, 0 },
4413 { "rel31", s_arm_rel31, 0 },
4414 { "fnstart", s_arm_unwind_fnstart, 0 },
4415 { "fnend", s_arm_unwind_fnend, 0 },
4416 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4417 { "personality", s_arm_unwind_personality, 0 },
4418 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4419 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4420 { "save", s_arm_unwind_save, 0 },
4421 { "vsave", s_arm_unwind_save, 1 },
4422 { "movsp", s_arm_unwind_movsp, 0 },
4423 { "pad", s_arm_unwind_pad, 0 },
4424 { "setfp", s_arm_unwind_setfp, 0 },
4425 { "unwind_raw", s_arm_unwind_raw, 0 },
4426 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4427 { "tlsdescseq", s_arm_tls_descseq, 0 },
4431 /* These are used for dwarf. */
4435 /* These are used for dwarf2. */
4436 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4437 { "loc", dwarf2_directive_loc, 0 },
4438 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4440 { "extend", float_cons, 'x' },
4441 { "ldouble", float_cons, 'x' },
4442 { "packed", float_cons, 'p' },
4444 {"secrel32", pe_directive_secrel, 0},
4449 /* Parser functions used exclusively in instruction operands. */
4451 /* Generic immediate-value read function for use in insn parsing.
4452 STR points to the beginning of the immediate (the leading #);
4453 VAL receives the value; if the value is outside [MIN, MAX]
4454 issue an error. PREFIX_OPT is true if the immediate prefix is
4458 parse_immediate (char **str, int *val, int min, int max,
4459 bfd_boolean prefix_opt)
4462 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4463 if (exp.X_op != O_constant)
4465 inst.error = _("constant expression required");
4469 if (exp.X_add_number < min || exp.X_add_number > max)
4471 inst.error = _("immediate value out of range");
4475 *val = exp.X_add_number;
4479 /* Less-generic immediate-value read function with the possibility of loading a
4480 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4481 instructions. Puts the result directly in inst.operands[i]. */
4484 parse_big_immediate (char **str, int i)
4489 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4491 if (exp.X_op == O_constant)
4493 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4494 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4495 O_constant. We have to be careful not to break compilation for
4496 32-bit X_add_number, though. */
4497 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4499 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4500 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4501 inst.operands[i].regisimm = 1;
4504 else if (exp.X_op == O_big
4505 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4507 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4509 /* Bignums have their least significant bits in
4510 generic_bignum[0]. Make sure we put 32 bits in imm and
4511 32 bits in reg, in a (hopefully) portable way. */
4512 gas_assert (parts != 0);
4514 /* Make sure that the number is not too big.
4515 PR 11972: Bignums can now be sign-extended to the
4516 size of a .octa so check that the out of range bits
4517 are all zero or all one. */
4518 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4520 LITTLENUM_TYPE m = -1;
4522 if (generic_bignum[parts * 2] != 0
4523 && generic_bignum[parts * 2] != m)
4526 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4527 if (generic_bignum[j] != generic_bignum[j-1])
4531 inst.operands[i].imm = 0;
4532 for (j = 0; j < parts; j++, idx++)
4533 inst.operands[i].imm |= generic_bignum[idx]
4534 << (LITTLENUM_NUMBER_OF_BITS * j);
4535 inst.operands[i].reg = 0;
4536 for (j = 0; j < parts; j++, idx++)
4537 inst.operands[i].reg |= generic_bignum[idx]
4538 << (LITTLENUM_NUMBER_OF_BITS * j);
4539 inst.operands[i].regisimm = 1;
4549 /* Returns the pseudo-register number of an FPA immediate constant,
4550 or FAIL if there isn't a valid constant here. */
4553 parse_fpa_immediate (char ** str)
4555 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4561 /* First try and match exact strings, this is to guarantee
4562 that some formats will work even for cross assembly. */
4564 for (i = 0; fp_const[i]; i++)
4566 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4570 *str += strlen (fp_const[i]);
4571 if (is_end_of_line[(unsigned char) **str])
4577 /* Just because we didn't get a match doesn't mean that the constant
4578 isn't valid, just that it is in a format that we don't
4579 automatically recognize. Try parsing it with the standard
4580 expression routines. */
4582 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4584 /* Look for a raw floating point number. */
4585 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4586 && is_end_of_line[(unsigned char) *save_in])
4588 for (i = 0; i < NUM_FLOAT_VALS; i++)
4590 for (j = 0; j < MAX_LITTLENUMS; j++)
4592 if (words[j] != fp_values[i][j])
4596 if (j == MAX_LITTLENUMS)
4604 /* Try and parse a more complex expression, this will probably fail
4605 unless the code uses a floating point prefix (eg "0f"). */
4606 save_in = input_line_pointer;
4607 input_line_pointer = *str;
4608 if (expression (&exp) == absolute_section
4609 && exp.X_op == O_big
4610 && exp.X_add_number < 0)
4612 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4614 if (gen_to_words (words, 5, (long) 15) == 0)
4616 for (i = 0; i < NUM_FLOAT_VALS; i++)
4618 for (j = 0; j < MAX_LITTLENUMS; j++)
4620 if (words[j] != fp_values[i][j])
4624 if (j == MAX_LITTLENUMS)
4626 *str = input_line_pointer;
4627 input_line_pointer = save_in;
4634 *str = input_line_pointer;
4635 input_line_pointer = save_in;
4636 inst.error = _("invalid FPA immediate expression");
4640 /* Returns 1 if a number has "quarter-precision" float format
4641 0baBbbbbbc defgh000 00000000 00000000. */
4644 is_quarter_float (unsigned imm)
4646 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4647 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4650 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4651 0baBbbbbbc defgh000 00000000 00000000.
4652 The zero and minus-zero cases need special handling, since they can't be
4653 encoded in the "quarter-precision" float format, but can nonetheless be
4654 loaded as integer constants. */
4657 parse_qfloat_immediate (char **ccp, int *immed)
4661 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4662 int found_fpchar = 0;
4664 skip_past_char (&str, '#');
4666 /* We must not accidentally parse an integer as a floating-point number. Make
4667 sure that the value we parse is not an integer by checking for special
4668 characters '.' or 'e'.
4669 FIXME: This is a horrible hack, but doing better is tricky because type
4670 information isn't in a very usable state at parse time. */
4672 skip_whitespace (fpnum);
4674 if (strncmp (fpnum, "0x", 2) == 0)
4678 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4679 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4689 if ((str = atof_ieee (str, 's', words)) != NULL)
4691 unsigned fpword = 0;
4694 /* Our FP word must be 32 bits (single-precision FP). */
4695 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4697 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4701 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4714 /* Shift operands. */
4717 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4720 struct asm_shift_name
4723 enum shift_kind kind;
4726 /* Third argument to parse_shift. */
4727 enum parse_shift_mode
4729 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4730 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4731 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4732 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4733 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4736 /* Parse a <shift> specifier on an ARM data processing instruction.
4737 This has three forms:
4739 (LSL|LSR|ASL|ASR|ROR) Rs
4740 (LSL|LSR|ASL|ASR|ROR) #imm
4743 Note that ASL is assimilated to LSL in the instruction encoding, and
4744 RRX to ROR #0 (which cannot be written as such). */
4747 parse_shift (char **str, int i, enum parse_shift_mode mode)
4749 const struct asm_shift_name *shift_name;
4750 enum shift_kind shift;
4755 for (p = *str; ISALPHA (*p); p++)
4760 inst.error = _("shift expression expected");
4764 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4767 if (shift_name == NULL)
4769 inst.error = _("shift expression expected");
4773 shift = shift_name->kind;
4777 case NO_SHIFT_RESTRICT:
4778 case SHIFT_IMMEDIATE: break;
4780 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4781 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4783 inst.error = _("'LSL' or 'ASR' required");
4788 case SHIFT_LSL_IMMEDIATE:
4789 if (shift != SHIFT_LSL)
4791 inst.error = _("'LSL' required");
4796 case SHIFT_ASR_IMMEDIATE:
4797 if (shift != SHIFT_ASR)
4799 inst.error = _("'ASR' required");
4807 if (shift != SHIFT_RRX)
4809 /* Whitespace can appear here if the next thing is a bare digit. */
4810 skip_whitespace (p);
4812 if (mode == NO_SHIFT_RESTRICT
4813 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4815 inst.operands[i].imm = reg;
4816 inst.operands[i].immisreg = 1;
4818 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4821 inst.operands[i].shift_kind = shift;
4822 inst.operands[i].shifted = 1;
4827 /* Parse a <shifter_operand> for an ARM data processing instruction:
4830 #<immediate>, <rotate>
4834 where <shift> is defined by parse_shift above, and <rotate> is a
4835 multiple of 2 between 0 and 30. Validation of immediate operands
4836 is deferred to md_apply_fix. */
4839 parse_shifter_operand (char **str, int i)
4844 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].reg = value;
4847 inst.operands[i].isreg = 1;
4849 /* parse_shift will override this if appropriate */
4850 inst.reloc.exp.X_op = O_constant;
4851 inst.reloc.exp.X_add_number = 0;
4853 if (skip_past_comma (str) == FAIL)
4856 /* Shift operation on register. */
4857 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4860 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4863 if (skip_past_comma (str) == SUCCESS)
4865 /* #x, y -- ie explicit rotation by Y. */
4866 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4869 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4871 inst.error = _("constant expression expected");
4875 value = exp.X_add_number;
4876 if (value < 0 || value > 30 || value % 2 != 0)
4878 inst.error = _("invalid rotation");
4881 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4883 inst.error = _("invalid constant");
4887 /* Convert to decoded value. md_apply_fix will put it back. */
4888 inst.reloc.exp.X_add_number
4889 = (((inst.reloc.exp.X_add_number << (32 - value))
4890 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4893 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4894 inst.reloc.pc_rel = 0;
4898 /* Group relocation information. Each entry in the table contains the
4899 textual name of the relocation as may appear in assembler source
4900 and must end with a colon.
4901 Along with this textual name are the relocation codes to be used if
4902 the corresponding instruction is an ALU instruction (ADD or SUB only),
4903 an LDR, an LDRS, or an LDC. */
4905 struct group_reloc_table_entry
4916 /* Varieties of non-ALU group relocation. */
4923 static struct group_reloc_table_entry group_reloc_table[] =
4924 { /* Program counter relative: */
4926 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4931 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4932 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4933 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4934 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4936 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4941 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4942 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4943 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4944 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4946 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4947 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4948 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4949 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4950 /* Section base relative */
4952 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4957 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4958 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4959 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4960 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4962 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4967 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4968 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4969 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4970 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4972 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4973 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4974 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4975 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4977 /* Given the address of a pointer pointing to the textual name of a group
4978 relocation as may appear in assembler source, attempt to find its details
4979 in group_reloc_table. The pointer will be updated to the character after
4980 the trailing colon. On failure, FAIL will be returned; SUCCESS
4981 otherwise. On success, *entry will be updated to point at the relevant
4982 group_reloc_table entry. */
4985 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4988 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4990 int length = strlen (group_reloc_table[i].name);
4992 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4993 && (*str)[length] == ':')
4995 *out = &group_reloc_table[i];
4996 *str += (length + 1);
5004 /* Parse a <shifter_operand> for an ARM data processing instruction
5005 (as for parse_shifter_operand) where group relocations are allowed:
5008 #<immediate>, <rotate>
5009 #:<group_reloc>:<expression>
5013 where <group_reloc> is one of the strings defined in group_reloc_table.
5014 The hashes are optional.
5016 Everything else is as for parse_shifter_operand. */
5018 static parse_operand_result
5019 parse_shifter_operand_group_reloc (char **str, int i)
5021 /* Determine if we have the sequence of characters #: or just :
5022 coming next. If we do, then we check for a group relocation.
5023 If we don't, punt the whole lot to parse_shifter_operand. */
5025 if (((*str)[0] == '#' && (*str)[1] == ':')
5026 || (*str)[0] == ':')
5028 struct group_reloc_table_entry *entry;
5030 if ((*str)[0] == '#')
5035 /* Try to parse a group relocation. Anything else is an error. */
5036 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5038 inst.error = _("unknown group relocation");
5039 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5042 /* We now have the group relocation table entry corresponding to
5043 the name in the assembler source. Next, we parse the expression. */
5044 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5045 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5047 /* Record the relocation type (always the ALU variant here). */
5048 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5049 gas_assert (inst.reloc.type != 0);
5051 return PARSE_OPERAND_SUCCESS;
5054 return parse_shifter_operand (str, i) == SUCCESS
5055 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5057 /* Never reached. */
5060 /* Parse a Neon alignment expression. Information is written to
5061 inst.operands[i]. We assume the initial ':' has been skipped.
5063 align .imm = align << 8, .immisalign=1, .preind=0 */
5064 static parse_operand_result
5065 parse_neon_alignment (char **str, int i)
5070 my_get_expression (&exp, &p, GE_NO_PREFIX);
5072 if (exp.X_op != O_constant)
5074 inst.error = _("alignment must be constant");
5075 return PARSE_OPERAND_FAIL;
5078 inst.operands[i].imm = exp.X_add_number << 8;
5079 inst.operands[i].immisalign = 1;
5080 /* Alignments are not pre-indexes. */
5081 inst.operands[i].preind = 0;
5084 return PARSE_OPERAND_SUCCESS;
5087 /* Parse all forms of an ARM address expression. Information is written
5088 to inst.operands[i] and/or inst.reloc.
5090 Preindexed addressing (.preind=1):
5092 [Rn, #offset] .reg=Rn .reloc.exp=offset
5093 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5094 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5095 .shift_kind=shift .reloc.exp=shift_imm
5097 These three may have a trailing ! which causes .writeback to be set also.
5099 Postindexed addressing (.postind=1, .writeback=1):
5101 [Rn], #offset .reg=Rn .reloc.exp=offset
5102 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5103 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5104 .shift_kind=shift .reloc.exp=shift_imm
5106 Unindexed addressing (.preind=0, .postind=0):
5108 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5112 [Rn]{!} shorthand for [Rn,#0]{!}
5113 =immediate .isreg=0 .reloc.exp=immediate
5114 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5116 It is the caller's responsibility to check for addressing modes not
5117 supported by the instruction, and to set inst.reloc.type. */
5119 static parse_operand_result
5120 parse_address_main (char **str, int i, int group_relocations,
5121 group_reloc_type group_type)
5126 if (skip_past_char (&p, '[') == FAIL)
5128 if (skip_past_char (&p, '=') == FAIL)
5130 /* Bare address - translate to PC-relative offset. */
5131 inst.reloc.pc_rel = 1;
5132 inst.operands[i].reg = REG_PC;
5133 inst.operands[i].isreg = 1;
5134 inst.operands[i].preind = 1;
5136 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5138 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5139 return PARSE_OPERAND_FAIL;
5142 return PARSE_OPERAND_SUCCESS;
5145 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5147 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5148 return PARSE_OPERAND_FAIL;
5150 inst.operands[i].reg = reg;
5151 inst.operands[i].isreg = 1;
5153 if (skip_past_comma (&p) == SUCCESS)
5155 inst.operands[i].preind = 1;
5158 else if (*p == '-') p++, inst.operands[i].negative = 1;
5160 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5162 inst.operands[i].imm = reg;
5163 inst.operands[i].immisreg = 1;
5165 if (skip_past_comma (&p) == SUCCESS)
5166 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5167 return PARSE_OPERAND_FAIL;
5169 else if (skip_past_char (&p, ':') == SUCCESS)
5171 /* FIXME: '@' should be used here, but it's filtered out by generic
5172 code before we get to see it here. This may be subject to
5174 parse_operand_result result = parse_neon_alignment (&p, i);
5176 if (result != PARSE_OPERAND_SUCCESS)
5181 if (inst.operands[i].negative)
5183 inst.operands[i].negative = 0;
5187 if (group_relocations
5188 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5190 struct group_reloc_table_entry *entry;
5192 /* Skip over the #: or : sequence. */
5198 /* Try to parse a group relocation. Anything else is an
5200 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5202 inst.error = _("unknown group relocation");
5203 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5206 /* We now have the group relocation table entry corresponding to
5207 the name in the assembler source. Next, we parse the
5209 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5210 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5212 /* Record the relocation type. */
5216 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5220 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5224 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5231 if (inst.reloc.type == 0)
5233 inst.error = _("this group relocation is not allowed on this instruction");
5234 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5240 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5241 return PARSE_OPERAND_FAIL;
5242 /* If the offset is 0, find out if it's a +0 or -0. */
5243 if (inst.reloc.exp.X_op == O_constant
5244 && inst.reloc.exp.X_add_number == 0)
5246 skip_whitespace (q);
5250 skip_whitespace (q);
5253 inst.operands[i].negative = 1;
5258 else if (skip_past_char (&p, ':') == SUCCESS)
5260 /* FIXME: '@' should be used here, but it's filtered out by generic code
5261 before we get to see it here. This may be subject to change. */
5262 parse_operand_result result = parse_neon_alignment (&p, i);
5264 if (result != PARSE_OPERAND_SUCCESS)
5268 if (skip_past_char (&p, ']') == FAIL)
5270 inst.error = _("']' expected");
5271 return PARSE_OPERAND_FAIL;
5274 if (skip_past_char (&p, '!') == SUCCESS)
5275 inst.operands[i].writeback = 1;
5277 else if (skip_past_comma (&p) == SUCCESS)
5279 if (skip_past_char (&p, '{') == SUCCESS)
5281 /* [Rn], {expr} - unindexed, with option */
5282 if (parse_immediate (&p, &inst.operands[i].imm,
5283 0, 255, TRUE) == FAIL)
5284 return PARSE_OPERAND_FAIL;
5286 if (skip_past_char (&p, '}') == FAIL)
5288 inst.error = _("'}' expected at end of 'option' field");
5289 return PARSE_OPERAND_FAIL;
5291 if (inst.operands[i].preind)
5293 inst.error = _("cannot combine index with option");
5294 return PARSE_OPERAND_FAIL;
5297 return PARSE_OPERAND_SUCCESS;
5301 inst.operands[i].postind = 1;
5302 inst.operands[i].writeback = 1;
5304 if (inst.operands[i].preind)
5306 inst.error = _("cannot combine pre- and post-indexing");
5307 return PARSE_OPERAND_FAIL;
5311 else if (*p == '-') p++, inst.operands[i].negative = 1;
5313 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5315 /* We might be using the immediate for alignment already. If we
5316 are, OR the register number into the low-order bits. */
5317 if (inst.operands[i].immisalign)
5318 inst.operands[i].imm |= reg;
5320 inst.operands[i].imm = reg;
5321 inst.operands[i].immisreg = 1;
5323 if (skip_past_comma (&p) == SUCCESS)
5324 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5325 return PARSE_OPERAND_FAIL;
5330 if (inst.operands[i].negative)
5332 inst.operands[i].negative = 0;
5335 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5336 return PARSE_OPERAND_FAIL;
5337 /* If the offset is 0, find out if it's a +0 or -0. */
5338 if (inst.reloc.exp.X_op == O_constant
5339 && inst.reloc.exp.X_add_number == 0)
5341 skip_whitespace (q);
5345 skip_whitespace (q);
5348 inst.operands[i].negative = 1;
5354 /* If at this point neither .preind nor .postind is set, we have a
5355 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5356 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5358 inst.operands[i].preind = 1;
5359 inst.reloc.exp.X_op = O_constant;
5360 inst.reloc.exp.X_add_number = 0;
5363 return PARSE_OPERAND_SUCCESS;
5367 parse_address (char **str, int i)
5369 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5373 static parse_operand_result
5374 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5376 return parse_address_main (str, i, 1, type);
5379 /* Parse an operand for a MOVW or MOVT instruction. */
5381 parse_half (char **str)
5386 skip_past_char (&p, '#');
5387 if (strncasecmp (p, ":lower16:", 9) == 0)
5388 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5389 else if (strncasecmp (p, ":upper16:", 9) == 0)
5390 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5392 if (inst.reloc.type != BFD_RELOC_UNUSED)
5395 skip_whitespace (p);
5398 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5401 if (inst.reloc.type == BFD_RELOC_UNUSED)
5403 if (inst.reloc.exp.X_op != O_constant)
5405 inst.error = _("constant expression expected");
5408 if (inst.reloc.exp.X_add_number < 0
5409 || inst.reloc.exp.X_add_number > 0xffff)
5411 inst.error = _("immediate value out of range");
5419 /* Miscellaneous. */
5421 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5422 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5424 parse_psr (char **str, bfd_boolean lhs)
5427 unsigned long psr_field;
5428 const struct asm_psr *psr;
5430 bfd_boolean is_apsr = FALSE;
5431 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5433 /* PR gas/12698: If the user has specified -march=all then m_profile will
5434 be TRUE, but we want to ignore it in this case as we are building for any
5435 CPU type, including non-m variants. */
5436 if (selected_cpu.core == arm_arch_any.core)
5439 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5440 feature for ease of use and backwards compatibility. */
5442 if (strncasecmp (p, "SPSR", 4) == 0)
5445 goto unsupported_psr;
5447 psr_field = SPSR_BIT;
5449 else if (strncasecmp (p, "CPSR", 4) == 0)
5452 goto unsupported_psr;
5456 else if (strncasecmp (p, "APSR", 4) == 0)
5458 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5459 and ARMv7-R architecture CPUs. */
5468 while (ISALNUM (*p) || *p == '_');
5470 if (strncasecmp (start, "iapsr", 5) == 0
5471 || strncasecmp (start, "eapsr", 5) == 0
5472 || strncasecmp (start, "xpsr", 4) == 0
5473 || strncasecmp (start, "psr", 3) == 0)
5474 p = start + strcspn (start, "rR") + 1;
5476 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5482 /* If APSR is being written, a bitfield may be specified. Note that
5483 APSR itself is handled above. */
5484 if (psr->field <= 3)
5486 psr_field = psr->field;
5492 /* M-profile MSR instructions have the mask field set to "10", except
5493 *PSR variants which modify APSR, which may use a different mask (and
5494 have been handled already). Do that by setting the PSR_f field
5496 return psr->field | (lhs ? PSR_f : 0);
5499 goto unsupported_psr;
5505 /* A suffix follows. */
5511 while (ISALNUM (*p) || *p == '_');
5515 /* APSR uses a notation for bits, rather than fields. */
5516 unsigned int nzcvq_bits = 0;
5517 unsigned int g_bit = 0;
5520 for (bit = start; bit != p; bit++)
5522 switch (TOLOWER (*bit))
5525 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5529 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5533 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5537 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5541 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5545 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5549 inst.error = _("unexpected bit specified after APSR");
5554 if (nzcvq_bits == 0x1f)
5559 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5561 inst.error = _("selected processor does not "
5562 "support DSP extension");
5569 if ((nzcvq_bits & 0x20) != 0
5570 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5571 || (g_bit & 0x2) != 0)
5573 inst.error = _("bad bitmask specified after APSR");
5579 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5584 psr_field |= psr->field;
5590 goto error; /* Garbage after "[CS]PSR". */
5592 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5593 is deprecated, but allow it anyway. */
5597 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5600 else if (!m_profile)
5601 /* These bits are never right for M-profile devices: don't set them
5602 (only code paths which read/write APSR reach here). */
5603 psr_field |= (PSR_c | PSR_f);
5609 inst.error = _("selected processor does not support requested special "
5610 "purpose register");
5614 inst.error = _("flag for {c}psr instruction expected");
5618 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5619 value suitable for splatting into the AIF field of the instruction. */
5622 parse_cps_flags (char **str)
5631 case '\0': case ',':
5634 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5635 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5636 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5639 inst.error = _("unrecognized CPS flag");
5644 if (saw_a_flag == 0)
5646 inst.error = _("missing CPS flags");
5654 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5655 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5658 parse_endian_specifier (char **str)
5663 if (strncasecmp (s, "BE", 2))
5665 else if (strncasecmp (s, "LE", 2))
5669 inst.error = _("valid endian specifiers are be or le");
5673 if (ISALNUM (s[2]) || s[2] == '_')
5675 inst.error = _("valid endian specifiers are be or le");
5680 return little_endian;
5683 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5684 value suitable for poking into the rotate field of an sxt or sxta
5685 instruction, or FAIL on error. */
5688 parse_ror (char **str)
5693 if (strncasecmp (s, "ROR", 3) == 0)
5697 inst.error = _("missing rotation field after comma");
5701 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5706 case 0: *str = s; return 0x0;
5707 case 8: *str = s; return 0x1;
5708 case 16: *str = s; return 0x2;
5709 case 24: *str = s; return 0x3;
5712 inst.error = _("rotation can only be 0, 8, 16, or 24");
5717 /* Parse a conditional code (from conds[] below). The value returned is in the
5718 range 0 .. 14, or FAIL. */
5720 parse_cond (char **str)
5723 const struct asm_cond *c;
5725 /* Condition codes are always 2 characters, so matching up to
5726 3 characters is sufficient. */
5731 while (ISALPHA (*q) && n < 3)
5733 cond[n] = TOLOWER (*q);
5738 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5741 inst.error = _("condition required");
5749 /* Parse an option for a barrier instruction. Returns the encoding for the
5752 parse_barrier (char **str)
5755 const struct asm_barrier_opt *o;
5758 while (ISALPHA (*q))
5761 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5770 /* Parse the operands of a table branch instruction. Similar to a memory
5773 parse_tb (char **str)
5778 if (skip_past_char (&p, '[') == FAIL)
5780 inst.error = _("'[' expected");
5784 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5786 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5789 inst.operands[0].reg = reg;
5791 if (skip_past_comma (&p) == FAIL)
5793 inst.error = _("',' expected");
5797 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5802 inst.operands[0].imm = reg;
5804 if (skip_past_comma (&p) == SUCCESS)
5806 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5808 if (inst.reloc.exp.X_add_number != 1)
5810 inst.error = _("invalid shift");
5813 inst.operands[0].shifted = 1;
5816 if (skip_past_char (&p, ']') == FAIL)
5818 inst.error = _("']' expected");
5825 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5826 information on the types the operands can take and how they are encoded.
5827 Up to four operands may be read; this function handles setting the
5828 ".present" field for each read operand itself.
5829 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5830 else returns FAIL. */
5833 parse_neon_mov (char **str, int *which_operand)
5835 int i = *which_operand, val;
5836 enum arm_reg_type rtype;
5838 struct neon_type_el optype;
5840 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5842 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5843 inst.operands[i].reg = val;
5844 inst.operands[i].isscalar = 1;
5845 inst.operands[i].vectype = optype;
5846 inst.operands[i++].present = 1;
5848 if (skip_past_comma (&ptr) == FAIL)
5851 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5854 inst.operands[i].reg = val;
5855 inst.operands[i].isreg = 1;
5856 inst.operands[i].present = 1;
5858 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5861 /* Cases 0, 1, 2, 3, 5 (D only). */
5862 if (skip_past_comma (&ptr) == FAIL)
5865 inst.operands[i].reg = val;
5866 inst.operands[i].isreg = 1;
5867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5869 inst.operands[i].isvec = 1;
5870 inst.operands[i].vectype = optype;
5871 inst.operands[i++].present = 1;
5873 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5875 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5876 Case 13: VMOV <Sd>, <Rm> */
5877 inst.operands[i].reg = val;
5878 inst.operands[i].isreg = 1;
5879 inst.operands[i].present = 1;
5881 if (rtype == REG_TYPE_NQ)
5883 first_error (_("can't use Neon quad register here"));
5886 else if (rtype != REG_TYPE_VFS)
5889 if (skip_past_comma (&ptr) == FAIL)
5891 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5893 inst.operands[i].reg = val;
5894 inst.operands[i].isreg = 1;
5895 inst.operands[i].present = 1;
5898 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5901 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5902 Case 1: VMOV<c><q> <Dd>, <Dm>
5903 Case 8: VMOV.F32 <Sd>, <Sm>
5904 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5906 inst.operands[i].reg = val;
5907 inst.operands[i].isreg = 1;
5908 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5909 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5910 inst.operands[i].isvec = 1;
5911 inst.operands[i].vectype = optype;
5912 inst.operands[i].present = 1;
5914 if (skip_past_comma (&ptr) == SUCCESS)
5919 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5922 inst.operands[i].reg = val;
5923 inst.operands[i].isreg = 1;
5924 inst.operands[i++].present = 1;
5926 if (skip_past_comma (&ptr) == FAIL)
5929 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i++].present = 1;
5937 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5938 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5939 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5940 Case 10: VMOV.F32 <Sd>, #<imm>
5941 Case 11: VMOV.F64 <Dd>, #<imm> */
5942 inst.operands[i].immisfloat = 1;
5943 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5944 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5945 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5949 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5953 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5956 inst.operands[i].reg = val;
5957 inst.operands[i].isreg = 1;
5958 inst.operands[i++].present = 1;
5960 if (skip_past_comma (&ptr) == FAIL)
5963 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5965 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5966 inst.operands[i].reg = val;
5967 inst.operands[i].isscalar = 1;
5968 inst.operands[i].present = 1;
5969 inst.operands[i].vectype = optype;
5971 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5973 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5974 inst.operands[i].reg = val;
5975 inst.operands[i].isreg = 1;
5976 inst.operands[i++].present = 1;
5978 if (skip_past_comma (&ptr) == FAIL)
5981 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5984 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5988 inst.operands[i].reg = val;
5989 inst.operands[i].isreg = 1;
5990 inst.operands[i].isvec = 1;
5991 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5992 inst.operands[i].vectype = optype;
5993 inst.operands[i].present = 1;
5995 if (rtype == REG_TYPE_VFS)
5999 if (skip_past_comma (&ptr) == FAIL)
6001 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6004 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6007 inst.operands[i].reg = val;
6008 inst.operands[i].isreg = 1;
6009 inst.operands[i].isvec = 1;
6010 inst.operands[i].issingle = 1;
6011 inst.operands[i].vectype = optype;
6012 inst.operands[i].present = 1;
6015 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6019 inst.operands[i].reg = val;
6020 inst.operands[i].isreg = 1;
6021 inst.operands[i].isvec = 1;
6022 inst.operands[i].issingle = 1;
6023 inst.operands[i].vectype = optype;
6024 inst.operands[i++].present = 1;
6029 first_error (_("parse error"));
6033 /* Successfully parsed the operands. Update args. */
6039 first_error (_("expected comma"));
6043 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6047 /* Use this macro when the operand constraints are different
6048 for ARM and THUMB (e.g. ldrd). */
6049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6050 ((arm_operand) | ((thumb_operand) << 16))
6052 /* Matcher codes for parse_operands. */
6053 enum operand_parse_code
6055 OP_stop, /* end of line */
6057 OP_RR, /* ARM register */
6058 OP_RRnpc, /* ARM register, not r15 */
6059 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6060 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6061 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6062 optional trailing ! */
6063 OP_RRw, /* ARM register, not r15, optional trailing ! */
6064 OP_RCP, /* Coprocessor number */
6065 OP_RCN, /* Coprocessor register */
6066 OP_RF, /* FPA register */
6067 OP_RVS, /* VFP single precision register */
6068 OP_RVD, /* VFP double precision register (0..15) */
6069 OP_RND, /* Neon double precision register (0..31) */
6070 OP_RNQ, /* Neon quad precision register */
6071 OP_RVSD, /* VFP single or double precision register */
6072 OP_RNDQ, /* Neon double or quad precision register */
6073 OP_RNSDQ, /* Neon single, double or quad precision register */
6074 OP_RNSC, /* Neon scalar D[X] */
6075 OP_RVC, /* VFP control register */
6076 OP_RMF, /* Maverick F register */
6077 OP_RMD, /* Maverick D register */
6078 OP_RMFX, /* Maverick FX register */
6079 OP_RMDX, /* Maverick DX register */
6080 OP_RMAX, /* Maverick AX register */
6081 OP_RMDS, /* Maverick DSPSC register */
6082 OP_RIWR, /* iWMMXt wR register */
6083 OP_RIWC, /* iWMMXt wC register */
6084 OP_RIWG, /* iWMMXt wCG register */
6085 OP_RXA, /* XScale accumulator register */
6087 OP_REGLST, /* ARM register list */
6088 OP_VRSLST, /* VFP single-precision register list */
6089 OP_VRDLST, /* VFP double-precision register list */
6090 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6091 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6092 OP_NSTRLST, /* Neon element/structure list */
6094 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6095 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6096 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6097 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6098 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6099 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6100 OP_VMOV, /* Neon VMOV operands. */
6101 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6102 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6103 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6105 OP_I0, /* immediate zero */
6106 OP_I7, /* immediate value 0 .. 7 */
6107 OP_I15, /* 0 .. 15 */
6108 OP_I16, /* 1 .. 16 */
6109 OP_I16z, /* 0 .. 16 */
6110 OP_I31, /* 0 .. 31 */
6111 OP_I31w, /* 0 .. 31, optional trailing ! */
6112 OP_I32, /* 1 .. 32 */
6113 OP_I32z, /* 0 .. 32 */
6114 OP_I63, /* 0 .. 63 */
6115 OP_I63s, /* -64 .. 63 */
6116 OP_I64, /* 1 .. 64 */
6117 OP_I64z, /* 0 .. 64 */
6118 OP_I255, /* 0 .. 255 */
6120 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6121 OP_I7b, /* 0 .. 7 */
6122 OP_I15b, /* 0 .. 15 */
6123 OP_I31b, /* 0 .. 31 */
6125 OP_SH, /* shifter operand */
6126 OP_SHG, /* shifter operand with possible group relocation */
6127 OP_ADDR, /* Memory address expression (any mode) */
6128 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6129 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6130 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6131 OP_EXP, /* arbitrary expression */
6132 OP_EXPi, /* same, with optional immediate prefix */
6133 OP_EXPr, /* same, with optional relocation suffix */
6134 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6136 OP_CPSF, /* CPS flags */
6137 OP_ENDI, /* Endianness specifier */
6138 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6139 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6140 OP_COND, /* conditional code */
6141 OP_TB, /* Table branch. */
6143 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6145 OP_RRnpc_I0, /* ARM register or literal 0 */
6146 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6147 OP_RR_EXi, /* ARM register or expression with imm prefix */
6148 OP_RF_IF, /* FPA register or immediate */
6149 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6150 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6152 /* Optional operands. */
6153 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6154 OP_oI31b, /* 0 .. 31 */
6155 OP_oI32b, /* 1 .. 32 */
6156 OP_oI32z, /* 0 .. 32 */
6157 OP_oIffffb, /* 0 .. 65535 */
6158 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6160 OP_oRR, /* ARM register */
6161 OP_oRRnpc, /* ARM register, not the PC */
6162 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6163 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6164 OP_oRND, /* Optional Neon double precision register */
6165 OP_oRNQ, /* Optional Neon quad precision register */
6166 OP_oRNDQ, /* Optional Neon double or quad precision register */
6167 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6168 OP_oSHll, /* LSL immediate */
6169 OP_oSHar, /* ASR immediate */
6170 OP_oSHllar, /* LSL or ASR immediate */
6171 OP_oROR, /* ROR 0/8/16/24 */
6172 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6174 /* Some pre-defined mixed (ARM/THUMB) operands. */
6175 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6176 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6177 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6179 OP_FIRST_OPTIONAL = OP_oI7b
6182 /* Generic instruction operand parser. This does no encoding and no
6183 semantic validation; it merely squirrels values away in the inst
6184 structure. Returns SUCCESS or FAIL depending on whether the
6185 specified grammar matched. */
6187 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6189 unsigned const int *upat = pattern;
6190 char *backtrack_pos = 0;
6191 const char *backtrack_error = 0;
6192 int i, val, backtrack_index = 0;
6193 enum arm_reg_type rtype;
6194 parse_operand_result result;
6195 unsigned int op_parse_code;
6197 #define po_char_or_fail(chr) \
6200 if (skip_past_char (&str, chr) == FAIL) \
6205 #define po_reg_or_fail(regtype) \
6208 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6209 & inst.operands[i].vectype); \
6212 first_error (_(reg_expected_msgs[regtype])); \
6215 inst.operands[i].reg = val; \
6216 inst.operands[i].isreg = 1; \
6217 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6218 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6219 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6220 || rtype == REG_TYPE_VFD \
6221 || rtype == REG_TYPE_NQ); \
6225 #define po_reg_or_goto(regtype, label) \
6228 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6229 & inst.operands[i].vectype); \
6233 inst.operands[i].reg = val; \
6234 inst.operands[i].isreg = 1; \
6235 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6236 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6237 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6238 || rtype == REG_TYPE_VFD \
6239 || rtype == REG_TYPE_NQ); \
6243 #define po_imm_or_fail(min, max, popt) \
6246 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6248 inst.operands[i].imm = val; \
6252 #define po_scalar_or_goto(elsz, label) \
6255 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isscalar = 1; \
6263 #define po_misc_or_fail(expr) \
6271 #define po_misc_or_fail_no_backtrack(expr) \
6275 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6276 backtrack_pos = 0; \
6277 if (result != PARSE_OPERAND_SUCCESS) \
6282 #define po_barrier_or_imm(str) \
6285 val = parse_barrier (&str); \
6288 if (ISALPHA (*str)) \
6295 if ((inst.instruction & 0xf0) == 0x60 \
6298 /* ISB can only take SY as an option. */ \
6299 inst.error = _("invalid barrier type"); \
6306 skip_whitespace (str);
6308 for (i = 0; upat[i] != OP_stop; i++)
6310 op_parse_code = upat[i];
6311 if (op_parse_code >= 1<<16)
6312 op_parse_code = thumb ? (op_parse_code >> 16)
6313 : (op_parse_code & ((1<<16)-1));
6315 if (op_parse_code >= OP_FIRST_OPTIONAL)
6317 /* Remember where we are in case we need to backtrack. */
6318 gas_assert (!backtrack_pos);
6319 backtrack_pos = str;
6320 backtrack_error = inst.error;
6321 backtrack_index = i;
6324 if (i > 0 && (i > 1 || inst.operands[0].present))
6325 po_char_or_fail (',');
6327 switch (op_parse_code)
6335 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6336 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6337 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6338 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6339 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6340 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6342 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6344 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6346 /* Also accept generic coprocessor regs for unknown registers. */
6348 po_reg_or_fail (REG_TYPE_CN);
6350 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6351 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6352 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6353 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6354 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6355 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6356 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6357 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6358 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6359 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6361 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6363 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6364 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6366 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6368 /* Neon scalar. Using an element size of 8 means that some invalid
6369 scalars are accepted here, so deal with those in later code. */
6370 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6374 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6377 po_imm_or_fail (0, 0, TRUE);
6382 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6387 po_scalar_or_goto (8, try_rr);
6390 po_reg_or_fail (REG_TYPE_RN);
6396 po_scalar_or_goto (8, try_nsdq);
6399 po_reg_or_fail (REG_TYPE_NSDQ);
6405 po_scalar_or_goto (8, try_ndq);
6408 po_reg_or_fail (REG_TYPE_NDQ);
6414 po_scalar_or_goto (8, try_vfd);
6417 po_reg_or_fail (REG_TYPE_VFD);
6422 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6423 not careful then bad things might happen. */
6424 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6429 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6432 /* There's a possibility of getting a 64-bit immediate here, so
6433 we need special handling. */
6434 if (parse_big_immediate (&str, i) == FAIL)
6436 inst.error = _("immediate value is out of range");
6444 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6447 po_imm_or_fail (0, 63, TRUE);
6452 po_char_or_fail ('[');
6453 po_reg_or_fail (REG_TYPE_RN);
6454 po_char_or_fail (']');
6460 po_reg_or_fail (REG_TYPE_RN);
6461 if (skip_past_char (&str, '!') == SUCCESS)
6462 inst.operands[i].writeback = 1;
6466 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6467 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6468 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6469 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6470 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6471 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6472 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6473 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6474 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6475 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6476 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6477 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6479 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6481 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6482 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6484 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6485 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6486 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6487 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6489 /* Immediate variants */
6491 po_char_or_fail ('{');
6492 po_imm_or_fail (0, 255, TRUE);
6493 po_char_or_fail ('}');
6497 /* The expression parser chokes on a trailing !, so we have
6498 to find it first and zap it. */
6501 while (*s && *s != ',')
6506 inst.operands[i].writeback = 1;
6508 po_imm_or_fail (0, 31, TRUE);
6516 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6521 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6526 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6528 if (inst.reloc.exp.X_op == O_symbol)
6530 val = parse_reloc (&str);
6533 inst.error = _("unrecognized relocation suffix");
6536 else if (val != BFD_RELOC_UNUSED)
6538 inst.operands[i].imm = val;
6539 inst.operands[i].hasreloc = 1;
6544 /* Operand for MOVW or MOVT. */
6546 po_misc_or_fail (parse_half (&str));
6549 /* Register or expression. */
6550 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6551 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6553 /* Register or immediate. */
6554 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6555 I0: po_imm_or_fail (0, 0, FALSE); break;
6557 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6559 if (!is_immediate_prefix (*str))
6562 val = parse_fpa_immediate (&str);
6565 /* FPA immediates are encoded as registers 8-15.
6566 parse_fpa_immediate has already applied the offset. */
6567 inst.operands[i].reg = val;
6568 inst.operands[i].isreg = 1;
6571 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6572 I32z: po_imm_or_fail (0, 32, FALSE); break;
6574 /* Two kinds of register. */
6577 struct reg_entry *rege = arm_reg_parse_multi (&str);
6579 || (rege->type != REG_TYPE_MMXWR
6580 && rege->type != REG_TYPE_MMXWC
6581 && rege->type != REG_TYPE_MMXWCG))
6583 inst.error = _("iWMMXt data or control register expected");
6586 inst.operands[i].reg = rege->number;
6587 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6593 struct reg_entry *rege = arm_reg_parse_multi (&str);
6595 || (rege->type != REG_TYPE_MMXWC
6596 && rege->type != REG_TYPE_MMXWCG))
6598 inst.error = _("iWMMXt control register expected");
6601 inst.operands[i].reg = rege->number;
6602 inst.operands[i].isreg = 1;
6607 case OP_CPSF: val = parse_cps_flags (&str); break;
6608 case OP_ENDI: val = parse_endian_specifier (&str); break;
6609 case OP_oROR: val = parse_ror (&str); break;
6610 case OP_COND: val = parse_cond (&str); break;
6611 case OP_oBARRIER_I15:
6612 po_barrier_or_imm (str); break;
6614 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6620 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6621 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6623 inst.error = _("Banked registers are not available with this "
6629 val = parse_psr (&str, op_parse_code == OP_wPSR);
6633 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6636 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6638 if (strncasecmp (str, "APSR_", 5) == 0)
6645 case 'c': found = (found & 1) ? 16 : found | 1; break;
6646 case 'n': found = (found & 2) ? 16 : found | 2; break;
6647 case 'z': found = (found & 4) ? 16 : found | 4; break;
6648 case 'v': found = (found & 8) ? 16 : found | 8; break;
6649 default: found = 16;
6653 inst.operands[i].isvec = 1;
6654 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6655 inst.operands[i].reg = REG_PC;
6662 po_misc_or_fail (parse_tb (&str));
6665 /* Register lists. */
6667 val = parse_reg_list (&str);
6670 inst.operands[1].writeback = 1;
6676 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6680 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6684 /* Allow Q registers too. */
6685 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6690 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6692 inst.operands[i].issingle = 1;
6697 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6702 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6703 &inst.operands[i].vectype);
6706 /* Addressing modes */
6708 po_misc_or_fail (parse_address (&str, i));
6712 po_misc_or_fail_no_backtrack (
6713 parse_address_group_reloc (&str, i, GROUP_LDR));
6717 po_misc_or_fail_no_backtrack (
6718 parse_address_group_reloc (&str, i, GROUP_LDRS));
6722 po_misc_or_fail_no_backtrack (
6723 parse_address_group_reloc (&str, i, GROUP_LDC));
6727 po_misc_or_fail (parse_shifter_operand (&str, i));
6731 po_misc_or_fail_no_backtrack (
6732 parse_shifter_operand_group_reloc (&str, i));
6736 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6740 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6744 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6748 as_fatal (_("unhandled operand code %d"), op_parse_code);
6751 /* Various value-based sanity checks and shared operations. We
6752 do not signal immediate failures for the register constraints;
6753 this allows a syntax error to take precedence. */
6754 switch (op_parse_code)
6762 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6763 inst.error = BAD_PC;
6768 if (inst.operands[i].isreg)
6770 if (inst.operands[i].reg == REG_PC)
6771 inst.error = BAD_PC;
6772 else if (inst.operands[i].reg == REG_SP)
6773 inst.error = BAD_SP;
6778 if (inst.operands[i].isreg
6779 && inst.operands[i].reg == REG_PC
6780 && (inst.operands[i].writeback || thumb))
6781 inst.error = BAD_PC;
6790 case OP_oBARRIER_I15:
6799 inst.operands[i].imm = val;
6806 /* If we get here, this operand was successfully parsed. */
6807 inst.operands[i].present = 1;
6811 inst.error = BAD_ARGS;
6816 /* The parse routine should already have set inst.error, but set a
6817 default here just in case. */
6819 inst.error = _("syntax error");
6823 /* Do not backtrack over a trailing optional argument that
6824 absorbed some text. We will only fail again, with the
6825 'garbage following instruction' error message, which is
6826 probably less helpful than the current one. */
6827 if (backtrack_index == i && backtrack_pos != str
6828 && upat[i+1] == OP_stop)
6831 inst.error = _("syntax error");
6835 /* Try again, skipping the optional argument at backtrack_pos. */
6836 str = backtrack_pos;
6837 inst.error = backtrack_error;
6838 inst.operands[backtrack_index].present = 0;
6839 i = backtrack_index;
6843 /* Check that we have parsed all the arguments. */
6844 if (*str != '\0' && !inst.error)
6845 inst.error = _("garbage following instruction");
6847 return inst.error ? FAIL : SUCCESS;
6850 #undef po_char_or_fail
6851 #undef po_reg_or_fail
6852 #undef po_reg_or_goto
6853 #undef po_imm_or_fail
6854 #undef po_scalar_or_fail
6855 #undef po_barrier_or_imm
6857 /* Shorthand macro for instruction encoding functions issuing errors. */
6858 #define constraint(expr, err) \
6869 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6870 instructions are unpredictable if these registers are used. This
6871 is the BadReg predicate in ARM's Thumb-2 documentation. */
6872 #define reject_bad_reg(reg) \
6874 if (reg == REG_SP || reg == REG_PC) \
6876 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6881 /* If REG is R13 (the stack pointer), warn that its use is
6883 #define warn_deprecated_sp(reg) \
6885 if (warn_on_deprecated && reg == REG_SP) \
6886 as_warn (_("use of r13 is deprecated")); \
6889 /* Functions for operand encoding. ARM, then Thumb. */
6891 #define rotate_left(v, n) (v << n | v >> (32 - n))
6893 /* If VAL can be encoded in the immediate field of an ARM instruction,
6894 return the encoded form. Otherwise, return FAIL. */
6897 encode_arm_immediate (unsigned int val)
6901 for (i = 0; i < 32; i += 2)
6902 if ((a = rotate_left (val, i)) <= 0xff)
6903 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6908 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6909 return the encoded form. Otherwise, return FAIL. */
6911 encode_thumb32_immediate (unsigned int val)
6918 for (i = 1; i <= 24; i++)
6921 if ((val & ~(0xff << i)) == 0)
6922 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6926 if (val == ((a << 16) | a))
6928 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6932 if (val == ((a << 16) | a))
6933 return 0x200 | (a >> 8);
6937 /* Encode a VFP SP or DP register number into inst.instruction. */
6940 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6942 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6945 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6948 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6951 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6956 first_error (_("D register out of range for selected VFP version"));
6964 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6968 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6972 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6976 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6980 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6984 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6992 /* Encode a <shift> in an ARM-format instruction. The immediate,
6993 if any, is handled by md_apply_fix. */
6995 encode_arm_shift (int i)
6997 if (inst.operands[i].shift_kind == SHIFT_RRX)
6998 inst.instruction |= SHIFT_ROR << 5;
7001 inst.instruction |= inst.operands[i].shift_kind << 5;
7002 if (inst.operands[i].immisreg)
7004 inst.instruction |= SHIFT_BY_REG;
7005 inst.instruction |= inst.operands[i].imm << 8;
7008 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7013 encode_arm_shifter_operand (int i)
7015 if (inst.operands[i].isreg)
7017 inst.instruction |= inst.operands[i].reg;
7018 encode_arm_shift (i);
7021 inst.instruction |= INST_IMMEDIATE;
7024 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7026 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7028 gas_assert (inst.operands[i].isreg);
7029 inst.instruction |= inst.operands[i].reg << 16;
7031 if (inst.operands[i].preind)
7035 inst.error = _("instruction does not accept preindexed addressing");
7038 inst.instruction |= PRE_INDEX;
7039 if (inst.operands[i].writeback)
7040 inst.instruction |= WRITE_BACK;
7043 else if (inst.operands[i].postind)
7045 gas_assert (inst.operands[i].writeback);
7047 inst.instruction |= WRITE_BACK;
7049 else /* unindexed - only for coprocessor */
7051 inst.error = _("instruction does not accept unindexed addressing");
7055 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7056 && (((inst.instruction & 0x000f0000) >> 16)
7057 == ((inst.instruction & 0x0000f000) >> 12)))
7058 as_warn ((inst.instruction & LOAD_BIT)
7059 ? _("destination register same as write-back base")
7060 : _("source register same as write-back base"));
7063 /* inst.operands[i] was set up by parse_address. Encode it into an
7064 ARM-format mode 2 load or store instruction. If is_t is true,
7065 reject forms that cannot be used with a T instruction (i.e. not
7068 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7070 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7072 encode_arm_addr_mode_common (i, is_t);
7074 if (inst.operands[i].immisreg)
7076 constraint ((inst.operands[i].imm == REG_PC
7077 || (is_pc && inst.operands[i].writeback)),
7079 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7080 inst.instruction |= inst.operands[i].imm;
7081 if (!inst.operands[i].negative)
7082 inst.instruction |= INDEX_UP;
7083 if (inst.operands[i].shifted)
7085 if (inst.operands[i].shift_kind == SHIFT_RRX)
7086 inst.instruction |= SHIFT_ROR << 5;
7089 inst.instruction |= inst.operands[i].shift_kind << 5;
7090 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7094 else /* immediate offset in inst.reloc */
7096 if (is_pc && !inst.reloc.pc_rel)
7098 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7100 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7101 cannot use PC in addressing.
7102 PC cannot be used in writeback addressing, either. */
7103 constraint ((is_t || inst.operands[i].writeback),
7106 /* Use of PC in str is deprecated for ARMv7. */
7107 if (warn_on_deprecated
7109 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7110 as_warn (_("use of PC in this instruction is deprecated"));
7113 if (inst.reloc.type == BFD_RELOC_UNUSED)
7115 /* Prefer + for zero encoded value. */
7116 if (!inst.operands[i].negative)
7117 inst.instruction |= INDEX_UP;
7118 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7123 /* inst.operands[i] was set up by parse_address. Encode it into an
7124 ARM-format mode 3 load or store instruction. Reject forms that
7125 cannot be used with such instructions. If is_t is true, reject
7126 forms that cannot be used with a T instruction (i.e. not
7129 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7131 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7133 inst.error = _("instruction does not accept scaled register index");
7137 encode_arm_addr_mode_common (i, is_t);
7139 if (inst.operands[i].immisreg)
7141 constraint ((inst.operands[i].imm == REG_PC
7142 || inst.operands[i].reg == REG_PC),
7144 inst.instruction |= inst.operands[i].imm;
7145 if (!inst.operands[i].negative)
7146 inst.instruction |= INDEX_UP;
7148 else /* immediate offset in inst.reloc */
7150 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7151 && inst.operands[i].writeback),
7153 inst.instruction |= HWOFFSET_IMM;
7154 if (inst.reloc.type == BFD_RELOC_UNUSED)
7156 /* Prefer + for zero encoded value. */
7157 if (!inst.operands[i].negative)
7158 inst.instruction |= INDEX_UP;
7160 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7165 /* inst.operands[i] was set up by parse_address. Encode it into an
7166 ARM-format instruction. Reject all forms which cannot be encoded
7167 into a coprocessor load/store instruction. If wb_ok is false,
7168 reject use of writeback; if unind_ok is false, reject use of
7169 unindexed addressing. If reloc_override is not 0, use it instead
7170 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7171 (in which case it is preserved). */
7174 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7176 inst.instruction |= inst.operands[i].reg << 16;
7178 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7180 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7182 gas_assert (!inst.operands[i].writeback);
7185 inst.error = _("instruction does not support unindexed addressing");
7188 inst.instruction |= inst.operands[i].imm;
7189 inst.instruction |= INDEX_UP;
7193 if (inst.operands[i].preind)
7194 inst.instruction |= PRE_INDEX;
7196 if (inst.operands[i].writeback)
7198 if (inst.operands[i].reg == REG_PC)
7200 inst.error = _("pc may not be used with write-back");
7205 inst.error = _("instruction does not support writeback");
7208 inst.instruction |= WRITE_BACK;
7212 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7213 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7214 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7215 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7218 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7220 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7223 /* Prefer + for zero encoded value. */
7224 if (!inst.operands[i].negative)
7225 inst.instruction |= INDEX_UP;
7230 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7231 Determine whether it can be performed with a move instruction; if
7232 it can, convert inst.instruction to that move instruction and
7233 return TRUE; if it can't, convert inst.instruction to a literal-pool
7234 load and return FALSE. If this is not a valid thing to do in the
7235 current context, set inst.error and return TRUE.
7237 inst.operands[i] describes the destination register. */
7240 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7245 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7249 if ((inst.instruction & tbit) == 0)
7251 inst.error = _("invalid pseudo operation");
7254 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7256 inst.error = _("constant expression expected");
7259 if (inst.reloc.exp.X_op == O_constant)
7263 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7265 /* This can be done with a mov(1) instruction. */
7266 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7267 inst.instruction |= inst.reloc.exp.X_add_number;
7273 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7276 /* This can be done with a mov instruction. */
7277 inst.instruction &= LITERAL_MASK;
7278 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7279 inst.instruction |= value & 0xfff;
7283 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7286 /* This can be done with a mvn instruction. */
7287 inst.instruction &= LITERAL_MASK;
7288 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7289 inst.instruction |= value & 0xfff;
7295 if (add_to_lit_pool () == FAIL)
7297 inst.error = _("literal pool insertion failed");
7300 inst.operands[1].reg = REG_PC;
7301 inst.operands[1].isreg = 1;
7302 inst.operands[1].preind = 1;
7303 inst.reloc.pc_rel = 1;
7304 inst.reloc.type = (thumb_p
7305 ? BFD_RELOC_ARM_THUMB_OFFSET
7307 ? BFD_RELOC_ARM_HWLITERAL
7308 : BFD_RELOC_ARM_LITERAL));
7312 /* Functions for instruction encoding, sorted by sub-architecture.
7313 First some generics; their names are taken from the conventional
7314 bit positions for register arguments in ARM format instructions. */
7324 inst.instruction |= inst.operands[0].reg << 12;
7330 inst.instruction |= inst.operands[0].reg << 12;
7331 inst.instruction |= inst.operands[1].reg;
7337 inst.instruction |= inst.operands[0].reg << 12;
7338 inst.instruction |= inst.operands[1].reg << 16;
7344 inst.instruction |= inst.operands[0].reg << 16;
7345 inst.instruction |= inst.operands[1].reg << 12;
7351 unsigned Rn = inst.operands[2].reg;
7352 /* Enforce restrictions on SWP instruction. */
7353 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7355 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7356 _("Rn must not overlap other operands"));
7358 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7359 if (warn_on_deprecated
7360 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7361 as_warn (_("swp{b} use is deprecated for this architecture"));
7364 inst.instruction |= inst.operands[0].reg << 12;
7365 inst.instruction |= inst.operands[1].reg;
7366 inst.instruction |= Rn << 16;
7372 inst.instruction |= inst.operands[0].reg << 12;
7373 inst.instruction |= inst.operands[1].reg << 16;
7374 inst.instruction |= inst.operands[2].reg;
7380 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7381 constraint (((inst.reloc.exp.X_op != O_constant
7382 && inst.reloc.exp.X_op != O_illegal)
7383 || inst.reloc.exp.X_add_number != 0),
7385 inst.instruction |= inst.operands[0].reg;
7386 inst.instruction |= inst.operands[1].reg << 12;
7387 inst.instruction |= inst.operands[2].reg << 16;
7393 inst.instruction |= inst.operands[0].imm;
7399 inst.instruction |= inst.operands[0].reg << 12;
7400 encode_arm_cp_address (1, TRUE, TRUE, 0);
7403 /* ARM instructions, in alphabetical order by function name (except
7404 that wrapper functions appear immediately after the function they
7407 /* This is a pseudo-op of the form "adr rd, label" to be converted
7408 into a relative address of the form "add rd, pc, #label-.-8". */
7413 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7415 /* Frag hacking will turn this into a sub instruction if the offset turns
7416 out to be negative. */
7417 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7418 inst.reloc.pc_rel = 1;
7419 inst.reloc.exp.X_add_number -= 8;
7422 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7423 into a relative address of the form:
7424 add rd, pc, #low(label-.-8)"
7425 add rd, rd, #high(label-.-8)" */
7430 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7432 /* Frag hacking will turn this into a sub instruction if the offset turns
7433 out to be negative. */
7434 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7435 inst.reloc.pc_rel = 1;
7436 inst.size = INSN_SIZE * 2;
7437 inst.reloc.exp.X_add_number -= 8;
7443 if (!inst.operands[1].present)
7444 inst.operands[1].reg = inst.operands[0].reg;
7445 inst.instruction |= inst.operands[0].reg << 12;
7446 inst.instruction |= inst.operands[1].reg << 16;
7447 encode_arm_shifter_operand (2);
7453 if (inst.operands[0].present)
7455 constraint ((inst.instruction & 0xf0) != 0x40
7456 && inst.operands[0].imm > 0xf
7457 && inst.operands[0].imm < 0x0,
7458 _("bad barrier type"));
7459 inst.instruction |= inst.operands[0].imm;
7462 inst.instruction |= 0xf;
7468 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7469 constraint (msb > 32, _("bit-field extends past end of register"));
7470 /* The instruction encoding stores the LSB and MSB,
7471 not the LSB and width. */
7472 inst.instruction |= inst.operands[0].reg << 12;
7473 inst.instruction |= inst.operands[1].imm << 7;
7474 inst.instruction |= (msb - 1) << 16;
7482 /* #0 in second position is alternative syntax for bfc, which is
7483 the same instruction but with REG_PC in the Rm field. */
7484 if (!inst.operands[1].isreg)
7485 inst.operands[1].reg = REG_PC;
7487 msb = inst.operands[2].imm + inst.operands[3].imm;
7488 constraint (msb > 32, _("bit-field extends past end of register"));
7489 /* The instruction encoding stores the LSB and MSB,
7490 not the LSB and width. */
7491 inst.instruction |= inst.operands[0].reg << 12;
7492 inst.instruction |= inst.operands[1].reg;
7493 inst.instruction |= inst.operands[2].imm << 7;
7494 inst.instruction |= (msb - 1) << 16;
7500 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7501 _("bit-field extends past end of register"));
7502 inst.instruction |= inst.operands[0].reg << 12;
7503 inst.instruction |= inst.operands[1].reg;
7504 inst.instruction |= inst.operands[2].imm << 7;
7505 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7508 /* ARM V5 breakpoint instruction (argument parse)
7509 BKPT <16 bit unsigned immediate>
7510 Instruction is not conditional.
7511 The bit pattern given in insns[] has the COND_ALWAYS condition,
7512 and it is an error if the caller tried to override that. */
7517 /* Top 12 of 16 bits to bits 19:8. */
7518 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7520 /* Bottom 4 of 16 bits to bits 3:0. */
7521 inst.instruction |= inst.operands[0].imm & 0xf;
7525 encode_branch (int default_reloc)
7527 if (inst.operands[0].hasreloc)
7529 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7530 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7531 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7532 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7533 ? BFD_RELOC_ARM_PLT32
7534 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7537 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7538 inst.reloc.pc_rel = 1;
7545 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7546 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7549 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7556 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7558 if (inst.cond == COND_ALWAYS)
7559 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7561 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7565 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7568 /* ARM V5 branch-link-exchange instruction (argument parse)
7569 BLX <target_addr> ie BLX(1)
7570 BLX{<condition>} <Rm> ie BLX(2)
7571 Unfortunately, there are two different opcodes for this mnemonic.
7572 So, the insns[].value is not used, and the code here zaps values
7573 into inst.instruction.
7574 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7579 if (inst.operands[0].isreg)
7581 /* Arg is a register; the opcode provided by insns[] is correct.
7582 It is not illegal to do "blx pc", just useless. */
7583 if (inst.operands[0].reg == REG_PC)
7584 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7586 inst.instruction |= inst.operands[0].reg;
7590 /* Arg is an address; this instruction cannot be executed
7591 conditionally, and the opcode must be adjusted.
7592 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7593 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7594 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7595 inst.instruction = 0xfa000000;
7596 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7603 bfd_boolean want_reloc;
7605 if (inst.operands[0].reg == REG_PC)
7606 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7608 inst.instruction |= inst.operands[0].reg;
7609 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7610 it is for ARMv4t or earlier. */
7611 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7612 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7616 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7621 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7625 /* ARM v5TEJ. Jump to Jazelle code. */
7630 if (inst.operands[0].reg == REG_PC)
7631 as_tsktsk (_("use of r15 in bxj is not really useful"));
7633 inst.instruction |= inst.operands[0].reg;
7636 /* Co-processor data operation:
7637 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7638 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7642 inst.instruction |= inst.operands[0].reg << 8;
7643 inst.instruction |= inst.operands[1].imm << 20;
7644 inst.instruction |= inst.operands[2].reg << 12;
7645 inst.instruction |= inst.operands[3].reg << 16;
7646 inst.instruction |= inst.operands[4].reg;
7647 inst.instruction |= inst.operands[5].imm << 5;
7653 inst.instruction |= inst.operands[0].reg << 16;
7654 encode_arm_shifter_operand (1);
7657 /* Transfer between coprocessor and ARM registers.
7658 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7663 No special properties. */
7670 Rd = inst.operands[2].reg;
7673 if (inst.instruction == 0xee000010
7674 || inst.instruction == 0xfe000010)
7676 reject_bad_reg (Rd);
7679 constraint (Rd == REG_SP, BAD_SP);
7684 if (inst.instruction == 0xe000010)
7685 constraint (Rd == REG_PC, BAD_PC);
7689 inst.instruction |= inst.operands[0].reg << 8;
7690 inst.instruction |= inst.operands[1].imm << 21;
7691 inst.instruction |= Rd << 12;
7692 inst.instruction |= inst.operands[3].reg << 16;
7693 inst.instruction |= inst.operands[4].reg;
7694 inst.instruction |= inst.operands[5].imm << 5;
7697 /* Transfer between coprocessor register and pair of ARM registers.
7698 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7703 Two XScale instructions are special cases of these:
7705 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7706 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7708 Result unpredictable if Rd or Rn is R15. */
7715 Rd = inst.operands[2].reg;
7716 Rn = inst.operands[3].reg;
7720 reject_bad_reg (Rd);
7721 reject_bad_reg (Rn);
7725 constraint (Rd == REG_PC, BAD_PC);
7726 constraint (Rn == REG_PC, BAD_PC);
7729 inst.instruction |= inst.operands[0].reg << 8;
7730 inst.instruction |= inst.operands[1].imm << 4;
7731 inst.instruction |= Rd << 12;
7732 inst.instruction |= Rn << 16;
7733 inst.instruction |= inst.operands[4].reg;
7739 inst.instruction |= inst.operands[0].imm << 6;
7740 if (inst.operands[1].present)
7742 inst.instruction |= CPSI_MMOD;
7743 inst.instruction |= inst.operands[1].imm;
7750 inst.instruction |= inst.operands[0].imm;
7756 unsigned Rd, Rn, Rm;
7758 Rd = inst.operands[0].reg;
7759 Rn = (inst.operands[1].present
7760 ? inst.operands[1].reg : Rd);
7761 Rm = inst.operands[2].reg;
7763 constraint ((Rd == REG_PC), BAD_PC);
7764 constraint ((Rn == REG_PC), BAD_PC);
7765 constraint ((Rm == REG_PC), BAD_PC);
7767 inst.instruction |= Rd << 16;
7768 inst.instruction |= Rn << 0;
7769 inst.instruction |= Rm << 8;
7775 /* There is no IT instruction in ARM mode. We
7776 process it to do the validation as if in
7777 thumb mode, just in case the code gets
7778 assembled for thumb using the unified syntax. */
7783 set_it_insn_type (IT_INSN);
7784 now_it.mask = (inst.instruction & 0xf) | 0x10;
7785 now_it.cc = inst.operands[0].imm;
7792 int base_reg = inst.operands[0].reg;
7793 int range = inst.operands[1].imm;
7795 inst.instruction |= base_reg << 16;
7796 inst.instruction |= range;
7798 if (inst.operands[1].writeback)
7799 inst.instruction |= LDM_TYPE_2_OR_3;
7801 if (inst.operands[0].writeback)
7803 inst.instruction |= WRITE_BACK;
7804 /* Check for unpredictable uses of writeback. */
7805 if (inst.instruction & LOAD_BIT)
7807 /* Not allowed in LDM type 2. */
7808 if ((inst.instruction & LDM_TYPE_2_OR_3)
7809 && ((range & (1 << REG_PC)) == 0))
7810 as_warn (_("writeback of base register is UNPREDICTABLE"));
7811 /* Only allowed if base reg not in list for other types. */
7812 else if (range & (1 << base_reg))
7813 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7817 /* Not allowed for type 2. */
7818 if (inst.instruction & LDM_TYPE_2_OR_3)
7819 as_warn (_("writeback of base register is UNPREDICTABLE"));
7820 /* Only allowed if base reg not in list, or first in list. */
7821 else if ((range & (1 << base_reg))
7822 && (range & ((1 << base_reg) - 1)))
7823 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7828 /* ARMv5TE load-consecutive (argument parse)
7837 constraint (inst.operands[0].reg % 2 != 0,
7838 _("first transfer register must be even"));
7839 constraint (inst.operands[1].present
7840 && inst.operands[1].reg != inst.operands[0].reg + 1,
7841 _("can only transfer two consecutive registers"));
7842 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7843 constraint (!inst.operands[2].isreg, _("'[' expected"));
7845 if (!inst.operands[1].present)
7846 inst.operands[1].reg = inst.operands[0].reg + 1;
7848 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7849 register and the first register written; we have to diagnose
7850 overlap between the base and the second register written here. */
7852 if (inst.operands[2].reg == inst.operands[1].reg
7853 && (inst.operands[2].writeback || inst.operands[2].postind))
7854 as_warn (_("base register written back, and overlaps "
7855 "second transfer register"));
7857 if (!(inst.instruction & V4_STR_BIT))
7859 /* For an index-register load, the index register must not overlap the
7860 destination (even if not write-back). */
7861 if (inst.operands[2].immisreg
7862 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7863 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7864 as_warn (_("index register overlaps transfer register"));
7866 inst.instruction |= inst.operands[0].reg << 12;
7867 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7873 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7874 || inst.operands[1].postind || inst.operands[1].writeback
7875 || inst.operands[1].immisreg || inst.operands[1].shifted
7876 || inst.operands[1].negative
7877 /* This can arise if the programmer has written
7879 or if they have mistakenly used a register name as the last
7882 It is very difficult to distinguish between these two cases
7883 because "rX" might actually be a label. ie the register
7884 name has been occluded by a symbol of the same name. So we
7885 just generate a general 'bad addressing mode' type error
7886 message and leave it up to the programmer to discover the
7887 true cause and fix their mistake. */
7888 || (inst.operands[1].reg == REG_PC),
7891 constraint (inst.reloc.exp.X_op != O_constant
7892 || inst.reloc.exp.X_add_number != 0,
7893 _("offset must be zero in ARM encoding"));
7895 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7897 inst.instruction |= inst.operands[0].reg << 12;
7898 inst.instruction |= inst.operands[1].reg << 16;
7899 inst.reloc.type = BFD_RELOC_UNUSED;
7905 constraint (inst.operands[0].reg % 2 != 0,
7906 _("even register required"));
7907 constraint (inst.operands[1].present
7908 && inst.operands[1].reg != inst.operands[0].reg + 1,
7909 _("can only load two consecutive registers"));
7910 /* If op 1 were present and equal to PC, this function wouldn't
7911 have been called in the first place. */
7912 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7914 inst.instruction |= inst.operands[0].reg << 12;
7915 inst.instruction |= inst.operands[2].reg << 16;
7921 inst.instruction |= inst.operands[0].reg << 12;
7922 if (!inst.operands[1].isreg)
7923 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7925 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7931 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7933 if (inst.operands[1].preind)
7935 constraint (inst.reloc.exp.X_op != O_constant
7936 || inst.reloc.exp.X_add_number != 0,
7937 _("this instruction requires a post-indexed address"));
7939 inst.operands[1].preind = 0;
7940 inst.operands[1].postind = 1;
7941 inst.operands[1].writeback = 1;
7943 inst.instruction |= inst.operands[0].reg << 12;
7944 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7947 /* Halfword and signed-byte load/store operations. */
7952 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7953 inst.instruction |= inst.operands[0].reg << 12;
7954 if (!inst.operands[1].isreg)
7955 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7957 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7963 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7965 if (inst.operands[1].preind)
7967 constraint (inst.reloc.exp.X_op != O_constant
7968 || inst.reloc.exp.X_add_number != 0,
7969 _("this instruction requires a post-indexed address"));
7971 inst.operands[1].preind = 0;
7972 inst.operands[1].postind = 1;
7973 inst.operands[1].writeback = 1;
7975 inst.instruction |= inst.operands[0].reg << 12;
7976 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7979 /* Co-processor register load/store.
7980 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7984 inst.instruction |= inst.operands[0].reg << 8;
7985 inst.instruction |= inst.operands[1].reg << 12;
7986 encode_arm_cp_address (2, TRUE, TRUE, 0);
7992 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7993 if (inst.operands[0].reg == inst.operands[1].reg
7994 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7995 && !(inst.instruction & 0x00400000))
7996 as_tsktsk (_("Rd and Rm should be different in mla"));
7998 inst.instruction |= inst.operands[0].reg << 16;
7999 inst.instruction |= inst.operands[1].reg;
8000 inst.instruction |= inst.operands[2].reg << 8;
8001 inst.instruction |= inst.operands[3].reg << 12;
8007 inst.instruction |= inst.operands[0].reg << 12;
8008 encode_arm_shifter_operand (1);
8011 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8018 top = (inst.instruction & 0x00400000) != 0;
8019 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8020 _(":lower16: not allowed this instruction"));
8021 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8022 _(":upper16: not allowed instruction"));
8023 inst.instruction |= inst.operands[0].reg << 12;
8024 if (inst.reloc.type == BFD_RELOC_UNUSED)
8026 imm = inst.reloc.exp.X_add_number;
8027 /* The value is in two pieces: 0:11, 16:19. */
8028 inst.instruction |= (imm & 0x00000fff);
8029 inst.instruction |= (imm & 0x0000f000) << 4;
8033 static void do_vfp_nsyn_opcode (const char *);
8036 do_vfp_nsyn_mrs (void)
8038 if (inst.operands[0].isvec)
8040 if (inst.operands[1].reg != 1)
8041 first_error (_("operand 1 must be FPSCR"));
8042 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8043 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8044 do_vfp_nsyn_opcode ("fmstat");
8046 else if (inst.operands[1].isvec)
8047 do_vfp_nsyn_opcode ("fmrx");
8055 do_vfp_nsyn_msr (void)
8057 if (inst.operands[0].isvec)
8058 do_vfp_nsyn_opcode ("fmxr");
8068 unsigned Rt = inst.operands[0].reg;
8070 if (thumb_mode && inst.operands[0].reg == REG_SP)
8072 inst.error = BAD_SP;
8076 /* APSR_ sets isvec. All other refs to PC are illegal. */
8077 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8079 inst.error = BAD_PC;
8083 if (inst.operands[1].reg != 1)
8084 first_error (_("operand 1 must be FPSCR"));
8086 inst.instruction |= (Rt << 12);
8092 unsigned Rt = inst.operands[1].reg;
8095 reject_bad_reg (Rt);
8096 else if (Rt == REG_PC)
8098 inst.error = BAD_PC;
8102 if (inst.operands[0].reg != 1)
8103 first_error (_("operand 0 must be FPSCR"));
8105 inst.instruction |= (Rt << 12);
8113 if (do_vfp_nsyn_mrs () == SUCCESS)
8116 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8117 inst.instruction |= inst.operands[0].reg << 12;
8119 if (inst.operands[1].isreg)
8121 br = inst.operands[1].reg;
8122 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8123 as_bad (_("bad register for mrs"));
8127 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8128 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8130 _("'APSR', 'CPSR' or 'SPSR' expected"));
8131 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8134 inst.instruction |= br;
8137 /* Two possible forms:
8138 "{C|S}PSR_<field>, Rm",
8139 "{C|S}PSR_f, #expression". */
8144 if (do_vfp_nsyn_msr () == SUCCESS)
8147 inst.instruction |= inst.operands[0].imm;
8148 if (inst.operands[1].isreg)
8149 inst.instruction |= inst.operands[1].reg;
8152 inst.instruction |= INST_IMMEDIATE;
8153 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8154 inst.reloc.pc_rel = 0;
8161 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8163 if (!inst.operands[2].present)
8164 inst.operands[2].reg = inst.operands[0].reg;
8165 inst.instruction |= inst.operands[0].reg << 16;
8166 inst.instruction |= inst.operands[1].reg;
8167 inst.instruction |= inst.operands[2].reg << 8;
8169 if (inst.operands[0].reg == inst.operands[1].reg
8170 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8171 as_tsktsk (_("Rd and Rm should be different in mul"));
8174 /* Long Multiply Parser
8175 UMULL RdLo, RdHi, Rm, Rs
8176 SMULL RdLo, RdHi, Rm, Rs
8177 UMLAL RdLo, RdHi, Rm, Rs
8178 SMLAL RdLo, RdHi, Rm, Rs. */
8183 inst.instruction |= inst.operands[0].reg << 12;
8184 inst.instruction |= inst.operands[1].reg << 16;
8185 inst.instruction |= inst.operands[2].reg;
8186 inst.instruction |= inst.operands[3].reg << 8;
8188 /* rdhi and rdlo must be different. */
8189 if (inst.operands[0].reg == inst.operands[1].reg)
8190 as_tsktsk (_("rdhi and rdlo must be different"));
8192 /* rdhi, rdlo and rm must all be different before armv6. */
8193 if ((inst.operands[0].reg == inst.operands[2].reg
8194 || inst.operands[1].reg == inst.operands[2].reg)
8195 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8196 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8202 if (inst.operands[0].present
8203 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8205 /* Architectural NOP hints are CPSR sets with no bits selected. */
8206 inst.instruction &= 0xf0000000;
8207 inst.instruction |= 0x0320f000;
8208 if (inst.operands[0].present)
8209 inst.instruction |= inst.operands[0].imm;
8213 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8214 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8215 Condition defaults to COND_ALWAYS.
8216 Error if Rd, Rn or Rm are R15. */
8221 inst.instruction |= inst.operands[0].reg << 12;
8222 inst.instruction |= inst.operands[1].reg << 16;
8223 inst.instruction |= inst.operands[2].reg;
8224 if (inst.operands[3].present)
8225 encode_arm_shift (3);
8228 /* ARM V6 PKHTB (Argument Parse). */
8233 if (!inst.operands[3].present)
8235 /* If the shift specifier is omitted, turn the instruction
8236 into pkhbt rd, rm, rn. */
8237 inst.instruction &= 0xfff00010;
8238 inst.instruction |= inst.operands[0].reg << 12;
8239 inst.instruction |= inst.operands[1].reg;
8240 inst.instruction |= inst.operands[2].reg << 16;
8244 inst.instruction |= inst.operands[0].reg << 12;
8245 inst.instruction |= inst.operands[1].reg << 16;
8246 inst.instruction |= inst.operands[2].reg;
8247 encode_arm_shift (3);
8251 /* ARMv5TE: Preload-Cache
8252 MP Extensions: Preload for write
8256 Syntactically, like LDR with B=1, W=0, L=1. */
8261 constraint (!inst.operands[0].isreg,
8262 _("'[' expected after PLD mnemonic"));
8263 constraint (inst.operands[0].postind,
8264 _("post-indexed expression used in preload instruction"));
8265 constraint (inst.operands[0].writeback,
8266 _("writeback used in preload instruction"));
8267 constraint (!inst.operands[0].preind,
8268 _("unindexed addressing used in preload instruction"));
8269 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8272 /* ARMv7: PLI <addr_mode> */
8276 constraint (!inst.operands[0].isreg,
8277 _("'[' expected after PLI mnemonic"));
8278 constraint (inst.operands[0].postind,
8279 _("post-indexed expression used in preload instruction"));
8280 constraint (inst.operands[0].writeback,
8281 _("writeback used in preload instruction"));
8282 constraint (!inst.operands[0].preind,
8283 _("unindexed addressing used in preload instruction"));
8284 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8285 inst.instruction &= ~PRE_INDEX;
8291 inst.operands[1] = inst.operands[0];
8292 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8293 inst.operands[0].isreg = 1;
8294 inst.operands[0].writeback = 1;
8295 inst.operands[0].reg = REG_SP;
8299 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8300 word at the specified address and the following word
8302 Unconditionally executed.
8303 Error if Rn is R15. */
8308 inst.instruction |= inst.operands[0].reg << 16;
8309 if (inst.operands[0].writeback)
8310 inst.instruction |= WRITE_BACK;
8313 /* ARM V6 ssat (argument parse). */
8318 inst.instruction |= inst.operands[0].reg << 12;
8319 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8320 inst.instruction |= inst.operands[2].reg;
8322 if (inst.operands[3].present)
8323 encode_arm_shift (3);
8326 /* ARM V6 usat (argument parse). */
8331 inst.instruction |= inst.operands[0].reg << 12;
8332 inst.instruction |= inst.operands[1].imm << 16;
8333 inst.instruction |= inst.operands[2].reg;
8335 if (inst.operands[3].present)
8336 encode_arm_shift (3);
8339 /* ARM V6 ssat16 (argument parse). */
8344 inst.instruction |= inst.operands[0].reg << 12;
8345 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8346 inst.instruction |= inst.operands[2].reg;
8352 inst.instruction |= inst.operands[0].reg << 12;
8353 inst.instruction |= inst.operands[1].imm << 16;
8354 inst.instruction |= inst.operands[2].reg;
8357 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8358 preserving the other bits.
8360 setend <endian_specifier>, where <endian_specifier> is either
8366 if (inst.operands[0].imm)
8367 inst.instruction |= 0x200;
8373 unsigned int Rm = (inst.operands[1].present
8374 ? inst.operands[1].reg
8375 : inst.operands[0].reg);
8377 inst.instruction |= inst.operands[0].reg << 12;
8378 inst.instruction |= Rm;
8379 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8381 inst.instruction |= inst.operands[2].reg << 8;
8382 inst.instruction |= SHIFT_BY_REG;
8383 /* PR 12854: Error on extraneous shifts. */
8384 constraint (inst.operands[2].shifted,
8385 _("extraneous shift as part of operand to shift insn"));
8388 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8394 inst.reloc.type = BFD_RELOC_ARM_SMC;
8395 inst.reloc.pc_rel = 0;
8401 inst.reloc.type = BFD_RELOC_ARM_HVC;
8402 inst.reloc.pc_rel = 0;
8408 inst.reloc.type = BFD_RELOC_ARM_SWI;
8409 inst.reloc.pc_rel = 0;
8412 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8413 SMLAxy{cond} Rd,Rm,Rs,Rn
8414 SMLAWy{cond} Rd,Rm,Rs,Rn
8415 Error if any register is R15. */
8420 inst.instruction |= inst.operands[0].reg << 16;
8421 inst.instruction |= inst.operands[1].reg;
8422 inst.instruction |= inst.operands[2].reg << 8;
8423 inst.instruction |= inst.operands[3].reg << 12;
8426 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8427 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8428 Error if any register is R15.
8429 Warning if Rdlo == Rdhi. */
8434 inst.instruction |= inst.operands[0].reg << 12;
8435 inst.instruction |= inst.operands[1].reg << 16;
8436 inst.instruction |= inst.operands[2].reg;
8437 inst.instruction |= inst.operands[3].reg << 8;
8439 if (inst.operands[0].reg == inst.operands[1].reg)
8440 as_tsktsk (_("rdhi and rdlo must be different"));
8443 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8444 SMULxy{cond} Rd,Rm,Rs
8445 Error if any register is R15. */
8450 inst.instruction |= inst.operands[0].reg << 16;
8451 inst.instruction |= inst.operands[1].reg;
8452 inst.instruction |= inst.operands[2].reg << 8;
8455 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8456 the same for both ARM and Thumb-2. */
8463 if (inst.operands[0].present)
8465 reg = inst.operands[0].reg;
8466 constraint (reg != REG_SP, _("SRS base register must be r13"));
8471 inst.instruction |= reg << 16;
8472 inst.instruction |= inst.operands[1].imm;
8473 if (inst.operands[0].writeback || inst.operands[1].writeback)
8474 inst.instruction |= WRITE_BACK;
8477 /* ARM V6 strex (argument parse). */
8482 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8483 || inst.operands[2].postind || inst.operands[2].writeback
8484 || inst.operands[2].immisreg || inst.operands[2].shifted
8485 || inst.operands[2].negative
8486 /* See comment in do_ldrex(). */
8487 || (inst.operands[2].reg == REG_PC),
8490 constraint (inst.operands[0].reg == inst.operands[1].reg
8491 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8493 constraint (inst.reloc.exp.X_op != O_constant
8494 || inst.reloc.exp.X_add_number != 0,
8495 _("offset must be zero in ARM encoding"));
8497 inst.instruction |= inst.operands[0].reg << 12;
8498 inst.instruction |= inst.operands[1].reg;
8499 inst.instruction |= inst.operands[2].reg << 16;
8500 inst.reloc.type = BFD_RELOC_UNUSED;
8506 constraint (inst.operands[1].reg % 2 != 0,
8507 _("even register required"));
8508 constraint (inst.operands[2].present
8509 && inst.operands[2].reg != inst.operands[1].reg + 1,
8510 _("can only store two consecutive registers"));
8511 /* If op 2 were present and equal to PC, this function wouldn't
8512 have been called in the first place. */
8513 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8515 constraint (inst.operands[0].reg == inst.operands[1].reg
8516 || inst.operands[0].reg == inst.operands[1].reg + 1
8517 || inst.operands[0].reg == inst.operands[3].reg,
8520 inst.instruction |= inst.operands[0].reg << 12;
8521 inst.instruction |= inst.operands[1].reg;
8522 inst.instruction |= inst.operands[3].reg << 16;
8525 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8526 extends it to 32-bits, and adds the result to a value in another
8527 register. You can specify a rotation by 0, 8, 16, or 24 bits
8528 before extracting the 16-bit value.
8529 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8530 Condition defaults to COND_ALWAYS.
8531 Error if any register uses R15. */
8536 inst.instruction |= inst.operands[0].reg << 12;
8537 inst.instruction |= inst.operands[1].reg << 16;
8538 inst.instruction |= inst.operands[2].reg;
8539 inst.instruction |= inst.operands[3].imm << 10;
8544 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8545 Condition defaults to COND_ALWAYS.
8546 Error if any register uses R15. */
8551 inst.instruction |= inst.operands[0].reg << 12;
8552 inst.instruction |= inst.operands[1].reg;
8553 inst.instruction |= inst.operands[2].imm << 10;
8556 /* VFP instructions. In a logical order: SP variant first, monad
8557 before dyad, arithmetic then move then load/store. */
8560 do_vfp_sp_monadic (void)
8562 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8563 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8567 do_vfp_sp_dyadic (void)
8569 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8570 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8571 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8575 do_vfp_sp_compare_z (void)
8577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8581 do_vfp_dp_sp_cvt (void)
8583 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8584 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8588 do_vfp_sp_dp_cvt (void)
8590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8595 do_vfp_reg_from_sp (void)
8597 inst.instruction |= inst.operands[0].reg << 12;
8598 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8602 do_vfp_reg2_from_sp2 (void)
8604 constraint (inst.operands[2].imm != 2,
8605 _("only two consecutive VFP SP registers allowed here"));
8606 inst.instruction |= inst.operands[0].reg << 12;
8607 inst.instruction |= inst.operands[1].reg << 16;
8608 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8612 do_vfp_sp_from_reg (void)
8614 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8615 inst.instruction |= inst.operands[1].reg << 12;
8619 do_vfp_sp2_from_reg2 (void)
8621 constraint (inst.operands[0].imm != 2,
8622 _("only two consecutive VFP SP registers allowed here"));
8623 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8624 inst.instruction |= inst.operands[1].reg << 12;
8625 inst.instruction |= inst.operands[2].reg << 16;
8629 do_vfp_sp_ldst (void)
8631 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8632 encode_arm_cp_address (1, FALSE, TRUE, 0);
8636 do_vfp_dp_ldst (void)
8638 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8639 encode_arm_cp_address (1, FALSE, TRUE, 0);
8644 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8646 if (inst.operands[0].writeback)
8647 inst.instruction |= WRITE_BACK;
8649 constraint (ldstm_type != VFP_LDSTMIA,
8650 _("this addressing mode requires base-register writeback"));
8651 inst.instruction |= inst.operands[0].reg << 16;
8652 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8653 inst.instruction |= inst.operands[1].imm;
8657 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8661 if (inst.operands[0].writeback)
8662 inst.instruction |= WRITE_BACK;
8664 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8665 _("this addressing mode requires base-register writeback"));
8667 inst.instruction |= inst.operands[0].reg << 16;
8668 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8670 count = inst.operands[1].imm << 1;
8671 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8674 inst.instruction |= count;
8678 do_vfp_sp_ldstmia (void)
8680 vfp_sp_ldstm (VFP_LDSTMIA);
8684 do_vfp_sp_ldstmdb (void)
8686 vfp_sp_ldstm (VFP_LDSTMDB);
8690 do_vfp_dp_ldstmia (void)
8692 vfp_dp_ldstm (VFP_LDSTMIA);
8696 do_vfp_dp_ldstmdb (void)
8698 vfp_dp_ldstm (VFP_LDSTMDB);
8702 do_vfp_xp_ldstmia (void)
8704 vfp_dp_ldstm (VFP_LDSTMIAX);
8708 do_vfp_xp_ldstmdb (void)
8710 vfp_dp_ldstm (VFP_LDSTMDBX);
8714 do_vfp_dp_rd_rm (void)
8716 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8717 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8721 do_vfp_dp_rn_rd (void)
8723 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8724 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8728 do_vfp_dp_rd_rn (void)
8730 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8731 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8735 do_vfp_dp_rd_rn_rm (void)
8737 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8738 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8739 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8749 do_vfp_dp_rm_rd_rn (void)
8751 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8752 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8753 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8756 /* VFPv3 instructions. */
8758 do_vfp_sp_const (void)
8760 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8761 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8762 inst.instruction |= (inst.operands[1].imm & 0x0f);
8766 do_vfp_dp_const (void)
8768 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8769 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8770 inst.instruction |= (inst.operands[1].imm & 0x0f);
8774 vfp_conv (int srcsize)
8776 int immbits = srcsize - inst.operands[1].imm;
8778 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8780 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8781 i.e. immbits must be in range 0 - 16. */
8782 inst.error = _("immediate value out of range, expected range [0, 16]");
8785 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8787 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8788 i.e. immbits must be in range 0 - 31. */
8789 inst.error = _("immediate value out of range, expected range [1, 32]");
8793 inst.instruction |= (immbits & 1) << 5;
8794 inst.instruction |= (immbits >> 1);
8798 do_vfp_sp_conv_16 (void)
8800 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8805 do_vfp_dp_conv_16 (void)
8807 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8812 do_vfp_sp_conv_32 (void)
8814 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8819 do_vfp_dp_conv_32 (void)
8821 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8825 /* FPA instructions. Also in a logical order. */
8830 inst.instruction |= inst.operands[0].reg << 16;
8831 inst.instruction |= inst.operands[1].reg;
8835 do_fpa_ldmstm (void)
8837 inst.instruction |= inst.operands[0].reg << 12;
8838 switch (inst.operands[1].imm)
8840 case 1: inst.instruction |= CP_T_X; break;
8841 case 2: inst.instruction |= CP_T_Y; break;
8842 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8847 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8849 /* The instruction specified "ea" or "fd", so we can only accept
8850 [Rn]{!}. The instruction does not really support stacking or
8851 unstacking, so we have to emulate these by setting appropriate
8852 bits and offsets. */
8853 constraint (inst.reloc.exp.X_op != O_constant
8854 || inst.reloc.exp.X_add_number != 0,
8855 _("this instruction does not support indexing"));
8857 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8858 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8860 if (!(inst.instruction & INDEX_UP))
8861 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8863 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8865 inst.operands[2].preind = 0;
8866 inst.operands[2].postind = 1;
8870 encode_arm_cp_address (2, TRUE, TRUE, 0);
8873 /* iWMMXt instructions: strictly in alphabetical order. */
8876 do_iwmmxt_tandorc (void)
8878 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8882 do_iwmmxt_textrc (void)
8884 inst.instruction |= inst.operands[0].reg << 12;
8885 inst.instruction |= inst.operands[1].imm;
8889 do_iwmmxt_textrm (void)
8891 inst.instruction |= inst.operands[0].reg << 12;
8892 inst.instruction |= inst.operands[1].reg << 16;
8893 inst.instruction |= inst.operands[2].imm;
8897 do_iwmmxt_tinsr (void)
8899 inst.instruction |= inst.operands[0].reg << 16;
8900 inst.instruction |= inst.operands[1].reg << 12;
8901 inst.instruction |= inst.operands[2].imm;
8905 do_iwmmxt_tmia (void)
8907 inst.instruction |= inst.operands[0].reg << 5;
8908 inst.instruction |= inst.operands[1].reg;
8909 inst.instruction |= inst.operands[2].reg << 12;
8913 do_iwmmxt_waligni (void)
8915 inst.instruction |= inst.operands[0].reg << 12;
8916 inst.instruction |= inst.operands[1].reg << 16;
8917 inst.instruction |= inst.operands[2].reg;
8918 inst.instruction |= inst.operands[3].imm << 20;
8922 do_iwmmxt_wmerge (void)
8924 inst.instruction |= inst.operands[0].reg << 12;
8925 inst.instruction |= inst.operands[1].reg << 16;
8926 inst.instruction |= inst.operands[2].reg;
8927 inst.instruction |= inst.operands[3].imm << 21;
8931 do_iwmmxt_wmov (void)
8933 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8934 inst.instruction |= inst.operands[0].reg << 12;
8935 inst.instruction |= inst.operands[1].reg << 16;
8936 inst.instruction |= inst.operands[1].reg;
8940 do_iwmmxt_wldstbh (void)
8943 inst.instruction |= inst.operands[0].reg << 12;
8945 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8947 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8948 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8952 do_iwmmxt_wldstw (void)
8954 /* RIWR_RIWC clears .isreg for a control register. */
8955 if (!inst.operands[0].isreg)
8957 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8958 inst.instruction |= 0xf0000000;
8961 inst.instruction |= inst.operands[0].reg << 12;
8962 encode_arm_cp_address (1, TRUE, TRUE, 0);
8966 do_iwmmxt_wldstd (void)
8968 inst.instruction |= inst.operands[0].reg << 12;
8969 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
8970 && inst.operands[1].immisreg)
8972 inst.instruction &= ~0x1a000ff;
8973 inst.instruction |= (0xf << 28);
8974 if (inst.operands[1].preind)
8975 inst.instruction |= PRE_INDEX;
8976 if (!inst.operands[1].negative)
8977 inst.instruction |= INDEX_UP;
8978 if (inst.operands[1].writeback)
8979 inst.instruction |= WRITE_BACK;
8980 inst.instruction |= inst.operands[1].reg << 16;
8981 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8982 inst.instruction |= inst.operands[1].imm;
8985 encode_arm_cp_address (1, TRUE, FALSE, 0);
8989 do_iwmmxt_wshufh (void)
8991 inst.instruction |= inst.operands[0].reg << 12;
8992 inst.instruction |= inst.operands[1].reg << 16;
8993 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8994 inst.instruction |= (inst.operands[2].imm & 0x0f);
8998 do_iwmmxt_wzero (void)
9000 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9001 inst.instruction |= inst.operands[0].reg;
9002 inst.instruction |= inst.operands[0].reg << 12;
9003 inst.instruction |= inst.operands[0].reg << 16;
9007 do_iwmmxt_wrwrwr_or_imm5 (void)
9009 if (inst.operands[2].isreg)
9012 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9013 _("immediate operand requires iWMMXt2"));
9015 if (inst.operands[2].imm == 0)
9017 switch ((inst.instruction >> 20) & 0xf)
9023 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9024 inst.operands[2].imm = 16;
9025 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9031 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9032 inst.operands[2].imm = 32;
9033 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9040 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9042 wrn = (inst.instruction >> 16) & 0xf;
9043 inst.instruction &= 0xff0fff0f;
9044 inst.instruction |= wrn;
9045 /* Bail out here; the instruction is now assembled. */
9050 /* Map 32 -> 0, etc. */
9051 inst.operands[2].imm &= 0x1f;
9052 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9056 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9057 operations first, then control, shift, and load/store. */
9059 /* Insns like "foo X,Y,Z". */
9062 do_mav_triple (void)
9064 inst.instruction |= inst.operands[0].reg << 16;
9065 inst.instruction |= inst.operands[1].reg;
9066 inst.instruction |= inst.operands[2].reg << 12;
9069 /* Insns like "foo W,X,Y,Z".
9070 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9075 inst.instruction |= inst.operands[0].reg << 5;
9076 inst.instruction |= inst.operands[1].reg << 12;
9077 inst.instruction |= inst.operands[2].reg << 16;
9078 inst.instruction |= inst.operands[3].reg;
9081 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9085 inst.instruction |= inst.operands[1].reg << 12;
9088 /* Maverick shift immediate instructions.
9089 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9090 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9095 int imm = inst.operands[2].imm;
9097 inst.instruction |= inst.operands[0].reg << 12;
9098 inst.instruction |= inst.operands[1].reg << 16;
9100 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9101 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9102 Bit 4 should be 0. */
9103 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9105 inst.instruction |= imm;
9108 /* XScale instructions. Also sorted arithmetic before move. */
9110 /* Xscale multiply-accumulate (argument parse)
9113 MIAxycc acc0,Rm,Rs. */
9118 inst.instruction |= inst.operands[1].reg;
9119 inst.instruction |= inst.operands[2].reg << 12;
9122 /* Xscale move-accumulator-register (argument parse)
9124 MARcc acc0,RdLo,RdHi. */
9129 inst.instruction |= inst.operands[1].reg << 12;
9130 inst.instruction |= inst.operands[2].reg << 16;
9133 /* Xscale move-register-accumulator (argument parse)
9135 MRAcc RdLo,RdHi,acc0. */
9140 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9141 inst.instruction |= inst.operands[0].reg << 12;
9142 inst.instruction |= inst.operands[1].reg << 16;
9145 /* Encoding functions relevant only to Thumb. */
9147 /* inst.operands[i] is a shifted-register operand; encode
9148 it into inst.instruction in the format used by Thumb32. */
9151 encode_thumb32_shifted_operand (int i)
9153 unsigned int value = inst.reloc.exp.X_add_number;
9154 unsigned int shift = inst.operands[i].shift_kind;
9156 constraint (inst.operands[i].immisreg,
9157 _("shift by register not allowed in thumb mode"));
9158 inst.instruction |= inst.operands[i].reg;
9159 if (shift == SHIFT_RRX)
9160 inst.instruction |= SHIFT_ROR << 4;
9163 constraint (inst.reloc.exp.X_op != O_constant,
9164 _("expression too complex"));
9166 constraint (value > 32
9167 || (value == 32 && (shift == SHIFT_LSL
9168 || shift == SHIFT_ROR)),
9169 _("shift expression is too large"));
9173 else if (value == 32)
9176 inst.instruction |= shift << 4;
9177 inst.instruction |= (value & 0x1c) << 10;
9178 inst.instruction |= (value & 0x03) << 6;
9183 /* inst.operands[i] was set up by parse_address. Encode it into a
9184 Thumb32 format load or store instruction. Reject forms that cannot
9185 be used with such instructions. If is_t is true, reject forms that
9186 cannot be used with a T instruction; if is_d is true, reject forms
9187 that cannot be used with a D instruction. If it is a store insn,
9191 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9193 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9195 constraint (!inst.operands[i].isreg,
9196 _("Instruction does not support =N addresses"));
9198 inst.instruction |= inst.operands[i].reg << 16;
9199 if (inst.operands[i].immisreg)
9201 constraint (is_pc, BAD_PC_ADDRESSING);
9202 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9203 constraint (inst.operands[i].negative,
9204 _("Thumb does not support negative register indexing"));
9205 constraint (inst.operands[i].postind,
9206 _("Thumb does not support register post-indexing"));
9207 constraint (inst.operands[i].writeback,
9208 _("Thumb does not support register indexing with writeback"));
9209 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9210 _("Thumb supports only LSL in shifted register indexing"));
9212 inst.instruction |= inst.operands[i].imm;
9213 if (inst.operands[i].shifted)
9215 constraint (inst.reloc.exp.X_op != O_constant,
9216 _("expression too complex"));
9217 constraint (inst.reloc.exp.X_add_number < 0
9218 || inst.reloc.exp.X_add_number > 3,
9219 _("shift out of range"));
9220 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9222 inst.reloc.type = BFD_RELOC_UNUSED;
9224 else if (inst.operands[i].preind)
9226 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9227 constraint (is_t && inst.operands[i].writeback,
9228 _("cannot use writeback with this instruction"));
9229 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9230 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9234 inst.instruction |= 0x01000000;
9235 if (inst.operands[i].writeback)
9236 inst.instruction |= 0x00200000;
9240 inst.instruction |= 0x00000c00;
9241 if (inst.operands[i].writeback)
9242 inst.instruction |= 0x00000100;
9244 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9246 else if (inst.operands[i].postind)
9248 gas_assert (inst.operands[i].writeback);
9249 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9250 constraint (is_t, _("cannot use post-indexing with this instruction"));
9253 inst.instruction |= 0x00200000;
9255 inst.instruction |= 0x00000900;
9256 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9258 else /* unindexed - only for coprocessor */
9259 inst.error = _("instruction does not accept unindexed addressing");
9262 /* Table of Thumb instructions which exist in both 16- and 32-bit
9263 encodings (the latter only in post-V6T2 cores). The index is the
9264 value used in the insns table below. When there is more than one
9265 possible 16-bit encoding for the instruction, this table always
9267 Also contains several pseudo-instructions used during relaxation. */
9268 #define T16_32_TAB \
9269 X(_adc, 4140, eb400000), \
9270 X(_adcs, 4140, eb500000), \
9271 X(_add, 1c00, eb000000), \
9272 X(_adds, 1c00, eb100000), \
9273 X(_addi, 0000, f1000000), \
9274 X(_addis, 0000, f1100000), \
9275 X(_add_pc,000f, f20f0000), \
9276 X(_add_sp,000d, f10d0000), \
9277 X(_adr, 000f, f20f0000), \
9278 X(_and, 4000, ea000000), \
9279 X(_ands, 4000, ea100000), \
9280 X(_asr, 1000, fa40f000), \
9281 X(_asrs, 1000, fa50f000), \
9282 X(_b, e000, f000b000), \
9283 X(_bcond, d000, f0008000), \
9284 X(_bic, 4380, ea200000), \
9285 X(_bics, 4380, ea300000), \
9286 X(_cmn, 42c0, eb100f00), \
9287 X(_cmp, 2800, ebb00f00), \
9288 X(_cpsie, b660, f3af8400), \
9289 X(_cpsid, b670, f3af8600), \
9290 X(_cpy, 4600, ea4f0000), \
9291 X(_dec_sp,80dd, f1ad0d00), \
9292 X(_eor, 4040, ea800000), \
9293 X(_eors, 4040, ea900000), \
9294 X(_inc_sp,00dd, f10d0d00), \
9295 X(_ldmia, c800, e8900000), \
9296 X(_ldr, 6800, f8500000), \
9297 X(_ldrb, 7800, f8100000), \
9298 X(_ldrh, 8800, f8300000), \
9299 X(_ldrsb, 5600, f9100000), \
9300 X(_ldrsh, 5e00, f9300000), \
9301 X(_ldr_pc,4800, f85f0000), \
9302 X(_ldr_pc2,4800, f85f0000), \
9303 X(_ldr_sp,9800, f85d0000), \
9304 X(_lsl, 0000, fa00f000), \
9305 X(_lsls, 0000, fa10f000), \
9306 X(_lsr, 0800, fa20f000), \
9307 X(_lsrs, 0800, fa30f000), \
9308 X(_mov, 2000, ea4f0000), \
9309 X(_movs, 2000, ea5f0000), \
9310 X(_mul, 4340, fb00f000), \
9311 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9312 X(_mvn, 43c0, ea6f0000), \
9313 X(_mvns, 43c0, ea7f0000), \
9314 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9315 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9316 X(_orr, 4300, ea400000), \
9317 X(_orrs, 4300, ea500000), \
9318 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9319 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9320 X(_rev, ba00, fa90f080), \
9321 X(_rev16, ba40, fa90f090), \
9322 X(_revsh, bac0, fa90f0b0), \
9323 X(_ror, 41c0, fa60f000), \
9324 X(_rors, 41c0, fa70f000), \
9325 X(_sbc, 4180, eb600000), \
9326 X(_sbcs, 4180, eb700000), \
9327 X(_stmia, c000, e8800000), \
9328 X(_str, 6000, f8400000), \
9329 X(_strb, 7000, f8000000), \
9330 X(_strh, 8000, f8200000), \
9331 X(_str_sp,9000, f84d0000), \
9332 X(_sub, 1e00, eba00000), \
9333 X(_subs, 1e00, ebb00000), \
9334 X(_subi, 8000, f1a00000), \
9335 X(_subis, 8000, f1b00000), \
9336 X(_sxtb, b240, fa4ff080), \
9337 X(_sxth, b200, fa0ff080), \
9338 X(_tst, 4200, ea100f00), \
9339 X(_uxtb, b2c0, fa5ff080), \
9340 X(_uxth, b280, fa1ff080), \
9341 X(_nop, bf00, f3af8000), \
9342 X(_yield, bf10, f3af8001), \
9343 X(_wfe, bf20, f3af8002), \
9344 X(_wfi, bf30, f3af8003), \
9345 X(_sev, bf40, f3af8004),
9347 /* To catch errors in encoding functions, the codes are all offset by
9348 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9349 as 16-bit instructions. */
9350 #define X(a,b,c) T_MNEM##a
9351 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9354 #define X(a,b,c) 0x##b
9355 static const unsigned short thumb_op16[] = { T16_32_TAB };
9356 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9359 #define X(a,b,c) 0x##c
9360 static const unsigned int thumb_op32[] = { T16_32_TAB };
9361 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9362 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9366 /* Thumb instruction encoders, in alphabetical order. */
9371 do_t_add_sub_w (void)
9375 Rd = inst.operands[0].reg;
9376 Rn = inst.operands[1].reg;
9378 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9379 is the SP-{plus,minus}-immediate form of the instruction. */
9381 constraint (Rd == REG_PC, BAD_PC);
9383 reject_bad_reg (Rd);
9385 inst.instruction |= (Rn << 16) | (Rd << 8);
9386 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9389 /* Parse an add or subtract instruction. We get here with inst.instruction
9390 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9397 Rd = inst.operands[0].reg;
9398 Rs = (inst.operands[1].present
9399 ? inst.operands[1].reg /* Rd, Rs, foo */
9400 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9403 set_it_insn_type_last ();
9411 flags = (inst.instruction == T_MNEM_adds
9412 || inst.instruction == T_MNEM_subs);
9414 narrow = !in_it_block ();
9416 narrow = in_it_block ();
9417 if (!inst.operands[2].isreg)
9421 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9423 add = (inst.instruction == T_MNEM_add
9424 || inst.instruction == T_MNEM_adds);
9426 if (inst.size_req != 4)
9428 /* Attempt to use a narrow opcode, with relaxation if
9430 if (Rd == REG_SP && Rs == REG_SP && !flags)
9431 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9432 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9433 opcode = T_MNEM_add_sp;
9434 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9435 opcode = T_MNEM_add_pc;
9436 else if (Rd <= 7 && Rs <= 7 && narrow)
9439 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9441 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9445 inst.instruction = THUMB_OP16(opcode);
9446 inst.instruction |= (Rd << 4) | Rs;
9447 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9448 if (inst.size_req != 2)
9449 inst.relax = opcode;
9452 constraint (inst.size_req == 2, BAD_HIREG);
9454 if (inst.size_req == 4
9455 || (inst.size_req != 2 && !opcode))
9459 constraint (add, BAD_PC);
9460 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9461 _("only SUBS PC, LR, #const allowed"));
9462 constraint (inst.reloc.exp.X_op != O_constant,
9463 _("expression too complex"));
9464 constraint (inst.reloc.exp.X_add_number < 0
9465 || inst.reloc.exp.X_add_number > 0xff,
9466 _("immediate value out of range"));
9467 inst.instruction = T2_SUBS_PC_LR
9468 | inst.reloc.exp.X_add_number;
9469 inst.reloc.type = BFD_RELOC_UNUSED;
9472 else if (Rs == REG_PC)
9474 /* Always use addw/subw. */
9475 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9476 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9480 inst.instruction = THUMB_OP32 (inst.instruction);
9481 inst.instruction = (inst.instruction & 0xe1ffffff)
9484 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9486 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9488 inst.instruction |= Rd << 8;
9489 inst.instruction |= Rs << 16;
9494 unsigned int value = inst.reloc.exp.X_add_number;
9495 unsigned int shift = inst.operands[2].shift_kind;
9497 Rn = inst.operands[2].reg;
9498 /* See if we can do this with a 16-bit instruction. */
9499 if (!inst.operands[2].shifted && inst.size_req != 4)
9501 if (Rd > 7 || Rs > 7 || Rn > 7)
9506 inst.instruction = ((inst.instruction == T_MNEM_adds
9507 || inst.instruction == T_MNEM_add)
9510 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9514 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9516 /* Thumb-1 cores (except v6-M) require at least one high
9517 register in a narrow non flag setting add. */
9518 if (Rd > 7 || Rn > 7
9519 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9520 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9527 inst.instruction = T_OPCODE_ADD_HI;
9528 inst.instruction |= (Rd & 8) << 4;
9529 inst.instruction |= (Rd & 7);
9530 inst.instruction |= Rn << 3;
9536 constraint (Rd == REG_PC, BAD_PC);
9537 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9538 constraint (Rs == REG_PC, BAD_PC);
9539 reject_bad_reg (Rn);
9541 /* If we get here, it can't be done in 16 bits. */
9542 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9543 _("shift must be constant"));
9544 inst.instruction = THUMB_OP32 (inst.instruction);
9545 inst.instruction |= Rd << 8;
9546 inst.instruction |= Rs << 16;
9547 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9548 _("shift value over 3 not allowed in thumb mode"));
9549 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9550 _("only LSL shift allowed in thumb mode"));
9551 encode_thumb32_shifted_operand (2);
9556 constraint (inst.instruction == T_MNEM_adds
9557 || inst.instruction == T_MNEM_subs,
9560 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9562 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9563 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9566 inst.instruction = (inst.instruction == T_MNEM_add
9568 inst.instruction |= (Rd << 4) | Rs;
9569 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9573 Rn = inst.operands[2].reg;
9574 constraint (inst.operands[2].shifted, _("unshifted register required"));
9576 /* We now have Rd, Rs, and Rn set to registers. */
9577 if (Rd > 7 || Rs > 7 || Rn > 7)
9579 /* Can't do this for SUB. */
9580 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9581 inst.instruction = T_OPCODE_ADD_HI;
9582 inst.instruction |= (Rd & 8) << 4;
9583 inst.instruction |= (Rd & 7);
9585 inst.instruction |= Rn << 3;
9587 inst.instruction |= Rs << 3;
9589 constraint (1, _("dest must overlap one source register"));
9593 inst.instruction = (inst.instruction == T_MNEM_add
9594 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9595 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9605 Rd = inst.operands[0].reg;
9606 reject_bad_reg (Rd);
9608 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9610 /* Defer to section relaxation. */
9611 inst.relax = inst.instruction;
9612 inst.instruction = THUMB_OP16 (inst.instruction);
9613 inst.instruction |= Rd << 4;
9615 else if (unified_syntax && inst.size_req != 2)
9617 /* Generate a 32-bit opcode. */
9618 inst.instruction = THUMB_OP32 (inst.instruction);
9619 inst.instruction |= Rd << 8;
9620 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9621 inst.reloc.pc_rel = 1;
9625 /* Generate a 16-bit opcode. */
9626 inst.instruction = THUMB_OP16 (inst.instruction);
9627 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9628 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9629 inst.reloc.pc_rel = 1;
9631 inst.instruction |= Rd << 4;
9635 /* Arithmetic instructions for which there is just one 16-bit
9636 instruction encoding, and it allows only two low registers.
9637 For maximal compatibility with ARM syntax, we allow three register
9638 operands even when Thumb-32 instructions are not available, as long
9639 as the first two are identical. For instance, both "sbc r0,r1" and
9640 "sbc r0,r0,r1" are allowed. */
9646 Rd = inst.operands[0].reg;
9647 Rs = (inst.operands[1].present
9648 ? inst.operands[1].reg /* Rd, Rs, foo */
9649 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9650 Rn = inst.operands[2].reg;
9652 reject_bad_reg (Rd);
9653 reject_bad_reg (Rs);
9654 if (inst.operands[2].isreg)
9655 reject_bad_reg (Rn);
9659 if (!inst.operands[2].isreg)
9661 /* For an immediate, we always generate a 32-bit opcode;
9662 section relaxation will shrink it later if possible. */
9663 inst.instruction = THUMB_OP32 (inst.instruction);
9664 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9665 inst.instruction |= Rd << 8;
9666 inst.instruction |= Rs << 16;
9667 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9673 /* See if we can do this with a 16-bit instruction. */
9674 if (THUMB_SETS_FLAGS (inst.instruction))
9675 narrow = !in_it_block ();
9677 narrow = in_it_block ();
9679 if (Rd > 7 || Rn > 7 || Rs > 7)
9681 if (inst.operands[2].shifted)
9683 if (inst.size_req == 4)
9689 inst.instruction = THUMB_OP16 (inst.instruction);
9690 inst.instruction |= Rd;
9691 inst.instruction |= Rn << 3;
9695 /* If we get here, it can't be done in 16 bits. */
9696 constraint (inst.operands[2].shifted
9697 && inst.operands[2].immisreg,
9698 _("shift must be constant"));
9699 inst.instruction = THUMB_OP32 (inst.instruction);
9700 inst.instruction |= Rd << 8;
9701 inst.instruction |= Rs << 16;
9702 encode_thumb32_shifted_operand (2);
9707 /* On its face this is a lie - the instruction does set the
9708 flags. However, the only supported mnemonic in this mode
9710 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9712 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9713 _("unshifted register required"));
9714 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9715 constraint (Rd != Rs,
9716 _("dest and source1 must be the same register"));
9718 inst.instruction = THUMB_OP16 (inst.instruction);
9719 inst.instruction |= Rd;
9720 inst.instruction |= Rn << 3;
9724 /* Similarly, but for instructions where the arithmetic operation is
9725 commutative, so we can allow either of them to be different from
9726 the destination operand in a 16-bit instruction. For instance, all
9727 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9734 Rd = inst.operands[0].reg;
9735 Rs = (inst.operands[1].present
9736 ? inst.operands[1].reg /* Rd, Rs, foo */
9737 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9738 Rn = inst.operands[2].reg;
9740 reject_bad_reg (Rd);
9741 reject_bad_reg (Rs);
9742 if (inst.operands[2].isreg)
9743 reject_bad_reg (Rn);
9747 if (!inst.operands[2].isreg)
9749 /* For an immediate, we always generate a 32-bit opcode;
9750 section relaxation will shrink it later if possible. */
9751 inst.instruction = THUMB_OP32 (inst.instruction);
9752 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9753 inst.instruction |= Rd << 8;
9754 inst.instruction |= Rs << 16;
9755 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9761 /* See if we can do this with a 16-bit instruction. */
9762 if (THUMB_SETS_FLAGS (inst.instruction))
9763 narrow = !in_it_block ();
9765 narrow = in_it_block ();
9767 if (Rd > 7 || Rn > 7 || Rs > 7)
9769 if (inst.operands[2].shifted)
9771 if (inst.size_req == 4)
9778 inst.instruction = THUMB_OP16 (inst.instruction);
9779 inst.instruction |= Rd;
9780 inst.instruction |= Rn << 3;
9785 inst.instruction = THUMB_OP16 (inst.instruction);
9786 inst.instruction |= Rd;
9787 inst.instruction |= Rs << 3;
9792 /* If we get here, it can't be done in 16 bits. */
9793 constraint (inst.operands[2].shifted
9794 && inst.operands[2].immisreg,
9795 _("shift must be constant"));
9796 inst.instruction = THUMB_OP32 (inst.instruction);
9797 inst.instruction |= Rd << 8;
9798 inst.instruction |= Rs << 16;
9799 encode_thumb32_shifted_operand (2);
9804 /* On its face this is a lie - the instruction does set the
9805 flags. However, the only supported mnemonic in this mode
9807 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9809 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9810 _("unshifted register required"));
9811 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9813 inst.instruction = THUMB_OP16 (inst.instruction);
9814 inst.instruction |= Rd;
9817 inst.instruction |= Rn << 3;
9819 inst.instruction |= Rs << 3;
9821 constraint (1, _("dest must overlap one source register"));
9828 if (inst.operands[0].present)
9830 constraint ((inst.instruction & 0xf0) != 0x40
9831 && inst.operands[0].imm > 0xf
9832 && inst.operands[0].imm < 0x0,
9833 _("bad barrier type"));
9834 inst.instruction |= inst.operands[0].imm;
9837 inst.instruction |= 0xf;
9844 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9845 constraint (msb > 32, _("bit-field extends past end of register"));
9846 /* The instruction encoding stores the LSB and MSB,
9847 not the LSB and width. */
9848 Rd = inst.operands[0].reg;
9849 reject_bad_reg (Rd);
9850 inst.instruction |= Rd << 8;
9851 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9852 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9853 inst.instruction |= msb - 1;
9862 Rd = inst.operands[0].reg;
9863 reject_bad_reg (Rd);
9865 /* #0 in second position is alternative syntax for bfc, which is
9866 the same instruction but with REG_PC in the Rm field. */
9867 if (!inst.operands[1].isreg)
9871 Rn = inst.operands[1].reg;
9872 reject_bad_reg (Rn);
9875 msb = inst.operands[2].imm + inst.operands[3].imm;
9876 constraint (msb > 32, _("bit-field extends past end of register"));
9877 /* The instruction encoding stores the LSB and MSB,
9878 not the LSB and width. */
9879 inst.instruction |= Rd << 8;
9880 inst.instruction |= Rn << 16;
9881 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9882 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9883 inst.instruction |= msb - 1;
9891 Rd = inst.operands[0].reg;
9892 Rn = inst.operands[1].reg;
9894 reject_bad_reg (Rd);
9895 reject_bad_reg (Rn);
9897 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9898 _("bit-field extends past end of register"));
9899 inst.instruction |= Rd << 8;
9900 inst.instruction |= Rn << 16;
9901 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9902 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9903 inst.instruction |= inst.operands[3].imm - 1;
9906 /* ARM V5 Thumb BLX (argument parse)
9907 BLX <target_addr> which is BLX(1)
9908 BLX <Rm> which is BLX(2)
9909 Unfortunately, there are two different opcodes for this mnemonic.
9910 So, the insns[].value is not used, and the code here zaps values
9911 into inst.instruction.
9913 ??? How to take advantage of the additional two bits of displacement
9914 available in Thumb32 mode? Need new relocation? */
9919 set_it_insn_type_last ();
9921 if (inst.operands[0].isreg)
9923 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9924 /* We have a register, so this is BLX(2). */
9925 inst.instruction |= inst.operands[0].reg << 3;
9929 /* No register. This must be BLX(1). */
9930 inst.instruction = 0xf000e800;
9931 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9943 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9947 /* Conditional branches inside IT blocks are encoded as unconditional
9954 if (cond != COND_ALWAYS)
9955 opcode = T_MNEM_bcond;
9957 opcode = inst.instruction;
9960 && (inst.size_req == 4
9961 || (inst.size_req != 2
9962 && (inst.operands[0].hasreloc
9963 || inst.reloc.exp.X_op == O_constant))))
9965 inst.instruction = THUMB_OP32(opcode);
9966 if (cond == COND_ALWAYS)
9967 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
9970 gas_assert (cond != 0xF);
9971 inst.instruction |= cond << 22;
9972 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
9977 inst.instruction = THUMB_OP16(opcode);
9978 if (cond == COND_ALWAYS)
9979 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
9982 inst.instruction |= cond << 8;
9983 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
9985 /* Allow section relaxation. */
9986 if (unified_syntax && inst.size_req != 2)
9987 inst.relax = opcode;
9989 inst.reloc.type = reloc;
9990 inst.reloc.pc_rel = 1;
9996 constraint (inst.cond != COND_ALWAYS,
9997 _("instruction is always unconditional"));
9998 if (inst.operands[0].present)
10000 constraint (inst.operands[0].imm > 255,
10001 _("immediate value out of range"));
10002 inst.instruction |= inst.operands[0].imm;
10003 set_it_insn_type (NEUTRAL_IT_INSN);
10008 do_t_branch23 (void)
10010 set_it_insn_type_last ();
10011 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10013 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10014 this file. We used to simply ignore the PLT reloc type here --
10015 the branch encoding is now needed to deal with TLSCALL relocs.
10016 So if we see a PLT reloc now, put it back to how it used to be to
10017 keep the preexisting behaviour. */
10018 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10019 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10021 #if defined(OBJ_COFF)
10022 /* If the destination of the branch is a defined symbol which does not have
10023 the THUMB_FUNC attribute, then we must be calling a function which has
10024 the (interfacearm) attribute. We look for the Thumb entry point to that
10025 function and change the branch to refer to that function instead. */
10026 if ( inst.reloc.exp.X_op == O_symbol
10027 && inst.reloc.exp.X_add_symbol != NULL
10028 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10029 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10030 inst.reloc.exp.X_add_symbol =
10031 find_real_start (inst.reloc.exp.X_add_symbol);
10038 set_it_insn_type_last ();
10039 inst.instruction |= inst.operands[0].reg << 3;
10040 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10041 should cause the alignment to be checked once it is known. This is
10042 because BX PC only works if the instruction is word aligned. */
10050 set_it_insn_type_last ();
10051 Rm = inst.operands[0].reg;
10052 reject_bad_reg (Rm);
10053 inst.instruction |= Rm << 16;
10062 Rd = inst.operands[0].reg;
10063 Rm = inst.operands[1].reg;
10065 reject_bad_reg (Rd);
10066 reject_bad_reg (Rm);
10068 inst.instruction |= Rd << 8;
10069 inst.instruction |= Rm << 16;
10070 inst.instruction |= Rm;
10076 set_it_insn_type (OUTSIDE_IT_INSN);
10077 inst.instruction |= inst.operands[0].imm;
10083 set_it_insn_type (OUTSIDE_IT_INSN);
10085 && (inst.operands[1].present || inst.size_req == 4)
10086 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10088 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10089 inst.instruction = 0xf3af8000;
10090 inst.instruction |= imod << 9;
10091 inst.instruction |= inst.operands[0].imm << 5;
10092 if (inst.operands[1].present)
10093 inst.instruction |= 0x100 | inst.operands[1].imm;
10097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10098 && (inst.operands[0].imm & 4),
10099 _("selected processor does not support 'A' form "
10100 "of this instruction"));
10101 constraint (inst.operands[1].present || inst.size_req == 4,
10102 _("Thumb does not support the 2-argument "
10103 "form of this instruction"));
10104 inst.instruction |= inst.operands[0].imm;
10108 /* THUMB CPY instruction (argument parse). */
10113 if (inst.size_req == 4)
10115 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10116 inst.instruction |= inst.operands[0].reg << 8;
10117 inst.instruction |= inst.operands[1].reg;
10121 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10122 inst.instruction |= (inst.operands[0].reg & 0x7);
10123 inst.instruction |= inst.operands[1].reg << 3;
10130 set_it_insn_type (OUTSIDE_IT_INSN);
10131 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10132 inst.instruction |= inst.operands[0].reg;
10133 inst.reloc.pc_rel = 1;
10134 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10140 inst.instruction |= inst.operands[0].imm;
10146 unsigned Rd, Rn, Rm;
10148 Rd = inst.operands[0].reg;
10149 Rn = (inst.operands[1].present
10150 ? inst.operands[1].reg : Rd);
10151 Rm = inst.operands[2].reg;
10153 reject_bad_reg (Rd);
10154 reject_bad_reg (Rn);
10155 reject_bad_reg (Rm);
10157 inst.instruction |= Rd << 8;
10158 inst.instruction |= Rn << 16;
10159 inst.instruction |= Rm;
10165 if (unified_syntax && inst.size_req == 4)
10166 inst.instruction = THUMB_OP32 (inst.instruction);
10168 inst.instruction = THUMB_OP16 (inst.instruction);
10174 unsigned int cond = inst.operands[0].imm;
10176 set_it_insn_type (IT_INSN);
10177 now_it.mask = (inst.instruction & 0xf) | 0x10;
10180 /* If the condition is a negative condition, invert the mask. */
10181 if ((cond & 0x1) == 0x0)
10183 unsigned int mask = inst.instruction & 0x000f;
10185 if ((mask & 0x7) == 0)
10186 /* no conversion needed */;
10187 else if ((mask & 0x3) == 0)
10189 else if ((mask & 0x1) == 0)
10194 inst.instruction &= 0xfff0;
10195 inst.instruction |= mask;
10198 inst.instruction |= cond << 4;
10201 /* Helper function used for both push/pop and ldm/stm. */
10203 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10207 load = (inst.instruction & (1 << 20)) != 0;
10209 if (mask & (1 << 13))
10210 inst.error = _("SP not allowed in register list");
10212 if ((mask & (1 << base)) != 0
10214 inst.error = _("having the base register in the register list when "
10215 "using write back is UNPREDICTABLE");
10219 if (mask & (1 << 15))
10221 if (mask & (1 << 14))
10222 inst.error = _("LR and PC should not both be in register list");
10224 set_it_insn_type_last ();
10229 if (mask & (1 << 15))
10230 inst.error = _("PC not allowed in register list");
10233 if ((mask & (mask - 1)) == 0)
10235 /* Single register transfers implemented as str/ldr. */
10238 if (inst.instruction & (1 << 23))
10239 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10241 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10245 if (inst.instruction & (1 << 23))
10246 inst.instruction = 0x00800000; /* ia -> [base] */
10248 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10251 inst.instruction |= 0xf8400000;
10253 inst.instruction |= 0x00100000;
10255 mask = ffs (mask) - 1;
10258 else if (writeback)
10259 inst.instruction |= WRITE_BACK;
10261 inst.instruction |= mask;
10262 inst.instruction |= base << 16;
10268 /* This really doesn't seem worth it. */
10269 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10270 _("expression too complex"));
10271 constraint (inst.operands[1].writeback,
10272 _("Thumb load/store multiple does not support {reglist}^"));
10274 if (unified_syntax)
10276 bfd_boolean narrow;
10280 /* See if we can use a 16-bit instruction. */
10281 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10282 && inst.size_req != 4
10283 && !(inst.operands[1].imm & ~0xff))
10285 mask = 1 << inst.operands[0].reg;
10287 if (inst.operands[0].reg <= 7)
10289 if (inst.instruction == T_MNEM_stmia
10290 ? inst.operands[0].writeback
10291 : (inst.operands[0].writeback
10292 == !(inst.operands[1].imm & mask)))
10294 if (inst.instruction == T_MNEM_stmia
10295 && (inst.operands[1].imm & mask)
10296 && (inst.operands[1].imm & (mask - 1)))
10297 as_warn (_("value stored for r%d is UNKNOWN"),
10298 inst.operands[0].reg);
10300 inst.instruction = THUMB_OP16 (inst.instruction);
10301 inst.instruction |= inst.operands[0].reg << 8;
10302 inst.instruction |= inst.operands[1].imm;
10305 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10307 /* This means 1 register in reg list one of 3 situations:
10308 1. Instruction is stmia, but without writeback.
10309 2. lmdia without writeback, but with Rn not in
10311 3. ldmia with writeback, but with Rn in reglist.
10312 Case 3 is UNPREDICTABLE behaviour, so we handle
10313 case 1 and 2 which can be converted into a 16-bit
10314 str or ldr. The SP cases are handled below. */
10315 unsigned long opcode;
10316 /* First, record an error for Case 3. */
10317 if (inst.operands[1].imm & mask
10318 && inst.operands[0].writeback)
10320 _("having the base register in the register list when "
10321 "using write back is UNPREDICTABLE");
10323 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10325 inst.instruction = THUMB_OP16 (opcode);
10326 inst.instruction |= inst.operands[0].reg << 3;
10327 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10331 else if (inst.operands[0] .reg == REG_SP)
10333 if (inst.operands[0].writeback)
10336 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10337 ? T_MNEM_push : T_MNEM_pop);
10338 inst.instruction |= inst.operands[1].imm;
10341 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10344 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10345 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10346 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10354 if (inst.instruction < 0xffff)
10355 inst.instruction = THUMB_OP32 (inst.instruction);
10357 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10358 inst.operands[0].writeback);
10363 constraint (inst.operands[0].reg > 7
10364 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10365 constraint (inst.instruction != T_MNEM_ldmia
10366 && inst.instruction != T_MNEM_stmia,
10367 _("Thumb-2 instruction only valid in unified syntax"));
10368 if (inst.instruction == T_MNEM_stmia)
10370 if (!inst.operands[0].writeback)
10371 as_warn (_("this instruction will write back the base register"));
10372 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10373 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10374 as_warn (_("value stored for r%d is UNKNOWN"),
10375 inst.operands[0].reg);
10379 if (!inst.operands[0].writeback
10380 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10381 as_warn (_("this instruction will write back the base register"));
10382 else if (inst.operands[0].writeback
10383 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10384 as_warn (_("this instruction will not write back the base register"));
10387 inst.instruction = THUMB_OP16 (inst.instruction);
10388 inst.instruction |= inst.operands[0].reg << 8;
10389 inst.instruction |= inst.operands[1].imm;
10396 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10397 || inst.operands[1].postind || inst.operands[1].writeback
10398 || inst.operands[1].immisreg || inst.operands[1].shifted
10399 || inst.operands[1].negative,
10402 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10404 inst.instruction |= inst.operands[0].reg << 12;
10405 inst.instruction |= inst.operands[1].reg << 16;
10406 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10412 if (!inst.operands[1].present)
10414 constraint (inst.operands[0].reg == REG_LR,
10415 _("r14 not allowed as first register "
10416 "when second register is omitted"));
10417 inst.operands[1].reg = inst.operands[0].reg + 1;
10419 constraint (inst.operands[0].reg == inst.operands[1].reg,
10422 inst.instruction |= inst.operands[0].reg << 12;
10423 inst.instruction |= inst.operands[1].reg << 8;
10424 inst.instruction |= inst.operands[2].reg << 16;
10430 unsigned long opcode;
10433 if (inst.operands[0].isreg
10434 && !inst.operands[0].preind
10435 && inst.operands[0].reg == REG_PC)
10436 set_it_insn_type_last ();
10438 opcode = inst.instruction;
10439 if (unified_syntax)
10441 if (!inst.operands[1].isreg)
10443 if (opcode <= 0xffff)
10444 inst.instruction = THUMB_OP32 (opcode);
10445 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10448 if (inst.operands[1].isreg
10449 && !inst.operands[1].writeback
10450 && !inst.operands[1].shifted && !inst.operands[1].postind
10451 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10452 && opcode <= 0xffff
10453 && inst.size_req != 4)
10455 /* Insn may have a 16-bit form. */
10456 Rn = inst.operands[1].reg;
10457 if (inst.operands[1].immisreg)
10459 inst.instruction = THUMB_OP16 (opcode);
10461 if (Rn <= 7 && inst.operands[1].imm <= 7)
10463 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10464 reject_bad_reg (inst.operands[1].imm);
10466 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10467 && opcode != T_MNEM_ldrsb)
10468 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10469 || (Rn == REG_SP && opcode == T_MNEM_str))
10476 if (inst.reloc.pc_rel)
10477 opcode = T_MNEM_ldr_pc2;
10479 opcode = T_MNEM_ldr_pc;
10483 if (opcode == T_MNEM_ldr)
10484 opcode = T_MNEM_ldr_sp;
10486 opcode = T_MNEM_str_sp;
10488 inst.instruction = inst.operands[0].reg << 8;
10492 inst.instruction = inst.operands[0].reg;
10493 inst.instruction |= inst.operands[1].reg << 3;
10495 inst.instruction |= THUMB_OP16 (opcode);
10496 if (inst.size_req == 2)
10497 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10499 inst.relax = opcode;
10503 /* Definitely a 32-bit variant. */
10505 /* Warning for Erratum 752419. */
10506 if (opcode == T_MNEM_ldr
10507 && inst.operands[0].reg == REG_SP
10508 && inst.operands[1].writeback == 1
10509 && !inst.operands[1].immisreg)
10511 if (no_cpu_selected ()
10512 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10513 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10514 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10515 as_warn (_("This instruction may be unpredictable "
10516 "if executed on M-profile cores "
10517 "with interrupts enabled."));
10520 /* Do some validations regarding addressing modes. */
10521 if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
10522 && opcode != T_MNEM_str)
10523 reject_bad_reg (inst.operands[1].imm);
10525 inst.instruction = THUMB_OP32 (opcode);
10526 inst.instruction |= inst.operands[0].reg << 12;
10527 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10531 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10533 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10535 /* Only [Rn,Rm] is acceptable. */
10536 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10537 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10538 || inst.operands[1].postind || inst.operands[1].shifted
10539 || inst.operands[1].negative,
10540 _("Thumb does not support this addressing mode"));
10541 inst.instruction = THUMB_OP16 (inst.instruction);
10545 inst.instruction = THUMB_OP16 (inst.instruction);
10546 if (!inst.operands[1].isreg)
10547 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10550 constraint (!inst.operands[1].preind
10551 || inst.operands[1].shifted
10552 || inst.operands[1].writeback,
10553 _("Thumb does not support this addressing mode"));
10554 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10556 constraint (inst.instruction & 0x0600,
10557 _("byte or halfword not valid for base register"));
10558 constraint (inst.operands[1].reg == REG_PC
10559 && !(inst.instruction & THUMB_LOAD_BIT),
10560 _("r15 based store not allowed"));
10561 constraint (inst.operands[1].immisreg,
10562 _("invalid base register for register offset"));
10564 if (inst.operands[1].reg == REG_PC)
10565 inst.instruction = T_OPCODE_LDR_PC;
10566 else if (inst.instruction & THUMB_LOAD_BIT)
10567 inst.instruction = T_OPCODE_LDR_SP;
10569 inst.instruction = T_OPCODE_STR_SP;
10571 inst.instruction |= inst.operands[0].reg << 8;
10572 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10576 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10577 if (!inst.operands[1].immisreg)
10579 /* Immediate offset. */
10580 inst.instruction |= inst.operands[0].reg;
10581 inst.instruction |= inst.operands[1].reg << 3;
10582 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10586 /* Register offset. */
10587 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10588 constraint (inst.operands[1].negative,
10589 _("Thumb does not support this addressing mode"));
10592 switch (inst.instruction)
10594 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10595 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10596 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10597 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10598 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10599 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10600 case 0x5600 /* ldrsb */:
10601 case 0x5e00 /* ldrsh */: break;
10605 inst.instruction |= inst.operands[0].reg;
10606 inst.instruction |= inst.operands[1].reg << 3;
10607 inst.instruction |= inst.operands[1].imm << 6;
10613 if (!inst.operands[1].present)
10615 inst.operands[1].reg = inst.operands[0].reg + 1;
10616 constraint (inst.operands[0].reg == REG_LR,
10617 _("r14 not allowed here"));
10619 inst.instruction |= inst.operands[0].reg << 12;
10620 inst.instruction |= inst.operands[1].reg << 8;
10621 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10627 inst.instruction |= inst.operands[0].reg << 12;
10628 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10634 unsigned Rd, Rn, Rm, Ra;
10636 Rd = inst.operands[0].reg;
10637 Rn = inst.operands[1].reg;
10638 Rm = inst.operands[2].reg;
10639 Ra = inst.operands[3].reg;
10641 reject_bad_reg (Rd);
10642 reject_bad_reg (Rn);
10643 reject_bad_reg (Rm);
10644 reject_bad_reg (Ra);
10646 inst.instruction |= Rd << 8;
10647 inst.instruction |= Rn << 16;
10648 inst.instruction |= Rm;
10649 inst.instruction |= Ra << 12;
10655 unsigned RdLo, RdHi, Rn, Rm;
10657 RdLo = inst.operands[0].reg;
10658 RdHi = inst.operands[1].reg;
10659 Rn = inst.operands[2].reg;
10660 Rm = inst.operands[3].reg;
10662 reject_bad_reg (RdLo);
10663 reject_bad_reg (RdHi);
10664 reject_bad_reg (Rn);
10665 reject_bad_reg (Rm);
10667 inst.instruction |= RdLo << 12;
10668 inst.instruction |= RdHi << 8;
10669 inst.instruction |= Rn << 16;
10670 inst.instruction |= Rm;
10674 do_t_mov_cmp (void)
10678 Rn = inst.operands[0].reg;
10679 Rm = inst.operands[1].reg;
10682 set_it_insn_type_last ();
10684 if (unified_syntax)
10686 int r0off = (inst.instruction == T_MNEM_mov
10687 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10688 unsigned long opcode;
10689 bfd_boolean narrow;
10690 bfd_boolean low_regs;
10692 low_regs = (Rn <= 7 && Rm <= 7);
10693 opcode = inst.instruction;
10694 if (in_it_block ())
10695 narrow = opcode != T_MNEM_movs;
10697 narrow = opcode != T_MNEM_movs || low_regs;
10698 if (inst.size_req == 4
10699 || inst.operands[1].shifted)
10702 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10703 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10704 && !inst.operands[1].shifted
10708 inst.instruction = T2_SUBS_PC_LR;
10712 if (opcode == T_MNEM_cmp)
10714 constraint (Rn == REG_PC, BAD_PC);
10717 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10719 warn_deprecated_sp (Rm);
10720 /* R15 was documented as a valid choice for Rm in ARMv6,
10721 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10722 tools reject R15, so we do too. */
10723 constraint (Rm == REG_PC, BAD_PC);
10726 reject_bad_reg (Rm);
10728 else if (opcode == T_MNEM_mov
10729 || opcode == T_MNEM_movs)
10731 if (inst.operands[1].isreg)
10733 if (opcode == T_MNEM_movs)
10735 reject_bad_reg (Rn);
10736 reject_bad_reg (Rm);
10740 /* This is mov.n. */
10741 if ((Rn == REG_SP || Rn == REG_PC)
10742 && (Rm == REG_SP || Rm == REG_PC))
10744 as_warn (_("Use of r%u as a source register is "
10745 "deprecated when r%u is the destination "
10746 "register."), Rm, Rn);
10751 /* This is mov.w. */
10752 constraint (Rn == REG_PC, BAD_PC);
10753 constraint (Rm == REG_PC, BAD_PC);
10754 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10758 reject_bad_reg (Rn);
10761 if (!inst.operands[1].isreg)
10763 /* Immediate operand. */
10764 if (!in_it_block () && opcode == T_MNEM_mov)
10766 if (low_regs && narrow)
10768 inst.instruction = THUMB_OP16 (opcode);
10769 inst.instruction |= Rn << 8;
10770 if (inst.size_req == 2)
10771 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10773 inst.relax = opcode;
10777 inst.instruction = THUMB_OP32 (inst.instruction);
10778 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10779 inst.instruction |= Rn << r0off;
10780 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10783 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10784 && (inst.instruction == T_MNEM_mov
10785 || inst.instruction == T_MNEM_movs))
10787 /* Register shifts are encoded as separate shift instructions. */
10788 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10790 if (in_it_block ())
10795 if (inst.size_req == 4)
10798 if (!low_regs || inst.operands[1].imm > 7)
10804 switch (inst.operands[1].shift_kind)
10807 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10810 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10813 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10816 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10822 inst.instruction = opcode;
10825 inst.instruction |= Rn;
10826 inst.instruction |= inst.operands[1].imm << 3;
10831 inst.instruction |= CONDS_BIT;
10833 inst.instruction |= Rn << 8;
10834 inst.instruction |= Rm << 16;
10835 inst.instruction |= inst.operands[1].imm;
10840 /* Some mov with immediate shift have narrow variants.
10841 Register shifts are handled above. */
10842 if (low_regs && inst.operands[1].shifted
10843 && (inst.instruction == T_MNEM_mov
10844 || inst.instruction == T_MNEM_movs))
10846 if (in_it_block ())
10847 narrow = (inst.instruction == T_MNEM_mov);
10849 narrow = (inst.instruction == T_MNEM_movs);
10854 switch (inst.operands[1].shift_kind)
10856 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10857 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10858 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10859 default: narrow = FALSE; break;
10865 inst.instruction |= Rn;
10866 inst.instruction |= Rm << 3;
10867 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10871 inst.instruction = THUMB_OP32 (inst.instruction);
10872 inst.instruction |= Rn << r0off;
10873 encode_thumb32_shifted_operand (1);
10877 switch (inst.instruction)
10880 inst.instruction = T_OPCODE_MOV_HR;
10881 inst.instruction |= (Rn & 0x8) << 4;
10882 inst.instruction |= (Rn & 0x7);
10883 inst.instruction |= Rm << 3;
10887 /* We know we have low registers at this point.
10888 Generate LSLS Rd, Rs, #0. */
10889 inst.instruction = T_OPCODE_LSL_I;
10890 inst.instruction |= Rn;
10891 inst.instruction |= Rm << 3;
10897 inst.instruction = T_OPCODE_CMP_LR;
10898 inst.instruction |= Rn;
10899 inst.instruction |= Rm << 3;
10903 inst.instruction = T_OPCODE_CMP_HR;
10904 inst.instruction |= (Rn & 0x8) << 4;
10905 inst.instruction |= (Rn & 0x7);
10906 inst.instruction |= Rm << 3;
10913 inst.instruction = THUMB_OP16 (inst.instruction);
10915 /* PR 10443: Do not silently ignore shifted operands. */
10916 constraint (inst.operands[1].shifted,
10917 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10919 if (inst.operands[1].isreg)
10921 if (Rn < 8 && Rm < 8)
10923 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10924 since a MOV instruction produces unpredictable results. */
10925 if (inst.instruction == T_OPCODE_MOV_I8)
10926 inst.instruction = T_OPCODE_ADD_I3;
10928 inst.instruction = T_OPCODE_CMP_LR;
10930 inst.instruction |= Rn;
10931 inst.instruction |= Rm << 3;
10935 if (inst.instruction == T_OPCODE_MOV_I8)
10936 inst.instruction = T_OPCODE_MOV_HR;
10938 inst.instruction = T_OPCODE_CMP_HR;
10944 constraint (Rn > 7,
10945 _("only lo regs allowed with immediate"));
10946 inst.instruction |= Rn << 8;
10947 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10958 top = (inst.instruction & 0x00800000) != 0;
10959 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10961 constraint (top, _(":lower16: not allowed this instruction"));
10962 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10964 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
10966 constraint (!top, _(":upper16: not allowed this instruction"));
10967 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
10970 Rd = inst.operands[0].reg;
10971 reject_bad_reg (Rd);
10973 inst.instruction |= Rd << 8;
10974 if (inst.reloc.type == BFD_RELOC_UNUSED)
10976 imm = inst.reloc.exp.X_add_number;
10977 inst.instruction |= (imm & 0xf000) << 4;
10978 inst.instruction |= (imm & 0x0800) << 15;
10979 inst.instruction |= (imm & 0x0700) << 4;
10980 inst.instruction |= (imm & 0x00ff);
10985 do_t_mvn_tst (void)
10989 Rn = inst.operands[0].reg;
10990 Rm = inst.operands[1].reg;
10992 if (inst.instruction == T_MNEM_cmp
10993 || inst.instruction == T_MNEM_cmn)
10994 constraint (Rn == REG_PC, BAD_PC);
10996 reject_bad_reg (Rn);
10997 reject_bad_reg (Rm);
10999 if (unified_syntax)
11001 int r0off = (inst.instruction == T_MNEM_mvn
11002 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11003 bfd_boolean narrow;
11005 if (inst.size_req == 4
11006 || inst.instruction > 0xffff
11007 || inst.operands[1].shifted
11008 || Rn > 7 || Rm > 7)
11010 else if (inst.instruction == T_MNEM_cmn)
11012 else if (THUMB_SETS_FLAGS (inst.instruction))
11013 narrow = !in_it_block ();
11015 narrow = in_it_block ();
11017 if (!inst.operands[1].isreg)
11019 /* For an immediate, we always generate a 32-bit opcode;
11020 section relaxation will shrink it later if possible. */
11021 if (inst.instruction < 0xffff)
11022 inst.instruction = THUMB_OP32 (inst.instruction);
11023 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11024 inst.instruction |= Rn << r0off;
11025 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11029 /* See if we can do this with a 16-bit instruction. */
11032 inst.instruction = THUMB_OP16 (inst.instruction);
11033 inst.instruction |= Rn;
11034 inst.instruction |= Rm << 3;
11038 constraint (inst.operands[1].shifted
11039 && inst.operands[1].immisreg,
11040 _("shift must be constant"));
11041 if (inst.instruction < 0xffff)
11042 inst.instruction = THUMB_OP32 (inst.instruction);
11043 inst.instruction |= Rn << r0off;
11044 encode_thumb32_shifted_operand (1);
11050 constraint (inst.instruction > 0xffff
11051 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11052 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11053 _("unshifted register required"));
11054 constraint (Rn > 7 || Rm > 7,
11057 inst.instruction = THUMB_OP16 (inst.instruction);
11058 inst.instruction |= Rn;
11059 inst.instruction |= Rm << 3;
11068 if (do_vfp_nsyn_mrs () == SUCCESS)
11071 Rd = inst.operands[0].reg;
11072 reject_bad_reg (Rd);
11073 inst.instruction |= Rd << 8;
11075 if (inst.operands[1].isreg)
11077 unsigned br = inst.operands[1].reg;
11078 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11079 as_bad (_("bad register for mrs"));
11081 inst.instruction |= br & (0xf << 16);
11082 inst.instruction |= (br & 0x300) >> 4;
11083 inst.instruction |= (br & SPSR_BIT) >> 2;
11087 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11089 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11090 constraint (flags != 0, _("selected processor does not support "
11091 "requested special purpose register"));
11093 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11095 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11096 _("'APSR', 'CPSR' or 'SPSR' expected"));
11098 inst.instruction |= (flags & SPSR_BIT) >> 2;
11099 inst.instruction |= inst.operands[1].imm & 0xff;
11100 inst.instruction |= 0xf0000;
11110 if (do_vfp_nsyn_msr () == SUCCESS)
11113 constraint (!inst.operands[1].isreg,
11114 _("Thumb encoding does not support an immediate here"));
11116 if (inst.operands[0].isreg)
11117 flags = (int)(inst.operands[0].reg);
11119 flags = inst.operands[0].imm;
11121 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11123 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11125 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11126 && (bits & ~(PSR_s | PSR_f)) != 0)
11127 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11129 _("selected processor does not support requested special "
11130 "purpose register"));
11133 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11134 "requested special purpose register"));
11136 Rn = inst.operands[1].reg;
11137 reject_bad_reg (Rn);
11139 inst.instruction |= (flags & SPSR_BIT) >> 2;
11140 inst.instruction |= (flags & 0xf0000) >> 8;
11141 inst.instruction |= (flags & 0x300) >> 4;
11142 inst.instruction |= (flags & 0xff);
11143 inst.instruction |= Rn << 16;
11149 bfd_boolean narrow;
11150 unsigned Rd, Rn, Rm;
11152 if (!inst.operands[2].present)
11153 inst.operands[2].reg = inst.operands[0].reg;
11155 Rd = inst.operands[0].reg;
11156 Rn = inst.operands[1].reg;
11157 Rm = inst.operands[2].reg;
11159 if (unified_syntax)
11161 if (inst.size_req == 4
11167 else if (inst.instruction == T_MNEM_muls)
11168 narrow = !in_it_block ();
11170 narrow = in_it_block ();
11174 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11175 constraint (Rn > 7 || Rm > 7,
11182 /* 16-bit MULS/Conditional MUL. */
11183 inst.instruction = THUMB_OP16 (inst.instruction);
11184 inst.instruction |= Rd;
11187 inst.instruction |= Rm << 3;
11189 inst.instruction |= Rn << 3;
11191 constraint (1, _("dest must overlap one source register"));
11195 constraint (inst.instruction != T_MNEM_mul,
11196 _("Thumb-2 MUL must not set flags"));
11198 inst.instruction = THUMB_OP32 (inst.instruction);
11199 inst.instruction |= Rd << 8;
11200 inst.instruction |= Rn << 16;
11201 inst.instruction |= Rm << 0;
11203 reject_bad_reg (Rd);
11204 reject_bad_reg (Rn);
11205 reject_bad_reg (Rm);
11212 unsigned RdLo, RdHi, Rn, Rm;
11214 RdLo = inst.operands[0].reg;
11215 RdHi = inst.operands[1].reg;
11216 Rn = inst.operands[2].reg;
11217 Rm = inst.operands[3].reg;
11219 reject_bad_reg (RdLo);
11220 reject_bad_reg (RdHi);
11221 reject_bad_reg (Rn);
11222 reject_bad_reg (Rm);
11224 inst.instruction |= RdLo << 12;
11225 inst.instruction |= RdHi << 8;
11226 inst.instruction |= Rn << 16;
11227 inst.instruction |= Rm;
11230 as_tsktsk (_("rdhi and rdlo must be different"));
11236 set_it_insn_type (NEUTRAL_IT_INSN);
11238 if (unified_syntax)
11240 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11242 inst.instruction = THUMB_OP32 (inst.instruction);
11243 inst.instruction |= inst.operands[0].imm;
11247 /* PR9722: Check for Thumb2 availability before
11248 generating a thumb2 nop instruction. */
11249 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11251 inst.instruction = THUMB_OP16 (inst.instruction);
11252 inst.instruction |= inst.operands[0].imm << 4;
11255 inst.instruction = 0x46c0;
11260 constraint (inst.operands[0].present,
11261 _("Thumb does not support NOP with hints"));
11262 inst.instruction = 0x46c0;
11269 if (unified_syntax)
11271 bfd_boolean narrow;
11273 if (THUMB_SETS_FLAGS (inst.instruction))
11274 narrow = !in_it_block ();
11276 narrow = in_it_block ();
11277 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11279 if (inst.size_req == 4)
11284 inst.instruction = THUMB_OP32 (inst.instruction);
11285 inst.instruction |= inst.operands[0].reg << 8;
11286 inst.instruction |= inst.operands[1].reg << 16;
11290 inst.instruction = THUMB_OP16 (inst.instruction);
11291 inst.instruction |= inst.operands[0].reg;
11292 inst.instruction |= inst.operands[1].reg << 3;
11297 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11299 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11301 inst.instruction = THUMB_OP16 (inst.instruction);
11302 inst.instruction |= inst.operands[0].reg;
11303 inst.instruction |= inst.operands[1].reg << 3;
11312 Rd = inst.operands[0].reg;
11313 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11315 reject_bad_reg (Rd);
11316 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11317 reject_bad_reg (Rn);
11319 inst.instruction |= Rd << 8;
11320 inst.instruction |= Rn << 16;
11322 if (!inst.operands[2].isreg)
11324 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11325 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11331 Rm = inst.operands[2].reg;
11332 reject_bad_reg (Rm);
11334 constraint (inst.operands[2].shifted
11335 && inst.operands[2].immisreg,
11336 _("shift must be constant"));
11337 encode_thumb32_shifted_operand (2);
11344 unsigned Rd, Rn, Rm;
11346 Rd = inst.operands[0].reg;
11347 Rn = inst.operands[1].reg;
11348 Rm = inst.operands[2].reg;
11350 reject_bad_reg (Rd);
11351 reject_bad_reg (Rn);
11352 reject_bad_reg (Rm);
11354 inst.instruction |= Rd << 8;
11355 inst.instruction |= Rn << 16;
11356 inst.instruction |= Rm;
11357 if (inst.operands[3].present)
11359 unsigned int val = inst.reloc.exp.X_add_number;
11360 constraint (inst.reloc.exp.X_op != O_constant,
11361 _("expression too complex"));
11362 inst.instruction |= (val & 0x1c) << 10;
11363 inst.instruction |= (val & 0x03) << 6;
11370 if (!inst.operands[3].present)
11374 inst.instruction &= ~0x00000020;
11376 /* PR 10168. Swap the Rm and Rn registers. */
11377 Rtmp = inst.operands[1].reg;
11378 inst.operands[1].reg = inst.operands[2].reg;
11379 inst.operands[2].reg = Rtmp;
11387 if (inst.operands[0].immisreg)
11388 reject_bad_reg (inst.operands[0].imm);
11390 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11394 do_t_push_pop (void)
11398 constraint (inst.operands[0].writeback,
11399 _("push/pop do not support {reglist}^"));
11400 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11401 _("expression too complex"));
11403 mask = inst.operands[0].imm;
11404 if ((mask & ~0xff) == 0)
11405 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11406 else if ((inst.instruction == T_MNEM_push
11407 && (mask & ~0xff) == 1 << REG_LR)
11408 || (inst.instruction == T_MNEM_pop
11409 && (mask & ~0xff) == 1 << REG_PC))
11411 inst.instruction = THUMB_OP16 (inst.instruction);
11412 inst.instruction |= THUMB_PP_PC_LR;
11413 inst.instruction |= mask & 0xff;
11415 else if (unified_syntax)
11417 inst.instruction = THUMB_OP32 (inst.instruction);
11418 encode_thumb2_ldmstm (13, mask, TRUE);
11422 inst.error = _("invalid register list to push/pop instruction");
11432 Rd = inst.operands[0].reg;
11433 Rm = inst.operands[1].reg;
11435 reject_bad_reg (Rd);
11436 reject_bad_reg (Rm);
11438 inst.instruction |= Rd << 8;
11439 inst.instruction |= Rm << 16;
11440 inst.instruction |= Rm;
11448 Rd = inst.operands[0].reg;
11449 Rm = inst.operands[1].reg;
11451 reject_bad_reg (Rd);
11452 reject_bad_reg (Rm);
11454 if (Rd <= 7 && Rm <= 7
11455 && inst.size_req != 4)
11457 inst.instruction = THUMB_OP16 (inst.instruction);
11458 inst.instruction |= Rd;
11459 inst.instruction |= Rm << 3;
11461 else if (unified_syntax)
11463 inst.instruction = THUMB_OP32 (inst.instruction);
11464 inst.instruction |= Rd << 8;
11465 inst.instruction |= Rm << 16;
11466 inst.instruction |= Rm;
11469 inst.error = BAD_HIREG;
11477 Rd = inst.operands[0].reg;
11478 Rm = inst.operands[1].reg;
11480 reject_bad_reg (Rd);
11481 reject_bad_reg (Rm);
11483 inst.instruction |= Rd << 8;
11484 inst.instruction |= Rm;
11492 Rd = inst.operands[0].reg;
11493 Rs = (inst.operands[1].present
11494 ? inst.operands[1].reg /* Rd, Rs, foo */
11495 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11497 reject_bad_reg (Rd);
11498 reject_bad_reg (Rs);
11499 if (inst.operands[2].isreg)
11500 reject_bad_reg (inst.operands[2].reg);
11502 inst.instruction |= Rd << 8;
11503 inst.instruction |= Rs << 16;
11504 if (!inst.operands[2].isreg)
11506 bfd_boolean narrow;
11508 if ((inst.instruction & 0x00100000) != 0)
11509 narrow = !in_it_block ();
11511 narrow = in_it_block ();
11513 if (Rd > 7 || Rs > 7)
11516 if (inst.size_req == 4 || !unified_syntax)
11519 if (inst.reloc.exp.X_op != O_constant
11520 || inst.reloc.exp.X_add_number != 0)
11523 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11524 relaxation, but it doesn't seem worth the hassle. */
11527 inst.reloc.type = BFD_RELOC_UNUSED;
11528 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11529 inst.instruction |= Rs << 3;
11530 inst.instruction |= Rd;
11534 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11535 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11539 encode_thumb32_shifted_operand (2);
11545 set_it_insn_type (OUTSIDE_IT_INSN);
11546 if (inst.operands[0].imm)
11547 inst.instruction |= 0x8;
11553 if (!inst.operands[1].present)
11554 inst.operands[1].reg = inst.operands[0].reg;
11556 if (unified_syntax)
11558 bfd_boolean narrow;
11561 switch (inst.instruction)
11564 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11566 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11568 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11570 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11574 if (THUMB_SETS_FLAGS (inst.instruction))
11575 narrow = !in_it_block ();
11577 narrow = in_it_block ();
11578 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11580 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11582 if (inst.operands[2].isreg
11583 && (inst.operands[1].reg != inst.operands[0].reg
11584 || inst.operands[2].reg > 7))
11586 if (inst.size_req == 4)
11589 reject_bad_reg (inst.operands[0].reg);
11590 reject_bad_reg (inst.operands[1].reg);
11594 if (inst.operands[2].isreg)
11596 reject_bad_reg (inst.operands[2].reg);
11597 inst.instruction = THUMB_OP32 (inst.instruction);
11598 inst.instruction |= inst.operands[0].reg << 8;
11599 inst.instruction |= inst.operands[1].reg << 16;
11600 inst.instruction |= inst.operands[2].reg;
11602 /* PR 12854: Error on extraneous shifts. */
11603 constraint (inst.operands[2].shifted,
11604 _("extraneous shift as part of operand to shift insn"));
11608 inst.operands[1].shifted = 1;
11609 inst.operands[1].shift_kind = shift_kind;
11610 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11611 ? T_MNEM_movs : T_MNEM_mov);
11612 inst.instruction |= inst.operands[0].reg << 8;
11613 encode_thumb32_shifted_operand (1);
11614 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11615 inst.reloc.type = BFD_RELOC_UNUSED;
11620 if (inst.operands[2].isreg)
11622 switch (shift_kind)
11624 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11625 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11626 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11627 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11631 inst.instruction |= inst.operands[0].reg;
11632 inst.instruction |= inst.operands[2].reg << 3;
11634 /* PR 12854: Error on extraneous shifts. */
11635 constraint (inst.operands[2].shifted,
11636 _("extraneous shift as part of operand to shift insn"));
11640 switch (shift_kind)
11642 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11643 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11644 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11647 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11648 inst.instruction |= inst.operands[0].reg;
11649 inst.instruction |= inst.operands[1].reg << 3;
11655 constraint (inst.operands[0].reg > 7
11656 || inst.operands[1].reg > 7, BAD_HIREG);
11657 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11659 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11661 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11662 constraint (inst.operands[0].reg != inst.operands[1].reg,
11663 _("source1 and dest must be same register"));
11665 switch (inst.instruction)
11667 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11668 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11669 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11670 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11674 inst.instruction |= inst.operands[0].reg;
11675 inst.instruction |= inst.operands[2].reg << 3;
11677 /* PR 12854: Error on extraneous shifts. */
11678 constraint (inst.operands[2].shifted,
11679 _("extraneous shift as part of operand to shift insn"));
11683 switch (inst.instruction)
11685 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11686 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11687 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11688 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11691 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11692 inst.instruction |= inst.operands[0].reg;
11693 inst.instruction |= inst.operands[1].reg << 3;
11701 unsigned Rd, Rn, Rm;
11703 Rd = inst.operands[0].reg;
11704 Rn = inst.operands[1].reg;
11705 Rm = inst.operands[2].reg;
11707 reject_bad_reg (Rd);
11708 reject_bad_reg (Rn);
11709 reject_bad_reg (Rm);
11711 inst.instruction |= Rd << 8;
11712 inst.instruction |= Rn << 16;
11713 inst.instruction |= Rm;
11719 unsigned Rd, Rn, Rm;
11721 Rd = inst.operands[0].reg;
11722 Rm = inst.operands[1].reg;
11723 Rn = inst.operands[2].reg;
11725 reject_bad_reg (Rd);
11726 reject_bad_reg (Rn);
11727 reject_bad_reg (Rm);
11729 inst.instruction |= Rd << 8;
11730 inst.instruction |= Rn << 16;
11731 inst.instruction |= Rm;
11737 unsigned int value = inst.reloc.exp.X_add_number;
11738 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11739 _("SMC is not permitted on this architecture"));
11740 constraint (inst.reloc.exp.X_op != O_constant,
11741 _("expression too complex"));
11742 inst.reloc.type = BFD_RELOC_UNUSED;
11743 inst.instruction |= (value & 0xf000) >> 12;
11744 inst.instruction |= (value & 0x0ff0);
11745 inst.instruction |= (value & 0x000f) << 16;
11751 unsigned int value = inst.reloc.exp.X_add_number;
11753 inst.reloc.type = BFD_RELOC_UNUSED;
11754 inst.instruction |= (value & 0x0fff);
11755 inst.instruction |= (value & 0xf000) << 4;
11759 do_t_ssat_usat (int bias)
11763 Rd = inst.operands[0].reg;
11764 Rn = inst.operands[2].reg;
11766 reject_bad_reg (Rd);
11767 reject_bad_reg (Rn);
11769 inst.instruction |= Rd << 8;
11770 inst.instruction |= inst.operands[1].imm - bias;
11771 inst.instruction |= Rn << 16;
11773 if (inst.operands[3].present)
11775 offsetT shift_amount = inst.reloc.exp.X_add_number;
11777 inst.reloc.type = BFD_RELOC_UNUSED;
11779 constraint (inst.reloc.exp.X_op != O_constant,
11780 _("expression too complex"));
11782 if (shift_amount != 0)
11784 constraint (shift_amount > 31,
11785 _("shift expression is too large"));
11787 if (inst.operands[3].shift_kind == SHIFT_ASR)
11788 inst.instruction |= 0x00200000; /* sh bit. */
11790 inst.instruction |= (shift_amount & 0x1c) << 10;
11791 inst.instruction |= (shift_amount & 0x03) << 6;
11799 do_t_ssat_usat (1);
11807 Rd = inst.operands[0].reg;
11808 Rn = inst.operands[2].reg;
11810 reject_bad_reg (Rd);
11811 reject_bad_reg (Rn);
11813 inst.instruction |= Rd << 8;
11814 inst.instruction |= inst.operands[1].imm - 1;
11815 inst.instruction |= Rn << 16;
11821 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11822 || inst.operands[2].postind || inst.operands[2].writeback
11823 || inst.operands[2].immisreg || inst.operands[2].shifted
11824 || inst.operands[2].negative,
11827 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11829 inst.instruction |= inst.operands[0].reg << 8;
11830 inst.instruction |= inst.operands[1].reg << 12;
11831 inst.instruction |= inst.operands[2].reg << 16;
11832 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11838 if (!inst.operands[2].present)
11839 inst.operands[2].reg = inst.operands[1].reg + 1;
11841 constraint (inst.operands[0].reg == inst.operands[1].reg
11842 || inst.operands[0].reg == inst.operands[2].reg
11843 || inst.operands[0].reg == inst.operands[3].reg,
11846 inst.instruction |= inst.operands[0].reg;
11847 inst.instruction |= inst.operands[1].reg << 12;
11848 inst.instruction |= inst.operands[2].reg << 8;
11849 inst.instruction |= inst.operands[3].reg << 16;
11855 unsigned Rd, Rn, Rm;
11857 Rd = inst.operands[0].reg;
11858 Rn = inst.operands[1].reg;
11859 Rm = inst.operands[2].reg;
11861 reject_bad_reg (Rd);
11862 reject_bad_reg (Rn);
11863 reject_bad_reg (Rm);
11865 inst.instruction |= Rd << 8;
11866 inst.instruction |= Rn << 16;
11867 inst.instruction |= Rm;
11868 inst.instruction |= inst.operands[3].imm << 4;
11876 Rd = inst.operands[0].reg;
11877 Rm = inst.operands[1].reg;
11879 reject_bad_reg (Rd);
11880 reject_bad_reg (Rm);
11882 if (inst.instruction <= 0xffff
11883 && inst.size_req != 4
11884 && Rd <= 7 && Rm <= 7
11885 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11887 inst.instruction = THUMB_OP16 (inst.instruction);
11888 inst.instruction |= Rd;
11889 inst.instruction |= Rm << 3;
11891 else if (unified_syntax)
11893 if (inst.instruction <= 0xffff)
11894 inst.instruction = THUMB_OP32 (inst.instruction);
11895 inst.instruction |= Rd << 8;
11896 inst.instruction |= Rm;
11897 inst.instruction |= inst.operands[2].imm << 4;
11901 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11902 _("Thumb encoding does not support rotation"));
11903 constraint (1, BAD_HIREG);
11910 /* We have to do the following check manually as ARM_EXT_OS only applies
11912 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11914 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11915 /* This only applies to the v6m howver, not later architectures. */
11916 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11917 as_bad (_("SVC is not permitted on this architecture"));
11918 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11921 inst.reloc.type = BFD_RELOC_ARM_SWI;
11930 half = (inst.instruction & 0x10) != 0;
11931 set_it_insn_type_last ();
11932 constraint (inst.operands[0].immisreg,
11933 _("instruction requires register index"));
11935 Rn = inst.operands[0].reg;
11936 Rm = inst.operands[0].imm;
11938 constraint (Rn == REG_SP, BAD_SP);
11939 reject_bad_reg (Rm);
11941 constraint (!half && inst.operands[0].shifted,
11942 _("instruction does not allow shifted index"));
11943 inst.instruction |= (Rn << 16) | Rm;
11949 do_t_ssat_usat (0);
11957 Rd = inst.operands[0].reg;
11958 Rn = inst.operands[2].reg;
11960 reject_bad_reg (Rd);
11961 reject_bad_reg (Rn);
11963 inst.instruction |= Rd << 8;
11964 inst.instruction |= inst.operands[1].imm;
11965 inst.instruction |= Rn << 16;
11968 /* Neon instruction encoder helpers. */
11970 /* Encodings for the different types for various Neon opcodes. */
11972 /* An "invalid" code for the following tables. */
11975 struct neon_tab_entry
11978 unsigned float_or_poly;
11979 unsigned scalar_or_imm;
11982 /* Map overloaded Neon opcodes to their respective encodings. */
11983 #define NEON_ENC_TAB \
11984 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11985 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11986 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11987 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11988 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11989 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11990 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11991 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11992 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11993 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11994 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11995 /* Register variants of the following two instructions are encoded as
11996 vcge / vcgt with the operands reversed. */ \
11997 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11998 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11999 X(vfma, N_INV, 0x0000c10, N_INV), \
12000 X(vfms, N_INV, 0x0200c10, N_INV), \
12001 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12002 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12003 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12004 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12005 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12006 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12007 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12008 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12009 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12010 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12011 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12012 X(vshl, 0x0000400, N_INV, 0x0800510), \
12013 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12014 X(vand, 0x0000110, N_INV, 0x0800030), \
12015 X(vbic, 0x0100110, N_INV, 0x0800030), \
12016 X(veor, 0x1000110, N_INV, N_INV), \
12017 X(vorn, 0x0300110, N_INV, 0x0800010), \
12018 X(vorr, 0x0200110, N_INV, 0x0800010), \
12019 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12020 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12021 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12022 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12023 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12024 X(vst1, 0x0000000, 0x0800000, N_INV), \
12025 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12026 X(vst2, 0x0000100, 0x0800100, N_INV), \
12027 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12028 X(vst3, 0x0000200, 0x0800200, N_INV), \
12029 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12030 X(vst4, 0x0000300, 0x0800300, N_INV), \
12031 X(vmovn, 0x1b20200, N_INV, N_INV), \
12032 X(vtrn, 0x1b20080, N_INV, N_INV), \
12033 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12034 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12035 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12036 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12037 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12038 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12039 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12040 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12041 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12042 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12043 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12047 #define X(OPC,I,F,S) N_MNEM_##OPC
12052 static const struct neon_tab_entry neon_enc_tab[] =
12054 #define X(OPC,I,F,S) { (I), (F), (S) }
12059 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12060 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12061 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12062 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12063 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12064 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12065 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12066 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12067 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12068 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12069 #define NEON_ENC_SINGLE_(X) \
12070 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12071 #define NEON_ENC_DOUBLE_(X) \
12072 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12074 #define NEON_ENCODE(type, inst) \
12077 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12078 inst.is_neon = 1; \
12082 #define check_neon_suffixes \
12085 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12087 as_bad (_("invalid neon suffix for non neon instruction")); \
12093 /* Define shapes for instruction operands. The following mnemonic characters
12094 are used in this table:
12096 F - VFP S<n> register
12097 D - Neon D<n> register
12098 Q - Neon Q<n> register
12102 L - D<n> register list
12104 This table is used to generate various data:
12105 - enumerations of the form NS_DDR to be used as arguments to
12107 - a table classifying shapes into single, double, quad, mixed.
12108 - a table used to drive neon_select_shape. */
12110 #define NEON_SHAPE_DEF \
12111 X(3, (D, D, D), DOUBLE), \
12112 X(3, (Q, Q, Q), QUAD), \
12113 X(3, (D, D, I), DOUBLE), \
12114 X(3, (Q, Q, I), QUAD), \
12115 X(3, (D, D, S), DOUBLE), \
12116 X(3, (Q, Q, S), QUAD), \
12117 X(2, (D, D), DOUBLE), \
12118 X(2, (Q, Q), QUAD), \
12119 X(2, (D, S), DOUBLE), \
12120 X(2, (Q, S), QUAD), \
12121 X(2, (D, R), DOUBLE), \
12122 X(2, (Q, R), QUAD), \
12123 X(2, (D, I), DOUBLE), \
12124 X(2, (Q, I), QUAD), \
12125 X(3, (D, L, D), DOUBLE), \
12126 X(2, (D, Q), MIXED), \
12127 X(2, (Q, D), MIXED), \
12128 X(3, (D, Q, I), MIXED), \
12129 X(3, (Q, D, I), MIXED), \
12130 X(3, (Q, D, D), MIXED), \
12131 X(3, (D, Q, Q), MIXED), \
12132 X(3, (Q, Q, D), MIXED), \
12133 X(3, (Q, D, S), MIXED), \
12134 X(3, (D, Q, S), MIXED), \
12135 X(4, (D, D, D, I), DOUBLE), \
12136 X(4, (Q, Q, Q, I), QUAD), \
12137 X(2, (F, F), SINGLE), \
12138 X(3, (F, F, F), SINGLE), \
12139 X(2, (F, I), SINGLE), \
12140 X(2, (F, D), MIXED), \
12141 X(2, (D, F), MIXED), \
12142 X(3, (F, F, I), MIXED), \
12143 X(4, (R, R, F, F), SINGLE), \
12144 X(4, (F, F, R, R), SINGLE), \
12145 X(3, (D, R, R), DOUBLE), \
12146 X(3, (R, R, D), DOUBLE), \
12147 X(2, (S, R), SINGLE), \
12148 X(2, (R, S), SINGLE), \
12149 X(2, (F, R), SINGLE), \
12150 X(2, (R, F), SINGLE)
12152 #define S2(A,B) NS_##A##B
12153 #define S3(A,B,C) NS_##A##B##C
12154 #define S4(A,B,C,D) NS_##A##B##C##D
12156 #define X(N, L, C) S##N L
12169 enum neon_shape_class
12177 #define X(N, L, C) SC_##C
12179 static enum neon_shape_class neon_shape_class[] =
12197 /* Register widths of above. */
12198 static unsigned neon_shape_el_size[] =
12209 struct neon_shape_info
12212 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12215 #define S2(A,B) { SE_##A, SE_##B }
12216 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12217 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12219 #define X(N, L, C) { N, S##N L }
12221 static struct neon_shape_info neon_shape_tab[] =
12231 /* Bit masks used in type checking given instructions.
12232 'N_EQK' means the type must be the same as (or based on in some way) the key
12233 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12234 set, various other bits can be set as well in order to modify the meaning of
12235 the type constraint. */
12237 enum neon_type_mask
12260 N_KEY = 0x1000000, /* Key element (main type specifier). */
12261 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12262 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12263 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12264 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12265 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12266 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12267 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12268 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12269 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12271 N_MAX_NONSPECIAL = N_F64
12274 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12276 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12277 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12278 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12279 #define N_SUF_32 (N_SU_32 | N_F32)
12280 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12281 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12283 /* Pass this as the first type argument to neon_check_type to ignore types
12285 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12287 /* Select a "shape" for the current instruction (describing register types or
12288 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12289 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12290 function of operand parsing, so this function doesn't need to be called.
12291 Shapes should be listed in order of decreasing length. */
12293 static enum neon_shape
12294 neon_select_shape (enum neon_shape shape, ...)
12297 enum neon_shape first_shape = shape;
12299 /* Fix missing optional operands. FIXME: we don't know at this point how
12300 many arguments we should have, so this makes the assumption that we have
12301 > 1. This is true of all current Neon opcodes, I think, but may not be
12302 true in the future. */
12303 if (!inst.operands[1].present)
12304 inst.operands[1] = inst.operands[0];
12306 va_start (ap, shape);
12308 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12313 for (j = 0; j < neon_shape_tab[shape].els; j++)
12315 if (!inst.operands[j].present)
12321 switch (neon_shape_tab[shape].el[j])
12324 if (!(inst.operands[j].isreg
12325 && inst.operands[j].isvec
12326 && inst.operands[j].issingle
12327 && !inst.operands[j].isquad))
12332 if (!(inst.operands[j].isreg
12333 && inst.operands[j].isvec
12334 && !inst.operands[j].isquad
12335 && !inst.operands[j].issingle))
12340 if (!(inst.operands[j].isreg
12341 && !inst.operands[j].isvec))
12346 if (!(inst.operands[j].isreg
12347 && inst.operands[j].isvec
12348 && inst.operands[j].isquad
12349 && !inst.operands[j].issingle))
12354 if (!(!inst.operands[j].isreg
12355 && !inst.operands[j].isscalar))
12360 if (!(!inst.operands[j].isreg
12361 && inst.operands[j].isscalar))
12377 if (shape == NS_NULL && first_shape != NS_NULL)
12378 first_error (_("invalid instruction shape"));
12383 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12384 means the Q bit should be set). */
12387 neon_quad (enum neon_shape shape)
12389 return neon_shape_class[shape] == SC_QUAD;
12393 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12396 /* Allow modification to be made to types which are constrained to be
12397 based on the key element, based on bits set alongside N_EQK. */
12398 if ((typebits & N_EQK) != 0)
12400 if ((typebits & N_HLF) != 0)
12402 else if ((typebits & N_DBL) != 0)
12404 if ((typebits & N_SGN) != 0)
12405 *g_type = NT_signed;
12406 else if ((typebits & N_UNS) != 0)
12407 *g_type = NT_unsigned;
12408 else if ((typebits & N_INT) != 0)
12409 *g_type = NT_integer;
12410 else if ((typebits & N_FLT) != 0)
12411 *g_type = NT_float;
12412 else if ((typebits & N_SIZ) != 0)
12413 *g_type = NT_untyped;
12417 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12418 operand type, i.e. the single type specified in a Neon instruction when it
12419 is the only one given. */
12421 static struct neon_type_el
12422 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12424 struct neon_type_el dest = *key;
12426 gas_assert ((thisarg & N_EQK) != 0);
12428 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12433 /* Convert Neon type and size into compact bitmask representation. */
12435 static enum neon_type_mask
12436 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12443 case 8: return N_8;
12444 case 16: return N_16;
12445 case 32: return N_32;
12446 case 64: return N_64;
12454 case 8: return N_I8;
12455 case 16: return N_I16;
12456 case 32: return N_I32;
12457 case 64: return N_I64;
12465 case 16: return N_F16;
12466 case 32: return N_F32;
12467 case 64: return N_F64;
12475 case 8: return N_P8;
12476 case 16: return N_P16;
12484 case 8: return N_S8;
12485 case 16: return N_S16;
12486 case 32: return N_S32;
12487 case 64: return N_S64;
12495 case 8: return N_U8;
12496 case 16: return N_U16;
12497 case 32: return N_U32;
12498 case 64: return N_U64;
12509 /* Convert compact Neon bitmask type representation to a type and size. Only
12510 handles the case where a single bit is set in the mask. */
12513 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12514 enum neon_type_mask mask)
12516 if ((mask & N_EQK) != 0)
12519 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12521 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12523 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12525 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12530 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12532 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12533 *type = NT_unsigned;
12534 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12535 *type = NT_integer;
12536 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12537 *type = NT_untyped;
12538 else if ((mask & (N_P8 | N_P16)) != 0)
12540 else if ((mask & (N_F32 | N_F64)) != 0)
12548 /* Modify a bitmask of allowed types. This is only needed for type
12552 modify_types_allowed (unsigned allowed, unsigned mods)
12555 enum neon_el_type type;
12561 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12563 if (el_type_of_type_chk (&type, &size,
12564 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12566 neon_modify_type_size (mods, &type, &size);
12567 destmask |= type_chk_of_el_type (type, size);
12574 /* Check type and return type classification.
12575 The manual states (paraphrase): If one datatype is given, it indicates the
12577 - the second operand, if there is one
12578 - the operand, if there is no second operand
12579 - the result, if there are no operands.
12580 This isn't quite good enough though, so we use a concept of a "key" datatype
12581 which is set on a per-instruction basis, which is the one which matters when
12582 only one data type is written.
12583 Note: this function has side-effects (e.g. filling in missing operands). All
12584 Neon instructions should call it before performing bit encoding. */
12586 static struct neon_type_el
12587 neon_check_type (unsigned els, enum neon_shape ns, ...)
12590 unsigned i, pass, key_el = 0;
12591 unsigned types[NEON_MAX_TYPE_ELS];
12592 enum neon_el_type k_type = NT_invtype;
12593 unsigned k_size = -1u;
12594 struct neon_type_el badtype = {NT_invtype, -1};
12595 unsigned key_allowed = 0;
12597 /* Optional registers in Neon instructions are always (not) in operand 1.
12598 Fill in the missing operand here, if it was omitted. */
12599 if (els > 1 && !inst.operands[1].present)
12600 inst.operands[1] = inst.operands[0];
12602 /* Suck up all the varargs. */
12604 for (i = 0; i < els; i++)
12606 unsigned thisarg = va_arg (ap, unsigned);
12607 if (thisarg == N_IGNORE_TYPE)
12612 types[i] = thisarg;
12613 if ((thisarg & N_KEY) != 0)
12618 if (inst.vectype.elems > 0)
12619 for (i = 0; i < els; i++)
12620 if (inst.operands[i].vectype.type != NT_invtype)
12622 first_error (_("types specified in both the mnemonic and operands"));
12626 /* Duplicate inst.vectype elements here as necessary.
12627 FIXME: No idea if this is exactly the same as the ARM assembler,
12628 particularly when an insn takes one register and one non-register
12630 if (inst.vectype.elems == 1 && els > 1)
12633 inst.vectype.elems = els;
12634 inst.vectype.el[key_el] = inst.vectype.el[0];
12635 for (j = 0; j < els; j++)
12637 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12640 else if (inst.vectype.elems == 0 && els > 0)
12643 /* No types were given after the mnemonic, so look for types specified
12644 after each operand. We allow some flexibility here; as long as the
12645 "key" operand has a type, we can infer the others. */
12646 for (j = 0; j < els; j++)
12647 if (inst.operands[j].vectype.type != NT_invtype)
12648 inst.vectype.el[j] = inst.operands[j].vectype;
12650 if (inst.operands[key_el].vectype.type != NT_invtype)
12652 for (j = 0; j < els; j++)
12653 if (inst.operands[j].vectype.type == NT_invtype)
12654 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12659 first_error (_("operand types can't be inferred"));
12663 else if (inst.vectype.elems != els)
12665 first_error (_("type specifier has the wrong number of parts"));
12669 for (pass = 0; pass < 2; pass++)
12671 for (i = 0; i < els; i++)
12673 unsigned thisarg = types[i];
12674 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12675 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12676 enum neon_el_type g_type = inst.vectype.el[i].type;
12677 unsigned g_size = inst.vectype.el[i].size;
12679 /* Decay more-specific signed & unsigned types to sign-insensitive
12680 integer types if sign-specific variants are unavailable. */
12681 if ((g_type == NT_signed || g_type == NT_unsigned)
12682 && (types_allowed & N_SU_ALL) == 0)
12683 g_type = NT_integer;
12685 /* If only untyped args are allowed, decay any more specific types to
12686 them. Some instructions only care about signs for some element
12687 sizes, so handle that properly. */
12688 if ((g_size == 8 && (types_allowed & N_8) != 0)
12689 || (g_size == 16 && (types_allowed & N_16) != 0)
12690 || (g_size == 32 && (types_allowed & N_32) != 0)
12691 || (g_size == 64 && (types_allowed & N_64) != 0))
12692 g_type = NT_untyped;
12696 if ((thisarg & N_KEY) != 0)
12700 key_allowed = thisarg & ~N_KEY;
12705 if ((thisarg & N_VFP) != 0)
12707 enum neon_shape_el regshape;
12708 unsigned regwidth, match;
12710 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12713 first_error (_("invalid instruction shape"));
12716 regshape = neon_shape_tab[ns].el[i];
12717 regwidth = neon_shape_el_size[regshape];
12719 /* In VFP mode, operands must match register widths. If we
12720 have a key operand, use its width, else use the width of
12721 the current operand. */
12727 if (regwidth != match)
12729 first_error (_("operand size must match register width"));
12734 if ((thisarg & N_EQK) == 0)
12736 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12738 if ((given_type & types_allowed) == 0)
12740 first_error (_("bad type in Neon instruction"));
12746 enum neon_el_type mod_k_type = k_type;
12747 unsigned mod_k_size = k_size;
12748 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12749 if (g_type != mod_k_type || g_size != mod_k_size)
12751 first_error (_("inconsistent types in Neon instruction"));
12759 return inst.vectype.el[key_el];
12762 /* Neon-style VFP instruction forwarding. */
12764 /* Thumb VFP instructions have 0xE in the condition field. */
12767 do_vfp_cond_or_thumb (void)
12772 inst.instruction |= 0xe0000000;
12774 inst.instruction |= inst.cond << 28;
12777 /* Look up and encode a simple mnemonic, for use as a helper function for the
12778 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12779 etc. It is assumed that operand parsing has already been done, and that the
12780 operands are in the form expected by the given opcode (this isn't necessarily
12781 the same as the form in which they were parsed, hence some massaging must
12782 take place before this function is called).
12783 Checks current arch version against that in the looked-up opcode. */
12786 do_vfp_nsyn_opcode (const char *opname)
12788 const struct asm_opcode *opcode;
12790 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12796 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12803 inst.instruction = opcode->tvalue;
12804 opcode->tencode ();
12808 inst.instruction = (inst.cond << 28) | opcode->avalue;
12809 opcode->aencode ();
12814 do_vfp_nsyn_add_sub (enum neon_shape rs)
12816 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12821 do_vfp_nsyn_opcode ("fadds");
12823 do_vfp_nsyn_opcode ("fsubs");
12828 do_vfp_nsyn_opcode ("faddd");
12830 do_vfp_nsyn_opcode ("fsubd");
12834 /* Check operand types to see if this is a VFP instruction, and if so call
12838 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12840 enum neon_shape rs;
12841 struct neon_type_el et;
12846 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12847 et = neon_check_type (2, rs,
12848 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12852 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12853 et = neon_check_type (3, rs,
12854 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12861 if (et.type != NT_invtype)
12872 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12874 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12879 do_vfp_nsyn_opcode ("fmacs");
12881 do_vfp_nsyn_opcode ("fnmacs");
12886 do_vfp_nsyn_opcode ("fmacd");
12888 do_vfp_nsyn_opcode ("fnmacd");
12893 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12895 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12900 do_vfp_nsyn_opcode ("ffmas");
12902 do_vfp_nsyn_opcode ("ffnmas");
12907 do_vfp_nsyn_opcode ("ffmad");
12909 do_vfp_nsyn_opcode ("ffnmad");
12914 do_vfp_nsyn_mul (enum neon_shape rs)
12917 do_vfp_nsyn_opcode ("fmuls");
12919 do_vfp_nsyn_opcode ("fmuld");
12923 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12925 int is_neg = (inst.instruction & 0x80) != 0;
12926 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12931 do_vfp_nsyn_opcode ("fnegs");
12933 do_vfp_nsyn_opcode ("fabss");
12938 do_vfp_nsyn_opcode ("fnegd");
12940 do_vfp_nsyn_opcode ("fabsd");
12944 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12945 insns belong to Neon, and are handled elsewhere. */
12948 do_vfp_nsyn_ldm_stm (int is_dbmode)
12950 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12954 do_vfp_nsyn_opcode ("fldmdbs");
12956 do_vfp_nsyn_opcode ("fldmias");
12961 do_vfp_nsyn_opcode ("fstmdbs");
12963 do_vfp_nsyn_opcode ("fstmias");
12968 do_vfp_nsyn_sqrt (void)
12970 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12971 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12974 do_vfp_nsyn_opcode ("fsqrts");
12976 do_vfp_nsyn_opcode ("fsqrtd");
12980 do_vfp_nsyn_div (void)
12982 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12983 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12984 N_F32 | N_F64 | N_KEY | N_VFP);
12987 do_vfp_nsyn_opcode ("fdivs");
12989 do_vfp_nsyn_opcode ("fdivd");
12993 do_vfp_nsyn_nmul (void)
12995 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12996 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12997 N_F32 | N_F64 | N_KEY | N_VFP);
13001 NEON_ENCODE (SINGLE, inst);
13002 do_vfp_sp_dyadic ();
13006 NEON_ENCODE (DOUBLE, inst);
13007 do_vfp_dp_rd_rn_rm ();
13009 do_vfp_cond_or_thumb ();
13013 do_vfp_nsyn_cmp (void)
13015 if (inst.operands[1].isreg)
13017 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13018 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13022 NEON_ENCODE (SINGLE, inst);
13023 do_vfp_sp_monadic ();
13027 NEON_ENCODE (DOUBLE, inst);
13028 do_vfp_dp_rd_rm ();
13033 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13034 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13036 switch (inst.instruction & 0x0fffffff)
13039 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13042 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13050 NEON_ENCODE (SINGLE, inst);
13051 do_vfp_sp_compare_z ();
13055 NEON_ENCODE (DOUBLE, inst);
13059 do_vfp_cond_or_thumb ();
13063 nsyn_insert_sp (void)
13065 inst.operands[1] = inst.operands[0];
13066 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13067 inst.operands[0].reg = REG_SP;
13068 inst.operands[0].isreg = 1;
13069 inst.operands[0].writeback = 1;
13070 inst.operands[0].present = 1;
13074 do_vfp_nsyn_push (void)
13077 if (inst.operands[1].issingle)
13078 do_vfp_nsyn_opcode ("fstmdbs");
13080 do_vfp_nsyn_opcode ("fstmdbd");
13084 do_vfp_nsyn_pop (void)
13087 if (inst.operands[1].issingle)
13088 do_vfp_nsyn_opcode ("fldmias");
13090 do_vfp_nsyn_opcode ("fldmiad");
13093 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13094 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13097 neon_dp_fixup (struct arm_it* insn)
13099 unsigned int i = insn->instruction;
13104 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13115 insn->instruction = i;
13118 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13122 neon_logbits (unsigned x)
13124 return ffs (x) - 4;
13127 #define LOW4(R) ((R) & 0xf)
13128 #define HI1(R) (((R) >> 4) & 1)
13130 /* Encode insns with bit pattern:
13132 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13133 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13135 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13136 different meaning for some instruction. */
13139 neon_three_same (int isquad, int ubit, int size)
13141 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13142 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13143 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13144 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13145 inst.instruction |= LOW4 (inst.operands[2].reg);
13146 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13147 inst.instruction |= (isquad != 0) << 6;
13148 inst.instruction |= (ubit != 0) << 24;
13150 inst.instruction |= neon_logbits (size) << 20;
13152 neon_dp_fixup (&inst);
13155 /* Encode instructions of the form:
13157 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13158 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13160 Don't write size if SIZE == -1. */
13163 neon_two_same (int qbit, int ubit, int size)
13165 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13166 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13167 inst.instruction |= LOW4 (inst.operands[1].reg);
13168 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13169 inst.instruction |= (qbit != 0) << 6;
13170 inst.instruction |= (ubit != 0) << 24;
13173 inst.instruction |= neon_logbits (size) << 18;
13175 neon_dp_fixup (&inst);
13178 /* Neon instruction encoders, in approximate order of appearance. */
13181 do_neon_dyadic_i_su (void)
13183 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13184 struct neon_type_el et = neon_check_type (3, rs,
13185 N_EQK, N_EQK, N_SU_32 | N_KEY);
13186 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13190 do_neon_dyadic_i64_su (void)
13192 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13193 struct neon_type_el et = neon_check_type (3, rs,
13194 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13195 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13199 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13202 unsigned size = et.size >> 3;
13203 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13204 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13205 inst.instruction |= LOW4 (inst.operands[1].reg);
13206 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13207 inst.instruction |= (isquad != 0) << 6;
13208 inst.instruction |= immbits << 16;
13209 inst.instruction |= (size >> 3) << 7;
13210 inst.instruction |= (size & 0x7) << 19;
13212 inst.instruction |= (uval != 0) << 24;
13214 neon_dp_fixup (&inst);
13218 do_neon_shl_imm (void)
13220 if (!inst.operands[2].isreg)
13222 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13223 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13224 NEON_ENCODE (IMMED, inst);
13225 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13229 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13230 struct neon_type_el et = neon_check_type (3, rs,
13231 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13234 /* VSHL/VQSHL 3-register variants have syntax such as:
13236 whereas other 3-register operations encoded by neon_three_same have
13239 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13241 tmp = inst.operands[2].reg;
13242 inst.operands[2].reg = inst.operands[1].reg;
13243 inst.operands[1].reg = tmp;
13244 NEON_ENCODE (INTEGER, inst);
13245 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13250 do_neon_qshl_imm (void)
13252 if (!inst.operands[2].isreg)
13254 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13255 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13257 NEON_ENCODE (IMMED, inst);
13258 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13259 inst.operands[2].imm);
13263 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13264 struct neon_type_el et = neon_check_type (3, rs,
13265 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13268 /* See note in do_neon_shl_imm. */
13269 tmp = inst.operands[2].reg;
13270 inst.operands[2].reg = inst.operands[1].reg;
13271 inst.operands[1].reg = tmp;
13272 NEON_ENCODE (INTEGER, inst);
13273 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13278 do_neon_rshl (void)
13280 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13281 struct neon_type_el et = neon_check_type (3, rs,
13282 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13285 tmp = inst.operands[2].reg;
13286 inst.operands[2].reg = inst.operands[1].reg;
13287 inst.operands[1].reg = tmp;
13288 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13292 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13294 /* Handle .I8 pseudo-instructions. */
13297 /* Unfortunately, this will make everything apart from zero out-of-range.
13298 FIXME is this the intended semantics? There doesn't seem much point in
13299 accepting .I8 if so. */
13300 immediate |= immediate << 8;
13306 if (immediate == (immediate & 0x000000ff))
13308 *immbits = immediate;
13311 else if (immediate == (immediate & 0x0000ff00))
13313 *immbits = immediate >> 8;
13316 else if (immediate == (immediate & 0x00ff0000))
13318 *immbits = immediate >> 16;
13321 else if (immediate == (immediate & 0xff000000))
13323 *immbits = immediate >> 24;
13326 if ((immediate & 0xffff) != (immediate >> 16))
13327 goto bad_immediate;
13328 immediate &= 0xffff;
13331 if (immediate == (immediate & 0x000000ff))
13333 *immbits = immediate;
13336 else if (immediate == (immediate & 0x0000ff00))
13338 *immbits = immediate >> 8;
13343 first_error (_("immediate value out of range"));
13347 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13351 neon_bits_same_in_bytes (unsigned imm)
13353 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13354 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13355 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13356 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13359 /* For immediate of above form, return 0bABCD. */
13362 neon_squash_bits (unsigned imm)
13364 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13365 | ((imm & 0x01000000) >> 21);
13368 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13371 neon_qfloat_bits (unsigned imm)
13373 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13376 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13377 the instruction. *OP is passed as the initial value of the op field, and
13378 may be set to a different value depending on the constant (i.e.
13379 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13380 MVN). If the immediate looks like a repeated pattern then also
13381 try smaller element sizes. */
13384 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13385 unsigned *immbits, int *op, int size,
13386 enum neon_el_type type)
13388 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13390 if (type == NT_float && !float_p)
13393 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13395 if (size != 32 || *op == 1)
13397 *immbits = neon_qfloat_bits (immlo);
13403 if (neon_bits_same_in_bytes (immhi)
13404 && neon_bits_same_in_bytes (immlo))
13408 *immbits = (neon_squash_bits (immhi) << 4)
13409 | neon_squash_bits (immlo);
13414 if (immhi != immlo)
13420 if (immlo == (immlo & 0x000000ff))
13425 else if (immlo == (immlo & 0x0000ff00))
13427 *immbits = immlo >> 8;
13430 else if (immlo == (immlo & 0x00ff0000))
13432 *immbits = immlo >> 16;
13435 else if (immlo == (immlo & 0xff000000))
13437 *immbits = immlo >> 24;
13440 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13442 *immbits = (immlo >> 8) & 0xff;
13445 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13447 *immbits = (immlo >> 16) & 0xff;
13451 if ((immlo & 0xffff) != (immlo >> 16))
13458 if (immlo == (immlo & 0x000000ff))
13463 else if (immlo == (immlo & 0x0000ff00))
13465 *immbits = immlo >> 8;
13469 if ((immlo & 0xff) != (immlo >> 8))
13474 if (immlo == (immlo & 0x000000ff))
13476 /* Don't allow MVN with 8-bit immediate. */
13486 /* Write immediate bits [7:0] to the following locations:
13488 |28/24|23 19|18 16|15 4|3 0|
13489 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13491 This function is used by VMOV/VMVN/VORR/VBIC. */
13494 neon_write_immbits (unsigned immbits)
13496 inst.instruction |= immbits & 0xf;
13497 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13498 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13501 /* Invert low-order SIZE bits of XHI:XLO. */
13504 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13506 unsigned immlo = xlo ? *xlo : 0;
13507 unsigned immhi = xhi ? *xhi : 0;
13512 immlo = (~immlo) & 0xff;
13516 immlo = (~immlo) & 0xffff;
13520 immhi = (~immhi) & 0xffffffff;
13521 /* fall through. */
13524 immlo = (~immlo) & 0xffffffff;
13539 do_neon_logic (void)
13541 if (inst.operands[2].present && inst.operands[2].isreg)
13543 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13544 neon_check_type (3, rs, N_IGNORE_TYPE);
13545 /* U bit and size field were set as part of the bitmask. */
13546 NEON_ENCODE (INTEGER, inst);
13547 neon_three_same (neon_quad (rs), 0, -1);
13551 const int three_ops_form = (inst.operands[2].present
13552 && !inst.operands[2].isreg);
13553 const int immoperand = (three_ops_form ? 2 : 1);
13554 enum neon_shape rs = (three_ops_form
13555 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13556 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13557 struct neon_type_el et = neon_check_type (2, rs,
13558 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13559 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13563 if (et.type == NT_invtype)
13566 if (three_ops_form)
13567 constraint (inst.operands[0].reg != inst.operands[1].reg,
13568 _("first and second operands shall be the same register"));
13570 NEON_ENCODE (IMMED, inst);
13572 immbits = inst.operands[immoperand].imm;
13575 /* .i64 is a pseudo-op, so the immediate must be a repeating
13577 if (immbits != (inst.operands[immoperand].regisimm ?
13578 inst.operands[immoperand].reg : 0))
13580 /* Set immbits to an invalid constant. */
13581 immbits = 0xdeadbeef;
13588 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13592 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13596 /* Pseudo-instruction for VBIC. */
13597 neon_invert_size (&immbits, 0, et.size);
13598 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13602 /* Pseudo-instruction for VORR. */
13603 neon_invert_size (&immbits, 0, et.size);
13604 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13614 inst.instruction |= neon_quad (rs) << 6;
13615 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13616 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13617 inst.instruction |= cmode << 8;
13618 neon_write_immbits (immbits);
13620 neon_dp_fixup (&inst);
13625 do_neon_bitfield (void)
13627 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13628 neon_check_type (3, rs, N_IGNORE_TYPE);
13629 neon_three_same (neon_quad (rs), 0, -1);
13633 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13636 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13637 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13639 if (et.type == NT_float)
13641 NEON_ENCODE (FLOAT, inst);
13642 neon_three_same (neon_quad (rs), 0, -1);
13646 NEON_ENCODE (INTEGER, inst);
13647 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13652 do_neon_dyadic_if_su (void)
13654 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13658 do_neon_dyadic_if_su_d (void)
13660 /* This version only allow D registers, but that constraint is enforced during
13661 operand parsing so we don't need to do anything extra here. */
13662 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13666 do_neon_dyadic_if_i_d (void)
13668 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13669 affected if we specify unsigned args. */
13670 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13673 enum vfp_or_neon_is_neon_bits
13676 NEON_CHECK_ARCH = 2
13679 /* Call this function if an instruction which may have belonged to the VFP or
13680 Neon instruction sets, but turned out to be a Neon instruction (due to the
13681 operand types involved, etc.). We have to check and/or fix-up a couple of
13684 - Make sure the user hasn't attempted to make a Neon instruction
13686 - Alter the value in the condition code field if necessary.
13687 - Make sure that the arch supports Neon instructions.
13689 Which of these operations take place depends on bits from enum
13690 vfp_or_neon_is_neon_bits.
13692 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13693 current instruction's condition is COND_ALWAYS, the condition field is
13694 changed to inst.uncond_value. This is necessary because instructions shared
13695 between VFP and Neon may be conditional for the VFP variants only, and the
13696 unconditional Neon version must have, e.g., 0xF in the condition field. */
13699 vfp_or_neon_is_neon (unsigned check)
13701 /* Conditions are always legal in Thumb mode (IT blocks). */
13702 if (!thumb_mode && (check & NEON_CHECK_CC))
13704 if (inst.cond != COND_ALWAYS)
13706 first_error (_(BAD_COND));
13709 if (inst.uncond_value != -1)
13710 inst.instruction |= inst.uncond_value << 28;
13713 if ((check & NEON_CHECK_ARCH)
13714 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13716 first_error (_(BAD_FPU));
13724 do_neon_addsub_if_i (void)
13726 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13729 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13732 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13733 affected if we specify unsigned args. */
13734 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13737 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13739 V<op> A,B (A is operand 0, B is operand 2)
13744 so handle that case specially. */
13747 neon_exchange_operands (void)
13749 void *scratch = alloca (sizeof (inst.operands[0]));
13750 if (inst.operands[1].present)
13752 /* Swap operands[1] and operands[2]. */
13753 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13754 inst.operands[1] = inst.operands[2];
13755 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13759 inst.operands[1] = inst.operands[2];
13760 inst.operands[2] = inst.operands[0];
13765 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13767 if (inst.operands[2].isreg)
13770 neon_exchange_operands ();
13771 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13775 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13776 struct neon_type_el et = neon_check_type (2, rs,
13777 N_EQK | N_SIZ, immtypes | N_KEY);
13779 NEON_ENCODE (IMMED, inst);
13780 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13781 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13782 inst.instruction |= LOW4 (inst.operands[1].reg);
13783 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13784 inst.instruction |= neon_quad (rs) << 6;
13785 inst.instruction |= (et.type == NT_float) << 10;
13786 inst.instruction |= neon_logbits (et.size) << 18;
13788 neon_dp_fixup (&inst);
13795 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13799 do_neon_cmp_inv (void)
13801 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13807 neon_compare (N_IF_32, N_IF_32, FALSE);
13810 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13811 scalars, which are encoded in 5 bits, M : Rm.
13812 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13813 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13817 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13819 unsigned regno = NEON_SCALAR_REG (scalar);
13820 unsigned elno = NEON_SCALAR_INDEX (scalar);
13825 if (regno > 7 || elno > 3)
13827 return regno | (elno << 3);
13830 if (regno > 15 || elno > 1)
13832 return regno | (elno << 4);
13836 first_error (_("scalar out of range for multiply instruction"));
13842 /* Encode multiply / multiply-accumulate scalar instructions. */
13845 neon_mul_mac (struct neon_type_el et, int ubit)
13849 /* Give a more helpful error message if we have an invalid type. */
13850 if (et.type == NT_invtype)
13853 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13854 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13855 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13856 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13857 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13858 inst.instruction |= LOW4 (scalar);
13859 inst.instruction |= HI1 (scalar) << 5;
13860 inst.instruction |= (et.type == NT_float) << 8;
13861 inst.instruction |= neon_logbits (et.size) << 20;
13862 inst.instruction |= (ubit != 0) << 24;
13864 neon_dp_fixup (&inst);
13868 do_neon_mac_maybe_scalar (void)
13870 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13873 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13876 if (inst.operands[2].isscalar)
13878 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13879 struct neon_type_el et = neon_check_type (3, rs,
13880 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13881 NEON_ENCODE (SCALAR, inst);
13882 neon_mul_mac (et, neon_quad (rs));
13886 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13887 affected if we specify unsigned args. */
13888 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13893 do_neon_fmac (void)
13895 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13898 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13901 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13907 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13908 struct neon_type_el et = neon_check_type (3, rs,
13909 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13910 neon_three_same (neon_quad (rs), 0, et.size);
13913 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13914 same types as the MAC equivalents. The polynomial type for this instruction
13915 is encoded the same as the integer type. */
13920 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13923 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13926 if (inst.operands[2].isscalar)
13927 do_neon_mac_maybe_scalar ();
13929 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13933 do_neon_qdmulh (void)
13935 if (inst.operands[2].isscalar)
13937 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13938 struct neon_type_el et = neon_check_type (3, rs,
13939 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13940 NEON_ENCODE (SCALAR, inst);
13941 neon_mul_mac (et, neon_quad (rs));
13945 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13946 struct neon_type_el et = neon_check_type (3, rs,
13947 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13948 NEON_ENCODE (INTEGER, inst);
13949 /* The U bit (rounding) comes from bit mask. */
13950 neon_three_same (neon_quad (rs), 0, et.size);
13955 do_neon_fcmp_absolute (void)
13957 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13958 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13959 /* Size field comes from bit mask. */
13960 neon_three_same (neon_quad (rs), 1, -1);
13964 do_neon_fcmp_absolute_inv (void)
13966 neon_exchange_operands ();
13967 do_neon_fcmp_absolute ();
13971 do_neon_step (void)
13973 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13974 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13975 neon_three_same (neon_quad (rs), 0, -1);
13979 do_neon_abs_neg (void)
13981 enum neon_shape rs;
13982 struct neon_type_el et;
13984 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
13987 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13990 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13991 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
13993 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13994 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13995 inst.instruction |= LOW4 (inst.operands[1].reg);
13996 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13997 inst.instruction |= neon_quad (rs) << 6;
13998 inst.instruction |= (et.type == NT_float) << 10;
13999 inst.instruction |= neon_logbits (et.size) << 18;
14001 neon_dp_fixup (&inst);
14007 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14008 struct neon_type_el et = neon_check_type (2, rs,
14009 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14010 int imm = inst.operands[2].imm;
14011 constraint (imm < 0 || (unsigned)imm >= et.size,
14012 _("immediate out of range for insert"));
14013 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14019 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14020 struct neon_type_el et = neon_check_type (2, rs,
14021 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14022 int imm = inst.operands[2].imm;
14023 constraint (imm < 1 || (unsigned)imm > et.size,
14024 _("immediate out of range for insert"));
14025 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14029 do_neon_qshlu_imm (void)
14031 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14032 struct neon_type_el et = neon_check_type (2, rs,
14033 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14034 int imm = inst.operands[2].imm;
14035 constraint (imm < 0 || (unsigned)imm >= et.size,
14036 _("immediate out of range for shift"));
14037 /* Only encodes the 'U present' variant of the instruction.
14038 In this case, signed types have OP (bit 8) set to 0.
14039 Unsigned types have OP set to 1. */
14040 inst.instruction |= (et.type == NT_unsigned) << 8;
14041 /* The rest of the bits are the same as other immediate shifts. */
14042 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14046 do_neon_qmovn (void)
14048 struct neon_type_el et = neon_check_type (2, NS_DQ,
14049 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14050 /* Saturating move where operands can be signed or unsigned, and the
14051 destination has the same signedness. */
14052 NEON_ENCODE (INTEGER, inst);
14053 if (et.type == NT_unsigned)
14054 inst.instruction |= 0xc0;
14056 inst.instruction |= 0x80;
14057 neon_two_same (0, 1, et.size / 2);
14061 do_neon_qmovun (void)
14063 struct neon_type_el et = neon_check_type (2, NS_DQ,
14064 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14065 /* Saturating move with unsigned results. Operands must be signed. */
14066 NEON_ENCODE (INTEGER, inst);
14067 neon_two_same (0, 1, et.size / 2);
14071 do_neon_rshift_sat_narrow (void)
14073 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14074 or unsigned. If operands are unsigned, results must also be unsigned. */
14075 struct neon_type_el et = neon_check_type (2, NS_DQI,
14076 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14077 int imm = inst.operands[2].imm;
14078 /* This gets the bounds check, size encoding and immediate bits calculation
14082 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14083 VQMOVN.I<size> <Dd>, <Qm>. */
14086 inst.operands[2].present = 0;
14087 inst.instruction = N_MNEM_vqmovn;
14092 constraint (imm < 1 || (unsigned)imm > et.size,
14093 _("immediate out of range"));
14094 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14098 do_neon_rshift_sat_narrow_u (void)
14100 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14101 or unsigned. If operands are unsigned, results must also be unsigned. */
14102 struct neon_type_el et = neon_check_type (2, NS_DQI,
14103 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14104 int imm = inst.operands[2].imm;
14105 /* This gets the bounds check, size encoding and immediate bits calculation
14109 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14110 VQMOVUN.I<size> <Dd>, <Qm>. */
14113 inst.operands[2].present = 0;
14114 inst.instruction = N_MNEM_vqmovun;
14119 constraint (imm < 1 || (unsigned)imm > et.size,
14120 _("immediate out of range"));
14121 /* FIXME: The manual is kind of unclear about what value U should have in
14122 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14124 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14128 do_neon_movn (void)
14130 struct neon_type_el et = neon_check_type (2, NS_DQ,
14131 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14132 NEON_ENCODE (INTEGER, inst);
14133 neon_two_same (0, 1, et.size / 2);
14137 do_neon_rshift_narrow (void)
14139 struct neon_type_el et = neon_check_type (2, NS_DQI,
14140 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14141 int imm = inst.operands[2].imm;
14142 /* This gets the bounds check, size encoding and immediate bits calculation
14146 /* If immediate is zero then we are a pseudo-instruction for
14147 VMOVN.I<size> <Dd>, <Qm> */
14150 inst.operands[2].present = 0;
14151 inst.instruction = N_MNEM_vmovn;
14156 constraint (imm < 1 || (unsigned)imm > et.size,
14157 _("immediate out of range for narrowing operation"));
14158 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14162 do_neon_shll (void)
14164 /* FIXME: Type checking when lengthening. */
14165 struct neon_type_el et = neon_check_type (2, NS_QDI,
14166 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14167 unsigned imm = inst.operands[2].imm;
14169 if (imm == et.size)
14171 /* Maximum shift variant. */
14172 NEON_ENCODE (INTEGER, inst);
14173 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14174 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14175 inst.instruction |= LOW4 (inst.operands[1].reg);
14176 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14177 inst.instruction |= neon_logbits (et.size) << 18;
14179 neon_dp_fixup (&inst);
14183 /* A more-specific type check for non-max versions. */
14184 et = neon_check_type (2, NS_QDI,
14185 N_EQK | N_DBL, N_SU_32 | N_KEY);
14186 NEON_ENCODE (IMMED, inst);
14187 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14191 /* Check the various types for the VCVT instruction, and return which version
14192 the current instruction is. */
14195 neon_cvt_flavour (enum neon_shape rs)
14197 #define CVT_VAR(C,X,Y) \
14198 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14199 if (et.type != NT_invtype) \
14201 inst.error = NULL; \
14204 struct neon_type_el et;
14205 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14206 || rs == NS_FF) ? N_VFP : 0;
14207 /* The instruction versions which take an immediate take one register
14208 argument, which is extended to the width of the full register. Thus the
14209 "source" and "destination" registers must have the same width. Hack that
14210 here by making the size equal to the key (wider, in this case) operand. */
14211 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14213 CVT_VAR (0, N_S32, N_F32);
14214 CVT_VAR (1, N_U32, N_F32);
14215 CVT_VAR (2, N_F32, N_S32);
14216 CVT_VAR (3, N_F32, N_U32);
14217 /* Half-precision conversions. */
14218 CVT_VAR (4, N_F32, N_F16);
14219 CVT_VAR (5, N_F16, N_F32);
14223 /* VFP instructions. */
14224 CVT_VAR (6, N_F32, N_F64);
14225 CVT_VAR (7, N_F64, N_F32);
14226 CVT_VAR (8, N_S32, N_F64 | key);
14227 CVT_VAR (9, N_U32, N_F64 | key);
14228 CVT_VAR (10, N_F64 | key, N_S32);
14229 CVT_VAR (11, N_F64 | key, N_U32);
14230 /* VFP instructions with bitshift. */
14231 CVT_VAR (12, N_F32 | key, N_S16);
14232 CVT_VAR (13, N_F32 | key, N_U16);
14233 CVT_VAR (14, N_F64 | key, N_S16);
14234 CVT_VAR (15, N_F64 | key, N_U16);
14235 CVT_VAR (16, N_S16, N_F32 | key);
14236 CVT_VAR (17, N_U16, N_F32 | key);
14237 CVT_VAR (18, N_S16, N_F64 | key);
14238 CVT_VAR (19, N_U16, N_F64 | key);
14244 /* Neon-syntax VFP conversions. */
14247 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14249 const char *opname = 0;
14251 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14253 /* Conversions with immediate bitshift. */
14254 const char *enc[] =
14278 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14280 opname = enc[flavour];
14281 constraint (inst.operands[0].reg != inst.operands[1].reg,
14282 _("operands 0 and 1 must be the same register"));
14283 inst.operands[1] = inst.operands[2];
14284 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14289 /* Conversions without bitshift. */
14290 const char *enc[] =
14306 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14307 opname = enc[flavour];
14311 do_vfp_nsyn_opcode (opname);
14315 do_vfp_nsyn_cvtz (void)
14317 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14318 int flavour = neon_cvt_flavour (rs);
14319 const char *enc[] =
14333 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14334 do_vfp_nsyn_opcode (enc[flavour]);
14338 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14340 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14341 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14342 int flavour = neon_cvt_flavour (rs);
14344 /* PR11109: Handle round-to-zero for VCVT conversions. */
14346 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14347 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14348 && (rs == NS_FD || rs == NS_FF))
14350 do_vfp_nsyn_cvtz ();
14354 /* VFP rather than Neon conversions. */
14357 do_vfp_nsyn_cvt (rs, flavour);
14367 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14369 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14372 /* Fixed-point conversion with #0 immediate is encoded as an
14373 integer conversion. */
14374 if (inst.operands[2].present && inst.operands[2].imm == 0)
14376 immbits = 32 - inst.operands[2].imm;
14377 NEON_ENCODE (IMMED, inst);
14379 inst.instruction |= enctab[flavour];
14380 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14381 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14382 inst.instruction |= LOW4 (inst.operands[1].reg);
14383 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14384 inst.instruction |= neon_quad (rs) << 6;
14385 inst.instruction |= 1 << 21;
14386 inst.instruction |= immbits << 16;
14388 neon_dp_fixup (&inst);
14396 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14398 NEON_ENCODE (INTEGER, inst);
14400 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14404 inst.instruction |= enctab[flavour];
14406 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14407 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14408 inst.instruction |= LOW4 (inst.operands[1].reg);
14409 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14410 inst.instruction |= neon_quad (rs) << 6;
14411 inst.instruction |= 2 << 18;
14413 neon_dp_fixup (&inst);
14417 /* Half-precision conversions for Advanced SIMD -- neon. */
14422 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14424 as_bad (_("operand size must match register width"));
14429 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14431 as_bad (_("operand size must match register width"));
14436 inst.instruction = 0x3b60600;
14438 inst.instruction = 0x3b60700;
14440 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14441 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14442 inst.instruction |= LOW4 (inst.operands[1].reg);
14443 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14444 neon_dp_fixup (&inst);
14448 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14449 do_vfp_nsyn_cvt (rs, flavour);
14454 do_neon_cvtr (void)
14456 do_neon_cvt_1 (FALSE);
14462 do_neon_cvt_1 (TRUE);
14466 do_neon_cvtb (void)
14468 inst.instruction = 0xeb20a40;
14470 /* The sizes are attached to the mnemonic. */
14471 if (inst.vectype.el[0].type != NT_invtype
14472 && inst.vectype.el[0].size == 16)
14473 inst.instruction |= 0x00010000;
14475 /* Programmer's syntax: the sizes are attached to the operands. */
14476 else if (inst.operands[0].vectype.type != NT_invtype
14477 && inst.operands[0].vectype.size == 16)
14478 inst.instruction |= 0x00010000;
14480 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14481 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14482 do_vfp_cond_or_thumb ();
14487 do_neon_cvtt (void)
14490 inst.instruction |= 0x80;
14494 neon_move_immediate (void)
14496 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14497 struct neon_type_el et = neon_check_type (2, rs,
14498 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14499 unsigned immlo, immhi = 0, immbits;
14500 int op, cmode, float_p;
14502 constraint (et.type == NT_invtype,
14503 _("operand size must be specified for immediate VMOV"));
14505 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14506 op = (inst.instruction & (1 << 5)) != 0;
14508 immlo = inst.operands[1].imm;
14509 if (inst.operands[1].regisimm)
14510 immhi = inst.operands[1].reg;
14512 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14513 _("immediate has bits set outside the operand size"));
14515 float_p = inst.operands[1].immisfloat;
14517 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14518 et.size, et.type)) == FAIL)
14520 /* Invert relevant bits only. */
14521 neon_invert_size (&immlo, &immhi, et.size);
14522 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14523 with one or the other; those cases are caught by
14524 neon_cmode_for_move_imm. */
14526 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14527 &op, et.size, et.type)) == FAIL)
14529 first_error (_("immediate out of range"));
14534 inst.instruction &= ~(1 << 5);
14535 inst.instruction |= op << 5;
14537 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14538 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14539 inst.instruction |= neon_quad (rs) << 6;
14540 inst.instruction |= cmode << 8;
14542 neon_write_immbits (immbits);
14548 if (inst.operands[1].isreg)
14550 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14552 NEON_ENCODE (INTEGER, inst);
14553 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14554 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14555 inst.instruction |= LOW4 (inst.operands[1].reg);
14556 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14557 inst.instruction |= neon_quad (rs) << 6;
14561 NEON_ENCODE (IMMED, inst);
14562 neon_move_immediate ();
14565 neon_dp_fixup (&inst);
14568 /* Encode instructions of form:
14570 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14571 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14574 neon_mixed_length (struct neon_type_el et, unsigned size)
14576 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14577 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14578 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14579 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14580 inst.instruction |= LOW4 (inst.operands[2].reg);
14581 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14582 inst.instruction |= (et.type == NT_unsigned) << 24;
14583 inst.instruction |= neon_logbits (size) << 20;
14585 neon_dp_fixup (&inst);
14589 do_neon_dyadic_long (void)
14591 /* FIXME: Type checking for lengthening op. */
14592 struct neon_type_el et = neon_check_type (3, NS_QDD,
14593 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14594 neon_mixed_length (et, et.size);
14598 do_neon_abal (void)
14600 struct neon_type_el et = neon_check_type (3, NS_QDD,
14601 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14602 neon_mixed_length (et, et.size);
14606 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14608 if (inst.operands[2].isscalar)
14610 struct neon_type_el et = neon_check_type (3, NS_QDS,
14611 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14612 NEON_ENCODE (SCALAR, inst);
14613 neon_mul_mac (et, et.type == NT_unsigned);
14617 struct neon_type_el et = neon_check_type (3, NS_QDD,
14618 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14619 NEON_ENCODE (INTEGER, inst);
14620 neon_mixed_length (et, et.size);
14625 do_neon_mac_maybe_scalar_long (void)
14627 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14631 do_neon_dyadic_wide (void)
14633 struct neon_type_el et = neon_check_type (3, NS_QQD,
14634 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14635 neon_mixed_length (et, et.size);
14639 do_neon_dyadic_narrow (void)
14641 struct neon_type_el et = neon_check_type (3, NS_QDD,
14642 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14643 /* Operand sign is unimportant, and the U bit is part of the opcode,
14644 so force the operand type to integer. */
14645 et.type = NT_integer;
14646 neon_mixed_length (et, et.size / 2);
14650 do_neon_mul_sat_scalar_long (void)
14652 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14656 do_neon_vmull (void)
14658 if (inst.operands[2].isscalar)
14659 do_neon_mac_maybe_scalar_long ();
14662 struct neon_type_el et = neon_check_type (3, NS_QDD,
14663 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14664 if (et.type == NT_poly)
14665 NEON_ENCODE (POLY, inst);
14667 NEON_ENCODE (INTEGER, inst);
14668 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14669 zero. Should be OK as-is. */
14670 neon_mixed_length (et, et.size);
14677 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14678 struct neon_type_el et = neon_check_type (3, rs,
14679 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14680 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14682 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14683 _("shift out of range"));
14684 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14685 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14686 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14687 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14688 inst.instruction |= LOW4 (inst.operands[2].reg);
14689 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14690 inst.instruction |= neon_quad (rs) << 6;
14691 inst.instruction |= imm << 8;
14693 neon_dp_fixup (&inst);
14699 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14700 struct neon_type_el et = neon_check_type (2, rs,
14701 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14702 unsigned op = (inst.instruction >> 7) & 3;
14703 /* N (width of reversed regions) is encoded as part of the bitmask. We
14704 extract it here to check the elements to be reversed are smaller.
14705 Otherwise we'd get a reserved instruction. */
14706 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14707 gas_assert (elsize != 0);
14708 constraint (et.size >= elsize,
14709 _("elements must be smaller than reversal region"));
14710 neon_two_same (neon_quad (rs), 1, et.size);
14716 if (inst.operands[1].isscalar)
14718 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14719 struct neon_type_el et = neon_check_type (2, rs,
14720 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14721 unsigned sizebits = et.size >> 3;
14722 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14723 int logsize = neon_logbits (et.size);
14724 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14726 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14729 NEON_ENCODE (SCALAR, inst);
14730 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14731 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14732 inst.instruction |= LOW4 (dm);
14733 inst.instruction |= HI1 (dm) << 5;
14734 inst.instruction |= neon_quad (rs) << 6;
14735 inst.instruction |= x << 17;
14736 inst.instruction |= sizebits << 16;
14738 neon_dp_fixup (&inst);
14742 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14743 struct neon_type_el et = neon_check_type (2, rs,
14744 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14745 /* Duplicate ARM register to lanes of vector. */
14746 NEON_ENCODE (ARMREG, inst);
14749 case 8: inst.instruction |= 0x400000; break;
14750 case 16: inst.instruction |= 0x000020; break;
14751 case 32: inst.instruction |= 0x000000; break;
14754 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14755 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14756 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14757 inst.instruction |= neon_quad (rs) << 21;
14758 /* The encoding for this instruction is identical for the ARM and Thumb
14759 variants, except for the condition field. */
14760 do_vfp_cond_or_thumb ();
14764 /* VMOV has particularly many variations. It can be one of:
14765 0. VMOV<c><q> <Qd>, <Qm>
14766 1. VMOV<c><q> <Dd>, <Dm>
14767 (Register operations, which are VORR with Rm = Rn.)
14768 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14769 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14771 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14772 (ARM register to scalar.)
14773 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14774 (Two ARM registers to vector.)
14775 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14776 (Scalar to ARM register.)
14777 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14778 (Vector to two ARM registers.)
14779 8. VMOV.F32 <Sd>, <Sm>
14780 9. VMOV.F64 <Dd>, <Dm>
14781 (VFP register moves.)
14782 10. VMOV.F32 <Sd>, #imm
14783 11. VMOV.F64 <Dd>, #imm
14784 (VFP float immediate load.)
14785 12. VMOV <Rd>, <Sm>
14786 (VFP single to ARM reg.)
14787 13. VMOV <Sd>, <Rm>
14788 (ARM reg to VFP single.)
14789 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14790 (Two ARM regs to two VFP singles.)
14791 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14792 (Two VFP singles to two ARM regs.)
14794 These cases can be disambiguated using neon_select_shape, except cases 1/9
14795 and 3/11 which depend on the operand type too.
14797 All the encoded bits are hardcoded by this function.
14799 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14800 Cases 5, 7 may be used with VFPv2 and above.
14802 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14803 can specify a type where it doesn't make sense to, and is ignored). */
14808 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14809 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14811 struct neon_type_el et;
14812 const char *ldconst = 0;
14816 case NS_DD: /* case 1/9. */
14817 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14818 /* It is not an error here if no type is given. */
14820 if (et.type == NT_float && et.size == 64)
14822 do_vfp_nsyn_opcode ("fcpyd");
14825 /* fall through. */
14827 case NS_QQ: /* case 0/1. */
14829 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14831 /* The architecture manual I have doesn't explicitly state which
14832 value the U bit should have for register->register moves, but
14833 the equivalent VORR instruction has U = 0, so do that. */
14834 inst.instruction = 0x0200110;
14835 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14836 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14837 inst.instruction |= LOW4 (inst.operands[1].reg);
14838 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14839 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14840 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14841 inst.instruction |= neon_quad (rs) << 6;
14843 neon_dp_fixup (&inst);
14847 case NS_DI: /* case 3/11. */
14848 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14850 if (et.type == NT_float && et.size == 64)
14852 /* case 11 (fconstd). */
14853 ldconst = "fconstd";
14854 goto encode_fconstd;
14856 /* fall through. */
14858 case NS_QI: /* case 2/3. */
14859 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14861 inst.instruction = 0x0800010;
14862 neon_move_immediate ();
14863 neon_dp_fixup (&inst);
14866 case NS_SR: /* case 4. */
14868 unsigned bcdebits = 0;
14870 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14871 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14873 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14874 logsize = neon_logbits (et.size);
14876 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14879 && et.size != 32, _(BAD_FPU));
14880 constraint (et.type == NT_invtype, _("bad type for scalar"));
14881 constraint (x >= 64 / et.size, _("scalar index out of range"));
14885 case 8: bcdebits = 0x8; break;
14886 case 16: bcdebits = 0x1; break;
14887 case 32: bcdebits = 0x0; break;
14891 bcdebits |= x << logsize;
14893 inst.instruction = 0xe000b10;
14894 do_vfp_cond_or_thumb ();
14895 inst.instruction |= LOW4 (dn) << 16;
14896 inst.instruction |= HI1 (dn) << 7;
14897 inst.instruction |= inst.operands[1].reg << 12;
14898 inst.instruction |= (bcdebits & 3) << 5;
14899 inst.instruction |= (bcdebits >> 2) << 21;
14903 case NS_DRR: /* case 5 (fmdrr). */
14904 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14907 inst.instruction = 0xc400b10;
14908 do_vfp_cond_or_thumb ();
14909 inst.instruction |= LOW4 (inst.operands[0].reg);
14910 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14911 inst.instruction |= inst.operands[1].reg << 12;
14912 inst.instruction |= inst.operands[2].reg << 16;
14915 case NS_RS: /* case 6. */
14918 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14919 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14920 unsigned abcdebits = 0;
14922 et = neon_check_type (2, NS_NULL,
14923 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14924 logsize = neon_logbits (et.size);
14926 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14928 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14929 && et.size != 32, _(BAD_FPU));
14930 constraint (et.type == NT_invtype, _("bad type for scalar"));
14931 constraint (x >= 64 / et.size, _("scalar index out of range"));
14935 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14936 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14937 case 32: abcdebits = 0x00; break;
14941 abcdebits |= x << logsize;
14942 inst.instruction = 0xe100b10;
14943 do_vfp_cond_or_thumb ();
14944 inst.instruction |= LOW4 (dn) << 16;
14945 inst.instruction |= HI1 (dn) << 7;
14946 inst.instruction |= inst.operands[0].reg << 12;
14947 inst.instruction |= (abcdebits & 3) << 5;
14948 inst.instruction |= (abcdebits >> 2) << 21;
14952 case NS_RRD: /* case 7 (fmrrd). */
14953 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14956 inst.instruction = 0xc500b10;
14957 do_vfp_cond_or_thumb ();
14958 inst.instruction |= inst.operands[0].reg << 12;
14959 inst.instruction |= inst.operands[1].reg << 16;
14960 inst.instruction |= LOW4 (inst.operands[2].reg);
14961 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14964 case NS_FF: /* case 8 (fcpys). */
14965 do_vfp_nsyn_opcode ("fcpys");
14968 case NS_FI: /* case 10 (fconsts). */
14969 ldconst = "fconsts";
14971 if (is_quarter_float (inst.operands[1].imm))
14973 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
14974 do_vfp_nsyn_opcode (ldconst);
14977 first_error (_("immediate out of range"));
14980 case NS_RF: /* case 12 (fmrs). */
14981 do_vfp_nsyn_opcode ("fmrs");
14984 case NS_FR: /* case 13 (fmsr). */
14985 do_vfp_nsyn_opcode ("fmsr");
14988 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14989 (one of which is a list), but we have parsed four. Do some fiddling to
14990 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14992 case NS_RRFF: /* case 14 (fmrrs). */
14993 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
14994 _("VFP registers must be adjacent"));
14995 inst.operands[2].imm = 2;
14996 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14997 do_vfp_nsyn_opcode ("fmrrs");
15000 case NS_FFRR: /* case 15 (fmsrr). */
15001 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15002 _("VFP registers must be adjacent"));
15003 inst.operands[1] = inst.operands[2];
15004 inst.operands[2] = inst.operands[3];
15005 inst.operands[0].imm = 2;
15006 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15007 do_vfp_nsyn_opcode ("fmsrr");
15016 do_neon_rshift_round_imm (void)
15018 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15019 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15020 int imm = inst.operands[2].imm;
15022 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15025 inst.operands[2].present = 0;
15030 constraint (imm < 1 || (unsigned)imm > et.size,
15031 _("immediate out of range for shift"));
15032 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15037 do_neon_movl (void)
15039 struct neon_type_el et = neon_check_type (2, NS_QD,
15040 N_EQK | N_DBL, N_SU_32 | N_KEY);
15041 unsigned sizebits = et.size >> 3;
15042 inst.instruction |= sizebits << 19;
15043 neon_two_same (0, et.type == NT_unsigned, -1);
15049 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15050 struct neon_type_el et = neon_check_type (2, rs,
15051 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15052 NEON_ENCODE (INTEGER, inst);
15053 neon_two_same (neon_quad (rs), 1, et.size);
15057 do_neon_zip_uzp (void)
15059 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15060 struct neon_type_el et = neon_check_type (2, rs,
15061 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15062 if (rs == NS_DD && et.size == 32)
15064 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15065 inst.instruction = N_MNEM_vtrn;
15069 neon_two_same (neon_quad (rs), 1, et.size);
15073 do_neon_sat_abs_neg (void)
15075 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15076 struct neon_type_el et = neon_check_type (2, rs,
15077 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15078 neon_two_same (neon_quad (rs), 1, et.size);
15082 do_neon_pair_long (void)
15084 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15085 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15086 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15087 inst.instruction |= (et.type == NT_unsigned) << 7;
15088 neon_two_same (neon_quad (rs), 1, et.size);
15092 do_neon_recip_est (void)
15094 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15095 struct neon_type_el et = neon_check_type (2, rs,
15096 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15097 inst.instruction |= (et.type == NT_float) << 8;
15098 neon_two_same (neon_quad (rs), 1, et.size);
15104 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15105 struct neon_type_el et = neon_check_type (2, rs,
15106 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15107 neon_two_same (neon_quad (rs), 1, et.size);
15113 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15114 struct neon_type_el et = neon_check_type (2, rs,
15115 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15116 neon_two_same (neon_quad (rs), 1, et.size);
15122 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15123 struct neon_type_el et = neon_check_type (2, rs,
15124 N_EQK | N_INT, N_8 | N_KEY);
15125 neon_two_same (neon_quad (rs), 1, et.size);
15131 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15132 neon_two_same (neon_quad (rs), 1, -1);
15136 do_neon_tbl_tbx (void)
15138 unsigned listlenbits;
15139 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15141 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15143 first_error (_("bad list length for table lookup"));
15147 listlenbits = inst.operands[1].imm - 1;
15148 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15149 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15150 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15151 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15152 inst.instruction |= LOW4 (inst.operands[2].reg);
15153 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15154 inst.instruction |= listlenbits << 8;
15156 neon_dp_fixup (&inst);
15160 do_neon_ldm_stm (void)
15162 /* P, U and L bits are part of bitmask. */
15163 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15164 unsigned offsetbits = inst.operands[1].imm * 2;
15166 if (inst.operands[1].issingle)
15168 do_vfp_nsyn_ldm_stm (is_dbmode);
15172 constraint (is_dbmode && !inst.operands[0].writeback,
15173 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15175 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15176 _("register list must contain at least 1 and at most 16 "
15179 inst.instruction |= inst.operands[0].reg << 16;
15180 inst.instruction |= inst.operands[0].writeback << 21;
15181 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15182 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15184 inst.instruction |= offsetbits;
15186 do_vfp_cond_or_thumb ();
15190 do_neon_ldr_str (void)
15192 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15194 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15195 And is UNPREDICTABLE in thumb mode. */
15197 && inst.operands[1].reg == REG_PC
15198 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15200 if (!thumb_mode && warn_on_deprecated)
15201 as_warn (_("Use of PC here is deprecated"));
15203 inst.error = _("Use of PC here is UNPREDICTABLE");
15206 if (inst.operands[0].issingle)
15209 do_vfp_nsyn_opcode ("flds");
15211 do_vfp_nsyn_opcode ("fsts");
15216 do_vfp_nsyn_opcode ("fldd");
15218 do_vfp_nsyn_opcode ("fstd");
15222 /* "interleave" version also handles non-interleaving register VLD1/VST1
15226 do_neon_ld_st_interleave (void)
15228 struct neon_type_el et = neon_check_type (1, NS_NULL,
15229 N_8 | N_16 | N_32 | N_64);
15230 unsigned alignbits = 0;
15232 /* The bits in this table go:
15233 0: register stride of one (0) or two (1)
15234 1,2: register list length, minus one (1, 2, 3, 4).
15235 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15236 We use -1 for invalid entries. */
15237 const int typetable[] =
15239 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15240 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15241 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15242 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15246 if (et.type == NT_invtype)
15249 if (inst.operands[1].immisalign)
15250 switch (inst.operands[1].imm >> 8)
15252 case 64: alignbits = 1; break;
15254 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15255 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15256 goto bad_alignment;
15260 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15261 goto bad_alignment;
15266 first_error (_("bad alignment"));
15270 inst.instruction |= alignbits << 4;
15271 inst.instruction |= neon_logbits (et.size) << 6;
15273 /* Bits [4:6] of the immediate in a list specifier encode register stride
15274 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15275 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15276 up the right value for "type" in a table based on this value and the given
15277 list style, then stick it back. */
15278 idx = ((inst.operands[0].imm >> 4) & 7)
15279 | (((inst.instruction >> 8) & 3) << 3);
15281 typebits = typetable[idx];
15283 constraint (typebits == -1, _("bad list type for instruction"));
15285 inst.instruction &= ~0xf00;
15286 inst.instruction |= typebits << 8;
15289 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15290 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15291 otherwise. The variable arguments are a list of pairs of legal (size, align)
15292 values, terminated with -1. */
15295 neon_alignment_bit (int size, int align, int *do_align, ...)
15298 int result = FAIL, thissize, thisalign;
15300 if (!inst.operands[1].immisalign)
15306 va_start (ap, do_align);
15310 thissize = va_arg (ap, int);
15311 if (thissize == -1)
15313 thisalign = va_arg (ap, int);
15315 if (size == thissize && align == thisalign)
15318 while (result != SUCCESS);
15322 if (result == SUCCESS)
15325 first_error (_("unsupported alignment for instruction"));
15331 do_neon_ld_st_lane (void)
15333 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15334 int align_good, do_align = 0;
15335 int logsize = neon_logbits (et.size);
15336 int align = inst.operands[1].imm >> 8;
15337 int n = (inst.instruction >> 8) & 3;
15338 int max_el = 64 / et.size;
15340 if (et.type == NT_invtype)
15343 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15344 _("bad list length"));
15345 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15346 _("scalar index out of range"));
15347 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15349 _("stride of 2 unavailable when element size is 8"));
15353 case 0: /* VLD1 / VST1. */
15354 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15356 if (align_good == FAIL)
15360 unsigned alignbits = 0;
15363 case 16: alignbits = 0x1; break;
15364 case 32: alignbits = 0x3; break;
15367 inst.instruction |= alignbits << 4;
15371 case 1: /* VLD2 / VST2. */
15372 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15374 if (align_good == FAIL)
15377 inst.instruction |= 1 << 4;
15380 case 2: /* VLD3 / VST3. */
15381 constraint (inst.operands[1].immisalign,
15382 _("can't use alignment with this instruction"));
15385 case 3: /* VLD4 / VST4. */
15386 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15387 16, 64, 32, 64, 32, 128, -1);
15388 if (align_good == FAIL)
15392 unsigned alignbits = 0;
15395 case 8: alignbits = 0x1; break;
15396 case 16: alignbits = 0x1; break;
15397 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15400 inst.instruction |= alignbits << 4;
15407 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15408 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15409 inst.instruction |= 1 << (4 + logsize);
15411 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15412 inst.instruction |= logsize << 10;
15415 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15418 do_neon_ld_dup (void)
15420 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15421 int align_good, do_align = 0;
15423 if (et.type == NT_invtype)
15426 switch ((inst.instruction >> 8) & 3)
15428 case 0: /* VLD1. */
15429 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15430 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15431 &do_align, 16, 16, 32, 32, -1);
15432 if (align_good == FAIL)
15434 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15437 case 2: inst.instruction |= 1 << 5; break;
15438 default: first_error (_("bad list length")); return;
15440 inst.instruction |= neon_logbits (et.size) << 6;
15443 case 1: /* VLD2. */
15444 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15445 &do_align, 8, 16, 16, 32, 32, 64, -1);
15446 if (align_good == FAIL)
15448 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15449 _("bad list length"));
15450 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15451 inst.instruction |= 1 << 5;
15452 inst.instruction |= neon_logbits (et.size) << 6;
15455 case 2: /* VLD3. */
15456 constraint (inst.operands[1].immisalign,
15457 _("can't use alignment with this instruction"));
15458 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15459 _("bad list length"));
15460 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15461 inst.instruction |= 1 << 5;
15462 inst.instruction |= neon_logbits (et.size) << 6;
15465 case 3: /* VLD4. */
15467 int align = inst.operands[1].imm >> 8;
15468 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15469 16, 64, 32, 64, 32, 128, -1);
15470 if (align_good == FAIL)
15472 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15473 _("bad list length"));
15474 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15475 inst.instruction |= 1 << 5;
15476 if (et.size == 32 && align == 128)
15477 inst.instruction |= 0x3 << 6;
15479 inst.instruction |= neon_logbits (et.size) << 6;
15486 inst.instruction |= do_align << 4;
15489 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15490 apart from bits [11:4]. */
15493 do_neon_ldx_stx (void)
15495 if (inst.operands[1].isreg)
15496 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15498 switch (NEON_LANE (inst.operands[0].imm))
15500 case NEON_INTERLEAVE_LANES:
15501 NEON_ENCODE (INTERLV, inst);
15502 do_neon_ld_st_interleave ();
15505 case NEON_ALL_LANES:
15506 NEON_ENCODE (DUP, inst);
15511 NEON_ENCODE (LANE, inst);
15512 do_neon_ld_st_lane ();
15515 /* L bit comes from bit mask. */
15516 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15517 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15518 inst.instruction |= inst.operands[1].reg << 16;
15520 if (inst.operands[1].postind)
15522 int postreg = inst.operands[1].imm & 0xf;
15523 constraint (!inst.operands[1].immisreg,
15524 _("post-index must be a register"));
15525 constraint (postreg == 0xd || postreg == 0xf,
15526 _("bad register for post-index"));
15527 inst.instruction |= postreg;
15529 else if (inst.operands[1].writeback)
15531 inst.instruction |= 0xd;
15534 inst.instruction |= 0xf;
15537 inst.instruction |= 0xf9000000;
15539 inst.instruction |= 0xf4000000;
15542 /* Overall per-instruction processing. */
15544 /* We need to be able to fix up arbitrary expressions in some statements.
15545 This is so that we can handle symbols that are an arbitrary distance from
15546 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15547 which returns part of an address in a form which will be valid for
15548 a data instruction. We do this by pushing the expression into a symbol
15549 in the expr_section, and creating a fix for that. */
15552 fix_new_arm (fragS * frag,
15566 /* Create an absolute valued symbol, so we have something to
15567 refer to in the object file. Unfortunately for us, gas's
15568 generic expression parsing will already have folded out
15569 any use of .set foo/.type foo %function that may have
15570 been used to set type information of the target location,
15571 that's being specified symbolically. We have to presume
15572 the user knows what they are doing. */
15576 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15578 symbol = symbol_find_or_make (name);
15579 S_SET_SEGMENT (symbol, absolute_section);
15580 symbol_set_frag (symbol, &zero_address_frag);
15581 S_SET_VALUE (symbol, exp->X_add_number);
15582 exp->X_op = O_symbol;
15583 exp->X_add_symbol = symbol;
15584 exp->X_add_number = 0;
15590 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15591 (enum bfd_reloc_code_real) reloc);
15595 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15596 pc_rel, (enum bfd_reloc_code_real) reloc);
15600 /* Mark whether the fix is to a THUMB instruction, or an ARM
15602 new_fix->tc_fix_data = thumb_mode;
15605 /* Create a frg for an instruction requiring relaxation. */
15607 output_relax_insn (void)
15613 /* The size of the instruction is unknown, so tie the debug info to the
15614 start of the instruction. */
15615 dwarf2_emit_insn (0);
15617 switch (inst.reloc.exp.X_op)
15620 sym = inst.reloc.exp.X_add_symbol;
15621 offset = inst.reloc.exp.X_add_number;
15625 offset = inst.reloc.exp.X_add_number;
15628 sym = make_expr_symbol (&inst.reloc.exp);
15632 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15633 inst.relax, sym, offset, NULL/*offset, opcode*/);
15634 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15637 /* Write a 32-bit thumb instruction to buf. */
15639 put_thumb32_insn (char * buf, unsigned long insn)
15641 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15642 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15646 output_inst (const char * str)
15652 as_bad ("%s -- `%s'", inst.error, str);
15657 output_relax_insn ();
15660 if (inst.size == 0)
15663 to = frag_more (inst.size);
15664 /* PR 9814: Record the thumb mode into the current frag so that we know
15665 what type of NOP padding to use, if necessary. We override any previous
15666 setting so that if the mode has changed then the NOPS that we use will
15667 match the encoding of the last instruction in the frag. */
15668 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15670 if (thumb_mode && (inst.size > THUMB_SIZE))
15672 gas_assert (inst.size == (2 * THUMB_SIZE));
15673 put_thumb32_insn (to, inst.instruction);
15675 else if (inst.size > INSN_SIZE)
15677 gas_assert (inst.size == (2 * INSN_SIZE));
15678 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15679 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15682 md_number_to_chars (to, inst.instruction, inst.size);
15684 if (inst.reloc.type != BFD_RELOC_UNUSED)
15685 fix_new_arm (frag_now, to - frag_now->fr_literal,
15686 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15689 dwarf2_emit_insn (inst.size);
15693 output_it_inst (int cond, int mask, char * to)
15695 unsigned long instruction = 0xbf00;
15698 instruction |= mask;
15699 instruction |= cond << 4;
15703 to = frag_more (2);
15705 dwarf2_emit_insn (2);
15709 md_number_to_chars (to, instruction, 2);
15714 /* Tag values used in struct asm_opcode's tag field. */
15717 OT_unconditional, /* Instruction cannot be conditionalized.
15718 The ARM condition field is still 0xE. */
15719 OT_unconditionalF, /* Instruction cannot be conditionalized
15720 and carries 0xF in its ARM condition field. */
15721 OT_csuffix, /* Instruction takes a conditional suffix. */
15722 OT_csuffixF, /* Some forms of the instruction take a conditional
15723 suffix, others place 0xF where the condition field
15725 OT_cinfix3, /* Instruction takes a conditional infix,
15726 beginning at character index 3. (In
15727 unified mode, it becomes a suffix.) */
15728 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15729 tsts, cmps, cmns, and teqs. */
15730 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15731 character index 3, even in unified mode. Used for
15732 legacy instructions where suffix and infix forms
15733 may be ambiguous. */
15734 OT_csuf_or_in3, /* Instruction takes either a conditional
15735 suffix or an infix at character index 3. */
15736 OT_odd_infix_unc, /* This is the unconditional variant of an
15737 instruction that takes a conditional infix
15738 at an unusual position. In unified mode,
15739 this variant will accept a suffix. */
15740 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15741 are the conditional variants of instructions that
15742 take conditional infixes in unusual positions.
15743 The infix appears at character index
15744 (tag - OT_odd_infix_0). These are not accepted
15745 in unified mode. */
15748 /* Subroutine of md_assemble, responsible for looking up the primary
15749 opcode from the mnemonic the user wrote. STR points to the
15750 beginning of the mnemonic.
15752 This is not simply a hash table lookup, because of conditional
15753 variants. Most instructions have conditional variants, which are
15754 expressed with a _conditional affix_ to the mnemonic. If we were
15755 to encode each conditional variant as a literal string in the opcode
15756 table, it would have approximately 20,000 entries.
15758 Most mnemonics take this affix as a suffix, and in unified syntax,
15759 'most' is upgraded to 'all'. However, in the divided syntax, some
15760 instructions take the affix as an infix, notably the s-variants of
15761 the arithmetic instructions. Of those instructions, all but six
15762 have the infix appear after the third character of the mnemonic.
15764 Accordingly, the algorithm for looking up primary opcodes given
15767 1. Look up the identifier in the opcode table.
15768 If we find a match, go to step U.
15770 2. Look up the last two characters of the identifier in the
15771 conditions table. If we find a match, look up the first N-2
15772 characters of the identifier in the opcode table. If we
15773 find a match, go to step CE.
15775 3. Look up the fourth and fifth characters of the identifier in
15776 the conditions table. If we find a match, extract those
15777 characters from the identifier, and look up the remaining
15778 characters in the opcode table. If we find a match, go
15783 U. Examine the tag field of the opcode structure, in case this is
15784 one of the six instructions with its conditional infix in an
15785 unusual place. If it is, the tag tells us where to find the
15786 infix; look it up in the conditions table and set inst.cond
15787 accordingly. Otherwise, this is an unconditional instruction.
15788 Again set inst.cond accordingly. Return the opcode structure.
15790 CE. Examine the tag field to make sure this is an instruction that
15791 should receive a conditional suffix. If it is not, fail.
15792 Otherwise, set inst.cond from the suffix we already looked up,
15793 and return the opcode structure.
15795 CM. Examine the tag field to make sure this is an instruction that
15796 should receive a conditional infix after the third character.
15797 If it is not, fail. Otherwise, undo the edits to the current
15798 line of input and proceed as for case CE. */
15800 static const struct asm_opcode *
15801 opcode_lookup (char **str)
15805 const struct asm_opcode *opcode;
15806 const struct asm_cond *cond;
15809 /* Scan up to the end of the mnemonic, which must end in white space,
15810 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15811 for (base = end = *str; *end != '\0'; end++)
15812 if (*end == ' ' || *end == '.')
15818 /* Handle a possible width suffix and/or Neon type suffix. */
15823 /* The .w and .n suffixes are only valid if the unified syntax is in
15825 if (unified_syntax && end[1] == 'w')
15827 else if (unified_syntax && end[1] == 'n')
15832 inst.vectype.elems = 0;
15834 *str = end + offset;
15836 if (end[offset] == '.')
15838 /* See if we have a Neon type suffix (possible in either unified or
15839 non-unified ARM syntax mode). */
15840 if (parse_neon_type (&inst.vectype, str) == FAIL)
15843 else if (end[offset] != '\0' && end[offset] != ' ')
15849 /* Look for unaffixed or special-case affixed mnemonic. */
15850 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15855 if (opcode->tag < OT_odd_infix_0)
15857 inst.cond = COND_ALWAYS;
15861 if (warn_on_deprecated && unified_syntax)
15862 as_warn (_("conditional infixes are deprecated in unified syntax"));
15863 affix = base + (opcode->tag - OT_odd_infix_0);
15864 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15867 inst.cond = cond->value;
15871 /* Cannot have a conditional suffix on a mnemonic of less than two
15873 if (end - base < 3)
15876 /* Look for suffixed mnemonic. */
15878 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15879 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15881 if (opcode && cond)
15884 switch (opcode->tag)
15886 case OT_cinfix3_legacy:
15887 /* Ignore conditional suffixes matched on infix only mnemonics. */
15891 case OT_cinfix3_deprecated:
15892 case OT_odd_infix_unc:
15893 if (!unified_syntax)
15895 /* else fall through */
15899 case OT_csuf_or_in3:
15900 inst.cond = cond->value;
15903 case OT_unconditional:
15904 case OT_unconditionalF:
15906 inst.cond = cond->value;
15909 /* Delayed diagnostic. */
15910 inst.error = BAD_COND;
15911 inst.cond = COND_ALWAYS;
15920 /* Cannot have a usual-position infix on a mnemonic of less than
15921 six characters (five would be a suffix). */
15922 if (end - base < 6)
15925 /* Look for infixed mnemonic in the usual position. */
15927 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15931 memcpy (save, affix, 2);
15932 memmove (affix, affix + 2, (end - affix) - 2);
15933 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15935 memmove (affix + 2, affix, (end - affix) - 2);
15936 memcpy (affix, save, 2);
15939 && (opcode->tag == OT_cinfix3
15940 || opcode->tag == OT_cinfix3_deprecated
15941 || opcode->tag == OT_csuf_or_in3
15942 || opcode->tag == OT_cinfix3_legacy))
15945 if (warn_on_deprecated && unified_syntax
15946 && (opcode->tag == OT_cinfix3
15947 || opcode->tag == OT_cinfix3_deprecated))
15948 as_warn (_("conditional infixes are deprecated in unified syntax"));
15950 inst.cond = cond->value;
15957 /* This function generates an initial IT instruction, leaving its block
15958 virtually open for the new instructions. Eventually,
15959 the mask will be updated by now_it_add_mask () each time
15960 a new instruction needs to be included in the IT block.
15961 Finally, the block is closed with close_automatic_it_block ().
15962 The block closure can be requested either from md_assemble (),
15963 a tencode (), or due to a label hook. */
15966 new_automatic_it_block (int cond)
15968 now_it.state = AUTOMATIC_IT_BLOCK;
15969 now_it.mask = 0x18;
15971 now_it.block_length = 1;
15972 mapping_state (MAP_THUMB);
15973 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
15976 /* Close an automatic IT block.
15977 See comments in new_automatic_it_block (). */
15980 close_automatic_it_block (void)
15982 now_it.mask = 0x10;
15983 now_it.block_length = 0;
15986 /* Update the mask of the current automatically-generated IT
15987 instruction. See comments in new_automatic_it_block (). */
15990 now_it_add_mask (int cond)
15992 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15993 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15994 | ((bitvalue) << (nbit)))
15995 const int resulting_bit = (cond & 1);
15997 now_it.mask &= 0xf;
15998 now_it.mask = SET_BIT_VALUE (now_it.mask,
16000 (5 - now_it.block_length));
16001 now_it.mask = SET_BIT_VALUE (now_it.mask,
16003 ((5 - now_it.block_length) - 1) );
16004 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16007 #undef SET_BIT_VALUE
16010 /* The IT blocks handling machinery is accessed through the these functions:
16011 it_fsm_pre_encode () from md_assemble ()
16012 set_it_insn_type () optional, from the tencode functions
16013 set_it_insn_type_last () ditto
16014 in_it_block () ditto
16015 it_fsm_post_encode () from md_assemble ()
16016 force_automatic_it_block_close () from label habdling functions
16019 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16020 initializing the IT insn type with a generic initial value depending
16021 on the inst.condition.
16022 2) During the tencode function, two things may happen:
16023 a) The tencode function overrides the IT insn type by
16024 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16025 b) The tencode function queries the IT block state by
16026 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16028 Both set_it_insn_type and in_it_block run the internal FSM state
16029 handling function (handle_it_state), because: a) setting the IT insn
16030 type may incur in an invalid state (exiting the function),
16031 and b) querying the state requires the FSM to be updated.
16032 Specifically we want to avoid creating an IT block for conditional
16033 branches, so it_fsm_pre_encode is actually a guess and we can't
16034 determine whether an IT block is required until the tencode () routine
16035 has decided what type of instruction this actually it.
16036 Because of this, if set_it_insn_type and in_it_block have to be used,
16037 set_it_insn_type has to be called first.
16039 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16040 determines the insn IT type depending on the inst.cond code.
16041 When a tencode () routine encodes an instruction that can be
16042 either outside an IT block, or, in the case of being inside, has to be
16043 the last one, set_it_insn_type_last () will determine the proper
16044 IT instruction type based on the inst.cond code. Otherwise,
16045 set_it_insn_type can be called for overriding that logic or
16046 for covering other cases.
16048 Calling handle_it_state () may not transition the IT block state to
16049 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16050 still queried. Instead, if the FSM determines that the state should
16051 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16052 after the tencode () function: that's what it_fsm_post_encode () does.
16054 Since in_it_block () calls the state handling function to get an
16055 updated state, an error may occur (due to invalid insns combination).
16056 In that case, inst.error is set.
16057 Therefore, inst.error has to be checked after the execution of
16058 the tencode () routine.
16060 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16061 any pending state change (if any) that didn't take place in
16062 handle_it_state () as explained above. */
16065 it_fsm_pre_encode (void)
16067 if (inst.cond != COND_ALWAYS)
16068 inst.it_insn_type = INSIDE_IT_INSN;
16070 inst.it_insn_type = OUTSIDE_IT_INSN;
16072 now_it.state_handled = 0;
16075 /* IT state FSM handling function. */
16078 handle_it_state (void)
16080 now_it.state_handled = 1;
16082 switch (now_it.state)
16084 case OUTSIDE_IT_BLOCK:
16085 switch (inst.it_insn_type)
16087 case OUTSIDE_IT_INSN:
16090 case INSIDE_IT_INSN:
16091 case INSIDE_IT_LAST_INSN:
16092 if (thumb_mode == 0)
16095 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16096 as_tsktsk (_("Warning: conditional outside an IT block"\
16101 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16102 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16104 /* Automatically generate the IT instruction. */
16105 new_automatic_it_block (inst.cond);
16106 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16107 close_automatic_it_block ();
16111 inst.error = BAD_OUT_IT;
16117 case IF_INSIDE_IT_LAST_INSN:
16118 case NEUTRAL_IT_INSN:
16122 now_it.state = MANUAL_IT_BLOCK;
16123 now_it.block_length = 0;
16128 case AUTOMATIC_IT_BLOCK:
16129 /* Three things may happen now:
16130 a) We should increment current it block size;
16131 b) We should close current it block (closing insn or 4 insns);
16132 c) We should close current it block and start a new one (due
16133 to incompatible conditions or
16134 4 insns-length block reached). */
16136 switch (inst.it_insn_type)
16138 case OUTSIDE_IT_INSN:
16139 /* The closure of the block shall happen immediatelly,
16140 so any in_it_block () call reports the block as closed. */
16141 force_automatic_it_block_close ();
16144 case INSIDE_IT_INSN:
16145 case INSIDE_IT_LAST_INSN:
16146 case IF_INSIDE_IT_LAST_INSN:
16147 now_it.block_length++;
16149 if (now_it.block_length > 4
16150 || !now_it_compatible (inst.cond))
16152 force_automatic_it_block_close ();
16153 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16154 new_automatic_it_block (inst.cond);
16158 now_it_add_mask (inst.cond);
16161 if (now_it.state == AUTOMATIC_IT_BLOCK
16162 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16163 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16164 close_automatic_it_block ();
16167 case NEUTRAL_IT_INSN:
16168 now_it.block_length++;
16170 if (now_it.block_length > 4)
16171 force_automatic_it_block_close ();
16173 now_it_add_mask (now_it.cc & 1);
16177 close_automatic_it_block ();
16178 now_it.state = MANUAL_IT_BLOCK;
16183 case MANUAL_IT_BLOCK:
16185 /* Check conditional suffixes. */
16186 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16189 now_it.mask &= 0x1f;
16190 is_last = (now_it.mask == 0x10);
16192 switch (inst.it_insn_type)
16194 case OUTSIDE_IT_INSN:
16195 inst.error = BAD_NOT_IT;
16198 case INSIDE_IT_INSN:
16199 if (cond != inst.cond)
16201 inst.error = BAD_IT_COND;
16206 case INSIDE_IT_LAST_INSN:
16207 case IF_INSIDE_IT_LAST_INSN:
16208 if (cond != inst.cond)
16210 inst.error = BAD_IT_COND;
16215 inst.error = BAD_BRANCH;
16220 case NEUTRAL_IT_INSN:
16221 /* The BKPT instruction is unconditional even in an IT block. */
16225 inst.error = BAD_IT_IT;
16236 it_fsm_post_encode (void)
16240 if (!now_it.state_handled)
16241 handle_it_state ();
16243 is_last = (now_it.mask == 0x10);
16246 now_it.state = OUTSIDE_IT_BLOCK;
16252 force_automatic_it_block_close (void)
16254 if (now_it.state == AUTOMATIC_IT_BLOCK)
16256 close_automatic_it_block ();
16257 now_it.state = OUTSIDE_IT_BLOCK;
16265 if (!now_it.state_handled)
16266 handle_it_state ();
16268 return now_it.state != OUTSIDE_IT_BLOCK;
16272 md_assemble (char *str)
16275 const struct asm_opcode * opcode;
16277 /* Align the previous label if needed. */
16278 if (last_label_seen != NULL)
16280 symbol_set_frag (last_label_seen, frag_now);
16281 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16282 S_SET_SEGMENT (last_label_seen, now_seg);
16285 memset (&inst, '\0', sizeof (inst));
16286 inst.reloc.type = BFD_RELOC_UNUSED;
16288 opcode = opcode_lookup (&p);
16291 /* It wasn't an instruction, but it might be a register alias of
16292 the form alias .req reg, or a Neon .dn/.qn directive. */
16293 if (! create_register_alias (str, p)
16294 && ! create_neon_reg_alias (str, p))
16295 as_bad (_("bad instruction `%s'"), str);
16300 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16301 as_warn (_("s suffix on comparison instruction is deprecated"));
16303 /* The value which unconditional instructions should have in place of the
16304 condition field. */
16305 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16309 arm_feature_set variant;
16311 variant = cpu_variant;
16312 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16313 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16314 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16315 /* Check that this instruction is supported for this CPU. */
16316 if (!opcode->tvariant
16317 || (thumb_mode == 1
16318 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16320 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16323 if (inst.cond != COND_ALWAYS && !unified_syntax
16324 && opcode->tencode != do_t_branch)
16326 as_bad (_("Thumb does not support conditional execution"));
16330 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16332 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16333 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16334 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16336 /* Two things are addressed here.
16337 1) Implicit require narrow instructions on Thumb-1.
16338 This avoids relaxation accidentally introducing Thumb-2
16340 2) Reject wide instructions in non Thumb-2 cores. */
16341 if (inst.size_req == 0)
16343 else if (inst.size_req == 4)
16345 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16351 inst.instruction = opcode->tvalue;
16353 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16355 /* Prepare the it_insn_type for those encodings that don't set
16357 it_fsm_pre_encode ();
16359 opcode->tencode ();
16361 it_fsm_post_encode ();
16364 if (!(inst.error || inst.relax))
16366 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16367 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16368 if (inst.size_req && inst.size_req != inst.size)
16370 as_bad (_("cannot honor width suffix -- `%s'"), str);
16375 /* Something has gone badly wrong if we try to relax a fixed size
16377 gas_assert (inst.size_req == 0 || !inst.relax);
16379 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16380 *opcode->tvariant);
16381 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16382 set those bits when Thumb-2 32-bit instructions are seen. ie.
16383 anything other than bl/blx and v6-M instructions.
16384 This is overly pessimistic for relaxable instructions. */
16385 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16387 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16388 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16389 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16392 check_neon_suffixes;
16396 mapping_state (MAP_THUMB);
16399 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16403 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16404 is_bx = (opcode->aencode == do_bx);
16406 /* Check that this instruction is supported for this CPU. */
16407 if (!(is_bx && fix_v4bx)
16408 && !(opcode->avariant &&
16409 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16411 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16416 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16420 inst.instruction = opcode->avalue;
16421 if (opcode->tag == OT_unconditionalF)
16422 inst.instruction |= 0xF << 28;
16424 inst.instruction |= inst.cond << 28;
16425 inst.size = INSN_SIZE;
16426 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16428 it_fsm_pre_encode ();
16429 opcode->aencode ();
16430 it_fsm_post_encode ();
16432 /* Arm mode bx is marked as both v4T and v5 because it's still required
16433 on a hypothetical non-thumb v5 core. */
16435 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16437 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16438 *opcode->avariant);
16440 check_neon_suffixes;
16444 mapping_state (MAP_ARM);
16449 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16457 check_it_blocks_finished (void)
16462 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16463 if (seg_info (sect)->tc_segment_info_data.current_it.state
16464 == MANUAL_IT_BLOCK)
16466 as_warn (_("section '%s' finished with an open IT block."),
16470 if (now_it.state == MANUAL_IT_BLOCK)
16471 as_warn (_("file finished with an open IT block."));
16475 /* Various frobbings of labels and their addresses. */
16478 arm_start_line_hook (void)
16480 last_label_seen = NULL;
16484 arm_frob_label (symbolS * sym)
16486 last_label_seen = sym;
16488 ARM_SET_THUMB (sym, thumb_mode);
16490 #if defined OBJ_COFF || defined OBJ_ELF
16491 ARM_SET_INTERWORK (sym, support_interwork);
16494 force_automatic_it_block_close ();
16496 /* Note - do not allow local symbols (.Lxxx) to be labelled
16497 as Thumb functions. This is because these labels, whilst
16498 they exist inside Thumb code, are not the entry points for
16499 possible ARM->Thumb calls. Also, these labels can be used
16500 as part of a computed goto or switch statement. eg gcc
16501 can generate code that looks like this:
16503 ldr r2, [pc, .Laaa]
16513 The first instruction loads the address of the jump table.
16514 The second instruction converts a table index into a byte offset.
16515 The third instruction gets the jump address out of the table.
16516 The fourth instruction performs the jump.
16518 If the address stored at .Laaa is that of a symbol which has the
16519 Thumb_Func bit set, then the linker will arrange for this address
16520 to have the bottom bit set, which in turn would mean that the
16521 address computation performed by the third instruction would end
16522 up with the bottom bit set. Since the ARM is capable of unaligned
16523 word loads, the instruction would then load the incorrect address
16524 out of the jump table, and chaos would ensue. */
16525 if (label_is_thumb_function_name
16526 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16527 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16529 /* When the address of a Thumb function is taken the bottom
16530 bit of that address should be set. This will allow
16531 interworking between Arm and Thumb functions to work
16534 THUMB_SET_FUNC (sym, 1);
16536 label_is_thumb_function_name = FALSE;
16539 dwarf2_emit_label (sym);
16543 arm_data_in_code (void)
16545 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16547 *input_line_pointer = '/';
16548 input_line_pointer += 5;
16549 *input_line_pointer = 0;
16557 arm_canonicalize_symbol_name (char * name)
16561 if (thumb_mode && (len = strlen (name)) > 5
16562 && streq (name + len - 5, "/data"))
16563 *(name + len - 5) = 0;
16568 /* Table of all register names defined by default. The user can
16569 define additional names with .req. Note that all register names
16570 should appear in both upper and lowercase variants. Some registers
16571 also have mixed-case names. */
16573 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16574 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16575 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16576 #define REGSET(p,t) \
16577 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16578 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16579 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16580 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16581 #define REGSETH(p,t) \
16582 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16583 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16584 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16585 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16586 #define REGSET2(p,t) \
16587 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16588 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16589 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16590 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16591 #define SPLRBANK(base,bank,t) \
16592 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16593 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16594 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16595 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16596 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16597 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16599 static const struct reg_entry reg_names[] =
16601 /* ARM integer registers. */
16602 REGSET(r, RN), REGSET(R, RN),
16604 /* ATPCS synonyms. */
16605 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16606 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16607 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16609 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16610 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16611 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16613 /* Well-known aliases. */
16614 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16615 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16617 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16618 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16620 /* Coprocessor numbers. */
16621 REGSET(p, CP), REGSET(P, CP),
16623 /* Coprocessor register numbers. The "cr" variants are for backward
16625 REGSET(c, CN), REGSET(C, CN),
16626 REGSET(cr, CN), REGSET(CR, CN),
16628 /* ARM banked registers. */
16629 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16630 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16631 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16632 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16633 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16634 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16635 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16637 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16638 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16639 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16640 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16641 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16642 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16643 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16644 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16646 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16647 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16648 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16649 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16650 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16651 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16652 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16653 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16654 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16656 /* FPA registers. */
16657 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16658 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16660 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16661 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16663 /* VFP SP registers. */
16664 REGSET(s,VFS), REGSET(S,VFS),
16665 REGSETH(s,VFS), REGSETH(S,VFS),
16667 /* VFP DP Registers. */
16668 REGSET(d,VFD), REGSET(D,VFD),
16669 /* Extra Neon DP registers. */
16670 REGSETH(d,VFD), REGSETH(D,VFD),
16672 /* Neon QP registers. */
16673 REGSET2(q,NQ), REGSET2(Q,NQ),
16675 /* VFP control registers. */
16676 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16677 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16678 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16679 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16680 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16681 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16683 /* Maverick DSP coprocessor registers. */
16684 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16685 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16687 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16688 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16689 REGDEF(dspsc,0,DSPSC),
16691 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16692 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16693 REGDEF(DSPSC,0,DSPSC),
16695 /* iWMMXt data registers - p0, c0-15. */
16696 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16698 /* iWMMXt control registers - p1, c0-3. */
16699 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16700 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16701 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16702 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16704 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16705 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16706 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16707 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16708 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16710 /* XScale accumulator registers. */
16711 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16717 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16718 within psr_required_here. */
16719 static const struct asm_psr psrs[] =
16721 /* Backward compatibility notation. Note that "all" is no longer
16722 truly all possible PSR bits. */
16723 {"all", PSR_c | PSR_f},
16727 /* Individual flags. */
16733 /* Combinations of flags. */
16734 {"fs", PSR_f | PSR_s},
16735 {"fx", PSR_f | PSR_x},
16736 {"fc", PSR_f | PSR_c},
16737 {"sf", PSR_s | PSR_f},
16738 {"sx", PSR_s | PSR_x},
16739 {"sc", PSR_s | PSR_c},
16740 {"xf", PSR_x | PSR_f},
16741 {"xs", PSR_x | PSR_s},
16742 {"xc", PSR_x | PSR_c},
16743 {"cf", PSR_c | PSR_f},
16744 {"cs", PSR_c | PSR_s},
16745 {"cx", PSR_c | PSR_x},
16746 {"fsx", PSR_f | PSR_s | PSR_x},
16747 {"fsc", PSR_f | PSR_s | PSR_c},
16748 {"fxs", PSR_f | PSR_x | PSR_s},
16749 {"fxc", PSR_f | PSR_x | PSR_c},
16750 {"fcs", PSR_f | PSR_c | PSR_s},
16751 {"fcx", PSR_f | PSR_c | PSR_x},
16752 {"sfx", PSR_s | PSR_f | PSR_x},
16753 {"sfc", PSR_s | PSR_f | PSR_c},
16754 {"sxf", PSR_s | PSR_x | PSR_f},
16755 {"sxc", PSR_s | PSR_x | PSR_c},
16756 {"scf", PSR_s | PSR_c | PSR_f},
16757 {"scx", PSR_s | PSR_c | PSR_x},
16758 {"xfs", PSR_x | PSR_f | PSR_s},
16759 {"xfc", PSR_x | PSR_f | PSR_c},
16760 {"xsf", PSR_x | PSR_s | PSR_f},
16761 {"xsc", PSR_x | PSR_s | PSR_c},
16762 {"xcf", PSR_x | PSR_c | PSR_f},
16763 {"xcs", PSR_x | PSR_c | PSR_s},
16764 {"cfs", PSR_c | PSR_f | PSR_s},
16765 {"cfx", PSR_c | PSR_f | PSR_x},
16766 {"csf", PSR_c | PSR_s | PSR_f},
16767 {"csx", PSR_c | PSR_s | PSR_x},
16768 {"cxf", PSR_c | PSR_x | PSR_f},
16769 {"cxs", PSR_c | PSR_x | PSR_s},
16770 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16771 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16772 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16773 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16774 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16775 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16776 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16777 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16778 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16779 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16780 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16781 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16782 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16783 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16784 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16785 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16786 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16787 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16788 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16789 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16790 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16791 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16792 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16793 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16796 /* Table of V7M psr names. */
16797 static const struct asm_psr v7m_psrs[] =
16799 {"apsr", 0 }, {"APSR", 0 },
16800 {"iapsr", 1 }, {"IAPSR", 1 },
16801 {"eapsr", 2 }, {"EAPSR", 2 },
16802 {"psr", 3 }, {"PSR", 3 },
16803 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16804 {"ipsr", 5 }, {"IPSR", 5 },
16805 {"epsr", 6 }, {"EPSR", 6 },
16806 {"iepsr", 7 }, {"IEPSR", 7 },
16807 {"msp", 8 }, {"MSP", 8 },
16808 {"psp", 9 }, {"PSP", 9 },
16809 {"primask", 16}, {"PRIMASK", 16},
16810 {"basepri", 17}, {"BASEPRI", 17},
16811 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16812 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16813 {"faultmask", 19}, {"FAULTMASK", 19},
16814 {"control", 20}, {"CONTROL", 20}
16817 /* Table of all shift-in-operand names. */
16818 static const struct asm_shift_name shift_names [] =
16820 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16821 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16822 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16823 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16824 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16825 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16828 /* Table of all explicit relocation names. */
16830 static struct reloc_entry reloc_names[] =
16832 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16833 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16834 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16835 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16836 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16837 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16838 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16839 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16840 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16841 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16842 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16843 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16844 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16845 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16846 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16847 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16848 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16849 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16853 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16854 static const struct asm_cond conds[] =
16858 {"cs", 0x2}, {"hs", 0x2},
16859 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16873 static struct asm_barrier_opt barrier_opt_names[] =
16875 { "sy", 0xf }, { "SY", 0xf },
16876 { "un", 0x7 }, { "UN", 0x7 },
16877 { "st", 0xe }, { "ST", 0xe },
16878 { "unst", 0x6 }, { "UNST", 0x6 },
16879 { "ish", 0xb }, { "ISH", 0xb },
16880 { "sh", 0xb }, { "SH", 0xb },
16881 { "ishst", 0xa }, { "ISHST", 0xa },
16882 { "shst", 0xa }, { "SHST", 0xa },
16883 { "nsh", 0x7 }, { "NSH", 0x7 },
16884 { "nshst", 0x6 }, { "NSHST", 0x6 },
16885 { "osh", 0x3 }, { "OSH", 0x3 },
16886 { "oshst", 0x2 }, { "OSHST", 0x2 }
16889 /* Table of ARM-format instructions. */
16891 /* Macros for gluing together operand strings. N.B. In all cases
16892 other than OPS0, the trailing OP_stop comes from default
16893 zero-initialization of the unspecified elements of the array. */
16894 #define OPS0() { OP_stop, }
16895 #define OPS1(a) { OP_##a, }
16896 #define OPS2(a,b) { OP_##a,OP_##b, }
16897 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16898 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16899 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16900 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16902 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16903 This is useful when mixing operands for ARM and THUMB, i.e. using the
16904 MIX_ARM_THUMB_OPERANDS macro.
16905 In order to use these macros, prefix the number of operands with _
16907 #define OPS_1(a) { a, }
16908 #define OPS_2(a,b) { a,b, }
16909 #define OPS_3(a,b,c) { a,b,c, }
16910 #define OPS_4(a,b,c,d) { a,b,c,d, }
16911 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16912 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16914 /* These macros abstract out the exact format of the mnemonic table and
16915 save some repeated characters. */
16917 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16918 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16919 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16920 THUMB_VARIANT, do_##ae, do_##te }
16922 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16923 a T_MNEM_xyz enumerator. */
16924 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16925 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16926 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16927 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16929 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16930 infix after the third character. */
16931 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16932 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16933 THUMB_VARIANT, do_##ae, do_##te }
16934 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16935 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16936 THUMB_VARIANT, do_##ae, do_##te }
16937 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16938 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16939 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16940 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16941 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16942 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16943 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16944 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16946 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16947 appear in the condition table. */
16948 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16949 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16950 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16952 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16953 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16954 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16955 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16956 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16957 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16958 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16959 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16960 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16961 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16962 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16963 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16964 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16965 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16966 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16967 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16968 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16969 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16970 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16971 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16973 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16974 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16975 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16976 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16978 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16979 field is still 0xE. Many of the Thumb variants can be executed
16980 conditionally, so this is checked separately. */
16981 #define TUE(mnem, op, top, nops, ops, ae, te) \
16982 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16983 THUMB_VARIANT, do_##ae, do_##te }
16985 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16986 condition code field. */
16987 #define TUF(mnem, op, top, nops, ops, ae, te) \
16988 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16989 THUMB_VARIANT, do_##ae, do_##te }
16991 /* ARM-only variants of all the above. */
16992 #define CE(mnem, op, nops, ops, ae) \
16993 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16995 #define C3(mnem, op, nops, ops, ae) \
16996 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16998 /* Legacy mnemonics that always have conditional infix after the third
17000 #define CL(mnem, op, nops, ops, ae) \
17001 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17002 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17004 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17005 #define cCE(mnem, op, nops, ops, ae) \
17006 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17008 /* Legacy coprocessor instructions where conditional infix and conditional
17009 suffix are ambiguous. For consistency this includes all FPA instructions,
17010 not just the potentially ambiguous ones. */
17011 #define cCL(mnem, op, nops, ops, ae) \
17012 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17013 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17015 /* Coprocessor, takes either a suffix or a position-3 infix
17016 (for an FPA corner case). */
17017 #define C3E(mnem, op, nops, ops, ae) \
17018 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17019 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17021 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17022 { m1 #m2 m3, OPS##nops ops, \
17023 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17024 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17026 #define CM(m1, m2, op, nops, ops, ae) \
17027 xCM_ (m1, , m2, op, nops, ops, ae), \
17028 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17029 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17030 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17031 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17032 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17033 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17034 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17035 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17036 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17037 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17038 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17039 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17040 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17041 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17042 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17043 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17044 xCM_ (m1, le, m2, op, nops, ops, ae), \
17045 xCM_ (m1, al, m2, op, nops, ops, ae)
17047 #define UE(mnem, op, nops, ops, ae) \
17048 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17050 #define UF(mnem, op, nops, ops, ae) \
17051 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17053 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17054 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17055 use the same encoding function for each. */
17056 #define NUF(mnem, op, nops, ops, enc) \
17057 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17058 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17060 /* Neon data processing, version which indirects through neon_enc_tab for
17061 the various overloaded versions of opcodes. */
17062 #define nUF(mnem, op, nops, ops, enc) \
17063 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17064 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17066 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17068 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17069 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17070 THUMB_VARIANT, do_##enc, do_##enc }
17072 #define NCE(mnem, op, nops, ops, enc) \
17073 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17075 #define NCEF(mnem, op, nops, ops, enc) \
17076 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17078 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17079 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17080 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17081 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17083 #define nCE(mnem, op, nops, ops, enc) \
17084 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17086 #define nCEF(mnem, op, nops, ops, enc) \
17087 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17091 static const struct asm_opcode insns[] =
17093 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17094 #define THUMB_VARIANT &arm_ext_v4t
17095 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17096 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17097 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17098 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17099 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17100 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17101 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17102 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17103 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17104 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17105 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17106 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17107 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17108 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17109 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17110 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17112 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17113 for setting PSR flag bits. They are obsolete in V6 and do not
17114 have Thumb equivalents. */
17115 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17116 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17117 CL("tstp", 110f000, 2, (RR, SH), cmp),
17118 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17119 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17120 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17121 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17122 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17123 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17125 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17126 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17127 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17128 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17130 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17131 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17132 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17134 OP_ADDRGLDR),ldst, t_ldst),
17135 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17137 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17138 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17139 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17140 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17141 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17142 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17144 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17145 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17146 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17147 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17150 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17151 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17152 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17154 /* Thumb-compatibility pseudo ops. */
17155 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17156 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17157 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17158 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17159 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17160 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17161 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17162 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17163 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17164 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17165 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17166 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17168 /* These may simplify to neg. */
17169 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17170 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17172 #undef THUMB_VARIANT
17173 #define THUMB_VARIANT & arm_ext_v6
17175 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17177 /* V1 instructions with no Thumb analogue prior to V6T2. */
17178 #undef THUMB_VARIANT
17179 #define THUMB_VARIANT & arm_ext_v6t2
17181 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17182 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17183 CL("teqp", 130f000, 2, (RR, SH), cmp),
17185 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17186 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17187 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17188 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17190 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17191 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17193 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17194 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17196 /* V1 instructions with no Thumb analogue at all. */
17197 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17198 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17200 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17201 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17202 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17203 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17204 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17205 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17206 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17207 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17210 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17211 #undef THUMB_VARIANT
17212 #define THUMB_VARIANT & arm_ext_v4t
17214 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17215 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17217 #undef THUMB_VARIANT
17218 #define THUMB_VARIANT & arm_ext_v6t2
17220 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17221 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17223 /* Generic coprocessor instructions. */
17224 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17225 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17226 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17227 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17228 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17229 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17230 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17233 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17235 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17236 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17239 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17240 #undef THUMB_VARIANT
17241 #define THUMB_VARIANT & arm_ext_msr
17243 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17244 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17247 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17248 #undef THUMB_VARIANT
17249 #define THUMB_VARIANT & arm_ext_v6t2
17251 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17252 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17253 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17254 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17255 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17256 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17257 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17258 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17261 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17262 #undef THUMB_VARIANT
17263 #define THUMB_VARIANT & arm_ext_v4t
17265 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17266 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17267 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17268 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17269 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17270 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17273 #define ARM_VARIANT & arm_ext_v4t_5
17275 /* ARM Architecture 4T. */
17276 /* Note: bx (and blx) are required on V5, even if the processor does
17277 not support Thumb. */
17278 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17281 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17282 #undef THUMB_VARIANT
17283 #define THUMB_VARIANT & arm_ext_v5t
17285 /* Note: blx has 2 variants; the .value coded here is for
17286 BLX(2). Only this variant has conditional execution. */
17287 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17288 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17290 #undef THUMB_VARIANT
17291 #define THUMB_VARIANT & arm_ext_v6t2
17293 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17294 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17295 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17296 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17297 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17298 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17299 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17300 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17303 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17304 #undef THUMB_VARIANT
17305 #define THUMB_VARIANT &arm_ext_v5exp
17307 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17308 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17309 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17310 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17312 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17313 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17315 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17316 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17317 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17318 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17320 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17321 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17322 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17323 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17325 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17326 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17328 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17329 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17330 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17331 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17334 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17335 #undef THUMB_VARIANT
17336 #define THUMB_VARIANT &arm_ext_v6t2
17338 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17339 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17341 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17342 ADDRGLDRS), ldrd, t_ldstd),
17344 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17345 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17348 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17350 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17353 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17354 #undef THUMB_VARIANT
17355 #define THUMB_VARIANT & arm_ext_v6
17357 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17358 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17359 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17360 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17361 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17362 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17363 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17364 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17365 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17366 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17368 #undef THUMB_VARIANT
17369 #define THUMB_VARIANT & arm_ext_v6t2
17371 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17372 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17374 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17375 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17377 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17378 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17380 /* ARM V6 not included in V7M. */
17381 #undef THUMB_VARIANT
17382 #define THUMB_VARIANT & arm_ext_v6_notm
17383 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17384 UF(rfeib, 9900a00, 1, (RRw), rfe),
17385 UF(rfeda, 8100a00, 1, (RRw), rfe),
17386 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17387 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17388 UF(rfefa, 9900a00, 1, (RRw), rfe),
17389 UF(rfeea, 8100a00, 1, (RRw), rfe),
17390 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17391 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17392 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17393 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17394 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17396 /* ARM V6 not included in V7M (eg. integer SIMD). */
17397 #undef THUMB_VARIANT
17398 #define THUMB_VARIANT & arm_ext_v6_dsp
17399 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17400 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17401 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17402 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17403 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17404 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17405 /* Old name for QASX. */
17406 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17407 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17408 /* Old name for QSAX. */
17409 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17410 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17411 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17412 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17413 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17414 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17415 /* Old name for SASX. */
17416 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17417 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17418 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17419 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17420 /* Old name for SHASX. */
17421 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17422 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17423 /* Old name for SHSAX. */
17424 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17425 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17426 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17427 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17428 /* Old name for SSAX. */
17429 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17430 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17431 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17432 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17433 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17434 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17435 /* Old name for UASX. */
17436 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17437 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17438 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17439 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17440 /* Old name for UHASX. */
17441 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17442 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17443 /* Old name for UHSAX. */
17444 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17445 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17446 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17447 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17448 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17449 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17450 /* Old name for UQASX. */
17451 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17452 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17453 /* Old name for UQSAX. */
17454 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17455 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17456 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17457 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17458 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17459 /* Old name for USAX. */
17460 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17461 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17462 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17463 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17464 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17465 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17466 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17467 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17468 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17469 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17470 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17471 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17472 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17473 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17474 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17475 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17476 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17477 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17478 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17479 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17480 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17481 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17482 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17483 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17484 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17485 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17486 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17487 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17488 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17489 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17490 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17491 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17492 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17493 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17496 #define ARM_VARIANT & arm_ext_v6k
17497 #undef THUMB_VARIANT
17498 #define THUMB_VARIANT & arm_ext_v6k
17500 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17501 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17502 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17503 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17505 #undef THUMB_VARIANT
17506 #define THUMB_VARIANT & arm_ext_v6_notm
17507 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17509 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17510 RRnpcb), strexd, t_strexd),
17512 #undef THUMB_VARIANT
17513 #define THUMB_VARIANT & arm_ext_v6t2
17514 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17516 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17518 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17520 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17522 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17525 #define ARM_VARIANT & arm_ext_sec
17526 #undef THUMB_VARIANT
17527 #define THUMB_VARIANT & arm_ext_sec
17529 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17532 #define ARM_VARIANT & arm_ext_virt
17533 #undef THUMB_VARIANT
17534 #define THUMB_VARIANT & arm_ext_virt
17536 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17537 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17540 #define ARM_VARIANT & arm_ext_v6t2
17541 #undef THUMB_VARIANT
17542 #define THUMB_VARIANT & arm_ext_v6t2
17544 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17545 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17546 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17547 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17549 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17550 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17551 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17552 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17554 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17555 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17556 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17557 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17559 /* Thumb-only instructions. */
17561 #define ARM_VARIANT NULL
17562 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17563 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17565 /* ARM does not really have an IT instruction, so always allow it.
17566 The opcode is copied from Thumb in order to allow warnings in
17567 -mimplicit-it=[never | arm] modes. */
17569 #define ARM_VARIANT & arm_ext_v1
17571 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17572 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17573 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17574 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17575 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17576 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17577 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17578 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17579 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17580 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17581 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17582 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17583 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17584 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17585 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17586 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17587 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17588 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17590 /* Thumb2 only instructions. */
17592 #define ARM_VARIANT NULL
17594 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17595 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17596 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17597 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17598 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17599 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17601 /* Hardware division instructions. */
17603 #define ARM_VARIANT & arm_ext_adiv
17604 #undef THUMB_VARIANT
17605 #define THUMB_VARIANT & arm_ext_div
17607 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17608 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17610 /* ARM V6M/V7 instructions. */
17612 #define ARM_VARIANT & arm_ext_barrier
17613 #undef THUMB_VARIANT
17614 #define THUMB_VARIANT & arm_ext_barrier
17616 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17617 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17618 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17620 /* ARM V7 instructions. */
17622 #define ARM_VARIANT & arm_ext_v7
17623 #undef THUMB_VARIANT
17624 #define THUMB_VARIANT & arm_ext_v7
17626 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17627 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17630 #define ARM_VARIANT & arm_ext_mp
17631 #undef THUMB_VARIANT
17632 #define THUMB_VARIANT & arm_ext_mp
17634 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17637 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17639 cCE("wfs", e200110, 1, (RR), rd),
17640 cCE("rfs", e300110, 1, (RR), rd),
17641 cCE("wfc", e400110, 1, (RR), rd),
17642 cCE("rfc", e500110, 1, (RR), rd),
17644 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17645 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17646 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17647 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17649 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17650 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17651 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17652 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17654 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17655 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17656 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17657 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17658 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17659 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17660 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17661 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17662 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17663 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17664 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17665 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17667 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17668 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17669 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17670 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17671 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17672 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17673 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17674 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17675 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17676 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17677 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17678 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17680 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17681 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17682 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17683 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17684 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17685 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17686 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17687 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17688 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17689 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17690 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17691 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17693 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17694 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17695 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17696 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17697 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17698 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17699 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17700 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17701 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17702 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17703 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17704 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17706 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17707 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17708 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17709 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17710 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17711 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17712 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17713 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17714 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17715 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17716 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17717 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17719 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17720 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17721 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17722 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17723 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17724 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17725 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17726 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17727 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17728 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17729 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17730 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17732 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17733 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17734 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17735 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17736 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17737 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17738 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17739 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17740 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17741 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17742 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17743 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17745 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17746 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17747 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17748 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17749 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17750 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17751 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17752 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17753 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17754 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17755 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17756 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17758 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17759 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17760 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17761 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17762 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17763 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17764 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17765 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17766 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17767 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17768 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17769 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17771 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17772 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17773 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17774 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17775 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17776 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17777 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17778 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17779 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17780 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17781 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17782 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17784 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17785 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17786 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17787 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17788 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17789 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17790 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17791 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17792 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17793 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17794 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17795 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17797 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17798 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17799 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17800 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17801 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17802 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17803 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17804 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17805 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17806 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17807 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17808 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17810 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17811 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17812 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17813 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17814 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17815 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17816 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17817 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17818 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17819 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17820 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17821 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17823 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17824 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17825 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17826 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17827 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17828 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17829 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17830 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17831 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17832 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17833 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17834 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17836 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17837 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17838 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17839 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17840 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17841 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17842 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17843 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17844 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17845 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17846 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17847 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17849 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17850 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17851 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17852 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17853 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17854 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17855 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17856 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17857 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17858 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17859 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17860 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17862 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17863 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17864 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17865 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17866 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17867 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17868 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17869 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17870 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17871 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17872 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17873 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17875 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17876 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17877 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17878 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17879 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17880 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17881 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17882 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17883 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17884 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17885 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17886 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17888 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17889 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17890 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17891 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17892 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17893 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17894 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17895 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17896 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17897 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17898 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17899 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17901 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17902 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17903 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17904 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17905 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17906 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17907 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17908 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17909 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17911 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17917 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17919 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17921 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17922 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17924 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17958 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17960 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17961 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17962 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17963 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
17971 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17973 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17974 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
17975 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
17976 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
17984 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17986 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17987 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
17988 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18032 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18033 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18034 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18036 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18037 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18038 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18039 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18040 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18041 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18042 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18043 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18044 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18045 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18046 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18047 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18049 /* The implementation of the FIX instruction is broken on some
18050 assemblers, in that it accepts a precision specifier as well as a
18051 rounding specifier, despite the fact that this is meaningless.
18052 To be more compatible, we accept it as well, though of course it
18053 does not set any bits. */
18054 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18055 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18056 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18057 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18058 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18059 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18060 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18061 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18062 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18063 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18064 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18065 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18066 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18068 /* Instructions that were new with the real FPA, call them V2. */
18070 #define ARM_VARIANT & fpu_fpa_ext_v2
18072 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18073 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18074 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18075 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18076 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18077 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18080 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18082 /* Moves and type conversions. */
18083 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18084 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18085 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18086 cCE("fmstat", ef1fa10, 0, (), noargs),
18087 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18088 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18089 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18090 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18091 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18092 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18093 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18094 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18095 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18096 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18098 /* Memory operations. */
18099 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18100 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18101 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18102 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18103 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18104 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18105 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18106 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18107 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18108 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18109 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18110 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18111 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18112 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18113 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18114 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18115 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18116 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18118 /* Monadic operations. */
18119 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18120 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18121 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18123 /* Dyadic operations. */
18124 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18125 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18126 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18127 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18128 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18129 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18130 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18131 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18132 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18135 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18136 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18137 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18138 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18140 /* Double precision load/store are still present on single precision
18141 implementations. */
18142 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18143 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18144 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18145 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18146 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18147 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18148 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18149 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18150 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18151 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18154 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18156 /* Moves and type conversions. */
18157 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18158 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18159 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18160 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18161 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18162 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18163 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18164 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18165 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18166 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18167 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18168 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18169 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18171 /* Monadic operations. */
18172 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18173 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18174 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18176 /* Dyadic operations. */
18177 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18178 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18179 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18180 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18181 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18182 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18183 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18184 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18185 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18188 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18189 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18190 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18191 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18194 #define ARM_VARIANT & fpu_vfp_ext_v2
18196 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18197 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18198 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18199 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18201 /* Instructions which may belong to either the Neon or VFP instruction sets.
18202 Individual encoder functions perform additional architecture checks. */
18204 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18205 #undef THUMB_VARIANT
18206 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18208 /* These mnemonics are unique to VFP. */
18209 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18210 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18211 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18212 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18213 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18214 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18215 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18216 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18217 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18218 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18220 /* Mnemonics shared by Neon and VFP. */
18221 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18222 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18223 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18225 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18226 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18228 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18229 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18231 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18232 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18233 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18234 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18235 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18236 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18237 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18238 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18240 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18241 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18242 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18243 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18246 /* NOTE: All VMOV encoding is special-cased! */
18247 NCE(vmov, 0, 1, (VMOV), neon_mov),
18248 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18250 #undef THUMB_VARIANT
18251 #define THUMB_VARIANT & fpu_neon_ext_v1
18253 #define ARM_VARIANT & fpu_neon_ext_v1
18255 /* Data processing with three registers of the same length. */
18256 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18257 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18258 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18259 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18260 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18261 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18262 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18263 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18264 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18265 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18266 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18267 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18268 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18269 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18270 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18271 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18272 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18273 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18274 /* If not immediate, fall back to neon_dyadic_i64_su.
18275 shl_imm should accept I8 I16 I32 I64,
18276 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18277 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18278 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18279 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18280 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18281 /* Logic ops, types optional & ignored. */
18282 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18283 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18284 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18285 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18286 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18287 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18288 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18289 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18290 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18291 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18292 /* Bitfield ops, untyped. */
18293 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18294 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18295 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18296 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18297 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18298 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18299 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18300 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18301 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18302 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18303 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18304 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18305 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18306 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18307 back to neon_dyadic_if_su. */
18308 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18309 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18310 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18311 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18312 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18313 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18314 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18315 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18316 /* Comparison. Type I8 I16 I32 F32. */
18317 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18318 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18319 /* As above, D registers only. */
18320 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18321 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18322 /* Int and float variants, signedness unimportant. */
18323 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18324 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18325 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18326 /* Add/sub take types I8 I16 I32 I64 F32. */
18327 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18328 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18329 /* vtst takes sizes 8, 16, 32. */
18330 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18331 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18332 /* VMUL takes I8 I16 I32 F32 P8. */
18333 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18334 /* VQD{R}MULH takes S16 S32. */
18335 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18336 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18337 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18338 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18339 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18340 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18341 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18342 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18343 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18344 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18345 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18346 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18347 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18348 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18349 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18350 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18352 /* Two address, int/float. Types S8 S16 S32 F32. */
18353 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18354 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18356 /* Data processing with two registers and a shift amount. */
18357 /* Right shifts, and variants with rounding.
18358 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18359 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18360 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18361 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18362 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18363 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18364 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18365 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18366 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18367 /* Shift and insert. Sizes accepted 8 16 32 64. */
18368 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18369 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18370 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18371 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18372 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18373 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18374 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18375 /* Right shift immediate, saturating & narrowing, with rounding variants.
18376 Types accepted S16 S32 S64 U16 U32 U64. */
18377 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18378 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18379 /* As above, unsigned. Types accepted S16 S32 S64. */
18380 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18381 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18382 /* Right shift narrowing. Types accepted I16 I32 I64. */
18383 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18384 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18385 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18386 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18387 /* CVT with optional immediate for fixed-point variant. */
18388 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18390 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18391 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18393 /* Data processing, three registers of different lengths. */
18394 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18395 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18396 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18397 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18398 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18399 /* If not scalar, fall back to neon_dyadic_long.
18400 Vector types as above, scalar types S16 S32 U16 U32. */
18401 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18402 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18403 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18404 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18405 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18406 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18407 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18408 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18409 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18410 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18411 /* Saturating doubling multiplies. Types S16 S32. */
18412 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18413 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18414 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18415 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18416 S16 S32 U16 U32. */
18417 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18419 /* Extract. Size 8. */
18420 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18421 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18423 /* Two registers, miscellaneous. */
18424 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18425 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18426 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18427 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18428 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18429 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18430 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18431 /* Vector replicate. Sizes 8 16 32. */
18432 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18433 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18434 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18435 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18436 /* VMOVN. Types I16 I32 I64. */
18437 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18438 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18439 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18440 /* VQMOVUN. Types S16 S32 S64. */
18441 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18442 /* VZIP / VUZP. Sizes 8 16 32. */
18443 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18444 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18445 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18446 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18447 /* VQABS / VQNEG. Types S8 S16 S32. */
18448 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18449 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18450 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18451 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18452 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18453 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18454 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18455 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18456 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18457 /* Reciprocal estimates. Types U32 F32. */
18458 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18459 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18460 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18461 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18462 /* VCLS. Types S8 S16 S32. */
18463 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18464 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18465 /* VCLZ. Types I8 I16 I32. */
18466 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18467 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18468 /* VCNT. Size 8. */
18469 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18470 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18471 /* Two address, untyped. */
18472 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18473 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18474 /* VTRN. Sizes 8 16 32. */
18475 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18476 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18478 /* Table lookup. Size 8. */
18479 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18480 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18482 #undef THUMB_VARIANT
18483 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18485 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18487 /* Neon element/structure load/store. */
18488 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18489 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18490 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18491 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18492 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18493 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18494 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18495 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18497 #undef THUMB_VARIANT
18498 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18500 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18501 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18502 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18503 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18504 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18505 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18506 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18507 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18508 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18509 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18511 #undef THUMB_VARIANT
18512 #define THUMB_VARIANT & fpu_vfp_ext_v3
18514 #define ARM_VARIANT & fpu_vfp_ext_v3
18516 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18517 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18518 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18519 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18520 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18521 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18522 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18523 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18524 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18527 #define ARM_VARIANT &fpu_vfp_ext_fma
18528 #undef THUMB_VARIANT
18529 #define THUMB_VARIANT &fpu_vfp_ext_fma
18530 /* Mnemonics shared by Neon and VFP. These are included in the
18531 VFP FMA variant; NEON and VFP FMA always includes the NEON
18532 FMA instructions. */
18533 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18534 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18535 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18536 the v form should always be used. */
18537 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18538 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18539 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18540 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18541 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18542 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18544 #undef THUMB_VARIANT
18546 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18548 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18549 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18550 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18551 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18552 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18553 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18554 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18555 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18558 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18560 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18561 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18562 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18563 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18564 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18565 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18566 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18567 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18568 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18569 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18570 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18571 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18572 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18573 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18574 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18575 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18576 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18577 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18578 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18579 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18580 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18581 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18582 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18583 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18584 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18585 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18586 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18587 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18588 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18589 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18590 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18591 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18592 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18593 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18594 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18595 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18596 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18597 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18598 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18599 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18600 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18601 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18602 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18603 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18604 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18605 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18606 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18607 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18608 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18609 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18610 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18611 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18612 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18613 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18614 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18615 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18616 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18617 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18618 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18619 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18620 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18621 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18622 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18623 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18624 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18625 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18626 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18627 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18628 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18629 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18630 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18631 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18632 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18633 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18634 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18635 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18636 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18637 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18638 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18639 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18640 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18641 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18642 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18643 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18644 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18645 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18646 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18647 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18648 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18649 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18650 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18651 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18652 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18653 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18654 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18655 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18656 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18657 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18658 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18659 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18661 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18662 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18663 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18664 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18665 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18666 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18671 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18672 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18673 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18674 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18675 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18676 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18677 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18678 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18679 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18680 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18681 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18682 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18683 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18684 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18685 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18686 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18687 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18688 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18689 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18690 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18691 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18692 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18693 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18696 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18703 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18704 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18705 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18706 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18707 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18708 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18709 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18710 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18711 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18712 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18713 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18714 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18715 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18716 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18717 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18718 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18719 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18720 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18721 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18724 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18726 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18727 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18728 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18729 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18730 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18731 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18732 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18733 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18734 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18735 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18736 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18737 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18738 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18739 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18740 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18741 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18742 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18743 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18744 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18745 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18746 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18747 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18748 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18749 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18750 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18751 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18752 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18753 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18754 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18755 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18759 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18760 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18764 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18775 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18779 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18787 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18788 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18789 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18790 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18791 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18792 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18793 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18794 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18795 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18796 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18797 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18798 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18799 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18800 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18801 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18802 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18803 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18804 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18805 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18806 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18807 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18808 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18809 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18810 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18811 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18812 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18813 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18814 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18815 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18816 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18817 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18818 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18819 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18820 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18821 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18822 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18823 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18824 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18825 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18826 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18827 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18828 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18829 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18830 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18831 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18832 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18833 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18834 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18835 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18836 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18837 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18838 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18839 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18840 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18841 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18842 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18843 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18844 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18845 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18846 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18847 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18848 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18849 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18850 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18851 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18852 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18853 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18854 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18855 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18856 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18857 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18858 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18859 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18860 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18861 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18862 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18865 #undef THUMB_VARIANT
18892 /* MD interface: bits in the object file. */
18894 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18895 for use in the a.out file, and stores them in the array pointed to by buf.
18896 This knows about the endian-ness of the target machine and does
18897 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18898 2 (short) and 4 (long) Floating numbers are put out as a series of
18899 LITTLENUMS (shorts, here at least). */
18902 md_number_to_chars (char * buf, valueT val, int n)
18904 if (target_big_endian)
18905 number_to_chars_bigendian (buf, val, n);
18907 number_to_chars_littleendian (buf, val, n);
18911 md_chars_to_number (char * buf, int n)
18914 unsigned char * where = (unsigned char *) buf;
18916 if (target_big_endian)
18921 result |= (*where++ & 255);
18929 result |= (where[n] & 255);
18936 /* MD interface: Sections. */
18938 /* Estimate the size of a frag before relaxing. Assume everything fits in
18942 md_estimate_size_before_relax (fragS * fragp,
18943 segT segtype ATTRIBUTE_UNUSED)
18949 /* Convert a machine dependent frag. */
18952 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18954 unsigned long insn;
18955 unsigned long old_op;
18963 buf = fragp->fr_literal + fragp->fr_fix;
18965 old_op = bfd_get_16(abfd, buf);
18966 if (fragp->fr_symbol)
18968 exp.X_op = O_symbol;
18969 exp.X_add_symbol = fragp->fr_symbol;
18973 exp.X_op = O_constant;
18975 exp.X_add_number = fragp->fr_offset;
18976 opcode = fragp->fr_subtype;
18979 case T_MNEM_ldr_pc:
18980 case T_MNEM_ldr_pc2:
18981 case T_MNEM_ldr_sp:
18982 case T_MNEM_str_sp:
18989 if (fragp->fr_var == 4)
18991 insn = THUMB_OP32 (opcode);
18992 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
18994 insn |= (old_op & 0x700) << 4;
18998 insn |= (old_op & 7) << 12;
18999 insn |= (old_op & 0x38) << 13;
19001 insn |= 0x00000c00;
19002 put_thumb32_insn (buf, insn);
19003 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19007 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19009 pc_rel = (opcode == T_MNEM_ldr_pc2);
19012 if (fragp->fr_var == 4)
19014 insn = THUMB_OP32 (opcode);
19015 insn |= (old_op & 0xf0) << 4;
19016 put_thumb32_insn (buf, insn);
19017 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19021 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19022 exp.X_add_number -= 4;
19030 if (fragp->fr_var == 4)
19032 int r0off = (opcode == T_MNEM_mov
19033 || opcode == T_MNEM_movs) ? 0 : 8;
19034 insn = THUMB_OP32 (opcode);
19035 insn = (insn & 0xe1ffffff) | 0x10000000;
19036 insn |= (old_op & 0x700) << r0off;
19037 put_thumb32_insn (buf, insn);
19038 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19042 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19047 if (fragp->fr_var == 4)
19049 insn = THUMB_OP32(opcode);
19050 put_thumb32_insn (buf, insn);
19051 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19054 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19058 if (fragp->fr_var == 4)
19060 insn = THUMB_OP32(opcode);
19061 insn |= (old_op & 0xf00) << 14;
19062 put_thumb32_insn (buf, insn);
19063 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19066 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19069 case T_MNEM_add_sp:
19070 case T_MNEM_add_pc:
19071 case T_MNEM_inc_sp:
19072 case T_MNEM_dec_sp:
19073 if (fragp->fr_var == 4)
19075 /* ??? Choose between add and addw. */
19076 insn = THUMB_OP32 (opcode);
19077 insn |= (old_op & 0xf0) << 4;
19078 put_thumb32_insn (buf, insn);
19079 if (opcode == T_MNEM_add_pc)
19080 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19082 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19085 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19093 if (fragp->fr_var == 4)
19095 insn = THUMB_OP32 (opcode);
19096 insn |= (old_op & 0xf0) << 4;
19097 insn |= (old_op & 0xf) << 16;
19098 put_thumb32_insn (buf, insn);
19099 if (insn & (1 << 20))
19100 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19102 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19105 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19111 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19112 (enum bfd_reloc_code_real) reloc_type);
19113 fixp->fx_file = fragp->fr_file;
19114 fixp->fx_line = fragp->fr_line;
19115 fragp->fr_fix += fragp->fr_var;
19118 /* Return the size of a relaxable immediate operand instruction.
19119 SHIFT and SIZE specify the form of the allowable immediate. */
19121 relax_immediate (fragS *fragp, int size, int shift)
19127 /* ??? Should be able to do better than this. */
19128 if (fragp->fr_symbol)
19131 low = (1 << shift) - 1;
19132 mask = (1 << (shift + size)) - (1 << shift);
19133 offset = fragp->fr_offset;
19134 /* Force misaligned offsets to 32-bit variant. */
19137 if (offset & ~mask)
19142 /* Get the address of a symbol during relaxation. */
19144 relaxed_symbol_addr (fragS *fragp, long stretch)
19150 sym = fragp->fr_symbol;
19151 sym_frag = symbol_get_frag (sym);
19152 know (S_GET_SEGMENT (sym) != absolute_section
19153 || sym_frag == &zero_address_frag);
19154 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19156 /* If frag has yet to be reached on this pass, assume it will
19157 move by STRETCH just as we did. If this is not so, it will
19158 be because some frag between grows, and that will force
19162 && sym_frag->relax_marker != fragp->relax_marker)
19166 /* Adjust stretch for any alignment frag. Note that if have
19167 been expanding the earlier code, the symbol may be
19168 defined in what appears to be an earlier frag. FIXME:
19169 This doesn't handle the fr_subtype field, which specifies
19170 a maximum number of bytes to skip when doing an
19172 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19174 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19177 stretch = - ((- stretch)
19178 & ~ ((1 << (int) f->fr_offset) - 1));
19180 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19192 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19195 relax_adr (fragS *fragp, asection *sec, long stretch)
19200 /* Assume worst case for symbols not known to be in the same section. */
19201 if (fragp->fr_symbol == NULL
19202 || !S_IS_DEFINED (fragp->fr_symbol)
19203 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19204 || S_IS_WEAK (fragp->fr_symbol))
19207 val = relaxed_symbol_addr (fragp, stretch);
19208 addr = fragp->fr_address + fragp->fr_fix;
19209 addr = (addr + 4) & ~3;
19210 /* Force misaligned targets to 32-bit variant. */
19214 if (val < 0 || val > 1020)
19219 /* Return the size of a relaxable add/sub immediate instruction. */
19221 relax_addsub (fragS *fragp, asection *sec)
19226 buf = fragp->fr_literal + fragp->fr_fix;
19227 op = bfd_get_16(sec->owner, buf);
19228 if ((op & 0xf) == ((op >> 4) & 0xf))
19229 return relax_immediate (fragp, 8, 0);
19231 return relax_immediate (fragp, 3, 0);
19235 /* Return the size of a relaxable branch instruction. BITS is the
19236 size of the offset field in the narrow instruction. */
19239 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19245 /* Assume worst case for symbols not known to be in the same section. */
19246 if (!S_IS_DEFINED (fragp->fr_symbol)
19247 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19248 || S_IS_WEAK (fragp->fr_symbol))
19252 if (S_IS_DEFINED (fragp->fr_symbol)
19253 && ARM_IS_FUNC (fragp->fr_symbol))
19256 /* PR 12532. Global symbols with default visibility might
19257 be preempted, so do not relax relocations to them. */
19258 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19259 && (! S_IS_LOCAL (fragp->fr_symbol)))
19263 val = relaxed_symbol_addr (fragp, stretch);
19264 addr = fragp->fr_address + fragp->fr_fix + 4;
19267 /* Offset is a signed value *2 */
19269 if (val >= limit || val < -limit)
19275 /* Relax a machine dependent frag. This returns the amount by which
19276 the current size of the frag should change. */
19279 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19284 oldsize = fragp->fr_var;
19285 switch (fragp->fr_subtype)
19287 case T_MNEM_ldr_pc2:
19288 newsize = relax_adr (fragp, sec, stretch);
19290 case T_MNEM_ldr_pc:
19291 case T_MNEM_ldr_sp:
19292 case T_MNEM_str_sp:
19293 newsize = relax_immediate (fragp, 8, 2);
19297 newsize = relax_immediate (fragp, 5, 2);
19301 newsize = relax_immediate (fragp, 5, 1);
19305 newsize = relax_immediate (fragp, 5, 0);
19308 newsize = relax_adr (fragp, sec, stretch);
19314 newsize = relax_immediate (fragp, 8, 0);
19317 newsize = relax_branch (fragp, sec, 11, stretch);
19320 newsize = relax_branch (fragp, sec, 8, stretch);
19322 case T_MNEM_add_sp:
19323 case T_MNEM_add_pc:
19324 newsize = relax_immediate (fragp, 8, 2);
19326 case T_MNEM_inc_sp:
19327 case T_MNEM_dec_sp:
19328 newsize = relax_immediate (fragp, 7, 2);
19334 newsize = relax_addsub (fragp, sec);
19340 fragp->fr_var = newsize;
19341 /* Freeze wide instructions that are at or before the same location as
19342 in the previous pass. This avoids infinite loops.
19343 Don't freeze them unconditionally because targets may be artificially
19344 misaligned by the expansion of preceding frags. */
19345 if (stretch <= 0 && newsize > 2)
19347 md_convert_frag (sec->owner, sec, fragp);
19351 return newsize - oldsize;
19354 /* Round up a section size to the appropriate boundary. */
19357 md_section_align (segT segment ATTRIBUTE_UNUSED,
19360 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19361 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19363 /* For a.out, force the section size to be aligned. If we don't do
19364 this, BFD will align it for us, but it will not write out the
19365 final bytes of the section. This may be a bug in BFD, but it is
19366 easier to fix it here since that is how the other a.out targets
19370 align = bfd_get_section_alignment (stdoutput, segment);
19371 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19378 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19379 of an rs_align_code fragment. */
19382 arm_handle_align (fragS * fragP)
19384 static char const arm_noop[2][2][4] =
19387 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19388 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19391 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19392 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19395 static char const thumb_noop[2][2][2] =
19398 {0xc0, 0x46}, /* LE */
19399 {0x46, 0xc0}, /* BE */
19402 {0x00, 0xbf}, /* LE */
19403 {0xbf, 0x00} /* BE */
19406 static char const wide_thumb_noop[2][4] =
19407 { /* Wide Thumb-2 */
19408 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19409 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19412 unsigned bytes, fix, noop_size;
19415 const char *narrow_noop = NULL;
19420 if (fragP->fr_type != rs_align_code)
19423 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19424 p = fragP->fr_literal + fragP->fr_fix;
19427 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19428 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19430 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19432 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19434 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19436 narrow_noop = thumb_noop[1][target_big_endian];
19437 noop = wide_thumb_noop[target_big_endian];
19440 noop = thumb_noop[0][target_big_endian];
19448 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19449 [target_big_endian];
19456 fragP->fr_var = noop_size;
19458 if (bytes & (noop_size - 1))
19460 fix = bytes & (noop_size - 1);
19462 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19464 memset (p, 0, fix);
19471 if (bytes & noop_size)
19473 /* Insert a narrow noop. */
19474 memcpy (p, narrow_noop, noop_size);
19476 bytes -= noop_size;
19480 /* Use wide noops for the remainder */
19484 while (bytes >= noop_size)
19486 memcpy (p, noop, noop_size);
19488 bytes -= noop_size;
19492 fragP->fr_fix += fix;
19495 /* Called from md_do_align. Used to create an alignment
19496 frag in a code section. */
19499 arm_frag_align_code (int n, int max)
19503 /* We assume that there will never be a requirement
19504 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19505 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19510 _("alignments greater than %d bytes not supported in .text sections."),
19511 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19512 as_fatal ("%s", err_msg);
19515 p = frag_var (rs_align_code,
19516 MAX_MEM_FOR_RS_ALIGN_CODE,
19518 (relax_substateT) max,
19525 /* Perform target specific initialisation of a frag.
19526 Note - despite the name this initialisation is not done when the frag
19527 is created, but only when its type is assigned. A frag can be created
19528 and used a long time before its type is set, so beware of assuming that
19529 this initialisationis performed first. */
19533 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19535 /* Record whether this frag is in an ARM or a THUMB area. */
19536 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19539 #else /* OBJ_ELF is defined. */
19541 arm_init_frag (fragS * fragP, int max_chars)
19543 /* If the current ARM vs THUMB mode has not already
19544 been recorded into this frag then do so now. */
19545 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19547 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19549 /* Record a mapping symbol for alignment frags. We will delete this
19550 later if the alignment ends up empty. */
19551 switch (fragP->fr_type)
19554 case rs_align_test:
19556 mapping_state_2 (MAP_DATA, max_chars);
19558 case rs_align_code:
19559 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19567 /* When we change sections we need to issue a new mapping symbol. */
19570 arm_elf_change_section (void)
19572 /* Link an unlinked unwind index table section to the .text section. */
19573 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19574 && elf_linked_to_section (now_seg) == NULL)
19575 elf_linked_to_section (now_seg) = text_section;
19579 arm_elf_section_type (const char * str, size_t len)
19581 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19582 return SHT_ARM_EXIDX;
19587 /* Code to deal with unwinding tables. */
19589 static void add_unwind_adjustsp (offsetT);
19591 /* Generate any deferred unwind frame offset. */
19594 flush_pending_unwind (void)
19598 offset = unwind.pending_offset;
19599 unwind.pending_offset = 0;
19601 add_unwind_adjustsp (offset);
19604 /* Add an opcode to this list for this function. Two-byte opcodes should
19605 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19609 add_unwind_opcode (valueT op, int length)
19611 /* Add any deferred stack adjustment. */
19612 if (unwind.pending_offset)
19613 flush_pending_unwind ();
19615 unwind.sp_restored = 0;
19617 if (unwind.opcode_count + length > unwind.opcode_alloc)
19619 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19620 if (unwind.opcodes)
19621 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19622 unwind.opcode_alloc);
19624 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19629 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19631 unwind.opcode_count++;
19635 /* Add unwind opcodes to adjust the stack pointer. */
19638 add_unwind_adjustsp (offsetT offset)
19642 if (offset > 0x200)
19644 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19649 /* Long form: 0xb2, uleb128. */
19650 /* This might not fit in a word so add the individual bytes,
19651 remembering the list is built in reverse order. */
19652 o = (valueT) ((offset - 0x204) >> 2);
19654 add_unwind_opcode (0, 1);
19656 /* Calculate the uleb128 encoding of the offset. */
19660 bytes[n] = o & 0x7f;
19666 /* Add the insn. */
19668 add_unwind_opcode (bytes[n - 1], 1);
19669 add_unwind_opcode (0xb2, 1);
19671 else if (offset > 0x100)
19673 /* Two short opcodes. */
19674 add_unwind_opcode (0x3f, 1);
19675 op = (offset - 0x104) >> 2;
19676 add_unwind_opcode (op, 1);
19678 else if (offset > 0)
19680 /* Short opcode. */
19681 op = (offset - 4) >> 2;
19682 add_unwind_opcode (op, 1);
19684 else if (offset < 0)
19687 while (offset > 0x100)
19689 add_unwind_opcode (0x7f, 1);
19692 op = ((offset - 4) >> 2) | 0x40;
19693 add_unwind_opcode (op, 1);
19697 /* Finish the list of unwind opcodes for this function. */
19699 finish_unwind_opcodes (void)
19703 if (unwind.fp_used)
19705 /* Adjust sp as necessary. */
19706 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19707 flush_pending_unwind ();
19709 /* After restoring sp from the frame pointer. */
19710 op = 0x90 | unwind.fp_reg;
19711 add_unwind_opcode (op, 1);
19714 flush_pending_unwind ();
19718 /* Start an exception table entry. If idx is nonzero this is an index table
19722 start_unwind_section (const segT text_seg, int idx)
19724 const char * text_name;
19725 const char * prefix;
19726 const char * prefix_once;
19727 const char * group_name;
19731 size_t sec_name_len;
19738 prefix = ELF_STRING_ARM_unwind;
19739 prefix_once = ELF_STRING_ARM_unwind_once;
19740 type = SHT_ARM_EXIDX;
19744 prefix = ELF_STRING_ARM_unwind_info;
19745 prefix_once = ELF_STRING_ARM_unwind_info_once;
19746 type = SHT_PROGBITS;
19749 text_name = segment_name (text_seg);
19750 if (streq (text_name, ".text"))
19753 if (strncmp (text_name, ".gnu.linkonce.t.",
19754 strlen (".gnu.linkonce.t.")) == 0)
19756 prefix = prefix_once;
19757 text_name += strlen (".gnu.linkonce.t.");
19760 prefix_len = strlen (prefix);
19761 text_len = strlen (text_name);
19762 sec_name_len = prefix_len + text_len;
19763 sec_name = (char *) xmalloc (sec_name_len + 1);
19764 memcpy (sec_name, prefix, prefix_len);
19765 memcpy (sec_name + prefix_len, text_name, text_len);
19766 sec_name[prefix_len + text_len] = '\0';
19772 /* Handle COMDAT group. */
19773 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19775 group_name = elf_group_name (text_seg);
19776 if (group_name == NULL)
19778 as_bad (_("Group section `%s' has no group signature"),
19779 segment_name (text_seg));
19780 ignore_rest_of_line ();
19783 flags |= SHF_GROUP;
19787 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19789 /* Set the section link for index tables. */
19791 elf_linked_to_section (now_seg) = text_seg;
19795 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19796 personality routine data. Returns zero, or the index table value for
19797 and inline entry. */
19800 create_unwind_entry (int have_data)
19805 /* The current word of data. */
19807 /* The number of bytes left in this word. */
19810 finish_unwind_opcodes ();
19812 /* Remember the current text section. */
19813 unwind.saved_seg = now_seg;
19814 unwind.saved_subseg = now_subseg;
19816 start_unwind_section (now_seg, 0);
19818 if (unwind.personality_routine == NULL)
19820 if (unwind.personality_index == -2)
19823 as_bad (_("handlerdata in cantunwind frame"));
19824 return 1; /* EXIDX_CANTUNWIND. */
19827 /* Use a default personality routine if none is specified. */
19828 if (unwind.personality_index == -1)
19830 if (unwind.opcode_count > 3)
19831 unwind.personality_index = 1;
19833 unwind.personality_index = 0;
19836 /* Space for the personality routine entry. */
19837 if (unwind.personality_index == 0)
19839 if (unwind.opcode_count > 3)
19840 as_bad (_("too many unwind opcodes for personality routine 0"));
19844 /* All the data is inline in the index table. */
19847 while (unwind.opcode_count > 0)
19849 unwind.opcode_count--;
19850 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19854 /* Pad with "finish" opcodes. */
19856 data = (data << 8) | 0xb0;
19863 /* We get two opcodes "free" in the first word. */
19864 size = unwind.opcode_count - 2;
19867 /* An extra byte is required for the opcode count. */
19868 size = unwind.opcode_count + 1;
19870 size = (size + 3) >> 2;
19872 as_bad (_("too many unwind opcodes"));
19874 frag_align (2, 0, 0);
19875 record_alignment (now_seg, 2);
19876 unwind.table_entry = expr_build_dot ();
19878 /* Allocate the table entry. */
19879 ptr = frag_more ((size << 2) + 4);
19880 where = frag_now_fix () - ((size << 2) + 4);
19882 switch (unwind.personality_index)
19885 /* ??? Should this be a PLT generating relocation? */
19886 /* Custom personality routine. */
19887 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19888 BFD_RELOC_ARM_PREL31);
19893 /* Set the first byte to the number of additional words. */
19898 /* ABI defined personality routines. */
19900 /* Three opcodes bytes are packed into the first word. */
19907 /* The size and first two opcode bytes go in the first word. */
19908 data = ((0x80 + unwind.personality_index) << 8) | size;
19913 /* Should never happen. */
19917 /* Pack the opcodes into words (MSB first), reversing the list at the same
19919 while (unwind.opcode_count > 0)
19923 md_number_to_chars (ptr, data, 4);
19928 unwind.opcode_count--;
19930 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19933 /* Finish off the last word. */
19936 /* Pad with "finish" opcodes. */
19938 data = (data << 8) | 0xb0;
19940 md_number_to_chars (ptr, data, 4);
19945 /* Add an empty descriptor if there is no user-specified data. */
19946 ptr = frag_more (4);
19947 md_number_to_chars (ptr, 0, 4);
19954 /* Initialize the DWARF-2 unwind information for this procedure. */
19957 tc_arm_frame_initial_instructions (void)
19959 cfi_add_CFA_def_cfa (REG_SP, 0);
19961 #endif /* OBJ_ELF */
19963 /* Convert REGNAME to a DWARF-2 register number. */
19966 tc_arm_regname_to_dw2regnum (char *regname)
19968 int reg = arm_reg_parse (®name, REG_TYPE_RN);
19978 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
19982 exp.X_op = O_secrel;
19983 exp.X_add_symbol = symbol;
19984 exp.X_add_number = 0;
19985 emit_expr (&exp, size);
19989 /* MD interface: Symbol and relocation handling. */
19991 /* Return the address within the segment that a PC-relative fixup is
19992 relative to. For ARM, PC-relative fixups applied to instructions
19993 are generally relative to the location of the fixup plus 8 bytes.
19994 Thumb branches are offset by 4, and Thumb loads relative to PC
19995 require special handling. */
19998 md_pcrel_from_section (fixS * fixP, segT seg)
20000 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20002 /* If this is pc-relative and we are going to emit a relocation
20003 then we just want to put out any pipeline compensation that the linker
20004 will need. Otherwise we want to use the calculated base.
20005 For WinCE we skip the bias for externals as well, since this
20006 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20008 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20009 || (arm_force_relocation (fixP)
20011 && !S_IS_EXTERNAL (fixP->fx_addsy)
20017 switch (fixP->fx_r_type)
20019 /* PC relative addressing on the Thumb is slightly odd as the
20020 bottom two bits of the PC are forced to zero for the
20021 calculation. This happens *after* application of the
20022 pipeline offset. However, Thumb adrl already adjusts for
20023 this, so we need not do it again. */
20024 case BFD_RELOC_ARM_THUMB_ADD:
20027 case BFD_RELOC_ARM_THUMB_OFFSET:
20028 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20029 case BFD_RELOC_ARM_T32_ADD_PC12:
20030 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20031 return (base + 4) & ~3;
20033 /* Thumb branches are simply offset by +4. */
20034 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20035 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20036 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20037 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20038 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20041 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20043 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20044 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20045 && ARM_IS_FUNC (fixP->fx_addsy)
20046 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20047 base = fixP->fx_where + fixP->fx_frag->fr_address;
20050 /* BLX is like branches above, but forces the low two bits of PC to
20052 case BFD_RELOC_THUMB_PCREL_BLX:
20054 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20055 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20056 && THUMB_IS_FUNC (fixP->fx_addsy)
20057 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20058 base = fixP->fx_where + fixP->fx_frag->fr_address;
20059 return (base + 4) & ~3;
20061 /* ARM mode branches are offset by +8. However, the Windows CE
20062 loader expects the relocation not to take this into account. */
20063 case BFD_RELOC_ARM_PCREL_BLX:
20065 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20066 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20067 && ARM_IS_FUNC (fixP->fx_addsy)
20068 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20069 base = fixP->fx_where + fixP->fx_frag->fr_address;
20072 case BFD_RELOC_ARM_PCREL_CALL:
20074 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20075 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20076 && THUMB_IS_FUNC (fixP->fx_addsy)
20077 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20078 base = fixP->fx_where + fixP->fx_frag->fr_address;
20081 case BFD_RELOC_ARM_PCREL_BRANCH:
20082 case BFD_RELOC_ARM_PCREL_JUMP:
20083 case BFD_RELOC_ARM_PLT32:
20085 /* When handling fixups immediately, because we have already
20086 discovered the value of a symbol, or the address of the frag involved
20087 we must account for the offset by +8, as the OS loader will never see the reloc.
20088 see fixup_segment() in write.c
20089 The S_IS_EXTERNAL test handles the case of global symbols.
20090 Those need the calculated base, not just the pipe compensation the linker will need. */
20092 && fixP->fx_addsy != NULL
20093 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20094 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20102 /* ARM mode loads relative to PC are also offset by +8. Unlike
20103 branches, the Windows CE loader *does* expect the relocation
20104 to take this into account. */
20105 case BFD_RELOC_ARM_OFFSET_IMM:
20106 case BFD_RELOC_ARM_OFFSET_IMM8:
20107 case BFD_RELOC_ARM_HWLITERAL:
20108 case BFD_RELOC_ARM_LITERAL:
20109 case BFD_RELOC_ARM_CP_OFF_IMM:
20113 /* Other PC-relative relocations are un-offset. */
20119 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20120 Otherwise we have no need to default values of symbols. */
20123 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20126 if (name[0] == '_' && name[1] == 'G'
20127 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20131 if (symbol_find (name))
20132 as_bad (_("GOT already in the symbol table"));
20134 GOT_symbol = symbol_new (name, undefined_section,
20135 (valueT) 0, & zero_address_frag);
20145 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20146 computed as two separate immediate values, added together. We
20147 already know that this value cannot be computed by just one ARM
20150 static unsigned int
20151 validate_immediate_twopart (unsigned int val,
20152 unsigned int * highpart)
20157 for (i = 0; i < 32; i += 2)
20158 if (((a = rotate_left (val, i)) & 0xff) != 0)
20164 * highpart = (a >> 8) | ((i + 24) << 7);
20166 else if (a & 0xff0000)
20168 if (a & 0xff000000)
20170 * highpart = (a >> 16) | ((i + 16) << 7);
20174 gas_assert (a & 0xff000000);
20175 * highpart = (a >> 24) | ((i + 8) << 7);
20178 return (a & 0xff) | (i << 7);
20185 validate_offset_imm (unsigned int val, int hwse)
20187 if ((hwse && val > 255) || val > 4095)
20192 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20193 negative immediate constant by altering the instruction. A bit of
20198 by inverting the second operand, and
20201 by negating the second operand. */
20204 negate_data_op (unsigned long * instruction,
20205 unsigned long value)
20208 unsigned long negated, inverted;
20210 negated = encode_arm_immediate (-value);
20211 inverted = encode_arm_immediate (~value);
20213 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20216 /* First negates. */
20217 case OPCODE_SUB: /* ADD <-> SUB */
20218 new_inst = OPCODE_ADD;
20223 new_inst = OPCODE_SUB;
20227 case OPCODE_CMP: /* CMP <-> CMN */
20228 new_inst = OPCODE_CMN;
20233 new_inst = OPCODE_CMP;
20237 /* Now Inverted ops. */
20238 case OPCODE_MOV: /* MOV <-> MVN */
20239 new_inst = OPCODE_MVN;
20244 new_inst = OPCODE_MOV;
20248 case OPCODE_AND: /* AND <-> BIC */
20249 new_inst = OPCODE_BIC;
20254 new_inst = OPCODE_AND;
20258 case OPCODE_ADC: /* ADC <-> SBC */
20259 new_inst = OPCODE_SBC;
20264 new_inst = OPCODE_ADC;
20268 /* We cannot do anything. */
20273 if (value == (unsigned) FAIL)
20276 *instruction &= OPCODE_MASK;
20277 *instruction |= new_inst << DATA_OP_SHIFT;
20281 /* Like negate_data_op, but for Thumb-2. */
20283 static unsigned int
20284 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20288 unsigned int negated, inverted;
20290 negated = encode_thumb32_immediate (-value);
20291 inverted = encode_thumb32_immediate (~value);
20293 rd = (*instruction >> 8) & 0xf;
20294 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20297 /* ADD <-> SUB. Includes CMP <-> CMN. */
20298 case T2_OPCODE_SUB:
20299 new_inst = T2_OPCODE_ADD;
20303 case T2_OPCODE_ADD:
20304 new_inst = T2_OPCODE_SUB;
20308 /* ORR <-> ORN. Includes MOV <-> MVN. */
20309 case T2_OPCODE_ORR:
20310 new_inst = T2_OPCODE_ORN;
20314 case T2_OPCODE_ORN:
20315 new_inst = T2_OPCODE_ORR;
20319 /* AND <-> BIC. TST has no inverted equivalent. */
20320 case T2_OPCODE_AND:
20321 new_inst = T2_OPCODE_BIC;
20328 case T2_OPCODE_BIC:
20329 new_inst = T2_OPCODE_AND;
20334 case T2_OPCODE_ADC:
20335 new_inst = T2_OPCODE_SBC;
20339 case T2_OPCODE_SBC:
20340 new_inst = T2_OPCODE_ADC;
20344 /* We cannot do anything. */
20349 if (value == (unsigned int)FAIL)
20352 *instruction &= T2_OPCODE_MASK;
20353 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20357 /* Read a 32-bit thumb instruction from buf. */
20358 static unsigned long
20359 get_thumb32_insn (char * buf)
20361 unsigned long insn;
20362 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20363 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20369 /* We usually want to set the low bit on the address of thumb function
20370 symbols. In particular .word foo - . should have the low bit set.
20371 Generic code tries to fold the difference of two symbols to
20372 a constant. Prevent this and force a relocation when the first symbols
20373 is a thumb function. */
20376 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20378 if (op == O_subtract
20379 && l->X_op == O_symbol
20380 && r->X_op == O_symbol
20381 && THUMB_IS_FUNC (l->X_add_symbol))
20383 l->X_op = O_subtract;
20384 l->X_op_symbol = r->X_add_symbol;
20385 l->X_add_number -= r->X_add_number;
20389 /* Process as normal. */
20393 /* Encode Thumb2 unconditional branches and calls. The encoding
20394 for the 2 are identical for the immediate values. */
20397 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20399 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20402 addressT S, I1, I2, lo, hi;
20404 S = (value >> 24) & 0x01;
20405 I1 = (value >> 23) & 0x01;
20406 I2 = (value >> 22) & 0x01;
20407 hi = (value >> 12) & 0x3ff;
20408 lo = (value >> 1) & 0x7ff;
20409 newval = md_chars_to_number (buf, THUMB_SIZE);
20410 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20411 newval |= (S << 10) | hi;
20412 newval2 &= ~T2I1I2MASK;
20413 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20414 md_number_to_chars (buf, newval, THUMB_SIZE);
20415 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20419 md_apply_fix (fixS * fixP,
20423 offsetT value = * valP;
20425 unsigned int newimm;
20426 unsigned long temp;
20428 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20430 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20432 /* Note whether this will delete the relocation. */
20434 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20437 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20438 consistency with the behaviour on 32-bit hosts. Remember value
20440 value &= 0xffffffff;
20441 value ^= 0x80000000;
20442 value -= 0x80000000;
20445 fixP->fx_addnumber = value;
20447 /* Same treatment for fixP->fx_offset. */
20448 fixP->fx_offset &= 0xffffffff;
20449 fixP->fx_offset ^= 0x80000000;
20450 fixP->fx_offset -= 0x80000000;
20452 switch (fixP->fx_r_type)
20454 case BFD_RELOC_NONE:
20455 /* This will need to go in the object file. */
20459 case BFD_RELOC_ARM_IMMEDIATE:
20460 /* We claim that this fixup has been processed here,
20461 even if in fact we generate an error because we do
20462 not have a reloc for it, so tc_gen_reloc will reject it. */
20465 if (fixP->fx_addsy)
20467 const char *msg = 0;
20469 if (! S_IS_DEFINED (fixP->fx_addsy))
20470 msg = _("undefined symbol %s used as an immediate value");
20471 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20472 msg = _("symbol %s is in a different section");
20473 else if (S_IS_WEAK (fixP->fx_addsy))
20474 msg = _("symbol %s is weak and may be overridden later");
20478 as_bad_where (fixP->fx_file, fixP->fx_line,
20479 msg, S_GET_NAME (fixP->fx_addsy));
20484 newimm = encode_arm_immediate (value);
20485 temp = md_chars_to_number (buf, INSN_SIZE);
20487 /* If the instruction will fail, see if we can fix things up by
20488 changing the opcode. */
20489 if (newimm == (unsigned int) FAIL
20490 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20492 as_bad_where (fixP->fx_file, fixP->fx_line,
20493 _("invalid constant (%lx) after fixup"),
20494 (unsigned long) value);
20498 newimm |= (temp & 0xfffff000);
20499 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20502 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20504 unsigned int highpart = 0;
20505 unsigned int newinsn = 0xe1a00000; /* nop. */
20507 if (fixP->fx_addsy)
20509 const char *msg = 0;
20511 if (! S_IS_DEFINED (fixP->fx_addsy))
20512 msg = _("undefined symbol %s used as an immediate value");
20513 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20514 msg = _("symbol %s is in a different section");
20515 else if (S_IS_WEAK (fixP->fx_addsy))
20516 msg = _("symbol %s is weak and may be overridden later");
20520 as_bad_where (fixP->fx_file, fixP->fx_line,
20521 msg, S_GET_NAME (fixP->fx_addsy));
20526 newimm = encode_arm_immediate (value);
20527 temp = md_chars_to_number (buf, INSN_SIZE);
20529 /* If the instruction will fail, see if we can fix things up by
20530 changing the opcode. */
20531 if (newimm == (unsigned int) FAIL
20532 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20534 /* No ? OK - try using two ADD instructions to generate
20536 newimm = validate_immediate_twopart (value, & highpart);
20538 /* Yes - then make sure that the second instruction is
20540 if (newimm != (unsigned int) FAIL)
20542 /* Still No ? Try using a negated value. */
20543 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20544 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20545 /* Otherwise - give up. */
20548 as_bad_where (fixP->fx_file, fixP->fx_line,
20549 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20554 /* Replace the first operand in the 2nd instruction (which
20555 is the PC) with the destination register. We have
20556 already added in the PC in the first instruction and we
20557 do not want to do it again. */
20558 newinsn &= ~ 0xf0000;
20559 newinsn |= ((newinsn & 0x0f000) << 4);
20562 newimm |= (temp & 0xfffff000);
20563 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20565 highpart |= (newinsn & 0xfffff000);
20566 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20570 case BFD_RELOC_ARM_OFFSET_IMM:
20571 if (!fixP->fx_done && seg->use_rela_p)
20574 case BFD_RELOC_ARM_LITERAL:
20580 if (validate_offset_imm (value, 0) == FAIL)
20582 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20583 as_bad_where (fixP->fx_file, fixP->fx_line,
20584 _("invalid literal constant: pool needs to be closer"));
20586 as_bad_where (fixP->fx_file, fixP->fx_line,
20587 _("bad immediate value for offset (%ld)"),
20592 newval = md_chars_to_number (buf, INSN_SIZE);
20594 newval &= 0xfffff000;
20597 newval &= 0xff7ff000;
20598 newval |= value | (sign ? INDEX_UP : 0);
20600 md_number_to_chars (buf, newval, INSN_SIZE);
20603 case BFD_RELOC_ARM_OFFSET_IMM8:
20604 case BFD_RELOC_ARM_HWLITERAL:
20610 if (validate_offset_imm (value, 1) == FAIL)
20612 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20613 as_bad_where (fixP->fx_file, fixP->fx_line,
20614 _("invalid literal constant: pool needs to be closer"));
20616 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20621 newval = md_chars_to_number (buf, INSN_SIZE);
20623 newval &= 0xfffff0f0;
20626 newval &= 0xff7ff0f0;
20627 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20629 md_number_to_chars (buf, newval, INSN_SIZE);
20632 case BFD_RELOC_ARM_T32_OFFSET_U8:
20633 if (value < 0 || value > 1020 || value % 4 != 0)
20634 as_bad_where (fixP->fx_file, fixP->fx_line,
20635 _("bad immediate value for offset (%ld)"), (long) value);
20638 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20640 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20643 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20644 /* This is a complicated relocation used for all varieties of Thumb32
20645 load/store instruction with immediate offset:
20647 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20648 *4, optional writeback(W)
20649 (doubleword load/store)
20651 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20652 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20653 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20654 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20655 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20657 Uppercase letters indicate bits that are already encoded at
20658 this point. Lowercase letters are our problem. For the
20659 second block of instructions, the secondary opcode nybble
20660 (bits 8..11) is present, and bit 23 is zero, even if this is
20661 a PC-relative operation. */
20662 newval = md_chars_to_number (buf, THUMB_SIZE);
20664 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20666 if ((newval & 0xf0000000) == 0xe0000000)
20668 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20670 newval |= (1 << 23);
20673 if (value % 4 != 0)
20675 as_bad_where (fixP->fx_file, fixP->fx_line,
20676 _("offset not a multiple of 4"));
20682 as_bad_where (fixP->fx_file, fixP->fx_line,
20683 _("offset out of range"));
20688 else if ((newval & 0x000f0000) == 0x000f0000)
20690 /* PC-relative, 12-bit offset. */
20692 newval |= (1 << 23);
20697 as_bad_where (fixP->fx_file, fixP->fx_line,
20698 _("offset out of range"));
20703 else if ((newval & 0x00000100) == 0x00000100)
20705 /* Writeback: 8-bit, +/- offset. */
20707 newval |= (1 << 9);
20712 as_bad_where (fixP->fx_file, fixP->fx_line,
20713 _("offset out of range"));
20718 else if ((newval & 0x00000f00) == 0x00000e00)
20720 /* T-instruction: positive 8-bit offset. */
20721 if (value < 0 || value > 0xff)
20723 as_bad_where (fixP->fx_file, fixP->fx_line,
20724 _("offset out of range"));
20732 /* Positive 12-bit or negative 8-bit offset. */
20736 newval |= (1 << 23);
20746 as_bad_where (fixP->fx_file, fixP->fx_line,
20747 _("offset out of range"));
20754 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20755 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20758 case BFD_RELOC_ARM_SHIFT_IMM:
20759 newval = md_chars_to_number (buf, INSN_SIZE);
20760 if (((unsigned long) value) > 32
20762 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20764 as_bad_where (fixP->fx_file, fixP->fx_line,
20765 _("shift expression is too large"));
20770 /* Shifts of zero must be done as lsl. */
20772 else if (value == 32)
20774 newval &= 0xfffff07f;
20775 newval |= (value & 0x1f) << 7;
20776 md_number_to_chars (buf, newval, INSN_SIZE);
20779 case BFD_RELOC_ARM_T32_IMMEDIATE:
20780 case BFD_RELOC_ARM_T32_ADD_IMM:
20781 case BFD_RELOC_ARM_T32_IMM12:
20782 case BFD_RELOC_ARM_T32_ADD_PC12:
20783 /* We claim that this fixup has been processed here,
20784 even if in fact we generate an error because we do
20785 not have a reloc for it, so tc_gen_reloc will reject it. */
20789 && ! S_IS_DEFINED (fixP->fx_addsy))
20791 as_bad_where (fixP->fx_file, fixP->fx_line,
20792 _("undefined symbol %s used as an immediate value"),
20793 S_GET_NAME (fixP->fx_addsy));
20797 newval = md_chars_to_number (buf, THUMB_SIZE);
20799 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20802 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20803 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20805 newimm = encode_thumb32_immediate (value);
20806 if (newimm == (unsigned int) FAIL)
20807 newimm = thumb32_negate_data_op (&newval, value);
20809 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20810 && newimm == (unsigned int) FAIL)
20812 /* Turn add/sum into addw/subw. */
20813 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20814 newval = (newval & 0xfeffffff) | 0x02000000;
20815 /* No flat 12-bit imm encoding for addsw/subsw. */
20816 if ((newval & 0x00100000) == 0)
20818 /* 12 bit immediate for addw/subw. */
20822 newval ^= 0x00a00000;
20825 newimm = (unsigned int) FAIL;
20831 if (newimm == (unsigned int)FAIL)
20833 as_bad_where (fixP->fx_file, fixP->fx_line,
20834 _("invalid constant (%lx) after fixup"),
20835 (unsigned long) value);
20839 newval |= (newimm & 0x800) << 15;
20840 newval |= (newimm & 0x700) << 4;
20841 newval |= (newimm & 0x0ff);
20843 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20844 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20847 case BFD_RELOC_ARM_SMC:
20848 if (((unsigned long) value) > 0xffff)
20849 as_bad_where (fixP->fx_file, fixP->fx_line,
20850 _("invalid smc expression"));
20851 newval = md_chars_to_number (buf, INSN_SIZE);
20852 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20853 md_number_to_chars (buf, newval, INSN_SIZE);
20856 case BFD_RELOC_ARM_HVC:
20857 if (((unsigned long) value) > 0xffff)
20858 as_bad_where (fixP->fx_file, fixP->fx_line,
20859 _("invalid hvc expression"));
20860 newval = md_chars_to_number (buf, INSN_SIZE);
20861 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20862 md_number_to_chars (buf, newval, INSN_SIZE);
20865 case BFD_RELOC_ARM_SWI:
20866 if (fixP->tc_fix_data != 0)
20868 if (((unsigned long) value) > 0xff)
20869 as_bad_where (fixP->fx_file, fixP->fx_line,
20870 _("invalid swi expression"));
20871 newval = md_chars_to_number (buf, THUMB_SIZE);
20873 md_number_to_chars (buf, newval, THUMB_SIZE);
20877 if (((unsigned long) value) > 0x00ffffff)
20878 as_bad_where (fixP->fx_file, fixP->fx_line,
20879 _("invalid swi expression"));
20880 newval = md_chars_to_number (buf, INSN_SIZE);
20882 md_number_to_chars (buf, newval, INSN_SIZE);
20886 case BFD_RELOC_ARM_MULTI:
20887 if (((unsigned long) value) > 0xffff)
20888 as_bad_where (fixP->fx_file, fixP->fx_line,
20889 _("invalid expression in load/store multiple"));
20890 newval = value | md_chars_to_number (buf, INSN_SIZE);
20891 md_number_to_chars (buf, newval, INSN_SIZE);
20895 case BFD_RELOC_ARM_PCREL_CALL:
20897 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20899 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20900 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20901 && THUMB_IS_FUNC (fixP->fx_addsy))
20902 /* Flip the bl to blx. This is a simple flip
20903 bit here because we generate PCREL_CALL for
20904 unconditional bls. */
20906 newval = md_chars_to_number (buf, INSN_SIZE);
20907 newval = newval | 0x10000000;
20908 md_number_to_chars (buf, newval, INSN_SIZE);
20914 goto arm_branch_common;
20916 case BFD_RELOC_ARM_PCREL_JUMP:
20917 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20919 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20920 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20921 && THUMB_IS_FUNC (fixP->fx_addsy))
20923 /* This would map to a bl<cond>, b<cond>,
20924 b<always> to a Thumb function. We
20925 need to force a relocation for this particular
20927 newval = md_chars_to_number (buf, INSN_SIZE);
20931 case BFD_RELOC_ARM_PLT32:
20933 case BFD_RELOC_ARM_PCREL_BRANCH:
20935 goto arm_branch_common;
20937 case BFD_RELOC_ARM_PCREL_BLX:
20940 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20942 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20943 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20944 && ARM_IS_FUNC (fixP->fx_addsy))
20946 /* Flip the blx to a bl and warn. */
20947 const char *name = S_GET_NAME (fixP->fx_addsy);
20948 newval = 0xeb000000;
20949 as_warn_where (fixP->fx_file, fixP->fx_line,
20950 _("blx to '%s' an ARM ISA state function changed to bl"),
20952 md_number_to_chars (buf, newval, INSN_SIZE);
20958 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20959 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20963 /* We are going to store value (shifted right by two) in the
20964 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20965 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20966 also be be clear. */
20968 as_bad_where (fixP->fx_file, fixP->fx_line,
20969 _("misaligned branch destination"));
20970 if ((value & (offsetT)0xfe000000) != (offsetT)0
20971 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
20972 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
20974 if (fixP->fx_done || !seg->use_rela_p)
20976 newval = md_chars_to_number (buf, INSN_SIZE);
20977 newval |= (value >> 2) & 0x00ffffff;
20978 /* Set the H bit on BLX instructions. */
20982 newval |= 0x01000000;
20984 newval &= ~0x01000000;
20986 md_number_to_chars (buf, newval, INSN_SIZE);
20990 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
20991 /* CBZ can only branch forward. */
20993 /* Attempts to use CBZ to branch to the next instruction
20994 (which, strictly speaking, are prohibited) will be turned into
20997 FIXME: It may be better to remove the instruction completely and
20998 perform relaxation. */
21001 newval = md_chars_to_number (buf, THUMB_SIZE);
21002 newval = 0xbf00; /* NOP encoding T1 */
21003 md_number_to_chars (buf, newval, THUMB_SIZE);
21008 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21010 if (fixP->fx_done || !seg->use_rela_p)
21012 newval = md_chars_to_number (buf, THUMB_SIZE);
21013 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21014 md_number_to_chars (buf, newval, THUMB_SIZE);
21019 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21020 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21021 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21023 if (fixP->fx_done || !seg->use_rela_p)
21025 newval = md_chars_to_number (buf, THUMB_SIZE);
21026 newval |= (value & 0x1ff) >> 1;
21027 md_number_to_chars (buf, newval, THUMB_SIZE);
21031 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21032 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21033 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21035 if (fixP->fx_done || !seg->use_rela_p)
21037 newval = md_chars_to_number (buf, THUMB_SIZE);
21038 newval |= (value & 0xfff) >> 1;
21039 md_number_to_chars (buf, newval, THUMB_SIZE);
21043 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21045 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21046 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21047 && ARM_IS_FUNC (fixP->fx_addsy)
21048 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21050 /* Force a relocation for a branch 20 bits wide. */
21053 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21054 as_bad_where (fixP->fx_file, fixP->fx_line,
21055 _("conditional branch out of range"));
21057 if (fixP->fx_done || !seg->use_rela_p)
21060 addressT S, J1, J2, lo, hi;
21062 S = (value & 0x00100000) >> 20;
21063 J2 = (value & 0x00080000) >> 19;
21064 J1 = (value & 0x00040000) >> 18;
21065 hi = (value & 0x0003f000) >> 12;
21066 lo = (value & 0x00000ffe) >> 1;
21068 newval = md_chars_to_number (buf, THUMB_SIZE);
21069 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21070 newval |= (S << 10) | hi;
21071 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21072 md_number_to_chars (buf, newval, THUMB_SIZE);
21073 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21077 case BFD_RELOC_THUMB_PCREL_BLX:
21078 /* If there is a blx from a thumb state function to
21079 another thumb function flip this to a bl and warn
21083 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21084 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21085 && THUMB_IS_FUNC (fixP->fx_addsy))
21087 const char *name = S_GET_NAME (fixP->fx_addsy);
21088 as_warn_where (fixP->fx_file, fixP->fx_line,
21089 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21091 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21092 newval = newval | 0x1000;
21093 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21094 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21099 goto thumb_bl_common;
21101 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21102 /* A bl from Thumb state ISA to an internal ARM state function
21103 is converted to a blx. */
21105 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21106 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21107 && ARM_IS_FUNC (fixP->fx_addsy)
21108 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21110 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21111 newval = newval & ~0x1000;
21112 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21113 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21120 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21121 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21122 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21125 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21126 /* For a BLX instruction, make sure that the relocation is rounded up
21127 to a word boundary. This follows the semantics of the instruction
21128 which specifies that bit 1 of the target address will come from bit
21129 1 of the base address. */
21130 value = (value + 1) & ~ 1;
21132 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21134 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21135 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21136 else if ((value & ~0x1ffffff)
21137 && ((value & ~0x1ffffff) != ~0x1ffffff))
21138 as_bad_where (fixP->fx_file, fixP->fx_line,
21139 _("Thumb2 branch out of range"));
21142 if (fixP->fx_done || !seg->use_rela_p)
21143 encode_thumb2_b_bl_offset (buf, value);
21147 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21148 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21149 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21151 if (fixP->fx_done || !seg->use_rela_p)
21152 encode_thumb2_b_bl_offset (buf, value);
21157 if (fixP->fx_done || !seg->use_rela_p)
21158 md_number_to_chars (buf, value, 1);
21162 if (fixP->fx_done || !seg->use_rela_p)
21163 md_number_to_chars (buf, value, 2);
21167 case BFD_RELOC_ARM_TLS_CALL:
21168 case BFD_RELOC_ARM_THM_TLS_CALL:
21169 case BFD_RELOC_ARM_TLS_DESCSEQ:
21170 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21171 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21174 case BFD_RELOC_ARM_TLS_GOTDESC:
21175 case BFD_RELOC_ARM_TLS_GD32:
21176 case BFD_RELOC_ARM_TLS_LE32:
21177 case BFD_RELOC_ARM_TLS_IE32:
21178 case BFD_RELOC_ARM_TLS_LDM32:
21179 case BFD_RELOC_ARM_TLS_LDO32:
21180 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21183 case BFD_RELOC_ARM_GOT32:
21184 case BFD_RELOC_ARM_GOTOFF:
21185 if (fixP->fx_done || !seg->use_rela_p)
21186 md_number_to_chars (buf, 0, 4);
21189 case BFD_RELOC_ARM_GOT_PREL:
21190 if (fixP->fx_done || !seg->use_rela_p)
21191 md_number_to_chars (buf, value, 4);
21194 case BFD_RELOC_ARM_TARGET2:
21195 /* TARGET2 is not partial-inplace, so we need to write the
21196 addend here for REL targets, because it won't be written out
21197 during reloc processing later. */
21198 if (fixP->fx_done || !seg->use_rela_p)
21199 md_number_to_chars (buf, fixP->fx_offset, 4);
21203 case BFD_RELOC_RVA:
21205 case BFD_RELOC_ARM_TARGET1:
21206 case BFD_RELOC_ARM_ROSEGREL32:
21207 case BFD_RELOC_ARM_SBREL32:
21208 case BFD_RELOC_32_PCREL:
21210 case BFD_RELOC_32_SECREL:
21212 if (fixP->fx_done || !seg->use_rela_p)
21214 /* For WinCE we only do this for pcrel fixups. */
21215 if (fixP->fx_done || fixP->fx_pcrel)
21217 md_number_to_chars (buf, value, 4);
21221 case BFD_RELOC_ARM_PREL31:
21222 if (fixP->fx_done || !seg->use_rela_p)
21224 newval = md_chars_to_number (buf, 4) & 0x80000000;
21225 if ((value ^ (value >> 1)) & 0x40000000)
21227 as_bad_where (fixP->fx_file, fixP->fx_line,
21228 _("rel31 relocation overflow"));
21230 newval |= value & 0x7fffffff;
21231 md_number_to_chars (buf, newval, 4);
21236 case BFD_RELOC_ARM_CP_OFF_IMM:
21237 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21238 if (value < -1023 || value > 1023 || (value & 3))
21239 as_bad_where (fixP->fx_file, fixP->fx_line,
21240 _("co-processor offset out of range"));
21245 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21246 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21247 newval = md_chars_to_number (buf, INSN_SIZE);
21249 newval = get_thumb32_insn (buf);
21251 newval &= 0xffffff00;
21254 newval &= 0xff7fff00;
21255 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21257 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21258 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21259 md_number_to_chars (buf, newval, INSN_SIZE);
21261 put_thumb32_insn (buf, newval);
21264 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21265 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21266 if (value < -255 || value > 255)
21267 as_bad_where (fixP->fx_file, fixP->fx_line,
21268 _("co-processor offset out of range"));
21270 goto cp_off_common;
21272 case BFD_RELOC_ARM_THUMB_OFFSET:
21273 newval = md_chars_to_number (buf, THUMB_SIZE);
21274 /* Exactly what ranges, and where the offset is inserted depends
21275 on the type of instruction, we can establish this from the
21277 switch (newval >> 12)
21279 case 4: /* PC load. */
21280 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21281 forced to zero for these loads; md_pcrel_from has already
21282 compensated for this. */
21284 as_bad_where (fixP->fx_file, fixP->fx_line,
21285 _("invalid offset, target not word aligned (0x%08lX)"),
21286 (((unsigned long) fixP->fx_frag->fr_address
21287 + (unsigned long) fixP->fx_where) & ~3)
21288 + (unsigned long) value);
21290 if (value & ~0x3fc)
21291 as_bad_where (fixP->fx_file, fixP->fx_line,
21292 _("invalid offset, value too big (0x%08lX)"),
21295 newval |= value >> 2;
21298 case 9: /* SP load/store. */
21299 if (value & ~0x3fc)
21300 as_bad_where (fixP->fx_file, fixP->fx_line,
21301 _("invalid offset, value too big (0x%08lX)"),
21303 newval |= value >> 2;
21306 case 6: /* Word load/store. */
21308 as_bad_where (fixP->fx_file, fixP->fx_line,
21309 _("invalid offset, value too big (0x%08lX)"),
21311 newval |= value << 4; /* 6 - 2. */
21314 case 7: /* Byte load/store. */
21316 as_bad_where (fixP->fx_file, fixP->fx_line,
21317 _("invalid offset, value too big (0x%08lX)"),
21319 newval |= value << 6;
21322 case 8: /* Halfword load/store. */
21324 as_bad_where (fixP->fx_file, fixP->fx_line,
21325 _("invalid offset, value too big (0x%08lX)"),
21327 newval |= value << 5; /* 6 - 1. */
21331 as_bad_where (fixP->fx_file, fixP->fx_line,
21332 "Unable to process relocation for thumb opcode: %lx",
21333 (unsigned long) newval);
21336 md_number_to_chars (buf, newval, THUMB_SIZE);
21339 case BFD_RELOC_ARM_THUMB_ADD:
21340 /* This is a complicated relocation, since we use it for all of
21341 the following immediate relocations:
21345 9bit ADD/SUB SP word-aligned
21346 10bit ADD PC/SP word-aligned
21348 The type of instruction being processed is encoded in the
21355 newval = md_chars_to_number (buf, THUMB_SIZE);
21357 int rd = (newval >> 4) & 0xf;
21358 int rs = newval & 0xf;
21359 int subtract = !!(newval & 0x8000);
21361 /* Check for HI regs, only very restricted cases allowed:
21362 Adjusting SP, and using PC or SP to get an address. */
21363 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21364 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21365 as_bad_where (fixP->fx_file, fixP->fx_line,
21366 _("invalid Hi register with immediate"));
21368 /* If value is negative, choose the opposite instruction. */
21372 subtract = !subtract;
21374 as_bad_where (fixP->fx_file, fixP->fx_line,
21375 _("immediate value out of range"));
21380 if (value & ~0x1fc)
21381 as_bad_where (fixP->fx_file, fixP->fx_line,
21382 _("invalid immediate for stack address calculation"));
21383 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21384 newval |= value >> 2;
21386 else if (rs == REG_PC || rs == REG_SP)
21388 if (subtract || value & ~0x3fc)
21389 as_bad_where (fixP->fx_file, fixP->fx_line,
21390 _("invalid immediate for address calculation (value = 0x%08lX)"),
21391 (unsigned long) value);
21392 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21394 newval |= value >> 2;
21399 as_bad_where (fixP->fx_file, fixP->fx_line,
21400 _("immediate value out of range"));
21401 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21402 newval |= (rd << 8) | value;
21407 as_bad_where (fixP->fx_file, fixP->fx_line,
21408 _("immediate value out of range"));
21409 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21410 newval |= rd | (rs << 3) | (value << 6);
21413 md_number_to_chars (buf, newval, THUMB_SIZE);
21416 case BFD_RELOC_ARM_THUMB_IMM:
21417 newval = md_chars_to_number (buf, THUMB_SIZE);
21418 if (value < 0 || value > 255)
21419 as_bad_where (fixP->fx_file, fixP->fx_line,
21420 _("invalid immediate: %ld is out of range"),
21423 md_number_to_chars (buf, newval, THUMB_SIZE);
21426 case BFD_RELOC_ARM_THUMB_SHIFT:
21427 /* 5bit shift value (0..32). LSL cannot take 32. */
21428 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21429 temp = newval & 0xf800;
21430 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21431 as_bad_where (fixP->fx_file, fixP->fx_line,
21432 _("invalid shift value: %ld"), (long) value);
21433 /* Shifts of zero must be encoded as LSL. */
21435 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21436 /* Shifts of 32 are encoded as zero. */
21437 else if (value == 32)
21439 newval |= value << 6;
21440 md_number_to_chars (buf, newval, THUMB_SIZE);
21443 case BFD_RELOC_VTABLE_INHERIT:
21444 case BFD_RELOC_VTABLE_ENTRY:
21448 case BFD_RELOC_ARM_MOVW:
21449 case BFD_RELOC_ARM_MOVT:
21450 case BFD_RELOC_ARM_THUMB_MOVW:
21451 case BFD_RELOC_ARM_THUMB_MOVT:
21452 if (fixP->fx_done || !seg->use_rela_p)
21454 /* REL format relocations are limited to a 16-bit addend. */
21455 if (!fixP->fx_done)
21457 if (value < -0x8000 || value > 0x7fff)
21458 as_bad_where (fixP->fx_file, fixP->fx_line,
21459 _("offset out of range"));
21461 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21462 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21467 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21468 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21470 newval = get_thumb32_insn (buf);
21471 newval &= 0xfbf08f00;
21472 newval |= (value & 0xf000) << 4;
21473 newval |= (value & 0x0800) << 15;
21474 newval |= (value & 0x0700) << 4;
21475 newval |= (value & 0x00ff);
21476 put_thumb32_insn (buf, newval);
21480 newval = md_chars_to_number (buf, 4);
21481 newval &= 0xfff0f000;
21482 newval |= value & 0x0fff;
21483 newval |= (value & 0xf000) << 4;
21484 md_number_to_chars (buf, newval, 4);
21489 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21490 case BFD_RELOC_ARM_ALU_PC_G0:
21491 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21492 case BFD_RELOC_ARM_ALU_PC_G1:
21493 case BFD_RELOC_ARM_ALU_PC_G2:
21494 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21495 case BFD_RELOC_ARM_ALU_SB_G0:
21496 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21497 case BFD_RELOC_ARM_ALU_SB_G1:
21498 case BFD_RELOC_ARM_ALU_SB_G2:
21499 gas_assert (!fixP->fx_done);
21500 if (!seg->use_rela_p)
21503 bfd_vma encoded_addend;
21504 bfd_vma addend_abs = abs (value);
21506 /* Check that the absolute value of the addend can be
21507 expressed as an 8-bit constant plus a rotation. */
21508 encoded_addend = encode_arm_immediate (addend_abs);
21509 if (encoded_addend == (unsigned int) FAIL)
21510 as_bad_where (fixP->fx_file, fixP->fx_line,
21511 _("the offset 0x%08lX is not representable"),
21512 (unsigned long) addend_abs);
21514 /* Extract the instruction. */
21515 insn = md_chars_to_number (buf, INSN_SIZE);
21517 /* If the addend is positive, use an ADD instruction.
21518 Otherwise use a SUB. Take care not to destroy the S bit. */
21519 insn &= 0xff1fffff;
21525 /* Place the encoded addend into the first 12 bits of the
21527 insn &= 0xfffff000;
21528 insn |= encoded_addend;
21530 /* Update the instruction. */
21531 md_number_to_chars (buf, insn, INSN_SIZE);
21535 case BFD_RELOC_ARM_LDR_PC_G0:
21536 case BFD_RELOC_ARM_LDR_PC_G1:
21537 case BFD_RELOC_ARM_LDR_PC_G2:
21538 case BFD_RELOC_ARM_LDR_SB_G0:
21539 case BFD_RELOC_ARM_LDR_SB_G1:
21540 case BFD_RELOC_ARM_LDR_SB_G2:
21541 gas_assert (!fixP->fx_done);
21542 if (!seg->use_rela_p)
21545 bfd_vma addend_abs = abs (value);
21547 /* Check that the absolute value of the addend can be
21548 encoded in 12 bits. */
21549 if (addend_abs >= 0x1000)
21550 as_bad_where (fixP->fx_file, fixP->fx_line,
21551 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21552 (unsigned long) addend_abs);
21554 /* Extract the instruction. */
21555 insn = md_chars_to_number (buf, INSN_SIZE);
21557 /* If the addend is negative, clear bit 23 of the instruction.
21558 Otherwise set it. */
21560 insn &= ~(1 << 23);
21564 /* Place the absolute value of the addend into the first 12 bits
21565 of the instruction. */
21566 insn &= 0xfffff000;
21567 insn |= addend_abs;
21569 /* Update the instruction. */
21570 md_number_to_chars (buf, insn, INSN_SIZE);
21574 case BFD_RELOC_ARM_LDRS_PC_G0:
21575 case BFD_RELOC_ARM_LDRS_PC_G1:
21576 case BFD_RELOC_ARM_LDRS_PC_G2:
21577 case BFD_RELOC_ARM_LDRS_SB_G0:
21578 case BFD_RELOC_ARM_LDRS_SB_G1:
21579 case BFD_RELOC_ARM_LDRS_SB_G2:
21580 gas_assert (!fixP->fx_done);
21581 if (!seg->use_rela_p)
21584 bfd_vma addend_abs = abs (value);
21586 /* Check that the absolute value of the addend can be
21587 encoded in 8 bits. */
21588 if (addend_abs >= 0x100)
21589 as_bad_where (fixP->fx_file, fixP->fx_line,
21590 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21591 (unsigned long) addend_abs);
21593 /* Extract the instruction. */
21594 insn = md_chars_to_number (buf, INSN_SIZE);
21596 /* If the addend is negative, clear bit 23 of the instruction.
21597 Otherwise set it. */
21599 insn &= ~(1 << 23);
21603 /* Place the first four bits of the absolute value of the addend
21604 into the first 4 bits of the instruction, and the remaining
21605 four into bits 8 .. 11. */
21606 insn &= 0xfffff0f0;
21607 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21609 /* Update the instruction. */
21610 md_number_to_chars (buf, insn, INSN_SIZE);
21614 case BFD_RELOC_ARM_LDC_PC_G0:
21615 case BFD_RELOC_ARM_LDC_PC_G1:
21616 case BFD_RELOC_ARM_LDC_PC_G2:
21617 case BFD_RELOC_ARM_LDC_SB_G0:
21618 case BFD_RELOC_ARM_LDC_SB_G1:
21619 case BFD_RELOC_ARM_LDC_SB_G2:
21620 gas_assert (!fixP->fx_done);
21621 if (!seg->use_rela_p)
21624 bfd_vma addend_abs = abs (value);
21626 /* Check that the absolute value of the addend is a multiple of
21627 four and, when divided by four, fits in 8 bits. */
21628 if (addend_abs & 0x3)
21629 as_bad_where (fixP->fx_file, fixP->fx_line,
21630 _("bad offset 0x%08lX (must be word-aligned)"),
21631 (unsigned long) addend_abs);
21633 if ((addend_abs >> 2) > 0xff)
21634 as_bad_where (fixP->fx_file, fixP->fx_line,
21635 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21636 (unsigned long) addend_abs);
21638 /* Extract the instruction. */
21639 insn = md_chars_to_number (buf, INSN_SIZE);
21641 /* If the addend is negative, clear bit 23 of the instruction.
21642 Otherwise set it. */
21644 insn &= ~(1 << 23);
21648 /* Place the addend (divided by four) into the first eight
21649 bits of the instruction. */
21650 insn &= 0xfffffff0;
21651 insn |= addend_abs >> 2;
21653 /* Update the instruction. */
21654 md_number_to_chars (buf, insn, INSN_SIZE);
21658 case BFD_RELOC_ARM_V4BX:
21659 /* This will need to go in the object file. */
21663 case BFD_RELOC_UNUSED:
21665 as_bad_where (fixP->fx_file, fixP->fx_line,
21666 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21670 /* Translate internal representation of relocation info to BFD target
21674 tc_gen_reloc (asection *section, fixS *fixp)
21677 bfd_reloc_code_real_type code;
21679 reloc = (arelent *) xmalloc (sizeof (arelent));
21681 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21682 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21683 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21685 if (fixp->fx_pcrel)
21687 if (section->use_rela_p)
21688 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21690 fixp->fx_offset = reloc->address;
21692 reloc->addend = fixp->fx_offset;
21694 switch (fixp->fx_r_type)
21697 if (fixp->fx_pcrel)
21699 code = BFD_RELOC_8_PCREL;
21704 if (fixp->fx_pcrel)
21706 code = BFD_RELOC_16_PCREL;
21711 if (fixp->fx_pcrel)
21713 code = BFD_RELOC_32_PCREL;
21717 case BFD_RELOC_ARM_MOVW:
21718 if (fixp->fx_pcrel)
21720 code = BFD_RELOC_ARM_MOVW_PCREL;
21724 case BFD_RELOC_ARM_MOVT:
21725 if (fixp->fx_pcrel)
21727 code = BFD_RELOC_ARM_MOVT_PCREL;
21731 case BFD_RELOC_ARM_THUMB_MOVW:
21732 if (fixp->fx_pcrel)
21734 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21738 case BFD_RELOC_ARM_THUMB_MOVT:
21739 if (fixp->fx_pcrel)
21741 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21745 case BFD_RELOC_NONE:
21746 case BFD_RELOC_ARM_PCREL_BRANCH:
21747 case BFD_RELOC_ARM_PCREL_BLX:
21748 case BFD_RELOC_RVA:
21749 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21750 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21751 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21752 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21753 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21754 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21755 case BFD_RELOC_VTABLE_ENTRY:
21756 case BFD_RELOC_VTABLE_INHERIT:
21758 case BFD_RELOC_32_SECREL:
21760 code = fixp->fx_r_type;
21763 case BFD_RELOC_THUMB_PCREL_BLX:
21765 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21766 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21769 code = BFD_RELOC_THUMB_PCREL_BLX;
21772 case BFD_RELOC_ARM_LITERAL:
21773 case BFD_RELOC_ARM_HWLITERAL:
21774 /* If this is called then the a literal has
21775 been referenced across a section boundary. */
21776 as_bad_where (fixp->fx_file, fixp->fx_line,
21777 _("literal referenced across section boundary"));
21781 case BFD_RELOC_ARM_TLS_CALL:
21782 case BFD_RELOC_ARM_THM_TLS_CALL:
21783 case BFD_RELOC_ARM_TLS_DESCSEQ:
21784 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21785 case BFD_RELOC_ARM_GOT32:
21786 case BFD_RELOC_ARM_GOTOFF:
21787 case BFD_RELOC_ARM_GOT_PREL:
21788 case BFD_RELOC_ARM_PLT32:
21789 case BFD_RELOC_ARM_TARGET1:
21790 case BFD_RELOC_ARM_ROSEGREL32:
21791 case BFD_RELOC_ARM_SBREL32:
21792 case BFD_RELOC_ARM_PREL31:
21793 case BFD_RELOC_ARM_TARGET2:
21794 case BFD_RELOC_ARM_TLS_LE32:
21795 case BFD_RELOC_ARM_TLS_LDO32:
21796 case BFD_RELOC_ARM_PCREL_CALL:
21797 case BFD_RELOC_ARM_PCREL_JUMP:
21798 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21799 case BFD_RELOC_ARM_ALU_PC_G0:
21800 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21801 case BFD_RELOC_ARM_ALU_PC_G1:
21802 case BFD_RELOC_ARM_ALU_PC_G2:
21803 case BFD_RELOC_ARM_LDR_PC_G0:
21804 case BFD_RELOC_ARM_LDR_PC_G1:
21805 case BFD_RELOC_ARM_LDR_PC_G2:
21806 case BFD_RELOC_ARM_LDRS_PC_G0:
21807 case BFD_RELOC_ARM_LDRS_PC_G1:
21808 case BFD_RELOC_ARM_LDRS_PC_G2:
21809 case BFD_RELOC_ARM_LDC_PC_G0:
21810 case BFD_RELOC_ARM_LDC_PC_G1:
21811 case BFD_RELOC_ARM_LDC_PC_G2:
21812 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21813 case BFD_RELOC_ARM_ALU_SB_G0:
21814 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21815 case BFD_RELOC_ARM_ALU_SB_G1:
21816 case BFD_RELOC_ARM_ALU_SB_G2:
21817 case BFD_RELOC_ARM_LDR_SB_G0:
21818 case BFD_RELOC_ARM_LDR_SB_G1:
21819 case BFD_RELOC_ARM_LDR_SB_G2:
21820 case BFD_RELOC_ARM_LDRS_SB_G0:
21821 case BFD_RELOC_ARM_LDRS_SB_G1:
21822 case BFD_RELOC_ARM_LDRS_SB_G2:
21823 case BFD_RELOC_ARM_LDC_SB_G0:
21824 case BFD_RELOC_ARM_LDC_SB_G1:
21825 case BFD_RELOC_ARM_LDC_SB_G2:
21826 case BFD_RELOC_ARM_V4BX:
21827 code = fixp->fx_r_type;
21830 case BFD_RELOC_ARM_TLS_GOTDESC:
21831 case BFD_RELOC_ARM_TLS_GD32:
21832 case BFD_RELOC_ARM_TLS_IE32:
21833 case BFD_RELOC_ARM_TLS_LDM32:
21834 /* BFD will include the symbol's address in the addend.
21835 But we don't want that, so subtract it out again here. */
21836 if (!S_IS_COMMON (fixp->fx_addsy))
21837 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21838 code = fixp->fx_r_type;
21842 case BFD_RELOC_ARM_IMMEDIATE:
21843 as_bad_where (fixp->fx_file, fixp->fx_line,
21844 _("internal relocation (type: IMMEDIATE) not fixed up"));
21847 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21848 as_bad_where (fixp->fx_file, fixp->fx_line,
21849 _("ADRL used for a symbol not defined in the same file"));
21852 case BFD_RELOC_ARM_OFFSET_IMM:
21853 if (section->use_rela_p)
21855 code = fixp->fx_r_type;
21859 if (fixp->fx_addsy != NULL
21860 && !S_IS_DEFINED (fixp->fx_addsy)
21861 && S_IS_LOCAL (fixp->fx_addsy))
21863 as_bad_where (fixp->fx_file, fixp->fx_line,
21864 _("undefined local label `%s'"),
21865 S_GET_NAME (fixp->fx_addsy));
21869 as_bad_where (fixp->fx_file, fixp->fx_line,
21870 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21877 switch (fixp->fx_r_type)
21879 case BFD_RELOC_NONE: type = "NONE"; break;
21880 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21881 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21882 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21883 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21884 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21885 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21886 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21887 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21888 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21889 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21890 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21891 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21892 default: type = _("<unknown>"); break;
21894 as_bad_where (fixp->fx_file, fixp->fx_line,
21895 _("cannot represent %s relocation in this object file format"),
21902 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21904 && fixp->fx_addsy == GOT_symbol)
21906 code = BFD_RELOC_ARM_GOTPC;
21907 reloc->addend = fixp->fx_offset = reloc->address;
21911 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21913 if (reloc->howto == NULL)
21915 as_bad_where (fixp->fx_file, fixp->fx_line,
21916 _("cannot represent %s relocation in this object file format"),
21917 bfd_get_reloc_code_name (code));
21921 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21922 vtable entry to be used in the relocation's section offset. */
21923 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21924 reloc->address = fixp->fx_offset;
21929 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21932 cons_fix_new_arm (fragS * frag,
21937 bfd_reloc_code_real_type type;
21941 FIXME: @@ Should look at CPU word size. */
21945 type = BFD_RELOC_8;
21948 type = BFD_RELOC_16;
21952 type = BFD_RELOC_32;
21955 type = BFD_RELOC_64;
21960 if (exp->X_op == O_secrel)
21962 exp->X_op = O_symbol;
21963 type = BFD_RELOC_32_SECREL;
21967 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
21970 #if defined (OBJ_COFF)
21972 arm_validate_fix (fixS * fixP)
21974 /* If the destination of the branch is a defined symbol which does not have
21975 the THUMB_FUNC attribute, then we must be calling a function which has
21976 the (interfacearm) attribute. We look for the Thumb entry point to that
21977 function and change the branch to refer to that function instead. */
21978 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
21979 && fixP->fx_addsy != NULL
21980 && S_IS_DEFINED (fixP->fx_addsy)
21981 && ! THUMB_IS_FUNC (fixP->fx_addsy))
21983 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
21990 arm_force_relocation (struct fix * fixp)
21992 #if defined (OBJ_COFF) && defined (TE_PE)
21993 if (fixp->fx_r_type == BFD_RELOC_RVA)
21997 /* In case we have a call or a branch to a function in ARM ISA mode from
21998 a thumb function or vice-versa force the relocation. These relocations
21999 are cleared off for some cores that might have blx and simple transformations
22003 switch (fixp->fx_r_type)
22005 case BFD_RELOC_ARM_PCREL_JUMP:
22006 case BFD_RELOC_ARM_PCREL_CALL:
22007 case BFD_RELOC_THUMB_PCREL_BLX:
22008 if (THUMB_IS_FUNC (fixp->fx_addsy))
22012 case BFD_RELOC_ARM_PCREL_BLX:
22013 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22014 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22015 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22016 if (ARM_IS_FUNC (fixp->fx_addsy))
22025 /* Resolve these relocations even if the symbol is extern or weak.
22026 Technically this is probably wrong due to symbol preemption.
22027 In practice these relocations do not have enough range to be useful
22028 at dynamic link time, and some code (e.g. in the Linux kernel)
22029 expects these references to be resolved. */
22030 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22031 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22032 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22033 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22034 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22035 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22036 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22037 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22038 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22039 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22040 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22041 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22042 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22043 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22046 /* Always leave these relocations for the linker. */
22047 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22048 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22049 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22052 /* Always generate relocations against function symbols. */
22053 if (fixp->fx_r_type == BFD_RELOC_32
22055 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22058 return generic_force_reloc (fixp);
22061 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22062 /* Relocations against function names must be left unadjusted,
22063 so that the linker can use this information to generate interworking
22064 stubs. The MIPS version of this function
22065 also prevents relocations that are mips-16 specific, but I do not
22066 know why it does this.
22069 There is one other problem that ought to be addressed here, but
22070 which currently is not: Taking the address of a label (rather
22071 than a function) and then later jumping to that address. Such
22072 addresses also ought to have their bottom bit set (assuming that
22073 they reside in Thumb code), but at the moment they will not. */
22076 arm_fix_adjustable (fixS * fixP)
22078 if (fixP->fx_addsy == NULL)
22081 /* Preserve relocations against symbols with function type. */
22082 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22085 if (THUMB_IS_FUNC (fixP->fx_addsy)
22086 && fixP->fx_subsy == NULL)
22089 /* We need the symbol name for the VTABLE entries. */
22090 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22091 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22094 /* Don't allow symbols to be discarded on GOT related relocs. */
22095 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22096 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22097 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22098 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22099 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22100 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22101 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22102 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22103 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22104 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22105 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22106 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22107 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22108 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22111 /* Similarly for group relocations. */
22112 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22113 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22114 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22117 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22118 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22119 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22120 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22121 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22122 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22123 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22124 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22125 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22130 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22135 elf32_arm_target_format (void)
22138 return (target_big_endian
22139 ? "elf32-bigarm-symbian"
22140 : "elf32-littlearm-symbian");
22141 #elif defined (TE_VXWORKS)
22142 return (target_big_endian
22143 ? "elf32-bigarm-vxworks"
22144 : "elf32-littlearm-vxworks");
22146 if (target_big_endian)
22147 return "elf32-bigarm";
22149 return "elf32-littlearm";
22154 armelf_frob_symbol (symbolS * symp,
22157 elf_frob_symbol (symp, puntp);
22161 /* MD interface: Finalization. */
22166 literal_pool * pool;
22168 /* Ensure that all the IT blocks are properly closed. */
22169 check_it_blocks_finished ();
22171 for (pool = list_of_pools; pool; pool = pool->next)
22173 /* Put it at the end of the relevant section. */
22174 subseg_set (pool->section, pool->sub_section);
22176 arm_elf_change_section ();
22183 /* Remove any excess mapping symbols generated for alignment frags in
22184 SEC. We may have created a mapping symbol before a zero byte
22185 alignment; remove it if there's a mapping symbol after the
22188 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22189 void *dummy ATTRIBUTE_UNUSED)
22191 segment_info_type *seginfo = seg_info (sec);
22194 if (seginfo == NULL || seginfo->frchainP == NULL)
22197 for (fragp = seginfo->frchainP->frch_root;
22199 fragp = fragp->fr_next)
22201 symbolS *sym = fragp->tc_frag_data.last_map;
22202 fragS *next = fragp->fr_next;
22204 /* Variable-sized frags have been converted to fixed size by
22205 this point. But if this was variable-sized to start with,
22206 there will be a fixed-size frag after it. So don't handle
22208 if (sym == NULL || next == NULL)
22211 if (S_GET_VALUE (sym) < next->fr_address)
22212 /* Not at the end of this frag. */
22214 know (S_GET_VALUE (sym) == next->fr_address);
22218 if (next->tc_frag_data.first_map != NULL)
22220 /* Next frag starts with a mapping symbol. Discard this
22222 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22226 if (next->fr_next == NULL)
22228 /* This mapping symbol is at the end of the section. Discard
22230 know (next->fr_fix == 0 && next->fr_var == 0);
22231 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22235 /* As long as we have empty frags without any mapping symbols,
22237 /* If the next frag is non-empty and does not start with a
22238 mapping symbol, then this mapping symbol is required. */
22239 if (next->fr_address != next->fr_next->fr_address)
22242 next = next->fr_next;
22244 while (next != NULL);
22249 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22253 arm_adjust_symtab (void)
22258 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22260 if (ARM_IS_THUMB (sym))
22262 if (THUMB_IS_FUNC (sym))
22264 /* Mark the symbol as a Thumb function. */
22265 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22266 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22267 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22269 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22270 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22272 as_bad (_("%s: unexpected function type: %d"),
22273 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22275 else switch (S_GET_STORAGE_CLASS (sym))
22278 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22281 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22284 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22292 if (ARM_IS_INTERWORK (sym))
22293 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22300 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22302 if (ARM_IS_THUMB (sym))
22304 elf_symbol_type * elf_sym;
22306 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22307 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22309 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22310 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22312 /* If it's a .thumb_func, declare it as so,
22313 otherwise tag label as .code 16. */
22314 if (THUMB_IS_FUNC (sym))
22315 elf_sym->internal_elf_sym.st_target_internal
22316 = ST_BRANCH_TO_THUMB;
22317 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22318 elf_sym->internal_elf_sym.st_info =
22319 ELF_ST_INFO (bind, STT_ARM_16BIT);
22324 /* Remove any overlapping mapping symbols generated by alignment frags. */
22325 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22326 /* Now do generic ELF adjustments. */
22327 elf_adjust_symtab ();
22331 /* MD interface: Initialization. */
22334 set_constant_flonums (void)
22338 for (i = 0; i < NUM_FLOAT_VALS; i++)
22339 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22343 /* Auto-select Thumb mode if it's the only available instruction set for the
22344 given architecture. */
22347 autoselect_thumb_from_cpu_variant (void)
22349 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22350 opcode_select (16);
22359 if ( (arm_ops_hsh = hash_new ()) == NULL
22360 || (arm_cond_hsh = hash_new ()) == NULL
22361 || (arm_shift_hsh = hash_new ()) == NULL
22362 || (arm_psr_hsh = hash_new ()) == NULL
22363 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22364 || (arm_reg_hsh = hash_new ()) == NULL
22365 || (arm_reloc_hsh = hash_new ()) == NULL
22366 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22367 as_fatal (_("virtual memory exhausted"));
22369 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22370 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22371 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22372 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22373 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22374 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22375 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22376 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22377 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22378 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22379 (void *) (v7m_psrs + i));
22380 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22381 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22383 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22385 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22386 (void *) (barrier_opt_names + i));
22388 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
22389 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
22392 set_constant_flonums ();
22394 /* Set the cpu variant based on the command-line options. We prefer
22395 -mcpu= over -march= if both are set (as for GCC); and we prefer
22396 -mfpu= over any other way of setting the floating point unit.
22397 Use of legacy options with new options are faulted. */
22400 if (mcpu_cpu_opt || march_cpu_opt)
22401 as_bad (_("use of old and new-style options to set CPU type"));
22403 mcpu_cpu_opt = legacy_cpu;
22405 else if (!mcpu_cpu_opt)
22406 mcpu_cpu_opt = march_cpu_opt;
22411 as_bad (_("use of old and new-style options to set FPU type"));
22413 mfpu_opt = legacy_fpu;
22415 else if (!mfpu_opt)
22417 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22418 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22419 /* Some environments specify a default FPU. If they don't, infer it
22420 from the processor. */
22422 mfpu_opt = mcpu_fpu_opt;
22424 mfpu_opt = march_fpu_opt;
22426 mfpu_opt = &fpu_default;
22432 if (mcpu_cpu_opt != NULL)
22433 mfpu_opt = &fpu_default;
22434 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22435 mfpu_opt = &fpu_arch_vfp_v2;
22437 mfpu_opt = &fpu_arch_fpa;
22443 mcpu_cpu_opt = &cpu_default;
22444 selected_cpu = cpu_default;
22448 selected_cpu = *mcpu_cpu_opt;
22450 mcpu_cpu_opt = &arm_arch_any;
22453 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22455 autoselect_thumb_from_cpu_variant ();
22457 arm_arch_used = thumb_arch_used = arm_arch_none;
22459 #if defined OBJ_COFF || defined OBJ_ELF
22461 unsigned int flags = 0;
22463 #if defined OBJ_ELF
22464 flags = meabi_flags;
22466 switch (meabi_flags)
22468 case EF_ARM_EABI_UNKNOWN:
22470 /* Set the flags in the private structure. */
22471 if (uses_apcs_26) flags |= F_APCS26;
22472 if (support_interwork) flags |= F_INTERWORK;
22473 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22474 if (pic_code) flags |= F_PIC;
22475 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22476 flags |= F_SOFT_FLOAT;
22478 switch (mfloat_abi_opt)
22480 case ARM_FLOAT_ABI_SOFT:
22481 case ARM_FLOAT_ABI_SOFTFP:
22482 flags |= F_SOFT_FLOAT;
22485 case ARM_FLOAT_ABI_HARD:
22486 if (flags & F_SOFT_FLOAT)
22487 as_bad (_("hard-float conflicts with specified fpu"));
22491 /* Using pure-endian doubles (even if soft-float). */
22492 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22493 flags |= F_VFP_FLOAT;
22495 #if defined OBJ_ELF
22496 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22497 flags |= EF_ARM_MAVERICK_FLOAT;
22500 case EF_ARM_EABI_VER4:
22501 case EF_ARM_EABI_VER5:
22502 /* No additional flags to set. */
22509 bfd_set_private_flags (stdoutput, flags);
22511 /* We have run out flags in the COFF header to encode the
22512 status of ATPCS support, so instead we create a dummy,
22513 empty, debug section called .arm.atpcs. */
22518 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22522 bfd_set_section_flags
22523 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22524 bfd_set_section_size (stdoutput, sec, 0);
22525 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22531 /* Record the CPU type as well. */
22532 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22533 mach = bfd_mach_arm_iWMMXt2;
22534 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22535 mach = bfd_mach_arm_iWMMXt;
22536 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22537 mach = bfd_mach_arm_XScale;
22538 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22539 mach = bfd_mach_arm_ep9312;
22540 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22541 mach = bfd_mach_arm_5TE;
22542 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22544 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22545 mach = bfd_mach_arm_5T;
22547 mach = bfd_mach_arm_5;
22549 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22551 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22552 mach = bfd_mach_arm_4T;
22554 mach = bfd_mach_arm_4;
22556 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22557 mach = bfd_mach_arm_3M;
22558 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22559 mach = bfd_mach_arm_3;
22560 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22561 mach = bfd_mach_arm_2a;
22562 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22563 mach = bfd_mach_arm_2;
22565 mach = bfd_mach_arm_unknown;
22567 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22570 /* Command line processing. */
22573 Invocation line includes a switch not recognized by the base assembler.
22574 See if it's a processor-specific option.
22576 This routine is somewhat complicated by the need for backwards
22577 compatibility (since older releases of gcc can't be changed).
22578 The new options try to make the interface as compatible as
22581 New options (supported) are:
22583 -mcpu=<cpu name> Assemble for selected processor
22584 -march=<architecture name> Assemble for selected architecture
22585 -mfpu=<fpu architecture> Assemble for selected FPU.
22586 -EB/-mbig-endian Big-endian
22587 -EL/-mlittle-endian Little-endian
22588 -k Generate PIC code
22589 -mthumb Start in Thumb mode
22590 -mthumb-interwork Code supports ARM/Thumb interworking
22592 -m[no-]warn-deprecated Warn about deprecated features
22594 For now we will also provide support for:
22596 -mapcs-32 32-bit Program counter
22597 -mapcs-26 26-bit Program counter
22598 -macps-float Floats passed in FP registers
22599 -mapcs-reentrant Reentrant code
22601 (sometime these will probably be replaced with -mapcs=<list of options>
22602 and -matpcs=<list of options>)
22604 The remaining options are only supported for back-wards compatibility.
22605 Cpu variants, the arm part is optional:
22606 -m[arm]1 Currently not supported.
22607 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22608 -m[arm]3 Arm 3 processor
22609 -m[arm]6[xx], Arm 6 processors
22610 -m[arm]7[xx][t][[d]m] Arm 7 processors
22611 -m[arm]8[10] Arm 8 processors
22612 -m[arm]9[20][tdmi] Arm 9 processors
22613 -mstrongarm[110[0]] StrongARM processors
22614 -mxscale XScale processors
22615 -m[arm]v[2345[t[e]]] Arm architectures
22616 -mall All (except the ARM1)
22618 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22619 -mfpe-old (No float load/store multiples)
22620 -mvfpxd VFP Single precision
22622 -mno-fpu Disable all floating point instructions
22624 The following CPU names are recognized:
22625 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22626 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22627 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22628 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22629 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22630 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22631 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22635 const char * md_shortopts = "m:k";
22637 #ifdef ARM_BI_ENDIAN
22638 #define OPTION_EB (OPTION_MD_BASE + 0)
22639 #define OPTION_EL (OPTION_MD_BASE + 1)
22641 #if TARGET_BYTES_BIG_ENDIAN
22642 #define OPTION_EB (OPTION_MD_BASE + 0)
22644 #define OPTION_EL (OPTION_MD_BASE + 1)
22647 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22649 struct option md_longopts[] =
22652 {"EB", no_argument, NULL, OPTION_EB},
22655 {"EL", no_argument, NULL, OPTION_EL},
22657 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22658 {NULL, no_argument, NULL, 0}
22661 size_t md_longopts_size = sizeof (md_longopts);
22663 struct arm_option_table
22665 char *option; /* Option name to match. */
22666 char *help; /* Help information. */
22667 int *var; /* Variable to change. */
22668 int value; /* What to change it to. */
22669 char *deprecated; /* If non-null, print this message. */
22672 struct arm_option_table arm_opts[] =
22674 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22675 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22676 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22677 &support_interwork, 1, NULL},
22678 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22679 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22680 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22682 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22683 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22684 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22685 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22688 /* These are recognized by the assembler, but have no affect on code. */
22689 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22690 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22692 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22693 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22694 &warn_on_deprecated, 0, NULL},
22695 {NULL, NULL, NULL, 0, NULL}
22698 struct arm_legacy_option_table
22700 char *option; /* Option name to match. */
22701 const arm_feature_set **var; /* Variable to change. */
22702 const arm_feature_set value; /* What to change it to. */
22703 char *deprecated; /* If non-null, print this message. */
22706 const struct arm_legacy_option_table arm_legacy_opts[] =
22708 /* DON'T add any new processors to this list -- we want the whole list
22709 to go away... Add them to the processors table instead. */
22710 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22711 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22712 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22713 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22714 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22715 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22716 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22717 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22718 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22719 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22720 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22721 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22722 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22723 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22724 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22725 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22726 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22727 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22728 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22729 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22730 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22731 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22732 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22733 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22734 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22735 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22736 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22737 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22738 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22739 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22740 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22741 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22742 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22743 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22744 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22745 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22746 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22747 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22748 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22749 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22750 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22751 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22752 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22753 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22754 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22755 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22756 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22757 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22758 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22759 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22760 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22761 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22762 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22763 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22764 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22765 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22766 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22767 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22768 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22769 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22770 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22771 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22772 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22773 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22774 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22775 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22776 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22777 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22778 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22779 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22780 N_("use -mcpu=strongarm110")},
22781 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22782 N_("use -mcpu=strongarm1100")},
22783 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22784 N_("use -mcpu=strongarm1110")},
22785 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22786 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22787 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22789 /* Architecture variants -- don't add any more to this list either. */
22790 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22791 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22792 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22793 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22794 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22795 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22796 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22797 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22798 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22799 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22800 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22801 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22802 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22803 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22804 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22805 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22806 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22807 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22809 /* Floating point variants -- don't add any more to this list either. */
22810 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22811 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22812 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22813 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22814 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22816 {NULL, NULL, ARM_ARCH_NONE, NULL}
22819 struct arm_cpu_option_table
22822 const arm_feature_set value;
22823 /* For some CPUs we assume an FPU unless the user explicitly sets
22825 const arm_feature_set default_fpu;
22826 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22828 const char *canonical_name;
22831 /* This list should, at a minimum, contain all the cpu names
22832 recognized by GCC. */
22833 static const struct arm_cpu_option_table arm_cpus[] =
22835 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22836 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22837 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22838 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22839 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22840 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22841 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22842 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22843 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22844 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22845 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22846 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22847 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22848 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22849 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22850 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22851 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22852 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22853 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22854 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22855 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22856 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22857 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22858 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22859 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22860 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22861 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22862 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22863 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22864 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22865 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22866 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22867 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22868 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22869 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22870 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22871 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22872 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22873 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22874 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22875 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22876 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22877 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22878 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22879 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22880 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22881 /* For V5 or later processors we default to using VFP; but the user
22882 should really set the FPU type explicitly. */
22883 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22884 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22885 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22886 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22887 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22888 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22889 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22890 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22891 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22892 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22893 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22894 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22895 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22896 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22897 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22898 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22899 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22900 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22901 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22902 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22903 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22904 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22905 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22906 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22907 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22908 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22909 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22910 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22911 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22912 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22913 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22914 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22915 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22916 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22917 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22918 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22919 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22920 FPU_NONE, "Cortex-A5"},
22921 {"cortex-a8", ARM_ARCH_V7A_SEC,
22922 ARM_FEATURE (0, FPU_VFP_V3
22923 | FPU_NEON_EXT_V1),
22925 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22926 ARM_FEATURE (0, FPU_VFP_V3
22927 | FPU_NEON_EXT_V1),
22929 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22930 FPU_ARCH_NEON_VFP_V4,
22932 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22933 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22935 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22936 FPU_NONE, "Cortex-R5"},
22937 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22938 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22939 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22940 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22941 /* ??? XSCALE is really an architecture. */
22942 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22943 /* ??? iwmmxt is not a processor. */
22944 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
22945 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
22946 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22948 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
22949 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
22952 struct arm_arch_option_table
22955 const arm_feature_set value;
22956 const arm_feature_set default_fpu;
22959 /* This list should, at a minimum, contain all the architecture names
22960 recognized by GCC. */
22961 static const struct arm_arch_option_table arm_archs[] =
22963 {"all", ARM_ANY, FPU_ARCH_FPA},
22964 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
22965 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
22966 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
22967 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
22968 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
22969 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
22970 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
22971 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
22972 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
22973 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
22974 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
22975 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
22976 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
22977 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
22978 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
22979 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
22980 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
22981 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
22982 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
22983 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
22984 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
22985 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
22986 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
22987 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
22988 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
22989 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
22990 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
22991 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
22992 /* The official spelling of the ARMv7 profile variants is the dashed form.
22993 Accept the non-dashed form for compatibility with old toolchains. */
22994 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22995 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22996 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
22997 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22998 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22999 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23000 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
23001 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
23002 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
23003 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
23004 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23007 /* ISA extensions in the co-processor and main instruction set space. */
23008 struct arm_option_extension_value_table
23011 const arm_feature_set value;
23012 const arm_feature_set allowed_archs;
23015 /* The following table must be in alphabetical order with a NULL last entry.
23017 static const struct arm_option_extension_value_table arm_extensions[] =
23019 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23020 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23021 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
23022 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
23023 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
23024 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
23025 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23026 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
23027 ARM_FEATURE (ARM_EXT_V6M, 0)},
23028 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23029 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
23030 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23031 ARM_FEATURE (ARM_EXT_V7A, 0)},
23032 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
23033 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23036 /* ISA floating-point and Advanced SIMD extensions. */
23037 struct arm_option_fpu_value_table
23040 const arm_feature_set value;
23043 /* This list should, at a minimum, contain all the fpu names
23044 recognized by GCC. */
23045 static const struct arm_option_fpu_value_table arm_fpus[] =
23047 {"softfpa", FPU_NONE},
23048 {"fpe", FPU_ARCH_FPE},
23049 {"fpe2", FPU_ARCH_FPE},
23050 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23051 {"fpa", FPU_ARCH_FPA},
23052 {"fpa10", FPU_ARCH_FPA},
23053 {"fpa11", FPU_ARCH_FPA},
23054 {"arm7500fe", FPU_ARCH_FPA},
23055 {"softvfp", FPU_ARCH_VFP},
23056 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23057 {"vfp", FPU_ARCH_VFP_V2},
23058 {"vfp9", FPU_ARCH_VFP_V2},
23059 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23060 {"vfp10", FPU_ARCH_VFP_V2},
23061 {"vfp10-r0", FPU_ARCH_VFP_V1},
23062 {"vfpxd", FPU_ARCH_VFP_V1xD},
23063 {"vfpv2", FPU_ARCH_VFP_V2},
23064 {"vfpv3", FPU_ARCH_VFP_V3},
23065 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23066 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23067 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23068 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23069 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23070 {"arm1020t", FPU_ARCH_VFP_V1},
23071 {"arm1020e", FPU_ARCH_VFP_V2},
23072 {"arm1136jfs", FPU_ARCH_VFP_V2},
23073 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23074 {"maverick", FPU_ARCH_MAVERICK},
23075 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23076 {"neon-fp16", FPU_ARCH_NEON_FP16},
23077 {"vfpv4", FPU_ARCH_VFP_V4},
23078 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23079 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23080 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23081 {NULL, ARM_ARCH_NONE}
23084 struct arm_option_value_table
23090 static const struct arm_option_value_table arm_float_abis[] =
23092 {"hard", ARM_FLOAT_ABI_HARD},
23093 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23094 {"soft", ARM_FLOAT_ABI_SOFT},
23099 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23100 static const struct arm_option_value_table arm_eabis[] =
23102 {"gnu", EF_ARM_EABI_UNKNOWN},
23103 {"4", EF_ARM_EABI_VER4},
23104 {"5", EF_ARM_EABI_VER5},
23109 struct arm_long_option_table
23111 char * option; /* Substring to match. */
23112 char * help; /* Help information. */
23113 int (* func) (char * subopt); /* Function to decode sub-option. */
23114 char * deprecated; /* If non-null, print this message. */
23118 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23120 arm_feature_set *ext_set = (arm_feature_set *)
23121 xmalloc (sizeof (arm_feature_set));
23123 /* We insist on extensions being specified in alphabetical order, and with
23124 extensions being added before being removed. We achieve this by having
23125 the global ARM_EXTENSIONS table in alphabetical order, and using the
23126 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23127 or removing it (0) and only allowing it to change in the order
23129 const struct arm_option_extension_value_table * opt = NULL;
23130 int adding_value = -1;
23132 /* Copy the feature set, so that we can modify it. */
23133 *ext_set = **opt_p;
23136 while (str != NULL && *str != 0)
23143 as_bad (_("invalid architectural extension"));
23148 ext = strchr (str, '+');
23151 optlen = ext - str;
23153 optlen = strlen (str);
23156 && strncmp (str, "no", 2) == 0)
23158 if (adding_value != 0)
23161 opt = arm_extensions;
23167 else if (optlen > 0)
23169 if (adding_value == -1)
23172 opt = arm_extensions;
23174 else if (adding_value != 1)
23176 as_bad (_("must specify extensions to add before specifying "
23177 "those to remove"));
23184 as_bad (_("missing architectural extension"));
23188 gas_assert (adding_value != -1);
23189 gas_assert (opt != NULL);
23191 /* Scan over the options table trying to find an exact match. */
23192 for (; opt->name != NULL; opt++)
23193 if (strncmp (opt->name, str, optlen) == 0
23194 && strlen (opt->name) == optlen)
23196 /* Check we can apply the extension to this architecture. */
23197 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23199 as_bad (_("extension does not apply to the base architecture"));
23203 /* Add or remove the extension. */
23205 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23207 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23212 if (opt->name == NULL)
23214 /* Did we fail to find an extension because it wasn't specified in
23215 alphabetical order, or because it does not exist? */
23217 for (opt = arm_extensions; opt->name != NULL; opt++)
23218 if (strncmp (opt->name, str, optlen) == 0)
23221 if (opt->name == NULL)
23222 as_bad (_("unknown architectural extension `%s'"), str);
23224 as_bad (_("architectural extensions must be specified in "
23225 "alphabetical order"));
23231 /* We should skip the extension we've just matched the next time
23243 arm_parse_cpu (char * str)
23245 const struct arm_cpu_option_table * opt;
23246 char * ext = strchr (str, '+');
23250 optlen = ext - str;
23252 optlen = strlen (str);
23256 as_bad (_("missing cpu name `%s'"), str);
23260 for (opt = arm_cpus; opt->name != NULL; opt++)
23261 if (strncmp (opt->name, str, optlen) == 0)
23263 mcpu_cpu_opt = &opt->value;
23264 mcpu_fpu_opt = &opt->default_fpu;
23265 if (opt->canonical_name)
23266 strcpy (selected_cpu_name, opt->canonical_name);
23271 for (i = 0; i < optlen; i++)
23272 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23273 selected_cpu_name[i] = 0;
23277 return arm_parse_extension (ext, &mcpu_cpu_opt);
23282 as_bad (_("unknown cpu `%s'"), str);
23287 arm_parse_arch (char * str)
23289 const struct arm_arch_option_table *opt;
23290 char *ext = strchr (str, '+');
23294 optlen = ext - str;
23296 optlen = strlen (str);
23300 as_bad (_("missing architecture name `%s'"), str);
23304 for (opt = arm_archs; opt->name != NULL; opt++)
23305 if (strncmp (opt->name, str, optlen) == 0)
23307 march_cpu_opt = &opt->value;
23308 march_fpu_opt = &opt->default_fpu;
23309 strcpy (selected_cpu_name, opt->name);
23312 return arm_parse_extension (ext, &march_cpu_opt);
23317 as_bad (_("unknown architecture `%s'\n"), str);
23322 arm_parse_fpu (char * str)
23324 const struct arm_option_fpu_value_table * opt;
23326 for (opt = arm_fpus; opt->name != NULL; opt++)
23327 if (streq (opt->name, str))
23329 mfpu_opt = &opt->value;
23333 as_bad (_("unknown floating point format `%s'\n"), str);
23338 arm_parse_float_abi (char * str)
23340 const struct arm_option_value_table * opt;
23342 for (opt = arm_float_abis; opt->name != NULL; opt++)
23343 if (streq (opt->name, str))
23345 mfloat_abi_opt = opt->value;
23349 as_bad (_("unknown floating point abi `%s'\n"), str);
23355 arm_parse_eabi (char * str)
23357 const struct arm_option_value_table *opt;
23359 for (opt = arm_eabis; opt->name != NULL; opt++)
23360 if (streq (opt->name, str))
23362 meabi_flags = opt->value;
23365 as_bad (_("unknown EABI `%s'\n"), str);
23371 arm_parse_it_mode (char * str)
23373 bfd_boolean ret = TRUE;
23375 if (streq ("arm", str))
23376 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23377 else if (streq ("thumb", str))
23378 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23379 else if (streq ("always", str))
23380 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23381 else if (streq ("never", str))
23382 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23385 as_bad (_("unknown implicit IT mode `%s', should be "\
23386 "arm, thumb, always, or never."), str);
23393 struct arm_long_option_table arm_long_opts[] =
23395 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23396 arm_parse_cpu, NULL},
23397 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23398 arm_parse_arch, NULL},
23399 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23400 arm_parse_fpu, NULL},
23401 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23402 arm_parse_float_abi, NULL},
23404 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23405 arm_parse_eabi, NULL},
23407 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23408 arm_parse_it_mode, NULL},
23409 {NULL, NULL, 0, NULL}
23413 md_parse_option (int c, char * arg)
23415 struct arm_option_table *opt;
23416 const struct arm_legacy_option_table *fopt;
23417 struct arm_long_option_table *lopt;
23423 target_big_endian = 1;
23429 target_big_endian = 0;
23433 case OPTION_FIX_V4BX:
23438 /* Listing option. Just ignore these, we don't support additional
23443 for (opt = arm_opts; opt->option != NULL; opt++)
23445 if (c == opt->option[0]
23446 && ((arg == NULL && opt->option[1] == 0)
23447 || streq (arg, opt->option + 1)))
23449 /* If the option is deprecated, tell the user. */
23450 if (warn_on_deprecated && opt->deprecated != NULL)
23451 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23452 arg ? arg : "", _(opt->deprecated));
23454 if (opt->var != NULL)
23455 *opt->var = opt->value;
23461 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23463 if (c == fopt->option[0]
23464 && ((arg == NULL && fopt->option[1] == 0)
23465 || streq (arg, fopt->option + 1)))
23467 /* If the option is deprecated, tell the user. */
23468 if (warn_on_deprecated && fopt->deprecated != NULL)
23469 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23470 arg ? arg : "", _(fopt->deprecated));
23472 if (fopt->var != NULL)
23473 *fopt->var = &fopt->value;
23479 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23481 /* These options are expected to have an argument. */
23482 if (c == lopt->option[0]
23484 && strncmp (arg, lopt->option + 1,
23485 strlen (lopt->option + 1)) == 0)
23487 /* If the option is deprecated, tell the user. */
23488 if (warn_on_deprecated && lopt->deprecated != NULL)
23489 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23490 _(lopt->deprecated));
23492 /* Call the sup-option parser. */
23493 return lopt->func (arg + strlen (lopt->option) - 1);
23504 md_show_usage (FILE * fp)
23506 struct arm_option_table *opt;
23507 struct arm_long_option_table *lopt;
23509 fprintf (fp, _(" ARM-specific assembler options:\n"));
23511 for (opt = arm_opts; opt->option != NULL; opt++)
23512 if (opt->help != NULL)
23513 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23515 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23516 if (lopt->help != NULL)
23517 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23521 -EB assemble code for a big-endian cpu\n"));
23526 -EL assemble code for a little-endian cpu\n"));
23530 --fix-v4bx Allow BX in ARMv4 code\n"));
23538 arm_feature_set flags;
23539 } cpu_arch_ver_table;
23541 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23542 least features first. */
23543 static const cpu_arch_ver_table cpu_arch_ver[] =
23549 {4, ARM_ARCH_V5TE},
23550 {5, ARM_ARCH_V5TEJ},
23554 {11, ARM_ARCH_V6M},
23555 {12, ARM_ARCH_V6SM},
23556 {8, ARM_ARCH_V6T2},
23557 {10, ARM_ARCH_V7A},
23558 {10, ARM_ARCH_V7R},
23559 {10, ARM_ARCH_V7M},
23563 /* Set an attribute if it has not already been set by the user. */
23565 aeabi_set_attribute_int (int tag, int value)
23568 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23569 || !attributes_set_explicitly[tag])
23570 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23574 aeabi_set_attribute_string (int tag, const char *value)
23577 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23578 || !attributes_set_explicitly[tag])
23579 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23582 /* Set the public EABI object attributes. */
23584 aeabi_set_public_attributes (void)
23588 arm_feature_set flags;
23589 arm_feature_set tmp;
23590 const cpu_arch_ver_table *p;
23592 /* Choose the architecture based on the capabilities of the requested cpu
23593 (if any) and/or the instructions actually used. */
23594 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23595 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23596 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23597 /*Allow the user to override the reported architecture. */
23600 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23601 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23604 /* We need to make sure that the attributes do not identify us as v6S-M
23605 when the only v6S-M feature in use is the Operating System Extensions. */
23606 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23607 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23608 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23612 for (p = cpu_arch_ver; p->val; p++)
23614 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23617 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23621 /* The table lookup above finds the last architecture to contribute
23622 a new feature. Unfortunately, Tag13 is a subset of the union of
23623 v6T2 and v7-M, so it is never seen as contributing a new feature.
23624 We can not search for the last entry which is entirely used,
23625 because if no CPU is specified we build up only those flags
23626 actually used. Perhaps we should separate out the specified
23627 and implicit cases. Avoid taking this path for -march=all by
23628 checking for contradictory v7-A / v7-M features. */
23630 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23631 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23632 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23635 /* Tag_CPU_name. */
23636 if (selected_cpu_name[0])
23640 q = selected_cpu_name;
23641 if (strncmp (q, "armv", 4) == 0)
23646 for (i = 0; q[i]; i++)
23647 q[i] = TOUPPER (q[i]);
23649 aeabi_set_attribute_string (Tag_CPU_name, q);
23652 /* Tag_CPU_arch. */
23653 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23655 /* Tag_CPU_arch_profile. */
23656 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23657 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23658 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23659 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23660 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23661 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23663 /* Tag_ARM_ISA_use. */
23664 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23666 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23668 /* Tag_THUMB_ISA_use. */
23669 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23671 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23672 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23674 /* Tag_VFP_arch. */
23675 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23676 aeabi_set_attribute_int (Tag_VFP_arch,
23677 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23679 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23680 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23681 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23682 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23683 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23684 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23685 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23686 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23687 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23689 /* Tag_ABI_HardFP_use. */
23690 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23691 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23692 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23694 /* Tag_WMMX_arch. */
23695 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23696 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23697 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23698 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23700 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23701 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23702 aeabi_set_attribute_int
23703 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23706 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23707 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23708 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23711 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23712 aeabi_set_attribute_int (Tag_DIV_use, 2);
23713 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23714 aeabi_set_attribute_int (Tag_DIV_use, 0);
23716 aeabi_set_attribute_int (Tag_DIV_use, 1);
23718 /* Tag_MP_extension_use. */
23719 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23720 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23722 /* Tag Virtualization_use. */
23723 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23725 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23728 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23731 /* Add the default contents for the .ARM.attributes section. */
23735 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23738 aeabi_set_public_attributes ();
23740 #endif /* OBJ_ELF */
23743 /* Parse a .cpu directive. */
23746 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23748 const struct arm_cpu_option_table *opt;
23752 name = input_line_pointer;
23753 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23754 input_line_pointer++;
23755 saved_char = *input_line_pointer;
23756 *input_line_pointer = 0;
23758 /* Skip the first "all" entry. */
23759 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23760 if (streq (opt->name, name))
23762 mcpu_cpu_opt = &opt->value;
23763 selected_cpu = opt->value;
23764 if (opt->canonical_name)
23765 strcpy (selected_cpu_name, opt->canonical_name);
23769 for (i = 0; opt->name[i]; i++)
23770 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23771 selected_cpu_name[i] = 0;
23773 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23774 *input_line_pointer = saved_char;
23775 demand_empty_rest_of_line ();
23778 as_bad (_("unknown cpu `%s'"), name);
23779 *input_line_pointer = saved_char;
23780 ignore_rest_of_line ();
23784 /* Parse a .arch directive. */
23787 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23789 const struct arm_arch_option_table *opt;
23793 name = input_line_pointer;
23794 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23795 input_line_pointer++;
23796 saved_char = *input_line_pointer;
23797 *input_line_pointer = 0;
23799 /* Skip the first "all" entry. */
23800 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23801 if (streq (opt->name, name))
23803 mcpu_cpu_opt = &opt->value;
23804 selected_cpu = opt->value;
23805 strcpy (selected_cpu_name, opt->name);
23806 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23807 *input_line_pointer = saved_char;
23808 demand_empty_rest_of_line ();
23812 as_bad (_("unknown architecture `%s'\n"), name);
23813 *input_line_pointer = saved_char;
23814 ignore_rest_of_line ();
23818 /* Parse a .object_arch directive. */
23821 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23823 const struct arm_arch_option_table *opt;
23827 name = input_line_pointer;
23828 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23829 input_line_pointer++;
23830 saved_char = *input_line_pointer;
23831 *input_line_pointer = 0;
23833 /* Skip the first "all" entry. */
23834 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23835 if (streq (opt->name, name))
23837 object_arch = &opt->value;
23838 *input_line_pointer = saved_char;
23839 demand_empty_rest_of_line ();
23843 as_bad (_("unknown architecture `%s'\n"), name);
23844 *input_line_pointer = saved_char;
23845 ignore_rest_of_line ();
23848 /* Parse a .arch_extension directive. */
23851 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23853 const struct arm_option_extension_value_table *opt;
23856 int adding_value = 1;
23858 name = input_line_pointer;
23859 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23860 input_line_pointer++;
23861 saved_char = *input_line_pointer;
23862 *input_line_pointer = 0;
23864 if (strlen (name) >= 2
23865 && strncmp (name, "no", 2) == 0)
23871 for (opt = arm_extensions; opt->name != NULL; opt++)
23872 if (streq (opt->name, name))
23874 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23876 as_bad (_("architectural extension `%s' is not allowed for the "
23877 "current base architecture"), name);
23882 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23884 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23886 mcpu_cpu_opt = &selected_cpu;
23887 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23888 *input_line_pointer = saved_char;
23889 demand_empty_rest_of_line ();
23893 if (opt->name == NULL)
23894 as_bad (_("unknown architecture `%s'\n"), name);
23896 *input_line_pointer = saved_char;
23897 ignore_rest_of_line ();
23900 /* Parse a .fpu directive. */
23903 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23905 const struct arm_option_fpu_value_table *opt;
23909 name = input_line_pointer;
23910 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23911 input_line_pointer++;
23912 saved_char = *input_line_pointer;
23913 *input_line_pointer = 0;
23915 for (opt = arm_fpus; opt->name != NULL; opt++)
23916 if (streq (opt->name, name))
23918 mfpu_opt = &opt->value;
23919 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23920 *input_line_pointer = saved_char;
23921 demand_empty_rest_of_line ();
23925 as_bad (_("unknown floating point format `%s'\n"), name);
23926 *input_line_pointer = saved_char;
23927 ignore_rest_of_line ();
23930 /* Copy symbol information. */
23933 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23935 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23939 /* Given a symbolic attribute NAME, return the proper integer value.
23940 Returns -1 if the attribute is not known. */
23943 arm_convert_symbolic_attribute (const char *name)
23945 static const struct
23950 attribute_table[] =
23952 /* When you modify this table you should
23953 also modify the list in doc/c-arm.texi. */
23954 #define T(tag) {#tag, tag}
23955 T (Tag_CPU_raw_name),
23958 T (Tag_CPU_arch_profile),
23959 T (Tag_ARM_ISA_use),
23960 T (Tag_THUMB_ISA_use),
23964 T (Tag_Advanced_SIMD_arch),
23965 T (Tag_PCS_config),
23966 T (Tag_ABI_PCS_R9_use),
23967 T (Tag_ABI_PCS_RW_data),
23968 T (Tag_ABI_PCS_RO_data),
23969 T (Tag_ABI_PCS_GOT_use),
23970 T (Tag_ABI_PCS_wchar_t),
23971 T (Tag_ABI_FP_rounding),
23972 T (Tag_ABI_FP_denormal),
23973 T (Tag_ABI_FP_exceptions),
23974 T (Tag_ABI_FP_user_exceptions),
23975 T (Tag_ABI_FP_number_model),
23976 T (Tag_ABI_align_needed),
23977 T (Tag_ABI_align8_needed),
23978 T (Tag_ABI_align_preserved),
23979 T (Tag_ABI_align8_preserved),
23980 T (Tag_ABI_enum_size),
23981 T (Tag_ABI_HardFP_use),
23982 T (Tag_ABI_VFP_args),
23983 T (Tag_ABI_WMMX_args),
23984 T (Tag_ABI_optimization_goals),
23985 T (Tag_ABI_FP_optimization_goals),
23986 T (Tag_compatibility),
23987 T (Tag_CPU_unaligned_access),
23988 T (Tag_FP_HP_extension),
23989 T (Tag_VFP_HP_extension),
23990 T (Tag_ABI_FP_16bit_format),
23991 T (Tag_MPextension_use),
23993 T (Tag_nodefaults),
23994 T (Tag_also_compatible_with),
23995 T (Tag_conformance),
23997 T (Tag_Virtualization_use),
23998 /* We deliberately do not include Tag_MPextension_use_legacy. */
24006 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24007 if (streq (name, attribute_table[i].name))
24008 return attribute_table[i].tag;
24014 /* Apply sym value for relocations only in the case that
24015 they are for local symbols and you have the respective
24016 architectural feature for blx and simple switches. */
24018 arm_apply_sym_value (struct fix * fixP)
24021 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24022 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24024 switch (fixP->fx_r_type)
24026 case BFD_RELOC_ARM_PCREL_BLX:
24027 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24028 if (ARM_IS_FUNC (fixP->fx_addsy))
24032 case BFD_RELOC_ARM_PCREL_CALL:
24033 case BFD_RELOC_THUMB_PCREL_BLX:
24034 if (THUMB_IS_FUNC (fixP->fx_addsy))
24045 #endif /* OBJ_ELF */