1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control * arm_ops_hsh;
729 static struct hash_control * arm_cond_hsh;
730 static struct hash_control * arm_shift_hsh;
731 static struct hash_control * arm_psr_hsh;
732 static struct hash_control * arm_v7m_psr_hsh;
733 static struct hash_control * arm_reg_hsh;
734 static struct hash_control * arm_reloc_hsh;
735 static struct hash_control * arm_barrier_opt_hsh;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS * last_label_seen;
747 static int label_is_thumb_function_name = FALSE;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals [MAX_LITERAL_POOL_SIZE];
756 unsigned int next_free_entry;
761 struct literal_pool * next;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool * list_of_pools = NULL;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it;
774 now_it_compatible (int cond)
776 return (cond & ~1) == (now_it.cc & ~1);
780 conditional_insn (void)
782 return inst.cond != COND_ALWAYS;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars[] = "#";
836 const char line_separator_chars[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str, char c)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS * sp)
877 if (symbol_get_value_expression (sp)->X_op == O_big)
880 if (symbol_get_value_expression (sp)->X_add_symbol)
882 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
883 || (symbol_get_value_expression (sp)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
890 static int in_my_get_expression = 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
913 case GE_NO_PREFIX: break;
915 if (!is_immediate_prefix (**str))
917 inst.error = _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG:
924 if (is_immediate_prefix (**str))
930 memset (ep, 0, sizeof (expressionS));
932 save_in = input_line_pointer;
933 input_line_pointer = *str;
934 in_my_get_expression = 1;
935 seg = expression (ep);
936 in_my_get_expression = 0;
938 if (ep->X_op == O_illegal || ep->X_op == O_absent)
940 /* We found a bad or missing expression in md_operand(). */
941 *str = input_line_pointer;
942 input_line_pointer = save_in;
943 if (inst.error == NULL)
944 inst.error = (ep->X_op == O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg != absolute_section
951 && seg != text_section
952 && seg != data_section
953 && seg != bss_section
954 && seg != undefined_section)
956 inst.error = _("bad segment");
957 *str = input_line_pointer;
958 input_line_pointer = save_in;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode != GE_OPT_PREFIX_BIG
969 && (ep->X_op == O_big
971 && (walk_no_bignums (ep->X_add_symbol)
973 && walk_no_bignums (ep->X_op_symbol))))))
975 inst.error = _("invalid constant");
976 *str = input_line_pointer;
977 input_line_pointer = save_in;
981 *str = input_line_pointer;
982 input_line_pointer = save_in;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type, char * litP, int * sizeP)
1004 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t = atof_ieee (input_line_pointer, type, words);
1041 input_line_pointer = t;
1042 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1044 if (target_big_endian)
1046 for (i = 0; i < prec; i++)
1048 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1049 litP += sizeof (LITTLENUM_TYPE);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1055 for (i = prec - 1; i >= 0; i--)
1057 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1058 litP += sizeof (LITTLENUM_TYPE);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i = 0; i < prec; i += 2)
1065 md_number_to_chars (litP, (valueT) words[i + 1],
1066 sizeof (LITTLENUM_TYPE));
1067 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1068 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1069 litP += 2 * sizeof (LITTLENUM_TYPE);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS * exp)
1081 if (in_my_get_expression)
1082 exp->X_op = O_illegal;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val)
1095 exp.X_op = O_illegal;
1097 if (is_immediate_prefix (*input_line_pointer))
1099 input_line_pointer++;
1103 if (exp.X_op != O_constant)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val = exp.X_add_number;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry *
1122 arm_reg_parse_multi (char **ccp)
1126 struct reg_entry *reg;
1128 #ifdef REGISTER_PREFIX
1129 if (*start != REGISTER_PREFIX)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start == OPTIONAL_REGISTER_PREFIX)
1139 if (!ISALPHA (*p) || !is_name_beginner (*p))
1144 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1146 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1156 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1157 enum arm_reg_type type)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg && reg->type == REG_TYPE_CN)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor = strtoul (start, ccp, 10);
1175 if (*ccp != start && processor <= 15)
1179 case REG_TYPE_MMXWC:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg && reg->type == REG_TYPE_MMXWCG)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp, enum arm_reg_type type)
1200 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1207 if (reg && reg->type == type)
1210 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type *type, char **str)
1239 while (type->elems < NEON_MAX_TYPE_ELS)
1241 enum neon_el_type thistype = NT_untyped;
1242 unsigned thissize = -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr))
1255 case 'i': thistype = NT_integer; break;
1256 case 'f': thistype = NT_float; break;
1257 case 'p': thistype = NT_poly; break;
1258 case 's': thistype = NT_signed; break;
1259 case 'u': thistype = NT_unsigned; break;
1261 thistype = NT_float;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype == NT_float && !ISDIGIT (*ptr))
1278 thissize = strtoul (ptr, &ptr, 10);
1280 if (thissize != 8 && thissize != 16 && thissize != 32
1283 as_bad (_("bad size %d in type specifier"), thissize);
1291 type->el[type->elems].type = thistype;
1292 type->el[type->elems].size = thissize;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type->elems == 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1323 struct neon_type optype;
1327 if (parse_neon_type (&optype, &str) == SUCCESS)
1329 if (optype.elems == 1)
1330 *vectype = optype.el[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1364 enum arm_reg_type *rtype,
1365 struct neon_typed_alias *typeinfo)
1368 struct reg_entry *reg = arm_reg_parse_multi (&str);
1369 struct neon_typed_alias atype;
1370 struct neon_type_el parsetype;
1374 atype.eltype.type = NT_invtype;
1375 atype.eltype.size = -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type == REG_TYPE_NDQ
1391 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1392 || (type == REG_TYPE_VFSD
1393 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1394 || (type == REG_TYPE_NSDQ
1395 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1396 || reg->type == REG_TYPE_NQ))
1397 || (type == REG_TYPE_MMXWC
1398 && (reg->type == REG_TYPE_MMXWCG)))
1399 type = (enum arm_reg_type) reg->type;
1401 if (type != reg->type)
1407 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1409 if ((atype.defined & NTA_HASTYPE) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype.defined |= NTA_HASTYPE;
1415 atype.eltype = parsetype;
1418 if (skip_past_char (&str, '[') == SUCCESS)
1420 if (type != REG_TYPE_VFD)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype.defined & NTA_HASINDEX) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype.defined |= NTA_HASINDEX;
1434 if (skip_past_char (&str, ']') == SUCCESS)
1435 atype.index = NEON_ALL_LANES;
1440 my_get_expression (&exp, &str, GE_NO_PREFIX);
1442 if (exp.X_op != O_constant)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str, ']') == FAIL)
1451 atype.index = exp.X_add_number;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1475 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1477 struct neon_typed_alias atype;
1479 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype.defined & NTA_HASINDEX) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype = atype.eltype;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1515 struct neon_typed_alias atype;
1517 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1519 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1522 if (atype.index == NEON_ALL_LANES)
1524 first_error (_("scalar must have an index"));
1527 else if (atype.index >= 64 / elsize)
1529 first_error (_("scalar index out of range"));
1534 *type = atype.eltype;
1538 return reg * 16 + atype.index;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp)
1546 char * str = * strp;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1567 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1577 first_error (_("bad range in register list"));
1581 for (i = cur_reg + 1; i < reg; i++)
1583 if (range & (1 << i))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range & (1 << reg))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg <= cur_reg)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str) != FAIL
1603 || (in_range = 1, *str++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1619 if (exp.X_op == O_constant)
1621 if (exp.X_add_number
1622 != (exp.X_add_number & 0x0000ffff))
1624 inst.error = _("invalid register mask");
1628 if ((range & exp.X_add_number) != 0)
1630 int regno = range & exp.X_add_number;
1633 regno = (1 << regno) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range |= exp.X_add_number;
1643 if (inst.reloc.type != 0)
1645 inst.error = _("expression too complex");
1649 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1650 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1651 inst.reloc.pc_rel = 0;
1655 if (*str == '|' || *str == '+')
1661 while (another_range);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1697 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1701 unsigned long mask = 0;
1706 inst.error = _("expecting {");
1715 regtype = REG_TYPE_VFS;
1720 regtype = REG_TYPE_VFD;
1723 case REGLIST_NEON_D:
1724 regtype = REG_TYPE_NDQ;
1728 if (etype != REGLIST_VFP_S)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1745 base_reg = max_regs;
1749 int setmask = 1, addregs = 1;
1751 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1753 if (new_base == FAIL)
1755 first_error (_(reg_expected_msgs[regtype]));
1759 if (new_base >= max_regs)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype == REG_TYPE_NQ)
1772 if (new_base < base_reg)
1773 base_reg = new_base;
1775 if (mask & (setmask << new_base))
1777 first_error (_("invalid register list"));
1781 if ((mask >> new_base) != 0 && ! warned)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask |= setmask << new_base;
1790 if (*str == '-') /* We have the start of a range expression */
1796 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1799 inst.error = gettext (reg_expected_msgs[regtype]);
1803 if (high_range >= max_regs)
1805 first_error (_("register out of range in list"));
1809 if (regtype == REG_TYPE_NQ)
1810 high_range = high_range + 1;
1812 if (high_range <= new_base)
1814 inst.error = _("register range not in ascending order");
1818 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1820 if (mask & (setmask << new_base))
1822 inst.error = _("invalid register list");
1826 mask |= setmask << new_base;
1831 while (skip_past_comma (&str) != FAIL);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count == 0 || count > max_regs)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i = 0; i < count; i++)
1845 if ((mask & (1u << i)) == 0)
1847 inst.error = _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1868 if (a->defined != b->defined)
1871 if ((a->defined & NTA_HASTYPE) != 0
1872 && (a->eltype.type != b->eltype.type
1873 || a->eltype.size != b->eltype.size))
1876 if ((a->defined & NTA_HASINDEX) != 0
1877 && (a->index != b->index))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str, unsigned *pbase,
1897 struct neon_type_el *eltype)
1904 int leading_brace = 0;
1905 enum arm_reg_type rtype = REG_TYPE_NDQ;
1906 const char *const incr_error = _("register stride must be 1 or 2");
1907 const char *const type_error = _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype;
1910 if (skip_past_char (&ptr, '{') == SUCCESS)
1915 struct neon_typed_alias atype;
1916 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1920 first_error (_(reg_expected_msgs[rtype]));
1927 if (rtype == REG_TYPE_NQ)
1933 else if (reg_incr == -1)
1935 reg_incr = getreg - base_reg;
1936 if (reg_incr < 1 || reg_incr > 2)
1938 first_error (_(incr_error));
1942 else if (getreg != base_reg + reg_incr * count)
1944 first_error (_(incr_error));
1948 if (! neon_alias_types_same (&atype, &firsttype))
1950 first_error (_(type_error));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype;
1959 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1961 lane = NEON_INTERLEAVE_LANES;
1962 else if (lane != NEON_INTERLEAVE_LANES)
1964 first_error (_(type_error));
1969 else if (reg_incr != 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1978 first_error (_(reg_expected_msgs[rtype]));
1981 if (! neon_alias_types_same (&htype, &firsttype))
1983 first_error (_(type_error));
1986 count += hireg + dregs - getreg;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype == REG_TYPE_NQ)
1997 if ((atype.defined & NTA_HASINDEX) != 0)
2001 else if (lane != atype.index)
2003 first_error (_(type_error));
2007 else if (lane == -1)
2008 lane = NEON_INTERLEAVE_LANES;
2009 else if (lane != NEON_INTERLEAVE_LANES)
2011 first_error (_(type_error));
2016 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane = NEON_INTERLEAVE_LANES;
2023 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2024 || (count > 1 && reg_incr == -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2032 first_error (_("expected }"));
2040 *eltype = firsttype.eltype;
2045 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str)
2056 struct reloc_entry *r;
2060 return BFD_RELOC_UNUSED;
2065 while (*q && *q != ')' && *q != ',')
2070 if ((r = (struct reloc_entry *)
2071 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2078 /* Directives: register aliases. */
2080 static struct reg_entry *
2081 insert_reg_alias (char *str, unsigned number, int type)
2083 struct reg_entry *new_reg;
2086 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2088 if (new_reg->builtin)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg->number != number || new_reg->type != type)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2099 name = xstrdup (str);
2100 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2102 new_reg->name = name;
2103 new_reg->number = number;
2104 new_reg->type = type;
2105 new_reg->builtin = FALSE;
2106 new_reg->neon = NULL;
2108 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2115 insert_neon_reg_alias (char *str, int number, int type,
2116 struct neon_typed_alias *atype)
2118 struct reg_entry *reg = insert_reg_alias (str, number, type);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg->neon = (struct neon_typed_alias *)
2129 xmalloc (sizeof (struct neon_typed_alias));
2130 *reg->neon = *atype;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname, char *p)
2144 struct reg_entry *old;
2145 char *oldname, *nbuf;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname, " .req ", 6) != 0)
2155 if (*oldname == '\0')
2158 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname = original_case_string;
2172 nlen = strlen (newname);
2175 nbuf = (char *) alloca (nlen + 1);
2176 memcpy (nbuf, newname, nlen);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2184 for (p = nbuf; *p; p++)
2187 if (strncmp (nbuf, newname, nlen))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2202 for (p = nbuf; *p; p++)
2205 if (strncmp (nbuf, newname, nlen))
2206 insert_reg_alias (nbuf, old->number, old->type);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname, char *p)
2225 enum arm_reg_type basetype;
2226 struct reg_entry *basereg;
2227 struct reg_entry mybasereg;
2228 struct neon_type ntype;
2229 struct neon_typed_alias typeinfo;
2230 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2233 typeinfo.defined = 0;
2234 typeinfo.eltype.type = NT_invtype;
2235 typeinfo.eltype.size = -1;
2236 typeinfo.index = -1;
2240 if (strncmp (p, " .dn ", 5) == 0)
2241 basetype = REG_TYPE_VFD;
2242 else if (strncmp (p, " .qn ", 5) == 0)
2243 basetype = REG_TYPE_NQ;
2252 basereg = arm_reg_parse_multi (&p);
2254 if (basereg && basereg->type != basetype)
2256 as_bad (_("bad type for register"));
2260 if (basereg == NULL)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp, &p, GE_NO_PREFIX);
2265 if (exp.X_op != O_constant)
2267 as_bad (_("expression must be constant"));
2270 basereg = &mybasereg;
2271 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2277 typeinfo = *basereg->neon;
2279 if (parse_neon_type (&ntype, &p) == SUCCESS)
2281 /* We got a type. */
2282 if (typeinfo.defined & NTA_HASTYPE)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo.defined |= NTA_HASTYPE;
2289 if (ntype.elems != 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo.eltype = ntype.el[0];
2297 if (skip_past_char (&p, '[') == SUCCESS)
2300 /* We got a scalar index. */
2302 if (typeinfo.defined & NTA_HASINDEX)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp, &p, GE_NO_PREFIX);
2310 if (exp.X_op != O_constant)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo.defined |= NTA_HASINDEX;
2317 typeinfo.index = exp.X_add_number;
2319 if (skip_past_char (&p, ']') == FAIL)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen = nameend - newname;
2332 newname = original_case_string;
2333 namelen = strlen (newname);
2336 namebuf = (char *) alloca (namelen + 1);
2337 strncpy (namebuf, newname, namelen);
2338 namebuf[namelen] = '\0';
2340 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2341 typeinfo.defined != 0 ? &typeinfo : NULL);
2343 /* Insert name in all uppercase. */
2344 for (p = namebuf; *p; p++)
2347 if (strncmp (namebuf, newname, namelen))
2348 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2349 typeinfo.defined != 0 ? &typeinfo : NULL);
2351 /* Insert name in all lowercase. */
2352 for (p = namebuf; *p; p++)
2355 if (strncmp (namebuf, newname, namelen))
2356 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2357 typeinfo.defined != 0 ? &typeinfo : NULL);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED)
2395 name = input_line_pointer;
2397 while (*input_line_pointer != 0
2398 && *input_line_pointer != ' '
2399 && *input_line_pointer != '\n')
2400 ++input_line_pointer;
2402 saved_char = *input_line_pointer;
2403 *input_line_pointer = 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2413 as_bad (_("unknown register alias '%s'"), name);
2414 else if (reg->builtin)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh, name, FALSE);
2423 free ((char *) reg->name);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf = strdup (name);
2433 for (p = nbuf; *p; p++)
2435 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2438 hash_delete (arm_reg_hsh, nbuf, FALSE);
2439 free ((char *) reg->name);
2445 for (p = nbuf; *p; p++)
2447 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2450 hash_delete (arm_reg_hsh, nbuf, FALSE);
2451 free ((char *) reg->name);
2461 *input_line_pointer = saved_char;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2479 const char * symname;
2486 type = BSF_NO_FLAGS;
2490 type = BSF_NO_FLAGS;
2494 type = BSF_NO_FLAGS;
2500 symbolP = symbol_new (symname, now_seg, value, frag);
2501 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2506 THUMB_SET_FUNC (symbolP, 0);
2507 ARM_SET_THUMB (symbolP, 0);
2508 ARM_SET_INTERWORK (symbolP, support_interwork);
2512 THUMB_SET_FUNC (symbolP, 1);
2513 ARM_SET_THUMB (symbolP, 1);
2514 ARM_SET_INTERWORK (symbolP, support_interwork);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag->tc_frag_data.first_map != NULL)
2535 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2536 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2538 frag->tc_frag_data.first_map = symbolP;
2540 if (frag->tc_frag_data.last_map != NULL)
2542 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2543 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2544 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2546 frag->tc_frag_data.last_map = symbolP;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state,
2555 valueT value, fragS *frag, offsetT bytes)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag->tc_frag_data.last_map != NULL
2559 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2561 symbolS *symp = frag->tc_frag_data.last_map;
2565 know (frag->tc_frag_data.first_map == symp);
2566 frag->tc_frag_data.first_map = NULL;
2568 frag->tc_frag_data.last_map = NULL;
2569 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2572 make_mapping_symbol (MAP_DATA, value, frag);
2573 make_mapping_symbol (state, value + bytes, frag);
2576 static void mapping_state_2 (enum mstate state, int max_chars);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state)
2584 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate == state)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2596 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2603 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2609 mapping_state_2 (state, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state, int max_chars)
2619 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2621 if (!SEG_NORMAL (now_seg))
2624 if (mapstate == state)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2630 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS * symbolP)
2644 const char * name = S_GET_NAME (symbolP);
2645 symbolS * new_target;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2661 real_start = ACONCAT ((STUB_NAME, name, NULL));
2662 new_target = symbol_find (real_start);
2664 if (new_target == NULL)
2666 as_warn (_("Failed to find real start of function: %s\n"), name);
2667 new_target = symbolP;
2675 opcode_select (int width)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width);
2713 s_arm (int ignore ATTRIBUTE_UNUSED)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED)
2731 temp = get_absolute_expression ();
2736 opcode_select (temp);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name = TRUE;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name = input_line_pointer;
2789 delim = get_symbol_end ();
2790 end_name = input_line_pointer;
2793 if (*input_line_pointer != ',')
2796 as_bad (_("expected comma after name \"%s\""), name);
2798 ignore_rest_of_line ();
2802 input_line_pointer++;
2805 if (name[0] == '.' && name[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP = symbol_find (name)) == NULL
2812 && (symbolP = md_undefined_symbol (name)) == NULL)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing & LISTING_SYMBOLS)
2820 extern struct list_info_struct * listing_tail;
2821 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2823 memset (dummy_frag, 0, sizeof (fragS));
2824 dummy_frag->fr_type = rs_fill;
2825 dummy_frag->line = listing_tail;
2826 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2827 dummy_frag->fr_symbol = symbolP;
2831 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP);
2844 && S_IS_DEFINED (symbolP)
2845 && S_GET_SEGMENT (symbolP) != reg_section)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2848 pseudo_set (symbolP);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP, 1);
2855 ARM_SET_THUMB (symbolP, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP, support_interwork);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED)
2871 name = input_line_pointer;
2872 delim = get_symbol_end ();
2874 if (!strcasecmp (name, "unified"))
2875 unified_syntax = TRUE;
2876 else if (!strcasecmp (name, "divided"))
2877 unified_syntax = FALSE;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name);
2883 *input_line_pointer = delim;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED)
2897 long max_alignment = 15;
2899 temp = get_absolute_expression ();
2900 if (temp > max_alignment)
2901 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer == ',')
2910 input_line_pointer++;
2911 temp_fill = get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp && !need_pass_2)
2926 if (!fill_p && subseg_text_p (now_seg))
2927 frag_align_code (temp, 0);
2929 frag_align (temp, (int) temp_fill, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg, temp);
2937 s_bss (int ignore ATTRIBUTE_UNUSED)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool *
2964 find_literal_pool (void)
2966 literal_pool * pool;
2968 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2970 if (pool->section == now_seg
2971 && pool->sub_section == now_subseg)
2978 static literal_pool *
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num = 1;
2983 literal_pool * pool;
2985 pool = find_literal_pool ();
2989 /* Create a new pool. */
2990 pool = (literal_pool *) xmalloc (sizeof (* pool));
2994 pool->next_free_entry = 0;
2995 pool->section = now_seg;
2996 pool->sub_section = now_subseg;
2997 pool->next = list_of_pools;
2998 pool->symbol = NULL;
3000 /* Add it to the list. */
3001 list_of_pools = pool;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool->symbol == NULL)
3007 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3008 (valueT) 0, &zero_address_frag);
3009 pool->id = latest_pool_num ++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool * pool;
3025 pool = find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry = 0; entry < pool->next_free_entry; entry ++)
3030 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3031 && (inst.reloc.exp.X_op == O_constant)
3032 && (pool->literals[entry].X_add_number
3033 == inst.reloc.exp.X_add_number)
3034 && (pool->literals[entry].X_unsigned
3035 == inst.reloc.exp.X_unsigned))
3038 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3039 && (inst.reloc.exp.X_op == O_symbol)
3040 && (pool->literals[entry].X_add_number
3041 == inst.reloc.exp.X_add_number)
3042 && (pool->literals[entry].X_add_symbol
3043 == inst.reloc.exp.X_add_symbol)
3044 && (pool->literals[entry].X_op_symbol
3045 == inst.reloc.exp.X_op_symbol))
3049 /* Do we need to create a new entry? */
3050 if (entry == pool->next_free_entry)
3052 if (entry >= MAX_LITERAL_POOL_SIZE)
3054 inst.error = _("literal pool overflow");
3058 pool->literals[entry] = inst.reloc.exp;
3059 pool->next_free_entry += 1;
3062 inst.reloc.exp.X_op = O_symbol;
3063 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3064 inst.reloc.exp.X_add_symbol = pool->symbol;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS * symbolP,
3074 const char * name, /* It is copied, the caller can modify. */
3075 segT segment, /* Segment identifier (SEG_<something>). */
3076 valueT valu, /* Symbol value. */
3077 fragS * frag) /* Associated fragment. */
3079 unsigned int name_length;
3080 char * preserved_copy_of_name;
3082 name_length = strlen (name) + 1; /* +1 for \0. */
3083 obstack_grow (¬es, name, name_length);
3084 preserved_copy_of_name = (char *) obstack_finish (¬es);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name =
3088 tc_canonicalize_symbol_name (preserved_copy_of_name);
3091 S_SET_NAME (symbolP, preserved_copy_of_name);
3093 S_SET_SEGMENT (symbolP, segment);
3094 S_SET_VALUE (symbolP, valu);
3095 symbol_clear_list_pointers (symbolP);
3097 symbol_set_frag (symbolP, frag);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen;
3103 if (symbol_table_frozen)
3107 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3109 obj_symbol_new_hook (symbolP);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP);
3116 verify_symbol_chain (symbol_rootP, symbol_lastP);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3125 literal_pool * pool;
3128 pool = find_literal_pool ();
3130 || pool->symbol == NULL
3131 || pool->next_free_entry == 0)
3134 mapping_state (MAP_DATA);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg, 2);
3143 sprintf (sym_name, "$$lit_\002%x", pool->id);
3145 symbol_locate (pool->symbol, sym_name, now_seg,
3146 (valueT) frag_now_fix (), frag_now);
3147 symbol_table_insert (pool->symbol);
3149 ARM_SET_THUMB (pool->symbol, thumb_mode);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3155 for (entry = 0; entry < pool->next_free_entry; entry ++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool->literals[entry]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool->next_free_entry = 0;
3161 pool->symbol = NULL;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3168 static valueT create_unwind_entry (int);
3169 static void start_unwind_section (const segT, int);
3170 static void add_unwind_opcode (valueT, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes);
3194 mapping_state (MAP_DATA);
3198 char *base = input_line_pointer;
3202 if (exp.X_op != O_symbol)
3203 emit_expr (&exp, (unsigned int) nbytes);
3206 char *before_reloc = input_line_pointer;
3207 reloc = parse_reloc (&input_line_pointer);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc == BFD_RELOC_UNUSED)
3215 emit_expr (&exp, (unsigned int) nbytes);
3218 reloc_howto_type *howto = (reloc_howto_type *)
3219 bfd_reloc_type_lookup (stdoutput,
3220 (bfd_reloc_code_real_type) reloc);
3221 int size = bfd_get_reloc_size (howto);
3223 if (reloc == BFD_RELOC_ARM_PLT32)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc = BFD_RELOC_UNUSED;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto->name, nbytes);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p = input_line_pointer;
3241 char *save_buf = (char *) alloca (input_line_pointer - base);
3242 memcpy (save_buf, base, input_line_pointer - base);
3243 memmove (base + (input_line_pointer - before_reloc),
3244 base, before_reloc - base);
3246 input_line_pointer = base + (input_line_pointer-before_reloc);
3248 memcpy (base, save_buf, p - base);
3250 offset = nbytes - size;
3251 p = frag_more ((int) nbytes);
3252 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3253 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3258 while (*input_line_pointer++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer --;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS * exp)
3271 expressionS exp_high = *exp;
3273 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3274 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3275 exp->X_add_number &= 0xffff;
3276 emit_expr (exp, (unsigned int) THUMB_SIZE);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode)
3284 if ((unsigned int) opcode < 0xe800u)
3286 else if ((unsigned int) opcode >= 0xe8000000u)
3293 emit_insn (expressionS *exp, int nbytes)
3297 if (exp->X_op == O_constant)
3302 size = thumb_insn_size (exp->X_add_number);
3306 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it.state == AUTOMATIC_IT_BLOCK)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3319 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3320 emit_thumb32_expr (exp);
3322 emit_expr (exp, (unsigned int) size);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM);
3374 if (! emit_insn (& exp, nbytes))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer --;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3397 if (*input_line_pointer == '1')
3398 highbit = 0x80000000;
3399 else if (*input_line_pointer != '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer++;
3403 if (*input_line_pointer != ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA);
3420 md_number_to_chars (p, highbit, 4);
3421 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3422 BFD_RELOC_ARM_PREL31);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3434 demand_empty_rest_of_line ();
3435 if (unwind.proc_start)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind.proc_start = expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind.opcode_count = 0;
3446 unwind.table_entry = NULL;
3447 unwind.personality_routine = NULL;
3448 unwind.personality_index = -1;
3449 unwind.frame_size = 0;
3450 unwind.fp_offset = 0;
3451 unwind.fp_reg = REG_SP;
3453 unwind.sp_restored = 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3463 demand_empty_rest_of_line ();
3464 if (!unwind.proc_start)
3465 as_bad (MISSING_FNSTART);
3467 if (unwind.table_entry)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3481 unsigned int marked_pr_dependency;
3483 demand_empty_rest_of_line ();
3485 if (!unwind.proc_start)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind.table_entry == NULL)
3493 val = create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind.saved_seg, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg, 2);
3502 ptr = frag_more (8);
3503 where = frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3507 BFD_RELOC_ARM_PREL31);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3513 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3514 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3516 static const char *const name[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3523 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3524 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3525 |= 1 << unwind.personality_index;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr + 4, val, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3534 BFD_RELOC_ARM_PREL31);
3536 /* Restore the original section. */
3537 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3539 unwind.proc_start = NULL;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3548 demand_empty_rest_of_line ();
3549 if (!unwind.proc_start)
3550 as_bad (MISSING_FNSTART);
3552 if (unwind.personality_routine || unwind.personality_index != -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind.personality_index = -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3566 if (!unwind.proc_start)
3567 as_bad (MISSING_FNSTART);
3569 if (unwind.personality_routine || unwind.personality_index != -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp.X_op != O_constant
3575 || exp.X_add_number < 0 || exp.X_add_number > 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind.personality_index = exp.X_add_number;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3595 if (!unwind.proc_start)
3596 as_bad (MISSING_FNSTART);
3598 if (unwind.personality_routine || unwind.personality_index != -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name = input_line_pointer;
3602 c = get_symbol_end ();
3603 p = input_line_pointer;
3604 unwind.personality_routine = symbol_find_or_make (name);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range = parse_reg_list (&input_line_pointer);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind.sp_restored && unwind.fp_reg == 12
3633 && (range & 0x3000) == 0x1000)
3635 unwind.opcode_count--;
3636 unwind.sp_restored = 0;
3637 range = (range | 0x2000) & ~0x1000;
3638 unwind.pending_offset = 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n = 0; n < 8; n++)
3648 /* Break at the first non-saved register. */
3649 if ((range & (1 << (n + 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op = 0x8000 | ((range >> 4) & 0xfff);
3657 add_unwind_opcode (op, 2);
3661 /* Use the short form. */
3663 op = 0xa8; /* Pop r14. */
3665 op = 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op, 1);
3674 op = 0xb100 | (range & 0xf);
3675 add_unwind_opcode (op, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n = 0; n < 16; n++)
3681 if (range & (1 << n))
3682 unwind.frame_size += 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer) != FAIL)
3700 exp.X_op = O_illegal;
3702 if (exp.X_op != O_constant)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs = exp.X_add_number;
3711 if (num_regs < 1 || num_regs > 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op = 0xb4 | (num_regs - 1);
3724 add_unwind_opcode (op, 1);
3729 op = 0xc800 | (reg << 4) | (num_regs - 1);
3730 add_unwind_opcode (op, 2);
3732 unwind.frame_size += num_regs * 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs = 0;
3745 int num_regs_below_16;
3747 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs = count;
3763 else if (start + count > 16)
3764 num_vfpv3_regs = start + count - 16;
3766 if (num_vfpv3_regs > 0)
3768 int start_offset = start > 16 ? start - 16 : 0;
3769 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3770 add_unwind_opcode (op, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3775 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3776 if (num_regs_below_16 > 0)
3778 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3779 add_unwind_opcode (op, 2);
3782 unwind.frame_size += count * 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op = 0xb8 | (count - 1);
3809 add_unwind_opcode (op, 1);
3814 op = 0xb300 | (reg << 4) | (count - 1);
3815 add_unwind_opcode (op, 2);
3817 unwind.frame_size += count * 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer == '{')
3833 input_line_pointer++;
3837 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3841 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer == '-')
3851 input_line_pointer++;
3852 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3855 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3858 else if (reg >= hi_reg)
3860 as_bad (_("bad register range"));
3863 for (; reg < hi_reg; reg++)
3867 while (skip_past_comma (&input_line_pointer) != FAIL);
3869 if (*input_line_pointer == '}')
3870 input_line_pointer++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i = 0; i < 16; i++)
3880 if (mask & (1 << i))
3881 unwind.frame_size += 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind.opcode_count > 0)
3889 i = unwind.opcodes[unwind.opcode_count - 1];
3890 if ((i & 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask & 0xfe00) == (1 << 9))
3898 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3899 unwind.opcode_count--;
3902 else if (i == 6 && unwind.opcode_count >= 2)
3904 i = unwind.opcodes[unwind.opcode_count - 2];
3908 op = 0xffff << (reg - 1);
3910 && ((mask & op) == (1u << (reg - 1))))
3912 op = (1 << (reg + i + 1)) - 1;
3913 op &= ~((1 << reg) - 1);
3915 unwind.opcode_count -= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg = 15; reg >= -1; reg--)
3926 /* Save registers in blocks. */
3928 || !(mask & (1 << reg)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op = 0xc0 | (hi_reg - 10);
3938 add_unwind_opcode (op, 1);
3943 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3944 add_unwind_opcode (op, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer == '{')
3965 input_line_pointer++;
3969 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3973 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer == '-')
3984 input_line_pointer++;
3985 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3988 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
3991 else if (reg >= hi_reg)
3993 as_bad (_("bad register range"));
3996 for (; reg < hi_reg; reg++)
4000 while (skip_past_comma (&input_line_pointer) != FAIL);
4002 if (*input_line_pointer == '}')
4003 input_line_pointer++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg = 0; reg < 16; reg++)
4013 if (mask & (1 << reg))
4014 unwind.frame_size += 4;
4017 add_unwind_opcode (op, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6)
4031 struct reg_entry *reg;
4032 bfd_boolean had_brace = FALSE;
4034 if (!unwind.proc_start)
4035 as_bad (MISSING_FNSTART);
4037 /* Figure out what sort of save we have. */
4038 peek = input_line_pointer;
4046 reg = arm_reg_parse_multi (&peek);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer = peek;
4065 s_arm_unwind_save_fpa (reg->number);
4068 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4094 if (!unwind.proc_start)
4095 as_bad (MISSING_FNSTART);
4097 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4100 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer) != FAIL)
4108 if (immediate_for_directive (&offset) == FAIL)
4114 demand_empty_rest_of_line ();
4116 if (reg == REG_SP || reg == REG_PC)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind.fp_reg != REG_SP)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op, 1);
4129 /* Record the information for later. */
4130 unwind.fp_reg = reg;
4131 unwind.fp_offset = unwind.frame_size - offset;
4132 unwind.sp_restored = 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4142 if (!unwind.proc_start)
4143 as_bad (MISSING_FNSTART);
4145 if (immediate_for_directive (&offset) == FAIL)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind.frame_size += offset;
4157 unwind.pending_offset += offset;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4171 if (!unwind.proc_start)
4172 as_bad (MISSING_FNSTART);
4174 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4175 if (skip_past_comma (&input_line_pointer) == FAIL)
4178 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4180 if (fp_reg == FAIL || sp_reg == FAIL)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer) != FAIL)
4190 if (immediate_for_directive (&offset) == FAIL)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind.fp_reg = fp_reg;
4208 if (sp_reg == REG_SP)
4209 unwind.fp_offset = unwind.frame_size - offset;
4211 unwind.fp_offset -= offset;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4220 /* This is an arbitrary limit. */
4221 unsigned char op[16];
4224 if (!unwind.proc_start)
4225 as_bad (MISSING_FNSTART);
4228 if (exp.X_op == O_constant
4229 && skip_past_comma (&input_line_pointer) != FAIL)
4231 unwind.frame_size += exp.X_add_number;
4235 exp.X_op = O_illegal;
4237 if (exp.X_op != O_constant)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op[count++] = exp.X_add_number;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer) == FAIL)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op[count], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4282 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4284 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4285 attributes_set_explicitly[tag] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p = obstack_next_free (&frchain_now->frch_obstack);
4307 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4308 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4329 if (exp.X_op == O_symbol)
4330 exp.X_op = O_secrel;
4332 emit_expr (&exp, 4);
4334 while (*input_line_pointer++ == ',');
4336 input_line_pointer--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq, 0 },
4355 { "bss", s_bss, 0 },
4356 { "align", s_align, 0 },
4357 { "arm", s_arm, 0 },
4358 { "thumb", s_thumb, 0 },
4359 { "code", s_code, 0 },
4360 { "force_thumb", s_force_thumb, 0 },
4361 { "thumb_func", s_thumb_func, 0 },
4362 { "thumb_set", s_thumb_set, 0 },
4363 { "even", s_even, 0 },
4364 { "ltorg", s_ltorg, 0 },
4365 { "pool", s_ltorg, 0 },
4366 { "syntax", s_syntax, 0 },
4367 { "cpu", s_arm_cpu, 0 },
4368 { "arch", s_arm_arch, 0 },
4369 { "object_arch", s_arm_object_arch, 0 },
4370 { "fpu", s_arm_fpu, 0 },
4371 { "arch_extension", s_arm_arch_extension, 0 },
4373 { "word", s_arm_elf_cons, 4 },
4374 { "long", s_arm_elf_cons, 4 },
4375 { "inst.n", s_arm_elf_inst, 2 },
4376 { "inst.w", s_arm_elf_inst, 4 },
4377 { "inst", s_arm_elf_inst, 0 },
4378 { "rel31", s_arm_rel31, 0 },
4379 { "fnstart", s_arm_unwind_fnstart, 0 },
4380 { "fnend", s_arm_unwind_fnend, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4382 { "personality", s_arm_unwind_personality, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4385 { "save", s_arm_unwind_save, 0 },
4386 { "vsave", s_arm_unwind_save, 1 },
4387 { "movsp", s_arm_unwind_movsp, 0 },
4388 { "pad", s_arm_unwind_pad, 0 },
4389 { "setfp", s_arm_unwind_setfp, 0 },
4390 { "unwind_raw", s_arm_unwind_raw, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4402 { "loc", dwarf2_directive_loc, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4405 { "extend", float_cons, 'x' },
4406 { "ldouble", float_cons, 'x' },
4407 { "packed", float_cons, 'p' },
4409 {"secrel32", pe_directive_secrel, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str, int *val, int min, int max,
4424 bfd_boolean prefix_opt)
4427 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4428 if (exp.X_op != O_constant)
4430 inst.error = _("constant expression required");
4434 if (exp.X_add_number < min || exp.X_add_number > max)
4436 inst.error = _("immediate value out of range");
4440 *val = exp.X_add_number;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str, int i)
4454 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4456 if (exp.X_op == O_constant)
4458 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4466 inst.operands[i].regisimm = 1;
4469 else if (exp.X_op == O_big
4470 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4472 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts != 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4485 LITTLENUM_TYPE m = -1;
4487 if (generic_bignum[parts * 2] != 0
4488 && generic_bignum[parts * 2] != m)
4491 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4492 if (generic_bignum[j] != generic_bignum[j-1])
4496 inst.operands[i].imm = 0;
4497 for (j = 0; j < parts; j++, idx++)
4498 inst.operands[i].imm |= generic_bignum[idx]
4499 << (LITTLENUM_NUMBER_OF_BITS * j);
4500 inst.operands[i].reg = 0;
4501 for (j = 0; j < parts; j++, idx++)
4502 inst.operands[i].reg |= generic_bignum[idx]
4503 << (LITTLENUM_NUMBER_OF_BITS * j);
4504 inst.operands[i].regisimm = 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str)
4520 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i = 0; fp_const[i]; i++)
4531 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4535 *str += strlen (fp_const[i]);
4536 if (is_end_of_line[(unsigned char) **str])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4549 /* Look for a raw floating point number. */
4550 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4551 && is_end_of_line[(unsigned char) *save_in])
4553 for (i = 0; i < NUM_FLOAT_VALS; i++)
4555 for (j = 0; j < MAX_LITTLENUMS; j++)
4557 if (words[j] != fp_values[i][j])
4561 if (j == MAX_LITTLENUMS)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in = input_line_pointer;
4572 input_line_pointer = *str;
4573 if (expression (&exp) == absolute_section
4574 && exp.X_op == O_big
4575 && exp.X_add_number < 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words, 5, (long) 15) == 0)
4581 for (i = 0; i < NUM_FLOAT_VALS; i++)
4583 for (j = 0; j < MAX_LITTLENUMS; j++)
4585 if (words[j] != fp_values[i][j])
4589 if (j == MAX_LITTLENUMS)
4591 *str = input_line_pointer;
4592 input_line_pointer = save_in;
4599 *str = input_line_pointer;
4600 input_line_pointer = save_in;
4601 inst.error = _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm)
4611 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp, int *immed)
4626 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4627 int found_fpchar = 0;
4629 skip_past_char (&str, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum);
4639 if (strncmp (fpnum, "0x", 2) == 0)
4643 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4644 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4654 if ((str = atof_ieee (str, 's', words)) != NULL)
4656 unsigned fpword = 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4662 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4666 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str, int i, enum parse_shift_mode mode)
4714 const struct asm_shift_name *shift_name;
4715 enum shift_kind shift;
4720 for (p = *str; ISALPHA (*p); p++)
4725 inst.error = _("shift expression expected");
4729 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4732 if (shift_name == NULL)
4734 inst.error = _("shift expression expected");
4738 shift = shift_name->kind;
4742 case NO_SHIFT_RESTRICT:
4743 case SHIFT_IMMEDIATE: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4746 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4748 inst.error = _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE:
4754 if (shift != SHIFT_LSL)
4756 inst.error = _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE:
4762 if (shift != SHIFT_ASR)
4764 inst.error = _("'ASR' required");
4772 if (shift != SHIFT_RRX)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p);
4777 if (mode == NO_SHIFT_RESTRICT
4778 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4780 inst.operands[i].imm = reg;
4781 inst.operands[i].immisreg = 1;
4783 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4786 inst.operands[i].shift_kind = shift;
4787 inst.operands[i].shifted = 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str, int i)
4809 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4811 inst.operands[i].reg = value;
4812 inst.operands[i].isreg = 1;
4814 /* parse_shift will override this if appropriate */
4815 inst.reloc.exp.X_op = O_constant;
4816 inst.reloc.exp.X_add_number = 0;
4818 if (skip_past_comma (str) == FAIL)
4821 /* Shift operation on register. */
4822 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4825 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4828 if (skip_past_comma (str) == SUCCESS)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4834 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4836 inst.error = _("constant expression expected");
4840 value = exp.X_add_number;
4841 if (value < 0 || value > 30 || value % 2 != 0)
4843 inst.error = _("invalid rotation");
4846 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4848 inst.error = _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst.reloc.exp.X_add_number
4854 = (((inst.reloc.exp.X_add_number << (32 - value))
4855 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4858 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4859 inst.reloc.pc_rel = 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4953 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4955 int length = strlen (group_reloc_table[i].name);
4957 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4958 && (*str)[length] == ':')
4960 *out = &group_reloc_table[i];
4961 *str += (length + 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str, int i)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str)[0] == '#' && (*str)[1] == ':')
4991 || (*str)[0] == ':')
4993 struct group_reloc_table_entry *entry;
4995 if ((*str)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5003 inst.error = _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5014 gas_assert (inst.reloc.type != 0);
5016 return PARSE_OPERAND_SUCCESS;
5019 return parse_shifter_operand (str, i) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str, int i)
5035 my_get_expression (&exp, &p, GE_NO_PREFIX);
5037 if (exp.X_op != O_constant)
5039 inst.error = _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL;
5043 inst.operands[i].imm = exp.X_add_number << 8;
5044 inst.operands[i].immisalign = 1;
5045 /* Alignments are not pre-indexes. */
5046 inst.operands[i].preind = 0;
5049 return PARSE_OPERAND_SUCCESS;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str, int i, int group_relocations,
5086 group_reloc_type group_type)
5091 if (skip_past_char (&p, '[') == FAIL)
5093 if (skip_past_char (&p, '=') == FAIL)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst.reloc.pc_rel = 1;
5097 inst.operands[i].reg = REG_PC;
5098 inst.operands[i].isreg = 1;
5099 inst.operands[i].preind = 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5104 return PARSE_OPERAND_FAIL;
5107 return PARSE_OPERAND_SUCCESS;
5110 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5112 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5113 return PARSE_OPERAND_FAIL;
5115 inst.operands[i].reg = reg;
5116 inst.operands[i].isreg = 1;
5118 if (skip_past_comma (&p) == SUCCESS)
5120 inst.operands[i].preind = 1;
5123 else if (*p == '-') p++, inst.operands[i].negative = 1;
5125 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5127 inst.operands[i].imm = reg;
5128 inst.operands[i].immisreg = 1;
5130 if (skip_past_comma (&p) == SUCCESS)
5131 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5132 return PARSE_OPERAND_FAIL;
5134 else if (skip_past_char (&p, ':') == SUCCESS)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result = parse_neon_alignment (&p, i);
5141 if (result != PARSE_OPERAND_SUCCESS)
5146 if (inst.operands[i].negative)
5148 inst.operands[i].negative = 0;
5152 if (group_relocations
5153 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5155 struct group_reloc_table_entry *entry;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5167 inst.error = _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5177 /* Record the relocation type. */
5181 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5185 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5189 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5196 if (inst.reloc.type == 0)
5198 inst.error = _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5205 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5206 return PARSE_OPERAND_FAIL;
5207 /* If the offset is 0, find out if it's a +0 or -0. */
5208 if (inst.reloc.exp.X_op == O_constant
5209 && inst.reloc.exp.X_add_number == 0)
5211 skip_whitespace (q);
5215 skip_whitespace (q);
5218 inst.operands[i].negative = 1;
5223 else if (skip_past_char (&p, ':') == SUCCESS)
5225 /* FIXME: '@' should be used here, but it's filtered out by generic code
5226 before we get to see it here. This may be subject to change. */
5227 parse_operand_result result = parse_neon_alignment (&p, i);
5229 if (result != PARSE_OPERAND_SUCCESS)
5233 if (skip_past_char (&p, ']') == FAIL)
5235 inst.error = _("']' expected");
5236 return PARSE_OPERAND_FAIL;
5239 if (skip_past_char (&p, '!') == SUCCESS)
5240 inst.operands[i].writeback = 1;
5242 else if (skip_past_comma (&p) == SUCCESS)
5244 if (skip_past_char (&p, '{') == SUCCESS)
5246 /* [Rn], {expr} - unindexed, with option */
5247 if (parse_immediate (&p, &inst.operands[i].imm,
5248 0, 255, TRUE) == FAIL)
5249 return PARSE_OPERAND_FAIL;
5251 if (skip_past_char (&p, '}') == FAIL)
5253 inst.error = _("'}' expected at end of 'option' field");
5254 return PARSE_OPERAND_FAIL;
5256 if (inst.operands[i].preind)
5258 inst.error = _("cannot combine index with option");
5259 return PARSE_OPERAND_FAIL;
5262 return PARSE_OPERAND_SUCCESS;
5266 inst.operands[i].postind = 1;
5267 inst.operands[i].writeback = 1;
5269 if (inst.operands[i].preind)
5271 inst.error = _("cannot combine pre- and post-indexing");
5272 return PARSE_OPERAND_FAIL;
5276 else if (*p == '-') p++, inst.operands[i].negative = 1;
5278 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5280 /* We might be using the immediate for alignment already. If we
5281 are, OR the register number into the low-order bits. */
5282 if (inst.operands[i].immisalign)
5283 inst.operands[i].imm |= reg;
5285 inst.operands[i].imm = reg;
5286 inst.operands[i].immisreg = 1;
5288 if (skip_past_comma (&p) == SUCCESS)
5289 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5290 return PARSE_OPERAND_FAIL;
5295 if (inst.operands[i].negative)
5297 inst.operands[i].negative = 0;
5300 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5301 return PARSE_OPERAND_FAIL;
5302 /* If the offset is 0, find out if it's a +0 or -0. */
5303 if (inst.reloc.exp.X_op == O_constant
5304 && inst.reloc.exp.X_add_number == 0)
5306 skip_whitespace (q);
5310 skip_whitespace (q);
5313 inst.operands[i].negative = 1;
5319 /* If at this point neither .preind nor .postind is set, we have a
5320 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5321 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5323 inst.operands[i].preind = 1;
5324 inst.reloc.exp.X_op = O_constant;
5325 inst.reloc.exp.X_add_number = 0;
5328 return PARSE_OPERAND_SUCCESS;
5332 parse_address (char **str, int i)
5334 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5338 static parse_operand_result
5339 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5341 return parse_address_main (str, i, 1, type);
5344 /* Parse an operand for a MOVW or MOVT instruction. */
5346 parse_half (char **str)
5351 skip_past_char (&p, '#');
5352 if (strncasecmp (p, ":lower16:", 9) == 0)
5353 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5354 else if (strncasecmp (p, ":upper16:", 9) == 0)
5355 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5357 if (inst.reloc.type != BFD_RELOC_UNUSED)
5360 skip_whitespace (p);
5363 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5366 if (inst.reloc.type == BFD_RELOC_UNUSED)
5368 if (inst.reloc.exp.X_op != O_constant)
5370 inst.error = _("constant expression expected");
5373 if (inst.reloc.exp.X_add_number < 0
5374 || inst.reloc.exp.X_add_number > 0xffff)
5376 inst.error = _("immediate value out of range");
5384 /* Miscellaneous. */
5386 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5387 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5389 parse_psr (char **str, bfd_boolean lhs)
5392 unsigned long psr_field;
5393 const struct asm_psr *psr;
5395 bfd_boolean is_apsr = FALSE;
5396 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5398 /* PR gas/12698: If the user has specified -march=all then m_profile will
5399 be TRUE, but we want to ignore it in this case as we are building for any
5400 CPU type, including non-m variants. */
5401 if (selected_cpu.core == arm_arch_any.core)
5404 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5405 feature for ease of use and backwards compatibility. */
5407 if (strncasecmp (p, "SPSR", 4) == 0)
5410 goto unsupported_psr;
5412 psr_field = SPSR_BIT;
5414 else if (strncasecmp (p, "CPSR", 4) == 0)
5417 goto unsupported_psr;
5421 else if (strncasecmp (p, "APSR", 4) == 0)
5423 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5424 and ARMv7-R architecture CPUs. */
5433 while (ISALNUM (*p) || *p == '_');
5435 if (strncasecmp (start, "iapsr", 5) == 0
5436 || strncasecmp (start, "eapsr", 5) == 0
5437 || strncasecmp (start, "xpsr", 4) == 0
5438 || strncasecmp (start, "psr", 3) == 0)
5439 p = start + strcspn (start, "rR") + 1;
5441 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5447 /* If APSR is being written, a bitfield may be specified. Note that
5448 APSR itself is handled above. */
5449 if (psr->field <= 3)
5451 psr_field = psr->field;
5457 /* M-profile MSR instructions have the mask field set to "10", except
5458 *PSR variants which modify APSR, which may use a different mask (and
5459 have been handled already). Do that by setting the PSR_f field
5461 return psr->field | (lhs ? PSR_f : 0);
5464 goto unsupported_psr;
5470 /* A suffix follows. */
5476 while (ISALNUM (*p) || *p == '_');
5480 /* APSR uses a notation for bits, rather than fields. */
5481 unsigned int nzcvq_bits = 0;
5482 unsigned int g_bit = 0;
5485 for (bit = start; bit != p; bit++)
5487 switch (TOLOWER (*bit))
5490 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5494 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5498 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5502 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5506 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5510 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5514 inst.error = _("unexpected bit specified after APSR");
5519 if (nzcvq_bits == 0x1f)
5524 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5526 inst.error = _("selected processor does not "
5527 "support DSP extension");
5534 if ((nzcvq_bits & 0x20) != 0
5535 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5536 || (g_bit & 0x2) != 0)
5538 inst.error = _("bad bitmask specified after APSR");
5544 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5549 psr_field |= psr->field;
5555 goto error; /* Garbage after "[CS]PSR". */
5557 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5558 is deprecated, but allow it anyway. */
5562 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5565 else if (!m_profile)
5566 /* These bits are never right for M-profile devices: don't set them
5567 (only code paths which read/write APSR reach here). */
5568 psr_field |= (PSR_c | PSR_f);
5574 inst.error = _("selected processor does not support requested special "
5575 "purpose register");
5579 inst.error = _("flag for {c}psr instruction expected");
5583 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5584 value suitable for splatting into the AIF field of the instruction. */
5587 parse_cps_flags (char **str)
5596 case '\0': case ',':
5599 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5600 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5601 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5604 inst.error = _("unrecognized CPS flag");
5609 if (saw_a_flag == 0)
5611 inst.error = _("missing CPS flags");
5619 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5620 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5623 parse_endian_specifier (char **str)
5628 if (strncasecmp (s, "BE", 2))
5630 else if (strncasecmp (s, "LE", 2))
5634 inst.error = _("valid endian specifiers are be or le");
5638 if (ISALNUM (s[2]) || s[2] == '_')
5640 inst.error = _("valid endian specifiers are be or le");
5645 return little_endian;
5648 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5649 value suitable for poking into the rotate field of an sxt or sxta
5650 instruction, or FAIL on error. */
5653 parse_ror (char **str)
5658 if (strncasecmp (s, "ROR", 3) == 0)
5662 inst.error = _("missing rotation field after comma");
5666 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5671 case 0: *str = s; return 0x0;
5672 case 8: *str = s; return 0x1;
5673 case 16: *str = s; return 0x2;
5674 case 24: *str = s; return 0x3;
5677 inst.error = _("rotation can only be 0, 8, 16, or 24");
5682 /* Parse a conditional code (from conds[] below). The value returned is in the
5683 range 0 .. 14, or FAIL. */
5685 parse_cond (char **str)
5688 const struct asm_cond *c;
5690 /* Condition codes are always 2 characters, so matching up to
5691 3 characters is sufficient. */
5696 while (ISALPHA (*q) && n < 3)
5698 cond[n] = TOLOWER (*q);
5703 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5706 inst.error = _("condition required");
5714 /* Parse an option for a barrier instruction. Returns the encoding for the
5717 parse_barrier (char **str)
5720 const struct asm_barrier_opt *o;
5723 while (ISALPHA (*q))
5726 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5735 /* Parse the operands of a table branch instruction. Similar to a memory
5738 parse_tb (char **str)
5743 if (skip_past_char (&p, '[') == FAIL)
5745 inst.error = _("'[' expected");
5749 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5751 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5754 inst.operands[0].reg = reg;
5756 if (skip_past_comma (&p) == FAIL)
5758 inst.error = _("',' expected");
5762 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5764 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5767 inst.operands[0].imm = reg;
5769 if (skip_past_comma (&p) == SUCCESS)
5771 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5773 if (inst.reloc.exp.X_add_number != 1)
5775 inst.error = _("invalid shift");
5778 inst.operands[0].shifted = 1;
5781 if (skip_past_char (&p, ']') == FAIL)
5783 inst.error = _("']' expected");
5790 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5791 information on the types the operands can take and how they are encoded.
5792 Up to four operands may be read; this function handles setting the
5793 ".present" field for each read operand itself.
5794 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5795 else returns FAIL. */
5798 parse_neon_mov (char **str, int *which_operand)
5800 int i = *which_operand, val;
5801 enum arm_reg_type rtype;
5803 struct neon_type_el optype;
5805 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5807 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5808 inst.operands[i].reg = val;
5809 inst.operands[i].isscalar = 1;
5810 inst.operands[i].vectype = optype;
5811 inst.operands[i++].present = 1;
5813 if (skip_past_comma (&ptr) == FAIL)
5816 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5819 inst.operands[i].reg = val;
5820 inst.operands[i].isreg = 1;
5821 inst.operands[i].present = 1;
5823 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5826 /* Cases 0, 1, 2, 3, 5 (D only). */
5827 if (skip_past_comma (&ptr) == FAIL)
5830 inst.operands[i].reg = val;
5831 inst.operands[i].isreg = 1;
5832 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5833 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5834 inst.operands[i].isvec = 1;
5835 inst.operands[i].vectype = optype;
5836 inst.operands[i++].present = 1;
5838 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5840 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5841 Case 13: VMOV <Sd>, <Rm> */
5842 inst.operands[i].reg = val;
5843 inst.operands[i].isreg = 1;
5844 inst.operands[i].present = 1;
5846 if (rtype == REG_TYPE_NQ)
5848 first_error (_("can't use Neon quad register here"));
5851 else if (rtype != REG_TYPE_VFS)
5854 if (skip_past_comma (&ptr) == FAIL)
5856 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5858 inst.operands[i].reg = val;
5859 inst.operands[i].isreg = 1;
5860 inst.operands[i].present = 1;
5863 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5866 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5867 Case 1: VMOV<c><q> <Dd>, <Dm>
5868 Case 8: VMOV.F32 <Sd>, <Sm>
5869 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5871 inst.operands[i].reg = val;
5872 inst.operands[i].isreg = 1;
5873 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5874 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5875 inst.operands[i].isvec = 1;
5876 inst.operands[i].vectype = optype;
5877 inst.operands[i].present = 1;
5879 if (skip_past_comma (&ptr) == SUCCESS)
5884 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5887 inst.operands[i].reg = val;
5888 inst.operands[i].isreg = 1;
5889 inst.operands[i++].present = 1;
5891 if (skip_past_comma (&ptr) == FAIL)
5894 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i++].present = 1;
5902 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5903 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5904 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5905 Case 10: VMOV.F32 <Sd>, #<imm>
5906 Case 11: VMOV.F64 <Dd>, #<imm> */
5907 inst.operands[i].immisfloat = 1;
5908 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5909 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5910 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5914 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5918 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5921 inst.operands[i].reg = val;
5922 inst.operands[i].isreg = 1;
5923 inst.operands[i++].present = 1;
5925 if (skip_past_comma (&ptr) == FAIL)
5928 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5930 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5931 inst.operands[i].reg = val;
5932 inst.operands[i].isscalar = 1;
5933 inst.operands[i].present = 1;
5934 inst.operands[i].vectype = optype;
5936 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5938 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5939 inst.operands[i].reg = val;
5940 inst.operands[i].isreg = 1;
5941 inst.operands[i++].present = 1;
5943 if (skip_past_comma (&ptr) == FAIL)
5946 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5949 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5953 inst.operands[i].reg = val;
5954 inst.operands[i].isreg = 1;
5955 inst.operands[i].isvec = 1;
5956 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5957 inst.operands[i].vectype = optype;
5958 inst.operands[i].present = 1;
5960 if (rtype == REG_TYPE_VFS)
5964 if (skip_past_comma (&ptr) == FAIL)
5966 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5969 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5972 inst.operands[i].reg = val;
5973 inst.operands[i].isreg = 1;
5974 inst.operands[i].isvec = 1;
5975 inst.operands[i].issingle = 1;
5976 inst.operands[i].vectype = optype;
5977 inst.operands[i].present = 1;
5980 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5984 inst.operands[i].reg = val;
5985 inst.operands[i].isreg = 1;
5986 inst.operands[i].isvec = 1;
5987 inst.operands[i].issingle = 1;
5988 inst.operands[i].vectype = optype;
5989 inst.operands[i++].present = 1;
5994 first_error (_("parse error"));
5998 /* Successfully parsed the operands. Update args. */
6004 first_error (_("expected comma"));
6008 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6012 /* Use this macro when the operand constraints are different
6013 for ARM and THUMB (e.g. ldrd). */
6014 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6015 ((arm_operand) | ((thumb_operand) << 16))
6017 /* Matcher codes for parse_operands. */
6018 enum operand_parse_code
6020 OP_stop, /* end of line */
6022 OP_RR, /* ARM register */
6023 OP_RRnpc, /* ARM register, not r15 */
6024 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6025 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6026 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6027 optional trailing ! */
6028 OP_RRw, /* ARM register, not r15, optional trailing ! */
6029 OP_RCP, /* Coprocessor number */
6030 OP_RCN, /* Coprocessor register */
6031 OP_RF, /* FPA register */
6032 OP_RVS, /* VFP single precision register */
6033 OP_RVD, /* VFP double precision register (0..15) */
6034 OP_RND, /* Neon double precision register (0..31) */
6035 OP_RNQ, /* Neon quad precision register */
6036 OP_RVSD, /* VFP single or double precision register */
6037 OP_RNDQ, /* Neon double or quad precision register */
6038 OP_RNSDQ, /* Neon single, double or quad precision register */
6039 OP_RNSC, /* Neon scalar D[X] */
6040 OP_RVC, /* VFP control register */
6041 OP_RMF, /* Maverick F register */
6042 OP_RMD, /* Maverick D register */
6043 OP_RMFX, /* Maverick FX register */
6044 OP_RMDX, /* Maverick DX register */
6045 OP_RMAX, /* Maverick AX register */
6046 OP_RMDS, /* Maverick DSPSC register */
6047 OP_RIWR, /* iWMMXt wR register */
6048 OP_RIWC, /* iWMMXt wC register */
6049 OP_RIWG, /* iWMMXt wCG register */
6050 OP_RXA, /* XScale accumulator register */
6052 OP_REGLST, /* ARM register list */
6053 OP_VRSLST, /* VFP single-precision register list */
6054 OP_VRDLST, /* VFP double-precision register list */
6055 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6056 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6057 OP_NSTRLST, /* Neon element/structure list */
6059 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6060 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6061 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6062 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6063 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6064 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6065 OP_VMOV, /* Neon VMOV operands. */
6066 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6067 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6068 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6070 OP_I0, /* immediate zero */
6071 OP_I7, /* immediate value 0 .. 7 */
6072 OP_I15, /* 0 .. 15 */
6073 OP_I16, /* 1 .. 16 */
6074 OP_I16z, /* 0 .. 16 */
6075 OP_I31, /* 0 .. 31 */
6076 OP_I31w, /* 0 .. 31, optional trailing ! */
6077 OP_I32, /* 1 .. 32 */
6078 OP_I32z, /* 0 .. 32 */
6079 OP_I63, /* 0 .. 63 */
6080 OP_I63s, /* -64 .. 63 */
6081 OP_I64, /* 1 .. 64 */
6082 OP_I64z, /* 0 .. 64 */
6083 OP_I255, /* 0 .. 255 */
6085 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6086 OP_I7b, /* 0 .. 7 */
6087 OP_I15b, /* 0 .. 15 */
6088 OP_I31b, /* 0 .. 31 */
6090 OP_SH, /* shifter operand */
6091 OP_SHG, /* shifter operand with possible group relocation */
6092 OP_ADDR, /* Memory address expression (any mode) */
6093 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6094 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6095 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6096 OP_EXP, /* arbitrary expression */
6097 OP_EXPi, /* same, with optional immediate prefix */
6098 OP_EXPr, /* same, with optional relocation suffix */
6099 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6101 OP_CPSF, /* CPS flags */
6102 OP_ENDI, /* Endianness specifier */
6103 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6104 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6105 OP_COND, /* conditional code */
6106 OP_TB, /* Table branch. */
6108 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6110 OP_RRnpc_I0, /* ARM register or literal 0 */
6111 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6112 OP_RR_EXi, /* ARM register or expression with imm prefix */
6113 OP_RF_IF, /* FPA register or immediate */
6114 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6115 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6117 /* Optional operands. */
6118 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6119 OP_oI31b, /* 0 .. 31 */
6120 OP_oI32b, /* 1 .. 32 */
6121 OP_oIffffb, /* 0 .. 65535 */
6122 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6124 OP_oRR, /* ARM register */
6125 OP_oRRnpc, /* ARM register, not the PC */
6126 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6127 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6128 OP_oRND, /* Optional Neon double precision register */
6129 OP_oRNQ, /* Optional Neon quad precision register */
6130 OP_oRNDQ, /* Optional Neon double or quad precision register */
6131 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6132 OP_oSHll, /* LSL immediate */
6133 OP_oSHar, /* ASR immediate */
6134 OP_oSHllar, /* LSL or ASR immediate */
6135 OP_oROR, /* ROR 0/8/16/24 */
6136 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6138 /* Some pre-defined mixed (ARM/THUMB) operands. */
6139 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6140 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6141 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6143 OP_FIRST_OPTIONAL = OP_oI7b
6146 /* Generic instruction operand parser. This does no encoding and no
6147 semantic validation; it merely squirrels values away in the inst
6148 structure. Returns SUCCESS or FAIL depending on whether the
6149 specified grammar matched. */
6151 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6153 unsigned const int *upat = pattern;
6154 char *backtrack_pos = 0;
6155 const char *backtrack_error = 0;
6156 int i, val, backtrack_index = 0;
6157 enum arm_reg_type rtype;
6158 parse_operand_result result;
6159 unsigned int op_parse_code;
6161 #define po_char_or_fail(chr) \
6164 if (skip_past_char (&str, chr) == FAIL) \
6169 #define po_reg_or_fail(regtype) \
6172 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6173 & inst.operands[i].vectype); \
6176 first_error (_(reg_expected_msgs[regtype])); \
6179 inst.operands[i].reg = val; \
6180 inst.operands[i].isreg = 1; \
6181 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6182 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6183 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6184 || rtype == REG_TYPE_VFD \
6185 || rtype == REG_TYPE_NQ); \
6189 #define po_reg_or_goto(regtype, label) \
6192 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6193 & inst.operands[i].vectype); \
6197 inst.operands[i].reg = val; \
6198 inst.operands[i].isreg = 1; \
6199 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6200 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6201 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6202 || rtype == REG_TYPE_VFD \
6203 || rtype == REG_TYPE_NQ); \
6207 #define po_imm_or_fail(min, max, popt) \
6210 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6212 inst.operands[i].imm = val; \
6216 #define po_scalar_or_goto(elsz, label) \
6219 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6222 inst.operands[i].reg = val; \
6223 inst.operands[i].isscalar = 1; \
6227 #define po_misc_or_fail(expr) \
6235 #define po_misc_or_fail_no_backtrack(expr) \
6239 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6240 backtrack_pos = 0; \
6241 if (result != PARSE_OPERAND_SUCCESS) \
6246 #define po_barrier_or_imm(str) \
6249 val = parse_barrier (&str); \
6252 if (ISALPHA (*str)) \
6259 if ((inst.instruction & 0xf0) == 0x60 \
6262 /* ISB can only take SY as an option. */ \
6263 inst.error = _("invalid barrier type"); \
6270 skip_whitespace (str);
6272 for (i = 0; upat[i] != OP_stop; i++)
6274 op_parse_code = upat[i];
6275 if (op_parse_code >= 1<<16)
6276 op_parse_code = thumb ? (op_parse_code >> 16)
6277 : (op_parse_code & ((1<<16)-1));
6279 if (op_parse_code >= OP_FIRST_OPTIONAL)
6281 /* Remember where we are in case we need to backtrack. */
6282 gas_assert (!backtrack_pos);
6283 backtrack_pos = str;
6284 backtrack_error = inst.error;
6285 backtrack_index = i;
6288 if (i > 0 && (i > 1 || inst.operands[0].present))
6289 po_char_or_fail (',');
6291 switch (op_parse_code)
6299 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6300 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6301 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6302 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6303 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6304 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6306 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6308 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6310 /* Also accept generic coprocessor regs for unknown registers. */
6312 po_reg_or_fail (REG_TYPE_CN);
6314 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6315 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6316 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6317 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6318 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6319 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6320 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6321 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6322 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6323 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6325 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6327 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6328 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6330 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6332 /* Neon scalar. Using an element size of 8 means that some invalid
6333 scalars are accepted here, so deal with those in later code. */
6334 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6338 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6341 po_imm_or_fail (0, 0, TRUE);
6346 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6351 po_scalar_or_goto (8, try_rr);
6354 po_reg_or_fail (REG_TYPE_RN);
6360 po_scalar_or_goto (8, try_nsdq);
6363 po_reg_or_fail (REG_TYPE_NSDQ);
6369 po_scalar_or_goto (8, try_ndq);
6372 po_reg_or_fail (REG_TYPE_NDQ);
6378 po_scalar_or_goto (8, try_vfd);
6381 po_reg_or_fail (REG_TYPE_VFD);
6386 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6387 not careful then bad things might happen. */
6388 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6393 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6396 /* There's a possibility of getting a 64-bit immediate here, so
6397 we need special handling. */
6398 if (parse_big_immediate (&str, i) == FAIL)
6400 inst.error = _("immediate value is out of range");
6408 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6411 po_imm_or_fail (0, 63, TRUE);
6416 po_char_or_fail ('[');
6417 po_reg_or_fail (REG_TYPE_RN);
6418 po_char_or_fail (']');
6424 po_reg_or_fail (REG_TYPE_RN);
6425 if (skip_past_char (&str, '!') == SUCCESS)
6426 inst.operands[i].writeback = 1;
6430 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6431 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6432 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6433 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6434 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6435 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6436 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6437 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6438 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6439 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6440 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6441 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6443 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6445 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6446 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6448 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6449 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6450 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6452 /* Immediate variants */
6454 po_char_or_fail ('{');
6455 po_imm_or_fail (0, 255, TRUE);
6456 po_char_or_fail ('}');
6460 /* The expression parser chokes on a trailing !, so we have
6461 to find it first and zap it. */
6464 while (*s && *s != ',')
6469 inst.operands[i].writeback = 1;
6471 po_imm_or_fail (0, 31, TRUE);
6479 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6484 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6489 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6491 if (inst.reloc.exp.X_op == O_symbol)
6493 val = parse_reloc (&str);
6496 inst.error = _("unrecognized relocation suffix");
6499 else if (val != BFD_RELOC_UNUSED)
6501 inst.operands[i].imm = val;
6502 inst.operands[i].hasreloc = 1;
6507 /* Operand for MOVW or MOVT. */
6509 po_misc_or_fail (parse_half (&str));
6512 /* Register or expression. */
6513 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6514 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6516 /* Register or immediate. */
6517 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6518 I0: po_imm_or_fail (0, 0, FALSE); break;
6520 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6522 if (!is_immediate_prefix (*str))
6525 val = parse_fpa_immediate (&str);
6528 /* FPA immediates are encoded as registers 8-15.
6529 parse_fpa_immediate has already applied the offset. */
6530 inst.operands[i].reg = val;
6531 inst.operands[i].isreg = 1;
6534 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6535 I32z: po_imm_or_fail (0, 32, FALSE); break;
6537 /* Two kinds of register. */
6540 struct reg_entry *rege = arm_reg_parse_multi (&str);
6542 || (rege->type != REG_TYPE_MMXWR
6543 && rege->type != REG_TYPE_MMXWC
6544 && rege->type != REG_TYPE_MMXWCG))
6546 inst.error = _("iWMMXt data or control register expected");
6549 inst.operands[i].reg = rege->number;
6550 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6556 struct reg_entry *rege = arm_reg_parse_multi (&str);
6558 || (rege->type != REG_TYPE_MMXWC
6559 && rege->type != REG_TYPE_MMXWCG))
6561 inst.error = _("iWMMXt control register expected");
6564 inst.operands[i].reg = rege->number;
6565 inst.operands[i].isreg = 1;
6570 case OP_CPSF: val = parse_cps_flags (&str); break;
6571 case OP_ENDI: val = parse_endian_specifier (&str); break;
6572 case OP_oROR: val = parse_ror (&str); break;
6573 case OP_COND: val = parse_cond (&str); break;
6574 case OP_oBARRIER_I15:
6575 po_barrier_or_imm (str); break;
6577 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6583 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6584 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6586 inst.error = _("Banked registers are not available with this "
6592 val = parse_psr (&str, op_parse_code == OP_wPSR);
6596 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6599 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6601 if (strncasecmp (str, "APSR_", 5) == 0)
6608 case 'c': found = (found & 1) ? 16 : found | 1; break;
6609 case 'n': found = (found & 2) ? 16 : found | 2; break;
6610 case 'z': found = (found & 4) ? 16 : found | 4; break;
6611 case 'v': found = (found & 8) ? 16 : found | 8; break;
6612 default: found = 16;
6616 inst.operands[i].isvec = 1;
6617 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6618 inst.operands[i].reg = REG_PC;
6625 po_misc_or_fail (parse_tb (&str));
6628 /* Register lists. */
6630 val = parse_reg_list (&str);
6633 inst.operands[1].writeback = 1;
6639 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6643 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6647 /* Allow Q registers too. */
6648 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6653 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6655 inst.operands[i].issingle = 1;
6660 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6665 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6666 &inst.operands[i].vectype);
6669 /* Addressing modes */
6671 po_misc_or_fail (parse_address (&str, i));
6675 po_misc_or_fail_no_backtrack (
6676 parse_address_group_reloc (&str, i, GROUP_LDR));
6680 po_misc_or_fail_no_backtrack (
6681 parse_address_group_reloc (&str, i, GROUP_LDRS));
6685 po_misc_or_fail_no_backtrack (
6686 parse_address_group_reloc (&str, i, GROUP_LDC));
6690 po_misc_or_fail (parse_shifter_operand (&str, i));
6694 po_misc_or_fail_no_backtrack (
6695 parse_shifter_operand_group_reloc (&str, i));
6699 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6703 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6707 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6711 as_fatal (_("unhandled operand code %d"), op_parse_code);
6714 /* Various value-based sanity checks and shared operations. We
6715 do not signal immediate failures for the register constraints;
6716 this allows a syntax error to take precedence. */
6717 switch (op_parse_code)
6725 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6726 inst.error = BAD_PC;
6731 if (inst.operands[i].isreg)
6733 if (inst.operands[i].reg == REG_PC)
6734 inst.error = BAD_PC;
6735 else if (inst.operands[i].reg == REG_SP)
6736 inst.error = BAD_SP;
6741 if (inst.operands[i].isreg
6742 && inst.operands[i].reg == REG_PC
6743 && (inst.operands[i].writeback || thumb))
6744 inst.error = BAD_PC;
6753 case OP_oBARRIER_I15:
6762 inst.operands[i].imm = val;
6769 /* If we get here, this operand was successfully parsed. */
6770 inst.operands[i].present = 1;
6774 inst.error = BAD_ARGS;
6779 /* The parse routine should already have set inst.error, but set a
6780 default here just in case. */
6782 inst.error = _("syntax error");
6786 /* Do not backtrack over a trailing optional argument that
6787 absorbed some text. We will only fail again, with the
6788 'garbage following instruction' error message, which is
6789 probably less helpful than the current one. */
6790 if (backtrack_index == i && backtrack_pos != str
6791 && upat[i+1] == OP_stop)
6794 inst.error = _("syntax error");
6798 /* Try again, skipping the optional argument at backtrack_pos. */
6799 str = backtrack_pos;
6800 inst.error = backtrack_error;
6801 inst.operands[backtrack_index].present = 0;
6802 i = backtrack_index;
6806 /* Check that we have parsed all the arguments. */
6807 if (*str != '\0' && !inst.error)
6808 inst.error = _("garbage following instruction");
6810 return inst.error ? FAIL : SUCCESS;
6813 #undef po_char_or_fail
6814 #undef po_reg_or_fail
6815 #undef po_reg_or_goto
6816 #undef po_imm_or_fail
6817 #undef po_scalar_or_fail
6818 #undef po_barrier_or_imm
6820 /* Shorthand macro for instruction encoding functions issuing errors. */
6821 #define constraint(expr, err) \
6832 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6833 instructions are unpredictable if these registers are used. This
6834 is the BadReg predicate in ARM's Thumb-2 documentation. */
6835 #define reject_bad_reg(reg) \
6837 if (reg == REG_SP || reg == REG_PC) \
6839 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6844 /* If REG is R13 (the stack pointer), warn that its use is
6846 #define warn_deprecated_sp(reg) \
6848 if (warn_on_deprecated && reg == REG_SP) \
6849 as_warn (_("use of r13 is deprecated")); \
6852 /* Functions for operand encoding. ARM, then Thumb. */
6854 #define rotate_left(v, n) (v << n | v >> (32 - n))
6856 /* If VAL can be encoded in the immediate field of an ARM instruction,
6857 return the encoded form. Otherwise, return FAIL. */
6860 encode_arm_immediate (unsigned int val)
6864 for (i = 0; i < 32; i += 2)
6865 if ((a = rotate_left (val, i)) <= 0xff)
6866 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6871 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6872 return the encoded form. Otherwise, return FAIL. */
6874 encode_thumb32_immediate (unsigned int val)
6881 for (i = 1; i <= 24; i++)
6884 if ((val & ~(0xff << i)) == 0)
6885 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6889 if (val == ((a << 16) | a))
6891 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6895 if (val == ((a << 16) | a))
6896 return 0x200 | (a >> 8);
6900 /* Encode a VFP SP or DP register number into inst.instruction. */
6903 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6905 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6908 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6911 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6914 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6919 first_error (_("D register out of range for selected VFP version"));
6927 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6931 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6935 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6939 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6943 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6947 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6955 /* Encode a <shift> in an ARM-format instruction. The immediate,
6956 if any, is handled by md_apply_fix. */
6958 encode_arm_shift (int i)
6960 if (inst.operands[i].shift_kind == SHIFT_RRX)
6961 inst.instruction |= SHIFT_ROR << 5;
6964 inst.instruction |= inst.operands[i].shift_kind << 5;
6965 if (inst.operands[i].immisreg)
6967 inst.instruction |= SHIFT_BY_REG;
6968 inst.instruction |= inst.operands[i].imm << 8;
6971 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6976 encode_arm_shifter_operand (int i)
6978 if (inst.operands[i].isreg)
6980 inst.instruction |= inst.operands[i].reg;
6981 encode_arm_shift (i);
6984 inst.instruction |= INST_IMMEDIATE;
6987 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6989 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6991 gas_assert (inst.operands[i].isreg);
6992 inst.instruction |= inst.operands[i].reg << 16;
6994 if (inst.operands[i].preind)
6998 inst.error = _("instruction does not accept preindexed addressing");
7001 inst.instruction |= PRE_INDEX;
7002 if (inst.operands[i].writeback)
7003 inst.instruction |= WRITE_BACK;
7006 else if (inst.operands[i].postind)
7008 gas_assert (inst.operands[i].writeback);
7010 inst.instruction |= WRITE_BACK;
7012 else /* unindexed - only for coprocessor */
7014 inst.error = _("instruction does not accept unindexed addressing");
7018 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7019 && (((inst.instruction & 0x000f0000) >> 16)
7020 == ((inst.instruction & 0x0000f000) >> 12)))
7021 as_warn ((inst.instruction & LOAD_BIT)
7022 ? _("destination register same as write-back base")
7023 : _("source register same as write-back base"));
7026 /* inst.operands[i] was set up by parse_address. Encode it into an
7027 ARM-format mode 2 load or store instruction. If is_t is true,
7028 reject forms that cannot be used with a T instruction (i.e. not
7031 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7033 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7035 encode_arm_addr_mode_common (i, is_t);
7037 if (inst.operands[i].immisreg)
7039 constraint ((inst.operands[i].imm == REG_PC
7040 || (is_pc && inst.operands[i].writeback)),
7042 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7043 inst.instruction |= inst.operands[i].imm;
7044 if (!inst.operands[i].negative)
7045 inst.instruction |= INDEX_UP;
7046 if (inst.operands[i].shifted)
7048 if (inst.operands[i].shift_kind == SHIFT_RRX)
7049 inst.instruction |= SHIFT_ROR << 5;
7052 inst.instruction |= inst.operands[i].shift_kind << 5;
7053 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7057 else /* immediate offset in inst.reloc */
7059 if (is_pc && !inst.reloc.pc_rel)
7061 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7063 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7064 cannot use PC in addressing.
7065 PC cannot be used in writeback addressing, either. */
7066 constraint ((is_t || inst.operands[i].writeback),
7069 /* Use of PC in str is deprecated for ARMv7. */
7070 if (warn_on_deprecated
7072 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7073 as_warn (_("use of PC in this instruction is deprecated"));
7076 if (inst.reloc.type == BFD_RELOC_UNUSED)
7078 /* Prefer + for zero encoded value. */
7079 if (!inst.operands[i].negative)
7080 inst.instruction |= INDEX_UP;
7081 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7086 /* inst.operands[i] was set up by parse_address. Encode it into an
7087 ARM-format mode 3 load or store instruction. Reject forms that
7088 cannot be used with such instructions. If is_t is true, reject
7089 forms that cannot be used with a T instruction (i.e. not
7092 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7094 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7096 inst.error = _("instruction does not accept scaled register index");
7100 encode_arm_addr_mode_common (i, is_t);
7102 if (inst.operands[i].immisreg)
7104 constraint ((inst.operands[i].imm == REG_PC
7105 || inst.operands[i].reg == REG_PC),
7107 inst.instruction |= inst.operands[i].imm;
7108 if (!inst.operands[i].negative)
7109 inst.instruction |= INDEX_UP;
7111 else /* immediate offset in inst.reloc */
7113 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7114 && inst.operands[i].writeback),
7116 inst.instruction |= HWOFFSET_IMM;
7117 if (inst.reloc.type == BFD_RELOC_UNUSED)
7119 /* Prefer + for zero encoded value. */
7120 if (!inst.operands[i].negative)
7121 inst.instruction |= INDEX_UP;
7123 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7128 /* inst.operands[i] was set up by parse_address. Encode it into an
7129 ARM-format instruction. Reject all forms which cannot be encoded
7130 into a coprocessor load/store instruction. If wb_ok is false,
7131 reject use of writeback; if unind_ok is false, reject use of
7132 unindexed addressing. If reloc_override is not 0, use it instead
7133 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7134 (in which case it is preserved). */
7137 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7139 inst.instruction |= inst.operands[i].reg << 16;
7141 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7143 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7145 gas_assert (!inst.operands[i].writeback);
7148 inst.error = _("instruction does not support unindexed addressing");
7151 inst.instruction |= inst.operands[i].imm;
7152 inst.instruction |= INDEX_UP;
7156 if (inst.operands[i].preind)
7157 inst.instruction |= PRE_INDEX;
7159 if (inst.operands[i].writeback)
7161 if (inst.operands[i].reg == REG_PC)
7163 inst.error = _("pc may not be used with write-back");
7168 inst.error = _("instruction does not support writeback");
7171 inst.instruction |= WRITE_BACK;
7175 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7176 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7177 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7178 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7181 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7183 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7186 /* Prefer + for zero encoded value. */
7187 if (!inst.operands[i].negative)
7188 inst.instruction |= INDEX_UP;
7193 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7194 Determine whether it can be performed with a move instruction; if
7195 it can, convert inst.instruction to that move instruction and
7196 return TRUE; if it can't, convert inst.instruction to a literal-pool
7197 load and return FALSE. If this is not a valid thing to do in the
7198 current context, set inst.error and return TRUE.
7200 inst.operands[i] describes the destination register. */
7203 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7208 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7212 if ((inst.instruction & tbit) == 0)
7214 inst.error = _("invalid pseudo operation");
7217 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7219 inst.error = _("constant expression expected");
7222 if (inst.reloc.exp.X_op == O_constant)
7226 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7228 /* This can be done with a mov(1) instruction. */
7229 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7230 inst.instruction |= inst.reloc.exp.X_add_number;
7236 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7239 /* This can be done with a mov instruction. */
7240 inst.instruction &= LITERAL_MASK;
7241 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7242 inst.instruction |= value & 0xfff;
7246 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7249 /* This can be done with a mvn instruction. */
7250 inst.instruction &= LITERAL_MASK;
7251 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7252 inst.instruction |= value & 0xfff;
7258 if (add_to_lit_pool () == FAIL)
7260 inst.error = _("literal pool insertion failed");
7263 inst.operands[1].reg = REG_PC;
7264 inst.operands[1].isreg = 1;
7265 inst.operands[1].preind = 1;
7266 inst.reloc.pc_rel = 1;
7267 inst.reloc.type = (thumb_p
7268 ? BFD_RELOC_ARM_THUMB_OFFSET
7270 ? BFD_RELOC_ARM_HWLITERAL
7271 : BFD_RELOC_ARM_LITERAL));
7275 /* Functions for instruction encoding, sorted by sub-architecture.
7276 First some generics; their names are taken from the conventional
7277 bit positions for register arguments in ARM format instructions. */
7287 inst.instruction |= inst.operands[0].reg << 12;
7293 inst.instruction |= inst.operands[0].reg << 12;
7294 inst.instruction |= inst.operands[1].reg;
7300 inst.instruction |= inst.operands[0].reg << 12;
7301 inst.instruction |= inst.operands[1].reg << 16;
7307 inst.instruction |= inst.operands[0].reg << 16;
7308 inst.instruction |= inst.operands[1].reg << 12;
7314 unsigned Rn = inst.operands[2].reg;
7315 /* Enforce restrictions on SWP instruction. */
7316 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7318 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7319 _("Rn must not overlap other operands"));
7321 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7322 if (warn_on_deprecated
7323 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7324 as_warn (_("swp{b} use is deprecated for this architecture"));
7327 inst.instruction |= inst.operands[0].reg << 12;
7328 inst.instruction |= inst.operands[1].reg;
7329 inst.instruction |= Rn << 16;
7335 inst.instruction |= inst.operands[0].reg << 12;
7336 inst.instruction |= inst.operands[1].reg << 16;
7337 inst.instruction |= inst.operands[2].reg;
7343 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7344 constraint (((inst.reloc.exp.X_op != O_constant
7345 && inst.reloc.exp.X_op != O_illegal)
7346 || inst.reloc.exp.X_add_number != 0),
7348 inst.instruction |= inst.operands[0].reg;
7349 inst.instruction |= inst.operands[1].reg << 12;
7350 inst.instruction |= inst.operands[2].reg << 16;
7356 inst.instruction |= inst.operands[0].imm;
7362 inst.instruction |= inst.operands[0].reg << 12;
7363 encode_arm_cp_address (1, TRUE, TRUE, 0);
7366 /* ARM instructions, in alphabetical order by function name (except
7367 that wrapper functions appear immediately after the function they
7370 /* This is a pseudo-op of the form "adr rd, label" to be converted
7371 into a relative address of the form "add rd, pc, #label-.-8". */
7376 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7378 /* Frag hacking will turn this into a sub instruction if the offset turns
7379 out to be negative. */
7380 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7381 inst.reloc.pc_rel = 1;
7382 inst.reloc.exp.X_add_number -= 8;
7385 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7386 into a relative address of the form:
7387 add rd, pc, #low(label-.-8)"
7388 add rd, rd, #high(label-.-8)" */
7393 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7395 /* Frag hacking will turn this into a sub instruction if the offset turns
7396 out to be negative. */
7397 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7398 inst.reloc.pc_rel = 1;
7399 inst.size = INSN_SIZE * 2;
7400 inst.reloc.exp.X_add_number -= 8;
7406 if (!inst.operands[1].present)
7407 inst.operands[1].reg = inst.operands[0].reg;
7408 inst.instruction |= inst.operands[0].reg << 12;
7409 inst.instruction |= inst.operands[1].reg << 16;
7410 encode_arm_shifter_operand (2);
7416 if (inst.operands[0].present)
7418 constraint ((inst.instruction & 0xf0) != 0x40
7419 && inst.operands[0].imm > 0xf
7420 && inst.operands[0].imm < 0x0,
7421 _("bad barrier type"));
7422 inst.instruction |= inst.operands[0].imm;
7425 inst.instruction |= 0xf;
7431 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7432 constraint (msb > 32, _("bit-field extends past end of register"));
7433 /* The instruction encoding stores the LSB and MSB,
7434 not the LSB and width. */
7435 inst.instruction |= inst.operands[0].reg << 12;
7436 inst.instruction |= inst.operands[1].imm << 7;
7437 inst.instruction |= (msb - 1) << 16;
7445 /* #0 in second position is alternative syntax for bfc, which is
7446 the same instruction but with REG_PC in the Rm field. */
7447 if (!inst.operands[1].isreg)
7448 inst.operands[1].reg = REG_PC;
7450 msb = inst.operands[2].imm + inst.operands[3].imm;
7451 constraint (msb > 32, _("bit-field extends past end of register"));
7452 /* The instruction encoding stores the LSB and MSB,
7453 not the LSB and width. */
7454 inst.instruction |= inst.operands[0].reg << 12;
7455 inst.instruction |= inst.operands[1].reg;
7456 inst.instruction |= inst.operands[2].imm << 7;
7457 inst.instruction |= (msb - 1) << 16;
7463 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7464 _("bit-field extends past end of register"));
7465 inst.instruction |= inst.operands[0].reg << 12;
7466 inst.instruction |= inst.operands[1].reg;
7467 inst.instruction |= inst.operands[2].imm << 7;
7468 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7471 /* ARM V5 breakpoint instruction (argument parse)
7472 BKPT <16 bit unsigned immediate>
7473 Instruction is not conditional.
7474 The bit pattern given in insns[] has the COND_ALWAYS condition,
7475 and it is an error if the caller tried to override that. */
7480 /* Top 12 of 16 bits to bits 19:8. */
7481 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7483 /* Bottom 4 of 16 bits to bits 3:0. */
7484 inst.instruction |= inst.operands[0].imm & 0xf;
7488 encode_branch (int default_reloc)
7490 if (inst.operands[0].hasreloc)
7492 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7493 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7494 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7495 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7496 ? BFD_RELOC_ARM_PLT32
7497 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7500 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7501 inst.reloc.pc_rel = 1;
7508 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7509 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7512 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7519 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7521 if (inst.cond == COND_ALWAYS)
7522 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7524 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7528 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7531 /* ARM V5 branch-link-exchange instruction (argument parse)
7532 BLX <target_addr> ie BLX(1)
7533 BLX{<condition>} <Rm> ie BLX(2)
7534 Unfortunately, there are two different opcodes for this mnemonic.
7535 So, the insns[].value is not used, and the code here zaps values
7536 into inst.instruction.
7537 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7542 if (inst.operands[0].isreg)
7544 /* Arg is a register; the opcode provided by insns[] is correct.
7545 It is not illegal to do "blx pc", just useless. */
7546 if (inst.operands[0].reg == REG_PC)
7547 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7549 inst.instruction |= inst.operands[0].reg;
7553 /* Arg is an address; this instruction cannot be executed
7554 conditionally, and the opcode must be adjusted.
7555 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7556 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7557 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7558 inst.instruction = 0xfa000000;
7559 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7566 bfd_boolean want_reloc;
7568 if (inst.operands[0].reg == REG_PC)
7569 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7571 inst.instruction |= inst.operands[0].reg;
7572 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7573 it is for ARMv4t or earlier. */
7574 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7575 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7579 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7584 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7588 /* ARM v5TEJ. Jump to Jazelle code. */
7593 if (inst.operands[0].reg == REG_PC)
7594 as_tsktsk (_("use of r15 in bxj is not really useful"));
7596 inst.instruction |= inst.operands[0].reg;
7599 /* Co-processor data operation:
7600 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7601 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7605 inst.instruction |= inst.operands[0].reg << 8;
7606 inst.instruction |= inst.operands[1].imm << 20;
7607 inst.instruction |= inst.operands[2].reg << 12;
7608 inst.instruction |= inst.operands[3].reg << 16;
7609 inst.instruction |= inst.operands[4].reg;
7610 inst.instruction |= inst.operands[5].imm << 5;
7616 inst.instruction |= inst.operands[0].reg << 16;
7617 encode_arm_shifter_operand (1);
7620 /* Transfer between coprocessor and ARM registers.
7621 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7626 No special properties. */
7633 Rd = inst.operands[2].reg;
7636 if (inst.instruction == 0xee000010
7637 || inst.instruction == 0xfe000010)
7639 reject_bad_reg (Rd);
7642 constraint (Rd == REG_SP, BAD_SP);
7647 if (inst.instruction == 0xe000010)
7648 constraint (Rd == REG_PC, BAD_PC);
7652 inst.instruction |= inst.operands[0].reg << 8;
7653 inst.instruction |= inst.operands[1].imm << 21;
7654 inst.instruction |= Rd << 12;
7655 inst.instruction |= inst.operands[3].reg << 16;
7656 inst.instruction |= inst.operands[4].reg;
7657 inst.instruction |= inst.operands[5].imm << 5;
7660 /* Transfer between coprocessor register and pair of ARM registers.
7661 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7666 Two XScale instructions are special cases of these:
7668 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7669 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7671 Result unpredictable if Rd or Rn is R15. */
7678 Rd = inst.operands[2].reg;
7679 Rn = inst.operands[3].reg;
7683 reject_bad_reg (Rd);
7684 reject_bad_reg (Rn);
7688 constraint (Rd == REG_PC, BAD_PC);
7689 constraint (Rn == REG_PC, BAD_PC);
7692 inst.instruction |= inst.operands[0].reg << 8;
7693 inst.instruction |= inst.operands[1].imm << 4;
7694 inst.instruction |= Rd << 12;
7695 inst.instruction |= Rn << 16;
7696 inst.instruction |= inst.operands[4].reg;
7702 inst.instruction |= inst.operands[0].imm << 6;
7703 if (inst.operands[1].present)
7705 inst.instruction |= CPSI_MMOD;
7706 inst.instruction |= inst.operands[1].imm;
7713 inst.instruction |= inst.operands[0].imm;
7719 unsigned Rd, Rn, Rm;
7721 Rd = inst.operands[0].reg;
7722 Rn = (inst.operands[1].present
7723 ? inst.operands[1].reg : Rd);
7724 Rm = inst.operands[2].reg;
7726 constraint ((Rd == REG_PC), BAD_PC);
7727 constraint ((Rn == REG_PC), BAD_PC);
7728 constraint ((Rm == REG_PC), BAD_PC);
7730 inst.instruction |= Rd << 16;
7731 inst.instruction |= Rn << 0;
7732 inst.instruction |= Rm << 8;
7738 /* There is no IT instruction in ARM mode. We
7739 process it to do the validation as if in
7740 thumb mode, just in case the code gets
7741 assembled for thumb using the unified syntax. */
7746 set_it_insn_type (IT_INSN);
7747 now_it.mask = (inst.instruction & 0xf) | 0x10;
7748 now_it.cc = inst.operands[0].imm;
7755 int base_reg = inst.operands[0].reg;
7756 int range = inst.operands[1].imm;
7758 inst.instruction |= base_reg << 16;
7759 inst.instruction |= range;
7761 if (inst.operands[1].writeback)
7762 inst.instruction |= LDM_TYPE_2_OR_3;
7764 if (inst.operands[0].writeback)
7766 inst.instruction |= WRITE_BACK;
7767 /* Check for unpredictable uses of writeback. */
7768 if (inst.instruction & LOAD_BIT)
7770 /* Not allowed in LDM type 2. */
7771 if ((inst.instruction & LDM_TYPE_2_OR_3)
7772 && ((range & (1 << REG_PC)) == 0))
7773 as_warn (_("writeback of base register is UNPREDICTABLE"));
7774 /* Only allowed if base reg not in list for other types. */
7775 else if (range & (1 << base_reg))
7776 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7780 /* Not allowed for type 2. */
7781 if (inst.instruction & LDM_TYPE_2_OR_3)
7782 as_warn (_("writeback of base register is UNPREDICTABLE"));
7783 /* Only allowed if base reg not in list, or first in list. */
7784 else if ((range & (1 << base_reg))
7785 && (range & ((1 << base_reg) - 1)))
7786 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7791 /* ARMv5TE load-consecutive (argument parse)
7800 constraint (inst.operands[0].reg % 2 != 0,
7801 _("first destination register must be even"));
7802 constraint (inst.operands[1].present
7803 && inst.operands[1].reg != inst.operands[0].reg + 1,
7804 _("can only load two consecutive registers"));
7805 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7806 constraint (!inst.operands[2].isreg, _("'[' expected"));
7808 if (!inst.operands[1].present)
7809 inst.operands[1].reg = inst.operands[0].reg + 1;
7811 if (inst.instruction & LOAD_BIT)
7813 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7814 register and the first register written; we have to diagnose
7815 overlap between the base and the second register written here. */
7817 if (inst.operands[2].reg == inst.operands[1].reg
7818 && (inst.operands[2].writeback || inst.operands[2].postind))
7819 as_warn (_("base register written back, and overlaps "
7820 "second destination register"));
7822 /* For an index-register load, the index register must not overlap the
7823 destination (even if not write-back). */
7824 else if (inst.operands[2].immisreg
7825 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7826 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7827 as_warn (_("index register overlaps destination register"));
7830 inst.instruction |= inst.operands[0].reg << 12;
7831 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7837 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7838 || inst.operands[1].postind || inst.operands[1].writeback
7839 || inst.operands[1].immisreg || inst.operands[1].shifted
7840 || inst.operands[1].negative
7841 /* This can arise if the programmer has written
7843 or if they have mistakenly used a register name as the last
7846 It is very difficult to distinguish between these two cases
7847 because "rX" might actually be a label. ie the register
7848 name has been occluded by a symbol of the same name. So we
7849 just generate a general 'bad addressing mode' type error
7850 message and leave it up to the programmer to discover the
7851 true cause and fix their mistake. */
7852 || (inst.operands[1].reg == REG_PC),
7855 constraint (inst.reloc.exp.X_op != O_constant
7856 || inst.reloc.exp.X_add_number != 0,
7857 _("offset must be zero in ARM encoding"));
7859 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7861 inst.instruction |= inst.operands[0].reg << 12;
7862 inst.instruction |= inst.operands[1].reg << 16;
7863 inst.reloc.type = BFD_RELOC_UNUSED;
7869 constraint (inst.operands[0].reg % 2 != 0,
7870 _("even register required"));
7871 constraint (inst.operands[1].present
7872 && inst.operands[1].reg != inst.operands[0].reg + 1,
7873 _("can only load two consecutive registers"));
7874 /* If op 1 were present and equal to PC, this function wouldn't
7875 have been called in the first place. */
7876 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7878 inst.instruction |= inst.operands[0].reg << 12;
7879 inst.instruction |= inst.operands[2].reg << 16;
7885 inst.instruction |= inst.operands[0].reg << 12;
7886 if (!inst.operands[1].isreg)
7887 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7889 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7895 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7897 if (inst.operands[1].preind)
7899 constraint (inst.reloc.exp.X_op != O_constant
7900 || inst.reloc.exp.X_add_number != 0,
7901 _("this instruction requires a post-indexed address"));
7903 inst.operands[1].preind = 0;
7904 inst.operands[1].postind = 1;
7905 inst.operands[1].writeback = 1;
7907 inst.instruction |= inst.operands[0].reg << 12;
7908 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7911 /* Halfword and signed-byte load/store operations. */
7916 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7917 inst.instruction |= inst.operands[0].reg << 12;
7918 if (!inst.operands[1].isreg)
7919 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7921 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7927 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7929 if (inst.operands[1].preind)
7931 constraint (inst.reloc.exp.X_op != O_constant
7932 || inst.reloc.exp.X_add_number != 0,
7933 _("this instruction requires a post-indexed address"));
7935 inst.operands[1].preind = 0;
7936 inst.operands[1].postind = 1;
7937 inst.operands[1].writeback = 1;
7939 inst.instruction |= inst.operands[0].reg << 12;
7940 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7943 /* Co-processor register load/store.
7944 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7948 inst.instruction |= inst.operands[0].reg << 8;
7949 inst.instruction |= inst.operands[1].reg << 12;
7950 encode_arm_cp_address (2, TRUE, TRUE, 0);
7956 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7957 if (inst.operands[0].reg == inst.operands[1].reg
7958 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7959 && !(inst.instruction & 0x00400000))
7960 as_tsktsk (_("Rd and Rm should be different in mla"));
7962 inst.instruction |= inst.operands[0].reg << 16;
7963 inst.instruction |= inst.operands[1].reg;
7964 inst.instruction |= inst.operands[2].reg << 8;
7965 inst.instruction |= inst.operands[3].reg << 12;
7971 inst.instruction |= inst.operands[0].reg << 12;
7972 encode_arm_shifter_operand (1);
7975 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7982 top = (inst.instruction & 0x00400000) != 0;
7983 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7984 _(":lower16: not allowed this instruction"));
7985 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7986 _(":upper16: not allowed instruction"));
7987 inst.instruction |= inst.operands[0].reg << 12;
7988 if (inst.reloc.type == BFD_RELOC_UNUSED)
7990 imm = inst.reloc.exp.X_add_number;
7991 /* The value is in two pieces: 0:11, 16:19. */
7992 inst.instruction |= (imm & 0x00000fff);
7993 inst.instruction |= (imm & 0x0000f000) << 4;
7997 static void do_vfp_nsyn_opcode (const char *);
8000 do_vfp_nsyn_mrs (void)
8002 if (inst.operands[0].isvec)
8004 if (inst.operands[1].reg != 1)
8005 first_error (_("operand 1 must be FPSCR"));
8006 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8007 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8008 do_vfp_nsyn_opcode ("fmstat");
8010 else if (inst.operands[1].isvec)
8011 do_vfp_nsyn_opcode ("fmrx");
8019 do_vfp_nsyn_msr (void)
8021 if (inst.operands[0].isvec)
8022 do_vfp_nsyn_opcode ("fmxr");
8032 unsigned Rt = inst.operands[0].reg;
8034 if (thumb_mode && inst.operands[0].reg == REG_SP)
8036 inst.error = BAD_SP;
8040 /* APSR_ sets isvec. All other refs to PC are illegal. */
8041 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8043 inst.error = BAD_PC;
8047 if (inst.operands[1].reg != 1)
8048 first_error (_("operand 1 must be FPSCR"));
8050 inst.instruction |= (Rt << 12);
8056 unsigned Rt = inst.operands[1].reg;
8059 reject_bad_reg (Rt);
8060 else if (Rt == REG_PC)
8062 inst.error = BAD_PC;
8066 if (inst.operands[0].reg != 1)
8067 first_error (_("operand 0 must be FPSCR"));
8069 inst.instruction |= (Rt << 12);
8077 if (do_vfp_nsyn_mrs () == SUCCESS)
8080 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8081 inst.instruction |= inst.operands[0].reg << 12;
8083 if (inst.operands[1].isreg)
8085 br = inst.operands[1].reg;
8086 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8087 as_bad (_("bad register for mrs"));
8091 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8092 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8094 _("'APSR', 'CPSR' or 'SPSR' expected"));
8095 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8098 inst.instruction |= br;
8101 /* Two possible forms:
8102 "{C|S}PSR_<field>, Rm",
8103 "{C|S}PSR_f, #expression". */
8108 if (do_vfp_nsyn_msr () == SUCCESS)
8111 inst.instruction |= inst.operands[0].imm;
8112 if (inst.operands[1].isreg)
8113 inst.instruction |= inst.operands[1].reg;
8116 inst.instruction |= INST_IMMEDIATE;
8117 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8118 inst.reloc.pc_rel = 0;
8125 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8127 if (!inst.operands[2].present)
8128 inst.operands[2].reg = inst.operands[0].reg;
8129 inst.instruction |= inst.operands[0].reg << 16;
8130 inst.instruction |= inst.operands[1].reg;
8131 inst.instruction |= inst.operands[2].reg << 8;
8133 if (inst.operands[0].reg == inst.operands[1].reg
8134 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8135 as_tsktsk (_("Rd and Rm should be different in mul"));
8138 /* Long Multiply Parser
8139 UMULL RdLo, RdHi, Rm, Rs
8140 SMULL RdLo, RdHi, Rm, Rs
8141 UMLAL RdLo, RdHi, Rm, Rs
8142 SMLAL RdLo, RdHi, Rm, Rs. */
8147 inst.instruction |= inst.operands[0].reg << 12;
8148 inst.instruction |= inst.operands[1].reg << 16;
8149 inst.instruction |= inst.operands[2].reg;
8150 inst.instruction |= inst.operands[3].reg << 8;
8152 /* rdhi and rdlo must be different. */
8153 if (inst.operands[0].reg == inst.operands[1].reg)
8154 as_tsktsk (_("rdhi and rdlo must be different"));
8156 /* rdhi, rdlo and rm must all be different before armv6. */
8157 if ((inst.operands[0].reg == inst.operands[2].reg
8158 || inst.operands[1].reg == inst.operands[2].reg)
8159 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8160 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8166 if (inst.operands[0].present
8167 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8169 /* Architectural NOP hints are CPSR sets with no bits selected. */
8170 inst.instruction &= 0xf0000000;
8171 inst.instruction |= 0x0320f000;
8172 if (inst.operands[0].present)
8173 inst.instruction |= inst.operands[0].imm;
8177 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8178 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8179 Condition defaults to COND_ALWAYS.
8180 Error if Rd, Rn or Rm are R15. */
8185 inst.instruction |= inst.operands[0].reg << 12;
8186 inst.instruction |= inst.operands[1].reg << 16;
8187 inst.instruction |= inst.operands[2].reg;
8188 if (inst.operands[3].present)
8189 encode_arm_shift (3);
8192 /* ARM V6 PKHTB (Argument Parse). */
8197 if (!inst.operands[3].present)
8199 /* If the shift specifier is omitted, turn the instruction
8200 into pkhbt rd, rm, rn. */
8201 inst.instruction &= 0xfff00010;
8202 inst.instruction |= inst.operands[0].reg << 12;
8203 inst.instruction |= inst.operands[1].reg;
8204 inst.instruction |= inst.operands[2].reg << 16;
8208 inst.instruction |= inst.operands[0].reg << 12;
8209 inst.instruction |= inst.operands[1].reg << 16;
8210 inst.instruction |= inst.operands[2].reg;
8211 encode_arm_shift (3);
8215 /* ARMv5TE: Preload-Cache
8216 MP Extensions: Preload for write
8220 Syntactically, like LDR with B=1, W=0, L=1. */
8225 constraint (!inst.operands[0].isreg,
8226 _("'[' expected after PLD mnemonic"));
8227 constraint (inst.operands[0].postind,
8228 _("post-indexed expression used in preload instruction"));
8229 constraint (inst.operands[0].writeback,
8230 _("writeback used in preload instruction"));
8231 constraint (!inst.operands[0].preind,
8232 _("unindexed addressing used in preload instruction"));
8233 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8236 /* ARMv7: PLI <addr_mode> */
8240 constraint (!inst.operands[0].isreg,
8241 _("'[' expected after PLI mnemonic"));
8242 constraint (inst.operands[0].postind,
8243 _("post-indexed expression used in preload instruction"));
8244 constraint (inst.operands[0].writeback,
8245 _("writeback used in preload instruction"));
8246 constraint (!inst.operands[0].preind,
8247 _("unindexed addressing used in preload instruction"));
8248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8249 inst.instruction &= ~PRE_INDEX;
8255 inst.operands[1] = inst.operands[0];
8256 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8257 inst.operands[0].isreg = 1;
8258 inst.operands[0].writeback = 1;
8259 inst.operands[0].reg = REG_SP;
8263 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8264 word at the specified address and the following word
8266 Unconditionally executed.
8267 Error if Rn is R15. */
8272 inst.instruction |= inst.operands[0].reg << 16;
8273 if (inst.operands[0].writeback)
8274 inst.instruction |= WRITE_BACK;
8277 /* ARM V6 ssat (argument parse). */
8282 inst.instruction |= inst.operands[0].reg << 12;
8283 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8284 inst.instruction |= inst.operands[2].reg;
8286 if (inst.operands[3].present)
8287 encode_arm_shift (3);
8290 /* ARM V6 usat (argument parse). */
8295 inst.instruction |= inst.operands[0].reg << 12;
8296 inst.instruction |= inst.operands[1].imm << 16;
8297 inst.instruction |= inst.operands[2].reg;
8299 if (inst.operands[3].present)
8300 encode_arm_shift (3);
8303 /* ARM V6 ssat16 (argument parse). */
8308 inst.instruction |= inst.operands[0].reg << 12;
8309 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8310 inst.instruction |= inst.operands[2].reg;
8316 inst.instruction |= inst.operands[0].reg << 12;
8317 inst.instruction |= inst.operands[1].imm << 16;
8318 inst.instruction |= inst.operands[2].reg;
8321 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8322 preserving the other bits.
8324 setend <endian_specifier>, where <endian_specifier> is either
8330 if (inst.operands[0].imm)
8331 inst.instruction |= 0x200;
8337 unsigned int Rm = (inst.operands[1].present
8338 ? inst.operands[1].reg
8339 : inst.operands[0].reg);
8341 inst.instruction |= inst.operands[0].reg << 12;
8342 inst.instruction |= Rm;
8343 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8345 inst.instruction |= inst.operands[2].reg << 8;
8346 inst.instruction |= SHIFT_BY_REG;
8349 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8355 inst.reloc.type = BFD_RELOC_ARM_SMC;
8356 inst.reloc.pc_rel = 0;
8362 inst.reloc.type = BFD_RELOC_ARM_HVC;
8363 inst.reloc.pc_rel = 0;
8369 inst.reloc.type = BFD_RELOC_ARM_SWI;
8370 inst.reloc.pc_rel = 0;
8373 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8374 SMLAxy{cond} Rd,Rm,Rs,Rn
8375 SMLAWy{cond} Rd,Rm,Rs,Rn
8376 Error if any register is R15. */
8381 inst.instruction |= inst.operands[0].reg << 16;
8382 inst.instruction |= inst.operands[1].reg;
8383 inst.instruction |= inst.operands[2].reg << 8;
8384 inst.instruction |= inst.operands[3].reg << 12;
8387 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8388 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8389 Error if any register is R15.
8390 Warning if Rdlo == Rdhi. */
8395 inst.instruction |= inst.operands[0].reg << 12;
8396 inst.instruction |= inst.operands[1].reg << 16;
8397 inst.instruction |= inst.operands[2].reg;
8398 inst.instruction |= inst.operands[3].reg << 8;
8400 if (inst.operands[0].reg == inst.operands[1].reg)
8401 as_tsktsk (_("rdhi and rdlo must be different"));
8404 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8405 SMULxy{cond} Rd,Rm,Rs
8406 Error if any register is R15. */
8411 inst.instruction |= inst.operands[0].reg << 16;
8412 inst.instruction |= inst.operands[1].reg;
8413 inst.instruction |= inst.operands[2].reg << 8;
8416 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8417 the same for both ARM and Thumb-2. */
8424 if (inst.operands[0].present)
8426 reg = inst.operands[0].reg;
8427 constraint (reg != REG_SP, _("SRS base register must be r13"));
8432 inst.instruction |= reg << 16;
8433 inst.instruction |= inst.operands[1].imm;
8434 if (inst.operands[0].writeback || inst.operands[1].writeback)
8435 inst.instruction |= WRITE_BACK;
8438 /* ARM V6 strex (argument parse). */
8443 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8444 || inst.operands[2].postind || inst.operands[2].writeback
8445 || inst.operands[2].immisreg || inst.operands[2].shifted
8446 || inst.operands[2].negative
8447 /* See comment in do_ldrex(). */
8448 || (inst.operands[2].reg == REG_PC),
8451 constraint (inst.operands[0].reg == inst.operands[1].reg
8452 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8454 constraint (inst.reloc.exp.X_op != O_constant
8455 || inst.reloc.exp.X_add_number != 0,
8456 _("offset must be zero in ARM encoding"));
8458 inst.instruction |= inst.operands[0].reg << 12;
8459 inst.instruction |= inst.operands[1].reg;
8460 inst.instruction |= inst.operands[2].reg << 16;
8461 inst.reloc.type = BFD_RELOC_UNUSED;
8467 constraint (inst.operands[1].reg % 2 != 0,
8468 _("even register required"));
8469 constraint (inst.operands[2].present
8470 && inst.operands[2].reg != inst.operands[1].reg + 1,
8471 _("can only store two consecutive registers"));
8472 /* If op 2 were present and equal to PC, this function wouldn't
8473 have been called in the first place. */
8474 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8476 constraint (inst.operands[0].reg == inst.operands[1].reg
8477 || inst.operands[0].reg == inst.operands[1].reg + 1
8478 || inst.operands[0].reg == inst.operands[3].reg,
8481 inst.instruction |= inst.operands[0].reg << 12;
8482 inst.instruction |= inst.operands[1].reg;
8483 inst.instruction |= inst.operands[3].reg << 16;
8486 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8487 extends it to 32-bits, and adds the result to a value in another
8488 register. You can specify a rotation by 0, 8, 16, or 24 bits
8489 before extracting the 16-bit value.
8490 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8491 Condition defaults to COND_ALWAYS.
8492 Error if any register uses R15. */
8497 inst.instruction |= inst.operands[0].reg << 12;
8498 inst.instruction |= inst.operands[1].reg << 16;
8499 inst.instruction |= inst.operands[2].reg;
8500 inst.instruction |= inst.operands[3].imm << 10;
8505 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8506 Condition defaults to COND_ALWAYS.
8507 Error if any register uses R15. */
8512 inst.instruction |= inst.operands[0].reg << 12;
8513 inst.instruction |= inst.operands[1].reg;
8514 inst.instruction |= inst.operands[2].imm << 10;
8517 /* VFP instructions. In a logical order: SP variant first, monad
8518 before dyad, arithmetic then move then load/store. */
8521 do_vfp_sp_monadic (void)
8523 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8524 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8528 do_vfp_sp_dyadic (void)
8530 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8531 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8532 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8536 do_vfp_sp_compare_z (void)
8538 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8542 do_vfp_dp_sp_cvt (void)
8544 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8545 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8549 do_vfp_sp_dp_cvt (void)
8551 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8552 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8556 do_vfp_reg_from_sp (void)
8558 inst.instruction |= inst.operands[0].reg << 12;
8559 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8563 do_vfp_reg2_from_sp2 (void)
8565 constraint (inst.operands[2].imm != 2,
8566 _("only two consecutive VFP SP registers allowed here"));
8567 inst.instruction |= inst.operands[0].reg << 12;
8568 inst.instruction |= inst.operands[1].reg << 16;
8569 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8573 do_vfp_sp_from_reg (void)
8575 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8576 inst.instruction |= inst.operands[1].reg << 12;
8580 do_vfp_sp2_from_reg2 (void)
8582 constraint (inst.operands[0].imm != 2,
8583 _("only two consecutive VFP SP registers allowed here"));
8584 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8585 inst.instruction |= inst.operands[1].reg << 12;
8586 inst.instruction |= inst.operands[2].reg << 16;
8590 do_vfp_sp_ldst (void)
8592 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8593 encode_arm_cp_address (1, FALSE, TRUE, 0);
8597 do_vfp_dp_ldst (void)
8599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8600 encode_arm_cp_address (1, FALSE, TRUE, 0);
8605 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8607 if (inst.operands[0].writeback)
8608 inst.instruction |= WRITE_BACK;
8610 constraint (ldstm_type != VFP_LDSTMIA,
8611 _("this addressing mode requires base-register writeback"));
8612 inst.instruction |= inst.operands[0].reg << 16;
8613 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8614 inst.instruction |= inst.operands[1].imm;
8618 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8622 if (inst.operands[0].writeback)
8623 inst.instruction |= WRITE_BACK;
8625 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8626 _("this addressing mode requires base-register writeback"));
8628 inst.instruction |= inst.operands[0].reg << 16;
8629 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8631 count = inst.operands[1].imm << 1;
8632 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8635 inst.instruction |= count;
8639 do_vfp_sp_ldstmia (void)
8641 vfp_sp_ldstm (VFP_LDSTMIA);
8645 do_vfp_sp_ldstmdb (void)
8647 vfp_sp_ldstm (VFP_LDSTMDB);
8651 do_vfp_dp_ldstmia (void)
8653 vfp_dp_ldstm (VFP_LDSTMIA);
8657 do_vfp_dp_ldstmdb (void)
8659 vfp_dp_ldstm (VFP_LDSTMDB);
8663 do_vfp_xp_ldstmia (void)
8665 vfp_dp_ldstm (VFP_LDSTMIAX);
8669 do_vfp_xp_ldstmdb (void)
8671 vfp_dp_ldstm (VFP_LDSTMDBX);
8675 do_vfp_dp_rd_rm (void)
8677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8678 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8682 do_vfp_dp_rn_rd (void)
8684 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8685 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8689 do_vfp_dp_rd_rn (void)
8691 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8692 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8696 do_vfp_dp_rd_rn_rm (void)
8698 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8699 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8700 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8706 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8710 do_vfp_dp_rm_rd_rn (void)
8712 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8713 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8714 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8717 /* VFPv3 instructions. */
8719 do_vfp_sp_const (void)
8721 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8722 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8723 inst.instruction |= (inst.operands[1].imm & 0x0f);
8727 do_vfp_dp_const (void)
8729 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8730 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8731 inst.instruction |= (inst.operands[1].imm & 0x0f);
8735 vfp_conv (int srcsize)
8737 unsigned immbits = srcsize - inst.operands[1].imm;
8738 inst.instruction |= (immbits & 1) << 5;
8739 inst.instruction |= (immbits >> 1);
8743 do_vfp_sp_conv_16 (void)
8745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8750 do_vfp_dp_conv_16 (void)
8752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8757 do_vfp_sp_conv_32 (void)
8759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8764 do_vfp_dp_conv_32 (void)
8766 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8770 /* FPA instructions. Also in a logical order. */
8775 inst.instruction |= inst.operands[0].reg << 16;
8776 inst.instruction |= inst.operands[1].reg;
8780 do_fpa_ldmstm (void)
8782 inst.instruction |= inst.operands[0].reg << 12;
8783 switch (inst.operands[1].imm)
8785 case 1: inst.instruction |= CP_T_X; break;
8786 case 2: inst.instruction |= CP_T_Y; break;
8787 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8792 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8794 /* The instruction specified "ea" or "fd", so we can only accept
8795 [Rn]{!}. The instruction does not really support stacking or
8796 unstacking, so we have to emulate these by setting appropriate
8797 bits and offsets. */
8798 constraint (inst.reloc.exp.X_op != O_constant
8799 || inst.reloc.exp.X_add_number != 0,
8800 _("this instruction does not support indexing"));
8802 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8803 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8805 if (!(inst.instruction & INDEX_UP))
8806 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8808 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8810 inst.operands[2].preind = 0;
8811 inst.operands[2].postind = 1;
8815 encode_arm_cp_address (2, TRUE, TRUE, 0);
8818 /* iWMMXt instructions: strictly in alphabetical order. */
8821 do_iwmmxt_tandorc (void)
8823 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8827 do_iwmmxt_textrc (void)
8829 inst.instruction |= inst.operands[0].reg << 12;
8830 inst.instruction |= inst.operands[1].imm;
8834 do_iwmmxt_textrm (void)
8836 inst.instruction |= inst.operands[0].reg << 12;
8837 inst.instruction |= inst.operands[1].reg << 16;
8838 inst.instruction |= inst.operands[2].imm;
8842 do_iwmmxt_tinsr (void)
8844 inst.instruction |= inst.operands[0].reg << 16;
8845 inst.instruction |= inst.operands[1].reg << 12;
8846 inst.instruction |= inst.operands[2].imm;
8850 do_iwmmxt_tmia (void)
8852 inst.instruction |= inst.operands[0].reg << 5;
8853 inst.instruction |= inst.operands[1].reg;
8854 inst.instruction |= inst.operands[2].reg << 12;
8858 do_iwmmxt_waligni (void)
8860 inst.instruction |= inst.operands[0].reg << 12;
8861 inst.instruction |= inst.operands[1].reg << 16;
8862 inst.instruction |= inst.operands[2].reg;
8863 inst.instruction |= inst.operands[3].imm << 20;
8867 do_iwmmxt_wmerge (void)
8869 inst.instruction |= inst.operands[0].reg << 12;
8870 inst.instruction |= inst.operands[1].reg << 16;
8871 inst.instruction |= inst.operands[2].reg;
8872 inst.instruction |= inst.operands[3].imm << 21;
8876 do_iwmmxt_wmov (void)
8878 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8879 inst.instruction |= inst.operands[0].reg << 12;
8880 inst.instruction |= inst.operands[1].reg << 16;
8881 inst.instruction |= inst.operands[1].reg;
8885 do_iwmmxt_wldstbh (void)
8888 inst.instruction |= inst.operands[0].reg << 12;
8890 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8892 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8893 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8897 do_iwmmxt_wldstw (void)
8899 /* RIWR_RIWC clears .isreg for a control register. */
8900 if (!inst.operands[0].isreg)
8902 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8903 inst.instruction |= 0xf0000000;
8906 inst.instruction |= inst.operands[0].reg << 12;
8907 encode_arm_cp_address (1, TRUE, TRUE, 0);
8911 do_iwmmxt_wldstd (void)
8913 inst.instruction |= inst.operands[0].reg << 12;
8914 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
8915 && inst.operands[1].immisreg)
8917 inst.instruction &= ~0x1a000ff;
8918 inst.instruction |= (0xf << 28);
8919 if (inst.operands[1].preind)
8920 inst.instruction |= PRE_INDEX;
8921 if (!inst.operands[1].negative)
8922 inst.instruction |= INDEX_UP;
8923 if (inst.operands[1].writeback)
8924 inst.instruction |= WRITE_BACK;
8925 inst.instruction |= inst.operands[1].reg << 16;
8926 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8927 inst.instruction |= inst.operands[1].imm;
8930 encode_arm_cp_address (1, TRUE, FALSE, 0);
8934 do_iwmmxt_wshufh (void)
8936 inst.instruction |= inst.operands[0].reg << 12;
8937 inst.instruction |= inst.operands[1].reg << 16;
8938 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8939 inst.instruction |= (inst.operands[2].imm & 0x0f);
8943 do_iwmmxt_wzero (void)
8945 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8946 inst.instruction |= inst.operands[0].reg;
8947 inst.instruction |= inst.operands[0].reg << 12;
8948 inst.instruction |= inst.operands[0].reg << 16;
8952 do_iwmmxt_wrwrwr_or_imm5 (void)
8954 if (inst.operands[2].isreg)
8957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8958 _("immediate operand requires iWMMXt2"));
8960 if (inst.operands[2].imm == 0)
8962 switch ((inst.instruction >> 20) & 0xf)
8968 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8969 inst.operands[2].imm = 16;
8970 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8976 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8977 inst.operands[2].imm = 32;
8978 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8985 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8987 wrn = (inst.instruction >> 16) & 0xf;
8988 inst.instruction &= 0xff0fff0f;
8989 inst.instruction |= wrn;
8990 /* Bail out here; the instruction is now assembled. */
8995 /* Map 32 -> 0, etc. */
8996 inst.operands[2].imm &= 0x1f;
8997 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9001 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9002 operations first, then control, shift, and load/store. */
9004 /* Insns like "foo X,Y,Z". */
9007 do_mav_triple (void)
9009 inst.instruction |= inst.operands[0].reg << 16;
9010 inst.instruction |= inst.operands[1].reg;
9011 inst.instruction |= inst.operands[2].reg << 12;
9014 /* Insns like "foo W,X,Y,Z".
9015 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9020 inst.instruction |= inst.operands[0].reg << 5;
9021 inst.instruction |= inst.operands[1].reg << 12;
9022 inst.instruction |= inst.operands[2].reg << 16;
9023 inst.instruction |= inst.operands[3].reg;
9026 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9030 inst.instruction |= inst.operands[1].reg << 12;
9033 /* Maverick shift immediate instructions.
9034 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9035 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9040 int imm = inst.operands[2].imm;
9042 inst.instruction |= inst.operands[0].reg << 12;
9043 inst.instruction |= inst.operands[1].reg << 16;
9045 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9046 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9047 Bit 4 should be 0. */
9048 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9050 inst.instruction |= imm;
9053 /* XScale instructions. Also sorted arithmetic before move. */
9055 /* Xscale multiply-accumulate (argument parse)
9058 MIAxycc acc0,Rm,Rs. */
9063 inst.instruction |= inst.operands[1].reg;
9064 inst.instruction |= inst.operands[2].reg << 12;
9067 /* Xscale move-accumulator-register (argument parse)
9069 MARcc acc0,RdLo,RdHi. */
9074 inst.instruction |= inst.operands[1].reg << 12;
9075 inst.instruction |= inst.operands[2].reg << 16;
9078 /* Xscale move-register-accumulator (argument parse)
9080 MRAcc RdLo,RdHi,acc0. */
9085 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9086 inst.instruction |= inst.operands[0].reg << 12;
9087 inst.instruction |= inst.operands[1].reg << 16;
9090 /* Encoding functions relevant only to Thumb. */
9092 /* inst.operands[i] is a shifted-register operand; encode
9093 it into inst.instruction in the format used by Thumb32. */
9096 encode_thumb32_shifted_operand (int i)
9098 unsigned int value = inst.reloc.exp.X_add_number;
9099 unsigned int shift = inst.operands[i].shift_kind;
9101 constraint (inst.operands[i].immisreg,
9102 _("shift by register not allowed in thumb mode"));
9103 inst.instruction |= inst.operands[i].reg;
9104 if (shift == SHIFT_RRX)
9105 inst.instruction |= SHIFT_ROR << 4;
9108 constraint (inst.reloc.exp.X_op != O_constant,
9109 _("expression too complex"));
9111 constraint (value > 32
9112 || (value == 32 && (shift == SHIFT_LSL
9113 || shift == SHIFT_ROR)),
9114 _("shift expression is too large"));
9118 else if (value == 32)
9121 inst.instruction |= shift << 4;
9122 inst.instruction |= (value & 0x1c) << 10;
9123 inst.instruction |= (value & 0x03) << 6;
9128 /* inst.operands[i] was set up by parse_address. Encode it into a
9129 Thumb32 format load or store instruction. Reject forms that cannot
9130 be used with such instructions. If is_t is true, reject forms that
9131 cannot be used with a T instruction; if is_d is true, reject forms
9132 that cannot be used with a D instruction. If it is a store insn,
9136 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9138 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9140 constraint (!inst.operands[i].isreg,
9141 _("Instruction does not support =N addresses"));
9143 inst.instruction |= inst.operands[i].reg << 16;
9144 if (inst.operands[i].immisreg)
9146 constraint (is_pc, BAD_PC_ADDRESSING);
9147 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9148 constraint (inst.operands[i].negative,
9149 _("Thumb does not support negative register indexing"));
9150 constraint (inst.operands[i].postind,
9151 _("Thumb does not support register post-indexing"));
9152 constraint (inst.operands[i].writeback,
9153 _("Thumb does not support register indexing with writeback"));
9154 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9155 _("Thumb supports only LSL in shifted register indexing"));
9157 inst.instruction |= inst.operands[i].imm;
9158 if (inst.operands[i].shifted)
9160 constraint (inst.reloc.exp.X_op != O_constant,
9161 _("expression too complex"));
9162 constraint (inst.reloc.exp.X_add_number < 0
9163 || inst.reloc.exp.X_add_number > 3,
9164 _("shift out of range"));
9165 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9167 inst.reloc.type = BFD_RELOC_UNUSED;
9169 else if (inst.operands[i].preind)
9171 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9172 constraint (is_t && inst.operands[i].writeback,
9173 _("cannot use writeback with this instruction"));
9174 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9175 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9179 inst.instruction |= 0x01000000;
9180 if (inst.operands[i].writeback)
9181 inst.instruction |= 0x00200000;
9185 inst.instruction |= 0x00000c00;
9186 if (inst.operands[i].writeback)
9187 inst.instruction |= 0x00000100;
9189 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9191 else if (inst.operands[i].postind)
9193 gas_assert (inst.operands[i].writeback);
9194 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9195 constraint (is_t, _("cannot use post-indexing with this instruction"));
9198 inst.instruction |= 0x00200000;
9200 inst.instruction |= 0x00000900;
9201 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9203 else /* unindexed - only for coprocessor */
9204 inst.error = _("instruction does not accept unindexed addressing");
9207 /* Table of Thumb instructions which exist in both 16- and 32-bit
9208 encodings (the latter only in post-V6T2 cores). The index is the
9209 value used in the insns table below. When there is more than one
9210 possible 16-bit encoding for the instruction, this table always
9212 Also contains several pseudo-instructions used during relaxation. */
9213 #define T16_32_TAB \
9214 X(_adc, 4140, eb400000), \
9215 X(_adcs, 4140, eb500000), \
9216 X(_add, 1c00, eb000000), \
9217 X(_adds, 1c00, eb100000), \
9218 X(_addi, 0000, f1000000), \
9219 X(_addis, 0000, f1100000), \
9220 X(_add_pc,000f, f20f0000), \
9221 X(_add_sp,000d, f10d0000), \
9222 X(_adr, 000f, f20f0000), \
9223 X(_and, 4000, ea000000), \
9224 X(_ands, 4000, ea100000), \
9225 X(_asr, 1000, fa40f000), \
9226 X(_asrs, 1000, fa50f000), \
9227 X(_b, e000, f000b000), \
9228 X(_bcond, d000, f0008000), \
9229 X(_bic, 4380, ea200000), \
9230 X(_bics, 4380, ea300000), \
9231 X(_cmn, 42c0, eb100f00), \
9232 X(_cmp, 2800, ebb00f00), \
9233 X(_cpsie, b660, f3af8400), \
9234 X(_cpsid, b670, f3af8600), \
9235 X(_cpy, 4600, ea4f0000), \
9236 X(_dec_sp,80dd, f1ad0d00), \
9237 X(_eor, 4040, ea800000), \
9238 X(_eors, 4040, ea900000), \
9239 X(_inc_sp,00dd, f10d0d00), \
9240 X(_ldmia, c800, e8900000), \
9241 X(_ldr, 6800, f8500000), \
9242 X(_ldrb, 7800, f8100000), \
9243 X(_ldrh, 8800, f8300000), \
9244 X(_ldrsb, 5600, f9100000), \
9245 X(_ldrsh, 5e00, f9300000), \
9246 X(_ldr_pc,4800, f85f0000), \
9247 X(_ldr_pc2,4800, f85f0000), \
9248 X(_ldr_sp,9800, f85d0000), \
9249 X(_lsl, 0000, fa00f000), \
9250 X(_lsls, 0000, fa10f000), \
9251 X(_lsr, 0800, fa20f000), \
9252 X(_lsrs, 0800, fa30f000), \
9253 X(_mov, 2000, ea4f0000), \
9254 X(_movs, 2000, ea5f0000), \
9255 X(_mul, 4340, fb00f000), \
9256 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9257 X(_mvn, 43c0, ea6f0000), \
9258 X(_mvns, 43c0, ea7f0000), \
9259 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9260 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9261 X(_orr, 4300, ea400000), \
9262 X(_orrs, 4300, ea500000), \
9263 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9264 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9265 X(_rev, ba00, fa90f080), \
9266 X(_rev16, ba40, fa90f090), \
9267 X(_revsh, bac0, fa90f0b0), \
9268 X(_ror, 41c0, fa60f000), \
9269 X(_rors, 41c0, fa70f000), \
9270 X(_sbc, 4180, eb600000), \
9271 X(_sbcs, 4180, eb700000), \
9272 X(_stmia, c000, e8800000), \
9273 X(_str, 6000, f8400000), \
9274 X(_strb, 7000, f8000000), \
9275 X(_strh, 8000, f8200000), \
9276 X(_str_sp,9000, f84d0000), \
9277 X(_sub, 1e00, eba00000), \
9278 X(_subs, 1e00, ebb00000), \
9279 X(_subi, 8000, f1a00000), \
9280 X(_subis, 8000, f1b00000), \
9281 X(_sxtb, b240, fa4ff080), \
9282 X(_sxth, b200, fa0ff080), \
9283 X(_tst, 4200, ea100f00), \
9284 X(_uxtb, b2c0, fa5ff080), \
9285 X(_uxth, b280, fa1ff080), \
9286 X(_nop, bf00, f3af8000), \
9287 X(_yield, bf10, f3af8001), \
9288 X(_wfe, bf20, f3af8002), \
9289 X(_wfi, bf30, f3af8003), \
9290 X(_sev, bf40, f3af8004),
9292 /* To catch errors in encoding functions, the codes are all offset by
9293 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9294 as 16-bit instructions. */
9295 #define X(a,b,c) T_MNEM##a
9296 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9299 #define X(a,b,c) 0x##b
9300 static const unsigned short thumb_op16[] = { T16_32_TAB };
9301 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9304 #define X(a,b,c) 0x##c
9305 static const unsigned int thumb_op32[] = { T16_32_TAB };
9306 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9307 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9311 /* Thumb instruction encoders, in alphabetical order. */
9316 do_t_add_sub_w (void)
9320 Rd = inst.operands[0].reg;
9321 Rn = inst.operands[1].reg;
9323 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9324 is the SP-{plus,minus}-immediate form of the instruction. */
9326 constraint (Rd == REG_PC, BAD_PC);
9328 reject_bad_reg (Rd);
9330 inst.instruction |= (Rn << 16) | (Rd << 8);
9331 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9334 /* Parse an add or subtract instruction. We get here with inst.instruction
9335 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9342 Rd = inst.operands[0].reg;
9343 Rs = (inst.operands[1].present
9344 ? inst.operands[1].reg /* Rd, Rs, foo */
9345 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9348 set_it_insn_type_last ();
9356 flags = (inst.instruction == T_MNEM_adds
9357 || inst.instruction == T_MNEM_subs);
9359 narrow = !in_it_block ();
9361 narrow = in_it_block ();
9362 if (!inst.operands[2].isreg)
9366 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9368 add = (inst.instruction == T_MNEM_add
9369 || inst.instruction == T_MNEM_adds);
9371 if (inst.size_req != 4)
9373 /* Attempt to use a narrow opcode, with relaxation if
9375 if (Rd == REG_SP && Rs == REG_SP && !flags)
9376 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9377 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9378 opcode = T_MNEM_add_sp;
9379 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9380 opcode = T_MNEM_add_pc;
9381 else if (Rd <= 7 && Rs <= 7 && narrow)
9384 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9386 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9390 inst.instruction = THUMB_OP16(opcode);
9391 inst.instruction |= (Rd << 4) | Rs;
9392 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9393 if (inst.size_req != 2)
9394 inst.relax = opcode;
9397 constraint (inst.size_req == 2, BAD_HIREG);
9399 if (inst.size_req == 4
9400 || (inst.size_req != 2 && !opcode))
9404 constraint (add, BAD_PC);
9405 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9406 _("only SUBS PC, LR, #const allowed"));
9407 constraint (inst.reloc.exp.X_op != O_constant,
9408 _("expression too complex"));
9409 constraint (inst.reloc.exp.X_add_number < 0
9410 || inst.reloc.exp.X_add_number > 0xff,
9411 _("immediate value out of range"));
9412 inst.instruction = T2_SUBS_PC_LR
9413 | inst.reloc.exp.X_add_number;
9414 inst.reloc.type = BFD_RELOC_UNUSED;
9417 else if (Rs == REG_PC)
9419 /* Always use addw/subw. */
9420 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9421 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9425 inst.instruction = THUMB_OP32 (inst.instruction);
9426 inst.instruction = (inst.instruction & 0xe1ffffff)
9429 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9431 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9433 inst.instruction |= Rd << 8;
9434 inst.instruction |= Rs << 16;
9439 Rn = inst.operands[2].reg;
9440 /* See if we can do this with a 16-bit instruction. */
9441 if (!inst.operands[2].shifted && inst.size_req != 4)
9443 if (Rd > 7 || Rs > 7 || Rn > 7)
9448 inst.instruction = ((inst.instruction == T_MNEM_adds
9449 || inst.instruction == T_MNEM_add)
9452 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9456 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9458 /* Thumb-1 cores (except v6-M) require at least one high
9459 register in a narrow non flag setting add. */
9460 if (Rd > 7 || Rn > 7
9461 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9462 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9469 inst.instruction = T_OPCODE_ADD_HI;
9470 inst.instruction |= (Rd & 8) << 4;
9471 inst.instruction |= (Rd & 7);
9472 inst.instruction |= Rn << 3;
9478 constraint (Rd == REG_PC, BAD_PC);
9479 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9480 constraint (Rs == REG_PC, BAD_PC);
9481 reject_bad_reg (Rn);
9483 /* If we get here, it can't be done in 16 bits. */
9484 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9485 _("shift must be constant"));
9486 inst.instruction = THUMB_OP32 (inst.instruction);
9487 inst.instruction |= Rd << 8;
9488 inst.instruction |= Rs << 16;
9489 encode_thumb32_shifted_operand (2);
9494 constraint (inst.instruction == T_MNEM_adds
9495 || inst.instruction == T_MNEM_subs,
9498 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9500 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9501 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9504 inst.instruction = (inst.instruction == T_MNEM_add
9506 inst.instruction |= (Rd << 4) | Rs;
9507 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9511 Rn = inst.operands[2].reg;
9512 constraint (inst.operands[2].shifted, _("unshifted register required"));
9514 /* We now have Rd, Rs, and Rn set to registers. */
9515 if (Rd > 7 || Rs > 7 || Rn > 7)
9517 /* Can't do this for SUB. */
9518 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9519 inst.instruction = T_OPCODE_ADD_HI;
9520 inst.instruction |= (Rd & 8) << 4;
9521 inst.instruction |= (Rd & 7);
9523 inst.instruction |= Rn << 3;
9525 inst.instruction |= Rs << 3;
9527 constraint (1, _("dest must overlap one source register"));
9531 inst.instruction = (inst.instruction == T_MNEM_add
9532 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9533 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9543 Rd = inst.operands[0].reg;
9544 reject_bad_reg (Rd);
9546 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9548 /* Defer to section relaxation. */
9549 inst.relax = inst.instruction;
9550 inst.instruction = THUMB_OP16 (inst.instruction);
9551 inst.instruction |= Rd << 4;
9553 else if (unified_syntax && inst.size_req != 2)
9555 /* Generate a 32-bit opcode. */
9556 inst.instruction = THUMB_OP32 (inst.instruction);
9557 inst.instruction |= Rd << 8;
9558 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9559 inst.reloc.pc_rel = 1;
9563 /* Generate a 16-bit opcode. */
9564 inst.instruction = THUMB_OP16 (inst.instruction);
9565 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9566 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9567 inst.reloc.pc_rel = 1;
9569 inst.instruction |= Rd << 4;
9573 /* Arithmetic instructions for which there is just one 16-bit
9574 instruction encoding, and it allows only two low registers.
9575 For maximal compatibility with ARM syntax, we allow three register
9576 operands even when Thumb-32 instructions are not available, as long
9577 as the first two are identical. For instance, both "sbc r0,r1" and
9578 "sbc r0,r0,r1" are allowed. */
9584 Rd = inst.operands[0].reg;
9585 Rs = (inst.operands[1].present
9586 ? inst.operands[1].reg /* Rd, Rs, foo */
9587 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9588 Rn = inst.operands[2].reg;
9590 reject_bad_reg (Rd);
9591 reject_bad_reg (Rs);
9592 if (inst.operands[2].isreg)
9593 reject_bad_reg (Rn);
9597 if (!inst.operands[2].isreg)
9599 /* For an immediate, we always generate a 32-bit opcode;
9600 section relaxation will shrink it later if possible. */
9601 inst.instruction = THUMB_OP32 (inst.instruction);
9602 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9603 inst.instruction |= Rd << 8;
9604 inst.instruction |= Rs << 16;
9605 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9611 /* See if we can do this with a 16-bit instruction. */
9612 if (THUMB_SETS_FLAGS (inst.instruction))
9613 narrow = !in_it_block ();
9615 narrow = in_it_block ();
9617 if (Rd > 7 || Rn > 7 || Rs > 7)
9619 if (inst.operands[2].shifted)
9621 if (inst.size_req == 4)
9627 inst.instruction = THUMB_OP16 (inst.instruction);
9628 inst.instruction |= Rd;
9629 inst.instruction |= Rn << 3;
9633 /* If we get here, it can't be done in 16 bits. */
9634 constraint (inst.operands[2].shifted
9635 && inst.operands[2].immisreg,
9636 _("shift must be constant"));
9637 inst.instruction = THUMB_OP32 (inst.instruction);
9638 inst.instruction |= Rd << 8;
9639 inst.instruction |= Rs << 16;
9640 encode_thumb32_shifted_operand (2);
9645 /* On its face this is a lie - the instruction does set the
9646 flags. However, the only supported mnemonic in this mode
9648 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9650 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9651 _("unshifted register required"));
9652 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9653 constraint (Rd != Rs,
9654 _("dest and source1 must be the same register"));
9656 inst.instruction = THUMB_OP16 (inst.instruction);
9657 inst.instruction |= Rd;
9658 inst.instruction |= Rn << 3;
9662 /* Similarly, but for instructions where the arithmetic operation is
9663 commutative, so we can allow either of them to be different from
9664 the destination operand in a 16-bit instruction. For instance, all
9665 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9672 Rd = inst.operands[0].reg;
9673 Rs = (inst.operands[1].present
9674 ? inst.operands[1].reg /* Rd, Rs, foo */
9675 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9676 Rn = inst.operands[2].reg;
9678 reject_bad_reg (Rd);
9679 reject_bad_reg (Rs);
9680 if (inst.operands[2].isreg)
9681 reject_bad_reg (Rn);
9685 if (!inst.operands[2].isreg)
9687 /* For an immediate, we always generate a 32-bit opcode;
9688 section relaxation will shrink it later if possible. */
9689 inst.instruction = THUMB_OP32 (inst.instruction);
9690 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9691 inst.instruction |= Rd << 8;
9692 inst.instruction |= Rs << 16;
9693 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9699 /* See if we can do this with a 16-bit instruction. */
9700 if (THUMB_SETS_FLAGS (inst.instruction))
9701 narrow = !in_it_block ();
9703 narrow = in_it_block ();
9705 if (Rd > 7 || Rn > 7 || Rs > 7)
9707 if (inst.operands[2].shifted)
9709 if (inst.size_req == 4)
9716 inst.instruction = THUMB_OP16 (inst.instruction);
9717 inst.instruction |= Rd;
9718 inst.instruction |= Rn << 3;
9723 inst.instruction = THUMB_OP16 (inst.instruction);
9724 inst.instruction |= Rd;
9725 inst.instruction |= Rs << 3;
9730 /* If we get here, it can't be done in 16 bits. */
9731 constraint (inst.operands[2].shifted
9732 && inst.operands[2].immisreg,
9733 _("shift must be constant"));
9734 inst.instruction = THUMB_OP32 (inst.instruction);
9735 inst.instruction |= Rd << 8;
9736 inst.instruction |= Rs << 16;
9737 encode_thumb32_shifted_operand (2);
9742 /* On its face this is a lie - the instruction does set the
9743 flags. However, the only supported mnemonic in this mode
9745 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9747 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9748 _("unshifted register required"));
9749 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9751 inst.instruction = THUMB_OP16 (inst.instruction);
9752 inst.instruction |= Rd;
9755 inst.instruction |= Rn << 3;
9757 inst.instruction |= Rs << 3;
9759 constraint (1, _("dest must overlap one source register"));
9766 if (inst.operands[0].present)
9768 constraint ((inst.instruction & 0xf0) != 0x40
9769 && inst.operands[0].imm > 0xf
9770 && inst.operands[0].imm < 0x0,
9771 _("bad barrier type"));
9772 inst.instruction |= inst.operands[0].imm;
9775 inst.instruction |= 0xf;
9782 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9783 constraint (msb > 32, _("bit-field extends past end of register"));
9784 /* The instruction encoding stores the LSB and MSB,
9785 not the LSB and width. */
9786 Rd = inst.operands[0].reg;
9787 reject_bad_reg (Rd);
9788 inst.instruction |= Rd << 8;
9789 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9790 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9791 inst.instruction |= msb - 1;
9800 Rd = inst.operands[0].reg;
9801 reject_bad_reg (Rd);
9803 /* #0 in second position is alternative syntax for bfc, which is
9804 the same instruction but with REG_PC in the Rm field. */
9805 if (!inst.operands[1].isreg)
9809 Rn = inst.operands[1].reg;
9810 reject_bad_reg (Rn);
9813 msb = inst.operands[2].imm + inst.operands[3].imm;
9814 constraint (msb > 32, _("bit-field extends past end of register"));
9815 /* The instruction encoding stores the LSB and MSB,
9816 not the LSB and width. */
9817 inst.instruction |= Rd << 8;
9818 inst.instruction |= Rn << 16;
9819 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9820 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9821 inst.instruction |= msb - 1;
9829 Rd = inst.operands[0].reg;
9830 Rn = inst.operands[1].reg;
9832 reject_bad_reg (Rd);
9833 reject_bad_reg (Rn);
9835 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9836 _("bit-field extends past end of register"));
9837 inst.instruction |= Rd << 8;
9838 inst.instruction |= Rn << 16;
9839 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9840 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9841 inst.instruction |= inst.operands[3].imm - 1;
9844 /* ARM V5 Thumb BLX (argument parse)
9845 BLX <target_addr> which is BLX(1)
9846 BLX <Rm> which is BLX(2)
9847 Unfortunately, there are two different opcodes for this mnemonic.
9848 So, the insns[].value is not used, and the code here zaps values
9849 into inst.instruction.
9851 ??? How to take advantage of the additional two bits of displacement
9852 available in Thumb32 mode? Need new relocation? */
9857 set_it_insn_type_last ();
9859 if (inst.operands[0].isreg)
9861 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9862 /* We have a register, so this is BLX(2). */
9863 inst.instruction |= inst.operands[0].reg << 3;
9867 /* No register. This must be BLX(1). */
9868 inst.instruction = 0xf000e800;
9869 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9881 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9885 /* Conditional branches inside IT blocks are encoded as unconditional
9892 if (cond != COND_ALWAYS)
9893 opcode = T_MNEM_bcond;
9895 opcode = inst.instruction;
9898 && (inst.size_req == 4
9899 || (inst.size_req != 2
9900 && (inst.operands[0].hasreloc
9901 || inst.reloc.exp.X_op == O_constant))))
9903 inst.instruction = THUMB_OP32(opcode);
9904 if (cond == COND_ALWAYS)
9905 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
9908 gas_assert (cond != 0xF);
9909 inst.instruction |= cond << 22;
9910 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
9915 inst.instruction = THUMB_OP16(opcode);
9916 if (cond == COND_ALWAYS)
9917 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
9920 inst.instruction |= cond << 8;
9921 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
9923 /* Allow section relaxation. */
9924 if (unified_syntax && inst.size_req != 2)
9925 inst.relax = opcode;
9927 inst.reloc.type = reloc;
9928 inst.reloc.pc_rel = 1;
9934 constraint (inst.cond != COND_ALWAYS,
9935 _("instruction is always unconditional"));
9936 if (inst.operands[0].present)
9938 constraint (inst.operands[0].imm > 255,
9939 _("immediate value out of range"));
9940 inst.instruction |= inst.operands[0].imm;
9941 set_it_insn_type (NEUTRAL_IT_INSN);
9946 do_t_branch23 (void)
9948 set_it_insn_type_last ();
9949 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
9951 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9952 this file. We used to simply ignore the PLT reloc type here --
9953 the branch encoding is now needed to deal with TLSCALL relocs.
9954 So if we see a PLT reloc now, put it back to how it used to be to
9955 keep the preexisting behaviour. */
9956 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
9957 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
9959 #if defined(OBJ_COFF)
9960 /* If the destination of the branch is a defined symbol which does not have
9961 the THUMB_FUNC attribute, then we must be calling a function which has
9962 the (interfacearm) attribute. We look for the Thumb entry point to that
9963 function and change the branch to refer to that function instead. */
9964 if ( inst.reloc.exp.X_op == O_symbol
9965 && inst.reloc.exp.X_add_symbol != NULL
9966 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
9967 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
9968 inst.reloc.exp.X_add_symbol =
9969 find_real_start (inst.reloc.exp.X_add_symbol);
9976 set_it_insn_type_last ();
9977 inst.instruction |= inst.operands[0].reg << 3;
9978 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9979 should cause the alignment to be checked once it is known. This is
9980 because BX PC only works if the instruction is word aligned. */
9988 set_it_insn_type_last ();
9989 Rm = inst.operands[0].reg;
9990 reject_bad_reg (Rm);
9991 inst.instruction |= Rm << 16;
10000 Rd = inst.operands[0].reg;
10001 Rm = inst.operands[1].reg;
10003 reject_bad_reg (Rd);
10004 reject_bad_reg (Rm);
10006 inst.instruction |= Rd << 8;
10007 inst.instruction |= Rm << 16;
10008 inst.instruction |= Rm;
10014 set_it_insn_type (OUTSIDE_IT_INSN);
10015 inst.instruction |= inst.operands[0].imm;
10021 set_it_insn_type (OUTSIDE_IT_INSN);
10023 && (inst.operands[1].present || inst.size_req == 4)
10024 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10026 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10027 inst.instruction = 0xf3af8000;
10028 inst.instruction |= imod << 9;
10029 inst.instruction |= inst.operands[0].imm << 5;
10030 if (inst.operands[1].present)
10031 inst.instruction |= 0x100 | inst.operands[1].imm;
10035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10036 && (inst.operands[0].imm & 4),
10037 _("selected processor does not support 'A' form "
10038 "of this instruction"));
10039 constraint (inst.operands[1].present || inst.size_req == 4,
10040 _("Thumb does not support the 2-argument "
10041 "form of this instruction"));
10042 inst.instruction |= inst.operands[0].imm;
10046 /* THUMB CPY instruction (argument parse). */
10051 if (inst.size_req == 4)
10053 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10054 inst.instruction |= inst.operands[0].reg << 8;
10055 inst.instruction |= inst.operands[1].reg;
10059 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10060 inst.instruction |= (inst.operands[0].reg & 0x7);
10061 inst.instruction |= inst.operands[1].reg << 3;
10068 set_it_insn_type (OUTSIDE_IT_INSN);
10069 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10070 inst.instruction |= inst.operands[0].reg;
10071 inst.reloc.pc_rel = 1;
10072 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10078 inst.instruction |= inst.operands[0].imm;
10084 unsigned Rd, Rn, Rm;
10086 Rd = inst.operands[0].reg;
10087 Rn = (inst.operands[1].present
10088 ? inst.operands[1].reg : Rd);
10089 Rm = inst.operands[2].reg;
10091 reject_bad_reg (Rd);
10092 reject_bad_reg (Rn);
10093 reject_bad_reg (Rm);
10095 inst.instruction |= Rd << 8;
10096 inst.instruction |= Rn << 16;
10097 inst.instruction |= Rm;
10103 if (unified_syntax && inst.size_req == 4)
10104 inst.instruction = THUMB_OP32 (inst.instruction);
10106 inst.instruction = THUMB_OP16 (inst.instruction);
10112 unsigned int cond = inst.operands[0].imm;
10114 set_it_insn_type (IT_INSN);
10115 now_it.mask = (inst.instruction & 0xf) | 0x10;
10118 /* If the condition is a negative condition, invert the mask. */
10119 if ((cond & 0x1) == 0x0)
10121 unsigned int mask = inst.instruction & 0x000f;
10123 if ((mask & 0x7) == 0)
10124 /* no conversion needed */;
10125 else if ((mask & 0x3) == 0)
10127 else if ((mask & 0x1) == 0)
10132 inst.instruction &= 0xfff0;
10133 inst.instruction |= mask;
10136 inst.instruction |= cond << 4;
10139 /* Helper function used for both push/pop and ldm/stm. */
10141 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10145 load = (inst.instruction & (1 << 20)) != 0;
10147 if (mask & (1 << 13))
10148 inst.error = _("SP not allowed in register list");
10150 if ((mask & (1 << base)) != 0
10152 inst.error = _("having the base register in the register list when "
10153 "using write back is UNPREDICTABLE");
10157 if (mask & (1 << 15))
10159 if (mask & (1 << 14))
10160 inst.error = _("LR and PC should not both be in register list");
10162 set_it_insn_type_last ();
10167 if (mask & (1 << 15))
10168 inst.error = _("PC not allowed in register list");
10171 if ((mask & (mask - 1)) == 0)
10173 /* Single register transfers implemented as str/ldr. */
10176 if (inst.instruction & (1 << 23))
10177 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10179 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10183 if (inst.instruction & (1 << 23))
10184 inst.instruction = 0x00800000; /* ia -> [base] */
10186 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10189 inst.instruction |= 0xf8400000;
10191 inst.instruction |= 0x00100000;
10193 mask = ffs (mask) - 1;
10196 else if (writeback)
10197 inst.instruction |= WRITE_BACK;
10199 inst.instruction |= mask;
10200 inst.instruction |= base << 16;
10206 /* This really doesn't seem worth it. */
10207 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10208 _("expression too complex"));
10209 constraint (inst.operands[1].writeback,
10210 _("Thumb load/store multiple does not support {reglist}^"));
10212 if (unified_syntax)
10214 bfd_boolean narrow;
10218 /* See if we can use a 16-bit instruction. */
10219 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10220 && inst.size_req != 4
10221 && !(inst.operands[1].imm & ~0xff))
10223 mask = 1 << inst.operands[0].reg;
10225 if (inst.operands[0].reg <= 7)
10227 if (inst.instruction == T_MNEM_stmia
10228 ? inst.operands[0].writeback
10229 : (inst.operands[0].writeback
10230 == !(inst.operands[1].imm & mask)))
10232 if (inst.instruction == T_MNEM_stmia
10233 && (inst.operands[1].imm & mask)
10234 && (inst.operands[1].imm & (mask - 1)))
10235 as_warn (_("value stored for r%d is UNKNOWN"),
10236 inst.operands[0].reg);
10238 inst.instruction = THUMB_OP16 (inst.instruction);
10239 inst.instruction |= inst.operands[0].reg << 8;
10240 inst.instruction |= inst.operands[1].imm;
10243 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10245 /* This means 1 register in reg list one of 3 situations:
10246 1. Instruction is stmia, but without writeback.
10247 2. lmdia without writeback, but with Rn not in
10249 3. ldmia with writeback, but with Rn in reglist.
10250 Case 3 is UNPREDICTABLE behaviour, so we handle
10251 case 1 and 2 which can be converted into a 16-bit
10252 str or ldr. The SP cases are handled below. */
10253 unsigned long opcode;
10254 /* First, record an error for Case 3. */
10255 if (inst.operands[1].imm & mask
10256 && inst.operands[0].writeback)
10258 _("having the base register in the register list when "
10259 "using write back is UNPREDICTABLE");
10261 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10263 inst.instruction = THUMB_OP16 (opcode);
10264 inst.instruction |= inst.operands[0].reg << 3;
10265 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10269 else if (inst.operands[0] .reg == REG_SP)
10271 if (inst.operands[0].writeback)
10274 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10275 ? T_MNEM_push : T_MNEM_pop);
10276 inst.instruction |= inst.operands[1].imm;
10279 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10282 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10283 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10284 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10292 if (inst.instruction < 0xffff)
10293 inst.instruction = THUMB_OP32 (inst.instruction);
10295 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10296 inst.operands[0].writeback);
10301 constraint (inst.operands[0].reg > 7
10302 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10303 constraint (inst.instruction != T_MNEM_ldmia
10304 && inst.instruction != T_MNEM_stmia,
10305 _("Thumb-2 instruction only valid in unified syntax"));
10306 if (inst.instruction == T_MNEM_stmia)
10308 if (!inst.operands[0].writeback)
10309 as_warn (_("this instruction will write back the base register"));
10310 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10311 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10312 as_warn (_("value stored for r%d is UNKNOWN"),
10313 inst.operands[0].reg);
10317 if (!inst.operands[0].writeback
10318 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10319 as_warn (_("this instruction will write back the base register"));
10320 else if (inst.operands[0].writeback
10321 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10322 as_warn (_("this instruction will not write back the base register"));
10325 inst.instruction = THUMB_OP16 (inst.instruction);
10326 inst.instruction |= inst.operands[0].reg << 8;
10327 inst.instruction |= inst.operands[1].imm;
10334 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10335 || inst.operands[1].postind || inst.operands[1].writeback
10336 || inst.operands[1].immisreg || inst.operands[1].shifted
10337 || inst.operands[1].negative,
10340 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10342 inst.instruction |= inst.operands[0].reg << 12;
10343 inst.instruction |= inst.operands[1].reg << 16;
10344 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10350 if (!inst.operands[1].present)
10352 constraint (inst.operands[0].reg == REG_LR,
10353 _("r14 not allowed as first register "
10354 "when second register is omitted"));
10355 inst.operands[1].reg = inst.operands[0].reg + 1;
10357 constraint (inst.operands[0].reg == inst.operands[1].reg,
10360 inst.instruction |= inst.operands[0].reg << 12;
10361 inst.instruction |= inst.operands[1].reg << 8;
10362 inst.instruction |= inst.operands[2].reg << 16;
10368 unsigned long opcode;
10371 if (inst.operands[0].isreg
10372 && !inst.operands[0].preind
10373 && inst.operands[0].reg == REG_PC)
10374 set_it_insn_type_last ();
10376 opcode = inst.instruction;
10377 if (unified_syntax)
10379 if (!inst.operands[1].isreg)
10381 if (opcode <= 0xffff)
10382 inst.instruction = THUMB_OP32 (opcode);
10383 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10386 if (inst.operands[1].isreg
10387 && !inst.operands[1].writeback
10388 && !inst.operands[1].shifted && !inst.operands[1].postind
10389 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10390 && opcode <= 0xffff
10391 && inst.size_req != 4)
10393 /* Insn may have a 16-bit form. */
10394 Rn = inst.operands[1].reg;
10395 if (inst.operands[1].immisreg)
10397 inst.instruction = THUMB_OP16 (opcode);
10399 if (Rn <= 7 && inst.operands[1].imm <= 7)
10401 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10402 reject_bad_reg (inst.operands[1].imm);
10404 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10405 && opcode != T_MNEM_ldrsb)
10406 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10407 || (Rn == REG_SP && opcode == T_MNEM_str))
10414 if (inst.reloc.pc_rel)
10415 opcode = T_MNEM_ldr_pc2;
10417 opcode = T_MNEM_ldr_pc;
10421 if (opcode == T_MNEM_ldr)
10422 opcode = T_MNEM_ldr_sp;
10424 opcode = T_MNEM_str_sp;
10426 inst.instruction = inst.operands[0].reg << 8;
10430 inst.instruction = inst.operands[0].reg;
10431 inst.instruction |= inst.operands[1].reg << 3;
10433 inst.instruction |= THUMB_OP16 (opcode);
10434 if (inst.size_req == 2)
10435 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10437 inst.relax = opcode;
10441 /* Definitely a 32-bit variant. */
10443 /* Warning for Erratum 752419. */
10444 if (opcode == T_MNEM_ldr
10445 && inst.operands[0].reg == REG_SP
10446 && inst.operands[1].writeback == 1
10447 && !inst.operands[1].immisreg)
10449 if (no_cpu_selected ()
10450 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10451 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10452 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10453 as_warn (_("This instruction may be unpredictable "
10454 "if executed on M-profile cores "
10455 "with interrupts enabled."));
10458 /* Do some validations regarding addressing modes. */
10459 if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
10460 && opcode != T_MNEM_str)
10461 reject_bad_reg (inst.operands[1].imm);
10463 inst.instruction = THUMB_OP32 (opcode);
10464 inst.instruction |= inst.operands[0].reg << 12;
10465 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10469 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10471 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10473 /* Only [Rn,Rm] is acceptable. */
10474 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10475 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10476 || inst.operands[1].postind || inst.operands[1].shifted
10477 || inst.operands[1].negative,
10478 _("Thumb does not support this addressing mode"));
10479 inst.instruction = THUMB_OP16 (inst.instruction);
10483 inst.instruction = THUMB_OP16 (inst.instruction);
10484 if (!inst.operands[1].isreg)
10485 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10488 constraint (!inst.operands[1].preind
10489 || inst.operands[1].shifted
10490 || inst.operands[1].writeback,
10491 _("Thumb does not support this addressing mode"));
10492 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10494 constraint (inst.instruction & 0x0600,
10495 _("byte or halfword not valid for base register"));
10496 constraint (inst.operands[1].reg == REG_PC
10497 && !(inst.instruction & THUMB_LOAD_BIT),
10498 _("r15 based store not allowed"));
10499 constraint (inst.operands[1].immisreg,
10500 _("invalid base register for register offset"));
10502 if (inst.operands[1].reg == REG_PC)
10503 inst.instruction = T_OPCODE_LDR_PC;
10504 else if (inst.instruction & THUMB_LOAD_BIT)
10505 inst.instruction = T_OPCODE_LDR_SP;
10507 inst.instruction = T_OPCODE_STR_SP;
10509 inst.instruction |= inst.operands[0].reg << 8;
10510 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10514 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10515 if (!inst.operands[1].immisreg)
10517 /* Immediate offset. */
10518 inst.instruction |= inst.operands[0].reg;
10519 inst.instruction |= inst.operands[1].reg << 3;
10520 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10524 /* Register offset. */
10525 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10526 constraint (inst.operands[1].negative,
10527 _("Thumb does not support this addressing mode"));
10530 switch (inst.instruction)
10532 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10533 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10534 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10535 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10536 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10537 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10538 case 0x5600 /* ldrsb */:
10539 case 0x5e00 /* ldrsh */: break;
10543 inst.instruction |= inst.operands[0].reg;
10544 inst.instruction |= inst.operands[1].reg << 3;
10545 inst.instruction |= inst.operands[1].imm << 6;
10551 if (!inst.operands[1].present)
10553 inst.operands[1].reg = inst.operands[0].reg + 1;
10554 constraint (inst.operands[0].reg == REG_LR,
10555 _("r14 not allowed here"));
10557 inst.instruction |= inst.operands[0].reg << 12;
10558 inst.instruction |= inst.operands[1].reg << 8;
10559 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10565 inst.instruction |= inst.operands[0].reg << 12;
10566 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10572 unsigned Rd, Rn, Rm, Ra;
10574 Rd = inst.operands[0].reg;
10575 Rn = inst.operands[1].reg;
10576 Rm = inst.operands[2].reg;
10577 Ra = inst.operands[3].reg;
10579 reject_bad_reg (Rd);
10580 reject_bad_reg (Rn);
10581 reject_bad_reg (Rm);
10582 reject_bad_reg (Ra);
10584 inst.instruction |= Rd << 8;
10585 inst.instruction |= Rn << 16;
10586 inst.instruction |= Rm;
10587 inst.instruction |= Ra << 12;
10593 unsigned RdLo, RdHi, Rn, Rm;
10595 RdLo = inst.operands[0].reg;
10596 RdHi = inst.operands[1].reg;
10597 Rn = inst.operands[2].reg;
10598 Rm = inst.operands[3].reg;
10600 reject_bad_reg (RdLo);
10601 reject_bad_reg (RdHi);
10602 reject_bad_reg (Rn);
10603 reject_bad_reg (Rm);
10605 inst.instruction |= RdLo << 12;
10606 inst.instruction |= RdHi << 8;
10607 inst.instruction |= Rn << 16;
10608 inst.instruction |= Rm;
10612 do_t_mov_cmp (void)
10616 Rn = inst.operands[0].reg;
10617 Rm = inst.operands[1].reg;
10620 set_it_insn_type_last ();
10622 if (unified_syntax)
10624 int r0off = (inst.instruction == T_MNEM_mov
10625 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10626 unsigned long opcode;
10627 bfd_boolean narrow;
10628 bfd_boolean low_regs;
10630 low_regs = (Rn <= 7 && Rm <= 7);
10631 opcode = inst.instruction;
10632 if (in_it_block ())
10633 narrow = opcode != T_MNEM_movs;
10635 narrow = opcode != T_MNEM_movs || low_regs;
10636 if (inst.size_req == 4
10637 || inst.operands[1].shifted)
10640 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10641 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10642 && !inst.operands[1].shifted
10646 inst.instruction = T2_SUBS_PC_LR;
10650 if (opcode == T_MNEM_cmp)
10652 constraint (Rn == REG_PC, BAD_PC);
10655 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10657 warn_deprecated_sp (Rm);
10658 /* R15 was documented as a valid choice for Rm in ARMv6,
10659 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10660 tools reject R15, so we do too. */
10661 constraint (Rm == REG_PC, BAD_PC);
10664 reject_bad_reg (Rm);
10666 else if (opcode == T_MNEM_mov
10667 || opcode == T_MNEM_movs)
10669 if (inst.operands[1].isreg)
10671 if (opcode == T_MNEM_movs)
10673 reject_bad_reg (Rn);
10674 reject_bad_reg (Rm);
10678 /* This is mov.n. */
10679 if ((Rn == REG_SP || Rn == REG_PC)
10680 && (Rm == REG_SP || Rm == REG_PC))
10682 as_warn (_("Use of r%u as a source register is "
10683 "deprecated when r%u is the destination "
10684 "register."), Rm, Rn);
10689 /* This is mov.w. */
10690 constraint (Rn == REG_PC, BAD_PC);
10691 constraint (Rm == REG_PC, BAD_PC);
10692 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10696 reject_bad_reg (Rn);
10699 if (!inst.operands[1].isreg)
10701 /* Immediate operand. */
10702 if (!in_it_block () && opcode == T_MNEM_mov)
10704 if (low_regs && narrow)
10706 inst.instruction = THUMB_OP16 (opcode);
10707 inst.instruction |= Rn << 8;
10708 if (inst.size_req == 2)
10709 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10711 inst.relax = opcode;
10715 inst.instruction = THUMB_OP32 (inst.instruction);
10716 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10717 inst.instruction |= Rn << r0off;
10718 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10721 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10722 && (inst.instruction == T_MNEM_mov
10723 || inst.instruction == T_MNEM_movs))
10725 /* Register shifts are encoded as separate shift instructions. */
10726 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10728 if (in_it_block ())
10733 if (inst.size_req == 4)
10736 if (!low_regs || inst.operands[1].imm > 7)
10742 switch (inst.operands[1].shift_kind)
10745 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10748 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10751 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10754 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10760 inst.instruction = opcode;
10763 inst.instruction |= Rn;
10764 inst.instruction |= inst.operands[1].imm << 3;
10769 inst.instruction |= CONDS_BIT;
10771 inst.instruction |= Rn << 8;
10772 inst.instruction |= Rm << 16;
10773 inst.instruction |= inst.operands[1].imm;
10778 /* Some mov with immediate shift have narrow variants.
10779 Register shifts are handled above. */
10780 if (low_regs && inst.operands[1].shifted
10781 && (inst.instruction == T_MNEM_mov
10782 || inst.instruction == T_MNEM_movs))
10784 if (in_it_block ())
10785 narrow = (inst.instruction == T_MNEM_mov);
10787 narrow = (inst.instruction == T_MNEM_movs);
10792 switch (inst.operands[1].shift_kind)
10794 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10795 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10796 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10797 default: narrow = FALSE; break;
10803 inst.instruction |= Rn;
10804 inst.instruction |= Rm << 3;
10805 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10809 inst.instruction = THUMB_OP32 (inst.instruction);
10810 inst.instruction |= Rn << r0off;
10811 encode_thumb32_shifted_operand (1);
10815 switch (inst.instruction)
10818 inst.instruction = T_OPCODE_MOV_HR;
10819 inst.instruction |= (Rn & 0x8) << 4;
10820 inst.instruction |= (Rn & 0x7);
10821 inst.instruction |= Rm << 3;
10825 /* We know we have low registers at this point.
10826 Generate LSLS Rd, Rs, #0. */
10827 inst.instruction = T_OPCODE_LSL_I;
10828 inst.instruction |= Rn;
10829 inst.instruction |= Rm << 3;
10835 inst.instruction = T_OPCODE_CMP_LR;
10836 inst.instruction |= Rn;
10837 inst.instruction |= Rm << 3;
10841 inst.instruction = T_OPCODE_CMP_HR;
10842 inst.instruction |= (Rn & 0x8) << 4;
10843 inst.instruction |= (Rn & 0x7);
10844 inst.instruction |= Rm << 3;
10851 inst.instruction = THUMB_OP16 (inst.instruction);
10853 /* PR 10443: Do not silently ignore shifted operands. */
10854 constraint (inst.operands[1].shifted,
10855 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10857 if (inst.operands[1].isreg)
10859 if (Rn < 8 && Rm < 8)
10861 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10862 since a MOV instruction produces unpredictable results. */
10863 if (inst.instruction == T_OPCODE_MOV_I8)
10864 inst.instruction = T_OPCODE_ADD_I3;
10866 inst.instruction = T_OPCODE_CMP_LR;
10868 inst.instruction |= Rn;
10869 inst.instruction |= Rm << 3;
10873 if (inst.instruction == T_OPCODE_MOV_I8)
10874 inst.instruction = T_OPCODE_MOV_HR;
10876 inst.instruction = T_OPCODE_CMP_HR;
10882 constraint (Rn > 7,
10883 _("only lo regs allowed with immediate"));
10884 inst.instruction |= Rn << 8;
10885 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10896 top = (inst.instruction & 0x00800000) != 0;
10897 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10899 constraint (top, _(":lower16: not allowed this instruction"));
10900 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10902 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
10904 constraint (!top, _(":upper16: not allowed this instruction"));
10905 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
10908 Rd = inst.operands[0].reg;
10909 reject_bad_reg (Rd);
10911 inst.instruction |= Rd << 8;
10912 if (inst.reloc.type == BFD_RELOC_UNUSED)
10914 imm = inst.reloc.exp.X_add_number;
10915 inst.instruction |= (imm & 0xf000) << 4;
10916 inst.instruction |= (imm & 0x0800) << 15;
10917 inst.instruction |= (imm & 0x0700) << 4;
10918 inst.instruction |= (imm & 0x00ff);
10923 do_t_mvn_tst (void)
10927 Rn = inst.operands[0].reg;
10928 Rm = inst.operands[1].reg;
10930 if (inst.instruction == T_MNEM_cmp
10931 || inst.instruction == T_MNEM_cmn)
10932 constraint (Rn == REG_PC, BAD_PC);
10934 reject_bad_reg (Rn);
10935 reject_bad_reg (Rm);
10937 if (unified_syntax)
10939 int r0off = (inst.instruction == T_MNEM_mvn
10940 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
10941 bfd_boolean narrow;
10943 if (inst.size_req == 4
10944 || inst.instruction > 0xffff
10945 || inst.operands[1].shifted
10946 || Rn > 7 || Rm > 7)
10948 else if (inst.instruction == T_MNEM_cmn)
10950 else if (THUMB_SETS_FLAGS (inst.instruction))
10951 narrow = !in_it_block ();
10953 narrow = in_it_block ();
10955 if (!inst.operands[1].isreg)
10957 /* For an immediate, we always generate a 32-bit opcode;
10958 section relaxation will shrink it later if possible. */
10959 if (inst.instruction < 0xffff)
10960 inst.instruction = THUMB_OP32 (inst.instruction);
10961 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10962 inst.instruction |= Rn << r0off;
10963 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10967 /* See if we can do this with a 16-bit instruction. */
10970 inst.instruction = THUMB_OP16 (inst.instruction);
10971 inst.instruction |= Rn;
10972 inst.instruction |= Rm << 3;
10976 constraint (inst.operands[1].shifted
10977 && inst.operands[1].immisreg,
10978 _("shift must be constant"));
10979 if (inst.instruction < 0xffff)
10980 inst.instruction = THUMB_OP32 (inst.instruction);
10981 inst.instruction |= Rn << r0off;
10982 encode_thumb32_shifted_operand (1);
10988 constraint (inst.instruction > 0xffff
10989 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
10990 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
10991 _("unshifted register required"));
10992 constraint (Rn > 7 || Rm > 7,
10995 inst.instruction = THUMB_OP16 (inst.instruction);
10996 inst.instruction |= Rn;
10997 inst.instruction |= Rm << 3;
11006 if (do_vfp_nsyn_mrs () == SUCCESS)
11009 Rd = inst.operands[0].reg;
11010 reject_bad_reg (Rd);
11011 inst.instruction |= Rd << 8;
11013 if (inst.operands[1].isreg)
11015 unsigned br = inst.operands[1].reg;
11016 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11017 as_bad (_("bad register for mrs"));
11019 inst.instruction |= br & (0xf << 16);
11020 inst.instruction |= (br & 0x300) >> 4;
11021 inst.instruction |= (br & SPSR_BIT) >> 2;
11025 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11027 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11028 constraint (flags != 0, _("selected processor does not support "
11029 "requested special purpose register"));
11031 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11033 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11034 _("'APSR', 'CPSR' or 'SPSR' expected"));
11036 inst.instruction |= (flags & SPSR_BIT) >> 2;
11037 inst.instruction |= inst.operands[1].imm & 0xff;
11038 inst.instruction |= 0xf0000;
11048 if (do_vfp_nsyn_msr () == SUCCESS)
11051 constraint (!inst.operands[1].isreg,
11052 _("Thumb encoding does not support an immediate here"));
11054 if (inst.operands[0].isreg)
11055 flags = (int)(inst.operands[0].reg);
11057 flags = inst.operands[0].imm;
11059 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11061 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11063 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11064 && (bits & ~(PSR_s | PSR_f)) != 0)
11065 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11067 _("selected processor does not support requested special "
11068 "purpose register"));
11071 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11072 "requested special purpose register"));
11074 Rn = inst.operands[1].reg;
11075 reject_bad_reg (Rn);
11077 inst.instruction |= (flags & SPSR_BIT) >> 2;
11078 inst.instruction |= (flags & 0xf0000) >> 8;
11079 inst.instruction |= (flags & 0x300) >> 4;
11080 inst.instruction |= (flags & 0xff);
11081 inst.instruction |= Rn << 16;
11087 bfd_boolean narrow;
11088 unsigned Rd, Rn, Rm;
11090 if (!inst.operands[2].present)
11091 inst.operands[2].reg = inst.operands[0].reg;
11093 Rd = inst.operands[0].reg;
11094 Rn = inst.operands[1].reg;
11095 Rm = inst.operands[2].reg;
11097 if (unified_syntax)
11099 if (inst.size_req == 4
11105 else if (inst.instruction == T_MNEM_muls)
11106 narrow = !in_it_block ();
11108 narrow = in_it_block ();
11112 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11113 constraint (Rn > 7 || Rm > 7,
11120 /* 16-bit MULS/Conditional MUL. */
11121 inst.instruction = THUMB_OP16 (inst.instruction);
11122 inst.instruction |= Rd;
11125 inst.instruction |= Rm << 3;
11127 inst.instruction |= Rn << 3;
11129 constraint (1, _("dest must overlap one source register"));
11133 constraint (inst.instruction != T_MNEM_mul,
11134 _("Thumb-2 MUL must not set flags"));
11136 inst.instruction = THUMB_OP32 (inst.instruction);
11137 inst.instruction |= Rd << 8;
11138 inst.instruction |= Rn << 16;
11139 inst.instruction |= Rm << 0;
11141 reject_bad_reg (Rd);
11142 reject_bad_reg (Rn);
11143 reject_bad_reg (Rm);
11150 unsigned RdLo, RdHi, Rn, Rm;
11152 RdLo = inst.operands[0].reg;
11153 RdHi = inst.operands[1].reg;
11154 Rn = inst.operands[2].reg;
11155 Rm = inst.operands[3].reg;
11157 reject_bad_reg (RdLo);
11158 reject_bad_reg (RdHi);
11159 reject_bad_reg (Rn);
11160 reject_bad_reg (Rm);
11162 inst.instruction |= RdLo << 12;
11163 inst.instruction |= RdHi << 8;
11164 inst.instruction |= Rn << 16;
11165 inst.instruction |= Rm;
11168 as_tsktsk (_("rdhi and rdlo must be different"));
11174 set_it_insn_type (NEUTRAL_IT_INSN);
11176 if (unified_syntax)
11178 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11180 inst.instruction = THUMB_OP32 (inst.instruction);
11181 inst.instruction |= inst.operands[0].imm;
11185 /* PR9722: Check for Thumb2 availability before
11186 generating a thumb2 nop instruction. */
11187 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11189 inst.instruction = THUMB_OP16 (inst.instruction);
11190 inst.instruction |= inst.operands[0].imm << 4;
11193 inst.instruction = 0x46c0;
11198 constraint (inst.operands[0].present,
11199 _("Thumb does not support NOP with hints"));
11200 inst.instruction = 0x46c0;
11207 if (unified_syntax)
11209 bfd_boolean narrow;
11211 if (THUMB_SETS_FLAGS (inst.instruction))
11212 narrow = !in_it_block ();
11214 narrow = in_it_block ();
11215 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11217 if (inst.size_req == 4)
11222 inst.instruction = THUMB_OP32 (inst.instruction);
11223 inst.instruction |= inst.operands[0].reg << 8;
11224 inst.instruction |= inst.operands[1].reg << 16;
11228 inst.instruction = THUMB_OP16 (inst.instruction);
11229 inst.instruction |= inst.operands[0].reg;
11230 inst.instruction |= inst.operands[1].reg << 3;
11235 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11237 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11239 inst.instruction = THUMB_OP16 (inst.instruction);
11240 inst.instruction |= inst.operands[0].reg;
11241 inst.instruction |= inst.operands[1].reg << 3;
11250 Rd = inst.operands[0].reg;
11251 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11253 reject_bad_reg (Rd);
11254 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11255 reject_bad_reg (Rn);
11257 inst.instruction |= Rd << 8;
11258 inst.instruction |= Rn << 16;
11260 if (!inst.operands[2].isreg)
11262 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11263 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11269 Rm = inst.operands[2].reg;
11270 reject_bad_reg (Rm);
11272 constraint (inst.operands[2].shifted
11273 && inst.operands[2].immisreg,
11274 _("shift must be constant"));
11275 encode_thumb32_shifted_operand (2);
11282 unsigned Rd, Rn, Rm;
11284 Rd = inst.operands[0].reg;
11285 Rn = inst.operands[1].reg;
11286 Rm = inst.operands[2].reg;
11288 reject_bad_reg (Rd);
11289 reject_bad_reg (Rn);
11290 reject_bad_reg (Rm);
11292 inst.instruction |= Rd << 8;
11293 inst.instruction |= Rn << 16;
11294 inst.instruction |= Rm;
11295 if (inst.operands[3].present)
11297 unsigned int val = inst.reloc.exp.X_add_number;
11298 constraint (inst.reloc.exp.X_op != O_constant,
11299 _("expression too complex"));
11300 inst.instruction |= (val & 0x1c) << 10;
11301 inst.instruction |= (val & 0x03) << 6;
11308 if (!inst.operands[3].present)
11312 inst.instruction &= ~0x00000020;
11314 /* PR 10168. Swap the Rm and Rn registers. */
11315 Rtmp = inst.operands[1].reg;
11316 inst.operands[1].reg = inst.operands[2].reg;
11317 inst.operands[2].reg = Rtmp;
11325 if (inst.operands[0].immisreg)
11326 reject_bad_reg (inst.operands[0].imm);
11328 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11332 do_t_push_pop (void)
11336 constraint (inst.operands[0].writeback,
11337 _("push/pop do not support {reglist}^"));
11338 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11339 _("expression too complex"));
11341 mask = inst.operands[0].imm;
11342 if ((mask & ~0xff) == 0)
11343 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11344 else if ((inst.instruction == T_MNEM_push
11345 && (mask & ~0xff) == 1 << REG_LR)
11346 || (inst.instruction == T_MNEM_pop
11347 && (mask & ~0xff) == 1 << REG_PC))
11349 inst.instruction = THUMB_OP16 (inst.instruction);
11350 inst.instruction |= THUMB_PP_PC_LR;
11351 inst.instruction |= mask & 0xff;
11353 else if (unified_syntax)
11355 inst.instruction = THUMB_OP32 (inst.instruction);
11356 encode_thumb2_ldmstm (13, mask, TRUE);
11360 inst.error = _("invalid register list to push/pop instruction");
11370 Rd = inst.operands[0].reg;
11371 Rm = inst.operands[1].reg;
11373 reject_bad_reg (Rd);
11374 reject_bad_reg (Rm);
11376 inst.instruction |= Rd << 8;
11377 inst.instruction |= Rm << 16;
11378 inst.instruction |= Rm;
11386 Rd = inst.operands[0].reg;
11387 Rm = inst.operands[1].reg;
11389 reject_bad_reg (Rd);
11390 reject_bad_reg (Rm);
11392 if (Rd <= 7 && Rm <= 7
11393 && inst.size_req != 4)
11395 inst.instruction = THUMB_OP16 (inst.instruction);
11396 inst.instruction |= Rd;
11397 inst.instruction |= Rm << 3;
11399 else if (unified_syntax)
11401 inst.instruction = THUMB_OP32 (inst.instruction);
11402 inst.instruction |= Rd << 8;
11403 inst.instruction |= Rm << 16;
11404 inst.instruction |= Rm;
11407 inst.error = BAD_HIREG;
11415 Rd = inst.operands[0].reg;
11416 Rm = inst.operands[1].reg;
11418 reject_bad_reg (Rd);
11419 reject_bad_reg (Rm);
11421 inst.instruction |= Rd << 8;
11422 inst.instruction |= Rm;
11430 Rd = inst.operands[0].reg;
11431 Rs = (inst.operands[1].present
11432 ? inst.operands[1].reg /* Rd, Rs, foo */
11433 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11435 reject_bad_reg (Rd);
11436 reject_bad_reg (Rs);
11437 if (inst.operands[2].isreg)
11438 reject_bad_reg (inst.operands[2].reg);
11440 inst.instruction |= Rd << 8;
11441 inst.instruction |= Rs << 16;
11442 if (!inst.operands[2].isreg)
11444 bfd_boolean narrow;
11446 if ((inst.instruction & 0x00100000) != 0)
11447 narrow = !in_it_block ();
11449 narrow = in_it_block ();
11451 if (Rd > 7 || Rs > 7)
11454 if (inst.size_req == 4 || !unified_syntax)
11457 if (inst.reloc.exp.X_op != O_constant
11458 || inst.reloc.exp.X_add_number != 0)
11461 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11462 relaxation, but it doesn't seem worth the hassle. */
11465 inst.reloc.type = BFD_RELOC_UNUSED;
11466 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11467 inst.instruction |= Rs << 3;
11468 inst.instruction |= Rd;
11472 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11473 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11477 encode_thumb32_shifted_operand (2);
11483 set_it_insn_type (OUTSIDE_IT_INSN);
11484 if (inst.operands[0].imm)
11485 inst.instruction |= 0x8;
11491 if (!inst.operands[1].present)
11492 inst.operands[1].reg = inst.operands[0].reg;
11494 if (unified_syntax)
11496 bfd_boolean narrow;
11499 switch (inst.instruction)
11502 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11504 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11506 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11508 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11512 if (THUMB_SETS_FLAGS (inst.instruction))
11513 narrow = !in_it_block ();
11515 narrow = in_it_block ();
11516 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11518 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11520 if (inst.operands[2].isreg
11521 && (inst.operands[1].reg != inst.operands[0].reg
11522 || inst.operands[2].reg > 7))
11524 if (inst.size_req == 4)
11527 reject_bad_reg (inst.operands[0].reg);
11528 reject_bad_reg (inst.operands[1].reg);
11532 if (inst.operands[2].isreg)
11534 reject_bad_reg (inst.operands[2].reg);
11535 inst.instruction = THUMB_OP32 (inst.instruction);
11536 inst.instruction |= inst.operands[0].reg << 8;
11537 inst.instruction |= inst.operands[1].reg << 16;
11538 inst.instruction |= inst.operands[2].reg;
11542 inst.operands[1].shifted = 1;
11543 inst.operands[1].shift_kind = shift_kind;
11544 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11545 ? T_MNEM_movs : T_MNEM_mov);
11546 inst.instruction |= inst.operands[0].reg << 8;
11547 encode_thumb32_shifted_operand (1);
11548 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11549 inst.reloc.type = BFD_RELOC_UNUSED;
11554 if (inst.operands[2].isreg)
11556 switch (shift_kind)
11558 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11559 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11560 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11561 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11565 inst.instruction |= inst.operands[0].reg;
11566 inst.instruction |= inst.operands[2].reg << 3;
11570 switch (shift_kind)
11572 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11573 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11574 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11577 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11578 inst.instruction |= inst.operands[0].reg;
11579 inst.instruction |= inst.operands[1].reg << 3;
11585 constraint (inst.operands[0].reg > 7
11586 || inst.operands[1].reg > 7, BAD_HIREG);
11587 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11589 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11591 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11592 constraint (inst.operands[0].reg != inst.operands[1].reg,
11593 _("source1 and dest must be same register"));
11595 switch (inst.instruction)
11597 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11598 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11599 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11600 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11604 inst.instruction |= inst.operands[0].reg;
11605 inst.instruction |= inst.operands[2].reg << 3;
11609 switch (inst.instruction)
11611 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11612 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11613 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11614 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11617 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11618 inst.instruction |= inst.operands[0].reg;
11619 inst.instruction |= inst.operands[1].reg << 3;
11627 unsigned Rd, Rn, Rm;
11629 Rd = inst.operands[0].reg;
11630 Rn = inst.operands[1].reg;
11631 Rm = inst.operands[2].reg;
11633 reject_bad_reg (Rd);
11634 reject_bad_reg (Rn);
11635 reject_bad_reg (Rm);
11637 inst.instruction |= Rd << 8;
11638 inst.instruction |= Rn << 16;
11639 inst.instruction |= Rm;
11645 unsigned Rd, Rn, Rm;
11647 Rd = inst.operands[0].reg;
11648 Rm = inst.operands[1].reg;
11649 Rn = inst.operands[2].reg;
11651 reject_bad_reg (Rd);
11652 reject_bad_reg (Rn);
11653 reject_bad_reg (Rm);
11655 inst.instruction |= Rd << 8;
11656 inst.instruction |= Rn << 16;
11657 inst.instruction |= Rm;
11663 unsigned int value = inst.reloc.exp.X_add_number;
11664 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11665 _("SMC is not permitted on this architecture"));
11666 constraint (inst.reloc.exp.X_op != O_constant,
11667 _("expression too complex"));
11668 inst.reloc.type = BFD_RELOC_UNUSED;
11669 inst.instruction |= (value & 0xf000) >> 12;
11670 inst.instruction |= (value & 0x0ff0);
11671 inst.instruction |= (value & 0x000f) << 16;
11677 unsigned int value = inst.reloc.exp.X_add_number;
11679 inst.reloc.type = BFD_RELOC_UNUSED;
11680 inst.instruction |= (value & 0x0fff);
11681 inst.instruction |= (value & 0xf000) << 4;
11685 do_t_ssat_usat (int bias)
11689 Rd = inst.operands[0].reg;
11690 Rn = inst.operands[2].reg;
11692 reject_bad_reg (Rd);
11693 reject_bad_reg (Rn);
11695 inst.instruction |= Rd << 8;
11696 inst.instruction |= inst.operands[1].imm - bias;
11697 inst.instruction |= Rn << 16;
11699 if (inst.operands[3].present)
11701 offsetT shift_amount = inst.reloc.exp.X_add_number;
11703 inst.reloc.type = BFD_RELOC_UNUSED;
11705 constraint (inst.reloc.exp.X_op != O_constant,
11706 _("expression too complex"));
11708 if (shift_amount != 0)
11710 constraint (shift_amount > 31,
11711 _("shift expression is too large"));
11713 if (inst.operands[3].shift_kind == SHIFT_ASR)
11714 inst.instruction |= 0x00200000; /* sh bit. */
11716 inst.instruction |= (shift_amount & 0x1c) << 10;
11717 inst.instruction |= (shift_amount & 0x03) << 6;
11725 do_t_ssat_usat (1);
11733 Rd = inst.operands[0].reg;
11734 Rn = inst.operands[2].reg;
11736 reject_bad_reg (Rd);
11737 reject_bad_reg (Rn);
11739 inst.instruction |= Rd << 8;
11740 inst.instruction |= inst.operands[1].imm - 1;
11741 inst.instruction |= Rn << 16;
11747 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11748 || inst.operands[2].postind || inst.operands[2].writeback
11749 || inst.operands[2].immisreg || inst.operands[2].shifted
11750 || inst.operands[2].negative,
11753 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11755 inst.instruction |= inst.operands[0].reg << 8;
11756 inst.instruction |= inst.operands[1].reg << 12;
11757 inst.instruction |= inst.operands[2].reg << 16;
11758 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11764 if (!inst.operands[2].present)
11765 inst.operands[2].reg = inst.operands[1].reg + 1;
11767 constraint (inst.operands[0].reg == inst.operands[1].reg
11768 || inst.operands[0].reg == inst.operands[2].reg
11769 || inst.operands[0].reg == inst.operands[3].reg,
11772 inst.instruction |= inst.operands[0].reg;
11773 inst.instruction |= inst.operands[1].reg << 12;
11774 inst.instruction |= inst.operands[2].reg << 8;
11775 inst.instruction |= inst.operands[3].reg << 16;
11781 unsigned Rd, Rn, Rm;
11783 Rd = inst.operands[0].reg;
11784 Rn = inst.operands[1].reg;
11785 Rm = inst.operands[2].reg;
11787 reject_bad_reg (Rd);
11788 reject_bad_reg (Rn);
11789 reject_bad_reg (Rm);
11791 inst.instruction |= Rd << 8;
11792 inst.instruction |= Rn << 16;
11793 inst.instruction |= Rm;
11794 inst.instruction |= inst.operands[3].imm << 4;
11802 Rd = inst.operands[0].reg;
11803 Rm = inst.operands[1].reg;
11805 reject_bad_reg (Rd);
11806 reject_bad_reg (Rm);
11808 if (inst.instruction <= 0xffff
11809 && inst.size_req != 4
11810 && Rd <= 7 && Rm <= 7
11811 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11813 inst.instruction = THUMB_OP16 (inst.instruction);
11814 inst.instruction |= Rd;
11815 inst.instruction |= Rm << 3;
11817 else if (unified_syntax)
11819 if (inst.instruction <= 0xffff)
11820 inst.instruction = THUMB_OP32 (inst.instruction);
11821 inst.instruction |= Rd << 8;
11822 inst.instruction |= Rm;
11823 inst.instruction |= inst.operands[2].imm << 4;
11827 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11828 _("Thumb encoding does not support rotation"));
11829 constraint (1, BAD_HIREG);
11836 /* We have to do the following check manually as ARM_EXT_OS only applies
11838 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11840 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11841 /* This only applies to the v6m howver, not later architectures. */
11842 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11843 as_bad (_("SVC is not permitted on this architecture"));
11844 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11847 inst.reloc.type = BFD_RELOC_ARM_SWI;
11856 half = (inst.instruction & 0x10) != 0;
11857 set_it_insn_type_last ();
11858 constraint (inst.operands[0].immisreg,
11859 _("instruction requires register index"));
11861 Rn = inst.operands[0].reg;
11862 Rm = inst.operands[0].imm;
11864 constraint (Rn == REG_SP, BAD_SP);
11865 reject_bad_reg (Rm);
11867 constraint (!half && inst.operands[0].shifted,
11868 _("instruction does not allow shifted index"));
11869 inst.instruction |= (Rn << 16) | Rm;
11875 do_t_ssat_usat (0);
11883 Rd = inst.operands[0].reg;
11884 Rn = inst.operands[2].reg;
11886 reject_bad_reg (Rd);
11887 reject_bad_reg (Rn);
11889 inst.instruction |= Rd << 8;
11890 inst.instruction |= inst.operands[1].imm;
11891 inst.instruction |= Rn << 16;
11894 /* Neon instruction encoder helpers. */
11896 /* Encodings for the different types for various Neon opcodes. */
11898 /* An "invalid" code for the following tables. */
11901 struct neon_tab_entry
11904 unsigned float_or_poly;
11905 unsigned scalar_or_imm;
11908 /* Map overloaded Neon opcodes to their respective encodings. */
11909 #define NEON_ENC_TAB \
11910 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11911 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11912 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11913 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11914 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11915 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11916 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11917 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11918 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11919 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11920 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11921 /* Register variants of the following two instructions are encoded as
11922 vcge / vcgt with the operands reversed. */ \
11923 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11924 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11925 X(vfma, N_INV, 0x0000c10, N_INV), \
11926 X(vfms, N_INV, 0x0200c10, N_INV), \
11927 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11928 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11929 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11930 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11931 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11932 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11933 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11934 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11935 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11936 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11937 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11938 X(vshl, 0x0000400, N_INV, 0x0800510), \
11939 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11940 X(vand, 0x0000110, N_INV, 0x0800030), \
11941 X(vbic, 0x0100110, N_INV, 0x0800030), \
11942 X(veor, 0x1000110, N_INV, N_INV), \
11943 X(vorn, 0x0300110, N_INV, 0x0800010), \
11944 X(vorr, 0x0200110, N_INV, 0x0800010), \
11945 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11946 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11947 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11948 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11949 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11950 X(vst1, 0x0000000, 0x0800000, N_INV), \
11951 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11952 X(vst2, 0x0000100, 0x0800100, N_INV), \
11953 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11954 X(vst3, 0x0000200, 0x0800200, N_INV), \
11955 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11956 X(vst4, 0x0000300, 0x0800300, N_INV), \
11957 X(vmovn, 0x1b20200, N_INV, N_INV), \
11958 X(vtrn, 0x1b20080, N_INV, N_INV), \
11959 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11960 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11961 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11962 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11963 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11964 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11965 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11966 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11967 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11968 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11969 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11973 #define X(OPC,I,F,S) N_MNEM_##OPC
11978 static const struct neon_tab_entry neon_enc_tab[] =
11980 #define X(OPC,I,F,S) { (I), (F), (S) }
11985 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11986 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11987 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11988 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11989 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11990 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11991 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11992 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11993 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11994 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11995 #define NEON_ENC_SINGLE_(X) \
11996 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11997 #define NEON_ENC_DOUBLE_(X) \
11998 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12000 #define NEON_ENCODE(type, inst) \
12003 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12004 inst.is_neon = 1; \
12008 #define check_neon_suffixes \
12011 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12013 as_bad (_("invalid neon suffix for non neon instruction")); \
12019 /* Define shapes for instruction operands. The following mnemonic characters
12020 are used in this table:
12022 F - VFP S<n> register
12023 D - Neon D<n> register
12024 Q - Neon Q<n> register
12028 L - D<n> register list
12030 This table is used to generate various data:
12031 - enumerations of the form NS_DDR to be used as arguments to
12033 - a table classifying shapes into single, double, quad, mixed.
12034 - a table used to drive neon_select_shape. */
12036 #define NEON_SHAPE_DEF \
12037 X(3, (D, D, D), DOUBLE), \
12038 X(3, (Q, Q, Q), QUAD), \
12039 X(3, (D, D, I), DOUBLE), \
12040 X(3, (Q, Q, I), QUAD), \
12041 X(3, (D, D, S), DOUBLE), \
12042 X(3, (Q, Q, S), QUAD), \
12043 X(2, (D, D), DOUBLE), \
12044 X(2, (Q, Q), QUAD), \
12045 X(2, (D, S), DOUBLE), \
12046 X(2, (Q, S), QUAD), \
12047 X(2, (D, R), DOUBLE), \
12048 X(2, (Q, R), QUAD), \
12049 X(2, (D, I), DOUBLE), \
12050 X(2, (Q, I), QUAD), \
12051 X(3, (D, L, D), DOUBLE), \
12052 X(2, (D, Q), MIXED), \
12053 X(2, (Q, D), MIXED), \
12054 X(3, (D, Q, I), MIXED), \
12055 X(3, (Q, D, I), MIXED), \
12056 X(3, (Q, D, D), MIXED), \
12057 X(3, (D, Q, Q), MIXED), \
12058 X(3, (Q, Q, D), MIXED), \
12059 X(3, (Q, D, S), MIXED), \
12060 X(3, (D, Q, S), MIXED), \
12061 X(4, (D, D, D, I), DOUBLE), \
12062 X(4, (Q, Q, Q, I), QUAD), \
12063 X(2, (F, F), SINGLE), \
12064 X(3, (F, F, F), SINGLE), \
12065 X(2, (F, I), SINGLE), \
12066 X(2, (F, D), MIXED), \
12067 X(2, (D, F), MIXED), \
12068 X(3, (F, F, I), MIXED), \
12069 X(4, (R, R, F, F), SINGLE), \
12070 X(4, (F, F, R, R), SINGLE), \
12071 X(3, (D, R, R), DOUBLE), \
12072 X(3, (R, R, D), DOUBLE), \
12073 X(2, (S, R), SINGLE), \
12074 X(2, (R, S), SINGLE), \
12075 X(2, (F, R), SINGLE), \
12076 X(2, (R, F), SINGLE)
12078 #define S2(A,B) NS_##A##B
12079 #define S3(A,B,C) NS_##A##B##C
12080 #define S4(A,B,C,D) NS_##A##B##C##D
12082 #define X(N, L, C) S##N L
12095 enum neon_shape_class
12103 #define X(N, L, C) SC_##C
12105 static enum neon_shape_class neon_shape_class[] =
12123 /* Register widths of above. */
12124 static unsigned neon_shape_el_size[] =
12135 struct neon_shape_info
12138 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12141 #define S2(A,B) { SE_##A, SE_##B }
12142 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12143 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12145 #define X(N, L, C) { N, S##N L }
12147 static struct neon_shape_info neon_shape_tab[] =
12157 /* Bit masks used in type checking given instructions.
12158 'N_EQK' means the type must be the same as (or based on in some way) the key
12159 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12160 set, various other bits can be set as well in order to modify the meaning of
12161 the type constraint. */
12163 enum neon_type_mask
12186 N_KEY = 0x1000000, /* Key element (main type specifier). */
12187 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12188 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12189 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12190 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12191 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12192 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12193 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12194 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12195 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12197 N_MAX_NONSPECIAL = N_F64
12200 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12202 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12203 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12204 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12205 #define N_SUF_32 (N_SU_32 | N_F32)
12206 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12207 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12209 /* Pass this as the first type argument to neon_check_type to ignore types
12211 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12213 /* Select a "shape" for the current instruction (describing register types or
12214 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12215 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12216 function of operand parsing, so this function doesn't need to be called.
12217 Shapes should be listed in order of decreasing length. */
12219 static enum neon_shape
12220 neon_select_shape (enum neon_shape shape, ...)
12223 enum neon_shape first_shape = shape;
12225 /* Fix missing optional operands. FIXME: we don't know at this point how
12226 many arguments we should have, so this makes the assumption that we have
12227 > 1. This is true of all current Neon opcodes, I think, but may not be
12228 true in the future. */
12229 if (!inst.operands[1].present)
12230 inst.operands[1] = inst.operands[0];
12232 va_start (ap, shape);
12234 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12239 for (j = 0; j < neon_shape_tab[shape].els; j++)
12241 if (!inst.operands[j].present)
12247 switch (neon_shape_tab[shape].el[j])
12250 if (!(inst.operands[j].isreg
12251 && inst.operands[j].isvec
12252 && inst.operands[j].issingle
12253 && !inst.operands[j].isquad))
12258 if (!(inst.operands[j].isreg
12259 && inst.operands[j].isvec
12260 && !inst.operands[j].isquad
12261 && !inst.operands[j].issingle))
12266 if (!(inst.operands[j].isreg
12267 && !inst.operands[j].isvec))
12272 if (!(inst.operands[j].isreg
12273 && inst.operands[j].isvec
12274 && inst.operands[j].isquad
12275 && !inst.operands[j].issingle))
12280 if (!(!inst.operands[j].isreg
12281 && !inst.operands[j].isscalar))
12286 if (!(!inst.operands[j].isreg
12287 && inst.operands[j].isscalar))
12303 if (shape == NS_NULL && first_shape != NS_NULL)
12304 first_error (_("invalid instruction shape"));
12309 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12310 means the Q bit should be set). */
12313 neon_quad (enum neon_shape shape)
12315 return neon_shape_class[shape] == SC_QUAD;
12319 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12322 /* Allow modification to be made to types which are constrained to be
12323 based on the key element, based on bits set alongside N_EQK. */
12324 if ((typebits & N_EQK) != 0)
12326 if ((typebits & N_HLF) != 0)
12328 else if ((typebits & N_DBL) != 0)
12330 if ((typebits & N_SGN) != 0)
12331 *g_type = NT_signed;
12332 else if ((typebits & N_UNS) != 0)
12333 *g_type = NT_unsigned;
12334 else if ((typebits & N_INT) != 0)
12335 *g_type = NT_integer;
12336 else if ((typebits & N_FLT) != 0)
12337 *g_type = NT_float;
12338 else if ((typebits & N_SIZ) != 0)
12339 *g_type = NT_untyped;
12343 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12344 operand type, i.e. the single type specified in a Neon instruction when it
12345 is the only one given. */
12347 static struct neon_type_el
12348 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12350 struct neon_type_el dest = *key;
12352 gas_assert ((thisarg & N_EQK) != 0);
12354 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12359 /* Convert Neon type and size into compact bitmask representation. */
12361 static enum neon_type_mask
12362 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12369 case 8: return N_8;
12370 case 16: return N_16;
12371 case 32: return N_32;
12372 case 64: return N_64;
12380 case 8: return N_I8;
12381 case 16: return N_I16;
12382 case 32: return N_I32;
12383 case 64: return N_I64;
12391 case 16: return N_F16;
12392 case 32: return N_F32;
12393 case 64: return N_F64;
12401 case 8: return N_P8;
12402 case 16: return N_P16;
12410 case 8: return N_S8;
12411 case 16: return N_S16;
12412 case 32: return N_S32;
12413 case 64: return N_S64;
12421 case 8: return N_U8;
12422 case 16: return N_U16;
12423 case 32: return N_U32;
12424 case 64: return N_U64;
12435 /* Convert compact Neon bitmask type representation to a type and size. Only
12436 handles the case where a single bit is set in the mask. */
12439 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12440 enum neon_type_mask mask)
12442 if ((mask & N_EQK) != 0)
12445 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12447 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12449 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12451 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12456 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12458 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12459 *type = NT_unsigned;
12460 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12461 *type = NT_integer;
12462 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12463 *type = NT_untyped;
12464 else if ((mask & (N_P8 | N_P16)) != 0)
12466 else if ((mask & (N_F32 | N_F64)) != 0)
12474 /* Modify a bitmask of allowed types. This is only needed for type
12478 modify_types_allowed (unsigned allowed, unsigned mods)
12481 enum neon_el_type type;
12487 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12489 if (el_type_of_type_chk (&type, &size,
12490 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12492 neon_modify_type_size (mods, &type, &size);
12493 destmask |= type_chk_of_el_type (type, size);
12500 /* Check type and return type classification.
12501 The manual states (paraphrase): If one datatype is given, it indicates the
12503 - the second operand, if there is one
12504 - the operand, if there is no second operand
12505 - the result, if there are no operands.
12506 This isn't quite good enough though, so we use a concept of a "key" datatype
12507 which is set on a per-instruction basis, which is the one which matters when
12508 only one data type is written.
12509 Note: this function has side-effects (e.g. filling in missing operands). All
12510 Neon instructions should call it before performing bit encoding. */
12512 static struct neon_type_el
12513 neon_check_type (unsigned els, enum neon_shape ns, ...)
12516 unsigned i, pass, key_el = 0;
12517 unsigned types[NEON_MAX_TYPE_ELS];
12518 enum neon_el_type k_type = NT_invtype;
12519 unsigned k_size = -1u;
12520 struct neon_type_el badtype = {NT_invtype, -1};
12521 unsigned key_allowed = 0;
12523 /* Optional registers in Neon instructions are always (not) in operand 1.
12524 Fill in the missing operand here, if it was omitted. */
12525 if (els > 1 && !inst.operands[1].present)
12526 inst.operands[1] = inst.operands[0];
12528 /* Suck up all the varargs. */
12530 for (i = 0; i < els; i++)
12532 unsigned thisarg = va_arg (ap, unsigned);
12533 if (thisarg == N_IGNORE_TYPE)
12538 types[i] = thisarg;
12539 if ((thisarg & N_KEY) != 0)
12544 if (inst.vectype.elems > 0)
12545 for (i = 0; i < els; i++)
12546 if (inst.operands[i].vectype.type != NT_invtype)
12548 first_error (_("types specified in both the mnemonic and operands"));
12552 /* Duplicate inst.vectype elements here as necessary.
12553 FIXME: No idea if this is exactly the same as the ARM assembler,
12554 particularly when an insn takes one register and one non-register
12556 if (inst.vectype.elems == 1 && els > 1)
12559 inst.vectype.elems = els;
12560 inst.vectype.el[key_el] = inst.vectype.el[0];
12561 for (j = 0; j < els; j++)
12563 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12566 else if (inst.vectype.elems == 0 && els > 0)
12569 /* No types were given after the mnemonic, so look for types specified
12570 after each operand. We allow some flexibility here; as long as the
12571 "key" operand has a type, we can infer the others. */
12572 for (j = 0; j < els; j++)
12573 if (inst.operands[j].vectype.type != NT_invtype)
12574 inst.vectype.el[j] = inst.operands[j].vectype;
12576 if (inst.operands[key_el].vectype.type != NT_invtype)
12578 for (j = 0; j < els; j++)
12579 if (inst.operands[j].vectype.type == NT_invtype)
12580 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12585 first_error (_("operand types can't be inferred"));
12589 else if (inst.vectype.elems != els)
12591 first_error (_("type specifier has the wrong number of parts"));
12595 for (pass = 0; pass < 2; pass++)
12597 for (i = 0; i < els; i++)
12599 unsigned thisarg = types[i];
12600 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12601 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12602 enum neon_el_type g_type = inst.vectype.el[i].type;
12603 unsigned g_size = inst.vectype.el[i].size;
12605 /* Decay more-specific signed & unsigned types to sign-insensitive
12606 integer types if sign-specific variants are unavailable. */
12607 if ((g_type == NT_signed || g_type == NT_unsigned)
12608 && (types_allowed & N_SU_ALL) == 0)
12609 g_type = NT_integer;
12611 /* If only untyped args are allowed, decay any more specific types to
12612 them. Some instructions only care about signs for some element
12613 sizes, so handle that properly. */
12614 if ((g_size == 8 && (types_allowed & N_8) != 0)
12615 || (g_size == 16 && (types_allowed & N_16) != 0)
12616 || (g_size == 32 && (types_allowed & N_32) != 0)
12617 || (g_size == 64 && (types_allowed & N_64) != 0))
12618 g_type = NT_untyped;
12622 if ((thisarg & N_KEY) != 0)
12626 key_allowed = thisarg & ~N_KEY;
12631 if ((thisarg & N_VFP) != 0)
12633 enum neon_shape_el regshape;
12634 unsigned regwidth, match;
12636 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12639 first_error (_("invalid instruction shape"));
12642 regshape = neon_shape_tab[ns].el[i];
12643 regwidth = neon_shape_el_size[regshape];
12645 /* In VFP mode, operands must match register widths. If we
12646 have a key operand, use its width, else use the width of
12647 the current operand. */
12653 if (regwidth != match)
12655 first_error (_("operand size must match register width"));
12660 if ((thisarg & N_EQK) == 0)
12662 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12664 if ((given_type & types_allowed) == 0)
12666 first_error (_("bad type in Neon instruction"));
12672 enum neon_el_type mod_k_type = k_type;
12673 unsigned mod_k_size = k_size;
12674 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12675 if (g_type != mod_k_type || g_size != mod_k_size)
12677 first_error (_("inconsistent types in Neon instruction"));
12685 return inst.vectype.el[key_el];
12688 /* Neon-style VFP instruction forwarding. */
12690 /* Thumb VFP instructions have 0xE in the condition field. */
12693 do_vfp_cond_or_thumb (void)
12698 inst.instruction |= 0xe0000000;
12700 inst.instruction |= inst.cond << 28;
12703 /* Look up and encode a simple mnemonic, for use as a helper function for the
12704 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12705 etc. It is assumed that operand parsing has already been done, and that the
12706 operands are in the form expected by the given opcode (this isn't necessarily
12707 the same as the form in which they were parsed, hence some massaging must
12708 take place before this function is called).
12709 Checks current arch version against that in the looked-up opcode. */
12712 do_vfp_nsyn_opcode (const char *opname)
12714 const struct asm_opcode *opcode;
12716 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12721 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12722 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12729 inst.instruction = opcode->tvalue;
12730 opcode->tencode ();
12734 inst.instruction = (inst.cond << 28) | opcode->avalue;
12735 opcode->aencode ();
12740 do_vfp_nsyn_add_sub (enum neon_shape rs)
12742 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12747 do_vfp_nsyn_opcode ("fadds");
12749 do_vfp_nsyn_opcode ("fsubs");
12754 do_vfp_nsyn_opcode ("faddd");
12756 do_vfp_nsyn_opcode ("fsubd");
12760 /* Check operand types to see if this is a VFP instruction, and if so call
12764 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12766 enum neon_shape rs;
12767 struct neon_type_el et;
12772 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12773 et = neon_check_type (2, rs,
12774 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12778 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12779 et = neon_check_type (3, rs,
12780 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12787 if (et.type != NT_invtype)
12798 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12800 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12805 do_vfp_nsyn_opcode ("fmacs");
12807 do_vfp_nsyn_opcode ("fnmacs");
12812 do_vfp_nsyn_opcode ("fmacd");
12814 do_vfp_nsyn_opcode ("fnmacd");
12819 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12821 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12826 do_vfp_nsyn_opcode ("ffmas");
12828 do_vfp_nsyn_opcode ("ffnmas");
12833 do_vfp_nsyn_opcode ("ffmad");
12835 do_vfp_nsyn_opcode ("ffnmad");
12840 do_vfp_nsyn_mul (enum neon_shape rs)
12843 do_vfp_nsyn_opcode ("fmuls");
12845 do_vfp_nsyn_opcode ("fmuld");
12849 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12851 int is_neg = (inst.instruction & 0x80) != 0;
12852 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12857 do_vfp_nsyn_opcode ("fnegs");
12859 do_vfp_nsyn_opcode ("fabss");
12864 do_vfp_nsyn_opcode ("fnegd");
12866 do_vfp_nsyn_opcode ("fabsd");
12870 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12871 insns belong to Neon, and are handled elsewhere. */
12874 do_vfp_nsyn_ldm_stm (int is_dbmode)
12876 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12880 do_vfp_nsyn_opcode ("fldmdbs");
12882 do_vfp_nsyn_opcode ("fldmias");
12887 do_vfp_nsyn_opcode ("fstmdbs");
12889 do_vfp_nsyn_opcode ("fstmias");
12894 do_vfp_nsyn_sqrt (void)
12896 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12897 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12900 do_vfp_nsyn_opcode ("fsqrts");
12902 do_vfp_nsyn_opcode ("fsqrtd");
12906 do_vfp_nsyn_div (void)
12908 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12909 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12910 N_F32 | N_F64 | N_KEY | N_VFP);
12913 do_vfp_nsyn_opcode ("fdivs");
12915 do_vfp_nsyn_opcode ("fdivd");
12919 do_vfp_nsyn_nmul (void)
12921 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12922 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12923 N_F32 | N_F64 | N_KEY | N_VFP);
12927 NEON_ENCODE (SINGLE, inst);
12928 do_vfp_sp_dyadic ();
12932 NEON_ENCODE (DOUBLE, inst);
12933 do_vfp_dp_rd_rn_rm ();
12935 do_vfp_cond_or_thumb ();
12939 do_vfp_nsyn_cmp (void)
12941 if (inst.operands[1].isreg)
12943 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12944 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12948 NEON_ENCODE (SINGLE, inst);
12949 do_vfp_sp_monadic ();
12953 NEON_ENCODE (DOUBLE, inst);
12954 do_vfp_dp_rd_rm ();
12959 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
12960 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
12962 switch (inst.instruction & 0x0fffffff)
12965 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
12968 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
12976 NEON_ENCODE (SINGLE, inst);
12977 do_vfp_sp_compare_z ();
12981 NEON_ENCODE (DOUBLE, inst);
12985 do_vfp_cond_or_thumb ();
12989 nsyn_insert_sp (void)
12991 inst.operands[1] = inst.operands[0];
12992 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
12993 inst.operands[0].reg = REG_SP;
12994 inst.operands[0].isreg = 1;
12995 inst.operands[0].writeback = 1;
12996 inst.operands[0].present = 1;
13000 do_vfp_nsyn_push (void)
13003 if (inst.operands[1].issingle)
13004 do_vfp_nsyn_opcode ("fstmdbs");
13006 do_vfp_nsyn_opcode ("fstmdbd");
13010 do_vfp_nsyn_pop (void)
13013 if (inst.operands[1].issingle)
13014 do_vfp_nsyn_opcode ("fldmias");
13016 do_vfp_nsyn_opcode ("fldmiad");
13019 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13020 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13023 neon_dp_fixup (struct arm_it* insn)
13025 unsigned int i = insn->instruction;
13030 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13041 insn->instruction = i;
13044 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13048 neon_logbits (unsigned x)
13050 return ffs (x) - 4;
13053 #define LOW4(R) ((R) & 0xf)
13054 #define HI1(R) (((R) >> 4) & 1)
13056 /* Encode insns with bit pattern:
13058 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13059 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13061 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13062 different meaning for some instruction. */
13065 neon_three_same (int isquad, int ubit, int size)
13067 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13068 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13069 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13070 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13071 inst.instruction |= LOW4 (inst.operands[2].reg);
13072 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13073 inst.instruction |= (isquad != 0) << 6;
13074 inst.instruction |= (ubit != 0) << 24;
13076 inst.instruction |= neon_logbits (size) << 20;
13078 neon_dp_fixup (&inst);
13081 /* Encode instructions of the form:
13083 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13084 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13086 Don't write size if SIZE == -1. */
13089 neon_two_same (int qbit, int ubit, int size)
13091 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13092 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13093 inst.instruction |= LOW4 (inst.operands[1].reg);
13094 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13095 inst.instruction |= (qbit != 0) << 6;
13096 inst.instruction |= (ubit != 0) << 24;
13099 inst.instruction |= neon_logbits (size) << 18;
13101 neon_dp_fixup (&inst);
13104 /* Neon instruction encoders, in approximate order of appearance. */
13107 do_neon_dyadic_i_su (void)
13109 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13110 struct neon_type_el et = neon_check_type (3, rs,
13111 N_EQK, N_EQK, N_SU_32 | N_KEY);
13112 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13116 do_neon_dyadic_i64_su (void)
13118 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13119 struct neon_type_el et = neon_check_type (3, rs,
13120 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13121 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13125 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13128 unsigned size = et.size >> 3;
13129 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13130 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13131 inst.instruction |= LOW4 (inst.operands[1].reg);
13132 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13133 inst.instruction |= (isquad != 0) << 6;
13134 inst.instruction |= immbits << 16;
13135 inst.instruction |= (size >> 3) << 7;
13136 inst.instruction |= (size & 0x7) << 19;
13138 inst.instruction |= (uval != 0) << 24;
13140 neon_dp_fixup (&inst);
13144 do_neon_shl_imm (void)
13146 if (!inst.operands[2].isreg)
13148 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13149 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13150 NEON_ENCODE (IMMED, inst);
13151 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13155 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13156 struct neon_type_el et = neon_check_type (3, rs,
13157 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13160 /* VSHL/VQSHL 3-register variants have syntax such as:
13162 whereas other 3-register operations encoded by neon_three_same have
13165 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13167 tmp = inst.operands[2].reg;
13168 inst.operands[2].reg = inst.operands[1].reg;
13169 inst.operands[1].reg = tmp;
13170 NEON_ENCODE (INTEGER, inst);
13171 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13176 do_neon_qshl_imm (void)
13178 if (!inst.operands[2].isreg)
13180 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13181 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13183 NEON_ENCODE (IMMED, inst);
13184 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13185 inst.operands[2].imm);
13189 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13190 struct neon_type_el et = neon_check_type (3, rs,
13191 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13194 /* See note in do_neon_shl_imm. */
13195 tmp = inst.operands[2].reg;
13196 inst.operands[2].reg = inst.operands[1].reg;
13197 inst.operands[1].reg = tmp;
13198 NEON_ENCODE (INTEGER, inst);
13199 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13204 do_neon_rshl (void)
13206 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13207 struct neon_type_el et = neon_check_type (3, rs,
13208 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13211 tmp = inst.operands[2].reg;
13212 inst.operands[2].reg = inst.operands[1].reg;
13213 inst.operands[1].reg = tmp;
13214 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13218 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13220 /* Handle .I8 pseudo-instructions. */
13223 /* Unfortunately, this will make everything apart from zero out-of-range.
13224 FIXME is this the intended semantics? There doesn't seem much point in
13225 accepting .I8 if so. */
13226 immediate |= immediate << 8;
13232 if (immediate == (immediate & 0x000000ff))
13234 *immbits = immediate;
13237 else if (immediate == (immediate & 0x0000ff00))
13239 *immbits = immediate >> 8;
13242 else if (immediate == (immediate & 0x00ff0000))
13244 *immbits = immediate >> 16;
13247 else if (immediate == (immediate & 0xff000000))
13249 *immbits = immediate >> 24;
13252 if ((immediate & 0xffff) != (immediate >> 16))
13253 goto bad_immediate;
13254 immediate &= 0xffff;
13257 if (immediate == (immediate & 0x000000ff))
13259 *immbits = immediate;
13262 else if (immediate == (immediate & 0x0000ff00))
13264 *immbits = immediate >> 8;
13269 first_error (_("immediate value out of range"));
13273 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13277 neon_bits_same_in_bytes (unsigned imm)
13279 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13280 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13281 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13282 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13285 /* For immediate of above form, return 0bABCD. */
13288 neon_squash_bits (unsigned imm)
13290 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13291 | ((imm & 0x01000000) >> 21);
13294 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13297 neon_qfloat_bits (unsigned imm)
13299 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13302 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13303 the instruction. *OP is passed as the initial value of the op field, and
13304 may be set to a different value depending on the constant (i.e.
13305 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13306 MVN). If the immediate looks like a repeated pattern then also
13307 try smaller element sizes. */
13310 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13311 unsigned *immbits, int *op, int size,
13312 enum neon_el_type type)
13314 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13316 if (type == NT_float && !float_p)
13319 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13321 if (size != 32 || *op == 1)
13323 *immbits = neon_qfloat_bits (immlo);
13329 if (neon_bits_same_in_bytes (immhi)
13330 && neon_bits_same_in_bytes (immlo))
13334 *immbits = (neon_squash_bits (immhi) << 4)
13335 | neon_squash_bits (immlo);
13340 if (immhi != immlo)
13346 if (immlo == (immlo & 0x000000ff))
13351 else if (immlo == (immlo & 0x0000ff00))
13353 *immbits = immlo >> 8;
13356 else if (immlo == (immlo & 0x00ff0000))
13358 *immbits = immlo >> 16;
13361 else if (immlo == (immlo & 0xff000000))
13363 *immbits = immlo >> 24;
13366 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13368 *immbits = (immlo >> 8) & 0xff;
13371 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13373 *immbits = (immlo >> 16) & 0xff;
13377 if ((immlo & 0xffff) != (immlo >> 16))
13384 if (immlo == (immlo & 0x000000ff))
13389 else if (immlo == (immlo & 0x0000ff00))
13391 *immbits = immlo >> 8;
13395 if ((immlo & 0xff) != (immlo >> 8))
13400 if (immlo == (immlo & 0x000000ff))
13402 /* Don't allow MVN with 8-bit immediate. */
13412 /* Write immediate bits [7:0] to the following locations:
13414 |28/24|23 19|18 16|15 4|3 0|
13415 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13417 This function is used by VMOV/VMVN/VORR/VBIC. */
13420 neon_write_immbits (unsigned immbits)
13422 inst.instruction |= immbits & 0xf;
13423 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13424 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13427 /* Invert low-order SIZE bits of XHI:XLO. */
13430 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13432 unsigned immlo = xlo ? *xlo : 0;
13433 unsigned immhi = xhi ? *xhi : 0;
13438 immlo = (~immlo) & 0xff;
13442 immlo = (~immlo) & 0xffff;
13446 immhi = (~immhi) & 0xffffffff;
13447 /* fall through. */
13450 immlo = (~immlo) & 0xffffffff;
13465 do_neon_logic (void)
13467 if (inst.operands[2].present && inst.operands[2].isreg)
13469 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13470 neon_check_type (3, rs, N_IGNORE_TYPE);
13471 /* U bit and size field were set as part of the bitmask. */
13472 NEON_ENCODE (INTEGER, inst);
13473 neon_three_same (neon_quad (rs), 0, -1);
13477 const int three_ops_form = (inst.operands[2].present
13478 && !inst.operands[2].isreg);
13479 const int immoperand = (three_ops_form ? 2 : 1);
13480 enum neon_shape rs = (three_ops_form
13481 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13482 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13483 struct neon_type_el et = neon_check_type (2, rs,
13484 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13485 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13489 if (et.type == NT_invtype)
13492 if (three_ops_form)
13493 constraint (inst.operands[0].reg != inst.operands[1].reg,
13494 _("first and second operands shall be the same register"));
13496 NEON_ENCODE (IMMED, inst);
13498 immbits = inst.operands[immoperand].imm;
13501 /* .i64 is a pseudo-op, so the immediate must be a repeating
13503 if (immbits != (inst.operands[immoperand].regisimm ?
13504 inst.operands[immoperand].reg : 0))
13506 /* Set immbits to an invalid constant. */
13507 immbits = 0xdeadbeef;
13514 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13518 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13522 /* Pseudo-instruction for VBIC. */
13523 neon_invert_size (&immbits, 0, et.size);
13524 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13528 /* Pseudo-instruction for VORR. */
13529 neon_invert_size (&immbits, 0, et.size);
13530 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13540 inst.instruction |= neon_quad (rs) << 6;
13541 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13542 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13543 inst.instruction |= cmode << 8;
13544 neon_write_immbits (immbits);
13546 neon_dp_fixup (&inst);
13551 do_neon_bitfield (void)
13553 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13554 neon_check_type (3, rs, N_IGNORE_TYPE);
13555 neon_three_same (neon_quad (rs), 0, -1);
13559 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13562 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13563 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13565 if (et.type == NT_float)
13567 NEON_ENCODE (FLOAT, inst);
13568 neon_three_same (neon_quad (rs), 0, -1);
13572 NEON_ENCODE (INTEGER, inst);
13573 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13578 do_neon_dyadic_if_su (void)
13580 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13584 do_neon_dyadic_if_su_d (void)
13586 /* This version only allow D registers, but that constraint is enforced during
13587 operand parsing so we don't need to do anything extra here. */
13588 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13592 do_neon_dyadic_if_i_d (void)
13594 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13595 affected if we specify unsigned args. */
13596 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13599 enum vfp_or_neon_is_neon_bits
13602 NEON_CHECK_ARCH = 2
13605 /* Call this function if an instruction which may have belonged to the VFP or
13606 Neon instruction sets, but turned out to be a Neon instruction (due to the
13607 operand types involved, etc.). We have to check and/or fix-up a couple of
13610 - Make sure the user hasn't attempted to make a Neon instruction
13612 - Alter the value in the condition code field if necessary.
13613 - Make sure that the arch supports Neon instructions.
13615 Which of these operations take place depends on bits from enum
13616 vfp_or_neon_is_neon_bits.
13618 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13619 current instruction's condition is COND_ALWAYS, the condition field is
13620 changed to inst.uncond_value. This is necessary because instructions shared
13621 between VFP and Neon may be conditional for the VFP variants only, and the
13622 unconditional Neon version must have, e.g., 0xF in the condition field. */
13625 vfp_or_neon_is_neon (unsigned check)
13627 /* Conditions are always legal in Thumb mode (IT blocks). */
13628 if (!thumb_mode && (check & NEON_CHECK_CC))
13630 if (inst.cond != COND_ALWAYS)
13632 first_error (_(BAD_COND));
13635 if (inst.uncond_value != -1)
13636 inst.instruction |= inst.uncond_value << 28;
13639 if ((check & NEON_CHECK_ARCH)
13640 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13642 first_error (_(BAD_FPU));
13650 do_neon_addsub_if_i (void)
13652 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13655 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13658 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13659 affected if we specify unsigned args. */
13660 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13663 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13665 V<op> A,B (A is operand 0, B is operand 2)
13670 so handle that case specially. */
13673 neon_exchange_operands (void)
13675 void *scratch = alloca (sizeof (inst.operands[0]));
13676 if (inst.operands[1].present)
13678 /* Swap operands[1] and operands[2]. */
13679 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13680 inst.operands[1] = inst.operands[2];
13681 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13685 inst.operands[1] = inst.operands[2];
13686 inst.operands[2] = inst.operands[0];
13691 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13693 if (inst.operands[2].isreg)
13696 neon_exchange_operands ();
13697 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13701 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13702 struct neon_type_el et = neon_check_type (2, rs,
13703 N_EQK | N_SIZ, immtypes | N_KEY);
13705 NEON_ENCODE (IMMED, inst);
13706 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13707 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13708 inst.instruction |= LOW4 (inst.operands[1].reg);
13709 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13710 inst.instruction |= neon_quad (rs) << 6;
13711 inst.instruction |= (et.type == NT_float) << 10;
13712 inst.instruction |= neon_logbits (et.size) << 18;
13714 neon_dp_fixup (&inst);
13721 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13725 do_neon_cmp_inv (void)
13727 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13733 neon_compare (N_IF_32, N_IF_32, FALSE);
13736 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13737 scalars, which are encoded in 5 bits, M : Rm.
13738 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13739 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13743 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13745 unsigned regno = NEON_SCALAR_REG (scalar);
13746 unsigned elno = NEON_SCALAR_INDEX (scalar);
13751 if (regno > 7 || elno > 3)
13753 return regno | (elno << 3);
13756 if (regno > 15 || elno > 1)
13758 return regno | (elno << 4);
13762 first_error (_("scalar out of range for multiply instruction"));
13768 /* Encode multiply / multiply-accumulate scalar instructions. */
13771 neon_mul_mac (struct neon_type_el et, int ubit)
13775 /* Give a more helpful error message if we have an invalid type. */
13776 if (et.type == NT_invtype)
13779 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13780 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13781 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13782 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13783 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13784 inst.instruction |= LOW4 (scalar);
13785 inst.instruction |= HI1 (scalar) << 5;
13786 inst.instruction |= (et.type == NT_float) << 8;
13787 inst.instruction |= neon_logbits (et.size) << 20;
13788 inst.instruction |= (ubit != 0) << 24;
13790 neon_dp_fixup (&inst);
13794 do_neon_mac_maybe_scalar (void)
13796 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13799 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13802 if (inst.operands[2].isscalar)
13804 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13805 struct neon_type_el et = neon_check_type (3, rs,
13806 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13807 NEON_ENCODE (SCALAR, inst);
13808 neon_mul_mac (et, neon_quad (rs));
13812 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13813 affected if we specify unsigned args. */
13814 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13819 do_neon_fmac (void)
13821 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13824 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13827 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13833 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13834 struct neon_type_el et = neon_check_type (3, rs,
13835 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13836 neon_three_same (neon_quad (rs), 0, et.size);
13839 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13840 same types as the MAC equivalents. The polynomial type for this instruction
13841 is encoded the same as the integer type. */
13846 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13849 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13852 if (inst.operands[2].isscalar)
13853 do_neon_mac_maybe_scalar ();
13855 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13859 do_neon_qdmulh (void)
13861 if (inst.operands[2].isscalar)
13863 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13864 struct neon_type_el et = neon_check_type (3, rs,
13865 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13866 NEON_ENCODE (SCALAR, inst);
13867 neon_mul_mac (et, neon_quad (rs));
13871 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13872 struct neon_type_el et = neon_check_type (3, rs,
13873 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13874 NEON_ENCODE (INTEGER, inst);
13875 /* The U bit (rounding) comes from bit mask. */
13876 neon_three_same (neon_quad (rs), 0, et.size);
13881 do_neon_fcmp_absolute (void)
13883 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13884 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13885 /* Size field comes from bit mask. */
13886 neon_three_same (neon_quad (rs), 1, -1);
13890 do_neon_fcmp_absolute_inv (void)
13892 neon_exchange_operands ();
13893 do_neon_fcmp_absolute ();
13897 do_neon_step (void)
13899 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13900 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13901 neon_three_same (neon_quad (rs), 0, -1);
13905 do_neon_abs_neg (void)
13907 enum neon_shape rs;
13908 struct neon_type_el et;
13910 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
13913 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13916 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13917 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
13919 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13920 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13921 inst.instruction |= LOW4 (inst.operands[1].reg);
13922 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13923 inst.instruction |= neon_quad (rs) << 6;
13924 inst.instruction |= (et.type == NT_float) << 10;
13925 inst.instruction |= neon_logbits (et.size) << 18;
13927 neon_dp_fixup (&inst);
13933 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13934 struct neon_type_el et = neon_check_type (2, rs,
13935 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13936 int imm = inst.operands[2].imm;
13937 constraint (imm < 0 || (unsigned)imm >= et.size,
13938 _("immediate out of range for insert"));
13939 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
13945 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13946 struct neon_type_el et = neon_check_type (2, rs,
13947 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13948 int imm = inst.operands[2].imm;
13949 constraint (imm < 1 || (unsigned)imm > et.size,
13950 _("immediate out of range for insert"));
13951 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
13955 do_neon_qshlu_imm (void)
13957 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13958 struct neon_type_el et = neon_check_type (2, rs,
13959 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
13960 int imm = inst.operands[2].imm;
13961 constraint (imm < 0 || (unsigned)imm >= et.size,
13962 _("immediate out of range for shift"));
13963 /* Only encodes the 'U present' variant of the instruction.
13964 In this case, signed types have OP (bit 8) set to 0.
13965 Unsigned types have OP set to 1. */
13966 inst.instruction |= (et.type == NT_unsigned) << 8;
13967 /* The rest of the bits are the same as other immediate shifts. */
13968 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
13972 do_neon_qmovn (void)
13974 struct neon_type_el et = neon_check_type (2, NS_DQ,
13975 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
13976 /* Saturating move where operands can be signed or unsigned, and the
13977 destination has the same signedness. */
13978 NEON_ENCODE (INTEGER, inst);
13979 if (et.type == NT_unsigned)
13980 inst.instruction |= 0xc0;
13982 inst.instruction |= 0x80;
13983 neon_two_same (0, 1, et.size / 2);
13987 do_neon_qmovun (void)
13989 struct neon_type_el et = neon_check_type (2, NS_DQ,
13990 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
13991 /* Saturating move with unsigned results. Operands must be signed. */
13992 NEON_ENCODE (INTEGER, inst);
13993 neon_two_same (0, 1, et.size / 2);
13997 do_neon_rshift_sat_narrow (void)
13999 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14000 or unsigned. If operands are unsigned, results must also be unsigned. */
14001 struct neon_type_el et = neon_check_type (2, NS_DQI,
14002 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14003 int imm = inst.operands[2].imm;
14004 /* This gets the bounds check, size encoding and immediate bits calculation
14008 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14009 VQMOVN.I<size> <Dd>, <Qm>. */
14012 inst.operands[2].present = 0;
14013 inst.instruction = N_MNEM_vqmovn;
14018 constraint (imm < 1 || (unsigned)imm > et.size,
14019 _("immediate out of range"));
14020 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14024 do_neon_rshift_sat_narrow_u (void)
14026 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14027 or unsigned. If operands are unsigned, results must also be unsigned. */
14028 struct neon_type_el et = neon_check_type (2, NS_DQI,
14029 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14030 int imm = inst.operands[2].imm;
14031 /* This gets the bounds check, size encoding and immediate bits calculation
14035 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14036 VQMOVUN.I<size> <Dd>, <Qm>. */
14039 inst.operands[2].present = 0;
14040 inst.instruction = N_MNEM_vqmovun;
14045 constraint (imm < 1 || (unsigned)imm > et.size,
14046 _("immediate out of range"));
14047 /* FIXME: The manual is kind of unclear about what value U should have in
14048 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14050 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14054 do_neon_movn (void)
14056 struct neon_type_el et = neon_check_type (2, NS_DQ,
14057 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14058 NEON_ENCODE (INTEGER, inst);
14059 neon_two_same (0, 1, et.size / 2);
14063 do_neon_rshift_narrow (void)
14065 struct neon_type_el et = neon_check_type (2, NS_DQI,
14066 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14067 int imm = inst.operands[2].imm;
14068 /* This gets the bounds check, size encoding and immediate bits calculation
14072 /* If immediate is zero then we are a pseudo-instruction for
14073 VMOVN.I<size> <Dd>, <Qm> */
14076 inst.operands[2].present = 0;
14077 inst.instruction = N_MNEM_vmovn;
14082 constraint (imm < 1 || (unsigned)imm > et.size,
14083 _("immediate out of range for narrowing operation"));
14084 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14088 do_neon_shll (void)
14090 /* FIXME: Type checking when lengthening. */
14091 struct neon_type_el et = neon_check_type (2, NS_QDI,
14092 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14093 unsigned imm = inst.operands[2].imm;
14095 if (imm == et.size)
14097 /* Maximum shift variant. */
14098 NEON_ENCODE (INTEGER, inst);
14099 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14100 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14101 inst.instruction |= LOW4 (inst.operands[1].reg);
14102 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14103 inst.instruction |= neon_logbits (et.size) << 18;
14105 neon_dp_fixup (&inst);
14109 /* A more-specific type check for non-max versions. */
14110 et = neon_check_type (2, NS_QDI,
14111 N_EQK | N_DBL, N_SU_32 | N_KEY);
14112 NEON_ENCODE (IMMED, inst);
14113 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14117 /* Check the various types for the VCVT instruction, and return which version
14118 the current instruction is. */
14121 neon_cvt_flavour (enum neon_shape rs)
14123 #define CVT_VAR(C,X,Y) \
14124 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14125 if (et.type != NT_invtype) \
14127 inst.error = NULL; \
14130 struct neon_type_el et;
14131 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14132 || rs == NS_FF) ? N_VFP : 0;
14133 /* The instruction versions which take an immediate take one register
14134 argument, which is extended to the width of the full register. Thus the
14135 "source" and "destination" registers must have the same width. Hack that
14136 here by making the size equal to the key (wider, in this case) operand. */
14137 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14139 CVT_VAR (0, N_S32, N_F32);
14140 CVT_VAR (1, N_U32, N_F32);
14141 CVT_VAR (2, N_F32, N_S32);
14142 CVT_VAR (3, N_F32, N_U32);
14143 /* Half-precision conversions. */
14144 CVT_VAR (4, N_F32, N_F16);
14145 CVT_VAR (5, N_F16, N_F32);
14149 /* VFP instructions. */
14150 CVT_VAR (6, N_F32, N_F64);
14151 CVT_VAR (7, N_F64, N_F32);
14152 CVT_VAR (8, N_S32, N_F64 | key);
14153 CVT_VAR (9, N_U32, N_F64 | key);
14154 CVT_VAR (10, N_F64 | key, N_S32);
14155 CVT_VAR (11, N_F64 | key, N_U32);
14156 /* VFP instructions with bitshift. */
14157 CVT_VAR (12, N_F32 | key, N_S16);
14158 CVT_VAR (13, N_F32 | key, N_U16);
14159 CVT_VAR (14, N_F64 | key, N_S16);
14160 CVT_VAR (15, N_F64 | key, N_U16);
14161 CVT_VAR (16, N_S16, N_F32 | key);
14162 CVT_VAR (17, N_U16, N_F32 | key);
14163 CVT_VAR (18, N_S16, N_F64 | key);
14164 CVT_VAR (19, N_U16, N_F64 | key);
14170 /* Neon-syntax VFP conversions. */
14173 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14175 const char *opname = 0;
14177 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14179 /* Conversions with immediate bitshift. */
14180 const char *enc[] =
14204 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14206 opname = enc[flavour];
14207 constraint (inst.operands[0].reg != inst.operands[1].reg,
14208 _("operands 0 and 1 must be the same register"));
14209 inst.operands[1] = inst.operands[2];
14210 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14215 /* Conversions without bitshift. */
14216 const char *enc[] =
14232 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14233 opname = enc[flavour];
14237 do_vfp_nsyn_opcode (opname);
14241 do_vfp_nsyn_cvtz (void)
14243 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14244 int flavour = neon_cvt_flavour (rs);
14245 const char *enc[] =
14259 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14260 do_vfp_nsyn_opcode (enc[flavour]);
14264 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14266 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14267 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14268 int flavour = neon_cvt_flavour (rs);
14270 /* PR11109: Handle round-to-zero for VCVT conversions. */
14272 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14273 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14274 && (rs == NS_FD || rs == NS_FF))
14276 do_vfp_nsyn_cvtz ();
14280 /* VFP rather than Neon conversions. */
14283 do_vfp_nsyn_cvt (rs, flavour);
14293 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14295 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14298 /* Fixed-point conversion with #0 immediate is encoded as an
14299 integer conversion. */
14300 if (inst.operands[2].present && inst.operands[2].imm == 0)
14302 immbits = 32 - inst.operands[2].imm;
14303 NEON_ENCODE (IMMED, inst);
14305 inst.instruction |= enctab[flavour];
14306 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14307 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14308 inst.instruction |= LOW4 (inst.operands[1].reg);
14309 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14310 inst.instruction |= neon_quad (rs) << 6;
14311 inst.instruction |= 1 << 21;
14312 inst.instruction |= immbits << 16;
14314 neon_dp_fixup (&inst);
14322 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14324 NEON_ENCODE (INTEGER, inst);
14326 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14330 inst.instruction |= enctab[flavour];
14332 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14333 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14334 inst.instruction |= LOW4 (inst.operands[1].reg);
14335 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14336 inst.instruction |= neon_quad (rs) << 6;
14337 inst.instruction |= 2 << 18;
14339 neon_dp_fixup (&inst);
14343 /* Half-precision conversions for Advanced SIMD -- neon. */
14348 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14350 as_bad (_("operand size must match register width"));
14355 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14357 as_bad (_("operand size must match register width"));
14362 inst.instruction = 0x3b60600;
14364 inst.instruction = 0x3b60700;
14366 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14367 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14368 inst.instruction |= LOW4 (inst.operands[1].reg);
14369 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14370 neon_dp_fixup (&inst);
14374 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14375 do_vfp_nsyn_cvt (rs, flavour);
14380 do_neon_cvtr (void)
14382 do_neon_cvt_1 (FALSE);
14388 do_neon_cvt_1 (TRUE);
14392 do_neon_cvtb (void)
14394 inst.instruction = 0xeb20a40;
14396 /* The sizes are attached to the mnemonic. */
14397 if (inst.vectype.el[0].type != NT_invtype
14398 && inst.vectype.el[0].size == 16)
14399 inst.instruction |= 0x00010000;
14401 /* Programmer's syntax: the sizes are attached to the operands. */
14402 else if (inst.operands[0].vectype.type != NT_invtype
14403 && inst.operands[0].vectype.size == 16)
14404 inst.instruction |= 0x00010000;
14406 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14407 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14408 do_vfp_cond_or_thumb ();
14413 do_neon_cvtt (void)
14416 inst.instruction |= 0x80;
14420 neon_move_immediate (void)
14422 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14423 struct neon_type_el et = neon_check_type (2, rs,
14424 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14425 unsigned immlo, immhi = 0, immbits;
14426 int op, cmode, float_p;
14428 constraint (et.type == NT_invtype,
14429 _("operand size must be specified for immediate VMOV"));
14431 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14432 op = (inst.instruction & (1 << 5)) != 0;
14434 immlo = inst.operands[1].imm;
14435 if (inst.operands[1].regisimm)
14436 immhi = inst.operands[1].reg;
14438 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14439 _("immediate has bits set outside the operand size"));
14441 float_p = inst.operands[1].immisfloat;
14443 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14444 et.size, et.type)) == FAIL)
14446 /* Invert relevant bits only. */
14447 neon_invert_size (&immlo, &immhi, et.size);
14448 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14449 with one or the other; those cases are caught by
14450 neon_cmode_for_move_imm. */
14452 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14453 &op, et.size, et.type)) == FAIL)
14455 first_error (_("immediate out of range"));
14460 inst.instruction &= ~(1 << 5);
14461 inst.instruction |= op << 5;
14463 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14464 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14465 inst.instruction |= neon_quad (rs) << 6;
14466 inst.instruction |= cmode << 8;
14468 neon_write_immbits (immbits);
14474 if (inst.operands[1].isreg)
14476 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14478 NEON_ENCODE (INTEGER, inst);
14479 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14480 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14481 inst.instruction |= LOW4 (inst.operands[1].reg);
14482 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14483 inst.instruction |= neon_quad (rs) << 6;
14487 NEON_ENCODE (IMMED, inst);
14488 neon_move_immediate ();
14491 neon_dp_fixup (&inst);
14494 /* Encode instructions of form:
14496 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14497 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14500 neon_mixed_length (struct neon_type_el et, unsigned size)
14502 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14503 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14504 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14505 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14506 inst.instruction |= LOW4 (inst.operands[2].reg);
14507 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14508 inst.instruction |= (et.type == NT_unsigned) << 24;
14509 inst.instruction |= neon_logbits (size) << 20;
14511 neon_dp_fixup (&inst);
14515 do_neon_dyadic_long (void)
14517 /* FIXME: Type checking for lengthening op. */
14518 struct neon_type_el et = neon_check_type (3, NS_QDD,
14519 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14520 neon_mixed_length (et, et.size);
14524 do_neon_abal (void)
14526 struct neon_type_el et = neon_check_type (3, NS_QDD,
14527 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14528 neon_mixed_length (et, et.size);
14532 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14534 if (inst.operands[2].isscalar)
14536 struct neon_type_el et = neon_check_type (3, NS_QDS,
14537 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14538 NEON_ENCODE (SCALAR, inst);
14539 neon_mul_mac (et, et.type == NT_unsigned);
14543 struct neon_type_el et = neon_check_type (3, NS_QDD,
14544 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14545 NEON_ENCODE (INTEGER, inst);
14546 neon_mixed_length (et, et.size);
14551 do_neon_mac_maybe_scalar_long (void)
14553 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14557 do_neon_dyadic_wide (void)
14559 struct neon_type_el et = neon_check_type (3, NS_QQD,
14560 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14561 neon_mixed_length (et, et.size);
14565 do_neon_dyadic_narrow (void)
14567 struct neon_type_el et = neon_check_type (3, NS_QDD,
14568 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14569 /* Operand sign is unimportant, and the U bit is part of the opcode,
14570 so force the operand type to integer. */
14571 et.type = NT_integer;
14572 neon_mixed_length (et, et.size / 2);
14576 do_neon_mul_sat_scalar_long (void)
14578 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14582 do_neon_vmull (void)
14584 if (inst.operands[2].isscalar)
14585 do_neon_mac_maybe_scalar_long ();
14588 struct neon_type_el et = neon_check_type (3, NS_QDD,
14589 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14590 if (et.type == NT_poly)
14591 NEON_ENCODE (POLY, inst);
14593 NEON_ENCODE (INTEGER, inst);
14594 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14595 zero. Should be OK as-is. */
14596 neon_mixed_length (et, et.size);
14603 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14604 struct neon_type_el et = neon_check_type (3, rs,
14605 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14606 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14608 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14609 _("shift out of range"));
14610 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14611 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14612 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14613 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14614 inst.instruction |= LOW4 (inst.operands[2].reg);
14615 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14616 inst.instruction |= neon_quad (rs) << 6;
14617 inst.instruction |= imm << 8;
14619 neon_dp_fixup (&inst);
14625 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14626 struct neon_type_el et = neon_check_type (2, rs,
14627 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14628 unsigned op = (inst.instruction >> 7) & 3;
14629 /* N (width of reversed regions) is encoded as part of the bitmask. We
14630 extract it here to check the elements to be reversed are smaller.
14631 Otherwise we'd get a reserved instruction. */
14632 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14633 gas_assert (elsize != 0);
14634 constraint (et.size >= elsize,
14635 _("elements must be smaller than reversal region"));
14636 neon_two_same (neon_quad (rs), 1, et.size);
14642 if (inst.operands[1].isscalar)
14644 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14645 struct neon_type_el et = neon_check_type (2, rs,
14646 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14647 unsigned sizebits = et.size >> 3;
14648 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14649 int logsize = neon_logbits (et.size);
14650 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14652 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14655 NEON_ENCODE (SCALAR, inst);
14656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14657 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14658 inst.instruction |= LOW4 (dm);
14659 inst.instruction |= HI1 (dm) << 5;
14660 inst.instruction |= neon_quad (rs) << 6;
14661 inst.instruction |= x << 17;
14662 inst.instruction |= sizebits << 16;
14664 neon_dp_fixup (&inst);
14668 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14669 struct neon_type_el et = neon_check_type (2, rs,
14670 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14671 /* Duplicate ARM register to lanes of vector. */
14672 NEON_ENCODE (ARMREG, inst);
14675 case 8: inst.instruction |= 0x400000; break;
14676 case 16: inst.instruction |= 0x000020; break;
14677 case 32: inst.instruction |= 0x000000; break;
14680 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14681 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14682 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14683 inst.instruction |= neon_quad (rs) << 21;
14684 /* The encoding for this instruction is identical for the ARM and Thumb
14685 variants, except for the condition field. */
14686 do_vfp_cond_or_thumb ();
14690 /* VMOV has particularly many variations. It can be one of:
14691 0. VMOV<c><q> <Qd>, <Qm>
14692 1. VMOV<c><q> <Dd>, <Dm>
14693 (Register operations, which are VORR with Rm = Rn.)
14694 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14695 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14697 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14698 (ARM register to scalar.)
14699 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14700 (Two ARM registers to vector.)
14701 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14702 (Scalar to ARM register.)
14703 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14704 (Vector to two ARM registers.)
14705 8. VMOV.F32 <Sd>, <Sm>
14706 9. VMOV.F64 <Dd>, <Dm>
14707 (VFP register moves.)
14708 10. VMOV.F32 <Sd>, #imm
14709 11. VMOV.F64 <Dd>, #imm
14710 (VFP float immediate load.)
14711 12. VMOV <Rd>, <Sm>
14712 (VFP single to ARM reg.)
14713 13. VMOV <Sd>, <Rm>
14714 (ARM reg to VFP single.)
14715 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14716 (Two ARM regs to two VFP singles.)
14717 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14718 (Two VFP singles to two ARM regs.)
14720 These cases can be disambiguated using neon_select_shape, except cases 1/9
14721 and 3/11 which depend on the operand type too.
14723 All the encoded bits are hardcoded by this function.
14725 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14726 Cases 5, 7 may be used with VFPv2 and above.
14728 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14729 can specify a type where it doesn't make sense to, and is ignored). */
14734 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14735 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14737 struct neon_type_el et;
14738 const char *ldconst = 0;
14742 case NS_DD: /* case 1/9. */
14743 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14744 /* It is not an error here if no type is given. */
14746 if (et.type == NT_float && et.size == 64)
14748 do_vfp_nsyn_opcode ("fcpyd");
14751 /* fall through. */
14753 case NS_QQ: /* case 0/1. */
14755 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14757 /* The architecture manual I have doesn't explicitly state which
14758 value the U bit should have for register->register moves, but
14759 the equivalent VORR instruction has U = 0, so do that. */
14760 inst.instruction = 0x0200110;
14761 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14762 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14763 inst.instruction |= LOW4 (inst.operands[1].reg);
14764 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14765 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14766 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14767 inst.instruction |= neon_quad (rs) << 6;
14769 neon_dp_fixup (&inst);
14773 case NS_DI: /* case 3/11. */
14774 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14776 if (et.type == NT_float && et.size == 64)
14778 /* case 11 (fconstd). */
14779 ldconst = "fconstd";
14780 goto encode_fconstd;
14782 /* fall through. */
14784 case NS_QI: /* case 2/3. */
14785 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14787 inst.instruction = 0x0800010;
14788 neon_move_immediate ();
14789 neon_dp_fixup (&inst);
14792 case NS_SR: /* case 4. */
14794 unsigned bcdebits = 0;
14796 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14797 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14799 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14800 logsize = neon_logbits (et.size);
14802 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14804 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14805 && et.size != 32, _(BAD_FPU));
14806 constraint (et.type == NT_invtype, _("bad type for scalar"));
14807 constraint (x >= 64 / et.size, _("scalar index out of range"));
14811 case 8: bcdebits = 0x8; break;
14812 case 16: bcdebits = 0x1; break;
14813 case 32: bcdebits = 0x0; break;
14817 bcdebits |= x << logsize;
14819 inst.instruction = 0xe000b10;
14820 do_vfp_cond_or_thumb ();
14821 inst.instruction |= LOW4 (dn) << 16;
14822 inst.instruction |= HI1 (dn) << 7;
14823 inst.instruction |= inst.operands[1].reg << 12;
14824 inst.instruction |= (bcdebits & 3) << 5;
14825 inst.instruction |= (bcdebits >> 2) << 21;
14829 case NS_DRR: /* case 5 (fmdrr). */
14830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14833 inst.instruction = 0xc400b10;
14834 do_vfp_cond_or_thumb ();
14835 inst.instruction |= LOW4 (inst.operands[0].reg);
14836 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14837 inst.instruction |= inst.operands[1].reg << 12;
14838 inst.instruction |= inst.operands[2].reg << 16;
14841 case NS_RS: /* case 6. */
14844 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14845 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14846 unsigned abcdebits = 0;
14848 et = neon_check_type (2, NS_NULL,
14849 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14850 logsize = neon_logbits (et.size);
14852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14854 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14855 && et.size != 32, _(BAD_FPU));
14856 constraint (et.type == NT_invtype, _("bad type for scalar"));
14857 constraint (x >= 64 / et.size, _("scalar index out of range"));
14861 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14862 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14863 case 32: abcdebits = 0x00; break;
14867 abcdebits |= x << logsize;
14868 inst.instruction = 0xe100b10;
14869 do_vfp_cond_or_thumb ();
14870 inst.instruction |= LOW4 (dn) << 16;
14871 inst.instruction |= HI1 (dn) << 7;
14872 inst.instruction |= inst.operands[0].reg << 12;
14873 inst.instruction |= (abcdebits & 3) << 5;
14874 inst.instruction |= (abcdebits >> 2) << 21;
14878 case NS_RRD: /* case 7 (fmrrd). */
14879 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14882 inst.instruction = 0xc500b10;
14883 do_vfp_cond_or_thumb ();
14884 inst.instruction |= inst.operands[0].reg << 12;
14885 inst.instruction |= inst.operands[1].reg << 16;
14886 inst.instruction |= LOW4 (inst.operands[2].reg);
14887 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14890 case NS_FF: /* case 8 (fcpys). */
14891 do_vfp_nsyn_opcode ("fcpys");
14894 case NS_FI: /* case 10 (fconsts). */
14895 ldconst = "fconsts";
14897 if (is_quarter_float (inst.operands[1].imm))
14899 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
14900 do_vfp_nsyn_opcode (ldconst);
14903 first_error (_("immediate out of range"));
14906 case NS_RF: /* case 12 (fmrs). */
14907 do_vfp_nsyn_opcode ("fmrs");
14910 case NS_FR: /* case 13 (fmsr). */
14911 do_vfp_nsyn_opcode ("fmsr");
14914 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14915 (one of which is a list), but we have parsed four. Do some fiddling to
14916 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14918 case NS_RRFF: /* case 14 (fmrrs). */
14919 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
14920 _("VFP registers must be adjacent"));
14921 inst.operands[2].imm = 2;
14922 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14923 do_vfp_nsyn_opcode ("fmrrs");
14926 case NS_FFRR: /* case 15 (fmsrr). */
14927 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
14928 _("VFP registers must be adjacent"));
14929 inst.operands[1] = inst.operands[2];
14930 inst.operands[2] = inst.operands[3];
14931 inst.operands[0].imm = 2;
14932 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14933 do_vfp_nsyn_opcode ("fmsrr");
14942 do_neon_rshift_round_imm (void)
14944 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14945 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14946 int imm = inst.operands[2].imm;
14948 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14951 inst.operands[2].present = 0;
14956 constraint (imm < 1 || (unsigned)imm > et.size,
14957 _("immediate out of range for shift"));
14958 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
14963 do_neon_movl (void)
14965 struct neon_type_el et = neon_check_type (2, NS_QD,
14966 N_EQK | N_DBL, N_SU_32 | N_KEY);
14967 unsigned sizebits = et.size >> 3;
14968 inst.instruction |= sizebits << 19;
14969 neon_two_same (0, et.type == NT_unsigned, -1);
14975 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14976 struct neon_type_el et = neon_check_type (2, rs,
14977 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14978 NEON_ENCODE (INTEGER, inst);
14979 neon_two_same (neon_quad (rs), 1, et.size);
14983 do_neon_zip_uzp (void)
14985 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14986 struct neon_type_el et = neon_check_type (2, rs,
14987 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14988 if (rs == NS_DD && et.size == 32)
14990 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14991 inst.instruction = N_MNEM_vtrn;
14995 neon_two_same (neon_quad (rs), 1, et.size);
14999 do_neon_sat_abs_neg (void)
15001 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15002 struct neon_type_el et = neon_check_type (2, rs,
15003 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15004 neon_two_same (neon_quad (rs), 1, et.size);
15008 do_neon_pair_long (void)
15010 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15011 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15012 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15013 inst.instruction |= (et.type == NT_unsigned) << 7;
15014 neon_two_same (neon_quad (rs), 1, et.size);
15018 do_neon_recip_est (void)
15020 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15021 struct neon_type_el et = neon_check_type (2, rs,
15022 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15023 inst.instruction |= (et.type == NT_float) << 8;
15024 neon_two_same (neon_quad (rs), 1, et.size);
15030 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15031 struct neon_type_el et = neon_check_type (2, rs,
15032 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15033 neon_two_same (neon_quad (rs), 1, et.size);
15039 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15040 struct neon_type_el et = neon_check_type (2, rs,
15041 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15042 neon_two_same (neon_quad (rs), 1, et.size);
15048 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15049 struct neon_type_el et = neon_check_type (2, rs,
15050 N_EQK | N_INT, N_8 | N_KEY);
15051 neon_two_same (neon_quad (rs), 1, et.size);
15057 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15058 neon_two_same (neon_quad (rs), 1, -1);
15062 do_neon_tbl_tbx (void)
15064 unsigned listlenbits;
15065 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15067 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15069 first_error (_("bad list length for table lookup"));
15073 listlenbits = inst.operands[1].imm - 1;
15074 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15075 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15076 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15077 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15078 inst.instruction |= LOW4 (inst.operands[2].reg);
15079 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15080 inst.instruction |= listlenbits << 8;
15082 neon_dp_fixup (&inst);
15086 do_neon_ldm_stm (void)
15088 /* P, U and L bits are part of bitmask. */
15089 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15090 unsigned offsetbits = inst.operands[1].imm * 2;
15092 if (inst.operands[1].issingle)
15094 do_vfp_nsyn_ldm_stm (is_dbmode);
15098 constraint (is_dbmode && !inst.operands[0].writeback,
15099 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15101 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15102 _("register list must contain at least 1 and at most 16 "
15105 inst.instruction |= inst.operands[0].reg << 16;
15106 inst.instruction |= inst.operands[0].writeback << 21;
15107 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15108 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15110 inst.instruction |= offsetbits;
15112 do_vfp_cond_or_thumb ();
15116 do_neon_ldr_str (void)
15118 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15120 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15121 And is UNPREDICTABLE in thumb mode. */
15123 && inst.operands[1].reg == REG_PC
15124 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15126 if (!thumb_mode && warn_on_deprecated)
15127 as_warn (_("Use of PC here is deprecated"));
15129 inst.error = _("Use of PC here is UNPREDICTABLE");
15132 if (inst.operands[0].issingle)
15135 do_vfp_nsyn_opcode ("flds");
15137 do_vfp_nsyn_opcode ("fsts");
15142 do_vfp_nsyn_opcode ("fldd");
15144 do_vfp_nsyn_opcode ("fstd");
15148 /* "interleave" version also handles non-interleaving register VLD1/VST1
15152 do_neon_ld_st_interleave (void)
15154 struct neon_type_el et = neon_check_type (1, NS_NULL,
15155 N_8 | N_16 | N_32 | N_64);
15156 unsigned alignbits = 0;
15158 /* The bits in this table go:
15159 0: register stride of one (0) or two (1)
15160 1,2: register list length, minus one (1, 2, 3, 4).
15161 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15162 We use -1 for invalid entries. */
15163 const int typetable[] =
15165 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15166 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15167 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15168 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15172 if (et.type == NT_invtype)
15175 if (inst.operands[1].immisalign)
15176 switch (inst.operands[1].imm >> 8)
15178 case 64: alignbits = 1; break;
15180 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15181 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15182 goto bad_alignment;
15186 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15187 goto bad_alignment;
15192 first_error (_("bad alignment"));
15196 inst.instruction |= alignbits << 4;
15197 inst.instruction |= neon_logbits (et.size) << 6;
15199 /* Bits [4:6] of the immediate in a list specifier encode register stride
15200 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15201 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15202 up the right value for "type" in a table based on this value and the given
15203 list style, then stick it back. */
15204 idx = ((inst.operands[0].imm >> 4) & 7)
15205 | (((inst.instruction >> 8) & 3) << 3);
15207 typebits = typetable[idx];
15209 constraint (typebits == -1, _("bad list type for instruction"));
15211 inst.instruction &= ~0xf00;
15212 inst.instruction |= typebits << 8;
15215 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15216 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15217 otherwise. The variable arguments are a list of pairs of legal (size, align)
15218 values, terminated with -1. */
15221 neon_alignment_bit (int size, int align, int *do_align, ...)
15224 int result = FAIL, thissize, thisalign;
15226 if (!inst.operands[1].immisalign)
15232 va_start (ap, do_align);
15236 thissize = va_arg (ap, int);
15237 if (thissize == -1)
15239 thisalign = va_arg (ap, int);
15241 if (size == thissize && align == thisalign)
15244 while (result != SUCCESS);
15248 if (result == SUCCESS)
15251 first_error (_("unsupported alignment for instruction"));
15257 do_neon_ld_st_lane (void)
15259 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15260 int align_good, do_align = 0;
15261 int logsize = neon_logbits (et.size);
15262 int align = inst.operands[1].imm >> 8;
15263 int n = (inst.instruction >> 8) & 3;
15264 int max_el = 64 / et.size;
15266 if (et.type == NT_invtype)
15269 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15270 _("bad list length"));
15271 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15272 _("scalar index out of range"));
15273 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15275 _("stride of 2 unavailable when element size is 8"));
15279 case 0: /* VLD1 / VST1. */
15280 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15282 if (align_good == FAIL)
15286 unsigned alignbits = 0;
15289 case 16: alignbits = 0x1; break;
15290 case 32: alignbits = 0x3; break;
15293 inst.instruction |= alignbits << 4;
15297 case 1: /* VLD2 / VST2. */
15298 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15300 if (align_good == FAIL)
15303 inst.instruction |= 1 << 4;
15306 case 2: /* VLD3 / VST3. */
15307 constraint (inst.operands[1].immisalign,
15308 _("can't use alignment with this instruction"));
15311 case 3: /* VLD4 / VST4. */
15312 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15313 16, 64, 32, 64, 32, 128, -1);
15314 if (align_good == FAIL)
15318 unsigned alignbits = 0;
15321 case 8: alignbits = 0x1; break;
15322 case 16: alignbits = 0x1; break;
15323 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15326 inst.instruction |= alignbits << 4;
15333 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15334 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15335 inst.instruction |= 1 << (4 + logsize);
15337 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15338 inst.instruction |= logsize << 10;
15341 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15344 do_neon_ld_dup (void)
15346 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15347 int align_good, do_align = 0;
15349 if (et.type == NT_invtype)
15352 switch ((inst.instruction >> 8) & 3)
15354 case 0: /* VLD1. */
15355 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15356 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15357 &do_align, 16, 16, 32, 32, -1);
15358 if (align_good == FAIL)
15360 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15363 case 2: inst.instruction |= 1 << 5; break;
15364 default: first_error (_("bad list length")); return;
15366 inst.instruction |= neon_logbits (et.size) << 6;
15369 case 1: /* VLD2. */
15370 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15371 &do_align, 8, 16, 16, 32, 32, 64, -1);
15372 if (align_good == FAIL)
15374 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15375 _("bad list length"));
15376 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15377 inst.instruction |= 1 << 5;
15378 inst.instruction |= neon_logbits (et.size) << 6;
15381 case 2: /* VLD3. */
15382 constraint (inst.operands[1].immisalign,
15383 _("can't use alignment with this instruction"));
15384 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15385 _("bad list length"));
15386 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15387 inst.instruction |= 1 << 5;
15388 inst.instruction |= neon_logbits (et.size) << 6;
15391 case 3: /* VLD4. */
15393 int align = inst.operands[1].imm >> 8;
15394 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15395 16, 64, 32, 64, 32, 128, -1);
15396 if (align_good == FAIL)
15398 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15399 _("bad list length"));
15400 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15401 inst.instruction |= 1 << 5;
15402 if (et.size == 32 && align == 128)
15403 inst.instruction |= 0x3 << 6;
15405 inst.instruction |= neon_logbits (et.size) << 6;
15412 inst.instruction |= do_align << 4;
15415 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15416 apart from bits [11:4]. */
15419 do_neon_ldx_stx (void)
15421 if (inst.operands[1].isreg)
15422 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15424 switch (NEON_LANE (inst.operands[0].imm))
15426 case NEON_INTERLEAVE_LANES:
15427 NEON_ENCODE (INTERLV, inst);
15428 do_neon_ld_st_interleave ();
15431 case NEON_ALL_LANES:
15432 NEON_ENCODE (DUP, inst);
15437 NEON_ENCODE (LANE, inst);
15438 do_neon_ld_st_lane ();
15441 /* L bit comes from bit mask. */
15442 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15443 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15444 inst.instruction |= inst.operands[1].reg << 16;
15446 if (inst.operands[1].postind)
15448 int postreg = inst.operands[1].imm & 0xf;
15449 constraint (!inst.operands[1].immisreg,
15450 _("post-index must be a register"));
15451 constraint (postreg == 0xd || postreg == 0xf,
15452 _("bad register for post-index"));
15453 inst.instruction |= postreg;
15455 else if (inst.operands[1].writeback)
15457 inst.instruction |= 0xd;
15460 inst.instruction |= 0xf;
15463 inst.instruction |= 0xf9000000;
15465 inst.instruction |= 0xf4000000;
15468 /* Overall per-instruction processing. */
15470 /* We need to be able to fix up arbitrary expressions in some statements.
15471 This is so that we can handle symbols that are an arbitrary distance from
15472 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15473 which returns part of an address in a form which will be valid for
15474 a data instruction. We do this by pushing the expression into a symbol
15475 in the expr_section, and creating a fix for that. */
15478 fix_new_arm (fragS * frag,
15492 /* Create an absolute valued symbol, so we have something to
15493 refer to in the object file. Unfortunately for us, gas's
15494 generic expression parsing will already have folded out
15495 any use of .set foo/.type foo %function that may have
15496 been used to set type information of the target location,
15497 that's being specified symbolically. We have to presume
15498 the user knows what they are doing. */
15502 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15504 symbol = symbol_find_or_make (name);
15505 S_SET_SEGMENT (symbol, absolute_section);
15506 symbol_set_frag (symbol, &zero_address_frag);
15507 S_SET_VALUE (symbol, exp->X_add_number);
15508 exp->X_op = O_symbol;
15509 exp->X_add_symbol = symbol;
15510 exp->X_add_number = 0;
15516 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15517 (enum bfd_reloc_code_real) reloc);
15521 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15522 pc_rel, (enum bfd_reloc_code_real) reloc);
15526 /* Mark whether the fix is to a THUMB instruction, or an ARM
15528 new_fix->tc_fix_data = thumb_mode;
15531 /* Create a frg for an instruction requiring relaxation. */
15533 output_relax_insn (void)
15539 /* The size of the instruction is unknown, so tie the debug info to the
15540 start of the instruction. */
15541 dwarf2_emit_insn (0);
15543 switch (inst.reloc.exp.X_op)
15546 sym = inst.reloc.exp.X_add_symbol;
15547 offset = inst.reloc.exp.X_add_number;
15551 offset = inst.reloc.exp.X_add_number;
15554 sym = make_expr_symbol (&inst.reloc.exp);
15558 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15559 inst.relax, sym, offset, NULL/*offset, opcode*/);
15560 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15563 /* Write a 32-bit thumb instruction to buf. */
15565 put_thumb32_insn (char * buf, unsigned long insn)
15567 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15568 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15572 output_inst (const char * str)
15578 as_bad ("%s -- `%s'", inst.error, str);
15583 output_relax_insn ();
15586 if (inst.size == 0)
15589 to = frag_more (inst.size);
15590 /* PR 9814: Record the thumb mode into the current frag so that we know
15591 what type of NOP padding to use, if necessary. We override any previous
15592 setting so that if the mode has changed then the NOPS that we use will
15593 match the encoding of the last instruction in the frag. */
15594 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15596 if (thumb_mode && (inst.size > THUMB_SIZE))
15598 gas_assert (inst.size == (2 * THUMB_SIZE));
15599 put_thumb32_insn (to, inst.instruction);
15601 else if (inst.size > INSN_SIZE)
15603 gas_assert (inst.size == (2 * INSN_SIZE));
15604 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15605 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15608 md_number_to_chars (to, inst.instruction, inst.size);
15610 if (inst.reloc.type != BFD_RELOC_UNUSED)
15611 fix_new_arm (frag_now, to - frag_now->fr_literal,
15612 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15615 dwarf2_emit_insn (inst.size);
15619 output_it_inst (int cond, int mask, char * to)
15621 unsigned long instruction = 0xbf00;
15624 instruction |= mask;
15625 instruction |= cond << 4;
15629 to = frag_more (2);
15631 dwarf2_emit_insn (2);
15635 md_number_to_chars (to, instruction, 2);
15640 /* Tag values used in struct asm_opcode's tag field. */
15643 OT_unconditional, /* Instruction cannot be conditionalized.
15644 The ARM condition field is still 0xE. */
15645 OT_unconditionalF, /* Instruction cannot be conditionalized
15646 and carries 0xF in its ARM condition field. */
15647 OT_csuffix, /* Instruction takes a conditional suffix. */
15648 OT_csuffixF, /* Some forms of the instruction take a conditional
15649 suffix, others place 0xF where the condition field
15651 OT_cinfix3, /* Instruction takes a conditional infix,
15652 beginning at character index 3. (In
15653 unified mode, it becomes a suffix.) */
15654 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15655 tsts, cmps, cmns, and teqs. */
15656 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15657 character index 3, even in unified mode. Used for
15658 legacy instructions where suffix and infix forms
15659 may be ambiguous. */
15660 OT_csuf_or_in3, /* Instruction takes either a conditional
15661 suffix or an infix at character index 3. */
15662 OT_odd_infix_unc, /* This is the unconditional variant of an
15663 instruction that takes a conditional infix
15664 at an unusual position. In unified mode,
15665 this variant will accept a suffix. */
15666 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15667 are the conditional variants of instructions that
15668 take conditional infixes in unusual positions.
15669 The infix appears at character index
15670 (tag - OT_odd_infix_0). These are not accepted
15671 in unified mode. */
15674 /* Subroutine of md_assemble, responsible for looking up the primary
15675 opcode from the mnemonic the user wrote. STR points to the
15676 beginning of the mnemonic.
15678 This is not simply a hash table lookup, because of conditional
15679 variants. Most instructions have conditional variants, which are
15680 expressed with a _conditional affix_ to the mnemonic. If we were
15681 to encode each conditional variant as a literal string in the opcode
15682 table, it would have approximately 20,000 entries.
15684 Most mnemonics take this affix as a suffix, and in unified syntax,
15685 'most' is upgraded to 'all'. However, in the divided syntax, some
15686 instructions take the affix as an infix, notably the s-variants of
15687 the arithmetic instructions. Of those instructions, all but six
15688 have the infix appear after the third character of the mnemonic.
15690 Accordingly, the algorithm for looking up primary opcodes given
15693 1. Look up the identifier in the opcode table.
15694 If we find a match, go to step U.
15696 2. Look up the last two characters of the identifier in the
15697 conditions table. If we find a match, look up the first N-2
15698 characters of the identifier in the opcode table. If we
15699 find a match, go to step CE.
15701 3. Look up the fourth and fifth characters of the identifier in
15702 the conditions table. If we find a match, extract those
15703 characters from the identifier, and look up the remaining
15704 characters in the opcode table. If we find a match, go
15709 U. Examine the tag field of the opcode structure, in case this is
15710 one of the six instructions with its conditional infix in an
15711 unusual place. If it is, the tag tells us where to find the
15712 infix; look it up in the conditions table and set inst.cond
15713 accordingly. Otherwise, this is an unconditional instruction.
15714 Again set inst.cond accordingly. Return the opcode structure.
15716 CE. Examine the tag field to make sure this is an instruction that
15717 should receive a conditional suffix. If it is not, fail.
15718 Otherwise, set inst.cond from the suffix we already looked up,
15719 and return the opcode structure.
15721 CM. Examine the tag field to make sure this is an instruction that
15722 should receive a conditional infix after the third character.
15723 If it is not, fail. Otherwise, undo the edits to the current
15724 line of input and proceed as for case CE. */
15726 static const struct asm_opcode *
15727 opcode_lookup (char **str)
15731 const struct asm_opcode *opcode;
15732 const struct asm_cond *cond;
15735 /* Scan up to the end of the mnemonic, which must end in white space,
15736 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15737 for (base = end = *str; *end != '\0'; end++)
15738 if (*end == ' ' || *end == '.')
15744 /* Handle a possible width suffix and/or Neon type suffix. */
15749 /* The .w and .n suffixes are only valid if the unified syntax is in
15751 if (unified_syntax && end[1] == 'w')
15753 else if (unified_syntax && end[1] == 'n')
15758 inst.vectype.elems = 0;
15760 *str = end + offset;
15762 if (end[offset] == '.')
15764 /* See if we have a Neon type suffix (possible in either unified or
15765 non-unified ARM syntax mode). */
15766 if (parse_neon_type (&inst.vectype, str) == FAIL)
15769 else if (end[offset] != '\0' && end[offset] != ' ')
15775 /* Look for unaffixed or special-case affixed mnemonic. */
15776 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15781 if (opcode->tag < OT_odd_infix_0)
15783 inst.cond = COND_ALWAYS;
15787 if (warn_on_deprecated && unified_syntax)
15788 as_warn (_("conditional infixes are deprecated in unified syntax"));
15789 affix = base + (opcode->tag - OT_odd_infix_0);
15790 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15793 inst.cond = cond->value;
15797 /* Cannot have a conditional suffix on a mnemonic of less than two
15799 if (end - base < 3)
15802 /* Look for suffixed mnemonic. */
15804 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15805 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15807 if (opcode && cond)
15810 switch (opcode->tag)
15812 case OT_cinfix3_legacy:
15813 /* Ignore conditional suffixes matched on infix only mnemonics. */
15817 case OT_cinfix3_deprecated:
15818 case OT_odd_infix_unc:
15819 if (!unified_syntax)
15821 /* else fall through */
15825 case OT_csuf_or_in3:
15826 inst.cond = cond->value;
15829 case OT_unconditional:
15830 case OT_unconditionalF:
15832 inst.cond = cond->value;
15835 /* Delayed diagnostic. */
15836 inst.error = BAD_COND;
15837 inst.cond = COND_ALWAYS;
15846 /* Cannot have a usual-position infix on a mnemonic of less than
15847 six characters (five would be a suffix). */
15848 if (end - base < 6)
15851 /* Look for infixed mnemonic in the usual position. */
15853 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15857 memcpy (save, affix, 2);
15858 memmove (affix, affix + 2, (end - affix) - 2);
15859 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15861 memmove (affix + 2, affix, (end - affix) - 2);
15862 memcpy (affix, save, 2);
15865 && (opcode->tag == OT_cinfix3
15866 || opcode->tag == OT_cinfix3_deprecated
15867 || opcode->tag == OT_csuf_or_in3
15868 || opcode->tag == OT_cinfix3_legacy))
15871 if (warn_on_deprecated && unified_syntax
15872 && (opcode->tag == OT_cinfix3
15873 || opcode->tag == OT_cinfix3_deprecated))
15874 as_warn (_("conditional infixes are deprecated in unified syntax"));
15876 inst.cond = cond->value;
15883 /* This function generates an initial IT instruction, leaving its block
15884 virtually open for the new instructions. Eventually,
15885 the mask will be updated by now_it_add_mask () each time
15886 a new instruction needs to be included in the IT block.
15887 Finally, the block is closed with close_automatic_it_block ().
15888 The block closure can be requested either from md_assemble (),
15889 a tencode (), or due to a label hook. */
15892 new_automatic_it_block (int cond)
15894 now_it.state = AUTOMATIC_IT_BLOCK;
15895 now_it.mask = 0x18;
15897 now_it.block_length = 1;
15898 mapping_state (MAP_THUMB);
15899 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
15902 /* Close an automatic IT block.
15903 See comments in new_automatic_it_block (). */
15906 close_automatic_it_block (void)
15908 now_it.mask = 0x10;
15909 now_it.block_length = 0;
15912 /* Update the mask of the current automatically-generated IT
15913 instruction. See comments in new_automatic_it_block (). */
15916 now_it_add_mask (int cond)
15918 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15919 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15920 | ((bitvalue) << (nbit)))
15921 const int resulting_bit = (cond & 1);
15923 now_it.mask &= 0xf;
15924 now_it.mask = SET_BIT_VALUE (now_it.mask,
15926 (5 - now_it.block_length));
15927 now_it.mask = SET_BIT_VALUE (now_it.mask,
15929 ((5 - now_it.block_length) - 1) );
15930 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
15933 #undef SET_BIT_VALUE
15936 /* The IT blocks handling machinery is accessed through the these functions:
15937 it_fsm_pre_encode () from md_assemble ()
15938 set_it_insn_type () optional, from the tencode functions
15939 set_it_insn_type_last () ditto
15940 in_it_block () ditto
15941 it_fsm_post_encode () from md_assemble ()
15942 force_automatic_it_block_close () from label habdling functions
15945 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15946 initializing the IT insn type with a generic initial value depending
15947 on the inst.condition.
15948 2) During the tencode function, two things may happen:
15949 a) The tencode function overrides the IT insn type by
15950 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15951 b) The tencode function queries the IT block state by
15952 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15954 Both set_it_insn_type and in_it_block run the internal FSM state
15955 handling function (handle_it_state), because: a) setting the IT insn
15956 type may incur in an invalid state (exiting the function),
15957 and b) querying the state requires the FSM to be updated.
15958 Specifically we want to avoid creating an IT block for conditional
15959 branches, so it_fsm_pre_encode is actually a guess and we can't
15960 determine whether an IT block is required until the tencode () routine
15961 has decided what type of instruction this actually it.
15962 Because of this, if set_it_insn_type and in_it_block have to be used,
15963 set_it_insn_type has to be called first.
15965 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15966 determines the insn IT type depending on the inst.cond code.
15967 When a tencode () routine encodes an instruction that can be
15968 either outside an IT block, or, in the case of being inside, has to be
15969 the last one, set_it_insn_type_last () will determine the proper
15970 IT instruction type based on the inst.cond code. Otherwise,
15971 set_it_insn_type can be called for overriding that logic or
15972 for covering other cases.
15974 Calling handle_it_state () may not transition the IT block state to
15975 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15976 still queried. Instead, if the FSM determines that the state should
15977 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15978 after the tencode () function: that's what it_fsm_post_encode () does.
15980 Since in_it_block () calls the state handling function to get an
15981 updated state, an error may occur (due to invalid insns combination).
15982 In that case, inst.error is set.
15983 Therefore, inst.error has to be checked after the execution of
15984 the tencode () routine.
15986 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15987 any pending state change (if any) that didn't take place in
15988 handle_it_state () as explained above. */
15991 it_fsm_pre_encode (void)
15993 if (inst.cond != COND_ALWAYS)
15994 inst.it_insn_type = INSIDE_IT_INSN;
15996 inst.it_insn_type = OUTSIDE_IT_INSN;
15998 now_it.state_handled = 0;
16001 /* IT state FSM handling function. */
16004 handle_it_state (void)
16006 now_it.state_handled = 1;
16008 switch (now_it.state)
16010 case OUTSIDE_IT_BLOCK:
16011 switch (inst.it_insn_type)
16013 case OUTSIDE_IT_INSN:
16016 case INSIDE_IT_INSN:
16017 case INSIDE_IT_LAST_INSN:
16018 if (thumb_mode == 0)
16021 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16022 as_tsktsk (_("Warning: conditional outside an IT block"\
16027 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16028 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16030 /* Automatically generate the IT instruction. */
16031 new_automatic_it_block (inst.cond);
16032 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16033 close_automatic_it_block ();
16037 inst.error = BAD_OUT_IT;
16043 case IF_INSIDE_IT_LAST_INSN:
16044 case NEUTRAL_IT_INSN:
16048 now_it.state = MANUAL_IT_BLOCK;
16049 now_it.block_length = 0;
16054 case AUTOMATIC_IT_BLOCK:
16055 /* Three things may happen now:
16056 a) We should increment current it block size;
16057 b) We should close current it block (closing insn or 4 insns);
16058 c) We should close current it block and start a new one (due
16059 to incompatible conditions or
16060 4 insns-length block reached). */
16062 switch (inst.it_insn_type)
16064 case OUTSIDE_IT_INSN:
16065 /* The closure of the block shall happen immediatelly,
16066 so any in_it_block () call reports the block as closed. */
16067 force_automatic_it_block_close ();
16070 case INSIDE_IT_INSN:
16071 case INSIDE_IT_LAST_INSN:
16072 case IF_INSIDE_IT_LAST_INSN:
16073 now_it.block_length++;
16075 if (now_it.block_length > 4
16076 || !now_it_compatible (inst.cond))
16078 force_automatic_it_block_close ();
16079 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16080 new_automatic_it_block (inst.cond);
16084 now_it_add_mask (inst.cond);
16087 if (now_it.state == AUTOMATIC_IT_BLOCK
16088 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16089 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16090 close_automatic_it_block ();
16093 case NEUTRAL_IT_INSN:
16094 now_it.block_length++;
16096 if (now_it.block_length > 4)
16097 force_automatic_it_block_close ();
16099 now_it_add_mask (now_it.cc & 1);
16103 close_automatic_it_block ();
16104 now_it.state = MANUAL_IT_BLOCK;
16109 case MANUAL_IT_BLOCK:
16111 /* Check conditional suffixes. */
16112 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16115 now_it.mask &= 0x1f;
16116 is_last = (now_it.mask == 0x10);
16118 switch (inst.it_insn_type)
16120 case OUTSIDE_IT_INSN:
16121 inst.error = BAD_NOT_IT;
16124 case INSIDE_IT_INSN:
16125 if (cond != inst.cond)
16127 inst.error = BAD_IT_COND;
16132 case INSIDE_IT_LAST_INSN:
16133 case IF_INSIDE_IT_LAST_INSN:
16134 if (cond != inst.cond)
16136 inst.error = BAD_IT_COND;
16141 inst.error = BAD_BRANCH;
16146 case NEUTRAL_IT_INSN:
16147 /* The BKPT instruction is unconditional even in an IT block. */
16151 inst.error = BAD_IT_IT;
16162 it_fsm_post_encode (void)
16166 if (!now_it.state_handled)
16167 handle_it_state ();
16169 is_last = (now_it.mask == 0x10);
16172 now_it.state = OUTSIDE_IT_BLOCK;
16178 force_automatic_it_block_close (void)
16180 if (now_it.state == AUTOMATIC_IT_BLOCK)
16182 close_automatic_it_block ();
16183 now_it.state = OUTSIDE_IT_BLOCK;
16191 if (!now_it.state_handled)
16192 handle_it_state ();
16194 return now_it.state != OUTSIDE_IT_BLOCK;
16198 md_assemble (char *str)
16201 const struct asm_opcode * opcode;
16203 /* Align the previous label if needed. */
16204 if (last_label_seen != NULL)
16206 symbol_set_frag (last_label_seen, frag_now);
16207 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16208 S_SET_SEGMENT (last_label_seen, now_seg);
16211 memset (&inst, '\0', sizeof (inst));
16212 inst.reloc.type = BFD_RELOC_UNUSED;
16214 opcode = opcode_lookup (&p);
16217 /* It wasn't an instruction, but it might be a register alias of
16218 the form alias .req reg, or a Neon .dn/.qn directive. */
16219 if (! create_register_alias (str, p)
16220 && ! create_neon_reg_alias (str, p))
16221 as_bad (_("bad instruction `%s'"), str);
16226 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16227 as_warn (_("s suffix on comparison instruction is deprecated"));
16229 /* The value which unconditional instructions should have in place of the
16230 condition field. */
16231 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16235 arm_feature_set variant;
16237 variant = cpu_variant;
16238 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16239 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16240 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16241 /* Check that this instruction is supported for this CPU. */
16242 if (!opcode->tvariant
16243 || (thumb_mode == 1
16244 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16246 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16249 if (inst.cond != COND_ALWAYS && !unified_syntax
16250 && opcode->tencode != do_t_branch)
16252 as_bad (_("Thumb does not support conditional execution"));
16256 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16258 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16259 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16260 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16262 /* Two things are addressed here.
16263 1) Implicit require narrow instructions on Thumb-1.
16264 This avoids relaxation accidentally introducing Thumb-2
16266 2) Reject wide instructions in non Thumb-2 cores. */
16267 if (inst.size_req == 0)
16269 else if (inst.size_req == 4)
16271 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16277 inst.instruction = opcode->tvalue;
16279 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16281 /* Prepare the it_insn_type for those encodings that don't set
16283 it_fsm_pre_encode ();
16285 opcode->tencode ();
16287 it_fsm_post_encode ();
16290 if (!(inst.error || inst.relax))
16292 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16293 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16294 if (inst.size_req && inst.size_req != inst.size)
16296 as_bad (_("cannot honor width suffix -- `%s'"), str);
16301 /* Something has gone badly wrong if we try to relax a fixed size
16303 gas_assert (inst.size_req == 0 || !inst.relax);
16305 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16306 *opcode->tvariant);
16307 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16308 set those bits when Thumb-2 32-bit instructions are seen. ie.
16309 anything other than bl/blx and v6-M instructions.
16310 This is overly pessimistic for relaxable instructions. */
16311 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16313 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16314 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16315 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16318 check_neon_suffixes;
16322 mapping_state (MAP_THUMB);
16325 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16329 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16330 is_bx = (opcode->aencode == do_bx);
16332 /* Check that this instruction is supported for this CPU. */
16333 if (!(is_bx && fix_v4bx)
16334 && !(opcode->avariant &&
16335 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16337 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16342 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16346 inst.instruction = opcode->avalue;
16347 if (opcode->tag == OT_unconditionalF)
16348 inst.instruction |= 0xF << 28;
16350 inst.instruction |= inst.cond << 28;
16351 inst.size = INSN_SIZE;
16352 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16354 it_fsm_pre_encode ();
16355 opcode->aencode ();
16356 it_fsm_post_encode ();
16358 /* Arm mode bx is marked as both v4T and v5 because it's still required
16359 on a hypothetical non-thumb v5 core. */
16361 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16363 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16364 *opcode->avariant);
16366 check_neon_suffixes;
16370 mapping_state (MAP_ARM);
16375 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16383 check_it_blocks_finished (void)
16388 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16389 if (seg_info (sect)->tc_segment_info_data.current_it.state
16390 == MANUAL_IT_BLOCK)
16392 as_warn (_("section '%s' finished with an open IT block."),
16396 if (now_it.state == MANUAL_IT_BLOCK)
16397 as_warn (_("file finished with an open IT block."));
16401 /* Various frobbings of labels and their addresses. */
16404 arm_start_line_hook (void)
16406 last_label_seen = NULL;
16410 arm_frob_label (symbolS * sym)
16412 last_label_seen = sym;
16414 ARM_SET_THUMB (sym, thumb_mode);
16416 #if defined OBJ_COFF || defined OBJ_ELF
16417 ARM_SET_INTERWORK (sym, support_interwork);
16420 force_automatic_it_block_close ();
16422 /* Note - do not allow local symbols (.Lxxx) to be labelled
16423 as Thumb functions. This is because these labels, whilst
16424 they exist inside Thumb code, are not the entry points for
16425 possible ARM->Thumb calls. Also, these labels can be used
16426 as part of a computed goto or switch statement. eg gcc
16427 can generate code that looks like this:
16429 ldr r2, [pc, .Laaa]
16439 The first instruction loads the address of the jump table.
16440 The second instruction converts a table index into a byte offset.
16441 The third instruction gets the jump address out of the table.
16442 The fourth instruction performs the jump.
16444 If the address stored at .Laaa is that of a symbol which has the
16445 Thumb_Func bit set, then the linker will arrange for this address
16446 to have the bottom bit set, which in turn would mean that the
16447 address computation performed by the third instruction would end
16448 up with the bottom bit set. Since the ARM is capable of unaligned
16449 word loads, the instruction would then load the incorrect address
16450 out of the jump table, and chaos would ensue. */
16451 if (label_is_thumb_function_name
16452 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16453 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16455 /* When the address of a Thumb function is taken the bottom
16456 bit of that address should be set. This will allow
16457 interworking between Arm and Thumb functions to work
16460 THUMB_SET_FUNC (sym, 1);
16462 label_is_thumb_function_name = FALSE;
16465 dwarf2_emit_label (sym);
16469 arm_data_in_code (void)
16471 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16473 *input_line_pointer = '/';
16474 input_line_pointer += 5;
16475 *input_line_pointer = 0;
16483 arm_canonicalize_symbol_name (char * name)
16487 if (thumb_mode && (len = strlen (name)) > 5
16488 && streq (name + len - 5, "/data"))
16489 *(name + len - 5) = 0;
16494 /* Table of all register names defined by default. The user can
16495 define additional names with .req. Note that all register names
16496 should appear in both upper and lowercase variants. Some registers
16497 also have mixed-case names. */
16499 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16500 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16501 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16502 #define REGSET(p,t) \
16503 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16504 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16505 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16506 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16507 #define REGSETH(p,t) \
16508 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16509 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16510 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16511 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16512 #define REGSET2(p,t) \
16513 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16514 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16515 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16516 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16517 #define SPLRBANK(base,bank,t) \
16518 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16519 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16520 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16521 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16522 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16523 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16525 static const struct reg_entry reg_names[] =
16527 /* ARM integer registers. */
16528 REGSET(r, RN), REGSET(R, RN),
16530 /* ATPCS synonyms. */
16531 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16532 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16533 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16535 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16536 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16537 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16539 /* Well-known aliases. */
16540 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16541 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16543 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16544 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16546 /* Coprocessor numbers. */
16547 REGSET(p, CP), REGSET(P, CP),
16549 /* Coprocessor register numbers. The "cr" variants are for backward
16551 REGSET(c, CN), REGSET(C, CN),
16552 REGSET(cr, CN), REGSET(CR, CN),
16554 /* ARM banked registers. */
16555 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16556 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16557 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16558 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16559 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16560 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16561 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16563 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16564 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16565 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16566 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16567 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16568 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16569 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16570 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16572 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16573 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16574 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16575 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16576 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16577 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16578 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16579 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16580 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16582 /* FPA registers. */
16583 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16584 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16586 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16587 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16589 /* VFP SP registers. */
16590 REGSET(s,VFS), REGSET(S,VFS),
16591 REGSETH(s,VFS), REGSETH(S,VFS),
16593 /* VFP DP Registers. */
16594 REGSET(d,VFD), REGSET(D,VFD),
16595 /* Extra Neon DP registers. */
16596 REGSETH(d,VFD), REGSETH(D,VFD),
16598 /* Neon QP registers. */
16599 REGSET2(q,NQ), REGSET2(Q,NQ),
16601 /* VFP control registers. */
16602 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16603 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16604 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16605 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16606 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16607 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16609 /* Maverick DSP coprocessor registers. */
16610 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16611 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16613 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16614 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16615 REGDEF(dspsc,0,DSPSC),
16617 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16618 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16619 REGDEF(DSPSC,0,DSPSC),
16621 /* iWMMXt data registers - p0, c0-15. */
16622 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16624 /* iWMMXt control registers - p1, c0-3. */
16625 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16626 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16627 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16628 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16630 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16631 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16632 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16633 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16634 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16636 /* XScale accumulator registers. */
16637 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16643 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16644 within psr_required_here. */
16645 static const struct asm_psr psrs[] =
16647 /* Backward compatibility notation. Note that "all" is no longer
16648 truly all possible PSR bits. */
16649 {"all", PSR_c | PSR_f},
16653 /* Individual flags. */
16659 /* Combinations of flags. */
16660 {"fs", PSR_f | PSR_s},
16661 {"fx", PSR_f | PSR_x},
16662 {"fc", PSR_f | PSR_c},
16663 {"sf", PSR_s | PSR_f},
16664 {"sx", PSR_s | PSR_x},
16665 {"sc", PSR_s | PSR_c},
16666 {"xf", PSR_x | PSR_f},
16667 {"xs", PSR_x | PSR_s},
16668 {"xc", PSR_x | PSR_c},
16669 {"cf", PSR_c | PSR_f},
16670 {"cs", PSR_c | PSR_s},
16671 {"cx", PSR_c | PSR_x},
16672 {"fsx", PSR_f | PSR_s | PSR_x},
16673 {"fsc", PSR_f | PSR_s | PSR_c},
16674 {"fxs", PSR_f | PSR_x | PSR_s},
16675 {"fxc", PSR_f | PSR_x | PSR_c},
16676 {"fcs", PSR_f | PSR_c | PSR_s},
16677 {"fcx", PSR_f | PSR_c | PSR_x},
16678 {"sfx", PSR_s | PSR_f | PSR_x},
16679 {"sfc", PSR_s | PSR_f | PSR_c},
16680 {"sxf", PSR_s | PSR_x | PSR_f},
16681 {"sxc", PSR_s | PSR_x | PSR_c},
16682 {"scf", PSR_s | PSR_c | PSR_f},
16683 {"scx", PSR_s | PSR_c | PSR_x},
16684 {"xfs", PSR_x | PSR_f | PSR_s},
16685 {"xfc", PSR_x | PSR_f | PSR_c},
16686 {"xsf", PSR_x | PSR_s | PSR_f},
16687 {"xsc", PSR_x | PSR_s | PSR_c},
16688 {"xcf", PSR_x | PSR_c | PSR_f},
16689 {"xcs", PSR_x | PSR_c | PSR_s},
16690 {"cfs", PSR_c | PSR_f | PSR_s},
16691 {"cfx", PSR_c | PSR_f | PSR_x},
16692 {"csf", PSR_c | PSR_s | PSR_f},
16693 {"csx", PSR_c | PSR_s | PSR_x},
16694 {"cxf", PSR_c | PSR_x | PSR_f},
16695 {"cxs", PSR_c | PSR_x | PSR_s},
16696 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16697 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16698 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16699 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16700 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16701 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16702 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16703 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16704 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16705 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16706 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16707 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16708 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16709 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16710 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16711 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16712 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16713 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16714 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16715 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16716 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16717 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16718 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16719 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16722 /* Table of V7M psr names. */
16723 static const struct asm_psr v7m_psrs[] =
16725 {"apsr", 0 }, {"APSR", 0 },
16726 {"iapsr", 1 }, {"IAPSR", 1 },
16727 {"eapsr", 2 }, {"EAPSR", 2 },
16728 {"psr", 3 }, {"PSR", 3 },
16729 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16730 {"ipsr", 5 }, {"IPSR", 5 },
16731 {"epsr", 6 }, {"EPSR", 6 },
16732 {"iepsr", 7 }, {"IEPSR", 7 },
16733 {"msp", 8 }, {"MSP", 8 },
16734 {"psp", 9 }, {"PSP", 9 },
16735 {"primask", 16}, {"PRIMASK", 16},
16736 {"basepri", 17}, {"BASEPRI", 17},
16737 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16738 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16739 {"faultmask", 19}, {"FAULTMASK", 19},
16740 {"control", 20}, {"CONTROL", 20}
16743 /* Table of all shift-in-operand names. */
16744 static const struct asm_shift_name shift_names [] =
16746 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16747 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16748 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16749 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16750 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16751 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16754 /* Table of all explicit relocation names. */
16756 static struct reloc_entry reloc_names[] =
16758 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16759 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16760 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16761 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16762 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16763 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16764 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16765 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16766 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16767 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16768 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16769 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16770 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16771 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16772 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16773 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16774 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16775 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16779 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16780 static const struct asm_cond conds[] =
16784 {"cs", 0x2}, {"hs", 0x2},
16785 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16799 static struct asm_barrier_opt barrier_opt_names[] =
16801 { "sy", 0xf }, { "SY", 0xf },
16802 { "un", 0x7 }, { "UN", 0x7 },
16803 { "st", 0xe }, { "ST", 0xe },
16804 { "unst", 0x6 }, { "UNST", 0x6 },
16805 { "ish", 0xb }, { "ISH", 0xb },
16806 { "sh", 0xb }, { "SH", 0xb },
16807 { "ishst", 0xa }, { "ISHST", 0xa },
16808 { "shst", 0xa }, { "SHST", 0xa },
16809 { "nsh", 0x7 }, { "NSH", 0x7 },
16810 { "nshst", 0x6 }, { "NSHST", 0x6 },
16811 { "osh", 0x3 }, { "OSH", 0x3 },
16812 { "oshst", 0x2 }, { "OSHST", 0x2 }
16815 /* Table of ARM-format instructions. */
16817 /* Macros for gluing together operand strings. N.B. In all cases
16818 other than OPS0, the trailing OP_stop comes from default
16819 zero-initialization of the unspecified elements of the array. */
16820 #define OPS0() { OP_stop, }
16821 #define OPS1(a) { OP_##a, }
16822 #define OPS2(a,b) { OP_##a,OP_##b, }
16823 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16824 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16825 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16826 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16828 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16829 This is useful when mixing operands for ARM and THUMB, i.e. using the
16830 MIX_ARM_THUMB_OPERANDS macro.
16831 In order to use these macros, prefix the number of operands with _
16833 #define OPS_1(a) { a, }
16834 #define OPS_2(a,b) { a,b, }
16835 #define OPS_3(a,b,c) { a,b,c, }
16836 #define OPS_4(a,b,c,d) { a,b,c,d, }
16837 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16838 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16840 /* These macros abstract out the exact format of the mnemonic table and
16841 save some repeated characters. */
16843 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16844 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16845 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16846 THUMB_VARIANT, do_##ae, do_##te }
16848 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16849 a T_MNEM_xyz enumerator. */
16850 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16851 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16852 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16853 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16855 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16856 infix after the third character. */
16857 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16858 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16859 THUMB_VARIANT, do_##ae, do_##te }
16860 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16861 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16862 THUMB_VARIANT, do_##ae, do_##te }
16863 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16864 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16865 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16866 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16867 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16868 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16869 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16870 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16872 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16873 appear in the condition table. */
16874 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16875 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16876 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16878 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16879 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16880 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16881 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16882 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16883 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16884 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16885 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16886 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16887 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16888 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16889 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16890 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16891 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16892 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16893 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16894 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16895 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16896 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16897 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16899 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16900 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16901 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16902 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16904 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16905 field is still 0xE. Many of the Thumb variants can be executed
16906 conditionally, so this is checked separately. */
16907 #define TUE(mnem, op, top, nops, ops, ae, te) \
16908 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16909 THUMB_VARIANT, do_##ae, do_##te }
16911 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16912 condition code field. */
16913 #define TUF(mnem, op, top, nops, ops, ae, te) \
16914 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16915 THUMB_VARIANT, do_##ae, do_##te }
16917 /* ARM-only variants of all the above. */
16918 #define CE(mnem, op, nops, ops, ae) \
16919 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16921 #define C3(mnem, op, nops, ops, ae) \
16922 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16924 /* Legacy mnemonics that always have conditional infix after the third
16926 #define CL(mnem, op, nops, ops, ae) \
16927 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16928 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16930 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16931 #define cCE(mnem, op, nops, ops, ae) \
16932 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16934 /* Legacy coprocessor instructions where conditional infix and conditional
16935 suffix are ambiguous. For consistency this includes all FPA instructions,
16936 not just the potentially ambiguous ones. */
16937 #define cCL(mnem, op, nops, ops, ae) \
16938 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16939 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16941 /* Coprocessor, takes either a suffix or a position-3 infix
16942 (for an FPA corner case). */
16943 #define C3E(mnem, op, nops, ops, ae) \
16944 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16945 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16947 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16948 { m1 #m2 m3, OPS##nops ops, \
16949 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16950 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16952 #define CM(m1, m2, op, nops, ops, ae) \
16953 xCM_ (m1, , m2, op, nops, ops, ae), \
16954 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16955 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16956 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16957 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16958 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16959 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16960 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16961 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16962 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16963 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16964 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16965 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16966 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16967 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16968 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16969 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16970 xCM_ (m1, le, m2, op, nops, ops, ae), \
16971 xCM_ (m1, al, m2, op, nops, ops, ae)
16973 #define UE(mnem, op, nops, ops, ae) \
16974 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16976 #define UF(mnem, op, nops, ops, ae) \
16977 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16979 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16980 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16981 use the same encoding function for each. */
16982 #define NUF(mnem, op, nops, ops, enc) \
16983 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16984 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16986 /* Neon data processing, version which indirects through neon_enc_tab for
16987 the various overloaded versions of opcodes. */
16988 #define nUF(mnem, op, nops, ops, enc) \
16989 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16990 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16992 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16994 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16995 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16996 THUMB_VARIANT, do_##enc, do_##enc }
16998 #define NCE(mnem, op, nops, ops, enc) \
16999 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17001 #define NCEF(mnem, op, nops, ops, enc) \
17002 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17004 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17005 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17006 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17007 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17009 #define nCE(mnem, op, nops, ops, enc) \
17010 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17012 #define nCEF(mnem, op, nops, ops, enc) \
17013 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17017 static const struct asm_opcode insns[] =
17019 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17020 #define THUMB_VARIANT &arm_ext_v4t
17021 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17022 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17023 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17024 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17025 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17026 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17027 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17028 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17029 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17030 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17031 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17032 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17033 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17034 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17035 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17036 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17038 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17039 for setting PSR flag bits. They are obsolete in V6 and do not
17040 have Thumb equivalents. */
17041 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17042 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17043 CL("tstp", 110f000, 2, (RR, SH), cmp),
17044 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17045 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17046 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17047 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17048 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17049 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17051 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17052 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17053 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17054 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17056 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17057 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17058 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17060 OP_ADDRGLDR),ldst, t_ldst),
17061 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17063 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17064 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17065 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17066 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17067 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17068 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17070 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17071 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17072 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17073 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17076 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17077 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17078 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17080 /* Thumb-compatibility pseudo ops. */
17081 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17082 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17083 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17084 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17085 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17086 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17087 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17088 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17089 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17090 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17091 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17092 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17094 /* These may simplify to neg. */
17095 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17096 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17098 #undef THUMB_VARIANT
17099 #define THUMB_VARIANT & arm_ext_v6
17101 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17103 /* V1 instructions with no Thumb analogue prior to V6T2. */
17104 #undef THUMB_VARIANT
17105 #define THUMB_VARIANT & arm_ext_v6t2
17107 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17108 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17109 CL("teqp", 130f000, 2, (RR, SH), cmp),
17111 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17112 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17113 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17114 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17116 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17117 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17119 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17120 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17122 /* V1 instructions with no Thumb analogue at all. */
17123 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17124 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17126 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17127 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17128 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17129 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17130 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17131 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17132 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17133 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17136 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17137 #undef THUMB_VARIANT
17138 #define THUMB_VARIANT & arm_ext_v4t
17140 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17141 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17143 #undef THUMB_VARIANT
17144 #define THUMB_VARIANT & arm_ext_v6t2
17146 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17147 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17149 /* Generic coprocessor instructions. */
17150 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17151 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17152 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17153 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17154 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17155 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17156 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17159 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17161 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17162 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17165 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17166 #undef THUMB_VARIANT
17167 #define THUMB_VARIANT & arm_ext_msr
17169 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17170 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17173 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17174 #undef THUMB_VARIANT
17175 #define THUMB_VARIANT & arm_ext_v6t2
17177 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17178 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17179 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17180 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17181 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17182 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17183 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17184 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17187 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17188 #undef THUMB_VARIANT
17189 #define THUMB_VARIANT & arm_ext_v4t
17191 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17192 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17193 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17194 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17195 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17196 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17199 #define ARM_VARIANT & arm_ext_v4t_5
17201 /* ARM Architecture 4T. */
17202 /* Note: bx (and blx) are required on V5, even if the processor does
17203 not support Thumb. */
17204 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17207 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17208 #undef THUMB_VARIANT
17209 #define THUMB_VARIANT & arm_ext_v5t
17211 /* Note: blx has 2 variants; the .value coded here is for
17212 BLX(2). Only this variant has conditional execution. */
17213 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17214 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17216 #undef THUMB_VARIANT
17217 #define THUMB_VARIANT & arm_ext_v6t2
17219 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17220 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17221 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17222 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17223 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17224 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17225 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17226 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17229 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17230 #undef THUMB_VARIANT
17231 #define THUMB_VARIANT &arm_ext_v5exp
17233 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17234 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17235 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17236 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17238 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17239 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17241 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17242 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17243 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17244 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17246 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17247 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17248 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17249 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17251 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17252 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17254 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17255 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17256 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17257 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17260 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17261 #undef THUMB_VARIANT
17262 #define THUMB_VARIANT &arm_ext_v6t2
17264 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17265 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17267 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17268 ADDRGLDRS), ldrd, t_ldstd),
17270 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17271 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17274 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17276 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17279 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17280 #undef THUMB_VARIANT
17281 #define THUMB_VARIANT & arm_ext_v6
17283 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17284 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17285 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17286 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17287 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17288 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17289 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17290 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17291 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17292 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17294 #undef THUMB_VARIANT
17295 #define THUMB_VARIANT & arm_ext_v6t2
17297 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17298 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17300 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17301 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17303 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17304 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17306 /* ARM V6 not included in V7M. */
17307 #undef THUMB_VARIANT
17308 #define THUMB_VARIANT & arm_ext_v6_notm
17309 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17310 UF(rfeib, 9900a00, 1, (RRw), rfe),
17311 UF(rfeda, 8100a00, 1, (RRw), rfe),
17312 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17313 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17314 UF(rfefa, 9900a00, 1, (RRw), rfe),
17315 UF(rfeea, 8100a00, 1, (RRw), rfe),
17316 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17317 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17318 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17319 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17320 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17322 /* ARM V6 not included in V7M (eg. integer SIMD). */
17323 #undef THUMB_VARIANT
17324 #define THUMB_VARIANT & arm_ext_v6_dsp
17325 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17326 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17327 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17328 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17329 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17330 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17331 /* Old name for QASX. */
17332 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17333 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17334 /* Old name for QSAX. */
17335 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17336 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17337 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17338 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17339 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17340 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17341 /* Old name for SASX. */
17342 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17343 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17344 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17345 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17346 /* Old name for SHASX. */
17347 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17348 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17349 /* Old name for SHSAX. */
17350 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17351 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17352 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17353 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17354 /* Old name for SSAX. */
17355 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17356 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17357 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17358 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17359 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17360 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17361 /* Old name for UASX. */
17362 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17363 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17364 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17365 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17366 /* Old name for UHASX. */
17367 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17368 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17369 /* Old name for UHSAX. */
17370 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17371 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17372 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17373 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17374 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17375 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17376 /* Old name for UQASX. */
17377 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17378 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17379 /* Old name for UQSAX. */
17380 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17381 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17382 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17383 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17384 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17385 /* Old name for USAX. */
17386 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17387 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17388 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17389 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17390 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17391 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17392 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17393 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17394 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17395 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17396 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17397 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17398 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17399 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17400 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17401 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17402 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17403 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17404 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17405 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17406 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17407 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17408 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17409 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17410 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17411 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17412 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17413 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17414 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17415 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17416 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17417 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17418 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17419 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17422 #define ARM_VARIANT & arm_ext_v6k
17423 #undef THUMB_VARIANT
17424 #define THUMB_VARIANT & arm_ext_v6k
17426 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17427 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17428 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17429 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17431 #undef THUMB_VARIANT
17432 #define THUMB_VARIANT & arm_ext_v6_notm
17433 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17435 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17436 RRnpcb), strexd, t_strexd),
17438 #undef THUMB_VARIANT
17439 #define THUMB_VARIANT & arm_ext_v6t2
17440 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17442 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17444 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17446 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17448 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17451 #define ARM_VARIANT & arm_ext_sec
17452 #undef THUMB_VARIANT
17453 #define THUMB_VARIANT & arm_ext_sec
17455 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17458 #define ARM_VARIANT & arm_ext_virt
17459 #undef THUMB_VARIANT
17460 #define THUMB_VARIANT & arm_ext_virt
17462 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17463 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17466 #define ARM_VARIANT & arm_ext_v6t2
17467 #undef THUMB_VARIANT
17468 #define THUMB_VARIANT & arm_ext_v6t2
17470 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17471 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17472 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17473 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17475 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17476 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17477 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17478 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17480 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17481 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17482 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17483 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17485 /* Thumb-only instructions. */
17487 #define ARM_VARIANT NULL
17488 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17489 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17491 /* ARM does not really have an IT instruction, so always allow it.
17492 The opcode is copied from Thumb in order to allow warnings in
17493 -mimplicit-it=[never | arm] modes. */
17495 #define ARM_VARIANT & arm_ext_v1
17497 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17498 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17499 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17500 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17501 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17502 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17503 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17504 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17505 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17506 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17507 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17508 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17509 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17510 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17511 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17512 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17513 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17514 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17516 /* Thumb2 only instructions. */
17518 #define ARM_VARIANT NULL
17520 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17521 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17522 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17523 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17524 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17525 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17527 /* Hardware division instructions. */
17529 #define ARM_VARIANT & arm_ext_adiv
17530 #undef THUMB_VARIANT
17531 #define THUMB_VARIANT & arm_ext_div
17533 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17534 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17536 /* ARM V6M/V7 instructions. */
17538 #define ARM_VARIANT & arm_ext_barrier
17539 #undef THUMB_VARIANT
17540 #define THUMB_VARIANT & arm_ext_barrier
17542 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17543 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17544 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17546 /* ARM V7 instructions. */
17548 #define ARM_VARIANT & arm_ext_v7
17549 #undef THUMB_VARIANT
17550 #define THUMB_VARIANT & arm_ext_v7
17552 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17553 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17556 #define ARM_VARIANT & arm_ext_mp
17557 #undef THUMB_VARIANT
17558 #define THUMB_VARIANT & arm_ext_mp
17560 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17563 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17565 cCE("wfs", e200110, 1, (RR), rd),
17566 cCE("rfs", e300110, 1, (RR), rd),
17567 cCE("wfc", e400110, 1, (RR), rd),
17568 cCE("rfc", e500110, 1, (RR), rd),
17570 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17571 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17572 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17573 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17575 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17576 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17577 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17578 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17580 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17581 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17582 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17583 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17584 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17585 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17586 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17587 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17588 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17589 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17590 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17591 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17593 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17594 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17595 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17596 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17597 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17598 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17599 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17600 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17601 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17602 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17603 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17604 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17606 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17607 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17608 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17609 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17610 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17611 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17612 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17613 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17614 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17615 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17616 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17617 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17619 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17620 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17621 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17622 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17623 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17624 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17625 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17626 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17627 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17628 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17629 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17630 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17632 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17633 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17634 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17635 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17636 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17637 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17638 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17639 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17640 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17641 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17642 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17643 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17645 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17646 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17647 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17648 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17649 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17650 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17651 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17652 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17653 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17654 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17655 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17656 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17658 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17659 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17660 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17661 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17662 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17663 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17664 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17665 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17666 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17667 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17668 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17669 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17671 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17672 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17673 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17674 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17675 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17676 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17677 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17678 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17679 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17680 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17681 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17682 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17684 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17685 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17686 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17687 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17688 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17689 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17690 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17691 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17692 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17693 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17694 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17695 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17697 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17698 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17699 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17700 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17701 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17702 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17703 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17704 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17705 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17706 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17707 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17708 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17710 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17711 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17712 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17713 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17714 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17715 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17716 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17717 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17718 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17719 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17720 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17721 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17723 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17724 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17725 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17726 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17727 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17728 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17729 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17730 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17731 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17732 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17733 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17734 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17736 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17737 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17738 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17739 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17740 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17741 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17742 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17743 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17744 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17745 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17746 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17747 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17749 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17750 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17751 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17752 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17753 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17754 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17755 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17756 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17757 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17758 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17759 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17760 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17762 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17763 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17764 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17765 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17766 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17767 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17768 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17769 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17770 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17771 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17772 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17773 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17775 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17776 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17777 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17778 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17779 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17780 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17781 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17782 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17783 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17784 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17785 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17786 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17788 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17789 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17790 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17791 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17792 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17793 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17794 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17795 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17796 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17797 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17798 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17799 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17801 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17802 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17803 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17804 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17805 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17806 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17807 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17808 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17809 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17810 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17811 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17812 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17814 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17815 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17816 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17817 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17818 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17819 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17820 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17821 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17822 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17823 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17824 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17825 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17827 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17828 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17829 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17830 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17831 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17832 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17833 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17834 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17835 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17836 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17837 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17838 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17840 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17841 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17842 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17843 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17844 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17845 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17846 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17847 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17848 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17849 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17850 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17851 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17853 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17854 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17855 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17856 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17857 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17858 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17859 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17860 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17861 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17862 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17863 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17864 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17866 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17867 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17868 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17869 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17870 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17871 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17872 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17873 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17874 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17875 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17876 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17877 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17879 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17880 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17881 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17882 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17883 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17884 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17885 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17886 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17887 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17888 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17889 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17890 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
17892 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
17893 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
17894 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
17895 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
17896 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
17897 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17898 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17899 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17900 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
17901 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
17902 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
17903 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
17905 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
17906 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
17907 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
17908 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
17909 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17911 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17913 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17919 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17921 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17922 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17924 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
17958 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
17959 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
17960 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
17962 cCL("flts", e000110, 2, (RF, RR), rn_rd),
17963 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
17964 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
17965 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
17966 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
17967 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
17968 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
17969 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
17970 cCL("flte", e080110, 2, (RF, RR), rn_rd),
17971 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
17972 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
17973 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
17975 /* The implementation of the FIX instruction is broken on some
17976 assemblers, in that it accepts a precision specifier as well as a
17977 rounding specifier, despite the fact that this is meaningless.
17978 To be more compatible, we accept it as well, though of course it
17979 does not set any bits. */
17980 cCE("fix", e100110, 2, (RR, RF), rd_rm),
17981 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
17982 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
17983 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
17984 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
17985 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
17986 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
17987 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
17988 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
17989 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
17990 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
17991 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
17992 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
17994 /* Instructions that were new with the real FPA, call them V2. */
17996 #define ARM_VARIANT & fpu_fpa_ext_v2
17998 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17999 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18000 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18001 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18002 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18003 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18006 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18008 /* Moves and type conversions. */
18009 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18010 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18011 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18012 cCE("fmstat", ef1fa10, 0, (), noargs),
18013 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18014 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18015 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18016 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18017 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18018 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18019 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18020 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18021 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18022 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18024 /* Memory operations. */
18025 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18026 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18027 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18028 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18029 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18030 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18031 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18032 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18033 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18034 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18035 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18036 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18037 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18038 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18039 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18040 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18041 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18042 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18044 /* Monadic operations. */
18045 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18046 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18047 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18049 /* Dyadic operations. */
18050 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18051 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18052 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18053 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18054 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18055 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18056 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18057 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18058 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18061 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18062 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18063 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18064 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18066 /* Double precision load/store are still present on single precision
18067 implementations. */
18068 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18069 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18070 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18071 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18072 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18073 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18074 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18075 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18076 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18077 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18080 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18082 /* Moves and type conversions. */
18083 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18084 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18085 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18086 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18087 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18088 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18089 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18090 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18091 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18092 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18093 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18094 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18095 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18097 /* Monadic operations. */
18098 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18099 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18100 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18102 /* Dyadic operations. */
18103 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18104 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18105 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18106 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18107 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18108 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18109 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18110 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18111 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18114 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18115 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18116 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18117 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18120 #define ARM_VARIANT & fpu_vfp_ext_v2
18122 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18123 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18124 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18125 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18127 /* Instructions which may belong to either the Neon or VFP instruction sets.
18128 Individual encoder functions perform additional architecture checks. */
18130 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18131 #undef THUMB_VARIANT
18132 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18134 /* These mnemonics are unique to VFP. */
18135 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18136 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18137 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18138 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18139 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18140 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18141 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18142 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18143 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18144 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18146 /* Mnemonics shared by Neon and VFP. */
18147 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18148 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18149 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18151 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18152 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18154 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18155 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18157 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18158 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18159 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18160 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18161 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18162 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18163 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18164 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18166 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
18167 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18168 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18169 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18172 /* NOTE: All VMOV encoding is special-cased! */
18173 NCE(vmov, 0, 1, (VMOV), neon_mov),
18174 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18176 #undef THUMB_VARIANT
18177 #define THUMB_VARIANT & fpu_neon_ext_v1
18179 #define ARM_VARIANT & fpu_neon_ext_v1
18181 /* Data processing with three registers of the same length. */
18182 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18183 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18184 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18185 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18186 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18187 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18188 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18189 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18190 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18191 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18192 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18193 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18194 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18195 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18196 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18197 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18198 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18199 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18200 /* If not immediate, fall back to neon_dyadic_i64_su.
18201 shl_imm should accept I8 I16 I32 I64,
18202 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18203 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18204 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18205 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18206 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18207 /* Logic ops, types optional & ignored. */
18208 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18209 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18210 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18211 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18212 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18213 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18214 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18215 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18216 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18217 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18218 /* Bitfield ops, untyped. */
18219 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18220 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18221 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18222 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18223 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18224 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18225 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18226 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18227 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18228 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18229 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18230 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18231 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18232 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18233 back to neon_dyadic_if_su. */
18234 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18235 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18236 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18237 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18238 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18239 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18240 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18241 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18242 /* Comparison. Type I8 I16 I32 F32. */
18243 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18244 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18245 /* As above, D registers only. */
18246 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18247 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18248 /* Int and float variants, signedness unimportant. */
18249 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18250 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18251 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18252 /* Add/sub take types I8 I16 I32 I64 F32. */
18253 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18254 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18255 /* vtst takes sizes 8, 16, 32. */
18256 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18257 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18258 /* VMUL takes I8 I16 I32 F32 P8. */
18259 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18260 /* VQD{R}MULH takes S16 S32. */
18261 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18262 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18263 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18264 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18265 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18266 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18267 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18268 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18269 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18270 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18271 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18272 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18273 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18274 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18275 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18276 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18278 /* Two address, int/float. Types S8 S16 S32 F32. */
18279 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18280 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18282 /* Data processing with two registers and a shift amount. */
18283 /* Right shifts, and variants with rounding.
18284 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18285 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18286 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18287 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18288 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18289 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18290 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18291 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18292 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18293 /* Shift and insert. Sizes accepted 8 16 32 64. */
18294 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18295 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18296 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18297 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18298 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18299 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18300 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18301 /* Right shift immediate, saturating & narrowing, with rounding variants.
18302 Types accepted S16 S32 S64 U16 U32 U64. */
18303 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18304 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18305 /* As above, unsigned. Types accepted S16 S32 S64. */
18306 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18307 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18308 /* Right shift narrowing. Types accepted I16 I32 I64. */
18309 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18310 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18311 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18312 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18313 /* CVT with optional immediate for fixed-point variant. */
18314 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18316 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18317 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18319 /* Data processing, three registers of different lengths. */
18320 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18321 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18322 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18323 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18324 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18325 /* If not scalar, fall back to neon_dyadic_long.
18326 Vector types as above, scalar types S16 S32 U16 U32. */
18327 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18328 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18329 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18330 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18331 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18332 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18333 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18334 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18335 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18336 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18337 /* Saturating doubling multiplies. Types S16 S32. */
18338 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18339 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18340 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18341 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18342 S16 S32 U16 U32. */
18343 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18345 /* Extract. Size 8. */
18346 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18347 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18349 /* Two registers, miscellaneous. */
18350 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18351 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18352 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18353 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18354 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18355 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18356 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18357 /* Vector replicate. Sizes 8 16 32. */
18358 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18359 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18360 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18361 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18362 /* VMOVN. Types I16 I32 I64. */
18363 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18364 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18365 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18366 /* VQMOVUN. Types S16 S32 S64. */
18367 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18368 /* VZIP / VUZP. Sizes 8 16 32. */
18369 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18370 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18371 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18372 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18373 /* VQABS / VQNEG. Types S8 S16 S32. */
18374 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18375 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18376 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18377 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18378 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18379 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18380 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18381 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18382 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18383 /* Reciprocal estimates. Types U32 F32. */
18384 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18385 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18386 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18387 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18388 /* VCLS. Types S8 S16 S32. */
18389 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18390 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18391 /* VCLZ. Types I8 I16 I32. */
18392 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18393 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18394 /* VCNT. Size 8. */
18395 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18396 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18397 /* Two address, untyped. */
18398 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18399 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18400 /* VTRN. Sizes 8 16 32. */
18401 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18402 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18404 /* Table lookup. Size 8. */
18405 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18406 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18408 #undef THUMB_VARIANT
18409 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18411 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18413 /* Neon element/structure load/store. */
18414 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18415 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18416 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18417 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18418 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18419 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18420 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18421 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18423 #undef THUMB_VARIANT
18424 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18426 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18427 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18428 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18429 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18430 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18431 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18432 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18433 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18434 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18435 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18437 #undef THUMB_VARIANT
18438 #define THUMB_VARIANT & fpu_vfp_ext_v3
18440 #define ARM_VARIANT & fpu_vfp_ext_v3
18442 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18443 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18444 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18445 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18446 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18447 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18448 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18449 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18450 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18453 #define ARM_VARIANT &fpu_vfp_ext_fma
18454 #undef THUMB_VARIANT
18455 #define THUMB_VARIANT &fpu_vfp_ext_fma
18456 /* Mnemonics shared by Neon and VFP. These are included in the
18457 VFP FMA variant; NEON and VFP FMA always includes the NEON
18458 FMA instructions. */
18459 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18460 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18461 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18462 the v form should always be used. */
18463 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18464 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18465 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18466 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18467 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18468 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18470 #undef THUMB_VARIANT
18472 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18474 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18475 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18476 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18477 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18478 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18479 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18480 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18481 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18484 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18486 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18487 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18488 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18489 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18490 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18491 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18492 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18493 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18494 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18495 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18496 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18497 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18498 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18499 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18500 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18501 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18502 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18503 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18504 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18505 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18506 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18507 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18508 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18509 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18510 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18511 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18512 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18513 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18514 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18515 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18516 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18517 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18518 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18519 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18520 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18521 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18522 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18523 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18524 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18525 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18526 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18527 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18528 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18529 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18530 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18531 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18532 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18533 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18534 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18535 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18536 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18537 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18538 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18539 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18540 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18541 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18542 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18543 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18544 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18545 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18546 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18547 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18548 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18549 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18550 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18551 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18552 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18553 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18554 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18555 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18556 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18557 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18558 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18559 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18560 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18561 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18562 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18563 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18564 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18565 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18566 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18567 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18568 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18569 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18570 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18571 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18572 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18573 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18574 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18575 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18576 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18577 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18578 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18579 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18580 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18581 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18582 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18583 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18584 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18585 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18586 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18587 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18588 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18589 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18590 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18591 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18592 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18593 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18594 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18595 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18596 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18597 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18598 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18599 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18600 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18601 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18602 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18603 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18604 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18605 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18606 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18607 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18608 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18609 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18610 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18611 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18612 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18613 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18614 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18615 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18616 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18617 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18618 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18619 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18620 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18621 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18622 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18623 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18624 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18625 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18626 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18627 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18628 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18629 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18630 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18631 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18632 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18633 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18634 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18635 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18636 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18637 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18638 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18639 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18640 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18641 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18642 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18643 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18644 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18645 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18646 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18647 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18650 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18652 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18653 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18654 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18655 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18656 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18657 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18658 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18659 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18662 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18673 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18690 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18691 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18692 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18693 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18696 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18703 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18704 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18706 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18707 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18708 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18711 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18713 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18714 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18715 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18716 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18717 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18718 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18719 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18720 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18721 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18722 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18723 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18724 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18725 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18726 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18727 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18728 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18729 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18730 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18731 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18732 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18733 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18734 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18735 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18736 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18737 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18738 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18739 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18740 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18741 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18742 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18743 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18744 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18745 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18746 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18747 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18748 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18749 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18750 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18751 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18752 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18753 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18754 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18755 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18756 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18757 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18758 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18759 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18760 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18761 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18762 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18763 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18764 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18765 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18766 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18767 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18768 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18769 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18770 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18771 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18772 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18773 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18774 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18775 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18776 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18777 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18778 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18779 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18780 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18781 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18782 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18783 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18784 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18785 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18786 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18787 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18788 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18791 #undef THUMB_VARIANT
18818 /* MD interface: bits in the object file. */
18820 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18821 for use in the a.out file, and stores them in the array pointed to by buf.
18822 This knows about the endian-ness of the target machine and does
18823 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18824 2 (short) and 4 (long) Floating numbers are put out as a series of
18825 LITTLENUMS (shorts, here at least). */
18828 md_number_to_chars (char * buf, valueT val, int n)
18830 if (target_big_endian)
18831 number_to_chars_bigendian (buf, val, n);
18833 number_to_chars_littleendian (buf, val, n);
18837 md_chars_to_number (char * buf, int n)
18840 unsigned char * where = (unsigned char *) buf;
18842 if (target_big_endian)
18847 result |= (*where++ & 255);
18855 result |= (where[n] & 255);
18862 /* MD interface: Sections. */
18864 /* Estimate the size of a frag before relaxing. Assume everything fits in
18868 md_estimate_size_before_relax (fragS * fragp,
18869 segT segtype ATTRIBUTE_UNUSED)
18875 /* Convert a machine dependent frag. */
18878 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18880 unsigned long insn;
18881 unsigned long old_op;
18889 buf = fragp->fr_literal + fragp->fr_fix;
18891 old_op = bfd_get_16(abfd, buf);
18892 if (fragp->fr_symbol)
18894 exp.X_op = O_symbol;
18895 exp.X_add_symbol = fragp->fr_symbol;
18899 exp.X_op = O_constant;
18901 exp.X_add_number = fragp->fr_offset;
18902 opcode = fragp->fr_subtype;
18905 case T_MNEM_ldr_pc:
18906 case T_MNEM_ldr_pc2:
18907 case T_MNEM_ldr_sp:
18908 case T_MNEM_str_sp:
18915 if (fragp->fr_var == 4)
18917 insn = THUMB_OP32 (opcode);
18918 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
18920 insn |= (old_op & 0x700) << 4;
18924 insn |= (old_op & 7) << 12;
18925 insn |= (old_op & 0x38) << 13;
18927 insn |= 0x00000c00;
18928 put_thumb32_insn (buf, insn);
18929 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
18933 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
18935 pc_rel = (opcode == T_MNEM_ldr_pc2);
18938 if (fragp->fr_var == 4)
18940 insn = THUMB_OP32 (opcode);
18941 insn |= (old_op & 0xf0) << 4;
18942 put_thumb32_insn (buf, insn);
18943 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
18947 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
18948 exp.X_add_number -= 4;
18956 if (fragp->fr_var == 4)
18958 int r0off = (opcode == T_MNEM_mov
18959 || opcode == T_MNEM_movs) ? 0 : 8;
18960 insn = THUMB_OP32 (opcode);
18961 insn = (insn & 0xe1ffffff) | 0x10000000;
18962 insn |= (old_op & 0x700) << r0off;
18963 put_thumb32_insn (buf, insn);
18964 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
18968 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
18973 if (fragp->fr_var == 4)
18975 insn = THUMB_OP32(opcode);
18976 put_thumb32_insn (buf, insn);
18977 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
18980 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
18984 if (fragp->fr_var == 4)
18986 insn = THUMB_OP32(opcode);
18987 insn |= (old_op & 0xf00) << 14;
18988 put_thumb32_insn (buf, insn);
18989 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
18992 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
18995 case T_MNEM_add_sp:
18996 case T_MNEM_add_pc:
18997 case T_MNEM_inc_sp:
18998 case T_MNEM_dec_sp:
18999 if (fragp->fr_var == 4)
19001 /* ??? Choose between add and addw. */
19002 insn = THUMB_OP32 (opcode);
19003 insn |= (old_op & 0xf0) << 4;
19004 put_thumb32_insn (buf, insn);
19005 if (opcode == T_MNEM_add_pc)
19006 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19008 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19011 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19019 if (fragp->fr_var == 4)
19021 insn = THUMB_OP32 (opcode);
19022 insn |= (old_op & 0xf0) << 4;
19023 insn |= (old_op & 0xf) << 16;
19024 put_thumb32_insn (buf, insn);
19025 if (insn & (1 << 20))
19026 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19028 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19031 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19037 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19038 (enum bfd_reloc_code_real) reloc_type);
19039 fixp->fx_file = fragp->fr_file;
19040 fixp->fx_line = fragp->fr_line;
19041 fragp->fr_fix += fragp->fr_var;
19044 /* Return the size of a relaxable immediate operand instruction.
19045 SHIFT and SIZE specify the form of the allowable immediate. */
19047 relax_immediate (fragS *fragp, int size, int shift)
19053 /* ??? Should be able to do better than this. */
19054 if (fragp->fr_symbol)
19057 low = (1 << shift) - 1;
19058 mask = (1 << (shift + size)) - (1 << shift);
19059 offset = fragp->fr_offset;
19060 /* Force misaligned offsets to 32-bit variant. */
19063 if (offset & ~mask)
19068 /* Get the address of a symbol during relaxation. */
19070 relaxed_symbol_addr (fragS *fragp, long stretch)
19076 sym = fragp->fr_symbol;
19077 sym_frag = symbol_get_frag (sym);
19078 know (S_GET_SEGMENT (sym) != absolute_section
19079 || sym_frag == &zero_address_frag);
19080 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19082 /* If frag has yet to be reached on this pass, assume it will
19083 move by STRETCH just as we did. If this is not so, it will
19084 be because some frag between grows, and that will force
19088 && sym_frag->relax_marker != fragp->relax_marker)
19092 /* Adjust stretch for any alignment frag. Note that if have
19093 been expanding the earlier code, the symbol may be
19094 defined in what appears to be an earlier frag. FIXME:
19095 This doesn't handle the fr_subtype field, which specifies
19096 a maximum number of bytes to skip when doing an
19098 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19100 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19103 stretch = - ((- stretch)
19104 & ~ ((1 << (int) f->fr_offset) - 1));
19106 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19118 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19121 relax_adr (fragS *fragp, asection *sec, long stretch)
19126 /* Assume worst case for symbols not known to be in the same section. */
19127 if (fragp->fr_symbol == NULL
19128 || !S_IS_DEFINED (fragp->fr_symbol)
19129 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19130 || S_IS_WEAK (fragp->fr_symbol))
19133 val = relaxed_symbol_addr (fragp, stretch);
19134 addr = fragp->fr_address + fragp->fr_fix;
19135 addr = (addr + 4) & ~3;
19136 /* Force misaligned targets to 32-bit variant. */
19140 if (val < 0 || val > 1020)
19145 /* Return the size of a relaxable add/sub immediate instruction. */
19147 relax_addsub (fragS *fragp, asection *sec)
19152 buf = fragp->fr_literal + fragp->fr_fix;
19153 op = bfd_get_16(sec->owner, buf);
19154 if ((op & 0xf) == ((op >> 4) & 0xf))
19155 return relax_immediate (fragp, 8, 0);
19157 return relax_immediate (fragp, 3, 0);
19161 /* Return the size of a relaxable branch instruction. BITS is the
19162 size of the offset field in the narrow instruction. */
19165 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19171 /* Assume worst case for symbols not known to be in the same section. */
19172 if (!S_IS_DEFINED (fragp->fr_symbol)
19173 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19174 || S_IS_WEAK (fragp->fr_symbol))
19178 if (S_IS_DEFINED (fragp->fr_symbol)
19179 && ARM_IS_FUNC (fragp->fr_symbol))
19182 /* PR 12532. Global symbols with default visibility might
19183 be preempted, so do not relax relocations to them. */
19184 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19185 && (! S_IS_LOCAL (fragp->fr_symbol)))
19189 val = relaxed_symbol_addr (fragp, stretch);
19190 addr = fragp->fr_address + fragp->fr_fix + 4;
19193 /* Offset is a signed value *2 */
19195 if (val >= limit || val < -limit)
19201 /* Relax a machine dependent frag. This returns the amount by which
19202 the current size of the frag should change. */
19205 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19210 oldsize = fragp->fr_var;
19211 switch (fragp->fr_subtype)
19213 case T_MNEM_ldr_pc2:
19214 newsize = relax_adr (fragp, sec, stretch);
19216 case T_MNEM_ldr_pc:
19217 case T_MNEM_ldr_sp:
19218 case T_MNEM_str_sp:
19219 newsize = relax_immediate (fragp, 8, 2);
19223 newsize = relax_immediate (fragp, 5, 2);
19227 newsize = relax_immediate (fragp, 5, 1);
19231 newsize = relax_immediate (fragp, 5, 0);
19234 newsize = relax_adr (fragp, sec, stretch);
19240 newsize = relax_immediate (fragp, 8, 0);
19243 newsize = relax_branch (fragp, sec, 11, stretch);
19246 newsize = relax_branch (fragp, sec, 8, stretch);
19248 case T_MNEM_add_sp:
19249 case T_MNEM_add_pc:
19250 newsize = relax_immediate (fragp, 8, 2);
19252 case T_MNEM_inc_sp:
19253 case T_MNEM_dec_sp:
19254 newsize = relax_immediate (fragp, 7, 2);
19260 newsize = relax_addsub (fragp, sec);
19266 fragp->fr_var = newsize;
19267 /* Freeze wide instructions that are at or before the same location as
19268 in the previous pass. This avoids infinite loops.
19269 Don't freeze them unconditionally because targets may be artificially
19270 misaligned by the expansion of preceding frags. */
19271 if (stretch <= 0 && newsize > 2)
19273 md_convert_frag (sec->owner, sec, fragp);
19277 return newsize - oldsize;
19280 /* Round up a section size to the appropriate boundary. */
19283 md_section_align (segT segment ATTRIBUTE_UNUSED,
19286 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19287 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19289 /* For a.out, force the section size to be aligned. If we don't do
19290 this, BFD will align it for us, but it will not write out the
19291 final bytes of the section. This may be a bug in BFD, but it is
19292 easier to fix it here since that is how the other a.out targets
19296 align = bfd_get_section_alignment (stdoutput, segment);
19297 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19304 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19305 of an rs_align_code fragment. */
19308 arm_handle_align (fragS * fragP)
19310 static char const arm_noop[2][2][4] =
19313 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19314 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19317 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19318 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19321 static char const thumb_noop[2][2][2] =
19324 {0xc0, 0x46}, /* LE */
19325 {0x46, 0xc0}, /* BE */
19328 {0x00, 0xbf}, /* LE */
19329 {0xbf, 0x00} /* BE */
19332 static char const wide_thumb_noop[2][4] =
19333 { /* Wide Thumb-2 */
19334 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19335 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19338 unsigned bytes, fix, noop_size;
19341 const char *narrow_noop = NULL;
19346 if (fragP->fr_type != rs_align_code)
19349 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19350 p = fragP->fr_literal + fragP->fr_fix;
19353 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19354 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19356 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19358 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19360 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19362 narrow_noop = thumb_noop[1][target_big_endian];
19363 noop = wide_thumb_noop[target_big_endian];
19366 noop = thumb_noop[0][target_big_endian];
19374 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19375 [target_big_endian];
19382 fragP->fr_var = noop_size;
19384 if (bytes & (noop_size - 1))
19386 fix = bytes & (noop_size - 1);
19388 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19390 memset (p, 0, fix);
19397 if (bytes & noop_size)
19399 /* Insert a narrow noop. */
19400 memcpy (p, narrow_noop, noop_size);
19402 bytes -= noop_size;
19406 /* Use wide noops for the remainder */
19410 while (bytes >= noop_size)
19412 memcpy (p, noop, noop_size);
19414 bytes -= noop_size;
19418 fragP->fr_fix += fix;
19421 /* Called from md_do_align. Used to create an alignment
19422 frag in a code section. */
19425 arm_frag_align_code (int n, int max)
19429 /* We assume that there will never be a requirement
19430 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19431 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19436 _("alignments greater than %d bytes not supported in .text sections."),
19437 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19438 as_fatal ("%s", err_msg);
19441 p = frag_var (rs_align_code,
19442 MAX_MEM_FOR_RS_ALIGN_CODE,
19444 (relax_substateT) max,
19451 /* Perform target specific initialisation of a frag.
19452 Note - despite the name this initialisation is not done when the frag
19453 is created, but only when its type is assigned. A frag can be created
19454 and used a long time before its type is set, so beware of assuming that
19455 this initialisationis performed first. */
19459 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19461 /* Record whether this frag is in an ARM or a THUMB area. */
19462 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19465 #else /* OBJ_ELF is defined. */
19467 arm_init_frag (fragS * fragP, int max_chars)
19469 /* If the current ARM vs THUMB mode has not already
19470 been recorded into this frag then do so now. */
19471 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19473 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19475 /* Record a mapping symbol for alignment frags. We will delete this
19476 later if the alignment ends up empty. */
19477 switch (fragP->fr_type)
19480 case rs_align_test:
19482 mapping_state_2 (MAP_DATA, max_chars);
19484 case rs_align_code:
19485 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19493 /* When we change sections we need to issue a new mapping symbol. */
19496 arm_elf_change_section (void)
19498 /* Link an unlinked unwind index table section to the .text section. */
19499 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19500 && elf_linked_to_section (now_seg) == NULL)
19501 elf_linked_to_section (now_seg) = text_section;
19505 arm_elf_section_type (const char * str, size_t len)
19507 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19508 return SHT_ARM_EXIDX;
19513 /* Code to deal with unwinding tables. */
19515 static void add_unwind_adjustsp (offsetT);
19517 /* Generate any deferred unwind frame offset. */
19520 flush_pending_unwind (void)
19524 offset = unwind.pending_offset;
19525 unwind.pending_offset = 0;
19527 add_unwind_adjustsp (offset);
19530 /* Add an opcode to this list for this function. Two-byte opcodes should
19531 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19535 add_unwind_opcode (valueT op, int length)
19537 /* Add any deferred stack adjustment. */
19538 if (unwind.pending_offset)
19539 flush_pending_unwind ();
19541 unwind.sp_restored = 0;
19543 if (unwind.opcode_count + length > unwind.opcode_alloc)
19545 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19546 if (unwind.opcodes)
19547 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19548 unwind.opcode_alloc);
19550 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19555 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19557 unwind.opcode_count++;
19561 /* Add unwind opcodes to adjust the stack pointer. */
19564 add_unwind_adjustsp (offsetT offset)
19568 if (offset > 0x200)
19570 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19575 /* Long form: 0xb2, uleb128. */
19576 /* This might not fit in a word so add the individual bytes,
19577 remembering the list is built in reverse order. */
19578 o = (valueT) ((offset - 0x204) >> 2);
19580 add_unwind_opcode (0, 1);
19582 /* Calculate the uleb128 encoding of the offset. */
19586 bytes[n] = o & 0x7f;
19592 /* Add the insn. */
19594 add_unwind_opcode (bytes[n - 1], 1);
19595 add_unwind_opcode (0xb2, 1);
19597 else if (offset > 0x100)
19599 /* Two short opcodes. */
19600 add_unwind_opcode (0x3f, 1);
19601 op = (offset - 0x104) >> 2;
19602 add_unwind_opcode (op, 1);
19604 else if (offset > 0)
19606 /* Short opcode. */
19607 op = (offset - 4) >> 2;
19608 add_unwind_opcode (op, 1);
19610 else if (offset < 0)
19613 while (offset > 0x100)
19615 add_unwind_opcode (0x7f, 1);
19618 op = ((offset - 4) >> 2) | 0x40;
19619 add_unwind_opcode (op, 1);
19623 /* Finish the list of unwind opcodes for this function. */
19625 finish_unwind_opcodes (void)
19629 if (unwind.fp_used)
19631 /* Adjust sp as necessary. */
19632 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19633 flush_pending_unwind ();
19635 /* After restoring sp from the frame pointer. */
19636 op = 0x90 | unwind.fp_reg;
19637 add_unwind_opcode (op, 1);
19640 flush_pending_unwind ();
19644 /* Start an exception table entry. If idx is nonzero this is an index table
19648 start_unwind_section (const segT text_seg, int idx)
19650 const char * text_name;
19651 const char * prefix;
19652 const char * prefix_once;
19653 const char * group_name;
19657 size_t sec_name_len;
19664 prefix = ELF_STRING_ARM_unwind;
19665 prefix_once = ELF_STRING_ARM_unwind_once;
19666 type = SHT_ARM_EXIDX;
19670 prefix = ELF_STRING_ARM_unwind_info;
19671 prefix_once = ELF_STRING_ARM_unwind_info_once;
19672 type = SHT_PROGBITS;
19675 text_name = segment_name (text_seg);
19676 if (streq (text_name, ".text"))
19679 if (strncmp (text_name, ".gnu.linkonce.t.",
19680 strlen (".gnu.linkonce.t.")) == 0)
19682 prefix = prefix_once;
19683 text_name += strlen (".gnu.linkonce.t.");
19686 prefix_len = strlen (prefix);
19687 text_len = strlen (text_name);
19688 sec_name_len = prefix_len + text_len;
19689 sec_name = (char *) xmalloc (sec_name_len + 1);
19690 memcpy (sec_name, prefix, prefix_len);
19691 memcpy (sec_name + prefix_len, text_name, text_len);
19692 sec_name[prefix_len + text_len] = '\0';
19698 /* Handle COMDAT group. */
19699 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19701 group_name = elf_group_name (text_seg);
19702 if (group_name == NULL)
19704 as_bad (_("Group section `%s' has no group signature"),
19705 segment_name (text_seg));
19706 ignore_rest_of_line ();
19709 flags |= SHF_GROUP;
19713 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19715 /* Set the section link for index tables. */
19717 elf_linked_to_section (now_seg) = text_seg;
19721 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19722 personality routine data. Returns zero, or the index table value for
19723 and inline entry. */
19726 create_unwind_entry (int have_data)
19731 /* The current word of data. */
19733 /* The number of bytes left in this word. */
19736 finish_unwind_opcodes ();
19738 /* Remember the current text section. */
19739 unwind.saved_seg = now_seg;
19740 unwind.saved_subseg = now_subseg;
19742 start_unwind_section (now_seg, 0);
19744 if (unwind.personality_routine == NULL)
19746 if (unwind.personality_index == -2)
19749 as_bad (_("handlerdata in cantunwind frame"));
19750 return 1; /* EXIDX_CANTUNWIND. */
19753 /* Use a default personality routine if none is specified. */
19754 if (unwind.personality_index == -1)
19756 if (unwind.opcode_count > 3)
19757 unwind.personality_index = 1;
19759 unwind.personality_index = 0;
19762 /* Space for the personality routine entry. */
19763 if (unwind.personality_index == 0)
19765 if (unwind.opcode_count > 3)
19766 as_bad (_("too many unwind opcodes for personality routine 0"));
19770 /* All the data is inline in the index table. */
19773 while (unwind.opcode_count > 0)
19775 unwind.opcode_count--;
19776 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19780 /* Pad with "finish" opcodes. */
19782 data = (data << 8) | 0xb0;
19789 /* We get two opcodes "free" in the first word. */
19790 size = unwind.opcode_count - 2;
19793 /* An extra byte is required for the opcode count. */
19794 size = unwind.opcode_count + 1;
19796 size = (size + 3) >> 2;
19798 as_bad (_("too many unwind opcodes"));
19800 frag_align (2, 0, 0);
19801 record_alignment (now_seg, 2);
19802 unwind.table_entry = expr_build_dot ();
19804 /* Allocate the table entry. */
19805 ptr = frag_more ((size << 2) + 4);
19806 where = frag_now_fix () - ((size << 2) + 4);
19808 switch (unwind.personality_index)
19811 /* ??? Should this be a PLT generating relocation? */
19812 /* Custom personality routine. */
19813 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19814 BFD_RELOC_ARM_PREL31);
19819 /* Set the first byte to the number of additional words. */
19824 /* ABI defined personality routines. */
19826 /* Three opcodes bytes are packed into the first word. */
19833 /* The size and first two opcode bytes go in the first word. */
19834 data = ((0x80 + unwind.personality_index) << 8) | size;
19839 /* Should never happen. */
19843 /* Pack the opcodes into words (MSB first), reversing the list at the same
19845 while (unwind.opcode_count > 0)
19849 md_number_to_chars (ptr, data, 4);
19854 unwind.opcode_count--;
19856 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19859 /* Finish off the last word. */
19862 /* Pad with "finish" opcodes. */
19864 data = (data << 8) | 0xb0;
19866 md_number_to_chars (ptr, data, 4);
19871 /* Add an empty descriptor if there is no user-specified data. */
19872 ptr = frag_more (4);
19873 md_number_to_chars (ptr, 0, 4);
19880 /* Initialize the DWARF-2 unwind information for this procedure. */
19883 tc_arm_frame_initial_instructions (void)
19885 cfi_add_CFA_def_cfa (REG_SP, 0);
19887 #endif /* OBJ_ELF */
19889 /* Convert REGNAME to a DWARF-2 register number. */
19892 tc_arm_regname_to_dw2regnum (char *regname)
19894 int reg = arm_reg_parse (®name, REG_TYPE_RN);
19904 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
19908 exp.X_op = O_secrel;
19909 exp.X_add_symbol = symbol;
19910 exp.X_add_number = 0;
19911 emit_expr (&exp, size);
19915 /* MD interface: Symbol and relocation handling. */
19917 /* Return the address within the segment that a PC-relative fixup is
19918 relative to. For ARM, PC-relative fixups applied to instructions
19919 are generally relative to the location of the fixup plus 8 bytes.
19920 Thumb branches are offset by 4, and Thumb loads relative to PC
19921 require special handling. */
19924 md_pcrel_from_section (fixS * fixP, segT seg)
19926 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
19928 /* If this is pc-relative and we are going to emit a relocation
19929 then we just want to put out any pipeline compensation that the linker
19930 will need. Otherwise we want to use the calculated base.
19931 For WinCE we skip the bias for externals as well, since this
19932 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19934 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
19935 || (arm_force_relocation (fixP)
19937 && !S_IS_EXTERNAL (fixP->fx_addsy)
19943 switch (fixP->fx_r_type)
19945 /* PC relative addressing on the Thumb is slightly odd as the
19946 bottom two bits of the PC are forced to zero for the
19947 calculation. This happens *after* application of the
19948 pipeline offset. However, Thumb adrl already adjusts for
19949 this, so we need not do it again. */
19950 case BFD_RELOC_ARM_THUMB_ADD:
19953 case BFD_RELOC_ARM_THUMB_OFFSET:
19954 case BFD_RELOC_ARM_T32_OFFSET_IMM:
19955 case BFD_RELOC_ARM_T32_ADD_PC12:
19956 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
19957 return (base + 4) & ~3;
19959 /* Thumb branches are simply offset by +4. */
19960 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19961 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19962 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19963 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19964 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19967 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19969 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19970 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19971 && ARM_IS_FUNC (fixP->fx_addsy)
19972 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19973 base = fixP->fx_where + fixP->fx_frag->fr_address;
19976 /* BLX is like branches above, but forces the low two bits of PC to
19978 case BFD_RELOC_THUMB_PCREL_BLX:
19980 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19981 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19982 && THUMB_IS_FUNC (fixP->fx_addsy)
19983 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19984 base = fixP->fx_where + fixP->fx_frag->fr_address;
19985 return (base + 4) & ~3;
19987 /* ARM mode branches are offset by +8. However, the Windows CE
19988 loader expects the relocation not to take this into account. */
19989 case BFD_RELOC_ARM_PCREL_BLX:
19991 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19992 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19993 && ARM_IS_FUNC (fixP->fx_addsy)
19994 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19995 base = fixP->fx_where + fixP->fx_frag->fr_address;
19998 case BFD_RELOC_ARM_PCREL_CALL:
20000 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20001 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20002 && THUMB_IS_FUNC (fixP->fx_addsy)
20003 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20004 base = fixP->fx_where + fixP->fx_frag->fr_address;
20007 case BFD_RELOC_ARM_PCREL_BRANCH:
20008 case BFD_RELOC_ARM_PCREL_JUMP:
20009 case BFD_RELOC_ARM_PLT32:
20011 /* When handling fixups immediately, because we have already
20012 discovered the value of a symbol, or the address of the frag involved
20013 we must account for the offset by +8, as the OS loader will never see the reloc.
20014 see fixup_segment() in write.c
20015 The S_IS_EXTERNAL test handles the case of global symbols.
20016 Those need the calculated base, not just the pipe compensation the linker will need. */
20018 && fixP->fx_addsy != NULL
20019 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20020 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20028 /* ARM mode loads relative to PC are also offset by +8. Unlike
20029 branches, the Windows CE loader *does* expect the relocation
20030 to take this into account. */
20031 case BFD_RELOC_ARM_OFFSET_IMM:
20032 case BFD_RELOC_ARM_OFFSET_IMM8:
20033 case BFD_RELOC_ARM_HWLITERAL:
20034 case BFD_RELOC_ARM_LITERAL:
20035 case BFD_RELOC_ARM_CP_OFF_IMM:
20039 /* Other PC-relative relocations are un-offset. */
20045 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20046 Otherwise we have no need to default values of symbols. */
20049 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20052 if (name[0] == '_' && name[1] == 'G'
20053 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20057 if (symbol_find (name))
20058 as_bad (_("GOT already in the symbol table"));
20060 GOT_symbol = symbol_new (name, undefined_section,
20061 (valueT) 0, & zero_address_frag);
20071 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20072 computed as two separate immediate values, added together. We
20073 already know that this value cannot be computed by just one ARM
20076 static unsigned int
20077 validate_immediate_twopart (unsigned int val,
20078 unsigned int * highpart)
20083 for (i = 0; i < 32; i += 2)
20084 if (((a = rotate_left (val, i)) & 0xff) != 0)
20090 * highpart = (a >> 8) | ((i + 24) << 7);
20092 else if (a & 0xff0000)
20094 if (a & 0xff000000)
20096 * highpart = (a >> 16) | ((i + 16) << 7);
20100 gas_assert (a & 0xff000000);
20101 * highpart = (a >> 24) | ((i + 8) << 7);
20104 return (a & 0xff) | (i << 7);
20111 validate_offset_imm (unsigned int val, int hwse)
20113 if ((hwse && val > 255) || val > 4095)
20118 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20119 negative immediate constant by altering the instruction. A bit of
20124 by inverting the second operand, and
20127 by negating the second operand. */
20130 negate_data_op (unsigned long * instruction,
20131 unsigned long value)
20134 unsigned long negated, inverted;
20136 negated = encode_arm_immediate (-value);
20137 inverted = encode_arm_immediate (~value);
20139 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20142 /* First negates. */
20143 case OPCODE_SUB: /* ADD <-> SUB */
20144 new_inst = OPCODE_ADD;
20149 new_inst = OPCODE_SUB;
20153 case OPCODE_CMP: /* CMP <-> CMN */
20154 new_inst = OPCODE_CMN;
20159 new_inst = OPCODE_CMP;
20163 /* Now Inverted ops. */
20164 case OPCODE_MOV: /* MOV <-> MVN */
20165 new_inst = OPCODE_MVN;
20170 new_inst = OPCODE_MOV;
20174 case OPCODE_AND: /* AND <-> BIC */
20175 new_inst = OPCODE_BIC;
20180 new_inst = OPCODE_AND;
20184 case OPCODE_ADC: /* ADC <-> SBC */
20185 new_inst = OPCODE_SBC;
20190 new_inst = OPCODE_ADC;
20194 /* We cannot do anything. */
20199 if (value == (unsigned) FAIL)
20202 *instruction &= OPCODE_MASK;
20203 *instruction |= new_inst << DATA_OP_SHIFT;
20207 /* Like negate_data_op, but for Thumb-2. */
20209 static unsigned int
20210 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20214 unsigned int negated, inverted;
20216 negated = encode_thumb32_immediate (-value);
20217 inverted = encode_thumb32_immediate (~value);
20219 rd = (*instruction >> 8) & 0xf;
20220 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20223 /* ADD <-> SUB. Includes CMP <-> CMN. */
20224 case T2_OPCODE_SUB:
20225 new_inst = T2_OPCODE_ADD;
20229 case T2_OPCODE_ADD:
20230 new_inst = T2_OPCODE_SUB;
20234 /* ORR <-> ORN. Includes MOV <-> MVN. */
20235 case T2_OPCODE_ORR:
20236 new_inst = T2_OPCODE_ORN;
20240 case T2_OPCODE_ORN:
20241 new_inst = T2_OPCODE_ORR;
20245 /* AND <-> BIC. TST has no inverted equivalent. */
20246 case T2_OPCODE_AND:
20247 new_inst = T2_OPCODE_BIC;
20254 case T2_OPCODE_BIC:
20255 new_inst = T2_OPCODE_AND;
20260 case T2_OPCODE_ADC:
20261 new_inst = T2_OPCODE_SBC;
20265 case T2_OPCODE_SBC:
20266 new_inst = T2_OPCODE_ADC;
20270 /* We cannot do anything. */
20275 if (value == (unsigned int)FAIL)
20278 *instruction &= T2_OPCODE_MASK;
20279 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20283 /* Read a 32-bit thumb instruction from buf. */
20284 static unsigned long
20285 get_thumb32_insn (char * buf)
20287 unsigned long insn;
20288 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20289 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20295 /* We usually want to set the low bit on the address of thumb function
20296 symbols. In particular .word foo - . should have the low bit set.
20297 Generic code tries to fold the difference of two symbols to
20298 a constant. Prevent this and force a relocation when the first symbols
20299 is a thumb function. */
20302 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20304 if (op == O_subtract
20305 && l->X_op == O_symbol
20306 && r->X_op == O_symbol
20307 && THUMB_IS_FUNC (l->X_add_symbol))
20309 l->X_op = O_subtract;
20310 l->X_op_symbol = r->X_add_symbol;
20311 l->X_add_number -= r->X_add_number;
20315 /* Process as normal. */
20319 /* Encode Thumb2 unconditional branches and calls. The encoding
20320 for the 2 are identical for the immediate values. */
20323 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20325 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20328 addressT S, I1, I2, lo, hi;
20330 S = (value >> 24) & 0x01;
20331 I1 = (value >> 23) & 0x01;
20332 I2 = (value >> 22) & 0x01;
20333 hi = (value >> 12) & 0x3ff;
20334 lo = (value >> 1) & 0x7ff;
20335 newval = md_chars_to_number (buf, THUMB_SIZE);
20336 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20337 newval |= (S << 10) | hi;
20338 newval2 &= ~T2I1I2MASK;
20339 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20340 md_number_to_chars (buf, newval, THUMB_SIZE);
20341 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20345 md_apply_fix (fixS * fixP,
20349 offsetT value = * valP;
20351 unsigned int newimm;
20352 unsigned long temp;
20354 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20356 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20358 /* Note whether this will delete the relocation. */
20360 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20363 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20364 consistency with the behaviour on 32-bit hosts. Remember value
20366 value &= 0xffffffff;
20367 value ^= 0x80000000;
20368 value -= 0x80000000;
20371 fixP->fx_addnumber = value;
20373 /* Same treatment for fixP->fx_offset. */
20374 fixP->fx_offset &= 0xffffffff;
20375 fixP->fx_offset ^= 0x80000000;
20376 fixP->fx_offset -= 0x80000000;
20378 switch (fixP->fx_r_type)
20380 case BFD_RELOC_NONE:
20381 /* This will need to go in the object file. */
20385 case BFD_RELOC_ARM_IMMEDIATE:
20386 /* We claim that this fixup has been processed here,
20387 even if in fact we generate an error because we do
20388 not have a reloc for it, so tc_gen_reloc will reject it. */
20391 if (fixP->fx_addsy)
20393 const char *msg = 0;
20395 if (! S_IS_DEFINED (fixP->fx_addsy))
20396 msg = _("undefined symbol %s used as an immediate value");
20397 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20398 msg = _("symbol %s is in a different section");
20399 else if (S_IS_WEAK (fixP->fx_addsy))
20400 msg = _("symbol %s is weak and may be overridden later");
20404 as_bad_where (fixP->fx_file, fixP->fx_line,
20405 msg, S_GET_NAME (fixP->fx_addsy));
20410 newimm = encode_arm_immediate (value);
20411 temp = md_chars_to_number (buf, INSN_SIZE);
20413 /* If the instruction will fail, see if we can fix things up by
20414 changing the opcode. */
20415 if (newimm == (unsigned int) FAIL
20416 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20418 as_bad_where (fixP->fx_file, fixP->fx_line,
20419 _("invalid constant (%lx) after fixup"),
20420 (unsigned long) value);
20424 newimm |= (temp & 0xfffff000);
20425 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20428 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20430 unsigned int highpart = 0;
20431 unsigned int newinsn = 0xe1a00000; /* nop. */
20433 if (fixP->fx_addsy)
20435 const char *msg = 0;
20437 if (! S_IS_DEFINED (fixP->fx_addsy))
20438 msg = _("undefined symbol %s used as an immediate value");
20439 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20440 msg = _("symbol %s is in a different section");
20441 else if (S_IS_WEAK (fixP->fx_addsy))
20442 msg = _("symbol %s is weak and may be overridden later");
20446 as_bad_where (fixP->fx_file, fixP->fx_line,
20447 msg, S_GET_NAME (fixP->fx_addsy));
20452 newimm = encode_arm_immediate (value);
20453 temp = md_chars_to_number (buf, INSN_SIZE);
20455 /* If the instruction will fail, see if we can fix things up by
20456 changing the opcode. */
20457 if (newimm == (unsigned int) FAIL
20458 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20460 /* No ? OK - try using two ADD instructions to generate
20462 newimm = validate_immediate_twopart (value, & highpart);
20464 /* Yes - then make sure that the second instruction is
20466 if (newimm != (unsigned int) FAIL)
20468 /* Still No ? Try using a negated value. */
20469 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20470 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20471 /* Otherwise - give up. */
20474 as_bad_where (fixP->fx_file, fixP->fx_line,
20475 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20480 /* Replace the first operand in the 2nd instruction (which
20481 is the PC) with the destination register. We have
20482 already added in the PC in the first instruction and we
20483 do not want to do it again. */
20484 newinsn &= ~ 0xf0000;
20485 newinsn |= ((newinsn & 0x0f000) << 4);
20488 newimm |= (temp & 0xfffff000);
20489 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20491 highpart |= (newinsn & 0xfffff000);
20492 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20496 case BFD_RELOC_ARM_OFFSET_IMM:
20497 if (!fixP->fx_done && seg->use_rela_p)
20500 case BFD_RELOC_ARM_LITERAL:
20506 if (validate_offset_imm (value, 0) == FAIL)
20508 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20509 as_bad_where (fixP->fx_file, fixP->fx_line,
20510 _("invalid literal constant: pool needs to be closer"));
20512 as_bad_where (fixP->fx_file, fixP->fx_line,
20513 _("bad immediate value for offset (%ld)"),
20518 newval = md_chars_to_number (buf, INSN_SIZE);
20520 newval &= 0xfffff000;
20523 newval &= 0xff7ff000;
20524 newval |= value | (sign ? INDEX_UP : 0);
20526 md_number_to_chars (buf, newval, INSN_SIZE);
20529 case BFD_RELOC_ARM_OFFSET_IMM8:
20530 case BFD_RELOC_ARM_HWLITERAL:
20536 if (validate_offset_imm (value, 1) == FAIL)
20538 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20539 as_bad_where (fixP->fx_file, fixP->fx_line,
20540 _("invalid literal constant: pool needs to be closer"));
20542 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20547 newval = md_chars_to_number (buf, INSN_SIZE);
20549 newval &= 0xfffff0f0;
20552 newval &= 0xff7ff0f0;
20553 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20555 md_number_to_chars (buf, newval, INSN_SIZE);
20558 case BFD_RELOC_ARM_T32_OFFSET_U8:
20559 if (value < 0 || value > 1020 || value % 4 != 0)
20560 as_bad_where (fixP->fx_file, fixP->fx_line,
20561 _("bad immediate value for offset (%ld)"), (long) value);
20564 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20566 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20569 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20570 /* This is a complicated relocation used for all varieties of Thumb32
20571 load/store instruction with immediate offset:
20573 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20574 *4, optional writeback(W)
20575 (doubleword load/store)
20577 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20578 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20579 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20580 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20581 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20583 Uppercase letters indicate bits that are already encoded at
20584 this point. Lowercase letters are our problem. For the
20585 second block of instructions, the secondary opcode nybble
20586 (bits 8..11) is present, and bit 23 is zero, even if this is
20587 a PC-relative operation. */
20588 newval = md_chars_to_number (buf, THUMB_SIZE);
20590 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20592 if ((newval & 0xf0000000) == 0xe0000000)
20594 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20596 newval |= (1 << 23);
20599 if (value % 4 != 0)
20601 as_bad_where (fixP->fx_file, fixP->fx_line,
20602 _("offset not a multiple of 4"));
20608 as_bad_where (fixP->fx_file, fixP->fx_line,
20609 _("offset out of range"));
20614 else if ((newval & 0x000f0000) == 0x000f0000)
20616 /* PC-relative, 12-bit offset. */
20618 newval |= (1 << 23);
20623 as_bad_where (fixP->fx_file, fixP->fx_line,
20624 _("offset out of range"));
20629 else if ((newval & 0x00000100) == 0x00000100)
20631 /* Writeback: 8-bit, +/- offset. */
20633 newval |= (1 << 9);
20638 as_bad_where (fixP->fx_file, fixP->fx_line,
20639 _("offset out of range"));
20644 else if ((newval & 0x00000f00) == 0x00000e00)
20646 /* T-instruction: positive 8-bit offset. */
20647 if (value < 0 || value > 0xff)
20649 as_bad_where (fixP->fx_file, fixP->fx_line,
20650 _("offset out of range"));
20658 /* Positive 12-bit or negative 8-bit offset. */
20662 newval |= (1 << 23);
20672 as_bad_where (fixP->fx_file, fixP->fx_line,
20673 _("offset out of range"));
20680 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20681 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20684 case BFD_RELOC_ARM_SHIFT_IMM:
20685 newval = md_chars_to_number (buf, INSN_SIZE);
20686 if (((unsigned long) value) > 32
20688 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20690 as_bad_where (fixP->fx_file, fixP->fx_line,
20691 _("shift expression is too large"));
20696 /* Shifts of zero must be done as lsl. */
20698 else if (value == 32)
20700 newval &= 0xfffff07f;
20701 newval |= (value & 0x1f) << 7;
20702 md_number_to_chars (buf, newval, INSN_SIZE);
20705 case BFD_RELOC_ARM_T32_IMMEDIATE:
20706 case BFD_RELOC_ARM_T32_ADD_IMM:
20707 case BFD_RELOC_ARM_T32_IMM12:
20708 case BFD_RELOC_ARM_T32_ADD_PC12:
20709 /* We claim that this fixup has been processed here,
20710 even if in fact we generate an error because we do
20711 not have a reloc for it, so tc_gen_reloc will reject it. */
20715 && ! S_IS_DEFINED (fixP->fx_addsy))
20717 as_bad_where (fixP->fx_file, fixP->fx_line,
20718 _("undefined symbol %s used as an immediate value"),
20719 S_GET_NAME (fixP->fx_addsy));
20723 newval = md_chars_to_number (buf, THUMB_SIZE);
20725 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20728 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20729 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20731 newimm = encode_thumb32_immediate (value);
20732 if (newimm == (unsigned int) FAIL)
20733 newimm = thumb32_negate_data_op (&newval, value);
20735 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20736 && newimm == (unsigned int) FAIL)
20738 /* Turn add/sum into addw/subw. */
20739 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20740 newval = (newval & 0xfeffffff) | 0x02000000;
20741 /* No flat 12-bit imm encoding for addsw/subsw. */
20742 if ((newval & 0x00100000) == 0)
20744 /* 12 bit immediate for addw/subw. */
20748 newval ^= 0x00a00000;
20751 newimm = (unsigned int) FAIL;
20757 if (newimm == (unsigned int)FAIL)
20759 as_bad_where (fixP->fx_file, fixP->fx_line,
20760 _("invalid constant (%lx) after fixup"),
20761 (unsigned long) value);
20765 newval |= (newimm & 0x800) << 15;
20766 newval |= (newimm & 0x700) << 4;
20767 newval |= (newimm & 0x0ff);
20769 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20770 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20773 case BFD_RELOC_ARM_SMC:
20774 if (((unsigned long) value) > 0xffff)
20775 as_bad_where (fixP->fx_file, fixP->fx_line,
20776 _("invalid smc expression"));
20777 newval = md_chars_to_number (buf, INSN_SIZE);
20778 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20779 md_number_to_chars (buf, newval, INSN_SIZE);
20782 case BFD_RELOC_ARM_HVC:
20783 if (((unsigned long) value) > 0xffff)
20784 as_bad_where (fixP->fx_file, fixP->fx_line,
20785 _("invalid hvc expression"));
20786 newval = md_chars_to_number (buf, INSN_SIZE);
20787 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20788 md_number_to_chars (buf, newval, INSN_SIZE);
20791 case BFD_RELOC_ARM_SWI:
20792 if (fixP->tc_fix_data != 0)
20794 if (((unsigned long) value) > 0xff)
20795 as_bad_where (fixP->fx_file, fixP->fx_line,
20796 _("invalid swi expression"));
20797 newval = md_chars_to_number (buf, THUMB_SIZE);
20799 md_number_to_chars (buf, newval, THUMB_SIZE);
20803 if (((unsigned long) value) > 0x00ffffff)
20804 as_bad_where (fixP->fx_file, fixP->fx_line,
20805 _("invalid swi expression"));
20806 newval = md_chars_to_number (buf, INSN_SIZE);
20808 md_number_to_chars (buf, newval, INSN_SIZE);
20812 case BFD_RELOC_ARM_MULTI:
20813 if (((unsigned long) value) > 0xffff)
20814 as_bad_where (fixP->fx_file, fixP->fx_line,
20815 _("invalid expression in load/store multiple"));
20816 newval = value | md_chars_to_number (buf, INSN_SIZE);
20817 md_number_to_chars (buf, newval, INSN_SIZE);
20821 case BFD_RELOC_ARM_PCREL_CALL:
20823 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20825 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20826 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20827 && THUMB_IS_FUNC (fixP->fx_addsy))
20828 /* Flip the bl to blx. This is a simple flip
20829 bit here because we generate PCREL_CALL for
20830 unconditional bls. */
20832 newval = md_chars_to_number (buf, INSN_SIZE);
20833 newval = newval | 0x10000000;
20834 md_number_to_chars (buf, newval, INSN_SIZE);
20840 goto arm_branch_common;
20842 case BFD_RELOC_ARM_PCREL_JUMP:
20843 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20845 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20846 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20847 && THUMB_IS_FUNC (fixP->fx_addsy))
20849 /* This would map to a bl<cond>, b<cond>,
20850 b<always> to a Thumb function. We
20851 need to force a relocation for this particular
20853 newval = md_chars_to_number (buf, INSN_SIZE);
20857 case BFD_RELOC_ARM_PLT32:
20859 case BFD_RELOC_ARM_PCREL_BRANCH:
20861 goto arm_branch_common;
20863 case BFD_RELOC_ARM_PCREL_BLX:
20866 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20868 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20869 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20870 && ARM_IS_FUNC (fixP->fx_addsy))
20872 /* Flip the blx to a bl and warn. */
20873 const char *name = S_GET_NAME (fixP->fx_addsy);
20874 newval = 0xeb000000;
20875 as_warn_where (fixP->fx_file, fixP->fx_line,
20876 _("blx to '%s' an ARM ISA state function changed to bl"),
20878 md_number_to_chars (buf, newval, INSN_SIZE);
20884 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20885 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20889 /* We are going to store value (shifted right by two) in the
20890 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20891 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20892 also be be clear. */
20894 as_bad_where (fixP->fx_file, fixP->fx_line,
20895 _("misaligned branch destination"));
20896 if ((value & (offsetT)0xfe000000) != (offsetT)0
20897 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
20898 as_bad_where (fixP->fx_file, fixP->fx_line,
20899 _("branch out of range"));
20901 if (fixP->fx_done || !seg->use_rela_p)
20903 newval = md_chars_to_number (buf, INSN_SIZE);
20904 newval |= (value >> 2) & 0x00ffffff;
20905 /* Set the H bit on BLX instructions. */
20909 newval |= 0x01000000;
20911 newval &= ~0x01000000;
20913 md_number_to_chars (buf, newval, INSN_SIZE);
20917 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
20918 /* CBZ can only branch forward. */
20920 /* Attempts to use CBZ to branch to the next instruction
20921 (which, strictly speaking, are prohibited) will be turned into
20924 FIXME: It may be better to remove the instruction completely and
20925 perform relaxation. */
20928 newval = md_chars_to_number (buf, THUMB_SIZE);
20929 newval = 0xbf00; /* NOP encoding T1 */
20930 md_number_to_chars (buf, newval, THUMB_SIZE);
20935 as_bad_where (fixP->fx_file, fixP->fx_line,
20936 _("branch out of range"));
20938 if (fixP->fx_done || !seg->use_rela_p)
20940 newval = md_chars_to_number (buf, THUMB_SIZE);
20941 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
20942 md_number_to_chars (buf, newval, THUMB_SIZE);
20947 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
20948 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
20949 as_bad_where (fixP->fx_file, fixP->fx_line,
20950 _("branch out of range"));
20952 if (fixP->fx_done || !seg->use_rela_p)
20954 newval = md_chars_to_number (buf, THUMB_SIZE);
20955 newval |= (value & 0x1ff) >> 1;
20956 md_number_to_chars (buf, newval, THUMB_SIZE);
20960 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
20961 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
20962 as_bad_where (fixP->fx_file, fixP->fx_line,
20963 _("branch out of range"));
20965 if (fixP->fx_done || !seg->use_rela_p)
20967 newval = md_chars_to_number (buf, THUMB_SIZE);
20968 newval |= (value & 0xfff) >> 1;
20969 md_number_to_chars (buf, newval, THUMB_SIZE);
20973 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20975 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20976 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20977 && ARM_IS_FUNC (fixP->fx_addsy)
20978 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20980 /* Force a relocation for a branch 20 bits wide. */
20983 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
20984 as_bad_where (fixP->fx_file, fixP->fx_line,
20985 _("conditional branch out of range"));
20987 if (fixP->fx_done || !seg->use_rela_p)
20990 addressT S, J1, J2, lo, hi;
20992 S = (value & 0x00100000) >> 20;
20993 J2 = (value & 0x00080000) >> 19;
20994 J1 = (value & 0x00040000) >> 18;
20995 hi = (value & 0x0003f000) >> 12;
20996 lo = (value & 0x00000ffe) >> 1;
20998 newval = md_chars_to_number (buf, THUMB_SIZE);
20999 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21000 newval |= (S << 10) | hi;
21001 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21002 md_number_to_chars (buf, newval, THUMB_SIZE);
21003 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21007 case BFD_RELOC_THUMB_PCREL_BLX:
21009 /* If there is a blx from a thumb state function to
21010 another thumb function flip this to a bl and warn
21014 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21015 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21016 && THUMB_IS_FUNC (fixP->fx_addsy))
21018 const char *name = S_GET_NAME (fixP->fx_addsy);
21019 as_warn_where (fixP->fx_file, fixP->fx_line,
21020 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21022 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21023 newval = newval | 0x1000;
21024 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21025 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21030 goto thumb_bl_common;
21032 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21034 /* A bl from Thumb state ISA to an internal ARM state function
21035 is converted to a blx. */
21037 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21038 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21039 && ARM_IS_FUNC (fixP->fx_addsy)
21040 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21042 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21043 newval = newval & ~0x1000;
21044 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21045 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21052 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21053 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21054 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21057 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21058 /* For a BLX instruction, make sure that the relocation is rounded up
21059 to a word boundary. This follows the semantics of the instruction
21060 which specifies that bit 1 of the target address will come from bit
21061 1 of the base address. */
21062 value = (value + 1) & ~ 1;
21065 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21067 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21069 as_bad_where (fixP->fx_file, fixP->fx_line,
21070 _("branch out of range"));
21072 else if ((value & ~0x1ffffff)
21073 && ((value & ~0x1ffffff) != ~0x1ffffff))
21075 as_bad_where (fixP->fx_file, fixP->fx_line,
21076 _("Thumb2 branch out of range"));
21080 if (fixP->fx_done || !seg->use_rela_p)
21081 encode_thumb2_b_bl_offset (buf, value);
21085 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21086 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
21087 as_bad_where (fixP->fx_file, fixP->fx_line,
21088 _("branch out of range"));
21090 if (fixP->fx_done || !seg->use_rela_p)
21091 encode_thumb2_b_bl_offset (buf, value);
21096 if (fixP->fx_done || !seg->use_rela_p)
21097 md_number_to_chars (buf, value, 1);
21101 if (fixP->fx_done || !seg->use_rela_p)
21102 md_number_to_chars (buf, value, 2);
21106 case BFD_RELOC_ARM_TLS_CALL:
21107 case BFD_RELOC_ARM_THM_TLS_CALL:
21108 case BFD_RELOC_ARM_TLS_DESCSEQ:
21109 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21110 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21113 case BFD_RELOC_ARM_TLS_GOTDESC:
21114 case BFD_RELOC_ARM_TLS_GD32:
21115 case BFD_RELOC_ARM_TLS_LE32:
21116 case BFD_RELOC_ARM_TLS_IE32:
21117 case BFD_RELOC_ARM_TLS_LDM32:
21118 case BFD_RELOC_ARM_TLS_LDO32:
21119 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21122 case BFD_RELOC_ARM_GOT32:
21123 case BFD_RELOC_ARM_GOTOFF:
21124 if (fixP->fx_done || !seg->use_rela_p)
21125 md_number_to_chars (buf, 0, 4);
21128 case BFD_RELOC_ARM_GOT_PREL:
21129 if (fixP->fx_done || !seg->use_rela_p)
21130 md_number_to_chars (buf, value, 4);
21133 case BFD_RELOC_ARM_TARGET2:
21134 /* TARGET2 is not partial-inplace, so we need to write the
21135 addend here for REL targets, because it won't be written out
21136 during reloc processing later. */
21137 if (fixP->fx_done || !seg->use_rela_p)
21138 md_number_to_chars (buf, fixP->fx_offset, 4);
21142 case BFD_RELOC_RVA:
21144 case BFD_RELOC_ARM_TARGET1:
21145 case BFD_RELOC_ARM_ROSEGREL32:
21146 case BFD_RELOC_ARM_SBREL32:
21147 case BFD_RELOC_32_PCREL:
21149 case BFD_RELOC_32_SECREL:
21151 if (fixP->fx_done || !seg->use_rela_p)
21153 /* For WinCE we only do this for pcrel fixups. */
21154 if (fixP->fx_done || fixP->fx_pcrel)
21156 md_number_to_chars (buf, value, 4);
21160 case BFD_RELOC_ARM_PREL31:
21161 if (fixP->fx_done || !seg->use_rela_p)
21163 newval = md_chars_to_number (buf, 4) & 0x80000000;
21164 if ((value ^ (value >> 1)) & 0x40000000)
21166 as_bad_where (fixP->fx_file, fixP->fx_line,
21167 _("rel31 relocation overflow"));
21169 newval |= value & 0x7fffffff;
21170 md_number_to_chars (buf, newval, 4);
21175 case BFD_RELOC_ARM_CP_OFF_IMM:
21176 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21177 if (value < -1023 || value > 1023 || (value & 3))
21178 as_bad_where (fixP->fx_file, fixP->fx_line,
21179 _("co-processor offset out of range"));
21184 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21185 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21186 newval = md_chars_to_number (buf, INSN_SIZE);
21188 newval = get_thumb32_insn (buf);
21190 newval &= 0xffffff00;
21193 newval &= 0xff7fff00;
21194 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21196 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21197 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21198 md_number_to_chars (buf, newval, INSN_SIZE);
21200 put_thumb32_insn (buf, newval);
21203 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21204 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21205 if (value < -255 || value > 255)
21206 as_bad_where (fixP->fx_file, fixP->fx_line,
21207 _("co-processor offset out of range"));
21209 goto cp_off_common;
21211 case BFD_RELOC_ARM_THUMB_OFFSET:
21212 newval = md_chars_to_number (buf, THUMB_SIZE);
21213 /* Exactly what ranges, and where the offset is inserted depends
21214 on the type of instruction, we can establish this from the
21216 switch (newval >> 12)
21218 case 4: /* PC load. */
21219 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21220 forced to zero for these loads; md_pcrel_from has already
21221 compensated for this. */
21223 as_bad_where (fixP->fx_file, fixP->fx_line,
21224 _("invalid offset, target not word aligned (0x%08lX)"),
21225 (((unsigned long) fixP->fx_frag->fr_address
21226 + (unsigned long) fixP->fx_where) & ~3)
21227 + (unsigned long) value);
21229 if (value & ~0x3fc)
21230 as_bad_where (fixP->fx_file, fixP->fx_line,
21231 _("invalid offset, value too big (0x%08lX)"),
21234 newval |= value >> 2;
21237 case 9: /* SP load/store. */
21238 if (value & ~0x3fc)
21239 as_bad_where (fixP->fx_file, fixP->fx_line,
21240 _("invalid offset, value too big (0x%08lX)"),
21242 newval |= value >> 2;
21245 case 6: /* Word load/store. */
21247 as_bad_where (fixP->fx_file, fixP->fx_line,
21248 _("invalid offset, value too big (0x%08lX)"),
21250 newval |= value << 4; /* 6 - 2. */
21253 case 7: /* Byte load/store. */
21255 as_bad_where (fixP->fx_file, fixP->fx_line,
21256 _("invalid offset, value too big (0x%08lX)"),
21258 newval |= value << 6;
21261 case 8: /* Halfword load/store. */
21263 as_bad_where (fixP->fx_file, fixP->fx_line,
21264 _("invalid offset, value too big (0x%08lX)"),
21266 newval |= value << 5; /* 6 - 1. */
21270 as_bad_where (fixP->fx_file, fixP->fx_line,
21271 "Unable to process relocation for thumb opcode: %lx",
21272 (unsigned long) newval);
21275 md_number_to_chars (buf, newval, THUMB_SIZE);
21278 case BFD_RELOC_ARM_THUMB_ADD:
21279 /* This is a complicated relocation, since we use it for all of
21280 the following immediate relocations:
21284 9bit ADD/SUB SP word-aligned
21285 10bit ADD PC/SP word-aligned
21287 The type of instruction being processed is encoded in the
21294 newval = md_chars_to_number (buf, THUMB_SIZE);
21296 int rd = (newval >> 4) & 0xf;
21297 int rs = newval & 0xf;
21298 int subtract = !!(newval & 0x8000);
21300 /* Check for HI regs, only very restricted cases allowed:
21301 Adjusting SP, and using PC or SP to get an address. */
21302 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21303 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21304 as_bad_where (fixP->fx_file, fixP->fx_line,
21305 _("invalid Hi register with immediate"));
21307 /* If value is negative, choose the opposite instruction. */
21311 subtract = !subtract;
21313 as_bad_where (fixP->fx_file, fixP->fx_line,
21314 _("immediate value out of range"));
21319 if (value & ~0x1fc)
21320 as_bad_where (fixP->fx_file, fixP->fx_line,
21321 _("invalid immediate for stack address calculation"));
21322 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21323 newval |= value >> 2;
21325 else if (rs == REG_PC || rs == REG_SP)
21327 if (subtract || value & ~0x3fc)
21328 as_bad_where (fixP->fx_file, fixP->fx_line,
21329 _("invalid immediate for address calculation (value = 0x%08lX)"),
21330 (unsigned long) value);
21331 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21333 newval |= value >> 2;
21338 as_bad_where (fixP->fx_file, fixP->fx_line,
21339 _("immediate value out of range"));
21340 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21341 newval |= (rd << 8) | value;
21346 as_bad_where (fixP->fx_file, fixP->fx_line,
21347 _("immediate value out of range"));
21348 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21349 newval |= rd | (rs << 3) | (value << 6);
21352 md_number_to_chars (buf, newval, THUMB_SIZE);
21355 case BFD_RELOC_ARM_THUMB_IMM:
21356 newval = md_chars_to_number (buf, THUMB_SIZE);
21357 if (value < 0 || value > 255)
21358 as_bad_where (fixP->fx_file, fixP->fx_line,
21359 _("invalid immediate: %ld is out of range"),
21362 md_number_to_chars (buf, newval, THUMB_SIZE);
21365 case BFD_RELOC_ARM_THUMB_SHIFT:
21366 /* 5bit shift value (0..32). LSL cannot take 32. */
21367 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21368 temp = newval & 0xf800;
21369 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21370 as_bad_where (fixP->fx_file, fixP->fx_line,
21371 _("invalid shift value: %ld"), (long) value);
21372 /* Shifts of zero must be encoded as LSL. */
21374 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21375 /* Shifts of 32 are encoded as zero. */
21376 else if (value == 32)
21378 newval |= value << 6;
21379 md_number_to_chars (buf, newval, THUMB_SIZE);
21382 case BFD_RELOC_VTABLE_INHERIT:
21383 case BFD_RELOC_VTABLE_ENTRY:
21387 case BFD_RELOC_ARM_MOVW:
21388 case BFD_RELOC_ARM_MOVT:
21389 case BFD_RELOC_ARM_THUMB_MOVW:
21390 case BFD_RELOC_ARM_THUMB_MOVT:
21391 if (fixP->fx_done || !seg->use_rela_p)
21393 /* REL format relocations are limited to a 16-bit addend. */
21394 if (!fixP->fx_done)
21396 if (value < -0x8000 || value > 0x7fff)
21397 as_bad_where (fixP->fx_file, fixP->fx_line,
21398 _("offset out of range"));
21400 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21401 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21406 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21407 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21409 newval = get_thumb32_insn (buf);
21410 newval &= 0xfbf08f00;
21411 newval |= (value & 0xf000) << 4;
21412 newval |= (value & 0x0800) << 15;
21413 newval |= (value & 0x0700) << 4;
21414 newval |= (value & 0x00ff);
21415 put_thumb32_insn (buf, newval);
21419 newval = md_chars_to_number (buf, 4);
21420 newval &= 0xfff0f000;
21421 newval |= value & 0x0fff;
21422 newval |= (value & 0xf000) << 4;
21423 md_number_to_chars (buf, newval, 4);
21428 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21429 case BFD_RELOC_ARM_ALU_PC_G0:
21430 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21431 case BFD_RELOC_ARM_ALU_PC_G1:
21432 case BFD_RELOC_ARM_ALU_PC_G2:
21433 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21434 case BFD_RELOC_ARM_ALU_SB_G0:
21435 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21436 case BFD_RELOC_ARM_ALU_SB_G1:
21437 case BFD_RELOC_ARM_ALU_SB_G2:
21438 gas_assert (!fixP->fx_done);
21439 if (!seg->use_rela_p)
21442 bfd_vma encoded_addend;
21443 bfd_vma addend_abs = abs (value);
21445 /* Check that the absolute value of the addend can be
21446 expressed as an 8-bit constant plus a rotation. */
21447 encoded_addend = encode_arm_immediate (addend_abs);
21448 if (encoded_addend == (unsigned int) FAIL)
21449 as_bad_where (fixP->fx_file, fixP->fx_line,
21450 _("the offset 0x%08lX is not representable"),
21451 (unsigned long) addend_abs);
21453 /* Extract the instruction. */
21454 insn = md_chars_to_number (buf, INSN_SIZE);
21456 /* If the addend is positive, use an ADD instruction.
21457 Otherwise use a SUB. Take care not to destroy the S bit. */
21458 insn &= 0xff1fffff;
21464 /* Place the encoded addend into the first 12 bits of the
21466 insn &= 0xfffff000;
21467 insn |= encoded_addend;
21469 /* Update the instruction. */
21470 md_number_to_chars (buf, insn, INSN_SIZE);
21474 case BFD_RELOC_ARM_LDR_PC_G0:
21475 case BFD_RELOC_ARM_LDR_PC_G1:
21476 case BFD_RELOC_ARM_LDR_PC_G2:
21477 case BFD_RELOC_ARM_LDR_SB_G0:
21478 case BFD_RELOC_ARM_LDR_SB_G1:
21479 case BFD_RELOC_ARM_LDR_SB_G2:
21480 gas_assert (!fixP->fx_done);
21481 if (!seg->use_rela_p)
21484 bfd_vma addend_abs = abs (value);
21486 /* Check that the absolute value of the addend can be
21487 encoded in 12 bits. */
21488 if (addend_abs >= 0x1000)
21489 as_bad_where (fixP->fx_file, fixP->fx_line,
21490 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21491 (unsigned long) addend_abs);
21493 /* Extract the instruction. */
21494 insn = md_chars_to_number (buf, INSN_SIZE);
21496 /* If the addend is negative, clear bit 23 of the instruction.
21497 Otherwise set it. */
21499 insn &= ~(1 << 23);
21503 /* Place the absolute value of the addend into the first 12 bits
21504 of the instruction. */
21505 insn &= 0xfffff000;
21506 insn |= addend_abs;
21508 /* Update the instruction. */
21509 md_number_to_chars (buf, insn, INSN_SIZE);
21513 case BFD_RELOC_ARM_LDRS_PC_G0:
21514 case BFD_RELOC_ARM_LDRS_PC_G1:
21515 case BFD_RELOC_ARM_LDRS_PC_G2:
21516 case BFD_RELOC_ARM_LDRS_SB_G0:
21517 case BFD_RELOC_ARM_LDRS_SB_G1:
21518 case BFD_RELOC_ARM_LDRS_SB_G2:
21519 gas_assert (!fixP->fx_done);
21520 if (!seg->use_rela_p)
21523 bfd_vma addend_abs = abs (value);
21525 /* Check that the absolute value of the addend can be
21526 encoded in 8 bits. */
21527 if (addend_abs >= 0x100)
21528 as_bad_where (fixP->fx_file, fixP->fx_line,
21529 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21530 (unsigned long) addend_abs);
21532 /* Extract the instruction. */
21533 insn = md_chars_to_number (buf, INSN_SIZE);
21535 /* If the addend is negative, clear bit 23 of the instruction.
21536 Otherwise set it. */
21538 insn &= ~(1 << 23);
21542 /* Place the first four bits of the absolute value of the addend
21543 into the first 4 bits of the instruction, and the remaining
21544 four into bits 8 .. 11. */
21545 insn &= 0xfffff0f0;
21546 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21548 /* Update the instruction. */
21549 md_number_to_chars (buf, insn, INSN_SIZE);
21553 case BFD_RELOC_ARM_LDC_PC_G0:
21554 case BFD_RELOC_ARM_LDC_PC_G1:
21555 case BFD_RELOC_ARM_LDC_PC_G2:
21556 case BFD_RELOC_ARM_LDC_SB_G0:
21557 case BFD_RELOC_ARM_LDC_SB_G1:
21558 case BFD_RELOC_ARM_LDC_SB_G2:
21559 gas_assert (!fixP->fx_done);
21560 if (!seg->use_rela_p)
21563 bfd_vma addend_abs = abs (value);
21565 /* Check that the absolute value of the addend is a multiple of
21566 four and, when divided by four, fits in 8 bits. */
21567 if (addend_abs & 0x3)
21568 as_bad_where (fixP->fx_file, fixP->fx_line,
21569 _("bad offset 0x%08lX (must be word-aligned)"),
21570 (unsigned long) addend_abs);
21572 if ((addend_abs >> 2) > 0xff)
21573 as_bad_where (fixP->fx_file, fixP->fx_line,
21574 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21575 (unsigned long) addend_abs);
21577 /* Extract the instruction. */
21578 insn = md_chars_to_number (buf, INSN_SIZE);
21580 /* If the addend is negative, clear bit 23 of the instruction.
21581 Otherwise set it. */
21583 insn &= ~(1 << 23);
21587 /* Place the addend (divided by four) into the first eight
21588 bits of the instruction. */
21589 insn &= 0xfffffff0;
21590 insn |= addend_abs >> 2;
21592 /* Update the instruction. */
21593 md_number_to_chars (buf, insn, INSN_SIZE);
21597 case BFD_RELOC_ARM_V4BX:
21598 /* This will need to go in the object file. */
21602 case BFD_RELOC_UNUSED:
21604 as_bad_where (fixP->fx_file, fixP->fx_line,
21605 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21609 /* Translate internal representation of relocation info to BFD target
21613 tc_gen_reloc (asection *section, fixS *fixp)
21616 bfd_reloc_code_real_type code;
21618 reloc = (arelent *) xmalloc (sizeof (arelent));
21620 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21621 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21622 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21624 if (fixp->fx_pcrel)
21626 if (section->use_rela_p)
21627 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21629 fixp->fx_offset = reloc->address;
21631 reloc->addend = fixp->fx_offset;
21633 switch (fixp->fx_r_type)
21636 if (fixp->fx_pcrel)
21638 code = BFD_RELOC_8_PCREL;
21643 if (fixp->fx_pcrel)
21645 code = BFD_RELOC_16_PCREL;
21650 if (fixp->fx_pcrel)
21652 code = BFD_RELOC_32_PCREL;
21656 case BFD_RELOC_ARM_MOVW:
21657 if (fixp->fx_pcrel)
21659 code = BFD_RELOC_ARM_MOVW_PCREL;
21663 case BFD_RELOC_ARM_MOVT:
21664 if (fixp->fx_pcrel)
21666 code = BFD_RELOC_ARM_MOVT_PCREL;
21670 case BFD_RELOC_ARM_THUMB_MOVW:
21671 if (fixp->fx_pcrel)
21673 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21677 case BFD_RELOC_ARM_THUMB_MOVT:
21678 if (fixp->fx_pcrel)
21680 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21684 case BFD_RELOC_NONE:
21685 case BFD_RELOC_ARM_PCREL_BRANCH:
21686 case BFD_RELOC_ARM_PCREL_BLX:
21687 case BFD_RELOC_RVA:
21688 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21689 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21690 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21691 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21692 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21693 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21694 case BFD_RELOC_VTABLE_ENTRY:
21695 case BFD_RELOC_VTABLE_INHERIT:
21697 case BFD_RELOC_32_SECREL:
21699 code = fixp->fx_r_type;
21702 case BFD_RELOC_THUMB_PCREL_BLX:
21704 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21705 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21708 code = BFD_RELOC_THUMB_PCREL_BLX;
21711 case BFD_RELOC_ARM_LITERAL:
21712 case BFD_RELOC_ARM_HWLITERAL:
21713 /* If this is called then the a literal has
21714 been referenced across a section boundary. */
21715 as_bad_where (fixp->fx_file, fixp->fx_line,
21716 _("literal referenced across section boundary"));
21720 case BFD_RELOC_ARM_TLS_CALL:
21721 case BFD_RELOC_ARM_THM_TLS_CALL:
21722 case BFD_RELOC_ARM_TLS_DESCSEQ:
21723 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21724 case BFD_RELOC_ARM_GOT32:
21725 case BFD_RELOC_ARM_GOTOFF:
21726 case BFD_RELOC_ARM_GOT_PREL:
21727 case BFD_RELOC_ARM_PLT32:
21728 case BFD_RELOC_ARM_TARGET1:
21729 case BFD_RELOC_ARM_ROSEGREL32:
21730 case BFD_RELOC_ARM_SBREL32:
21731 case BFD_RELOC_ARM_PREL31:
21732 case BFD_RELOC_ARM_TARGET2:
21733 case BFD_RELOC_ARM_TLS_LE32:
21734 case BFD_RELOC_ARM_TLS_LDO32:
21735 case BFD_RELOC_ARM_PCREL_CALL:
21736 case BFD_RELOC_ARM_PCREL_JUMP:
21737 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21738 case BFD_RELOC_ARM_ALU_PC_G0:
21739 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21740 case BFD_RELOC_ARM_ALU_PC_G1:
21741 case BFD_RELOC_ARM_ALU_PC_G2:
21742 case BFD_RELOC_ARM_LDR_PC_G0:
21743 case BFD_RELOC_ARM_LDR_PC_G1:
21744 case BFD_RELOC_ARM_LDR_PC_G2:
21745 case BFD_RELOC_ARM_LDRS_PC_G0:
21746 case BFD_RELOC_ARM_LDRS_PC_G1:
21747 case BFD_RELOC_ARM_LDRS_PC_G2:
21748 case BFD_RELOC_ARM_LDC_PC_G0:
21749 case BFD_RELOC_ARM_LDC_PC_G1:
21750 case BFD_RELOC_ARM_LDC_PC_G2:
21751 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21752 case BFD_RELOC_ARM_ALU_SB_G0:
21753 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21754 case BFD_RELOC_ARM_ALU_SB_G1:
21755 case BFD_RELOC_ARM_ALU_SB_G2:
21756 case BFD_RELOC_ARM_LDR_SB_G0:
21757 case BFD_RELOC_ARM_LDR_SB_G1:
21758 case BFD_RELOC_ARM_LDR_SB_G2:
21759 case BFD_RELOC_ARM_LDRS_SB_G0:
21760 case BFD_RELOC_ARM_LDRS_SB_G1:
21761 case BFD_RELOC_ARM_LDRS_SB_G2:
21762 case BFD_RELOC_ARM_LDC_SB_G0:
21763 case BFD_RELOC_ARM_LDC_SB_G1:
21764 case BFD_RELOC_ARM_LDC_SB_G2:
21765 case BFD_RELOC_ARM_V4BX:
21766 code = fixp->fx_r_type;
21769 case BFD_RELOC_ARM_TLS_GOTDESC:
21770 case BFD_RELOC_ARM_TLS_GD32:
21771 case BFD_RELOC_ARM_TLS_IE32:
21772 case BFD_RELOC_ARM_TLS_LDM32:
21773 /* BFD will include the symbol's address in the addend.
21774 But we don't want that, so subtract it out again here. */
21775 if (!S_IS_COMMON (fixp->fx_addsy))
21776 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21777 code = fixp->fx_r_type;
21781 case BFD_RELOC_ARM_IMMEDIATE:
21782 as_bad_where (fixp->fx_file, fixp->fx_line,
21783 _("internal relocation (type: IMMEDIATE) not fixed up"));
21786 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21787 as_bad_where (fixp->fx_file, fixp->fx_line,
21788 _("ADRL used for a symbol not defined in the same file"));
21791 case BFD_RELOC_ARM_OFFSET_IMM:
21792 if (section->use_rela_p)
21794 code = fixp->fx_r_type;
21798 if (fixp->fx_addsy != NULL
21799 && !S_IS_DEFINED (fixp->fx_addsy)
21800 && S_IS_LOCAL (fixp->fx_addsy))
21802 as_bad_where (fixp->fx_file, fixp->fx_line,
21803 _("undefined local label `%s'"),
21804 S_GET_NAME (fixp->fx_addsy));
21808 as_bad_where (fixp->fx_file, fixp->fx_line,
21809 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21816 switch (fixp->fx_r_type)
21818 case BFD_RELOC_NONE: type = "NONE"; break;
21819 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21820 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21821 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21822 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21823 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21824 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21825 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21826 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21827 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21828 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21829 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21830 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21831 default: type = _("<unknown>"); break;
21833 as_bad_where (fixp->fx_file, fixp->fx_line,
21834 _("cannot represent %s relocation in this object file format"),
21841 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21843 && fixp->fx_addsy == GOT_symbol)
21845 code = BFD_RELOC_ARM_GOTPC;
21846 reloc->addend = fixp->fx_offset = reloc->address;
21850 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21852 if (reloc->howto == NULL)
21854 as_bad_where (fixp->fx_file, fixp->fx_line,
21855 _("cannot represent %s relocation in this object file format"),
21856 bfd_get_reloc_code_name (code));
21860 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21861 vtable entry to be used in the relocation's section offset. */
21862 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21863 reloc->address = fixp->fx_offset;
21868 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21871 cons_fix_new_arm (fragS * frag,
21876 bfd_reloc_code_real_type type;
21880 FIXME: @@ Should look at CPU word size. */
21884 type = BFD_RELOC_8;
21887 type = BFD_RELOC_16;
21891 type = BFD_RELOC_32;
21894 type = BFD_RELOC_64;
21899 if (exp->X_op == O_secrel)
21901 exp->X_op = O_symbol;
21902 type = BFD_RELOC_32_SECREL;
21906 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
21909 #if defined (OBJ_COFF)
21911 arm_validate_fix (fixS * fixP)
21913 /* If the destination of the branch is a defined symbol which does not have
21914 the THUMB_FUNC attribute, then we must be calling a function which has
21915 the (interfacearm) attribute. We look for the Thumb entry point to that
21916 function and change the branch to refer to that function instead. */
21917 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
21918 && fixP->fx_addsy != NULL
21919 && S_IS_DEFINED (fixP->fx_addsy)
21920 && ! THUMB_IS_FUNC (fixP->fx_addsy))
21922 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
21929 arm_force_relocation (struct fix * fixp)
21931 #if defined (OBJ_COFF) && defined (TE_PE)
21932 if (fixp->fx_r_type == BFD_RELOC_RVA)
21936 /* In case we have a call or a branch to a function in ARM ISA mode from
21937 a thumb function or vice-versa force the relocation. These relocations
21938 are cleared off for some cores that might have blx and simple transformations
21942 switch (fixp->fx_r_type)
21944 case BFD_RELOC_ARM_PCREL_JUMP:
21945 case BFD_RELOC_ARM_PCREL_CALL:
21946 case BFD_RELOC_THUMB_PCREL_BLX:
21947 if (THUMB_IS_FUNC (fixp->fx_addsy))
21951 case BFD_RELOC_ARM_PCREL_BLX:
21952 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21953 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21954 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21955 if (ARM_IS_FUNC (fixp->fx_addsy))
21964 /* Resolve these relocations even if the symbol is extern or weak.
21965 Technically this is probably wrong due to symbol preemption.
21966 In practice these relocations do not have enough range to be useful
21967 at dynamic link time, and some code (e.g. in the Linux kernel)
21968 expects these references to be resolved. */
21969 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
21970 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
21971 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
21972 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
21973 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21974 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
21975 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
21976 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
21977 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21978 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
21979 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
21980 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
21981 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
21982 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
21985 /* Always leave these relocations for the linker. */
21986 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
21987 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
21988 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
21991 /* Always generate relocations against function symbols. */
21992 if (fixp->fx_r_type == BFD_RELOC_32
21994 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
21997 return generic_force_reloc (fixp);
22000 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22001 /* Relocations against function names must be left unadjusted,
22002 so that the linker can use this information to generate interworking
22003 stubs. The MIPS version of this function
22004 also prevents relocations that are mips-16 specific, but I do not
22005 know why it does this.
22008 There is one other problem that ought to be addressed here, but
22009 which currently is not: Taking the address of a label (rather
22010 than a function) and then later jumping to that address. Such
22011 addresses also ought to have their bottom bit set (assuming that
22012 they reside in Thumb code), but at the moment they will not. */
22015 arm_fix_adjustable (fixS * fixP)
22017 if (fixP->fx_addsy == NULL)
22020 /* Preserve relocations against symbols with function type. */
22021 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22024 if (THUMB_IS_FUNC (fixP->fx_addsy)
22025 && fixP->fx_subsy == NULL)
22028 /* We need the symbol name for the VTABLE entries. */
22029 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22030 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22033 /* Don't allow symbols to be discarded on GOT related relocs. */
22034 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22035 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22036 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22037 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22038 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22039 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22040 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22041 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22042 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22043 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22044 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22045 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22046 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22047 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22050 /* Similarly for group relocations. */
22051 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22052 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22053 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22056 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22057 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22058 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22059 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22060 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22061 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22062 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22063 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22064 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22069 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22074 elf32_arm_target_format (void)
22077 return (target_big_endian
22078 ? "elf32-bigarm-symbian"
22079 : "elf32-littlearm-symbian");
22080 #elif defined (TE_VXWORKS)
22081 return (target_big_endian
22082 ? "elf32-bigarm-vxworks"
22083 : "elf32-littlearm-vxworks");
22085 if (target_big_endian)
22086 return "elf32-bigarm";
22088 return "elf32-littlearm";
22093 armelf_frob_symbol (symbolS * symp,
22096 elf_frob_symbol (symp, puntp);
22100 /* MD interface: Finalization. */
22105 literal_pool * pool;
22107 /* Ensure that all the IT blocks are properly closed. */
22108 check_it_blocks_finished ();
22110 for (pool = list_of_pools; pool; pool = pool->next)
22112 /* Put it at the end of the relevant section. */
22113 subseg_set (pool->section, pool->sub_section);
22115 arm_elf_change_section ();
22122 /* Remove any excess mapping symbols generated for alignment frags in
22123 SEC. We may have created a mapping symbol before a zero byte
22124 alignment; remove it if there's a mapping symbol after the
22127 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22128 void *dummy ATTRIBUTE_UNUSED)
22130 segment_info_type *seginfo = seg_info (sec);
22133 if (seginfo == NULL || seginfo->frchainP == NULL)
22136 for (fragp = seginfo->frchainP->frch_root;
22138 fragp = fragp->fr_next)
22140 symbolS *sym = fragp->tc_frag_data.last_map;
22141 fragS *next = fragp->fr_next;
22143 /* Variable-sized frags have been converted to fixed size by
22144 this point. But if this was variable-sized to start with,
22145 there will be a fixed-size frag after it. So don't handle
22147 if (sym == NULL || next == NULL)
22150 if (S_GET_VALUE (sym) < next->fr_address)
22151 /* Not at the end of this frag. */
22153 know (S_GET_VALUE (sym) == next->fr_address);
22157 if (next->tc_frag_data.first_map != NULL)
22159 /* Next frag starts with a mapping symbol. Discard this
22161 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22165 if (next->fr_next == NULL)
22167 /* This mapping symbol is at the end of the section. Discard
22169 know (next->fr_fix == 0 && next->fr_var == 0);
22170 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22174 /* As long as we have empty frags without any mapping symbols,
22176 /* If the next frag is non-empty and does not start with a
22177 mapping symbol, then this mapping symbol is required. */
22178 if (next->fr_address != next->fr_next->fr_address)
22181 next = next->fr_next;
22183 while (next != NULL);
22188 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22192 arm_adjust_symtab (void)
22197 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22199 if (ARM_IS_THUMB (sym))
22201 if (THUMB_IS_FUNC (sym))
22203 /* Mark the symbol as a Thumb function. */
22204 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22205 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22206 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22208 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22209 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22211 as_bad (_("%s: unexpected function type: %d"),
22212 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22214 else switch (S_GET_STORAGE_CLASS (sym))
22217 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22220 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22223 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22231 if (ARM_IS_INTERWORK (sym))
22232 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22239 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22241 if (ARM_IS_THUMB (sym))
22243 elf_symbol_type * elf_sym;
22245 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22246 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22248 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22249 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22251 /* If it's a .thumb_func, declare it as so,
22252 otherwise tag label as .code 16. */
22253 if (THUMB_IS_FUNC (sym))
22254 elf_sym->internal_elf_sym.st_target_internal
22255 = ST_BRANCH_TO_THUMB;
22256 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22257 elf_sym->internal_elf_sym.st_info =
22258 ELF_ST_INFO (bind, STT_ARM_16BIT);
22263 /* Remove any overlapping mapping symbols generated by alignment frags. */
22264 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22265 /* Now do generic ELF adjustments. */
22266 elf_adjust_symtab ();
22270 /* MD interface: Initialization. */
22273 set_constant_flonums (void)
22277 for (i = 0; i < NUM_FLOAT_VALS; i++)
22278 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22282 /* Auto-select Thumb mode if it's the only available instruction set for the
22283 given architecture. */
22286 autoselect_thumb_from_cpu_variant (void)
22288 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22289 opcode_select (16);
22298 if ( (arm_ops_hsh = hash_new ()) == NULL
22299 || (arm_cond_hsh = hash_new ()) == NULL
22300 || (arm_shift_hsh = hash_new ()) == NULL
22301 || (arm_psr_hsh = hash_new ()) == NULL
22302 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22303 || (arm_reg_hsh = hash_new ()) == NULL
22304 || (arm_reloc_hsh = hash_new ()) == NULL
22305 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22306 as_fatal (_("virtual memory exhausted"));
22308 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22309 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22310 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22311 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22312 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22313 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22314 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22315 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22316 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22317 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22318 (void *) (v7m_psrs + i));
22319 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22320 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22322 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22324 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22325 (void *) (barrier_opt_names + i));
22327 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
22328 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
22331 set_constant_flonums ();
22333 /* Set the cpu variant based on the command-line options. We prefer
22334 -mcpu= over -march= if both are set (as for GCC); and we prefer
22335 -mfpu= over any other way of setting the floating point unit.
22336 Use of legacy options with new options are faulted. */
22339 if (mcpu_cpu_opt || march_cpu_opt)
22340 as_bad (_("use of old and new-style options to set CPU type"));
22342 mcpu_cpu_opt = legacy_cpu;
22344 else if (!mcpu_cpu_opt)
22345 mcpu_cpu_opt = march_cpu_opt;
22350 as_bad (_("use of old and new-style options to set FPU type"));
22352 mfpu_opt = legacy_fpu;
22354 else if (!mfpu_opt)
22356 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22357 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22358 /* Some environments specify a default FPU. If they don't, infer it
22359 from the processor. */
22361 mfpu_opt = mcpu_fpu_opt;
22363 mfpu_opt = march_fpu_opt;
22365 mfpu_opt = &fpu_default;
22371 if (mcpu_cpu_opt != NULL)
22372 mfpu_opt = &fpu_default;
22373 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22374 mfpu_opt = &fpu_arch_vfp_v2;
22376 mfpu_opt = &fpu_arch_fpa;
22382 mcpu_cpu_opt = &cpu_default;
22383 selected_cpu = cpu_default;
22387 selected_cpu = *mcpu_cpu_opt;
22389 mcpu_cpu_opt = &arm_arch_any;
22392 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22394 autoselect_thumb_from_cpu_variant ();
22396 arm_arch_used = thumb_arch_used = arm_arch_none;
22398 #if defined OBJ_COFF || defined OBJ_ELF
22400 unsigned int flags = 0;
22402 #if defined OBJ_ELF
22403 flags = meabi_flags;
22405 switch (meabi_flags)
22407 case EF_ARM_EABI_UNKNOWN:
22409 /* Set the flags in the private structure. */
22410 if (uses_apcs_26) flags |= F_APCS26;
22411 if (support_interwork) flags |= F_INTERWORK;
22412 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22413 if (pic_code) flags |= F_PIC;
22414 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22415 flags |= F_SOFT_FLOAT;
22417 switch (mfloat_abi_opt)
22419 case ARM_FLOAT_ABI_SOFT:
22420 case ARM_FLOAT_ABI_SOFTFP:
22421 flags |= F_SOFT_FLOAT;
22424 case ARM_FLOAT_ABI_HARD:
22425 if (flags & F_SOFT_FLOAT)
22426 as_bad (_("hard-float conflicts with specified fpu"));
22430 /* Using pure-endian doubles (even if soft-float). */
22431 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22432 flags |= F_VFP_FLOAT;
22434 #if defined OBJ_ELF
22435 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22436 flags |= EF_ARM_MAVERICK_FLOAT;
22439 case EF_ARM_EABI_VER4:
22440 case EF_ARM_EABI_VER5:
22441 /* No additional flags to set. */
22448 bfd_set_private_flags (stdoutput, flags);
22450 /* We have run out flags in the COFF header to encode the
22451 status of ATPCS support, so instead we create a dummy,
22452 empty, debug section called .arm.atpcs. */
22457 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22461 bfd_set_section_flags
22462 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22463 bfd_set_section_size (stdoutput, sec, 0);
22464 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22470 /* Record the CPU type as well. */
22471 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22472 mach = bfd_mach_arm_iWMMXt2;
22473 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22474 mach = bfd_mach_arm_iWMMXt;
22475 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22476 mach = bfd_mach_arm_XScale;
22477 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22478 mach = bfd_mach_arm_ep9312;
22479 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22480 mach = bfd_mach_arm_5TE;
22481 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22483 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22484 mach = bfd_mach_arm_5T;
22486 mach = bfd_mach_arm_5;
22488 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22490 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22491 mach = bfd_mach_arm_4T;
22493 mach = bfd_mach_arm_4;
22495 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22496 mach = bfd_mach_arm_3M;
22497 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22498 mach = bfd_mach_arm_3;
22499 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22500 mach = bfd_mach_arm_2a;
22501 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22502 mach = bfd_mach_arm_2;
22504 mach = bfd_mach_arm_unknown;
22506 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22509 /* Command line processing. */
22512 Invocation line includes a switch not recognized by the base assembler.
22513 See if it's a processor-specific option.
22515 This routine is somewhat complicated by the need for backwards
22516 compatibility (since older releases of gcc can't be changed).
22517 The new options try to make the interface as compatible as
22520 New options (supported) are:
22522 -mcpu=<cpu name> Assemble for selected processor
22523 -march=<architecture name> Assemble for selected architecture
22524 -mfpu=<fpu architecture> Assemble for selected FPU.
22525 -EB/-mbig-endian Big-endian
22526 -EL/-mlittle-endian Little-endian
22527 -k Generate PIC code
22528 -mthumb Start in Thumb mode
22529 -mthumb-interwork Code supports ARM/Thumb interworking
22531 -m[no-]warn-deprecated Warn about deprecated features
22533 For now we will also provide support for:
22535 -mapcs-32 32-bit Program counter
22536 -mapcs-26 26-bit Program counter
22537 -macps-float Floats passed in FP registers
22538 -mapcs-reentrant Reentrant code
22540 (sometime these will probably be replaced with -mapcs=<list of options>
22541 and -matpcs=<list of options>)
22543 The remaining options are only supported for back-wards compatibility.
22544 Cpu variants, the arm part is optional:
22545 -m[arm]1 Currently not supported.
22546 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22547 -m[arm]3 Arm 3 processor
22548 -m[arm]6[xx], Arm 6 processors
22549 -m[arm]7[xx][t][[d]m] Arm 7 processors
22550 -m[arm]8[10] Arm 8 processors
22551 -m[arm]9[20][tdmi] Arm 9 processors
22552 -mstrongarm[110[0]] StrongARM processors
22553 -mxscale XScale processors
22554 -m[arm]v[2345[t[e]]] Arm architectures
22555 -mall All (except the ARM1)
22557 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22558 -mfpe-old (No float load/store multiples)
22559 -mvfpxd VFP Single precision
22561 -mno-fpu Disable all floating point instructions
22563 The following CPU names are recognized:
22564 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22565 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22566 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22567 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22568 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22569 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22570 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22574 const char * md_shortopts = "m:k";
22576 #ifdef ARM_BI_ENDIAN
22577 #define OPTION_EB (OPTION_MD_BASE + 0)
22578 #define OPTION_EL (OPTION_MD_BASE + 1)
22580 #if TARGET_BYTES_BIG_ENDIAN
22581 #define OPTION_EB (OPTION_MD_BASE + 0)
22583 #define OPTION_EL (OPTION_MD_BASE + 1)
22586 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22588 struct option md_longopts[] =
22591 {"EB", no_argument, NULL, OPTION_EB},
22594 {"EL", no_argument, NULL, OPTION_EL},
22596 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22597 {NULL, no_argument, NULL, 0}
22600 size_t md_longopts_size = sizeof (md_longopts);
22602 struct arm_option_table
22604 char *option; /* Option name to match. */
22605 char *help; /* Help information. */
22606 int *var; /* Variable to change. */
22607 int value; /* What to change it to. */
22608 char *deprecated; /* If non-null, print this message. */
22611 struct arm_option_table arm_opts[] =
22613 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22614 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22615 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22616 &support_interwork, 1, NULL},
22617 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22618 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22619 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22621 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22622 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22623 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22624 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22627 /* These are recognized by the assembler, but have no affect on code. */
22628 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22629 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22631 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22632 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22633 &warn_on_deprecated, 0, NULL},
22634 {NULL, NULL, NULL, 0, NULL}
22637 struct arm_legacy_option_table
22639 char *option; /* Option name to match. */
22640 const arm_feature_set **var; /* Variable to change. */
22641 const arm_feature_set value; /* What to change it to. */
22642 char *deprecated; /* If non-null, print this message. */
22645 const struct arm_legacy_option_table arm_legacy_opts[] =
22647 /* DON'T add any new processors to this list -- we want the whole list
22648 to go away... Add them to the processors table instead. */
22649 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22650 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22651 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22652 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22653 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22654 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22655 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22656 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22657 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22658 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22659 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22660 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22661 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22662 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22663 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22664 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22665 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22666 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22667 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22668 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22669 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22670 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22671 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22672 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22673 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22674 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22675 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22676 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22677 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22678 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22679 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22680 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22681 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22682 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22683 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22684 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22685 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22686 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22687 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22688 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22689 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22690 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22691 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22692 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22693 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22694 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22695 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22696 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22697 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22698 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22699 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22700 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22701 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22702 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22703 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22704 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22705 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22706 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22707 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22708 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22709 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22710 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22711 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22712 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22713 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22714 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22715 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22716 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22717 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22718 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22719 N_("use -mcpu=strongarm110")},
22720 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22721 N_("use -mcpu=strongarm1100")},
22722 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22723 N_("use -mcpu=strongarm1110")},
22724 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22725 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22726 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22728 /* Architecture variants -- don't add any more to this list either. */
22729 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22730 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22731 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22732 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22733 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22734 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22735 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22736 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22737 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22738 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22739 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22740 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22741 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22742 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22743 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22744 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22745 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22746 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22748 /* Floating point variants -- don't add any more to this list either. */
22749 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22750 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22751 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22752 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22753 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22755 {NULL, NULL, ARM_ARCH_NONE, NULL}
22758 struct arm_cpu_option_table
22761 const arm_feature_set value;
22762 /* For some CPUs we assume an FPU unless the user explicitly sets
22764 const arm_feature_set default_fpu;
22765 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22767 const char *canonical_name;
22770 /* This list should, at a minimum, contain all the cpu names
22771 recognized by GCC. */
22772 static const struct arm_cpu_option_table arm_cpus[] =
22774 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22775 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22776 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22777 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22778 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22779 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22780 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22781 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22782 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22783 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22784 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22785 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22786 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22787 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22788 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22789 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22790 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22791 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22792 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22793 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22794 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22795 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22796 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22797 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22798 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22799 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22800 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22801 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22802 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22803 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22804 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22805 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22806 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22807 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22808 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22809 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22810 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22811 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22812 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22813 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22814 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22815 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22816 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22817 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22818 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22819 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22820 /* For V5 or later processors we default to using VFP; but the user
22821 should really set the FPU type explicitly. */
22822 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22823 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22824 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22825 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22826 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22827 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22828 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22829 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22830 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22831 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22832 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22833 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22834 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22835 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22836 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22837 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22838 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22839 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22840 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22841 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22842 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22843 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22844 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22845 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22846 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22847 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22848 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22849 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22850 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22851 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22852 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22853 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22854 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22855 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22856 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22857 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22858 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22859 FPU_NONE, "Cortex-A5"},
22860 {"cortex-a8", ARM_ARCH_V7A_SEC,
22861 ARM_FEATURE (0, FPU_VFP_V3
22862 | FPU_NEON_EXT_V1),
22864 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22865 ARM_FEATURE (0, FPU_VFP_V3
22866 | FPU_NEON_EXT_V1),
22868 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22869 FPU_ARCH_NEON_VFP_V4,
22871 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22872 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22874 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22875 FPU_NONE, "Cortex-R5"},
22876 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22877 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22878 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22879 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22880 /* ??? XSCALE is really an architecture. */
22881 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22882 /* ??? iwmmxt is not a processor. */
22883 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
22884 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
22885 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22887 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
22888 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
22891 struct arm_arch_option_table
22894 const arm_feature_set value;
22895 const arm_feature_set default_fpu;
22898 /* This list should, at a minimum, contain all the architecture names
22899 recognized by GCC. */
22900 static const struct arm_arch_option_table arm_archs[] =
22902 {"all", ARM_ANY, FPU_ARCH_FPA},
22903 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
22904 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
22905 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
22906 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
22907 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
22908 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
22909 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
22910 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
22911 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
22912 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
22913 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
22914 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
22915 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
22916 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
22917 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
22918 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
22919 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
22920 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
22921 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
22922 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
22923 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
22924 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
22925 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
22926 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
22927 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
22928 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
22929 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
22930 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
22931 /* The official spelling of the ARMv7 profile variants is the dashed form.
22932 Accept the non-dashed form for compatibility with old toolchains. */
22933 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22934 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22935 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
22936 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22937 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22938 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
22939 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
22940 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
22941 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
22942 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
22943 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
22946 /* ISA extensions in the co-processor and main instruction set space. */
22947 struct arm_option_extension_value_table
22950 const arm_feature_set value;
22951 const arm_feature_set allowed_archs;
22954 /* The following table must be in alphabetical order with a NULL last entry.
22956 static const struct arm_option_extension_value_table arm_extensions[] =
22958 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
22959 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
22960 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
22961 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
22962 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
22963 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
22964 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
22965 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
22966 ARM_FEATURE (ARM_EXT_V6M, 0)},
22967 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
22968 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
22969 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
22970 ARM_FEATURE (ARM_EXT_V7A, 0)},
22971 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
22972 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
22975 /* ISA floating-point and Advanced SIMD extensions. */
22976 struct arm_option_fpu_value_table
22979 const arm_feature_set value;
22982 /* This list should, at a minimum, contain all the fpu names
22983 recognized by GCC. */
22984 static const struct arm_option_fpu_value_table arm_fpus[] =
22986 {"softfpa", FPU_NONE},
22987 {"fpe", FPU_ARCH_FPE},
22988 {"fpe2", FPU_ARCH_FPE},
22989 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
22990 {"fpa", FPU_ARCH_FPA},
22991 {"fpa10", FPU_ARCH_FPA},
22992 {"fpa11", FPU_ARCH_FPA},
22993 {"arm7500fe", FPU_ARCH_FPA},
22994 {"softvfp", FPU_ARCH_VFP},
22995 {"softvfp+vfp", FPU_ARCH_VFP_V2},
22996 {"vfp", FPU_ARCH_VFP_V2},
22997 {"vfp9", FPU_ARCH_VFP_V2},
22998 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
22999 {"vfp10", FPU_ARCH_VFP_V2},
23000 {"vfp10-r0", FPU_ARCH_VFP_V1},
23001 {"vfpxd", FPU_ARCH_VFP_V1xD},
23002 {"vfpv2", FPU_ARCH_VFP_V2},
23003 {"vfpv3", FPU_ARCH_VFP_V3},
23004 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23005 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23006 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23007 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23008 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23009 {"arm1020t", FPU_ARCH_VFP_V1},
23010 {"arm1020e", FPU_ARCH_VFP_V2},
23011 {"arm1136jfs", FPU_ARCH_VFP_V2},
23012 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23013 {"maverick", FPU_ARCH_MAVERICK},
23014 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23015 {"neon-fp16", FPU_ARCH_NEON_FP16},
23016 {"vfpv4", FPU_ARCH_VFP_V4},
23017 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23018 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23019 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23020 {NULL, ARM_ARCH_NONE}
23023 struct arm_option_value_table
23029 static const struct arm_option_value_table arm_float_abis[] =
23031 {"hard", ARM_FLOAT_ABI_HARD},
23032 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23033 {"soft", ARM_FLOAT_ABI_SOFT},
23038 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23039 static const struct arm_option_value_table arm_eabis[] =
23041 {"gnu", EF_ARM_EABI_UNKNOWN},
23042 {"4", EF_ARM_EABI_VER4},
23043 {"5", EF_ARM_EABI_VER5},
23048 struct arm_long_option_table
23050 char * option; /* Substring to match. */
23051 char * help; /* Help information. */
23052 int (* func) (char * subopt); /* Function to decode sub-option. */
23053 char * deprecated; /* If non-null, print this message. */
23057 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23059 arm_feature_set *ext_set = (arm_feature_set *)
23060 xmalloc (sizeof (arm_feature_set));
23062 /* We insist on extensions being specified in alphabetical order, and with
23063 extensions being added before being removed. We achieve this by having
23064 the global ARM_EXTENSIONS table in alphabetical order, and using the
23065 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23066 or removing it (0) and only allowing it to change in the order
23068 const struct arm_option_extension_value_table * opt = NULL;
23069 int adding_value = -1;
23071 /* Copy the feature set, so that we can modify it. */
23072 *ext_set = **opt_p;
23075 while (str != NULL && *str != 0)
23082 as_bad (_("invalid architectural extension"));
23087 ext = strchr (str, '+');
23090 optlen = ext - str;
23092 optlen = strlen (str);
23095 && strncmp (str, "no", 2) == 0)
23097 if (adding_value != 0)
23100 opt = arm_extensions;
23106 else if (optlen > 0)
23108 if (adding_value == -1)
23111 opt = arm_extensions;
23113 else if (adding_value != 1)
23115 as_bad (_("must specify extensions to add before specifying "
23116 "those to remove"));
23123 as_bad (_("missing architectural extension"));
23127 gas_assert (adding_value != -1);
23128 gas_assert (opt != NULL);
23130 /* Scan over the options table trying to find an exact match. */
23131 for (; opt->name != NULL; opt++)
23132 if (strncmp (opt->name, str, optlen) == 0
23133 && strlen (opt->name) == optlen)
23135 /* Check we can apply the extension to this architecture. */
23136 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23138 as_bad (_("extension does not apply to the base architecture"));
23142 /* Add or remove the extension. */
23144 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23146 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23151 if (opt->name == NULL)
23153 /* Did we fail to find an extension because it wasn't specified in
23154 alphabetical order, or because it does not exist? */
23156 for (opt = arm_extensions; opt->name != NULL; opt++)
23157 if (strncmp (opt->name, str, optlen) == 0)
23160 if (opt->name == NULL)
23161 as_bad (_("unknown architectural extension `%s'"), str);
23163 as_bad (_("architectural extensions must be specified in "
23164 "alphabetical order"));
23170 /* We should skip the extension we've just matched the next time
23182 arm_parse_cpu (char * str)
23184 const struct arm_cpu_option_table * opt;
23185 char * ext = strchr (str, '+');
23189 optlen = ext - str;
23191 optlen = strlen (str);
23195 as_bad (_("missing cpu name `%s'"), str);
23199 for (opt = arm_cpus; opt->name != NULL; opt++)
23200 if (strncmp (opt->name, str, optlen) == 0)
23202 mcpu_cpu_opt = &opt->value;
23203 mcpu_fpu_opt = &opt->default_fpu;
23204 if (opt->canonical_name)
23205 strcpy (selected_cpu_name, opt->canonical_name);
23210 for (i = 0; i < optlen; i++)
23211 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23212 selected_cpu_name[i] = 0;
23216 return arm_parse_extension (ext, &mcpu_cpu_opt);
23221 as_bad (_("unknown cpu `%s'"), str);
23226 arm_parse_arch (char * str)
23228 const struct arm_arch_option_table *opt;
23229 char *ext = strchr (str, '+');
23233 optlen = ext - str;
23235 optlen = strlen (str);
23239 as_bad (_("missing architecture name `%s'"), str);
23243 for (opt = arm_archs; opt->name != NULL; opt++)
23244 if (strncmp (opt->name, str, optlen) == 0)
23246 march_cpu_opt = &opt->value;
23247 march_fpu_opt = &opt->default_fpu;
23248 strcpy (selected_cpu_name, opt->name);
23251 return arm_parse_extension (ext, &march_cpu_opt);
23256 as_bad (_("unknown architecture `%s'\n"), str);
23261 arm_parse_fpu (char * str)
23263 const struct arm_option_fpu_value_table * opt;
23265 for (opt = arm_fpus; opt->name != NULL; opt++)
23266 if (streq (opt->name, str))
23268 mfpu_opt = &opt->value;
23272 as_bad (_("unknown floating point format `%s'\n"), str);
23277 arm_parse_float_abi (char * str)
23279 const struct arm_option_value_table * opt;
23281 for (opt = arm_float_abis; opt->name != NULL; opt++)
23282 if (streq (opt->name, str))
23284 mfloat_abi_opt = opt->value;
23288 as_bad (_("unknown floating point abi `%s'\n"), str);
23294 arm_parse_eabi (char * str)
23296 const struct arm_option_value_table *opt;
23298 for (opt = arm_eabis; opt->name != NULL; opt++)
23299 if (streq (opt->name, str))
23301 meabi_flags = opt->value;
23304 as_bad (_("unknown EABI `%s'\n"), str);
23310 arm_parse_it_mode (char * str)
23312 bfd_boolean ret = TRUE;
23314 if (streq ("arm", str))
23315 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23316 else if (streq ("thumb", str))
23317 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23318 else if (streq ("always", str))
23319 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23320 else if (streq ("never", str))
23321 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23324 as_bad (_("unknown implicit IT mode `%s', should be "\
23325 "arm, thumb, always, or never."), str);
23332 struct arm_long_option_table arm_long_opts[] =
23334 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23335 arm_parse_cpu, NULL},
23336 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23337 arm_parse_arch, NULL},
23338 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23339 arm_parse_fpu, NULL},
23340 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23341 arm_parse_float_abi, NULL},
23343 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23344 arm_parse_eabi, NULL},
23346 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23347 arm_parse_it_mode, NULL},
23348 {NULL, NULL, 0, NULL}
23352 md_parse_option (int c, char * arg)
23354 struct arm_option_table *opt;
23355 const struct arm_legacy_option_table *fopt;
23356 struct arm_long_option_table *lopt;
23362 target_big_endian = 1;
23368 target_big_endian = 0;
23372 case OPTION_FIX_V4BX:
23377 /* Listing option. Just ignore these, we don't support additional
23382 for (opt = arm_opts; opt->option != NULL; opt++)
23384 if (c == opt->option[0]
23385 && ((arg == NULL && opt->option[1] == 0)
23386 || streq (arg, opt->option + 1)))
23388 /* If the option is deprecated, tell the user. */
23389 if (warn_on_deprecated && opt->deprecated != NULL)
23390 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23391 arg ? arg : "", _(opt->deprecated));
23393 if (opt->var != NULL)
23394 *opt->var = opt->value;
23400 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23402 if (c == fopt->option[0]
23403 && ((arg == NULL && fopt->option[1] == 0)
23404 || streq (arg, fopt->option + 1)))
23406 /* If the option is deprecated, tell the user. */
23407 if (warn_on_deprecated && fopt->deprecated != NULL)
23408 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23409 arg ? arg : "", _(fopt->deprecated));
23411 if (fopt->var != NULL)
23412 *fopt->var = &fopt->value;
23418 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23420 /* These options are expected to have an argument. */
23421 if (c == lopt->option[0]
23423 && strncmp (arg, lopt->option + 1,
23424 strlen (lopt->option + 1)) == 0)
23426 /* If the option is deprecated, tell the user. */
23427 if (warn_on_deprecated && lopt->deprecated != NULL)
23428 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23429 _(lopt->deprecated));
23431 /* Call the sup-option parser. */
23432 return lopt->func (arg + strlen (lopt->option) - 1);
23443 md_show_usage (FILE * fp)
23445 struct arm_option_table *opt;
23446 struct arm_long_option_table *lopt;
23448 fprintf (fp, _(" ARM-specific assembler options:\n"));
23450 for (opt = arm_opts; opt->option != NULL; opt++)
23451 if (opt->help != NULL)
23452 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23454 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23455 if (lopt->help != NULL)
23456 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23460 -EB assemble code for a big-endian cpu\n"));
23465 -EL assemble code for a little-endian cpu\n"));
23469 --fix-v4bx Allow BX in ARMv4 code\n"));
23477 arm_feature_set flags;
23478 } cpu_arch_ver_table;
23480 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23481 least features first. */
23482 static const cpu_arch_ver_table cpu_arch_ver[] =
23488 {4, ARM_ARCH_V5TE},
23489 {5, ARM_ARCH_V5TEJ},
23493 {11, ARM_ARCH_V6M},
23494 {12, ARM_ARCH_V6SM},
23495 {8, ARM_ARCH_V6T2},
23496 {10, ARM_ARCH_V7A},
23497 {10, ARM_ARCH_V7R},
23498 {10, ARM_ARCH_V7M},
23502 /* Set an attribute if it has not already been set by the user. */
23504 aeabi_set_attribute_int (int tag, int value)
23507 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23508 || !attributes_set_explicitly[tag])
23509 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23513 aeabi_set_attribute_string (int tag, const char *value)
23516 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23517 || !attributes_set_explicitly[tag])
23518 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23521 /* Set the public EABI object attributes. */
23523 aeabi_set_public_attributes (void)
23527 arm_feature_set flags;
23528 arm_feature_set tmp;
23529 const cpu_arch_ver_table *p;
23531 /* Choose the architecture based on the capabilities of the requested cpu
23532 (if any) and/or the instructions actually used. */
23533 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23534 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23535 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23536 /*Allow the user to override the reported architecture. */
23539 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23540 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23543 /* We need to make sure that the attributes do not identify us as v6S-M
23544 when the only v6S-M feature in use is the Operating System Extensions. */
23545 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23546 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23547 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23551 for (p = cpu_arch_ver; p->val; p++)
23553 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23556 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23560 /* The table lookup above finds the last architecture to contribute
23561 a new feature. Unfortunately, Tag13 is a subset of the union of
23562 v6T2 and v7-M, so it is never seen as contributing a new feature.
23563 We can not search for the last entry which is entirely used,
23564 because if no CPU is specified we build up only those flags
23565 actually used. Perhaps we should separate out the specified
23566 and implicit cases. Avoid taking this path for -march=all by
23567 checking for contradictory v7-A / v7-M features. */
23569 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23570 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23571 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23574 /* Tag_CPU_name. */
23575 if (selected_cpu_name[0])
23579 q = selected_cpu_name;
23580 if (strncmp (q, "armv", 4) == 0)
23585 for (i = 0; q[i]; i++)
23586 q[i] = TOUPPER (q[i]);
23588 aeabi_set_attribute_string (Tag_CPU_name, q);
23591 /* Tag_CPU_arch. */
23592 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23594 /* Tag_CPU_arch_profile. */
23595 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23596 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23597 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23598 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23599 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23600 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23602 /* Tag_ARM_ISA_use. */
23603 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23605 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23607 /* Tag_THUMB_ISA_use. */
23608 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23610 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23611 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23613 /* Tag_VFP_arch. */
23614 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23615 aeabi_set_attribute_int (Tag_VFP_arch,
23616 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23618 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23619 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23620 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23621 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23622 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23623 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23624 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23625 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23626 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23628 /* Tag_ABI_HardFP_use. */
23629 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23630 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23631 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23633 /* Tag_WMMX_arch. */
23634 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23635 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23636 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23637 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23639 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23640 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23641 aeabi_set_attribute_int
23642 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23645 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23646 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23647 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23650 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23651 aeabi_set_attribute_int (Tag_DIV_use, 2);
23652 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23653 aeabi_set_attribute_int (Tag_DIV_use, 0);
23655 aeabi_set_attribute_int (Tag_DIV_use, 1);
23657 /* Tag_MP_extension_use. */
23658 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23659 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23661 /* Tag Virtualization_use. */
23662 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23664 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23667 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23670 /* Add the default contents for the .ARM.attributes section. */
23674 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23677 aeabi_set_public_attributes ();
23679 #endif /* OBJ_ELF */
23682 /* Parse a .cpu directive. */
23685 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23687 const struct arm_cpu_option_table *opt;
23691 name = input_line_pointer;
23692 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23693 input_line_pointer++;
23694 saved_char = *input_line_pointer;
23695 *input_line_pointer = 0;
23697 /* Skip the first "all" entry. */
23698 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23699 if (streq (opt->name, name))
23701 mcpu_cpu_opt = &opt->value;
23702 selected_cpu = opt->value;
23703 if (opt->canonical_name)
23704 strcpy (selected_cpu_name, opt->canonical_name);
23708 for (i = 0; opt->name[i]; i++)
23709 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23710 selected_cpu_name[i] = 0;
23712 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23713 *input_line_pointer = saved_char;
23714 demand_empty_rest_of_line ();
23717 as_bad (_("unknown cpu `%s'"), name);
23718 *input_line_pointer = saved_char;
23719 ignore_rest_of_line ();
23723 /* Parse a .arch directive. */
23726 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23728 const struct arm_arch_option_table *opt;
23732 name = input_line_pointer;
23733 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23734 input_line_pointer++;
23735 saved_char = *input_line_pointer;
23736 *input_line_pointer = 0;
23738 /* Skip the first "all" entry. */
23739 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23740 if (streq (opt->name, name))
23742 mcpu_cpu_opt = &opt->value;
23743 selected_cpu = opt->value;
23744 strcpy (selected_cpu_name, opt->name);
23745 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23746 *input_line_pointer = saved_char;
23747 demand_empty_rest_of_line ();
23751 as_bad (_("unknown architecture `%s'\n"), name);
23752 *input_line_pointer = saved_char;
23753 ignore_rest_of_line ();
23757 /* Parse a .object_arch directive. */
23760 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23762 const struct arm_arch_option_table *opt;
23766 name = input_line_pointer;
23767 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23768 input_line_pointer++;
23769 saved_char = *input_line_pointer;
23770 *input_line_pointer = 0;
23772 /* Skip the first "all" entry. */
23773 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23774 if (streq (opt->name, name))
23776 object_arch = &opt->value;
23777 *input_line_pointer = saved_char;
23778 demand_empty_rest_of_line ();
23782 as_bad (_("unknown architecture `%s'\n"), name);
23783 *input_line_pointer = saved_char;
23784 ignore_rest_of_line ();
23787 /* Parse a .arch_extension directive. */
23790 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23792 const struct arm_option_extension_value_table *opt;
23795 int adding_value = 1;
23797 name = input_line_pointer;
23798 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23799 input_line_pointer++;
23800 saved_char = *input_line_pointer;
23801 *input_line_pointer = 0;
23803 if (strlen (name) >= 2
23804 && strncmp (name, "no", 2) == 0)
23810 for (opt = arm_extensions; opt->name != NULL; opt++)
23811 if (streq (opt->name, name))
23813 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23815 as_bad (_("architectural extension `%s' is not allowed for the "
23816 "current base architecture"), name);
23821 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23823 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23825 mcpu_cpu_opt = &selected_cpu;
23826 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23827 *input_line_pointer = saved_char;
23828 demand_empty_rest_of_line ();
23832 if (opt->name == NULL)
23833 as_bad (_("unknown architecture `%s'\n"), name);
23835 *input_line_pointer = saved_char;
23836 ignore_rest_of_line ();
23839 /* Parse a .fpu directive. */
23842 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23844 const struct arm_option_fpu_value_table *opt;
23848 name = input_line_pointer;
23849 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23850 input_line_pointer++;
23851 saved_char = *input_line_pointer;
23852 *input_line_pointer = 0;
23854 for (opt = arm_fpus; opt->name != NULL; opt++)
23855 if (streq (opt->name, name))
23857 mfpu_opt = &opt->value;
23858 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23859 *input_line_pointer = saved_char;
23860 demand_empty_rest_of_line ();
23864 as_bad (_("unknown floating point format `%s'\n"), name);
23865 *input_line_pointer = saved_char;
23866 ignore_rest_of_line ();
23869 /* Copy symbol information. */
23872 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23874 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23878 /* Given a symbolic attribute NAME, return the proper integer value.
23879 Returns -1 if the attribute is not known. */
23882 arm_convert_symbolic_attribute (const char *name)
23884 static const struct
23889 attribute_table[] =
23891 /* When you modify this table you should
23892 also modify the list in doc/c-arm.texi. */
23893 #define T(tag) {#tag, tag}
23894 T (Tag_CPU_raw_name),
23897 T (Tag_CPU_arch_profile),
23898 T (Tag_ARM_ISA_use),
23899 T (Tag_THUMB_ISA_use),
23903 T (Tag_Advanced_SIMD_arch),
23904 T (Tag_PCS_config),
23905 T (Tag_ABI_PCS_R9_use),
23906 T (Tag_ABI_PCS_RW_data),
23907 T (Tag_ABI_PCS_RO_data),
23908 T (Tag_ABI_PCS_GOT_use),
23909 T (Tag_ABI_PCS_wchar_t),
23910 T (Tag_ABI_FP_rounding),
23911 T (Tag_ABI_FP_denormal),
23912 T (Tag_ABI_FP_exceptions),
23913 T (Tag_ABI_FP_user_exceptions),
23914 T (Tag_ABI_FP_number_model),
23915 T (Tag_ABI_align_needed),
23916 T (Tag_ABI_align8_needed),
23917 T (Tag_ABI_align_preserved),
23918 T (Tag_ABI_align8_preserved),
23919 T (Tag_ABI_enum_size),
23920 T (Tag_ABI_HardFP_use),
23921 T (Tag_ABI_VFP_args),
23922 T (Tag_ABI_WMMX_args),
23923 T (Tag_ABI_optimization_goals),
23924 T (Tag_ABI_FP_optimization_goals),
23925 T (Tag_compatibility),
23926 T (Tag_CPU_unaligned_access),
23927 T (Tag_FP_HP_extension),
23928 T (Tag_VFP_HP_extension),
23929 T (Tag_ABI_FP_16bit_format),
23930 T (Tag_MPextension_use),
23932 T (Tag_nodefaults),
23933 T (Tag_also_compatible_with),
23934 T (Tag_conformance),
23936 T (Tag_Virtualization_use),
23937 /* We deliberately do not include Tag_MPextension_use_legacy. */
23945 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
23946 if (streq (name, attribute_table[i].name))
23947 return attribute_table[i].tag;
23953 /* Apply sym value for relocations only in the case that
23954 they are for local symbols and you have the respective
23955 architectural feature for blx and simple switches. */
23957 arm_apply_sym_value (struct fix * fixP)
23960 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23961 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
23963 switch (fixP->fx_r_type)
23965 case BFD_RELOC_ARM_PCREL_BLX:
23966 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23967 if (ARM_IS_FUNC (fixP->fx_addsy))
23971 case BFD_RELOC_ARM_PCREL_CALL:
23972 case BFD_RELOC_THUMB_PCREL_BLX:
23973 if (THUMB_IS_FUNC (fixP->fx_addsy))
23984 #endif /* OBJ_ELF */