1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
727 #define BAD_RANGE _("branch out of range")
729 static struct hash_control * arm_ops_hsh;
730 static struct hash_control * arm_cond_hsh;
731 static struct hash_control * arm_shift_hsh;
732 static struct hash_control * arm_psr_hsh;
733 static struct hash_control * arm_v7m_psr_hsh;
734 static struct hash_control * arm_reg_hsh;
735 static struct hash_control * arm_reloc_hsh;
736 static struct hash_control * arm_barrier_opt_hsh;
738 /* Stuff needed to resolve the label ambiguity
747 symbolS * last_label_seen;
748 static int label_is_thumb_function_name = FALSE;
750 /* Literal pool structure. Held on a per-section
751 and per-sub-section basis. */
753 #define MAX_LITERAL_POOL_SIZE 1024
754 typedef struct literal_pool
756 expressionS literals [MAX_LITERAL_POOL_SIZE];
757 unsigned int next_free_entry;
763 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
765 struct literal_pool * next;
768 /* Pointer to a linked list of literal pools. */
769 literal_pool * list_of_pools = NULL;
772 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
774 static struct current_it now_it;
778 now_it_compatible (int cond)
780 return (cond & ~1) == (now_it.cc & ~1);
784 conditional_insn (void)
786 return inst.cond != COND_ALWAYS;
789 static int in_it_block (void);
791 static int handle_it_state (void);
793 static void force_automatic_it_block_close (void);
795 static void it_fsm_post_encode (void);
797 #define set_it_insn_type(type) \
800 inst.it_insn_type = type; \
801 if (handle_it_state () == FAIL) \
806 #define set_it_insn_type_nonvoid(type, failret) \
809 inst.it_insn_type = type; \
810 if (handle_it_state () == FAIL) \
815 #define set_it_insn_type_last() \
818 if (inst.cond == COND_ALWAYS) \
819 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
821 set_it_insn_type (INSIDE_IT_LAST_INSN); \
827 /* This array holds the chars that always start a comment. If the
828 pre-processor is disabled, these aren't very useful. */
829 const char comment_chars[] = "@";
831 /* This array holds the chars that only start a comment at the beginning of
832 a line. If the line seems to have the form '# 123 filename'
833 .line and .file directives will appear in the pre-processed output. */
834 /* Note that input_file.c hand checks for '#' at the beginning of the
835 first line of the input file. This is because the compiler outputs
836 #NO_APP at the beginning of its output. */
837 /* Also note that comments like this one will always work. */
838 const char line_comment_chars[] = "#";
840 const char line_separator_chars[] = ";";
842 /* Chars that can be used to separate mant
843 from exp in floating point numbers. */
844 const char EXP_CHARS[] = "eE";
846 /* Chars that mean this number is a floating point constant. */
850 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
852 /* Prefix characters that indicate the start of an immediate
854 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
856 /* Separator character handling. */
858 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
861 skip_past_char (char ** str, char c)
872 #define skip_past_comma(str) skip_past_char (str, ',')
874 /* Arithmetic expressions (possibly involving symbols). */
876 /* Return TRUE if anything in the expression is a bignum. */
879 walk_no_bignums (symbolS * sp)
881 if (symbol_get_value_expression (sp)->X_op == O_big)
884 if (symbol_get_value_expression (sp)->X_add_symbol)
886 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
887 || (symbol_get_value_expression (sp)->X_op_symbol
888 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
894 static int in_my_get_expression = 0;
896 /* Third argument to my_get_expression. */
897 #define GE_NO_PREFIX 0
898 #define GE_IMM_PREFIX 1
899 #define GE_OPT_PREFIX 2
900 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
901 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
902 #define GE_OPT_PREFIX_BIG 3
905 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
910 /* In unified syntax, all prefixes are optional. */
912 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
917 case GE_NO_PREFIX: break;
919 if (!is_immediate_prefix (**str))
921 inst.error = _("immediate expression requires a # prefix");
927 case GE_OPT_PREFIX_BIG:
928 if (is_immediate_prefix (**str))
934 memset (ep, 0, sizeof (expressionS));
936 save_in = input_line_pointer;
937 input_line_pointer = *str;
938 in_my_get_expression = 1;
939 seg = expression (ep);
940 in_my_get_expression = 0;
942 if (ep->X_op == O_illegal || ep->X_op == O_absent)
944 /* We found a bad or missing expression in md_operand(). */
945 *str = input_line_pointer;
946 input_line_pointer = save_in;
947 if (inst.error == NULL)
948 inst.error = (ep->X_op == O_absent
949 ? _("missing expression") :_("bad expression"));
954 if (seg != absolute_section
955 && seg != text_section
956 && seg != data_section
957 && seg != bss_section
958 && seg != undefined_section)
960 inst.error = _("bad segment");
961 *str = input_line_pointer;
962 input_line_pointer = save_in;
969 /* Get rid of any bignums now, so that we don't generate an error for which
970 we can't establish a line number later on. Big numbers are never valid
971 in instructions, which is where this routine is always called. */
972 if (prefix_mode != GE_OPT_PREFIX_BIG
973 && (ep->X_op == O_big
975 && (walk_no_bignums (ep->X_add_symbol)
977 && walk_no_bignums (ep->X_op_symbol))))))
979 inst.error = _("invalid constant");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
985 *str = input_line_pointer;
986 input_line_pointer = save_in;
990 /* Turn a string in input_line_pointer into a floating point constant
991 of type TYPE, and store the appropriate bytes in *LITP. The number
992 of LITTLENUMS emitted is stored in *SIZEP. An error message is
993 returned, or NULL on OK.
995 Note that fp constants aren't represent in the normal way on the ARM.
996 In big endian mode, things are as expected. However, in little endian
997 mode fp constants are big-endian word-wise, and little-endian byte-wise
998 within the words. For example, (double) 1.1 in big endian mode is
999 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1000 the byte sequence 99 99 f1 3f 9a 99 99 99.
1002 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1005 md_atof (int type, char * litP, int * sizeP)
1008 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1040 return _("Unrecognized or unsupported floating point constant");
1043 t = atof_ieee (input_line_pointer, type, words);
1045 input_line_pointer = t;
1046 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1048 if (target_big_endian)
1050 for (i = 0; i < prec; i++)
1052 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1053 litP += sizeof (LITTLENUM_TYPE);
1058 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1059 for (i = prec - 1; i >= 0; i--)
1061 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1062 litP += sizeof (LITTLENUM_TYPE);
1065 /* For a 4 byte float the order of elements in `words' is 1 0.
1066 For an 8 byte float the order is 1 0 3 2. */
1067 for (i = 0; i < prec; i += 2)
1069 md_number_to_chars (litP, (valueT) words[i + 1],
1070 sizeof (LITTLENUM_TYPE));
1071 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1072 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += 2 * sizeof (LITTLENUM_TYPE);
1080 /* We handle all bad expressions here, so that we can report the faulty
1081 instruction in the error message. */
1083 md_operand (expressionS * exp)
1085 if (in_my_get_expression)
1086 exp->X_op = O_illegal;
1089 /* Immediate values. */
1091 /* Generic immediate-value read function for use in directives.
1092 Accepts anything that 'expression' can fold to a constant.
1093 *val receives the number. */
1096 immediate_for_directive (int *val)
1099 exp.X_op = O_illegal;
1101 if (is_immediate_prefix (*input_line_pointer))
1103 input_line_pointer++;
1107 if (exp.X_op != O_constant)
1109 as_bad (_("expected #constant"));
1110 ignore_rest_of_line ();
1113 *val = exp.X_add_number;
1118 /* Register parsing. */
1120 /* Generic register parser. CCP points to what should be the
1121 beginning of a register name. If it is indeed a valid register
1122 name, advance CCP over it and return the reg_entry structure;
1123 otherwise return NULL. Does not issue diagnostics. */
1125 static struct reg_entry *
1126 arm_reg_parse_multi (char **ccp)
1130 struct reg_entry *reg;
1132 #ifdef REGISTER_PREFIX
1133 if (*start != REGISTER_PREFIX)
1137 #ifdef OPTIONAL_REGISTER_PREFIX
1138 if (*start == OPTIONAL_REGISTER_PREFIX)
1143 if (!ISALPHA (*p) || !is_name_beginner (*p))
1148 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1150 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1160 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1161 enum arm_reg_type type)
1163 /* Alternative syntaxes are accepted for a few register classes. */
1170 /* Generic coprocessor register names are allowed for these. */
1171 if (reg && reg->type == REG_TYPE_CN)
1176 /* For backward compatibility, a bare number is valid here. */
1178 unsigned long processor = strtoul (start, ccp, 10);
1179 if (*ccp != start && processor <= 15)
1183 case REG_TYPE_MMXWC:
1184 /* WC includes WCG. ??? I'm not sure this is true for all
1185 instructions that take WC registers. */
1186 if (reg && reg->type == REG_TYPE_MMXWCG)
1197 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1198 return value is the register number or FAIL. */
1201 arm_reg_parse (char **ccp, enum arm_reg_type type)
1204 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1207 /* Do not allow a scalar (reg+index) to parse as a register. */
1208 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1211 if (reg && reg->type == type)
1214 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1221 /* Parse a Neon type specifier. *STR should point at the leading '.'
1222 character. Does no verification at this stage that the type fits the opcode
1229 Can all be legally parsed by this function.
1231 Fills in neon_type struct pointer with parsed information, and updates STR
1232 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1233 type, FAIL if not. */
1236 parse_neon_type (struct neon_type *type, char **str)
1243 while (type->elems < NEON_MAX_TYPE_ELS)
1245 enum neon_el_type thistype = NT_untyped;
1246 unsigned thissize = -1u;
1253 /* Just a size without an explicit type. */
1257 switch (TOLOWER (*ptr))
1259 case 'i': thistype = NT_integer; break;
1260 case 'f': thistype = NT_float; break;
1261 case 'p': thistype = NT_poly; break;
1262 case 's': thistype = NT_signed; break;
1263 case 'u': thistype = NT_unsigned; break;
1265 thistype = NT_float;
1270 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1276 /* .f is an abbreviation for .f32. */
1277 if (thistype == NT_float && !ISDIGIT (*ptr))
1282 thissize = strtoul (ptr, &ptr, 10);
1284 if (thissize != 8 && thissize != 16 && thissize != 32
1287 as_bad (_("bad size %d in type specifier"), thissize);
1295 type->el[type->elems].type = thistype;
1296 type->el[type->elems].size = thissize;
1301 /* Empty/missing type is not a successful parse. */
1302 if (type->elems == 0)
1310 /* Errors may be set multiple times during parsing or bit encoding
1311 (particularly in the Neon bits), but usually the earliest error which is set
1312 will be the most meaningful. Avoid overwriting it with later (cascading)
1313 errors by calling this function. */
1316 first_error (const char *err)
1322 /* Parse a single type, e.g. ".s32", leading period included. */
1324 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1327 struct neon_type optype;
1331 if (parse_neon_type (&optype, &str) == SUCCESS)
1333 if (optype.elems == 1)
1334 *vectype = optype.el[0];
1337 first_error (_("only one type should be specified for operand"));
1343 first_error (_("vector type expected"));
1355 /* Special meanings for indices (which have a range of 0-7), which will fit into
1358 #define NEON_ALL_LANES 15
1359 #define NEON_INTERLEAVE_LANES 14
1361 /* Parse either a register or a scalar, with an optional type. Return the
1362 register number, and optionally fill in the actual type of the register
1363 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1364 type/index information in *TYPEINFO. */
1367 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1368 enum arm_reg_type *rtype,
1369 struct neon_typed_alias *typeinfo)
1372 struct reg_entry *reg = arm_reg_parse_multi (&str);
1373 struct neon_typed_alias atype;
1374 struct neon_type_el parsetype;
1378 atype.eltype.type = NT_invtype;
1379 atype.eltype.size = -1;
1381 /* Try alternate syntax for some types of register. Note these are mutually
1382 exclusive with the Neon syntax extensions. */
1385 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1393 /* Undo polymorphism when a set of register types may be accepted. */
1394 if ((type == REG_TYPE_NDQ
1395 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1396 || (type == REG_TYPE_VFSD
1397 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1398 || (type == REG_TYPE_NSDQ
1399 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1400 || reg->type == REG_TYPE_NQ))
1401 || (type == REG_TYPE_MMXWC
1402 && (reg->type == REG_TYPE_MMXWCG)))
1403 type = (enum arm_reg_type) reg->type;
1405 if (type != reg->type)
1411 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1413 if ((atype.defined & NTA_HASTYPE) != 0)
1415 first_error (_("can't redefine type for operand"));
1418 atype.defined |= NTA_HASTYPE;
1419 atype.eltype = parsetype;
1422 if (skip_past_char (&str, '[') == SUCCESS)
1424 if (type != REG_TYPE_VFD)
1426 first_error (_("only D registers may be indexed"));
1430 if ((atype.defined & NTA_HASINDEX) != 0)
1432 first_error (_("can't change index for operand"));
1436 atype.defined |= NTA_HASINDEX;
1438 if (skip_past_char (&str, ']') == SUCCESS)
1439 atype.index = NEON_ALL_LANES;
1444 my_get_expression (&exp, &str, GE_NO_PREFIX);
1446 if (exp.X_op != O_constant)
1448 first_error (_("constant expression required"));
1452 if (skip_past_char (&str, ']') == FAIL)
1455 atype.index = exp.X_add_number;
1470 /* Like arm_reg_parse, but allow allow the following extra features:
1471 - If RTYPE is non-zero, return the (possibly restricted) type of the
1472 register (e.g. Neon double or quad reg when either has been requested).
1473 - If this is a Neon vector type with additional type information, fill
1474 in the struct pointed to by VECTYPE (if non-NULL).
1475 This function will fault on encountering a scalar. */
1478 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1479 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1481 struct neon_typed_alias atype;
1483 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1488 /* Do not allow regname(... to parse as a register. */
1492 /* Do not allow a scalar (reg+index) to parse as a register. */
1493 if ((atype.defined & NTA_HASINDEX) != 0)
1495 first_error (_("register operand expected, but got scalar"));
1500 *vectype = atype.eltype;
1507 #define NEON_SCALAR_REG(X) ((X) >> 4)
1508 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1510 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1511 have enough information to be able to do a good job bounds-checking. So, we
1512 just do easy checks here, and do further checks later. */
1515 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1519 struct neon_typed_alias atype;
1521 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1523 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1526 if (atype.index == NEON_ALL_LANES)
1528 first_error (_("scalar must have an index"));
1531 else if (atype.index >= 64 / elsize)
1533 first_error (_("scalar index out of range"));
1538 *type = atype.eltype;
1542 return reg * 16 + atype.index;
1545 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1548 parse_reg_list (char ** strp)
1550 char * str = * strp;
1554 /* We come back here if we get ranges concatenated by '+' or '|'. */
1569 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1571 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1581 first_error (_("bad range in register list"));
1585 for (i = cur_reg + 1; i < reg; i++)
1587 if (range & (1 << i))
1589 (_("Warning: duplicated register (r%d) in register list"),
1597 if (range & (1 << reg))
1598 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1600 else if (reg <= cur_reg)
1601 as_tsktsk (_("Warning: register range not in ascending order"));
1606 while (skip_past_comma (&str) != FAIL
1607 || (in_range = 1, *str++ == '-'));
1612 first_error (_("missing `}'"));
1620 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1623 if (exp.X_op == O_constant)
1625 if (exp.X_add_number
1626 != (exp.X_add_number & 0x0000ffff))
1628 inst.error = _("invalid register mask");
1632 if ((range & exp.X_add_number) != 0)
1634 int regno = range & exp.X_add_number;
1637 regno = (1 << regno) - 1;
1639 (_("Warning: duplicated register (r%d) in register list"),
1643 range |= exp.X_add_number;
1647 if (inst.reloc.type != 0)
1649 inst.error = _("expression too complex");
1653 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1654 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1655 inst.reloc.pc_rel = 0;
1659 if (*str == '|' || *str == '+')
1665 while (another_range);
1671 /* Types of registers in a list. */
1680 /* Parse a VFP register list. If the string is invalid return FAIL.
1681 Otherwise return the number of registers, and set PBASE to the first
1682 register. Parses registers of type ETYPE.
1683 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1684 - Q registers can be used to specify pairs of D registers
1685 - { } can be omitted from around a singleton register list
1686 FIXME: This is not implemented, as it would require backtracking in
1689 This could be done (the meaning isn't really ambiguous), but doesn't
1690 fit in well with the current parsing framework.
1691 - 32 D registers may be used (also true for VFPv3).
1692 FIXME: Types are ignored in these register lists, which is probably a
1696 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1701 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1705 unsigned long mask = 0;
1710 inst.error = _("expecting {");
1719 regtype = REG_TYPE_VFS;
1724 regtype = REG_TYPE_VFD;
1727 case REGLIST_NEON_D:
1728 regtype = REG_TYPE_NDQ;
1732 if (etype != REGLIST_VFP_S)
1734 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1735 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1739 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1742 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1749 base_reg = max_regs;
1753 int setmask = 1, addregs = 1;
1755 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1757 if (new_base == FAIL)
1759 first_error (_(reg_expected_msgs[regtype]));
1763 if (new_base >= max_regs)
1765 first_error (_("register out of range in list"));
1769 /* Note: a value of 2 * n is returned for the register Q<n>. */
1770 if (regtype == REG_TYPE_NQ)
1776 if (new_base < base_reg)
1777 base_reg = new_base;
1779 if (mask & (setmask << new_base))
1781 first_error (_("invalid register list"));
1785 if ((mask >> new_base) != 0 && ! warned)
1787 as_tsktsk (_("register list not in ascending order"));
1791 mask |= setmask << new_base;
1794 if (*str == '-') /* We have the start of a range expression */
1800 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1803 inst.error = gettext (reg_expected_msgs[regtype]);
1807 if (high_range >= max_regs)
1809 first_error (_("register out of range in list"));
1813 if (regtype == REG_TYPE_NQ)
1814 high_range = high_range + 1;
1816 if (high_range <= new_base)
1818 inst.error = _("register range not in ascending order");
1822 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1824 if (mask & (setmask << new_base))
1826 inst.error = _("invalid register list");
1830 mask |= setmask << new_base;
1835 while (skip_past_comma (&str) != FAIL);
1839 /* Sanity check -- should have raised a parse error above. */
1840 if (count == 0 || count > max_regs)
1845 /* Final test -- the registers must be consecutive. */
1847 for (i = 0; i < count; i++)
1849 if ((mask & (1u << i)) == 0)
1851 inst.error = _("non-contiguous register range");
1861 /* True if two alias types are the same. */
1864 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1872 if (a->defined != b->defined)
1875 if ((a->defined & NTA_HASTYPE) != 0
1876 && (a->eltype.type != b->eltype.type
1877 || a->eltype.size != b->eltype.size))
1880 if ((a->defined & NTA_HASINDEX) != 0
1881 && (a->index != b->index))
1887 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1888 The base register is put in *PBASE.
1889 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1891 The register stride (minus one) is put in bit 4 of the return value.
1892 Bits [6:5] encode the list length (minus one).
1893 The type of the list elements is put in *ELTYPE, if non-NULL. */
1895 #define NEON_LANE(X) ((X) & 0xf)
1896 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1897 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1900 parse_neon_el_struct_list (char **str, unsigned *pbase,
1901 struct neon_type_el *eltype)
1908 int leading_brace = 0;
1909 enum arm_reg_type rtype = REG_TYPE_NDQ;
1910 const char *const incr_error = _("register stride must be 1 or 2");
1911 const char *const type_error = _("mismatched element/structure types in list");
1912 struct neon_typed_alias firsttype;
1914 if (skip_past_char (&ptr, '{') == SUCCESS)
1919 struct neon_typed_alias atype;
1920 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1924 first_error (_(reg_expected_msgs[rtype]));
1931 if (rtype == REG_TYPE_NQ)
1937 else if (reg_incr == -1)
1939 reg_incr = getreg - base_reg;
1940 if (reg_incr < 1 || reg_incr > 2)
1942 first_error (_(incr_error));
1946 else if (getreg != base_reg + reg_incr * count)
1948 first_error (_(incr_error));
1952 if (! neon_alias_types_same (&atype, &firsttype))
1954 first_error (_(type_error));
1958 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1962 struct neon_typed_alias htype;
1963 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1965 lane = NEON_INTERLEAVE_LANES;
1966 else if (lane != NEON_INTERLEAVE_LANES)
1968 first_error (_(type_error));
1973 else if (reg_incr != 1)
1975 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1979 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1982 first_error (_(reg_expected_msgs[rtype]));
1985 if (! neon_alias_types_same (&htype, &firsttype))
1987 first_error (_(type_error));
1990 count += hireg + dregs - getreg;
1994 /* If we're using Q registers, we can't use [] or [n] syntax. */
1995 if (rtype == REG_TYPE_NQ)
2001 if ((atype.defined & NTA_HASINDEX) != 0)
2005 else if (lane != atype.index)
2007 first_error (_(type_error));
2011 else if (lane == -1)
2012 lane = NEON_INTERLEAVE_LANES;
2013 else if (lane != NEON_INTERLEAVE_LANES)
2015 first_error (_(type_error));
2020 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2022 /* No lane set by [x]. We must be interleaving structures. */
2024 lane = NEON_INTERLEAVE_LANES;
2027 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2028 || (count > 1 && reg_incr == -1))
2030 first_error (_("error parsing element/structure list"));
2034 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2036 first_error (_("expected }"));
2044 *eltype = firsttype.eltype;
2049 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2052 /* Parse an explicit relocation suffix on an expression. This is
2053 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2054 arm_reloc_hsh contains no entries, so this function can only
2055 succeed if there is no () after the word. Returns -1 on error,
2056 BFD_RELOC_UNUSED if there wasn't any suffix. */
2058 parse_reloc (char **str)
2060 struct reloc_entry *r;
2064 return BFD_RELOC_UNUSED;
2069 while (*q && *q != ')' && *q != ',')
2074 if ((r = (struct reloc_entry *)
2075 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2082 /* Directives: register aliases. */
2084 static struct reg_entry *
2085 insert_reg_alias (char *str, unsigned number, int type)
2087 struct reg_entry *new_reg;
2090 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2092 if (new_reg->builtin)
2093 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2095 /* Only warn about a redefinition if it's not defined as the
2097 else if (new_reg->number != number || new_reg->type != type)
2098 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2103 name = xstrdup (str);
2104 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2106 new_reg->name = name;
2107 new_reg->number = number;
2108 new_reg->type = type;
2109 new_reg->builtin = FALSE;
2110 new_reg->neon = NULL;
2112 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2119 insert_neon_reg_alias (char *str, int number, int type,
2120 struct neon_typed_alias *atype)
2122 struct reg_entry *reg = insert_reg_alias (str, number, type);
2126 first_error (_("attempt to redefine typed alias"));
2132 reg->neon = (struct neon_typed_alias *)
2133 xmalloc (sizeof (struct neon_typed_alias));
2134 *reg->neon = *atype;
2138 /* Look for the .req directive. This is of the form:
2140 new_register_name .req existing_register_name
2142 If we find one, or if it looks sufficiently like one that we want to
2143 handle any error here, return TRUE. Otherwise return FALSE. */
2146 create_register_alias (char * newname, char *p)
2148 struct reg_entry *old;
2149 char *oldname, *nbuf;
2152 /* The input scrubber ensures that whitespace after the mnemonic is
2153 collapsed to single spaces. */
2155 if (strncmp (oldname, " .req ", 6) != 0)
2159 if (*oldname == '\0')
2162 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2165 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2169 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2170 the desired alias name, and p points to its end. If not, then
2171 the desired alias name is in the global original_case_string. */
2172 #ifdef TC_CASE_SENSITIVE
2175 newname = original_case_string;
2176 nlen = strlen (newname);
2179 nbuf = (char *) alloca (nlen + 1);
2180 memcpy (nbuf, newname, nlen);
2183 /* Create aliases under the new name as stated; an all-lowercase
2184 version of the new name; and an all-uppercase version of the new
2186 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2188 for (p = nbuf; *p; p++)
2191 if (strncmp (nbuf, newname, nlen))
2193 /* If this attempt to create an additional alias fails, do not bother
2194 trying to create the all-lower case alias. We will fail and issue
2195 a second, duplicate error message. This situation arises when the
2196 programmer does something like:
2199 The second .req creates the "Foo" alias but then fails to create
2200 the artificial FOO alias because it has already been created by the
2202 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2206 for (p = nbuf; *p; p++)
2209 if (strncmp (nbuf, newname, nlen))
2210 insert_reg_alias (nbuf, old->number, old->type);
2216 /* Create a Neon typed/indexed register alias using directives, e.g.:
2221 These typed registers can be used instead of the types specified after the
2222 Neon mnemonic, so long as all operands given have types. Types can also be
2223 specified directly, e.g.:
2224 vadd d0.s32, d1.s32, d2.s32 */
2227 create_neon_reg_alias (char *newname, char *p)
2229 enum arm_reg_type basetype;
2230 struct reg_entry *basereg;
2231 struct reg_entry mybasereg;
2232 struct neon_type ntype;
2233 struct neon_typed_alias typeinfo;
2234 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2237 typeinfo.defined = 0;
2238 typeinfo.eltype.type = NT_invtype;
2239 typeinfo.eltype.size = -1;
2240 typeinfo.index = -1;
2244 if (strncmp (p, " .dn ", 5) == 0)
2245 basetype = REG_TYPE_VFD;
2246 else if (strncmp (p, " .qn ", 5) == 0)
2247 basetype = REG_TYPE_NQ;
2256 basereg = arm_reg_parse_multi (&p);
2258 if (basereg && basereg->type != basetype)
2260 as_bad (_("bad type for register"));
2264 if (basereg == NULL)
2267 /* Try parsing as an integer. */
2268 my_get_expression (&exp, &p, GE_NO_PREFIX);
2269 if (exp.X_op != O_constant)
2271 as_bad (_("expression must be constant"));
2274 basereg = &mybasereg;
2275 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2281 typeinfo = *basereg->neon;
2283 if (parse_neon_type (&ntype, &p) == SUCCESS)
2285 /* We got a type. */
2286 if (typeinfo.defined & NTA_HASTYPE)
2288 as_bad (_("can't redefine the type of a register alias"));
2292 typeinfo.defined |= NTA_HASTYPE;
2293 if (ntype.elems != 1)
2295 as_bad (_("you must specify a single type only"));
2298 typeinfo.eltype = ntype.el[0];
2301 if (skip_past_char (&p, '[') == SUCCESS)
2304 /* We got a scalar index. */
2306 if (typeinfo.defined & NTA_HASINDEX)
2308 as_bad (_("can't redefine the index of a scalar alias"));
2312 my_get_expression (&exp, &p, GE_NO_PREFIX);
2314 if (exp.X_op != O_constant)
2316 as_bad (_("scalar index must be constant"));
2320 typeinfo.defined |= NTA_HASINDEX;
2321 typeinfo.index = exp.X_add_number;
2323 if (skip_past_char (&p, ']') == FAIL)
2325 as_bad (_("expecting ]"));
2330 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2331 the desired alias name, and p points to its end. If not, then
2332 the desired alias name is in the global original_case_string. */
2333 #ifdef TC_CASE_SENSITIVE
2334 namelen = nameend - newname;
2336 newname = original_case_string;
2337 namelen = strlen (newname);
2340 namebuf = (char *) alloca (namelen + 1);
2341 strncpy (namebuf, newname, namelen);
2342 namebuf[namelen] = '\0';
2344 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2345 typeinfo.defined != 0 ? &typeinfo : NULL);
2347 /* Insert name in all uppercase. */
2348 for (p = namebuf; *p; p++)
2351 if (strncmp (namebuf, newname, namelen))
2352 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2353 typeinfo.defined != 0 ? &typeinfo : NULL);
2355 /* Insert name in all lowercase. */
2356 for (p = namebuf; *p; p++)
2359 if (strncmp (namebuf, newname, namelen))
2360 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2361 typeinfo.defined != 0 ? &typeinfo : NULL);
2366 /* Should never be called, as .req goes between the alias and the
2367 register name, not at the beginning of the line. */
2370 s_req (int a ATTRIBUTE_UNUSED)
2372 as_bad (_("invalid syntax for .req directive"));
2376 s_dn (int a ATTRIBUTE_UNUSED)
2378 as_bad (_("invalid syntax for .dn directive"));
2382 s_qn (int a ATTRIBUTE_UNUSED)
2384 as_bad (_("invalid syntax for .qn directive"));
2387 /* The .unreq directive deletes an alias which was previously defined
2388 by .req. For example:
2394 s_unreq (int a ATTRIBUTE_UNUSED)
2399 name = input_line_pointer;
2401 while (*input_line_pointer != 0
2402 && *input_line_pointer != ' '
2403 && *input_line_pointer != '\n')
2404 ++input_line_pointer;
2406 saved_char = *input_line_pointer;
2407 *input_line_pointer = 0;
2410 as_bad (_("invalid syntax for .unreq directive"));
2413 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2417 as_bad (_("unknown register alias '%s'"), name);
2418 else if (reg->builtin)
2419 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2426 hash_delete (arm_reg_hsh, name, FALSE);
2427 free ((char *) reg->name);
2432 /* Also locate the all upper case and all lower case versions.
2433 Do not complain if we cannot find one or the other as it
2434 was probably deleted above. */
2436 nbuf = strdup (name);
2437 for (p = nbuf; *p; p++)
2439 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2442 hash_delete (arm_reg_hsh, nbuf, FALSE);
2443 free ((char *) reg->name);
2449 for (p = nbuf; *p; p++)
2451 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2454 hash_delete (arm_reg_hsh, nbuf, FALSE);
2455 free ((char *) reg->name);
2465 *input_line_pointer = saved_char;
2466 demand_empty_rest_of_line ();
2469 /* Directives: Instruction set selection. */
2472 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2473 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2474 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2475 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2477 /* Create a new mapping symbol for the transition to STATE. */
2480 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2483 const char * symname;
2490 type = BSF_NO_FLAGS;
2494 type = BSF_NO_FLAGS;
2498 type = BSF_NO_FLAGS;
2504 symbolP = symbol_new (symname, now_seg, value, frag);
2505 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2510 THUMB_SET_FUNC (symbolP, 0);
2511 ARM_SET_THUMB (symbolP, 0);
2512 ARM_SET_INTERWORK (symbolP, support_interwork);
2516 THUMB_SET_FUNC (symbolP, 1);
2517 ARM_SET_THUMB (symbolP, 1);
2518 ARM_SET_INTERWORK (symbolP, support_interwork);
2526 /* Save the mapping symbols for future reference. Also check that
2527 we do not place two mapping symbols at the same offset within a
2528 frag. We'll handle overlap between frags in
2529 check_mapping_symbols.
2531 If .fill or other data filling directive generates zero sized data,
2532 the mapping symbol for the following code will have the same value
2533 as the one generated for the data filling directive. In this case,
2534 we replace the old symbol with the new one at the same address. */
2537 if (frag->tc_frag_data.first_map != NULL)
2539 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2540 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2542 frag->tc_frag_data.first_map = symbolP;
2544 if (frag->tc_frag_data.last_map != NULL)
2546 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2547 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2548 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2550 frag->tc_frag_data.last_map = symbolP;
2553 /* We must sometimes convert a region marked as code to data during
2554 code alignment, if an odd number of bytes have to be padded. The
2555 code mapping symbol is pushed to an aligned address. */
2558 insert_data_mapping_symbol (enum mstate state,
2559 valueT value, fragS *frag, offsetT bytes)
2561 /* If there was already a mapping symbol, remove it. */
2562 if (frag->tc_frag_data.last_map != NULL
2563 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2565 symbolS *symp = frag->tc_frag_data.last_map;
2569 know (frag->tc_frag_data.first_map == symp);
2570 frag->tc_frag_data.first_map = NULL;
2572 frag->tc_frag_data.last_map = NULL;
2573 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2576 make_mapping_symbol (MAP_DATA, value, frag);
2577 make_mapping_symbol (state, value + bytes, frag);
2580 static void mapping_state_2 (enum mstate state, int max_chars);
2582 /* Set the mapping state to STATE. Only call this when about to
2583 emit some STATE bytes to the file. */
2586 mapping_state (enum mstate state)
2588 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2590 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2592 if (mapstate == state)
2593 /* The mapping symbol has already been emitted.
2594 There is nothing else to do. */
2597 if (state == MAP_ARM || state == MAP_THUMB)
2599 All ARM instructions require 4-byte alignment.
2600 (Almost) all Thumb instructions require 2-byte alignment.
2602 When emitting instructions into any section, mark the section
2605 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2606 but themselves require 2-byte alignment; this applies to some
2607 PC- relative forms. However, these cases will invovle implicit
2608 literal pool generation or an explicit .align >=2, both of
2609 which will cause the section to me marked with sufficient
2610 alignment. Thus, we don't handle those cases here. */
2611 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2613 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2614 /* This case will be evaluated later in the next else. */
2616 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2617 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2619 /* Only add the symbol if the offset is > 0:
2620 if we're at the first frag, check it's size > 0;
2621 if we're not at the first frag, then for sure
2622 the offset is > 0. */
2623 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2624 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2627 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2630 mapping_state_2 (state, 0);
2634 /* Same as mapping_state, but MAX_CHARS bytes have already been
2635 allocated. Put the mapping symbol that far back. */
2638 mapping_state_2 (enum mstate state, int max_chars)
2640 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2642 if (!SEG_NORMAL (now_seg))
2645 if (mapstate == state)
2646 /* The mapping symbol has already been emitted.
2647 There is nothing else to do. */
2650 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2651 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2654 #define mapping_state(x) ((void)0)
2655 #define mapping_state_2(x, y) ((void)0)
2658 /* Find the real, Thumb encoded start of a Thumb function. */
2662 find_real_start (symbolS * symbolP)
2665 const char * name = S_GET_NAME (symbolP);
2666 symbolS * new_target;
2668 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2669 #define STUB_NAME ".real_start_of"
2674 /* The compiler may generate BL instructions to local labels because
2675 it needs to perform a branch to a far away location. These labels
2676 do not have a corresponding ".real_start_of" label. We check
2677 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2678 the ".real_start_of" convention for nonlocal branches. */
2679 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2682 real_start = ACONCAT ((STUB_NAME, name, NULL));
2683 new_target = symbol_find (real_start);
2685 if (new_target == NULL)
2687 as_warn (_("Failed to find real start of function: %s\n"), name);
2688 new_target = symbolP;
2696 opcode_select (int width)
2703 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2704 as_bad (_("selected processor does not support THUMB opcodes"));
2707 /* No need to force the alignment, since we will have been
2708 coming from ARM mode, which is word-aligned. */
2709 record_alignment (now_seg, 1);
2716 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2717 as_bad (_("selected processor does not support ARM opcodes"));
2722 frag_align (2, 0, 0);
2724 record_alignment (now_seg, 1);
2729 as_bad (_("invalid instruction size selected (%d)"), width);
2734 s_arm (int ignore ATTRIBUTE_UNUSED)
2737 demand_empty_rest_of_line ();
2741 s_thumb (int ignore ATTRIBUTE_UNUSED)
2744 demand_empty_rest_of_line ();
2748 s_code (int unused ATTRIBUTE_UNUSED)
2752 temp = get_absolute_expression ();
2757 opcode_select (temp);
2761 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2766 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2768 /* If we are not already in thumb mode go into it, EVEN if
2769 the target processor does not support thumb instructions.
2770 This is used by gcc/config/arm/lib1funcs.asm for example
2771 to compile interworking support functions even if the
2772 target processor should not support interworking. */
2776 record_alignment (now_seg, 1);
2779 demand_empty_rest_of_line ();
2783 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2787 /* The following label is the name/address of the start of a Thumb function.
2788 We need to know this for the interworking support. */
2789 label_is_thumb_function_name = TRUE;
2792 /* Perform a .set directive, but also mark the alias as
2793 being a thumb function. */
2796 s_thumb_set (int equiv)
2798 /* XXX the following is a duplicate of the code for s_set() in read.c
2799 We cannot just call that code as we need to get at the symbol that
2806 /* Especial apologies for the random logic:
2807 This just grew, and could be parsed much more simply!
2809 name = input_line_pointer;
2810 delim = get_symbol_end ();
2811 end_name = input_line_pointer;
2814 if (*input_line_pointer != ',')
2817 as_bad (_("expected comma after name \"%s\""), name);
2819 ignore_rest_of_line ();
2823 input_line_pointer++;
2826 if (name[0] == '.' && name[1] == '\0')
2828 /* XXX - this should not happen to .thumb_set. */
2832 if ((symbolP = symbol_find (name)) == NULL
2833 && (symbolP = md_undefined_symbol (name)) == NULL)
2836 /* When doing symbol listings, play games with dummy fragments living
2837 outside the normal fragment chain to record the file and line info
2839 if (listing & LISTING_SYMBOLS)
2841 extern struct list_info_struct * listing_tail;
2842 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2844 memset (dummy_frag, 0, sizeof (fragS));
2845 dummy_frag->fr_type = rs_fill;
2846 dummy_frag->line = listing_tail;
2847 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2848 dummy_frag->fr_symbol = symbolP;
2852 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2855 /* "set" symbols are local unless otherwise specified. */
2856 SF_SET_LOCAL (symbolP);
2857 #endif /* OBJ_COFF */
2858 } /* Make a new symbol. */
2860 symbol_table_insert (symbolP);
2865 && S_IS_DEFINED (symbolP)
2866 && S_GET_SEGMENT (symbolP) != reg_section)
2867 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2869 pseudo_set (symbolP);
2871 demand_empty_rest_of_line ();
2873 /* XXX Now we come to the Thumb specific bit of code. */
2875 THUMB_SET_FUNC (symbolP, 1);
2876 ARM_SET_THUMB (symbolP, 1);
2877 #if defined OBJ_ELF || defined OBJ_COFF
2878 ARM_SET_INTERWORK (symbolP, support_interwork);
2882 /* Directives: Mode selection. */
2884 /* .syntax [unified|divided] - choose the new unified syntax
2885 (same for Arm and Thumb encoding, modulo slight differences in what
2886 can be represented) or the old divergent syntax for each mode. */
2888 s_syntax (int unused ATTRIBUTE_UNUSED)
2892 name = input_line_pointer;
2893 delim = get_symbol_end ();
2895 if (!strcasecmp (name, "unified"))
2896 unified_syntax = TRUE;
2897 else if (!strcasecmp (name, "divided"))
2898 unified_syntax = FALSE;
2901 as_bad (_("unrecognized syntax mode \"%s\""), name);
2904 *input_line_pointer = delim;
2905 demand_empty_rest_of_line ();
2908 /* Directives: sectioning and alignment. */
2910 /* Same as s_align_ptwo but align 0 => align 2. */
2913 s_align (int unused ATTRIBUTE_UNUSED)
2918 long max_alignment = 15;
2920 temp = get_absolute_expression ();
2921 if (temp > max_alignment)
2922 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2925 as_bad (_("alignment negative. 0 assumed."));
2929 if (*input_line_pointer == ',')
2931 input_line_pointer++;
2932 temp_fill = get_absolute_expression ();
2944 /* Only make a frag if we HAVE to. */
2945 if (temp && !need_pass_2)
2947 if (!fill_p && subseg_text_p (now_seg))
2948 frag_align_code (temp, 0);
2950 frag_align (temp, (int) temp_fill, 0);
2952 demand_empty_rest_of_line ();
2954 record_alignment (now_seg, temp);
2958 s_bss (int ignore ATTRIBUTE_UNUSED)
2960 /* We don't support putting frags in the BSS segment, we fake it by
2961 marking in_bss, then looking at s_skip for clues. */
2962 subseg_set (bss_section, 0);
2963 demand_empty_rest_of_line ();
2965 #ifdef md_elf_section_change_hook
2966 md_elf_section_change_hook ();
2971 s_even (int ignore ATTRIBUTE_UNUSED)
2973 /* Never make frag if expect extra pass. */
2975 frag_align (1, 0, 0);
2977 record_alignment (now_seg, 1);
2979 demand_empty_rest_of_line ();
2982 /* Directives: Literal pools. */
2984 static literal_pool *
2985 find_literal_pool (void)
2987 literal_pool * pool;
2989 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2991 if (pool->section == now_seg
2992 && pool->sub_section == now_subseg)
2999 static literal_pool *
3000 find_or_make_literal_pool (void)
3002 /* Next literal pool ID number. */
3003 static unsigned int latest_pool_num = 1;
3004 literal_pool * pool;
3006 pool = find_literal_pool ();
3010 /* Create a new pool. */
3011 pool = (literal_pool *) xmalloc (sizeof (* pool));
3015 pool->next_free_entry = 0;
3016 pool->section = now_seg;
3017 pool->sub_section = now_subseg;
3018 pool->next = list_of_pools;
3019 pool->symbol = NULL;
3021 /* Add it to the list. */
3022 list_of_pools = pool;
3025 /* New pools, and emptied pools, will have a NULL symbol. */
3026 if (pool->symbol == NULL)
3028 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3029 (valueT) 0, &zero_address_frag);
3030 pool->id = latest_pool_num ++;
3037 /* Add the literal in the global 'inst'
3038 structure to the relevant literal pool. */
3041 add_to_lit_pool (void)
3043 literal_pool * pool;
3046 pool = find_or_make_literal_pool ();
3048 /* Check if this literal value is already in the pool. */
3049 for (entry = 0; entry < pool->next_free_entry; entry ++)
3051 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3052 && (inst.reloc.exp.X_op == O_constant)
3053 && (pool->literals[entry].X_add_number
3054 == inst.reloc.exp.X_add_number)
3055 && (pool->literals[entry].X_unsigned
3056 == inst.reloc.exp.X_unsigned))
3059 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3060 && (inst.reloc.exp.X_op == O_symbol)
3061 && (pool->literals[entry].X_add_number
3062 == inst.reloc.exp.X_add_number)
3063 && (pool->literals[entry].X_add_symbol
3064 == inst.reloc.exp.X_add_symbol)
3065 && (pool->literals[entry].X_op_symbol
3066 == inst.reloc.exp.X_op_symbol))
3070 /* Do we need to create a new entry? */
3071 if (entry == pool->next_free_entry)
3073 if (entry >= MAX_LITERAL_POOL_SIZE)
3075 inst.error = _("literal pool overflow");
3079 pool->literals[entry] = inst.reloc.exp;
3081 /* PR ld/12974: Record the location of the first source line to reference
3082 this entry in the literal pool. If it turns out during linking that the
3083 symbol does not exist we will be able to give an accurate line number for
3084 the (first use of the) missing reference. */
3085 if (debug_type == DEBUG_DWARF2)
3086 dwarf2_where (pool->locs + entry);
3088 pool->next_free_entry += 1;
3091 inst.reloc.exp.X_op = O_symbol;
3092 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3093 inst.reloc.exp.X_add_symbol = pool->symbol;
3098 /* Can't use symbol_new here, so have to create a symbol and then at
3099 a later date assign it a value. Thats what these functions do. */
3102 symbol_locate (symbolS * symbolP,
3103 const char * name, /* It is copied, the caller can modify. */
3104 segT segment, /* Segment identifier (SEG_<something>). */
3105 valueT valu, /* Symbol value. */
3106 fragS * frag) /* Associated fragment. */
3108 unsigned int name_length;
3109 char * preserved_copy_of_name;
3111 name_length = strlen (name) + 1; /* +1 for \0. */
3112 obstack_grow (¬es, name, name_length);
3113 preserved_copy_of_name = (char *) obstack_finish (¬es);
3115 #ifdef tc_canonicalize_symbol_name
3116 preserved_copy_of_name =
3117 tc_canonicalize_symbol_name (preserved_copy_of_name);
3120 S_SET_NAME (symbolP, preserved_copy_of_name);
3122 S_SET_SEGMENT (symbolP, segment);
3123 S_SET_VALUE (symbolP, valu);
3124 symbol_clear_list_pointers (symbolP);
3126 symbol_set_frag (symbolP, frag);
3128 /* Link to end of symbol chain. */
3130 extern int symbol_table_frozen;
3132 if (symbol_table_frozen)
3136 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3138 obj_symbol_new_hook (symbolP);
3140 #ifdef tc_symbol_new_hook
3141 tc_symbol_new_hook (symbolP);
3145 verify_symbol_chain (symbol_rootP, symbol_lastP);
3146 #endif /* DEBUG_SYMS */
3151 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3154 literal_pool * pool;
3157 pool = find_literal_pool ();
3159 || pool->symbol == NULL
3160 || pool->next_free_entry == 0)
3163 mapping_state (MAP_DATA);
3165 /* Align pool as you have word accesses.
3166 Only make a frag if we have to. */
3168 frag_align (2, 0, 0);
3170 record_alignment (now_seg, 2);
3172 sprintf (sym_name, "$$lit_\002%x", pool->id);
3174 symbol_locate (pool->symbol, sym_name, now_seg,
3175 (valueT) frag_now_fix (), frag_now);
3176 symbol_table_insert (pool->symbol);
3178 ARM_SET_THUMB (pool->symbol, thumb_mode);
3180 #if defined OBJ_COFF || defined OBJ_ELF
3181 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3184 for (entry = 0; entry < pool->next_free_entry; entry ++)
3187 if (debug_type == DEBUG_DWARF2)
3188 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3190 /* First output the expression in the instruction to the pool. */
3191 emit_expr (&(pool->literals[entry]), 4); /* .word */
3194 /* Mark the pool as empty. */
3195 pool->next_free_entry = 0;
3196 pool->symbol = NULL;
3200 /* Forward declarations for functions below, in the MD interface
3202 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3203 static valueT create_unwind_entry (int);
3204 static void start_unwind_section (const segT, int);
3205 static void add_unwind_opcode (valueT, int);
3206 static void flush_pending_unwind (void);
3208 /* Directives: Data. */
3211 s_arm_elf_cons (int nbytes)
3215 #ifdef md_flush_pending_output
3216 md_flush_pending_output ();
3219 if (is_it_end_of_statement ())
3221 demand_empty_rest_of_line ();
3225 #ifdef md_cons_align
3226 md_cons_align (nbytes);
3229 mapping_state (MAP_DATA);
3233 char *base = input_line_pointer;
3237 if (exp.X_op != O_symbol)
3238 emit_expr (&exp, (unsigned int) nbytes);
3241 char *before_reloc = input_line_pointer;
3242 reloc = parse_reloc (&input_line_pointer);
3245 as_bad (_("unrecognized relocation suffix"));
3246 ignore_rest_of_line ();
3249 else if (reloc == BFD_RELOC_UNUSED)
3250 emit_expr (&exp, (unsigned int) nbytes);
3253 reloc_howto_type *howto = (reloc_howto_type *)
3254 bfd_reloc_type_lookup (stdoutput,
3255 (bfd_reloc_code_real_type) reloc);
3256 int size = bfd_get_reloc_size (howto);
3258 if (reloc == BFD_RELOC_ARM_PLT32)
3260 as_bad (_("(plt) is only valid on branch targets"));
3261 reloc = BFD_RELOC_UNUSED;
3266 as_bad (_("%s relocations do not fit in %d bytes"),
3267 howto->name, nbytes);
3270 /* We've parsed an expression stopping at O_symbol.
3271 But there may be more expression left now that we
3272 have parsed the relocation marker. Parse it again.
3273 XXX Surely there is a cleaner way to do this. */
3274 char *p = input_line_pointer;
3276 char *save_buf = (char *) alloca (input_line_pointer - base);
3277 memcpy (save_buf, base, input_line_pointer - base);
3278 memmove (base + (input_line_pointer - before_reloc),
3279 base, before_reloc - base);
3281 input_line_pointer = base + (input_line_pointer-before_reloc);
3283 memcpy (base, save_buf, p - base);
3285 offset = nbytes - size;
3286 p = frag_more ((int) nbytes);
3287 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3288 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3293 while (*input_line_pointer++ == ',');
3295 /* Put terminator back into stream. */
3296 input_line_pointer --;
3297 demand_empty_rest_of_line ();
3300 /* Emit an expression containing a 32-bit thumb instruction.
3301 Implementation based on put_thumb32_insn. */
3304 emit_thumb32_expr (expressionS * exp)
3306 expressionS exp_high = *exp;
3308 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3309 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3310 exp->X_add_number &= 0xffff;
3311 emit_expr (exp, (unsigned int) THUMB_SIZE);
3314 /* Guess the instruction size based on the opcode. */
3317 thumb_insn_size (int opcode)
3319 if ((unsigned int) opcode < 0xe800u)
3321 else if ((unsigned int) opcode >= 0xe8000000u)
3328 emit_insn (expressionS *exp, int nbytes)
3332 if (exp->X_op == O_constant)
3337 size = thumb_insn_size (exp->X_add_number);
3341 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3343 as_bad (_(".inst.n operand too big. "\
3344 "Use .inst.w instead"));
3349 if (now_it.state == AUTOMATIC_IT_BLOCK)
3350 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3352 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3354 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3355 emit_thumb32_expr (exp);
3357 emit_expr (exp, (unsigned int) size);
3359 it_fsm_post_encode ();
3363 as_bad (_("cannot determine Thumb instruction size. " \
3364 "Use .inst.n/.inst.w instead"));
3367 as_bad (_("constant expression required"));
3372 /* Like s_arm_elf_cons but do not use md_cons_align and
3373 set the mapping state to MAP_ARM/MAP_THUMB. */
3376 s_arm_elf_inst (int nbytes)
3378 if (is_it_end_of_statement ())
3380 demand_empty_rest_of_line ();
3384 /* Calling mapping_state () here will not change ARM/THUMB,
3385 but will ensure not to be in DATA state. */
3388 mapping_state (MAP_THUMB);
3393 as_bad (_("width suffixes are invalid in ARM mode"));
3394 ignore_rest_of_line ();
3400 mapping_state (MAP_ARM);
3409 if (! emit_insn (& exp, nbytes))
3411 ignore_rest_of_line ();
3415 while (*input_line_pointer++ == ',');
3417 /* Put terminator back into stream. */
3418 input_line_pointer --;
3419 demand_empty_rest_of_line ();
3422 /* Parse a .rel31 directive. */
3425 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3432 if (*input_line_pointer == '1')
3433 highbit = 0x80000000;
3434 else if (*input_line_pointer != '0')
3435 as_bad (_("expected 0 or 1"));
3437 input_line_pointer++;
3438 if (*input_line_pointer != ',')
3439 as_bad (_("missing comma"));
3440 input_line_pointer++;
3442 #ifdef md_flush_pending_output
3443 md_flush_pending_output ();
3446 #ifdef md_cons_align
3450 mapping_state (MAP_DATA);
3455 md_number_to_chars (p, highbit, 4);
3456 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3457 BFD_RELOC_ARM_PREL31);
3459 demand_empty_rest_of_line ();
3462 /* Directives: AEABI stack-unwind tables. */
3464 /* Parse an unwind_fnstart directive. Simply records the current location. */
3467 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3469 demand_empty_rest_of_line ();
3470 if (unwind.proc_start)
3472 as_bad (_("duplicate .fnstart directive"));
3476 /* Mark the start of the function. */
3477 unwind.proc_start = expr_build_dot ();
3479 /* Reset the rest of the unwind info. */
3480 unwind.opcode_count = 0;
3481 unwind.table_entry = NULL;
3482 unwind.personality_routine = NULL;
3483 unwind.personality_index = -1;
3484 unwind.frame_size = 0;
3485 unwind.fp_offset = 0;
3486 unwind.fp_reg = REG_SP;
3488 unwind.sp_restored = 0;
3492 /* Parse a handlerdata directive. Creates the exception handling table entry
3493 for the function. */
3496 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3498 demand_empty_rest_of_line ();
3499 if (!unwind.proc_start)
3500 as_bad (MISSING_FNSTART);
3502 if (unwind.table_entry)
3503 as_bad (_("duplicate .handlerdata directive"));
3505 create_unwind_entry (1);
3508 /* Parse an unwind_fnend directive. Generates the index table entry. */
3511 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3516 unsigned int marked_pr_dependency;
3518 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3522 as_bad (_(".fnend directive without .fnstart"));
3526 /* Add eh table entry. */
3527 if (unwind.table_entry == NULL)
3528 val = create_unwind_entry (0);
3532 /* Add index table entry. This is two words. */
3533 start_unwind_section (unwind.saved_seg, 1);
3534 frag_align (2, 0, 0);
3535 record_alignment (now_seg, 2);
3537 ptr = frag_more (8);
3538 where = frag_now_fix () - 8;
3540 /* Self relative offset of the function start. */
3541 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3542 BFD_RELOC_ARM_PREL31);
3544 /* Indicate dependency on EHABI-defined personality routines to the
3545 linker, if it hasn't been done already. */
3546 marked_pr_dependency
3547 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3548 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3549 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3551 static const char *const name[] =
3553 "__aeabi_unwind_cpp_pr0",
3554 "__aeabi_unwind_cpp_pr1",
3555 "__aeabi_unwind_cpp_pr2"
3557 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3558 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3559 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3560 |= 1 << unwind.personality_index;
3564 /* Inline exception table entry. */
3565 md_number_to_chars (ptr + 4, val, 4);
3567 /* Self relative offset of the table entry. */
3568 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3569 BFD_RELOC_ARM_PREL31);
3571 /* Restore the original section. */
3572 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3574 unwind.proc_start = NULL;
3578 /* Parse an unwind_cantunwind directive. */
3581 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3583 demand_empty_rest_of_line ();
3584 if (!unwind.proc_start)
3585 as_bad (MISSING_FNSTART);
3587 if (unwind.personality_routine || unwind.personality_index != -1)
3588 as_bad (_("personality routine specified for cantunwind frame"));
3590 unwind.personality_index = -2;
3594 /* Parse a personalityindex directive. */
3597 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3601 if (!unwind.proc_start)
3602 as_bad (MISSING_FNSTART);
3604 if (unwind.personality_routine || unwind.personality_index != -1)
3605 as_bad (_("duplicate .personalityindex directive"));
3609 if (exp.X_op != O_constant
3610 || exp.X_add_number < 0 || exp.X_add_number > 15)
3612 as_bad (_("bad personality routine number"));
3613 ignore_rest_of_line ();
3617 unwind.personality_index = exp.X_add_number;
3619 demand_empty_rest_of_line ();
3623 /* Parse a personality directive. */
3626 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3630 if (!unwind.proc_start)
3631 as_bad (MISSING_FNSTART);
3633 if (unwind.personality_routine || unwind.personality_index != -1)
3634 as_bad (_("duplicate .personality directive"));
3636 name = input_line_pointer;
3637 c = get_symbol_end ();
3638 p = input_line_pointer;
3639 unwind.personality_routine = symbol_find_or_make (name);
3641 demand_empty_rest_of_line ();
3645 /* Parse a directive saving core registers. */
3648 s_arm_unwind_save_core (void)
3654 range = parse_reg_list (&input_line_pointer);
3657 as_bad (_("expected register list"));
3658 ignore_rest_of_line ();
3662 demand_empty_rest_of_line ();
3664 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3665 into .unwind_save {..., sp...}. We aren't bothered about the value of
3666 ip because it is clobbered by calls. */
3667 if (unwind.sp_restored && unwind.fp_reg == 12
3668 && (range & 0x3000) == 0x1000)
3670 unwind.opcode_count--;
3671 unwind.sp_restored = 0;
3672 range = (range | 0x2000) & ~0x1000;
3673 unwind.pending_offset = 0;
3679 /* See if we can use the short opcodes. These pop a block of up to 8
3680 registers starting with r4, plus maybe r14. */
3681 for (n = 0; n < 8; n++)
3683 /* Break at the first non-saved register. */
3684 if ((range & (1 << (n + 4))) == 0)
3687 /* See if there are any other bits set. */
3688 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3690 /* Use the long form. */
3691 op = 0x8000 | ((range >> 4) & 0xfff);
3692 add_unwind_opcode (op, 2);
3696 /* Use the short form. */
3698 op = 0xa8; /* Pop r14. */
3700 op = 0xa0; /* Do not pop r14. */
3702 add_unwind_opcode (op, 1);
3709 op = 0xb100 | (range & 0xf);
3710 add_unwind_opcode (op, 2);
3713 /* Record the number of bytes pushed. */
3714 for (n = 0; n < 16; n++)
3716 if (range & (1 << n))
3717 unwind.frame_size += 4;
3722 /* Parse a directive saving FPA registers. */
3725 s_arm_unwind_save_fpa (int reg)
3731 /* Get Number of registers to transfer. */
3732 if (skip_past_comma (&input_line_pointer) != FAIL)
3735 exp.X_op = O_illegal;
3737 if (exp.X_op != O_constant)
3739 as_bad (_("expected , <constant>"));
3740 ignore_rest_of_line ();
3744 num_regs = exp.X_add_number;
3746 if (num_regs < 1 || num_regs > 4)
3748 as_bad (_("number of registers must be in the range [1:4]"));
3749 ignore_rest_of_line ();
3753 demand_empty_rest_of_line ();
3758 op = 0xb4 | (num_regs - 1);
3759 add_unwind_opcode (op, 1);
3764 op = 0xc800 | (reg << 4) | (num_regs - 1);
3765 add_unwind_opcode (op, 2);
3767 unwind.frame_size += num_regs * 12;
3771 /* Parse a directive saving VFP registers for ARMv6 and above. */
3774 s_arm_unwind_save_vfp_armv6 (void)
3779 int num_vfpv3_regs = 0;
3780 int num_regs_below_16;
3782 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3785 as_bad (_("expected register list"));
3786 ignore_rest_of_line ();
3790 demand_empty_rest_of_line ();
3792 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3793 than FSTMX/FLDMX-style ones). */
3795 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3797 num_vfpv3_regs = count;
3798 else if (start + count > 16)
3799 num_vfpv3_regs = start + count - 16;
3801 if (num_vfpv3_regs > 0)
3803 int start_offset = start > 16 ? start - 16 : 0;
3804 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3805 add_unwind_opcode (op, 2);
3808 /* Generate opcode for registers numbered in the range 0 .. 15. */
3809 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3810 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3811 if (num_regs_below_16 > 0)
3813 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3814 add_unwind_opcode (op, 2);
3817 unwind.frame_size += count * 8;
3821 /* Parse a directive saving VFP registers for pre-ARMv6. */
3824 s_arm_unwind_save_vfp (void)
3830 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3833 as_bad (_("expected register list"));
3834 ignore_rest_of_line ();
3838 demand_empty_rest_of_line ();
3843 op = 0xb8 | (count - 1);
3844 add_unwind_opcode (op, 1);
3849 op = 0xb300 | (reg << 4) | (count - 1);
3850 add_unwind_opcode (op, 2);
3852 unwind.frame_size += count * 8 + 4;
3856 /* Parse a directive saving iWMMXt data registers. */
3859 s_arm_unwind_save_mmxwr (void)
3867 if (*input_line_pointer == '{')
3868 input_line_pointer++;
3872 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3876 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3881 as_tsktsk (_("register list not in ascending order"));
3884 if (*input_line_pointer == '-')
3886 input_line_pointer++;
3887 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3890 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3893 else if (reg >= hi_reg)
3895 as_bad (_("bad register range"));
3898 for (; reg < hi_reg; reg++)
3902 while (skip_past_comma (&input_line_pointer) != FAIL);
3904 if (*input_line_pointer == '}')
3905 input_line_pointer++;
3907 demand_empty_rest_of_line ();
3909 /* Generate any deferred opcodes because we're going to be looking at
3911 flush_pending_unwind ();
3913 for (i = 0; i < 16; i++)
3915 if (mask & (1 << i))
3916 unwind.frame_size += 8;
3919 /* Attempt to combine with a previous opcode. We do this because gcc
3920 likes to output separate unwind directives for a single block of
3922 if (unwind.opcode_count > 0)
3924 i = unwind.opcodes[unwind.opcode_count - 1];
3925 if ((i & 0xf8) == 0xc0)
3928 /* Only merge if the blocks are contiguous. */
3931 if ((mask & 0xfe00) == (1 << 9))
3933 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3934 unwind.opcode_count--;
3937 else if (i == 6 && unwind.opcode_count >= 2)
3939 i = unwind.opcodes[unwind.opcode_count - 2];
3943 op = 0xffff << (reg - 1);
3945 && ((mask & op) == (1u << (reg - 1))))
3947 op = (1 << (reg + i + 1)) - 1;
3948 op &= ~((1 << reg) - 1);
3950 unwind.opcode_count -= 2;
3957 /* We want to generate opcodes in the order the registers have been
3958 saved, ie. descending order. */
3959 for (reg = 15; reg >= -1; reg--)
3961 /* Save registers in blocks. */
3963 || !(mask & (1 << reg)))
3965 /* We found an unsaved reg. Generate opcodes to save the
3972 op = 0xc0 | (hi_reg - 10);
3973 add_unwind_opcode (op, 1);
3978 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3979 add_unwind_opcode (op, 2);
3988 ignore_rest_of_line ();
3992 s_arm_unwind_save_mmxwcg (void)
3999 if (*input_line_pointer == '{')
4000 input_line_pointer++;
4004 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4008 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4014 as_tsktsk (_("register list not in ascending order"));
4017 if (*input_line_pointer == '-')
4019 input_line_pointer++;
4020 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4023 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4026 else if (reg >= hi_reg)
4028 as_bad (_("bad register range"));
4031 for (; reg < hi_reg; reg++)
4035 while (skip_past_comma (&input_line_pointer) != FAIL);
4037 if (*input_line_pointer == '}')
4038 input_line_pointer++;
4040 demand_empty_rest_of_line ();
4042 /* Generate any deferred opcodes because we're going to be looking at
4044 flush_pending_unwind ();
4046 for (reg = 0; reg < 16; reg++)
4048 if (mask & (1 << reg))
4049 unwind.frame_size += 4;
4052 add_unwind_opcode (op, 2);
4055 ignore_rest_of_line ();
4059 /* Parse an unwind_save directive.
4060 If the argument is non-zero, this is a .vsave directive. */
4063 s_arm_unwind_save (int arch_v6)
4066 struct reg_entry *reg;
4067 bfd_boolean had_brace = FALSE;
4069 if (!unwind.proc_start)
4070 as_bad (MISSING_FNSTART);
4072 /* Figure out what sort of save we have. */
4073 peek = input_line_pointer;
4081 reg = arm_reg_parse_multi (&peek);
4085 as_bad (_("register expected"));
4086 ignore_rest_of_line ();
4095 as_bad (_("FPA .unwind_save does not take a register list"));
4096 ignore_rest_of_line ();
4099 input_line_pointer = peek;
4100 s_arm_unwind_save_fpa (reg->number);
4103 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4106 s_arm_unwind_save_vfp_armv6 ();
4108 s_arm_unwind_save_vfp ();
4110 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4111 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4114 as_bad (_(".unwind_save does not support this kind of register"));
4115 ignore_rest_of_line ();
4120 /* Parse an unwind_movsp directive. */
4123 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4129 if (!unwind.proc_start)
4130 as_bad (MISSING_FNSTART);
4132 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4135 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4136 ignore_rest_of_line ();
4140 /* Optional constant. */
4141 if (skip_past_comma (&input_line_pointer) != FAIL)
4143 if (immediate_for_directive (&offset) == FAIL)
4149 demand_empty_rest_of_line ();
4151 if (reg == REG_SP || reg == REG_PC)
4153 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4157 if (unwind.fp_reg != REG_SP)
4158 as_bad (_("unexpected .unwind_movsp directive"));
4160 /* Generate opcode to restore the value. */
4162 add_unwind_opcode (op, 1);
4164 /* Record the information for later. */
4165 unwind.fp_reg = reg;
4166 unwind.fp_offset = unwind.frame_size - offset;
4167 unwind.sp_restored = 1;
4170 /* Parse an unwind_pad directive. */
4173 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4177 if (!unwind.proc_start)
4178 as_bad (MISSING_FNSTART);
4180 if (immediate_for_directive (&offset) == FAIL)
4185 as_bad (_("stack increment must be multiple of 4"));
4186 ignore_rest_of_line ();
4190 /* Don't generate any opcodes, just record the details for later. */
4191 unwind.frame_size += offset;
4192 unwind.pending_offset += offset;
4194 demand_empty_rest_of_line ();
4197 /* Parse an unwind_setfp directive. */
4200 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4206 if (!unwind.proc_start)
4207 as_bad (MISSING_FNSTART);
4209 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4210 if (skip_past_comma (&input_line_pointer) == FAIL)
4213 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4215 if (fp_reg == FAIL || sp_reg == FAIL)
4217 as_bad (_("expected <reg>, <reg>"));
4218 ignore_rest_of_line ();
4222 /* Optional constant. */
4223 if (skip_past_comma (&input_line_pointer) != FAIL)
4225 if (immediate_for_directive (&offset) == FAIL)
4231 demand_empty_rest_of_line ();
4233 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4235 as_bad (_("register must be either sp or set by a previous"
4236 "unwind_movsp directive"));
4240 /* Don't generate any opcodes, just record the information for later. */
4241 unwind.fp_reg = fp_reg;
4243 if (sp_reg == REG_SP)
4244 unwind.fp_offset = unwind.frame_size - offset;
4246 unwind.fp_offset -= offset;
4249 /* Parse an unwind_raw directive. */
4252 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4255 /* This is an arbitrary limit. */
4256 unsigned char op[16];
4259 if (!unwind.proc_start)
4260 as_bad (MISSING_FNSTART);
4263 if (exp.X_op == O_constant
4264 && skip_past_comma (&input_line_pointer) != FAIL)
4266 unwind.frame_size += exp.X_add_number;
4270 exp.X_op = O_illegal;
4272 if (exp.X_op != O_constant)
4274 as_bad (_("expected <offset>, <opcode>"));
4275 ignore_rest_of_line ();
4281 /* Parse the opcode. */
4286 as_bad (_("unwind opcode too long"));
4287 ignore_rest_of_line ();
4289 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4291 as_bad (_("invalid unwind opcode"));
4292 ignore_rest_of_line ();
4295 op[count++] = exp.X_add_number;
4297 /* Parse the next byte. */
4298 if (skip_past_comma (&input_line_pointer) == FAIL)
4304 /* Add the opcode bytes in reverse order. */
4306 add_unwind_opcode (op[count], 1);
4308 demand_empty_rest_of_line ();
4312 /* Parse a .eabi_attribute directive. */
4315 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4317 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4319 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4320 attributes_set_explicitly[tag] = 1;
4323 /* Emit a tls fix for the symbol. */
4326 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4330 #ifdef md_flush_pending_output
4331 md_flush_pending_output ();
4334 #ifdef md_cons_align
4338 /* Since we're just labelling the code, there's no need to define a
4341 p = obstack_next_free (&frchain_now->frch_obstack);
4342 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4343 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4344 : BFD_RELOC_ARM_TLS_DESCSEQ);
4346 #endif /* OBJ_ELF */
4348 static void s_arm_arch (int);
4349 static void s_arm_object_arch (int);
4350 static void s_arm_cpu (int);
4351 static void s_arm_fpu (int);
4352 static void s_arm_arch_extension (int);
4357 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4364 if (exp.X_op == O_symbol)
4365 exp.X_op = O_secrel;
4367 emit_expr (&exp, 4);
4369 while (*input_line_pointer++ == ',');
4371 input_line_pointer--;
4372 demand_empty_rest_of_line ();
4376 /* This table describes all the machine specific pseudo-ops the assembler
4377 has to support. The fields are:
4378 pseudo-op name without dot
4379 function to call to execute this pseudo-op
4380 Integer arg to pass to the function. */
4382 const pseudo_typeS md_pseudo_table[] =
4384 /* Never called because '.req' does not start a line. */
4385 { "req", s_req, 0 },
4386 /* Following two are likewise never called. */
4389 { "unreq", s_unreq, 0 },
4390 { "bss", s_bss, 0 },
4391 { "align", s_align, 0 },
4392 { "arm", s_arm, 0 },
4393 { "thumb", s_thumb, 0 },
4394 { "code", s_code, 0 },
4395 { "force_thumb", s_force_thumb, 0 },
4396 { "thumb_func", s_thumb_func, 0 },
4397 { "thumb_set", s_thumb_set, 0 },
4398 { "even", s_even, 0 },
4399 { "ltorg", s_ltorg, 0 },
4400 { "pool", s_ltorg, 0 },
4401 { "syntax", s_syntax, 0 },
4402 { "cpu", s_arm_cpu, 0 },
4403 { "arch", s_arm_arch, 0 },
4404 { "object_arch", s_arm_object_arch, 0 },
4405 { "fpu", s_arm_fpu, 0 },
4406 { "arch_extension", s_arm_arch_extension, 0 },
4408 { "word", s_arm_elf_cons, 4 },
4409 { "long", s_arm_elf_cons, 4 },
4410 { "inst.n", s_arm_elf_inst, 2 },
4411 { "inst.w", s_arm_elf_inst, 4 },
4412 { "inst", s_arm_elf_inst, 0 },
4413 { "rel31", s_arm_rel31, 0 },
4414 { "fnstart", s_arm_unwind_fnstart, 0 },
4415 { "fnend", s_arm_unwind_fnend, 0 },
4416 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4417 { "personality", s_arm_unwind_personality, 0 },
4418 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4419 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4420 { "save", s_arm_unwind_save, 0 },
4421 { "vsave", s_arm_unwind_save, 1 },
4422 { "movsp", s_arm_unwind_movsp, 0 },
4423 { "pad", s_arm_unwind_pad, 0 },
4424 { "setfp", s_arm_unwind_setfp, 0 },
4425 { "unwind_raw", s_arm_unwind_raw, 0 },
4426 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4427 { "tlsdescseq", s_arm_tls_descseq, 0 },
4431 /* These are used for dwarf. */
4435 /* These are used for dwarf2. */
4436 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4437 { "loc", dwarf2_directive_loc, 0 },
4438 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4440 { "extend", float_cons, 'x' },
4441 { "ldouble", float_cons, 'x' },
4442 { "packed", float_cons, 'p' },
4444 {"secrel32", pe_directive_secrel, 0},
4449 /* Parser functions used exclusively in instruction operands. */
4451 /* Generic immediate-value read function for use in insn parsing.
4452 STR points to the beginning of the immediate (the leading #);
4453 VAL receives the value; if the value is outside [MIN, MAX]
4454 issue an error. PREFIX_OPT is true if the immediate prefix is
4458 parse_immediate (char **str, int *val, int min, int max,
4459 bfd_boolean prefix_opt)
4462 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4463 if (exp.X_op != O_constant)
4465 inst.error = _("constant expression required");
4469 if (exp.X_add_number < min || exp.X_add_number > max)
4471 inst.error = _("immediate value out of range");
4475 *val = exp.X_add_number;
4479 /* Less-generic immediate-value read function with the possibility of loading a
4480 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4481 instructions. Puts the result directly in inst.operands[i]. */
4484 parse_big_immediate (char **str, int i)
4489 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4491 if (exp.X_op == O_constant)
4493 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4494 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4495 O_constant. We have to be careful not to break compilation for
4496 32-bit X_add_number, though. */
4497 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4499 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4500 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4501 inst.operands[i].regisimm = 1;
4504 else if (exp.X_op == O_big
4505 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4507 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4509 /* Bignums have their least significant bits in
4510 generic_bignum[0]. Make sure we put 32 bits in imm and
4511 32 bits in reg, in a (hopefully) portable way. */
4512 gas_assert (parts != 0);
4514 /* Make sure that the number is not too big.
4515 PR 11972: Bignums can now be sign-extended to the
4516 size of a .octa so check that the out of range bits
4517 are all zero or all one. */
4518 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4520 LITTLENUM_TYPE m = -1;
4522 if (generic_bignum[parts * 2] != 0
4523 && generic_bignum[parts * 2] != m)
4526 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4527 if (generic_bignum[j] != generic_bignum[j-1])
4531 inst.operands[i].imm = 0;
4532 for (j = 0; j < parts; j++, idx++)
4533 inst.operands[i].imm |= generic_bignum[idx]
4534 << (LITTLENUM_NUMBER_OF_BITS * j);
4535 inst.operands[i].reg = 0;
4536 for (j = 0; j < parts; j++, idx++)
4537 inst.operands[i].reg |= generic_bignum[idx]
4538 << (LITTLENUM_NUMBER_OF_BITS * j);
4539 inst.operands[i].regisimm = 1;
4549 /* Returns the pseudo-register number of an FPA immediate constant,
4550 or FAIL if there isn't a valid constant here. */
4553 parse_fpa_immediate (char ** str)
4555 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4561 /* First try and match exact strings, this is to guarantee
4562 that some formats will work even for cross assembly. */
4564 for (i = 0; fp_const[i]; i++)
4566 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4570 *str += strlen (fp_const[i]);
4571 if (is_end_of_line[(unsigned char) **str])
4577 /* Just because we didn't get a match doesn't mean that the constant
4578 isn't valid, just that it is in a format that we don't
4579 automatically recognize. Try parsing it with the standard
4580 expression routines. */
4582 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4584 /* Look for a raw floating point number. */
4585 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4586 && is_end_of_line[(unsigned char) *save_in])
4588 for (i = 0; i < NUM_FLOAT_VALS; i++)
4590 for (j = 0; j < MAX_LITTLENUMS; j++)
4592 if (words[j] != fp_values[i][j])
4596 if (j == MAX_LITTLENUMS)
4604 /* Try and parse a more complex expression, this will probably fail
4605 unless the code uses a floating point prefix (eg "0f"). */
4606 save_in = input_line_pointer;
4607 input_line_pointer = *str;
4608 if (expression (&exp) == absolute_section
4609 && exp.X_op == O_big
4610 && exp.X_add_number < 0)
4612 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4614 if (gen_to_words (words, 5, (long) 15) == 0)
4616 for (i = 0; i < NUM_FLOAT_VALS; i++)
4618 for (j = 0; j < MAX_LITTLENUMS; j++)
4620 if (words[j] != fp_values[i][j])
4624 if (j == MAX_LITTLENUMS)
4626 *str = input_line_pointer;
4627 input_line_pointer = save_in;
4634 *str = input_line_pointer;
4635 input_line_pointer = save_in;
4636 inst.error = _("invalid FPA immediate expression");
4640 /* Returns 1 if a number has "quarter-precision" float format
4641 0baBbbbbbc defgh000 00000000 00000000. */
4644 is_quarter_float (unsigned imm)
4646 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4647 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4650 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4651 0baBbbbbbc defgh000 00000000 00000000.
4652 The zero and minus-zero cases need special handling, since they can't be
4653 encoded in the "quarter-precision" float format, but can nonetheless be
4654 loaded as integer constants. */
4657 parse_qfloat_immediate (char **ccp, int *immed)
4661 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4662 int found_fpchar = 0;
4664 skip_past_char (&str, '#');
4666 /* We must not accidentally parse an integer as a floating-point number. Make
4667 sure that the value we parse is not an integer by checking for special
4668 characters '.' or 'e'.
4669 FIXME: This is a horrible hack, but doing better is tricky because type
4670 information isn't in a very usable state at parse time. */
4672 skip_whitespace (fpnum);
4674 if (strncmp (fpnum, "0x", 2) == 0)
4678 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4679 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4689 if ((str = atof_ieee (str, 's', words)) != NULL)
4691 unsigned fpword = 0;
4694 /* Our FP word must be 32 bits (single-precision FP). */
4695 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4697 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4701 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4714 /* Shift operands. */
4717 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4720 struct asm_shift_name
4723 enum shift_kind kind;
4726 /* Third argument to parse_shift. */
4727 enum parse_shift_mode
4729 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4730 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4731 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4732 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4733 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4736 /* Parse a <shift> specifier on an ARM data processing instruction.
4737 This has three forms:
4739 (LSL|LSR|ASL|ASR|ROR) Rs
4740 (LSL|LSR|ASL|ASR|ROR) #imm
4743 Note that ASL is assimilated to LSL in the instruction encoding, and
4744 RRX to ROR #0 (which cannot be written as such). */
4747 parse_shift (char **str, int i, enum parse_shift_mode mode)
4749 const struct asm_shift_name *shift_name;
4750 enum shift_kind shift;
4755 for (p = *str; ISALPHA (*p); p++)
4760 inst.error = _("shift expression expected");
4764 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4767 if (shift_name == NULL)
4769 inst.error = _("shift expression expected");
4773 shift = shift_name->kind;
4777 case NO_SHIFT_RESTRICT:
4778 case SHIFT_IMMEDIATE: break;
4780 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4781 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4783 inst.error = _("'LSL' or 'ASR' required");
4788 case SHIFT_LSL_IMMEDIATE:
4789 if (shift != SHIFT_LSL)
4791 inst.error = _("'LSL' required");
4796 case SHIFT_ASR_IMMEDIATE:
4797 if (shift != SHIFT_ASR)
4799 inst.error = _("'ASR' required");
4807 if (shift != SHIFT_RRX)
4809 /* Whitespace can appear here if the next thing is a bare digit. */
4810 skip_whitespace (p);
4812 if (mode == NO_SHIFT_RESTRICT
4813 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4815 inst.operands[i].imm = reg;
4816 inst.operands[i].immisreg = 1;
4818 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4821 inst.operands[i].shift_kind = shift;
4822 inst.operands[i].shifted = 1;
4827 /* Parse a <shifter_operand> for an ARM data processing instruction:
4830 #<immediate>, <rotate>
4834 where <shift> is defined by parse_shift above, and <rotate> is a
4835 multiple of 2 between 0 and 30. Validation of immediate operands
4836 is deferred to md_apply_fix. */
4839 parse_shifter_operand (char **str, int i)
4844 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].reg = value;
4847 inst.operands[i].isreg = 1;
4849 /* parse_shift will override this if appropriate */
4850 inst.reloc.exp.X_op = O_constant;
4851 inst.reloc.exp.X_add_number = 0;
4853 if (skip_past_comma (str) == FAIL)
4856 /* Shift operation on register. */
4857 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4860 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4863 if (skip_past_comma (str) == SUCCESS)
4865 /* #x, y -- ie explicit rotation by Y. */
4866 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4869 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4871 inst.error = _("constant expression expected");
4875 value = exp.X_add_number;
4876 if (value < 0 || value > 30 || value % 2 != 0)
4878 inst.error = _("invalid rotation");
4881 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4883 inst.error = _("invalid constant");
4887 /* Encode as specified. */
4888 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4892 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4893 inst.reloc.pc_rel = 0;
4897 /* Group relocation information. Each entry in the table contains the
4898 textual name of the relocation as may appear in assembler source
4899 and must end with a colon.
4900 Along with this textual name are the relocation codes to be used if
4901 the corresponding instruction is an ALU instruction (ADD or SUB only),
4902 an LDR, an LDRS, or an LDC. */
4904 struct group_reloc_table_entry
4915 /* Varieties of non-ALU group relocation. */
4922 static struct group_reloc_table_entry group_reloc_table[] =
4923 { /* Program counter relative: */
4925 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4930 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4931 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4932 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4933 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4935 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4940 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4941 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4942 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4943 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4945 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4946 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4947 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4948 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4949 /* Section base relative */
4951 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4956 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4957 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4958 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4959 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4961 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4966 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4967 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4968 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4969 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4971 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4972 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4973 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4974 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4976 /* Given the address of a pointer pointing to the textual name of a group
4977 relocation as may appear in assembler source, attempt to find its details
4978 in group_reloc_table. The pointer will be updated to the character after
4979 the trailing colon. On failure, FAIL will be returned; SUCCESS
4980 otherwise. On success, *entry will be updated to point at the relevant
4981 group_reloc_table entry. */
4984 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4987 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4989 int length = strlen (group_reloc_table[i].name);
4991 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4992 && (*str)[length] == ':')
4994 *out = &group_reloc_table[i];
4995 *str += (length + 1);
5003 /* Parse a <shifter_operand> for an ARM data processing instruction
5004 (as for parse_shifter_operand) where group relocations are allowed:
5007 #<immediate>, <rotate>
5008 #:<group_reloc>:<expression>
5012 where <group_reloc> is one of the strings defined in group_reloc_table.
5013 The hashes are optional.
5015 Everything else is as for parse_shifter_operand. */
5017 static parse_operand_result
5018 parse_shifter_operand_group_reloc (char **str, int i)
5020 /* Determine if we have the sequence of characters #: or just :
5021 coming next. If we do, then we check for a group relocation.
5022 If we don't, punt the whole lot to parse_shifter_operand. */
5024 if (((*str)[0] == '#' && (*str)[1] == ':')
5025 || (*str)[0] == ':')
5027 struct group_reloc_table_entry *entry;
5029 if ((*str)[0] == '#')
5034 /* Try to parse a group relocation. Anything else is an error. */
5035 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5037 inst.error = _("unknown group relocation");
5038 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5041 /* We now have the group relocation table entry corresponding to
5042 the name in the assembler source. Next, we parse the expression. */
5043 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5044 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5046 /* Record the relocation type (always the ALU variant here). */
5047 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5048 gas_assert (inst.reloc.type != 0);
5050 return PARSE_OPERAND_SUCCESS;
5053 return parse_shifter_operand (str, i) == SUCCESS
5054 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5056 /* Never reached. */
5059 /* Parse a Neon alignment expression. Information is written to
5060 inst.operands[i]. We assume the initial ':' has been skipped.
5062 align .imm = align << 8, .immisalign=1, .preind=0 */
5063 static parse_operand_result
5064 parse_neon_alignment (char **str, int i)
5069 my_get_expression (&exp, &p, GE_NO_PREFIX);
5071 if (exp.X_op != O_constant)
5073 inst.error = _("alignment must be constant");
5074 return PARSE_OPERAND_FAIL;
5077 inst.operands[i].imm = exp.X_add_number << 8;
5078 inst.operands[i].immisalign = 1;
5079 /* Alignments are not pre-indexes. */
5080 inst.operands[i].preind = 0;
5083 return PARSE_OPERAND_SUCCESS;
5086 /* Parse all forms of an ARM address expression. Information is written
5087 to inst.operands[i] and/or inst.reloc.
5089 Preindexed addressing (.preind=1):
5091 [Rn, #offset] .reg=Rn .reloc.exp=offset
5092 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5093 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5094 .shift_kind=shift .reloc.exp=shift_imm
5096 These three may have a trailing ! which causes .writeback to be set also.
5098 Postindexed addressing (.postind=1, .writeback=1):
5100 [Rn], #offset .reg=Rn .reloc.exp=offset
5101 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5102 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5103 .shift_kind=shift .reloc.exp=shift_imm
5105 Unindexed addressing (.preind=0, .postind=0):
5107 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5111 [Rn]{!} shorthand for [Rn,#0]{!}
5112 =immediate .isreg=0 .reloc.exp=immediate
5113 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5115 It is the caller's responsibility to check for addressing modes not
5116 supported by the instruction, and to set inst.reloc.type. */
5118 static parse_operand_result
5119 parse_address_main (char **str, int i, int group_relocations,
5120 group_reloc_type group_type)
5125 if (skip_past_char (&p, '[') == FAIL)
5127 if (skip_past_char (&p, '=') == FAIL)
5129 /* Bare address - translate to PC-relative offset. */
5130 inst.reloc.pc_rel = 1;
5131 inst.operands[i].reg = REG_PC;
5132 inst.operands[i].isreg = 1;
5133 inst.operands[i].preind = 1;
5135 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5137 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5138 return PARSE_OPERAND_FAIL;
5141 return PARSE_OPERAND_SUCCESS;
5144 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5146 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5147 return PARSE_OPERAND_FAIL;
5149 inst.operands[i].reg = reg;
5150 inst.operands[i].isreg = 1;
5152 if (skip_past_comma (&p) == SUCCESS)
5154 inst.operands[i].preind = 1;
5157 else if (*p == '-') p++, inst.operands[i].negative = 1;
5159 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5161 inst.operands[i].imm = reg;
5162 inst.operands[i].immisreg = 1;
5164 if (skip_past_comma (&p) == SUCCESS)
5165 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5166 return PARSE_OPERAND_FAIL;
5168 else if (skip_past_char (&p, ':') == SUCCESS)
5170 /* FIXME: '@' should be used here, but it's filtered out by generic
5171 code before we get to see it here. This may be subject to
5173 parse_operand_result result = parse_neon_alignment (&p, i);
5175 if (result != PARSE_OPERAND_SUCCESS)
5180 if (inst.operands[i].negative)
5182 inst.operands[i].negative = 0;
5186 if (group_relocations
5187 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5189 struct group_reloc_table_entry *entry;
5191 /* Skip over the #: or : sequence. */
5197 /* Try to parse a group relocation. Anything else is an
5199 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5201 inst.error = _("unknown group relocation");
5202 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5205 /* We now have the group relocation table entry corresponding to
5206 the name in the assembler source. Next, we parse the
5208 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5209 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5211 /* Record the relocation type. */
5215 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5219 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5223 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5230 if (inst.reloc.type == 0)
5232 inst.error = _("this group relocation is not allowed on this instruction");
5233 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5239 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5240 return PARSE_OPERAND_FAIL;
5241 /* If the offset is 0, find out if it's a +0 or -0. */
5242 if (inst.reloc.exp.X_op == O_constant
5243 && inst.reloc.exp.X_add_number == 0)
5245 skip_whitespace (q);
5249 skip_whitespace (q);
5252 inst.operands[i].negative = 1;
5257 else if (skip_past_char (&p, ':') == SUCCESS)
5259 /* FIXME: '@' should be used here, but it's filtered out by generic code
5260 before we get to see it here. This may be subject to change. */
5261 parse_operand_result result = parse_neon_alignment (&p, i);
5263 if (result != PARSE_OPERAND_SUCCESS)
5267 if (skip_past_char (&p, ']') == FAIL)
5269 inst.error = _("']' expected");
5270 return PARSE_OPERAND_FAIL;
5273 if (skip_past_char (&p, '!') == SUCCESS)
5274 inst.operands[i].writeback = 1;
5276 else if (skip_past_comma (&p) == SUCCESS)
5278 if (skip_past_char (&p, '{') == SUCCESS)
5280 /* [Rn], {expr} - unindexed, with option */
5281 if (parse_immediate (&p, &inst.operands[i].imm,
5282 0, 255, TRUE) == FAIL)
5283 return PARSE_OPERAND_FAIL;
5285 if (skip_past_char (&p, '}') == FAIL)
5287 inst.error = _("'}' expected at end of 'option' field");
5288 return PARSE_OPERAND_FAIL;
5290 if (inst.operands[i].preind)
5292 inst.error = _("cannot combine index with option");
5293 return PARSE_OPERAND_FAIL;
5296 return PARSE_OPERAND_SUCCESS;
5300 inst.operands[i].postind = 1;
5301 inst.operands[i].writeback = 1;
5303 if (inst.operands[i].preind)
5305 inst.error = _("cannot combine pre- and post-indexing");
5306 return PARSE_OPERAND_FAIL;
5310 else if (*p == '-') p++, inst.operands[i].negative = 1;
5312 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5314 /* We might be using the immediate for alignment already. If we
5315 are, OR the register number into the low-order bits. */
5316 if (inst.operands[i].immisalign)
5317 inst.operands[i].imm |= reg;
5319 inst.operands[i].imm = reg;
5320 inst.operands[i].immisreg = 1;
5322 if (skip_past_comma (&p) == SUCCESS)
5323 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5324 return PARSE_OPERAND_FAIL;
5329 if (inst.operands[i].negative)
5331 inst.operands[i].negative = 0;
5334 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5335 return PARSE_OPERAND_FAIL;
5336 /* If the offset is 0, find out if it's a +0 or -0. */
5337 if (inst.reloc.exp.X_op == O_constant
5338 && inst.reloc.exp.X_add_number == 0)
5340 skip_whitespace (q);
5344 skip_whitespace (q);
5347 inst.operands[i].negative = 1;
5353 /* If at this point neither .preind nor .postind is set, we have a
5354 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5355 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5357 inst.operands[i].preind = 1;
5358 inst.reloc.exp.X_op = O_constant;
5359 inst.reloc.exp.X_add_number = 0;
5362 return PARSE_OPERAND_SUCCESS;
5366 parse_address (char **str, int i)
5368 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5372 static parse_operand_result
5373 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5375 return parse_address_main (str, i, 1, type);
5378 /* Parse an operand for a MOVW or MOVT instruction. */
5380 parse_half (char **str)
5385 skip_past_char (&p, '#');
5386 if (strncasecmp (p, ":lower16:", 9) == 0)
5387 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5388 else if (strncasecmp (p, ":upper16:", 9) == 0)
5389 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5391 if (inst.reloc.type != BFD_RELOC_UNUSED)
5394 skip_whitespace (p);
5397 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5400 if (inst.reloc.type == BFD_RELOC_UNUSED)
5402 if (inst.reloc.exp.X_op != O_constant)
5404 inst.error = _("constant expression expected");
5407 if (inst.reloc.exp.X_add_number < 0
5408 || inst.reloc.exp.X_add_number > 0xffff)
5410 inst.error = _("immediate value out of range");
5418 /* Miscellaneous. */
5420 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5421 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5423 parse_psr (char **str, bfd_boolean lhs)
5426 unsigned long psr_field;
5427 const struct asm_psr *psr;
5429 bfd_boolean is_apsr = FALSE;
5430 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5432 /* PR gas/12698: If the user has specified -march=all then m_profile will
5433 be TRUE, but we want to ignore it in this case as we are building for any
5434 CPU type, including non-m variants. */
5435 if (selected_cpu.core == arm_arch_any.core)
5438 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5439 feature for ease of use and backwards compatibility. */
5441 if (strncasecmp (p, "SPSR", 4) == 0)
5444 goto unsupported_psr;
5446 psr_field = SPSR_BIT;
5448 else if (strncasecmp (p, "CPSR", 4) == 0)
5451 goto unsupported_psr;
5455 else if (strncasecmp (p, "APSR", 4) == 0)
5457 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5458 and ARMv7-R architecture CPUs. */
5467 while (ISALNUM (*p) || *p == '_');
5469 if (strncasecmp (start, "iapsr", 5) == 0
5470 || strncasecmp (start, "eapsr", 5) == 0
5471 || strncasecmp (start, "xpsr", 4) == 0
5472 || strncasecmp (start, "psr", 3) == 0)
5473 p = start + strcspn (start, "rR") + 1;
5475 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5481 /* If APSR is being written, a bitfield may be specified. Note that
5482 APSR itself is handled above. */
5483 if (psr->field <= 3)
5485 psr_field = psr->field;
5491 /* M-profile MSR instructions have the mask field set to "10", except
5492 *PSR variants which modify APSR, which may use a different mask (and
5493 have been handled already). Do that by setting the PSR_f field
5495 return psr->field | (lhs ? PSR_f : 0);
5498 goto unsupported_psr;
5504 /* A suffix follows. */
5510 while (ISALNUM (*p) || *p == '_');
5514 /* APSR uses a notation for bits, rather than fields. */
5515 unsigned int nzcvq_bits = 0;
5516 unsigned int g_bit = 0;
5519 for (bit = start; bit != p; bit++)
5521 switch (TOLOWER (*bit))
5524 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5528 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5532 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5536 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5540 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5544 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5548 inst.error = _("unexpected bit specified after APSR");
5553 if (nzcvq_bits == 0x1f)
5558 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5560 inst.error = _("selected processor does not "
5561 "support DSP extension");
5568 if ((nzcvq_bits & 0x20) != 0
5569 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5570 || (g_bit & 0x2) != 0)
5572 inst.error = _("bad bitmask specified after APSR");
5578 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5583 psr_field |= psr->field;
5589 goto error; /* Garbage after "[CS]PSR". */
5591 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5592 is deprecated, but allow it anyway. */
5596 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5599 else if (!m_profile)
5600 /* These bits are never right for M-profile devices: don't set them
5601 (only code paths which read/write APSR reach here). */
5602 psr_field |= (PSR_c | PSR_f);
5608 inst.error = _("selected processor does not support requested special "
5609 "purpose register");
5613 inst.error = _("flag for {c}psr instruction expected");
5617 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5618 value suitable for splatting into the AIF field of the instruction. */
5621 parse_cps_flags (char **str)
5630 case '\0': case ',':
5633 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5634 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5635 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5638 inst.error = _("unrecognized CPS flag");
5643 if (saw_a_flag == 0)
5645 inst.error = _("missing CPS flags");
5653 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5654 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5657 parse_endian_specifier (char **str)
5662 if (strncasecmp (s, "BE", 2))
5664 else if (strncasecmp (s, "LE", 2))
5668 inst.error = _("valid endian specifiers are be or le");
5672 if (ISALNUM (s[2]) || s[2] == '_')
5674 inst.error = _("valid endian specifiers are be or le");
5679 return little_endian;
5682 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5683 value suitable for poking into the rotate field of an sxt or sxta
5684 instruction, or FAIL on error. */
5687 parse_ror (char **str)
5692 if (strncasecmp (s, "ROR", 3) == 0)
5696 inst.error = _("missing rotation field after comma");
5700 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5705 case 0: *str = s; return 0x0;
5706 case 8: *str = s; return 0x1;
5707 case 16: *str = s; return 0x2;
5708 case 24: *str = s; return 0x3;
5711 inst.error = _("rotation can only be 0, 8, 16, or 24");
5716 /* Parse a conditional code (from conds[] below). The value returned is in the
5717 range 0 .. 14, or FAIL. */
5719 parse_cond (char **str)
5722 const struct asm_cond *c;
5724 /* Condition codes are always 2 characters, so matching up to
5725 3 characters is sufficient. */
5730 while (ISALPHA (*q) && n < 3)
5732 cond[n] = TOLOWER (*q);
5737 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5740 inst.error = _("condition required");
5748 /* Parse an option for a barrier instruction. Returns the encoding for the
5751 parse_barrier (char **str)
5754 const struct asm_barrier_opt *o;
5757 while (ISALPHA (*q))
5760 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5769 /* Parse the operands of a table branch instruction. Similar to a memory
5772 parse_tb (char **str)
5777 if (skip_past_char (&p, '[') == FAIL)
5779 inst.error = _("'[' expected");
5783 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5785 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5788 inst.operands[0].reg = reg;
5790 if (skip_past_comma (&p) == FAIL)
5792 inst.error = _("',' expected");
5796 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5798 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5801 inst.operands[0].imm = reg;
5803 if (skip_past_comma (&p) == SUCCESS)
5805 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5807 if (inst.reloc.exp.X_add_number != 1)
5809 inst.error = _("invalid shift");
5812 inst.operands[0].shifted = 1;
5815 if (skip_past_char (&p, ']') == FAIL)
5817 inst.error = _("']' expected");
5824 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5825 information on the types the operands can take and how they are encoded.
5826 Up to four operands may be read; this function handles setting the
5827 ".present" field for each read operand itself.
5828 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5829 else returns FAIL. */
5832 parse_neon_mov (char **str, int *which_operand)
5834 int i = *which_operand, val;
5835 enum arm_reg_type rtype;
5837 struct neon_type_el optype;
5839 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5841 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5842 inst.operands[i].reg = val;
5843 inst.operands[i].isscalar = 1;
5844 inst.operands[i].vectype = optype;
5845 inst.operands[i++].present = 1;
5847 if (skip_past_comma (&ptr) == FAIL)
5850 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5853 inst.operands[i].reg = val;
5854 inst.operands[i].isreg = 1;
5855 inst.operands[i].present = 1;
5857 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5860 /* Cases 0, 1, 2, 3, 5 (D only). */
5861 if (skip_past_comma (&ptr) == FAIL)
5864 inst.operands[i].reg = val;
5865 inst.operands[i].isreg = 1;
5866 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5867 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5868 inst.operands[i].isvec = 1;
5869 inst.operands[i].vectype = optype;
5870 inst.operands[i++].present = 1;
5872 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5874 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5875 Case 13: VMOV <Sd>, <Rm> */
5876 inst.operands[i].reg = val;
5877 inst.operands[i].isreg = 1;
5878 inst.operands[i].present = 1;
5880 if (rtype == REG_TYPE_NQ)
5882 first_error (_("can't use Neon quad register here"));
5885 else if (rtype != REG_TYPE_VFS)
5888 if (skip_past_comma (&ptr) == FAIL)
5890 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5892 inst.operands[i].reg = val;
5893 inst.operands[i].isreg = 1;
5894 inst.operands[i].present = 1;
5897 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5900 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5901 Case 1: VMOV<c><q> <Dd>, <Dm>
5902 Case 8: VMOV.F32 <Sd>, <Sm>
5903 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5905 inst.operands[i].reg = val;
5906 inst.operands[i].isreg = 1;
5907 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5908 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5909 inst.operands[i].isvec = 1;
5910 inst.operands[i].vectype = optype;
5911 inst.operands[i].present = 1;
5913 if (skip_past_comma (&ptr) == SUCCESS)
5918 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5921 inst.operands[i].reg = val;
5922 inst.operands[i].isreg = 1;
5923 inst.operands[i++].present = 1;
5925 if (skip_past_comma (&ptr) == FAIL)
5928 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5931 inst.operands[i].reg = val;
5932 inst.operands[i].isreg = 1;
5933 inst.operands[i++].present = 1;
5936 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5937 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5938 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5939 Case 10: VMOV.F32 <Sd>, #<imm>
5940 Case 11: VMOV.F64 <Dd>, #<imm> */
5941 inst.operands[i].immisfloat = 1;
5942 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5943 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5944 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5948 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5952 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5955 inst.operands[i].reg = val;
5956 inst.operands[i].isreg = 1;
5957 inst.operands[i++].present = 1;
5959 if (skip_past_comma (&ptr) == FAIL)
5962 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5964 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5965 inst.operands[i].reg = val;
5966 inst.operands[i].isscalar = 1;
5967 inst.operands[i].present = 1;
5968 inst.operands[i].vectype = optype;
5970 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5972 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5973 inst.operands[i].reg = val;
5974 inst.operands[i].isreg = 1;
5975 inst.operands[i++].present = 1;
5977 if (skip_past_comma (&ptr) == FAIL)
5980 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5983 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i].isvec = 1;
5990 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5991 inst.operands[i].vectype = optype;
5992 inst.operands[i].present = 1;
5994 if (rtype == REG_TYPE_VFS)
5998 if (skip_past_comma (&ptr) == FAIL)
6000 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6003 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6006 inst.operands[i].reg = val;
6007 inst.operands[i].isreg = 1;
6008 inst.operands[i].isvec = 1;
6009 inst.operands[i].issingle = 1;
6010 inst.operands[i].vectype = optype;
6011 inst.operands[i].present = 1;
6014 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6018 inst.operands[i].reg = val;
6019 inst.operands[i].isreg = 1;
6020 inst.operands[i].isvec = 1;
6021 inst.operands[i].issingle = 1;
6022 inst.operands[i].vectype = optype;
6023 inst.operands[i++].present = 1;
6028 first_error (_("parse error"));
6032 /* Successfully parsed the operands. Update args. */
6038 first_error (_("expected comma"));
6042 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6046 /* Use this macro when the operand constraints are different
6047 for ARM and THUMB (e.g. ldrd). */
6048 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6049 ((arm_operand) | ((thumb_operand) << 16))
6051 /* Matcher codes for parse_operands. */
6052 enum operand_parse_code
6054 OP_stop, /* end of line */
6056 OP_RR, /* ARM register */
6057 OP_RRnpc, /* ARM register, not r15 */
6058 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6059 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6060 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6061 optional trailing ! */
6062 OP_RRw, /* ARM register, not r15, optional trailing ! */
6063 OP_RCP, /* Coprocessor number */
6064 OP_RCN, /* Coprocessor register */
6065 OP_RF, /* FPA register */
6066 OP_RVS, /* VFP single precision register */
6067 OP_RVD, /* VFP double precision register (0..15) */
6068 OP_RND, /* Neon double precision register (0..31) */
6069 OP_RNQ, /* Neon quad precision register */
6070 OP_RVSD, /* VFP single or double precision register */
6071 OP_RNDQ, /* Neon double or quad precision register */
6072 OP_RNSDQ, /* Neon single, double or quad precision register */
6073 OP_RNSC, /* Neon scalar D[X] */
6074 OP_RVC, /* VFP control register */
6075 OP_RMF, /* Maverick F register */
6076 OP_RMD, /* Maverick D register */
6077 OP_RMFX, /* Maverick FX register */
6078 OP_RMDX, /* Maverick DX register */
6079 OP_RMAX, /* Maverick AX register */
6080 OP_RMDS, /* Maverick DSPSC register */
6081 OP_RIWR, /* iWMMXt wR register */
6082 OP_RIWC, /* iWMMXt wC register */
6083 OP_RIWG, /* iWMMXt wCG register */
6084 OP_RXA, /* XScale accumulator register */
6086 OP_REGLST, /* ARM register list */
6087 OP_VRSLST, /* VFP single-precision register list */
6088 OP_VRDLST, /* VFP double-precision register list */
6089 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6090 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6091 OP_NSTRLST, /* Neon element/structure list */
6093 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6094 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6095 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6096 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6097 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6098 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6099 OP_VMOV, /* Neon VMOV operands. */
6100 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6101 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6102 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6104 OP_I0, /* immediate zero */
6105 OP_I7, /* immediate value 0 .. 7 */
6106 OP_I15, /* 0 .. 15 */
6107 OP_I16, /* 1 .. 16 */
6108 OP_I16z, /* 0 .. 16 */
6109 OP_I31, /* 0 .. 31 */
6110 OP_I31w, /* 0 .. 31, optional trailing ! */
6111 OP_I32, /* 1 .. 32 */
6112 OP_I32z, /* 0 .. 32 */
6113 OP_I63, /* 0 .. 63 */
6114 OP_I63s, /* -64 .. 63 */
6115 OP_I64, /* 1 .. 64 */
6116 OP_I64z, /* 0 .. 64 */
6117 OP_I255, /* 0 .. 255 */
6119 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6120 OP_I7b, /* 0 .. 7 */
6121 OP_I15b, /* 0 .. 15 */
6122 OP_I31b, /* 0 .. 31 */
6124 OP_SH, /* shifter operand */
6125 OP_SHG, /* shifter operand with possible group relocation */
6126 OP_ADDR, /* Memory address expression (any mode) */
6127 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6128 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6129 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6130 OP_EXP, /* arbitrary expression */
6131 OP_EXPi, /* same, with optional immediate prefix */
6132 OP_EXPr, /* same, with optional relocation suffix */
6133 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6135 OP_CPSF, /* CPS flags */
6136 OP_ENDI, /* Endianness specifier */
6137 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6138 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6139 OP_COND, /* conditional code */
6140 OP_TB, /* Table branch. */
6142 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6144 OP_RRnpc_I0, /* ARM register or literal 0 */
6145 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6146 OP_RR_EXi, /* ARM register or expression with imm prefix */
6147 OP_RF_IF, /* FPA register or immediate */
6148 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6149 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6151 /* Optional operands. */
6152 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6153 OP_oI31b, /* 0 .. 31 */
6154 OP_oI32b, /* 1 .. 32 */
6155 OP_oI32z, /* 0 .. 32 */
6156 OP_oIffffb, /* 0 .. 65535 */
6157 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6159 OP_oRR, /* ARM register */
6160 OP_oRRnpc, /* ARM register, not the PC */
6161 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6162 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6163 OP_oRND, /* Optional Neon double precision register */
6164 OP_oRNQ, /* Optional Neon quad precision register */
6165 OP_oRNDQ, /* Optional Neon double or quad precision register */
6166 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6167 OP_oSHll, /* LSL immediate */
6168 OP_oSHar, /* ASR immediate */
6169 OP_oSHllar, /* LSL or ASR immediate */
6170 OP_oROR, /* ROR 0/8/16/24 */
6171 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6173 /* Some pre-defined mixed (ARM/THUMB) operands. */
6174 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6175 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6176 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6178 OP_FIRST_OPTIONAL = OP_oI7b
6181 /* Generic instruction operand parser. This does no encoding and no
6182 semantic validation; it merely squirrels values away in the inst
6183 structure. Returns SUCCESS or FAIL depending on whether the
6184 specified grammar matched. */
6186 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6188 unsigned const int *upat = pattern;
6189 char *backtrack_pos = 0;
6190 const char *backtrack_error = 0;
6191 int i, val, backtrack_index = 0;
6192 enum arm_reg_type rtype;
6193 parse_operand_result result;
6194 unsigned int op_parse_code;
6196 #define po_char_or_fail(chr) \
6199 if (skip_past_char (&str, chr) == FAIL) \
6204 #define po_reg_or_fail(regtype) \
6207 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6208 & inst.operands[i].vectype); \
6211 first_error (_(reg_expected_msgs[regtype])); \
6214 inst.operands[i].reg = val; \
6215 inst.operands[i].isreg = 1; \
6216 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6217 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6218 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6219 || rtype == REG_TYPE_VFD \
6220 || rtype == REG_TYPE_NQ); \
6224 #define po_reg_or_goto(regtype, label) \
6227 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6228 & inst.operands[i].vectype); \
6232 inst.operands[i].reg = val; \
6233 inst.operands[i].isreg = 1; \
6234 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6235 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6236 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6237 || rtype == REG_TYPE_VFD \
6238 || rtype == REG_TYPE_NQ); \
6242 #define po_imm_or_fail(min, max, popt) \
6245 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6247 inst.operands[i].imm = val; \
6251 #define po_scalar_or_goto(elsz, label) \
6254 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6257 inst.operands[i].reg = val; \
6258 inst.operands[i].isscalar = 1; \
6262 #define po_misc_or_fail(expr) \
6270 #define po_misc_or_fail_no_backtrack(expr) \
6274 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6275 backtrack_pos = 0; \
6276 if (result != PARSE_OPERAND_SUCCESS) \
6281 #define po_barrier_or_imm(str) \
6284 val = parse_barrier (&str); \
6287 if (ISALPHA (*str)) \
6294 if ((inst.instruction & 0xf0) == 0x60 \
6297 /* ISB can only take SY as an option. */ \
6298 inst.error = _("invalid barrier type"); \
6305 skip_whitespace (str);
6307 for (i = 0; upat[i] != OP_stop; i++)
6309 op_parse_code = upat[i];
6310 if (op_parse_code >= 1<<16)
6311 op_parse_code = thumb ? (op_parse_code >> 16)
6312 : (op_parse_code & ((1<<16)-1));
6314 if (op_parse_code >= OP_FIRST_OPTIONAL)
6316 /* Remember where we are in case we need to backtrack. */
6317 gas_assert (!backtrack_pos);
6318 backtrack_pos = str;
6319 backtrack_error = inst.error;
6320 backtrack_index = i;
6323 if (i > 0 && (i > 1 || inst.operands[0].present))
6324 po_char_or_fail (',');
6326 switch (op_parse_code)
6334 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6335 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6336 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6337 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6338 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6339 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6341 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6343 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6345 /* Also accept generic coprocessor regs for unknown registers. */
6347 po_reg_or_fail (REG_TYPE_CN);
6349 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6350 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6351 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6352 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6353 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6354 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6355 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6356 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6357 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6358 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6360 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6362 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6363 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6365 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6367 /* Neon scalar. Using an element size of 8 means that some invalid
6368 scalars are accepted here, so deal with those in later code. */
6369 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6373 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6376 po_imm_or_fail (0, 0, TRUE);
6381 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6386 po_scalar_or_goto (8, try_rr);
6389 po_reg_or_fail (REG_TYPE_RN);
6395 po_scalar_or_goto (8, try_nsdq);
6398 po_reg_or_fail (REG_TYPE_NSDQ);
6404 po_scalar_or_goto (8, try_ndq);
6407 po_reg_or_fail (REG_TYPE_NDQ);
6413 po_scalar_or_goto (8, try_vfd);
6416 po_reg_or_fail (REG_TYPE_VFD);
6421 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6422 not careful then bad things might happen. */
6423 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6428 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6431 /* There's a possibility of getting a 64-bit immediate here, so
6432 we need special handling. */
6433 if (parse_big_immediate (&str, i) == FAIL)
6435 inst.error = _("immediate value is out of range");
6443 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6446 po_imm_or_fail (0, 63, TRUE);
6451 po_char_or_fail ('[');
6452 po_reg_or_fail (REG_TYPE_RN);
6453 po_char_or_fail (']');
6459 po_reg_or_fail (REG_TYPE_RN);
6460 if (skip_past_char (&str, '!') == SUCCESS)
6461 inst.operands[i].writeback = 1;
6465 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6466 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6467 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6468 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6469 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6470 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6471 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6472 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6473 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6474 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6475 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6476 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6478 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6480 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6481 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6483 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6484 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6485 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6486 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6488 /* Immediate variants */
6490 po_char_or_fail ('{');
6491 po_imm_or_fail (0, 255, TRUE);
6492 po_char_or_fail ('}');
6496 /* The expression parser chokes on a trailing !, so we have
6497 to find it first and zap it. */
6500 while (*s && *s != ',')
6505 inst.operands[i].writeback = 1;
6507 po_imm_or_fail (0, 31, TRUE);
6515 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6520 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6525 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6527 if (inst.reloc.exp.X_op == O_symbol)
6529 val = parse_reloc (&str);
6532 inst.error = _("unrecognized relocation suffix");
6535 else if (val != BFD_RELOC_UNUSED)
6537 inst.operands[i].imm = val;
6538 inst.operands[i].hasreloc = 1;
6543 /* Operand for MOVW or MOVT. */
6545 po_misc_or_fail (parse_half (&str));
6548 /* Register or expression. */
6549 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6550 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6552 /* Register or immediate. */
6553 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6554 I0: po_imm_or_fail (0, 0, FALSE); break;
6556 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6558 if (!is_immediate_prefix (*str))
6561 val = parse_fpa_immediate (&str);
6564 /* FPA immediates are encoded as registers 8-15.
6565 parse_fpa_immediate has already applied the offset. */
6566 inst.operands[i].reg = val;
6567 inst.operands[i].isreg = 1;
6570 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6571 I32z: po_imm_or_fail (0, 32, FALSE); break;
6573 /* Two kinds of register. */
6576 struct reg_entry *rege = arm_reg_parse_multi (&str);
6578 || (rege->type != REG_TYPE_MMXWR
6579 && rege->type != REG_TYPE_MMXWC
6580 && rege->type != REG_TYPE_MMXWCG))
6582 inst.error = _("iWMMXt data or control register expected");
6585 inst.operands[i].reg = rege->number;
6586 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6592 struct reg_entry *rege = arm_reg_parse_multi (&str);
6594 || (rege->type != REG_TYPE_MMXWC
6595 && rege->type != REG_TYPE_MMXWCG))
6597 inst.error = _("iWMMXt control register expected");
6600 inst.operands[i].reg = rege->number;
6601 inst.operands[i].isreg = 1;
6606 case OP_CPSF: val = parse_cps_flags (&str); break;
6607 case OP_ENDI: val = parse_endian_specifier (&str); break;
6608 case OP_oROR: val = parse_ror (&str); break;
6609 case OP_COND: val = parse_cond (&str); break;
6610 case OP_oBARRIER_I15:
6611 po_barrier_or_imm (str); break;
6613 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6619 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6620 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6622 inst.error = _("Banked registers are not available with this "
6628 val = parse_psr (&str, op_parse_code == OP_wPSR);
6632 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6635 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6637 if (strncasecmp (str, "APSR_", 5) == 0)
6644 case 'c': found = (found & 1) ? 16 : found | 1; break;
6645 case 'n': found = (found & 2) ? 16 : found | 2; break;
6646 case 'z': found = (found & 4) ? 16 : found | 4; break;
6647 case 'v': found = (found & 8) ? 16 : found | 8; break;
6648 default: found = 16;
6652 inst.operands[i].isvec = 1;
6653 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6654 inst.operands[i].reg = REG_PC;
6661 po_misc_or_fail (parse_tb (&str));
6664 /* Register lists. */
6666 val = parse_reg_list (&str);
6669 inst.operands[1].writeback = 1;
6675 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6679 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6683 /* Allow Q registers too. */
6684 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6689 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6691 inst.operands[i].issingle = 1;
6696 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6701 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6702 &inst.operands[i].vectype);
6705 /* Addressing modes */
6707 po_misc_or_fail (parse_address (&str, i));
6711 po_misc_or_fail_no_backtrack (
6712 parse_address_group_reloc (&str, i, GROUP_LDR));
6716 po_misc_or_fail_no_backtrack (
6717 parse_address_group_reloc (&str, i, GROUP_LDRS));
6721 po_misc_or_fail_no_backtrack (
6722 parse_address_group_reloc (&str, i, GROUP_LDC));
6726 po_misc_or_fail (parse_shifter_operand (&str, i));
6730 po_misc_or_fail_no_backtrack (
6731 parse_shifter_operand_group_reloc (&str, i));
6735 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6739 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6743 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6747 as_fatal (_("unhandled operand code %d"), op_parse_code);
6750 /* Various value-based sanity checks and shared operations. We
6751 do not signal immediate failures for the register constraints;
6752 this allows a syntax error to take precedence. */
6753 switch (op_parse_code)
6761 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6762 inst.error = BAD_PC;
6767 if (inst.operands[i].isreg)
6769 if (inst.operands[i].reg == REG_PC)
6770 inst.error = BAD_PC;
6771 else if (inst.operands[i].reg == REG_SP)
6772 inst.error = BAD_SP;
6777 if (inst.operands[i].isreg
6778 && inst.operands[i].reg == REG_PC
6779 && (inst.operands[i].writeback || thumb))
6780 inst.error = BAD_PC;
6789 case OP_oBARRIER_I15:
6798 inst.operands[i].imm = val;
6805 /* If we get here, this operand was successfully parsed. */
6806 inst.operands[i].present = 1;
6810 inst.error = BAD_ARGS;
6815 /* The parse routine should already have set inst.error, but set a
6816 default here just in case. */
6818 inst.error = _("syntax error");
6822 /* Do not backtrack over a trailing optional argument that
6823 absorbed some text. We will only fail again, with the
6824 'garbage following instruction' error message, which is
6825 probably less helpful than the current one. */
6826 if (backtrack_index == i && backtrack_pos != str
6827 && upat[i+1] == OP_stop)
6830 inst.error = _("syntax error");
6834 /* Try again, skipping the optional argument at backtrack_pos. */
6835 str = backtrack_pos;
6836 inst.error = backtrack_error;
6837 inst.operands[backtrack_index].present = 0;
6838 i = backtrack_index;
6842 /* Check that we have parsed all the arguments. */
6843 if (*str != '\0' && !inst.error)
6844 inst.error = _("garbage following instruction");
6846 return inst.error ? FAIL : SUCCESS;
6849 #undef po_char_or_fail
6850 #undef po_reg_or_fail
6851 #undef po_reg_or_goto
6852 #undef po_imm_or_fail
6853 #undef po_scalar_or_fail
6854 #undef po_barrier_or_imm
6856 /* Shorthand macro for instruction encoding functions issuing errors. */
6857 #define constraint(expr, err) \
6868 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6869 instructions are unpredictable if these registers are used. This
6870 is the BadReg predicate in ARM's Thumb-2 documentation. */
6871 #define reject_bad_reg(reg) \
6873 if (reg == REG_SP || reg == REG_PC) \
6875 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6880 /* If REG is R13 (the stack pointer), warn that its use is
6882 #define warn_deprecated_sp(reg) \
6884 if (warn_on_deprecated && reg == REG_SP) \
6885 as_warn (_("use of r13 is deprecated")); \
6888 /* Functions for operand encoding. ARM, then Thumb. */
6890 #define rotate_left(v, n) (v << n | v >> (32 - n))
6892 /* If VAL can be encoded in the immediate field of an ARM instruction,
6893 return the encoded form. Otherwise, return FAIL. */
6896 encode_arm_immediate (unsigned int val)
6900 for (i = 0; i < 32; i += 2)
6901 if ((a = rotate_left (val, i)) <= 0xff)
6902 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6907 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6908 return the encoded form. Otherwise, return FAIL. */
6910 encode_thumb32_immediate (unsigned int val)
6917 for (i = 1; i <= 24; i++)
6920 if ((val & ~(0xff << i)) == 0)
6921 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6925 if (val == ((a << 16) | a))
6927 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6931 if (val == ((a << 16) | a))
6932 return 0x200 | (a >> 8);
6936 /* Encode a VFP SP or DP register number into inst.instruction. */
6939 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6941 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6944 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6947 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6950 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6955 first_error (_("D register out of range for selected VFP version"));
6963 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6967 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6971 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6975 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6979 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6983 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6991 /* Encode a <shift> in an ARM-format instruction. The immediate,
6992 if any, is handled by md_apply_fix. */
6994 encode_arm_shift (int i)
6996 if (inst.operands[i].shift_kind == SHIFT_RRX)
6997 inst.instruction |= SHIFT_ROR << 5;
7000 inst.instruction |= inst.operands[i].shift_kind << 5;
7001 if (inst.operands[i].immisreg)
7003 inst.instruction |= SHIFT_BY_REG;
7004 inst.instruction |= inst.operands[i].imm << 8;
7007 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7012 encode_arm_shifter_operand (int i)
7014 if (inst.operands[i].isreg)
7016 inst.instruction |= inst.operands[i].reg;
7017 encode_arm_shift (i);
7021 inst.instruction |= INST_IMMEDIATE;
7022 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7023 inst.instruction |= inst.operands[i].imm;
7027 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7029 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7031 gas_assert (inst.operands[i].isreg);
7032 inst.instruction |= inst.operands[i].reg << 16;
7034 if (inst.operands[i].preind)
7038 inst.error = _("instruction does not accept preindexed addressing");
7041 inst.instruction |= PRE_INDEX;
7042 if (inst.operands[i].writeback)
7043 inst.instruction |= WRITE_BACK;
7046 else if (inst.operands[i].postind)
7048 gas_assert (inst.operands[i].writeback);
7050 inst.instruction |= WRITE_BACK;
7052 else /* unindexed - only for coprocessor */
7054 inst.error = _("instruction does not accept unindexed addressing");
7058 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7059 && (((inst.instruction & 0x000f0000) >> 16)
7060 == ((inst.instruction & 0x0000f000) >> 12)))
7061 as_warn ((inst.instruction & LOAD_BIT)
7062 ? _("destination register same as write-back base")
7063 : _("source register same as write-back base"));
7066 /* inst.operands[i] was set up by parse_address. Encode it into an
7067 ARM-format mode 2 load or store instruction. If is_t is true,
7068 reject forms that cannot be used with a T instruction (i.e. not
7071 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7073 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7075 encode_arm_addr_mode_common (i, is_t);
7077 if (inst.operands[i].immisreg)
7079 constraint ((inst.operands[i].imm == REG_PC
7080 || (is_pc && inst.operands[i].writeback)),
7082 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7083 inst.instruction |= inst.operands[i].imm;
7084 if (!inst.operands[i].negative)
7085 inst.instruction |= INDEX_UP;
7086 if (inst.operands[i].shifted)
7088 if (inst.operands[i].shift_kind == SHIFT_RRX)
7089 inst.instruction |= SHIFT_ROR << 5;
7092 inst.instruction |= inst.operands[i].shift_kind << 5;
7093 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7097 else /* immediate offset in inst.reloc */
7099 if (is_pc && !inst.reloc.pc_rel)
7101 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7103 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7104 cannot use PC in addressing.
7105 PC cannot be used in writeback addressing, either. */
7106 constraint ((is_t || inst.operands[i].writeback),
7109 /* Use of PC in str is deprecated for ARMv7. */
7110 if (warn_on_deprecated
7112 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7113 as_warn (_("use of PC in this instruction is deprecated"));
7116 if (inst.reloc.type == BFD_RELOC_UNUSED)
7118 /* Prefer + for zero encoded value. */
7119 if (!inst.operands[i].negative)
7120 inst.instruction |= INDEX_UP;
7121 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7126 /* inst.operands[i] was set up by parse_address. Encode it into an
7127 ARM-format mode 3 load or store instruction. Reject forms that
7128 cannot be used with such instructions. If is_t is true, reject
7129 forms that cannot be used with a T instruction (i.e. not
7132 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7134 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7136 inst.error = _("instruction does not accept scaled register index");
7140 encode_arm_addr_mode_common (i, is_t);
7142 if (inst.operands[i].immisreg)
7144 constraint ((inst.operands[i].imm == REG_PC
7145 || inst.operands[i].reg == REG_PC),
7147 inst.instruction |= inst.operands[i].imm;
7148 if (!inst.operands[i].negative)
7149 inst.instruction |= INDEX_UP;
7151 else /* immediate offset in inst.reloc */
7153 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7154 && inst.operands[i].writeback),
7156 inst.instruction |= HWOFFSET_IMM;
7157 if (inst.reloc.type == BFD_RELOC_UNUSED)
7159 /* Prefer + for zero encoded value. */
7160 if (!inst.operands[i].negative)
7161 inst.instruction |= INDEX_UP;
7163 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7168 /* inst.operands[i] was set up by parse_address. Encode it into an
7169 ARM-format instruction. Reject all forms which cannot be encoded
7170 into a coprocessor load/store instruction. If wb_ok is false,
7171 reject use of writeback; if unind_ok is false, reject use of
7172 unindexed addressing. If reloc_override is not 0, use it instead
7173 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7174 (in which case it is preserved). */
7177 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7179 inst.instruction |= inst.operands[i].reg << 16;
7181 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7183 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7185 gas_assert (!inst.operands[i].writeback);
7188 inst.error = _("instruction does not support unindexed addressing");
7191 inst.instruction |= inst.operands[i].imm;
7192 inst.instruction |= INDEX_UP;
7196 if (inst.operands[i].preind)
7197 inst.instruction |= PRE_INDEX;
7199 if (inst.operands[i].writeback)
7201 if (inst.operands[i].reg == REG_PC)
7203 inst.error = _("pc may not be used with write-back");
7208 inst.error = _("instruction does not support writeback");
7211 inst.instruction |= WRITE_BACK;
7215 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7216 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7217 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7218 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7221 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7223 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7226 /* Prefer + for zero encoded value. */
7227 if (!inst.operands[i].negative)
7228 inst.instruction |= INDEX_UP;
7233 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7234 Determine whether it can be performed with a move instruction; if
7235 it can, convert inst.instruction to that move instruction and
7236 return TRUE; if it can't, convert inst.instruction to a literal-pool
7237 load and return FALSE. If this is not a valid thing to do in the
7238 current context, set inst.error and return TRUE.
7240 inst.operands[i] describes the destination register. */
7243 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7248 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7252 if ((inst.instruction & tbit) == 0)
7254 inst.error = _("invalid pseudo operation");
7257 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7259 inst.error = _("constant expression expected");
7262 if (inst.reloc.exp.X_op == O_constant)
7266 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7268 /* This can be done with a mov(1) instruction. */
7269 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7270 inst.instruction |= inst.reloc.exp.X_add_number;
7276 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7279 /* This can be done with a mov instruction. */
7280 inst.instruction &= LITERAL_MASK;
7281 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7282 inst.instruction |= value & 0xfff;
7286 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7289 /* This can be done with a mvn instruction. */
7290 inst.instruction &= LITERAL_MASK;
7291 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7292 inst.instruction |= value & 0xfff;
7298 if (add_to_lit_pool () == FAIL)
7300 inst.error = _("literal pool insertion failed");
7303 inst.operands[1].reg = REG_PC;
7304 inst.operands[1].isreg = 1;
7305 inst.operands[1].preind = 1;
7306 inst.reloc.pc_rel = 1;
7307 inst.reloc.type = (thumb_p
7308 ? BFD_RELOC_ARM_THUMB_OFFSET
7310 ? BFD_RELOC_ARM_HWLITERAL
7311 : BFD_RELOC_ARM_LITERAL));
7315 /* Functions for instruction encoding, sorted by sub-architecture.
7316 First some generics; their names are taken from the conventional
7317 bit positions for register arguments in ARM format instructions. */
7327 inst.instruction |= inst.operands[0].reg << 12;
7333 inst.instruction |= inst.operands[0].reg << 12;
7334 inst.instruction |= inst.operands[1].reg;
7340 inst.instruction |= inst.operands[0].reg << 12;
7341 inst.instruction |= inst.operands[1].reg << 16;
7347 inst.instruction |= inst.operands[0].reg << 16;
7348 inst.instruction |= inst.operands[1].reg << 12;
7354 unsigned Rn = inst.operands[2].reg;
7355 /* Enforce restrictions on SWP instruction. */
7356 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7358 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7359 _("Rn must not overlap other operands"));
7361 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7362 if (warn_on_deprecated
7363 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7364 as_warn (_("swp{b} use is deprecated for this architecture"));
7367 inst.instruction |= inst.operands[0].reg << 12;
7368 inst.instruction |= inst.operands[1].reg;
7369 inst.instruction |= Rn << 16;
7375 inst.instruction |= inst.operands[0].reg << 12;
7376 inst.instruction |= inst.operands[1].reg << 16;
7377 inst.instruction |= inst.operands[2].reg;
7383 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7384 constraint (((inst.reloc.exp.X_op != O_constant
7385 && inst.reloc.exp.X_op != O_illegal)
7386 || inst.reloc.exp.X_add_number != 0),
7388 inst.instruction |= inst.operands[0].reg;
7389 inst.instruction |= inst.operands[1].reg << 12;
7390 inst.instruction |= inst.operands[2].reg << 16;
7396 inst.instruction |= inst.operands[0].imm;
7402 inst.instruction |= inst.operands[0].reg << 12;
7403 encode_arm_cp_address (1, TRUE, TRUE, 0);
7406 /* ARM instructions, in alphabetical order by function name (except
7407 that wrapper functions appear immediately after the function they
7410 /* This is a pseudo-op of the form "adr rd, label" to be converted
7411 into a relative address of the form "add rd, pc, #label-.-8". */
7416 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7418 /* Frag hacking will turn this into a sub instruction if the offset turns
7419 out to be negative. */
7420 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7421 inst.reloc.pc_rel = 1;
7422 inst.reloc.exp.X_add_number -= 8;
7425 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7426 into a relative address of the form:
7427 add rd, pc, #low(label-.-8)"
7428 add rd, rd, #high(label-.-8)" */
7433 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7435 /* Frag hacking will turn this into a sub instruction if the offset turns
7436 out to be negative. */
7437 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7438 inst.reloc.pc_rel = 1;
7439 inst.size = INSN_SIZE * 2;
7440 inst.reloc.exp.X_add_number -= 8;
7446 if (!inst.operands[1].present)
7447 inst.operands[1].reg = inst.operands[0].reg;
7448 inst.instruction |= inst.operands[0].reg << 12;
7449 inst.instruction |= inst.operands[1].reg << 16;
7450 encode_arm_shifter_operand (2);
7456 if (inst.operands[0].present)
7458 constraint ((inst.instruction & 0xf0) != 0x40
7459 && inst.operands[0].imm > 0xf
7460 && inst.operands[0].imm < 0x0,
7461 _("bad barrier type"));
7462 inst.instruction |= inst.operands[0].imm;
7465 inst.instruction |= 0xf;
7471 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7472 constraint (msb > 32, _("bit-field extends past end of register"));
7473 /* The instruction encoding stores the LSB and MSB,
7474 not the LSB and width. */
7475 inst.instruction |= inst.operands[0].reg << 12;
7476 inst.instruction |= inst.operands[1].imm << 7;
7477 inst.instruction |= (msb - 1) << 16;
7485 /* #0 in second position is alternative syntax for bfc, which is
7486 the same instruction but with REG_PC in the Rm field. */
7487 if (!inst.operands[1].isreg)
7488 inst.operands[1].reg = REG_PC;
7490 msb = inst.operands[2].imm + inst.operands[3].imm;
7491 constraint (msb > 32, _("bit-field extends past end of register"));
7492 /* The instruction encoding stores the LSB and MSB,
7493 not the LSB and width. */
7494 inst.instruction |= inst.operands[0].reg << 12;
7495 inst.instruction |= inst.operands[1].reg;
7496 inst.instruction |= inst.operands[2].imm << 7;
7497 inst.instruction |= (msb - 1) << 16;
7503 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7504 _("bit-field extends past end of register"));
7505 inst.instruction |= inst.operands[0].reg << 12;
7506 inst.instruction |= inst.operands[1].reg;
7507 inst.instruction |= inst.operands[2].imm << 7;
7508 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7511 /* ARM V5 breakpoint instruction (argument parse)
7512 BKPT <16 bit unsigned immediate>
7513 Instruction is not conditional.
7514 The bit pattern given in insns[] has the COND_ALWAYS condition,
7515 and it is an error if the caller tried to override that. */
7520 /* Top 12 of 16 bits to bits 19:8. */
7521 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7523 /* Bottom 4 of 16 bits to bits 3:0. */
7524 inst.instruction |= inst.operands[0].imm & 0xf;
7528 encode_branch (int default_reloc)
7530 if (inst.operands[0].hasreloc)
7532 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7533 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7534 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7535 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7536 ? BFD_RELOC_ARM_PLT32
7537 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7540 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7541 inst.reloc.pc_rel = 1;
7548 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7549 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7552 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7559 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7561 if (inst.cond == COND_ALWAYS)
7562 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7564 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7568 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7571 /* ARM V5 branch-link-exchange instruction (argument parse)
7572 BLX <target_addr> ie BLX(1)
7573 BLX{<condition>} <Rm> ie BLX(2)
7574 Unfortunately, there are two different opcodes for this mnemonic.
7575 So, the insns[].value is not used, and the code here zaps values
7576 into inst.instruction.
7577 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7582 if (inst.operands[0].isreg)
7584 /* Arg is a register; the opcode provided by insns[] is correct.
7585 It is not illegal to do "blx pc", just useless. */
7586 if (inst.operands[0].reg == REG_PC)
7587 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7589 inst.instruction |= inst.operands[0].reg;
7593 /* Arg is an address; this instruction cannot be executed
7594 conditionally, and the opcode must be adjusted.
7595 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7596 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7597 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7598 inst.instruction = 0xfa000000;
7599 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7606 bfd_boolean want_reloc;
7608 if (inst.operands[0].reg == REG_PC)
7609 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7611 inst.instruction |= inst.operands[0].reg;
7612 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7613 it is for ARMv4t or earlier. */
7614 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7615 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7619 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7624 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7628 /* ARM v5TEJ. Jump to Jazelle code. */
7633 if (inst.operands[0].reg == REG_PC)
7634 as_tsktsk (_("use of r15 in bxj is not really useful"));
7636 inst.instruction |= inst.operands[0].reg;
7639 /* Co-processor data operation:
7640 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7641 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7645 inst.instruction |= inst.operands[0].reg << 8;
7646 inst.instruction |= inst.operands[1].imm << 20;
7647 inst.instruction |= inst.operands[2].reg << 12;
7648 inst.instruction |= inst.operands[3].reg << 16;
7649 inst.instruction |= inst.operands[4].reg;
7650 inst.instruction |= inst.operands[5].imm << 5;
7656 inst.instruction |= inst.operands[0].reg << 16;
7657 encode_arm_shifter_operand (1);
7660 /* Transfer between coprocessor and ARM registers.
7661 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7666 No special properties. */
7673 Rd = inst.operands[2].reg;
7676 if (inst.instruction == 0xee000010
7677 || inst.instruction == 0xfe000010)
7679 reject_bad_reg (Rd);
7682 constraint (Rd == REG_SP, BAD_SP);
7687 if (inst.instruction == 0xe000010)
7688 constraint (Rd == REG_PC, BAD_PC);
7692 inst.instruction |= inst.operands[0].reg << 8;
7693 inst.instruction |= inst.operands[1].imm << 21;
7694 inst.instruction |= Rd << 12;
7695 inst.instruction |= inst.operands[3].reg << 16;
7696 inst.instruction |= inst.operands[4].reg;
7697 inst.instruction |= inst.operands[5].imm << 5;
7700 /* Transfer between coprocessor register and pair of ARM registers.
7701 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7706 Two XScale instructions are special cases of these:
7708 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7709 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7711 Result unpredictable if Rd or Rn is R15. */
7718 Rd = inst.operands[2].reg;
7719 Rn = inst.operands[3].reg;
7723 reject_bad_reg (Rd);
7724 reject_bad_reg (Rn);
7728 constraint (Rd == REG_PC, BAD_PC);
7729 constraint (Rn == REG_PC, BAD_PC);
7732 inst.instruction |= inst.operands[0].reg << 8;
7733 inst.instruction |= inst.operands[1].imm << 4;
7734 inst.instruction |= Rd << 12;
7735 inst.instruction |= Rn << 16;
7736 inst.instruction |= inst.operands[4].reg;
7742 inst.instruction |= inst.operands[0].imm << 6;
7743 if (inst.operands[1].present)
7745 inst.instruction |= CPSI_MMOD;
7746 inst.instruction |= inst.operands[1].imm;
7753 inst.instruction |= inst.operands[0].imm;
7759 unsigned Rd, Rn, Rm;
7761 Rd = inst.operands[0].reg;
7762 Rn = (inst.operands[1].present
7763 ? inst.operands[1].reg : Rd);
7764 Rm = inst.operands[2].reg;
7766 constraint ((Rd == REG_PC), BAD_PC);
7767 constraint ((Rn == REG_PC), BAD_PC);
7768 constraint ((Rm == REG_PC), BAD_PC);
7770 inst.instruction |= Rd << 16;
7771 inst.instruction |= Rn << 0;
7772 inst.instruction |= Rm << 8;
7778 /* There is no IT instruction in ARM mode. We
7779 process it to do the validation as if in
7780 thumb mode, just in case the code gets
7781 assembled for thumb using the unified syntax. */
7786 set_it_insn_type (IT_INSN);
7787 now_it.mask = (inst.instruction & 0xf) | 0x10;
7788 now_it.cc = inst.operands[0].imm;
7795 int base_reg = inst.operands[0].reg;
7796 int range = inst.operands[1].imm;
7798 inst.instruction |= base_reg << 16;
7799 inst.instruction |= range;
7801 if (inst.operands[1].writeback)
7802 inst.instruction |= LDM_TYPE_2_OR_3;
7804 if (inst.operands[0].writeback)
7806 inst.instruction |= WRITE_BACK;
7807 /* Check for unpredictable uses of writeback. */
7808 if (inst.instruction & LOAD_BIT)
7810 /* Not allowed in LDM type 2. */
7811 if ((inst.instruction & LDM_TYPE_2_OR_3)
7812 && ((range & (1 << REG_PC)) == 0))
7813 as_warn (_("writeback of base register is UNPREDICTABLE"));
7814 /* Only allowed if base reg not in list for other types. */
7815 else if (range & (1 << base_reg))
7816 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7820 /* Not allowed for type 2. */
7821 if (inst.instruction & LDM_TYPE_2_OR_3)
7822 as_warn (_("writeback of base register is UNPREDICTABLE"));
7823 /* Only allowed if base reg not in list, or first in list. */
7824 else if ((range & (1 << base_reg))
7825 && (range & ((1 << base_reg) - 1)))
7826 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7831 /* ARMv5TE load-consecutive (argument parse)
7840 constraint (inst.operands[0].reg % 2 != 0,
7841 _("first transfer register must be even"));
7842 constraint (inst.operands[1].present
7843 && inst.operands[1].reg != inst.operands[0].reg + 1,
7844 _("can only transfer two consecutive registers"));
7845 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7846 constraint (!inst.operands[2].isreg, _("'[' expected"));
7848 if (!inst.operands[1].present)
7849 inst.operands[1].reg = inst.operands[0].reg + 1;
7851 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7852 register and the first register written; we have to diagnose
7853 overlap between the base and the second register written here. */
7855 if (inst.operands[2].reg == inst.operands[1].reg
7856 && (inst.operands[2].writeback || inst.operands[2].postind))
7857 as_warn (_("base register written back, and overlaps "
7858 "second transfer register"));
7860 if (!(inst.instruction & V4_STR_BIT))
7862 /* For an index-register load, the index register must not overlap the
7863 destination (even if not write-back). */
7864 if (inst.operands[2].immisreg
7865 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7866 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7867 as_warn (_("index register overlaps transfer register"));
7869 inst.instruction |= inst.operands[0].reg << 12;
7870 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7876 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7877 || inst.operands[1].postind || inst.operands[1].writeback
7878 || inst.operands[1].immisreg || inst.operands[1].shifted
7879 || inst.operands[1].negative
7880 /* This can arise if the programmer has written
7882 or if they have mistakenly used a register name as the last
7885 It is very difficult to distinguish between these two cases
7886 because "rX" might actually be a label. ie the register
7887 name has been occluded by a symbol of the same name. So we
7888 just generate a general 'bad addressing mode' type error
7889 message and leave it up to the programmer to discover the
7890 true cause and fix their mistake. */
7891 || (inst.operands[1].reg == REG_PC),
7894 constraint (inst.reloc.exp.X_op != O_constant
7895 || inst.reloc.exp.X_add_number != 0,
7896 _("offset must be zero in ARM encoding"));
7898 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7900 inst.instruction |= inst.operands[0].reg << 12;
7901 inst.instruction |= inst.operands[1].reg << 16;
7902 inst.reloc.type = BFD_RELOC_UNUSED;
7908 constraint (inst.operands[0].reg % 2 != 0,
7909 _("even register required"));
7910 constraint (inst.operands[1].present
7911 && inst.operands[1].reg != inst.operands[0].reg + 1,
7912 _("can only load two consecutive registers"));
7913 /* If op 1 were present and equal to PC, this function wouldn't
7914 have been called in the first place. */
7915 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7917 inst.instruction |= inst.operands[0].reg << 12;
7918 inst.instruction |= inst.operands[2].reg << 16;
7921 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7922 which is not a multiple of four is UNPREDICTABLE. */
7924 check_ldr_r15_aligned (void)
7926 constraint (!(inst.operands[1].immisreg)
7927 && (inst.operands[0].reg == REG_PC
7928 && inst.operands[1].reg == REG_PC
7929 && (inst.reloc.exp.X_add_number & 0x3)),
7930 _("ldr to register 15 must be 4-byte alligned"));
7936 inst.instruction |= inst.operands[0].reg << 12;
7937 if (!inst.operands[1].isreg)
7938 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7940 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7941 check_ldr_r15_aligned ();
7947 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7949 if (inst.operands[1].preind)
7951 constraint (inst.reloc.exp.X_op != O_constant
7952 || inst.reloc.exp.X_add_number != 0,
7953 _("this instruction requires a post-indexed address"));
7955 inst.operands[1].preind = 0;
7956 inst.operands[1].postind = 1;
7957 inst.operands[1].writeback = 1;
7959 inst.instruction |= inst.operands[0].reg << 12;
7960 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7963 /* Halfword and signed-byte load/store operations. */
7968 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7969 inst.instruction |= inst.operands[0].reg << 12;
7970 if (!inst.operands[1].isreg)
7971 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7973 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7979 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7981 if (inst.operands[1].preind)
7983 constraint (inst.reloc.exp.X_op != O_constant
7984 || inst.reloc.exp.X_add_number != 0,
7985 _("this instruction requires a post-indexed address"));
7987 inst.operands[1].preind = 0;
7988 inst.operands[1].postind = 1;
7989 inst.operands[1].writeback = 1;
7991 inst.instruction |= inst.operands[0].reg << 12;
7992 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7995 /* Co-processor register load/store.
7996 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8000 inst.instruction |= inst.operands[0].reg << 8;
8001 inst.instruction |= inst.operands[1].reg << 12;
8002 encode_arm_cp_address (2, TRUE, TRUE, 0);
8008 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8009 if (inst.operands[0].reg == inst.operands[1].reg
8010 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8011 && !(inst.instruction & 0x00400000))
8012 as_tsktsk (_("Rd and Rm should be different in mla"));
8014 inst.instruction |= inst.operands[0].reg << 16;
8015 inst.instruction |= inst.operands[1].reg;
8016 inst.instruction |= inst.operands[2].reg << 8;
8017 inst.instruction |= inst.operands[3].reg << 12;
8023 inst.instruction |= inst.operands[0].reg << 12;
8024 encode_arm_shifter_operand (1);
8027 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8034 top = (inst.instruction & 0x00400000) != 0;
8035 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8036 _(":lower16: not allowed this instruction"));
8037 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8038 _(":upper16: not allowed instruction"));
8039 inst.instruction |= inst.operands[0].reg << 12;
8040 if (inst.reloc.type == BFD_RELOC_UNUSED)
8042 imm = inst.reloc.exp.X_add_number;
8043 /* The value is in two pieces: 0:11, 16:19. */
8044 inst.instruction |= (imm & 0x00000fff);
8045 inst.instruction |= (imm & 0x0000f000) << 4;
8049 static void do_vfp_nsyn_opcode (const char *);
8052 do_vfp_nsyn_mrs (void)
8054 if (inst.operands[0].isvec)
8056 if (inst.operands[1].reg != 1)
8057 first_error (_("operand 1 must be FPSCR"));
8058 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8059 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8060 do_vfp_nsyn_opcode ("fmstat");
8062 else if (inst.operands[1].isvec)
8063 do_vfp_nsyn_opcode ("fmrx");
8071 do_vfp_nsyn_msr (void)
8073 if (inst.operands[0].isvec)
8074 do_vfp_nsyn_opcode ("fmxr");
8084 unsigned Rt = inst.operands[0].reg;
8086 if (thumb_mode && inst.operands[0].reg == REG_SP)
8088 inst.error = BAD_SP;
8092 /* APSR_ sets isvec. All other refs to PC are illegal. */
8093 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8095 inst.error = BAD_PC;
8099 if (inst.operands[1].reg != 1)
8100 first_error (_("operand 1 must be FPSCR"));
8102 inst.instruction |= (Rt << 12);
8108 unsigned Rt = inst.operands[1].reg;
8111 reject_bad_reg (Rt);
8112 else if (Rt == REG_PC)
8114 inst.error = BAD_PC;
8118 if (inst.operands[0].reg != 1)
8119 first_error (_("operand 0 must be FPSCR"));
8121 inst.instruction |= (Rt << 12);
8129 if (do_vfp_nsyn_mrs () == SUCCESS)
8132 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8133 inst.instruction |= inst.operands[0].reg << 12;
8135 if (inst.operands[1].isreg)
8137 br = inst.operands[1].reg;
8138 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8139 as_bad (_("bad register for mrs"));
8143 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8144 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8146 _("'APSR', 'CPSR' or 'SPSR' expected"));
8147 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8150 inst.instruction |= br;
8153 /* Two possible forms:
8154 "{C|S}PSR_<field>, Rm",
8155 "{C|S}PSR_f, #expression". */
8160 if (do_vfp_nsyn_msr () == SUCCESS)
8163 inst.instruction |= inst.operands[0].imm;
8164 if (inst.operands[1].isreg)
8165 inst.instruction |= inst.operands[1].reg;
8168 inst.instruction |= INST_IMMEDIATE;
8169 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8170 inst.reloc.pc_rel = 0;
8177 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8179 if (!inst.operands[2].present)
8180 inst.operands[2].reg = inst.operands[0].reg;
8181 inst.instruction |= inst.operands[0].reg << 16;
8182 inst.instruction |= inst.operands[1].reg;
8183 inst.instruction |= inst.operands[2].reg << 8;
8185 if (inst.operands[0].reg == inst.operands[1].reg
8186 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8187 as_tsktsk (_("Rd and Rm should be different in mul"));
8190 /* Long Multiply Parser
8191 UMULL RdLo, RdHi, Rm, Rs
8192 SMULL RdLo, RdHi, Rm, Rs
8193 UMLAL RdLo, RdHi, Rm, Rs
8194 SMLAL RdLo, RdHi, Rm, Rs. */
8199 inst.instruction |= inst.operands[0].reg << 12;
8200 inst.instruction |= inst.operands[1].reg << 16;
8201 inst.instruction |= inst.operands[2].reg;
8202 inst.instruction |= inst.operands[3].reg << 8;
8204 /* rdhi and rdlo must be different. */
8205 if (inst.operands[0].reg == inst.operands[1].reg)
8206 as_tsktsk (_("rdhi and rdlo must be different"));
8208 /* rdhi, rdlo and rm must all be different before armv6. */
8209 if ((inst.operands[0].reg == inst.operands[2].reg
8210 || inst.operands[1].reg == inst.operands[2].reg)
8211 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8212 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8218 if (inst.operands[0].present
8219 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8221 /* Architectural NOP hints are CPSR sets with no bits selected. */
8222 inst.instruction &= 0xf0000000;
8223 inst.instruction |= 0x0320f000;
8224 if (inst.operands[0].present)
8225 inst.instruction |= inst.operands[0].imm;
8229 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8230 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8231 Condition defaults to COND_ALWAYS.
8232 Error if Rd, Rn or Rm are R15. */
8237 inst.instruction |= inst.operands[0].reg << 12;
8238 inst.instruction |= inst.operands[1].reg << 16;
8239 inst.instruction |= inst.operands[2].reg;
8240 if (inst.operands[3].present)
8241 encode_arm_shift (3);
8244 /* ARM V6 PKHTB (Argument Parse). */
8249 if (!inst.operands[3].present)
8251 /* If the shift specifier is omitted, turn the instruction
8252 into pkhbt rd, rm, rn. */
8253 inst.instruction &= 0xfff00010;
8254 inst.instruction |= inst.operands[0].reg << 12;
8255 inst.instruction |= inst.operands[1].reg;
8256 inst.instruction |= inst.operands[2].reg << 16;
8260 inst.instruction |= inst.operands[0].reg << 12;
8261 inst.instruction |= inst.operands[1].reg << 16;
8262 inst.instruction |= inst.operands[2].reg;
8263 encode_arm_shift (3);
8267 /* ARMv5TE: Preload-Cache
8268 MP Extensions: Preload for write
8272 Syntactically, like LDR with B=1, W=0, L=1. */
8277 constraint (!inst.operands[0].isreg,
8278 _("'[' expected after PLD mnemonic"));
8279 constraint (inst.operands[0].postind,
8280 _("post-indexed expression used in preload instruction"));
8281 constraint (inst.operands[0].writeback,
8282 _("writeback used in preload instruction"));
8283 constraint (!inst.operands[0].preind,
8284 _("unindexed addressing used in preload instruction"));
8285 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8288 /* ARMv7: PLI <addr_mode> */
8292 constraint (!inst.operands[0].isreg,
8293 _("'[' expected after PLI mnemonic"));
8294 constraint (inst.operands[0].postind,
8295 _("post-indexed expression used in preload instruction"));
8296 constraint (inst.operands[0].writeback,
8297 _("writeback used in preload instruction"));
8298 constraint (!inst.operands[0].preind,
8299 _("unindexed addressing used in preload instruction"));
8300 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8301 inst.instruction &= ~PRE_INDEX;
8307 inst.operands[1] = inst.operands[0];
8308 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8309 inst.operands[0].isreg = 1;
8310 inst.operands[0].writeback = 1;
8311 inst.operands[0].reg = REG_SP;
8315 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8316 word at the specified address and the following word
8318 Unconditionally executed.
8319 Error if Rn is R15. */
8324 inst.instruction |= inst.operands[0].reg << 16;
8325 if (inst.operands[0].writeback)
8326 inst.instruction |= WRITE_BACK;
8329 /* ARM V6 ssat (argument parse). */
8334 inst.instruction |= inst.operands[0].reg << 12;
8335 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8336 inst.instruction |= inst.operands[2].reg;
8338 if (inst.operands[3].present)
8339 encode_arm_shift (3);
8342 /* ARM V6 usat (argument parse). */
8347 inst.instruction |= inst.operands[0].reg << 12;
8348 inst.instruction |= inst.operands[1].imm << 16;
8349 inst.instruction |= inst.operands[2].reg;
8351 if (inst.operands[3].present)
8352 encode_arm_shift (3);
8355 /* ARM V6 ssat16 (argument parse). */
8360 inst.instruction |= inst.operands[0].reg << 12;
8361 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8362 inst.instruction |= inst.operands[2].reg;
8368 inst.instruction |= inst.operands[0].reg << 12;
8369 inst.instruction |= inst.operands[1].imm << 16;
8370 inst.instruction |= inst.operands[2].reg;
8373 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8374 preserving the other bits.
8376 setend <endian_specifier>, where <endian_specifier> is either
8382 if (inst.operands[0].imm)
8383 inst.instruction |= 0x200;
8389 unsigned int Rm = (inst.operands[1].present
8390 ? inst.operands[1].reg
8391 : inst.operands[0].reg);
8393 inst.instruction |= inst.operands[0].reg << 12;
8394 inst.instruction |= Rm;
8395 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8397 inst.instruction |= inst.operands[2].reg << 8;
8398 inst.instruction |= SHIFT_BY_REG;
8399 /* PR 12854: Error on extraneous shifts. */
8400 constraint (inst.operands[2].shifted,
8401 _("extraneous shift as part of operand to shift insn"));
8404 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8410 inst.reloc.type = BFD_RELOC_ARM_SMC;
8411 inst.reloc.pc_rel = 0;
8417 inst.reloc.type = BFD_RELOC_ARM_HVC;
8418 inst.reloc.pc_rel = 0;
8424 inst.reloc.type = BFD_RELOC_ARM_SWI;
8425 inst.reloc.pc_rel = 0;
8428 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8429 SMLAxy{cond} Rd,Rm,Rs,Rn
8430 SMLAWy{cond} Rd,Rm,Rs,Rn
8431 Error if any register is R15. */
8436 inst.instruction |= inst.operands[0].reg << 16;
8437 inst.instruction |= inst.operands[1].reg;
8438 inst.instruction |= inst.operands[2].reg << 8;
8439 inst.instruction |= inst.operands[3].reg << 12;
8442 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8443 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8444 Error if any register is R15.
8445 Warning if Rdlo == Rdhi. */
8450 inst.instruction |= inst.operands[0].reg << 12;
8451 inst.instruction |= inst.operands[1].reg << 16;
8452 inst.instruction |= inst.operands[2].reg;
8453 inst.instruction |= inst.operands[3].reg << 8;
8455 if (inst.operands[0].reg == inst.operands[1].reg)
8456 as_tsktsk (_("rdhi and rdlo must be different"));
8459 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8460 SMULxy{cond} Rd,Rm,Rs
8461 Error if any register is R15. */
8466 inst.instruction |= inst.operands[0].reg << 16;
8467 inst.instruction |= inst.operands[1].reg;
8468 inst.instruction |= inst.operands[2].reg << 8;
8471 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8472 the same for both ARM and Thumb-2. */
8479 if (inst.operands[0].present)
8481 reg = inst.operands[0].reg;
8482 constraint (reg != REG_SP, _("SRS base register must be r13"));
8487 inst.instruction |= reg << 16;
8488 inst.instruction |= inst.operands[1].imm;
8489 if (inst.operands[0].writeback || inst.operands[1].writeback)
8490 inst.instruction |= WRITE_BACK;
8493 /* ARM V6 strex (argument parse). */
8498 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8499 || inst.operands[2].postind || inst.operands[2].writeback
8500 || inst.operands[2].immisreg || inst.operands[2].shifted
8501 || inst.operands[2].negative
8502 /* See comment in do_ldrex(). */
8503 || (inst.operands[2].reg == REG_PC),
8506 constraint (inst.operands[0].reg == inst.operands[1].reg
8507 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8509 constraint (inst.reloc.exp.X_op != O_constant
8510 || inst.reloc.exp.X_add_number != 0,
8511 _("offset must be zero in ARM encoding"));
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= inst.operands[1].reg;
8515 inst.instruction |= inst.operands[2].reg << 16;
8516 inst.reloc.type = BFD_RELOC_UNUSED;
8522 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8523 || inst.operands[2].postind || inst.operands[2].writeback
8524 || inst.operands[2].immisreg || inst.operands[2].shifted
8525 || inst.operands[2].negative,
8528 constraint (inst.operands[0].reg == inst.operands[1].reg
8529 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8537 constraint (inst.operands[1].reg % 2 != 0,
8538 _("even register required"));
8539 constraint (inst.operands[2].present
8540 && inst.operands[2].reg != inst.operands[1].reg + 1,
8541 _("can only store two consecutive registers"));
8542 /* If op 2 were present and equal to PC, this function wouldn't
8543 have been called in the first place. */
8544 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8546 constraint (inst.operands[0].reg == inst.operands[1].reg
8547 || inst.operands[0].reg == inst.operands[1].reg + 1
8548 || inst.operands[0].reg == inst.operands[3].reg,
8551 inst.instruction |= inst.operands[0].reg << 12;
8552 inst.instruction |= inst.operands[1].reg;
8553 inst.instruction |= inst.operands[3].reg << 16;
8556 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8557 extends it to 32-bits, and adds the result to a value in another
8558 register. You can specify a rotation by 0, 8, 16, or 24 bits
8559 before extracting the 16-bit value.
8560 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8561 Condition defaults to COND_ALWAYS.
8562 Error if any register uses R15. */
8567 inst.instruction |= inst.operands[0].reg << 12;
8568 inst.instruction |= inst.operands[1].reg << 16;
8569 inst.instruction |= inst.operands[2].reg;
8570 inst.instruction |= inst.operands[3].imm << 10;
8575 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8576 Condition defaults to COND_ALWAYS.
8577 Error if any register uses R15. */
8582 inst.instruction |= inst.operands[0].reg << 12;
8583 inst.instruction |= inst.operands[1].reg;
8584 inst.instruction |= inst.operands[2].imm << 10;
8587 /* VFP instructions. In a logical order: SP variant first, monad
8588 before dyad, arithmetic then move then load/store. */
8591 do_vfp_sp_monadic (void)
8593 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8594 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8598 do_vfp_sp_dyadic (void)
8600 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8601 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8602 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8606 do_vfp_sp_compare_z (void)
8608 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8612 do_vfp_dp_sp_cvt (void)
8614 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8615 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8619 do_vfp_sp_dp_cvt (void)
8621 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8622 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8626 do_vfp_reg_from_sp (void)
8628 inst.instruction |= inst.operands[0].reg << 12;
8629 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8633 do_vfp_reg2_from_sp2 (void)
8635 constraint (inst.operands[2].imm != 2,
8636 _("only two consecutive VFP SP registers allowed here"));
8637 inst.instruction |= inst.operands[0].reg << 12;
8638 inst.instruction |= inst.operands[1].reg << 16;
8639 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8643 do_vfp_sp_from_reg (void)
8645 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8646 inst.instruction |= inst.operands[1].reg << 12;
8650 do_vfp_sp2_from_reg2 (void)
8652 constraint (inst.operands[0].imm != 2,
8653 _("only two consecutive VFP SP registers allowed here"));
8654 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8655 inst.instruction |= inst.operands[1].reg << 12;
8656 inst.instruction |= inst.operands[2].reg << 16;
8660 do_vfp_sp_ldst (void)
8662 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8663 encode_arm_cp_address (1, FALSE, TRUE, 0);
8667 do_vfp_dp_ldst (void)
8669 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8670 encode_arm_cp_address (1, FALSE, TRUE, 0);
8675 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8677 if (inst.operands[0].writeback)
8678 inst.instruction |= WRITE_BACK;
8680 constraint (ldstm_type != VFP_LDSTMIA,
8681 _("this addressing mode requires base-register writeback"));
8682 inst.instruction |= inst.operands[0].reg << 16;
8683 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8684 inst.instruction |= inst.operands[1].imm;
8688 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8692 if (inst.operands[0].writeback)
8693 inst.instruction |= WRITE_BACK;
8695 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8696 _("this addressing mode requires base-register writeback"));
8698 inst.instruction |= inst.operands[0].reg << 16;
8699 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8701 count = inst.operands[1].imm << 1;
8702 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8705 inst.instruction |= count;
8709 do_vfp_sp_ldstmia (void)
8711 vfp_sp_ldstm (VFP_LDSTMIA);
8715 do_vfp_sp_ldstmdb (void)
8717 vfp_sp_ldstm (VFP_LDSTMDB);
8721 do_vfp_dp_ldstmia (void)
8723 vfp_dp_ldstm (VFP_LDSTMIA);
8727 do_vfp_dp_ldstmdb (void)
8729 vfp_dp_ldstm (VFP_LDSTMDB);
8733 do_vfp_xp_ldstmia (void)
8735 vfp_dp_ldstm (VFP_LDSTMIAX);
8739 do_vfp_xp_ldstmdb (void)
8741 vfp_dp_ldstm (VFP_LDSTMDBX);
8745 do_vfp_dp_rd_rm (void)
8747 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8748 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8752 do_vfp_dp_rn_rd (void)
8754 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8755 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8759 do_vfp_dp_rd_rn (void)
8761 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8762 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8766 do_vfp_dp_rd_rn_rm (void)
8768 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8769 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8770 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8776 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8780 do_vfp_dp_rm_rd_rn (void)
8782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8783 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8784 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8787 /* VFPv3 instructions. */
8789 do_vfp_sp_const (void)
8791 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8792 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8793 inst.instruction |= (inst.operands[1].imm & 0x0f);
8797 do_vfp_dp_const (void)
8799 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8800 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8801 inst.instruction |= (inst.operands[1].imm & 0x0f);
8805 vfp_conv (int srcsize)
8807 int immbits = srcsize - inst.operands[1].imm;
8809 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8811 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8812 i.e. immbits must be in range 0 - 16. */
8813 inst.error = _("immediate value out of range, expected range [0, 16]");
8816 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8818 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8819 i.e. immbits must be in range 0 - 31. */
8820 inst.error = _("immediate value out of range, expected range [1, 32]");
8824 inst.instruction |= (immbits & 1) << 5;
8825 inst.instruction |= (immbits >> 1);
8829 do_vfp_sp_conv_16 (void)
8831 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8836 do_vfp_dp_conv_16 (void)
8838 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8843 do_vfp_sp_conv_32 (void)
8845 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8850 do_vfp_dp_conv_32 (void)
8852 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8856 /* FPA instructions. Also in a logical order. */
8861 inst.instruction |= inst.operands[0].reg << 16;
8862 inst.instruction |= inst.operands[1].reg;
8866 do_fpa_ldmstm (void)
8868 inst.instruction |= inst.operands[0].reg << 12;
8869 switch (inst.operands[1].imm)
8871 case 1: inst.instruction |= CP_T_X; break;
8872 case 2: inst.instruction |= CP_T_Y; break;
8873 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8878 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8880 /* The instruction specified "ea" or "fd", so we can only accept
8881 [Rn]{!}. The instruction does not really support stacking or
8882 unstacking, so we have to emulate these by setting appropriate
8883 bits and offsets. */
8884 constraint (inst.reloc.exp.X_op != O_constant
8885 || inst.reloc.exp.X_add_number != 0,
8886 _("this instruction does not support indexing"));
8888 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8889 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8891 if (!(inst.instruction & INDEX_UP))
8892 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8894 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8896 inst.operands[2].preind = 0;
8897 inst.operands[2].postind = 1;
8901 encode_arm_cp_address (2, TRUE, TRUE, 0);
8904 /* iWMMXt instructions: strictly in alphabetical order. */
8907 do_iwmmxt_tandorc (void)
8909 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8913 do_iwmmxt_textrc (void)
8915 inst.instruction |= inst.operands[0].reg << 12;
8916 inst.instruction |= inst.operands[1].imm;
8920 do_iwmmxt_textrm (void)
8922 inst.instruction |= inst.operands[0].reg << 12;
8923 inst.instruction |= inst.operands[1].reg << 16;
8924 inst.instruction |= inst.operands[2].imm;
8928 do_iwmmxt_tinsr (void)
8930 inst.instruction |= inst.operands[0].reg << 16;
8931 inst.instruction |= inst.operands[1].reg << 12;
8932 inst.instruction |= inst.operands[2].imm;
8936 do_iwmmxt_tmia (void)
8938 inst.instruction |= inst.operands[0].reg << 5;
8939 inst.instruction |= inst.operands[1].reg;
8940 inst.instruction |= inst.operands[2].reg << 12;
8944 do_iwmmxt_waligni (void)
8946 inst.instruction |= inst.operands[0].reg << 12;
8947 inst.instruction |= inst.operands[1].reg << 16;
8948 inst.instruction |= inst.operands[2].reg;
8949 inst.instruction |= inst.operands[3].imm << 20;
8953 do_iwmmxt_wmerge (void)
8955 inst.instruction |= inst.operands[0].reg << 12;
8956 inst.instruction |= inst.operands[1].reg << 16;
8957 inst.instruction |= inst.operands[2].reg;
8958 inst.instruction |= inst.operands[3].imm << 21;
8962 do_iwmmxt_wmov (void)
8964 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8965 inst.instruction |= inst.operands[0].reg << 12;
8966 inst.instruction |= inst.operands[1].reg << 16;
8967 inst.instruction |= inst.operands[1].reg;
8971 do_iwmmxt_wldstbh (void)
8974 inst.instruction |= inst.operands[0].reg << 12;
8976 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8978 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8979 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8983 do_iwmmxt_wldstw (void)
8985 /* RIWR_RIWC clears .isreg for a control register. */
8986 if (!inst.operands[0].isreg)
8988 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8989 inst.instruction |= 0xf0000000;
8992 inst.instruction |= inst.operands[0].reg << 12;
8993 encode_arm_cp_address (1, TRUE, TRUE, 0);
8997 do_iwmmxt_wldstd (void)
8999 inst.instruction |= inst.operands[0].reg << 12;
9000 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9001 && inst.operands[1].immisreg)
9003 inst.instruction &= ~0x1a000ff;
9004 inst.instruction |= (0xf << 28);
9005 if (inst.operands[1].preind)
9006 inst.instruction |= PRE_INDEX;
9007 if (!inst.operands[1].negative)
9008 inst.instruction |= INDEX_UP;
9009 if (inst.operands[1].writeback)
9010 inst.instruction |= WRITE_BACK;
9011 inst.instruction |= inst.operands[1].reg << 16;
9012 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9013 inst.instruction |= inst.operands[1].imm;
9016 encode_arm_cp_address (1, TRUE, FALSE, 0);
9020 do_iwmmxt_wshufh (void)
9022 inst.instruction |= inst.operands[0].reg << 12;
9023 inst.instruction |= inst.operands[1].reg << 16;
9024 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9025 inst.instruction |= (inst.operands[2].imm & 0x0f);
9029 do_iwmmxt_wzero (void)
9031 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9032 inst.instruction |= inst.operands[0].reg;
9033 inst.instruction |= inst.operands[0].reg << 12;
9034 inst.instruction |= inst.operands[0].reg << 16;
9038 do_iwmmxt_wrwrwr_or_imm5 (void)
9040 if (inst.operands[2].isreg)
9043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9044 _("immediate operand requires iWMMXt2"));
9046 if (inst.operands[2].imm == 0)
9048 switch ((inst.instruction >> 20) & 0xf)
9054 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9055 inst.operands[2].imm = 16;
9056 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9062 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9063 inst.operands[2].imm = 32;
9064 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9071 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9073 wrn = (inst.instruction >> 16) & 0xf;
9074 inst.instruction &= 0xff0fff0f;
9075 inst.instruction |= wrn;
9076 /* Bail out here; the instruction is now assembled. */
9081 /* Map 32 -> 0, etc. */
9082 inst.operands[2].imm &= 0x1f;
9083 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9087 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9088 operations first, then control, shift, and load/store. */
9090 /* Insns like "foo X,Y,Z". */
9093 do_mav_triple (void)
9095 inst.instruction |= inst.operands[0].reg << 16;
9096 inst.instruction |= inst.operands[1].reg;
9097 inst.instruction |= inst.operands[2].reg << 12;
9100 /* Insns like "foo W,X,Y,Z".
9101 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9106 inst.instruction |= inst.operands[0].reg << 5;
9107 inst.instruction |= inst.operands[1].reg << 12;
9108 inst.instruction |= inst.operands[2].reg << 16;
9109 inst.instruction |= inst.operands[3].reg;
9112 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9116 inst.instruction |= inst.operands[1].reg << 12;
9119 /* Maverick shift immediate instructions.
9120 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9121 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9126 int imm = inst.operands[2].imm;
9128 inst.instruction |= inst.operands[0].reg << 12;
9129 inst.instruction |= inst.operands[1].reg << 16;
9131 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9132 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9133 Bit 4 should be 0. */
9134 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9136 inst.instruction |= imm;
9139 /* XScale instructions. Also sorted arithmetic before move. */
9141 /* Xscale multiply-accumulate (argument parse)
9144 MIAxycc acc0,Rm,Rs. */
9149 inst.instruction |= inst.operands[1].reg;
9150 inst.instruction |= inst.operands[2].reg << 12;
9153 /* Xscale move-accumulator-register (argument parse)
9155 MARcc acc0,RdLo,RdHi. */
9160 inst.instruction |= inst.operands[1].reg << 12;
9161 inst.instruction |= inst.operands[2].reg << 16;
9164 /* Xscale move-register-accumulator (argument parse)
9166 MRAcc RdLo,RdHi,acc0. */
9171 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9172 inst.instruction |= inst.operands[0].reg << 12;
9173 inst.instruction |= inst.operands[1].reg << 16;
9176 /* Encoding functions relevant only to Thumb. */
9178 /* inst.operands[i] is a shifted-register operand; encode
9179 it into inst.instruction in the format used by Thumb32. */
9182 encode_thumb32_shifted_operand (int i)
9184 unsigned int value = inst.reloc.exp.X_add_number;
9185 unsigned int shift = inst.operands[i].shift_kind;
9187 constraint (inst.operands[i].immisreg,
9188 _("shift by register not allowed in thumb mode"));
9189 inst.instruction |= inst.operands[i].reg;
9190 if (shift == SHIFT_RRX)
9191 inst.instruction |= SHIFT_ROR << 4;
9194 constraint (inst.reloc.exp.X_op != O_constant,
9195 _("expression too complex"));
9197 constraint (value > 32
9198 || (value == 32 && (shift == SHIFT_LSL
9199 || shift == SHIFT_ROR)),
9200 _("shift expression is too large"));
9204 else if (value == 32)
9207 inst.instruction |= shift << 4;
9208 inst.instruction |= (value & 0x1c) << 10;
9209 inst.instruction |= (value & 0x03) << 6;
9214 /* inst.operands[i] was set up by parse_address. Encode it into a
9215 Thumb32 format load or store instruction. Reject forms that cannot
9216 be used with such instructions. If is_t is true, reject forms that
9217 cannot be used with a T instruction; if is_d is true, reject forms
9218 that cannot be used with a D instruction. If it is a store insn,
9222 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9224 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9226 constraint (!inst.operands[i].isreg,
9227 _("Instruction does not support =N addresses"));
9229 inst.instruction |= inst.operands[i].reg << 16;
9230 if (inst.operands[i].immisreg)
9232 constraint (is_pc, BAD_PC_ADDRESSING);
9233 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9234 constraint (inst.operands[i].negative,
9235 _("Thumb does not support negative register indexing"));
9236 constraint (inst.operands[i].postind,
9237 _("Thumb does not support register post-indexing"));
9238 constraint (inst.operands[i].writeback,
9239 _("Thumb does not support register indexing with writeback"));
9240 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9241 _("Thumb supports only LSL in shifted register indexing"));
9243 inst.instruction |= inst.operands[i].imm;
9244 if (inst.operands[i].shifted)
9246 constraint (inst.reloc.exp.X_op != O_constant,
9247 _("expression too complex"));
9248 constraint (inst.reloc.exp.X_add_number < 0
9249 || inst.reloc.exp.X_add_number > 3,
9250 _("shift out of range"));
9251 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9253 inst.reloc.type = BFD_RELOC_UNUSED;
9255 else if (inst.operands[i].preind)
9257 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9258 constraint (is_t && inst.operands[i].writeback,
9259 _("cannot use writeback with this instruction"));
9260 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9261 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9265 inst.instruction |= 0x01000000;
9266 if (inst.operands[i].writeback)
9267 inst.instruction |= 0x00200000;
9271 inst.instruction |= 0x00000c00;
9272 if (inst.operands[i].writeback)
9273 inst.instruction |= 0x00000100;
9275 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9277 else if (inst.operands[i].postind)
9279 gas_assert (inst.operands[i].writeback);
9280 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9281 constraint (is_t, _("cannot use post-indexing with this instruction"));
9284 inst.instruction |= 0x00200000;
9286 inst.instruction |= 0x00000900;
9287 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9289 else /* unindexed - only for coprocessor */
9290 inst.error = _("instruction does not accept unindexed addressing");
9293 /* Table of Thumb instructions which exist in both 16- and 32-bit
9294 encodings (the latter only in post-V6T2 cores). The index is the
9295 value used in the insns table below. When there is more than one
9296 possible 16-bit encoding for the instruction, this table always
9298 Also contains several pseudo-instructions used during relaxation. */
9299 #define T16_32_TAB \
9300 X(_adc, 4140, eb400000), \
9301 X(_adcs, 4140, eb500000), \
9302 X(_add, 1c00, eb000000), \
9303 X(_adds, 1c00, eb100000), \
9304 X(_addi, 0000, f1000000), \
9305 X(_addis, 0000, f1100000), \
9306 X(_add_pc,000f, f20f0000), \
9307 X(_add_sp,000d, f10d0000), \
9308 X(_adr, 000f, f20f0000), \
9309 X(_and, 4000, ea000000), \
9310 X(_ands, 4000, ea100000), \
9311 X(_asr, 1000, fa40f000), \
9312 X(_asrs, 1000, fa50f000), \
9313 X(_b, e000, f000b000), \
9314 X(_bcond, d000, f0008000), \
9315 X(_bic, 4380, ea200000), \
9316 X(_bics, 4380, ea300000), \
9317 X(_cmn, 42c0, eb100f00), \
9318 X(_cmp, 2800, ebb00f00), \
9319 X(_cpsie, b660, f3af8400), \
9320 X(_cpsid, b670, f3af8600), \
9321 X(_cpy, 4600, ea4f0000), \
9322 X(_dec_sp,80dd, f1ad0d00), \
9323 X(_eor, 4040, ea800000), \
9324 X(_eors, 4040, ea900000), \
9325 X(_inc_sp,00dd, f10d0d00), \
9326 X(_ldmia, c800, e8900000), \
9327 X(_ldr, 6800, f8500000), \
9328 X(_ldrb, 7800, f8100000), \
9329 X(_ldrh, 8800, f8300000), \
9330 X(_ldrsb, 5600, f9100000), \
9331 X(_ldrsh, 5e00, f9300000), \
9332 X(_ldr_pc,4800, f85f0000), \
9333 X(_ldr_pc2,4800, f85f0000), \
9334 X(_ldr_sp,9800, f85d0000), \
9335 X(_lsl, 0000, fa00f000), \
9336 X(_lsls, 0000, fa10f000), \
9337 X(_lsr, 0800, fa20f000), \
9338 X(_lsrs, 0800, fa30f000), \
9339 X(_mov, 2000, ea4f0000), \
9340 X(_movs, 2000, ea5f0000), \
9341 X(_mul, 4340, fb00f000), \
9342 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9343 X(_mvn, 43c0, ea6f0000), \
9344 X(_mvns, 43c0, ea7f0000), \
9345 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9346 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9347 X(_orr, 4300, ea400000), \
9348 X(_orrs, 4300, ea500000), \
9349 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9350 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9351 X(_rev, ba00, fa90f080), \
9352 X(_rev16, ba40, fa90f090), \
9353 X(_revsh, bac0, fa90f0b0), \
9354 X(_ror, 41c0, fa60f000), \
9355 X(_rors, 41c0, fa70f000), \
9356 X(_sbc, 4180, eb600000), \
9357 X(_sbcs, 4180, eb700000), \
9358 X(_stmia, c000, e8800000), \
9359 X(_str, 6000, f8400000), \
9360 X(_strb, 7000, f8000000), \
9361 X(_strh, 8000, f8200000), \
9362 X(_str_sp,9000, f84d0000), \
9363 X(_sub, 1e00, eba00000), \
9364 X(_subs, 1e00, ebb00000), \
9365 X(_subi, 8000, f1a00000), \
9366 X(_subis, 8000, f1b00000), \
9367 X(_sxtb, b240, fa4ff080), \
9368 X(_sxth, b200, fa0ff080), \
9369 X(_tst, 4200, ea100f00), \
9370 X(_uxtb, b2c0, fa5ff080), \
9371 X(_uxth, b280, fa1ff080), \
9372 X(_nop, bf00, f3af8000), \
9373 X(_yield, bf10, f3af8001), \
9374 X(_wfe, bf20, f3af8002), \
9375 X(_wfi, bf30, f3af8003), \
9376 X(_sev, bf40, f3af8004),
9378 /* To catch errors in encoding functions, the codes are all offset by
9379 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9380 as 16-bit instructions. */
9381 #define X(a,b,c) T_MNEM##a
9382 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9385 #define X(a,b,c) 0x##b
9386 static const unsigned short thumb_op16[] = { T16_32_TAB };
9387 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9390 #define X(a,b,c) 0x##c
9391 static const unsigned int thumb_op32[] = { T16_32_TAB };
9392 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9393 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9397 /* Thumb instruction encoders, in alphabetical order. */
9402 do_t_add_sub_w (void)
9406 Rd = inst.operands[0].reg;
9407 Rn = inst.operands[1].reg;
9409 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9410 is the SP-{plus,minus}-immediate form of the instruction. */
9412 constraint (Rd == REG_PC, BAD_PC);
9414 reject_bad_reg (Rd);
9416 inst.instruction |= (Rn << 16) | (Rd << 8);
9417 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9420 /* Parse an add or subtract instruction. We get here with inst.instruction
9421 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9428 Rd = inst.operands[0].reg;
9429 Rs = (inst.operands[1].present
9430 ? inst.operands[1].reg /* Rd, Rs, foo */
9431 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9434 set_it_insn_type_last ();
9442 flags = (inst.instruction == T_MNEM_adds
9443 || inst.instruction == T_MNEM_subs);
9445 narrow = !in_it_block ();
9447 narrow = in_it_block ();
9448 if (!inst.operands[2].isreg)
9452 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9454 add = (inst.instruction == T_MNEM_add
9455 || inst.instruction == T_MNEM_adds);
9457 if (inst.size_req != 4)
9459 /* Attempt to use a narrow opcode, with relaxation if
9461 if (Rd == REG_SP && Rs == REG_SP && !flags)
9462 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9463 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9464 opcode = T_MNEM_add_sp;
9465 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9466 opcode = T_MNEM_add_pc;
9467 else if (Rd <= 7 && Rs <= 7 && narrow)
9470 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9472 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9476 inst.instruction = THUMB_OP16(opcode);
9477 inst.instruction |= (Rd << 4) | Rs;
9478 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9479 if (inst.size_req != 2)
9480 inst.relax = opcode;
9483 constraint (inst.size_req == 2, BAD_HIREG);
9485 if (inst.size_req == 4
9486 || (inst.size_req != 2 && !opcode))
9490 constraint (add, BAD_PC);
9491 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9492 _("only SUBS PC, LR, #const allowed"));
9493 constraint (inst.reloc.exp.X_op != O_constant,
9494 _("expression too complex"));
9495 constraint (inst.reloc.exp.X_add_number < 0
9496 || inst.reloc.exp.X_add_number > 0xff,
9497 _("immediate value out of range"));
9498 inst.instruction = T2_SUBS_PC_LR
9499 | inst.reloc.exp.X_add_number;
9500 inst.reloc.type = BFD_RELOC_UNUSED;
9503 else if (Rs == REG_PC)
9505 /* Always use addw/subw. */
9506 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9507 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9511 inst.instruction = THUMB_OP32 (inst.instruction);
9512 inst.instruction = (inst.instruction & 0xe1ffffff)
9515 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9517 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9519 inst.instruction |= Rd << 8;
9520 inst.instruction |= Rs << 16;
9525 unsigned int value = inst.reloc.exp.X_add_number;
9526 unsigned int shift = inst.operands[2].shift_kind;
9528 Rn = inst.operands[2].reg;
9529 /* See if we can do this with a 16-bit instruction. */
9530 if (!inst.operands[2].shifted && inst.size_req != 4)
9532 if (Rd > 7 || Rs > 7 || Rn > 7)
9537 inst.instruction = ((inst.instruction == T_MNEM_adds
9538 || inst.instruction == T_MNEM_add)
9541 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9545 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9547 /* Thumb-1 cores (except v6-M) require at least one high
9548 register in a narrow non flag setting add. */
9549 if (Rd > 7 || Rn > 7
9550 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9551 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9558 inst.instruction = T_OPCODE_ADD_HI;
9559 inst.instruction |= (Rd & 8) << 4;
9560 inst.instruction |= (Rd & 7);
9561 inst.instruction |= Rn << 3;
9567 constraint (Rd == REG_PC, BAD_PC);
9568 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9569 constraint (Rs == REG_PC, BAD_PC);
9570 reject_bad_reg (Rn);
9572 /* If we get here, it can't be done in 16 bits. */
9573 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9574 _("shift must be constant"));
9575 inst.instruction = THUMB_OP32 (inst.instruction);
9576 inst.instruction |= Rd << 8;
9577 inst.instruction |= Rs << 16;
9578 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9579 _("shift value over 3 not allowed in thumb mode"));
9580 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9581 _("only LSL shift allowed in thumb mode"));
9582 encode_thumb32_shifted_operand (2);
9587 constraint (inst.instruction == T_MNEM_adds
9588 || inst.instruction == T_MNEM_subs,
9591 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9593 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9594 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9597 inst.instruction = (inst.instruction == T_MNEM_add
9599 inst.instruction |= (Rd << 4) | Rs;
9600 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9604 Rn = inst.operands[2].reg;
9605 constraint (inst.operands[2].shifted, _("unshifted register required"));
9607 /* We now have Rd, Rs, and Rn set to registers. */
9608 if (Rd > 7 || Rs > 7 || Rn > 7)
9610 /* Can't do this for SUB. */
9611 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9612 inst.instruction = T_OPCODE_ADD_HI;
9613 inst.instruction |= (Rd & 8) << 4;
9614 inst.instruction |= (Rd & 7);
9616 inst.instruction |= Rn << 3;
9618 inst.instruction |= Rs << 3;
9620 constraint (1, _("dest must overlap one source register"));
9624 inst.instruction = (inst.instruction == T_MNEM_add
9625 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9626 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9636 Rd = inst.operands[0].reg;
9637 reject_bad_reg (Rd);
9639 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9641 /* Defer to section relaxation. */
9642 inst.relax = inst.instruction;
9643 inst.instruction = THUMB_OP16 (inst.instruction);
9644 inst.instruction |= Rd << 4;
9646 else if (unified_syntax && inst.size_req != 2)
9648 /* Generate a 32-bit opcode. */
9649 inst.instruction = THUMB_OP32 (inst.instruction);
9650 inst.instruction |= Rd << 8;
9651 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9652 inst.reloc.pc_rel = 1;
9656 /* Generate a 16-bit opcode. */
9657 inst.instruction = THUMB_OP16 (inst.instruction);
9658 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9659 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9660 inst.reloc.pc_rel = 1;
9662 inst.instruction |= Rd << 4;
9666 /* Arithmetic instructions for which there is just one 16-bit
9667 instruction encoding, and it allows only two low registers.
9668 For maximal compatibility with ARM syntax, we allow three register
9669 operands even when Thumb-32 instructions are not available, as long
9670 as the first two are identical. For instance, both "sbc r0,r1" and
9671 "sbc r0,r0,r1" are allowed. */
9677 Rd = inst.operands[0].reg;
9678 Rs = (inst.operands[1].present
9679 ? inst.operands[1].reg /* Rd, Rs, foo */
9680 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9681 Rn = inst.operands[2].reg;
9683 reject_bad_reg (Rd);
9684 reject_bad_reg (Rs);
9685 if (inst.operands[2].isreg)
9686 reject_bad_reg (Rn);
9690 if (!inst.operands[2].isreg)
9692 /* For an immediate, we always generate a 32-bit opcode;
9693 section relaxation will shrink it later if possible. */
9694 inst.instruction = THUMB_OP32 (inst.instruction);
9695 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9696 inst.instruction |= Rd << 8;
9697 inst.instruction |= Rs << 16;
9698 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9704 /* See if we can do this with a 16-bit instruction. */
9705 if (THUMB_SETS_FLAGS (inst.instruction))
9706 narrow = !in_it_block ();
9708 narrow = in_it_block ();
9710 if (Rd > 7 || Rn > 7 || Rs > 7)
9712 if (inst.operands[2].shifted)
9714 if (inst.size_req == 4)
9720 inst.instruction = THUMB_OP16 (inst.instruction);
9721 inst.instruction |= Rd;
9722 inst.instruction |= Rn << 3;
9726 /* If we get here, it can't be done in 16 bits. */
9727 constraint (inst.operands[2].shifted
9728 && inst.operands[2].immisreg,
9729 _("shift must be constant"));
9730 inst.instruction = THUMB_OP32 (inst.instruction);
9731 inst.instruction |= Rd << 8;
9732 inst.instruction |= Rs << 16;
9733 encode_thumb32_shifted_operand (2);
9738 /* On its face this is a lie - the instruction does set the
9739 flags. However, the only supported mnemonic in this mode
9741 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9743 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9744 _("unshifted register required"));
9745 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9746 constraint (Rd != Rs,
9747 _("dest and source1 must be the same register"));
9749 inst.instruction = THUMB_OP16 (inst.instruction);
9750 inst.instruction |= Rd;
9751 inst.instruction |= Rn << 3;
9755 /* Similarly, but for instructions where the arithmetic operation is
9756 commutative, so we can allow either of them to be different from
9757 the destination operand in a 16-bit instruction. For instance, all
9758 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9765 Rd = inst.operands[0].reg;
9766 Rs = (inst.operands[1].present
9767 ? inst.operands[1].reg /* Rd, Rs, foo */
9768 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9769 Rn = inst.operands[2].reg;
9771 reject_bad_reg (Rd);
9772 reject_bad_reg (Rs);
9773 if (inst.operands[2].isreg)
9774 reject_bad_reg (Rn);
9778 if (!inst.operands[2].isreg)
9780 /* For an immediate, we always generate a 32-bit opcode;
9781 section relaxation will shrink it later if possible. */
9782 inst.instruction = THUMB_OP32 (inst.instruction);
9783 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9784 inst.instruction |= Rd << 8;
9785 inst.instruction |= Rs << 16;
9786 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9792 /* See if we can do this with a 16-bit instruction. */
9793 if (THUMB_SETS_FLAGS (inst.instruction))
9794 narrow = !in_it_block ();
9796 narrow = in_it_block ();
9798 if (Rd > 7 || Rn > 7 || Rs > 7)
9800 if (inst.operands[2].shifted)
9802 if (inst.size_req == 4)
9809 inst.instruction = THUMB_OP16 (inst.instruction);
9810 inst.instruction |= Rd;
9811 inst.instruction |= Rn << 3;
9816 inst.instruction = THUMB_OP16 (inst.instruction);
9817 inst.instruction |= Rd;
9818 inst.instruction |= Rs << 3;
9823 /* If we get here, it can't be done in 16 bits. */
9824 constraint (inst.operands[2].shifted
9825 && inst.operands[2].immisreg,
9826 _("shift must be constant"));
9827 inst.instruction = THUMB_OP32 (inst.instruction);
9828 inst.instruction |= Rd << 8;
9829 inst.instruction |= Rs << 16;
9830 encode_thumb32_shifted_operand (2);
9835 /* On its face this is a lie - the instruction does set the
9836 flags. However, the only supported mnemonic in this mode
9838 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9840 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9841 _("unshifted register required"));
9842 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9844 inst.instruction = THUMB_OP16 (inst.instruction);
9845 inst.instruction |= Rd;
9848 inst.instruction |= Rn << 3;
9850 inst.instruction |= Rs << 3;
9852 constraint (1, _("dest must overlap one source register"));
9859 if (inst.operands[0].present)
9861 constraint ((inst.instruction & 0xf0) != 0x40
9862 && inst.operands[0].imm > 0xf
9863 && inst.operands[0].imm < 0x0,
9864 _("bad barrier type"));
9865 inst.instruction |= inst.operands[0].imm;
9868 inst.instruction |= 0xf;
9875 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9876 constraint (msb > 32, _("bit-field extends past end of register"));
9877 /* The instruction encoding stores the LSB and MSB,
9878 not the LSB and width. */
9879 Rd = inst.operands[0].reg;
9880 reject_bad_reg (Rd);
9881 inst.instruction |= Rd << 8;
9882 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9883 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9884 inst.instruction |= msb - 1;
9893 Rd = inst.operands[0].reg;
9894 reject_bad_reg (Rd);
9896 /* #0 in second position is alternative syntax for bfc, which is
9897 the same instruction but with REG_PC in the Rm field. */
9898 if (!inst.operands[1].isreg)
9902 Rn = inst.operands[1].reg;
9903 reject_bad_reg (Rn);
9906 msb = inst.operands[2].imm + inst.operands[3].imm;
9907 constraint (msb > 32, _("bit-field extends past end of register"));
9908 /* The instruction encoding stores the LSB and MSB,
9909 not the LSB and width. */
9910 inst.instruction |= Rd << 8;
9911 inst.instruction |= Rn << 16;
9912 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9913 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9914 inst.instruction |= msb - 1;
9922 Rd = inst.operands[0].reg;
9923 Rn = inst.operands[1].reg;
9925 reject_bad_reg (Rd);
9926 reject_bad_reg (Rn);
9928 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9929 _("bit-field extends past end of register"));
9930 inst.instruction |= Rd << 8;
9931 inst.instruction |= Rn << 16;
9932 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9933 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9934 inst.instruction |= inst.operands[3].imm - 1;
9937 /* ARM V5 Thumb BLX (argument parse)
9938 BLX <target_addr> which is BLX(1)
9939 BLX <Rm> which is BLX(2)
9940 Unfortunately, there are two different opcodes for this mnemonic.
9941 So, the insns[].value is not used, and the code here zaps values
9942 into inst.instruction.
9944 ??? How to take advantage of the additional two bits of displacement
9945 available in Thumb32 mode? Need new relocation? */
9950 set_it_insn_type_last ();
9952 if (inst.operands[0].isreg)
9954 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9955 /* We have a register, so this is BLX(2). */
9956 inst.instruction |= inst.operands[0].reg << 3;
9960 /* No register. This must be BLX(1). */
9961 inst.instruction = 0xf000e800;
9962 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9974 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9978 /* Conditional branches inside IT blocks are encoded as unconditional
9985 if (cond != COND_ALWAYS)
9986 opcode = T_MNEM_bcond;
9988 opcode = inst.instruction;
9991 && (inst.size_req == 4
9992 || (inst.size_req != 2
9993 && (inst.operands[0].hasreloc
9994 || inst.reloc.exp.X_op == O_constant))))
9996 inst.instruction = THUMB_OP32(opcode);
9997 if (cond == COND_ALWAYS)
9998 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10001 gas_assert (cond != 0xF);
10002 inst.instruction |= cond << 22;
10003 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10008 inst.instruction = THUMB_OP16(opcode);
10009 if (cond == COND_ALWAYS)
10010 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10013 inst.instruction |= cond << 8;
10014 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10016 /* Allow section relaxation. */
10017 if (unified_syntax && inst.size_req != 2)
10018 inst.relax = opcode;
10020 inst.reloc.type = reloc;
10021 inst.reloc.pc_rel = 1;
10027 constraint (inst.cond != COND_ALWAYS,
10028 _("instruction is always unconditional"));
10029 if (inst.operands[0].present)
10031 constraint (inst.operands[0].imm > 255,
10032 _("immediate value out of range"));
10033 inst.instruction |= inst.operands[0].imm;
10034 set_it_insn_type (NEUTRAL_IT_INSN);
10039 do_t_branch23 (void)
10041 set_it_insn_type_last ();
10042 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10044 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10045 this file. We used to simply ignore the PLT reloc type here --
10046 the branch encoding is now needed to deal with TLSCALL relocs.
10047 So if we see a PLT reloc now, put it back to how it used to be to
10048 keep the preexisting behaviour. */
10049 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10050 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10052 #if defined(OBJ_COFF)
10053 /* If the destination of the branch is a defined symbol which does not have
10054 the THUMB_FUNC attribute, then we must be calling a function which has
10055 the (interfacearm) attribute. We look for the Thumb entry point to that
10056 function and change the branch to refer to that function instead. */
10057 if ( inst.reloc.exp.X_op == O_symbol
10058 && inst.reloc.exp.X_add_symbol != NULL
10059 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10060 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10061 inst.reloc.exp.X_add_symbol =
10062 find_real_start (inst.reloc.exp.X_add_symbol);
10069 set_it_insn_type_last ();
10070 inst.instruction |= inst.operands[0].reg << 3;
10071 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10072 should cause the alignment to be checked once it is known. This is
10073 because BX PC only works if the instruction is word aligned. */
10081 set_it_insn_type_last ();
10082 Rm = inst.operands[0].reg;
10083 reject_bad_reg (Rm);
10084 inst.instruction |= Rm << 16;
10093 Rd = inst.operands[0].reg;
10094 Rm = inst.operands[1].reg;
10096 reject_bad_reg (Rd);
10097 reject_bad_reg (Rm);
10099 inst.instruction |= Rd << 8;
10100 inst.instruction |= Rm << 16;
10101 inst.instruction |= Rm;
10107 set_it_insn_type (OUTSIDE_IT_INSN);
10108 inst.instruction |= inst.operands[0].imm;
10114 set_it_insn_type (OUTSIDE_IT_INSN);
10116 && (inst.operands[1].present || inst.size_req == 4)
10117 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10119 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10120 inst.instruction = 0xf3af8000;
10121 inst.instruction |= imod << 9;
10122 inst.instruction |= inst.operands[0].imm << 5;
10123 if (inst.operands[1].present)
10124 inst.instruction |= 0x100 | inst.operands[1].imm;
10128 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10129 && (inst.operands[0].imm & 4),
10130 _("selected processor does not support 'A' form "
10131 "of this instruction"));
10132 constraint (inst.operands[1].present || inst.size_req == 4,
10133 _("Thumb does not support the 2-argument "
10134 "form of this instruction"));
10135 inst.instruction |= inst.operands[0].imm;
10139 /* THUMB CPY instruction (argument parse). */
10144 if (inst.size_req == 4)
10146 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10147 inst.instruction |= inst.operands[0].reg << 8;
10148 inst.instruction |= inst.operands[1].reg;
10152 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10153 inst.instruction |= (inst.operands[0].reg & 0x7);
10154 inst.instruction |= inst.operands[1].reg << 3;
10161 set_it_insn_type (OUTSIDE_IT_INSN);
10162 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10163 inst.instruction |= inst.operands[0].reg;
10164 inst.reloc.pc_rel = 1;
10165 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10171 inst.instruction |= inst.operands[0].imm;
10177 unsigned Rd, Rn, Rm;
10179 Rd = inst.operands[0].reg;
10180 Rn = (inst.operands[1].present
10181 ? inst.operands[1].reg : Rd);
10182 Rm = inst.operands[2].reg;
10184 reject_bad_reg (Rd);
10185 reject_bad_reg (Rn);
10186 reject_bad_reg (Rm);
10188 inst.instruction |= Rd << 8;
10189 inst.instruction |= Rn << 16;
10190 inst.instruction |= Rm;
10196 if (unified_syntax && inst.size_req == 4)
10197 inst.instruction = THUMB_OP32 (inst.instruction);
10199 inst.instruction = THUMB_OP16 (inst.instruction);
10205 unsigned int cond = inst.operands[0].imm;
10207 set_it_insn_type (IT_INSN);
10208 now_it.mask = (inst.instruction & 0xf) | 0x10;
10211 /* If the condition is a negative condition, invert the mask. */
10212 if ((cond & 0x1) == 0x0)
10214 unsigned int mask = inst.instruction & 0x000f;
10216 if ((mask & 0x7) == 0)
10217 /* no conversion needed */;
10218 else if ((mask & 0x3) == 0)
10220 else if ((mask & 0x1) == 0)
10225 inst.instruction &= 0xfff0;
10226 inst.instruction |= mask;
10229 inst.instruction |= cond << 4;
10232 /* Helper function used for both push/pop and ldm/stm. */
10234 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10238 load = (inst.instruction & (1 << 20)) != 0;
10240 if (mask & (1 << 13))
10241 inst.error = _("SP not allowed in register list");
10243 if ((mask & (1 << base)) != 0
10245 inst.error = _("having the base register in the register list when "
10246 "using write back is UNPREDICTABLE");
10250 if (mask & (1 << 15))
10252 if (mask & (1 << 14))
10253 inst.error = _("LR and PC should not both be in register list");
10255 set_it_insn_type_last ();
10260 if (mask & (1 << 15))
10261 inst.error = _("PC not allowed in register list");
10264 if ((mask & (mask - 1)) == 0)
10266 /* Single register transfers implemented as str/ldr. */
10269 if (inst.instruction & (1 << 23))
10270 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10272 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10276 if (inst.instruction & (1 << 23))
10277 inst.instruction = 0x00800000; /* ia -> [base] */
10279 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10282 inst.instruction |= 0xf8400000;
10284 inst.instruction |= 0x00100000;
10286 mask = ffs (mask) - 1;
10289 else if (writeback)
10290 inst.instruction |= WRITE_BACK;
10292 inst.instruction |= mask;
10293 inst.instruction |= base << 16;
10299 /* This really doesn't seem worth it. */
10300 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10301 _("expression too complex"));
10302 constraint (inst.operands[1].writeback,
10303 _("Thumb load/store multiple does not support {reglist}^"));
10305 if (unified_syntax)
10307 bfd_boolean narrow;
10311 /* See if we can use a 16-bit instruction. */
10312 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10313 && inst.size_req != 4
10314 && !(inst.operands[1].imm & ~0xff))
10316 mask = 1 << inst.operands[0].reg;
10318 if (inst.operands[0].reg <= 7)
10320 if (inst.instruction == T_MNEM_stmia
10321 ? inst.operands[0].writeback
10322 : (inst.operands[0].writeback
10323 == !(inst.operands[1].imm & mask)))
10325 if (inst.instruction == T_MNEM_stmia
10326 && (inst.operands[1].imm & mask)
10327 && (inst.operands[1].imm & (mask - 1)))
10328 as_warn (_("value stored for r%d is UNKNOWN"),
10329 inst.operands[0].reg);
10331 inst.instruction = THUMB_OP16 (inst.instruction);
10332 inst.instruction |= inst.operands[0].reg << 8;
10333 inst.instruction |= inst.operands[1].imm;
10336 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10338 /* This means 1 register in reg list one of 3 situations:
10339 1. Instruction is stmia, but without writeback.
10340 2. lmdia without writeback, but with Rn not in
10342 3. ldmia with writeback, but with Rn in reglist.
10343 Case 3 is UNPREDICTABLE behaviour, so we handle
10344 case 1 and 2 which can be converted into a 16-bit
10345 str or ldr. The SP cases are handled below. */
10346 unsigned long opcode;
10347 /* First, record an error for Case 3. */
10348 if (inst.operands[1].imm & mask
10349 && inst.operands[0].writeback)
10351 _("having the base register in the register list when "
10352 "using write back is UNPREDICTABLE");
10354 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10356 inst.instruction = THUMB_OP16 (opcode);
10357 inst.instruction |= inst.operands[0].reg << 3;
10358 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10362 else if (inst.operands[0] .reg == REG_SP)
10364 if (inst.operands[0].writeback)
10367 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10368 ? T_MNEM_push : T_MNEM_pop);
10369 inst.instruction |= inst.operands[1].imm;
10372 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10375 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10376 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10377 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10385 if (inst.instruction < 0xffff)
10386 inst.instruction = THUMB_OP32 (inst.instruction);
10388 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10389 inst.operands[0].writeback);
10394 constraint (inst.operands[0].reg > 7
10395 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10396 constraint (inst.instruction != T_MNEM_ldmia
10397 && inst.instruction != T_MNEM_stmia,
10398 _("Thumb-2 instruction only valid in unified syntax"));
10399 if (inst.instruction == T_MNEM_stmia)
10401 if (!inst.operands[0].writeback)
10402 as_warn (_("this instruction will write back the base register"));
10403 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10404 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10405 as_warn (_("value stored for r%d is UNKNOWN"),
10406 inst.operands[0].reg);
10410 if (!inst.operands[0].writeback
10411 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10412 as_warn (_("this instruction will write back the base register"));
10413 else if (inst.operands[0].writeback
10414 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10415 as_warn (_("this instruction will not write back the base register"));
10418 inst.instruction = THUMB_OP16 (inst.instruction);
10419 inst.instruction |= inst.operands[0].reg << 8;
10420 inst.instruction |= inst.operands[1].imm;
10427 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10428 || inst.operands[1].postind || inst.operands[1].writeback
10429 || inst.operands[1].immisreg || inst.operands[1].shifted
10430 || inst.operands[1].negative,
10433 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10435 inst.instruction |= inst.operands[0].reg << 12;
10436 inst.instruction |= inst.operands[1].reg << 16;
10437 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10443 if (!inst.operands[1].present)
10445 constraint (inst.operands[0].reg == REG_LR,
10446 _("r14 not allowed as first register "
10447 "when second register is omitted"));
10448 inst.operands[1].reg = inst.operands[0].reg + 1;
10450 constraint (inst.operands[0].reg == inst.operands[1].reg,
10453 inst.instruction |= inst.operands[0].reg << 12;
10454 inst.instruction |= inst.operands[1].reg << 8;
10455 inst.instruction |= inst.operands[2].reg << 16;
10461 unsigned long opcode;
10464 if (inst.operands[0].isreg
10465 && !inst.operands[0].preind
10466 && inst.operands[0].reg == REG_PC)
10467 set_it_insn_type_last ();
10469 opcode = inst.instruction;
10470 if (unified_syntax)
10472 if (!inst.operands[1].isreg)
10474 if (opcode <= 0xffff)
10475 inst.instruction = THUMB_OP32 (opcode);
10476 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10479 if (inst.operands[1].isreg
10480 && !inst.operands[1].writeback
10481 && !inst.operands[1].shifted && !inst.operands[1].postind
10482 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10483 && opcode <= 0xffff
10484 && inst.size_req != 4)
10486 /* Insn may have a 16-bit form. */
10487 Rn = inst.operands[1].reg;
10488 if (inst.operands[1].immisreg)
10490 inst.instruction = THUMB_OP16 (opcode);
10492 if (Rn <= 7 && inst.operands[1].imm <= 7)
10494 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10495 reject_bad_reg (inst.operands[1].imm);
10497 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10498 && opcode != T_MNEM_ldrsb)
10499 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10500 || (Rn == REG_SP && opcode == T_MNEM_str))
10507 if (inst.reloc.pc_rel)
10508 opcode = T_MNEM_ldr_pc2;
10510 opcode = T_MNEM_ldr_pc;
10514 if (opcode == T_MNEM_ldr)
10515 opcode = T_MNEM_ldr_sp;
10517 opcode = T_MNEM_str_sp;
10519 inst.instruction = inst.operands[0].reg << 8;
10523 inst.instruction = inst.operands[0].reg;
10524 inst.instruction |= inst.operands[1].reg << 3;
10526 inst.instruction |= THUMB_OP16 (opcode);
10527 if (inst.size_req == 2)
10528 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10530 inst.relax = opcode;
10534 /* Definitely a 32-bit variant. */
10536 /* Warning for Erratum 752419. */
10537 if (opcode == T_MNEM_ldr
10538 && inst.operands[0].reg == REG_SP
10539 && inst.operands[1].writeback == 1
10540 && !inst.operands[1].immisreg)
10542 if (no_cpu_selected ()
10543 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10544 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10545 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10546 as_warn (_("This instruction may be unpredictable "
10547 "if executed on M-profile cores "
10548 "with interrupts enabled."));
10551 /* Do some validations regarding addressing modes. */
10552 if (inst.operands[1].immisreg)
10553 reject_bad_reg (inst.operands[1].imm);
10555 constraint (inst.operands[1].writeback == 1
10556 && inst.operands[0].reg == inst.operands[1].reg,
10559 inst.instruction = THUMB_OP32 (opcode);
10560 inst.instruction |= inst.operands[0].reg << 12;
10561 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10562 check_ldr_r15_aligned ();
10566 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10568 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10570 /* Only [Rn,Rm] is acceptable. */
10571 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10572 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10573 || inst.operands[1].postind || inst.operands[1].shifted
10574 || inst.operands[1].negative,
10575 _("Thumb does not support this addressing mode"));
10576 inst.instruction = THUMB_OP16 (inst.instruction);
10580 inst.instruction = THUMB_OP16 (inst.instruction);
10581 if (!inst.operands[1].isreg)
10582 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10585 constraint (!inst.operands[1].preind
10586 || inst.operands[1].shifted
10587 || inst.operands[1].writeback,
10588 _("Thumb does not support this addressing mode"));
10589 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10591 constraint (inst.instruction & 0x0600,
10592 _("byte or halfword not valid for base register"));
10593 constraint (inst.operands[1].reg == REG_PC
10594 && !(inst.instruction & THUMB_LOAD_BIT),
10595 _("r15 based store not allowed"));
10596 constraint (inst.operands[1].immisreg,
10597 _("invalid base register for register offset"));
10599 if (inst.operands[1].reg == REG_PC)
10600 inst.instruction = T_OPCODE_LDR_PC;
10601 else if (inst.instruction & THUMB_LOAD_BIT)
10602 inst.instruction = T_OPCODE_LDR_SP;
10604 inst.instruction = T_OPCODE_STR_SP;
10606 inst.instruction |= inst.operands[0].reg << 8;
10607 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10611 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10612 if (!inst.operands[1].immisreg)
10614 /* Immediate offset. */
10615 inst.instruction |= inst.operands[0].reg;
10616 inst.instruction |= inst.operands[1].reg << 3;
10617 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10621 /* Register offset. */
10622 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10623 constraint (inst.operands[1].negative,
10624 _("Thumb does not support this addressing mode"));
10627 switch (inst.instruction)
10629 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10630 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10631 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10632 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10633 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10634 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10635 case 0x5600 /* ldrsb */:
10636 case 0x5e00 /* ldrsh */: break;
10640 inst.instruction |= inst.operands[0].reg;
10641 inst.instruction |= inst.operands[1].reg << 3;
10642 inst.instruction |= inst.operands[1].imm << 6;
10648 if (!inst.operands[1].present)
10650 inst.operands[1].reg = inst.operands[0].reg + 1;
10651 constraint (inst.operands[0].reg == REG_LR,
10652 _("r14 not allowed here"));
10654 inst.instruction |= inst.operands[0].reg << 12;
10655 inst.instruction |= inst.operands[1].reg << 8;
10656 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10662 inst.instruction |= inst.operands[0].reg << 12;
10663 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10669 unsigned Rd, Rn, Rm, Ra;
10671 Rd = inst.operands[0].reg;
10672 Rn = inst.operands[1].reg;
10673 Rm = inst.operands[2].reg;
10674 Ra = inst.operands[3].reg;
10676 reject_bad_reg (Rd);
10677 reject_bad_reg (Rn);
10678 reject_bad_reg (Rm);
10679 reject_bad_reg (Ra);
10681 inst.instruction |= Rd << 8;
10682 inst.instruction |= Rn << 16;
10683 inst.instruction |= Rm;
10684 inst.instruction |= Ra << 12;
10690 unsigned RdLo, RdHi, Rn, Rm;
10692 RdLo = inst.operands[0].reg;
10693 RdHi = inst.operands[1].reg;
10694 Rn = inst.operands[2].reg;
10695 Rm = inst.operands[3].reg;
10697 reject_bad_reg (RdLo);
10698 reject_bad_reg (RdHi);
10699 reject_bad_reg (Rn);
10700 reject_bad_reg (Rm);
10702 inst.instruction |= RdLo << 12;
10703 inst.instruction |= RdHi << 8;
10704 inst.instruction |= Rn << 16;
10705 inst.instruction |= Rm;
10709 do_t_mov_cmp (void)
10713 Rn = inst.operands[0].reg;
10714 Rm = inst.operands[1].reg;
10717 set_it_insn_type_last ();
10719 if (unified_syntax)
10721 int r0off = (inst.instruction == T_MNEM_mov
10722 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10723 unsigned long opcode;
10724 bfd_boolean narrow;
10725 bfd_boolean low_regs;
10727 low_regs = (Rn <= 7 && Rm <= 7);
10728 opcode = inst.instruction;
10729 if (in_it_block ())
10730 narrow = opcode != T_MNEM_movs;
10732 narrow = opcode != T_MNEM_movs || low_regs;
10733 if (inst.size_req == 4
10734 || inst.operands[1].shifted)
10737 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10738 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10739 && !inst.operands[1].shifted
10743 inst.instruction = T2_SUBS_PC_LR;
10747 if (opcode == T_MNEM_cmp)
10749 constraint (Rn == REG_PC, BAD_PC);
10752 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10754 warn_deprecated_sp (Rm);
10755 /* R15 was documented as a valid choice for Rm in ARMv6,
10756 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10757 tools reject R15, so we do too. */
10758 constraint (Rm == REG_PC, BAD_PC);
10761 reject_bad_reg (Rm);
10763 else if (opcode == T_MNEM_mov
10764 || opcode == T_MNEM_movs)
10766 if (inst.operands[1].isreg)
10768 if (opcode == T_MNEM_movs)
10770 reject_bad_reg (Rn);
10771 reject_bad_reg (Rm);
10775 /* This is mov.n. */
10776 if ((Rn == REG_SP || Rn == REG_PC)
10777 && (Rm == REG_SP || Rm == REG_PC))
10779 as_warn (_("Use of r%u as a source register is "
10780 "deprecated when r%u is the destination "
10781 "register."), Rm, Rn);
10786 /* This is mov.w. */
10787 constraint (Rn == REG_PC, BAD_PC);
10788 constraint (Rm == REG_PC, BAD_PC);
10789 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10793 reject_bad_reg (Rn);
10796 if (!inst.operands[1].isreg)
10798 /* Immediate operand. */
10799 if (!in_it_block () && opcode == T_MNEM_mov)
10801 if (low_regs && narrow)
10803 inst.instruction = THUMB_OP16 (opcode);
10804 inst.instruction |= Rn << 8;
10805 if (inst.size_req == 2)
10806 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10808 inst.relax = opcode;
10812 inst.instruction = THUMB_OP32 (inst.instruction);
10813 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10814 inst.instruction |= Rn << r0off;
10815 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10818 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10819 && (inst.instruction == T_MNEM_mov
10820 || inst.instruction == T_MNEM_movs))
10822 /* Register shifts are encoded as separate shift instructions. */
10823 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10825 if (in_it_block ())
10830 if (inst.size_req == 4)
10833 if (!low_regs || inst.operands[1].imm > 7)
10839 switch (inst.operands[1].shift_kind)
10842 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10845 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10848 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10851 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10857 inst.instruction = opcode;
10860 inst.instruction |= Rn;
10861 inst.instruction |= inst.operands[1].imm << 3;
10866 inst.instruction |= CONDS_BIT;
10868 inst.instruction |= Rn << 8;
10869 inst.instruction |= Rm << 16;
10870 inst.instruction |= inst.operands[1].imm;
10875 /* Some mov with immediate shift have narrow variants.
10876 Register shifts are handled above. */
10877 if (low_regs && inst.operands[1].shifted
10878 && (inst.instruction == T_MNEM_mov
10879 || inst.instruction == T_MNEM_movs))
10881 if (in_it_block ())
10882 narrow = (inst.instruction == T_MNEM_mov);
10884 narrow = (inst.instruction == T_MNEM_movs);
10889 switch (inst.operands[1].shift_kind)
10891 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10892 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10893 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10894 default: narrow = FALSE; break;
10900 inst.instruction |= Rn;
10901 inst.instruction |= Rm << 3;
10902 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10906 inst.instruction = THUMB_OP32 (inst.instruction);
10907 inst.instruction |= Rn << r0off;
10908 encode_thumb32_shifted_operand (1);
10912 switch (inst.instruction)
10915 inst.instruction = T_OPCODE_MOV_HR;
10916 inst.instruction |= (Rn & 0x8) << 4;
10917 inst.instruction |= (Rn & 0x7);
10918 inst.instruction |= Rm << 3;
10922 /* We know we have low registers at this point.
10923 Generate LSLS Rd, Rs, #0. */
10924 inst.instruction = T_OPCODE_LSL_I;
10925 inst.instruction |= Rn;
10926 inst.instruction |= Rm << 3;
10932 inst.instruction = T_OPCODE_CMP_LR;
10933 inst.instruction |= Rn;
10934 inst.instruction |= Rm << 3;
10938 inst.instruction = T_OPCODE_CMP_HR;
10939 inst.instruction |= (Rn & 0x8) << 4;
10940 inst.instruction |= (Rn & 0x7);
10941 inst.instruction |= Rm << 3;
10948 inst.instruction = THUMB_OP16 (inst.instruction);
10950 /* PR 10443: Do not silently ignore shifted operands. */
10951 constraint (inst.operands[1].shifted,
10952 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10954 if (inst.operands[1].isreg)
10956 if (Rn < 8 && Rm < 8)
10958 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10959 since a MOV instruction produces unpredictable results. */
10960 if (inst.instruction == T_OPCODE_MOV_I8)
10961 inst.instruction = T_OPCODE_ADD_I3;
10963 inst.instruction = T_OPCODE_CMP_LR;
10965 inst.instruction |= Rn;
10966 inst.instruction |= Rm << 3;
10970 if (inst.instruction == T_OPCODE_MOV_I8)
10971 inst.instruction = T_OPCODE_MOV_HR;
10973 inst.instruction = T_OPCODE_CMP_HR;
10979 constraint (Rn > 7,
10980 _("only lo regs allowed with immediate"));
10981 inst.instruction |= Rn << 8;
10982 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10993 top = (inst.instruction & 0x00800000) != 0;
10994 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10996 constraint (top, _(":lower16: not allowed this instruction"));
10997 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10999 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11001 constraint (!top, _(":upper16: not allowed this instruction"));
11002 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11005 Rd = inst.operands[0].reg;
11006 reject_bad_reg (Rd);
11008 inst.instruction |= Rd << 8;
11009 if (inst.reloc.type == BFD_RELOC_UNUSED)
11011 imm = inst.reloc.exp.X_add_number;
11012 inst.instruction |= (imm & 0xf000) << 4;
11013 inst.instruction |= (imm & 0x0800) << 15;
11014 inst.instruction |= (imm & 0x0700) << 4;
11015 inst.instruction |= (imm & 0x00ff);
11020 do_t_mvn_tst (void)
11024 Rn = inst.operands[0].reg;
11025 Rm = inst.operands[1].reg;
11027 if (inst.instruction == T_MNEM_cmp
11028 || inst.instruction == T_MNEM_cmn)
11029 constraint (Rn == REG_PC, BAD_PC);
11031 reject_bad_reg (Rn);
11032 reject_bad_reg (Rm);
11034 if (unified_syntax)
11036 int r0off = (inst.instruction == T_MNEM_mvn
11037 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11038 bfd_boolean narrow;
11040 if (inst.size_req == 4
11041 || inst.instruction > 0xffff
11042 || inst.operands[1].shifted
11043 || Rn > 7 || Rm > 7)
11045 else if (inst.instruction == T_MNEM_cmn)
11047 else if (THUMB_SETS_FLAGS (inst.instruction))
11048 narrow = !in_it_block ();
11050 narrow = in_it_block ();
11052 if (!inst.operands[1].isreg)
11054 /* For an immediate, we always generate a 32-bit opcode;
11055 section relaxation will shrink it later if possible. */
11056 if (inst.instruction < 0xffff)
11057 inst.instruction = THUMB_OP32 (inst.instruction);
11058 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11059 inst.instruction |= Rn << r0off;
11060 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11064 /* See if we can do this with a 16-bit instruction. */
11067 inst.instruction = THUMB_OP16 (inst.instruction);
11068 inst.instruction |= Rn;
11069 inst.instruction |= Rm << 3;
11073 constraint (inst.operands[1].shifted
11074 && inst.operands[1].immisreg,
11075 _("shift must be constant"));
11076 if (inst.instruction < 0xffff)
11077 inst.instruction = THUMB_OP32 (inst.instruction);
11078 inst.instruction |= Rn << r0off;
11079 encode_thumb32_shifted_operand (1);
11085 constraint (inst.instruction > 0xffff
11086 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11087 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11088 _("unshifted register required"));
11089 constraint (Rn > 7 || Rm > 7,
11092 inst.instruction = THUMB_OP16 (inst.instruction);
11093 inst.instruction |= Rn;
11094 inst.instruction |= Rm << 3;
11103 if (do_vfp_nsyn_mrs () == SUCCESS)
11106 Rd = inst.operands[0].reg;
11107 reject_bad_reg (Rd);
11108 inst.instruction |= Rd << 8;
11110 if (inst.operands[1].isreg)
11112 unsigned br = inst.operands[1].reg;
11113 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11114 as_bad (_("bad register for mrs"));
11116 inst.instruction |= br & (0xf << 16);
11117 inst.instruction |= (br & 0x300) >> 4;
11118 inst.instruction |= (br & SPSR_BIT) >> 2;
11122 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11124 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11125 constraint (flags != 0, _("selected processor does not support "
11126 "requested special purpose register"));
11128 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11130 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11131 _("'APSR', 'CPSR' or 'SPSR' expected"));
11133 inst.instruction |= (flags & SPSR_BIT) >> 2;
11134 inst.instruction |= inst.operands[1].imm & 0xff;
11135 inst.instruction |= 0xf0000;
11145 if (do_vfp_nsyn_msr () == SUCCESS)
11148 constraint (!inst.operands[1].isreg,
11149 _("Thumb encoding does not support an immediate here"));
11151 if (inst.operands[0].isreg)
11152 flags = (int)(inst.operands[0].reg);
11154 flags = inst.operands[0].imm;
11156 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11158 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11160 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11161 && (bits & ~(PSR_s | PSR_f)) != 0)
11162 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11164 _("selected processor does not support requested special "
11165 "purpose register"));
11168 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11169 "requested special purpose register"));
11171 Rn = inst.operands[1].reg;
11172 reject_bad_reg (Rn);
11174 inst.instruction |= (flags & SPSR_BIT) >> 2;
11175 inst.instruction |= (flags & 0xf0000) >> 8;
11176 inst.instruction |= (flags & 0x300) >> 4;
11177 inst.instruction |= (flags & 0xff);
11178 inst.instruction |= Rn << 16;
11184 bfd_boolean narrow;
11185 unsigned Rd, Rn, Rm;
11187 if (!inst.operands[2].present)
11188 inst.operands[2].reg = inst.operands[0].reg;
11190 Rd = inst.operands[0].reg;
11191 Rn = inst.operands[1].reg;
11192 Rm = inst.operands[2].reg;
11194 if (unified_syntax)
11196 if (inst.size_req == 4
11202 else if (inst.instruction == T_MNEM_muls)
11203 narrow = !in_it_block ();
11205 narrow = in_it_block ();
11209 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11210 constraint (Rn > 7 || Rm > 7,
11217 /* 16-bit MULS/Conditional MUL. */
11218 inst.instruction = THUMB_OP16 (inst.instruction);
11219 inst.instruction |= Rd;
11222 inst.instruction |= Rm << 3;
11224 inst.instruction |= Rn << 3;
11226 constraint (1, _("dest must overlap one source register"));
11230 constraint (inst.instruction != T_MNEM_mul,
11231 _("Thumb-2 MUL must not set flags"));
11233 inst.instruction = THUMB_OP32 (inst.instruction);
11234 inst.instruction |= Rd << 8;
11235 inst.instruction |= Rn << 16;
11236 inst.instruction |= Rm << 0;
11238 reject_bad_reg (Rd);
11239 reject_bad_reg (Rn);
11240 reject_bad_reg (Rm);
11247 unsigned RdLo, RdHi, Rn, Rm;
11249 RdLo = inst.operands[0].reg;
11250 RdHi = inst.operands[1].reg;
11251 Rn = inst.operands[2].reg;
11252 Rm = inst.operands[3].reg;
11254 reject_bad_reg (RdLo);
11255 reject_bad_reg (RdHi);
11256 reject_bad_reg (Rn);
11257 reject_bad_reg (Rm);
11259 inst.instruction |= RdLo << 12;
11260 inst.instruction |= RdHi << 8;
11261 inst.instruction |= Rn << 16;
11262 inst.instruction |= Rm;
11265 as_tsktsk (_("rdhi and rdlo must be different"));
11271 set_it_insn_type (NEUTRAL_IT_INSN);
11273 if (unified_syntax)
11275 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11277 inst.instruction = THUMB_OP32 (inst.instruction);
11278 inst.instruction |= inst.operands[0].imm;
11282 /* PR9722: Check for Thumb2 availability before
11283 generating a thumb2 nop instruction. */
11284 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11286 inst.instruction = THUMB_OP16 (inst.instruction);
11287 inst.instruction |= inst.operands[0].imm << 4;
11290 inst.instruction = 0x46c0;
11295 constraint (inst.operands[0].present,
11296 _("Thumb does not support NOP with hints"));
11297 inst.instruction = 0x46c0;
11304 if (unified_syntax)
11306 bfd_boolean narrow;
11308 if (THUMB_SETS_FLAGS (inst.instruction))
11309 narrow = !in_it_block ();
11311 narrow = in_it_block ();
11312 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11314 if (inst.size_req == 4)
11319 inst.instruction = THUMB_OP32 (inst.instruction);
11320 inst.instruction |= inst.operands[0].reg << 8;
11321 inst.instruction |= inst.operands[1].reg << 16;
11325 inst.instruction = THUMB_OP16 (inst.instruction);
11326 inst.instruction |= inst.operands[0].reg;
11327 inst.instruction |= inst.operands[1].reg << 3;
11332 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11334 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11336 inst.instruction = THUMB_OP16 (inst.instruction);
11337 inst.instruction |= inst.operands[0].reg;
11338 inst.instruction |= inst.operands[1].reg << 3;
11347 Rd = inst.operands[0].reg;
11348 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11350 reject_bad_reg (Rd);
11351 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11352 reject_bad_reg (Rn);
11354 inst.instruction |= Rd << 8;
11355 inst.instruction |= Rn << 16;
11357 if (!inst.operands[2].isreg)
11359 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11360 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11366 Rm = inst.operands[2].reg;
11367 reject_bad_reg (Rm);
11369 constraint (inst.operands[2].shifted
11370 && inst.operands[2].immisreg,
11371 _("shift must be constant"));
11372 encode_thumb32_shifted_operand (2);
11379 unsigned Rd, Rn, Rm;
11381 Rd = inst.operands[0].reg;
11382 Rn = inst.operands[1].reg;
11383 Rm = inst.operands[2].reg;
11385 reject_bad_reg (Rd);
11386 reject_bad_reg (Rn);
11387 reject_bad_reg (Rm);
11389 inst.instruction |= Rd << 8;
11390 inst.instruction |= Rn << 16;
11391 inst.instruction |= Rm;
11392 if (inst.operands[3].present)
11394 unsigned int val = inst.reloc.exp.X_add_number;
11395 constraint (inst.reloc.exp.X_op != O_constant,
11396 _("expression too complex"));
11397 inst.instruction |= (val & 0x1c) << 10;
11398 inst.instruction |= (val & 0x03) << 6;
11405 if (!inst.operands[3].present)
11409 inst.instruction &= ~0x00000020;
11411 /* PR 10168. Swap the Rm and Rn registers. */
11412 Rtmp = inst.operands[1].reg;
11413 inst.operands[1].reg = inst.operands[2].reg;
11414 inst.operands[2].reg = Rtmp;
11422 if (inst.operands[0].immisreg)
11423 reject_bad_reg (inst.operands[0].imm);
11425 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11429 do_t_push_pop (void)
11433 constraint (inst.operands[0].writeback,
11434 _("push/pop do not support {reglist}^"));
11435 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11436 _("expression too complex"));
11438 mask = inst.operands[0].imm;
11439 if ((mask & ~0xff) == 0)
11440 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11441 else if ((inst.instruction == T_MNEM_push
11442 && (mask & ~0xff) == 1 << REG_LR)
11443 || (inst.instruction == T_MNEM_pop
11444 && (mask & ~0xff) == 1 << REG_PC))
11446 inst.instruction = THUMB_OP16 (inst.instruction);
11447 inst.instruction |= THUMB_PP_PC_LR;
11448 inst.instruction |= mask & 0xff;
11450 else if (unified_syntax)
11452 inst.instruction = THUMB_OP32 (inst.instruction);
11453 encode_thumb2_ldmstm (13, mask, TRUE);
11457 inst.error = _("invalid register list to push/pop instruction");
11467 Rd = inst.operands[0].reg;
11468 Rm = inst.operands[1].reg;
11470 reject_bad_reg (Rd);
11471 reject_bad_reg (Rm);
11473 inst.instruction |= Rd << 8;
11474 inst.instruction |= Rm << 16;
11475 inst.instruction |= Rm;
11483 Rd = inst.operands[0].reg;
11484 Rm = inst.operands[1].reg;
11486 reject_bad_reg (Rd);
11487 reject_bad_reg (Rm);
11489 if (Rd <= 7 && Rm <= 7
11490 && inst.size_req != 4)
11492 inst.instruction = THUMB_OP16 (inst.instruction);
11493 inst.instruction |= Rd;
11494 inst.instruction |= Rm << 3;
11496 else if (unified_syntax)
11498 inst.instruction = THUMB_OP32 (inst.instruction);
11499 inst.instruction |= Rd << 8;
11500 inst.instruction |= Rm << 16;
11501 inst.instruction |= Rm;
11504 inst.error = BAD_HIREG;
11512 Rd = inst.operands[0].reg;
11513 Rm = inst.operands[1].reg;
11515 reject_bad_reg (Rd);
11516 reject_bad_reg (Rm);
11518 inst.instruction |= Rd << 8;
11519 inst.instruction |= Rm;
11527 Rd = inst.operands[0].reg;
11528 Rs = (inst.operands[1].present
11529 ? inst.operands[1].reg /* Rd, Rs, foo */
11530 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11532 reject_bad_reg (Rd);
11533 reject_bad_reg (Rs);
11534 if (inst.operands[2].isreg)
11535 reject_bad_reg (inst.operands[2].reg);
11537 inst.instruction |= Rd << 8;
11538 inst.instruction |= Rs << 16;
11539 if (!inst.operands[2].isreg)
11541 bfd_boolean narrow;
11543 if ((inst.instruction & 0x00100000) != 0)
11544 narrow = !in_it_block ();
11546 narrow = in_it_block ();
11548 if (Rd > 7 || Rs > 7)
11551 if (inst.size_req == 4 || !unified_syntax)
11554 if (inst.reloc.exp.X_op != O_constant
11555 || inst.reloc.exp.X_add_number != 0)
11558 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11559 relaxation, but it doesn't seem worth the hassle. */
11562 inst.reloc.type = BFD_RELOC_UNUSED;
11563 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11564 inst.instruction |= Rs << 3;
11565 inst.instruction |= Rd;
11569 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11570 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11574 encode_thumb32_shifted_operand (2);
11580 set_it_insn_type (OUTSIDE_IT_INSN);
11581 if (inst.operands[0].imm)
11582 inst.instruction |= 0x8;
11588 if (!inst.operands[1].present)
11589 inst.operands[1].reg = inst.operands[0].reg;
11591 if (unified_syntax)
11593 bfd_boolean narrow;
11596 switch (inst.instruction)
11599 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11601 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11603 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11605 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11609 if (THUMB_SETS_FLAGS (inst.instruction))
11610 narrow = !in_it_block ();
11612 narrow = in_it_block ();
11613 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11615 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11617 if (inst.operands[2].isreg
11618 && (inst.operands[1].reg != inst.operands[0].reg
11619 || inst.operands[2].reg > 7))
11621 if (inst.size_req == 4)
11624 reject_bad_reg (inst.operands[0].reg);
11625 reject_bad_reg (inst.operands[1].reg);
11629 if (inst.operands[2].isreg)
11631 reject_bad_reg (inst.operands[2].reg);
11632 inst.instruction = THUMB_OP32 (inst.instruction);
11633 inst.instruction |= inst.operands[0].reg << 8;
11634 inst.instruction |= inst.operands[1].reg << 16;
11635 inst.instruction |= inst.operands[2].reg;
11637 /* PR 12854: Error on extraneous shifts. */
11638 constraint (inst.operands[2].shifted,
11639 _("extraneous shift as part of operand to shift insn"));
11643 inst.operands[1].shifted = 1;
11644 inst.operands[1].shift_kind = shift_kind;
11645 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11646 ? T_MNEM_movs : T_MNEM_mov);
11647 inst.instruction |= inst.operands[0].reg << 8;
11648 encode_thumb32_shifted_operand (1);
11649 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11650 inst.reloc.type = BFD_RELOC_UNUSED;
11655 if (inst.operands[2].isreg)
11657 switch (shift_kind)
11659 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11660 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11661 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11662 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11666 inst.instruction |= inst.operands[0].reg;
11667 inst.instruction |= inst.operands[2].reg << 3;
11669 /* PR 12854: Error on extraneous shifts. */
11670 constraint (inst.operands[2].shifted,
11671 _("extraneous shift as part of operand to shift insn"));
11675 switch (shift_kind)
11677 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11678 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11679 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11682 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11683 inst.instruction |= inst.operands[0].reg;
11684 inst.instruction |= inst.operands[1].reg << 3;
11690 constraint (inst.operands[0].reg > 7
11691 || inst.operands[1].reg > 7, BAD_HIREG);
11692 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11694 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11696 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11697 constraint (inst.operands[0].reg != inst.operands[1].reg,
11698 _("source1 and dest must be same register"));
11700 switch (inst.instruction)
11702 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11703 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11704 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11705 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11709 inst.instruction |= inst.operands[0].reg;
11710 inst.instruction |= inst.operands[2].reg << 3;
11712 /* PR 12854: Error on extraneous shifts. */
11713 constraint (inst.operands[2].shifted,
11714 _("extraneous shift as part of operand to shift insn"));
11718 switch (inst.instruction)
11720 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11721 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11722 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11723 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11726 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11727 inst.instruction |= inst.operands[0].reg;
11728 inst.instruction |= inst.operands[1].reg << 3;
11736 unsigned Rd, Rn, Rm;
11738 Rd = inst.operands[0].reg;
11739 Rn = inst.operands[1].reg;
11740 Rm = inst.operands[2].reg;
11742 reject_bad_reg (Rd);
11743 reject_bad_reg (Rn);
11744 reject_bad_reg (Rm);
11746 inst.instruction |= Rd << 8;
11747 inst.instruction |= Rn << 16;
11748 inst.instruction |= Rm;
11754 unsigned Rd, Rn, Rm;
11756 Rd = inst.operands[0].reg;
11757 Rm = inst.operands[1].reg;
11758 Rn = inst.operands[2].reg;
11760 reject_bad_reg (Rd);
11761 reject_bad_reg (Rn);
11762 reject_bad_reg (Rm);
11764 inst.instruction |= Rd << 8;
11765 inst.instruction |= Rn << 16;
11766 inst.instruction |= Rm;
11772 unsigned int value = inst.reloc.exp.X_add_number;
11773 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11774 _("SMC is not permitted on this architecture"));
11775 constraint (inst.reloc.exp.X_op != O_constant,
11776 _("expression too complex"));
11777 inst.reloc.type = BFD_RELOC_UNUSED;
11778 inst.instruction |= (value & 0xf000) >> 12;
11779 inst.instruction |= (value & 0x0ff0);
11780 inst.instruction |= (value & 0x000f) << 16;
11786 unsigned int value = inst.reloc.exp.X_add_number;
11788 inst.reloc.type = BFD_RELOC_UNUSED;
11789 inst.instruction |= (value & 0x0fff);
11790 inst.instruction |= (value & 0xf000) << 4;
11794 do_t_ssat_usat (int bias)
11798 Rd = inst.operands[0].reg;
11799 Rn = inst.operands[2].reg;
11801 reject_bad_reg (Rd);
11802 reject_bad_reg (Rn);
11804 inst.instruction |= Rd << 8;
11805 inst.instruction |= inst.operands[1].imm - bias;
11806 inst.instruction |= Rn << 16;
11808 if (inst.operands[3].present)
11810 offsetT shift_amount = inst.reloc.exp.X_add_number;
11812 inst.reloc.type = BFD_RELOC_UNUSED;
11814 constraint (inst.reloc.exp.X_op != O_constant,
11815 _("expression too complex"));
11817 if (shift_amount != 0)
11819 constraint (shift_amount > 31,
11820 _("shift expression is too large"));
11822 if (inst.operands[3].shift_kind == SHIFT_ASR)
11823 inst.instruction |= 0x00200000; /* sh bit. */
11825 inst.instruction |= (shift_amount & 0x1c) << 10;
11826 inst.instruction |= (shift_amount & 0x03) << 6;
11834 do_t_ssat_usat (1);
11842 Rd = inst.operands[0].reg;
11843 Rn = inst.operands[2].reg;
11845 reject_bad_reg (Rd);
11846 reject_bad_reg (Rn);
11848 inst.instruction |= Rd << 8;
11849 inst.instruction |= inst.operands[1].imm - 1;
11850 inst.instruction |= Rn << 16;
11856 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11857 || inst.operands[2].postind || inst.operands[2].writeback
11858 || inst.operands[2].immisreg || inst.operands[2].shifted
11859 || inst.operands[2].negative,
11862 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11864 inst.instruction |= inst.operands[0].reg << 8;
11865 inst.instruction |= inst.operands[1].reg << 12;
11866 inst.instruction |= inst.operands[2].reg << 16;
11867 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11873 if (!inst.operands[2].present)
11874 inst.operands[2].reg = inst.operands[1].reg + 1;
11876 constraint (inst.operands[0].reg == inst.operands[1].reg
11877 || inst.operands[0].reg == inst.operands[2].reg
11878 || inst.operands[0].reg == inst.operands[3].reg,
11881 inst.instruction |= inst.operands[0].reg;
11882 inst.instruction |= inst.operands[1].reg << 12;
11883 inst.instruction |= inst.operands[2].reg << 8;
11884 inst.instruction |= inst.operands[3].reg << 16;
11890 unsigned Rd, Rn, Rm;
11892 Rd = inst.operands[0].reg;
11893 Rn = inst.operands[1].reg;
11894 Rm = inst.operands[2].reg;
11896 reject_bad_reg (Rd);
11897 reject_bad_reg (Rn);
11898 reject_bad_reg (Rm);
11900 inst.instruction |= Rd << 8;
11901 inst.instruction |= Rn << 16;
11902 inst.instruction |= Rm;
11903 inst.instruction |= inst.operands[3].imm << 4;
11911 Rd = inst.operands[0].reg;
11912 Rm = inst.operands[1].reg;
11914 reject_bad_reg (Rd);
11915 reject_bad_reg (Rm);
11917 if (inst.instruction <= 0xffff
11918 && inst.size_req != 4
11919 && Rd <= 7 && Rm <= 7
11920 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11922 inst.instruction = THUMB_OP16 (inst.instruction);
11923 inst.instruction |= Rd;
11924 inst.instruction |= Rm << 3;
11926 else if (unified_syntax)
11928 if (inst.instruction <= 0xffff)
11929 inst.instruction = THUMB_OP32 (inst.instruction);
11930 inst.instruction |= Rd << 8;
11931 inst.instruction |= Rm;
11932 inst.instruction |= inst.operands[2].imm << 4;
11936 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11937 _("Thumb encoding does not support rotation"));
11938 constraint (1, BAD_HIREG);
11945 /* We have to do the following check manually as ARM_EXT_OS only applies
11947 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11949 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11950 /* This only applies to the v6m howver, not later architectures. */
11951 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11952 as_bad (_("SVC is not permitted on this architecture"));
11953 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11956 inst.reloc.type = BFD_RELOC_ARM_SWI;
11965 half = (inst.instruction & 0x10) != 0;
11966 set_it_insn_type_last ();
11967 constraint (inst.operands[0].immisreg,
11968 _("instruction requires register index"));
11970 Rn = inst.operands[0].reg;
11971 Rm = inst.operands[0].imm;
11973 constraint (Rn == REG_SP, BAD_SP);
11974 reject_bad_reg (Rm);
11976 constraint (!half && inst.operands[0].shifted,
11977 _("instruction does not allow shifted index"));
11978 inst.instruction |= (Rn << 16) | Rm;
11984 do_t_ssat_usat (0);
11992 Rd = inst.operands[0].reg;
11993 Rn = inst.operands[2].reg;
11995 reject_bad_reg (Rd);
11996 reject_bad_reg (Rn);
11998 inst.instruction |= Rd << 8;
11999 inst.instruction |= inst.operands[1].imm;
12000 inst.instruction |= Rn << 16;
12003 /* Neon instruction encoder helpers. */
12005 /* Encodings for the different types for various Neon opcodes. */
12007 /* An "invalid" code for the following tables. */
12010 struct neon_tab_entry
12013 unsigned float_or_poly;
12014 unsigned scalar_or_imm;
12017 /* Map overloaded Neon opcodes to their respective encodings. */
12018 #define NEON_ENC_TAB \
12019 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12020 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12021 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12022 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12023 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12024 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12025 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12026 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12027 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12028 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12029 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12030 /* Register variants of the following two instructions are encoded as
12031 vcge / vcgt with the operands reversed. */ \
12032 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12033 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12034 X(vfma, N_INV, 0x0000c10, N_INV), \
12035 X(vfms, N_INV, 0x0200c10, N_INV), \
12036 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12037 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12038 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12039 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12040 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12041 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12042 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12043 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12044 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12045 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12046 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12047 X(vshl, 0x0000400, N_INV, 0x0800510), \
12048 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12049 X(vand, 0x0000110, N_INV, 0x0800030), \
12050 X(vbic, 0x0100110, N_INV, 0x0800030), \
12051 X(veor, 0x1000110, N_INV, N_INV), \
12052 X(vorn, 0x0300110, N_INV, 0x0800010), \
12053 X(vorr, 0x0200110, N_INV, 0x0800010), \
12054 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12055 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12056 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12057 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12058 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12059 X(vst1, 0x0000000, 0x0800000, N_INV), \
12060 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12061 X(vst2, 0x0000100, 0x0800100, N_INV), \
12062 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12063 X(vst3, 0x0000200, 0x0800200, N_INV), \
12064 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12065 X(vst4, 0x0000300, 0x0800300, N_INV), \
12066 X(vmovn, 0x1b20200, N_INV, N_INV), \
12067 X(vtrn, 0x1b20080, N_INV, N_INV), \
12068 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12069 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12070 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12071 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12072 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12073 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12074 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12075 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12076 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12077 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12078 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12082 #define X(OPC,I,F,S) N_MNEM_##OPC
12087 static const struct neon_tab_entry neon_enc_tab[] =
12089 #define X(OPC,I,F,S) { (I), (F), (S) }
12094 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12095 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12096 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12097 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12098 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12099 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12100 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12101 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12102 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12103 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12104 #define NEON_ENC_SINGLE_(X) \
12105 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12106 #define NEON_ENC_DOUBLE_(X) \
12107 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12109 #define NEON_ENCODE(type, inst) \
12112 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12113 inst.is_neon = 1; \
12117 #define check_neon_suffixes \
12120 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12122 as_bad (_("invalid neon suffix for non neon instruction")); \
12128 /* Define shapes for instruction operands. The following mnemonic characters
12129 are used in this table:
12131 F - VFP S<n> register
12132 D - Neon D<n> register
12133 Q - Neon Q<n> register
12137 L - D<n> register list
12139 This table is used to generate various data:
12140 - enumerations of the form NS_DDR to be used as arguments to
12142 - a table classifying shapes into single, double, quad, mixed.
12143 - a table used to drive neon_select_shape. */
12145 #define NEON_SHAPE_DEF \
12146 X(3, (D, D, D), DOUBLE), \
12147 X(3, (Q, Q, Q), QUAD), \
12148 X(3, (D, D, I), DOUBLE), \
12149 X(3, (Q, Q, I), QUAD), \
12150 X(3, (D, D, S), DOUBLE), \
12151 X(3, (Q, Q, S), QUAD), \
12152 X(2, (D, D), DOUBLE), \
12153 X(2, (Q, Q), QUAD), \
12154 X(2, (D, S), DOUBLE), \
12155 X(2, (Q, S), QUAD), \
12156 X(2, (D, R), DOUBLE), \
12157 X(2, (Q, R), QUAD), \
12158 X(2, (D, I), DOUBLE), \
12159 X(2, (Q, I), QUAD), \
12160 X(3, (D, L, D), DOUBLE), \
12161 X(2, (D, Q), MIXED), \
12162 X(2, (Q, D), MIXED), \
12163 X(3, (D, Q, I), MIXED), \
12164 X(3, (Q, D, I), MIXED), \
12165 X(3, (Q, D, D), MIXED), \
12166 X(3, (D, Q, Q), MIXED), \
12167 X(3, (Q, Q, D), MIXED), \
12168 X(3, (Q, D, S), MIXED), \
12169 X(3, (D, Q, S), MIXED), \
12170 X(4, (D, D, D, I), DOUBLE), \
12171 X(4, (Q, Q, Q, I), QUAD), \
12172 X(2, (F, F), SINGLE), \
12173 X(3, (F, F, F), SINGLE), \
12174 X(2, (F, I), SINGLE), \
12175 X(2, (F, D), MIXED), \
12176 X(2, (D, F), MIXED), \
12177 X(3, (F, F, I), MIXED), \
12178 X(4, (R, R, F, F), SINGLE), \
12179 X(4, (F, F, R, R), SINGLE), \
12180 X(3, (D, R, R), DOUBLE), \
12181 X(3, (R, R, D), DOUBLE), \
12182 X(2, (S, R), SINGLE), \
12183 X(2, (R, S), SINGLE), \
12184 X(2, (F, R), SINGLE), \
12185 X(2, (R, F), SINGLE)
12187 #define S2(A,B) NS_##A##B
12188 #define S3(A,B,C) NS_##A##B##C
12189 #define S4(A,B,C,D) NS_##A##B##C##D
12191 #define X(N, L, C) S##N L
12204 enum neon_shape_class
12212 #define X(N, L, C) SC_##C
12214 static enum neon_shape_class neon_shape_class[] =
12232 /* Register widths of above. */
12233 static unsigned neon_shape_el_size[] =
12244 struct neon_shape_info
12247 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12250 #define S2(A,B) { SE_##A, SE_##B }
12251 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12252 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12254 #define X(N, L, C) { N, S##N L }
12256 static struct neon_shape_info neon_shape_tab[] =
12266 /* Bit masks used in type checking given instructions.
12267 'N_EQK' means the type must be the same as (or based on in some way) the key
12268 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12269 set, various other bits can be set as well in order to modify the meaning of
12270 the type constraint. */
12272 enum neon_type_mask
12295 N_KEY = 0x1000000, /* Key element (main type specifier). */
12296 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12297 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12298 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12299 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12300 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12301 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12302 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12303 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12304 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12306 N_MAX_NONSPECIAL = N_F64
12309 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12311 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12312 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12313 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12314 #define N_SUF_32 (N_SU_32 | N_F32)
12315 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12316 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12318 /* Pass this as the first type argument to neon_check_type to ignore types
12320 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12322 /* Select a "shape" for the current instruction (describing register types or
12323 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12324 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12325 function of operand parsing, so this function doesn't need to be called.
12326 Shapes should be listed in order of decreasing length. */
12328 static enum neon_shape
12329 neon_select_shape (enum neon_shape shape, ...)
12332 enum neon_shape first_shape = shape;
12334 /* Fix missing optional operands. FIXME: we don't know at this point how
12335 many arguments we should have, so this makes the assumption that we have
12336 > 1. This is true of all current Neon opcodes, I think, but may not be
12337 true in the future. */
12338 if (!inst.operands[1].present)
12339 inst.operands[1] = inst.operands[0];
12341 va_start (ap, shape);
12343 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12348 for (j = 0; j < neon_shape_tab[shape].els; j++)
12350 if (!inst.operands[j].present)
12356 switch (neon_shape_tab[shape].el[j])
12359 if (!(inst.operands[j].isreg
12360 && inst.operands[j].isvec
12361 && inst.operands[j].issingle
12362 && !inst.operands[j].isquad))
12367 if (!(inst.operands[j].isreg
12368 && inst.operands[j].isvec
12369 && !inst.operands[j].isquad
12370 && !inst.operands[j].issingle))
12375 if (!(inst.operands[j].isreg
12376 && !inst.operands[j].isvec))
12381 if (!(inst.operands[j].isreg
12382 && inst.operands[j].isvec
12383 && inst.operands[j].isquad
12384 && !inst.operands[j].issingle))
12389 if (!(!inst.operands[j].isreg
12390 && !inst.operands[j].isscalar))
12395 if (!(!inst.operands[j].isreg
12396 && inst.operands[j].isscalar))
12412 if (shape == NS_NULL && first_shape != NS_NULL)
12413 first_error (_("invalid instruction shape"));
12418 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12419 means the Q bit should be set). */
12422 neon_quad (enum neon_shape shape)
12424 return neon_shape_class[shape] == SC_QUAD;
12428 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12431 /* Allow modification to be made to types which are constrained to be
12432 based on the key element, based on bits set alongside N_EQK. */
12433 if ((typebits & N_EQK) != 0)
12435 if ((typebits & N_HLF) != 0)
12437 else if ((typebits & N_DBL) != 0)
12439 if ((typebits & N_SGN) != 0)
12440 *g_type = NT_signed;
12441 else if ((typebits & N_UNS) != 0)
12442 *g_type = NT_unsigned;
12443 else if ((typebits & N_INT) != 0)
12444 *g_type = NT_integer;
12445 else if ((typebits & N_FLT) != 0)
12446 *g_type = NT_float;
12447 else if ((typebits & N_SIZ) != 0)
12448 *g_type = NT_untyped;
12452 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12453 operand type, i.e. the single type specified in a Neon instruction when it
12454 is the only one given. */
12456 static struct neon_type_el
12457 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12459 struct neon_type_el dest = *key;
12461 gas_assert ((thisarg & N_EQK) != 0);
12463 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12468 /* Convert Neon type and size into compact bitmask representation. */
12470 static enum neon_type_mask
12471 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12478 case 8: return N_8;
12479 case 16: return N_16;
12480 case 32: return N_32;
12481 case 64: return N_64;
12489 case 8: return N_I8;
12490 case 16: return N_I16;
12491 case 32: return N_I32;
12492 case 64: return N_I64;
12500 case 16: return N_F16;
12501 case 32: return N_F32;
12502 case 64: return N_F64;
12510 case 8: return N_P8;
12511 case 16: return N_P16;
12519 case 8: return N_S8;
12520 case 16: return N_S16;
12521 case 32: return N_S32;
12522 case 64: return N_S64;
12530 case 8: return N_U8;
12531 case 16: return N_U16;
12532 case 32: return N_U32;
12533 case 64: return N_U64;
12544 /* Convert compact Neon bitmask type representation to a type and size. Only
12545 handles the case where a single bit is set in the mask. */
12548 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12549 enum neon_type_mask mask)
12551 if ((mask & N_EQK) != 0)
12554 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12556 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12558 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12560 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12565 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12567 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12568 *type = NT_unsigned;
12569 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12570 *type = NT_integer;
12571 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12572 *type = NT_untyped;
12573 else if ((mask & (N_P8 | N_P16)) != 0)
12575 else if ((mask & (N_F32 | N_F64)) != 0)
12583 /* Modify a bitmask of allowed types. This is only needed for type
12587 modify_types_allowed (unsigned allowed, unsigned mods)
12590 enum neon_el_type type;
12596 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12598 if (el_type_of_type_chk (&type, &size,
12599 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12601 neon_modify_type_size (mods, &type, &size);
12602 destmask |= type_chk_of_el_type (type, size);
12609 /* Check type and return type classification.
12610 The manual states (paraphrase): If one datatype is given, it indicates the
12612 - the second operand, if there is one
12613 - the operand, if there is no second operand
12614 - the result, if there are no operands.
12615 This isn't quite good enough though, so we use a concept of a "key" datatype
12616 which is set on a per-instruction basis, which is the one which matters when
12617 only one data type is written.
12618 Note: this function has side-effects (e.g. filling in missing operands). All
12619 Neon instructions should call it before performing bit encoding. */
12621 static struct neon_type_el
12622 neon_check_type (unsigned els, enum neon_shape ns, ...)
12625 unsigned i, pass, key_el = 0;
12626 unsigned types[NEON_MAX_TYPE_ELS];
12627 enum neon_el_type k_type = NT_invtype;
12628 unsigned k_size = -1u;
12629 struct neon_type_el badtype = {NT_invtype, -1};
12630 unsigned key_allowed = 0;
12632 /* Optional registers in Neon instructions are always (not) in operand 1.
12633 Fill in the missing operand here, if it was omitted. */
12634 if (els > 1 && !inst.operands[1].present)
12635 inst.operands[1] = inst.operands[0];
12637 /* Suck up all the varargs. */
12639 for (i = 0; i < els; i++)
12641 unsigned thisarg = va_arg (ap, unsigned);
12642 if (thisarg == N_IGNORE_TYPE)
12647 types[i] = thisarg;
12648 if ((thisarg & N_KEY) != 0)
12653 if (inst.vectype.elems > 0)
12654 for (i = 0; i < els; i++)
12655 if (inst.operands[i].vectype.type != NT_invtype)
12657 first_error (_("types specified in both the mnemonic and operands"));
12661 /* Duplicate inst.vectype elements here as necessary.
12662 FIXME: No idea if this is exactly the same as the ARM assembler,
12663 particularly when an insn takes one register and one non-register
12665 if (inst.vectype.elems == 1 && els > 1)
12668 inst.vectype.elems = els;
12669 inst.vectype.el[key_el] = inst.vectype.el[0];
12670 for (j = 0; j < els; j++)
12672 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12675 else if (inst.vectype.elems == 0 && els > 0)
12678 /* No types were given after the mnemonic, so look for types specified
12679 after each operand. We allow some flexibility here; as long as the
12680 "key" operand has a type, we can infer the others. */
12681 for (j = 0; j < els; j++)
12682 if (inst.operands[j].vectype.type != NT_invtype)
12683 inst.vectype.el[j] = inst.operands[j].vectype;
12685 if (inst.operands[key_el].vectype.type != NT_invtype)
12687 for (j = 0; j < els; j++)
12688 if (inst.operands[j].vectype.type == NT_invtype)
12689 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12694 first_error (_("operand types can't be inferred"));
12698 else if (inst.vectype.elems != els)
12700 first_error (_("type specifier has the wrong number of parts"));
12704 for (pass = 0; pass < 2; pass++)
12706 for (i = 0; i < els; i++)
12708 unsigned thisarg = types[i];
12709 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12710 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12711 enum neon_el_type g_type = inst.vectype.el[i].type;
12712 unsigned g_size = inst.vectype.el[i].size;
12714 /* Decay more-specific signed & unsigned types to sign-insensitive
12715 integer types if sign-specific variants are unavailable. */
12716 if ((g_type == NT_signed || g_type == NT_unsigned)
12717 && (types_allowed & N_SU_ALL) == 0)
12718 g_type = NT_integer;
12720 /* If only untyped args are allowed, decay any more specific types to
12721 them. Some instructions only care about signs for some element
12722 sizes, so handle that properly. */
12723 if ((g_size == 8 && (types_allowed & N_8) != 0)
12724 || (g_size == 16 && (types_allowed & N_16) != 0)
12725 || (g_size == 32 && (types_allowed & N_32) != 0)
12726 || (g_size == 64 && (types_allowed & N_64) != 0))
12727 g_type = NT_untyped;
12731 if ((thisarg & N_KEY) != 0)
12735 key_allowed = thisarg & ~N_KEY;
12740 if ((thisarg & N_VFP) != 0)
12742 enum neon_shape_el regshape;
12743 unsigned regwidth, match;
12745 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12748 first_error (_("invalid instruction shape"));
12751 regshape = neon_shape_tab[ns].el[i];
12752 regwidth = neon_shape_el_size[regshape];
12754 /* In VFP mode, operands must match register widths. If we
12755 have a key operand, use its width, else use the width of
12756 the current operand. */
12762 if (regwidth != match)
12764 first_error (_("operand size must match register width"));
12769 if ((thisarg & N_EQK) == 0)
12771 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12773 if ((given_type & types_allowed) == 0)
12775 first_error (_("bad type in Neon instruction"));
12781 enum neon_el_type mod_k_type = k_type;
12782 unsigned mod_k_size = k_size;
12783 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12784 if (g_type != mod_k_type || g_size != mod_k_size)
12786 first_error (_("inconsistent types in Neon instruction"));
12794 return inst.vectype.el[key_el];
12797 /* Neon-style VFP instruction forwarding. */
12799 /* Thumb VFP instructions have 0xE in the condition field. */
12802 do_vfp_cond_or_thumb (void)
12807 inst.instruction |= 0xe0000000;
12809 inst.instruction |= inst.cond << 28;
12812 /* Look up and encode a simple mnemonic, for use as a helper function for the
12813 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12814 etc. It is assumed that operand parsing has already been done, and that the
12815 operands are in the form expected by the given opcode (this isn't necessarily
12816 the same as the form in which they were parsed, hence some massaging must
12817 take place before this function is called).
12818 Checks current arch version against that in the looked-up opcode. */
12821 do_vfp_nsyn_opcode (const char *opname)
12823 const struct asm_opcode *opcode;
12825 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12831 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12838 inst.instruction = opcode->tvalue;
12839 opcode->tencode ();
12843 inst.instruction = (inst.cond << 28) | opcode->avalue;
12844 opcode->aencode ();
12849 do_vfp_nsyn_add_sub (enum neon_shape rs)
12851 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12856 do_vfp_nsyn_opcode ("fadds");
12858 do_vfp_nsyn_opcode ("fsubs");
12863 do_vfp_nsyn_opcode ("faddd");
12865 do_vfp_nsyn_opcode ("fsubd");
12869 /* Check operand types to see if this is a VFP instruction, and if so call
12873 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12875 enum neon_shape rs;
12876 struct neon_type_el et;
12881 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12882 et = neon_check_type (2, rs,
12883 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12887 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12888 et = neon_check_type (3, rs,
12889 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12896 if (et.type != NT_invtype)
12907 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12909 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12914 do_vfp_nsyn_opcode ("fmacs");
12916 do_vfp_nsyn_opcode ("fnmacs");
12921 do_vfp_nsyn_opcode ("fmacd");
12923 do_vfp_nsyn_opcode ("fnmacd");
12928 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12930 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12935 do_vfp_nsyn_opcode ("ffmas");
12937 do_vfp_nsyn_opcode ("ffnmas");
12942 do_vfp_nsyn_opcode ("ffmad");
12944 do_vfp_nsyn_opcode ("ffnmad");
12949 do_vfp_nsyn_mul (enum neon_shape rs)
12952 do_vfp_nsyn_opcode ("fmuls");
12954 do_vfp_nsyn_opcode ("fmuld");
12958 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12960 int is_neg = (inst.instruction & 0x80) != 0;
12961 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12966 do_vfp_nsyn_opcode ("fnegs");
12968 do_vfp_nsyn_opcode ("fabss");
12973 do_vfp_nsyn_opcode ("fnegd");
12975 do_vfp_nsyn_opcode ("fabsd");
12979 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12980 insns belong to Neon, and are handled elsewhere. */
12983 do_vfp_nsyn_ldm_stm (int is_dbmode)
12985 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12989 do_vfp_nsyn_opcode ("fldmdbs");
12991 do_vfp_nsyn_opcode ("fldmias");
12996 do_vfp_nsyn_opcode ("fstmdbs");
12998 do_vfp_nsyn_opcode ("fstmias");
13003 do_vfp_nsyn_sqrt (void)
13005 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13006 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13009 do_vfp_nsyn_opcode ("fsqrts");
13011 do_vfp_nsyn_opcode ("fsqrtd");
13015 do_vfp_nsyn_div (void)
13017 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13018 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13019 N_F32 | N_F64 | N_KEY | N_VFP);
13022 do_vfp_nsyn_opcode ("fdivs");
13024 do_vfp_nsyn_opcode ("fdivd");
13028 do_vfp_nsyn_nmul (void)
13030 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13031 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13032 N_F32 | N_F64 | N_KEY | N_VFP);
13036 NEON_ENCODE (SINGLE, inst);
13037 do_vfp_sp_dyadic ();
13041 NEON_ENCODE (DOUBLE, inst);
13042 do_vfp_dp_rd_rn_rm ();
13044 do_vfp_cond_or_thumb ();
13048 do_vfp_nsyn_cmp (void)
13050 if (inst.operands[1].isreg)
13052 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13053 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13057 NEON_ENCODE (SINGLE, inst);
13058 do_vfp_sp_monadic ();
13062 NEON_ENCODE (DOUBLE, inst);
13063 do_vfp_dp_rd_rm ();
13068 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13069 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13071 switch (inst.instruction & 0x0fffffff)
13074 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13077 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13085 NEON_ENCODE (SINGLE, inst);
13086 do_vfp_sp_compare_z ();
13090 NEON_ENCODE (DOUBLE, inst);
13094 do_vfp_cond_or_thumb ();
13098 nsyn_insert_sp (void)
13100 inst.operands[1] = inst.operands[0];
13101 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13102 inst.operands[0].reg = REG_SP;
13103 inst.operands[0].isreg = 1;
13104 inst.operands[0].writeback = 1;
13105 inst.operands[0].present = 1;
13109 do_vfp_nsyn_push (void)
13112 if (inst.operands[1].issingle)
13113 do_vfp_nsyn_opcode ("fstmdbs");
13115 do_vfp_nsyn_opcode ("fstmdbd");
13119 do_vfp_nsyn_pop (void)
13122 if (inst.operands[1].issingle)
13123 do_vfp_nsyn_opcode ("fldmias");
13125 do_vfp_nsyn_opcode ("fldmiad");
13128 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13129 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13132 neon_dp_fixup (struct arm_it* insn)
13134 unsigned int i = insn->instruction;
13139 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13150 insn->instruction = i;
13153 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13157 neon_logbits (unsigned x)
13159 return ffs (x) - 4;
13162 #define LOW4(R) ((R) & 0xf)
13163 #define HI1(R) (((R) >> 4) & 1)
13165 /* Encode insns with bit pattern:
13167 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13168 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13170 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13171 different meaning for some instruction. */
13174 neon_three_same (int isquad, int ubit, int size)
13176 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13177 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13178 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13179 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13180 inst.instruction |= LOW4 (inst.operands[2].reg);
13181 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13182 inst.instruction |= (isquad != 0) << 6;
13183 inst.instruction |= (ubit != 0) << 24;
13185 inst.instruction |= neon_logbits (size) << 20;
13187 neon_dp_fixup (&inst);
13190 /* Encode instructions of the form:
13192 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13193 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13195 Don't write size if SIZE == -1. */
13198 neon_two_same (int qbit, int ubit, int size)
13200 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13201 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13202 inst.instruction |= LOW4 (inst.operands[1].reg);
13203 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13204 inst.instruction |= (qbit != 0) << 6;
13205 inst.instruction |= (ubit != 0) << 24;
13208 inst.instruction |= neon_logbits (size) << 18;
13210 neon_dp_fixup (&inst);
13213 /* Neon instruction encoders, in approximate order of appearance. */
13216 do_neon_dyadic_i_su (void)
13218 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13219 struct neon_type_el et = neon_check_type (3, rs,
13220 N_EQK, N_EQK, N_SU_32 | N_KEY);
13221 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13225 do_neon_dyadic_i64_su (void)
13227 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13228 struct neon_type_el et = neon_check_type (3, rs,
13229 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13230 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13234 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13237 unsigned size = et.size >> 3;
13238 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13239 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13240 inst.instruction |= LOW4 (inst.operands[1].reg);
13241 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13242 inst.instruction |= (isquad != 0) << 6;
13243 inst.instruction |= immbits << 16;
13244 inst.instruction |= (size >> 3) << 7;
13245 inst.instruction |= (size & 0x7) << 19;
13247 inst.instruction |= (uval != 0) << 24;
13249 neon_dp_fixup (&inst);
13253 do_neon_shl_imm (void)
13255 if (!inst.operands[2].isreg)
13257 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13258 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13259 NEON_ENCODE (IMMED, inst);
13260 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13264 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13265 struct neon_type_el et = neon_check_type (3, rs,
13266 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13269 /* VSHL/VQSHL 3-register variants have syntax such as:
13271 whereas other 3-register operations encoded by neon_three_same have
13274 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13276 tmp = inst.operands[2].reg;
13277 inst.operands[2].reg = inst.operands[1].reg;
13278 inst.operands[1].reg = tmp;
13279 NEON_ENCODE (INTEGER, inst);
13280 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13285 do_neon_qshl_imm (void)
13287 if (!inst.operands[2].isreg)
13289 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13290 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13292 NEON_ENCODE (IMMED, inst);
13293 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13294 inst.operands[2].imm);
13298 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13299 struct neon_type_el et = neon_check_type (3, rs,
13300 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13303 /* See note in do_neon_shl_imm. */
13304 tmp = inst.operands[2].reg;
13305 inst.operands[2].reg = inst.operands[1].reg;
13306 inst.operands[1].reg = tmp;
13307 NEON_ENCODE (INTEGER, inst);
13308 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13313 do_neon_rshl (void)
13315 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13316 struct neon_type_el et = neon_check_type (3, rs,
13317 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13320 tmp = inst.operands[2].reg;
13321 inst.operands[2].reg = inst.operands[1].reg;
13322 inst.operands[1].reg = tmp;
13323 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13327 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13329 /* Handle .I8 pseudo-instructions. */
13332 /* Unfortunately, this will make everything apart from zero out-of-range.
13333 FIXME is this the intended semantics? There doesn't seem much point in
13334 accepting .I8 if so. */
13335 immediate |= immediate << 8;
13341 if (immediate == (immediate & 0x000000ff))
13343 *immbits = immediate;
13346 else if (immediate == (immediate & 0x0000ff00))
13348 *immbits = immediate >> 8;
13351 else if (immediate == (immediate & 0x00ff0000))
13353 *immbits = immediate >> 16;
13356 else if (immediate == (immediate & 0xff000000))
13358 *immbits = immediate >> 24;
13361 if ((immediate & 0xffff) != (immediate >> 16))
13362 goto bad_immediate;
13363 immediate &= 0xffff;
13366 if (immediate == (immediate & 0x000000ff))
13368 *immbits = immediate;
13371 else if (immediate == (immediate & 0x0000ff00))
13373 *immbits = immediate >> 8;
13378 first_error (_("immediate value out of range"));
13382 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13386 neon_bits_same_in_bytes (unsigned imm)
13388 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13389 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13390 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13391 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13394 /* For immediate of above form, return 0bABCD. */
13397 neon_squash_bits (unsigned imm)
13399 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13400 | ((imm & 0x01000000) >> 21);
13403 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13406 neon_qfloat_bits (unsigned imm)
13408 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13411 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13412 the instruction. *OP is passed as the initial value of the op field, and
13413 may be set to a different value depending on the constant (i.e.
13414 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13415 MVN). If the immediate looks like a repeated pattern then also
13416 try smaller element sizes. */
13419 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13420 unsigned *immbits, int *op, int size,
13421 enum neon_el_type type)
13423 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13425 if (type == NT_float && !float_p)
13428 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13430 if (size != 32 || *op == 1)
13432 *immbits = neon_qfloat_bits (immlo);
13438 if (neon_bits_same_in_bytes (immhi)
13439 && neon_bits_same_in_bytes (immlo))
13443 *immbits = (neon_squash_bits (immhi) << 4)
13444 | neon_squash_bits (immlo);
13449 if (immhi != immlo)
13455 if (immlo == (immlo & 0x000000ff))
13460 else if (immlo == (immlo & 0x0000ff00))
13462 *immbits = immlo >> 8;
13465 else if (immlo == (immlo & 0x00ff0000))
13467 *immbits = immlo >> 16;
13470 else if (immlo == (immlo & 0xff000000))
13472 *immbits = immlo >> 24;
13475 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13477 *immbits = (immlo >> 8) & 0xff;
13480 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13482 *immbits = (immlo >> 16) & 0xff;
13486 if ((immlo & 0xffff) != (immlo >> 16))
13493 if (immlo == (immlo & 0x000000ff))
13498 else if (immlo == (immlo & 0x0000ff00))
13500 *immbits = immlo >> 8;
13504 if ((immlo & 0xff) != (immlo >> 8))
13509 if (immlo == (immlo & 0x000000ff))
13511 /* Don't allow MVN with 8-bit immediate. */
13521 /* Write immediate bits [7:0] to the following locations:
13523 |28/24|23 19|18 16|15 4|3 0|
13524 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13526 This function is used by VMOV/VMVN/VORR/VBIC. */
13529 neon_write_immbits (unsigned immbits)
13531 inst.instruction |= immbits & 0xf;
13532 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13533 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13536 /* Invert low-order SIZE bits of XHI:XLO. */
13539 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13541 unsigned immlo = xlo ? *xlo : 0;
13542 unsigned immhi = xhi ? *xhi : 0;
13547 immlo = (~immlo) & 0xff;
13551 immlo = (~immlo) & 0xffff;
13555 immhi = (~immhi) & 0xffffffff;
13556 /* fall through. */
13559 immlo = (~immlo) & 0xffffffff;
13574 do_neon_logic (void)
13576 if (inst.operands[2].present && inst.operands[2].isreg)
13578 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13579 neon_check_type (3, rs, N_IGNORE_TYPE);
13580 /* U bit and size field were set as part of the bitmask. */
13581 NEON_ENCODE (INTEGER, inst);
13582 neon_three_same (neon_quad (rs), 0, -1);
13586 const int three_ops_form = (inst.operands[2].present
13587 && !inst.operands[2].isreg);
13588 const int immoperand = (three_ops_form ? 2 : 1);
13589 enum neon_shape rs = (three_ops_form
13590 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13591 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13592 struct neon_type_el et = neon_check_type (2, rs,
13593 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13594 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13598 if (et.type == NT_invtype)
13601 if (three_ops_form)
13602 constraint (inst.operands[0].reg != inst.operands[1].reg,
13603 _("first and second operands shall be the same register"));
13605 NEON_ENCODE (IMMED, inst);
13607 immbits = inst.operands[immoperand].imm;
13610 /* .i64 is a pseudo-op, so the immediate must be a repeating
13612 if (immbits != (inst.operands[immoperand].regisimm ?
13613 inst.operands[immoperand].reg : 0))
13615 /* Set immbits to an invalid constant. */
13616 immbits = 0xdeadbeef;
13623 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13627 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13631 /* Pseudo-instruction for VBIC. */
13632 neon_invert_size (&immbits, 0, et.size);
13633 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13637 /* Pseudo-instruction for VORR. */
13638 neon_invert_size (&immbits, 0, et.size);
13639 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13649 inst.instruction |= neon_quad (rs) << 6;
13650 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13651 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13652 inst.instruction |= cmode << 8;
13653 neon_write_immbits (immbits);
13655 neon_dp_fixup (&inst);
13660 do_neon_bitfield (void)
13662 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13663 neon_check_type (3, rs, N_IGNORE_TYPE);
13664 neon_three_same (neon_quad (rs), 0, -1);
13668 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13671 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13672 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13674 if (et.type == NT_float)
13676 NEON_ENCODE (FLOAT, inst);
13677 neon_three_same (neon_quad (rs), 0, -1);
13681 NEON_ENCODE (INTEGER, inst);
13682 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13687 do_neon_dyadic_if_su (void)
13689 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13693 do_neon_dyadic_if_su_d (void)
13695 /* This version only allow D registers, but that constraint is enforced during
13696 operand parsing so we don't need to do anything extra here. */
13697 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13701 do_neon_dyadic_if_i_d (void)
13703 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13704 affected if we specify unsigned args. */
13705 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13708 enum vfp_or_neon_is_neon_bits
13711 NEON_CHECK_ARCH = 2
13714 /* Call this function if an instruction which may have belonged to the VFP or
13715 Neon instruction sets, but turned out to be a Neon instruction (due to the
13716 operand types involved, etc.). We have to check and/or fix-up a couple of
13719 - Make sure the user hasn't attempted to make a Neon instruction
13721 - Alter the value in the condition code field if necessary.
13722 - Make sure that the arch supports Neon instructions.
13724 Which of these operations take place depends on bits from enum
13725 vfp_or_neon_is_neon_bits.
13727 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13728 current instruction's condition is COND_ALWAYS, the condition field is
13729 changed to inst.uncond_value. This is necessary because instructions shared
13730 between VFP and Neon may be conditional for the VFP variants only, and the
13731 unconditional Neon version must have, e.g., 0xF in the condition field. */
13734 vfp_or_neon_is_neon (unsigned check)
13736 /* Conditions are always legal in Thumb mode (IT blocks). */
13737 if (!thumb_mode && (check & NEON_CHECK_CC))
13739 if (inst.cond != COND_ALWAYS)
13741 first_error (_(BAD_COND));
13744 if (inst.uncond_value != -1)
13745 inst.instruction |= inst.uncond_value << 28;
13748 if ((check & NEON_CHECK_ARCH)
13749 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13751 first_error (_(BAD_FPU));
13759 do_neon_addsub_if_i (void)
13761 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13764 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13767 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13768 affected if we specify unsigned args. */
13769 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13772 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13774 V<op> A,B (A is operand 0, B is operand 2)
13779 so handle that case specially. */
13782 neon_exchange_operands (void)
13784 void *scratch = alloca (sizeof (inst.operands[0]));
13785 if (inst.operands[1].present)
13787 /* Swap operands[1] and operands[2]. */
13788 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13789 inst.operands[1] = inst.operands[2];
13790 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13794 inst.operands[1] = inst.operands[2];
13795 inst.operands[2] = inst.operands[0];
13800 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13802 if (inst.operands[2].isreg)
13805 neon_exchange_operands ();
13806 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13810 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13811 struct neon_type_el et = neon_check_type (2, rs,
13812 N_EQK | N_SIZ, immtypes | N_KEY);
13814 NEON_ENCODE (IMMED, inst);
13815 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13816 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13817 inst.instruction |= LOW4 (inst.operands[1].reg);
13818 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13819 inst.instruction |= neon_quad (rs) << 6;
13820 inst.instruction |= (et.type == NT_float) << 10;
13821 inst.instruction |= neon_logbits (et.size) << 18;
13823 neon_dp_fixup (&inst);
13830 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13834 do_neon_cmp_inv (void)
13836 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13842 neon_compare (N_IF_32, N_IF_32, FALSE);
13845 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13846 scalars, which are encoded in 5 bits, M : Rm.
13847 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13848 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13852 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13854 unsigned regno = NEON_SCALAR_REG (scalar);
13855 unsigned elno = NEON_SCALAR_INDEX (scalar);
13860 if (regno > 7 || elno > 3)
13862 return regno | (elno << 3);
13865 if (regno > 15 || elno > 1)
13867 return regno | (elno << 4);
13871 first_error (_("scalar out of range for multiply instruction"));
13877 /* Encode multiply / multiply-accumulate scalar instructions. */
13880 neon_mul_mac (struct neon_type_el et, int ubit)
13884 /* Give a more helpful error message if we have an invalid type. */
13885 if (et.type == NT_invtype)
13888 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13889 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13890 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13891 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13892 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13893 inst.instruction |= LOW4 (scalar);
13894 inst.instruction |= HI1 (scalar) << 5;
13895 inst.instruction |= (et.type == NT_float) << 8;
13896 inst.instruction |= neon_logbits (et.size) << 20;
13897 inst.instruction |= (ubit != 0) << 24;
13899 neon_dp_fixup (&inst);
13903 do_neon_mac_maybe_scalar (void)
13905 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13908 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13911 if (inst.operands[2].isscalar)
13913 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13914 struct neon_type_el et = neon_check_type (3, rs,
13915 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13916 NEON_ENCODE (SCALAR, inst);
13917 neon_mul_mac (et, neon_quad (rs));
13921 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13922 affected if we specify unsigned args. */
13923 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13928 do_neon_fmac (void)
13930 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13933 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13936 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13942 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13943 struct neon_type_el et = neon_check_type (3, rs,
13944 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13945 neon_three_same (neon_quad (rs), 0, et.size);
13948 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13949 same types as the MAC equivalents. The polynomial type for this instruction
13950 is encoded the same as the integer type. */
13955 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13958 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13961 if (inst.operands[2].isscalar)
13962 do_neon_mac_maybe_scalar ();
13964 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13968 do_neon_qdmulh (void)
13970 if (inst.operands[2].isscalar)
13972 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13973 struct neon_type_el et = neon_check_type (3, rs,
13974 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13975 NEON_ENCODE (SCALAR, inst);
13976 neon_mul_mac (et, neon_quad (rs));
13980 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13981 struct neon_type_el et = neon_check_type (3, rs,
13982 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13983 NEON_ENCODE (INTEGER, inst);
13984 /* The U bit (rounding) comes from bit mask. */
13985 neon_three_same (neon_quad (rs), 0, et.size);
13990 do_neon_fcmp_absolute (void)
13992 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13993 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13994 /* Size field comes from bit mask. */
13995 neon_three_same (neon_quad (rs), 1, -1);
13999 do_neon_fcmp_absolute_inv (void)
14001 neon_exchange_operands ();
14002 do_neon_fcmp_absolute ();
14006 do_neon_step (void)
14008 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14009 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14010 neon_three_same (neon_quad (rs), 0, -1);
14014 do_neon_abs_neg (void)
14016 enum neon_shape rs;
14017 struct neon_type_el et;
14019 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14022 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14025 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14026 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14028 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14029 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14030 inst.instruction |= LOW4 (inst.operands[1].reg);
14031 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14032 inst.instruction |= neon_quad (rs) << 6;
14033 inst.instruction |= (et.type == NT_float) << 10;
14034 inst.instruction |= neon_logbits (et.size) << 18;
14036 neon_dp_fixup (&inst);
14042 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14043 struct neon_type_el et = neon_check_type (2, rs,
14044 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14045 int imm = inst.operands[2].imm;
14046 constraint (imm < 0 || (unsigned)imm >= et.size,
14047 _("immediate out of range for insert"));
14048 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14054 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14055 struct neon_type_el et = neon_check_type (2, rs,
14056 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14057 int imm = inst.operands[2].imm;
14058 constraint (imm < 1 || (unsigned)imm > et.size,
14059 _("immediate out of range for insert"));
14060 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14064 do_neon_qshlu_imm (void)
14066 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14067 struct neon_type_el et = neon_check_type (2, rs,
14068 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14069 int imm = inst.operands[2].imm;
14070 constraint (imm < 0 || (unsigned)imm >= et.size,
14071 _("immediate out of range for shift"));
14072 /* Only encodes the 'U present' variant of the instruction.
14073 In this case, signed types have OP (bit 8) set to 0.
14074 Unsigned types have OP set to 1. */
14075 inst.instruction |= (et.type == NT_unsigned) << 8;
14076 /* The rest of the bits are the same as other immediate shifts. */
14077 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14081 do_neon_qmovn (void)
14083 struct neon_type_el et = neon_check_type (2, NS_DQ,
14084 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14085 /* Saturating move where operands can be signed or unsigned, and the
14086 destination has the same signedness. */
14087 NEON_ENCODE (INTEGER, inst);
14088 if (et.type == NT_unsigned)
14089 inst.instruction |= 0xc0;
14091 inst.instruction |= 0x80;
14092 neon_two_same (0, 1, et.size / 2);
14096 do_neon_qmovun (void)
14098 struct neon_type_el et = neon_check_type (2, NS_DQ,
14099 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14100 /* Saturating move with unsigned results. Operands must be signed. */
14101 NEON_ENCODE (INTEGER, inst);
14102 neon_two_same (0, 1, et.size / 2);
14106 do_neon_rshift_sat_narrow (void)
14108 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14109 or unsigned. If operands are unsigned, results must also be unsigned. */
14110 struct neon_type_el et = neon_check_type (2, NS_DQI,
14111 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14112 int imm = inst.operands[2].imm;
14113 /* This gets the bounds check, size encoding and immediate bits calculation
14117 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14118 VQMOVN.I<size> <Dd>, <Qm>. */
14121 inst.operands[2].present = 0;
14122 inst.instruction = N_MNEM_vqmovn;
14127 constraint (imm < 1 || (unsigned)imm > et.size,
14128 _("immediate out of range"));
14129 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14133 do_neon_rshift_sat_narrow_u (void)
14135 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14136 or unsigned. If operands are unsigned, results must also be unsigned. */
14137 struct neon_type_el et = neon_check_type (2, NS_DQI,
14138 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14139 int imm = inst.operands[2].imm;
14140 /* This gets the bounds check, size encoding and immediate bits calculation
14144 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14145 VQMOVUN.I<size> <Dd>, <Qm>. */
14148 inst.operands[2].present = 0;
14149 inst.instruction = N_MNEM_vqmovun;
14154 constraint (imm < 1 || (unsigned)imm > et.size,
14155 _("immediate out of range"));
14156 /* FIXME: The manual is kind of unclear about what value U should have in
14157 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14159 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14163 do_neon_movn (void)
14165 struct neon_type_el et = neon_check_type (2, NS_DQ,
14166 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14167 NEON_ENCODE (INTEGER, inst);
14168 neon_two_same (0, 1, et.size / 2);
14172 do_neon_rshift_narrow (void)
14174 struct neon_type_el et = neon_check_type (2, NS_DQI,
14175 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14176 int imm = inst.operands[2].imm;
14177 /* This gets the bounds check, size encoding and immediate bits calculation
14181 /* If immediate is zero then we are a pseudo-instruction for
14182 VMOVN.I<size> <Dd>, <Qm> */
14185 inst.operands[2].present = 0;
14186 inst.instruction = N_MNEM_vmovn;
14191 constraint (imm < 1 || (unsigned)imm > et.size,
14192 _("immediate out of range for narrowing operation"));
14193 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14197 do_neon_shll (void)
14199 /* FIXME: Type checking when lengthening. */
14200 struct neon_type_el et = neon_check_type (2, NS_QDI,
14201 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14202 unsigned imm = inst.operands[2].imm;
14204 if (imm == et.size)
14206 /* Maximum shift variant. */
14207 NEON_ENCODE (INTEGER, inst);
14208 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14209 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14210 inst.instruction |= LOW4 (inst.operands[1].reg);
14211 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14212 inst.instruction |= neon_logbits (et.size) << 18;
14214 neon_dp_fixup (&inst);
14218 /* A more-specific type check for non-max versions. */
14219 et = neon_check_type (2, NS_QDI,
14220 N_EQK | N_DBL, N_SU_32 | N_KEY);
14221 NEON_ENCODE (IMMED, inst);
14222 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14226 /* Check the various types for the VCVT instruction, and return which version
14227 the current instruction is. */
14230 neon_cvt_flavour (enum neon_shape rs)
14232 #define CVT_VAR(C,X,Y) \
14233 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14234 if (et.type != NT_invtype) \
14236 inst.error = NULL; \
14239 struct neon_type_el et;
14240 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14241 || rs == NS_FF) ? N_VFP : 0;
14242 /* The instruction versions which take an immediate take one register
14243 argument, which is extended to the width of the full register. Thus the
14244 "source" and "destination" registers must have the same width. Hack that
14245 here by making the size equal to the key (wider, in this case) operand. */
14246 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14248 CVT_VAR (0, N_S32, N_F32);
14249 CVT_VAR (1, N_U32, N_F32);
14250 CVT_VAR (2, N_F32, N_S32);
14251 CVT_VAR (3, N_F32, N_U32);
14252 /* Half-precision conversions. */
14253 CVT_VAR (4, N_F32, N_F16);
14254 CVT_VAR (5, N_F16, N_F32);
14258 /* VFP instructions. */
14259 CVT_VAR (6, N_F32, N_F64);
14260 CVT_VAR (7, N_F64, N_F32);
14261 CVT_VAR (8, N_S32, N_F64 | key);
14262 CVT_VAR (9, N_U32, N_F64 | key);
14263 CVT_VAR (10, N_F64 | key, N_S32);
14264 CVT_VAR (11, N_F64 | key, N_U32);
14265 /* VFP instructions with bitshift. */
14266 CVT_VAR (12, N_F32 | key, N_S16);
14267 CVT_VAR (13, N_F32 | key, N_U16);
14268 CVT_VAR (14, N_F64 | key, N_S16);
14269 CVT_VAR (15, N_F64 | key, N_U16);
14270 CVT_VAR (16, N_S16, N_F32 | key);
14271 CVT_VAR (17, N_U16, N_F32 | key);
14272 CVT_VAR (18, N_S16, N_F64 | key);
14273 CVT_VAR (19, N_U16, N_F64 | key);
14279 /* Neon-syntax VFP conversions. */
14282 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14284 const char *opname = 0;
14286 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14288 /* Conversions with immediate bitshift. */
14289 const char *enc[] =
14313 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14315 opname = enc[flavour];
14316 constraint (inst.operands[0].reg != inst.operands[1].reg,
14317 _("operands 0 and 1 must be the same register"));
14318 inst.operands[1] = inst.operands[2];
14319 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14324 /* Conversions without bitshift. */
14325 const char *enc[] =
14341 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14342 opname = enc[flavour];
14346 do_vfp_nsyn_opcode (opname);
14350 do_vfp_nsyn_cvtz (void)
14352 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14353 int flavour = neon_cvt_flavour (rs);
14354 const char *enc[] =
14368 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14369 do_vfp_nsyn_opcode (enc[flavour]);
14373 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14375 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14376 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14377 int flavour = neon_cvt_flavour (rs);
14379 /* PR11109: Handle round-to-zero for VCVT conversions. */
14381 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14382 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14383 && (rs == NS_FD || rs == NS_FF))
14385 do_vfp_nsyn_cvtz ();
14389 /* VFP rather than Neon conversions. */
14392 do_vfp_nsyn_cvt (rs, flavour);
14402 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14404 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14407 /* Fixed-point conversion with #0 immediate is encoded as an
14408 integer conversion. */
14409 if (inst.operands[2].present && inst.operands[2].imm == 0)
14411 immbits = 32 - inst.operands[2].imm;
14412 NEON_ENCODE (IMMED, inst);
14414 inst.instruction |= enctab[flavour];
14415 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14416 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14417 inst.instruction |= LOW4 (inst.operands[1].reg);
14418 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14419 inst.instruction |= neon_quad (rs) << 6;
14420 inst.instruction |= 1 << 21;
14421 inst.instruction |= immbits << 16;
14423 neon_dp_fixup (&inst);
14431 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14433 NEON_ENCODE (INTEGER, inst);
14435 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14439 inst.instruction |= enctab[flavour];
14441 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14442 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14443 inst.instruction |= LOW4 (inst.operands[1].reg);
14444 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14445 inst.instruction |= neon_quad (rs) << 6;
14446 inst.instruction |= 2 << 18;
14448 neon_dp_fixup (&inst);
14452 /* Half-precision conversions for Advanced SIMD -- neon. */
14457 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14459 as_bad (_("operand size must match register width"));
14464 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14466 as_bad (_("operand size must match register width"));
14471 inst.instruction = 0x3b60600;
14473 inst.instruction = 0x3b60700;
14475 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14476 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14477 inst.instruction |= LOW4 (inst.operands[1].reg);
14478 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14479 neon_dp_fixup (&inst);
14483 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14484 do_vfp_nsyn_cvt (rs, flavour);
14489 do_neon_cvtr (void)
14491 do_neon_cvt_1 (FALSE);
14497 do_neon_cvt_1 (TRUE);
14501 do_neon_cvtb (void)
14503 inst.instruction = 0xeb20a40;
14505 /* The sizes are attached to the mnemonic. */
14506 if (inst.vectype.el[0].type != NT_invtype
14507 && inst.vectype.el[0].size == 16)
14508 inst.instruction |= 0x00010000;
14510 /* Programmer's syntax: the sizes are attached to the operands. */
14511 else if (inst.operands[0].vectype.type != NT_invtype
14512 && inst.operands[0].vectype.size == 16)
14513 inst.instruction |= 0x00010000;
14515 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14516 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14517 do_vfp_cond_or_thumb ();
14522 do_neon_cvtt (void)
14525 inst.instruction |= 0x80;
14529 neon_move_immediate (void)
14531 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14532 struct neon_type_el et = neon_check_type (2, rs,
14533 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14534 unsigned immlo, immhi = 0, immbits;
14535 int op, cmode, float_p;
14537 constraint (et.type == NT_invtype,
14538 _("operand size must be specified for immediate VMOV"));
14540 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14541 op = (inst.instruction & (1 << 5)) != 0;
14543 immlo = inst.operands[1].imm;
14544 if (inst.operands[1].regisimm)
14545 immhi = inst.operands[1].reg;
14547 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14548 _("immediate has bits set outside the operand size"));
14550 float_p = inst.operands[1].immisfloat;
14552 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14553 et.size, et.type)) == FAIL)
14555 /* Invert relevant bits only. */
14556 neon_invert_size (&immlo, &immhi, et.size);
14557 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14558 with one or the other; those cases are caught by
14559 neon_cmode_for_move_imm. */
14561 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14562 &op, et.size, et.type)) == FAIL)
14564 first_error (_("immediate out of range"));
14569 inst.instruction &= ~(1 << 5);
14570 inst.instruction |= op << 5;
14572 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14573 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14574 inst.instruction |= neon_quad (rs) << 6;
14575 inst.instruction |= cmode << 8;
14577 neon_write_immbits (immbits);
14583 if (inst.operands[1].isreg)
14585 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14587 NEON_ENCODE (INTEGER, inst);
14588 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14589 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14590 inst.instruction |= LOW4 (inst.operands[1].reg);
14591 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14592 inst.instruction |= neon_quad (rs) << 6;
14596 NEON_ENCODE (IMMED, inst);
14597 neon_move_immediate ();
14600 neon_dp_fixup (&inst);
14603 /* Encode instructions of form:
14605 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14606 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14609 neon_mixed_length (struct neon_type_el et, unsigned size)
14611 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14612 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14613 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14614 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14615 inst.instruction |= LOW4 (inst.operands[2].reg);
14616 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14617 inst.instruction |= (et.type == NT_unsigned) << 24;
14618 inst.instruction |= neon_logbits (size) << 20;
14620 neon_dp_fixup (&inst);
14624 do_neon_dyadic_long (void)
14626 /* FIXME: Type checking for lengthening op. */
14627 struct neon_type_el et = neon_check_type (3, NS_QDD,
14628 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14629 neon_mixed_length (et, et.size);
14633 do_neon_abal (void)
14635 struct neon_type_el et = neon_check_type (3, NS_QDD,
14636 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14637 neon_mixed_length (et, et.size);
14641 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14643 if (inst.operands[2].isscalar)
14645 struct neon_type_el et = neon_check_type (3, NS_QDS,
14646 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14647 NEON_ENCODE (SCALAR, inst);
14648 neon_mul_mac (et, et.type == NT_unsigned);
14652 struct neon_type_el et = neon_check_type (3, NS_QDD,
14653 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14654 NEON_ENCODE (INTEGER, inst);
14655 neon_mixed_length (et, et.size);
14660 do_neon_mac_maybe_scalar_long (void)
14662 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14666 do_neon_dyadic_wide (void)
14668 struct neon_type_el et = neon_check_type (3, NS_QQD,
14669 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14670 neon_mixed_length (et, et.size);
14674 do_neon_dyadic_narrow (void)
14676 struct neon_type_el et = neon_check_type (3, NS_QDD,
14677 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14678 /* Operand sign is unimportant, and the U bit is part of the opcode,
14679 so force the operand type to integer. */
14680 et.type = NT_integer;
14681 neon_mixed_length (et, et.size / 2);
14685 do_neon_mul_sat_scalar_long (void)
14687 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14691 do_neon_vmull (void)
14693 if (inst.operands[2].isscalar)
14694 do_neon_mac_maybe_scalar_long ();
14697 struct neon_type_el et = neon_check_type (3, NS_QDD,
14698 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14699 if (et.type == NT_poly)
14700 NEON_ENCODE (POLY, inst);
14702 NEON_ENCODE (INTEGER, inst);
14703 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14704 zero. Should be OK as-is. */
14705 neon_mixed_length (et, et.size);
14712 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14713 struct neon_type_el et = neon_check_type (3, rs,
14714 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14715 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14717 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14718 _("shift out of range"));
14719 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14720 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14721 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14722 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14723 inst.instruction |= LOW4 (inst.operands[2].reg);
14724 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14725 inst.instruction |= neon_quad (rs) << 6;
14726 inst.instruction |= imm << 8;
14728 neon_dp_fixup (&inst);
14734 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14735 struct neon_type_el et = neon_check_type (2, rs,
14736 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14737 unsigned op = (inst.instruction >> 7) & 3;
14738 /* N (width of reversed regions) is encoded as part of the bitmask. We
14739 extract it here to check the elements to be reversed are smaller.
14740 Otherwise we'd get a reserved instruction. */
14741 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14742 gas_assert (elsize != 0);
14743 constraint (et.size >= elsize,
14744 _("elements must be smaller than reversal region"));
14745 neon_two_same (neon_quad (rs), 1, et.size);
14751 if (inst.operands[1].isscalar)
14753 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14754 struct neon_type_el et = neon_check_type (2, rs,
14755 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14756 unsigned sizebits = et.size >> 3;
14757 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14758 int logsize = neon_logbits (et.size);
14759 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14761 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14764 NEON_ENCODE (SCALAR, inst);
14765 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14766 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14767 inst.instruction |= LOW4 (dm);
14768 inst.instruction |= HI1 (dm) << 5;
14769 inst.instruction |= neon_quad (rs) << 6;
14770 inst.instruction |= x << 17;
14771 inst.instruction |= sizebits << 16;
14773 neon_dp_fixup (&inst);
14777 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14778 struct neon_type_el et = neon_check_type (2, rs,
14779 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14780 /* Duplicate ARM register to lanes of vector. */
14781 NEON_ENCODE (ARMREG, inst);
14784 case 8: inst.instruction |= 0x400000; break;
14785 case 16: inst.instruction |= 0x000020; break;
14786 case 32: inst.instruction |= 0x000000; break;
14789 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14790 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14791 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14792 inst.instruction |= neon_quad (rs) << 21;
14793 /* The encoding for this instruction is identical for the ARM and Thumb
14794 variants, except for the condition field. */
14795 do_vfp_cond_or_thumb ();
14799 /* VMOV has particularly many variations. It can be one of:
14800 0. VMOV<c><q> <Qd>, <Qm>
14801 1. VMOV<c><q> <Dd>, <Dm>
14802 (Register operations, which are VORR with Rm = Rn.)
14803 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14804 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14806 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14807 (ARM register to scalar.)
14808 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14809 (Two ARM registers to vector.)
14810 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14811 (Scalar to ARM register.)
14812 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14813 (Vector to two ARM registers.)
14814 8. VMOV.F32 <Sd>, <Sm>
14815 9. VMOV.F64 <Dd>, <Dm>
14816 (VFP register moves.)
14817 10. VMOV.F32 <Sd>, #imm
14818 11. VMOV.F64 <Dd>, #imm
14819 (VFP float immediate load.)
14820 12. VMOV <Rd>, <Sm>
14821 (VFP single to ARM reg.)
14822 13. VMOV <Sd>, <Rm>
14823 (ARM reg to VFP single.)
14824 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14825 (Two ARM regs to two VFP singles.)
14826 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14827 (Two VFP singles to two ARM regs.)
14829 These cases can be disambiguated using neon_select_shape, except cases 1/9
14830 and 3/11 which depend on the operand type too.
14832 All the encoded bits are hardcoded by this function.
14834 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14835 Cases 5, 7 may be used with VFPv2 and above.
14837 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14838 can specify a type where it doesn't make sense to, and is ignored). */
14843 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14844 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14846 struct neon_type_el et;
14847 const char *ldconst = 0;
14851 case NS_DD: /* case 1/9. */
14852 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14853 /* It is not an error here if no type is given. */
14855 if (et.type == NT_float && et.size == 64)
14857 do_vfp_nsyn_opcode ("fcpyd");
14860 /* fall through. */
14862 case NS_QQ: /* case 0/1. */
14864 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14866 /* The architecture manual I have doesn't explicitly state which
14867 value the U bit should have for register->register moves, but
14868 the equivalent VORR instruction has U = 0, so do that. */
14869 inst.instruction = 0x0200110;
14870 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14871 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14872 inst.instruction |= LOW4 (inst.operands[1].reg);
14873 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14874 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14875 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14876 inst.instruction |= neon_quad (rs) << 6;
14878 neon_dp_fixup (&inst);
14882 case NS_DI: /* case 3/11. */
14883 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14885 if (et.type == NT_float && et.size == 64)
14887 /* case 11 (fconstd). */
14888 ldconst = "fconstd";
14889 goto encode_fconstd;
14891 /* fall through. */
14893 case NS_QI: /* case 2/3. */
14894 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14896 inst.instruction = 0x0800010;
14897 neon_move_immediate ();
14898 neon_dp_fixup (&inst);
14901 case NS_SR: /* case 4. */
14903 unsigned bcdebits = 0;
14905 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14906 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14908 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14909 logsize = neon_logbits (et.size);
14911 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14913 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14914 && et.size != 32, _(BAD_FPU));
14915 constraint (et.type == NT_invtype, _("bad type for scalar"));
14916 constraint (x >= 64 / et.size, _("scalar index out of range"));
14920 case 8: bcdebits = 0x8; break;
14921 case 16: bcdebits = 0x1; break;
14922 case 32: bcdebits = 0x0; break;
14926 bcdebits |= x << logsize;
14928 inst.instruction = 0xe000b10;
14929 do_vfp_cond_or_thumb ();
14930 inst.instruction |= LOW4 (dn) << 16;
14931 inst.instruction |= HI1 (dn) << 7;
14932 inst.instruction |= inst.operands[1].reg << 12;
14933 inst.instruction |= (bcdebits & 3) << 5;
14934 inst.instruction |= (bcdebits >> 2) << 21;
14938 case NS_DRR: /* case 5 (fmdrr). */
14939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14942 inst.instruction = 0xc400b10;
14943 do_vfp_cond_or_thumb ();
14944 inst.instruction |= LOW4 (inst.operands[0].reg);
14945 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14946 inst.instruction |= inst.operands[1].reg << 12;
14947 inst.instruction |= inst.operands[2].reg << 16;
14950 case NS_RS: /* case 6. */
14953 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14954 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14955 unsigned abcdebits = 0;
14957 et = neon_check_type (2, NS_NULL,
14958 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14959 logsize = neon_logbits (et.size);
14961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14963 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14964 && et.size != 32, _(BAD_FPU));
14965 constraint (et.type == NT_invtype, _("bad type for scalar"));
14966 constraint (x >= 64 / et.size, _("scalar index out of range"));
14970 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14971 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14972 case 32: abcdebits = 0x00; break;
14976 abcdebits |= x << logsize;
14977 inst.instruction = 0xe100b10;
14978 do_vfp_cond_or_thumb ();
14979 inst.instruction |= LOW4 (dn) << 16;
14980 inst.instruction |= HI1 (dn) << 7;
14981 inst.instruction |= inst.operands[0].reg << 12;
14982 inst.instruction |= (abcdebits & 3) << 5;
14983 inst.instruction |= (abcdebits >> 2) << 21;
14987 case NS_RRD: /* case 7 (fmrrd). */
14988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14991 inst.instruction = 0xc500b10;
14992 do_vfp_cond_or_thumb ();
14993 inst.instruction |= inst.operands[0].reg << 12;
14994 inst.instruction |= inst.operands[1].reg << 16;
14995 inst.instruction |= LOW4 (inst.operands[2].reg);
14996 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14999 case NS_FF: /* case 8 (fcpys). */
15000 do_vfp_nsyn_opcode ("fcpys");
15003 case NS_FI: /* case 10 (fconsts). */
15004 ldconst = "fconsts";
15006 if (is_quarter_float (inst.operands[1].imm))
15008 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15009 do_vfp_nsyn_opcode (ldconst);
15012 first_error (_("immediate out of range"));
15015 case NS_RF: /* case 12 (fmrs). */
15016 do_vfp_nsyn_opcode ("fmrs");
15019 case NS_FR: /* case 13 (fmsr). */
15020 do_vfp_nsyn_opcode ("fmsr");
15023 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15024 (one of which is a list), but we have parsed four. Do some fiddling to
15025 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15027 case NS_RRFF: /* case 14 (fmrrs). */
15028 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15029 _("VFP registers must be adjacent"));
15030 inst.operands[2].imm = 2;
15031 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15032 do_vfp_nsyn_opcode ("fmrrs");
15035 case NS_FFRR: /* case 15 (fmsrr). */
15036 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15037 _("VFP registers must be adjacent"));
15038 inst.operands[1] = inst.operands[2];
15039 inst.operands[2] = inst.operands[3];
15040 inst.operands[0].imm = 2;
15041 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15042 do_vfp_nsyn_opcode ("fmsrr");
15051 do_neon_rshift_round_imm (void)
15053 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15054 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15055 int imm = inst.operands[2].imm;
15057 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15060 inst.operands[2].present = 0;
15065 constraint (imm < 1 || (unsigned)imm > et.size,
15066 _("immediate out of range for shift"));
15067 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15072 do_neon_movl (void)
15074 struct neon_type_el et = neon_check_type (2, NS_QD,
15075 N_EQK | N_DBL, N_SU_32 | N_KEY);
15076 unsigned sizebits = et.size >> 3;
15077 inst.instruction |= sizebits << 19;
15078 neon_two_same (0, et.type == NT_unsigned, -1);
15084 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15085 struct neon_type_el et = neon_check_type (2, rs,
15086 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15087 NEON_ENCODE (INTEGER, inst);
15088 neon_two_same (neon_quad (rs), 1, et.size);
15092 do_neon_zip_uzp (void)
15094 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15095 struct neon_type_el et = neon_check_type (2, rs,
15096 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15097 if (rs == NS_DD && et.size == 32)
15099 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15100 inst.instruction = N_MNEM_vtrn;
15104 neon_two_same (neon_quad (rs), 1, et.size);
15108 do_neon_sat_abs_neg (void)
15110 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15111 struct neon_type_el et = neon_check_type (2, rs,
15112 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15113 neon_two_same (neon_quad (rs), 1, et.size);
15117 do_neon_pair_long (void)
15119 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15120 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15121 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15122 inst.instruction |= (et.type == NT_unsigned) << 7;
15123 neon_two_same (neon_quad (rs), 1, et.size);
15127 do_neon_recip_est (void)
15129 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15130 struct neon_type_el et = neon_check_type (2, rs,
15131 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15132 inst.instruction |= (et.type == NT_float) << 8;
15133 neon_two_same (neon_quad (rs), 1, et.size);
15139 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15140 struct neon_type_el et = neon_check_type (2, rs,
15141 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15142 neon_two_same (neon_quad (rs), 1, et.size);
15148 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15149 struct neon_type_el et = neon_check_type (2, rs,
15150 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15151 neon_two_same (neon_quad (rs), 1, et.size);
15157 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15158 struct neon_type_el et = neon_check_type (2, rs,
15159 N_EQK | N_INT, N_8 | N_KEY);
15160 neon_two_same (neon_quad (rs), 1, et.size);
15166 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15167 neon_two_same (neon_quad (rs), 1, -1);
15171 do_neon_tbl_tbx (void)
15173 unsigned listlenbits;
15174 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15176 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15178 first_error (_("bad list length for table lookup"));
15182 listlenbits = inst.operands[1].imm - 1;
15183 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15184 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15185 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15186 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15187 inst.instruction |= LOW4 (inst.operands[2].reg);
15188 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15189 inst.instruction |= listlenbits << 8;
15191 neon_dp_fixup (&inst);
15195 do_neon_ldm_stm (void)
15197 /* P, U and L bits are part of bitmask. */
15198 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15199 unsigned offsetbits = inst.operands[1].imm * 2;
15201 if (inst.operands[1].issingle)
15203 do_vfp_nsyn_ldm_stm (is_dbmode);
15207 constraint (is_dbmode && !inst.operands[0].writeback,
15208 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15210 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15211 _("register list must contain at least 1 and at most 16 "
15214 inst.instruction |= inst.operands[0].reg << 16;
15215 inst.instruction |= inst.operands[0].writeback << 21;
15216 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15217 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15219 inst.instruction |= offsetbits;
15221 do_vfp_cond_or_thumb ();
15225 do_neon_ldr_str (void)
15227 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15229 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15230 And is UNPREDICTABLE in thumb mode. */
15232 && inst.operands[1].reg == REG_PC
15233 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15235 if (!thumb_mode && warn_on_deprecated)
15236 as_warn (_("Use of PC here is deprecated"));
15238 inst.error = _("Use of PC here is UNPREDICTABLE");
15241 if (inst.operands[0].issingle)
15244 do_vfp_nsyn_opcode ("flds");
15246 do_vfp_nsyn_opcode ("fsts");
15251 do_vfp_nsyn_opcode ("fldd");
15253 do_vfp_nsyn_opcode ("fstd");
15257 /* "interleave" version also handles non-interleaving register VLD1/VST1
15261 do_neon_ld_st_interleave (void)
15263 struct neon_type_el et = neon_check_type (1, NS_NULL,
15264 N_8 | N_16 | N_32 | N_64);
15265 unsigned alignbits = 0;
15267 /* The bits in this table go:
15268 0: register stride of one (0) or two (1)
15269 1,2: register list length, minus one (1, 2, 3, 4).
15270 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15271 We use -1 for invalid entries. */
15272 const int typetable[] =
15274 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15275 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15276 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15277 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15281 if (et.type == NT_invtype)
15284 if (inst.operands[1].immisalign)
15285 switch (inst.operands[1].imm >> 8)
15287 case 64: alignbits = 1; break;
15289 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15290 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15291 goto bad_alignment;
15295 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15296 goto bad_alignment;
15301 first_error (_("bad alignment"));
15305 inst.instruction |= alignbits << 4;
15306 inst.instruction |= neon_logbits (et.size) << 6;
15308 /* Bits [4:6] of the immediate in a list specifier encode register stride
15309 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15310 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15311 up the right value for "type" in a table based on this value and the given
15312 list style, then stick it back. */
15313 idx = ((inst.operands[0].imm >> 4) & 7)
15314 | (((inst.instruction >> 8) & 3) << 3);
15316 typebits = typetable[idx];
15318 constraint (typebits == -1, _("bad list type for instruction"));
15320 inst.instruction &= ~0xf00;
15321 inst.instruction |= typebits << 8;
15324 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15325 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15326 otherwise. The variable arguments are a list of pairs of legal (size, align)
15327 values, terminated with -1. */
15330 neon_alignment_bit (int size, int align, int *do_align, ...)
15333 int result = FAIL, thissize, thisalign;
15335 if (!inst.operands[1].immisalign)
15341 va_start (ap, do_align);
15345 thissize = va_arg (ap, int);
15346 if (thissize == -1)
15348 thisalign = va_arg (ap, int);
15350 if (size == thissize && align == thisalign)
15353 while (result != SUCCESS);
15357 if (result == SUCCESS)
15360 first_error (_("unsupported alignment for instruction"));
15366 do_neon_ld_st_lane (void)
15368 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15369 int align_good, do_align = 0;
15370 int logsize = neon_logbits (et.size);
15371 int align = inst.operands[1].imm >> 8;
15372 int n = (inst.instruction >> 8) & 3;
15373 int max_el = 64 / et.size;
15375 if (et.type == NT_invtype)
15378 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15379 _("bad list length"));
15380 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15381 _("scalar index out of range"));
15382 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15384 _("stride of 2 unavailable when element size is 8"));
15388 case 0: /* VLD1 / VST1. */
15389 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15391 if (align_good == FAIL)
15395 unsigned alignbits = 0;
15398 case 16: alignbits = 0x1; break;
15399 case 32: alignbits = 0x3; break;
15402 inst.instruction |= alignbits << 4;
15406 case 1: /* VLD2 / VST2. */
15407 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15409 if (align_good == FAIL)
15412 inst.instruction |= 1 << 4;
15415 case 2: /* VLD3 / VST3. */
15416 constraint (inst.operands[1].immisalign,
15417 _("can't use alignment with this instruction"));
15420 case 3: /* VLD4 / VST4. */
15421 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15422 16, 64, 32, 64, 32, 128, -1);
15423 if (align_good == FAIL)
15427 unsigned alignbits = 0;
15430 case 8: alignbits = 0x1; break;
15431 case 16: alignbits = 0x1; break;
15432 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15435 inst.instruction |= alignbits << 4;
15442 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15443 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15444 inst.instruction |= 1 << (4 + logsize);
15446 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15447 inst.instruction |= logsize << 10;
15450 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15453 do_neon_ld_dup (void)
15455 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15456 int align_good, do_align = 0;
15458 if (et.type == NT_invtype)
15461 switch ((inst.instruction >> 8) & 3)
15463 case 0: /* VLD1. */
15464 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15465 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15466 &do_align, 16, 16, 32, 32, -1);
15467 if (align_good == FAIL)
15469 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15472 case 2: inst.instruction |= 1 << 5; break;
15473 default: first_error (_("bad list length")); return;
15475 inst.instruction |= neon_logbits (et.size) << 6;
15478 case 1: /* VLD2. */
15479 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15480 &do_align, 8, 16, 16, 32, 32, 64, -1);
15481 if (align_good == FAIL)
15483 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15484 _("bad list length"));
15485 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15486 inst.instruction |= 1 << 5;
15487 inst.instruction |= neon_logbits (et.size) << 6;
15490 case 2: /* VLD3. */
15491 constraint (inst.operands[1].immisalign,
15492 _("can't use alignment with this instruction"));
15493 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15494 _("bad list length"));
15495 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15496 inst.instruction |= 1 << 5;
15497 inst.instruction |= neon_logbits (et.size) << 6;
15500 case 3: /* VLD4. */
15502 int align = inst.operands[1].imm >> 8;
15503 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15504 16, 64, 32, 64, 32, 128, -1);
15505 if (align_good == FAIL)
15507 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15508 _("bad list length"));
15509 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15510 inst.instruction |= 1 << 5;
15511 if (et.size == 32 && align == 128)
15512 inst.instruction |= 0x3 << 6;
15514 inst.instruction |= neon_logbits (et.size) << 6;
15521 inst.instruction |= do_align << 4;
15524 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15525 apart from bits [11:4]. */
15528 do_neon_ldx_stx (void)
15530 if (inst.operands[1].isreg)
15531 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15533 switch (NEON_LANE (inst.operands[0].imm))
15535 case NEON_INTERLEAVE_LANES:
15536 NEON_ENCODE (INTERLV, inst);
15537 do_neon_ld_st_interleave ();
15540 case NEON_ALL_LANES:
15541 NEON_ENCODE (DUP, inst);
15546 NEON_ENCODE (LANE, inst);
15547 do_neon_ld_st_lane ();
15550 /* L bit comes from bit mask. */
15551 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15552 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15553 inst.instruction |= inst.operands[1].reg << 16;
15555 if (inst.operands[1].postind)
15557 int postreg = inst.operands[1].imm & 0xf;
15558 constraint (!inst.operands[1].immisreg,
15559 _("post-index must be a register"));
15560 constraint (postreg == 0xd || postreg == 0xf,
15561 _("bad register for post-index"));
15562 inst.instruction |= postreg;
15564 else if (inst.operands[1].writeback)
15566 inst.instruction |= 0xd;
15569 inst.instruction |= 0xf;
15572 inst.instruction |= 0xf9000000;
15574 inst.instruction |= 0xf4000000;
15577 /* Overall per-instruction processing. */
15579 /* We need to be able to fix up arbitrary expressions in some statements.
15580 This is so that we can handle symbols that are an arbitrary distance from
15581 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15582 which returns part of an address in a form which will be valid for
15583 a data instruction. We do this by pushing the expression into a symbol
15584 in the expr_section, and creating a fix for that. */
15587 fix_new_arm (fragS * frag,
15601 /* Create an absolute valued symbol, so we have something to
15602 refer to in the object file. Unfortunately for us, gas's
15603 generic expression parsing will already have folded out
15604 any use of .set foo/.type foo %function that may have
15605 been used to set type information of the target location,
15606 that's being specified symbolically. We have to presume
15607 the user knows what they are doing. */
15611 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15613 symbol = symbol_find_or_make (name);
15614 S_SET_SEGMENT (symbol, absolute_section);
15615 symbol_set_frag (symbol, &zero_address_frag);
15616 S_SET_VALUE (symbol, exp->X_add_number);
15617 exp->X_op = O_symbol;
15618 exp->X_add_symbol = symbol;
15619 exp->X_add_number = 0;
15625 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15626 (enum bfd_reloc_code_real) reloc);
15630 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15631 pc_rel, (enum bfd_reloc_code_real) reloc);
15635 /* Mark whether the fix is to a THUMB instruction, or an ARM
15637 new_fix->tc_fix_data = thumb_mode;
15640 /* Create a frg for an instruction requiring relaxation. */
15642 output_relax_insn (void)
15648 /* The size of the instruction is unknown, so tie the debug info to the
15649 start of the instruction. */
15650 dwarf2_emit_insn (0);
15652 switch (inst.reloc.exp.X_op)
15655 sym = inst.reloc.exp.X_add_symbol;
15656 offset = inst.reloc.exp.X_add_number;
15660 offset = inst.reloc.exp.X_add_number;
15663 sym = make_expr_symbol (&inst.reloc.exp);
15667 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15668 inst.relax, sym, offset, NULL/*offset, opcode*/);
15669 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15672 /* Write a 32-bit thumb instruction to buf. */
15674 put_thumb32_insn (char * buf, unsigned long insn)
15676 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15677 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15681 output_inst (const char * str)
15687 as_bad ("%s -- `%s'", inst.error, str);
15692 output_relax_insn ();
15695 if (inst.size == 0)
15698 to = frag_more (inst.size);
15699 /* PR 9814: Record the thumb mode into the current frag so that we know
15700 what type of NOP padding to use, if necessary. We override any previous
15701 setting so that if the mode has changed then the NOPS that we use will
15702 match the encoding of the last instruction in the frag. */
15703 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15705 if (thumb_mode && (inst.size > THUMB_SIZE))
15707 gas_assert (inst.size == (2 * THUMB_SIZE));
15708 put_thumb32_insn (to, inst.instruction);
15710 else if (inst.size > INSN_SIZE)
15712 gas_assert (inst.size == (2 * INSN_SIZE));
15713 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15714 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15717 md_number_to_chars (to, inst.instruction, inst.size);
15719 if (inst.reloc.type != BFD_RELOC_UNUSED)
15720 fix_new_arm (frag_now, to - frag_now->fr_literal,
15721 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15724 dwarf2_emit_insn (inst.size);
15728 output_it_inst (int cond, int mask, char * to)
15730 unsigned long instruction = 0xbf00;
15733 instruction |= mask;
15734 instruction |= cond << 4;
15738 to = frag_more (2);
15740 dwarf2_emit_insn (2);
15744 md_number_to_chars (to, instruction, 2);
15749 /* Tag values used in struct asm_opcode's tag field. */
15752 OT_unconditional, /* Instruction cannot be conditionalized.
15753 The ARM condition field is still 0xE. */
15754 OT_unconditionalF, /* Instruction cannot be conditionalized
15755 and carries 0xF in its ARM condition field. */
15756 OT_csuffix, /* Instruction takes a conditional suffix. */
15757 OT_csuffixF, /* Some forms of the instruction take a conditional
15758 suffix, others place 0xF where the condition field
15760 OT_cinfix3, /* Instruction takes a conditional infix,
15761 beginning at character index 3. (In
15762 unified mode, it becomes a suffix.) */
15763 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15764 tsts, cmps, cmns, and teqs. */
15765 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15766 character index 3, even in unified mode. Used for
15767 legacy instructions where suffix and infix forms
15768 may be ambiguous. */
15769 OT_csuf_or_in3, /* Instruction takes either a conditional
15770 suffix or an infix at character index 3. */
15771 OT_odd_infix_unc, /* This is the unconditional variant of an
15772 instruction that takes a conditional infix
15773 at an unusual position. In unified mode,
15774 this variant will accept a suffix. */
15775 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15776 are the conditional variants of instructions that
15777 take conditional infixes in unusual positions.
15778 The infix appears at character index
15779 (tag - OT_odd_infix_0). These are not accepted
15780 in unified mode. */
15783 /* Subroutine of md_assemble, responsible for looking up the primary
15784 opcode from the mnemonic the user wrote. STR points to the
15785 beginning of the mnemonic.
15787 This is not simply a hash table lookup, because of conditional
15788 variants. Most instructions have conditional variants, which are
15789 expressed with a _conditional affix_ to the mnemonic. If we were
15790 to encode each conditional variant as a literal string in the opcode
15791 table, it would have approximately 20,000 entries.
15793 Most mnemonics take this affix as a suffix, and in unified syntax,
15794 'most' is upgraded to 'all'. However, in the divided syntax, some
15795 instructions take the affix as an infix, notably the s-variants of
15796 the arithmetic instructions. Of those instructions, all but six
15797 have the infix appear after the third character of the mnemonic.
15799 Accordingly, the algorithm for looking up primary opcodes given
15802 1. Look up the identifier in the opcode table.
15803 If we find a match, go to step U.
15805 2. Look up the last two characters of the identifier in the
15806 conditions table. If we find a match, look up the first N-2
15807 characters of the identifier in the opcode table. If we
15808 find a match, go to step CE.
15810 3. Look up the fourth and fifth characters of the identifier in
15811 the conditions table. If we find a match, extract those
15812 characters from the identifier, and look up the remaining
15813 characters in the opcode table. If we find a match, go
15818 U. Examine the tag field of the opcode structure, in case this is
15819 one of the six instructions with its conditional infix in an
15820 unusual place. If it is, the tag tells us where to find the
15821 infix; look it up in the conditions table and set inst.cond
15822 accordingly. Otherwise, this is an unconditional instruction.
15823 Again set inst.cond accordingly. Return the opcode structure.
15825 CE. Examine the tag field to make sure this is an instruction that
15826 should receive a conditional suffix. If it is not, fail.
15827 Otherwise, set inst.cond from the suffix we already looked up,
15828 and return the opcode structure.
15830 CM. Examine the tag field to make sure this is an instruction that
15831 should receive a conditional infix after the third character.
15832 If it is not, fail. Otherwise, undo the edits to the current
15833 line of input and proceed as for case CE. */
15835 static const struct asm_opcode *
15836 opcode_lookup (char **str)
15840 const struct asm_opcode *opcode;
15841 const struct asm_cond *cond;
15844 /* Scan up to the end of the mnemonic, which must end in white space,
15845 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15846 for (base = end = *str; *end != '\0'; end++)
15847 if (*end == ' ' || *end == '.')
15853 /* Handle a possible width suffix and/or Neon type suffix. */
15858 /* The .w and .n suffixes are only valid if the unified syntax is in
15860 if (unified_syntax && end[1] == 'w')
15862 else if (unified_syntax && end[1] == 'n')
15867 inst.vectype.elems = 0;
15869 *str = end + offset;
15871 if (end[offset] == '.')
15873 /* See if we have a Neon type suffix (possible in either unified or
15874 non-unified ARM syntax mode). */
15875 if (parse_neon_type (&inst.vectype, str) == FAIL)
15878 else if (end[offset] != '\0' && end[offset] != ' ')
15884 /* Look for unaffixed or special-case affixed mnemonic. */
15885 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15890 if (opcode->tag < OT_odd_infix_0)
15892 inst.cond = COND_ALWAYS;
15896 if (warn_on_deprecated && unified_syntax)
15897 as_warn (_("conditional infixes are deprecated in unified syntax"));
15898 affix = base + (opcode->tag - OT_odd_infix_0);
15899 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15902 inst.cond = cond->value;
15906 /* Cannot have a conditional suffix on a mnemonic of less than two
15908 if (end - base < 3)
15911 /* Look for suffixed mnemonic. */
15913 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15914 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15916 if (opcode && cond)
15919 switch (opcode->tag)
15921 case OT_cinfix3_legacy:
15922 /* Ignore conditional suffixes matched on infix only mnemonics. */
15926 case OT_cinfix3_deprecated:
15927 case OT_odd_infix_unc:
15928 if (!unified_syntax)
15930 /* else fall through */
15934 case OT_csuf_or_in3:
15935 inst.cond = cond->value;
15938 case OT_unconditional:
15939 case OT_unconditionalF:
15941 inst.cond = cond->value;
15944 /* Delayed diagnostic. */
15945 inst.error = BAD_COND;
15946 inst.cond = COND_ALWAYS;
15955 /* Cannot have a usual-position infix on a mnemonic of less than
15956 six characters (five would be a suffix). */
15957 if (end - base < 6)
15960 /* Look for infixed mnemonic in the usual position. */
15962 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15966 memcpy (save, affix, 2);
15967 memmove (affix, affix + 2, (end - affix) - 2);
15968 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15970 memmove (affix + 2, affix, (end - affix) - 2);
15971 memcpy (affix, save, 2);
15974 && (opcode->tag == OT_cinfix3
15975 || opcode->tag == OT_cinfix3_deprecated
15976 || opcode->tag == OT_csuf_or_in3
15977 || opcode->tag == OT_cinfix3_legacy))
15980 if (warn_on_deprecated && unified_syntax
15981 && (opcode->tag == OT_cinfix3
15982 || opcode->tag == OT_cinfix3_deprecated))
15983 as_warn (_("conditional infixes are deprecated in unified syntax"));
15985 inst.cond = cond->value;
15992 /* This function generates an initial IT instruction, leaving its block
15993 virtually open for the new instructions. Eventually,
15994 the mask will be updated by now_it_add_mask () each time
15995 a new instruction needs to be included in the IT block.
15996 Finally, the block is closed with close_automatic_it_block ().
15997 The block closure can be requested either from md_assemble (),
15998 a tencode (), or due to a label hook. */
16001 new_automatic_it_block (int cond)
16003 now_it.state = AUTOMATIC_IT_BLOCK;
16004 now_it.mask = 0x18;
16006 now_it.block_length = 1;
16007 mapping_state (MAP_THUMB);
16008 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16011 /* Close an automatic IT block.
16012 See comments in new_automatic_it_block (). */
16015 close_automatic_it_block (void)
16017 now_it.mask = 0x10;
16018 now_it.block_length = 0;
16021 /* Update the mask of the current automatically-generated IT
16022 instruction. See comments in new_automatic_it_block (). */
16025 now_it_add_mask (int cond)
16027 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16028 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16029 | ((bitvalue) << (nbit)))
16030 const int resulting_bit = (cond & 1);
16032 now_it.mask &= 0xf;
16033 now_it.mask = SET_BIT_VALUE (now_it.mask,
16035 (5 - now_it.block_length));
16036 now_it.mask = SET_BIT_VALUE (now_it.mask,
16038 ((5 - now_it.block_length) - 1) );
16039 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16042 #undef SET_BIT_VALUE
16045 /* The IT blocks handling machinery is accessed through the these functions:
16046 it_fsm_pre_encode () from md_assemble ()
16047 set_it_insn_type () optional, from the tencode functions
16048 set_it_insn_type_last () ditto
16049 in_it_block () ditto
16050 it_fsm_post_encode () from md_assemble ()
16051 force_automatic_it_block_close () from label habdling functions
16054 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16055 initializing the IT insn type with a generic initial value depending
16056 on the inst.condition.
16057 2) During the tencode function, two things may happen:
16058 a) The tencode function overrides the IT insn type by
16059 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16060 b) The tencode function queries the IT block state by
16061 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16063 Both set_it_insn_type and in_it_block run the internal FSM state
16064 handling function (handle_it_state), because: a) setting the IT insn
16065 type may incur in an invalid state (exiting the function),
16066 and b) querying the state requires the FSM to be updated.
16067 Specifically we want to avoid creating an IT block for conditional
16068 branches, so it_fsm_pre_encode is actually a guess and we can't
16069 determine whether an IT block is required until the tencode () routine
16070 has decided what type of instruction this actually it.
16071 Because of this, if set_it_insn_type and in_it_block have to be used,
16072 set_it_insn_type has to be called first.
16074 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16075 determines the insn IT type depending on the inst.cond code.
16076 When a tencode () routine encodes an instruction that can be
16077 either outside an IT block, or, in the case of being inside, has to be
16078 the last one, set_it_insn_type_last () will determine the proper
16079 IT instruction type based on the inst.cond code. Otherwise,
16080 set_it_insn_type can be called for overriding that logic or
16081 for covering other cases.
16083 Calling handle_it_state () may not transition the IT block state to
16084 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16085 still queried. Instead, if the FSM determines that the state should
16086 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16087 after the tencode () function: that's what it_fsm_post_encode () does.
16089 Since in_it_block () calls the state handling function to get an
16090 updated state, an error may occur (due to invalid insns combination).
16091 In that case, inst.error is set.
16092 Therefore, inst.error has to be checked after the execution of
16093 the tencode () routine.
16095 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16096 any pending state change (if any) that didn't take place in
16097 handle_it_state () as explained above. */
16100 it_fsm_pre_encode (void)
16102 if (inst.cond != COND_ALWAYS)
16103 inst.it_insn_type = INSIDE_IT_INSN;
16105 inst.it_insn_type = OUTSIDE_IT_INSN;
16107 now_it.state_handled = 0;
16110 /* IT state FSM handling function. */
16113 handle_it_state (void)
16115 now_it.state_handled = 1;
16117 switch (now_it.state)
16119 case OUTSIDE_IT_BLOCK:
16120 switch (inst.it_insn_type)
16122 case OUTSIDE_IT_INSN:
16125 case INSIDE_IT_INSN:
16126 case INSIDE_IT_LAST_INSN:
16127 if (thumb_mode == 0)
16130 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16131 as_tsktsk (_("Warning: conditional outside an IT block"\
16136 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16137 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16139 /* Automatically generate the IT instruction. */
16140 new_automatic_it_block (inst.cond);
16141 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16142 close_automatic_it_block ();
16146 inst.error = BAD_OUT_IT;
16152 case IF_INSIDE_IT_LAST_INSN:
16153 case NEUTRAL_IT_INSN:
16157 now_it.state = MANUAL_IT_BLOCK;
16158 now_it.block_length = 0;
16163 case AUTOMATIC_IT_BLOCK:
16164 /* Three things may happen now:
16165 a) We should increment current it block size;
16166 b) We should close current it block (closing insn or 4 insns);
16167 c) We should close current it block and start a new one (due
16168 to incompatible conditions or
16169 4 insns-length block reached). */
16171 switch (inst.it_insn_type)
16173 case OUTSIDE_IT_INSN:
16174 /* The closure of the block shall happen immediatelly,
16175 so any in_it_block () call reports the block as closed. */
16176 force_automatic_it_block_close ();
16179 case INSIDE_IT_INSN:
16180 case INSIDE_IT_LAST_INSN:
16181 case IF_INSIDE_IT_LAST_INSN:
16182 now_it.block_length++;
16184 if (now_it.block_length > 4
16185 || !now_it_compatible (inst.cond))
16187 force_automatic_it_block_close ();
16188 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16189 new_automatic_it_block (inst.cond);
16193 now_it_add_mask (inst.cond);
16196 if (now_it.state == AUTOMATIC_IT_BLOCK
16197 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16198 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16199 close_automatic_it_block ();
16202 case NEUTRAL_IT_INSN:
16203 now_it.block_length++;
16205 if (now_it.block_length > 4)
16206 force_automatic_it_block_close ();
16208 now_it_add_mask (now_it.cc & 1);
16212 close_automatic_it_block ();
16213 now_it.state = MANUAL_IT_BLOCK;
16218 case MANUAL_IT_BLOCK:
16220 /* Check conditional suffixes. */
16221 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16224 now_it.mask &= 0x1f;
16225 is_last = (now_it.mask == 0x10);
16227 switch (inst.it_insn_type)
16229 case OUTSIDE_IT_INSN:
16230 inst.error = BAD_NOT_IT;
16233 case INSIDE_IT_INSN:
16234 if (cond != inst.cond)
16236 inst.error = BAD_IT_COND;
16241 case INSIDE_IT_LAST_INSN:
16242 case IF_INSIDE_IT_LAST_INSN:
16243 if (cond != inst.cond)
16245 inst.error = BAD_IT_COND;
16250 inst.error = BAD_BRANCH;
16255 case NEUTRAL_IT_INSN:
16256 /* The BKPT instruction is unconditional even in an IT block. */
16260 inst.error = BAD_IT_IT;
16271 it_fsm_post_encode (void)
16275 if (!now_it.state_handled)
16276 handle_it_state ();
16278 is_last = (now_it.mask == 0x10);
16281 now_it.state = OUTSIDE_IT_BLOCK;
16287 force_automatic_it_block_close (void)
16289 if (now_it.state == AUTOMATIC_IT_BLOCK)
16291 close_automatic_it_block ();
16292 now_it.state = OUTSIDE_IT_BLOCK;
16300 if (!now_it.state_handled)
16301 handle_it_state ();
16303 return now_it.state != OUTSIDE_IT_BLOCK;
16307 md_assemble (char *str)
16310 const struct asm_opcode * opcode;
16312 /* Align the previous label if needed. */
16313 if (last_label_seen != NULL)
16315 symbol_set_frag (last_label_seen, frag_now);
16316 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16317 S_SET_SEGMENT (last_label_seen, now_seg);
16320 memset (&inst, '\0', sizeof (inst));
16321 inst.reloc.type = BFD_RELOC_UNUSED;
16323 opcode = opcode_lookup (&p);
16326 /* It wasn't an instruction, but it might be a register alias of
16327 the form alias .req reg, or a Neon .dn/.qn directive. */
16328 if (! create_register_alias (str, p)
16329 && ! create_neon_reg_alias (str, p))
16330 as_bad (_("bad instruction `%s'"), str);
16335 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16336 as_warn (_("s suffix on comparison instruction is deprecated"));
16338 /* The value which unconditional instructions should have in place of the
16339 condition field. */
16340 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16344 arm_feature_set variant;
16346 variant = cpu_variant;
16347 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16348 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16349 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16350 /* Check that this instruction is supported for this CPU. */
16351 if (!opcode->tvariant
16352 || (thumb_mode == 1
16353 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16355 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16358 if (inst.cond != COND_ALWAYS && !unified_syntax
16359 && opcode->tencode != do_t_branch)
16361 as_bad (_("Thumb does not support conditional execution"));
16365 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16367 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16368 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16369 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16371 /* Two things are addressed here.
16372 1) Implicit require narrow instructions on Thumb-1.
16373 This avoids relaxation accidentally introducing Thumb-2
16375 2) Reject wide instructions in non Thumb-2 cores. */
16376 if (inst.size_req == 0)
16378 else if (inst.size_req == 4)
16380 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16386 inst.instruction = opcode->tvalue;
16388 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16390 /* Prepare the it_insn_type for those encodings that don't set
16392 it_fsm_pre_encode ();
16394 opcode->tencode ();
16396 it_fsm_post_encode ();
16399 if (!(inst.error || inst.relax))
16401 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16402 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16403 if (inst.size_req && inst.size_req != inst.size)
16405 as_bad (_("cannot honor width suffix -- `%s'"), str);
16410 /* Something has gone badly wrong if we try to relax a fixed size
16412 gas_assert (inst.size_req == 0 || !inst.relax);
16414 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16415 *opcode->tvariant);
16416 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16417 set those bits when Thumb-2 32-bit instructions are seen. ie.
16418 anything other than bl/blx and v6-M instructions.
16419 This is overly pessimistic for relaxable instructions. */
16420 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16422 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16423 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16424 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16427 check_neon_suffixes;
16431 mapping_state (MAP_THUMB);
16434 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16438 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16439 is_bx = (opcode->aencode == do_bx);
16441 /* Check that this instruction is supported for this CPU. */
16442 if (!(is_bx && fix_v4bx)
16443 && !(opcode->avariant &&
16444 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16446 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16451 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16455 inst.instruction = opcode->avalue;
16456 if (opcode->tag == OT_unconditionalF)
16457 inst.instruction |= 0xF << 28;
16459 inst.instruction |= inst.cond << 28;
16460 inst.size = INSN_SIZE;
16461 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16463 it_fsm_pre_encode ();
16464 opcode->aencode ();
16465 it_fsm_post_encode ();
16467 /* Arm mode bx is marked as both v4T and v5 because it's still required
16468 on a hypothetical non-thumb v5 core. */
16470 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16472 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16473 *opcode->avariant);
16475 check_neon_suffixes;
16479 mapping_state (MAP_ARM);
16484 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16492 check_it_blocks_finished (void)
16497 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16498 if (seg_info (sect)->tc_segment_info_data.current_it.state
16499 == MANUAL_IT_BLOCK)
16501 as_warn (_("section '%s' finished with an open IT block."),
16505 if (now_it.state == MANUAL_IT_BLOCK)
16506 as_warn (_("file finished with an open IT block."));
16510 /* Various frobbings of labels and their addresses. */
16513 arm_start_line_hook (void)
16515 last_label_seen = NULL;
16519 arm_frob_label (symbolS * sym)
16521 last_label_seen = sym;
16523 ARM_SET_THUMB (sym, thumb_mode);
16525 #if defined OBJ_COFF || defined OBJ_ELF
16526 ARM_SET_INTERWORK (sym, support_interwork);
16529 force_automatic_it_block_close ();
16531 /* Note - do not allow local symbols (.Lxxx) to be labelled
16532 as Thumb functions. This is because these labels, whilst
16533 they exist inside Thumb code, are not the entry points for
16534 possible ARM->Thumb calls. Also, these labels can be used
16535 as part of a computed goto or switch statement. eg gcc
16536 can generate code that looks like this:
16538 ldr r2, [pc, .Laaa]
16548 The first instruction loads the address of the jump table.
16549 The second instruction converts a table index into a byte offset.
16550 The third instruction gets the jump address out of the table.
16551 The fourth instruction performs the jump.
16553 If the address stored at .Laaa is that of a symbol which has the
16554 Thumb_Func bit set, then the linker will arrange for this address
16555 to have the bottom bit set, which in turn would mean that the
16556 address computation performed by the third instruction would end
16557 up with the bottom bit set. Since the ARM is capable of unaligned
16558 word loads, the instruction would then load the incorrect address
16559 out of the jump table, and chaos would ensue. */
16560 if (label_is_thumb_function_name
16561 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16562 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16564 /* When the address of a Thumb function is taken the bottom
16565 bit of that address should be set. This will allow
16566 interworking between Arm and Thumb functions to work
16569 THUMB_SET_FUNC (sym, 1);
16571 label_is_thumb_function_name = FALSE;
16574 dwarf2_emit_label (sym);
16578 arm_data_in_code (void)
16580 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16582 *input_line_pointer = '/';
16583 input_line_pointer += 5;
16584 *input_line_pointer = 0;
16592 arm_canonicalize_symbol_name (char * name)
16596 if (thumb_mode && (len = strlen (name)) > 5
16597 && streq (name + len - 5, "/data"))
16598 *(name + len - 5) = 0;
16603 /* Table of all register names defined by default. The user can
16604 define additional names with .req. Note that all register names
16605 should appear in both upper and lowercase variants. Some registers
16606 also have mixed-case names. */
16608 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16609 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16610 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16611 #define REGSET(p,t) \
16612 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16613 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16614 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16615 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16616 #define REGSETH(p,t) \
16617 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16618 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16619 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16620 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16621 #define REGSET2(p,t) \
16622 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16623 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16624 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16625 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16626 #define SPLRBANK(base,bank,t) \
16627 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16628 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16629 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16630 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16631 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16632 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16634 static const struct reg_entry reg_names[] =
16636 /* ARM integer registers. */
16637 REGSET(r, RN), REGSET(R, RN),
16639 /* ATPCS synonyms. */
16640 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16641 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16642 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16644 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16645 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16646 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16648 /* Well-known aliases. */
16649 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16650 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16652 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16653 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16655 /* Coprocessor numbers. */
16656 REGSET(p, CP), REGSET(P, CP),
16658 /* Coprocessor register numbers. The "cr" variants are for backward
16660 REGSET(c, CN), REGSET(C, CN),
16661 REGSET(cr, CN), REGSET(CR, CN),
16663 /* ARM banked registers. */
16664 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16665 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16666 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16667 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16668 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16669 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16670 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16672 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16673 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16674 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16675 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16676 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16677 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16678 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16679 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16681 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16682 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16683 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16684 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16685 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16686 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16687 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16688 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16689 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16691 /* FPA registers. */
16692 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16693 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16695 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16696 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16698 /* VFP SP registers. */
16699 REGSET(s,VFS), REGSET(S,VFS),
16700 REGSETH(s,VFS), REGSETH(S,VFS),
16702 /* VFP DP Registers. */
16703 REGSET(d,VFD), REGSET(D,VFD),
16704 /* Extra Neon DP registers. */
16705 REGSETH(d,VFD), REGSETH(D,VFD),
16707 /* Neon QP registers. */
16708 REGSET2(q,NQ), REGSET2(Q,NQ),
16710 /* VFP control registers. */
16711 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16712 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16713 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16714 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16715 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16716 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16718 /* Maverick DSP coprocessor registers. */
16719 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16720 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16722 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16723 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16724 REGDEF(dspsc,0,DSPSC),
16726 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16727 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16728 REGDEF(DSPSC,0,DSPSC),
16730 /* iWMMXt data registers - p0, c0-15. */
16731 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16733 /* iWMMXt control registers - p1, c0-3. */
16734 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16735 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16736 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16737 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16739 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16740 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16741 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16742 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16743 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16745 /* XScale accumulator registers. */
16746 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16752 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16753 within psr_required_here. */
16754 static const struct asm_psr psrs[] =
16756 /* Backward compatibility notation. Note that "all" is no longer
16757 truly all possible PSR bits. */
16758 {"all", PSR_c | PSR_f},
16762 /* Individual flags. */
16768 /* Combinations of flags. */
16769 {"fs", PSR_f | PSR_s},
16770 {"fx", PSR_f | PSR_x},
16771 {"fc", PSR_f | PSR_c},
16772 {"sf", PSR_s | PSR_f},
16773 {"sx", PSR_s | PSR_x},
16774 {"sc", PSR_s | PSR_c},
16775 {"xf", PSR_x | PSR_f},
16776 {"xs", PSR_x | PSR_s},
16777 {"xc", PSR_x | PSR_c},
16778 {"cf", PSR_c | PSR_f},
16779 {"cs", PSR_c | PSR_s},
16780 {"cx", PSR_c | PSR_x},
16781 {"fsx", PSR_f | PSR_s | PSR_x},
16782 {"fsc", PSR_f | PSR_s | PSR_c},
16783 {"fxs", PSR_f | PSR_x | PSR_s},
16784 {"fxc", PSR_f | PSR_x | PSR_c},
16785 {"fcs", PSR_f | PSR_c | PSR_s},
16786 {"fcx", PSR_f | PSR_c | PSR_x},
16787 {"sfx", PSR_s | PSR_f | PSR_x},
16788 {"sfc", PSR_s | PSR_f | PSR_c},
16789 {"sxf", PSR_s | PSR_x | PSR_f},
16790 {"sxc", PSR_s | PSR_x | PSR_c},
16791 {"scf", PSR_s | PSR_c | PSR_f},
16792 {"scx", PSR_s | PSR_c | PSR_x},
16793 {"xfs", PSR_x | PSR_f | PSR_s},
16794 {"xfc", PSR_x | PSR_f | PSR_c},
16795 {"xsf", PSR_x | PSR_s | PSR_f},
16796 {"xsc", PSR_x | PSR_s | PSR_c},
16797 {"xcf", PSR_x | PSR_c | PSR_f},
16798 {"xcs", PSR_x | PSR_c | PSR_s},
16799 {"cfs", PSR_c | PSR_f | PSR_s},
16800 {"cfx", PSR_c | PSR_f | PSR_x},
16801 {"csf", PSR_c | PSR_s | PSR_f},
16802 {"csx", PSR_c | PSR_s | PSR_x},
16803 {"cxf", PSR_c | PSR_x | PSR_f},
16804 {"cxs", PSR_c | PSR_x | PSR_s},
16805 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16806 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16807 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16808 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16809 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16810 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16811 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16812 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16813 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16814 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16815 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16816 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16817 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16818 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16819 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16820 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16821 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16822 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16823 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16824 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16825 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16826 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16827 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16828 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16831 /* Table of V7M psr names. */
16832 static const struct asm_psr v7m_psrs[] =
16834 {"apsr", 0 }, {"APSR", 0 },
16835 {"iapsr", 1 }, {"IAPSR", 1 },
16836 {"eapsr", 2 }, {"EAPSR", 2 },
16837 {"psr", 3 }, {"PSR", 3 },
16838 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16839 {"ipsr", 5 }, {"IPSR", 5 },
16840 {"epsr", 6 }, {"EPSR", 6 },
16841 {"iepsr", 7 }, {"IEPSR", 7 },
16842 {"msp", 8 }, {"MSP", 8 },
16843 {"psp", 9 }, {"PSP", 9 },
16844 {"primask", 16}, {"PRIMASK", 16},
16845 {"basepri", 17}, {"BASEPRI", 17},
16846 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16847 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16848 {"faultmask", 19}, {"FAULTMASK", 19},
16849 {"control", 20}, {"CONTROL", 20}
16852 /* Table of all shift-in-operand names. */
16853 static const struct asm_shift_name shift_names [] =
16855 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16856 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16857 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16858 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16859 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16860 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16863 /* Table of all explicit relocation names. */
16865 static struct reloc_entry reloc_names[] =
16867 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16868 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16869 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16870 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16871 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16872 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16873 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16874 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16875 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16876 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16877 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16878 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16879 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16880 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16881 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16882 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16883 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16884 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16888 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16889 static const struct asm_cond conds[] =
16893 {"cs", 0x2}, {"hs", 0x2},
16894 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16908 static struct asm_barrier_opt barrier_opt_names[] =
16910 { "sy", 0xf }, { "SY", 0xf },
16911 { "un", 0x7 }, { "UN", 0x7 },
16912 { "st", 0xe }, { "ST", 0xe },
16913 { "unst", 0x6 }, { "UNST", 0x6 },
16914 { "ish", 0xb }, { "ISH", 0xb },
16915 { "sh", 0xb }, { "SH", 0xb },
16916 { "ishst", 0xa }, { "ISHST", 0xa },
16917 { "shst", 0xa }, { "SHST", 0xa },
16918 { "nsh", 0x7 }, { "NSH", 0x7 },
16919 { "nshst", 0x6 }, { "NSHST", 0x6 },
16920 { "osh", 0x3 }, { "OSH", 0x3 },
16921 { "oshst", 0x2 }, { "OSHST", 0x2 }
16924 /* Table of ARM-format instructions. */
16926 /* Macros for gluing together operand strings. N.B. In all cases
16927 other than OPS0, the trailing OP_stop comes from default
16928 zero-initialization of the unspecified elements of the array. */
16929 #define OPS0() { OP_stop, }
16930 #define OPS1(a) { OP_##a, }
16931 #define OPS2(a,b) { OP_##a,OP_##b, }
16932 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16933 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16934 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16935 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16937 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16938 This is useful when mixing operands for ARM and THUMB, i.e. using the
16939 MIX_ARM_THUMB_OPERANDS macro.
16940 In order to use these macros, prefix the number of operands with _
16942 #define OPS_1(a) { a, }
16943 #define OPS_2(a,b) { a,b, }
16944 #define OPS_3(a,b,c) { a,b,c, }
16945 #define OPS_4(a,b,c,d) { a,b,c,d, }
16946 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16947 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16949 /* These macros abstract out the exact format of the mnemonic table and
16950 save some repeated characters. */
16952 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16953 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16954 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16955 THUMB_VARIANT, do_##ae, do_##te }
16957 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16958 a T_MNEM_xyz enumerator. */
16959 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16960 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16961 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16962 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16964 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16965 infix after the third character. */
16966 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16967 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16968 THUMB_VARIANT, do_##ae, do_##te }
16969 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16970 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16971 THUMB_VARIANT, do_##ae, do_##te }
16972 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16973 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16974 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16975 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16976 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16977 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16978 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16979 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16981 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16982 appear in the condition table. */
16983 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16984 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16985 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16987 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16988 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16989 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16990 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16991 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16992 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16993 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16994 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16995 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16996 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16997 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16998 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16999 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17000 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17001 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17002 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17003 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17004 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17005 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17006 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17008 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17009 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17010 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17011 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17013 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17014 field is still 0xE. Many of the Thumb variants can be executed
17015 conditionally, so this is checked separately. */
17016 #define TUE(mnem, op, top, nops, ops, ae, te) \
17017 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17018 THUMB_VARIANT, do_##ae, do_##te }
17020 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17021 condition code field. */
17022 #define TUF(mnem, op, top, nops, ops, ae, te) \
17023 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17024 THUMB_VARIANT, do_##ae, do_##te }
17026 /* ARM-only variants of all the above. */
17027 #define CE(mnem, op, nops, ops, ae) \
17028 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17030 #define C3(mnem, op, nops, ops, ae) \
17031 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17033 /* Legacy mnemonics that always have conditional infix after the third
17035 #define CL(mnem, op, nops, ops, ae) \
17036 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17037 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17039 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17040 #define cCE(mnem, op, nops, ops, ae) \
17041 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17043 /* Legacy coprocessor instructions where conditional infix and conditional
17044 suffix are ambiguous. For consistency this includes all FPA instructions,
17045 not just the potentially ambiguous ones. */
17046 #define cCL(mnem, op, nops, ops, ae) \
17047 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17048 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17050 /* Coprocessor, takes either a suffix or a position-3 infix
17051 (for an FPA corner case). */
17052 #define C3E(mnem, op, nops, ops, ae) \
17053 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17054 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17056 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17057 { m1 #m2 m3, OPS##nops ops, \
17058 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17059 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17061 #define CM(m1, m2, op, nops, ops, ae) \
17062 xCM_ (m1, , m2, op, nops, ops, ae), \
17063 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17064 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17065 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17066 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17067 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17068 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17069 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17070 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17071 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17072 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17073 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17074 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17075 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17076 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17077 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17078 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17079 xCM_ (m1, le, m2, op, nops, ops, ae), \
17080 xCM_ (m1, al, m2, op, nops, ops, ae)
17082 #define UE(mnem, op, nops, ops, ae) \
17083 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17085 #define UF(mnem, op, nops, ops, ae) \
17086 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17088 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17089 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17090 use the same encoding function for each. */
17091 #define NUF(mnem, op, nops, ops, enc) \
17092 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17093 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17095 /* Neon data processing, version which indirects through neon_enc_tab for
17096 the various overloaded versions of opcodes. */
17097 #define nUF(mnem, op, nops, ops, enc) \
17098 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17099 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17101 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17103 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17104 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17105 THUMB_VARIANT, do_##enc, do_##enc }
17107 #define NCE(mnem, op, nops, ops, enc) \
17108 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17110 #define NCEF(mnem, op, nops, ops, enc) \
17111 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17113 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17114 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17115 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17116 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17118 #define nCE(mnem, op, nops, ops, enc) \
17119 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17121 #define nCEF(mnem, op, nops, ops, enc) \
17122 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17126 static const struct asm_opcode insns[] =
17128 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17129 #define THUMB_VARIANT &arm_ext_v4t
17130 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17131 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17132 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17133 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17134 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17135 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17136 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17137 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17138 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17139 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17140 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17141 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17142 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17143 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17144 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17145 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17147 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17148 for setting PSR flag bits. They are obsolete in V6 and do not
17149 have Thumb equivalents. */
17150 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17151 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17152 CL("tstp", 110f000, 2, (RR, SH), cmp),
17153 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17154 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17155 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17156 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17157 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17158 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17160 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17161 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17162 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17163 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17165 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17166 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17167 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17169 OP_ADDRGLDR),ldst, t_ldst),
17170 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17172 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17173 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17174 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17175 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17176 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17177 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17179 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17180 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17181 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17182 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17185 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17186 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17187 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17189 /* Thumb-compatibility pseudo ops. */
17190 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17191 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17192 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17193 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17194 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17195 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17196 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17197 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17198 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17199 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17200 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17201 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17203 /* These may simplify to neg. */
17204 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17205 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17207 #undef THUMB_VARIANT
17208 #define THUMB_VARIANT & arm_ext_v6
17210 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17212 /* V1 instructions with no Thumb analogue prior to V6T2. */
17213 #undef THUMB_VARIANT
17214 #define THUMB_VARIANT & arm_ext_v6t2
17216 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17217 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17218 CL("teqp", 130f000, 2, (RR, SH), cmp),
17220 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17221 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17222 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17223 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17225 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17226 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17228 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17229 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17231 /* V1 instructions with no Thumb analogue at all. */
17232 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17233 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17235 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17236 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17237 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17238 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17239 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17240 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17241 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17242 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17245 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17246 #undef THUMB_VARIANT
17247 #define THUMB_VARIANT & arm_ext_v4t
17249 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17250 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17252 #undef THUMB_VARIANT
17253 #define THUMB_VARIANT & arm_ext_v6t2
17255 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17256 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17258 /* Generic coprocessor instructions. */
17259 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17260 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17261 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17262 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17263 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17264 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17265 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17268 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17270 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17271 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17274 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17275 #undef THUMB_VARIANT
17276 #define THUMB_VARIANT & arm_ext_msr
17278 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17279 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17282 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17283 #undef THUMB_VARIANT
17284 #define THUMB_VARIANT & arm_ext_v6t2
17286 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17287 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17288 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17289 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17290 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17291 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17292 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17293 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17296 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17297 #undef THUMB_VARIANT
17298 #define THUMB_VARIANT & arm_ext_v4t
17300 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17301 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17302 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17303 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17304 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17305 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17308 #define ARM_VARIANT & arm_ext_v4t_5
17310 /* ARM Architecture 4T. */
17311 /* Note: bx (and blx) are required on V5, even if the processor does
17312 not support Thumb. */
17313 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17316 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17317 #undef THUMB_VARIANT
17318 #define THUMB_VARIANT & arm_ext_v5t
17320 /* Note: blx has 2 variants; the .value coded here is for
17321 BLX(2). Only this variant has conditional execution. */
17322 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17323 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17325 #undef THUMB_VARIANT
17326 #define THUMB_VARIANT & arm_ext_v6t2
17328 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17329 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17330 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17331 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17332 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17333 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17334 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17335 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17338 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17339 #undef THUMB_VARIANT
17340 #define THUMB_VARIANT &arm_ext_v5exp
17342 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17343 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17344 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17345 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17347 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17348 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17350 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17351 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17352 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17353 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17355 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17356 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17357 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17358 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17360 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17361 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17363 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17364 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17365 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17366 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17369 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17370 #undef THUMB_VARIANT
17371 #define THUMB_VARIANT &arm_ext_v6t2
17373 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17374 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17376 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17377 ADDRGLDRS), ldrd, t_ldstd),
17379 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17380 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17383 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17385 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17388 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17389 #undef THUMB_VARIANT
17390 #define THUMB_VARIANT & arm_ext_v6
17392 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17393 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17394 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17395 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17396 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17397 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17398 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17399 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17400 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17401 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17403 #undef THUMB_VARIANT
17404 #define THUMB_VARIANT & arm_ext_v6t2
17406 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17407 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17409 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17410 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17412 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17413 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17415 /* ARM V6 not included in V7M. */
17416 #undef THUMB_VARIANT
17417 #define THUMB_VARIANT & arm_ext_v6_notm
17418 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17419 UF(rfeib, 9900a00, 1, (RRw), rfe),
17420 UF(rfeda, 8100a00, 1, (RRw), rfe),
17421 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17422 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17423 UF(rfefa, 9900a00, 1, (RRw), rfe),
17424 UF(rfeea, 8100a00, 1, (RRw), rfe),
17425 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17426 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17427 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17428 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17429 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17431 /* ARM V6 not included in V7M (eg. integer SIMD). */
17432 #undef THUMB_VARIANT
17433 #define THUMB_VARIANT & arm_ext_v6_dsp
17434 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17435 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17436 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17437 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17438 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17439 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17440 /* Old name for QASX. */
17441 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17442 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17443 /* Old name for QSAX. */
17444 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17445 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17446 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17447 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17448 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17449 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17450 /* Old name for SASX. */
17451 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17452 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17453 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17454 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17455 /* Old name for SHASX. */
17456 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17457 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17458 /* Old name for SHSAX. */
17459 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17460 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17461 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17462 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17463 /* Old name for SSAX. */
17464 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17465 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17466 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17467 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17468 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17469 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17470 /* Old name for UASX. */
17471 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17472 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17473 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17474 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17475 /* Old name for UHASX. */
17476 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17477 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17478 /* Old name for UHSAX. */
17479 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17480 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17481 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17482 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17483 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17484 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17485 /* Old name for UQASX. */
17486 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17487 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17488 /* Old name for UQSAX. */
17489 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17490 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17491 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17492 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17493 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17494 /* Old name for USAX. */
17495 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17496 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17497 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17498 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17499 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17500 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17501 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17502 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17503 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17504 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17505 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17506 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17507 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17508 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17509 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17510 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17511 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17512 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17513 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17514 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17515 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17516 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17517 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17518 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17519 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17520 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17521 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17522 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17523 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17524 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17525 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17526 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17527 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17528 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17531 #define ARM_VARIANT & arm_ext_v6k
17532 #undef THUMB_VARIANT
17533 #define THUMB_VARIANT & arm_ext_v6k
17535 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17536 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17537 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17538 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17540 #undef THUMB_VARIANT
17541 #define THUMB_VARIANT & arm_ext_v6_notm
17542 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17544 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17545 RRnpcb), strexd, t_strexd),
17547 #undef THUMB_VARIANT
17548 #define THUMB_VARIANT & arm_ext_v6t2
17549 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17551 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17553 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17555 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17557 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17560 #define ARM_VARIANT & arm_ext_sec
17561 #undef THUMB_VARIANT
17562 #define THUMB_VARIANT & arm_ext_sec
17564 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17567 #define ARM_VARIANT & arm_ext_virt
17568 #undef THUMB_VARIANT
17569 #define THUMB_VARIANT & arm_ext_virt
17571 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17572 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17575 #define ARM_VARIANT & arm_ext_v6t2
17576 #undef THUMB_VARIANT
17577 #define THUMB_VARIANT & arm_ext_v6t2
17579 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17580 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17581 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17582 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17584 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17585 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17586 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17587 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17589 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17590 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17591 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17592 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17594 /* Thumb-only instructions. */
17596 #define ARM_VARIANT NULL
17597 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17598 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17600 /* ARM does not really have an IT instruction, so always allow it.
17601 The opcode is copied from Thumb in order to allow warnings in
17602 -mimplicit-it=[never | arm] modes. */
17604 #define ARM_VARIANT & arm_ext_v1
17606 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17607 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17608 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17609 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17610 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17611 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17612 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17613 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17614 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17615 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17616 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17617 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17618 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17619 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17620 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17621 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17622 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17623 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17625 /* Thumb2 only instructions. */
17627 #define ARM_VARIANT NULL
17629 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17630 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17631 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17632 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17633 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17634 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17636 /* Hardware division instructions. */
17638 #define ARM_VARIANT & arm_ext_adiv
17639 #undef THUMB_VARIANT
17640 #define THUMB_VARIANT & arm_ext_div
17642 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17643 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17645 /* ARM V6M/V7 instructions. */
17647 #define ARM_VARIANT & arm_ext_barrier
17648 #undef THUMB_VARIANT
17649 #define THUMB_VARIANT & arm_ext_barrier
17651 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17652 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17653 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17655 /* ARM V7 instructions. */
17657 #define ARM_VARIANT & arm_ext_v7
17658 #undef THUMB_VARIANT
17659 #define THUMB_VARIANT & arm_ext_v7
17661 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17662 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17665 #define ARM_VARIANT & arm_ext_mp
17666 #undef THUMB_VARIANT
17667 #define THUMB_VARIANT & arm_ext_mp
17669 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17672 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17674 cCE("wfs", e200110, 1, (RR), rd),
17675 cCE("rfs", e300110, 1, (RR), rd),
17676 cCE("wfc", e400110, 1, (RR), rd),
17677 cCE("rfc", e500110, 1, (RR), rd),
17679 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17680 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17681 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17682 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17684 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17685 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17686 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17687 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17689 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17690 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17691 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17692 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17693 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17694 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17695 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17696 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17697 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17698 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17699 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17700 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17702 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17703 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17704 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17705 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17706 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17707 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17708 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17709 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17710 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17711 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17712 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17713 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17715 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17716 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17717 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17718 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17719 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17720 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17721 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17722 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17723 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17724 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17725 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17726 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17728 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17729 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17730 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17731 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17732 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17733 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17734 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17735 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17736 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17737 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17738 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17739 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17741 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17742 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17743 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17744 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17745 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17746 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17747 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17748 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17749 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17750 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17751 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17752 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17754 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17755 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17756 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17757 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17758 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17759 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17760 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17761 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17762 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17763 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17764 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17765 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17767 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17768 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17769 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17770 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17771 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17772 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17773 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17774 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17775 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17776 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17777 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17778 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17780 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17781 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17782 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17783 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17784 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17785 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17786 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17787 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17788 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17789 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17790 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17791 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17793 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17794 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17795 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17796 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17797 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17798 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17799 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17800 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17801 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17802 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17803 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17804 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17806 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17807 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17808 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17809 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17810 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17811 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17812 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17813 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17814 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17815 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17816 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17817 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17819 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17820 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17821 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17822 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17823 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17824 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17825 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17826 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17827 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17828 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17829 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17830 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17832 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17833 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17834 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17835 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17836 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17837 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17838 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17839 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17840 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17841 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17842 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17843 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17845 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17846 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17847 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17848 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17849 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17850 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17851 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17852 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17853 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17854 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17855 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17856 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17858 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17859 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17860 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17861 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17862 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17863 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17864 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17865 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17866 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17867 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17868 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17869 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17871 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17872 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17873 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17874 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17875 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17876 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17877 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17878 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17879 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17880 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17881 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17882 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17884 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17885 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17886 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17887 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17888 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17889 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17890 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17891 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17892 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17893 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17894 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17895 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17897 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17898 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17899 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17900 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17901 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17902 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17903 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17904 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17905 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17906 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17907 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17908 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17911 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17913 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17917 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17919 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17921 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17924 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17958 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17960 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17962 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17963 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17965 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17971 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17973 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17975 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17976 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17978 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17984 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17986 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17988 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18067 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18068 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18069 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18071 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18072 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18073 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18074 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18075 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18076 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18077 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18078 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18079 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18080 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18081 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18082 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18084 /* The implementation of the FIX instruction is broken on some
18085 assemblers, in that it accepts a precision specifier as well as a
18086 rounding specifier, despite the fact that this is meaningless.
18087 To be more compatible, we accept it as well, though of course it
18088 does not set any bits. */
18089 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18090 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18091 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18092 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18093 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18094 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18095 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18096 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18097 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18098 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18099 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18100 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18101 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18103 /* Instructions that were new with the real FPA, call them V2. */
18105 #define ARM_VARIANT & fpu_fpa_ext_v2
18107 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18108 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18109 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18110 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18111 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18112 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18115 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18117 /* Moves and type conversions. */
18118 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18119 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18120 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18121 cCE("fmstat", ef1fa10, 0, (), noargs),
18122 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18123 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18124 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18125 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18126 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18127 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18128 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18129 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18130 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18131 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18133 /* Memory operations. */
18134 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18135 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18136 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18137 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18138 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18139 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18140 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18141 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18142 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18143 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18144 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18145 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18146 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18147 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18148 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18149 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18150 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18151 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18153 /* Monadic operations. */
18154 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18155 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18156 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18158 /* Dyadic operations. */
18159 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18160 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18161 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18162 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18163 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18164 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18165 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18166 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18167 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18170 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18171 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18172 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18173 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18175 /* Double precision load/store are still present on single precision
18176 implementations. */
18177 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18178 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18179 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18180 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18181 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18182 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18183 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18184 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18185 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18186 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18189 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18191 /* Moves and type conversions. */
18192 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18193 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18194 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18195 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18196 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18197 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18198 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18199 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18200 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18201 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18202 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18203 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18204 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18206 /* Monadic operations. */
18207 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18208 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18209 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18211 /* Dyadic operations. */
18212 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18213 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18214 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18215 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18216 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18217 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18218 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18219 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18220 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18223 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18224 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18225 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18226 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18229 #define ARM_VARIANT & fpu_vfp_ext_v2
18231 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18232 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18233 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18234 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18236 /* Instructions which may belong to either the Neon or VFP instruction sets.
18237 Individual encoder functions perform additional architecture checks. */
18239 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18240 #undef THUMB_VARIANT
18241 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18243 /* These mnemonics are unique to VFP. */
18244 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18245 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18246 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18247 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18248 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18249 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18250 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18251 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18252 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18253 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18255 /* Mnemonics shared by Neon and VFP. */
18256 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18257 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18258 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18260 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18261 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18263 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18264 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18266 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18267 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18268 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18269 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18270 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18271 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18272 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18273 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18275 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18276 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18277 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18278 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18281 /* NOTE: All VMOV encoding is special-cased! */
18282 NCE(vmov, 0, 1, (VMOV), neon_mov),
18283 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18285 #undef THUMB_VARIANT
18286 #define THUMB_VARIANT & fpu_neon_ext_v1
18288 #define ARM_VARIANT & fpu_neon_ext_v1
18290 /* Data processing with three registers of the same length. */
18291 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18292 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18293 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18294 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18295 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18296 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18297 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18298 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18299 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18300 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18301 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18302 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18303 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18304 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18305 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18306 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18307 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18308 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18309 /* If not immediate, fall back to neon_dyadic_i64_su.
18310 shl_imm should accept I8 I16 I32 I64,
18311 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18312 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18313 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18314 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18315 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18316 /* Logic ops, types optional & ignored. */
18317 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18318 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18319 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18320 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18321 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18322 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18323 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18324 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18325 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18326 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18327 /* Bitfield ops, untyped. */
18328 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18329 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18330 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18331 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18332 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18333 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18334 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18335 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18336 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18337 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18338 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18339 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18340 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18341 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18342 back to neon_dyadic_if_su. */
18343 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18344 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18345 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18346 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18347 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18348 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18349 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18350 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18351 /* Comparison. Type I8 I16 I32 F32. */
18352 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18353 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18354 /* As above, D registers only. */
18355 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18356 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18357 /* Int and float variants, signedness unimportant. */
18358 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18359 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18360 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18361 /* Add/sub take types I8 I16 I32 I64 F32. */
18362 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18363 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18364 /* vtst takes sizes 8, 16, 32. */
18365 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18366 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18367 /* VMUL takes I8 I16 I32 F32 P8. */
18368 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18369 /* VQD{R}MULH takes S16 S32. */
18370 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18371 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18372 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18373 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18374 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18375 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18376 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18377 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18378 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18379 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18380 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18381 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18382 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18383 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18384 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18385 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18387 /* Two address, int/float. Types S8 S16 S32 F32. */
18388 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18389 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18391 /* Data processing with two registers and a shift amount. */
18392 /* Right shifts, and variants with rounding.
18393 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18394 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18395 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18396 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18397 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18398 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18399 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18400 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18401 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18402 /* Shift and insert. Sizes accepted 8 16 32 64. */
18403 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18404 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18405 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18406 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18407 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18408 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18409 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18410 /* Right shift immediate, saturating & narrowing, with rounding variants.
18411 Types accepted S16 S32 S64 U16 U32 U64. */
18412 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18413 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18414 /* As above, unsigned. Types accepted S16 S32 S64. */
18415 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18416 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18417 /* Right shift narrowing. Types accepted I16 I32 I64. */
18418 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18419 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18420 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18421 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18422 /* CVT with optional immediate for fixed-point variant. */
18423 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18425 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18426 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18428 /* Data processing, three registers of different lengths. */
18429 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18430 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18431 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18432 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18433 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18434 /* If not scalar, fall back to neon_dyadic_long.
18435 Vector types as above, scalar types S16 S32 U16 U32. */
18436 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18437 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18438 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18439 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18440 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18441 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18442 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18443 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18444 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18445 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18446 /* Saturating doubling multiplies. Types S16 S32. */
18447 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18448 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18449 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18450 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18451 S16 S32 U16 U32. */
18452 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18454 /* Extract. Size 8. */
18455 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18456 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18458 /* Two registers, miscellaneous. */
18459 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18460 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18461 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18462 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18463 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18464 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18465 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18466 /* Vector replicate. Sizes 8 16 32. */
18467 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18468 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18469 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18470 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18471 /* VMOVN. Types I16 I32 I64. */
18472 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18473 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18474 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18475 /* VQMOVUN. Types S16 S32 S64. */
18476 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18477 /* VZIP / VUZP. Sizes 8 16 32. */
18478 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18479 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18480 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18481 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18482 /* VQABS / VQNEG. Types S8 S16 S32. */
18483 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18484 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18485 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18486 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18487 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18488 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18489 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18490 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18491 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18492 /* Reciprocal estimates. Types U32 F32. */
18493 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18494 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18495 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18496 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18497 /* VCLS. Types S8 S16 S32. */
18498 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18499 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18500 /* VCLZ. Types I8 I16 I32. */
18501 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18502 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18503 /* VCNT. Size 8. */
18504 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18505 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18506 /* Two address, untyped. */
18507 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18508 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18509 /* VTRN. Sizes 8 16 32. */
18510 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18511 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18513 /* Table lookup. Size 8. */
18514 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18515 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18517 #undef THUMB_VARIANT
18518 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18520 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18522 /* Neon element/structure load/store. */
18523 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18524 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18525 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18526 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18527 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18528 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18529 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18530 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18532 #undef THUMB_VARIANT
18533 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18535 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18536 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18537 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18538 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18539 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18540 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18541 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18542 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18543 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18544 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18546 #undef THUMB_VARIANT
18547 #define THUMB_VARIANT & fpu_vfp_ext_v3
18549 #define ARM_VARIANT & fpu_vfp_ext_v3
18551 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18552 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18553 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18554 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18555 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18556 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18557 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18558 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18559 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18562 #define ARM_VARIANT &fpu_vfp_ext_fma
18563 #undef THUMB_VARIANT
18564 #define THUMB_VARIANT &fpu_vfp_ext_fma
18565 /* Mnemonics shared by Neon and VFP. These are included in the
18566 VFP FMA variant; NEON and VFP FMA always includes the NEON
18567 FMA instructions. */
18568 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18569 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18570 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18571 the v form should always be used. */
18572 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18573 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18574 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18575 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18576 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18577 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18579 #undef THUMB_VARIANT
18581 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18583 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18584 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18585 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18586 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18587 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18588 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18589 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18590 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18593 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18595 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18596 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18597 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18598 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18599 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18600 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18601 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18602 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18603 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18604 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18605 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18606 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18607 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18608 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18609 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18610 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18611 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18612 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18613 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18614 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18615 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18616 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18617 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18618 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18619 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18620 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18621 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18622 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18623 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18624 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18625 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18626 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18627 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18628 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18629 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18630 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18631 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18632 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18633 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18634 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18635 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18636 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18637 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18638 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18639 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18640 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18641 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18642 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18643 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18644 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18645 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18646 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18647 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18648 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18649 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18650 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18651 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18652 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18653 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18654 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18655 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18656 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18657 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18658 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18659 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18662 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18663 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18664 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18665 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18684 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18690 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18691 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18692 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18693 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18696 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18697 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18698 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18699 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18700 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18701 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18703 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18704 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18706 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18707 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18708 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18709 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18710 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18711 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18712 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18713 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18714 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18715 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18716 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18717 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18718 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18719 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18720 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18721 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18722 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18723 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18724 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18725 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18726 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18727 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18728 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18729 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18733 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18734 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18735 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18736 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18737 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18738 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18739 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18740 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18741 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18742 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18743 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18744 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18745 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18746 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18747 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18748 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18749 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18750 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18751 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18752 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18753 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18754 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18755 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18759 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18761 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18762 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18763 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18764 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18765 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18766 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18767 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18775 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18779 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18782 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18786 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18787 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18788 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18789 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18790 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18791 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18792 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18793 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18794 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18806 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18809 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18810 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18822 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18823 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18824 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18825 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18826 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18827 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18828 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18829 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18830 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18831 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18832 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18833 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18834 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18835 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18836 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18837 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18838 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18839 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18840 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18841 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18842 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18843 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18844 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18845 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18846 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18847 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18848 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18849 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18850 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18851 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18852 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18853 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18854 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18855 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18856 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18857 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18858 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18859 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18860 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18861 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18862 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18863 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18864 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18865 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18866 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18867 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18868 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18869 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18870 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18871 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18872 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18873 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18874 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18875 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18876 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18877 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18878 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18879 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18880 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18881 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18882 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18883 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18884 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18885 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18886 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18887 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18888 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18889 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18890 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18891 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18892 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18893 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18894 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18895 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18896 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18897 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18900 #undef THUMB_VARIANT
18927 /* MD interface: bits in the object file. */
18929 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18930 for use in the a.out file, and stores them in the array pointed to by buf.
18931 This knows about the endian-ness of the target machine and does
18932 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18933 2 (short) and 4 (long) Floating numbers are put out as a series of
18934 LITTLENUMS (shorts, here at least). */
18937 md_number_to_chars (char * buf, valueT val, int n)
18939 if (target_big_endian)
18940 number_to_chars_bigendian (buf, val, n);
18942 number_to_chars_littleendian (buf, val, n);
18946 md_chars_to_number (char * buf, int n)
18949 unsigned char * where = (unsigned char *) buf;
18951 if (target_big_endian)
18956 result |= (*where++ & 255);
18964 result |= (where[n] & 255);
18971 /* MD interface: Sections. */
18973 /* Estimate the size of a frag before relaxing. Assume everything fits in
18977 md_estimate_size_before_relax (fragS * fragp,
18978 segT segtype ATTRIBUTE_UNUSED)
18984 /* Convert a machine dependent frag. */
18987 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18989 unsigned long insn;
18990 unsigned long old_op;
18998 buf = fragp->fr_literal + fragp->fr_fix;
19000 old_op = bfd_get_16(abfd, buf);
19001 if (fragp->fr_symbol)
19003 exp.X_op = O_symbol;
19004 exp.X_add_symbol = fragp->fr_symbol;
19008 exp.X_op = O_constant;
19010 exp.X_add_number = fragp->fr_offset;
19011 opcode = fragp->fr_subtype;
19014 case T_MNEM_ldr_pc:
19015 case T_MNEM_ldr_pc2:
19016 case T_MNEM_ldr_sp:
19017 case T_MNEM_str_sp:
19024 if (fragp->fr_var == 4)
19026 insn = THUMB_OP32 (opcode);
19027 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19029 insn |= (old_op & 0x700) << 4;
19033 insn |= (old_op & 7) << 12;
19034 insn |= (old_op & 0x38) << 13;
19036 insn |= 0x00000c00;
19037 put_thumb32_insn (buf, insn);
19038 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19042 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19044 pc_rel = (opcode == T_MNEM_ldr_pc2);
19047 if (fragp->fr_var == 4)
19049 insn = THUMB_OP32 (opcode);
19050 insn |= (old_op & 0xf0) << 4;
19051 put_thumb32_insn (buf, insn);
19052 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19056 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19057 exp.X_add_number -= 4;
19065 if (fragp->fr_var == 4)
19067 int r0off = (opcode == T_MNEM_mov
19068 || opcode == T_MNEM_movs) ? 0 : 8;
19069 insn = THUMB_OP32 (opcode);
19070 insn = (insn & 0xe1ffffff) | 0x10000000;
19071 insn |= (old_op & 0x700) << r0off;
19072 put_thumb32_insn (buf, insn);
19073 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19077 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19082 if (fragp->fr_var == 4)
19084 insn = THUMB_OP32(opcode);
19085 put_thumb32_insn (buf, insn);
19086 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19089 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19093 if (fragp->fr_var == 4)
19095 insn = THUMB_OP32(opcode);
19096 insn |= (old_op & 0xf00) << 14;
19097 put_thumb32_insn (buf, insn);
19098 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19101 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19104 case T_MNEM_add_sp:
19105 case T_MNEM_add_pc:
19106 case T_MNEM_inc_sp:
19107 case T_MNEM_dec_sp:
19108 if (fragp->fr_var == 4)
19110 /* ??? Choose between add and addw. */
19111 insn = THUMB_OP32 (opcode);
19112 insn |= (old_op & 0xf0) << 4;
19113 put_thumb32_insn (buf, insn);
19114 if (opcode == T_MNEM_add_pc)
19115 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19117 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19120 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19128 if (fragp->fr_var == 4)
19130 insn = THUMB_OP32 (opcode);
19131 insn |= (old_op & 0xf0) << 4;
19132 insn |= (old_op & 0xf) << 16;
19133 put_thumb32_insn (buf, insn);
19134 if (insn & (1 << 20))
19135 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19137 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19140 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19146 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19147 (enum bfd_reloc_code_real) reloc_type);
19148 fixp->fx_file = fragp->fr_file;
19149 fixp->fx_line = fragp->fr_line;
19150 fragp->fr_fix += fragp->fr_var;
19153 /* Return the size of a relaxable immediate operand instruction.
19154 SHIFT and SIZE specify the form of the allowable immediate. */
19156 relax_immediate (fragS *fragp, int size, int shift)
19162 /* ??? Should be able to do better than this. */
19163 if (fragp->fr_symbol)
19166 low = (1 << shift) - 1;
19167 mask = (1 << (shift + size)) - (1 << shift);
19168 offset = fragp->fr_offset;
19169 /* Force misaligned offsets to 32-bit variant. */
19172 if (offset & ~mask)
19177 /* Get the address of a symbol during relaxation. */
19179 relaxed_symbol_addr (fragS *fragp, long stretch)
19185 sym = fragp->fr_symbol;
19186 sym_frag = symbol_get_frag (sym);
19187 know (S_GET_SEGMENT (sym) != absolute_section
19188 || sym_frag == &zero_address_frag);
19189 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19191 /* If frag has yet to be reached on this pass, assume it will
19192 move by STRETCH just as we did. If this is not so, it will
19193 be because some frag between grows, and that will force
19197 && sym_frag->relax_marker != fragp->relax_marker)
19201 /* Adjust stretch for any alignment frag. Note that if have
19202 been expanding the earlier code, the symbol may be
19203 defined in what appears to be an earlier frag. FIXME:
19204 This doesn't handle the fr_subtype field, which specifies
19205 a maximum number of bytes to skip when doing an
19207 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19209 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19212 stretch = - ((- stretch)
19213 & ~ ((1 << (int) f->fr_offset) - 1));
19215 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19227 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19230 relax_adr (fragS *fragp, asection *sec, long stretch)
19235 /* Assume worst case for symbols not known to be in the same section. */
19236 if (fragp->fr_symbol == NULL
19237 || !S_IS_DEFINED (fragp->fr_symbol)
19238 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19239 || S_IS_WEAK (fragp->fr_symbol))
19242 val = relaxed_symbol_addr (fragp, stretch);
19243 addr = fragp->fr_address + fragp->fr_fix;
19244 addr = (addr + 4) & ~3;
19245 /* Force misaligned targets to 32-bit variant. */
19249 if (val < 0 || val > 1020)
19254 /* Return the size of a relaxable add/sub immediate instruction. */
19256 relax_addsub (fragS *fragp, asection *sec)
19261 buf = fragp->fr_literal + fragp->fr_fix;
19262 op = bfd_get_16(sec->owner, buf);
19263 if ((op & 0xf) == ((op >> 4) & 0xf))
19264 return relax_immediate (fragp, 8, 0);
19266 return relax_immediate (fragp, 3, 0);
19270 /* Return the size of a relaxable branch instruction. BITS is the
19271 size of the offset field in the narrow instruction. */
19274 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19280 /* Assume worst case for symbols not known to be in the same section. */
19281 if (!S_IS_DEFINED (fragp->fr_symbol)
19282 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19283 || S_IS_WEAK (fragp->fr_symbol))
19287 if (S_IS_DEFINED (fragp->fr_symbol)
19288 && ARM_IS_FUNC (fragp->fr_symbol))
19291 /* PR 12532. Global symbols with default visibility might
19292 be preempted, so do not relax relocations to them. */
19293 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19294 && (! S_IS_LOCAL (fragp->fr_symbol)))
19298 val = relaxed_symbol_addr (fragp, stretch);
19299 addr = fragp->fr_address + fragp->fr_fix + 4;
19302 /* Offset is a signed value *2 */
19304 if (val >= limit || val < -limit)
19310 /* Relax a machine dependent frag. This returns the amount by which
19311 the current size of the frag should change. */
19314 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19319 oldsize = fragp->fr_var;
19320 switch (fragp->fr_subtype)
19322 case T_MNEM_ldr_pc2:
19323 newsize = relax_adr (fragp, sec, stretch);
19325 case T_MNEM_ldr_pc:
19326 case T_MNEM_ldr_sp:
19327 case T_MNEM_str_sp:
19328 newsize = relax_immediate (fragp, 8, 2);
19332 newsize = relax_immediate (fragp, 5, 2);
19336 newsize = relax_immediate (fragp, 5, 1);
19340 newsize = relax_immediate (fragp, 5, 0);
19343 newsize = relax_adr (fragp, sec, stretch);
19349 newsize = relax_immediate (fragp, 8, 0);
19352 newsize = relax_branch (fragp, sec, 11, stretch);
19355 newsize = relax_branch (fragp, sec, 8, stretch);
19357 case T_MNEM_add_sp:
19358 case T_MNEM_add_pc:
19359 newsize = relax_immediate (fragp, 8, 2);
19361 case T_MNEM_inc_sp:
19362 case T_MNEM_dec_sp:
19363 newsize = relax_immediate (fragp, 7, 2);
19369 newsize = relax_addsub (fragp, sec);
19375 fragp->fr_var = newsize;
19376 /* Freeze wide instructions that are at or before the same location as
19377 in the previous pass. This avoids infinite loops.
19378 Don't freeze them unconditionally because targets may be artificially
19379 misaligned by the expansion of preceding frags. */
19380 if (stretch <= 0 && newsize > 2)
19382 md_convert_frag (sec->owner, sec, fragp);
19386 return newsize - oldsize;
19389 /* Round up a section size to the appropriate boundary. */
19392 md_section_align (segT segment ATTRIBUTE_UNUSED,
19395 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19396 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19398 /* For a.out, force the section size to be aligned. If we don't do
19399 this, BFD will align it for us, but it will not write out the
19400 final bytes of the section. This may be a bug in BFD, but it is
19401 easier to fix it here since that is how the other a.out targets
19405 align = bfd_get_section_alignment (stdoutput, segment);
19406 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19413 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19414 of an rs_align_code fragment. */
19417 arm_handle_align (fragS * fragP)
19419 static char const arm_noop[2][2][4] =
19422 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19423 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19426 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19427 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19430 static char const thumb_noop[2][2][2] =
19433 {0xc0, 0x46}, /* LE */
19434 {0x46, 0xc0}, /* BE */
19437 {0x00, 0xbf}, /* LE */
19438 {0xbf, 0x00} /* BE */
19441 static char const wide_thumb_noop[2][4] =
19442 { /* Wide Thumb-2 */
19443 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19444 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19447 unsigned bytes, fix, noop_size;
19450 const char *narrow_noop = NULL;
19455 if (fragP->fr_type != rs_align_code)
19458 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19459 p = fragP->fr_literal + fragP->fr_fix;
19462 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19463 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19465 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19467 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19469 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19471 narrow_noop = thumb_noop[1][target_big_endian];
19472 noop = wide_thumb_noop[target_big_endian];
19475 noop = thumb_noop[0][target_big_endian];
19483 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19484 [target_big_endian];
19491 fragP->fr_var = noop_size;
19493 if (bytes & (noop_size - 1))
19495 fix = bytes & (noop_size - 1);
19497 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19499 memset (p, 0, fix);
19506 if (bytes & noop_size)
19508 /* Insert a narrow noop. */
19509 memcpy (p, narrow_noop, noop_size);
19511 bytes -= noop_size;
19515 /* Use wide noops for the remainder */
19519 while (bytes >= noop_size)
19521 memcpy (p, noop, noop_size);
19523 bytes -= noop_size;
19527 fragP->fr_fix += fix;
19530 /* Called from md_do_align. Used to create an alignment
19531 frag in a code section. */
19534 arm_frag_align_code (int n, int max)
19538 /* We assume that there will never be a requirement
19539 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19540 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19545 _("alignments greater than %d bytes not supported in .text sections."),
19546 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19547 as_fatal ("%s", err_msg);
19550 p = frag_var (rs_align_code,
19551 MAX_MEM_FOR_RS_ALIGN_CODE,
19553 (relax_substateT) max,
19560 /* Perform target specific initialisation of a frag.
19561 Note - despite the name this initialisation is not done when the frag
19562 is created, but only when its type is assigned. A frag can be created
19563 and used a long time before its type is set, so beware of assuming that
19564 this initialisationis performed first. */
19568 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19570 /* Record whether this frag is in an ARM or a THUMB area. */
19571 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19574 #else /* OBJ_ELF is defined. */
19576 arm_init_frag (fragS * fragP, int max_chars)
19578 /* If the current ARM vs THUMB mode has not already
19579 been recorded into this frag then do so now. */
19580 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19582 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19584 /* Record a mapping symbol for alignment frags. We will delete this
19585 later if the alignment ends up empty. */
19586 switch (fragP->fr_type)
19589 case rs_align_test:
19591 mapping_state_2 (MAP_DATA, max_chars);
19593 case rs_align_code:
19594 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19602 /* When we change sections we need to issue a new mapping symbol. */
19605 arm_elf_change_section (void)
19607 /* Link an unlinked unwind index table section to the .text section. */
19608 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19609 && elf_linked_to_section (now_seg) == NULL)
19610 elf_linked_to_section (now_seg) = text_section;
19614 arm_elf_section_type (const char * str, size_t len)
19616 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19617 return SHT_ARM_EXIDX;
19622 /* Code to deal with unwinding tables. */
19624 static void add_unwind_adjustsp (offsetT);
19626 /* Generate any deferred unwind frame offset. */
19629 flush_pending_unwind (void)
19633 offset = unwind.pending_offset;
19634 unwind.pending_offset = 0;
19636 add_unwind_adjustsp (offset);
19639 /* Add an opcode to this list for this function. Two-byte opcodes should
19640 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19644 add_unwind_opcode (valueT op, int length)
19646 /* Add any deferred stack adjustment. */
19647 if (unwind.pending_offset)
19648 flush_pending_unwind ();
19650 unwind.sp_restored = 0;
19652 if (unwind.opcode_count + length > unwind.opcode_alloc)
19654 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19655 if (unwind.opcodes)
19656 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19657 unwind.opcode_alloc);
19659 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19664 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19666 unwind.opcode_count++;
19670 /* Add unwind opcodes to adjust the stack pointer. */
19673 add_unwind_adjustsp (offsetT offset)
19677 if (offset > 0x200)
19679 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19684 /* Long form: 0xb2, uleb128. */
19685 /* This might not fit in a word so add the individual bytes,
19686 remembering the list is built in reverse order. */
19687 o = (valueT) ((offset - 0x204) >> 2);
19689 add_unwind_opcode (0, 1);
19691 /* Calculate the uleb128 encoding of the offset. */
19695 bytes[n] = o & 0x7f;
19701 /* Add the insn. */
19703 add_unwind_opcode (bytes[n - 1], 1);
19704 add_unwind_opcode (0xb2, 1);
19706 else if (offset > 0x100)
19708 /* Two short opcodes. */
19709 add_unwind_opcode (0x3f, 1);
19710 op = (offset - 0x104) >> 2;
19711 add_unwind_opcode (op, 1);
19713 else if (offset > 0)
19715 /* Short opcode. */
19716 op = (offset - 4) >> 2;
19717 add_unwind_opcode (op, 1);
19719 else if (offset < 0)
19722 while (offset > 0x100)
19724 add_unwind_opcode (0x7f, 1);
19727 op = ((offset - 4) >> 2) | 0x40;
19728 add_unwind_opcode (op, 1);
19732 /* Finish the list of unwind opcodes for this function. */
19734 finish_unwind_opcodes (void)
19738 if (unwind.fp_used)
19740 /* Adjust sp as necessary. */
19741 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19742 flush_pending_unwind ();
19744 /* After restoring sp from the frame pointer. */
19745 op = 0x90 | unwind.fp_reg;
19746 add_unwind_opcode (op, 1);
19749 flush_pending_unwind ();
19753 /* Start an exception table entry. If idx is nonzero this is an index table
19757 start_unwind_section (const segT text_seg, int idx)
19759 const char * text_name;
19760 const char * prefix;
19761 const char * prefix_once;
19762 const char * group_name;
19766 size_t sec_name_len;
19773 prefix = ELF_STRING_ARM_unwind;
19774 prefix_once = ELF_STRING_ARM_unwind_once;
19775 type = SHT_ARM_EXIDX;
19779 prefix = ELF_STRING_ARM_unwind_info;
19780 prefix_once = ELF_STRING_ARM_unwind_info_once;
19781 type = SHT_PROGBITS;
19784 text_name = segment_name (text_seg);
19785 if (streq (text_name, ".text"))
19788 if (strncmp (text_name, ".gnu.linkonce.t.",
19789 strlen (".gnu.linkonce.t.")) == 0)
19791 prefix = prefix_once;
19792 text_name += strlen (".gnu.linkonce.t.");
19795 prefix_len = strlen (prefix);
19796 text_len = strlen (text_name);
19797 sec_name_len = prefix_len + text_len;
19798 sec_name = (char *) xmalloc (sec_name_len + 1);
19799 memcpy (sec_name, prefix, prefix_len);
19800 memcpy (sec_name + prefix_len, text_name, text_len);
19801 sec_name[prefix_len + text_len] = '\0';
19807 /* Handle COMDAT group. */
19808 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19810 group_name = elf_group_name (text_seg);
19811 if (group_name == NULL)
19813 as_bad (_("Group section `%s' has no group signature"),
19814 segment_name (text_seg));
19815 ignore_rest_of_line ();
19818 flags |= SHF_GROUP;
19822 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19824 /* Set the section link for index tables. */
19826 elf_linked_to_section (now_seg) = text_seg;
19830 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19831 personality routine data. Returns zero, or the index table value for
19832 and inline entry. */
19835 create_unwind_entry (int have_data)
19840 /* The current word of data. */
19842 /* The number of bytes left in this word. */
19845 finish_unwind_opcodes ();
19847 /* Remember the current text section. */
19848 unwind.saved_seg = now_seg;
19849 unwind.saved_subseg = now_subseg;
19851 start_unwind_section (now_seg, 0);
19853 if (unwind.personality_routine == NULL)
19855 if (unwind.personality_index == -2)
19858 as_bad (_("handlerdata in cantunwind frame"));
19859 return 1; /* EXIDX_CANTUNWIND. */
19862 /* Use a default personality routine if none is specified. */
19863 if (unwind.personality_index == -1)
19865 if (unwind.opcode_count > 3)
19866 unwind.personality_index = 1;
19868 unwind.personality_index = 0;
19871 /* Space for the personality routine entry. */
19872 if (unwind.personality_index == 0)
19874 if (unwind.opcode_count > 3)
19875 as_bad (_("too many unwind opcodes for personality routine 0"));
19879 /* All the data is inline in the index table. */
19882 while (unwind.opcode_count > 0)
19884 unwind.opcode_count--;
19885 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19889 /* Pad with "finish" opcodes. */
19891 data = (data << 8) | 0xb0;
19898 /* We get two opcodes "free" in the first word. */
19899 size = unwind.opcode_count - 2;
19902 /* An extra byte is required for the opcode count. */
19903 size = unwind.opcode_count + 1;
19905 size = (size + 3) >> 2;
19907 as_bad (_("too many unwind opcodes"));
19909 frag_align (2, 0, 0);
19910 record_alignment (now_seg, 2);
19911 unwind.table_entry = expr_build_dot ();
19913 /* Allocate the table entry. */
19914 ptr = frag_more ((size << 2) + 4);
19915 where = frag_now_fix () - ((size << 2) + 4);
19917 switch (unwind.personality_index)
19920 /* ??? Should this be a PLT generating relocation? */
19921 /* Custom personality routine. */
19922 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19923 BFD_RELOC_ARM_PREL31);
19928 /* Set the first byte to the number of additional words. */
19933 /* ABI defined personality routines. */
19935 /* Three opcodes bytes are packed into the first word. */
19942 /* The size and first two opcode bytes go in the first word. */
19943 data = ((0x80 + unwind.personality_index) << 8) | size;
19948 /* Should never happen. */
19952 /* Pack the opcodes into words (MSB first), reversing the list at the same
19954 while (unwind.opcode_count > 0)
19958 md_number_to_chars (ptr, data, 4);
19963 unwind.opcode_count--;
19965 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19968 /* Finish off the last word. */
19971 /* Pad with "finish" opcodes. */
19973 data = (data << 8) | 0xb0;
19975 md_number_to_chars (ptr, data, 4);
19980 /* Add an empty descriptor if there is no user-specified data. */
19981 ptr = frag_more (4);
19982 md_number_to_chars (ptr, 0, 4);
19989 /* Initialize the DWARF-2 unwind information for this procedure. */
19992 tc_arm_frame_initial_instructions (void)
19994 cfi_add_CFA_def_cfa (REG_SP, 0);
19996 #endif /* OBJ_ELF */
19998 /* Convert REGNAME to a DWARF-2 register number. */
20001 tc_arm_regname_to_dw2regnum (char *regname)
20003 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20013 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20017 exp.X_op = O_secrel;
20018 exp.X_add_symbol = symbol;
20019 exp.X_add_number = 0;
20020 emit_expr (&exp, size);
20024 /* MD interface: Symbol and relocation handling. */
20026 /* Return the address within the segment that a PC-relative fixup is
20027 relative to. For ARM, PC-relative fixups applied to instructions
20028 are generally relative to the location of the fixup plus 8 bytes.
20029 Thumb branches are offset by 4, and Thumb loads relative to PC
20030 require special handling. */
20033 md_pcrel_from_section (fixS * fixP, segT seg)
20035 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20037 /* If this is pc-relative and we are going to emit a relocation
20038 then we just want to put out any pipeline compensation that the linker
20039 will need. Otherwise we want to use the calculated base.
20040 For WinCE we skip the bias for externals as well, since this
20041 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20043 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20044 || (arm_force_relocation (fixP)
20046 && !S_IS_EXTERNAL (fixP->fx_addsy)
20052 switch (fixP->fx_r_type)
20054 /* PC relative addressing on the Thumb is slightly odd as the
20055 bottom two bits of the PC are forced to zero for the
20056 calculation. This happens *after* application of the
20057 pipeline offset. However, Thumb adrl already adjusts for
20058 this, so we need not do it again. */
20059 case BFD_RELOC_ARM_THUMB_ADD:
20062 case BFD_RELOC_ARM_THUMB_OFFSET:
20063 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20064 case BFD_RELOC_ARM_T32_ADD_PC12:
20065 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20066 return (base + 4) & ~3;
20068 /* Thumb branches are simply offset by +4. */
20069 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20070 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20071 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20072 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20073 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20076 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20078 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20079 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20080 && ARM_IS_FUNC (fixP->fx_addsy)
20081 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20082 base = fixP->fx_where + fixP->fx_frag->fr_address;
20085 /* BLX is like branches above, but forces the low two bits of PC to
20087 case BFD_RELOC_THUMB_PCREL_BLX:
20089 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20090 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20091 && THUMB_IS_FUNC (fixP->fx_addsy)
20092 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20093 base = fixP->fx_where + fixP->fx_frag->fr_address;
20094 return (base + 4) & ~3;
20096 /* ARM mode branches are offset by +8. However, the Windows CE
20097 loader expects the relocation not to take this into account. */
20098 case BFD_RELOC_ARM_PCREL_BLX:
20100 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20101 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20102 && ARM_IS_FUNC (fixP->fx_addsy)
20103 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20104 base = fixP->fx_where + fixP->fx_frag->fr_address;
20107 case BFD_RELOC_ARM_PCREL_CALL:
20109 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20110 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20111 && THUMB_IS_FUNC (fixP->fx_addsy)
20112 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20113 base = fixP->fx_where + fixP->fx_frag->fr_address;
20116 case BFD_RELOC_ARM_PCREL_BRANCH:
20117 case BFD_RELOC_ARM_PCREL_JUMP:
20118 case BFD_RELOC_ARM_PLT32:
20120 /* When handling fixups immediately, because we have already
20121 discovered the value of a symbol, or the address of the frag involved
20122 we must account for the offset by +8, as the OS loader will never see the reloc.
20123 see fixup_segment() in write.c
20124 The S_IS_EXTERNAL test handles the case of global symbols.
20125 Those need the calculated base, not just the pipe compensation the linker will need. */
20127 && fixP->fx_addsy != NULL
20128 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20129 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20137 /* ARM mode loads relative to PC are also offset by +8. Unlike
20138 branches, the Windows CE loader *does* expect the relocation
20139 to take this into account. */
20140 case BFD_RELOC_ARM_OFFSET_IMM:
20141 case BFD_RELOC_ARM_OFFSET_IMM8:
20142 case BFD_RELOC_ARM_HWLITERAL:
20143 case BFD_RELOC_ARM_LITERAL:
20144 case BFD_RELOC_ARM_CP_OFF_IMM:
20148 /* Other PC-relative relocations are un-offset. */
20154 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20155 Otherwise we have no need to default values of symbols. */
20158 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20161 if (name[0] == '_' && name[1] == 'G'
20162 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20166 if (symbol_find (name))
20167 as_bad (_("GOT already in the symbol table"));
20169 GOT_symbol = symbol_new (name, undefined_section,
20170 (valueT) 0, & zero_address_frag);
20180 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20181 computed as two separate immediate values, added together. We
20182 already know that this value cannot be computed by just one ARM
20185 static unsigned int
20186 validate_immediate_twopart (unsigned int val,
20187 unsigned int * highpart)
20192 for (i = 0; i < 32; i += 2)
20193 if (((a = rotate_left (val, i)) & 0xff) != 0)
20199 * highpart = (a >> 8) | ((i + 24) << 7);
20201 else if (a & 0xff0000)
20203 if (a & 0xff000000)
20205 * highpart = (a >> 16) | ((i + 16) << 7);
20209 gas_assert (a & 0xff000000);
20210 * highpart = (a >> 24) | ((i + 8) << 7);
20213 return (a & 0xff) | (i << 7);
20220 validate_offset_imm (unsigned int val, int hwse)
20222 if ((hwse && val > 255) || val > 4095)
20227 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20228 negative immediate constant by altering the instruction. A bit of
20233 by inverting the second operand, and
20236 by negating the second operand. */
20239 negate_data_op (unsigned long * instruction,
20240 unsigned long value)
20243 unsigned long negated, inverted;
20245 negated = encode_arm_immediate (-value);
20246 inverted = encode_arm_immediate (~value);
20248 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20251 /* First negates. */
20252 case OPCODE_SUB: /* ADD <-> SUB */
20253 new_inst = OPCODE_ADD;
20258 new_inst = OPCODE_SUB;
20262 case OPCODE_CMP: /* CMP <-> CMN */
20263 new_inst = OPCODE_CMN;
20268 new_inst = OPCODE_CMP;
20272 /* Now Inverted ops. */
20273 case OPCODE_MOV: /* MOV <-> MVN */
20274 new_inst = OPCODE_MVN;
20279 new_inst = OPCODE_MOV;
20283 case OPCODE_AND: /* AND <-> BIC */
20284 new_inst = OPCODE_BIC;
20289 new_inst = OPCODE_AND;
20293 case OPCODE_ADC: /* ADC <-> SBC */
20294 new_inst = OPCODE_SBC;
20299 new_inst = OPCODE_ADC;
20303 /* We cannot do anything. */
20308 if (value == (unsigned) FAIL)
20311 *instruction &= OPCODE_MASK;
20312 *instruction |= new_inst << DATA_OP_SHIFT;
20316 /* Like negate_data_op, but for Thumb-2. */
20318 static unsigned int
20319 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20323 unsigned int negated, inverted;
20325 negated = encode_thumb32_immediate (-value);
20326 inverted = encode_thumb32_immediate (~value);
20328 rd = (*instruction >> 8) & 0xf;
20329 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20332 /* ADD <-> SUB. Includes CMP <-> CMN. */
20333 case T2_OPCODE_SUB:
20334 new_inst = T2_OPCODE_ADD;
20338 case T2_OPCODE_ADD:
20339 new_inst = T2_OPCODE_SUB;
20343 /* ORR <-> ORN. Includes MOV <-> MVN. */
20344 case T2_OPCODE_ORR:
20345 new_inst = T2_OPCODE_ORN;
20349 case T2_OPCODE_ORN:
20350 new_inst = T2_OPCODE_ORR;
20354 /* AND <-> BIC. TST has no inverted equivalent. */
20355 case T2_OPCODE_AND:
20356 new_inst = T2_OPCODE_BIC;
20363 case T2_OPCODE_BIC:
20364 new_inst = T2_OPCODE_AND;
20369 case T2_OPCODE_ADC:
20370 new_inst = T2_OPCODE_SBC;
20374 case T2_OPCODE_SBC:
20375 new_inst = T2_OPCODE_ADC;
20379 /* We cannot do anything. */
20384 if (value == (unsigned int)FAIL)
20387 *instruction &= T2_OPCODE_MASK;
20388 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20392 /* Read a 32-bit thumb instruction from buf. */
20393 static unsigned long
20394 get_thumb32_insn (char * buf)
20396 unsigned long insn;
20397 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20398 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20404 /* We usually want to set the low bit on the address of thumb function
20405 symbols. In particular .word foo - . should have the low bit set.
20406 Generic code tries to fold the difference of two symbols to
20407 a constant. Prevent this and force a relocation when the first symbols
20408 is a thumb function. */
20411 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20413 if (op == O_subtract
20414 && l->X_op == O_symbol
20415 && r->X_op == O_symbol
20416 && THUMB_IS_FUNC (l->X_add_symbol))
20418 l->X_op = O_subtract;
20419 l->X_op_symbol = r->X_add_symbol;
20420 l->X_add_number -= r->X_add_number;
20424 /* Process as normal. */
20428 /* Encode Thumb2 unconditional branches and calls. The encoding
20429 for the 2 are identical for the immediate values. */
20432 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20434 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20437 addressT S, I1, I2, lo, hi;
20439 S = (value >> 24) & 0x01;
20440 I1 = (value >> 23) & 0x01;
20441 I2 = (value >> 22) & 0x01;
20442 hi = (value >> 12) & 0x3ff;
20443 lo = (value >> 1) & 0x7ff;
20444 newval = md_chars_to_number (buf, THUMB_SIZE);
20445 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20446 newval |= (S << 10) | hi;
20447 newval2 &= ~T2I1I2MASK;
20448 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20449 md_number_to_chars (buf, newval, THUMB_SIZE);
20450 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20454 md_apply_fix (fixS * fixP,
20458 offsetT value = * valP;
20460 unsigned int newimm;
20461 unsigned long temp;
20463 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20465 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20467 /* Note whether this will delete the relocation. */
20469 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20472 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20473 consistency with the behaviour on 32-bit hosts. Remember value
20475 value &= 0xffffffff;
20476 value ^= 0x80000000;
20477 value -= 0x80000000;
20480 fixP->fx_addnumber = value;
20482 /* Same treatment for fixP->fx_offset. */
20483 fixP->fx_offset &= 0xffffffff;
20484 fixP->fx_offset ^= 0x80000000;
20485 fixP->fx_offset -= 0x80000000;
20487 switch (fixP->fx_r_type)
20489 case BFD_RELOC_NONE:
20490 /* This will need to go in the object file. */
20494 case BFD_RELOC_ARM_IMMEDIATE:
20495 /* We claim that this fixup has been processed here,
20496 even if in fact we generate an error because we do
20497 not have a reloc for it, so tc_gen_reloc will reject it. */
20500 if (fixP->fx_addsy)
20502 const char *msg = 0;
20504 if (! S_IS_DEFINED (fixP->fx_addsy))
20505 msg = _("undefined symbol %s used as an immediate value");
20506 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20507 msg = _("symbol %s is in a different section");
20508 else if (S_IS_WEAK (fixP->fx_addsy))
20509 msg = _("symbol %s is weak and may be overridden later");
20513 as_bad_where (fixP->fx_file, fixP->fx_line,
20514 msg, S_GET_NAME (fixP->fx_addsy));
20519 newimm = encode_arm_immediate (value);
20520 temp = md_chars_to_number (buf, INSN_SIZE);
20522 /* If the instruction will fail, see if we can fix things up by
20523 changing the opcode. */
20524 if (newimm == (unsigned int) FAIL
20525 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20527 as_bad_where (fixP->fx_file, fixP->fx_line,
20528 _("invalid constant (%lx) after fixup"),
20529 (unsigned long) value);
20533 newimm |= (temp & 0xfffff000);
20534 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20537 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20539 unsigned int highpart = 0;
20540 unsigned int newinsn = 0xe1a00000; /* nop. */
20542 if (fixP->fx_addsy)
20544 const char *msg = 0;
20546 if (! S_IS_DEFINED (fixP->fx_addsy))
20547 msg = _("undefined symbol %s used as an immediate value");
20548 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20549 msg = _("symbol %s is in a different section");
20550 else if (S_IS_WEAK (fixP->fx_addsy))
20551 msg = _("symbol %s is weak and may be overridden later");
20555 as_bad_where (fixP->fx_file, fixP->fx_line,
20556 msg, S_GET_NAME (fixP->fx_addsy));
20561 newimm = encode_arm_immediate (value);
20562 temp = md_chars_to_number (buf, INSN_SIZE);
20564 /* If the instruction will fail, see if we can fix things up by
20565 changing the opcode. */
20566 if (newimm == (unsigned int) FAIL
20567 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20569 /* No ? OK - try using two ADD instructions to generate
20571 newimm = validate_immediate_twopart (value, & highpart);
20573 /* Yes - then make sure that the second instruction is
20575 if (newimm != (unsigned int) FAIL)
20577 /* Still No ? Try using a negated value. */
20578 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20579 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20580 /* Otherwise - give up. */
20583 as_bad_where (fixP->fx_file, fixP->fx_line,
20584 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20589 /* Replace the first operand in the 2nd instruction (which
20590 is the PC) with the destination register. We have
20591 already added in the PC in the first instruction and we
20592 do not want to do it again. */
20593 newinsn &= ~ 0xf0000;
20594 newinsn |= ((newinsn & 0x0f000) << 4);
20597 newimm |= (temp & 0xfffff000);
20598 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20600 highpart |= (newinsn & 0xfffff000);
20601 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20605 case BFD_RELOC_ARM_OFFSET_IMM:
20606 if (!fixP->fx_done && seg->use_rela_p)
20609 case BFD_RELOC_ARM_LITERAL:
20615 if (validate_offset_imm (value, 0) == FAIL)
20617 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20618 as_bad_where (fixP->fx_file, fixP->fx_line,
20619 _("invalid literal constant: pool needs to be closer"));
20621 as_bad_where (fixP->fx_file, fixP->fx_line,
20622 _("bad immediate value for offset (%ld)"),
20627 newval = md_chars_to_number (buf, INSN_SIZE);
20629 newval &= 0xfffff000;
20632 newval &= 0xff7ff000;
20633 newval |= value | (sign ? INDEX_UP : 0);
20635 md_number_to_chars (buf, newval, INSN_SIZE);
20638 case BFD_RELOC_ARM_OFFSET_IMM8:
20639 case BFD_RELOC_ARM_HWLITERAL:
20645 if (validate_offset_imm (value, 1) == FAIL)
20647 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20648 as_bad_where (fixP->fx_file, fixP->fx_line,
20649 _("invalid literal constant: pool needs to be closer"));
20651 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20656 newval = md_chars_to_number (buf, INSN_SIZE);
20658 newval &= 0xfffff0f0;
20661 newval &= 0xff7ff0f0;
20662 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20664 md_number_to_chars (buf, newval, INSN_SIZE);
20667 case BFD_RELOC_ARM_T32_OFFSET_U8:
20668 if (value < 0 || value > 1020 || value % 4 != 0)
20669 as_bad_where (fixP->fx_file, fixP->fx_line,
20670 _("bad immediate value for offset (%ld)"), (long) value);
20673 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20675 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20678 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20679 /* This is a complicated relocation used for all varieties of Thumb32
20680 load/store instruction with immediate offset:
20682 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20683 *4, optional writeback(W)
20684 (doubleword load/store)
20686 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20687 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20688 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20689 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20690 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20692 Uppercase letters indicate bits that are already encoded at
20693 this point. Lowercase letters are our problem. For the
20694 second block of instructions, the secondary opcode nybble
20695 (bits 8..11) is present, and bit 23 is zero, even if this is
20696 a PC-relative operation. */
20697 newval = md_chars_to_number (buf, THUMB_SIZE);
20699 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20701 if ((newval & 0xf0000000) == 0xe0000000)
20703 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20705 newval |= (1 << 23);
20708 if (value % 4 != 0)
20710 as_bad_where (fixP->fx_file, fixP->fx_line,
20711 _("offset not a multiple of 4"));
20717 as_bad_where (fixP->fx_file, fixP->fx_line,
20718 _("offset out of range"));
20723 else if ((newval & 0x000f0000) == 0x000f0000)
20725 /* PC-relative, 12-bit offset. */
20727 newval |= (1 << 23);
20732 as_bad_where (fixP->fx_file, fixP->fx_line,
20733 _("offset out of range"));
20738 else if ((newval & 0x00000100) == 0x00000100)
20740 /* Writeback: 8-bit, +/- offset. */
20742 newval |= (1 << 9);
20747 as_bad_where (fixP->fx_file, fixP->fx_line,
20748 _("offset out of range"));
20753 else if ((newval & 0x00000f00) == 0x00000e00)
20755 /* T-instruction: positive 8-bit offset. */
20756 if (value < 0 || value > 0xff)
20758 as_bad_where (fixP->fx_file, fixP->fx_line,
20759 _("offset out of range"));
20767 /* Positive 12-bit or negative 8-bit offset. */
20771 newval |= (1 << 23);
20781 as_bad_where (fixP->fx_file, fixP->fx_line,
20782 _("offset out of range"));
20789 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20790 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20793 case BFD_RELOC_ARM_SHIFT_IMM:
20794 newval = md_chars_to_number (buf, INSN_SIZE);
20795 if (((unsigned long) value) > 32
20797 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20799 as_bad_where (fixP->fx_file, fixP->fx_line,
20800 _("shift expression is too large"));
20805 /* Shifts of zero must be done as lsl. */
20807 else if (value == 32)
20809 newval &= 0xfffff07f;
20810 newval |= (value & 0x1f) << 7;
20811 md_number_to_chars (buf, newval, INSN_SIZE);
20814 case BFD_RELOC_ARM_T32_IMMEDIATE:
20815 case BFD_RELOC_ARM_T32_ADD_IMM:
20816 case BFD_RELOC_ARM_T32_IMM12:
20817 case BFD_RELOC_ARM_T32_ADD_PC12:
20818 /* We claim that this fixup has been processed here,
20819 even if in fact we generate an error because we do
20820 not have a reloc for it, so tc_gen_reloc will reject it. */
20824 && ! S_IS_DEFINED (fixP->fx_addsy))
20826 as_bad_where (fixP->fx_file, fixP->fx_line,
20827 _("undefined symbol %s used as an immediate value"),
20828 S_GET_NAME (fixP->fx_addsy));
20832 newval = md_chars_to_number (buf, THUMB_SIZE);
20834 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20837 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20838 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20840 newimm = encode_thumb32_immediate (value);
20841 if (newimm == (unsigned int) FAIL)
20842 newimm = thumb32_negate_data_op (&newval, value);
20844 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20845 && newimm == (unsigned int) FAIL)
20847 /* Turn add/sum into addw/subw. */
20848 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20849 newval = (newval & 0xfeffffff) | 0x02000000;
20850 /* No flat 12-bit imm encoding for addsw/subsw. */
20851 if ((newval & 0x00100000) == 0)
20853 /* 12 bit immediate for addw/subw. */
20857 newval ^= 0x00a00000;
20860 newimm = (unsigned int) FAIL;
20866 if (newimm == (unsigned int)FAIL)
20868 as_bad_where (fixP->fx_file, fixP->fx_line,
20869 _("invalid constant (%lx) after fixup"),
20870 (unsigned long) value);
20874 newval |= (newimm & 0x800) << 15;
20875 newval |= (newimm & 0x700) << 4;
20876 newval |= (newimm & 0x0ff);
20878 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20879 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20882 case BFD_RELOC_ARM_SMC:
20883 if (((unsigned long) value) > 0xffff)
20884 as_bad_where (fixP->fx_file, fixP->fx_line,
20885 _("invalid smc expression"));
20886 newval = md_chars_to_number (buf, INSN_SIZE);
20887 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20888 md_number_to_chars (buf, newval, INSN_SIZE);
20891 case BFD_RELOC_ARM_HVC:
20892 if (((unsigned long) value) > 0xffff)
20893 as_bad_where (fixP->fx_file, fixP->fx_line,
20894 _("invalid hvc expression"));
20895 newval = md_chars_to_number (buf, INSN_SIZE);
20896 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20897 md_number_to_chars (buf, newval, INSN_SIZE);
20900 case BFD_RELOC_ARM_SWI:
20901 if (fixP->tc_fix_data != 0)
20903 if (((unsigned long) value) > 0xff)
20904 as_bad_where (fixP->fx_file, fixP->fx_line,
20905 _("invalid swi expression"));
20906 newval = md_chars_to_number (buf, THUMB_SIZE);
20908 md_number_to_chars (buf, newval, THUMB_SIZE);
20912 if (((unsigned long) value) > 0x00ffffff)
20913 as_bad_where (fixP->fx_file, fixP->fx_line,
20914 _("invalid swi expression"));
20915 newval = md_chars_to_number (buf, INSN_SIZE);
20917 md_number_to_chars (buf, newval, INSN_SIZE);
20921 case BFD_RELOC_ARM_MULTI:
20922 if (((unsigned long) value) > 0xffff)
20923 as_bad_where (fixP->fx_file, fixP->fx_line,
20924 _("invalid expression in load/store multiple"));
20925 newval = value | md_chars_to_number (buf, INSN_SIZE);
20926 md_number_to_chars (buf, newval, INSN_SIZE);
20930 case BFD_RELOC_ARM_PCREL_CALL:
20932 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20934 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20935 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20936 && THUMB_IS_FUNC (fixP->fx_addsy))
20937 /* Flip the bl to blx. This is a simple flip
20938 bit here because we generate PCREL_CALL for
20939 unconditional bls. */
20941 newval = md_chars_to_number (buf, INSN_SIZE);
20942 newval = newval | 0x10000000;
20943 md_number_to_chars (buf, newval, INSN_SIZE);
20949 goto arm_branch_common;
20951 case BFD_RELOC_ARM_PCREL_JUMP:
20952 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20954 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20955 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20956 && THUMB_IS_FUNC (fixP->fx_addsy))
20958 /* This would map to a bl<cond>, b<cond>,
20959 b<always> to a Thumb function. We
20960 need to force a relocation for this particular
20962 newval = md_chars_to_number (buf, INSN_SIZE);
20966 case BFD_RELOC_ARM_PLT32:
20968 case BFD_RELOC_ARM_PCREL_BRANCH:
20970 goto arm_branch_common;
20972 case BFD_RELOC_ARM_PCREL_BLX:
20975 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20977 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20978 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20979 && ARM_IS_FUNC (fixP->fx_addsy))
20981 /* Flip the blx to a bl and warn. */
20982 const char *name = S_GET_NAME (fixP->fx_addsy);
20983 newval = 0xeb000000;
20984 as_warn_where (fixP->fx_file, fixP->fx_line,
20985 _("blx to '%s' an ARM ISA state function changed to bl"),
20987 md_number_to_chars (buf, newval, INSN_SIZE);
20993 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20994 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20998 /* We are going to store value (shifted right by two) in the
20999 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21000 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21001 also be be clear. */
21003 as_bad_where (fixP->fx_file, fixP->fx_line,
21004 _("misaligned branch destination"));
21005 if ((value & (offsetT)0xfe000000) != (offsetT)0
21006 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21007 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21009 if (fixP->fx_done || !seg->use_rela_p)
21011 newval = md_chars_to_number (buf, INSN_SIZE);
21012 newval |= (value >> 2) & 0x00ffffff;
21013 /* Set the H bit on BLX instructions. */
21017 newval |= 0x01000000;
21019 newval &= ~0x01000000;
21021 md_number_to_chars (buf, newval, INSN_SIZE);
21025 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21026 /* CBZ can only branch forward. */
21028 /* Attempts to use CBZ to branch to the next instruction
21029 (which, strictly speaking, are prohibited) will be turned into
21032 FIXME: It may be better to remove the instruction completely and
21033 perform relaxation. */
21036 newval = md_chars_to_number (buf, THUMB_SIZE);
21037 newval = 0xbf00; /* NOP encoding T1 */
21038 md_number_to_chars (buf, newval, THUMB_SIZE);
21043 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21045 if (fixP->fx_done || !seg->use_rela_p)
21047 newval = md_chars_to_number (buf, THUMB_SIZE);
21048 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21049 md_number_to_chars (buf, newval, THUMB_SIZE);
21054 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21055 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21056 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21058 if (fixP->fx_done || !seg->use_rela_p)
21060 newval = md_chars_to_number (buf, THUMB_SIZE);
21061 newval |= (value & 0x1ff) >> 1;
21062 md_number_to_chars (buf, newval, THUMB_SIZE);
21066 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21067 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21068 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21070 if (fixP->fx_done || !seg->use_rela_p)
21072 newval = md_chars_to_number (buf, THUMB_SIZE);
21073 newval |= (value & 0xfff) >> 1;
21074 md_number_to_chars (buf, newval, THUMB_SIZE);
21078 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21080 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21081 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21082 && ARM_IS_FUNC (fixP->fx_addsy)
21083 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21085 /* Force a relocation for a branch 20 bits wide. */
21088 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21089 as_bad_where (fixP->fx_file, fixP->fx_line,
21090 _("conditional branch out of range"));
21092 if (fixP->fx_done || !seg->use_rela_p)
21095 addressT S, J1, J2, lo, hi;
21097 S = (value & 0x00100000) >> 20;
21098 J2 = (value & 0x00080000) >> 19;
21099 J1 = (value & 0x00040000) >> 18;
21100 hi = (value & 0x0003f000) >> 12;
21101 lo = (value & 0x00000ffe) >> 1;
21103 newval = md_chars_to_number (buf, THUMB_SIZE);
21104 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21105 newval |= (S << 10) | hi;
21106 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21107 md_number_to_chars (buf, newval, THUMB_SIZE);
21108 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21112 case BFD_RELOC_THUMB_PCREL_BLX:
21113 /* If there is a blx from a thumb state function to
21114 another thumb function flip this to a bl and warn
21118 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21119 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21120 && THUMB_IS_FUNC (fixP->fx_addsy))
21122 const char *name = S_GET_NAME (fixP->fx_addsy);
21123 as_warn_where (fixP->fx_file, fixP->fx_line,
21124 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21126 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21127 newval = newval | 0x1000;
21128 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21129 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21134 goto thumb_bl_common;
21136 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21137 /* A bl from Thumb state ISA to an internal ARM state function
21138 is converted to a blx. */
21140 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21141 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21142 && ARM_IS_FUNC (fixP->fx_addsy)
21143 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21145 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21146 newval = newval & ~0x1000;
21147 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21148 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21155 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21156 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21157 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21160 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21161 /* For a BLX instruction, make sure that the relocation is rounded up
21162 to a word boundary. This follows the semantics of the instruction
21163 which specifies that bit 1 of the target address will come from bit
21164 1 of the base address. */
21165 value = (value + 1) & ~ 1;
21167 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21169 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21170 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21171 else if ((value & ~0x1ffffff)
21172 && ((value & ~0x1ffffff) != ~0x1ffffff))
21173 as_bad_where (fixP->fx_file, fixP->fx_line,
21174 _("Thumb2 branch out of range"));
21177 if (fixP->fx_done || !seg->use_rela_p)
21178 encode_thumb2_b_bl_offset (buf, value);
21182 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21183 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21184 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21186 if (fixP->fx_done || !seg->use_rela_p)
21187 encode_thumb2_b_bl_offset (buf, value);
21192 if (fixP->fx_done || !seg->use_rela_p)
21193 md_number_to_chars (buf, value, 1);
21197 if (fixP->fx_done || !seg->use_rela_p)
21198 md_number_to_chars (buf, value, 2);
21202 case BFD_RELOC_ARM_TLS_CALL:
21203 case BFD_RELOC_ARM_THM_TLS_CALL:
21204 case BFD_RELOC_ARM_TLS_DESCSEQ:
21205 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21206 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21209 case BFD_RELOC_ARM_TLS_GOTDESC:
21210 case BFD_RELOC_ARM_TLS_GD32:
21211 case BFD_RELOC_ARM_TLS_LE32:
21212 case BFD_RELOC_ARM_TLS_IE32:
21213 case BFD_RELOC_ARM_TLS_LDM32:
21214 case BFD_RELOC_ARM_TLS_LDO32:
21215 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21218 case BFD_RELOC_ARM_GOT32:
21219 case BFD_RELOC_ARM_GOTOFF:
21220 if (fixP->fx_done || !seg->use_rela_p)
21221 md_number_to_chars (buf, 0, 4);
21224 case BFD_RELOC_ARM_GOT_PREL:
21225 if (fixP->fx_done || !seg->use_rela_p)
21226 md_number_to_chars (buf, value, 4);
21229 case BFD_RELOC_ARM_TARGET2:
21230 /* TARGET2 is not partial-inplace, so we need to write the
21231 addend here for REL targets, because it won't be written out
21232 during reloc processing later. */
21233 if (fixP->fx_done || !seg->use_rela_p)
21234 md_number_to_chars (buf, fixP->fx_offset, 4);
21238 case BFD_RELOC_RVA:
21240 case BFD_RELOC_ARM_TARGET1:
21241 case BFD_RELOC_ARM_ROSEGREL32:
21242 case BFD_RELOC_ARM_SBREL32:
21243 case BFD_RELOC_32_PCREL:
21245 case BFD_RELOC_32_SECREL:
21247 if (fixP->fx_done || !seg->use_rela_p)
21249 /* For WinCE we only do this for pcrel fixups. */
21250 if (fixP->fx_done || fixP->fx_pcrel)
21252 md_number_to_chars (buf, value, 4);
21256 case BFD_RELOC_ARM_PREL31:
21257 if (fixP->fx_done || !seg->use_rela_p)
21259 newval = md_chars_to_number (buf, 4) & 0x80000000;
21260 if ((value ^ (value >> 1)) & 0x40000000)
21262 as_bad_where (fixP->fx_file, fixP->fx_line,
21263 _("rel31 relocation overflow"));
21265 newval |= value & 0x7fffffff;
21266 md_number_to_chars (buf, newval, 4);
21271 case BFD_RELOC_ARM_CP_OFF_IMM:
21272 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21273 if (value < -1023 || value > 1023 || (value & 3))
21274 as_bad_where (fixP->fx_file, fixP->fx_line,
21275 _("co-processor offset out of range"));
21280 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21281 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21282 newval = md_chars_to_number (buf, INSN_SIZE);
21284 newval = get_thumb32_insn (buf);
21286 newval &= 0xffffff00;
21289 newval &= 0xff7fff00;
21290 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21292 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21293 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21294 md_number_to_chars (buf, newval, INSN_SIZE);
21296 put_thumb32_insn (buf, newval);
21299 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21300 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21301 if (value < -255 || value > 255)
21302 as_bad_where (fixP->fx_file, fixP->fx_line,
21303 _("co-processor offset out of range"));
21305 goto cp_off_common;
21307 case BFD_RELOC_ARM_THUMB_OFFSET:
21308 newval = md_chars_to_number (buf, THUMB_SIZE);
21309 /* Exactly what ranges, and where the offset is inserted depends
21310 on the type of instruction, we can establish this from the
21312 switch (newval >> 12)
21314 case 4: /* PC load. */
21315 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21316 forced to zero for these loads; md_pcrel_from has already
21317 compensated for this. */
21319 as_bad_where (fixP->fx_file, fixP->fx_line,
21320 _("invalid offset, target not word aligned (0x%08lX)"),
21321 (((unsigned long) fixP->fx_frag->fr_address
21322 + (unsigned long) fixP->fx_where) & ~3)
21323 + (unsigned long) value);
21325 if (value & ~0x3fc)
21326 as_bad_where (fixP->fx_file, fixP->fx_line,
21327 _("invalid offset, value too big (0x%08lX)"),
21330 newval |= value >> 2;
21333 case 9: /* SP load/store. */
21334 if (value & ~0x3fc)
21335 as_bad_where (fixP->fx_file, fixP->fx_line,
21336 _("invalid offset, value too big (0x%08lX)"),
21338 newval |= value >> 2;
21341 case 6: /* Word load/store. */
21343 as_bad_where (fixP->fx_file, fixP->fx_line,
21344 _("invalid offset, value too big (0x%08lX)"),
21346 newval |= value << 4; /* 6 - 2. */
21349 case 7: /* Byte load/store. */
21351 as_bad_where (fixP->fx_file, fixP->fx_line,
21352 _("invalid offset, value too big (0x%08lX)"),
21354 newval |= value << 6;
21357 case 8: /* Halfword load/store. */
21359 as_bad_where (fixP->fx_file, fixP->fx_line,
21360 _("invalid offset, value too big (0x%08lX)"),
21362 newval |= value << 5; /* 6 - 1. */
21366 as_bad_where (fixP->fx_file, fixP->fx_line,
21367 "Unable to process relocation for thumb opcode: %lx",
21368 (unsigned long) newval);
21371 md_number_to_chars (buf, newval, THUMB_SIZE);
21374 case BFD_RELOC_ARM_THUMB_ADD:
21375 /* This is a complicated relocation, since we use it for all of
21376 the following immediate relocations:
21380 9bit ADD/SUB SP word-aligned
21381 10bit ADD PC/SP word-aligned
21383 The type of instruction being processed is encoded in the
21390 newval = md_chars_to_number (buf, THUMB_SIZE);
21392 int rd = (newval >> 4) & 0xf;
21393 int rs = newval & 0xf;
21394 int subtract = !!(newval & 0x8000);
21396 /* Check for HI regs, only very restricted cases allowed:
21397 Adjusting SP, and using PC or SP to get an address. */
21398 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21399 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21400 as_bad_where (fixP->fx_file, fixP->fx_line,
21401 _("invalid Hi register with immediate"));
21403 /* If value is negative, choose the opposite instruction. */
21407 subtract = !subtract;
21409 as_bad_where (fixP->fx_file, fixP->fx_line,
21410 _("immediate value out of range"));
21415 if (value & ~0x1fc)
21416 as_bad_where (fixP->fx_file, fixP->fx_line,
21417 _("invalid immediate for stack address calculation"));
21418 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21419 newval |= value >> 2;
21421 else if (rs == REG_PC || rs == REG_SP)
21423 if (subtract || value & ~0x3fc)
21424 as_bad_where (fixP->fx_file, fixP->fx_line,
21425 _("invalid immediate for address calculation (value = 0x%08lX)"),
21426 (unsigned long) value);
21427 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21429 newval |= value >> 2;
21434 as_bad_where (fixP->fx_file, fixP->fx_line,
21435 _("immediate value out of range"));
21436 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21437 newval |= (rd << 8) | value;
21442 as_bad_where (fixP->fx_file, fixP->fx_line,
21443 _("immediate value out of range"));
21444 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21445 newval |= rd | (rs << 3) | (value << 6);
21448 md_number_to_chars (buf, newval, THUMB_SIZE);
21451 case BFD_RELOC_ARM_THUMB_IMM:
21452 newval = md_chars_to_number (buf, THUMB_SIZE);
21453 if (value < 0 || value > 255)
21454 as_bad_where (fixP->fx_file, fixP->fx_line,
21455 _("invalid immediate: %ld is out of range"),
21458 md_number_to_chars (buf, newval, THUMB_SIZE);
21461 case BFD_RELOC_ARM_THUMB_SHIFT:
21462 /* 5bit shift value (0..32). LSL cannot take 32. */
21463 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21464 temp = newval & 0xf800;
21465 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21466 as_bad_where (fixP->fx_file, fixP->fx_line,
21467 _("invalid shift value: %ld"), (long) value);
21468 /* Shifts of zero must be encoded as LSL. */
21470 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21471 /* Shifts of 32 are encoded as zero. */
21472 else if (value == 32)
21474 newval |= value << 6;
21475 md_number_to_chars (buf, newval, THUMB_SIZE);
21478 case BFD_RELOC_VTABLE_INHERIT:
21479 case BFD_RELOC_VTABLE_ENTRY:
21483 case BFD_RELOC_ARM_MOVW:
21484 case BFD_RELOC_ARM_MOVT:
21485 case BFD_RELOC_ARM_THUMB_MOVW:
21486 case BFD_RELOC_ARM_THUMB_MOVT:
21487 if (fixP->fx_done || !seg->use_rela_p)
21489 /* REL format relocations are limited to a 16-bit addend. */
21490 if (!fixP->fx_done)
21492 if (value < -0x8000 || value > 0x7fff)
21493 as_bad_where (fixP->fx_file, fixP->fx_line,
21494 _("offset out of range"));
21496 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21497 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21502 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21503 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21505 newval = get_thumb32_insn (buf);
21506 newval &= 0xfbf08f00;
21507 newval |= (value & 0xf000) << 4;
21508 newval |= (value & 0x0800) << 15;
21509 newval |= (value & 0x0700) << 4;
21510 newval |= (value & 0x00ff);
21511 put_thumb32_insn (buf, newval);
21515 newval = md_chars_to_number (buf, 4);
21516 newval &= 0xfff0f000;
21517 newval |= value & 0x0fff;
21518 newval |= (value & 0xf000) << 4;
21519 md_number_to_chars (buf, newval, 4);
21524 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21525 case BFD_RELOC_ARM_ALU_PC_G0:
21526 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21527 case BFD_RELOC_ARM_ALU_PC_G1:
21528 case BFD_RELOC_ARM_ALU_PC_G2:
21529 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21530 case BFD_RELOC_ARM_ALU_SB_G0:
21531 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21532 case BFD_RELOC_ARM_ALU_SB_G1:
21533 case BFD_RELOC_ARM_ALU_SB_G2:
21534 gas_assert (!fixP->fx_done);
21535 if (!seg->use_rela_p)
21538 bfd_vma encoded_addend;
21539 bfd_vma addend_abs = abs (value);
21541 /* Check that the absolute value of the addend can be
21542 expressed as an 8-bit constant plus a rotation. */
21543 encoded_addend = encode_arm_immediate (addend_abs);
21544 if (encoded_addend == (unsigned int) FAIL)
21545 as_bad_where (fixP->fx_file, fixP->fx_line,
21546 _("the offset 0x%08lX is not representable"),
21547 (unsigned long) addend_abs);
21549 /* Extract the instruction. */
21550 insn = md_chars_to_number (buf, INSN_SIZE);
21552 /* If the addend is positive, use an ADD instruction.
21553 Otherwise use a SUB. Take care not to destroy the S bit. */
21554 insn &= 0xff1fffff;
21560 /* Place the encoded addend into the first 12 bits of the
21562 insn &= 0xfffff000;
21563 insn |= encoded_addend;
21565 /* Update the instruction. */
21566 md_number_to_chars (buf, insn, INSN_SIZE);
21570 case BFD_RELOC_ARM_LDR_PC_G0:
21571 case BFD_RELOC_ARM_LDR_PC_G1:
21572 case BFD_RELOC_ARM_LDR_PC_G2:
21573 case BFD_RELOC_ARM_LDR_SB_G0:
21574 case BFD_RELOC_ARM_LDR_SB_G1:
21575 case BFD_RELOC_ARM_LDR_SB_G2:
21576 gas_assert (!fixP->fx_done);
21577 if (!seg->use_rela_p)
21580 bfd_vma addend_abs = abs (value);
21582 /* Check that the absolute value of the addend can be
21583 encoded in 12 bits. */
21584 if (addend_abs >= 0x1000)
21585 as_bad_where (fixP->fx_file, fixP->fx_line,
21586 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21587 (unsigned long) addend_abs);
21589 /* Extract the instruction. */
21590 insn = md_chars_to_number (buf, INSN_SIZE);
21592 /* If the addend is negative, clear bit 23 of the instruction.
21593 Otherwise set it. */
21595 insn &= ~(1 << 23);
21599 /* Place the absolute value of the addend into the first 12 bits
21600 of the instruction. */
21601 insn &= 0xfffff000;
21602 insn |= addend_abs;
21604 /* Update the instruction. */
21605 md_number_to_chars (buf, insn, INSN_SIZE);
21609 case BFD_RELOC_ARM_LDRS_PC_G0:
21610 case BFD_RELOC_ARM_LDRS_PC_G1:
21611 case BFD_RELOC_ARM_LDRS_PC_G2:
21612 case BFD_RELOC_ARM_LDRS_SB_G0:
21613 case BFD_RELOC_ARM_LDRS_SB_G1:
21614 case BFD_RELOC_ARM_LDRS_SB_G2:
21615 gas_assert (!fixP->fx_done);
21616 if (!seg->use_rela_p)
21619 bfd_vma addend_abs = abs (value);
21621 /* Check that the absolute value of the addend can be
21622 encoded in 8 bits. */
21623 if (addend_abs >= 0x100)
21624 as_bad_where (fixP->fx_file, fixP->fx_line,
21625 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21626 (unsigned long) addend_abs);
21628 /* Extract the instruction. */
21629 insn = md_chars_to_number (buf, INSN_SIZE);
21631 /* If the addend is negative, clear bit 23 of the instruction.
21632 Otherwise set it. */
21634 insn &= ~(1 << 23);
21638 /* Place the first four bits of the absolute value of the addend
21639 into the first 4 bits of the instruction, and the remaining
21640 four into bits 8 .. 11. */
21641 insn &= 0xfffff0f0;
21642 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21644 /* Update the instruction. */
21645 md_number_to_chars (buf, insn, INSN_SIZE);
21649 case BFD_RELOC_ARM_LDC_PC_G0:
21650 case BFD_RELOC_ARM_LDC_PC_G1:
21651 case BFD_RELOC_ARM_LDC_PC_G2:
21652 case BFD_RELOC_ARM_LDC_SB_G0:
21653 case BFD_RELOC_ARM_LDC_SB_G1:
21654 case BFD_RELOC_ARM_LDC_SB_G2:
21655 gas_assert (!fixP->fx_done);
21656 if (!seg->use_rela_p)
21659 bfd_vma addend_abs = abs (value);
21661 /* Check that the absolute value of the addend is a multiple of
21662 four and, when divided by four, fits in 8 bits. */
21663 if (addend_abs & 0x3)
21664 as_bad_where (fixP->fx_file, fixP->fx_line,
21665 _("bad offset 0x%08lX (must be word-aligned)"),
21666 (unsigned long) addend_abs);
21668 if ((addend_abs >> 2) > 0xff)
21669 as_bad_where (fixP->fx_file, fixP->fx_line,
21670 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21671 (unsigned long) addend_abs);
21673 /* Extract the instruction. */
21674 insn = md_chars_to_number (buf, INSN_SIZE);
21676 /* If the addend is negative, clear bit 23 of the instruction.
21677 Otherwise set it. */
21679 insn &= ~(1 << 23);
21683 /* Place the addend (divided by four) into the first eight
21684 bits of the instruction. */
21685 insn &= 0xfffffff0;
21686 insn |= addend_abs >> 2;
21688 /* Update the instruction. */
21689 md_number_to_chars (buf, insn, INSN_SIZE);
21693 case BFD_RELOC_ARM_V4BX:
21694 /* This will need to go in the object file. */
21698 case BFD_RELOC_UNUSED:
21700 as_bad_where (fixP->fx_file, fixP->fx_line,
21701 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21705 /* Translate internal representation of relocation info to BFD target
21709 tc_gen_reloc (asection *section, fixS *fixp)
21712 bfd_reloc_code_real_type code;
21714 reloc = (arelent *) xmalloc (sizeof (arelent));
21716 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21717 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21718 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21720 if (fixp->fx_pcrel)
21722 if (section->use_rela_p)
21723 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21725 fixp->fx_offset = reloc->address;
21727 reloc->addend = fixp->fx_offset;
21729 switch (fixp->fx_r_type)
21732 if (fixp->fx_pcrel)
21734 code = BFD_RELOC_8_PCREL;
21739 if (fixp->fx_pcrel)
21741 code = BFD_RELOC_16_PCREL;
21746 if (fixp->fx_pcrel)
21748 code = BFD_RELOC_32_PCREL;
21752 case BFD_RELOC_ARM_MOVW:
21753 if (fixp->fx_pcrel)
21755 code = BFD_RELOC_ARM_MOVW_PCREL;
21759 case BFD_RELOC_ARM_MOVT:
21760 if (fixp->fx_pcrel)
21762 code = BFD_RELOC_ARM_MOVT_PCREL;
21766 case BFD_RELOC_ARM_THUMB_MOVW:
21767 if (fixp->fx_pcrel)
21769 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21773 case BFD_RELOC_ARM_THUMB_MOVT:
21774 if (fixp->fx_pcrel)
21776 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21780 case BFD_RELOC_NONE:
21781 case BFD_RELOC_ARM_PCREL_BRANCH:
21782 case BFD_RELOC_ARM_PCREL_BLX:
21783 case BFD_RELOC_RVA:
21784 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21785 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21786 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21787 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21788 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21789 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21790 case BFD_RELOC_VTABLE_ENTRY:
21791 case BFD_RELOC_VTABLE_INHERIT:
21793 case BFD_RELOC_32_SECREL:
21795 code = fixp->fx_r_type;
21798 case BFD_RELOC_THUMB_PCREL_BLX:
21800 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21801 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21804 code = BFD_RELOC_THUMB_PCREL_BLX;
21807 case BFD_RELOC_ARM_LITERAL:
21808 case BFD_RELOC_ARM_HWLITERAL:
21809 /* If this is called then the a literal has
21810 been referenced across a section boundary. */
21811 as_bad_where (fixp->fx_file, fixp->fx_line,
21812 _("literal referenced across section boundary"));
21816 case BFD_RELOC_ARM_TLS_CALL:
21817 case BFD_RELOC_ARM_THM_TLS_CALL:
21818 case BFD_RELOC_ARM_TLS_DESCSEQ:
21819 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21820 case BFD_RELOC_ARM_GOT32:
21821 case BFD_RELOC_ARM_GOTOFF:
21822 case BFD_RELOC_ARM_GOT_PREL:
21823 case BFD_RELOC_ARM_PLT32:
21824 case BFD_RELOC_ARM_TARGET1:
21825 case BFD_RELOC_ARM_ROSEGREL32:
21826 case BFD_RELOC_ARM_SBREL32:
21827 case BFD_RELOC_ARM_PREL31:
21828 case BFD_RELOC_ARM_TARGET2:
21829 case BFD_RELOC_ARM_TLS_LE32:
21830 case BFD_RELOC_ARM_TLS_LDO32:
21831 case BFD_RELOC_ARM_PCREL_CALL:
21832 case BFD_RELOC_ARM_PCREL_JUMP:
21833 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21834 case BFD_RELOC_ARM_ALU_PC_G0:
21835 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21836 case BFD_RELOC_ARM_ALU_PC_G1:
21837 case BFD_RELOC_ARM_ALU_PC_G2:
21838 case BFD_RELOC_ARM_LDR_PC_G0:
21839 case BFD_RELOC_ARM_LDR_PC_G1:
21840 case BFD_RELOC_ARM_LDR_PC_G2:
21841 case BFD_RELOC_ARM_LDRS_PC_G0:
21842 case BFD_RELOC_ARM_LDRS_PC_G1:
21843 case BFD_RELOC_ARM_LDRS_PC_G2:
21844 case BFD_RELOC_ARM_LDC_PC_G0:
21845 case BFD_RELOC_ARM_LDC_PC_G1:
21846 case BFD_RELOC_ARM_LDC_PC_G2:
21847 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21848 case BFD_RELOC_ARM_ALU_SB_G0:
21849 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21850 case BFD_RELOC_ARM_ALU_SB_G1:
21851 case BFD_RELOC_ARM_ALU_SB_G2:
21852 case BFD_RELOC_ARM_LDR_SB_G0:
21853 case BFD_RELOC_ARM_LDR_SB_G1:
21854 case BFD_RELOC_ARM_LDR_SB_G2:
21855 case BFD_RELOC_ARM_LDRS_SB_G0:
21856 case BFD_RELOC_ARM_LDRS_SB_G1:
21857 case BFD_RELOC_ARM_LDRS_SB_G2:
21858 case BFD_RELOC_ARM_LDC_SB_G0:
21859 case BFD_RELOC_ARM_LDC_SB_G1:
21860 case BFD_RELOC_ARM_LDC_SB_G2:
21861 case BFD_RELOC_ARM_V4BX:
21862 code = fixp->fx_r_type;
21865 case BFD_RELOC_ARM_TLS_GOTDESC:
21866 case BFD_RELOC_ARM_TLS_GD32:
21867 case BFD_RELOC_ARM_TLS_IE32:
21868 case BFD_RELOC_ARM_TLS_LDM32:
21869 /* BFD will include the symbol's address in the addend.
21870 But we don't want that, so subtract it out again here. */
21871 if (!S_IS_COMMON (fixp->fx_addsy))
21872 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21873 code = fixp->fx_r_type;
21877 case BFD_RELOC_ARM_IMMEDIATE:
21878 as_bad_where (fixp->fx_file, fixp->fx_line,
21879 _("internal relocation (type: IMMEDIATE) not fixed up"));
21882 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21883 as_bad_where (fixp->fx_file, fixp->fx_line,
21884 _("ADRL used for a symbol not defined in the same file"));
21887 case BFD_RELOC_ARM_OFFSET_IMM:
21888 if (section->use_rela_p)
21890 code = fixp->fx_r_type;
21894 if (fixp->fx_addsy != NULL
21895 && !S_IS_DEFINED (fixp->fx_addsy)
21896 && S_IS_LOCAL (fixp->fx_addsy))
21898 as_bad_where (fixp->fx_file, fixp->fx_line,
21899 _("undefined local label `%s'"),
21900 S_GET_NAME (fixp->fx_addsy));
21904 as_bad_where (fixp->fx_file, fixp->fx_line,
21905 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21912 switch (fixp->fx_r_type)
21914 case BFD_RELOC_NONE: type = "NONE"; break;
21915 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21916 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21917 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21918 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21919 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21920 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21921 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21922 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21923 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21924 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21925 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21926 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21927 default: type = _("<unknown>"); break;
21929 as_bad_where (fixp->fx_file, fixp->fx_line,
21930 _("cannot represent %s relocation in this object file format"),
21937 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21939 && fixp->fx_addsy == GOT_symbol)
21941 code = BFD_RELOC_ARM_GOTPC;
21942 reloc->addend = fixp->fx_offset = reloc->address;
21946 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21948 if (reloc->howto == NULL)
21950 as_bad_where (fixp->fx_file, fixp->fx_line,
21951 _("cannot represent %s relocation in this object file format"),
21952 bfd_get_reloc_code_name (code));
21956 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21957 vtable entry to be used in the relocation's section offset. */
21958 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21959 reloc->address = fixp->fx_offset;
21964 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21967 cons_fix_new_arm (fragS * frag,
21972 bfd_reloc_code_real_type type;
21976 FIXME: @@ Should look at CPU word size. */
21980 type = BFD_RELOC_8;
21983 type = BFD_RELOC_16;
21987 type = BFD_RELOC_32;
21990 type = BFD_RELOC_64;
21995 if (exp->X_op == O_secrel)
21997 exp->X_op = O_symbol;
21998 type = BFD_RELOC_32_SECREL;
22002 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22005 #if defined (OBJ_COFF)
22007 arm_validate_fix (fixS * fixP)
22009 /* If the destination of the branch is a defined symbol which does not have
22010 the THUMB_FUNC attribute, then we must be calling a function which has
22011 the (interfacearm) attribute. We look for the Thumb entry point to that
22012 function and change the branch to refer to that function instead. */
22013 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22014 && fixP->fx_addsy != NULL
22015 && S_IS_DEFINED (fixP->fx_addsy)
22016 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22018 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22025 arm_force_relocation (struct fix * fixp)
22027 #if defined (OBJ_COFF) && defined (TE_PE)
22028 if (fixp->fx_r_type == BFD_RELOC_RVA)
22032 /* In case we have a call or a branch to a function in ARM ISA mode from
22033 a thumb function or vice-versa force the relocation. These relocations
22034 are cleared off for some cores that might have blx and simple transformations
22038 switch (fixp->fx_r_type)
22040 case BFD_RELOC_ARM_PCREL_JUMP:
22041 case BFD_RELOC_ARM_PCREL_CALL:
22042 case BFD_RELOC_THUMB_PCREL_BLX:
22043 if (THUMB_IS_FUNC (fixp->fx_addsy))
22047 case BFD_RELOC_ARM_PCREL_BLX:
22048 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22049 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22050 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22051 if (ARM_IS_FUNC (fixp->fx_addsy))
22060 /* Resolve these relocations even if the symbol is extern or weak.
22061 Technically this is probably wrong due to symbol preemption.
22062 In practice these relocations do not have enough range to be useful
22063 at dynamic link time, and some code (e.g. in the Linux kernel)
22064 expects these references to be resolved. */
22065 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22066 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22067 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22068 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22069 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22070 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22071 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22072 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22073 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22074 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22075 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22076 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22077 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22078 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22081 /* Always leave these relocations for the linker. */
22082 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22083 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22084 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22087 /* Always generate relocations against function symbols. */
22088 if (fixp->fx_r_type == BFD_RELOC_32
22090 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22093 return generic_force_reloc (fixp);
22096 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22097 /* Relocations against function names must be left unadjusted,
22098 so that the linker can use this information to generate interworking
22099 stubs. The MIPS version of this function
22100 also prevents relocations that are mips-16 specific, but I do not
22101 know why it does this.
22104 There is one other problem that ought to be addressed here, but
22105 which currently is not: Taking the address of a label (rather
22106 than a function) and then later jumping to that address. Such
22107 addresses also ought to have their bottom bit set (assuming that
22108 they reside in Thumb code), but at the moment they will not. */
22111 arm_fix_adjustable (fixS * fixP)
22113 if (fixP->fx_addsy == NULL)
22116 /* Preserve relocations against symbols with function type. */
22117 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22120 if (THUMB_IS_FUNC (fixP->fx_addsy)
22121 && fixP->fx_subsy == NULL)
22124 /* We need the symbol name for the VTABLE entries. */
22125 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22126 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22129 /* Don't allow symbols to be discarded on GOT related relocs. */
22130 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22131 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22132 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22133 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22134 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22135 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22136 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22137 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22138 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22139 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22140 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22141 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22142 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22143 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22146 /* Similarly for group relocations. */
22147 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22148 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22149 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22152 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22153 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22154 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22155 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22156 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22157 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22158 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22159 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22160 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22165 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22170 elf32_arm_target_format (void)
22173 return (target_big_endian
22174 ? "elf32-bigarm-symbian"
22175 : "elf32-littlearm-symbian");
22176 #elif defined (TE_VXWORKS)
22177 return (target_big_endian
22178 ? "elf32-bigarm-vxworks"
22179 : "elf32-littlearm-vxworks");
22181 if (target_big_endian)
22182 return "elf32-bigarm";
22184 return "elf32-littlearm";
22189 armelf_frob_symbol (symbolS * symp,
22192 elf_frob_symbol (symp, puntp);
22196 /* MD interface: Finalization. */
22201 literal_pool * pool;
22203 /* Ensure that all the IT blocks are properly closed. */
22204 check_it_blocks_finished ();
22206 for (pool = list_of_pools; pool; pool = pool->next)
22208 /* Put it at the end of the relevant section. */
22209 subseg_set (pool->section, pool->sub_section);
22211 arm_elf_change_section ();
22218 /* Remove any excess mapping symbols generated for alignment frags in
22219 SEC. We may have created a mapping symbol before a zero byte
22220 alignment; remove it if there's a mapping symbol after the
22223 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22224 void *dummy ATTRIBUTE_UNUSED)
22226 segment_info_type *seginfo = seg_info (sec);
22229 if (seginfo == NULL || seginfo->frchainP == NULL)
22232 for (fragp = seginfo->frchainP->frch_root;
22234 fragp = fragp->fr_next)
22236 symbolS *sym = fragp->tc_frag_data.last_map;
22237 fragS *next = fragp->fr_next;
22239 /* Variable-sized frags have been converted to fixed size by
22240 this point. But if this was variable-sized to start with,
22241 there will be a fixed-size frag after it. So don't handle
22243 if (sym == NULL || next == NULL)
22246 if (S_GET_VALUE (sym) < next->fr_address)
22247 /* Not at the end of this frag. */
22249 know (S_GET_VALUE (sym) == next->fr_address);
22253 if (next->tc_frag_data.first_map != NULL)
22255 /* Next frag starts with a mapping symbol. Discard this
22257 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22261 if (next->fr_next == NULL)
22263 /* This mapping symbol is at the end of the section. Discard
22265 know (next->fr_fix == 0 && next->fr_var == 0);
22266 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22270 /* As long as we have empty frags without any mapping symbols,
22272 /* If the next frag is non-empty and does not start with a
22273 mapping symbol, then this mapping symbol is required. */
22274 if (next->fr_address != next->fr_next->fr_address)
22277 next = next->fr_next;
22279 while (next != NULL);
22284 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22288 arm_adjust_symtab (void)
22293 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22295 if (ARM_IS_THUMB (sym))
22297 if (THUMB_IS_FUNC (sym))
22299 /* Mark the symbol as a Thumb function. */
22300 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22301 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22302 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22304 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22305 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22307 as_bad (_("%s: unexpected function type: %d"),
22308 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22310 else switch (S_GET_STORAGE_CLASS (sym))
22313 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22316 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22319 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22327 if (ARM_IS_INTERWORK (sym))
22328 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22335 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22337 if (ARM_IS_THUMB (sym))
22339 elf_symbol_type * elf_sym;
22341 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22342 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22344 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22345 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22347 /* If it's a .thumb_func, declare it as so,
22348 otherwise tag label as .code 16. */
22349 if (THUMB_IS_FUNC (sym))
22350 elf_sym->internal_elf_sym.st_target_internal
22351 = ST_BRANCH_TO_THUMB;
22352 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22353 elf_sym->internal_elf_sym.st_info =
22354 ELF_ST_INFO (bind, STT_ARM_16BIT);
22359 /* Remove any overlapping mapping symbols generated by alignment frags. */
22360 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22361 /* Now do generic ELF adjustments. */
22362 elf_adjust_symtab ();
22366 /* MD interface: Initialization. */
22369 set_constant_flonums (void)
22373 for (i = 0; i < NUM_FLOAT_VALS; i++)
22374 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22378 /* Auto-select Thumb mode if it's the only available instruction set for the
22379 given architecture. */
22382 autoselect_thumb_from_cpu_variant (void)
22384 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22385 opcode_select (16);
22394 if ( (arm_ops_hsh = hash_new ()) == NULL
22395 || (arm_cond_hsh = hash_new ()) == NULL
22396 || (arm_shift_hsh = hash_new ()) == NULL
22397 || (arm_psr_hsh = hash_new ()) == NULL
22398 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22399 || (arm_reg_hsh = hash_new ()) == NULL
22400 || (arm_reloc_hsh = hash_new ()) == NULL
22401 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22402 as_fatal (_("virtual memory exhausted"));
22404 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22405 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22406 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22407 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22408 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22409 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22410 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22411 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22412 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22413 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22414 (void *) (v7m_psrs + i));
22415 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22416 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22418 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22420 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22421 (void *) (barrier_opt_names + i));
22423 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
22424 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
22427 set_constant_flonums ();
22429 /* Set the cpu variant based on the command-line options. We prefer
22430 -mcpu= over -march= if both are set (as for GCC); and we prefer
22431 -mfpu= over any other way of setting the floating point unit.
22432 Use of legacy options with new options are faulted. */
22435 if (mcpu_cpu_opt || march_cpu_opt)
22436 as_bad (_("use of old and new-style options to set CPU type"));
22438 mcpu_cpu_opt = legacy_cpu;
22440 else if (!mcpu_cpu_opt)
22441 mcpu_cpu_opt = march_cpu_opt;
22446 as_bad (_("use of old and new-style options to set FPU type"));
22448 mfpu_opt = legacy_fpu;
22450 else if (!mfpu_opt)
22452 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22453 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22454 /* Some environments specify a default FPU. If they don't, infer it
22455 from the processor. */
22457 mfpu_opt = mcpu_fpu_opt;
22459 mfpu_opt = march_fpu_opt;
22461 mfpu_opt = &fpu_default;
22467 if (mcpu_cpu_opt != NULL)
22468 mfpu_opt = &fpu_default;
22469 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22470 mfpu_opt = &fpu_arch_vfp_v2;
22472 mfpu_opt = &fpu_arch_fpa;
22478 mcpu_cpu_opt = &cpu_default;
22479 selected_cpu = cpu_default;
22483 selected_cpu = *mcpu_cpu_opt;
22485 mcpu_cpu_opt = &arm_arch_any;
22488 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22490 autoselect_thumb_from_cpu_variant ();
22492 arm_arch_used = thumb_arch_used = arm_arch_none;
22494 #if defined OBJ_COFF || defined OBJ_ELF
22496 unsigned int flags = 0;
22498 #if defined OBJ_ELF
22499 flags = meabi_flags;
22501 switch (meabi_flags)
22503 case EF_ARM_EABI_UNKNOWN:
22505 /* Set the flags in the private structure. */
22506 if (uses_apcs_26) flags |= F_APCS26;
22507 if (support_interwork) flags |= F_INTERWORK;
22508 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22509 if (pic_code) flags |= F_PIC;
22510 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22511 flags |= F_SOFT_FLOAT;
22513 switch (mfloat_abi_opt)
22515 case ARM_FLOAT_ABI_SOFT:
22516 case ARM_FLOAT_ABI_SOFTFP:
22517 flags |= F_SOFT_FLOAT;
22520 case ARM_FLOAT_ABI_HARD:
22521 if (flags & F_SOFT_FLOAT)
22522 as_bad (_("hard-float conflicts with specified fpu"));
22526 /* Using pure-endian doubles (even if soft-float). */
22527 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22528 flags |= F_VFP_FLOAT;
22530 #if defined OBJ_ELF
22531 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22532 flags |= EF_ARM_MAVERICK_FLOAT;
22535 case EF_ARM_EABI_VER4:
22536 case EF_ARM_EABI_VER5:
22537 /* No additional flags to set. */
22544 bfd_set_private_flags (stdoutput, flags);
22546 /* We have run out flags in the COFF header to encode the
22547 status of ATPCS support, so instead we create a dummy,
22548 empty, debug section called .arm.atpcs. */
22553 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22557 bfd_set_section_flags
22558 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22559 bfd_set_section_size (stdoutput, sec, 0);
22560 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22566 /* Record the CPU type as well. */
22567 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22568 mach = bfd_mach_arm_iWMMXt2;
22569 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22570 mach = bfd_mach_arm_iWMMXt;
22571 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22572 mach = bfd_mach_arm_XScale;
22573 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22574 mach = bfd_mach_arm_ep9312;
22575 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22576 mach = bfd_mach_arm_5TE;
22577 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22579 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22580 mach = bfd_mach_arm_5T;
22582 mach = bfd_mach_arm_5;
22584 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22586 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22587 mach = bfd_mach_arm_4T;
22589 mach = bfd_mach_arm_4;
22591 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22592 mach = bfd_mach_arm_3M;
22593 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22594 mach = bfd_mach_arm_3;
22595 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22596 mach = bfd_mach_arm_2a;
22597 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22598 mach = bfd_mach_arm_2;
22600 mach = bfd_mach_arm_unknown;
22602 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22605 /* Command line processing. */
22608 Invocation line includes a switch not recognized by the base assembler.
22609 See if it's a processor-specific option.
22611 This routine is somewhat complicated by the need for backwards
22612 compatibility (since older releases of gcc can't be changed).
22613 The new options try to make the interface as compatible as
22616 New options (supported) are:
22618 -mcpu=<cpu name> Assemble for selected processor
22619 -march=<architecture name> Assemble for selected architecture
22620 -mfpu=<fpu architecture> Assemble for selected FPU.
22621 -EB/-mbig-endian Big-endian
22622 -EL/-mlittle-endian Little-endian
22623 -k Generate PIC code
22624 -mthumb Start in Thumb mode
22625 -mthumb-interwork Code supports ARM/Thumb interworking
22627 -m[no-]warn-deprecated Warn about deprecated features
22629 For now we will also provide support for:
22631 -mapcs-32 32-bit Program counter
22632 -mapcs-26 26-bit Program counter
22633 -macps-float Floats passed in FP registers
22634 -mapcs-reentrant Reentrant code
22636 (sometime these will probably be replaced with -mapcs=<list of options>
22637 and -matpcs=<list of options>)
22639 The remaining options are only supported for back-wards compatibility.
22640 Cpu variants, the arm part is optional:
22641 -m[arm]1 Currently not supported.
22642 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22643 -m[arm]3 Arm 3 processor
22644 -m[arm]6[xx], Arm 6 processors
22645 -m[arm]7[xx][t][[d]m] Arm 7 processors
22646 -m[arm]8[10] Arm 8 processors
22647 -m[arm]9[20][tdmi] Arm 9 processors
22648 -mstrongarm[110[0]] StrongARM processors
22649 -mxscale XScale processors
22650 -m[arm]v[2345[t[e]]] Arm architectures
22651 -mall All (except the ARM1)
22653 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22654 -mfpe-old (No float load/store multiples)
22655 -mvfpxd VFP Single precision
22657 -mno-fpu Disable all floating point instructions
22659 The following CPU names are recognized:
22660 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22661 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22662 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22663 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22664 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22665 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22666 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22670 const char * md_shortopts = "m:k";
22672 #ifdef ARM_BI_ENDIAN
22673 #define OPTION_EB (OPTION_MD_BASE + 0)
22674 #define OPTION_EL (OPTION_MD_BASE + 1)
22676 #if TARGET_BYTES_BIG_ENDIAN
22677 #define OPTION_EB (OPTION_MD_BASE + 0)
22679 #define OPTION_EL (OPTION_MD_BASE + 1)
22682 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22684 struct option md_longopts[] =
22687 {"EB", no_argument, NULL, OPTION_EB},
22690 {"EL", no_argument, NULL, OPTION_EL},
22692 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22693 {NULL, no_argument, NULL, 0}
22696 size_t md_longopts_size = sizeof (md_longopts);
22698 struct arm_option_table
22700 char *option; /* Option name to match. */
22701 char *help; /* Help information. */
22702 int *var; /* Variable to change. */
22703 int value; /* What to change it to. */
22704 char *deprecated; /* If non-null, print this message. */
22707 struct arm_option_table arm_opts[] =
22709 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22710 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22711 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22712 &support_interwork, 1, NULL},
22713 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22714 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22715 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22717 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22718 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22719 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22720 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22723 /* These are recognized by the assembler, but have no affect on code. */
22724 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22725 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22727 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22728 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22729 &warn_on_deprecated, 0, NULL},
22730 {NULL, NULL, NULL, 0, NULL}
22733 struct arm_legacy_option_table
22735 char *option; /* Option name to match. */
22736 const arm_feature_set **var; /* Variable to change. */
22737 const arm_feature_set value; /* What to change it to. */
22738 char *deprecated; /* If non-null, print this message. */
22741 const struct arm_legacy_option_table arm_legacy_opts[] =
22743 /* DON'T add any new processors to this list -- we want the whole list
22744 to go away... Add them to the processors table instead. */
22745 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22746 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22747 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22748 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22749 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22750 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22751 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22752 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22753 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22754 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22755 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22756 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22757 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22758 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22759 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22760 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22761 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22762 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22763 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22764 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22765 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22766 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22767 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22768 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22769 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22770 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22771 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22772 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22773 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22774 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22775 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22776 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22777 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22778 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22779 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22780 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22781 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22782 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22783 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22784 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22785 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22786 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22787 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22788 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22789 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22790 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22791 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22792 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22793 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22794 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22795 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22796 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22797 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22798 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22799 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22800 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22801 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22802 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22803 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22804 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22805 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22806 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22807 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22808 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22809 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22810 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22811 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22812 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22813 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22814 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22815 N_("use -mcpu=strongarm110")},
22816 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22817 N_("use -mcpu=strongarm1100")},
22818 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22819 N_("use -mcpu=strongarm1110")},
22820 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22821 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22822 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22824 /* Architecture variants -- don't add any more to this list either. */
22825 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22826 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22827 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22828 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22829 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22830 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22831 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22832 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22833 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22834 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22835 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22836 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22837 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22838 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22839 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22840 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22841 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22842 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22844 /* Floating point variants -- don't add any more to this list either. */
22845 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22846 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22847 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22848 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22849 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22851 {NULL, NULL, ARM_ARCH_NONE, NULL}
22854 struct arm_cpu_option_table
22857 const arm_feature_set value;
22858 /* For some CPUs we assume an FPU unless the user explicitly sets
22860 const arm_feature_set default_fpu;
22861 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22863 const char *canonical_name;
22866 /* This list should, at a minimum, contain all the cpu names
22867 recognized by GCC. */
22868 static const struct arm_cpu_option_table arm_cpus[] =
22870 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22871 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22872 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22873 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22874 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22875 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22876 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22877 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22878 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22879 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22880 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22881 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22882 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22883 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22884 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22885 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22886 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22887 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22888 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22889 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22890 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22891 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22892 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22893 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22894 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22895 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22896 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22897 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22898 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22899 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22900 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22901 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22902 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22903 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22904 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22905 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22906 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22907 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22908 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22909 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22910 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22911 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22912 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22913 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22914 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22915 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22916 /* For V5 or later processors we default to using VFP; but the user
22917 should really set the FPU type explicitly. */
22918 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22919 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22920 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22921 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22922 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22923 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22924 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22925 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22926 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22927 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22928 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22929 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22930 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22931 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22932 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22933 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22934 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22935 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22936 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22937 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22938 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22939 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22940 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22941 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22942 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22943 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22944 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22945 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22946 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22947 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22948 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22949 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22950 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22951 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22952 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22953 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22954 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22955 FPU_NONE, "Cortex-A5"},
22956 {"cortex-a8", ARM_ARCH_V7A_SEC,
22957 ARM_FEATURE (0, FPU_VFP_V3
22958 | FPU_NEON_EXT_V1),
22960 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22961 ARM_FEATURE (0, FPU_VFP_V3
22962 | FPU_NEON_EXT_V1),
22964 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22965 FPU_ARCH_NEON_VFP_V4,
22967 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22968 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22970 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22971 FPU_NONE, "Cortex-R5"},
22972 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22973 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22974 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22975 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22976 /* ??? XSCALE is really an architecture. */
22977 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22978 /* ??? iwmmxt is not a processor. */
22979 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
22980 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
22981 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22983 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
22984 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
22987 struct arm_arch_option_table
22990 const arm_feature_set value;
22991 const arm_feature_set default_fpu;
22994 /* This list should, at a minimum, contain all the architecture names
22995 recognized by GCC. */
22996 static const struct arm_arch_option_table arm_archs[] =
22998 {"all", ARM_ANY, FPU_ARCH_FPA},
22999 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
23000 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
23001 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
23002 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
23003 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
23004 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
23005 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
23006 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
23007 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
23008 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
23009 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
23010 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
23011 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
23012 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
23013 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
23014 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
23015 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
23016 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
23017 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
23018 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
23019 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
23020 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
23021 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
23022 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
23023 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
23024 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
23025 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
23026 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
23027 /* The official spelling of the ARMv7 profile variants is the dashed form.
23028 Accept the non-dashed form for compatibility with old toolchains. */
23029 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23030 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23031 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23032 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23033 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23034 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23035 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
23036 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
23037 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
23038 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
23039 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23042 /* ISA extensions in the co-processor and main instruction set space. */
23043 struct arm_option_extension_value_table
23046 const arm_feature_set value;
23047 const arm_feature_set allowed_archs;
23050 /* The following table must be in alphabetical order with a NULL last entry.
23052 static const struct arm_option_extension_value_table arm_extensions[] =
23054 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23055 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23056 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
23057 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
23058 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
23059 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
23060 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23061 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
23062 ARM_FEATURE (ARM_EXT_V6M, 0)},
23063 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23064 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
23065 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23066 ARM_FEATURE (ARM_EXT_V7A, 0)},
23067 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
23068 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23071 /* ISA floating-point and Advanced SIMD extensions. */
23072 struct arm_option_fpu_value_table
23075 const arm_feature_set value;
23078 /* This list should, at a minimum, contain all the fpu names
23079 recognized by GCC. */
23080 static const struct arm_option_fpu_value_table arm_fpus[] =
23082 {"softfpa", FPU_NONE},
23083 {"fpe", FPU_ARCH_FPE},
23084 {"fpe2", FPU_ARCH_FPE},
23085 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23086 {"fpa", FPU_ARCH_FPA},
23087 {"fpa10", FPU_ARCH_FPA},
23088 {"fpa11", FPU_ARCH_FPA},
23089 {"arm7500fe", FPU_ARCH_FPA},
23090 {"softvfp", FPU_ARCH_VFP},
23091 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23092 {"vfp", FPU_ARCH_VFP_V2},
23093 {"vfp9", FPU_ARCH_VFP_V2},
23094 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23095 {"vfp10", FPU_ARCH_VFP_V2},
23096 {"vfp10-r0", FPU_ARCH_VFP_V1},
23097 {"vfpxd", FPU_ARCH_VFP_V1xD},
23098 {"vfpv2", FPU_ARCH_VFP_V2},
23099 {"vfpv3", FPU_ARCH_VFP_V3},
23100 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23101 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23102 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23103 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23104 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23105 {"arm1020t", FPU_ARCH_VFP_V1},
23106 {"arm1020e", FPU_ARCH_VFP_V2},
23107 {"arm1136jfs", FPU_ARCH_VFP_V2},
23108 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23109 {"maverick", FPU_ARCH_MAVERICK},
23110 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23111 {"neon-fp16", FPU_ARCH_NEON_FP16},
23112 {"vfpv4", FPU_ARCH_VFP_V4},
23113 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23114 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23115 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23116 {NULL, ARM_ARCH_NONE}
23119 struct arm_option_value_table
23125 static const struct arm_option_value_table arm_float_abis[] =
23127 {"hard", ARM_FLOAT_ABI_HARD},
23128 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23129 {"soft", ARM_FLOAT_ABI_SOFT},
23134 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23135 static const struct arm_option_value_table arm_eabis[] =
23137 {"gnu", EF_ARM_EABI_UNKNOWN},
23138 {"4", EF_ARM_EABI_VER4},
23139 {"5", EF_ARM_EABI_VER5},
23144 struct arm_long_option_table
23146 char * option; /* Substring to match. */
23147 char * help; /* Help information. */
23148 int (* func) (char * subopt); /* Function to decode sub-option. */
23149 char * deprecated; /* If non-null, print this message. */
23153 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23155 arm_feature_set *ext_set = (arm_feature_set *)
23156 xmalloc (sizeof (arm_feature_set));
23158 /* We insist on extensions being specified in alphabetical order, and with
23159 extensions being added before being removed. We achieve this by having
23160 the global ARM_EXTENSIONS table in alphabetical order, and using the
23161 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23162 or removing it (0) and only allowing it to change in the order
23164 const struct arm_option_extension_value_table * opt = NULL;
23165 int adding_value = -1;
23167 /* Copy the feature set, so that we can modify it. */
23168 *ext_set = **opt_p;
23171 while (str != NULL && *str != 0)
23178 as_bad (_("invalid architectural extension"));
23183 ext = strchr (str, '+');
23186 optlen = ext - str;
23188 optlen = strlen (str);
23191 && strncmp (str, "no", 2) == 0)
23193 if (adding_value != 0)
23196 opt = arm_extensions;
23202 else if (optlen > 0)
23204 if (adding_value == -1)
23207 opt = arm_extensions;
23209 else if (adding_value != 1)
23211 as_bad (_("must specify extensions to add before specifying "
23212 "those to remove"));
23219 as_bad (_("missing architectural extension"));
23223 gas_assert (adding_value != -1);
23224 gas_assert (opt != NULL);
23226 /* Scan over the options table trying to find an exact match. */
23227 for (; opt->name != NULL; opt++)
23228 if (strncmp (opt->name, str, optlen) == 0
23229 && strlen (opt->name) == optlen)
23231 /* Check we can apply the extension to this architecture. */
23232 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23234 as_bad (_("extension does not apply to the base architecture"));
23238 /* Add or remove the extension. */
23240 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23242 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23247 if (opt->name == NULL)
23249 /* Did we fail to find an extension because it wasn't specified in
23250 alphabetical order, or because it does not exist? */
23252 for (opt = arm_extensions; opt->name != NULL; opt++)
23253 if (strncmp (opt->name, str, optlen) == 0)
23256 if (opt->name == NULL)
23257 as_bad (_("unknown architectural extension `%s'"), str);
23259 as_bad (_("architectural extensions must be specified in "
23260 "alphabetical order"));
23266 /* We should skip the extension we've just matched the next time
23278 arm_parse_cpu (char * str)
23280 const struct arm_cpu_option_table * opt;
23281 char * ext = strchr (str, '+');
23285 optlen = ext - str;
23287 optlen = strlen (str);
23291 as_bad (_("missing cpu name `%s'"), str);
23295 for (opt = arm_cpus; opt->name != NULL; opt++)
23296 if (strncmp (opt->name, str, optlen) == 0)
23298 mcpu_cpu_opt = &opt->value;
23299 mcpu_fpu_opt = &opt->default_fpu;
23300 if (opt->canonical_name)
23301 strcpy (selected_cpu_name, opt->canonical_name);
23306 for (i = 0; i < optlen; i++)
23307 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23308 selected_cpu_name[i] = 0;
23312 return arm_parse_extension (ext, &mcpu_cpu_opt);
23317 as_bad (_("unknown cpu `%s'"), str);
23322 arm_parse_arch (char * str)
23324 const struct arm_arch_option_table *opt;
23325 char *ext = strchr (str, '+');
23329 optlen = ext - str;
23331 optlen = strlen (str);
23335 as_bad (_("missing architecture name `%s'"), str);
23339 for (opt = arm_archs; opt->name != NULL; opt++)
23340 if (strncmp (opt->name, str, optlen) == 0)
23342 march_cpu_opt = &opt->value;
23343 march_fpu_opt = &opt->default_fpu;
23344 strcpy (selected_cpu_name, opt->name);
23347 return arm_parse_extension (ext, &march_cpu_opt);
23352 as_bad (_("unknown architecture `%s'\n"), str);
23357 arm_parse_fpu (char * str)
23359 const struct arm_option_fpu_value_table * opt;
23361 for (opt = arm_fpus; opt->name != NULL; opt++)
23362 if (streq (opt->name, str))
23364 mfpu_opt = &opt->value;
23368 as_bad (_("unknown floating point format `%s'\n"), str);
23373 arm_parse_float_abi (char * str)
23375 const struct arm_option_value_table * opt;
23377 for (opt = arm_float_abis; opt->name != NULL; opt++)
23378 if (streq (opt->name, str))
23380 mfloat_abi_opt = opt->value;
23384 as_bad (_("unknown floating point abi `%s'\n"), str);
23390 arm_parse_eabi (char * str)
23392 const struct arm_option_value_table *opt;
23394 for (opt = arm_eabis; opt->name != NULL; opt++)
23395 if (streq (opt->name, str))
23397 meabi_flags = opt->value;
23400 as_bad (_("unknown EABI `%s'\n"), str);
23406 arm_parse_it_mode (char * str)
23408 bfd_boolean ret = TRUE;
23410 if (streq ("arm", str))
23411 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23412 else if (streq ("thumb", str))
23413 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23414 else if (streq ("always", str))
23415 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23416 else if (streq ("never", str))
23417 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23420 as_bad (_("unknown implicit IT mode `%s', should be "\
23421 "arm, thumb, always, or never."), str);
23428 struct arm_long_option_table arm_long_opts[] =
23430 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23431 arm_parse_cpu, NULL},
23432 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23433 arm_parse_arch, NULL},
23434 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23435 arm_parse_fpu, NULL},
23436 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23437 arm_parse_float_abi, NULL},
23439 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23440 arm_parse_eabi, NULL},
23442 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23443 arm_parse_it_mode, NULL},
23444 {NULL, NULL, 0, NULL}
23448 md_parse_option (int c, char * arg)
23450 struct arm_option_table *opt;
23451 const struct arm_legacy_option_table *fopt;
23452 struct arm_long_option_table *lopt;
23458 target_big_endian = 1;
23464 target_big_endian = 0;
23468 case OPTION_FIX_V4BX:
23473 /* Listing option. Just ignore these, we don't support additional
23478 for (opt = arm_opts; opt->option != NULL; opt++)
23480 if (c == opt->option[0]
23481 && ((arg == NULL && opt->option[1] == 0)
23482 || streq (arg, opt->option + 1)))
23484 /* If the option is deprecated, tell the user. */
23485 if (warn_on_deprecated && opt->deprecated != NULL)
23486 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23487 arg ? arg : "", _(opt->deprecated));
23489 if (opt->var != NULL)
23490 *opt->var = opt->value;
23496 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23498 if (c == fopt->option[0]
23499 && ((arg == NULL && fopt->option[1] == 0)
23500 || streq (arg, fopt->option + 1)))
23502 /* If the option is deprecated, tell the user. */
23503 if (warn_on_deprecated && fopt->deprecated != NULL)
23504 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23505 arg ? arg : "", _(fopt->deprecated));
23507 if (fopt->var != NULL)
23508 *fopt->var = &fopt->value;
23514 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23516 /* These options are expected to have an argument. */
23517 if (c == lopt->option[0]
23519 && strncmp (arg, lopt->option + 1,
23520 strlen (lopt->option + 1)) == 0)
23522 /* If the option is deprecated, tell the user. */
23523 if (warn_on_deprecated && lopt->deprecated != NULL)
23524 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23525 _(lopt->deprecated));
23527 /* Call the sup-option parser. */
23528 return lopt->func (arg + strlen (lopt->option) - 1);
23539 md_show_usage (FILE * fp)
23541 struct arm_option_table *opt;
23542 struct arm_long_option_table *lopt;
23544 fprintf (fp, _(" ARM-specific assembler options:\n"));
23546 for (opt = arm_opts; opt->option != NULL; opt++)
23547 if (opt->help != NULL)
23548 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23550 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23551 if (lopt->help != NULL)
23552 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23556 -EB assemble code for a big-endian cpu\n"));
23561 -EL assemble code for a little-endian cpu\n"));
23565 --fix-v4bx Allow BX in ARMv4 code\n"));
23573 arm_feature_set flags;
23574 } cpu_arch_ver_table;
23576 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23577 least features first. */
23578 static const cpu_arch_ver_table cpu_arch_ver[] =
23584 {4, ARM_ARCH_V5TE},
23585 {5, ARM_ARCH_V5TEJ},
23589 {11, ARM_ARCH_V6M},
23590 {12, ARM_ARCH_V6SM},
23591 {8, ARM_ARCH_V6T2},
23592 {10, ARM_ARCH_V7A},
23593 {10, ARM_ARCH_V7R},
23594 {10, ARM_ARCH_V7M},
23598 /* Set an attribute if it has not already been set by the user. */
23600 aeabi_set_attribute_int (int tag, int value)
23603 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23604 || !attributes_set_explicitly[tag])
23605 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23609 aeabi_set_attribute_string (int tag, const char *value)
23612 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23613 || !attributes_set_explicitly[tag])
23614 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23617 /* Set the public EABI object attributes. */
23619 aeabi_set_public_attributes (void)
23623 arm_feature_set flags;
23624 arm_feature_set tmp;
23625 const cpu_arch_ver_table *p;
23627 /* Choose the architecture based on the capabilities of the requested cpu
23628 (if any) and/or the instructions actually used. */
23629 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23630 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23631 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23632 /*Allow the user to override the reported architecture. */
23635 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23636 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23639 /* We need to make sure that the attributes do not identify us as v6S-M
23640 when the only v6S-M feature in use is the Operating System Extensions. */
23641 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23642 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23643 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23647 for (p = cpu_arch_ver; p->val; p++)
23649 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23652 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23656 /* The table lookup above finds the last architecture to contribute
23657 a new feature. Unfortunately, Tag13 is a subset of the union of
23658 v6T2 and v7-M, so it is never seen as contributing a new feature.
23659 We can not search for the last entry which is entirely used,
23660 because if no CPU is specified we build up only those flags
23661 actually used. Perhaps we should separate out the specified
23662 and implicit cases. Avoid taking this path for -march=all by
23663 checking for contradictory v7-A / v7-M features. */
23665 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23666 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23667 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23670 /* Tag_CPU_name. */
23671 if (selected_cpu_name[0])
23675 q = selected_cpu_name;
23676 if (strncmp (q, "armv", 4) == 0)
23681 for (i = 0; q[i]; i++)
23682 q[i] = TOUPPER (q[i]);
23684 aeabi_set_attribute_string (Tag_CPU_name, q);
23687 /* Tag_CPU_arch. */
23688 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23690 /* Tag_CPU_arch_profile. */
23691 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23692 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23693 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23694 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23695 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23696 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23698 /* Tag_ARM_ISA_use. */
23699 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23701 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23703 /* Tag_THUMB_ISA_use. */
23704 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23706 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23707 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23709 /* Tag_VFP_arch. */
23710 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23711 aeabi_set_attribute_int (Tag_VFP_arch,
23712 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23714 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23715 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23716 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23717 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23718 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23719 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23720 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23721 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23722 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23724 /* Tag_ABI_HardFP_use. */
23725 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23726 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23727 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23729 /* Tag_WMMX_arch. */
23730 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23731 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23732 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23733 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23735 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23736 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23737 aeabi_set_attribute_int
23738 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23741 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23742 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23743 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23746 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23747 aeabi_set_attribute_int (Tag_DIV_use, 2);
23748 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23749 aeabi_set_attribute_int (Tag_DIV_use, 0);
23751 aeabi_set_attribute_int (Tag_DIV_use, 1);
23753 /* Tag_MP_extension_use. */
23754 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23755 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23757 /* Tag Virtualization_use. */
23758 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23760 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23763 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23766 /* Add the default contents for the .ARM.attributes section. */
23770 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23773 aeabi_set_public_attributes ();
23775 #endif /* OBJ_ELF */
23778 /* Parse a .cpu directive. */
23781 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23783 const struct arm_cpu_option_table *opt;
23787 name = input_line_pointer;
23788 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23789 input_line_pointer++;
23790 saved_char = *input_line_pointer;
23791 *input_line_pointer = 0;
23793 /* Skip the first "all" entry. */
23794 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23795 if (streq (opt->name, name))
23797 mcpu_cpu_opt = &opt->value;
23798 selected_cpu = opt->value;
23799 if (opt->canonical_name)
23800 strcpy (selected_cpu_name, opt->canonical_name);
23804 for (i = 0; opt->name[i]; i++)
23805 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23806 selected_cpu_name[i] = 0;
23808 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23809 *input_line_pointer = saved_char;
23810 demand_empty_rest_of_line ();
23813 as_bad (_("unknown cpu `%s'"), name);
23814 *input_line_pointer = saved_char;
23815 ignore_rest_of_line ();
23819 /* Parse a .arch directive. */
23822 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23824 const struct arm_arch_option_table *opt;
23828 name = input_line_pointer;
23829 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23830 input_line_pointer++;
23831 saved_char = *input_line_pointer;
23832 *input_line_pointer = 0;
23834 /* Skip the first "all" entry. */
23835 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23836 if (streq (opt->name, name))
23838 mcpu_cpu_opt = &opt->value;
23839 selected_cpu = opt->value;
23840 strcpy (selected_cpu_name, opt->name);
23841 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23842 *input_line_pointer = saved_char;
23843 demand_empty_rest_of_line ();
23847 as_bad (_("unknown architecture `%s'\n"), name);
23848 *input_line_pointer = saved_char;
23849 ignore_rest_of_line ();
23853 /* Parse a .object_arch directive. */
23856 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23858 const struct arm_arch_option_table *opt;
23862 name = input_line_pointer;
23863 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23864 input_line_pointer++;
23865 saved_char = *input_line_pointer;
23866 *input_line_pointer = 0;
23868 /* Skip the first "all" entry. */
23869 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23870 if (streq (opt->name, name))
23872 object_arch = &opt->value;
23873 *input_line_pointer = saved_char;
23874 demand_empty_rest_of_line ();
23878 as_bad (_("unknown architecture `%s'\n"), name);
23879 *input_line_pointer = saved_char;
23880 ignore_rest_of_line ();
23883 /* Parse a .arch_extension directive. */
23886 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23888 const struct arm_option_extension_value_table *opt;
23891 int adding_value = 1;
23893 name = input_line_pointer;
23894 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23895 input_line_pointer++;
23896 saved_char = *input_line_pointer;
23897 *input_line_pointer = 0;
23899 if (strlen (name) >= 2
23900 && strncmp (name, "no", 2) == 0)
23906 for (opt = arm_extensions; opt->name != NULL; opt++)
23907 if (streq (opt->name, name))
23909 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23911 as_bad (_("architectural extension `%s' is not allowed for the "
23912 "current base architecture"), name);
23917 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23919 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23921 mcpu_cpu_opt = &selected_cpu;
23922 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23923 *input_line_pointer = saved_char;
23924 demand_empty_rest_of_line ();
23928 if (opt->name == NULL)
23929 as_bad (_("unknown architecture `%s'\n"), name);
23931 *input_line_pointer = saved_char;
23932 ignore_rest_of_line ();
23935 /* Parse a .fpu directive. */
23938 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23940 const struct arm_option_fpu_value_table *opt;
23944 name = input_line_pointer;
23945 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23946 input_line_pointer++;
23947 saved_char = *input_line_pointer;
23948 *input_line_pointer = 0;
23950 for (opt = arm_fpus; opt->name != NULL; opt++)
23951 if (streq (opt->name, name))
23953 mfpu_opt = &opt->value;
23954 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23955 *input_line_pointer = saved_char;
23956 demand_empty_rest_of_line ();
23960 as_bad (_("unknown floating point format `%s'\n"), name);
23961 *input_line_pointer = saved_char;
23962 ignore_rest_of_line ();
23965 /* Copy symbol information. */
23968 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23970 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23974 /* Given a symbolic attribute NAME, return the proper integer value.
23975 Returns -1 if the attribute is not known. */
23978 arm_convert_symbolic_attribute (const char *name)
23980 static const struct
23985 attribute_table[] =
23987 /* When you modify this table you should
23988 also modify the list in doc/c-arm.texi. */
23989 #define T(tag) {#tag, tag}
23990 T (Tag_CPU_raw_name),
23993 T (Tag_CPU_arch_profile),
23994 T (Tag_ARM_ISA_use),
23995 T (Tag_THUMB_ISA_use),
23999 T (Tag_Advanced_SIMD_arch),
24000 T (Tag_PCS_config),
24001 T (Tag_ABI_PCS_R9_use),
24002 T (Tag_ABI_PCS_RW_data),
24003 T (Tag_ABI_PCS_RO_data),
24004 T (Tag_ABI_PCS_GOT_use),
24005 T (Tag_ABI_PCS_wchar_t),
24006 T (Tag_ABI_FP_rounding),
24007 T (Tag_ABI_FP_denormal),
24008 T (Tag_ABI_FP_exceptions),
24009 T (Tag_ABI_FP_user_exceptions),
24010 T (Tag_ABI_FP_number_model),
24011 T (Tag_ABI_align_needed),
24012 T (Tag_ABI_align8_needed),
24013 T (Tag_ABI_align_preserved),
24014 T (Tag_ABI_align8_preserved),
24015 T (Tag_ABI_enum_size),
24016 T (Tag_ABI_HardFP_use),
24017 T (Tag_ABI_VFP_args),
24018 T (Tag_ABI_WMMX_args),
24019 T (Tag_ABI_optimization_goals),
24020 T (Tag_ABI_FP_optimization_goals),
24021 T (Tag_compatibility),
24022 T (Tag_CPU_unaligned_access),
24023 T (Tag_FP_HP_extension),
24024 T (Tag_VFP_HP_extension),
24025 T (Tag_ABI_FP_16bit_format),
24026 T (Tag_MPextension_use),
24028 T (Tag_nodefaults),
24029 T (Tag_also_compatible_with),
24030 T (Tag_conformance),
24032 T (Tag_Virtualization_use),
24033 /* We deliberately do not include Tag_MPextension_use_legacy. */
24041 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24042 if (streq (name, attribute_table[i].name))
24043 return attribute_table[i].tag;
24049 /* Apply sym value for relocations only in the case that
24050 they are for local symbols and you have the respective
24051 architectural feature for blx and simple switches. */
24053 arm_apply_sym_value (struct fix * fixP)
24056 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24057 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24059 switch (fixP->fx_r_type)
24061 case BFD_RELOC_ARM_PCREL_BLX:
24062 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24063 if (ARM_IS_FUNC (fixP->fx_addsy))
24067 case BFD_RELOC_ARM_PCREL_CALL:
24068 case BFD_RELOC_THUMB_PCREL_BLX:
24069 if (THUMB_IS_FUNC (fixP->fx_addsy))
24080 #endif /* OBJ_ELF */