1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* ??? This is currently unused. */
41 #define internalError() \
42 as_fatal (_("ARM Internal Error, line %d, %s"), __LINE__, __FILE__)
44 #define internalError() as_fatal (_("ARM Internal Error"))
47 /* Types of processor to assemble for. */
48 #define ARM_1 0x00000001
49 #define ARM_2 0x00000002
50 #define ARM_3 0x00000004
52 #define ARM_6 0x00000008
53 #define ARM_7 ARM_6 /* same core instruction set */
54 #define ARM_CPU_MASK 0x0000000f
56 /* The following bitmasks control CPU extensions (ARM7 onwards): */
57 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
58 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
59 #define ARM_THUMB 0x00000040 /* allow BX instruction */
61 #define ARM_ARCHv4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP 0x00fffffe
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCHv4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
93 static int target_oabi = 0;
95 #if defined OBJ_COFF || defined OBJ_ELF
96 /* Flags stored in private area of BFD structure */
97 static boolean uses_apcs_26 = false;
98 static boolean support_interwork = false;
99 static boolean uses_apcs_float = false;
100 static boolean pic_code = false;
103 /* This array holds the chars that always start a comment. If the
104 pre-processor is disabled, these aren't very useful */
105 CONST char comment_chars[] = "@";
107 /* This array holds the chars that only start a comment at the beginning of
108 a line. If the line seems to have the form '# 123 filename'
109 .line and .file directives will appear in the pre-processed output */
110 /* Note that input_file.c hand checks for '#' at the beginning of the
111 first line of the input file. This is because the compiler outputs
112 #NO_APP at the beginning of its output. */
113 /* Also note that comments like this one will always work. */
114 CONST char line_comment_chars[] = "#";
116 CONST char line_separator_chars[] = "";
118 /* Chars that can be used to separate mant from exp in floating point nums */
119 CONST char EXP_CHARS[] = "eE";
121 /* Chars that mean this number is a floating point constant */
125 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
127 CONST int md_reloc_size = 8; /* Size of relocation record */
129 static int thumb_mode = 0; /* non-zero if assembling thumb instructions */
131 typedef struct arm_fix
139 unsigned long instruction;
144 bfd_reloc_code_real_type type;
154 CONST char *template;
158 static CONST struct asm_shift shift[] =
174 #define NO_SHIFT_RESTRICT 1
175 #define SHIFT_RESTRICT 0
177 #define NUM_FLOAT_VALS 8
179 CONST char *fp_const[] =
181 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
184 /* Number of littlenums required to hold an extended precision number */
185 #define MAX_LITTLENUMS 6
187 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
197 #define CP_T_X 0x00008000
198 #define CP_T_Y 0x00400000
199 #define CP_T_Pre 0x01000000
200 #define CP_T_UD 0x00800000
201 #define CP_T_WB 0x00200000
203 #define CONDS_BIT (0x00100000)
204 #define LOAD_BIT (0x00100000)
205 #define TRANS_BIT (0x00200000)
209 CONST char *template;
213 /* This is to save a hash look-up in the common case */
214 #define COND_ALWAYS 0xe0000000
216 static CONST struct asm_cond conds[] =
220 {"cs", 0x20000000}, {"hs", 0x20000000},
221 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
236 /* Warning: If the top bit of the set_bits is set, then the standard
237 instruction bitmask is ignored, and the new bitmask is taken from
241 CONST char *template; /* Basic flag string */
242 unsigned long set_bits; /* Bits to set */
245 static CONST struct asm_flg s_flag[] =
251 static CONST struct asm_flg ldr_flags[] =
255 {"bt", 0x00400000 | TRANS_BIT},
262 static CONST struct asm_flg str_flags[] =
266 {"bt", 0x00400000 | TRANS_BIT},
271 static CONST struct asm_flg byte_flag[] =
277 static CONST struct asm_flg cmp_flags[] =
284 static CONST struct asm_flg ldm_flags[] =
297 static CONST struct asm_flg stm_flags[] =
310 static CONST struct asm_flg lfm_flags[] =
317 static CONST struct asm_flg sfm_flags[] =
324 static CONST struct asm_flg round_flags[] =
332 /* The implementation of the FIX instruction is broken on some assemblers,
333 in that it accepts a precision specifier as well as a rounding specifier,
334 despite the fact that this is meaningless. To be more compatible, we
335 accept it as well, though of course it does not set any bits. */
336 static CONST struct asm_flg fix_flags[] =
353 static CONST struct asm_flg except_flag[] =
359 static CONST struct asm_flg cplong_flag[] =
367 CONST char *template;
368 unsigned long number;
371 #define PSR_FIELD_MASK 0x000f0000
373 #define PSR_FLAGS 0x00080000
374 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
375 #define PSR_ALL 0x00090000
384 static CONST struct asm_psr psrs[] =
388 {"cpsr_all", CPSR_ALL},
390 {"spsr_all", SPSR_ALL},
393 {"cpsr_flg", CPSR_FLG},
394 {"spsr_flg", SPSR_FLG},
397 {"cpsr_c", CPSR_CTL},
398 {"cpsr_ctl", CPSR_CTL},
399 {"spsr_c", SPSR_CTL},
400 {"spsr_ctl", SPSR_CTL}
403 /* Functions called by parser */
404 /* ARM instructions */
405 static void do_arit PARAMS ((char *operands, unsigned long flags));
406 static void do_cmp PARAMS ((char *operands, unsigned long flags));
407 static void do_mov PARAMS ((char *operands, unsigned long flags));
408 static void do_ldst PARAMS ((char *operands, unsigned long flags));
409 static void do_ldmstm PARAMS ((char *operands, unsigned long flags));
410 static void do_branch PARAMS ((char *operands, unsigned long flags));
411 static void do_swi PARAMS ((char *operands, unsigned long flags));
412 /* Pseudo Op codes */
413 static void do_adr PARAMS ((char *operands, unsigned long flags));
414 static void do_nop PARAMS ((char *operands, unsigned long flags));
416 static void do_mul PARAMS ((char *operands, unsigned long flags));
417 static void do_mla PARAMS ((char *operands, unsigned long flags));
419 static void do_swap PARAMS ((char *operands, unsigned long flags));
421 static void do_msr PARAMS ((char *operands, unsigned long flags));
422 static void do_mrs PARAMS ((char *operands, unsigned long flags));
424 static void do_mull PARAMS ((char *operands, unsigned long flags));
426 static void do_bx PARAMS ((char *operands, unsigned long flags));
428 /* Coprocessor Instructions */
429 static void do_cdp PARAMS ((char *operands, unsigned long flags));
430 static void do_lstc PARAMS ((char *operands, unsigned long flags));
431 static void do_co_reg PARAMS ((char *operands, unsigned long flags));
432 static void do_fp_ctrl PARAMS ((char *operands, unsigned long flags));
433 static void do_fp_ldst PARAMS ((char *operands, unsigned long flags));
434 static void do_fp_ldmstm PARAMS ((char *operands, unsigned long flags));
435 static void do_fp_dyadic PARAMS ((char *operands, unsigned long flags));
436 static void do_fp_monadic PARAMS ((char *operands, unsigned long flags));
437 static void do_fp_cmp PARAMS ((char *operands, unsigned long flags));
438 static void do_fp_from_reg PARAMS ((char *operands, unsigned long flags));
439 static void do_fp_to_reg PARAMS ((char *operands, unsigned long flags));
441 static void fix_new_arm PARAMS ((fragS *frag, int where,
442 short int size, expressionS *exp,
443 int pc_rel, int reloc));
444 static int arm_reg_parse PARAMS ((char **ccp));
445 static int arm_psr_parse PARAMS ((char **ccp));
446 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT,
448 static int add_to_lit_pool PARAMS ((void));
449 static unsigned validate_immediate PARAMS ((unsigned));
450 static int validate_offset_imm PARAMS ((int, int));
451 static void opcode_select PARAMS ((int));
452 static void end_of_line PARAMS ((char *));
453 static int reg_required_here PARAMS ((char **, int));
454 static int psr_required_here PARAMS ((char **, int, int));
455 static int co_proc_number PARAMS ((char **));
456 static int cp_opc_expr PARAMS ((char **, int, int));
457 static int cp_reg_required_here PARAMS ((char **, int));
458 static int fp_reg_required_here PARAMS ((char **, int));
459 static int cp_address_offset PARAMS ((char **));
460 static int cp_address_required_here PARAMS ((char **));
461 static int my_get_float_expression PARAMS ((char **));
462 static int skip_past_comma PARAMS ((char **));
463 static int walk_no_bignums PARAMS ((symbolS *));
464 static int negate_data_op PARAMS ((unsigned long *,
466 static int data_op2 PARAMS ((char **));
467 static int fp_op2 PARAMS ((char **));
468 static long reg_list PARAMS ((char **));
469 static void thumb_load_store PARAMS ((char *, int, int));
470 static int decode_shift PARAMS ((char **, int));
471 static int ldst_extend PARAMS ((char **, int));
472 static void thumb_add_sub PARAMS ((char *, int));
473 static void insert_reg PARAMS ((int));
474 static void thumb_shift PARAMS ((char *, int));
475 static void thumb_mov_compare PARAMS ((char *, int));
476 static void set_constant_flonums PARAMS ((void));
477 static valueT md_chars_to_number PARAMS ((char *, int));
478 static void insert_reg_alias PARAMS ((char *, int));
479 static void output_inst PARAMS ((char *));
481 /* ARM instructions take 4bytes in the object file, Thumb instructions
485 /* LONGEST_INST is the longest basic instruction name without conditions or
487 * ARM7M has 4 of length 5
490 #define LONGEST_INST 5
494 CONST char *template; /* Basic string to match */
495 unsigned long value; /* Basic instruction code */
496 CONST char *comp_suffix; /* Compulsory suffix that must follow conds */
497 CONST struct asm_flg *flags; /* Bits to toggle if flag 'n' set */
498 unsigned long variants; /* Which CPU variants this exists for */
499 /* Function to call to parse args */
500 void (*parms) PARAMS ((char *, unsigned long));
503 static CONST struct asm_opcode insns[] =
505 /* ARM Instructions */
506 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
507 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
508 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
509 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
510 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
511 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
512 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
513 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
514 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
515 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
516 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
517 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
518 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
519 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
520 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
521 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
522 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
523 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
524 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
525 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
526 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
527 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
528 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
531 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
532 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
534 /* ARM 2 multiplies */
535 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
536 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
538 /* ARM 3 - swp instructions */
539 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
541 /* ARM 6 Coprocessor instructions */
542 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
543 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
545 /* ARM 7M long multiplies - need signed/unsigned flags! */
546 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
547 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
548 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
549 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
551 /* ARM THUMB interworking */
552 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
554 /* Floating point instructions */
555 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
556 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
557 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
558 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
559 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
560 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
561 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
562 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
563 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
564 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
565 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
566 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
567 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
568 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
569 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
570 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
571 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
572 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
573 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
574 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
575 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
576 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
577 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
578 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
579 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
580 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
581 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
582 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
583 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
584 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
585 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
586 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
587 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
588 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
589 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
590 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
591 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
592 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
593 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
594 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
595 be an optional suffix, but part of the instruction. To be compatible,
597 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
598 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
599 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
600 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
602 /* Generic copressor instructions */
603 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
604 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
605 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
606 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
607 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
610 /* defines for various bits that we will want to toggle */
612 #define INST_IMMEDIATE 0x02000000
613 #define OFFSET_REG 0x02000000
614 #define HWOFFSET_IMM 0x00400000
615 #define SHIFT_BY_REG 0x00000010
616 #define PRE_INDEX 0x01000000
617 #define INDEX_UP 0x00800000
618 #define WRITE_BACK 0x00200000
619 #define MULTI_SET_PSR 0x00400000
621 #define LITERAL_MASK 0xf000f000
622 #define COND_MASK 0xf0000000
623 #define OPCODE_MASK 0xfe1fffff
624 #define DATA_OP_SHIFT 21
626 /* Codes to distinguish the arithmetic instructions */
638 #define OPCODE_CMP 10
639 #define OPCODE_CMN 11
640 #define OPCODE_ORR 12
641 #define OPCODE_MOV 13
642 #define OPCODE_BIC 14
643 #define OPCODE_MVN 15
645 static void do_t_nop PARAMS ((char *operands));
646 static void do_t_arit PARAMS ((char *operands));
647 static void do_t_add PARAMS ((char *operands));
648 static void do_t_asr PARAMS ((char *operands));
649 static void do_t_branch9 PARAMS ((char *operands));
650 static void do_t_branch12 PARAMS ((char *operands));
651 static void do_t_branch23 PARAMS ((char *operands));
652 static void do_t_bx PARAMS ((char *operands));
653 static void do_t_compare PARAMS ((char *operands));
654 static void do_t_ldmstm PARAMS ((char *operands));
655 static void do_t_ldr PARAMS ((char *operands));
656 static void do_t_ldrb PARAMS ((char *operands));
657 static void do_t_ldrh PARAMS ((char *operands));
658 static void do_t_lds PARAMS ((char *operands));
659 static void do_t_lsl PARAMS ((char *operands));
660 static void do_t_lsr PARAMS ((char *operands));
661 static void do_t_mov PARAMS ((char *operands));
662 static void do_t_push_pop PARAMS ((char *operands));
663 static void do_t_str PARAMS ((char *operands));
664 static void do_t_strb PARAMS ((char *operands));
665 static void do_t_strh PARAMS ((char *operands));
666 static void do_t_sub PARAMS ((char *operands));
667 static void do_t_swi PARAMS ((char *operands));
668 static void do_t_adr PARAMS ((char *operands));
670 #define T_OPCODE_MUL 0x4340
671 #define T_OPCODE_TST 0x4200
672 #define T_OPCODE_CMN 0x42c0
673 #define T_OPCODE_NEG 0x4240
674 #define T_OPCODE_MVN 0x43c0
676 #define T_OPCODE_ADD_R3 0x1800
677 #define T_OPCODE_SUB_R3 0x1a00
678 #define T_OPCODE_ADD_HI 0x4400
679 #define T_OPCODE_ADD_ST 0xb000
680 #define T_OPCODE_SUB_ST 0xb080
681 #define T_OPCODE_ADD_SP 0xa800
682 #define T_OPCODE_ADD_PC 0xa000
683 #define T_OPCODE_ADD_I8 0x3000
684 #define T_OPCODE_SUB_I8 0x3800
685 #define T_OPCODE_ADD_I3 0x1c00
686 #define T_OPCODE_SUB_I3 0x1e00
688 #define T_OPCODE_ASR_R 0x4100
689 #define T_OPCODE_LSL_R 0x4080
690 #define T_OPCODE_LSR_R 0x40c0
691 #define T_OPCODE_ASR_I 0x1000
692 #define T_OPCODE_LSL_I 0x0000
693 #define T_OPCODE_LSR_I 0x0800
695 #define T_OPCODE_MOV_I8 0x2000
696 #define T_OPCODE_CMP_I8 0x2800
697 #define T_OPCODE_CMP_LR 0x4280
698 #define T_OPCODE_MOV_HR 0x4600
699 #define T_OPCODE_CMP_HR 0x4500
701 #define T_OPCODE_LDR_PC 0x4800
702 #define T_OPCODE_LDR_SP 0x9800
703 #define T_OPCODE_STR_SP 0x9000
704 #define T_OPCODE_LDR_IW 0x6800
705 #define T_OPCODE_STR_IW 0x6000
706 #define T_OPCODE_LDR_IH 0x8800
707 #define T_OPCODE_STR_IH 0x8000
708 #define T_OPCODE_LDR_IB 0x7800
709 #define T_OPCODE_STR_IB 0x7000
710 #define T_OPCODE_LDR_RW 0x5800
711 #define T_OPCODE_STR_RW 0x5000
712 #define T_OPCODE_LDR_RH 0x5a00
713 #define T_OPCODE_STR_RH 0x5200
714 #define T_OPCODE_LDR_RB 0x5c00
715 #define T_OPCODE_STR_RB 0x5400
717 #define T_OPCODE_PUSH 0xb400
718 #define T_OPCODE_POP 0xbc00
720 #define T_OPCODE_BRANCH 0xe7fe
722 static int thumb_reg PARAMS ((char **str, int hi_lo));
724 #define THUMB_SIZE 2 /* Size of thumb instruction */
725 #define THUMB_REG_LO 0x1
726 #define THUMB_REG_HI 0x2
727 #define THUMB_REG_ANY 0x3
729 #define THUMB_H1 0x0080
730 #define THUMB_H2 0x0040
737 #define THUMB_COMPARE 1
740 #define THUMB_STORE 1
742 #define THUMB_PP_PC_LR 0x0100
744 /* These three are used for immediate shifts, do not alter */
746 #define THUMB_HALFWORD 1
751 CONST char *template; /* Basic string to match */
752 unsigned long value; /* Basic instruction code */
754 /* Function to call to parse args */
755 void (*parms) PARAMS ((char *));
758 static CONST struct thumb_opcode tinsns[] =
760 {"adc", 0x4140, 2, do_t_arit},
761 {"add", 0x0000, 2, do_t_add},
762 {"and", 0x4000, 2, do_t_arit},
763 {"asr", 0x0000, 2, do_t_asr},
764 {"b", T_OPCODE_BRANCH, 2, do_t_branch12},
765 {"beq", 0xd0fe, 2, do_t_branch9},
766 {"bne", 0xd1fe, 2, do_t_branch9},
767 {"bcs", 0xd2fe, 2, do_t_branch9},
768 {"bhs", 0xd2fe, 2, do_t_branch9},
769 {"bcc", 0xd3fe, 2, do_t_branch9},
770 {"bul", 0xd3fe, 2, do_t_branch9},
771 {"blo", 0xd3fe, 2, do_t_branch9},
772 {"bmi", 0xd4fe, 2, do_t_branch9},
773 {"bpl", 0xd5fe, 2, do_t_branch9},
774 {"bvs", 0xd6fe, 2, do_t_branch9},
775 {"bvc", 0xd7fe, 2, do_t_branch9},
776 {"bhi", 0xd8fe, 2, do_t_branch9},
777 {"bls", 0xd9fe, 2, do_t_branch9},
778 {"bge", 0xdafe, 2, do_t_branch9},
779 {"blt", 0xdbfe, 2, do_t_branch9},
780 {"bgt", 0xdcfe, 2, do_t_branch9},
781 {"ble", 0xddfe, 2, do_t_branch9},
782 {"bic", 0x4380, 2, do_t_arit},
783 {"bl", 0xf7fffffe, 4, do_t_branch23},
784 {"bx", 0x4700, 2, do_t_bx},
785 {"cmn", T_OPCODE_CMN, 2, do_t_arit},
786 {"cmp", 0x0000, 2, do_t_compare},
787 {"eor", 0x4040, 2, do_t_arit},
788 {"ldmia", 0xc800, 2, do_t_ldmstm},
789 {"ldr", 0x0000, 2, do_t_ldr},
790 {"ldrb", 0x0000, 2, do_t_ldrb},
791 {"ldrh", 0x0000, 2, do_t_ldrh},
792 {"ldrsb", 0x5600, 2, do_t_lds},
793 {"ldrsh", 0x5e00, 2, do_t_lds},
794 {"ldsb", 0x5600, 2, do_t_lds},
795 {"ldsh", 0x5e00, 2, do_t_lds},
796 {"lsl", 0x0000, 2, do_t_lsl},
797 {"lsr", 0x0000, 2, do_t_lsr},
798 {"mov", 0x0000, 2, do_t_mov},
799 {"mul", T_OPCODE_MUL, 2, do_t_arit},
800 {"mvn", T_OPCODE_MVN, 2, do_t_arit},
801 {"neg", T_OPCODE_NEG, 2, do_t_arit},
802 {"orr", 0x4300, 2, do_t_arit},
803 {"pop", 0xbc00, 2, do_t_push_pop},
804 {"push", 0xb400, 2, do_t_push_pop},
805 {"ror", 0x41c0, 2, do_t_arit},
806 {"sbc", 0x4180, 2, do_t_arit},
807 {"stmia", 0xc000, 2, do_t_ldmstm},
808 {"str", 0x0000, 2, do_t_str},
809 {"strb", 0x0000, 2, do_t_strb},
810 {"strh", 0x0000, 2, do_t_strh},
811 {"swi", 0xdf00, 2, do_t_swi},
812 {"sub", 0x0000, 2, do_t_sub},
813 {"tst", T_OPCODE_TST, 2, do_t_arit},
815 {"adr", 0x0000, 2, do_t_adr},
816 {"nop", 0x46C0, 2, do_t_nop}, /* mov r8,r8 */
825 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
826 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
827 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
833 /* These are the standard names; Users can add aliases with .req */
834 static CONST struct reg_entry reg_table[] =
836 /* Processor Register Numbers */
837 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
838 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
839 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
840 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
841 /* APCS conventions */
842 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
843 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
844 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
845 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
847 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
848 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
849 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
850 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
851 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
852 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
853 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
854 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
855 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
856 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
860 #define bad_args _("Bad arguments to instruction");
861 #define bad_pc _("r15 not allowed here");
863 static struct hash_control *arm_ops_hsh = NULL;
864 static struct hash_control *arm_tops_hsh = NULL;
865 static struct hash_control *arm_cond_hsh = NULL;
866 static struct hash_control *arm_shift_hsh = NULL;
867 static struct hash_control *arm_reg_hsh = NULL;
868 static struct hash_control *arm_psr_hsh = NULL;
870 /* This table describes all the machine specific pseudo-ops the assembler
871 has to support. The fields are:
872 pseudo-op name without dot
873 function to call to execute this pseudo-op
874 Integer arg to pass to the function
877 static void s_req PARAMS ((int));
878 static void s_align PARAMS ((int));
879 static void s_bss PARAMS ((int));
880 static void s_even PARAMS ((int));
881 static void s_ltorg PARAMS ((int));
882 static void s_arm PARAMS ((int));
883 static void s_thumb PARAMS ((int));
884 static void s_code PARAMS ((int));
885 static void s_force_thumb PARAMS ((int));
886 static void s_thumb_func PARAMS ((int));
888 static int my_get_expression PARAMS ((expressionS *, char **));
890 CONST pseudo_typeS md_pseudo_table[] =
892 {"req", s_req, 0}, /* Never called becasue '.req' does not start line */
894 {"align", s_align, 0},
896 {"thumb", s_thumb, 0},
898 {"force_thumb", s_force_thumb, 0},
899 {"thumb_func", s_thumb_func, 0},
901 {"ltorg", s_ltorg, 0},
902 {"pool", s_ltorg, 0},
904 {"extend", float_cons, 'x'},
905 {"ldouble", float_cons, 'x'},
906 {"packed", float_cons, 'p'},
910 /* Stuff needed to resolve the label ambiguity
920 symbolS * last_label_seen;
921 static int label_is_thumb_function_name = false;
925 #define MAX_LITERAL_POOL_SIZE 1024
927 typedef struct literalS
929 struct expressionS exp;
933 literalT literals[MAX_LITERAL_POOL_SIZE];
934 int next_literal_pool_place = 0; /* Next free entry in the pool */
935 int lit_pool_num = 1; /* Next literal pool number */
936 symbolS *current_poolP = NULL;
937 symbolS *symbol_make_empty PARAMS ((void));
944 if (current_poolP == NULL)
945 current_poolP = symbol_make_empty();
947 /* Check if this literal value is already in the pool: */
948 while (lit_count < next_literal_pool_place)
950 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
951 && inst.reloc.exp.X_op == O_constant
952 && literals[lit_count].exp.X_add_number == inst.reloc.exp.X_add_number
953 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
958 if (lit_count == next_literal_pool_place) /* new entry */
960 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
962 inst.error = _("Literal Pool Overflow");
966 literals[next_literal_pool_place].exp = inst.reloc.exp;
967 lit_count = next_literal_pool_place++;
970 inst.reloc.exp.X_op = O_symbol;
971 inst.reloc.exp.X_add_number = (lit_count)*4-8;
972 inst.reloc.exp.X_add_symbol = current_poolP;
977 /* Can't use symbol_new here, so have to create a symbol and then at
978 a later date assign it a value. Thats what these functions do */
980 symbol_locate (symbolP, name, segment, valu, frag)
982 CONST char *name; /* It is copied, the caller can modify */
983 segT segment; /* Segment identifier (SEG_<something>) */
984 valueT valu; /* Symbol value */
985 fragS *frag; /* Associated fragment */
987 unsigned int name_length;
988 char *preserved_copy_of_name;
990 name_length = strlen (name) + 1; /* +1 for \0 */
991 obstack_grow (¬es, name, name_length);
992 preserved_copy_of_name = obstack_finish (¬es);
993 #ifdef STRIP_UNDERSCORE
994 if (preserved_copy_of_name[0] == '_')
995 preserved_copy_of_name++;
998 #ifdef tc_canonicalize_symbol_name
999 preserved_copy_of_name =
1000 tc_canonicalize_symbol_name (preserved_copy_of_name);
1003 S_SET_NAME (symbolP, preserved_copy_of_name);
1005 S_SET_SEGMENT (symbolP, segment);
1006 S_SET_VALUE (symbolP, valu);
1007 symbol_clear_list_pointers(symbolP);
1009 symbolP->sy_frag = frag;
1012 * Link to end of symbol chain.
1015 extern int symbol_table_frozen;
1016 if (symbol_table_frozen)
1020 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1022 obj_symbol_new_hook (symbolP);
1024 #ifdef tc_symbol_new_hook
1025 tc_symbol_new_hook (symbolP);
1029 verify_symbol_chain(symbol_rootP, symbol_lastP);
1030 #endif /* DEBUG_SYMS */
1034 symbol_make_empty ()
1038 symbolP = (symbolS *) obstack_alloc (¬es, sizeof (symbolS));
1040 /* symbol must be born in some fixed state. This seems as good as any. */
1041 memset (symbolP, 0, sizeof (symbolS));
1043 symbolP->bsym = bfd_make_empty_symbol (stdoutput);
1044 assert (symbolP->bsym != 0);
1045 symbolP->bsym->udata.p = (PTR) symbolP;
1050 /* Check that an immediate is valid, and if so, convert it to the right format. */
1053 validate_immediate (val)
1059 #define rotate_left(v, n) (v << n | v >> (32 - n))
1061 for (i = 0; i < 32; i += 2)
1062 if ((a = rotate_left (val, i)) <= 0xff)
1063 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1068 validate_offset_imm (val, hwse)
1072 if ((hwse && (val < -255 || val > 255))
1073 || (val < -4095 || val > 4095))
1083 as_bad (_("Invalid syntax for .req directive."));
1090 /* We don't support putting frags in the BSS segment, we fake it by
1091 marking in_bss, then looking at s_skip for clues?.. */
1092 subseg_set (bss_section, 0);
1093 demand_empty_rest_of_line ();
1100 if (!need_pass_2) /* Never make frag if expect extra pass. */
1101 frag_align (1, 0, 0);
1102 record_alignment (now_seg, 1);
1103 demand_empty_rest_of_line ();
1113 if (current_poolP == NULL)
1117 as_tsktsk (_("Nothing to put in the pool\n"));
1121 /* Align pool as you have word accesses */
1122 /* Only make a frag if we have to ... */
1124 frag_align (2, 0, 0);
1126 record_alignment (now_seg, 2);
1129 as_tsktsk (_("Inserting implicit pool at change of section"));
1131 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1133 symbol_locate (current_poolP, sym_name, now_seg,
1134 (valueT) frag_now_fix (), frag_now);
1135 symbol_table_insert (current_poolP);
1137 ARM_SET_THUMB (current_poolP, thumb_mode);
1138 #if defined OBJ_COFF || defined OBJ_ELF
1139 ARM_SET_INTERWORK (current_poolP, support_interwork);
1142 while (lit_count < next_literal_pool_place)
1143 /* First output the expression in the instruction to the pool */
1144 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1146 next_literal_pool_place = 0;
1147 current_poolP = NULL;
1150 #if 0 /* not used */
1152 arm_align (power, fill)
1156 /* Only make a frag if we HAVE to ... */
1157 if (power && !need_pass_2)
1158 frag_align (power, fill, 0);
1160 record_alignment (now_seg, power);
1165 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1169 register long temp_fill;
1170 long max_alignment = 15;
1172 temp = get_absolute_expression ();
1173 if (temp > max_alignment)
1174 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1177 as_bad (_("Alignment negative. 0 assumed."));
1181 if (*input_line_pointer == ',')
1183 input_line_pointer++;
1184 temp_fill = get_absolute_expression ();
1192 /* Only make a frag if we HAVE to. . . */
1193 if (temp && !need_pass_2)
1194 frag_align (temp, (int) temp_fill, 0);
1195 demand_empty_rest_of_line ();
1197 record_alignment (now_seg, temp);
1201 s_force_thumb (ignore)
1204 /* If we are not already in thumb mode go into it, EVEN if
1205 the target processor does not support thumb instructions.
1206 This is used by gcc/config/arm/lib1funcs.asm for example
1207 to compile interworking support functions even if the
1208 target processor should not support interworking. */
1214 record_alignment (now_seg, 1);
1217 demand_empty_rest_of_line ();
1221 s_thumb_func (ignore)
1224 /* The following label is the name/address of the start of a Thumb function.
1225 We need to know this for the interworking support. */
1227 label_is_thumb_function_name = true;
1229 demand_empty_rest_of_line();
1233 opcode_select (width)
1241 if (! (cpu_variant & ARM_THUMB))
1242 as_bad (_("selected processor does not support THUMB opcodes"));
1244 /* No need to force the alignment, since we will have been
1245 coming from ARM mode, which is word-aligned. */
1246 record_alignment (now_seg, 1);
1253 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1254 as_bad (_("selected processor does not support ARM opcodes"));
1257 frag_align (2, 0, 0);
1258 record_alignment (now_seg, 1);
1263 as_bad (_("invalid instruction size selected (%d)"), width);
1272 demand_empty_rest_of_line ();
1280 demand_empty_rest_of_line ();
1289 temp = get_absolute_expression ();
1294 opcode_select(temp);
1298 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1310 inst.error = _("Garbage following instruction");
1314 skip_past_comma (str)
1320 while ((c = *p) == ' ' || c == ',')
1323 if (c == ',' && comma++)
1331 return comma ? SUCCESS : FAIL;
1334 /* A standard register must be given at this point. Shift is the place to
1335 put it in the instruction. */
1338 reg_required_here (str, shift)
1342 static char buff [128]; /* XXX */
1346 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1349 inst.instruction |= reg << shift;
1353 /* Restore the start point, we may have got a reg of the wrong class. */
1356 /* In the few cases where we might be able to accept something else
1357 this error can be overridden */
1358 sprintf (buff, _("Register expected, not '%.100s'"), start);
1365 psr_required_here (str, cpsr, spsr)
1371 char * start = *str;
1372 psr = arm_psr_parse (str);
1374 if (psr == cpsr || psr == spsr)
1377 inst.instruction |= 1 << 22;
1382 /* In the few cases where we might be able to accept something else
1383 this error can be overridden */
1384 inst.error = _("<psr(f)> expected");
1386 /* Restore the start point. */
1392 co_proc_number (str)
1395 int processor, pchar;
1397 while (**str == ' ')
1400 /* The data sheet seems to imply that just a number on its own is valid
1401 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1403 if (**str == 'p' || **str == 'P')
1407 if (pchar >= '0' && pchar <= '9')
1409 processor = pchar - '0';
1410 if (**str >= '0' && **str <= '9')
1412 processor = processor * 10 + *(*str)++ - '0';
1415 inst.error = _("Illegal co-processor number");
1422 inst.error = _("Bad or missing co-processor number");
1426 inst.instruction |= processor << 8;
1431 cp_opc_expr (str, where, length)
1438 while (**str == ' ')
1441 memset (&expr, '\0', sizeof (expr));
1443 if (my_get_expression (&expr, str))
1445 if (expr.X_op != O_constant)
1447 inst.error = _("bad or missing expression");
1451 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1453 inst.error = _("immediate co-processor expression too large");
1457 inst.instruction |= expr.X_add_number << where;
1462 cp_reg_required_here (str, where)
1469 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1472 inst.instruction |= reg << where;
1476 /* In the few cases where we might be able to accept something else
1477 this error can be overridden */
1478 inst.error = _("Co-processor register expected");
1480 /* Restore the start point */
1486 fp_reg_required_here (str, where)
1493 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1496 inst.instruction |= reg << where;
1500 /* In the few cases where we might be able to accept something else
1501 this error can be overridden */
1502 inst.error = _("Floating point register expected");
1504 /* Restore the start point */
1510 cp_address_offset (str)
1515 while (**str == ' ')
1520 inst.error = _("immediate expression expected");
1525 if (my_get_expression (&inst.reloc.exp, str))
1527 if (inst.reloc.exp.X_op == O_constant)
1529 offset = inst.reloc.exp.X_add_number;
1532 inst.error = _("co-processor address must be word aligned");
1536 if (offset > 1023 || offset < -1023)
1538 inst.error = _("offset too large");
1543 inst.instruction |= INDEX_UP;
1547 inst.instruction |= offset >> 2;
1550 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1556 cp_address_required_here (str)
1571 if ((reg = reg_required_here (&p, 16)) == FAIL)
1580 if (skip_past_comma (&p) == SUCCESS)
1583 write_back = WRITE_BACK;
1586 inst.error = _("pc may not be used in post-increment");
1590 if (cp_address_offset (&p) == FAIL)
1594 pre_inc = PRE_INDEX | INDEX_UP;
1598 /* '['Rn, #expr']'[!] */
1600 if (skip_past_comma (&p) == FAIL)
1602 inst.error = _("pre-indexed expression expected");
1606 pre_inc = PRE_INDEX;
1607 if (cp_address_offset (&p) == FAIL)
1615 inst.error = _("missing ]");
1626 inst.error = _("pc may not be used with write-back");
1631 write_back = WRITE_BACK;
1637 if (my_get_expression (&inst.reloc.exp, &p))
1640 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1641 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1642 inst.reloc.pc_rel = 1;
1643 inst.instruction |= (REG_PC << 16);
1644 pre_inc = PRE_INDEX;
1647 inst.instruction |= write_back | pre_inc;
1655 unsigned long flags;
1657 /* Do nothing really */
1658 inst.instruction |= flags; /* This is pointless */
1666 unsigned long flags;
1668 /* Only one syntax */
1672 if (reg_required_here (&str, 12) == FAIL)
1674 inst.error = bad_args;
1678 if (skip_past_comma (&str) == FAIL
1679 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1681 inst.error = _("<psr> expected");
1685 inst.instruction |= flags;
1690 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
1694 unsigned long flags;
1701 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1703 inst.instruction |= PSR_ALL;
1705 /* Sytax should be "<psr>, Rm" */
1706 if (skip_past_comma (&str) == FAIL
1707 || (reg = reg_required_here (&str, 0)) == FAIL)
1709 inst.error = bad_args;
1715 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1717 inst.instruction |= PSR_FLAGS;
1719 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1721 inst.instruction |= PSR_CONTROL;
1725 inst.error = bad_args;
1729 if (skip_past_comma (&str) == FAIL)
1731 inst.error = bad_args;
1735 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1737 if ((reg = reg_required_here (&str, 0)) != FAIL)
1739 /* Immediate expression */
1740 else if (*(str++) == '#')
1743 if (my_get_expression (&inst.reloc.exp, &str))
1745 inst.error = _("Register or shift expression expected");
1749 if (inst.reloc.exp.X_add_symbol)
1751 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1752 inst.reloc.pc_rel = 0;
1756 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1759 inst.error = _("Invalid constant");
1763 inst.instruction |= value;
1766 flags |= INST_IMMEDIATE;
1770 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1776 inst.instruction |= flags;
1781 /* Long Multiply Parser
1782 UMULL RdLo, RdHi, Rm, Rs
1783 SMULL RdLo, RdHi, Rm, Rs
1784 UMLAL RdLo, RdHi, Rm, Rs
1785 SMLAL RdLo, RdHi, Rm, Rs
1788 do_mull (str, flags)
1790 unsigned long flags;
1792 int rdlo, rdhi, rm, rs;
1794 /* only one format "rdlo, rdhi, rm, rs" */
1798 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1800 inst.error = bad_args;
1804 if (skip_past_comma (&str) == FAIL
1805 || (rdhi = reg_required_here (&str, 16)) == FAIL)
1807 inst.error = bad_args;
1811 if (skip_past_comma (&str) == FAIL
1812 || (rm = reg_required_here (&str, 0)) == FAIL)
1814 inst.error = bad_args;
1818 /* rdhi, rdlo and rm must all be different */
1819 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
1820 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
1822 if (skip_past_comma (&str) == FAIL
1823 || (rs = reg_required_here (&str, 8)) == FAIL)
1825 inst.error = bad_args;
1829 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
1831 inst.error = bad_pc;
1835 inst.instruction |= flags;
1843 unsigned long flags;
1847 /* only one format "rd, rm, rs" */
1851 if ((rd = reg_required_here (&str, 16)) == FAIL)
1853 inst.error = bad_args;
1859 inst.error = bad_pc;
1863 if (skip_past_comma (&str) == FAIL
1864 || (rm = reg_required_here (&str, 0)) == FAIL)
1866 inst.error = bad_args;
1872 inst.error = bad_pc;
1877 as_tsktsk (_("rd and rm should be different in mul"));
1879 if (skip_past_comma (&str) == FAIL
1880 || (rm = reg_required_here (&str, 8)) == FAIL)
1882 inst.error = bad_args;
1888 inst.error = bad_pc;
1892 inst.instruction |= flags;
1900 unsigned long flags;
1904 /* only one format "rd, rm, rs, rn" */
1908 if ((rd = reg_required_here (&str, 16)) == FAIL)
1910 inst.error = bad_args;
1916 inst.error = bad_pc;
1920 if (skip_past_comma (&str) == FAIL
1921 || (rm = reg_required_here (&str, 0)) == FAIL)
1923 inst.error = bad_args;
1929 inst.error = bad_pc;
1934 as_tsktsk (_("rd and rm should be different in mla"));
1936 if (skip_past_comma (&str) == FAIL
1937 || (rd = reg_required_here (&str, 8)) == FAIL
1938 || skip_past_comma (&str) == FAIL
1939 || (rm = reg_required_here (&str, 12)) == FAIL)
1941 inst.error = bad_args;
1945 if (rd == REG_PC || rm == REG_PC)
1947 inst.error = bad_pc;
1951 inst.instruction |= flags;
1956 /* Returns the index into fp_values of a floating point number, or -1 if
1957 not in the table. */
1959 my_get_float_expression (str)
1962 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1967 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
1968 /* Look for a raw floating point number */
1969 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
1970 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
1972 for (i = 0; i < NUM_FLOAT_VALS; i++)
1974 for (j = 0; j < MAX_LITTLENUMS; j++)
1976 if (words[j] != fp_values[i][j])
1980 if (j == MAX_LITTLENUMS)
1988 /* Try and parse a more complex expression, this will probably fail
1989 unless the code uses a floating point prefix (eg "0f") */
1990 save_in = input_line_pointer;
1991 input_line_pointer = *str;
1992 if (expression (&exp) == absolute_section
1993 && exp.X_op == O_big
1994 && exp.X_add_number < 0)
1996 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
1998 if (gen_to_words (words, 5, (long)15) == 0)
2000 for (i = 0; i < NUM_FLOAT_VALS; i++)
2002 for (j = 0; j < MAX_LITTLENUMS; j++)
2004 if (words[j] != fp_values[i][j])
2008 if (j == MAX_LITTLENUMS)
2010 *str = input_line_pointer;
2011 input_line_pointer = save_in;
2018 *str = input_line_pointer;
2019 input_line_pointer = save_in;
2023 /* Return true if anything in the expression is a bignum */
2025 walk_no_bignums (sp)
2028 if (sp->sy_value.X_op == O_big)
2031 if (sp->sy_value.X_add_symbol)
2033 return (walk_no_bignums (sp->sy_value.X_add_symbol)
2034 || (sp->sy_value.X_op_symbol
2035 && walk_no_bignums (sp->sy_value.X_op_symbol)));
2042 my_get_expression (ep, str)
2049 save_in = input_line_pointer;
2050 input_line_pointer = *str;
2051 seg = expression (ep);
2054 if (seg != absolute_section
2055 && seg != text_section
2056 && seg != data_section
2057 && seg != bss_section
2058 && seg != undefined_section)
2060 inst.error = _("bad_segment");
2061 *str = input_line_pointer;
2062 input_line_pointer = save_in;
2067 /* Get rid of any bignums now, so that we don't generate an error for which
2068 we can't establish a line number later on. Big numbers are never valid
2069 in instructions, which is where this routine is always called. */
2070 if (ep->X_op == O_big
2071 || (ep->X_add_symbol
2072 && (walk_no_bignums (ep->X_add_symbol)
2074 && walk_no_bignums (ep->X_op_symbol)))))
2076 inst.error = _("Invalid constant");
2077 *str = input_line_pointer;
2078 input_line_pointer = save_in;
2082 *str = input_line_pointer;
2083 input_line_pointer = save_in;
2087 /* unrestrict should be one if <shift> <register> is permitted for this
2091 decode_shift (str, unrestrict)
2095 struct asm_shift *shft;
2099 while (**str == ' ')
2102 for (p = *str; isalpha (*p); p++)
2107 inst.error = _("Shift expression expected");
2113 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2117 if (!strncmp (*str, "rrx", 3)
2118 || !strncmp (*str, "RRX", 3))
2121 inst.instruction |= shft->value;
2128 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2130 inst.instruction |= shft->value | SHIFT_BY_REG;
2138 if (my_get_expression (&inst.reloc.exp, &p))
2141 /* Validate some simple #expressions */
2142 if (inst.reloc.exp.X_op == O_constant)
2144 unsigned num = inst.reloc.exp.X_add_number;
2146 /* Reject operations greater than 32, or lsl #32 */
2147 if (num > 32 || (num == 32 && shft->value == 0))
2149 inst.error = _("Invalid immediate shift");
2153 /* Shifts of zero should be converted to lsl (which is zero)*/
2160 /* Shifts of 32 are encoded as 0, for those shifts that
2165 inst.instruction |= (num << 7) | shft->value;
2170 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2171 inst.reloc.pc_rel = 0;
2172 inst.instruction |= shft->value;
2178 inst.error = unrestrict ? _("shift requires register or #expression")
2179 : _("shift requires #expression");
2185 inst.error = _("Shift expression expected");
2189 /* Do those data_ops which can take a negative immediate constant */
2190 /* by altering the instuction. A bit of a hack really */
2194 by inverting the second operand, and
2197 by negating the second operand.
2200 negate_data_op (instruction, value)
2201 unsigned long *instruction;
2202 unsigned long value;
2205 unsigned long negated, inverted;
2207 negated = validate_immediate (-value);
2208 inverted = validate_immediate (~value);
2210 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2214 case OPCODE_SUB: /* ADD <-> SUB */
2215 new_inst = OPCODE_ADD;
2220 new_inst = OPCODE_SUB;
2224 case OPCODE_CMP: /* CMP <-> CMN */
2225 new_inst = OPCODE_CMN;
2230 new_inst = OPCODE_CMP;
2234 /* Now Inverted ops */
2235 case OPCODE_MOV: /* MOV <-> MVN */
2236 new_inst = OPCODE_MVN;
2241 new_inst = OPCODE_MOV;
2245 case OPCODE_AND: /* AND <-> BIC */
2246 new_inst = OPCODE_BIC;
2251 new_inst = OPCODE_AND;
2255 case OPCODE_ADC: /* ADC <-> SBC */
2256 new_inst = OPCODE_SBC;
2261 new_inst = OPCODE_ADC;
2265 /* We cannot do anything */
2273 *instruction &= OPCODE_MASK;
2274 *instruction |= new_inst << DATA_OP_SHIFT;
2285 while (**str == ' ')
2288 if (reg_required_here (str, 0) != FAIL)
2290 if (skip_past_comma (str) == SUCCESS)
2292 /* Shift operation on register */
2293 return decode_shift (str, NO_SHIFT_RESTRICT);
2299 /* Immediate expression */
2300 if (*((*str)++) == '#')
2303 if (my_get_expression (&inst.reloc.exp, str))
2306 if (inst.reloc.exp.X_add_symbol)
2308 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2309 inst.reloc.pc_rel = 0;
2313 if (skip_past_comma (str) == SUCCESS)
2315 /* #x, y -- ie explicit rotation by Y */
2316 if (my_get_expression (&expr, str))
2319 if (expr.X_op != O_constant)
2321 inst.error = _("Constant expression expected");
2325 /* Rotate must be a multiple of 2 */
2326 if (((unsigned) expr.X_add_number) > 30
2327 || (expr.X_add_number & 1) != 0
2328 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2330 inst.error = _("Invalid constant");
2333 inst.instruction |= INST_IMMEDIATE;
2334 inst.instruction |= inst.reloc.exp.X_add_number;
2335 inst.instruction |= expr.X_add_number << 7;
2339 /* Implicit rotation, select a suitable one */
2340 value = validate_immediate (inst.reloc.exp.X_add_number);
2344 /* Can't be done, perhaps the code reads something like
2345 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2346 if ((value = negate_data_op (&inst.instruction,
2347 inst.reloc.exp.X_add_number))
2350 inst.error = _("Invalid constant");
2355 inst.instruction |= value;
2358 inst.instruction |= INST_IMMEDIATE;
2362 inst.error = _("Register or shift expression expected");
2371 while (**str == ' ')
2374 if (fp_reg_required_here (str, 0) != FAIL)
2378 /* Immediate expression */
2379 if (*((*str)++) == '#')
2384 while (**str == ' ')
2387 /* First try and match exact strings, this is to guarantee that
2388 some formats will work even for cross assembly */
2390 for (i = 0; fp_const[i]; i++)
2392 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2396 *str += strlen (fp_const[i]);
2397 if (is_end_of_line[(int)**str] || **str == '\0')
2399 inst.instruction |= i + 8;
2406 /* Just because we didn't get a match doesn't mean that the
2407 constant isn't valid, just that it is in a format that we
2408 don't automatically recognize. Try parsing it with
2409 the standard expression routines. */
2410 if ((i = my_get_float_expression (str)) >= 0)
2412 inst.instruction |= i + 8;
2416 inst.error = _("Invalid floating point immediate expression");
2419 inst.error = _("Floating point register or immediate expression expected");
2425 do_arit (str, flags)
2427 unsigned long flags;
2432 if (reg_required_here (&str, 12) == FAIL
2433 || skip_past_comma (&str) == FAIL
2434 || reg_required_here (&str, 16) == FAIL
2435 || skip_past_comma (&str) == FAIL
2436 || data_op2 (&str) == FAIL)
2439 inst.error = bad_args;
2443 inst.instruction |= flags;
2451 unsigned long flags;
2453 /* This is a pseudo-op of the form "adr rd, label" to be converted
2454 into a relative address of the form "add rd, pc, #label-.-8" */
2459 if (reg_required_here (&str, 12) == FAIL
2460 || skip_past_comma (&str) == FAIL
2461 || my_get_expression (&inst.reloc.exp, &str))
2464 inst.error = bad_args;
2467 /* Frag hacking will turn this into a sub instruction if the offset turns
2468 out to be negative. */
2469 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2470 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2471 inst.reloc.pc_rel = 1;
2472 inst.instruction |= flags;
2480 unsigned long flags;
2485 if (reg_required_here (&str, 16) == FAIL)
2488 inst.error = bad_args;
2492 if (skip_past_comma (&str) == FAIL
2493 || data_op2 (&str) == FAIL)
2496 inst.error = bad_args;
2500 inst.instruction |= flags;
2501 if ((flags & 0x0000f000) == 0)
2502 inst.instruction |= CONDS_BIT;
2511 unsigned long flags;
2516 if (reg_required_here (&str, 12) == FAIL)
2519 inst.error = bad_args;
2523 if (skip_past_comma (&str) == FAIL
2524 || data_op2 (&str) == FAIL)
2527 inst.error = bad_args;
2531 inst.instruction |= flags;
2537 ldst_extend (str, hwse)
2547 if (my_get_expression (&inst.reloc.exp, str))
2550 if (inst.reloc.exp.X_op == O_constant)
2552 int value = inst.reloc.exp.X_add_number;
2554 if ((hwse && (value < -255 || value > 255))
2555 || (value < -4095 || value > 4095))
2557 inst.error = _("address offset too large");
2567 /* Halfword and signextension instructions have the
2568 immediate value split across bits 11..8 and bits 3..0 */
2570 inst.instruction |= add | HWOFFSET_IMM | (value >> 4) << 8 | value & 0xF;
2572 inst.instruction |= add | value;
2578 inst.instruction |= HWOFFSET_IMM;
2579 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2582 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2583 inst.reloc.pc_rel = 0;
2588 add = 0; /* and fall through */
2590 (*str)++; /* and fall through */
2592 if (reg_required_here (str, 0) == FAIL)
2596 inst.instruction |= add;
2599 inst.instruction |= add | OFFSET_REG;
2600 if (skip_past_comma (str) == SUCCESS)
2601 return decode_shift (str, SHIFT_RESTRICT);
2609 do_ldst (str, flags)
2611 unsigned long flags;
2618 /* This is not ideal, but it is the simplest way of dealing with the
2619 ARM7T halfword instructions (since they use a different
2620 encoding, but the same mnemonic): */
2621 if (halfword = ((flags & 0x80000000) != 0))
2623 /* This is actually a load/store of a halfword, or a
2624 signed-extension load */
2625 if ((cpu_variant & ARM_HALFWORD) == 0)
2628 = _("Processor does not support halfwords or signed bytes");
2632 inst.instruction = (inst.instruction & COND_MASK)
2633 | (flags & ~COND_MASK);
2641 if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
2644 if (skip_past_comma (&str) == FAIL)
2646 inst.error = _("Address expected");
2658 if ((reg = reg_required_here (&str, 16)) == FAIL)
2661 conflict_reg = (((conflict_reg == reg)
2662 && (inst.instruction & LOAD_BIT))
2671 if (skip_past_comma (&str) == SUCCESS)
2673 /* [Rn],... (post inc) */
2674 if (ldst_extend (&str, halfword) == FAIL)
2677 as_warn (_("destination register same as write-back base\n"));
2683 inst.instruction |= HWOFFSET_IMM;
2691 as_warn (_("destination register same as write-back base\n"));
2693 inst.instruction |= WRITE_BACK;
2697 if (! (flags & TRANS_BIT))
2704 if (skip_past_comma (&str) == FAIL)
2706 inst.error = _("pre-indexed expression expected");
2711 if (ldst_extend (&str, halfword) == FAIL)
2719 inst.error = _("missing ]");
2729 as_tsktsk (_("destination register same as write-back base\n"));
2731 inst.instruction |= WRITE_BACK;
2735 else if (*str == '=')
2737 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2743 if (my_get_expression (&inst.reloc.exp, &str))
2746 if (inst.reloc.exp.X_op != O_constant
2747 && inst.reloc.exp.X_op != O_symbol)
2749 inst.error = _("Constant expression expected");
2753 if (inst.reloc.exp.X_op == O_constant
2754 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2756 /* This can be done with a mov instruction */
2757 inst.instruction &= LITERAL_MASK;
2758 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2759 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2765 /* Insert into literal pool */
2766 if (add_to_lit_pool () == FAIL)
2769 inst.error = _("literal pool insertion failed");
2773 /* Change the instruction exp to point to the pool */
2776 inst.instruction |= HWOFFSET_IMM;
2777 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
2780 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
2781 inst.reloc.pc_rel = 1;
2782 inst.instruction |= (REG_PC << 16);
2788 if (my_get_expression (&inst.reloc.exp, &str))
2793 inst.instruction |= HWOFFSET_IMM;
2794 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2797 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2798 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
2799 inst.reloc.pc_rel = 1;
2800 inst.instruction |= (REG_PC << 16);
2804 if (pre_inc && (flags & TRANS_BIT))
2805 inst.error = _("Pre-increment instruction with translate");
2807 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
2820 /* We come back here if we get ranges concatenated by '+' or '|' */
2838 if ((reg = reg_required_here (& str, -1)) == FAIL)
2847 inst.error = _("Bad range in register list");
2851 for (i = cur_reg + 1; i < reg; i++)
2853 if (range & (1 << i))
2855 (_("Warning: Duplicated register (r%d) in register list"),
2863 if (range & (1 << reg))
2864 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
2866 else if (reg <= cur_reg)
2867 as_tsktsk (_("Warning: Register range not in ascending order"));
2871 } while (skip_past_comma (&str) != FAIL
2872 || (in_range = 1, *str++ == '-'));
2879 inst.error = _("Missing `}'");
2887 if (my_get_expression (&expr, &str))
2890 if (expr.X_op == O_constant)
2892 if (expr.X_add_number
2893 != (expr.X_add_number & 0x0000ffff))
2895 inst.error = _("invalid register mask");
2899 if ((range & expr.X_add_number) != 0)
2901 int regno = range & expr.X_add_number;
2904 regno = (1 << regno) - 1;
2906 (_("Warning: Duplicated register (r%d) in register list"),
2910 range |= expr.X_add_number;
2914 if (inst.reloc.type != 0)
2916 inst.error = _("expression too complex");
2920 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
2921 inst.reloc.type = BFD_RELOC_ARM_MULTI;
2922 inst.reloc.pc_rel = 0;
2929 if (*str == '|' || *str == '+')
2934 } while (another_range);
2941 do_ldmstm (str, flags)
2943 unsigned long flags;
2951 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
2954 if (base_reg == REG_PC)
2956 inst.error = _("r15 not allowed as base register");
2964 flags |= WRITE_BACK;
2968 if (skip_past_comma (&str) == FAIL
2969 || (range = reg_list (&str)) == FAIL)
2972 inst.error = bad_args;
2979 flags |= MULTI_SET_PSR;
2982 inst.instruction |= flags | range;
2990 unsigned long flags;
2992 /* Allow optional leading '#'. */
2998 if (my_get_expression (&inst.reloc.exp, &str))
3001 inst.reloc.type = BFD_RELOC_ARM_SWI;
3002 inst.reloc.pc_rel = 0;
3003 inst.instruction |= flags;
3009 do_swap (str, flags)
3011 unsigned long flags;
3018 if ((reg = reg_required_here (&str, 12)) == FAIL)
3023 inst.error = _("r15 not allowed in swap");
3027 if (skip_past_comma (&str) == FAIL
3028 || (reg = reg_required_here (&str, 0)) == FAIL)
3031 inst.error = bad_args;
3037 inst.error = _("r15 not allowed in swap");
3041 if (skip_past_comma (&str) == FAIL
3044 inst.error = bad_args;
3051 if ((reg = reg_required_here (&str, 16)) == FAIL)
3056 inst.error = bad_pc;
3065 inst.error = _("missing ]");
3069 inst.instruction |= flags;
3075 do_branch (str, flags)
3077 unsigned long flags;
3079 if (my_get_expression (&inst.reloc.exp, &str))
3081 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3082 inst.reloc.pc_rel = 1;
3090 unsigned long flags;
3097 if ((reg = reg_required_here (&str, 0)) == FAIL)
3101 as_tsktsk (_("Use of r15 in bx has undefined behaviour"));
3110 unsigned long flags;
3112 /* Co-processor data operation.
3113 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3117 if (co_proc_number (&str) == FAIL)
3120 inst.error = bad_args;
3124 if (skip_past_comma (&str) == FAIL
3125 || cp_opc_expr (&str, 20,4) == FAIL)
3128 inst.error = bad_args;
3132 if (skip_past_comma (&str) == FAIL
3133 || cp_reg_required_here (&str, 12) == FAIL)
3136 inst.error = bad_args;
3140 if (skip_past_comma (&str) == FAIL
3141 || cp_reg_required_here (&str, 16) == FAIL)
3144 inst.error = bad_args;
3148 if (skip_past_comma (&str) == FAIL
3149 || cp_reg_required_here (&str, 0) == FAIL)
3152 inst.error = bad_args;
3156 if (skip_past_comma (&str) == SUCCESS)
3158 if (cp_opc_expr (&str, 5, 3) == FAIL)
3161 inst.error = bad_args;
3171 do_lstc (str, flags)
3173 unsigned long flags;
3175 /* Co-processor register load/store.
3176 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3181 if (co_proc_number (&str) == FAIL)
3184 inst.error = bad_args;
3188 if (skip_past_comma (&str) == FAIL
3189 || cp_reg_required_here (&str, 12) == FAIL)
3192 inst.error = bad_args;
3196 if (skip_past_comma (&str) == FAIL
3197 || cp_address_required_here (&str) == FAIL)
3200 inst.error = bad_args;
3204 inst.instruction |= flags;
3210 do_co_reg (str, flags)
3212 unsigned long flags;
3214 /* Co-processor register transfer.
3215 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3220 if (co_proc_number (&str) == FAIL)
3223 inst.error = bad_args;
3227 if (skip_past_comma (&str) == FAIL
3228 || cp_opc_expr (&str, 21, 3) == FAIL)
3231 inst.error = bad_args;
3235 if (skip_past_comma (&str) == FAIL
3236 || reg_required_here (&str, 12) == FAIL)
3239 inst.error = bad_args;
3243 if (skip_past_comma (&str) == FAIL
3244 || cp_reg_required_here (&str, 16) == FAIL)
3247 inst.error = bad_args;
3251 if (skip_past_comma (&str) == FAIL
3252 || cp_reg_required_here (&str, 0) == FAIL)
3255 inst.error = bad_args;
3259 if (skip_past_comma (&str) == SUCCESS)
3261 if (cp_opc_expr (&str, 5, 3) == FAIL)
3264 inst.error = bad_args;
3274 do_fp_ctrl (str, flags)
3276 unsigned long flags;
3278 /* FP control registers.
3279 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3284 if (reg_required_here (&str, 12) == FAIL)
3287 inst.error = bad_args;
3296 do_fp_ldst (str, flags)
3298 unsigned long flags;
3303 switch (inst.suffix)
3308 inst.instruction |= CP_T_X;
3311 inst.instruction |= CP_T_Y;
3314 inst.instruction |= CP_T_X | CP_T_Y;
3320 if (fp_reg_required_here (&str, 12) == FAIL)
3323 inst.error = bad_args;
3327 if (skip_past_comma (&str) == FAIL
3328 || cp_address_required_here (&str) == FAIL)
3331 inst.error = bad_args;
3339 do_fp_ldmstm (str, flags)
3341 unsigned long flags;
3348 if (fp_reg_required_here (&str, 12) == FAIL)
3351 inst.error = bad_args;
3355 /* Get Number of registers to transfer */
3356 if (skip_past_comma (&str) == FAIL
3357 || my_get_expression (&inst.reloc.exp, &str))
3360 inst.error = _("constant expression expected");
3364 if (inst.reloc.exp.X_op != O_constant)
3366 inst.error = _("Constant value required for number of registers");
3370 num_regs = inst.reloc.exp.X_add_number;
3372 if (num_regs < 1 || num_regs > 4)
3374 inst.error = _("number of registers must be in the range [1:4]");
3381 inst.instruction |= CP_T_X;
3384 inst.instruction |= CP_T_Y;
3387 inst.instruction |= CP_T_Y | CP_T_X;
3401 /* The instruction specified "ea" or "fd", so we can only accept
3402 [Rn]{!}. The instruction does not really support stacking or
3403 unstacking, so we have to emulate these by setting appropriate
3404 bits and offsets. */
3405 if (skip_past_comma (&str) == FAIL
3409 inst.error = bad_args;
3417 if ((reg = reg_required_here (&str, 16)) == FAIL)
3425 inst.error = bad_args;
3436 inst.error = _("R15 not allowed as base register with write-back");
3443 if (flags & CP_T_Pre)
3446 offset = 3 * num_regs;
3452 /* Post-increment */
3456 offset = 3 * num_regs;
3460 /* No write-back, so convert this into a standard pre-increment
3461 instruction -- aesthetically more pleasing. */
3462 flags = CP_T_Pre | CP_T_UD;
3467 inst.instruction |= flags | offset;
3469 else if (skip_past_comma (&str) == FAIL
3470 || cp_address_required_here (&str) == FAIL)
3473 inst.error = bad_args;
3481 do_fp_dyadic (str, flags)
3483 unsigned long flags;
3488 switch (inst.suffix)
3493 inst.instruction |= 0x00000080;
3496 inst.instruction |= 0x00080000;
3502 if (fp_reg_required_here (&str, 12) == FAIL)
3505 inst.error = bad_args;
3509 if (skip_past_comma (&str) == FAIL
3510 || fp_reg_required_here (&str, 16) == FAIL)
3513 inst.error = bad_args;
3517 if (skip_past_comma (&str) == FAIL
3518 || fp_op2 (&str) == FAIL)
3521 inst.error = bad_args;
3525 inst.instruction |= flags;
3531 do_fp_monadic (str, flags)
3533 unsigned long flags;
3538 switch (inst.suffix)
3543 inst.instruction |= 0x00000080;
3546 inst.instruction |= 0x00080000;
3552 if (fp_reg_required_here (&str, 12) == FAIL)
3555 inst.error = bad_args;
3559 if (skip_past_comma (&str) == FAIL
3560 || fp_op2 (&str) == FAIL)
3563 inst.error = bad_args;
3567 inst.instruction |= flags;
3573 do_fp_cmp (str, flags)
3575 unsigned long flags;
3580 if (fp_reg_required_here (&str, 16) == FAIL)
3583 inst.error = bad_args;
3587 if (skip_past_comma (&str) == FAIL
3588 || fp_op2 (&str) == FAIL)
3591 inst.error = bad_args;
3595 inst.instruction |= flags;
3601 do_fp_from_reg (str, flags)
3603 unsigned long flags;
3608 switch (inst.suffix)
3613 inst.instruction |= 0x00000080;
3616 inst.instruction |= 0x00080000;
3622 if (fp_reg_required_here (&str, 16) == FAIL)
3625 inst.error = bad_args;
3629 if (skip_past_comma (&str) == FAIL
3630 || reg_required_here (&str, 12) == FAIL)
3633 inst.error = bad_args;
3637 inst.instruction |= flags;
3643 do_fp_to_reg (str, flags)
3645 unsigned long flags;
3650 if (reg_required_here (&str, 12) == FAIL)
3653 if (skip_past_comma (&str) == FAIL
3654 || fp_reg_required_here (&str, 0) == FAIL)
3657 inst.error = bad_args;
3661 inst.instruction |= flags;
3666 /* Thumb specific routines */
3668 /* Parse and validate that a register is of the right form, this saves
3669 repeated checking of this information in many similar cases.
3670 Unlike the 32-bit case we do not insert the register into the opcode
3671 here, since the position is often unknown until the full instruction
3674 thumb_reg (strp, hi_lo)
3680 if ((reg = reg_required_here (strp, -1)) == FAIL)
3688 inst.error = _("lo register required");
3696 inst.error = _("hi register required");
3708 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3711 thumb_add_sub (str, subtract)
3715 int Rd, Rs, Rn = FAIL;
3720 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3721 || skip_past_comma (&str) == FAIL)
3724 inst.error = bad_args;
3732 if (my_get_expression (&inst.reloc.exp, &str))
3737 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3740 if (skip_past_comma (&str) == FAIL)
3742 /* Two operand format, shuffle the registers and pretend there
3747 else if (*str == '#')
3750 if (my_get_expression (&inst.reloc.exp, &str))
3753 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3757 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3758 for the latter case, EXPR contains the immediate that was found. */
3761 /* All register format. */
3762 if (Rd > 7 || Rs > 7 || Rn > 7)
3766 inst.error = _("dest and source1 must be the same register");
3770 /* Can't do this for SUB */
3773 inst.error = _("subtract valid only on lo regs");
3777 inst.instruction = (T_OPCODE_ADD_HI
3778 | (Rd > 7 ? THUMB_H1 : 0)
3779 | (Rn > 7 ? THUMB_H2 : 0));
3780 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
3784 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
3785 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
3790 /* Immediate expression, now things start to get nasty. */
3792 /* First deal with HI regs, only very restricted cases allowed:
3793 Adjusting SP, and using PC or SP to get an address. */
3794 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
3795 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
3797 inst.error = _("invalid Hi register with immediate");
3801 if (inst.reloc.exp.X_op != O_constant)
3803 /* Value isn't known yet, all we can do is store all the fragments
3804 we know about in the instruction and let the reloc hacking
3806 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
3807 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
3811 int offset = inst.reloc.exp.X_add_number;
3821 /* Quick check, in case offset is MIN_INT */
3824 inst.error = _("immediate value out of range");
3833 if (offset & ~0x1fc)
3835 inst.error = _("invalid immediate value for stack adjust");
3838 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
3839 inst.instruction |= offset >> 2;
3841 else if (Rs == REG_PC || Rs == REG_SP)
3844 || (offset & ~0x3fc))
3846 inst.error = _("invalid immediate for address calculation");
3849 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
3851 inst.instruction |= (Rd << 8) | (offset >> 2);
3857 inst.error = _("immediate value out of range");
3860 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
3861 inst.instruction |= (Rd << 8) | offset;
3867 inst.error = _("immediate value out of range");
3870 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
3871 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
3879 thumb_shift (str, shift)
3883 int Rd, Rs, Rn = FAIL;
3888 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
3889 || skip_past_comma (&str) == FAIL)
3892 inst.error = bad_args;
3898 /* Two operand immediate format, set Rs to Rd. */
3901 if (my_get_expression (&inst.reloc.exp, &str))
3906 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3909 if (skip_past_comma (&str) == FAIL)
3911 /* Two operand format, shuffle the registers and pretend there
3916 else if (*str == '#')
3919 if (my_get_expression (&inst.reloc.exp, &str))
3922 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3926 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3927 for the latter case, EXPR contains the immediate that was found. */
3933 inst.error = _("source1 and dest must be same register");
3939 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
3940 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
3941 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
3944 inst.instruction |= Rd | (Rn << 3);
3950 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
3951 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
3952 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
3955 if (inst.reloc.exp.X_op != O_constant)
3957 /* Value isn't known yet, create a dummy reloc and let reloc
3958 hacking fix it up */
3960 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
3964 unsigned shift_value = inst.reloc.exp.X_add_number;
3966 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
3968 inst.error = _("Invalid immediate for shift");
3972 /* Shifts of zero are handled by converting to LSL */
3973 if (shift_value == 0)
3974 inst.instruction = T_OPCODE_LSL_I;
3976 /* Shifts of 32 are encoded as a shift of zero */
3977 if (shift_value == 32)
3980 inst.instruction |= shift_value << 6;
3983 inst.instruction |= Rd | (Rs << 3);
3989 thumb_mov_compare (str, move)
3998 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3999 || skip_past_comma (&str) == FAIL)
4002 inst.error = bad_args;
4009 if (my_get_expression (&inst.reloc.exp, &str))
4012 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4017 if (Rs < 8 && Rd < 8)
4019 if (move == THUMB_MOVE)
4020 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4021 since a MOV instruction produces unpredictable results */
4022 inst.instruction = T_OPCODE_ADD_I3;
4024 inst.instruction = T_OPCODE_CMP_LR;
4025 inst.instruction |= Rd | (Rs << 3);
4029 if (move == THUMB_MOVE)
4030 inst.instruction = T_OPCODE_MOV_HR;
4032 inst.instruction = T_OPCODE_CMP_HR;
4035 inst.instruction |= THUMB_H1;
4038 inst.instruction |= THUMB_H2;
4040 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4047 inst.error = _("only lo regs allowed with immediate");
4051 if (move == THUMB_MOVE)
4052 inst.instruction = T_OPCODE_MOV_I8;
4054 inst.instruction = T_OPCODE_CMP_I8;
4056 inst.instruction |= Rd << 8;
4058 if (inst.reloc.exp.X_op != O_constant)
4059 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4062 unsigned value = inst.reloc.exp.X_add_number;
4066 inst.error = _("invalid immediate");
4070 inst.instruction |= value;
4078 thumb_load_store (str, load_store, size)
4083 int Rd, Rb, Ro = FAIL;
4088 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4089 || skip_past_comma (&str) == FAIL)
4092 inst.error = bad_args;
4099 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4102 if (skip_past_comma (&str) != FAIL)
4107 if (my_get_expression (&inst.reloc.exp, &str))
4110 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4115 inst.reloc.exp.X_op = O_constant;
4116 inst.reloc.exp.X_add_number = 0;
4121 inst.error = _("expected ']'");
4126 else if (*str == '=')
4128 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4134 if (my_get_expression (& inst.reloc.exp, & str))
4139 if ( inst.reloc.exp.X_op != O_constant
4140 && inst.reloc.exp.X_op != O_symbol)
4142 inst.error = "Constant expression expected";
4146 if (inst.reloc.exp.X_op == O_constant
4147 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4149 /* This can be done with a mov instruction */
4151 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4152 inst.instruction |= inst.reloc.exp.X_add_number;
4156 /* Insert into literal pool */
4157 if (add_to_lit_pool () == FAIL)
4160 inst.error = "literal pool insertion failed";
4164 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4165 inst.reloc.pc_rel = 1;
4166 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4167 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4173 if (my_get_expression (&inst.reloc.exp, &str))
4176 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4177 inst.reloc.pc_rel = 1;
4178 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4179 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4184 if (Rb == REG_PC || Rb == REG_SP)
4186 if (size != THUMB_WORD)
4188 inst.error = _("byte or halfword not valid for base register");
4191 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4193 inst.error = _("R15 based store not allowed");
4196 else if (Ro != FAIL)
4198 inst.error = _("Invalid base register for register offset");
4203 inst.instruction = T_OPCODE_LDR_PC;
4204 else if (load_store == THUMB_LOAD)
4205 inst.instruction = T_OPCODE_LDR_SP;
4207 inst.instruction = T_OPCODE_STR_SP;
4209 inst.instruction |= Rd << 8;
4210 if (inst.reloc.exp.X_op == O_constant)
4212 unsigned offset = inst.reloc.exp.X_add_number;
4214 if (offset & ~0x3fc)
4216 inst.error = _("invalid offset");
4220 inst.instruction |= offset >> 2;
4223 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4227 inst.error = _("invalid base register in load/store");
4230 else if (Ro == FAIL)
4232 /* Immediate offset */
4233 if (size == THUMB_WORD)
4234 inst.instruction = (load_store == THUMB_LOAD
4235 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4236 else if (size == THUMB_HALFWORD)
4237 inst.instruction = (load_store == THUMB_LOAD
4238 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4240 inst.instruction = (load_store == THUMB_LOAD
4241 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4243 inst.instruction |= Rd | (Rb << 3);
4245 if (inst.reloc.exp.X_op == O_constant)
4247 unsigned offset = inst.reloc.exp.X_add_number;
4249 if (offset & ~(0x1f << size))
4251 inst.error = _("Invalid offset");
4254 inst.instruction |= (offset >> size) << 6;
4257 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4261 /* Register offset */
4262 if (size == THUMB_WORD)
4263 inst.instruction = (load_store == THUMB_LOAD
4264 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4265 else if (size == THUMB_HALFWORD)
4266 inst.instruction = (load_store == THUMB_LOAD
4267 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4269 inst.instruction = (load_store == THUMB_LOAD
4270 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4272 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4287 /* Handle the Format 4 instructions that do not have equivalents in other
4288 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4299 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4302 if (skip_past_comma (&str) == FAIL
4303 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4306 inst.error = bad_args;
4310 if (skip_past_comma (&str) != FAIL)
4312 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4313 (It isn't allowed for CMP either, but that isn't handled by this
4315 if (inst.instruction == T_OPCODE_TST
4316 || inst.instruction == T_OPCODE_CMN
4317 || inst.instruction == T_OPCODE_NEG
4318 || inst.instruction == T_OPCODE_MVN)
4320 inst.error = bad_args;
4324 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4329 inst.error = _("dest and source1 one must be the same register");
4335 if (inst.instruction == T_OPCODE_MUL
4337 as_tsktsk (_("Rs and Rd must be different in MUL"));
4339 inst.instruction |= Rd | (Rs << 3);
4347 thumb_add_sub (str, 0);
4354 thumb_shift (str, THUMB_ASR);
4361 if (my_get_expression (&inst.reloc.exp, &str))
4363 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4364 inst.reloc.pc_rel = 1;
4372 if (my_get_expression (&inst.reloc.exp, &str))
4374 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4375 inst.reloc.pc_rel = 1;
4379 /* Find the real, Thumb encoded start of a Thumb function. */
4382 find_real_start (symbolP)
4386 const char * name = S_GET_NAME (symbolP);
4387 symbolS * new_target;
4389 /* This definitonmust agree with the one in gcc/config/arm/thumb.c */
4390 #define STUB_NAME ".real_start_of"
4395 /* Names that start with '.' are local labels, not function entry points.
4396 The compiler may generate BL instructions to these labels because it
4397 needs to perform a branch to a far away location. */
4401 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4402 sprintf (real_start, "%s%s", STUB_NAME, name);
4404 new_target = symbol_find (real_start);
4406 if (new_target == NULL)
4408 as_warn ("Failed to find real start of function: %s\n", name);
4409 new_target = symbolP;
4422 if (my_get_expression (&inst.reloc.exp, &str))
4424 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4425 inst.reloc.pc_rel = 1;
4428 /* If the destination of the branch is a defined symbol which does not have
4429 the THUMB_FUNC attribute, then we must be calling a function which has
4430 the (interfacearm) attribute. We look for the Thumb entry point to that
4431 function and change the branch to refer to that function instead. */
4432 if ( inst.reloc.exp.X_op == O_symbol
4433 && inst.reloc.exp.X_add_symbol != NULL
4434 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4435 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4436 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4448 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4451 /* This sets THUMB_H2 from the top bit of reg. */
4452 inst.instruction |= reg << 3;
4454 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4455 should cause the alignment to be checked once it is known. This is
4456 because BX PC only works if the instruction is word aligned. */
4465 thumb_mov_compare (str, THUMB_COMPARE);
4478 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4482 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4486 if (skip_past_comma (&str) == FAIL
4487 || (range = reg_list (&str)) == FAIL)
4490 inst.error = bad_args;
4494 if (inst.reloc.type != BFD_RELOC_NONE)
4496 /* This really doesn't seem worth it. */
4497 inst.reloc.type = BFD_RELOC_NONE;
4498 inst.error = _("Expression too complex");
4504 inst.error = _("only lo-regs valid in load/store multiple");
4508 inst.instruction |= (Rb << 8) | range;
4516 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4523 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4530 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4542 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4543 || skip_past_comma (&str) == FAIL
4545 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4546 || skip_past_comma (&str) == FAIL
4547 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4551 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4555 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4563 thumb_shift (str, THUMB_LSL);
4570 thumb_shift (str, THUMB_LSR);
4577 thumb_mov_compare (str, THUMB_MOVE);
4589 if ((range = reg_list (&str)) == FAIL)
4592 inst.error = bad_args;
4596 if (inst.reloc.type != BFD_RELOC_NONE)
4598 /* This really doesn't seem worth it. */
4599 inst.reloc.type = BFD_RELOC_NONE;
4600 inst.error = _("Expression too complex");
4606 if ((inst.instruction == T_OPCODE_PUSH
4607 && (range & ~0xff) == 1 << REG_LR)
4608 || (inst.instruction == T_OPCODE_POP
4609 && (range & ~0xff) == 1 << REG_PC))
4611 inst.instruction |= THUMB_PP_PC_LR;
4616 inst.error = _("invalid register list to push/pop instruction");
4621 inst.instruction |= range;
4629 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4636 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4643 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4650 thumb_add_sub (str, 1);
4660 if (my_get_expression (&inst.reloc.exp, &str))
4663 inst.reloc.type = BFD_RELOC_ARM_SWI;
4672 /* This is a pseudo-op of the form "adr rd, label" to be converted
4673 into a relative address of the form "add rd, pc, #label-.-4" */
4677 if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
4678 || skip_past_comma (&str) == FAIL
4679 || my_get_expression (&inst.reloc.exp, &str))
4682 inst.error = bad_args;
4686 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4687 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust */
4688 inst.reloc.pc_rel = 1;
4689 inst.instruction |= REG_PC; /* Rd is already placed into the instruction */
4697 int len = strlen (reg_table[entry].name) + 2;
4698 char *buf = (char *) xmalloc (len);
4699 char *buf2 = (char *) xmalloc (len);
4702 #ifdef REGISTER_PREFIX
4703 buf[i++] = REGISTER_PREFIX;
4706 strcpy (buf + i, reg_table[entry].name);
4708 for (i = 0; buf[i]; i++)
4709 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4713 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4714 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4718 insert_reg_alias (str, regnum)
4722 struct reg_entry *new =
4723 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4724 char *name = xmalloc (strlen (str) + 1);
4728 new->number = regnum;
4730 hash_insert (arm_reg_hsh, name, (PTR) new);
4734 set_constant_flonums ()
4738 for (i = 0; i < NUM_FLOAT_VALS; i++)
4739 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4748 if ((arm_ops_hsh = hash_new ()) == NULL
4749 || (arm_tops_hsh = hash_new ()) == NULL
4750 || (arm_cond_hsh = hash_new ()) == NULL
4751 || (arm_shift_hsh = hash_new ()) == NULL
4752 || (arm_reg_hsh = hash_new ()) == NULL
4753 || (arm_psr_hsh = hash_new ()) == NULL)
4754 as_fatal (_("Virtual memory exhausted"));
4756 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4757 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4758 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
4759 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
4760 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
4761 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
4762 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
4763 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
4764 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
4765 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
4767 for (i = 0; reg_table[i].name; i++)
4770 set_constant_flonums ();
4772 #if defined OBJ_COFF || defined OBJ_ELF
4774 unsigned int flags = 0;
4776 /* Set the flags in the private structure */
4777 if (uses_apcs_26) flags |= F_APCS26;
4778 if (support_interwork) flags |= F_INTERWORK;
4779 if (uses_apcs_float) flags |= F_APCS_FLOAT;
4780 if (pic_code) flags |= F_PIC;
4782 bfd_set_private_flags (stdoutput, flags);
4789 /* Record the CPU type as well */
4790 switch (cpu_variant & ARM_CPU_MASK)
4793 mach = bfd_mach_arm_2;
4796 case ARM_3: /* also ARM_250 */
4797 mach = bfd_mach_arm_2a;
4801 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined */
4802 mach = bfd_mach_arm_4;
4805 case ARM_7: /* also ARM_6 */
4806 mach = bfd_mach_arm_3;
4810 /* Catch special cases */
4811 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
4813 if (cpu_variant & ARM_THUMB)
4814 mach = bfd_mach_arm_4T;
4815 else if ((cpu_variant & ARM_ARCHv4) == ARM_ARCHv4)
4816 mach = bfd_mach_arm_4;
4817 else if (cpu_variant & ARM_LONGMUL)
4818 mach = bfd_mach_arm_3M;
4821 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
4825 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
4826 for use in the a.out file, and stores them in the array pointed to by buf.
4827 This knows about the endian-ness of the target machine and does
4828 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
4829 2 (short) and 4 (long) Floating numbers are put out as a series of
4830 LITTLENUMS (shorts, here at least)
4833 md_number_to_chars (buf, val, n)
4838 if (target_big_endian)
4839 number_to_chars_bigendian (buf, val, n);
4841 number_to_chars_littleendian (buf, val, n);
4845 md_chars_to_number (buf, n)
4850 unsigned char *where = (unsigned char *) buf;
4852 if (target_big_endian)
4857 result |= (*where++ & 255);
4865 result |= (where[n] & 255);
4872 /* Turn a string in input_line_pointer into a floating point constant
4873 of type TYPE, and store the appropriate bytes in *litP. The number
4874 of LITTLENUMS emitted is stored in *sizeP . An error message is
4875 returned, or NULL on OK.
4877 Note that fp constants aren't represent in the normal way on the ARM.
4878 In big endian mode, things are as expected. However, in little endian
4879 mode fp constants are big-endian word-wise, and little-endian byte-wise
4880 within the words. For example, (double) 1.1 in big endian mode is
4881 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
4882 the byte sequence 99 99 f1 3f 9a 99 99 99.
4884 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
4887 md_atof (type, litP, sizeP)
4893 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4925 return _("Bad call to MD_ATOF()");
4928 t = atof_ieee (input_line_pointer, type, words);
4930 input_line_pointer = t;
4933 if (target_big_endian)
4935 for (i = 0; i < prec; i++)
4937 md_number_to_chars (litP, (valueT) words[i], 2);
4943 /* For a 4 byte float the order of elements in `words' is 1 0. For an
4944 8 byte float the order is 1 0 3 2. */
4945 for (i = 0; i < prec; i += 2)
4947 md_number_to_chars (litP, (valueT) words[i + 1], 2);
4948 md_number_to_chars (litP + 2, (valueT) words[i], 2);
4956 /* We have already put the pipeline compensation in the instruction */
4959 md_pcrel_from (fixP)
4963 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
4964 && fixP->fx_subsy == NULL)
4965 return 0; /* HACK */
4967 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
4969 /* PC relative addressing on the Thumb is slightly odd
4970 as the bottom two bits of the PC are forced to zero
4971 for the calculation */
4972 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
4975 return fixP->fx_where + fixP->fx_frag->fr_address;
4978 /* Round up a section size to the appropriate boundary. */
4980 md_section_align (segment, size)
4985 /* Don't align the dwarf2 debug sections */
4986 if (!strncmp(segment->name,".debug",5))
4989 /* Round all sects to multiple of 4 */
4990 return (size + 3) & ~3;
4993 /* We have no need to default values of symbols. */
4997 md_undefined_symbol (name)
5003 /* arm_reg_parse () := if it looks like a register, return its token and
5004 advance the pointer. */
5008 register char **ccp;
5013 struct reg_entry *reg;
5015 #ifdef REGISTER_PREFIX
5016 if (*start != REGISTER_PREFIX)
5021 #ifdef OPTIONAL_REGISTER_PREFIX
5022 if (*p == OPTIONAL_REGISTER_PREFIX)
5026 if (!isalpha (*p) || !is_name_beginner (*p))
5030 while (isalpha (c) || isdigit (c) || c == '_')
5034 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5048 register char **ccp;
5052 CONST struct asm_psr *psr;
5056 while (isalpha (c) || c == '_')
5060 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5073 md_apply_fix3 (fixP, val, seg)
5078 offsetT value = *val;
5080 unsigned int newimm;
5083 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5084 arm_fix_data *arm_data = (arm_fix_data *) fixP->tc_fix_data;
5086 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5088 /* Note whether this will delete the relocation. */
5089 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5090 if ((fixP->fx_addsy == 0 || fixP->fx_addsy->sy_value.X_op == O_constant)
5093 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5097 /* If this symbol is in a different section then we need to leave it for
5098 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5099 so we have to undo it's effects here. */
5102 if (fixP->fx_addsy != NULL
5103 && S_IS_DEFINED (fixP->fx_addsy)
5104 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5106 if (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
5109 value += md_pcrel_from (fixP);
5113 fixP->fx_addnumber = value; /* Remember value for emit_reloc */
5115 switch (fixP->fx_r_type)
5117 case BFD_RELOC_ARM_IMMEDIATE:
5118 newimm = validate_immediate (value);
5119 temp = md_chars_to_number (buf, INSN_SIZE);
5121 /* If the instruction will fail, see if we can fix things up by
5122 changing the opcode. */
5123 if (newimm == (unsigned int) FAIL
5124 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5126 as_bad_where (fixP->fx_file, fixP->fx_line,
5127 _("invalid constant after fixup\n"));
5131 newimm |= (temp & 0xfffff000);
5132 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5135 case BFD_RELOC_ARM_OFFSET_IMM:
5137 if ((value = validate_offset_imm (value, 0)) == FAIL)
5139 as_bad (_("bad immediate value for offset (%d)"), val);
5145 newval = md_chars_to_number (buf, INSN_SIZE);
5146 newval &= 0xff7ff000;
5147 newval |= value | (sign ? INDEX_UP : 0);
5148 md_number_to_chars (buf, newval, INSN_SIZE);
5151 case BFD_RELOC_ARM_OFFSET_IMM8:
5152 case BFD_RELOC_ARM_HWLITERAL:
5154 if ((value = validate_offset_imm (value, 1)) == FAIL)
5156 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5157 as_bad_where (fixP->fx_file, fixP->fx_line,
5158 _("invalid literal constant: pool needs to be closer\n"));
5160 as_bad (_("bad immediate value for offset (%d)"), value);
5167 newval = md_chars_to_number (buf, INSN_SIZE);
5168 newval &= 0xff7ff0f0;
5169 newval |= ((value >> 4) << 8) | value & 0xf | (sign ? INDEX_UP : 0);
5170 md_number_to_chars (buf, newval, INSN_SIZE);
5173 case BFD_RELOC_ARM_LITERAL:
5178 if ((value = validate_offset_imm (value, 0)) == FAIL)
5180 as_bad_where (fixP->fx_file, fixP->fx_line,
5181 _("invalid literal constant: pool needs to be closer\n"));
5185 newval = md_chars_to_number (buf, INSN_SIZE);
5186 newval &= 0xff7ff000;
5187 newval |= value | (sign ? INDEX_UP : 0);
5188 md_number_to_chars (buf, newval, INSN_SIZE);
5191 case BFD_RELOC_ARM_SHIFT_IMM:
5192 newval = md_chars_to_number (buf, INSN_SIZE);
5193 if (((unsigned long) value) > 32
5195 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5197 as_bad_where (fixP->fx_file, fixP->fx_line,
5198 _("shift expression is too large"));
5203 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5204 else if (value == 32)
5206 newval &= 0xfffff07f;
5207 newval |= (value & 0x1f) << 7;
5208 md_number_to_chars (buf, newval , INSN_SIZE);
5211 case BFD_RELOC_ARM_SWI:
5212 if (arm_data->thumb_mode)
5214 if (((unsigned long) value) > 0xff)
5215 as_bad_where (fixP->fx_file, fixP->fx_line,
5216 _("Invalid swi expression"));
5217 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5219 md_number_to_chars (buf, newval, THUMB_SIZE);
5223 if (((unsigned long) value) > 0x00ffffff)
5224 as_bad_where (fixP->fx_file, fixP->fx_line,
5225 _("Invalid swi expression"));
5226 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5228 md_number_to_chars (buf, newval , INSN_SIZE);
5232 case BFD_RELOC_ARM_MULTI:
5233 if (((unsigned long) value) > 0xffff)
5234 as_bad_where (fixP->fx_file, fixP->fx_line,
5235 _("Invalid expression in load/store multiple"));
5236 newval = value | md_chars_to_number (buf, INSN_SIZE);
5237 md_number_to_chars (buf, newval, INSN_SIZE);
5240 case BFD_RELOC_ARM_PCREL_BRANCH:
5243 value = (value >> 2) & 0x00ffffff;
5245 value = fixP->fx_offset;
5247 value = (value >> 2) & 0x00ffffff;
5249 newval = md_chars_to_number (buf, INSN_SIZE);
5252 newval = (newval & 0xff000000);
5254 newval = (newval & 0xff000000);
5255 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5256 newval = value | (newval & 0xff000000);
5257 md_number_to_chars (buf, newval, INSN_SIZE);
5260 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5261 newval = md_chars_to_number (buf, THUMB_SIZE);
5263 addressT diff = (newval & 0xff) << 1;
5268 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5269 as_bad_where (fixP->fx_file, fixP->fx_line,
5270 _("Branch out of range"));
5271 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5273 md_number_to_chars (buf, newval, THUMB_SIZE);
5276 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5277 newval = md_chars_to_number (buf, THUMB_SIZE);
5279 addressT diff = (newval & 0x7ff) << 1;
5284 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5285 as_bad_where (fixP->fx_file, fixP->fx_line,
5286 _("Branch out of range"));
5287 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5289 md_number_to_chars (buf, newval, THUMB_SIZE);
5292 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5297 newval = md_chars_to_number (buf, THUMB_SIZE);
5298 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5299 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5300 if (diff & 0x400000)
5303 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5304 as_bad_where (fixP->fx_file, fixP->fx_line,
5305 _("Branch with link out of range"));
5307 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5308 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5309 md_number_to_chars (buf, newval, THUMB_SIZE);
5310 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5315 if (fixP->fx_done || fixP->fx_pcrel)
5316 md_number_to_chars (buf, value, 1);
5318 else if (!target_oabi)
5320 value = fixP->fx_offset;
5321 md_number_to_chars (buf, value, 1);
5327 if (fixP->fx_done || fixP->fx_pcrel)
5328 md_number_to_chars (buf, value, 2);
5330 else if (!target_oabi)
5332 value = fixP->fx_offset;
5333 md_number_to_chars (buf, value, 2);
5341 if (fixP->fx_done || fixP->fx_pcrel)
5342 md_number_to_chars (buf, value, 4);
5346 value = fixP->fx_offset;
5347 md_number_to_chars (buf, value, 4);
5349 else if (fixP->fx_done || fixP->fx_pcrel)
5350 md_number_to_chars (buf, value, 4);
5354 case BFD_RELOC_ARM_CP_OFF_IMM:
5356 if (value < -1023 || value > 1023 || (value & 3))
5357 as_bad_where (fixP->fx_file, fixP->fx_line,
5358 _("Illegal value for co-processor offset"));
5361 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5362 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5363 md_number_to_chars (buf, newval , INSN_SIZE);
5366 case BFD_RELOC_ARM_THUMB_OFFSET:
5367 newval = md_chars_to_number (buf, THUMB_SIZE);
5368 /* Exactly what ranges, and where the offset is inserted depends on
5369 the type of instruction, we can establish this from the top 4 bits */
5370 switch (newval >> 12)
5372 case 4: /* PC load */
5373 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5374 forced to zero for these loads, so we will need to round
5375 up the offset if the instruction address is not word
5376 aligned (since the final address produced must be, and
5377 we can only describe word-aligned immediate offsets). */
5379 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5380 as_bad_where (fixP->fx_file, fixP->fx_line,
5381 _("Invalid offset, target not word aligned (0x%08X)"),
5382 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5384 if ((value + 2) & ~0x3fe)
5385 as_bad_where (fixP->fx_file, fixP->fx_line,
5386 _("Invalid offset"));
5388 /* Round up, since pc will be rounded down. */
5389 newval |= (value + 2) >> 2;
5392 case 9: /* SP load/store */
5394 as_bad_where (fixP->fx_file, fixP->fx_line,
5395 _("Invalid offset"));
5396 newval |= value >> 2;
5399 case 6: /* Word load/store */
5401 as_bad_where (fixP->fx_file, fixP->fx_line,
5402 _("Invalid offset"));
5403 newval |= value << 4; /* 6 - 2 */
5406 case 7: /* Byte load/store */
5408 as_bad_where (fixP->fx_file, fixP->fx_line,
5409 _("Invalid offset"));
5410 newval |= value << 6;
5413 case 8: /* Halfword load/store */
5415 as_bad_where (fixP->fx_file, fixP->fx_line,
5416 _("Invalid offset"));
5417 newval |= value << 5; /* 6 - 1 */
5421 as_bad_where (fixP->fx_file, fixP->fx_line,
5422 "Unable to process relocation for thumb opcode: %x", newval);
5425 md_number_to_chars (buf, newval, THUMB_SIZE);
5428 case BFD_RELOC_ARM_THUMB_ADD:
5429 /* This is a complicated relocation, since we use it for all of
5430 the following immediate relocations:
5433 9bit ADD/SUB SP word-aligned
5434 10bit ADD PC/SP word-aligned
5436 The type of instruction being processed is encoded in the
5442 newval = md_chars_to_number (buf, THUMB_SIZE);
5444 int rd = (newval >> 4) & 0xf;
5445 int rs = newval & 0xf;
5446 int subtract = newval & 0x8000;
5451 as_bad_where (fixP->fx_file, fixP->fx_line,
5452 _("Invalid immediate for stack address calculation"));
5453 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5454 newval |= value >> 2;
5456 else if (rs == REG_PC || rs == REG_SP)
5460 as_bad_where (fixP->fx_file, fixP->fx_line,
5461 _("Invalid immediate for address calculation (value = 0x%08X)"), value);
5462 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5464 newval |= value >> 2;
5469 as_bad_where (fixP->fx_file, fixP->fx_line,
5470 _("Invalid 8bit immediate"));
5471 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5472 newval |= (rd << 8) | value;
5477 as_bad_where (fixP->fx_file, fixP->fx_line,
5478 _("Invalid 3bit immediate"));
5479 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5480 newval |= rd | (rs << 3) | (value << 6);
5483 md_number_to_chars (buf, newval , THUMB_SIZE);
5486 case BFD_RELOC_ARM_THUMB_IMM:
5487 newval = md_chars_to_number (buf, THUMB_SIZE);
5488 switch (newval >> 11)
5490 case 0x04: /* 8bit immediate MOV */
5491 case 0x05: /* 8bit immediate CMP */
5492 if (value < 0 || value > 255)
5493 as_bad_where (fixP->fx_file, fixP->fx_line,
5494 _("Invalid immediate: %d is too large"), value);
5501 md_number_to_chars (buf, newval , THUMB_SIZE);
5504 case BFD_RELOC_ARM_THUMB_SHIFT:
5505 /* 5bit shift value (0..31) */
5506 if (value < 0 || value > 31)
5507 as_bad_where (fixP->fx_file, fixP->fx_line,
5508 _("Illegal Thumb shift value: %d"), value);
5509 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5510 newval |= value << 6;
5511 md_number_to_chars (buf, newval , THUMB_SIZE);
5514 case BFD_RELOC_VTABLE_INHERIT:
5515 case BFD_RELOC_VTABLE_ENTRY:
5519 case BFD_RELOC_NONE:
5521 as_bad_where (fixP->fx_file, fixP->fx_line,
5522 _("Bad relocation fixup type (%d)\n"), fixP->fx_r_type);
5528 /* Translate internal representation of relocation info to BFD target
5531 tc_gen_reloc (section, fixp)
5536 bfd_reloc_code_real_type code;
5538 reloc = (arelent *) xmalloc (sizeof (arelent));
5540 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
5541 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5543 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5545 if (fixp->fx_pcrel == 0)
5546 reloc->addend = fixp->fx_offset;
5548 reloc->addend = fixp->fx_offset = reloc->address;
5550 reloc->addend = fixp->fx_offset;
5553 switch (fixp->fx_r_type)
5558 code = BFD_RELOC_8_PCREL;
5565 code = BFD_RELOC_16_PCREL;
5572 code = BFD_RELOC_32_PCREL;
5576 case BFD_RELOC_ARM_PCREL_BRANCH:
5578 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5579 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5580 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5581 case BFD_RELOC_VTABLE_ENTRY:
5582 case BFD_RELOC_VTABLE_INHERIT:
5583 code = fixp->fx_r_type;
5586 case BFD_RELOC_ARM_LITERAL:
5587 case BFD_RELOC_ARM_HWLITERAL:
5588 /* If this is called then the a literal has been referenced across
5589 a section boundry - possibly due to an implicit dump */
5590 as_bad_where (fixp->fx_file, fixp->fx_line,
5591 _("Literal referenced across section boundry (Implicit dump?)"));
5594 case BFD_RELOC_ARM_IMMEDIATE:
5595 as_bad_where (fixp->fx_file, fixp->fx_line,
5596 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5600 case BFD_RELOC_ARM_OFFSET_IMM:
5601 as_bad_where (fixp->fx_file, fixp->fx_line,
5602 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
5609 switch (fixp->fx_r_type)
5611 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
5612 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
5613 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
5614 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
5615 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
5616 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
5617 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
5618 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
5619 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
5620 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
5621 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
5622 default: type = "<unknown>"; break;
5624 as_bad_where (fixp->fx_file, fixp->fx_line,
5625 _("Can not represent %s relocation in this object file format (%d)"),
5626 type, fixp->fx_pcrel);
5631 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
5633 if (reloc->howto == NULL)
5635 as_bad_where (fixp->fx_file, fixp->fx_line,
5636 _("Can not represent %s relocation in this object file format"),
5637 bfd_get_reloc_code_name (code));
5645 md_estimate_size_before_relax (fragP, segtype)
5649 as_fatal (_("md_estimate_size_before_relax\n"));
5661 as_bad (inst.error);
5665 to = frag_more (inst.size);
5666 if (thumb_mode && (inst.size > THUMB_SIZE))
5668 assert (inst.size == (2 * THUMB_SIZE));
5669 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
5670 md_number_to_chars (to + 2, inst.instruction, THUMB_SIZE);
5673 md_number_to_chars (to, inst.instruction, inst.size);
5675 if (inst.reloc.type != BFD_RELOC_NONE)
5676 fix_new_arm (frag_now, to - frag_now->fr_literal,
5677 inst.size, &inst.reloc.exp, inst.reloc.pc_rel,
5688 char *p, *q, *start;
5690 /* Align the instruction */
5691 /* this may not be the right thing to do but ... */
5692 /* arm_align (2, 0); */
5693 listing_prev_line (); /* Defined in listing.h */
5695 /* Align the previous label if needed */
5696 if (last_label_seen != NULL)
5698 last_label_seen->sy_frag = frag_now;
5699 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5700 S_SET_SEGMENT (last_label_seen, now_seg);
5703 memset (&inst, '\0', sizeof (inst));
5704 inst.reloc.type = BFD_RELOC_NONE;
5707 str++; /* Skip leading white space */
5709 /* scan up to the end of the op-code, which must end in white space or
5711 for (start = p = str; *p != '\0'; p++)
5717 as_bad (_("No operator -- statement `%s'\n"), str);
5723 CONST struct thumb_opcode *opcode;
5727 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
5731 inst.instruction = opcode->value;
5732 inst.size = opcode->size;
5733 (*opcode->parms)(p);
5734 output_inst (start);
5740 CONST struct asm_opcode *opcode;
5742 inst.size = INSN_SIZE;
5743 /* p now points to the end of the opcode, probably white space, but we
5744 have to break the opcode up in case it contains condionals and flags;
5745 keep trying with progressively smaller basic instructions until one
5746 matches, or we run out of opcode. */
5747 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
5748 for (; q != str; q--)
5752 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
5754 if (opcode && opcode->template)
5756 unsigned long flag_bits = 0;
5759 /* Check that this instruction is supported for this CPU */
5760 if ((opcode->variants & cpu_variant) == 0)
5763 inst.instruction = opcode->value;
5764 if (q == p) /* Just a simple opcode */
5766 if (opcode->comp_suffix != 0)
5767 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
5768 opcode->comp_suffix);
5771 inst.instruction |= COND_ALWAYS;
5772 (*opcode->parms)(q, 0);
5774 output_inst (start);
5778 /* Now check for a conditional */
5782 CONST struct asm_cond *cond;
5786 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
5790 if (cond->value == 0xf0000000)
5792 _("Warning: Use of the 'nv' conditional is deprecated\n"));
5794 inst.instruction |= cond->value;
5798 inst.instruction |= COND_ALWAYS;
5801 inst.instruction |= COND_ALWAYS;
5803 /* if there is a compulsory suffix, it should come here, before
5804 any optional flags. */
5805 if (opcode->comp_suffix)
5807 CONST char *s = opcode->comp_suffix;
5819 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
5820 opcode->comp_suffix);
5827 /* The remainder, if any should now be flags for the instruction;
5828 Scan these checking each one found with the opcode. */
5832 CONST struct asm_flg *flag = opcode->flags;
5841 for (flagno = 0; flag[flagno].template; flagno++)
5843 if (! strcmp (r, flag[flagno].template))
5845 flag_bits |= flag[flagno].set_bits;
5851 if (! flag[flagno].template)
5858 (*opcode->parms) (p, flag_bits);
5859 output_inst (start);
5868 /* It wasn't an instruction, but it might be a register alias of the form
5878 if (*q && !strncmp (q, ".req ", 4))
5881 char * copy_of_str = str;
5888 for (r = q; *r != '\0'; r++)
5898 regnum = arm_reg_parse (& q);
5901 reg = arm_reg_parse (& str);
5907 insert_reg_alias (str, regnum);
5911 as_warn (_("register '%s' does not exist\n"), q);
5914 else if (regnum != FAIL)
5917 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str );
5919 /* Do not warn abpout redefinitions to the same alias. */
5922 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
5926 as_warn (_("ignoring incomplete .req pseuso op"));
5933 as_bad (_("bad instruction `%s'"), start);
5938 * Invocation line includes a switch not recognized by the base assembler.
5939 * See if it's a processor-specific option. These are:
5940 * Cpu variants, the arm part is optional:
5941 * -m[arm]1 Currently not supported.
5942 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
5943 * -m[arm]3 Arm 3 processor
5944 * -m[arm]6[xx], Arm 6 processors
5945 * -m[arm]7[xx][t][[d]m] Arm 7 processors
5946 * -mstrongarm[110] Arm 8 processors
5947 * -mall All (except the ARM1)
5949 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
5950 * -mfpe-old (No float load/store multiples)
5951 * -mno-fpu Disable all floating point instructions
5952 * Run-time endian selection:
5953 * -EB big endian cpu
5954 * -EL little endian cpu
5955 * ARM Procedure Calling Standard:
5956 * -mapcs-32 32 bit APCS
5957 * -mapcs-26 26 bit APCS
5958 * -mapcs-float Pass floats in float regs
5959 * -mapcs-reentrant Position independent code
5960 * -mthumb-interwork Code supports Arm/Thumb interworking
5963 CONST char *md_shortopts = "m:";
5964 struct option md_longopts[] =
5966 #ifdef ARM_BI_ENDIAN
5967 #define OPTION_EB (OPTION_MD_BASE + 0)
5968 {"EB", no_argument, NULL, OPTION_EB},
5969 #define OPTION_EL (OPTION_MD_BASE + 1)
5970 {"EL", no_argument, NULL, OPTION_EL},
5972 #define OPTION_OABI (OPTION_MD_BASE +2)
5973 {"oabi", no_argument, NULL, OPTION_OABI},
5976 {NULL, no_argument, NULL, 0}
5978 size_t md_longopts_size = sizeof (md_longopts);
5981 md_parse_option (c, arg)
5989 #ifdef ARM_BI_ENDIAN
5991 target_big_endian = 1;
5994 target_big_endian = 0;
6002 if (! strcmp (str, "fpa10"))
6003 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6004 else if (! strcmp (str, "fpa11"))
6005 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6006 else if (! strcmp (str, "fpe-old"))
6007 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6013 if (! strcmp (str, "no-fpu"))
6014 cpu_variant &= ~FPU_ALL;
6018 if (!strcmp (str, "oabi"))
6023 /* Limit assembler to generating only Thumb instructions: */
6024 if (! strcmp (str, "thumb"))
6026 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6027 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6030 else if (! strcmp (str, "thumb-interwork"))
6032 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCHv4;
6033 #if defined OBJ_COFF || defined OBJ_ELF
6034 support_interwork = true;
6042 if (! strcmp (str, "all"))
6044 cpu_variant = ARM_ALL | FPU_ALL;
6047 #if defined OBJ_COFF || defined OBJ_ELF
6048 if (! strncmp (str, "apcs-", 5))
6050 /* GCC passes on all command line options starting "-mapcs-..."
6051 to us, so we must parse them here. */
6055 if (! strcmp (str, "32"))
6057 uses_apcs_26 = false;
6060 else if (! strcmp (str, "26"))
6062 uses_apcs_26 = true;
6065 else if (! strcmp (str, "frame"))
6067 /* Stack frames are being generated - does not affect
6071 else if (! strcmp (str, "stack-check"))
6073 /* Stack checking is being performed - does not affect
6074 linkage, but does require that the functions
6075 __rt_stkovf_split_small and __rt_stkovf_split_big be
6076 present in the final link. */
6080 else if (! strcmp (str, "float"))
6082 /* Floating point arguments are being passed in the floating
6083 point registers. This does affect linking, since this
6084 version of the APCS is incompatible with the version that
6085 passes floating points in the integer registers. */
6087 uses_apcs_float = true;
6090 else if (! strcmp (str, "reentrant"))
6092 /* Reentrant code has been generated. This does affect
6093 linking, since there is no point in linking reentrant/
6094 position independent code with absolute position code. */
6099 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6103 /* Strip off optional "arm" */
6104 if (! strncmp (str, "arm", 3))
6110 if (! strcmp (str, "1"))
6111 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6117 if (! strcmp (str, "2"))
6118 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6119 else if (! strcmp (str, "250"))
6120 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6126 if (! strcmp (str, "3"))
6127 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6133 if (! strcmp (str, "strongarm") || ! strcmp (str, "strongarm110"))
6134 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6140 if (! strcmp (str, "8"))
6141 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6146 switch (strtol (str, NULL, 10))
6153 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6161 switch (strtol (str, & str, 10)) /* Eat the processor name */
6173 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6179 cpu_variant |= (ARM_THUMB | ARM_ARCHv4);
6183 cpu_variant |= ARM_LONGMUL;
6186 case 'f': /* fe => fp enabled cpu. */
6192 case 'c': /* Unknown */
6193 case 'd': /* debug */
6194 case 'i': /* embedded ice */
6195 /* Included for completeness in ARM processor naming. */
6205 /* Select variant based on architecture rather than processor */
6211 case 'a': cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; break;
6212 case 0: cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; break;
6213 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6218 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6222 case 'm': cpu_variant |= ARM_LONGMUL; break;
6224 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6229 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCHv4;
6233 case 't': cpu_variant |= ARM_THUMB; break;
6235 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6240 as_bad (_("Invalid architecture variant -m%s"), arg);
6247 as_bad (_("Invalid processor variant -m%s"), arg);
6266 ARM Specific Assembler Options:\n\
6267 -m[arm][<processor name>] select processor variant\n\
6268 -m[arm]v[2|2a|3|3m|4|4t] select architecture variant\n\
6269 -mthumb only allow Thumb instructions\n\
6270 -mthumb-interwork mark the assembled code as supporting interworking\n\
6271 -mall allow any instruction\n\
6272 -mfpa10, -mfpa11 select floating point architecture\n\
6273 -mfpe-old don't allow floating-point multiple instructions\n\
6274 -mno-fpu don't allow any floating-point instructions.\n"));
6275 #if defined OBJ_COFF || defined OBJ_ELF
6278 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n"));
6281 -mapcs-float floating point args are passed in FP regs\n"));
6284 -mapcs-reentrant the code is position independent/reentrant\n"));
6286 #ifdef ARM_BI_ENDIAN
6289 -EB assemble code for a big endian cpu\n\
6290 -EL assemble code for a little endian cpu\n"));
6294 /* We need to be able to fix up arbitrary expressions in some statements.
6295 This is so that we can handle symbols that are an arbitrary distance from
6296 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6297 which returns part of an address in a form which will be valid for
6298 a data instruction. We do this by pushing the expression into a symbol
6299 in the expr_section, and creating a fix for that. */
6302 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6311 arm_fix_data *arm_data;
6319 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6323 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6328 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6329 arm_data = (arm_fix_data *) obstack_alloc (¬es, sizeof (arm_fix_data));
6330 new_fix->tc_fix_data = (PTR) arm_data;
6331 arm_data->thumb_mode = thumb_mode;
6336 /* A good place to do this, although this was probably not intended
6337 * for this kind of use. We need to dump the literal pool before
6338 * references are made to a null symbol pointer. */
6342 if (current_poolP != NULL)
6344 subseg_set (text_section, 0); /* Put it at the end of text section */
6346 listing_prev_line ();
6351 arm_start_line_hook ()
6353 last_label_seen = NULL;
6357 arm_frob_label (sym)
6360 last_label_seen = sym;
6361 ARM_SET_THUMB (sym, thumb_mode);
6362 #if defined OBJ_COFF || defined OBJ_ELF
6363 ARM_SET_INTERWORK (sym, support_interwork);
6366 if (label_is_thumb_function_name)
6368 /* When the address of a Thumb function is taken the bottom
6369 bit of that address should be set. This will allow
6370 interworking between Arm and Thumb functions to work
6373 THUMB_SET_FUNC (sym, 1);
6375 label_is_thumb_function_name = false;
6379 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6383 #define S_GET_STORAGE_CLASS(S) (elf_symbol ((S)->bsym)->internal_elf_sym.st_info)
6384 #define S_SET_STORAGE_CLASS(S,V) (elf_symbol ((S)->bsym)->internal_elf_sym.st_info = (V))
6387 arm_adjust_symtab ()
6392 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6394 if (ARM_IS_THUMB (sym))
6396 if (THUMB_IS_FUNC (sym))
6398 /* Mark the symbol as a Thumb function. */
6399 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6400 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6401 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6403 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6404 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6406 as_bad (_("%s: unexpected function type: %d"), S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6408 else switch (S_GET_STORAGE_CLASS (sym))
6411 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6414 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6417 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6419 default: /* do nothing */
6424 if (ARM_IS_INTERWORK (sym))
6425 coffsymbol(sym->bsym)->native->u.syment.n_flags = 0xFF;
6431 armelf_adjust_symtab ()
6434 elf_symbol_type *elf_sym;
6437 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6439 if (ARM_IS_THUMB (sym))
6441 if (THUMB_IS_FUNC (sym))
6443 elf_sym = elf_symbol(sym->bsym);
6444 bind = ELF_ST_BIND(elf_sym);
6445 elf_sym->internal_elf_sym.st_info = ELF_ST_INFO(bind, STT_ARM_TFUNC);
6456 armelf_frob_symbol (symp, puntp)
6461 elf_frob_symbol (symp, puntp);
6468 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6470 *input_line_pointer = '/';
6471 input_line_pointer += 5;
6472 *input_line_pointer = 0;
6479 arm_canonicalize_symbol_name (name)
6484 if (thumb_mode && (len = strlen (name)) > 5
6485 && ! strcmp (name + len - 5, "/data"))
6487 *(name + len - 5) = 0;
6493 /* Relocations against Thumb function names must be left unadjusted,
6494 so that the linker can use this information to correctly set the
6495 bottom bit of their addresses. The MIPS version of this function
6496 also prevents relocations that are mips-16 specific, but I do not
6497 know why it does this.
6500 There is one other problem that ought to be addressed here, but
6501 which currently is not: Taking the address of a label (rather
6502 than a function) and then later jumping to that address. Such
6503 address also ought to have their bottom bit set (assuming that
6504 they reside in Thumb code), but at the moment they will not. */
6507 arm_fix_adjustable (fixP)
6511 if (fixP->fx_addsy == NULL)
6514 /* Prevent all adjustments to global symbols. */
6515 if (S_IS_EXTERN (fixP->fx_addsy))
6517 if (S_IS_WEAK (fixP->fx_addsy))
6520 if (THUMB_IS_FUNC (fixP->fx_addsy)
6521 && fixP->fx_subsy == NULL)
6524 /* We need the symbol name for the VTABLE entries */
6525 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
6526 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6531 #endif /* OBJ_ELF */
6535 elf32_arm_force_relocation (fixp)
6538 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
6539 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6542 if (fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
6550 arm_validate_fix (fixP)
6553 /* If the destination of the branch is a defined symbol which does not have
6554 the THUMB_FUNC attribute, then we must be calling a function which has
6555 the (interfacearm) attribute. We look for the Thumb entry point to that
6556 function and change the branch to refer to that function instead. */
6557 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
6558 && fixP->fx_addsy != NULL
6559 && S_IS_DEFINED (fixP->fx_addsy)
6560 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6562 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6570 elf32_arm_target_format ()
6572 if (target_big_endian)
6574 return "elf32-bigarm-oabi";
6576 return "elf32-bigarm";
6579 return "elf32-littlearm-oabi";
6581 return "elf32-littlearm";