1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
354 /* The maximum number of operands we need. */
355 #define ARM_IT_MAX_OPERANDS 6
360 unsigned long instruction;
364 /* "uncond_value" is set to the value in place of the conditional field in
365 unconditional versions of the instruction, or -1 if nothing is
368 struct neon_type vectype;
369 /* This does not indicate an actual NEON instruction, only that
370 the mnemonic accepts neon-style type suffixes. */
372 /* Set to the opcode if the instruction needs relaxation.
373 Zero if the instruction is not relaxed. */
377 bfd_reloc_code_real_type type;
382 enum it_instruction_type it_insn_type;
388 struct neon_type_el vectype;
389 unsigned present : 1; /* Operand present. */
390 unsigned isreg : 1; /* Operand was a register. */
391 unsigned immisreg : 1; /* .imm field is a second register. */
392 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
393 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
394 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
395 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
396 instructions. This allows us to disambiguate ARM <-> vector insns. */
397 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
398 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
399 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
400 unsigned issingle : 1; /* Operand is VFP single-precision register. */
401 unsigned hasreloc : 1; /* Operand has relocation suffix. */
402 unsigned writeback : 1; /* Operand has trailing ! */
403 unsigned preind : 1; /* Preindexed address. */
404 unsigned postind : 1; /* Postindexed address. */
405 unsigned negative : 1; /* Index register was negated. */
406 unsigned shifted : 1; /* Shift applied to operation. */
407 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 } operands[ARM_IT_MAX_OPERANDS];
411 static struct arm_it inst;
413 #define NUM_FLOAT_VALS 8
415 const char * fp_const[] =
417 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
420 /* Number of littlenums required to hold an extended precision number. */
421 #define MAX_LITTLENUMS 6
423 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
433 #define CP_T_X 0x00008000
434 #define CP_T_Y 0x00400000
436 #define CONDS_BIT 0x00100000
437 #define LOAD_BIT 0x00100000
439 #define DOUBLE_LOAD_FLAG 0x00000001
443 const char * template_name;
447 #define COND_ALWAYS 0xE
451 const char * template_name;
455 struct asm_barrier_opt
457 const char * template_name;
461 /* The bit that distinguishes CPSR and SPSR. */
462 #define SPSR_BIT (1 << 22)
464 /* The individual PSR flag bits. */
465 #define PSR_c (1 << 16)
466 #define PSR_x (1 << 17)
467 #define PSR_s (1 << 18)
468 #define PSR_f (1 << 19)
473 bfd_reloc_code_real_type reloc;
478 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
479 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
484 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
487 /* Bits for DEFINED field in neon_typed_alias. */
488 #define NTA_HASTYPE 1
489 #define NTA_HASINDEX 2
491 struct neon_typed_alias
493 unsigned char defined;
495 struct neon_type_el eltype;
498 /* ARM register categories. This includes coprocessor numbers and various
499 architecture extensions' registers. */
526 /* Structure for a hash table entry for a register.
527 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
528 information which states whether a vector type or index is specified (for a
529 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
535 unsigned char builtin;
536 struct neon_typed_alias * neon;
539 /* Diagnostics used when we don't get a register of the expected type. */
540 const char * const reg_expected_msgs[] =
542 N_("ARM register expected"),
543 N_("bad or missing co-processor number"),
544 N_("co-processor register expected"),
545 N_("FPA register expected"),
546 N_("VFP single precision register expected"),
547 N_("VFP/Neon double precision register expected"),
548 N_("Neon quad precision register expected"),
549 N_("VFP single or double precision register expected"),
550 N_("Neon double or quad precision register expected"),
551 N_("VFP single, double or Neon quad precision register expected"),
552 N_("VFP system register expected"),
553 N_("Maverick MVF register expected"),
554 N_("Maverick MVD register expected"),
555 N_("Maverick MVFX register expected"),
556 N_("Maverick MVDX register expected"),
557 N_("Maverick MVAX register expected"),
558 N_("Maverick DSPSC register expected"),
559 N_("iWMMXt data register expected"),
560 N_("iWMMXt control register expected"),
561 N_("iWMMXt scalar register expected"),
562 N_("XScale accumulator register expected"),
565 /* Some well known registers that we refer to directly elsewhere. */
571 /* ARM instructions take 4bytes in the object file, Thumb instructions
577 /* Basic string to match. */
578 const char * template_name;
580 /* Parameters to instruction. */
581 unsigned int operands[8];
583 /* Conditional tag - see opcode_lookup. */
584 unsigned int tag : 4;
586 /* Basic instruction code. */
587 unsigned int avalue : 28;
589 /* Thumb-format instruction code. */
592 /* Which architecture variant provides this instruction. */
593 const arm_feature_set * avariant;
594 const arm_feature_set * tvariant;
596 /* Function to call to encode instruction in ARM format. */
597 void (* aencode) (void);
599 /* Function to call to encode instruction in Thumb format. */
600 void (* tencode) (void);
603 /* Defines for various bits that we will want to toggle. */
604 #define INST_IMMEDIATE 0x02000000
605 #define OFFSET_REG 0x02000000
606 #define HWOFFSET_IMM 0x00400000
607 #define SHIFT_BY_REG 0x00000010
608 #define PRE_INDEX 0x01000000
609 #define INDEX_UP 0x00800000
610 #define WRITE_BACK 0x00200000
611 #define LDM_TYPE_2_OR_3 0x00400000
612 #define CPSI_MMOD 0x00020000
614 #define LITERAL_MASK 0xf000f000
615 #define OPCODE_MASK 0xfe1fffff
616 #define V4_STR_BIT 0x00000020
618 #define T2_SUBS_PC_LR 0xf3de8f00
620 #define DATA_OP_SHIFT 21
622 #define T2_OPCODE_MASK 0xfe1fffff
623 #define T2_DATA_OP_SHIFT 21
625 #define A_COND_MASK 0xf0000000
626 #define A_PUSH_POP_OP_MASK 0x0fff0000
628 /* Opcodes for pushing/poping registers to/from the stack. */
629 #define A1_OPCODE_PUSH 0x092d0000
630 #define A2_OPCODE_PUSH 0x052d0004
631 #define A2_OPCODE_POP 0x049d0004
633 /* Codes to distinguish the arithmetic instructions. */
644 #define OPCODE_CMP 10
645 #define OPCODE_CMN 11
646 #define OPCODE_ORR 12
647 #define OPCODE_MOV 13
648 #define OPCODE_BIC 14
649 #define OPCODE_MVN 15
651 #define T2_OPCODE_AND 0
652 #define T2_OPCODE_BIC 1
653 #define T2_OPCODE_ORR 2
654 #define T2_OPCODE_ORN 3
655 #define T2_OPCODE_EOR 4
656 #define T2_OPCODE_ADD 8
657 #define T2_OPCODE_ADC 10
658 #define T2_OPCODE_SBC 11
659 #define T2_OPCODE_SUB 13
660 #define T2_OPCODE_RSB 14
662 #define T_OPCODE_MUL 0x4340
663 #define T_OPCODE_TST 0x4200
664 #define T_OPCODE_CMN 0x42c0
665 #define T_OPCODE_NEG 0x4240
666 #define T_OPCODE_MVN 0x43c0
668 #define T_OPCODE_ADD_R3 0x1800
669 #define T_OPCODE_SUB_R3 0x1a00
670 #define T_OPCODE_ADD_HI 0x4400
671 #define T_OPCODE_ADD_ST 0xb000
672 #define T_OPCODE_SUB_ST 0xb080
673 #define T_OPCODE_ADD_SP 0xa800
674 #define T_OPCODE_ADD_PC 0xa000
675 #define T_OPCODE_ADD_I8 0x3000
676 #define T_OPCODE_SUB_I8 0x3800
677 #define T_OPCODE_ADD_I3 0x1c00
678 #define T_OPCODE_SUB_I3 0x1e00
680 #define T_OPCODE_ASR_R 0x4100
681 #define T_OPCODE_LSL_R 0x4080
682 #define T_OPCODE_LSR_R 0x40c0
683 #define T_OPCODE_ROR_R 0x41c0
684 #define T_OPCODE_ASR_I 0x1000
685 #define T_OPCODE_LSL_I 0x0000
686 #define T_OPCODE_LSR_I 0x0800
688 #define T_OPCODE_MOV_I8 0x2000
689 #define T_OPCODE_CMP_I8 0x2800
690 #define T_OPCODE_CMP_LR 0x4280
691 #define T_OPCODE_MOV_HR 0x4600
692 #define T_OPCODE_CMP_HR 0x4500
694 #define T_OPCODE_LDR_PC 0x4800
695 #define T_OPCODE_LDR_SP 0x9800
696 #define T_OPCODE_STR_SP 0x9000
697 #define T_OPCODE_LDR_IW 0x6800
698 #define T_OPCODE_STR_IW 0x6000
699 #define T_OPCODE_LDR_IH 0x8800
700 #define T_OPCODE_STR_IH 0x8000
701 #define T_OPCODE_LDR_IB 0x7800
702 #define T_OPCODE_STR_IB 0x7000
703 #define T_OPCODE_LDR_RW 0x5800
704 #define T_OPCODE_STR_RW 0x5000
705 #define T_OPCODE_LDR_RH 0x5a00
706 #define T_OPCODE_STR_RH 0x5200
707 #define T_OPCODE_LDR_RB 0x5c00
708 #define T_OPCODE_STR_RB 0x5400
710 #define T_OPCODE_PUSH 0xb400
711 #define T_OPCODE_POP 0xbc00
713 #define T_OPCODE_BRANCH 0xe000
715 #define THUMB_SIZE 2 /* Size of thumb instruction. */
716 #define THUMB_PP_PC_LR 0x0100
717 #define THUMB_LOAD_BIT 0x0800
718 #define THUMB2_LOAD_BIT 0x00100000
720 #define BAD_ARGS _("bad arguments to instruction")
721 #define BAD_SP _("r13 not allowed here")
722 #define BAD_PC _("r15 not allowed here")
723 #define BAD_COND _("instruction cannot be conditional")
724 #define BAD_OVERLAP _("registers may not be the same")
725 #define BAD_HIREG _("lo register required")
726 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
727 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
728 #define BAD_BRANCH _("branch must be last instruction in IT block")
729 #define BAD_NOT_IT _("instruction not allowed in IT block")
730 #define BAD_FPU _("selected FPU does not support instruction")
731 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
732 #define BAD_IT_COND _("incorrect condition in IT block")
733 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
734 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
735 #define BAD_PC_ADDRESSING \
736 _("cannot use register index with PC-relative addressing")
737 #define BAD_PC_WRITEBACK \
738 _("cannot use writeback with PC-relative addressing")
739 #define BAD_RANGE _("branch out of range")
741 static struct hash_control * arm_ops_hsh;
742 static struct hash_control * arm_cond_hsh;
743 static struct hash_control * arm_shift_hsh;
744 static struct hash_control * arm_psr_hsh;
745 static struct hash_control * arm_v7m_psr_hsh;
746 static struct hash_control * arm_reg_hsh;
747 static struct hash_control * arm_reloc_hsh;
748 static struct hash_control * arm_barrier_opt_hsh;
750 /* Stuff needed to resolve the label ambiguity
759 symbolS * last_label_seen;
760 static int label_is_thumb_function_name = FALSE;
762 /* Literal pool structure. Held on a per-section
763 and per-sub-section basis. */
765 #define MAX_LITERAL_POOL_SIZE 1024
766 typedef struct literal_pool
768 expressionS literals [MAX_LITERAL_POOL_SIZE];
769 unsigned int next_free_entry;
775 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
777 struct literal_pool * next;
780 /* Pointer to a linked list of literal pools. */
781 literal_pool * list_of_pools = NULL;
784 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
786 static struct current_it now_it;
790 now_it_compatible (int cond)
792 return (cond & ~1) == (now_it.cc & ~1);
796 conditional_insn (void)
798 return inst.cond != COND_ALWAYS;
801 static int in_it_block (void);
803 static int handle_it_state (void);
805 static void force_automatic_it_block_close (void);
807 static void it_fsm_post_encode (void);
809 #define set_it_insn_type(type) \
812 inst.it_insn_type = type; \
813 if (handle_it_state () == FAIL) \
818 #define set_it_insn_type_nonvoid(type, failret) \
821 inst.it_insn_type = type; \
822 if (handle_it_state () == FAIL) \
827 #define set_it_insn_type_last() \
830 if (inst.cond == COND_ALWAYS) \
831 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
833 set_it_insn_type (INSIDE_IT_LAST_INSN); \
839 /* This array holds the chars that always start a comment. If the
840 pre-processor is disabled, these aren't very useful. */
841 const char comment_chars[] = "@";
843 /* This array holds the chars that only start a comment at the beginning of
844 a line. If the line seems to have the form '# 123 filename'
845 .line and .file directives will appear in the pre-processed output. */
846 /* Note that input_file.c hand checks for '#' at the beginning of the
847 first line of the input file. This is because the compiler outputs
848 #NO_APP at the beginning of its output. */
849 /* Also note that comments like this one will always work. */
850 const char line_comment_chars[] = "#";
852 const char line_separator_chars[] = ";";
854 /* Chars that can be used to separate mant
855 from exp in floating point numbers. */
856 const char EXP_CHARS[] = "eE";
858 /* Chars that mean this number is a floating point constant. */
862 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
864 /* Prefix characters that indicate the start of an immediate
866 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
868 /* Separator character handling. */
870 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
873 skip_past_char (char ** str, char c)
884 #define skip_past_comma(str) skip_past_char (str, ',')
886 /* Arithmetic expressions (possibly involving symbols). */
888 /* Return TRUE if anything in the expression is a bignum. */
891 walk_no_bignums (symbolS * sp)
893 if (symbol_get_value_expression (sp)->X_op == O_big)
896 if (symbol_get_value_expression (sp)->X_add_symbol)
898 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
899 || (symbol_get_value_expression (sp)->X_op_symbol
900 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
906 static int in_my_get_expression = 0;
908 /* Third argument to my_get_expression. */
909 #define GE_NO_PREFIX 0
910 #define GE_IMM_PREFIX 1
911 #define GE_OPT_PREFIX 2
912 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
913 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
914 #define GE_OPT_PREFIX_BIG 3
917 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
922 /* In unified syntax, all prefixes are optional. */
924 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
929 case GE_NO_PREFIX: break;
931 if (!is_immediate_prefix (**str))
933 inst.error = _("immediate expression requires a # prefix");
939 case GE_OPT_PREFIX_BIG:
940 if (is_immediate_prefix (**str))
946 memset (ep, 0, sizeof (expressionS));
948 save_in = input_line_pointer;
949 input_line_pointer = *str;
950 in_my_get_expression = 1;
951 seg = expression (ep);
952 in_my_get_expression = 0;
954 if (ep->X_op == O_illegal || ep->X_op == O_absent)
956 /* We found a bad or missing expression in md_operand(). */
957 *str = input_line_pointer;
958 input_line_pointer = save_in;
959 if (inst.error == NULL)
960 inst.error = (ep->X_op == O_absent
961 ? _("missing expression") :_("bad expression"));
966 if (seg != absolute_section
967 && seg != text_section
968 && seg != data_section
969 && seg != bss_section
970 && seg != undefined_section)
972 inst.error = _("bad segment");
973 *str = input_line_pointer;
974 input_line_pointer = save_in;
981 /* Get rid of any bignums now, so that we don't generate an error for which
982 we can't establish a line number later on. Big numbers are never valid
983 in instructions, which is where this routine is always called. */
984 if (prefix_mode != GE_OPT_PREFIX_BIG
985 && (ep->X_op == O_big
987 && (walk_no_bignums (ep->X_add_symbol)
989 && walk_no_bignums (ep->X_op_symbol))))))
991 inst.error = _("invalid constant");
992 *str = input_line_pointer;
993 input_line_pointer = save_in;
997 *str = input_line_pointer;
998 input_line_pointer = save_in;
1002 /* Turn a string in input_line_pointer into a floating point constant
1003 of type TYPE, and store the appropriate bytes in *LITP. The number
1004 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1005 returned, or NULL on OK.
1007 Note that fp constants aren't represent in the normal way on the ARM.
1008 In big endian mode, things are as expected. However, in little endian
1009 mode fp constants are big-endian word-wise, and little-endian byte-wise
1010 within the words. For example, (double) 1.1 in big endian mode is
1011 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1012 the byte sequence 99 99 f1 3f 9a 99 99 99.
1014 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1017 md_atof (int type, char * litP, int * sizeP)
1020 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1052 return _("Unrecognized or unsupported floating point constant");
1055 t = atof_ieee (input_line_pointer, type, words);
1057 input_line_pointer = t;
1058 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1060 if (target_big_endian)
1062 for (i = 0; i < prec; i++)
1064 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1065 litP += sizeof (LITTLENUM_TYPE);
1070 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1071 for (i = prec - 1; i >= 0; i--)
1073 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1074 litP += sizeof (LITTLENUM_TYPE);
1077 /* For a 4 byte float the order of elements in `words' is 1 0.
1078 For an 8 byte float the order is 1 0 3 2. */
1079 for (i = 0; i < prec; i += 2)
1081 md_number_to_chars (litP, (valueT) words[i + 1],
1082 sizeof (LITTLENUM_TYPE));
1083 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1084 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1085 litP += 2 * sizeof (LITTLENUM_TYPE);
1092 /* We handle all bad expressions here, so that we can report the faulty
1093 instruction in the error message. */
1095 md_operand (expressionS * exp)
1097 if (in_my_get_expression)
1098 exp->X_op = O_illegal;
1101 /* Immediate values. */
1103 /* Generic immediate-value read function for use in directives.
1104 Accepts anything that 'expression' can fold to a constant.
1105 *val receives the number. */
1108 immediate_for_directive (int *val)
1111 exp.X_op = O_illegal;
1113 if (is_immediate_prefix (*input_line_pointer))
1115 input_line_pointer++;
1119 if (exp.X_op != O_constant)
1121 as_bad (_("expected #constant"));
1122 ignore_rest_of_line ();
1125 *val = exp.X_add_number;
1130 /* Register parsing. */
1132 /* Generic register parser. CCP points to what should be the
1133 beginning of a register name. If it is indeed a valid register
1134 name, advance CCP over it and return the reg_entry structure;
1135 otherwise return NULL. Does not issue diagnostics. */
1137 static struct reg_entry *
1138 arm_reg_parse_multi (char **ccp)
1142 struct reg_entry *reg;
1144 #ifdef REGISTER_PREFIX
1145 if (*start != REGISTER_PREFIX)
1149 #ifdef OPTIONAL_REGISTER_PREFIX
1150 if (*start == OPTIONAL_REGISTER_PREFIX)
1155 if (!ISALPHA (*p) || !is_name_beginner (*p))
1160 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1162 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1172 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1173 enum arm_reg_type type)
1175 /* Alternative syntaxes are accepted for a few register classes. */
1182 /* Generic coprocessor register names are allowed for these. */
1183 if (reg && reg->type == REG_TYPE_CN)
1188 /* For backward compatibility, a bare number is valid here. */
1190 unsigned long processor = strtoul (start, ccp, 10);
1191 if (*ccp != start && processor <= 15)
1195 case REG_TYPE_MMXWC:
1196 /* WC includes WCG. ??? I'm not sure this is true for all
1197 instructions that take WC registers. */
1198 if (reg && reg->type == REG_TYPE_MMXWCG)
1209 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1210 return value is the register number or FAIL. */
1213 arm_reg_parse (char **ccp, enum arm_reg_type type)
1216 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1219 /* Do not allow a scalar (reg+index) to parse as a register. */
1220 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1223 if (reg && reg->type == type)
1226 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1233 /* Parse a Neon type specifier. *STR should point at the leading '.'
1234 character. Does no verification at this stage that the type fits the opcode
1241 Can all be legally parsed by this function.
1243 Fills in neon_type struct pointer with parsed information, and updates STR
1244 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1245 type, FAIL if not. */
1248 parse_neon_type (struct neon_type *type, char **str)
1255 while (type->elems < NEON_MAX_TYPE_ELS)
1257 enum neon_el_type thistype = NT_untyped;
1258 unsigned thissize = -1u;
1265 /* Just a size without an explicit type. */
1269 switch (TOLOWER (*ptr))
1271 case 'i': thistype = NT_integer; break;
1272 case 'f': thistype = NT_float; break;
1273 case 'p': thistype = NT_poly; break;
1274 case 's': thistype = NT_signed; break;
1275 case 'u': thistype = NT_unsigned; break;
1277 thistype = NT_float;
1282 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1288 /* .f is an abbreviation for .f32. */
1289 if (thistype == NT_float && !ISDIGIT (*ptr))
1294 thissize = strtoul (ptr, &ptr, 10);
1296 if (thissize != 8 && thissize != 16 && thissize != 32
1299 as_bad (_("bad size %d in type specifier"), thissize);
1307 type->el[type->elems].type = thistype;
1308 type->el[type->elems].size = thissize;
1313 /* Empty/missing type is not a successful parse. */
1314 if (type->elems == 0)
1322 /* Errors may be set multiple times during parsing or bit encoding
1323 (particularly in the Neon bits), but usually the earliest error which is set
1324 will be the most meaningful. Avoid overwriting it with later (cascading)
1325 errors by calling this function. */
1328 first_error (const char *err)
1334 /* Parse a single type, e.g. ".s32", leading period included. */
1336 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1339 struct neon_type optype;
1343 if (parse_neon_type (&optype, &str) == SUCCESS)
1345 if (optype.elems == 1)
1346 *vectype = optype.el[0];
1349 first_error (_("only one type should be specified for operand"));
1355 first_error (_("vector type expected"));
1367 /* Special meanings for indices (which have a range of 0-7), which will fit into
1370 #define NEON_ALL_LANES 15
1371 #define NEON_INTERLEAVE_LANES 14
1373 /* Parse either a register or a scalar, with an optional type. Return the
1374 register number, and optionally fill in the actual type of the register
1375 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1376 type/index information in *TYPEINFO. */
1379 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1380 enum arm_reg_type *rtype,
1381 struct neon_typed_alias *typeinfo)
1384 struct reg_entry *reg = arm_reg_parse_multi (&str);
1385 struct neon_typed_alias atype;
1386 struct neon_type_el parsetype;
1390 atype.eltype.type = NT_invtype;
1391 atype.eltype.size = -1;
1393 /* Try alternate syntax for some types of register. Note these are mutually
1394 exclusive with the Neon syntax extensions. */
1397 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1405 /* Undo polymorphism when a set of register types may be accepted. */
1406 if ((type == REG_TYPE_NDQ
1407 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1408 || (type == REG_TYPE_VFSD
1409 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1410 || (type == REG_TYPE_NSDQ
1411 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1412 || reg->type == REG_TYPE_NQ))
1413 || (type == REG_TYPE_MMXWC
1414 && (reg->type == REG_TYPE_MMXWCG)))
1415 type = (enum arm_reg_type) reg->type;
1417 if (type != reg->type)
1423 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1425 if ((atype.defined & NTA_HASTYPE) != 0)
1427 first_error (_("can't redefine type for operand"));
1430 atype.defined |= NTA_HASTYPE;
1431 atype.eltype = parsetype;
1434 if (skip_past_char (&str, '[') == SUCCESS)
1436 if (type != REG_TYPE_VFD)
1438 first_error (_("only D registers may be indexed"));
1442 if ((atype.defined & NTA_HASINDEX) != 0)
1444 first_error (_("can't change index for operand"));
1448 atype.defined |= NTA_HASINDEX;
1450 if (skip_past_char (&str, ']') == SUCCESS)
1451 atype.index = NEON_ALL_LANES;
1456 my_get_expression (&exp, &str, GE_NO_PREFIX);
1458 if (exp.X_op != O_constant)
1460 first_error (_("constant expression required"));
1464 if (skip_past_char (&str, ']') == FAIL)
1467 atype.index = exp.X_add_number;
1482 /* Like arm_reg_parse, but allow allow the following extra features:
1483 - If RTYPE is non-zero, return the (possibly restricted) type of the
1484 register (e.g. Neon double or quad reg when either has been requested).
1485 - If this is a Neon vector type with additional type information, fill
1486 in the struct pointed to by VECTYPE (if non-NULL).
1487 This function will fault on encountering a scalar. */
1490 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1491 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1493 struct neon_typed_alias atype;
1495 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1500 /* Do not allow regname(... to parse as a register. */
1504 /* Do not allow a scalar (reg+index) to parse as a register. */
1505 if ((atype.defined & NTA_HASINDEX) != 0)
1507 first_error (_("register operand expected, but got scalar"));
1512 *vectype = atype.eltype;
1519 #define NEON_SCALAR_REG(X) ((X) >> 4)
1520 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1522 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1523 have enough information to be able to do a good job bounds-checking. So, we
1524 just do easy checks here, and do further checks later. */
1527 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1531 struct neon_typed_alias atype;
1533 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1535 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1538 if (atype.index == NEON_ALL_LANES)
1540 first_error (_("scalar must have an index"));
1543 else if (atype.index >= 64 / elsize)
1545 first_error (_("scalar index out of range"));
1550 *type = atype.eltype;
1554 return reg * 16 + atype.index;
1557 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1560 parse_reg_list (char ** strp)
1562 char * str = * strp;
1566 /* We come back here if we get ranges concatenated by '+' or '|'. */
1581 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1583 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1593 first_error (_("bad range in register list"));
1597 for (i = cur_reg + 1; i < reg; i++)
1599 if (range & (1 << i))
1601 (_("Warning: duplicated register (r%d) in register list"),
1609 if (range & (1 << reg))
1610 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1612 else if (reg <= cur_reg)
1613 as_tsktsk (_("Warning: register range not in ascending order"));
1618 while (skip_past_comma (&str) != FAIL
1619 || (in_range = 1, *str++ == '-'));
1624 first_error (_("missing `}'"));
1632 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1635 if (exp.X_op == O_constant)
1637 if (exp.X_add_number
1638 != (exp.X_add_number & 0x0000ffff))
1640 inst.error = _("invalid register mask");
1644 if ((range & exp.X_add_number) != 0)
1646 int regno = range & exp.X_add_number;
1649 regno = (1 << regno) - 1;
1651 (_("Warning: duplicated register (r%d) in register list"),
1655 range |= exp.X_add_number;
1659 if (inst.reloc.type != 0)
1661 inst.error = _("expression too complex");
1665 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1666 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1667 inst.reloc.pc_rel = 0;
1671 if (*str == '|' || *str == '+')
1677 while (another_range);
1683 /* Types of registers in a list. */
1692 /* Parse a VFP register list. If the string is invalid return FAIL.
1693 Otherwise return the number of registers, and set PBASE to the first
1694 register. Parses registers of type ETYPE.
1695 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1696 - Q registers can be used to specify pairs of D registers
1697 - { } can be omitted from around a singleton register list
1698 FIXME: This is not implemented, as it would require backtracking in
1701 This could be done (the meaning isn't really ambiguous), but doesn't
1702 fit in well with the current parsing framework.
1703 - 32 D registers may be used (also true for VFPv3).
1704 FIXME: Types are ignored in these register lists, which is probably a
1708 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1713 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1717 unsigned long mask = 0;
1722 inst.error = _("expecting {");
1731 regtype = REG_TYPE_VFS;
1736 regtype = REG_TYPE_VFD;
1739 case REGLIST_NEON_D:
1740 regtype = REG_TYPE_NDQ;
1744 if (etype != REGLIST_VFP_S)
1746 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1747 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1751 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1754 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1761 base_reg = max_regs;
1765 int setmask = 1, addregs = 1;
1767 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1769 if (new_base == FAIL)
1771 first_error (_(reg_expected_msgs[regtype]));
1775 if (new_base >= max_regs)
1777 first_error (_("register out of range in list"));
1781 /* Note: a value of 2 * n is returned for the register Q<n>. */
1782 if (regtype == REG_TYPE_NQ)
1788 if (new_base < base_reg)
1789 base_reg = new_base;
1791 if (mask & (setmask << new_base))
1793 first_error (_("invalid register list"));
1797 if ((mask >> new_base) != 0 && ! warned)
1799 as_tsktsk (_("register list not in ascending order"));
1803 mask |= setmask << new_base;
1806 if (*str == '-') /* We have the start of a range expression */
1812 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1815 inst.error = gettext (reg_expected_msgs[regtype]);
1819 if (high_range >= max_regs)
1821 first_error (_("register out of range in list"));
1825 if (regtype == REG_TYPE_NQ)
1826 high_range = high_range + 1;
1828 if (high_range <= new_base)
1830 inst.error = _("register range not in ascending order");
1834 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1836 if (mask & (setmask << new_base))
1838 inst.error = _("invalid register list");
1842 mask |= setmask << new_base;
1847 while (skip_past_comma (&str) != FAIL);
1851 /* Sanity check -- should have raised a parse error above. */
1852 if (count == 0 || count > max_regs)
1857 /* Final test -- the registers must be consecutive. */
1859 for (i = 0; i < count; i++)
1861 if ((mask & (1u << i)) == 0)
1863 inst.error = _("non-contiguous register range");
1873 /* True if two alias types are the same. */
1876 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1884 if (a->defined != b->defined)
1887 if ((a->defined & NTA_HASTYPE) != 0
1888 && (a->eltype.type != b->eltype.type
1889 || a->eltype.size != b->eltype.size))
1892 if ((a->defined & NTA_HASINDEX) != 0
1893 && (a->index != b->index))
1899 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1900 The base register is put in *PBASE.
1901 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1903 The register stride (minus one) is put in bit 4 of the return value.
1904 Bits [6:5] encode the list length (minus one).
1905 The type of the list elements is put in *ELTYPE, if non-NULL. */
1907 #define NEON_LANE(X) ((X) & 0xf)
1908 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1909 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1912 parse_neon_el_struct_list (char **str, unsigned *pbase,
1913 struct neon_type_el *eltype)
1920 int leading_brace = 0;
1921 enum arm_reg_type rtype = REG_TYPE_NDQ;
1922 const char *const incr_error = _("register stride must be 1 or 2");
1923 const char *const type_error = _("mismatched element/structure types in list");
1924 struct neon_typed_alias firsttype;
1926 if (skip_past_char (&ptr, '{') == SUCCESS)
1931 struct neon_typed_alias atype;
1932 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1936 first_error (_(reg_expected_msgs[rtype]));
1943 if (rtype == REG_TYPE_NQ)
1949 else if (reg_incr == -1)
1951 reg_incr = getreg - base_reg;
1952 if (reg_incr < 1 || reg_incr > 2)
1954 first_error (_(incr_error));
1958 else if (getreg != base_reg + reg_incr * count)
1960 first_error (_(incr_error));
1964 if (! neon_alias_types_same (&atype, &firsttype))
1966 first_error (_(type_error));
1970 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1974 struct neon_typed_alias htype;
1975 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1977 lane = NEON_INTERLEAVE_LANES;
1978 else if (lane != NEON_INTERLEAVE_LANES)
1980 first_error (_(type_error));
1985 else if (reg_incr != 1)
1987 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1991 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1994 first_error (_(reg_expected_msgs[rtype]));
1997 if (! neon_alias_types_same (&htype, &firsttype))
1999 first_error (_(type_error));
2002 count += hireg + dregs - getreg;
2006 /* If we're using Q registers, we can't use [] or [n] syntax. */
2007 if (rtype == REG_TYPE_NQ)
2013 if ((atype.defined & NTA_HASINDEX) != 0)
2017 else if (lane != atype.index)
2019 first_error (_(type_error));
2023 else if (lane == -1)
2024 lane = NEON_INTERLEAVE_LANES;
2025 else if (lane != NEON_INTERLEAVE_LANES)
2027 first_error (_(type_error));
2032 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2034 /* No lane set by [x]. We must be interleaving structures. */
2036 lane = NEON_INTERLEAVE_LANES;
2039 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2040 || (count > 1 && reg_incr == -1))
2042 first_error (_("error parsing element/structure list"));
2046 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2048 first_error (_("expected }"));
2056 *eltype = firsttype.eltype;
2061 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2064 /* Parse an explicit relocation suffix on an expression. This is
2065 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2066 arm_reloc_hsh contains no entries, so this function can only
2067 succeed if there is no () after the word. Returns -1 on error,
2068 BFD_RELOC_UNUSED if there wasn't any suffix. */
2071 parse_reloc (char **str)
2073 struct reloc_entry *r;
2077 return BFD_RELOC_UNUSED;
2082 while (*q && *q != ')' && *q != ',')
2087 if ((r = (struct reloc_entry *)
2088 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2095 /* Directives: register aliases. */
2097 static struct reg_entry *
2098 insert_reg_alias (char *str, unsigned number, int type)
2100 struct reg_entry *new_reg;
2103 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2105 if (new_reg->builtin)
2106 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2108 /* Only warn about a redefinition if it's not defined as the
2110 else if (new_reg->number != number || new_reg->type != type)
2111 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2116 name = xstrdup (str);
2117 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2119 new_reg->name = name;
2120 new_reg->number = number;
2121 new_reg->type = type;
2122 new_reg->builtin = FALSE;
2123 new_reg->neon = NULL;
2125 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2132 insert_neon_reg_alias (char *str, int number, int type,
2133 struct neon_typed_alias *atype)
2135 struct reg_entry *reg = insert_reg_alias (str, number, type);
2139 first_error (_("attempt to redefine typed alias"));
2145 reg->neon = (struct neon_typed_alias *)
2146 xmalloc (sizeof (struct neon_typed_alias));
2147 *reg->neon = *atype;
2151 /* Look for the .req directive. This is of the form:
2153 new_register_name .req existing_register_name
2155 If we find one, or if it looks sufficiently like one that we want to
2156 handle any error here, return TRUE. Otherwise return FALSE. */
2159 create_register_alias (char * newname, char *p)
2161 struct reg_entry *old;
2162 char *oldname, *nbuf;
2165 /* The input scrubber ensures that whitespace after the mnemonic is
2166 collapsed to single spaces. */
2168 if (strncmp (oldname, " .req ", 6) != 0)
2172 if (*oldname == '\0')
2175 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2178 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2182 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2183 the desired alias name, and p points to its end. If not, then
2184 the desired alias name is in the global original_case_string. */
2185 #ifdef TC_CASE_SENSITIVE
2188 newname = original_case_string;
2189 nlen = strlen (newname);
2192 nbuf = (char *) alloca (nlen + 1);
2193 memcpy (nbuf, newname, nlen);
2196 /* Create aliases under the new name as stated; an all-lowercase
2197 version of the new name; and an all-uppercase version of the new
2199 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2201 for (p = nbuf; *p; p++)
2204 if (strncmp (nbuf, newname, nlen))
2206 /* If this attempt to create an additional alias fails, do not bother
2207 trying to create the all-lower case alias. We will fail and issue
2208 a second, duplicate error message. This situation arises when the
2209 programmer does something like:
2212 The second .req creates the "Foo" alias but then fails to create
2213 the artificial FOO alias because it has already been created by the
2215 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2219 for (p = nbuf; *p; p++)
2222 if (strncmp (nbuf, newname, nlen))
2223 insert_reg_alias (nbuf, old->number, old->type);
2229 /* Create a Neon typed/indexed register alias using directives, e.g.:
2234 These typed registers can be used instead of the types specified after the
2235 Neon mnemonic, so long as all operands given have types. Types can also be
2236 specified directly, e.g.:
2237 vadd d0.s32, d1.s32, d2.s32 */
2240 create_neon_reg_alias (char *newname, char *p)
2242 enum arm_reg_type basetype;
2243 struct reg_entry *basereg;
2244 struct reg_entry mybasereg;
2245 struct neon_type ntype;
2246 struct neon_typed_alias typeinfo;
2247 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2250 typeinfo.defined = 0;
2251 typeinfo.eltype.type = NT_invtype;
2252 typeinfo.eltype.size = -1;
2253 typeinfo.index = -1;
2257 if (strncmp (p, " .dn ", 5) == 0)
2258 basetype = REG_TYPE_VFD;
2259 else if (strncmp (p, " .qn ", 5) == 0)
2260 basetype = REG_TYPE_NQ;
2269 basereg = arm_reg_parse_multi (&p);
2271 if (basereg && basereg->type != basetype)
2273 as_bad (_("bad type for register"));
2277 if (basereg == NULL)
2280 /* Try parsing as an integer. */
2281 my_get_expression (&exp, &p, GE_NO_PREFIX);
2282 if (exp.X_op != O_constant)
2284 as_bad (_("expression must be constant"));
2287 basereg = &mybasereg;
2288 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2294 typeinfo = *basereg->neon;
2296 if (parse_neon_type (&ntype, &p) == SUCCESS)
2298 /* We got a type. */
2299 if (typeinfo.defined & NTA_HASTYPE)
2301 as_bad (_("can't redefine the type of a register alias"));
2305 typeinfo.defined |= NTA_HASTYPE;
2306 if (ntype.elems != 1)
2308 as_bad (_("you must specify a single type only"));
2311 typeinfo.eltype = ntype.el[0];
2314 if (skip_past_char (&p, '[') == SUCCESS)
2317 /* We got a scalar index. */
2319 if (typeinfo.defined & NTA_HASINDEX)
2321 as_bad (_("can't redefine the index of a scalar alias"));
2325 my_get_expression (&exp, &p, GE_NO_PREFIX);
2327 if (exp.X_op != O_constant)
2329 as_bad (_("scalar index must be constant"));
2333 typeinfo.defined |= NTA_HASINDEX;
2334 typeinfo.index = exp.X_add_number;
2336 if (skip_past_char (&p, ']') == FAIL)
2338 as_bad (_("expecting ]"));
2343 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2344 the desired alias name, and p points to its end. If not, then
2345 the desired alias name is in the global original_case_string. */
2346 #ifdef TC_CASE_SENSITIVE
2347 namelen = nameend - newname;
2349 newname = original_case_string;
2350 namelen = strlen (newname);
2353 namebuf = (char *) alloca (namelen + 1);
2354 strncpy (namebuf, newname, namelen);
2355 namebuf[namelen] = '\0';
2357 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2358 typeinfo.defined != 0 ? &typeinfo : NULL);
2360 /* Insert name in all uppercase. */
2361 for (p = namebuf; *p; p++)
2364 if (strncmp (namebuf, newname, namelen))
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2368 /* Insert name in all lowercase. */
2369 for (p = namebuf; *p; p++)
2372 if (strncmp (namebuf, newname, namelen))
2373 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2374 typeinfo.defined != 0 ? &typeinfo : NULL);
2379 /* Should never be called, as .req goes between the alias and the
2380 register name, not at the beginning of the line. */
2383 s_req (int a ATTRIBUTE_UNUSED)
2385 as_bad (_("invalid syntax for .req directive"));
2389 s_dn (int a ATTRIBUTE_UNUSED)
2391 as_bad (_("invalid syntax for .dn directive"));
2395 s_qn (int a ATTRIBUTE_UNUSED)
2397 as_bad (_("invalid syntax for .qn directive"));
2400 /* The .unreq directive deletes an alias which was previously defined
2401 by .req. For example:
2407 s_unreq (int a ATTRIBUTE_UNUSED)
2412 name = input_line_pointer;
2414 while (*input_line_pointer != 0
2415 && *input_line_pointer != ' '
2416 && *input_line_pointer != '\n')
2417 ++input_line_pointer;
2419 saved_char = *input_line_pointer;
2420 *input_line_pointer = 0;
2423 as_bad (_("invalid syntax for .unreq directive"));
2426 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2430 as_bad (_("unknown register alias '%s'"), name);
2431 else if (reg->builtin)
2432 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2439 hash_delete (arm_reg_hsh, name, FALSE);
2440 free ((char *) reg->name);
2445 /* Also locate the all upper case and all lower case versions.
2446 Do not complain if we cannot find one or the other as it
2447 was probably deleted above. */
2449 nbuf = strdup (name);
2450 for (p = nbuf; *p; p++)
2452 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2455 hash_delete (arm_reg_hsh, nbuf, FALSE);
2456 free ((char *) reg->name);
2462 for (p = nbuf; *p; p++)
2464 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2467 hash_delete (arm_reg_hsh, nbuf, FALSE);
2468 free ((char *) reg->name);
2478 *input_line_pointer = saved_char;
2479 demand_empty_rest_of_line ();
2482 /* Directives: Instruction set selection. */
2485 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2486 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2487 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2488 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2490 /* Create a new mapping symbol for the transition to STATE. */
2493 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2496 const char * symname;
2503 type = BSF_NO_FLAGS;
2507 type = BSF_NO_FLAGS;
2511 type = BSF_NO_FLAGS;
2517 symbolP = symbol_new (symname, now_seg, value, frag);
2518 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2523 THUMB_SET_FUNC (symbolP, 0);
2524 ARM_SET_THUMB (symbolP, 0);
2525 ARM_SET_INTERWORK (symbolP, support_interwork);
2529 THUMB_SET_FUNC (symbolP, 1);
2530 ARM_SET_THUMB (symbolP, 1);
2531 ARM_SET_INTERWORK (symbolP, support_interwork);
2539 /* Save the mapping symbols for future reference. Also check that
2540 we do not place two mapping symbols at the same offset within a
2541 frag. We'll handle overlap between frags in
2542 check_mapping_symbols.
2544 If .fill or other data filling directive generates zero sized data,
2545 the mapping symbol for the following code will have the same value
2546 as the one generated for the data filling directive. In this case,
2547 we replace the old symbol with the new one at the same address. */
2550 if (frag->tc_frag_data.first_map != NULL)
2552 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2553 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2555 frag->tc_frag_data.first_map = symbolP;
2557 if (frag->tc_frag_data.last_map != NULL)
2559 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2560 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2561 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2563 frag->tc_frag_data.last_map = symbolP;
2566 /* We must sometimes convert a region marked as code to data during
2567 code alignment, if an odd number of bytes have to be padded. The
2568 code mapping symbol is pushed to an aligned address. */
2571 insert_data_mapping_symbol (enum mstate state,
2572 valueT value, fragS *frag, offsetT bytes)
2574 /* If there was already a mapping symbol, remove it. */
2575 if (frag->tc_frag_data.last_map != NULL
2576 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2578 symbolS *symp = frag->tc_frag_data.last_map;
2582 know (frag->tc_frag_data.first_map == symp);
2583 frag->tc_frag_data.first_map = NULL;
2585 frag->tc_frag_data.last_map = NULL;
2586 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2589 make_mapping_symbol (MAP_DATA, value, frag);
2590 make_mapping_symbol (state, value + bytes, frag);
2593 static void mapping_state_2 (enum mstate state, int max_chars);
2595 /* Set the mapping state to STATE. Only call this when about to
2596 emit some STATE bytes to the file. */
2599 mapping_state (enum mstate state)
2601 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2603 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2605 if (mapstate == state)
2606 /* The mapping symbol has already been emitted.
2607 There is nothing else to do. */
2610 if (state == MAP_ARM || state == MAP_THUMB)
2612 All ARM instructions require 4-byte alignment.
2613 (Almost) all Thumb instructions require 2-byte alignment.
2615 When emitting instructions into any section, mark the section
2618 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2619 but themselves require 2-byte alignment; this applies to some
2620 PC- relative forms. However, these cases will invovle implicit
2621 literal pool generation or an explicit .align >=2, both of
2622 which will cause the section to me marked with sufficient
2623 alignment. Thus, we don't handle those cases here. */
2624 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2626 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2627 /* This case will be evaluated later in the next else. */
2629 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2630 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2632 /* Only add the symbol if the offset is > 0:
2633 if we're at the first frag, check it's size > 0;
2634 if we're not at the first frag, then for sure
2635 the offset is > 0. */
2636 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2637 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2640 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2643 mapping_state_2 (state, 0);
2647 /* Same as mapping_state, but MAX_CHARS bytes have already been
2648 allocated. Put the mapping symbol that far back. */
2651 mapping_state_2 (enum mstate state, int max_chars)
2653 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2655 if (!SEG_NORMAL (now_seg))
2658 if (mapstate == state)
2659 /* The mapping symbol has already been emitted.
2660 There is nothing else to do. */
2663 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2664 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2667 #define mapping_state(x) ((void)0)
2668 #define mapping_state_2(x, y) ((void)0)
2671 /* Find the real, Thumb encoded start of a Thumb function. */
2675 find_real_start (symbolS * symbolP)
2678 const char * name = S_GET_NAME (symbolP);
2679 symbolS * new_target;
2681 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2682 #define STUB_NAME ".real_start_of"
2687 /* The compiler may generate BL instructions to local labels because
2688 it needs to perform a branch to a far away location. These labels
2689 do not have a corresponding ".real_start_of" label. We check
2690 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2691 the ".real_start_of" convention for nonlocal branches. */
2692 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2695 real_start = ACONCAT ((STUB_NAME, name, NULL));
2696 new_target = symbol_find (real_start);
2698 if (new_target == NULL)
2700 as_warn (_("Failed to find real start of function: %s\n"), name);
2701 new_target = symbolP;
2709 opcode_select (int width)
2716 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2717 as_bad (_("selected processor does not support THUMB opcodes"));
2720 /* No need to force the alignment, since we will have been
2721 coming from ARM mode, which is word-aligned. */
2722 record_alignment (now_seg, 1);
2729 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2730 as_bad (_("selected processor does not support ARM opcodes"));
2735 frag_align (2, 0, 0);
2737 record_alignment (now_seg, 1);
2742 as_bad (_("invalid instruction size selected (%d)"), width);
2747 s_arm (int ignore ATTRIBUTE_UNUSED)
2750 demand_empty_rest_of_line ();
2754 s_thumb (int ignore ATTRIBUTE_UNUSED)
2757 demand_empty_rest_of_line ();
2761 s_code (int unused ATTRIBUTE_UNUSED)
2765 temp = get_absolute_expression ();
2770 opcode_select (temp);
2774 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2779 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2781 /* If we are not already in thumb mode go into it, EVEN if
2782 the target processor does not support thumb instructions.
2783 This is used by gcc/config/arm/lib1funcs.asm for example
2784 to compile interworking support functions even if the
2785 target processor should not support interworking. */
2789 record_alignment (now_seg, 1);
2792 demand_empty_rest_of_line ();
2796 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2800 /* The following label is the name/address of the start of a Thumb function.
2801 We need to know this for the interworking support. */
2802 label_is_thumb_function_name = TRUE;
2805 /* Perform a .set directive, but also mark the alias as
2806 being a thumb function. */
2809 s_thumb_set (int equiv)
2811 /* XXX the following is a duplicate of the code for s_set() in read.c
2812 We cannot just call that code as we need to get at the symbol that
2819 /* Especial apologies for the random logic:
2820 This just grew, and could be parsed much more simply!
2822 name = input_line_pointer;
2823 delim = get_symbol_end ();
2824 end_name = input_line_pointer;
2827 if (*input_line_pointer != ',')
2830 as_bad (_("expected comma after name \"%s\""), name);
2832 ignore_rest_of_line ();
2836 input_line_pointer++;
2839 if (name[0] == '.' && name[1] == '\0')
2841 /* XXX - this should not happen to .thumb_set. */
2845 if ((symbolP = symbol_find (name)) == NULL
2846 && (symbolP = md_undefined_symbol (name)) == NULL)
2849 /* When doing symbol listings, play games with dummy fragments living
2850 outside the normal fragment chain to record the file and line info
2852 if (listing & LISTING_SYMBOLS)
2854 extern struct list_info_struct * listing_tail;
2855 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2857 memset (dummy_frag, 0, sizeof (fragS));
2858 dummy_frag->fr_type = rs_fill;
2859 dummy_frag->line = listing_tail;
2860 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2861 dummy_frag->fr_symbol = symbolP;
2865 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2868 /* "set" symbols are local unless otherwise specified. */
2869 SF_SET_LOCAL (symbolP);
2870 #endif /* OBJ_COFF */
2871 } /* Make a new symbol. */
2873 symbol_table_insert (symbolP);
2878 && S_IS_DEFINED (symbolP)
2879 && S_GET_SEGMENT (symbolP) != reg_section)
2880 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2882 pseudo_set (symbolP);
2884 demand_empty_rest_of_line ();
2886 /* XXX Now we come to the Thumb specific bit of code. */
2888 THUMB_SET_FUNC (symbolP, 1);
2889 ARM_SET_THUMB (symbolP, 1);
2890 #if defined OBJ_ELF || defined OBJ_COFF
2891 ARM_SET_INTERWORK (symbolP, support_interwork);
2895 /* Directives: Mode selection. */
2897 /* .syntax [unified|divided] - choose the new unified syntax
2898 (same for Arm and Thumb encoding, modulo slight differences in what
2899 can be represented) or the old divergent syntax for each mode. */
2901 s_syntax (int unused ATTRIBUTE_UNUSED)
2905 name = input_line_pointer;
2906 delim = get_symbol_end ();
2908 if (!strcasecmp (name, "unified"))
2909 unified_syntax = TRUE;
2910 else if (!strcasecmp (name, "divided"))
2911 unified_syntax = FALSE;
2914 as_bad (_("unrecognized syntax mode \"%s\""), name);
2917 *input_line_pointer = delim;
2918 demand_empty_rest_of_line ();
2921 /* Directives: sectioning and alignment. */
2923 /* Same as s_align_ptwo but align 0 => align 2. */
2926 s_align (int unused ATTRIBUTE_UNUSED)
2931 long max_alignment = 15;
2933 temp = get_absolute_expression ();
2934 if (temp > max_alignment)
2935 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2938 as_bad (_("alignment negative. 0 assumed."));
2942 if (*input_line_pointer == ',')
2944 input_line_pointer++;
2945 temp_fill = get_absolute_expression ();
2957 /* Only make a frag if we HAVE to. */
2958 if (temp && !need_pass_2)
2960 if (!fill_p && subseg_text_p (now_seg))
2961 frag_align_code (temp, 0);
2963 frag_align (temp, (int) temp_fill, 0);
2965 demand_empty_rest_of_line ();
2967 record_alignment (now_seg, temp);
2971 s_bss (int ignore ATTRIBUTE_UNUSED)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: Literal pools. */
2997 static literal_pool *
2998 find_literal_pool (void)
3000 literal_pool * pool;
3002 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3004 if (pool->section == now_seg
3005 && pool->sub_section == now_subseg)
3012 static literal_pool *
3013 find_or_make_literal_pool (void)
3015 /* Next literal pool ID number. */
3016 static unsigned int latest_pool_num = 1;
3017 literal_pool * pool;
3019 pool = find_literal_pool ();
3023 /* Create a new pool. */
3024 pool = (literal_pool *) xmalloc (sizeof (* pool));
3028 pool->next_free_entry = 0;
3029 pool->section = now_seg;
3030 pool->sub_section = now_subseg;
3031 pool->next = list_of_pools;
3032 pool->symbol = NULL;
3034 /* Add it to the list. */
3035 list_of_pools = pool;
3038 /* New pools, and emptied pools, will have a NULL symbol. */
3039 if (pool->symbol == NULL)
3041 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3042 (valueT) 0, &zero_address_frag);
3043 pool->id = latest_pool_num ++;
3050 /* Add the literal in the global 'inst'
3051 structure to the relevant literal pool. */
3054 add_to_lit_pool (void)
3056 literal_pool * pool;
3059 pool = find_or_make_literal_pool ();
3061 /* Check if this literal value is already in the pool. */
3062 for (entry = 0; entry < pool->next_free_entry; entry ++)
3064 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3065 && (inst.reloc.exp.X_op == O_constant)
3066 && (pool->literals[entry].X_add_number
3067 == inst.reloc.exp.X_add_number)
3068 && (pool->literals[entry].X_unsigned
3069 == inst.reloc.exp.X_unsigned))
3072 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3073 && (inst.reloc.exp.X_op == O_symbol)
3074 && (pool->literals[entry].X_add_number
3075 == inst.reloc.exp.X_add_number)
3076 && (pool->literals[entry].X_add_symbol
3077 == inst.reloc.exp.X_add_symbol)
3078 && (pool->literals[entry].X_op_symbol
3079 == inst.reloc.exp.X_op_symbol))
3083 /* Do we need to create a new entry? */
3084 if (entry == pool->next_free_entry)
3086 if (entry >= MAX_LITERAL_POOL_SIZE)
3088 inst.error = _("literal pool overflow");
3092 pool->literals[entry] = inst.reloc.exp;
3094 /* PR ld/12974: Record the location of the first source line to reference
3095 this entry in the literal pool. If it turns out during linking that the
3096 symbol does not exist we will be able to give an accurate line number for
3097 the (first use of the) missing reference. */
3098 if (debug_type == DEBUG_DWARF2)
3099 dwarf2_where (pool->locs + entry);
3101 pool->next_free_entry += 1;
3104 inst.reloc.exp.X_op = O_symbol;
3105 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3106 inst.reloc.exp.X_add_symbol = pool->symbol;
3111 /* Can't use symbol_new here, so have to create a symbol and then at
3112 a later date assign it a value. Thats what these functions do. */
3115 symbol_locate (symbolS * symbolP,
3116 const char * name, /* It is copied, the caller can modify. */
3117 segT segment, /* Segment identifier (SEG_<something>). */
3118 valueT valu, /* Symbol value. */
3119 fragS * frag) /* Associated fragment. */
3121 unsigned int name_length;
3122 char * preserved_copy_of_name;
3124 name_length = strlen (name) + 1; /* +1 for \0. */
3125 obstack_grow (¬es, name, name_length);
3126 preserved_copy_of_name = (char *) obstack_finish (¬es);
3128 #ifdef tc_canonicalize_symbol_name
3129 preserved_copy_of_name =
3130 tc_canonicalize_symbol_name (preserved_copy_of_name);
3133 S_SET_NAME (symbolP, preserved_copy_of_name);
3135 S_SET_SEGMENT (symbolP, segment);
3136 S_SET_VALUE (symbolP, valu);
3137 symbol_clear_list_pointers (symbolP);
3139 symbol_set_frag (symbolP, frag);
3141 /* Link to end of symbol chain. */
3143 extern int symbol_table_frozen;
3145 if (symbol_table_frozen)
3149 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3151 obj_symbol_new_hook (symbolP);
3153 #ifdef tc_symbol_new_hook
3154 tc_symbol_new_hook (symbolP);
3158 verify_symbol_chain (symbol_rootP, symbol_lastP);
3159 #endif /* DEBUG_SYMS */
3164 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3167 literal_pool * pool;
3170 pool = find_literal_pool ();
3172 || pool->symbol == NULL
3173 || pool->next_free_entry == 0)
3176 mapping_state (MAP_DATA);
3178 /* Align pool as you have word accesses.
3179 Only make a frag if we have to. */
3181 frag_align (2, 0, 0);
3183 record_alignment (now_seg, 2);
3185 sprintf (sym_name, "$$lit_\002%x", pool->id);
3187 symbol_locate (pool->symbol, sym_name, now_seg,
3188 (valueT) frag_now_fix (), frag_now);
3189 symbol_table_insert (pool->symbol);
3191 ARM_SET_THUMB (pool->symbol, thumb_mode);
3193 #if defined OBJ_COFF || defined OBJ_ELF
3194 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3197 for (entry = 0; entry < pool->next_free_entry; entry ++)
3200 if (debug_type == DEBUG_DWARF2)
3201 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3203 /* First output the expression in the instruction to the pool. */
3204 emit_expr (&(pool->literals[entry]), 4); /* .word */
3207 /* Mark the pool as empty. */
3208 pool->next_free_entry = 0;
3209 pool->symbol = NULL;
3213 /* Forward declarations for functions below, in the MD interface
3215 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3216 static valueT create_unwind_entry (int);
3217 static void start_unwind_section (const segT, int);
3218 static void add_unwind_opcode (valueT, int);
3219 static void flush_pending_unwind (void);
3221 /* Directives: Data. */
3224 s_arm_elf_cons (int nbytes)
3228 #ifdef md_flush_pending_output
3229 md_flush_pending_output ();
3232 if (is_it_end_of_statement ())
3234 demand_empty_rest_of_line ();
3238 #ifdef md_cons_align
3239 md_cons_align (nbytes);
3242 mapping_state (MAP_DATA);
3246 char *base = input_line_pointer;
3250 if (exp.X_op != O_symbol)
3251 emit_expr (&exp, (unsigned int) nbytes);
3254 char *before_reloc = input_line_pointer;
3255 reloc = parse_reloc (&input_line_pointer);
3258 as_bad (_("unrecognized relocation suffix"));
3259 ignore_rest_of_line ();
3262 else if (reloc == BFD_RELOC_UNUSED)
3263 emit_expr (&exp, (unsigned int) nbytes);
3266 reloc_howto_type *howto = (reloc_howto_type *)
3267 bfd_reloc_type_lookup (stdoutput,
3268 (bfd_reloc_code_real_type) reloc);
3269 int size = bfd_get_reloc_size (howto);
3271 if (reloc == BFD_RELOC_ARM_PLT32)
3273 as_bad (_("(plt) is only valid on branch targets"));
3274 reloc = BFD_RELOC_UNUSED;
3279 as_bad (_("%s relocations do not fit in %d bytes"),
3280 howto->name, nbytes);
3283 /* We've parsed an expression stopping at O_symbol.
3284 But there may be more expression left now that we
3285 have parsed the relocation marker. Parse it again.
3286 XXX Surely there is a cleaner way to do this. */
3287 char *p = input_line_pointer;
3289 char *save_buf = (char *) alloca (input_line_pointer - base);
3290 memcpy (save_buf, base, input_line_pointer - base);
3291 memmove (base + (input_line_pointer - before_reloc),
3292 base, before_reloc - base);
3294 input_line_pointer = base + (input_line_pointer-before_reloc);
3296 memcpy (base, save_buf, p - base);
3298 offset = nbytes - size;
3299 p = frag_more ((int) nbytes);
3300 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3301 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3306 while (*input_line_pointer++ == ',');
3308 /* Put terminator back into stream. */
3309 input_line_pointer --;
3310 demand_empty_rest_of_line ();
3313 /* Emit an expression containing a 32-bit thumb instruction.
3314 Implementation based on put_thumb32_insn. */
3317 emit_thumb32_expr (expressionS * exp)
3319 expressionS exp_high = *exp;
3321 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3322 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3323 exp->X_add_number &= 0xffff;
3324 emit_expr (exp, (unsigned int) THUMB_SIZE);
3327 /* Guess the instruction size based on the opcode. */
3330 thumb_insn_size (int opcode)
3332 if ((unsigned int) opcode < 0xe800u)
3334 else if ((unsigned int) opcode >= 0xe8000000u)
3341 emit_insn (expressionS *exp, int nbytes)
3345 if (exp->X_op == O_constant)
3350 size = thumb_insn_size (exp->X_add_number);
3354 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3356 as_bad (_(".inst.n operand too big. "\
3357 "Use .inst.w instead"));
3362 if (now_it.state == AUTOMATIC_IT_BLOCK)
3363 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3365 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3367 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3368 emit_thumb32_expr (exp);
3370 emit_expr (exp, (unsigned int) size);
3372 it_fsm_post_encode ();
3376 as_bad (_("cannot determine Thumb instruction size. " \
3377 "Use .inst.n/.inst.w instead"));
3380 as_bad (_("constant expression required"));
3385 /* Like s_arm_elf_cons but do not use md_cons_align and
3386 set the mapping state to MAP_ARM/MAP_THUMB. */
3389 s_arm_elf_inst (int nbytes)
3391 if (is_it_end_of_statement ())
3393 demand_empty_rest_of_line ();
3397 /* Calling mapping_state () here will not change ARM/THUMB,
3398 but will ensure not to be in DATA state. */
3401 mapping_state (MAP_THUMB);
3406 as_bad (_("width suffixes are invalid in ARM mode"));
3407 ignore_rest_of_line ();
3413 mapping_state (MAP_ARM);
3422 if (! emit_insn (& exp, nbytes))
3424 ignore_rest_of_line ();
3428 while (*input_line_pointer++ == ',');
3430 /* Put terminator back into stream. */
3431 input_line_pointer --;
3432 demand_empty_rest_of_line ();
3435 /* Parse a .rel31 directive. */
3438 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3445 if (*input_line_pointer == '1')
3446 highbit = 0x80000000;
3447 else if (*input_line_pointer != '0')
3448 as_bad (_("expected 0 or 1"));
3450 input_line_pointer++;
3451 if (*input_line_pointer != ',')
3452 as_bad (_("missing comma"));
3453 input_line_pointer++;
3455 #ifdef md_flush_pending_output
3456 md_flush_pending_output ();
3459 #ifdef md_cons_align
3463 mapping_state (MAP_DATA);
3468 md_number_to_chars (p, highbit, 4);
3469 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3470 BFD_RELOC_ARM_PREL31);
3472 demand_empty_rest_of_line ();
3475 /* Directives: AEABI stack-unwind tables. */
3477 /* Parse an unwind_fnstart directive. Simply records the current location. */
3480 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3482 demand_empty_rest_of_line ();
3483 if (unwind.proc_start)
3485 as_bad (_("duplicate .fnstart directive"));
3489 /* Mark the start of the function. */
3490 unwind.proc_start = expr_build_dot ();
3492 /* Reset the rest of the unwind info. */
3493 unwind.opcode_count = 0;
3494 unwind.table_entry = NULL;
3495 unwind.personality_routine = NULL;
3496 unwind.personality_index = -1;
3497 unwind.frame_size = 0;
3498 unwind.fp_offset = 0;
3499 unwind.fp_reg = REG_SP;
3501 unwind.sp_restored = 0;
3505 /* Parse a handlerdata directive. Creates the exception handling table entry
3506 for the function. */
3509 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3511 demand_empty_rest_of_line ();
3512 if (!unwind.proc_start)
3513 as_bad (MISSING_FNSTART);
3515 if (unwind.table_entry)
3516 as_bad (_("duplicate .handlerdata directive"));
3518 create_unwind_entry (1);
3521 /* Parse an unwind_fnend directive. Generates the index table entry. */
3524 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3529 unsigned int marked_pr_dependency;
3531 demand_empty_rest_of_line ();
3533 if (!unwind.proc_start)
3535 as_bad (_(".fnend directive without .fnstart"));
3539 /* Add eh table entry. */
3540 if (unwind.table_entry == NULL)
3541 val = create_unwind_entry (0);
3545 /* Add index table entry. This is two words. */
3546 start_unwind_section (unwind.saved_seg, 1);
3547 frag_align (2, 0, 0);
3548 record_alignment (now_seg, 2);
3550 ptr = frag_more (8);
3552 where = frag_now_fix () - 8;
3554 /* Self relative offset of the function start. */
3555 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3556 BFD_RELOC_ARM_PREL31);
3558 /* Indicate dependency on EHABI-defined personality routines to the
3559 linker, if it hasn't been done already. */
3560 marked_pr_dependency
3561 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3562 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3563 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3565 static const char *const name[] =
3567 "__aeabi_unwind_cpp_pr0",
3568 "__aeabi_unwind_cpp_pr1",
3569 "__aeabi_unwind_cpp_pr2"
3571 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3572 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3573 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3574 |= 1 << unwind.personality_index;
3578 /* Inline exception table entry. */
3579 md_number_to_chars (ptr + 4, val, 4);
3581 /* Self relative offset of the table entry. */
3582 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3583 BFD_RELOC_ARM_PREL31);
3585 /* Restore the original section. */
3586 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3588 unwind.proc_start = NULL;
3592 /* Parse an unwind_cantunwind directive. */
3595 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3597 demand_empty_rest_of_line ();
3598 if (!unwind.proc_start)
3599 as_bad (MISSING_FNSTART);
3601 if (unwind.personality_routine || unwind.personality_index != -1)
3602 as_bad (_("personality routine specified for cantunwind frame"));
3604 unwind.personality_index = -2;
3608 /* Parse a personalityindex directive. */
3611 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3615 if (!unwind.proc_start)
3616 as_bad (MISSING_FNSTART);
3618 if (unwind.personality_routine || unwind.personality_index != -1)
3619 as_bad (_("duplicate .personalityindex directive"));
3623 if (exp.X_op != O_constant
3624 || exp.X_add_number < 0 || exp.X_add_number > 15)
3626 as_bad (_("bad personality routine number"));
3627 ignore_rest_of_line ();
3631 unwind.personality_index = exp.X_add_number;
3633 demand_empty_rest_of_line ();
3637 /* Parse a personality directive. */
3640 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3644 if (!unwind.proc_start)
3645 as_bad (MISSING_FNSTART);
3647 if (unwind.personality_routine || unwind.personality_index != -1)
3648 as_bad (_("duplicate .personality directive"));
3650 name = input_line_pointer;
3651 c = get_symbol_end ();
3652 p = input_line_pointer;
3653 unwind.personality_routine = symbol_find_or_make (name);
3655 demand_empty_rest_of_line ();
3659 /* Parse a directive saving core registers. */
3662 s_arm_unwind_save_core (void)
3668 range = parse_reg_list (&input_line_pointer);
3671 as_bad (_("expected register list"));
3672 ignore_rest_of_line ();
3676 demand_empty_rest_of_line ();
3678 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3679 into .unwind_save {..., sp...}. We aren't bothered about the value of
3680 ip because it is clobbered by calls. */
3681 if (unwind.sp_restored && unwind.fp_reg == 12
3682 && (range & 0x3000) == 0x1000)
3684 unwind.opcode_count--;
3685 unwind.sp_restored = 0;
3686 range = (range | 0x2000) & ~0x1000;
3687 unwind.pending_offset = 0;
3693 /* See if we can use the short opcodes. These pop a block of up to 8
3694 registers starting with r4, plus maybe r14. */
3695 for (n = 0; n < 8; n++)
3697 /* Break at the first non-saved register. */
3698 if ((range & (1 << (n + 4))) == 0)
3701 /* See if there are any other bits set. */
3702 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3704 /* Use the long form. */
3705 op = 0x8000 | ((range >> 4) & 0xfff);
3706 add_unwind_opcode (op, 2);
3710 /* Use the short form. */
3712 op = 0xa8; /* Pop r14. */
3714 op = 0xa0; /* Do not pop r14. */
3716 add_unwind_opcode (op, 1);
3723 op = 0xb100 | (range & 0xf);
3724 add_unwind_opcode (op, 2);
3727 /* Record the number of bytes pushed. */
3728 for (n = 0; n < 16; n++)
3730 if (range & (1 << n))
3731 unwind.frame_size += 4;
3736 /* Parse a directive saving FPA registers. */
3739 s_arm_unwind_save_fpa (int reg)
3745 /* Get Number of registers to transfer. */
3746 if (skip_past_comma (&input_line_pointer) != FAIL)
3749 exp.X_op = O_illegal;
3751 if (exp.X_op != O_constant)
3753 as_bad (_("expected , <constant>"));
3754 ignore_rest_of_line ();
3758 num_regs = exp.X_add_number;
3760 if (num_regs < 1 || num_regs > 4)
3762 as_bad (_("number of registers must be in the range [1:4]"));
3763 ignore_rest_of_line ();
3767 demand_empty_rest_of_line ();
3772 op = 0xb4 | (num_regs - 1);
3773 add_unwind_opcode (op, 1);
3778 op = 0xc800 | (reg << 4) | (num_regs - 1);
3779 add_unwind_opcode (op, 2);
3781 unwind.frame_size += num_regs * 12;
3785 /* Parse a directive saving VFP registers for ARMv6 and above. */
3788 s_arm_unwind_save_vfp_armv6 (void)
3793 int num_vfpv3_regs = 0;
3794 int num_regs_below_16;
3796 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3799 as_bad (_("expected register list"));
3800 ignore_rest_of_line ();
3804 demand_empty_rest_of_line ();
3806 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3807 than FSTMX/FLDMX-style ones). */
3809 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3811 num_vfpv3_regs = count;
3812 else if (start + count > 16)
3813 num_vfpv3_regs = start + count - 16;
3815 if (num_vfpv3_regs > 0)
3817 int start_offset = start > 16 ? start - 16 : 0;
3818 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3819 add_unwind_opcode (op, 2);
3822 /* Generate opcode for registers numbered in the range 0 .. 15. */
3823 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3824 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3825 if (num_regs_below_16 > 0)
3827 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3828 add_unwind_opcode (op, 2);
3831 unwind.frame_size += count * 8;
3835 /* Parse a directive saving VFP registers for pre-ARMv6. */
3838 s_arm_unwind_save_vfp (void)
3844 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3847 as_bad (_("expected register list"));
3848 ignore_rest_of_line ();
3852 demand_empty_rest_of_line ();
3857 op = 0xb8 | (count - 1);
3858 add_unwind_opcode (op, 1);
3863 op = 0xb300 | (reg << 4) | (count - 1);
3864 add_unwind_opcode (op, 2);
3866 unwind.frame_size += count * 8 + 4;
3870 /* Parse a directive saving iWMMXt data registers. */
3873 s_arm_unwind_save_mmxwr (void)
3881 if (*input_line_pointer == '{')
3882 input_line_pointer++;
3886 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3890 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3895 as_tsktsk (_("register list not in ascending order"));
3898 if (*input_line_pointer == '-')
3900 input_line_pointer++;
3901 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3904 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3907 else if (reg >= hi_reg)
3909 as_bad (_("bad register range"));
3912 for (; reg < hi_reg; reg++)
3916 while (skip_past_comma (&input_line_pointer) != FAIL);
3918 if (*input_line_pointer == '}')
3919 input_line_pointer++;
3921 demand_empty_rest_of_line ();
3923 /* Generate any deferred opcodes because we're going to be looking at
3925 flush_pending_unwind ();
3927 for (i = 0; i < 16; i++)
3929 if (mask & (1 << i))
3930 unwind.frame_size += 8;
3933 /* Attempt to combine with a previous opcode. We do this because gcc
3934 likes to output separate unwind directives for a single block of
3936 if (unwind.opcode_count > 0)
3938 i = unwind.opcodes[unwind.opcode_count - 1];
3939 if ((i & 0xf8) == 0xc0)
3942 /* Only merge if the blocks are contiguous. */
3945 if ((mask & 0xfe00) == (1 << 9))
3947 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3948 unwind.opcode_count--;
3951 else if (i == 6 && unwind.opcode_count >= 2)
3953 i = unwind.opcodes[unwind.opcode_count - 2];
3957 op = 0xffff << (reg - 1);
3959 && ((mask & op) == (1u << (reg - 1))))
3961 op = (1 << (reg + i + 1)) - 1;
3962 op &= ~((1 << reg) - 1);
3964 unwind.opcode_count -= 2;
3971 /* We want to generate opcodes in the order the registers have been
3972 saved, ie. descending order. */
3973 for (reg = 15; reg >= -1; reg--)
3975 /* Save registers in blocks. */
3977 || !(mask & (1 << reg)))
3979 /* We found an unsaved reg. Generate opcodes to save the
3986 op = 0xc0 | (hi_reg - 10);
3987 add_unwind_opcode (op, 1);
3992 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3993 add_unwind_opcode (op, 2);
4002 ignore_rest_of_line ();
4006 s_arm_unwind_save_mmxwcg (void)
4013 if (*input_line_pointer == '{')
4014 input_line_pointer++;
4018 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4022 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4028 as_tsktsk (_("register list not in ascending order"));
4031 if (*input_line_pointer == '-')
4033 input_line_pointer++;
4034 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4037 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4040 else if (reg >= hi_reg)
4042 as_bad (_("bad register range"));
4045 for (; reg < hi_reg; reg++)
4049 while (skip_past_comma (&input_line_pointer) != FAIL);
4051 if (*input_line_pointer == '}')
4052 input_line_pointer++;
4054 demand_empty_rest_of_line ();
4056 /* Generate any deferred opcodes because we're going to be looking at
4058 flush_pending_unwind ();
4060 for (reg = 0; reg < 16; reg++)
4062 if (mask & (1 << reg))
4063 unwind.frame_size += 4;
4066 add_unwind_opcode (op, 2);
4069 ignore_rest_of_line ();
4073 /* Parse an unwind_save directive.
4074 If the argument is non-zero, this is a .vsave directive. */
4077 s_arm_unwind_save (int arch_v6)
4080 struct reg_entry *reg;
4081 bfd_boolean had_brace = FALSE;
4083 if (!unwind.proc_start)
4084 as_bad (MISSING_FNSTART);
4086 /* Figure out what sort of save we have. */
4087 peek = input_line_pointer;
4095 reg = arm_reg_parse_multi (&peek);
4099 as_bad (_("register expected"));
4100 ignore_rest_of_line ();
4109 as_bad (_("FPA .unwind_save does not take a register list"));
4110 ignore_rest_of_line ();
4113 input_line_pointer = peek;
4114 s_arm_unwind_save_fpa (reg->number);
4117 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4120 s_arm_unwind_save_vfp_armv6 ();
4122 s_arm_unwind_save_vfp ();
4124 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4125 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4128 as_bad (_(".unwind_save does not support this kind of register"));
4129 ignore_rest_of_line ();
4134 /* Parse an unwind_movsp directive. */
4137 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4143 if (!unwind.proc_start)
4144 as_bad (MISSING_FNSTART);
4146 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4149 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4150 ignore_rest_of_line ();
4154 /* Optional constant. */
4155 if (skip_past_comma (&input_line_pointer) != FAIL)
4157 if (immediate_for_directive (&offset) == FAIL)
4163 demand_empty_rest_of_line ();
4165 if (reg == REG_SP || reg == REG_PC)
4167 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4171 if (unwind.fp_reg != REG_SP)
4172 as_bad (_("unexpected .unwind_movsp directive"));
4174 /* Generate opcode to restore the value. */
4176 add_unwind_opcode (op, 1);
4178 /* Record the information for later. */
4179 unwind.fp_reg = reg;
4180 unwind.fp_offset = unwind.frame_size - offset;
4181 unwind.sp_restored = 1;
4184 /* Parse an unwind_pad directive. */
4187 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4191 if (!unwind.proc_start)
4192 as_bad (MISSING_FNSTART);
4194 if (immediate_for_directive (&offset) == FAIL)
4199 as_bad (_("stack increment must be multiple of 4"));
4200 ignore_rest_of_line ();
4204 /* Don't generate any opcodes, just record the details for later. */
4205 unwind.frame_size += offset;
4206 unwind.pending_offset += offset;
4208 demand_empty_rest_of_line ();
4211 /* Parse an unwind_setfp directive. */
4214 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4220 if (!unwind.proc_start)
4221 as_bad (MISSING_FNSTART);
4223 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4224 if (skip_past_comma (&input_line_pointer) == FAIL)
4227 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4229 if (fp_reg == FAIL || sp_reg == FAIL)
4231 as_bad (_("expected <reg>, <reg>"));
4232 ignore_rest_of_line ();
4236 /* Optional constant. */
4237 if (skip_past_comma (&input_line_pointer) != FAIL)
4239 if (immediate_for_directive (&offset) == FAIL)
4245 demand_empty_rest_of_line ();
4247 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4249 as_bad (_("register must be either sp or set by a previous"
4250 "unwind_movsp directive"));
4254 /* Don't generate any opcodes, just record the information for later. */
4255 unwind.fp_reg = fp_reg;
4257 if (sp_reg == REG_SP)
4258 unwind.fp_offset = unwind.frame_size - offset;
4260 unwind.fp_offset -= offset;
4263 /* Parse an unwind_raw directive. */
4266 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4269 /* This is an arbitrary limit. */
4270 unsigned char op[16];
4273 if (!unwind.proc_start)
4274 as_bad (MISSING_FNSTART);
4277 if (exp.X_op == O_constant
4278 && skip_past_comma (&input_line_pointer) != FAIL)
4280 unwind.frame_size += exp.X_add_number;
4284 exp.X_op = O_illegal;
4286 if (exp.X_op != O_constant)
4288 as_bad (_("expected <offset>, <opcode>"));
4289 ignore_rest_of_line ();
4295 /* Parse the opcode. */
4300 as_bad (_("unwind opcode too long"));
4301 ignore_rest_of_line ();
4303 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4305 as_bad (_("invalid unwind opcode"));
4306 ignore_rest_of_line ();
4309 op[count++] = exp.X_add_number;
4311 /* Parse the next byte. */
4312 if (skip_past_comma (&input_line_pointer) == FAIL)
4318 /* Add the opcode bytes in reverse order. */
4320 add_unwind_opcode (op[count], 1);
4322 demand_empty_rest_of_line ();
4326 /* Parse a .eabi_attribute directive. */
4329 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4331 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4333 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4334 attributes_set_explicitly[tag] = 1;
4337 /* Emit a tls fix for the symbol. */
4340 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4344 #ifdef md_flush_pending_output
4345 md_flush_pending_output ();
4348 #ifdef md_cons_align
4352 /* Since we're just labelling the code, there's no need to define a
4355 p = obstack_next_free (&frchain_now->frch_obstack);
4356 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4357 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4358 : BFD_RELOC_ARM_TLS_DESCSEQ);
4360 #endif /* OBJ_ELF */
4362 static void s_arm_arch (int);
4363 static void s_arm_object_arch (int);
4364 static void s_arm_cpu (int);
4365 static void s_arm_fpu (int);
4366 static void s_arm_arch_extension (int);
4371 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4378 if (exp.X_op == O_symbol)
4379 exp.X_op = O_secrel;
4381 emit_expr (&exp, 4);
4383 while (*input_line_pointer++ == ',');
4385 input_line_pointer--;
4386 demand_empty_rest_of_line ();
4390 /* This table describes all the machine specific pseudo-ops the assembler
4391 has to support. The fields are:
4392 pseudo-op name without dot
4393 function to call to execute this pseudo-op
4394 Integer arg to pass to the function. */
4396 const pseudo_typeS md_pseudo_table[] =
4398 /* Never called because '.req' does not start a line. */
4399 { "req", s_req, 0 },
4400 /* Following two are likewise never called. */
4403 { "unreq", s_unreq, 0 },
4404 { "bss", s_bss, 0 },
4405 { "align", s_align, 0 },
4406 { "arm", s_arm, 0 },
4407 { "thumb", s_thumb, 0 },
4408 { "code", s_code, 0 },
4409 { "force_thumb", s_force_thumb, 0 },
4410 { "thumb_func", s_thumb_func, 0 },
4411 { "thumb_set", s_thumb_set, 0 },
4412 { "even", s_even, 0 },
4413 { "ltorg", s_ltorg, 0 },
4414 { "pool", s_ltorg, 0 },
4415 { "syntax", s_syntax, 0 },
4416 { "cpu", s_arm_cpu, 0 },
4417 { "arch", s_arm_arch, 0 },
4418 { "object_arch", s_arm_object_arch, 0 },
4419 { "fpu", s_arm_fpu, 0 },
4420 { "arch_extension", s_arm_arch_extension, 0 },
4422 { "word", s_arm_elf_cons, 4 },
4423 { "long", s_arm_elf_cons, 4 },
4424 { "inst.n", s_arm_elf_inst, 2 },
4425 { "inst.w", s_arm_elf_inst, 4 },
4426 { "inst", s_arm_elf_inst, 0 },
4427 { "rel31", s_arm_rel31, 0 },
4428 { "fnstart", s_arm_unwind_fnstart, 0 },
4429 { "fnend", s_arm_unwind_fnend, 0 },
4430 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4431 { "personality", s_arm_unwind_personality, 0 },
4432 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4433 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4434 { "save", s_arm_unwind_save, 0 },
4435 { "vsave", s_arm_unwind_save, 1 },
4436 { "movsp", s_arm_unwind_movsp, 0 },
4437 { "pad", s_arm_unwind_pad, 0 },
4438 { "setfp", s_arm_unwind_setfp, 0 },
4439 { "unwind_raw", s_arm_unwind_raw, 0 },
4440 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4441 { "tlsdescseq", s_arm_tls_descseq, 0 },
4445 /* These are used for dwarf. */
4449 /* These are used for dwarf2. */
4450 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4451 { "loc", dwarf2_directive_loc, 0 },
4452 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4454 { "extend", float_cons, 'x' },
4455 { "ldouble", float_cons, 'x' },
4456 { "packed", float_cons, 'p' },
4458 {"secrel32", pe_directive_secrel, 0},
4463 /* Parser functions used exclusively in instruction operands. */
4465 /* Generic immediate-value read function for use in insn parsing.
4466 STR points to the beginning of the immediate (the leading #);
4467 VAL receives the value; if the value is outside [MIN, MAX]
4468 issue an error. PREFIX_OPT is true if the immediate prefix is
4472 parse_immediate (char **str, int *val, int min, int max,
4473 bfd_boolean prefix_opt)
4476 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4477 if (exp.X_op != O_constant)
4479 inst.error = _("constant expression required");
4483 if (exp.X_add_number < min || exp.X_add_number > max)
4485 inst.error = _("immediate value out of range");
4489 *val = exp.X_add_number;
4493 /* Less-generic immediate-value read function with the possibility of loading a
4494 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4495 instructions. Puts the result directly in inst.operands[i]. */
4498 parse_big_immediate (char **str, int i)
4503 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4505 if (exp.X_op == O_constant)
4507 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4508 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4509 O_constant. We have to be careful not to break compilation for
4510 32-bit X_add_number, though. */
4511 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4513 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4514 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4515 inst.operands[i].regisimm = 1;
4518 else if (exp.X_op == O_big
4519 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4521 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4523 /* Bignums have their least significant bits in
4524 generic_bignum[0]. Make sure we put 32 bits in imm and
4525 32 bits in reg, in a (hopefully) portable way. */
4526 gas_assert (parts != 0);
4528 /* Make sure that the number is not too big.
4529 PR 11972: Bignums can now be sign-extended to the
4530 size of a .octa so check that the out of range bits
4531 are all zero or all one. */
4532 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4534 LITTLENUM_TYPE m = -1;
4536 if (generic_bignum[parts * 2] != 0
4537 && generic_bignum[parts * 2] != m)
4540 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4541 if (generic_bignum[j] != generic_bignum[j-1])
4545 inst.operands[i].imm = 0;
4546 for (j = 0; j < parts; j++, idx++)
4547 inst.operands[i].imm |= generic_bignum[idx]
4548 << (LITTLENUM_NUMBER_OF_BITS * j);
4549 inst.operands[i].reg = 0;
4550 for (j = 0; j < parts; j++, idx++)
4551 inst.operands[i].reg |= generic_bignum[idx]
4552 << (LITTLENUM_NUMBER_OF_BITS * j);
4553 inst.operands[i].regisimm = 1;
4563 /* Returns the pseudo-register number of an FPA immediate constant,
4564 or FAIL if there isn't a valid constant here. */
4567 parse_fpa_immediate (char ** str)
4569 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4575 /* First try and match exact strings, this is to guarantee
4576 that some formats will work even for cross assembly. */
4578 for (i = 0; fp_const[i]; i++)
4580 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4584 *str += strlen (fp_const[i]);
4585 if (is_end_of_line[(unsigned char) **str])
4591 /* Just because we didn't get a match doesn't mean that the constant
4592 isn't valid, just that it is in a format that we don't
4593 automatically recognize. Try parsing it with the standard
4594 expression routines. */
4596 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4598 /* Look for a raw floating point number. */
4599 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4600 && is_end_of_line[(unsigned char) *save_in])
4602 for (i = 0; i < NUM_FLOAT_VALS; i++)
4604 for (j = 0; j < MAX_LITTLENUMS; j++)
4606 if (words[j] != fp_values[i][j])
4610 if (j == MAX_LITTLENUMS)
4618 /* Try and parse a more complex expression, this will probably fail
4619 unless the code uses a floating point prefix (eg "0f"). */
4620 save_in = input_line_pointer;
4621 input_line_pointer = *str;
4622 if (expression (&exp) == absolute_section
4623 && exp.X_op == O_big
4624 && exp.X_add_number < 0)
4626 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4628 if (gen_to_words (words, 5, (long) 15) == 0)
4630 for (i = 0; i < NUM_FLOAT_VALS; i++)
4632 for (j = 0; j < MAX_LITTLENUMS; j++)
4634 if (words[j] != fp_values[i][j])
4638 if (j == MAX_LITTLENUMS)
4640 *str = input_line_pointer;
4641 input_line_pointer = save_in;
4648 *str = input_line_pointer;
4649 input_line_pointer = save_in;
4650 inst.error = _("invalid FPA immediate expression");
4654 /* Returns 1 if a number has "quarter-precision" float format
4655 0baBbbbbbc defgh000 00000000 00000000. */
4658 is_quarter_float (unsigned imm)
4660 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4661 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4664 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4665 0baBbbbbbc defgh000 00000000 00000000.
4666 The zero and minus-zero cases need special handling, since they can't be
4667 encoded in the "quarter-precision" float format, but can nonetheless be
4668 loaded as integer constants. */
4671 parse_qfloat_immediate (char **ccp, int *immed)
4675 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4676 int found_fpchar = 0;
4678 skip_past_char (&str, '#');
4680 /* We must not accidentally parse an integer as a floating-point number. Make
4681 sure that the value we parse is not an integer by checking for special
4682 characters '.' or 'e'.
4683 FIXME: This is a horrible hack, but doing better is tricky because type
4684 information isn't in a very usable state at parse time. */
4686 skip_whitespace (fpnum);
4688 if (strncmp (fpnum, "0x", 2) == 0)
4692 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4693 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4703 if ((str = atof_ieee (str, 's', words)) != NULL)
4705 unsigned fpword = 0;
4708 /* Our FP word must be 32 bits (single-precision FP). */
4709 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4711 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4715 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4728 /* Shift operands. */
4731 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4734 struct asm_shift_name
4737 enum shift_kind kind;
4740 /* Third argument to parse_shift. */
4741 enum parse_shift_mode
4743 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4744 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4745 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4746 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4747 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4750 /* Parse a <shift> specifier on an ARM data processing instruction.
4751 This has three forms:
4753 (LSL|LSR|ASL|ASR|ROR) Rs
4754 (LSL|LSR|ASL|ASR|ROR) #imm
4757 Note that ASL is assimilated to LSL in the instruction encoding, and
4758 RRX to ROR #0 (which cannot be written as such). */
4761 parse_shift (char **str, int i, enum parse_shift_mode mode)
4763 const struct asm_shift_name *shift_name;
4764 enum shift_kind shift;
4769 for (p = *str; ISALPHA (*p); p++)
4774 inst.error = _("shift expression expected");
4778 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4781 if (shift_name == NULL)
4783 inst.error = _("shift expression expected");
4787 shift = shift_name->kind;
4791 case NO_SHIFT_RESTRICT:
4792 case SHIFT_IMMEDIATE: break;
4794 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4795 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4797 inst.error = _("'LSL' or 'ASR' required");
4802 case SHIFT_LSL_IMMEDIATE:
4803 if (shift != SHIFT_LSL)
4805 inst.error = _("'LSL' required");
4810 case SHIFT_ASR_IMMEDIATE:
4811 if (shift != SHIFT_ASR)
4813 inst.error = _("'ASR' required");
4821 if (shift != SHIFT_RRX)
4823 /* Whitespace can appear here if the next thing is a bare digit. */
4824 skip_whitespace (p);
4826 if (mode == NO_SHIFT_RESTRICT
4827 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4829 inst.operands[i].imm = reg;
4830 inst.operands[i].immisreg = 1;
4832 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4835 inst.operands[i].shift_kind = shift;
4836 inst.operands[i].shifted = 1;
4841 /* Parse a <shifter_operand> for an ARM data processing instruction:
4844 #<immediate>, <rotate>
4848 where <shift> is defined by parse_shift above, and <rotate> is a
4849 multiple of 2 between 0 and 30. Validation of immediate operands
4850 is deferred to md_apply_fix. */
4853 parse_shifter_operand (char **str, int i)
4858 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4860 inst.operands[i].reg = value;
4861 inst.operands[i].isreg = 1;
4863 /* parse_shift will override this if appropriate */
4864 inst.reloc.exp.X_op = O_constant;
4865 inst.reloc.exp.X_add_number = 0;
4867 if (skip_past_comma (str) == FAIL)
4870 /* Shift operation on register. */
4871 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4874 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4877 if (skip_past_comma (str) == SUCCESS)
4879 /* #x, y -- ie explicit rotation by Y. */
4880 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4883 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4885 inst.error = _("constant expression expected");
4889 value = exp.X_add_number;
4890 if (value < 0 || value > 30 || value % 2 != 0)
4892 inst.error = _("invalid rotation");
4895 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4897 inst.error = _("invalid constant");
4901 /* Encode as specified. */
4902 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4906 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4907 inst.reloc.pc_rel = 0;
4911 /* Group relocation information. Each entry in the table contains the
4912 textual name of the relocation as may appear in assembler source
4913 and must end with a colon.
4914 Along with this textual name are the relocation codes to be used if
4915 the corresponding instruction is an ALU instruction (ADD or SUB only),
4916 an LDR, an LDRS, or an LDC. */
4918 struct group_reloc_table_entry
4929 /* Varieties of non-ALU group relocation. */
4936 static struct group_reloc_table_entry group_reloc_table[] =
4937 { /* Program counter relative: */
4939 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4944 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4945 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4946 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4947 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4949 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4954 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4955 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4956 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4957 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4959 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4960 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4961 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4962 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4963 /* Section base relative */
4965 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4970 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4971 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4972 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4973 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4975 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4980 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4981 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4982 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4983 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4985 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4986 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4987 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4988 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4990 /* Given the address of a pointer pointing to the textual name of a group
4991 relocation as may appear in assembler source, attempt to find its details
4992 in group_reloc_table. The pointer will be updated to the character after
4993 the trailing colon. On failure, FAIL will be returned; SUCCESS
4994 otherwise. On success, *entry will be updated to point at the relevant
4995 group_reloc_table entry. */
4998 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5001 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5003 int length = strlen (group_reloc_table[i].name);
5005 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5006 && (*str)[length] == ':')
5008 *out = &group_reloc_table[i];
5009 *str += (length + 1);
5017 /* Parse a <shifter_operand> for an ARM data processing instruction
5018 (as for parse_shifter_operand) where group relocations are allowed:
5021 #<immediate>, <rotate>
5022 #:<group_reloc>:<expression>
5026 where <group_reloc> is one of the strings defined in group_reloc_table.
5027 The hashes are optional.
5029 Everything else is as for parse_shifter_operand. */
5031 static parse_operand_result
5032 parse_shifter_operand_group_reloc (char **str, int i)
5034 /* Determine if we have the sequence of characters #: or just :
5035 coming next. If we do, then we check for a group relocation.
5036 If we don't, punt the whole lot to parse_shifter_operand. */
5038 if (((*str)[0] == '#' && (*str)[1] == ':')
5039 || (*str)[0] == ':')
5041 struct group_reloc_table_entry *entry;
5043 if ((*str)[0] == '#')
5048 /* Try to parse a group relocation. Anything else is an error. */
5049 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5051 inst.error = _("unknown group relocation");
5052 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5055 /* We now have the group relocation table entry corresponding to
5056 the name in the assembler source. Next, we parse the expression. */
5057 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5058 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5060 /* Record the relocation type (always the ALU variant here). */
5061 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5062 gas_assert (inst.reloc.type != 0);
5064 return PARSE_OPERAND_SUCCESS;
5067 return parse_shifter_operand (str, i) == SUCCESS
5068 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5070 /* Never reached. */
5073 /* Parse a Neon alignment expression. Information is written to
5074 inst.operands[i]. We assume the initial ':' has been skipped.
5076 align .imm = align << 8, .immisalign=1, .preind=0 */
5077 static parse_operand_result
5078 parse_neon_alignment (char **str, int i)
5083 my_get_expression (&exp, &p, GE_NO_PREFIX);
5085 if (exp.X_op != O_constant)
5087 inst.error = _("alignment must be constant");
5088 return PARSE_OPERAND_FAIL;
5091 inst.operands[i].imm = exp.X_add_number << 8;
5092 inst.operands[i].immisalign = 1;
5093 /* Alignments are not pre-indexes. */
5094 inst.operands[i].preind = 0;
5097 return PARSE_OPERAND_SUCCESS;
5100 /* Parse all forms of an ARM address expression. Information is written
5101 to inst.operands[i] and/or inst.reloc.
5103 Preindexed addressing (.preind=1):
5105 [Rn, #offset] .reg=Rn .reloc.exp=offset
5106 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5107 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5108 .shift_kind=shift .reloc.exp=shift_imm
5110 These three may have a trailing ! which causes .writeback to be set also.
5112 Postindexed addressing (.postind=1, .writeback=1):
5114 [Rn], #offset .reg=Rn .reloc.exp=offset
5115 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5117 .shift_kind=shift .reloc.exp=shift_imm
5119 Unindexed addressing (.preind=0, .postind=0):
5121 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5125 [Rn]{!} shorthand for [Rn,#0]{!}
5126 =immediate .isreg=0 .reloc.exp=immediate
5127 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5129 It is the caller's responsibility to check for addressing modes not
5130 supported by the instruction, and to set inst.reloc.type. */
5132 static parse_operand_result
5133 parse_address_main (char **str, int i, int group_relocations,
5134 group_reloc_type group_type)
5139 if (skip_past_char (&p, '[') == FAIL)
5141 if (skip_past_char (&p, '=') == FAIL)
5143 /* Bare address - translate to PC-relative offset. */
5144 inst.reloc.pc_rel = 1;
5145 inst.operands[i].reg = REG_PC;
5146 inst.operands[i].isreg = 1;
5147 inst.operands[i].preind = 1;
5149 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5151 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5152 return PARSE_OPERAND_FAIL;
5155 return PARSE_OPERAND_SUCCESS;
5158 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5160 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5161 return PARSE_OPERAND_FAIL;
5163 inst.operands[i].reg = reg;
5164 inst.operands[i].isreg = 1;
5166 if (skip_past_comma (&p) == SUCCESS)
5168 inst.operands[i].preind = 1;
5171 else if (*p == '-') p++, inst.operands[i].negative = 1;
5173 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5175 inst.operands[i].imm = reg;
5176 inst.operands[i].immisreg = 1;
5178 if (skip_past_comma (&p) == SUCCESS)
5179 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5180 return PARSE_OPERAND_FAIL;
5182 else if (skip_past_char (&p, ':') == SUCCESS)
5184 /* FIXME: '@' should be used here, but it's filtered out by generic
5185 code before we get to see it here. This may be subject to
5187 parse_operand_result result = parse_neon_alignment (&p, i);
5189 if (result != PARSE_OPERAND_SUCCESS)
5194 if (inst.operands[i].negative)
5196 inst.operands[i].negative = 0;
5200 if (group_relocations
5201 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5203 struct group_reloc_table_entry *entry;
5205 /* Skip over the #: or : sequence. */
5211 /* Try to parse a group relocation. Anything else is an
5213 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5215 inst.error = _("unknown group relocation");
5216 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5219 /* We now have the group relocation table entry corresponding to
5220 the name in the assembler source. Next, we parse the
5222 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5223 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5225 /* Record the relocation type. */
5229 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5233 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5237 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5244 if (inst.reloc.type == 0)
5246 inst.error = _("this group relocation is not allowed on this instruction");
5247 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5253 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5254 return PARSE_OPERAND_FAIL;
5255 /* If the offset is 0, find out if it's a +0 or -0. */
5256 if (inst.reloc.exp.X_op == O_constant
5257 && inst.reloc.exp.X_add_number == 0)
5259 skip_whitespace (q);
5263 skip_whitespace (q);
5266 inst.operands[i].negative = 1;
5271 else if (skip_past_char (&p, ':') == SUCCESS)
5273 /* FIXME: '@' should be used here, but it's filtered out by generic code
5274 before we get to see it here. This may be subject to change. */
5275 parse_operand_result result = parse_neon_alignment (&p, i);
5277 if (result != PARSE_OPERAND_SUCCESS)
5281 if (skip_past_char (&p, ']') == FAIL)
5283 inst.error = _("']' expected");
5284 return PARSE_OPERAND_FAIL;
5287 if (skip_past_char (&p, '!') == SUCCESS)
5288 inst.operands[i].writeback = 1;
5290 else if (skip_past_comma (&p) == SUCCESS)
5292 if (skip_past_char (&p, '{') == SUCCESS)
5294 /* [Rn], {expr} - unindexed, with option */
5295 if (parse_immediate (&p, &inst.operands[i].imm,
5296 0, 255, TRUE) == FAIL)
5297 return PARSE_OPERAND_FAIL;
5299 if (skip_past_char (&p, '}') == FAIL)
5301 inst.error = _("'}' expected at end of 'option' field");
5302 return PARSE_OPERAND_FAIL;
5304 if (inst.operands[i].preind)
5306 inst.error = _("cannot combine index with option");
5307 return PARSE_OPERAND_FAIL;
5310 return PARSE_OPERAND_SUCCESS;
5314 inst.operands[i].postind = 1;
5315 inst.operands[i].writeback = 1;
5317 if (inst.operands[i].preind)
5319 inst.error = _("cannot combine pre- and post-indexing");
5320 return PARSE_OPERAND_FAIL;
5324 else if (*p == '-') p++, inst.operands[i].negative = 1;
5326 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5328 /* We might be using the immediate for alignment already. If we
5329 are, OR the register number into the low-order bits. */
5330 if (inst.operands[i].immisalign)
5331 inst.operands[i].imm |= reg;
5333 inst.operands[i].imm = reg;
5334 inst.operands[i].immisreg = 1;
5336 if (skip_past_comma (&p) == SUCCESS)
5337 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5338 return PARSE_OPERAND_FAIL;
5343 if (inst.operands[i].negative)
5345 inst.operands[i].negative = 0;
5348 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5349 return PARSE_OPERAND_FAIL;
5350 /* If the offset is 0, find out if it's a +0 or -0. */
5351 if (inst.reloc.exp.X_op == O_constant
5352 && inst.reloc.exp.X_add_number == 0)
5354 skip_whitespace (q);
5358 skip_whitespace (q);
5361 inst.operands[i].negative = 1;
5367 /* If at this point neither .preind nor .postind is set, we have a
5368 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5369 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5371 inst.operands[i].preind = 1;
5372 inst.reloc.exp.X_op = O_constant;
5373 inst.reloc.exp.X_add_number = 0;
5376 return PARSE_OPERAND_SUCCESS;
5380 parse_address (char **str, int i)
5382 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5386 static parse_operand_result
5387 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5389 return parse_address_main (str, i, 1, type);
5392 /* Parse an operand for a MOVW or MOVT instruction. */
5394 parse_half (char **str)
5399 skip_past_char (&p, '#');
5400 if (strncasecmp (p, ":lower16:", 9) == 0)
5401 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5402 else if (strncasecmp (p, ":upper16:", 9) == 0)
5403 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5405 if (inst.reloc.type != BFD_RELOC_UNUSED)
5408 skip_whitespace (p);
5411 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5414 if (inst.reloc.type == BFD_RELOC_UNUSED)
5416 if (inst.reloc.exp.X_op != O_constant)
5418 inst.error = _("constant expression expected");
5421 if (inst.reloc.exp.X_add_number < 0
5422 || inst.reloc.exp.X_add_number > 0xffff)
5424 inst.error = _("immediate value out of range");
5432 /* Miscellaneous. */
5434 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5435 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5437 parse_psr (char **str, bfd_boolean lhs)
5440 unsigned long psr_field;
5441 const struct asm_psr *psr;
5443 bfd_boolean is_apsr = FALSE;
5444 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5446 /* PR gas/12698: If the user has specified -march=all then m_profile will
5447 be TRUE, but we want to ignore it in this case as we are building for any
5448 CPU type, including non-m variants. */
5449 if (selected_cpu.core == arm_arch_any.core)
5452 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5453 feature for ease of use and backwards compatibility. */
5455 if (strncasecmp (p, "SPSR", 4) == 0)
5458 goto unsupported_psr;
5460 psr_field = SPSR_BIT;
5462 else if (strncasecmp (p, "CPSR", 4) == 0)
5465 goto unsupported_psr;
5469 else if (strncasecmp (p, "APSR", 4) == 0)
5471 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5472 and ARMv7-R architecture CPUs. */
5481 while (ISALNUM (*p) || *p == '_');
5483 if (strncasecmp (start, "iapsr", 5) == 0
5484 || strncasecmp (start, "eapsr", 5) == 0
5485 || strncasecmp (start, "xpsr", 4) == 0
5486 || strncasecmp (start, "psr", 3) == 0)
5487 p = start + strcspn (start, "rR") + 1;
5489 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5495 /* If APSR is being written, a bitfield may be specified. Note that
5496 APSR itself is handled above. */
5497 if (psr->field <= 3)
5499 psr_field = psr->field;
5505 /* M-profile MSR instructions have the mask field set to "10", except
5506 *PSR variants which modify APSR, which may use a different mask (and
5507 have been handled already). Do that by setting the PSR_f field
5509 return psr->field | (lhs ? PSR_f : 0);
5512 goto unsupported_psr;
5518 /* A suffix follows. */
5524 while (ISALNUM (*p) || *p == '_');
5528 /* APSR uses a notation for bits, rather than fields. */
5529 unsigned int nzcvq_bits = 0;
5530 unsigned int g_bit = 0;
5533 for (bit = start; bit != p; bit++)
5535 switch (TOLOWER (*bit))
5538 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5542 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5546 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5550 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5554 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5558 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5562 inst.error = _("unexpected bit specified after APSR");
5567 if (nzcvq_bits == 0x1f)
5572 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5574 inst.error = _("selected processor does not "
5575 "support DSP extension");
5582 if ((nzcvq_bits & 0x20) != 0
5583 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5584 || (g_bit & 0x2) != 0)
5586 inst.error = _("bad bitmask specified after APSR");
5592 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5597 psr_field |= psr->field;
5603 goto error; /* Garbage after "[CS]PSR". */
5605 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5606 is deprecated, but allow it anyway. */
5610 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5613 else if (!m_profile)
5614 /* These bits are never right for M-profile devices: don't set them
5615 (only code paths which read/write APSR reach here). */
5616 psr_field |= (PSR_c | PSR_f);
5622 inst.error = _("selected processor does not support requested special "
5623 "purpose register");
5627 inst.error = _("flag for {c}psr instruction expected");
5631 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5632 value suitable for splatting into the AIF field of the instruction. */
5635 parse_cps_flags (char **str)
5644 case '\0': case ',':
5647 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5648 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5649 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5652 inst.error = _("unrecognized CPS flag");
5657 if (saw_a_flag == 0)
5659 inst.error = _("missing CPS flags");
5667 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5668 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5671 parse_endian_specifier (char **str)
5676 if (strncasecmp (s, "BE", 2))
5678 else if (strncasecmp (s, "LE", 2))
5682 inst.error = _("valid endian specifiers are be or le");
5686 if (ISALNUM (s[2]) || s[2] == '_')
5688 inst.error = _("valid endian specifiers are be or le");
5693 return little_endian;
5696 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5697 value suitable for poking into the rotate field of an sxt or sxta
5698 instruction, or FAIL on error. */
5701 parse_ror (char **str)
5706 if (strncasecmp (s, "ROR", 3) == 0)
5710 inst.error = _("missing rotation field after comma");
5714 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5719 case 0: *str = s; return 0x0;
5720 case 8: *str = s; return 0x1;
5721 case 16: *str = s; return 0x2;
5722 case 24: *str = s; return 0x3;
5725 inst.error = _("rotation can only be 0, 8, 16, or 24");
5730 /* Parse a conditional code (from conds[] below). The value returned is in the
5731 range 0 .. 14, or FAIL. */
5733 parse_cond (char **str)
5736 const struct asm_cond *c;
5738 /* Condition codes are always 2 characters, so matching up to
5739 3 characters is sufficient. */
5744 while (ISALPHA (*q) && n < 3)
5746 cond[n] = TOLOWER (*q);
5751 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5754 inst.error = _("condition required");
5762 /* Parse an option for a barrier instruction. Returns the encoding for the
5765 parse_barrier (char **str)
5768 const struct asm_barrier_opt *o;
5771 while (ISALPHA (*q))
5774 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5783 /* Parse the operands of a table branch instruction. Similar to a memory
5786 parse_tb (char **str)
5791 if (skip_past_char (&p, '[') == FAIL)
5793 inst.error = _("'[' expected");
5797 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5802 inst.operands[0].reg = reg;
5804 if (skip_past_comma (&p) == FAIL)
5806 inst.error = _("',' expected");
5810 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5812 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5815 inst.operands[0].imm = reg;
5817 if (skip_past_comma (&p) == SUCCESS)
5819 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5821 if (inst.reloc.exp.X_add_number != 1)
5823 inst.error = _("invalid shift");
5826 inst.operands[0].shifted = 1;
5829 if (skip_past_char (&p, ']') == FAIL)
5831 inst.error = _("']' expected");
5838 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5839 information on the types the operands can take and how they are encoded.
5840 Up to four operands may be read; this function handles setting the
5841 ".present" field for each read operand itself.
5842 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5843 else returns FAIL. */
5846 parse_neon_mov (char **str, int *which_operand)
5848 int i = *which_operand, val;
5849 enum arm_reg_type rtype;
5851 struct neon_type_el optype;
5853 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5855 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5856 inst.operands[i].reg = val;
5857 inst.operands[i].isscalar = 1;
5858 inst.operands[i].vectype = optype;
5859 inst.operands[i++].present = 1;
5861 if (skip_past_comma (&ptr) == FAIL)
5864 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5867 inst.operands[i].reg = val;
5868 inst.operands[i].isreg = 1;
5869 inst.operands[i].present = 1;
5871 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5874 /* Cases 0, 1, 2, 3, 5 (D only). */
5875 if (skip_past_comma (&ptr) == FAIL)
5878 inst.operands[i].reg = val;
5879 inst.operands[i].isreg = 1;
5880 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5881 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5882 inst.operands[i].isvec = 1;
5883 inst.operands[i].vectype = optype;
5884 inst.operands[i++].present = 1;
5886 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5888 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5889 Case 13: VMOV <Sd>, <Rm> */
5890 inst.operands[i].reg = val;
5891 inst.operands[i].isreg = 1;
5892 inst.operands[i].present = 1;
5894 if (rtype == REG_TYPE_NQ)
5896 first_error (_("can't use Neon quad register here"));
5899 else if (rtype != REG_TYPE_VFS)
5902 if (skip_past_comma (&ptr) == FAIL)
5904 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5906 inst.operands[i].reg = val;
5907 inst.operands[i].isreg = 1;
5908 inst.operands[i].present = 1;
5911 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5914 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5915 Case 1: VMOV<c><q> <Dd>, <Dm>
5916 Case 8: VMOV.F32 <Sd>, <Sm>
5917 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5919 inst.operands[i].reg = val;
5920 inst.operands[i].isreg = 1;
5921 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5922 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5923 inst.operands[i].isvec = 1;
5924 inst.operands[i].vectype = optype;
5925 inst.operands[i].present = 1;
5927 if (skip_past_comma (&ptr) == SUCCESS)
5932 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5935 inst.operands[i].reg = val;
5936 inst.operands[i].isreg = 1;
5937 inst.operands[i++].present = 1;
5939 if (skip_past_comma (&ptr) == FAIL)
5942 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5945 inst.operands[i].reg = val;
5946 inst.operands[i].isreg = 1;
5947 inst.operands[i].present = 1;
5950 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5951 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5952 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5953 Case 10: VMOV.F32 <Sd>, #<imm>
5954 Case 11: VMOV.F64 <Dd>, #<imm> */
5955 inst.operands[i].immisfloat = 1;
5956 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5957 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5958 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5962 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5966 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5969 inst.operands[i].reg = val;
5970 inst.operands[i].isreg = 1;
5971 inst.operands[i++].present = 1;
5973 if (skip_past_comma (&ptr) == FAIL)
5976 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5978 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5979 inst.operands[i].reg = val;
5980 inst.operands[i].isscalar = 1;
5981 inst.operands[i].present = 1;
5982 inst.operands[i].vectype = optype;
5984 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5986 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i++].present = 1;
5991 if (skip_past_comma (&ptr) == FAIL)
5994 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5997 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6001 inst.operands[i].reg = val;
6002 inst.operands[i].isreg = 1;
6003 inst.operands[i].isvec = 1;
6004 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6005 inst.operands[i].vectype = optype;
6006 inst.operands[i].present = 1;
6008 if (rtype == REG_TYPE_VFS)
6012 if (skip_past_comma (&ptr) == FAIL)
6014 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6017 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6020 inst.operands[i].reg = val;
6021 inst.operands[i].isreg = 1;
6022 inst.operands[i].isvec = 1;
6023 inst.operands[i].issingle = 1;
6024 inst.operands[i].vectype = optype;
6025 inst.operands[i].present = 1;
6028 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6032 inst.operands[i].reg = val;
6033 inst.operands[i].isreg = 1;
6034 inst.operands[i].isvec = 1;
6035 inst.operands[i].issingle = 1;
6036 inst.operands[i].vectype = optype;
6037 inst.operands[i].present = 1;
6042 first_error (_("parse error"));
6046 /* Successfully parsed the operands. Update args. */
6052 first_error (_("expected comma"));
6056 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6060 /* Use this macro when the operand constraints are different
6061 for ARM and THUMB (e.g. ldrd). */
6062 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6063 ((arm_operand) | ((thumb_operand) << 16))
6065 /* Matcher codes for parse_operands. */
6066 enum operand_parse_code
6068 OP_stop, /* end of line */
6070 OP_RR, /* ARM register */
6071 OP_RRnpc, /* ARM register, not r15 */
6072 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6073 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6074 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6075 optional trailing ! */
6076 OP_RRw, /* ARM register, not r15, optional trailing ! */
6077 OP_RCP, /* Coprocessor number */
6078 OP_RCN, /* Coprocessor register */
6079 OP_RF, /* FPA register */
6080 OP_RVS, /* VFP single precision register */
6081 OP_RVD, /* VFP double precision register (0..15) */
6082 OP_RND, /* Neon double precision register (0..31) */
6083 OP_RNQ, /* Neon quad precision register */
6084 OP_RVSD, /* VFP single or double precision register */
6085 OP_RNDQ, /* Neon double or quad precision register */
6086 OP_RNSDQ, /* Neon single, double or quad precision register */
6087 OP_RNSC, /* Neon scalar D[X] */
6088 OP_RVC, /* VFP control register */
6089 OP_RMF, /* Maverick F register */
6090 OP_RMD, /* Maverick D register */
6091 OP_RMFX, /* Maverick FX register */
6092 OP_RMDX, /* Maverick DX register */
6093 OP_RMAX, /* Maverick AX register */
6094 OP_RMDS, /* Maverick DSPSC register */
6095 OP_RIWR, /* iWMMXt wR register */
6096 OP_RIWC, /* iWMMXt wC register */
6097 OP_RIWG, /* iWMMXt wCG register */
6098 OP_RXA, /* XScale accumulator register */
6100 OP_REGLST, /* ARM register list */
6101 OP_VRSLST, /* VFP single-precision register list */
6102 OP_VRDLST, /* VFP double-precision register list */
6103 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6104 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6105 OP_NSTRLST, /* Neon element/structure list */
6107 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6108 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6109 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6110 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6111 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6112 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6113 OP_VMOV, /* Neon VMOV operands. */
6114 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6115 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6116 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6118 OP_I0, /* immediate zero */
6119 OP_I7, /* immediate value 0 .. 7 */
6120 OP_I15, /* 0 .. 15 */
6121 OP_I16, /* 1 .. 16 */
6122 OP_I16z, /* 0 .. 16 */
6123 OP_I31, /* 0 .. 31 */
6124 OP_I31w, /* 0 .. 31, optional trailing ! */
6125 OP_I32, /* 1 .. 32 */
6126 OP_I32z, /* 0 .. 32 */
6127 OP_I63, /* 0 .. 63 */
6128 OP_I63s, /* -64 .. 63 */
6129 OP_I64, /* 1 .. 64 */
6130 OP_I64z, /* 0 .. 64 */
6131 OP_I255, /* 0 .. 255 */
6133 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6134 OP_I7b, /* 0 .. 7 */
6135 OP_I15b, /* 0 .. 15 */
6136 OP_I31b, /* 0 .. 31 */
6138 OP_SH, /* shifter operand */
6139 OP_SHG, /* shifter operand with possible group relocation */
6140 OP_ADDR, /* Memory address expression (any mode) */
6141 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6142 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6143 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6144 OP_EXP, /* arbitrary expression */
6145 OP_EXPi, /* same, with optional immediate prefix */
6146 OP_EXPr, /* same, with optional relocation suffix */
6147 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6149 OP_CPSF, /* CPS flags */
6150 OP_ENDI, /* Endianness specifier */
6151 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6152 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6153 OP_COND, /* conditional code */
6154 OP_TB, /* Table branch. */
6156 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6158 OP_RRnpc_I0, /* ARM register or literal 0 */
6159 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6160 OP_RR_EXi, /* ARM register or expression with imm prefix */
6161 OP_RF_IF, /* FPA register or immediate */
6162 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6163 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6165 /* Optional operands. */
6166 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6167 OP_oI31b, /* 0 .. 31 */
6168 OP_oI32b, /* 1 .. 32 */
6169 OP_oI32z, /* 0 .. 32 */
6170 OP_oIffffb, /* 0 .. 65535 */
6171 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6173 OP_oRR, /* ARM register */
6174 OP_oRRnpc, /* ARM register, not the PC */
6175 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6176 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6177 OP_oRND, /* Optional Neon double precision register */
6178 OP_oRNQ, /* Optional Neon quad precision register */
6179 OP_oRNDQ, /* Optional Neon double or quad precision register */
6180 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6181 OP_oSHll, /* LSL immediate */
6182 OP_oSHar, /* ASR immediate */
6183 OP_oSHllar, /* LSL or ASR immediate */
6184 OP_oROR, /* ROR 0/8/16/24 */
6185 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6187 /* Some pre-defined mixed (ARM/THUMB) operands. */
6188 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6189 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6190 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6192 OP_FIRST_OPTIONAL = OP_oI7b
6195 /* Generic instruction operand parser. This does no encoding and no
6196 semantic validation; it merely squirrels values away in the inst
6197 structure. Returns SUCCESS or FAIL depending on whether the
6198 specified grammar matched. */
6200 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6202 unsigned const int *upat = pattern;
6203 char *backtrack_pos = 0;
6204 const char *backtrack_error = 0;
6205 int i, val = 0, backtrack_index = 0;
6206 enum arm_reg_type rtype;
6207 parse_operand_result result;
6208 unsigned int op_parse_code;
6210 #define po_char_or_fail(chr) \
6213 if (skip_past_char (&str, chr) == FAIL) \
6218 #define po_reg_or_fail(regtype) \
6221 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6222 & inst.operands[i].vectype); \
6225 first_error (_(reg_expected_msgs[regtype])); \
6228 inst.operands[i].reg = val; \
6229 inst.operands[i].isreg = 1; \
6230 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6231 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6232 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6233 || rtype == REG_TYPE_VFD \
6234 || rtype == REG_TYPE_NQ); \
6238 #define po_reg_or_goto(regtype, label) \
6241 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6242 & inst.operands[i].vectype); \
6246 inst.operands[i].reg = val; \
6247 inst.operands[i].isreg = 1; \
6248 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6249 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6250 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6251 || rtype == REG_TYPE_VFD \
6252 || rtype == REG_TYPE_NQ); \
6256 #define po_imm_or_fail(min, max, popt) \
6259 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6261 inst.operands[i].imm = val; \
6265 #define po_scalar_or_goto(elsz, label) \
6268 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6271 inst.operands[i].reg = val; \
6272 inst.operands[i].isscalar = 1; \
6276 #define po_misc_or_fail(expr) \
6284 #define po_misc_or_fail_no_backtrack(expr) \
6288 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6289 backtrack_pos = 0; \
6290 if (result != PARSE_OPERAND_SUCCESS) \
6295 #define po_barrier_or_imm(str) \
6298 val = parse_barrier (&str); \
6301 if (ISALPHA (*str)) \
6308 if ((inst.instruction & 0xf0) == 0x60 \
6311 /* ISB can only take SY as an option. */ \
6312 inst.error = _("invalid barrier type"); \
6319 skip_whitespace (str);
6321 for (i = 0; upat[i] != OP_stop; i++)
6323 op_parse_code = upat[i];
6324 if (op_parse_code >= 1<<16)
6325 op_parse_code = thumb ? (op_parse_code >> 16)
6326 : (op_parse_code & ((1<<16)-1));
6328 if (op_parse_code >= OP_FIRST_OPTIONAL)
6330 /* Remember where we are in case we need to backtrack. */
6331 gas_assert (!backtrack_pos);
6332 backtrack_pos = str;
6333 backtrack_error = inst.error;
6334 backtrack_index = i;
6337 if (i > 0 && (i > 1 || inst.operands[0].present))
6338 po_char_or_fail (',');
6340 switch (op_parse_code)
6348 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6349 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6350 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6351 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6352 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6353 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6355 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6357 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6359 /* Also accept generic coprocessor regs for unknown registers. */
6361 po_reg_or_fail (REG_TYPE_CN);
6363 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6364 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6365 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6366 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6367 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6368 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6369 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6370 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6371 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6372 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6374 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6376 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6377 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6379 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6381 /* Neon scalar. Using an element size of 8 means that some invalid
6382 scalars are accepted here, so deal with those in later code. */
6383 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6387 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6390 po_imm_or_fail (0, 0, TRUE);
6395 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6400 po_scalar_or_goto (8, try_rr);
6403 po_reg_or_fail (REG_TYPE_RN);
6409 po_scalar_or_goto (8, try_nsdq);
6412 po_reg_or_fail (REG_TYPE_NSDQ);
6418 po_scalar_or_goto (8, try_ndq);
6421 po_reg_or_fail (REG_TYPE_NDQ);
6427 po_scalar_or_goto (8, try_vfd);
6430 po_reg_or_fail (REG_TYPE_VFD);
6435 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6436 not careful then bad things might happen. */
6437 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6442 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6445 /* There's a possibility of getting a 64-bit immediate here, so
6446 we need special handling. */
6447 if (parse_big_immediate (&str, i) == FAIL)
6449 inst.error = _("immediate value is out of range");
6457 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6460 po_imm_or_fail (0, 63, TRUE);
6465 po_char_or_fail ('[');
6466 po_reg_or_fail (REG_TYPE_RN);
6467 po_char_or_fail (']');
6473 po_reg_or_fail (REG_TYPE_RN);
6474 if (skip_past_char (&str, '!') == SUCCESS)
6475 inst.operands[i].writeback = 1;
6479 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6480 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6481 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6482 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6483 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6484 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6485 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6486 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6487 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6488 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6489 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6490 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6492 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6494 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6495 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6497 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6498 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6499 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6500 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6502 /* Immediate variants */
6504 po_char_or_fail ('{');
6505 po_imm_or_fail (0, 255, TRUE);
6506 po_char_or_fail ('}');
6510 /* The expression parser chokes on a trailing !, so we have
6511 to find it first and zap it. */
6514 while (*s && *s != ',')
6519 inst.operands[i].writeback = 1;
6521 po_imm_or_fail (0, 31, TRUE);
6529 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6534 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6539 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6541 if (inst.reloc.exp.X_op == O_symbol)
6543 val = parse_reloc (&str);
6546 inst.error = _("unrecognized relocation suffix");
6549 else if (val != BFD_RELOC_UNUSED)
6551 inst.operands[i].imm = val;
6552 inst.operands[i].hasreloc = 1;
6557 /* Operand for MOVW or MOVT. */
6559 po_misc_or_fail (parse_half (&str));
6562 /* Register or expression. */
6563 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6564 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6566 /* Register or immediate. */
6567 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6568 I0: po_imm_or_fail (0, 0, FALSE); break;
6570 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6572 if (!is_immediate_prefix (*str))
6575 val = parse_fpa_immediate (&str);
6578 /* FPA immediates are encoded as registers 8-15.
6579 parse_fpa_immediate has already applied the offset. */
6580 inst.operands[i].reg = val;
6581 inst.operands[i].isreg = 1;
6584 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6585 I32z: po_imm_or_fail (0, 32, FALSE); break;
6587 /* Two kinds of register. */
6590 struct reg_entry *rege = arm_reg_parse_multi (&str);
6592 || (rege->type != REG_TYPE_MMXWR
6593 && rege->type != REG_TYPE_MMXWC
6594 && rege->type != REG_TYPE_MMXWCG))
6596 inst.error = _("iWMMXt data or control register expected");
6599 inst.operands[i].reg = rege->number;
6600 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6606 struct reg_entry *rege = arm_reg_parse_multi (&str);
6608 || (rege->type != REG_TYPE_MMXWC
6609 && rege->type != REG_TYPE_MMXWCG))
6611 inst.error = _("iWMMXt control register expected");
6614 inst.operands[i].reg = rege->number;
6615 inst.operands[i].isreg = 1;
6620 case OP_CPSF: val = parse_cps_flags (&str); break;
6621 case OP_ENDI: val = parse_endian_specifier (&str); break;
6622 case OP_oROR: val = parse_ror (&str); break;
6623 case OP_COND: val = parse_cond (&str); break;
6624 case OP_oBARRIER_I15:
6625 po_barrier_or_imm (str); break;
6627 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6633 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6634 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6636 inst.error = _("Banked registers are not available with this "
6642 val = parse_psr (&str, op_parse_code == OP_wPSR);
6646 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6651 if (strncasecmp (str, "APSR_", 5) == 0)
6658 case 'c': found = (found & 1) ? 16 : found | 1; break;
6659 case 'n': found = (found & 2) ? 16 : found | 2; break;
6660 case 'z': found = (found & 4) ? 16 : found | 4; break;
6661 case 'v': found = (found & 8) ? 16 : found | 8; break;
6662 default: found = 16;
6666 inst.operands[i].isvec = 1;
6667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6668 inst.operands[i].reg = REG_PC;
6675 po_misc_or_fail (parse_tb (&str));
6678 /* Register lists. */
6680 val = parse_reg_list (&str);
6683 inst.operands[1].writeback = 1;
6689 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6693 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6697 /* Allow Q registers too. */
6698 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6703 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6705 inst.operands[i].issingle = 1;
6710 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6715 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6716 &inst.operands[i].vectype);
6719 /* Addressing modes */
6721 po_misc_or_fail (parse_address (&str, i));
6725 po_misc_or_fail_no_backtrack (
6726 parse_address_group_reloc (&str, i, GROUP_LDR));
6730 po_misc_or_fail_no_backtrack (
6731 parse_address_group_reloc (&str, i, GROUP_LDRS));
6735 po_misc_or_fail_no_backtrack (
6736 parse_address_group_reloc (&str, i, GROUP_LDC));
6740 po_misc_or_fail (parse_shifter_operand (&str, i));
6744 po_misc_or_fail_no_backtrack (
6745 parse_shifter_operand_group_reloc (&str, i));
6749 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6753 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6757 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6761 as_fatal (_("unhandled operand code %d"), op_parse_code);
6764 /* Various value-based sanity checks and shared operations. We
6765 do not signal immediate failures for the register constraints;
6766 this allows a syntax error to take precedence. */
6767 switch (op_parse_code)
6775 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6776 inst.error = BAD_PC;
6781 if (inst.operands[i].isreg)
6783 if (inst.operands[i].reg == REG_PC)
6784 inst.error = BAD_PC;
6785 else if (inst.operands[i].reg == REG_SP)
6786 inst.error = BAD_SP;
6791 if (inst.operands[i].isreg
6792 && inst.operands[i].reg == REG_PC
6793 && (inst.operands[i].writeback || thumb))
6794 inst.error = BAD_PC;
6803 case OP_oBARRIER_I15:
6812 inst.operands[i].imm = val;
6819 /* If we get here, this operand was successfully parsed. */
6820 inst.operands[i].present = 1;
6824 inst.error = BAD_ARGS;
6829 /* The parse routine should already have set inst.error, but set a
6830 default here just in case. */
6832 inst.error = _("syntax error");
6836 /* Do not backtrack over a trailing optional argument that
6837 absorbed some text. We will only fail again, with the
6838 'garbage following instruction' error message, which is
6839 probably less helpful than the current one. */
6840 if (backtrack_index == i && backtrack_pos != str
6841 && upat[i+1] == OP_stop)
6844 inst.error = _("syntax error");
6848 /* Try again, skipping the optional argument at backtrack_pos. */
6849 str = backtrack_pos;
6850 inst.error = backtrack_error;
6851 inst.operands[backtrack_index].present = 0;
6852 i = backtrack_index;
6856 /* Check that we have parsed all the arguments. */
6857 if (*str != '\0' && !inst.error)
6858 inst.error = _("garbage following instruction");
6860 return inst.error ? FAIL : SUCCESS;
6863 #undef po_char_or_fail
6864 #undef po_reg_or_fail
6865 #undef po_reg_or_goto
6866 #undef po_imm_or_fail
6867 #undef po_scalar_or_fail
6868 #undef po_barrier_or_imm
6870 /* Shorthand macro for instruction encoding functions issuing errors. */
6871 #define constraint(expr, err) \
6882 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6883 instructions are unpredictable if these registers are used. This
6884 is the BadReg predicate in ARM's Thumb-2 documentation. */
6885 #define reject_bad_reg(reg) \
6887 if (reg == REG_SP || reg == REG_PC) \
6889 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6894 /* If REG is R13 (the stack pointer), warn that its use is
6896 #define warn_deprecated_sp(reg) \
6898 if (warn_on_deprecated && reg == REG_SP) \
6899 as_warn (_("use of r13 is deprecated")); \
6902 /* Functions for operand encoding. ARM, then Thumb. */
6904 #define rotate_left(v, n) (v << n | v >> (32 - n))
6906 /* If VAL can be encoded in the immediate field of an ARM instruction,
6907 return the encoded form. Otherwise, return FAIL. */
6910 encode_arm_immediate (unsigned int val)
6914 for (i = 0; i < 32; i += 2)
6915 if ((a = rotate_left (val, i)) <= 0xff)
6916 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6921 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6922 return the encoded form. Otherwise, return FAIL. */
6924 encode_thumb32_immediate (unsigned int val)
6931 for (i = 1; i <= 24; i++)
6934 if ((val & ~(0xff << i)) == 0)
6935 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6939 if (val == ((a << 16) | a))
6941 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6945 if (val == ((a << 16) | a))
6946 return 0x200 | (a >> 8);
6950 /* Encode a VFP SP or DP register number into inst.instruction. */
6953 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6955 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6958 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6961 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6964 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6969 first_error (_("D register out of range for selected VFP version"));
6977 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6981 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6985 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6989 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6993 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6997 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7005 /* Encode a <shift> in an ARM-format instruction. The immediate,
7006 if any, is handled by md_apply_fix. */
7008 encode_arm_shift (int i)
7010 if (inst.operands[i].shift_kind == SHIFT_RRX)
7011 inst.instruction |= SHIFT_ROR << 5;
7014 inst.instruction |= inst.operands[i].shift_kind << 5;
7015 if (inst.operands[i].immisreg)
7017 inst.instruction |= SHIFT_BY_REG;
7018 inst.instruction |= inst.operands[i].imm << 8;
7021 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7026 encode_arm_shifter_operand (int i)
7028 if (inst.operands[i].isreg)
7030 inst.instruction |= inst.operands[i].reg;
7031 encode_arm_shift (i);
7035 inst.instruction |= INST_IMMEDIATE;
7036 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7037 inst.instruction |= inst.operands[i].imm;
7041 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7043 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7046 Generate an error if the operand is not a register. */
7047 constraint (!inst.operands[i].isreg,
7048 _("Instruction does not support =N addresses"));
7050 inst.instruction |= inst.operands[i].reg << 16;
7052 if (inst.operands[i].preind)
7056 inst.error = _("instruction does not accept preindexed addressing");
7059 inst.instruction |= PRE_INDEX;
7060 if (inst.operands[i].writeback)
7061 inst.instruction |= WRITE_BACK;
7064 else if (inst.operands[i].postind)
7066 gas_assert (inst.operands[i].writeback);
7068 inst.instruction |= WRITE_BACK;
7070 else /* unindexed - only for coprocessor */
7072 inst.error = _("instruction does not accept unindexed addressing");
7076 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7077 && (((inst.instruction & 0x000f0000) >> 16)
7078 == ((inst.instruction & 0x0000f000) >> 12)))
7079 as_warn ((inst.instruction & LOAD_BIT)
7080 ? _("destination register same as write-back base")
7081 : _("source register same as write-back base"));
7084 /* inst.operands[i] was set up by parse_address. Encode it into an
7085 ARM-format mode 2 load or store instruction. If is_t is true,
7086 reject forms that cannot be used with a T instruction (i.e. not
7089 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7091 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7093 encode_arm_addr_mode_common (i, is_t);
7095 if (inst.operands[i].immisreg)
7097 constraint ((inst.operands[i].imm == REG_PC
7098 || (is_pc && inst.operands[i].writeback)),
7100 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7101 inst.instruction |= inst.operands[i].imm;
7102 if (!inst.operands[i].negative)
7103 inst.instruction |= INDEX_UP;
7104 if (inst.operands[i].shifted)
7106 if (inst.operands[i].shift_kind == SHIFT_RRX)
7107 inst.instruction |= SHIFT_ROR << 5;
7110 inst.instruction |= inst.operands[i].shift_kind << 5;
7111 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7115 else /* immediate offset in inst.reloc */
7117 if (is_pc && !inst.reloc.pc_rel)
7119 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7121 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7122 cannot use PC in addressing.
7123 PC cannot be used in writeback addressing, either. */
7124 constraint ((is_t || inst.operands[i].writeback),
7127 /* Use of PC in str is deprecated for ARMv7. */
7128 if (warn_on_deprecated
7130 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7131 as_warn (_("use of PC in this instruction is deprecated"));
7134 if (inst.reloc.type == BFD_RELOC_UNUSED)
7136 /* Prefer + for zero encoded value. */
7137 if (!inst.operands[i].negative)
7138 inst.instruction |= INDEX_UP;
7139 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7144 /* inst.operands[i] was set up by parse_address. Encode it into an
7145 ARM-format mode 3 load or store instruction. Reject forms that
7146 cannot be used with such instructions. If is_t is true, reject
7147 forms that cannot be used with a T instruction (i.e. not
7150 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7152 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7154 inst.error = _("instruction does not accept scaled register index");
7158 encode_arm_addr_mode_common (i, is_t);
7160 if (inst.operands[i].immisreg)
7162 constraint ((inst.operands[i].imm == REG_PC
7163 || inst.operands[i].reg == REG_PC),
7165 inst.instruction |= inst.operands[i].imm;
7166 if (!inst.operands[i].negative)
7167 inst.instruction |= INDEX_UP;
7169 else /* immediate offset in inst.reloc */
7171 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7172 && inst.operands[i].writeback),
7174 inst.instruction |= HWOFFSET_IMM;
7175 if (inst.reloc.type == BFD_RELOC_UNUSED)
7177 /* Prefer + for zero encoded value. */
7178 if (!inst.operands[i].negative)
7179 inst.instruction |= INDEX_UP;
7181 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7186 /* inst.operands[i] was set up by parse_address. Encode it into an
7187 ARM-format instruction. Reject all forms which cannot be encoded
7188 into a coprocessor load/store instruction. If wb_ok is false,
7189 reject use of writeback; if unind_ok is false, reject use of
7190 unindexed addressing. If reloc_override is not 0, use it instead
7191 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7192 (in which case it is preserved). */
7195 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7197 inst.instruction |= inst.operands[i].reg << 16;
7199 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7201 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7203 gas_assert (!inst.operands[i].writeback);
7206 inst.error = _("instruction does not support unindexed addressing");
7209 inst.instruction |= inst.operands[i].imm;
7210 inst.instruction |= INDEX_UP;
7214 if (inst.operands[i].preind)
7215 inst.instruction |= PRE_INDEX;
7217 if (inst.operands[i].writeback)
7219 if (inst.operands[i].reg == REG_PC)
7221 inst.error = _("pc may not be used with write-back");
7226 inst.error = _("instruction does not support writeback");
7229 inst.instruction |= WRITE_BACK;
7233 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7234 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7235 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7236 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7239 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7241 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7244 /* Prefer + for zero encoded value. */
7245 if (!inst.operands[i].negative)
7246 inst.instruction |= INDEX_UP;
7251 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7252 Determine whether it can be performed with a move instruction; if
7253 it can, convert inst.instruction to that move instruction and
7254 return TRUE; if it can't, convert inst.instruction to a literal-pool
7255 load and return FALSE. If this is not a valid thing to do in the
7256 current context, set inst.error and return TRUE.
7258 inst.operands[i] describes the destination register. */
7261 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7266 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7270 if ((inst.instruction & tbit) == 0)
7272 inst.error = _("invalid pseudo operation");
7275 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7277 inst.error = _("constant expression expected");
7280 if (inst.reloc.exp.X_op == O_constant)
7284 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7286 /* This can be done with a mov(1) instruction. */
7287 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7288 inst.instruction |= inst.reloc.exp.X_add_number;
7294 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7297 /* This can be done with a mov instruction. */
7298 inst.instruction &= LITERAL_MASK;
7299 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7300 inst.instruction |= value & 0xfff;
7304 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7307 /* This can be done with a mvn instruction. */
7308 inst.instruction &= LITERAL_MASK;
7309 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7310 inst.instruction |= value & 0xfff;
7316 if (add_to_lit_pool () == FAIL)
7318 inst.error = _("literal pool insertion failed");
7321 inst.operands[1].reg = REG_PC;
7322 inst.operands[1].isreg = 1;
7323 inst.operands[1].preind = 1;
7324 inst.reloc.pc_rel = 1;
7325 inst.reloc.type = (thumb_p
7326 ? BFD_RELOC_ARM_THUMB_OFFSET
7328 ? BFD_RELOC_ARM_HWLITERAL
7329 : BFD_RELOC_ARM_LITERAL));
7333 /* Functions for instruction encoding, sorted by sub-architecture.
7334 First some generics; their names are taken from the conventional
7335 bit positions for register arguments in ARM format instructions. */
7345 inst.instruction |= inst.operands[0].reg << 12;
7351 inst.instruction |= inst.operands[0].reg << 12;
7352 inst.instruction |= inst.operands[1].reg;
7358 inst.instruction |= inst.operands[0].reg << 12;
7359 inst.instruction |= inst.operands[1].reg << 16;
7365 inst.instruction |= inst.operands[0].reg << 16;
7366 inst.instruction |= inst.operands[1].reg << 12;
7372 unsigned Rn = inst.operands[2].reg;
7373 /* Enforce restrictions on SWP instruction. */
7374 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7376 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7377 _("Rn must not overlap other operands"));
7379 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7380 if (warn_on_deprecated
7381 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7382 as_warn (_("swp{b} use is deprecated for this architecture"));
7385 inst.instruction |= inst.operands[0].reg << 12;
7386 inst.instruction |= inst.operands[1].reg;
7387 inst.instruction |= Rn << 16;
7393 inst.instruction |= inst.operands[0].reg << 12;
7394 inst.instruction |= inst.operands[1].reg << 16;
7395 inst.instruction |= inst.operands[2].reg;
7401 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7402 constraint (((inst.reloc.exp.X_op != O_constant
7403 && inst.reloc.exp.X_op != O_illegal)
7404 || inst.reloc.exp.X_add_number != 0),
7406 inst.instruction |= inst.operands[0].reg;
7407 inst.instruction |= inst.operands[1].reg << 12;
7408 inst.instruction |= inst.operands[2].reg << 16;
7414 inst.instruction |= inst.operands[0].imm;
7420 inst.instruction |= inst.operands[0].reg << 12;
7421 encode_arm_cp_address (1, TRUE, TRUE, 0);
7424 /* ARM instructions, in alphabetical order by function name (except
7425 that wrapper functions appear immediately after the function they
7428 /* This is a pseudo-op of the form "adr rd, label" to be converted
7429 into a relative address of the form "add rd, pc, #label-.-8". */
7434 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7436 /* Frag hacking will turn this into a sub instruction if the offset turns
7437 out to be negative. */
7438 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7439 inst.reloc.pc_rel = 1;
7440 inst.reloc.exp.X_add_number -= 8;
7443 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7444 into a relative address of the form:
7445 add rd, pc, #low(label-.-8)"
7446 add rd, rd, #high(label-.-8)" */
7451 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7453 /* Frag hacking will turn this into a sub instruction if the offset turns
7454 out to be negative. */
7455 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7456 inst.reloc.pc_rel = 1;
7457 inst.size = INSN_SIZE * 2;
7458 inst.reloc.exp.X_add_number -= 8;
7464 if (!inst.operands[1].present)
7465 inst.operands[1].reg = inst.operands[0].reg;
7466 inst.instruction |= inst.operands[0].reg << 12;
7467 inst.instruction |= inst.operands[1].reg << 16;
7468 encode_arm_shifter_operand (2);
7474 if (inst.operands[0].present)
7476 constraint ((inst.instruction & 0xf0) != 0x40
7477 && inst.operands[0].imm > 0xf
7478 && inst.operands[0].imm < 0x0,
7479 _("bad barrier type"));
7480 inst.instruction |= inst.operands[0].imm;
7483 inst.instruction |= 0xf;
7489 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7490 constraint (msb > 32, _("bit-field extends past end of register"));
7491 /* The instruction encoding stores the LSB and MSB,
7492 not the LSB and width. */
7493 inst.instruction |= inst.operands[0].reg << 12;
7494 inst.instruction |= inst.operands[1].imm << 7;
7495 inst.instruction |= (msb - 1) << 16;
7503 /* #0 in second position is alternative syntax for bfc, which is
7504 the same instruction but with REG_PC in the Rm field. */
7505 if (!inst.operands[1].isreg)
7506 inst.operands[1].reg = REG_PC;
7508 msb = inst.operands[2].imm + inst.operands[3].imm;
7509 constraint (msb > 32, _("bit-field extends past end of register"));
7510 /* The instruction encoding stores the LSB and MSB,
7511 not the LSB and width. */
7512 inst.instruction |= inst.operands[0].reg << 12;
7513 inst.instruction |= inst.operands[1].reg;
7514 inst.instruction |= inst.operands[2].imm << 7;
7515 inst.instruction |= (msb - 1) << 16;
7521 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7522 _("bit-field extends past end of register"));
7523 inst.instruction |= inst.operands[0].reg << 12;
7524 inst.instruction |= inst.operands[1].reg;
7525 inst.instruction |= inst.operands[2].imm << 7;
7526 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7529 /* ARM V5 breakpoint instruction (argument parse)
7530 BKPT <16 bit unsigned immediate>
7531 Instruction is not conditional.
7532 The bit pattern given in insns[] has the COND_ALWAYS condition,
7533 and it is an error if the caller tried to override that. */
7538 /* Top 12 of 16 bits to bits 19:8. */
7539 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7541 /* Bottom 4 of 16 bits to bits 3:0. */
7542 inst.instruction |= inst.operands[0].imm & 0xf;
7546 encode_branch (int default_reloc)
7548 if (inst.operands[0].hasreloc)
7550 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7551 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7552 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7553 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7554 ? BFD_RELOC_ARM_PLT32
7555 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7558 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7559 inst.reloc.pc_rel = 1;
7566 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7567 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7570 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7577 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7579 if (inst.cond == COND_ALWAYS)
7580 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7582 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7586 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7589 /* ARM V5 branch-link-exchange instruction (argument parse)
7590 BLX <target_addr> ie BLX(1)
7591 BLX{<condition>} <Rm> ie BLX(2)
7592 Unfortunately, there are two different opcodes for this mnemonic.
7593 So, the insns[].value is not used, and the code here zaps values
7594 into inst.instruction.
7595 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7600 if (inst.operands[0].isreg)
7602 /* Arg is a register; the opcode provided by insns[] is correct.
7603 It is not illegal to do "blx pc", just useless. */
7604 if (inst.operands[0].reg == REG_PC)
7605 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7607 inst.instruction |= inst.operands[0].reg;
7611 /* Arg is an address; this instruction cannot be executed
7612 conditionally, and the opcode must be adjusted.
7613 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7614 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7615 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7616 inst.instruction = 0xfa000000;
7617 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7624 bfd_boolean want_reloc;
7626 if (inst.operands[0].reg == REG_PC)
7627 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7629 inst.instruction |= inst.operands[0].reg;
7630 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7631 it is for ARMv4t or earlier. */
7632 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7633 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7637 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7642 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7646 /* ARM v5TEJ. Jump to Jazelle code. */
7651 if (inst.operands[0].reg == REG_PC)
7652 as_tsktsk (_("use of r15 in bxj is not really useful"));
7654 inst.instruction |= inst.operands[0].reg;
7657 /* Co-processor data operation:
7658 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7659 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7663 inst.instruction |= inst.operands[0].reg << 8;
7664 inst.instruction |= inst.operands[1].imm << 20;
7665 inst.instruction |= inst.operands[2].reg << 12;
7666 inst.instruction |= inst.operands[3].reg << 16;
7667 inst.instruction |= inst.operands[4].reg;
7668 inst.instruction |= inst.operands[5].imm << 5;
7674 inst.instruction |= inst.operands[0].reg << 16;
7675 encode_arm_shifter_operand (1);
7678 /* Transfer between coprocessor and ARM registers.
7679 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7684 No special properties. */
7691 Rd = inst.operands[2].reg;
7694 if (inst.instruction == 0xee000010
7695 || inst.instruction == 0xfe000010)
7697 reject_bad_reg (Rd);
7700 constraint (Rd == REG_SP, BAD_SP);
7705 if (inst.instruction == 0xe000010)
7706 constraint (Rd == REG_PC, BAD_PC);
7710 inst.instruction |= inst.operands[0].reg << 8;
7711 inst.instruction |= inst.operands[1].imm << 21;
7712 inst.instruction |= Rd << 12;
7713 inst.instruction |= inst.operands[3].reg << 16;
7714 inst.instruction |= inst.operands[4].reg;
7715 inst.instruction |= inst.operands[5].imm << 5;
7718 /* Transfer between coprocessor register and pair of ARM registers.
7719 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7724 Two XScale instructions are special cases of these:
7726 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7727 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7729 Result unpredictable if Rd or Rn is R15. */
7736 Rd = inst.operands[2].reg;
7737 Rn = inst.operands[3].reg;
7741 reject_bad_reg (Rd);
7742 reject_bad_reg (Rn);
7746 constraint (Rd == REG_PC, BAD_PC);
7747 constraint (Rn == REG_PC, BAD_PC);
7750 inst.instruction |= inst.operands[0].reg << 8;
7751 inst.instruction |= inst.operands[1].imm << 4;
7752 inst.instruction |= Rd << 12;
7753 inst.instruction |= Rn << 16;
7754 inst.instruction |= inst.operands[4].reg;
7760 inst.instruction |= inst.operands[0].imm << 6;
7761 if (inst.operands[1].present)
7763 inst.instruction |= CPSI_MMOD;
7764 inst.instruction |= inst.operands[1].imm;
7771 inst.instruction |= inst.operands[0].imm;
7777 unsigned Rd, Rn, Rm;
7779 Rd = inst.operands[0].reg;
7780 Rn = (inst.operands[1].present
7781 ? inst.operands[1].reg : Rd);
7782 Rm = inst.operands[2].reg;
7784 constraint ((Rd == REG_PC), BAD_PC);
7785 constraint ((Rn == REG_PC), BAD_PC);
7786 constraint ((Rm == REG_PC), BAD_PC);
7788 inst.instruction |= Rd << 16;
7789 inst.instruction |= Rn << 0;
7790 inst.instruction |= Rm << 8;
7796 /* There is no IT instruction in ARM mode. We
7797 process it to do the validation as if in
7798 thumb mode, just in case the code gets
7799 assembled for thumb using the unified syntax. */
7804 set_it_insn_type (IT_INSN);
7805 now_it.mask = (inst.instruction & 0xf) | 0x10;
7806 now_it.cc = inst.operands[0].imm;
7810 /* If there is only one register in the register list,
7811 then return its register number. Otherwise return -1. */
7813 only_one_reg_in_list (int range)
7815 int i = ffs (range) - 1;
7816 return (i > 15 || range != (1 << i)) ? -1 : i;
7820 encode_ldmstm(int from_push_pop_mnem)
7822 int base_reg = inst.operands[0].reg;
7823 int range = inst.operands[1].imm;
7826 inst.instruction |= base_reg << 16;
7827 inst.instruction |= range;
7829 if (inst.operands[1].writeback)
7830 inst.instruction |= LDM_TYPE_2_OR_3;
7832 if (inst.operands[0].writeback)
7834 inst.instruction |= WRITE_BACK;
7835 /* Check for unpredictable uses of writeback. */
7836 if (inst.instruction & LOAD_BIT)
7838 /* Not allowed in LDM type 2. */
7839 if ((inst.instruction & LDM_TYPE_2_OR_3)
7840 && ((range & (1 << REG_PC)) == 0))
7841 as_warn (_("writeback of base register is UNPREDICTABLE"));
7842 /* Only allowed if base reg not in list for other types. */
7843 else if (range & (1 << base_reg))
7844 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7848 /* Not allowed for type 2. */
7849 if (inst.instruction & LDM_TYPE_2_OR_3)
7850 as_warn (_("writeback of base register is UNPREDICTABLE"));
7851 /* Only allowed if base reg not in list, or first in list. */
7852 else if ((range & (1 << base_reg))
7853 && (range & ((1 << base_reg) - 1)))
7854 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7858 /* If PUSH/POP has only one register, then use the A2 encoding. */
7859 one_reg = only_one_reg_in_list (range);
7860 if (from_push_pop_mnem && one_reg >= 0)
7862 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7864 inst.instruction &= A_COND_MASK;
7865 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7866 inst.instruction |= one_reg << 12;
7873 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7876 /* ARMv5TE load-consecutive (argument parse)
7885 constraint (inst.operands[0].reg % 2 != 0,
7886 _("first transfer register must be even"));
7887 constraint (inst.operands[1].present
7888 && inst.operands[1].reg != inst.operands[0].reg + 1,
7889 _("can only transfer two consecutive registers"));
7890 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7891 constraint (!inst.operands[2].isreg, _("'[' expected"));
7893 if (!inst.operands[1].present)
7894 inst.operands[1].reg = inst.operands[0].reg + 1;
7896 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7897 register and the first register written; we have to diagnose
7898 overlap between the base and the second register written here. */
7900 if (inst.operands[2].reg == inst.operands[1].reg
7901 && (inst.operands[2].writeback || inst.operands[2].postind))
7902 as_warn (_("base register written back, and overlaps "
7903 "second transfer register"));
7905 if (!(inst.instruction & V4_STR_BIT))
7907 /* For an index-register load, the index register must not overlap the
7908 destination (even if not write-back). */
7909 if (inst.operands[2].immisreg
7910 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7911 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7912 as_warn (_("index register overlaps transfer register"));
7914 inst.instruction |= inst.operands[0].reg << 12;
7915 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7921 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7922 || inst.operands[1].postind || inst.operands[1].writeback
7923 || inst.operands[1].immisreg || inst.operands[1].shifted
7924 || inst.operands[1].negative
7925 /* This can arise if the programmer has written
7927 or if they have mistakenly used a register name as the last
7930 It is very difficult to distinguish between these two cases
7931 because "rX" might actually be a label. ie the register
7932 name has been occluded by a symbol of the same name. So we
7933 just generate a general 'bad addressing mode' type error
7934 message and leave it up to the programmer to discover the
7935 true cause and fix their mistake. */
7936 || (inst.operands[1].reg == REG_PC),
7939 constraint (inst.reloc.exp.X_op != O_constant
7940 || inst.reloc.exp.X_add_number != 0,
7941 _("offset must be zero in ARM encoding"));
7943 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7945 inst.instruction |= inst.operands[0].reg << 12;
7946 inst.instruction |= inst.operands[1].reg << 16;
7947 inst.reloc.type = BFD_RELOC_UNUSED;
7953 constraint (inst.operands[0].reg % 2 != 0,
7954 _("even register required"));
7955 constraint (inst.operands[1].present
7956 && inst.operands[1].reg != inst.operands[0].reg + 1,
7957 _("can only load two consecutive registers"));
7958 /* If op 1 were present and equal to PC, this function wouldn't
7959 have been called in the first place. */
7960 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7962 inst.instruction |= inst.operands[0].reg << 12;
7963 inst.instruction |= inst.operands[2].reg << 16;
7966 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7967 which is not a multiple of four is UNPREDICTABLE. */
7969 check_ldr_r15_aligned (void)
7971 constraint (!(inst.operands[1].immisreg)
7972 && (inst.operands[0].reg == REG_PC
7973 && inst.operands[1].reg == REG_PC
7974 && (inst.reloc.exp.X_add_number & 0x3)),
7975 _("ldr to register 15 must be 4-byte alligned"));
7981 inst.instruction |= inst.operands[0].reg << 12;
7982 if (!inst.operands[1].isreg)
7983 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7985 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7986 check_ldr_r15_aligned ();
7992 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7994 if (inst.operands[1].preind)
7996 constraint (inst.reloc.exp.X_op != O_constant
7997 || inst.reloc.exp.X_add_number != 0,
7998 _("this instruction requires a post-indexed address"));
8000 inst.operands[1].preind = 0;
8001 inst.operands[1].postind = 1;
8002 inst.operands[1].writeback = 1;
8004 inst.instruction |= inst.operands[0].reg << 12;
8005 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8008 /* Halfword and signed-byte load/store operations. */
8013 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8014 inst.instruction |= inst.operands[0].reg << 12;
8015 if (!inst.operands[1].isreg)
8016 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8018 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8024 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8026 if (inst.operands[1].preind)
8028 constraint (inst.reloc.exp.X_op != O_constant
8029 || inst.reloc.exp.X_add_number != 0,
8030 _("this instruction requires a post-indexed address"));
8032 inst.operands[1].preind = 0;
8033 inst.operands[1].postind = 1;
8034 inst.operands[1].writeback = 1;
8036 inst.instruction |= inst.operands[0].reg << 12;
8037 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8040 /* Co-processor register load/store.
8041 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8045 inst.instruction |= inst.operands[0].reg << 8;
8046 inst.instruction |= inst.operands[1].reg << 12;
8047 encode_arm_cp_address (2, TRUE, TRUE, 0);
8053 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8054 if (inst.operands[0].reg == inst.operands[1].reg
8055 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8056 && !(inst.instruction & 0x00400000))
8057 as_tsktsk (_("Rd and Rm should be different in mla"));
8059 inst.instruction |= inst.operands[0].reg << 16;
8060 inst.instruction |= inst.operands[1].reg;
8061 inst.instruction |= inst.operands[2].reg << 8;
8062 inst.instruction |= inst.operands[3].reg << 12;
8068 inst.instruction |= inst.operands[0].reg << 12;
8069 encode_arm_shifter_operand (1);
8072 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8079 top = (inst.instruction & 0x00400000) != 0;
8080 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8081 _(":lower16: not allowed this instruction"));
8082 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8083 _(":upper16: not allowed instruction"));
8084 inst.instruction |= inst.operands[0].reg << 12;
8085 if (inst.reloc.type == BFD_RELOC_UNUSED)
8087 imm = inst.reloc.exp.X_add_number;
8088 /* The value is in two pieces: 0:11, 16:19. */
8089 inst.instruction |= (imm & 0x00000fff);
8090 inst.instruction |= (imm & 0x0000f000) << 4;
8094 static void do_vfp_nsyn_opcode (const char *);
8097 do_vfp_nsyn_mrs (void)
8099 if (inst.operands[0].isvec)
8101 if (inst.operands[1].reg != 1)
8102 first_error (_("operand 1 must be FPSCR"));
8103 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8104 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8105 do_vfp_nsyn_opcode ("fmstat");
8107 else if (inst.operands[1].isvec)
8108 do_vfp_nsyn_opcode ("fmrx");
8116 do_vfp_nsyn_msr (void)
8118 if (inst.operands[0].isvec)
8119 do_vfp_nsyn_opcode ("fmxr");
8129 unsigned Rt = inst.operands[0].reg;
8131 if (thumb_mode && inst.operands[0].reg == REG_SP)
8133 inst.error = BAD_SP;
8137 /* APSR_ sets isvec. All other refs to PC are illegal. */
8138 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8140 inst.error = BAD_PC;
8144 switch (inst.operands[1].reg)
8151 inst.instruction |= (inst.operands[1].reg << 16);
8154 first_error (_("operand 1 must be a VFP extension System Register"));
8157 inst.instruction |= (Rt << 12);
8163 unsigned Rt = inst.operands[1].reg;
8166 reject_bad_reg (Rt);
8167 else if (Rt == REG_PC)
8169 inst.error = BAD_PC;
8173 switch (inst.operands[0].reg)
8178 inst.instruction |= (inst.operands[0].reg << 16);
8181 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8184 inst.instruction |= (Rt << 12);
8192 if (do_vfp_nsyn_mrs () == SUCCESS)
8195 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8196 inst.instruction |= inst.operands[0].reg << 12;
8198 if (inst.operands[1].isreg)
8200 br = inst.operands[1].reg;
8201 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8202 as_bad (_("bad register for mrs"));
8206 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8207 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8209 _("'APSR', 'CPSR' or 'SPSR' expected"));
8210 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8213 inst.instruction |= br;
8216 /* Two possible forms:
8217 "{C|S}PSR_<field>, Rm",
8218 "{C|S}PSR_f, #expression". */
8223 if (do_vfp_nsyn_msr () == SUCCESS)
8226 inst.instruction |= inst.operands[0].imm;
8227 if (inst.operands[1].isreg)
8228 inst.instruction |= inst.operands[1].reg;
8231 inst.instruction |= INST_IMMEDIATE;
8232 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8233 inst.reloc.pc_rel = 0;
8240 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8242 if (!inst.operands[2].present)
8243 inst.operands[2].reg = inst.operands[0].reg;
8244 inst.instruction |= inst.operands[0].reg << 16;
8245 inst.instruction |= inst.operands[1].reg;
8246 inst.instruction |= inst.operands[2].reg << 8;
8248 if (inst.operands[0].reg == inst.operands[1].reg
8249 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8250 as_tsktsk (_("Rd and Rm should be different in mul"));
8253 /* Long Multiply Parser
8254 UMULL RdLo, RdHi, Rm, Rs
8255 SMULL RdLo, RdHi, Rm, Rs
8256 UMLAL RdLo, RdHi, Rm, Rs
8257 SMLAL RdLo, RdHi, Rm, Rs. */
8262 inst.instruction |= inst.operands[0].reg << 12;
8263 inst.instruction |= inst.operands[1].reg << 16;
8264 inst.instruction |= inst.operands[2].reg;
8265 inst.instruction |= inst.operands[3].reg << 8;
8267 /* rdhi and rdlo must be different. */
8268 if (inst.operands[0].reg == inst.operands[1].reg)
8269 as_tsktsk (_("rdhi and rdlo must be different"));
8271 /* rdhi, rdlo and rm must all be different before armv6. */
8272 if ((inst.operands[0].reg == inst.operands[2].reg
8273 || inst.operands[1].reg == inst.operands[2].reg)
8274 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8275 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8281 if (inst.operands[0].present
8282 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8284 /* Architectural NOP hints are CPSR sets with no bits selected. */
8285 inst.instruction &= 0xf0000000;
8286 inst.instruction |= 0x0320f000;
8287 if (inst.operands[0].present)
8288 inst.instruction |= inst.operands[0].imm;
8292 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8293 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8294 Condition defaults to COND_ALWAYS.
8295 Error if Rd, Rn or Rm are R15. */
8300 inst.instruction |= inst.operands[0].reg << 12;
8301 inst.instruction |= inst.operands[1].reg << 16;
8302 inst.instruction |= inst.operands[2].reg;
8303 if (inst.operands[3].present)
8304 encode_arm_shift (3);
8307 /* ARM V6 PKHTB (Argument Parse). */
8312 if (!inst.operands[3].present)
8314 /* If the shift specifier is omitted, turn the instruction
8315 into pkhbt rd, rm, rn. */
8316 inst.instruction &= 0xfff00010;
8317 inst.instruction |= inst.operands[0].reg << 12;
8318 inst.instruction |= inst.operands[1].reg;
8319 inst.instruction |= inst.operands[2].reg << 16;
8323 inst.instruction |= inst.operands[0].reg << 12;
8324 inst.instruction |= inst.operands[1].reg << 16;
8325 inst.instruction |= inst.operands[2].reg;
8326 encode_arm_shift (3);
8330 /* ARMv5TE: Preload-Cache
8331 MP Extensions: Preload for write
8335 Syntactically, like LDR with B=1, W=0, L=1. */
8340 constraint (!inst.operands[0].isreg,
8341 _("'[' expected after PLD mnemonic"));
8342 constraint (inst.operands[0].postind,
8343 _("post-indexed expression used in preload instruction"));
8344 constraint (inst.operands[0].writeback,
8345 _("writeback used in preload instruction"));
8346 constraint (!inst.operands[0].preind,
8347 _("unindexed addressing used in preload instruction"));
8348 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8351 /* ARMv7: PLI <addr_mode> */
8355 constraint (!inst.operands[0].isreg,
8356 _("'[' expected after PLI mnemonic"));
8357 constraint (inst.operands[0].postind,
8358 _("post-indexed expression used in preload instruction"));
8359 constraint (inst.operands[0].writeback,
8360 _("writeback used in preload instruction"));
8361 constraint (!inst.operands[0].preind,
8362 _("unindexed addressing used in preload instruction"));
8363 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8364 inst.instruction &= ~PRE_INDEX;
8370 inst.operands[1] = inst.operands[0];
8371 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8372 inst.operands[0].isreg = 1;
8373 inst.operands[0].writeback = 1;
8374 inst.operands[0].reg = REG_SP;
8375 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8378 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8379 word at the specified address and the following word
8381 Unconditionally executed.
8382 Error if Rn is R15. */
8387 inst.instruction |= inst.operands[0].reg << 16;
8388 if (inst.operands[0].writeback)
8389 inst.instruction |= WRITE_BACK;
8392 /* ARM V6 ssat (argument parse). */
8397 inst.instruction |= inst.operands[0].reg << 12;
8398 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8399 inst.instruction |= inst.operands[2].reg;
8401 if (inst.operands[3].present)
8402 encode_arm_shift (3);
8405 /* ARM V6 usat (argument parse). */
8410 inst.instruction |= inst.operands[0].reg << 12;
8411 inst.instruction |= inst.operands[1].imm << 16;
8412 inst.instruction |= inst.operands[2].reg;
8414 if (inst.operands[3].present)
8415 encode_arm_shift (3);
8418 /* ARM V6 ssat16 (argument parse). */
8423 inst.instruction |= inst.operands[0].reg << 12;
8424 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8425 inst.instruction |= inst.operands[2].reg;
8431 inst.instruction |= inst.operands[0].reg << 12;
8432 inst.instruction |= inst.operands[1].imm << 16;
8433 inst.instruction |= inst.operands[2].reg;
8436 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8437 preserving the other bits.
8439 setend <endian_specifier>, where <endian_specifier> is either
8445 if (inst.operands[0].imm)
8446 inst.instruction |= 0x200;
8452 unsigned int Rm = (inst.operands[1].present
8453 ? inst.operands[1].reg
8454 : inst.operands[0].reg);
8456 inst.instruction |= inst.operands[0].reg << 12;
8457 inst.instruction |= Rm;
8458 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8460 inst.instruction |= inst.operands[2].reg << 8;
8461 inst.instruction |= SHIFT_BY_REG;
8462 /* PR 12854: Error on extraneous shifts. */
8463 constraint (inst.operands[2].shifted,
8464 _("extraneous shift as part of operand to shift insn"));
8467 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8473 inst.reloc.type = BFD_RELOC_ARM_SMC;
8474 inst.reloc.pc_rel = 0;
8480 inst.reloc.type = BFD_RELOC_ARM_HVC;
8481 inst.reloc.pc_rel = 0;
8487 inst.reloc.type = BFD_RELOC_ARM_SWI;
8488 inst.reloc.pc_rel = 0;
8491 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8492 SMLAxy{cond} Rd,Rm,Rs,Rn
8493 SMLAWy{cond} Rd,Rm,Rs,Rn
8494 Error if any register is R15. */
8499 inst.instruction |= inst.operands[0].reg << 16;
8500 inst.instruction |= inst.operands[1].reg;
8501 inst.instruction |= inst.operands[2].reg << 8;
8502 inst.instruction |= inst.operands[3].reg << 12;
8505 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8506 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8507 Error if any register is R15.
8508 Warning if Rdlo == Rdhi. */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= inst.operands[1].reg << 16;
8515 inst.instruction |= inst.operands[2].reg;
8516 inst.instruction |= inst.operands[3].reg << 8;
8518 if (inst.operands[0].reg == inst.operands[1].reg)
8519 as_tsktsk (_("rdhi and rdlo must be different"));
8522 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8523 SMULxy{cond} Rd,Rm,Rs
8524 Error if any register is R15. */
8529 inst.instruction |= inst.operands[0].reg << 16;
8530 inst.instruction |= inst.operands[1].reg;
8531 inst.instruction |= inst.operands[2].reg << 8;
8534 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8535 the same for both ARM and Thumb-2. */
8542 if (inst.operands[0].present)
8544 reg = inst.operands[0].reg;
8545 constraint (reg != REG_SP, _("SRS base register must be r13"));
8550 inst.instruction |= reg << 16;
8551 inst.instruction |= inst.operands[1].imm;
8552 if (inst.operands[0].writeback || inst.operands[1].writeback)
8553 inst.instruction |= WRITE_BACK;
8556 /* ARM V6 strex (argument parse). */
8561 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8562 || inst.operands[2].postind || inst.operands[2].writeback
8563 || inst.operands[2].immisreg || inst.operands[2].shifted
8564 || inst.operands[2].negative
8565 /* See comment in do_ldrex(). */
8566 || (inst.operands[2].reg == REG_PC),
8569 constraint (inst.operands[0].reg == inst.operands[1].reg
8570 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8572 constraint (inst.reloc.exp.X_op != O_constant
8573 || inst.reloc.exp.X_add_number != 0,
8574 _("offset must be zero in ARM encoding"));
8576 inst.instruction |= inst.operands[0].reg << 12;
8577 inst.instruction |= inst.operands[1].reg;
8578 inst.instruction |= inst.operands[2].reg << 16;
8579 inst.reloc.type = BFD_RELOC_UNUSED;
8585 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8586 || inst.operands[2].postind || inst.operands[2].writeback
8587 || inst.operands[2].immisreg || inst.operands[2].shifted
8588 || inst.operands[2].negative,
8591 constraint (inst.operands[0].reg == inst.operands[1].reg
8592 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8600 constraint (inst.operands[1].reg % 2 != 0,
8601 _("even register required"));
8602 constraint (inst.operands[2].present
8603 && inst.operands[2].reg != inst.operands[1].reg + 1,
8604 _("can only store two consecutive registers"));
8605 /* If op 2 were present and equal to PC, this function wouldn't
8606 have been called in the first place. */
8607 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8609 constraint (inst.operands[0].reg == inst.operands[1].reg
8610 || inst.operands[0].reg == inst.operands[1].reg + 1
8611 || inst.operands[0].reg == inst.operands[3].reg,
8614 inst.instruction |= inst.operands[0].reg << 12;
8615 inst.instruction |= inst.operands[1].reg;
8616 inst.instruction |= inst.operands[3].reg << 16;
8619 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8620 extends it to 32-bits, and adds the result to a value in another
8621 register. You can specify a rotation by 0, 8, 16, or 24 bits
8622 before extracting the 16-bit value.
8623 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8624 Condition defaults to COND_ALWAYS.
8625 Error if any register uses R15. */
8630 inst.instruction |= inst.operands[0].reg << 12;
8631 inst.instruction |= inst.operands[1].reg << 16;
8632 inst.instruction |= inst.operands[2].reg;
8633 inst.instruction |= inst.operands[3].imm << 10;
8638 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8639 Condition defaults to COND_ALWAYS.
8640 Error if any register uses R15. */
8645 inst.instruction |= inst.operands[0].reg << 12;
8646 inst.instruction |= inst.operands[1].reg;
8647 inst.instruction |= inst.operands[2].imm << 10;
8650 /* VFP instructions. In a logical order: SP variant first, monad
8651 before dyad, arithmetic then move then load/store. */
8654 do_vfp_sp_monadic (void)
8656 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8657 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8661 do_vfp_sp_dyadic (void)
8663 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8664 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8665 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8669 do_vfp_sp_compare_z (void)
8671 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8675 do_vfp_dp_sp_cvt (void)
8677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8678 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8682 do_vfp_sp_dp_cvt (void)
8684 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8685 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8689 do_vfp_reg_from_sp (void)
8691 inst.instruction |= inst.operands[0].reg << 12;
8692 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8696 do_vfp_reg2_from_sp2 (void)
8698 constraint (inst.operands[2].imm != 2,
8699 _("only two consecutive VFP SP registers allowed here"));
8700 inst.instruction |= inst.operands[0].reg << 12;
8701 inst.instruction |= inst.operands[1].reg << 16;
8702 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8706 do_vfp_sp_from_reg (void)
8708 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8709 inst.instruction |= inst.operands[1].reg << 12;
8713 do_vfp_sp2_from_reg2 (void)
8715 constraint (inst.operands[0].imm != 2,
8716 _("only two consecutive VFP SP registers allowed here"));
8717 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8718 inst.instruction |= inst.operands[1].reg << 12;
8719 inst.instruction |= inst.operands[2].reg << 16;
8723 do_vfp_sp_ldst (void)
8725 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8726 encode_arm_cp_address (1, FALSE, TRUE, 0);
8730 do_vfp_dp_ldst (void)
8732 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8733 encode_arm_cp_address (1, FALSE, TRUE, 0);
8738 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8740 if (inst.operands[0].writeback)
8741 inst.instruction |= WRITE_BACK;
8743 constraint (ldstm_type != VFP_LDSTMIA,
8744 _("this addressing mode requires base-register writeback"));
8745 inst.instruction |= inst.operands[0].reg << 16;
8746 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8747 inst.instruction |= inst.operands[1].imm;
8751 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8755 if (inst.operands[0].writeback)
8756 inst.instruction |= WRITE_BACK;
8758 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8759 _("this addressing mode requires base-register writeback"));
8761 inst.instruction |= inst.operands[0].reg << 16;
8762 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8764 count = inst.operands[1].imm << 1;
8765 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8768 inst.instruction |= count;
8772 do_vfp_sp_ldstmia (void)
8774 vfp_sp_ldstm (VFP_LDSTMIA);
8778 do_vfp_sp_ldstmdb (void)
8780 vfp_sp_ldstm (VFP_LDSTMDB);
8784 do_vfp_dp_ldstmia (void)
8786 vfp_dp_ldstm (VFP_LDSTMIA);
8790 do_vfp_dp_ldstmdb (void)
8792 vfp_dp_ldstm (VFP_LDSTMDB);
8796 do_vfp_xp_ldstmia (void)
8798 vfp_dp_ldstm (VFP_LDSTMIAX);
8802 do_vfp_xp_ldstmdb (void)
8804 vfp_dp_ldstm (VFP_LDSTMDBX);
8808 do_vfp_dp_rd_rm (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8815 do_vfp_dp_rn_rd (void)
8817 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8818 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8822 do_vfp_dp_rd_rn (void)
8824 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8825 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8829 do_vfp_dp_rd_rn_rm (void)
8831 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8832 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8833 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8839 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8843 do_vfp_dp_rm_rd_rn (void)
8845 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8846 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8847 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8850 /* VFPv3 instructions. */
8852 do_vfp_sp_const (void)
8854 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8855 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8856 inst.instruction |= (inst.operands[1].imm & 0x0f);
8860 do_vfp_dp_const (void)
8862 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8863 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8864 inst.instruction |= (inst.operands[1].imm & 0x0f);
8868 vfp_conv (int srcsize)
8870 int immbits = srcsize - inst.operands[1].imm;
8872 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8874 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8875 i.e. immbits must be in range 0 - 16. */
8876 inst.error = _("immediate value out of range, expected range [0, 16]");
8879 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8881 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8882 i.e. immbits must be in range 0 - 31. */
8883 inst.error = _("immediate value out of range, expected range [1, 32]");
8887 inst.instruction |= (immbits & 1) << 5;
8888 inst.instruction |= (immbits >> 1);
8892 do_vfp_sp_conv_16 (void)
8894 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8899 do_vfp_dp_conv_16 (void)
8901 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8906 do_vfp_sp_conv_32 (void)
8908 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8913 do_vfp_dp_conv_32 (void)
8915 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8919 /* FPA instructions. Also in a logical order. */
8924 inst.instruction |= inst.operands[0].reg << 16;
8925 inst.instruction |= inst.operands[1].reg;
8929 do_fpa_ldmstm (void)
8931 inst.instruction |= inst.operands[0].reg << 12;
8932 switch (inst.operands[1].imm)
8934 case 1: inst.instruction |= CP_T_X; break;
8935 case 2: inst.instruction |= CP_T_Y; break;
8936 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8941 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8943 /* The instruction specified "ea" or "fd", so we can only accept
8944 [Rn]{!}. The instruction does not really support stacking or
8945 unstacking, so we have to emulate these by setting appropriate
8946 bits and offsets. */
8947 constraint (inst.reloc.exp.X_op != O_constant
8948 || inst.reloc.exp.X_add_number != 0,
8949 _("this instruction does not support indexing"));
8951 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8952 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8954 if (!(inst.instruction & INDEX_UP))
8955 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8957 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8959 inst.operands[2].preind = 0;
8960 inst.operands[2].postind = 1;
8964 encode_arm_cp_address (2, TRUE, TRUE, 0);
8967 /* iWMMXt instructions: strictly in alphabetical order. */
8970 do_iwmmxt_tandorc (void)
8972 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8976 do_iwmmxt_textrc (void)
8978 inst.instruction |= inst.operands[0].reg << 12;
8979 inst.instruction |= inst.operands[1].imm;
8983 do_iwmmxt_textrm (void)
8985 inst.instruction |= inst.operands[0].reg << 12;
8986 inst.instruction |= inst.operands[1].reg << 16;
8987 inst.instruction |= inst.operands[2].imm;
8991 do_iwmmxt_tinsr (void)
8993 inst.instruction |= inst.operands[0].reg << 16;
8994 inst.instruction |= inst.operands[1].reg << 12;
8995 inst.instruction |= inst.operands[2].imm;
8999 do_iwmmxt_tmia (void)
9001 inst.instruction |= inst.operands[0].reg << 5;
9002 inst.instruction |= inst.operands[1].reg;
9003 inst.instruction |= inst.operands[2].reg << 12;
9007 do_iwmmxt_waligni (void)
9009 inst.instruction |= inst.operands[0].reg << 12;
9010 inst.instruction |= inst.operands[1].reg << 16;
9011 inst.instruction |= inst.operands[2].reg;
9012 inst.instruction |= inst.operands[3].imm << 20;
9016 do_iwmmxt_wmerge (void)
9018 inst.instruction |= inst.operands[0].reg << 12;
9019 inst.instruction |= inst.operands[1].reg << 16;
9020 inst.instruction |= inst.operands[2].reg;
9021 inst.instruction |= inst.operands[3].imm << 21;
9025 do_iwmmxt_wmov (void)
9027 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9028 inst.instruction |= inst.operands[0].reg << 12;
9029 inst.instruction |= inst.operands[1].reg << 16;
9030 inst.instruction |= inst.operands[1].reg;
9034 do_iwmmxt_wldstbh (void)
9037 inst.instruction |= inst.operands[0].reg << 12;
9039 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9041 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9042 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9046 do_iwmmxt_wldstw (void)
9048 /* RIWR_RIWC clears .isreg for a control register. */
9049 if (!inst.operands[0].isreg)
9051 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9052 inst.instruction |= 0xf0000000;
9055 inst.instruction |= inst.operands[0].reg << 12;
9056 encode_arm_cp_address (1, TRUE, TRUE, 0);
9060 do_iwmmxt_wldstd (void)
9062 inst.instruction |= inst.operands[0].reg << 12;
9063 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9064 && inst.operands[1].immisreg)
9066 inst.instruction &= ~0x1a000ff;
9067 inst.instruction |= (0xf << 28);
9068 if (inst.operands[1].preind)
9069 inst.instruction |= PRE_INDEX;
9070 if (!inst.operands[1].negative)
9071 inst.instruction |= INDEX_UP;
9072 if (inst.operands[1].writeback)
9073 inst.instruction |= WRITE_BACK;
9074 inst.instruction |= inst.operands[1].reg << 16;
9075 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9076 inst.instruction |= inst.operands[1].imm;
9079 encode_arm_cp_address (1, TRUE, FALSE, 0);
9083 do_iwmmxt_wshufh (void)
9085 inst.instruction |= inst.operands[0].reg << 12;
9086 inst.instruction |= inst.operands[1].reg << 16;
9087 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9088 inst.instruction |= (inst.operands[2].imm & 0x0f);
9092 do_iwmmxt_wzero (void)
9094 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9095 inst.instruction |= inst.operands[0].reg;
9096 inst.instruction |= inst.operands[0].reg << 12;
9097 inst.instruction |= inst.operands[0].reg << 16;
9101 do_iwmmxt_wrwrwr_or_imm5 (void)
9103 if (inst.operands[2].isreg)
9106 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9107 _("immediate operand requires iWMMXt2"));
9109 if (inst.operands[2].imm == 0)
9111 switch ((inst.instruction >> 20) & 0xf)
9117 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9118 inst.operands[2].imm = 16;
9119 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9125 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9126 inst.operands[2].imm = 32;
9127 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9134 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9136 wrn = (inst.instruction >> 16) & 0xf;
9137 inst.instruction &= 0xff0fff0f;
9138 inst.instruction |= wrn;
9139 /* Bail out here; the instruction is now assembled. */
9144 /* Map 32 -> 0, etc. */
9145 inst.operands[2].imm &= 0x1f;
9146 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9150 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9151 operations first, then control, shift, and load/store. */
9153 /* Insns like "foo X,Y,Z". */
9156 do_mav_triple (void)
9158 inst.instruction |= inst.operands[0].reg << 16;
9159 inst.instruction |= inst.operands[1].reg;
9160 inst.instruction |= inst.operands[2].reg << 12;
9163 /* Insns like "foo W,X,Y,Z".
9164 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9169 inst.instruction |= inst.operands[0].reg << 5;
9170 inst.instruction |= inst.operands[1].reg << 12;
9171 inst.instruction |= inst.operands[2].reg << 16;
9172 inst.instruction |= inst.operands[3].reg;
9175 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9179 inst.instruction |= inst.operands[1].reg << 12;
9182 /* Maverick shift immediate instructions.
9183 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9184 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9189 int imm = inst.operands[2].imm;
9191 inst.instruction |= inst.operands[0].reg << 12;
9192 inst.instruction |= inst.operands[1].reg << 16;
9194 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9195 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9196 Bit 4 should be 0. */
9197 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9199 inst.instruction |= imm;
9202 /* XScale instructions. Also sorted arithmetic before move. */
9204 /* Xscale multiply-accumulate (argument parse)
9207 MIAxycc acc0,Rm,Rs. */
9212 inst.instruction |= inst.operands[1].reg;
9213 inst.instruction |= inst.operands[2].reg << 12;
9216 /* Xscale move-accumulator-register (argument parse)
9218 MARcc acc0,RdLo,RdHi. */
9223 inst.instruction |= inst.operands[1].reg << 12;
9224 inst.instruction |= inst.operands[2].reg << 16;
9227 /* Xscale move-register-accumulator (argument parse)
9229 MRAcc RdLo,RdHi,acc0. */
9234 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9235 inst.instruction |= inst.operands[0].reg << 12;
9236 inst.instruction |= inst.operands[1].reg << 16;
9239 /* Encoding functions relevant only to Thumb. */
9241 /* inst.operands[i] is a shifted-register operand; encode
9242 it into inst.instruction in the format used by Thumb32. */
9245 encode_thumb32_shifted_operand (int i)
9247 unsigned int value = inst.reloc.exp.X_add_number;
9248 unsigned int shift = inst.operands[i].shift_kind;
9250 constraint (inst.operands[i].immisreg,
9251 _("shift by register not allowed in thumb mode"));
9252 inst.instruction |= inst.operands[i].reg;
9253 if (shift == SHIFT_RRX)
9254 inst.instruction |= SHIFT_ROR << 4;
9257 constraint (inst.reloc.exp.X_op != O_constant,
9258 _("expression too complex"));
9260 constraint (value > 32
9261 || (value == 32 && (shift == SHIFT_LSL
9262 || shift == SHIFT_ROR)),
9263 _("shift expression is too large"));
9267 else if (value == 32)
9270 inst.instruction |= shift << 4;
9271 inst.instruction |= (value & 0x1c) << 10;
9272 inst.instruction |= (value & 0x03) << 6;
9277 /* inst.operands[i] was set up by parse_address. Encode it into a
9278 Thumb32 format load or store instruction. Reject forms that cannot
9279 be used with such instructions. If is_t is true, reject forms that
9280 cannot be used with a T instruction; if is_d is true, reject forms
9281 that cannot be used with a D instruction. If it is a store insn,
9285 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9287 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9289 constraint (!inst.operands[i].isreg,
9290 _("Instruction does not support =N addresses"));
9292 inst.instruction |= inst.operands[i].reg << 16;
9293 if (inst.operands[i].immisreg)
9295 constraint (is_pc, BAD_PC_ADDRESSING);
9296 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9297 constraint (inst.operands[i].negative,
9298 _("Thumb does not support negative register indexing"));
9299 constraint (inst.operands[i].postind,
9300 _("Thumb does not support register post-indexing"));
9301 constraint (inst.operands[i].writeback,
9302 _("Thumb does not support register indexing with writeback"));
9303 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9304 _("Thumb supports only LSL in shifted register indexing"));
9306 inst.instruction |= inst.operands[i].imm;
9307 if (inst.operands[i].shifted)
9309 constraint (inst.reloc.exp.X_op != O_constant,
9310 _("expression too complex"));
9311 constraint (inst.reloc.exp.X_add_number < 0
9312 || inst.reloc.exp.X_add_number > 3,
9313 _("shift out of range"));
9314 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9316 inst.reloc.type = BFD_RELOC_UNUSED;
9318 else if (inst.operands[i].preind)
9320 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9321 constraint (is_t && inst.operands[i].writeback,
9322 _("cannot use writeback with this instruction"));
9323 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9324 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9328 inst.instruction |= 0x01000000;
9329 if (inst.operands[i].writeback)
9330 inst.instruction |= 0x00200000;
9334 inst.instruction |= 0x00000c00;
9335 if (inst.operands[i].writeback)
9336 inst.instruction |= 0x00000100;
9338 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9340 else if (inst.operands[i].postind)
9342 gas_assert (inst.operands[i].writeback);
9343 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9344 constraint (is_t, _("cannot use post-indexing with this instruction"));
9347 inst.instruction |= 0x00200000;
9349 inst.instruction |= 0x00000900;
9350 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9352 else /* unindexed - only for coprocessor */
9353 inst.error = _("instruction does not accept unindexed addressing");
9356 /* Table of Thumb instructions which exist in both 16- and 32-bit
9357 encodings (the latter only in post-V6T2 cores). The index is the
9358 value used in the insns table below. When there is more than one
9359 possible 16-bit encoding for the instruction, this table always
9361 Also contains several pseudo-instructions used during relaxation. */
9362 #define T16_32_TAB \
9363 X(_adc, 4140, eb400000), \
9364 X(_adcs, 4140, eb500000), \
9365 X(_add, 1c00, eb000000), \
9366 X(_adds, 1c00, eb100000), \
9367 X(_addi, 0000, f1000000), \
9368 X(_addis, 0000, f1100000), \
9369 X(_add_pc,000f, f20f0000), \
9370 X(_add_sp,000d, f10d0000), \
9371 X(_adr, 000f, f20f0000), \
9372 X(_and, 4000, ea000000), \
9373 X(_ands, 4000, ea100000), \
9374 X(_asr, 1000, fa40f000), \
9375 X(_asrs, 1000, fa50f000), \
9376 X(_b, e000, f000b000), \
9377 X(_bcond, d000, f0008000), \
9378 X(_bic, 4380, ea200000), \
9379 X(_bics, 4380, ea300000), \
9380 X(_cmn, 42c0, eb100f00), \
9381 X(_cmp, 2800, ebb00f00), \
9382 X(_cpsie, b660, f3af8400), \
9383 X(_cpsid, b670, f3af8600), \
9384 X(_cpy, 4600, ea4f0000), \
9385 X(_dec_sp,80dd, f1ad0d00), \
9386 X(_eor, 4040, ea800000), \
9387 X(_eors, 4040, ea900000), \
9388 X(_inc_sp,00dd, f10d0d00), \
9389 X(_ldmia, c800, e8900000), \
9390 X(_ldr, 6800, f8500000), \
9391 X(_ldrb, 7800, f8100000), \
9392 X(_ldrh, 8800, f8300000), \
9393 X(_ldrsb, 5600, f9100000), \
9394 X(_ldrsh, 5e00, f9300000), \
9395 X(_ldr_pc,4800, f85f0000), \
9396 X(_ldr_pc2,4800, f85f0000), \
9397 X(_ldr_sp,9800, f85d0000), \
9398 X(_lsl, 0000, fa00f000), \
9399 X(_lsls, 0000, fa10f000), \
9400 X(_lsr, 0800, fa20f000), \
9401 X(_lsrs, 0800, fa30f000), \
9402 X(_mov, 2000, ea4f0000), \
9403 X(_movs, 2000, ea5f0000), \
9404 X(_mul, 4340, fb00f000), \
9405 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9406 X(_mvn, 43c0, ea6f0000), \
9407 X(_mvns, 43c0, ea7f0000), \
9408 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9409 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9410 X(_orr, 4300, ea400000), \
9411 X(_orrs, 4300, ea500000), \
9412 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9413 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9414 X(_rev, ba00, fa90f080), \
9415 X(_rev16, ba40, fa90f090), \
9416 X(_revsh, bac0, fa90f0b0), \
9417 X(_ror, 41c0, fa60f000), \
9418 X(_rors, 41c0, fa70f000), \
9419 X(_sbc, 4180, eb600000), \
9420 X(_sbcs, 4180, eb700000), \
9421 X(_stmia, c000, e8800000), \
9422 X(_str, 6000, f8400000), \
9423 X(_strb, 7000, f8000000), \
9424 X(_strh, 8000, f8200000), \
9425 X(_str_sp,9000, f84d0000), \
9426 X(_sub, 1e00, eba00000), \
9427 X(_subs, 1e00, ebb00000), \
9428 X(_subi, 8000, f1a00000), \
9429 X(_subis, 8000, f1b00000), \
9430 X(_sxtb, b240, fa4ff080), \
9431 X(_sxth, b200, fa0ff080), \
9432 X(_tst, 4200, ea100f00), \
9433 X(_uxtb, b2c0, fa5ff080), \
9434 X(_uxth, b280, fa1ff080), \
9435 X(_nop, bf00, f3af8000), \
9436 X(_yield, bf10, f3af8001), \
9437 X(_wfe, bf20, f3af8002), \
9438 X(_wfi, bf30, f3af8003), \
9439 X(_sev, bf40, f3af8004),
9441 /* To catch errors in encoding functions, the codes are all offset by
9442 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9443 as 16-bit instructions. */
9444 #define X(a,b,c) T_MNEM##a
9445 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9448 #define X(a,b,c) 0x##b
9449 static const unsigned short thumb_op16[] = { T16_32_TAB };
9450 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9453 #define X(a,b,c) 0x##c
9454 static const unsigned int thumb_op32[] = { T16_32_TAB };
9455 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9456 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9460 /* Thumb instruction encoders, in alphabetical order. */
9465 do_t_add_sub_w (void)
9469 Rd = inst.operands[0].reg;
9470 Rn = inst.operands[1].reg;
9472 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9473 is the SP-{plus,minus}-immediate form of the instruction. */
9475 constraint (Rd == REG_PC, BAD_PC);
9477 reject_bad_reg (Rd);
9479 inst.instruction |= (Rn << 16) | (Rd << 8);
9480 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9483 /* Parse an add or subtract instruction. We get here with inst.instruction
9484 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9491 Rd = inst.operands[0].reg;
9492 Rs = (inst.operands[1].present
9493 ? inst.operands[1].reg /* Rd, Rs, foo */
9494 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9497 set_it_insn_type_last ();
9505 flags = (inst.instruction == T_MNEM_adds
9506 || inst.instruction == T_MNEM_subs);
9508 narrow = !in_it_block ();
9510 narrow = in_it_block ();
9511 if (!inst.operands[2].isreg)
9515 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9517 add = (inst.instruction == T_MNEM_add
9518 || inst.instruction == T_MNEM_adds);
9520 if (inst.size_req != 4)
9522 /* Attempt to use a narrow opcode, with relaxation if
9524 if (Rd == REG_SP && Rs == REG_SP && !flags)
9525 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9526 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9527 opcode = T_MNEM_add_sp;
9528 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9529 opcode = T_MNEM_add_pc;
9530 else if (Rd <= 7 && Rs <= 7 && narrow)
9533 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9535 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9539 inst.instruction = THUMB_OP16(opcode);
9540 inst.instruction |= (Rd << 4) | Rs;
9541 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9542 if (inst.size_req != 2)
9543 inst.relax = opcode;
9546 constraint (inst.size_req == 2, BAD_HIREG);
9548 if (inst.size_req == 4
9549 || (inst.size_req != 2 && !opcode))
9553 constraint (add, BAD_PC);
9554 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9555 _("only SUBS PC, LR, #const allowed"));
9556 constraint (inst.reloc.exp.X_op != O_constant,
9557 _("expression too complex"));
9558 constraint (inst.reloc.exp.X_add_number < 0
9559 || inst.reloc.exp.X_add_number > 0xff,
9560 _("immediate value out of range"));
9561 inst.instruction = T2_SUBS_PC_LR
9562 | inst.reloc.exp.X_add_number;
9563 inst.reloc.type = BFD_RELOC_UNUSED;
9566 else if (Rs == REG_PC)
9568 /* Always use addw/subw. */
9569 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9570 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9574 inst.instruction = THUMB_OP32 (inst.instruction);
9575 inst.instruction = (inst.instruction & 0xe1ffffff)
9578 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9580 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9582 inst.instruction |= Rd << 8;
9583 inst.instruction |= Rs << 16;
9588 unsigned int value = inst.reloc.exp.X_add_number;
9589 unsigned int shift = inst.operands[2].shift_kind;
9591 Rn = inst.operands[2].reg;
9592 /* See if we can do this with a 16-bit instruction. */
9593 if (!inst.operands[2].shifted && inst.size_req != 4)
9595 if (Rd > 7 || Rs > 7 || Rn > 7)
9600 inst.instruction = ((inst.instruction == T_MNEM_adds
9601 || inst.instruction == T_MNEM_add)
9604 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9608 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9610 /* Thumb-1 cores (except v6-M) require at least one high
9611 register in a narrow non flag setting add. */
9612 if (Rd > 7 || Rn > 7
9613 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9614 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9621 inst.instruction = T_OPCODE_ADD_HI;
9622 inst.instruction |= (Rd & 8) << 4;
9623 inst.instruction |= (Rd & 7);
9624 inst.instruction |= Rn << 3;
9630 constraint (Rd == REG_PC, BAD_PC);
9631 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9632 constraint (Rs == REG_PC, BAD_PC);
9633 reject_bad_reg (Rn);
9635 /* If we get here, it can't be done in 16 bits. */
9636 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9637 _("shift must be constant"));
9638 inst.instruction = THUMB_OP32 (inst.instruction);
9639 inst.instruction |= Rd << 8;
9640 inst.instruction |= Rs << 16;
9641 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9642 _("shift value over 3 not allowed in thumb mode"));
9643 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9644 _("only LSL shift allowed in thumb mode"));
9645 encode_thumb32_shifted_operand (2);
9650 constraint (inst.instruction == T_MNEM_adds
9651 || inst.instruction == T_MNEM_subs,
9654 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9656 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9657 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9660 inst.instruction = (inst.instruction == T_MNEM_add
9662 inst.instruction |= (Rd << 4) | Rs;
9663 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9667 Rn = inst.operands[2].reg;
9668 constraint (inst.operands[2].shifted, _("unshifted register required"));
9670 /* We now have Rd, Rs, and Rn set to registers. */
9671 if (Rd > 7 || Rs > 7 || Rn > 7)
9673 /* Can't do this for SUB. */
9674 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9675 inst.instruction = T_OPCODE_ADD_HI;
9676 inst.instruction |= (Rd & 8) << 4;
9677 inst.instruction |= (Rd & 7);
9679 inst.instruction |= Rn << 3;
9681 inst.instruction |= Rs << 3;
9683 constraint (1, _("dest must overlap one source register"));
9687 inst.instruction = (inst.instruction == T_MNEM_add
9688 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9689 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9699 Rd = inst.operands[0].reg;
9700 reject_bad_reg (Rd);
9702 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9704 /* Defer to section relaxation. */
9705 inst.relax = inst.instruction;
9706 inst.instruction = THUMB_OP16 (inst.instruction);
9707 inst.instruction |= Rd << 4;
9709 else if (unified_syntax && inst.size_req != 2)
9711 /* Generate a 32-bit opcode. */
9712 inst.instruction = THUMB_OP32 (inst.instruction);
9713 inst.instruction |= Rd << 8;
9714 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9715 inst.reloc.pc_rel = 1;
9719 /* Generate a 16-bit opcode. */
9720 inst.instruction = THUMB_OP16 (inst.instruction);
9721 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9722 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9723 inst.reloc.pc_rel = 1;
9725 inst.instruction |= Rd << 4;
9729 /* Arithmetic instructions for which there is just one 16-bit
9730 instruction encoding, and it allows only two low registers.
9731 For maximal compatibility with ARM syntax, we allow three register
9732 operands even when Thumb-32 instructions are not available, as long
9733 as the first two are identical. For instance, both "sbc r0,r1" and
9734 "sbc r0,r0,r1" are allowed. */
9740 Rd = inst.operands[0].reg;
9741 Rs = (inst.operands[1].present
9742 ? inst.operands[1].reg /* Rd, Rs, foo */
9743 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9744 Rn = inst.operands[2].reg;
9746 reject_bad_reg (Rd);
9747 reject_bad_reg (Rs);
9748 if (inst.operands[2].isreg)
9749 reject_bad_reg (Rn);
9753 if (!inst.operands[2].isreg)
9755 /* For an immediate, we always generate a 32-bit opcode;
9756 section relaxation will shrink it later if possible. */
9757 inst.instruction = THUMB_OP32 (inst.instruction);
9758 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9759 inst.instruction |= Rd << 8;
9760 inst.instruction |= Rs << 16;
9761 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9767 /* See if we can do this with a 16-bit instruction. */
9768 if (THUMB_SETS_FLAGS (inst.instruction))
9769 narrow = !in_it_block ();
9771 narrow = in_it_block ();
9773 if (Rd > 7 || Rn > 7 || Rs > 7)
9775 if (inst.operands[2].shifted)
9777 if (inst.size_req == 4)
9783 inst.instruction = THUMB_OP16 (inst.instruction);
9784 inst.instruction |= Rd;
9785 inst.instruction |= Rn << 3;
9789 /* If we get here, it can't be done in 16 bits. */
9790 constraint (inst.operands[2].shifted
9791 && inst.operands[2].immisreg,
9792 _("shift must be constant"));
9793 inst.instruction = THUMB_OP32 (inst.instruction);
9794 inst.instruction |= Rd << 8;
9795 inst.instruction |= Rs << 16;
9796 encode_thumb32_shifted_operand (2);
9801 /* On its face this is a lie - the instruction does set the
9802 flags. However, the only supported mnemonic in this mode
9804 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9806 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9807 _("unshifted register required"));
9808 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9809 constraint (Rd != Rs,
9810 _("dest and source1 must be the same register"));
9812 inst.instruction = THUMB_OP16 (inst.instruction);
9813 inst.instruction |= Rd;
9814 inst.instruction |= Rn << 3;
9818 /* Similarly, but for instructions where the arithmetic operation is
9819 commutative, so we can allow either of them to be different from
9820 the destination operand in a 16-bit instruction. For instance, all
9821 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9828 Rd = inst.operands[0].reg;
9829 Rs = (inst.operands[1].present
9830 ? inst.operands[1].reg /* Rd, Rs, foo */
9831 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9832 Rn = inst.operands[2].reg;
9834 reject_bad_reg (Rd);
9835 reject_bad_reg (Rs);
9836 if (inst.operands[2].isreg)
9837 reject_bad_reg (Rn);
9841 if (!inst.operands[2].isreg)
9843 /* For an immediate, we always generate a 32-bit opcode;
9844 section relaxation will shrink it later if possible. */
9845 inst.instruction = THUMB_OP32 (inst.instruction);
9846 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9847 inst.instruction |= Rd << 8;
9848 inst.instruction |= Rs << 16;
9849 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9855 /* See if we can do this with a 16-bit instruction. */
9856 if (THUMB_SETS_FLAGS (inst.instruction))
9857 narrow = !in_it_block ();
9859 narrow = in_it_block ();
9861 if (Rd > 7 || Rn > 7 || Rs > 7)
9863 if (inst.operands[2].shifted)
9865 if (inst.size_req == 4)
9872 inst.instruction = THUMB_OP16 (inst.instruction);
9873 inst.instruction |= Rd;
9874 inst.instruction |= Rn << 3;
9879 inst.instruction = THUMB_OP16 (inst.instruction);
9880 inst.instruction |= Rd;
9881 inst.instruction |= Rs << 3;
9886 /* If we get here, it can't be done in 16 bits. */
9887 constraint (inst.operands[2].shifted
9888 && inst.operands[2].immisreg,
9889 _("shift must be constant"));
9890 inst.instruction = THUMB_OP32 (inst.instruction);
9891 inst.instruction |= Rd << 8;
9892 inst.instruction |= Rs << 16;
9893 encode_thumb32_shifted_operand (2);
9898 /* On its face this is a lie - the instruction does set the
9899 flags. However, the only supported mnemonic in this mode
9901 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9903 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9904 _("unshifted register required"));
9905 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9907 inst.instruction = THUMB_OP16 (inst.instruction);
9908 inst.instruction |= Rd;
9911 inst.instruction |= Rn << 3;
9913 inst.instruction |= Rs << 3;
9915 constraint (1, _("dest must overlap one source register"));
9922 if (inst.operands[0].present)
9924 constraint ((inst.instruction & 0xf0) != 0x40
9925 && inst.operands[0].imm > 0xf
9926 && inst.operands[0].imm < 0x0,
9927 _("bad barrier type"));
9928 inst.instruction |= inst.operands[0].imm;
9931 inst.instruction |= 0xf;
9938 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9939 constraint (msb > 32, _("bit-field extends past end of register"));
9940 /* The instruction encoding stores the LSB and MSB,
9941 not the LSB and width. */
9942 Rd = inst.operands[0].reg;
9943 reject_bad_reg (Rd);
9944 inst.instruction |= Rd << 8;
9945 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9946 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9947 inst.instruction |= msb - 1;
9956 Rd = inst.operands[0].reg;
9957 reject_bad_reg (Rd);
9959 /* #0 in second position is alternative syntax for bfc, which is
9960 the same instruction but with REG_PC in the Rm field. */
9961 if (!inst.operands[1].isreg)
9965 Rn = inst.operands[1].reg;
9966 reject_bad_reg (Rn);
9969 msb = inst.operands[2].imm + inst.operands[3].imm;
9970 constraint (msb > 32, _("bit-field extends past end of register"));
9971 /* The instruction encoding stores the LSB and MSB,
9972 not the LSB and width. */
9973 inst.instruction |= Rd << 8;
9974 inst.instruction |= Rn << 16;
9975 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9976 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9977 inst.instruction |= msb - 1;
9985 Rd = inst.operands[0].reg;
9986 Rn = inst.operands[1].reg;
9988 reject_bad_reg (Rd);
9989 reject_bad_reg (Rn);
9991 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9992 _("bit-field extends past end of register"));
9993 inst.instruction |= Rd << 8;
9994 inst.instruction |= Rn << 16;
9995 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9996 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9997 inst.instruction |= inst.operands[3].imm - 1;
10000 /* ARM V5 Thumb BLX (argument parse)
10001 BLX <target_addr> which is BLX(1)
10002 BLX <Rm> which is BLX(2)
10003 Unfortunately, there are two different opcodes for this mnemonic.
10004 So, the insns[].value is not used, and the code here zaps values
10005 into inst.instruction.
10007 ??? How to take advantage of the additional two bits of displacement
10008 available in Thumb32 mode? Need new relocation? */
10013 set_it_insn_type_last ();
10015 if (inst.operands[0].isreg)
10017 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10018 /* We have a register, so this is BLX(2). */
10019 inst.instruction |= inst.operands[0].reg << 3;
10023 /* No register. This must be BLX(1). */
10024 inst.instruction = 0xf000e800;
10025 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10037 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10039 if (in_it_block ())
10041 /* Conditional branches inside IT blocks are encoded as unconditional
10043 cond = COND_ALWAYS;
10048 if (cond != COND_ALWAYS)
10049 opcode = T_MNEM_bcond;
10051 opcode = inst.instruction;
10054 && (inst.size_req == 4
10055 || (inst.size_req != 2
10056 && (inst.operands[0].hasreloc
10057 || inst.reloc.exp.X_op == O_constant))))
10059 inst.instruction = THUMB_OP32(opcode);
10060 if (cond == COND_ALWAYS)
10061 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10064 gas_assert (cond != 0xF);
10065 inst.instruction |= cond << 22;
10066 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10071 inst.instruction = THUMB_OP16(opcode);
10072 if (cond == COND_ALWAYS)
10073 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10076 inst.instruction |= cond << 8;
10077 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10079 /* Allow section relaxation. */
10080 if (unified_syntax && inst.size_req != 2)
10081 inst.relax = opcode;
10083 inst.reloc.type = reloc;
10084 inst.reloc.pc_rel = 1;
10090 constraint (inst.cond != COND_ALWAYS,
10091 _("instruction is always unconditional"));
10092 if (inst.operands[0].present)
10094 constraint (inst.operands[0].imm > 255,
10095 _("immediate value out of range"));
10096 inst.instruction |= inst.operands[0].imm;
10097 set_it_insn_type (NEUTRAL_IT_INSN);
10102 do_t_branch23 (void)
10104 set_it_insn_type_last ();
10105 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10107 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10108 this file. We used to simply ignore the PLT reloc type here --
10109 the branch encoding is now needed to deal with TLSCALL relocs.
10110 So if we see a PLT reloc now, put it back to how it used to be to
10111 keep the preexisting behaviour. */
10112 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10113 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10115 #if defined(OBJ_COFF)
10116 /* If the destination of the branch is a defined symbol which does not have
10117 the THUMB_FUNC attribute, then we must be calling a function which has
10118 the (interfacearm) attribute. We look for the Thumb entry point to that
10119 function and change the branch to refer to that function instead. */
10120 if ( inst.reloc.exp.X_op == O_symbol
10121 && inst.reloc.exp.X_add_symbol != NULL
10122 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10123 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10124 inst.reloc.exp.X_add_symbol =
10125 find_real_start (inst.reloc.exp.X_add_symbol);
10132 set_it_insn_type_last ();
10133 inst.instruction |= inst.operands[0].reg << 3;
10134 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10135 should cause the alignment to be checked once it is known. This is
10136 because BX PC only works if the instruction is word aligned. */
10144 set_it_insn_type_last ();
10145 Rm = inst.operands[0].reg;
10146 reject_bad_reg (Rm);
10147 inst.instruction |= Rm << 16;
10156 Rd = inst.operands[0].reg;
10157 Rm = inst.operands[1].reg;
10159 reject_bad_reg (Rd);
10160 reject_bad_reg (Rm);
10162 inst.instruction |= Rd << 8;
10163 inst.instruction |= Rm << 16;
10164 inst.instruction |= Rm;
10170 set_it_insn_type (OUTSIDE_IT_INSN);
10171 inst.instruction |= inst.operands[0].imm;
10177 set_it_insn_type (OUTSIDE_IT_INSN);
10179 && (inst.operands[1].present || inst.size_req == 4)
10180 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10182 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10183 inst.instruction = 0xf3af8000;
10184 inst.instruction |= imod << 9;
10185 inst.instruction |= inst.operands[0].imm << 5;
10186 if (inst.operands[1].present)
10187 inst.instruction |= 0x100 | inst.operands[1].imm;
10191 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10192 && (inst.operands[0].imm & 4),
10193 _("selected processor does not support 'A' form "
10194 "of this instruction"));
10195 constraint (inst.operands[1].present || inst.size_req == 4,
10196 _("Thumb does not support the 2-argument "
10197 "form of this instruction"));
10198 inst.instruction |= inst.operands[0].imm;
10202 /* THUMB CPY instruction (argument parse). */
10207 if (inst.size_req == 4)
10209 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10210 inst.instruction |= inst.operands[0].reg << 8;
10211 inst.instruction |= inst.operands[1].reg;
10215 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10216 inst.instruction |= (inst.operands[0].reg & 0x7);
10217 inst.instruction |= inst.operands[1].reg << 3;
10224 set_it_insn_type (OUTSIDE_IT_INSN);
10225 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10226 inst.instruction |= inst.operands[0].reg;
10227 inst.reloc.pc_rel = 1;
10228 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10234 inst.instruction |= inst.operands[0].imm;
10240 unsigned Rd, Rn, Rm;
10242 Rd = inst.operands[0].reg;
10243 Rn = (inst.operands[1].present
10244 ? inst.operands[1].reg : Rd);
10245 Rm = inst.operands[2].reg;
10247 reject_bad_reg (Rd);
10248 reject_bad_reg (Rn);
10249 reject_bad_reg (Rm);
10251 inst.instruction |= Rd << 8;
10252 inst.instruction |= Rn << 16;
10253 inst.instruction |= Rm;
10259 if (unified_syntax && inst.size_req == 4)
10260 inst.instruction = THUMB_OP32 (inst.instruction);
10262 inst.instruction = THUMB_OP16 (inst.instruction);
10268 unsigned int cond = inst.operands[0].imm;
10270 set_it_insn_type (IT_INSN);
10271 now_it.mask = (inst.instruction & 0xf) | 0x10;
10274 /* If the condition is a negative condition, invert the mask. */
10275 if ((cond & 0x1) == 0x0)
10277 unsigned int mask = inst.instruction & 0x000f;
10279 if ((mask & 0x7) == 0)
10280 /* no conversion needed */;
10281 else if ((mask & 0x3) == 0)
10283 else if ((mask & 0x1) == 0)
10288 inst.instruction &= 0xfff0;
10289 inst.instruction |= mask;
10292 inst.instruction |= cond << 4;
10295 /* Helper function used for both push/pop and ldm/stm. */
10297 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10301 load = (inst.instruction & (1 << 20)) != 0;
10303 if (mask & (1 << 13))
10304 inst.error = _("SP not allowed in register list");
10306 if ((mask & (1 << base)) != 0
10308 inst.error = _("having the base register in the register list when "
10309 "using write back is UNPREDICTABLE");
10313 if (mask & (1 << 15))
10315 if (mask & (1 << 14))
10316 inst.error = _("LR and PC should not both be in register list");
10318 set_it_insn_type_last ();
10323 if (mask & (1 << 15))
10324 inst.error = _("PC not allowed in register list");
10327 if ((mask & (mask - 1)) == 0)
10329 /* Single register transfers implemented as str/ldr. */
10332 if (inst.instruction & (1 << 23))
10333 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10335 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10339 if (inst.instruction & (1 << 23))
10340 inst.instruction = 0x00800000; /* ia -> [base] */
10342 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10345 inst.instruction |= 0xf8400000;
10347 inst.instruction |= 0x00100000;
10349 mask = ffs (mask) - 1;
10352 else if (writeback)
10353 inst.instruction |= WRITE_BACK;
10355 inst.instruction |= mask;
10356 inst.instruction |= base << 16;
10362 /* This really doesn't seem worth it. */
10363 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10364 _("expression too complex"));
10365 constraint (inst.operands[1].writeback,
10366 _("Thumb load/store multiple does not support {reglist}^"));
10368 if (unified_syntax)
10370 bfd_boolean narrow;
10374 /* See if we can use a 16-bit instruction. */
10375 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10376 && inst.size_req != 4
10377 && !(inst.operands[1].imm & ~0xff))
10379 mask = 1 << inst.operands[0].reg;
10381 if (inst.operands[0].reg <= 7)
10383 if (inst.instruction == T_MNEM_stmia
10384 ? inst.operands[0].writeback
10385 : (inst.operands[0].writeback
10386 == !(inst.operands[1].imm & mask)))
10388 if (inst.instruction == T_MNEM_stmia
10389 && (inst.operands[1].imm & mask)
10390 && (inst.operands[1].imm & (mask - 1)))
10391 as_warn (_("value stored for r%d is UNKNOWN"),
10392 inst.operands[0].reg);
10394 inst.instruction = THUMB_OP16 (inst.instruction);
10395 inst.instruction |= inst.operands[0].reg << 8;
10396 inst.instruction |= inst.operands[1].imm;
10399 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10401 /* This means 1 register in reg list one of 3 situations:
10402 1. Instruction is stmia, but without writeback.
10403 2. lmdia without writeback, but with Rn not in
10405 3. ldmia with writeback, but with Rn in reglist.
10406 Case 3 is UNPREDICTABLE behaviour, so we handle
10407 case 1 and 2 which can be converted into a 16-bit
10408 str or ldr. The SP cases are handled below. */
10409 unsigned long opcode;
10410 /* First, record an error for Case 3. */
10411 if (inst.operands[1].imm & mask
10412 && inst.operands[0].writeback)
10414 _("having the base register in the register list when "
10415 "using write back is UNPREDICTABLE");
10417 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10419 inst.instruction = THUMB_OP16 (opcode);
10420 inst.instruction |= inst.operands[0].reg << 3;
10421 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10425 else if (inst.operands[0] .reg == REG_SP)
10427 if (inst.operands[0].writeback)
10430 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10431 ? T_MNEM_push : T_MNEM_pop);
10432 inst.instruction |= inst.operands[1].imm;
10435 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10438 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10439 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10440 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10448 if (inst.instruction < 0xffff)
10449 inst.instruction = THUMB_OP32 (inst.instruction);
10451 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10452 inst.operands[0].writeback);
10457 constraint (inst.operands[0].reg > 7
10458 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10459 constraint (inst.instruction != T_MNEM_ldmia
10460 && inst.instruction != T_MNEM_stmia,
10461 _("Thumb-2 instruction only valid in unified syntax"));
10462 if (inst.instruction == T_MNEM_stmia)
10464 if (!inst.operands[0].writeback)
10465 as_warn (_("this instruction will write back the base register"));
10466 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10467 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10468 as_warn (_("value stored for r%d is UNKNOWN"),
10469 inst.operands[0].reg);
10473 if (!inst.operands[0].writeback
10474 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10475 as_warn (_("this instruction will write back the base register"));
10476 else if (inst.operands[0].writeback
10477 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10478 as_warn (_("this instruction will not write back the base register"));
10481 inst.instruction = THUMB_OP16 (inst.instruction);
10482 inst.instruction |= inst.operands[0].reg << 8;
10483 inst.instruction |= inst.operands[1].imm;
10490 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10491 || inst.operands[1].postind || inst.operands[1].writeback
10492 || inst.operands[1].immisreg || inst.operands[1].shifted
10493 || inst.operands[1].negative,
10496 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10498 inst.instruction |= inst.operands[0].reg << 12;
10499 inst.instruction |= inst.operands[1].reg << 16;
10500 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10506 if (!inst.operands[1].present)
10508 constraint (inst.operands[0].reg == REG_LR,
10509 _("r14 not allowed as first register "
10510 "when second register is omitted"));
10511 inst.operands[1].reg = inst.operands[0].reg + 1;
10513 constraint (inst.operands[0].reg == inst.operands[1].reg,
10516 inst.instruction |= inst.operands[0].reg << 12;
10517 inst.instruction |= inst.operands[1].reg << 8;
10518 inst.instruction |= inst.operands[2].reg << 16;
10524 unsigned long opcode;
10527 if (inst.operands[0].isreg
10528 && !inst.operands[0].preind
10529 && inst.operands[0].reg == REG_PC)
10530 set_it_insn_type_last ();
10532 opcode = inst.instruction;
10533 if (unified_syntax)
10535 if (!inst.operands[1].isreg)
10537 if (opcode <= 0xffff)
10538 inst.instruction = THUMB_OP32 (opcode);
10539 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10542 if (inst.operands[1].isreg
10543 && !inst.operands[1].writeback
10544 && !inst.operands[1].shifted && !inst.operands[1].postind
10545 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10546 && opcode <= 0xffff
10547 && inst.size_req != 4)
10549 /* Insn may have a 16-bit form. */
10550 Rn = inst.operands[1].reg;
10551 if (inst.operands[1].immisreg)
10553 inst.instruction = THUMB_OP16 (opcode);
10555 if (Rn <= 7 && inst.operands[1].imm <= 7)
10557 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10558 reject_bad_reg (inst.operands[1].imm);
10560 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10561 && opcode != T_MNEM_ldrsb)
10562 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10563 || (Rn == REG_SP && opcode == T_MNEM_str))
10570 if (inst.reloc.pc_rel)
10571 opcode = T_MNEM_ldr_pc2;
10573 opcode = T_MNEM_ldr_pc;
10577 if (opcode == T_MNEM_ldr)
10578 opcode = T_MNEM_ldr_sp;
10580 opcode = T_MNEM_str_sp;
10582 inst.instruction = inst.operands[0].reg << 8;
10586 inst.instruction = inst.operands[0].reg;
10587 inst.instruction |= inst.operands[1].reg << 3;
10589 inst.instruction |= THUMB_OP16 (opcode);
10590 if (inst.size_req == 2)
10591 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10593 inst.relax = opcode;
10597 /* Definitely a 32-bit variant. */
10599 /* Warning for Erratum 752419. */
10600 if (opcode == T_MNEM_ldr
10601 && inst.operands[0].reg == REG_SP
10602 && inst.operands[1].writeback == 1
10603 && !inst.operands[1].immisreg)
10605 if (no_cpu_selected ()
10606 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10607 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10608 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10609 as_warn (_("This instruction may be unpredictable "
10610 "if executed on M-profile cores "
10611 "with interrupts enabled."));
10614 /* Do some validations regarding addressing modes. */
10615 if (inst.operands[1].immisreg)
10616 reject_bad_reg (inst.operands[1].imm);
10618 constraint (inst.operands[1].writeback == 1
10619 && inst.operands[0].reg == inst.operands[1].reg,
10622 inst.instruction = THUMB_OP32 (opcode);
10623 inst.instruction |= inst.operands[0].reg << 12;
10624 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10625 check_ldr_r15_aligned ();
10629 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10631 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10633 /* Only [Rn,Rm] is acceptable. */
10634 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10635 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10636 || inst.operands[1].postind || inst.operands[1].shifted
10637 || inst.operands[1].negative,
10638 _("Thumb does not support this addressing mode"));
10639 inst.instruction = THUMB_OP16 (inst.instruction);
10643 inst.instruction = THUMB_OP16 (inst.instruction);
10644 if (!inst.operands[1].isreg)
10645 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10648 constraint (!inst.operands[1].preind
10649 || inst.operands[1].shifted
10650 || inst.operands[1].writeback,
10651 _("Thumb does not support this addressing mode"));
10652 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10654 constraint (inst.instruction & 0x0600,
10655 _("byte or halfword not valid for base register"));
10656 constraint (inst.operands[1].reg == REG_PC
10657 && !(inst.instruction & THUMB_LOAD_BIT),
10658 _("r15 based store not allowed"));
10659 constraint (inst.operands[1].immisreg,
10660 _("invalid base register for register offset"));
10662 if (inst.operands[1].reg == REG_PC)
10663 inst.instruction = T_OPCODE_LDR_PC;
10664 else if (inst.instruction & THUMB_LOAD_BIT)
10665 inst.instruction = T_OPCODE_LDR_SP;
10667 inst.instruction = T_OPCODE_STR_SP;
10669 inst.instruction |= inst.operands[0].reg << 8;
10670 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10674 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10675 if (!inst.operands[1].immisreg)
10677 /* Immediate offset. */
10678 inst.instruction |= inst.operands[0].reg;
10679 inst.instruction |= inst.operands[1].reg << 3;
10680 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10684 /* Register offset. */
10685 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10686 constraint (inst.operands[1].negative,
10687 _("Thumb does not support this addressing mode"));
10690 switch (inst.instruction)
10692 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10693 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10694 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10695 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10696 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10697 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10698 case 0x5600 /* ldrsb */:
10699 case 0x5e00 /* ldrsh */: break;
10703 inst.instruction |= inst.operands[0].reg;
10704 inst.instruction |= inst.operands[1].reg << 3;
10705 inst.instruction |= inst.operands[1].imm << 6;
10711 if (!inst.operands[1].present)
10713 inst.operands[1].reg = inst.operands[0].reg + 1;
10714 constraint (inst.operands[0].reg == REG_LR,
10715 _("r14 not allowed here"));
10716 constraint (inst.operands[0].reg == REG_R12,
10717 _("r12 not allowed here"));
10720 if (inst.operands[2].writeback
10721 && (inst.operands[0].reg == inst.operands[2].reg
10722 || inst.operands[1].reg == inst.operands[2].reg))
10723 as_warn (_("base register written back, and overlaps "
10724 "one of transfer registers"));
10726 inst.instruction |= inst.operands[0].reg << 12;
10727 inst.instruction |= inst.operands[1].reg << 8;
10728 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10734 inst.instruction |= inst.operands[0].reg << 12;
10735 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10741 unsigned Rd, Rn, Rm, Ra;
10743 Rd = inst.operands[0].reg;
10744 Rn = inst.operands[1].reg;
10745 Rm = inst.operands[2].reg;
10746 Ra = inst.operands[3].reg;
10748 reject_bad_reg (Rd);
10749 reject_bad_reg (Rn);
10750 reject_bad_reg (Rm);
10751 reject_bad_reg (Ra);
10753 inst.instruction |= Rd << 8;
10754 inst.instruction |= Rn << 16;
10755 inst.instruction |= Rm;
10756 inst.instruction |= Ra << 12;
10762 unsigned RdLo, RdHi, Rn, Rm;
10764 RdLo = inst.operands[0].reg;
10765 RdHi = inst.operands[1].reg;
10766 Rn = inst.operands[2].reg;
10767 Rm = inst.operands[3].reg;
10769 reject_bad_reg (RdLo);
10770 reject_bad_reg (RdHi);
10771 reject_bad_reg (Rn);
10772 reject_bad_reg (Rm);
10774 inst.instruction |= RdLo << 12;
10775 inst.instruction |= RdHi << 8;
10776 inst.instruction |= Rn << 16;
10777 inst.instruction |= Rm;
10781 do_t_mov_cmp (void)
10785 Rn = inst.operands[0].reg;
10786 Rm = inst.operands[1].reg;
10789 set_it_insn_type_last ();
10791 if (unified_syntax)
10793 int r0off = (inst.instruction == T_MNEM_mov
10794 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10795 unsigned long opcode;
10796 bfd_boolean narrow;
10797 bfd_boolean low_regs;
10799 low_regs = (Rn <= 7 && Rm <= 7);
10800 opcode = inst.instruction;
10801 if (in_it_block ())
10802 narrow = opcode != T_MNEM_movs;
10804 narrow = opcode != T_MNEM_movs || low_regs;
10805 if (inst.size_req == 4
10806 || inst.operands[1].shifted)
10809 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10810 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10811 && !inst.operands[1].shifted
10815 inst.instruction = T2_SUBS_PC_LR;
10819 if (opcode == T_MNEM_cmp)
10821 constraint (Rn == REG_PC, BAD_PC);
10824 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10826 warn_deprecated_sp (Rm);
10827 /* R15 was documented as a valid choice for Rm in ARMv6,
10828 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10829 tools reject R15, so we do too. */
10830 constraint (Rm == REG_PC, BAD_PC);
10833 reject_bad_reg (Rm);
10835 else if (opcode == T_MNEM_mov
10836 || opcode == T_MNEM_movs)
10838 if (inst.operands[1].isreg)
10840 if (opcode == T_MNEM_movs)
10842 reject_bad_reg (Rn);
10843 reject_bad_reg (Rm);
10847 /* This is mov.n. */
10848 if ((Rn == REG_SP || Rn == REG_PC)
10849 && (Rm == REG_SP || Rm == REG_PC))
10851 as_warn (_("Use of r%u as a source register is "
10852 "deprecated when r%u is the destination "
10853 "register."), Rm, Rn);
10858 /* This is mov.w. */
10859 constraint (Rn == REG_PC, BAD_PC);
10860 constraint (Rm == REG_PC, BAD_PC);
10861 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10865 reject_bad_reg (Rn);
10868 if (!inst.operands[1].isreg)
10870 /* Immediate operand. */
10871 if (!in_it_block () && opcode == T_MNEM_mov)
10873 if (low_regs && narrow)
10875 inst.instruction = THUMB_OP16 (opcode);
10876 inst.instruction |= Rn << 8;
10877 if (inst.size_req == 2)
10878 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10880 inst.relax = opcode;
10884 inst.instruction = THUMB_OP32 (inst.instruction);
10885 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10886 inst.instruction |= Rn << r0off;
10887 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10890 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10891 && (inst.instruction == T_MNEM_mov
10892 || inst.instruction == T_MNEM_movs))
10894 /* Register shifts are encoded as separate shift instructions. */
10895 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10897 if (in_it_block ())
10902 if (inst.size_req == 4)
10905 if (!low_regs || inst.operands[1].imm > 7)
10911 switch (inst.operands[1].shift_kind)
10914 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10917 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10920 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10923 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10929 inst.instruction = opcode;
10932 inst.instruction |= Rn;
10933 inst.instruction |= inst.operands[1].imm << 3;
10938 inst.instruction |= CONDS_BIT;
10940 inst.instruction |= Rn << 8;
10941 inst.instruction |= Rm << 16;
10942 inst.instruction |= inst.operands[1].imm;
10947 /* Some mov with immediate shift have narrow variants.
10948 Register shifts are handled above. */
10949 if (low_regs && inst.operands[1].shifted
10950 && (inst.instruction == T_MNEM_mov
10951 || inst.instruction == T_MNEM_movs))
10953 if (in_it_block ())
10954 narrow = (inst.instruction == T_MNEM_mov);
10956 narrow = (inst.instruction == T_MNEM_movs);
10961 switch (inst.operands[1].shift_kind)
10963 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10964 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10965 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10966 default: narrow = FALSE; break;
10972 inst.instruction |= Rn;
10973 inst.instruction |= Rm << 3;
10974 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10978 inst.instruction = THUMB_OP32 (inst.instruction);
10979 inst.instruction |= Rn << r0off;
10980 encode_thumb32_shifted_operand (1);
10984 switch (inst.instruction)
10987 /* In v4t or v5t a move of two lowregs produces unpredictable
10988 results. Don't allow this. */
10991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
10992 "MOV Rd, Rs with two low registers is not "
10993 "permitted on this architecture");
10994 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
10998 inst.instruction = T_OPCODE_MOV_HR;
10999 inst.instruction |= (Rn & 0x8) << 4;
11000 inst.instruction |= (Rn & 0x7);
11001 inst.instruction |= Rm << 3;
11005 /* We know we have low registers at this point.
11006 Generate LSLS Rd, Rs, #0. */
11007 inst.instruction = T_OPCODE_LSL_I;
11008 inst.instruction |= Rn;
11009 inst.instruction |= Rm << 3;
11015 inst.instruction = T_OPCODE_CMP_LR;
11016 inst.instruction |= Rn;
11017 inst.instruction |= Rm << 3;
11021 inst.instruction = T_OPCODE_CMP_HR;
11022 inst.instruction |= (Rn & 0x8) << 4;
11023 inst.instruction |= (Rn & 0x7);
11024 inst.instruction |= Rm << 3;
11031 inst.instruction = THUMB_OP16 (inst.instruction);
11033 /* PR 10443: Do not silently ignore shifted operands. */
11034 constraint (inst.operands[1].shifted,
11035 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11037 if (inst.operands[1].isreg)
11039 if (Rn < 8 && Rm < 8)
11041 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11042 since a MOV instruction produces unpredictable results. */
11043 if (inst.instruction == T_OPCODE_MOV_I8)
11044 inst.instruction = T_OPCODE_ADD_I3;
11046 inst.instruction = T_OPCODE_CMP_LR;
11048 inst.instruction |= Rn;
11049 inst.instruction |= Rm << 3;
11053 if (inst.instruction == T_OPCODE_MOV_I8)
11054 inst.instruction = T_OPCODE_MOV_HR;
11056 inst.instruction = T_OPCODE_CMP_HR;
11062 constraint (Rn > 7,
11063 _("only lo regs allowed with immediate"));
11064 inst.instruction |= Rn << 8;
11065 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11076 top = (inst.instruction & 0x00800000) != 0;
11077 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11079 constraint (top, _(":lower16: not allowed this instruction"));
11080 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11082 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11084 constraint (!top, _(":upper16: not allowed this instruction"));
11085 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11088 Rd = inst.operands[0].reg;
11089 reject_bad_reg (Rd);
11091 inst.instruction |= Rd << 8;
11092 if (inst.reloc.type == BFD_RELOC_UNUSED)
11094 imm = inst.reloc.exp.X_add_number;
11095 inst.instruction |= (imm & 0xf000) << 4;
11096 inst.instruction |= (imm & 0x0800) << 15;
11097 inst.instruction |= (imm & 0x0700) << 4;
11098 inst.instruction |= (imm & 0x00ff);
11103 do_t_mvn_tst (void)
11107 Rn = inst.operands[0].reg;
11108 Rm = inst.operands[1].reg;
11110 if (inst.instruction == T_MNEM_cmp
11111 || inst.instruction == T_MNEM_cmn)
11112 constraint (Rn == REG_PC, BAD_PC);
11114 reject_bad_reg (Rn);
11115 reject_bad_reg (Rm);
11117 if (unified_syntax)
11119 int r0off = (inst.instruction == T_MNEM_mvn
11120 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11121 bfd_boolean narrow;
11123 if (inst.size_req == 4
11124 || inst.instruction > 0xffff
11125 || inst.operands[1].shifted
11126 || Rn > 7 || Rm > 7)
11128 else if (inst.instruction == T_MNEM_cmn)
11130 else if (THUMB_SETS_FLAGS (inst.instruction))
11131 narrow = !in_it_block ();
11133 narrow = in_it_block ();
11135 if (!inst.operands[1].isreg)
11137 /* For an immediate, we always generate a 32-bit opcode;
11138 section relaxation will shrink it later if possible. */
11139 if (inst.instruction < 0xffff)
11140 inst.instruction = THUMB_OP32 (inst.instruction);
11141 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11142 inst.instruction |= Rn << r0off;
11143 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11147 /* See if we can do this with a 16-bit instruction. */
11150 inst.instruction = THUMB_OP16 (inst.instruction);
11151 inst.instruction |= Rn;
11152 inst.instruction |= Rm << 3;
11156 constraint (inst.operands[1].shifted
11157 && inst.operands[1].immisreg,
11158 _("shift must be constant"));
11159 if (inst.instruction < 0xffff)
11160 inst.instruction = THUMB_OP32 (inst.instruction);
11161 inst.instruction |= Rn << r0off;
11162 encode_thumb32_shifted_operand (1);
11168 constraint (inst.instruction > 0xffff
11169 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11170 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11171 _("unshifted register required"));
11172 constraint (Rn > 7 || Rm > 7,
11175 inst.instruction = THUMB_OP16 (inst.instruction);
11176 inst.instruction |= Rn;
11177 inst.instruction |= Rm << 3;
11186 if (do_vfp_nsyn_mrs () == SUCCESS)
11189 Rd = inst.operands[0].reg;
11190 reject_bad_reg (Rd);
11191 inst.instruction |= Rd << 8;
11193 if (inst.operands[1].isreg)
11195 unsigned br = inst.operands[1].reg;
11196 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11197 as_bad (_("bad register for mrs"));
11199 inst.instruction |= br & (0xf << 16);
11200 inst.instruction |= (br & 0x300) >> 4;
11201 inst.instruction |= (br & SPSR_BIT) >> 2;
11205 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11207 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11209 /* PR gas/12698: The constraint is only applied for m_profile.
11210 If the user has specified -march=all, we want to ignore it as
11211 we are building for any CPU type, including non-m variants. */
11212 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11213 constraint ((flags != 0) && m_profile, _("selected processor does "
11214 "not support requested special purpose register"));
11217 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11219 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11220 _("'APSR', 'CPSR' or 'SPSR' expected"));
11222 inst.instruction |= (flags & SPSR_BIT) >> 2;
11223 inst.instruction |= inst.operands[1].imm & 0xff;
11224 inst.instruction |= 0xf0000;
11234 if (do_vfp_nsyn_msr () == SUCCESS)
11237 constraint (!inst.operands[1].isreg,
11238 _("Thumb encoding does not support an immediate here"));
11240 if (inst.operands[0].isreg)
11241 flags = (int)(inst.operands[0].reg);
11243 flags = inst.operands[0].imm;
11245 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11247 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11249 /* PR gas/12698: The constraint is only applied for m_profile.
11250 If the user has specified -march=all, we want to ignore it as
11251 we are building for any CPU type, including non-m variants. */
11252 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11253 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11254 && (bits & ~(PSR_s | PSR_f)) != 0)
11255 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11256 && bits != PSR_f)) && m_profile,
11257 _("selected processor does not support requested special "
11258 "purpose register"));
11261 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11262 "requested special purpose register"));
11264 Rn = inst.operands[1].reg;
11265 reject_bad_reg (Rn);
11267 inst.instruction |= (flags & SPSR_BIT) >> 2;
11268 inst.instruction |= (flags & 0xf0000) >> 8;
11269 inst.instruction |= (flags & 0x300) >> 4;
11270 inst.instruction |= (flags & 0xff);
11271 inst.instruction |= Rn << 16;
11277 bfd_boolean narrow;
11278 unsigned Rd, Rn, Rm;
11280 if (!inst.operands[2].present)
11281 inst.operands[2].reg = inst.operands[0].reg;
11283 Rd = inst.operands[0].reg;
11284 Rn = inst.operands[1].reg;
11285 Rm = inst.operands[2].reg;
11287 if (unified_syntax)
11289 if (inst.size_req == 4
11295 else if (inst.instruction == T_MNEM_muls)
11296 narrow = !in_it_block ();
11298 narrow = in_it_block ();
11302 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11303 constraint (Rn > 7 || Rm > 7,
11310 /* 16-bit MULS/Conditional MUL. */
11311 inst.instruction = THUMB_OP16 (inst.instruction);
11312 inst.instruction |= Rd;
11315 inst.instruction |= Rm << 3;
11317 inst.instruction |= Rn << 3;
11319 constraint (1, _("dest must overlap one source register"));
11323 constraint (inst.instruction != T_MNEM_mul,
11324 _("Thumb-2 MUL must not set flags"));
11326 inst.instruction = THUMB_OP32 (inst.instruction);
11327 inst.instruction |= Rd << 8;
11328 inst.instruction |= Rn << 16;
11329 inst.instruction |= Rm << 0;
11331 reject_bad_reg (Rd);
11332 reject_bad_reg (Rn);
11333 reject_bad_reg (Rm);
11340 unsigned RdLo, RdHi, Rn, Rm;
11342 RdLo = inst.operands[0].reg;
11343 RdHi = inst.operands[1].reg;
11344 Rn = inst.operands[2].reg;
11345 Rm = inst.operands[3].reg;
11347 reject_bad_reg (RdLo);
11348 reject_bad_reg (RdHi);
11349 reject_bad_reg (Rn);
11350 reject_bad_reg (Rm);
11352 inst.instruction |= RdLo << 12;
11353 inst.instruction |= RdHi << 8;
11354 inst.instruction |= Rn << 16;
11355 inst.instruction |= Rm;
11358 as_tsktsk (_("rdhi and rdlo must be different"));
11364 set_it_insn_type (NEUTRAL_IT_INSN);
11366 if (unified_syntax)
11368 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11370 inst.instruction = THUMB_OP32 (inst.instruction);
11371 inst.instruction |= inst.operands[0].imm;
11375 /* PR9722: Check for Thumb2 availability before
11376 generating a thumb2 nop instruction. */
11377 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11379 inst.instruction = THUMB_OP16 (inst.instruction);
11380 inst.instruction |= inst.operands[0].imm << 4;
11383 inst.instruction = 0x46c0;
11388 constraint (inst.operands[0].present,
11389 _("Thumb does not support NOP with hints"));
11390 inst.instruction = 0x46c0;
11397 if (unified_syntax)
11399 bfd_boolean narrow;
11401 if (THUMB_SETS_FLAGS (inst.instruction))
11402 narrow = !in_it_block ();
11404 narrow = in_it_block ();
11405 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11407 if (inst.size_req == 4)
11412 inst.instruction = THUMB_OP32 (inst.instruction);
11413 inst.instruction |= inst.operands[0].reg << 8;
11414 inst.instruction |= inst.operands[1].reg << 16;
11418 inst.instruction = THUMB_OP16 (inst.instruction);
11419 inst.instruction |= inst.operands[0].reg;
11420 inst.instruction |= inst.operands[1].reg << 3;
11425 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11427 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11429 inst.instruction = THUMB_OP16 (inst.instruction);
11430 inst.instruction |= inst.operands[0].reg;
11431 inst.instruction |= inst.operands[1].reg << 3;
11440 Rd = inst.operands[0].reg;
11441 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11443 reject_bad_reg (Rd);
11444 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11445 reject_bad_reg (Rn);
11447 inst.instruction |= Rd << 8;
11448 inst.instruction |= Rn << 16;
11450 if (!inst.operands[2].isreg)
11452 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11453 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11459 Rm = inst.operands[2].reg;
11460 reject_bad_reg (Rm);
11462 constraint (inst.operands[2].shifted
11463 && inst.operands[2].immisreg,
11464 _("shift must be constant"));
11465 encode_thumb32_shifted_operand (2);
11472 unsigned Rd, Rn, Rm;
11474 Rd = inst.operands[0].reg;
11475 Rn = inst.operands[1].reg;
11476 Rm = inst.operands[2].reg;
11478 reject_bad_reg (Rd);
11479 reject_bad_reg (Rn);
11480 reject_bad_reg (Rm);
11482 inst.instruction |= Rd << 8;
11483 inst.instruction |= Rn << 16;
11484 inst.instruction |= Rm;
11485 if (inst.operands[3].present)
11487 unsigned int val = inst.reloc.exp.X_add_number;
11488 constraint (inst.reloc.exp.X_op != O_constant,
11489 _("expression too complex"));
11490 inst.instruction |= (val & 0x1c) << 10;
11491 inst.instruction |= (val & 0x03) << 6;
11498 if (!inst.operands[3].present)
11502 inst.instruction &= ~0x00000020;
11504 /* PR 10168. Swap the Rm and Rn registers. */
11505 Rtmp = inst.operands[1].reg;
11506 inst.operands[1].reg = inst.operands[2].reg;
11507 inst.operands[2].reg = Rtmp;
11515 if (inst.operands[0].immisreg)
11516 reject_bad_reg (inst.operands[0].imm);
11518 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11522 do_t_push_pop (void)
11526 constraint (inst.operands[0].writeback,
11527 _("push/pop do not support {reglist}^"));
11528 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11529 _("expression too complex"));
11531 mask = inst.operands[0].imm;
11532 if ((mask & ~0xff) == 0)
11533 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11534 else if ((inst.instruction == T_MNEM_push
11535 && (mask & ~0xff) == 1 << REG_LR)
11536 || (inst.instruction == T_MNEM_pop
11537 && (mask & ~0xff) == 1 << REG_PC))
11539 inst.instruction = THUMB_OP16 (inst.instruction);
11540 inst.instruction |= THUMB_PP_PC_LR;
11541 inst.instruction |= mask & 0xff;
11543 else if (unified_syntax)
11545 inst.instruction = THUMB_OP32 (inst.instruction);
11546 encode_thumb2_ldmstm (13, mask, TRUE);
11550 inst.error = _("invalid register list to push/pop instruction");
11560 Rd = inst.operands[0].reg;
11561 Rm = inst.operands[1].reg;
11563 reject_bad_reg (Rd);
11564 reject_bad_reg (Rm);
11566 inst.instruction |= Rd << 8;
11567 inst.instruction |= Rm << 16;
11568 inst.instruction |= Rm;
11576 Rd = inst.operands[0].reg;
11577 Rm = inst.operands[1].reg;
11579 reject_bad_reg (Rd);
11580 reject_bad_reg (Rm);
11582 if (Rd <= 7 && Rm <= 7
11583 && inst.size_req != 4)
11585 inst.instruction = THUMB_OP16 (inst.instruction);
11586 inst.instruction |= Rd;
11587 inst.instruction |= Rm << 3;
11589 else if (unified_syntax)
11591 inst.instruction = THUMB_OP32 (inst.instruction);
11592 inst.instruction |= Rd << 8;
11593 inst.instruction |= Rm << 16;
11594 inst.instruction |= Rm;
11597 inst.error = BAD_HIREG;
11605 Rd = inst.operands[0].reg;
11606 Rm = inst.operands[1].reg;
11608 reject_bad_reg (Rd);
11609 reject_bad_reg (Rm);
11611 inst.instruction |= Rd << 8;
11612 inst.instruction |= Rm;
11620 Rd = inst.operands[0].reg;
11621 Rs = (inst.operands[1].present
11622 ? inst.operands[1].reg /* Rd, Rs, foo */
11623 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11625 reject_bad_reg (Rd);
11626 reject_bad_reg (Rs);
11627 if (inst.operands[2].isreg)
11628 reject_bad_reg (inst.operands[2].reg);
11630 inst.instruction |= Rd << 8;
11631 inst.instruction |= Rs << 16;
11632 if (!inst.operands[2].isreg)
11634 bfd_boolean narrow;
11636 if ((inst.instruction & 0x00100000) != 0)
11637 narrow = !in_it_block ();
11639 narrow = in_it_block ();
11641 if (Rd > 7 || Rs > 7)
11644 if (inst.size_req == 4 || !unified_syntax)
11647 if (inst.reloc.exp.X_op != O_constant
11648 || inst.reloc.exp.X_add_number != 0)
11651 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11652 relaxation, but it doesn't seem worth the hassle. */
11655 inst.reloc.type = BFD_RELOC_UNUSED;
11656 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11657 inst.instruction |= Rs << 3;
11658 inst.instruction |= Rd;
11662 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11663 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11667 encode_thumb32_shifted_operand (2);
11673 set_it_insn_type (OUTSIDE_IT_INSN);
11674 if (inst.operands[0].imm)
11675 inst.instruction |= 0x8;
11681 if (!inst.operands[1].present)
11682 inst.operands[1].reg = inst.operands[0].reg;
11684 if (unified_syntax)
11686 bfd_boolean narrow;
11689 switch (inst.instruction)
11692 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11694 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11696 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11698 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11702 if (THUMB_SETS_FLAGS (inst.instruction))
11703 narrow = !in_it_block ();
11705 narrow = in_it_block ();
11706 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11708 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11710 if (inst.operands[2].isreg
11711 && (inst.operands[1].reg != inst.operands[0].reg
11712 || inst.operands[2].reg > 7))
11714 if (inst.size_req == 4)
11717 reject_bad_reg (inst.operands[0].reg);
11718 reject_bad_reg (inst.operands[1].reg);
11722 if (inst.operands[2].isreg)
11724 reject_bad_reg (inst.operands[2].reg);
11725 inst.instruction = THUMB_OP32 (inst.instruction);
11726 inst.instruction |= inst.operands[0].reg << 8;
11727 inst.instruction |= inst.operands[1].reg << 16;
11728 inst.instruction |= inst.operands[2].reg;
11730 /* PR 12854: Error on extraneous shifts. */
11731 constraint (inst.operands[2].shifted,
11732 _("extraneous shift as part of operand to shift insn"));
11736 inst.operands[1].shifted = 1;
11737 inst.operands[1].shift_kind = shift_kind;
11738 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11739 ? T_MNEM_movs : T_MNEM_mov);
11740 inst.instruction |= inst.operands[0].reg << 8;
11741 encode_thumb32_shifted_operand (1);
11742 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11743 inst.reloc.type = BFD_RELOC_UNUSED;
11748 if (inst.operands[2].isreg)
11750 switch (shift_kind)
11752 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11753 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11754 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11755 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11759 inst.instruction |= inst.operands[0].reg;
11760 inst.instruction |= inst.operands[2].reg << 3;
11762 /* PR 12854: Error on extraneous shifts. */
11763 constraint (inst.operands[2].shifted,
11764 _("extraneous shift as part of operand to shift insn"));
11768 switch (shift_kind)
11770 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11771 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11772 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11775 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11776 inst.instruction |= inst.operands[0].reg;
11777 inst.instruction |= inst.operands[1].reg << 3;
11783 constraint (inst.operands[0].reg > 7
11784 || inst.operands[1].reg > 7, BAD_HIREG);
11785 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11787 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11789 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11790 constraint (inst.operands[0].reg != inst.operands[1].reg,
11791 _("source1 and dest must be same register"));
11793 switch (inst.instruction)
11795 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11796 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11797 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11798 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11802 inst.instruction |= inst.operands[0].reg;
11803 inst.instruction |= inst.operands[2].reg << 3;
11805 /* PR 12854: Error on extraneous shifts. */
11806 constraint (inst.operands[2].shifted,
11807 _("extraneous shift as part of operand to shift insn"));
11811 switch (inst.instruction)
11813 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11814 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11815 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11816 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11819 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11820 inst.instruction |= inst.operands[0].reg;
11821 inst.instruction |= inst.operands[1].reg << 3;
11829 unsigned Rd, Rn, Rm;
11831 Rd = inst.operands[0].reg;
11832 Rn = inst.operands[1].reg;
11833 Rm = inst.operands[2].reg;
11835 reject_bad_reg (Rd);
11836 reject_bad_reg (Rn);
11837 reject_bad_reg (Rm);
11839 inst.instruction |= Rd << 8;
11840 inst.instruction |= Rn << 16;
11841 inst.instruction |= Rm;
11847 unsigned Rd, Rn, Rm;
11849 Rd = inst.operands[0].reg;
11850 Rm = inst.operands[1].reg;
11851 Rn = inst.operands[2].reg;
11853 reject_bad_reg (Rd);
11854 reject_bad_reg (Rn);
11855 reject_bad_reg (Rm);
11857 inst.instruction |= Rd << 8;
11858 inst.instruction |= Rn << 16;
11859 inst.instruction |= Rm;
11865 unsigned int value = inst.reloc.exp.X_add_number;
11866 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11867 _("SMC is not permitted on this architecture"));
11868 constraint (inst.reloc.exp.X_op != O_constant,
11869 _("expression too complex"));
11870 inst.reloc.type = BFD_RELOC_UNUSED;
11871 inst.instruction |= (value & 0xf000) >> 12;
11872 inst.instruction |= (value & 0x0ff0);
11873 inst.instruction |= (value & 0x000f) << 16;
11879 unsigned int value = inst.reloc.exp.X_add_number;
11881 inst.reloc.type = BFD_RELOC_UNUSED;
11882 inst.instruction |= (value & 0x0fff);
11883 inst.instruction |= (value & 0xf000) << 4;
11887 do_t_ssat_usat (int bias)
11891 Rd = inst.operands[0].reg;
11892 Rn = inst.operands[2].reg;
11894 reject_bad_reg (Rd);
11895 reject_bad_reg (Rn);
11897 inst.instruction |= Rd << 8;
11898 inst.instruction |= inst.operands[1].imm - bias;
11899 inst.instruction |= Rn << 16;
11901 if (inst.operands[3].present)
11903 offsetT shift_amount = inst.reloc.exp.X_add_number;
11905 inst.reloc.type = BFD_RELOC_UNUSED;
11907 constraint (inst.reloc.exp.X_op != O_constant,
11908 _("expression too complex"));
11910 if (shift_amount != 0)
11912 constraint (shift_amount > 31,
11913 _("shift expression is too large"));
11915 if (inst.operands[3].shift_kind == SHIFT_ASR)
11916 inst.instruction |= 0x00200000; /* sh bit. */
11918 inst.instruction |= (shift_amount & 0x1c) << 10;
11919 inst.instruction |= (shift_amount & 0x03) << 6;
11927 do_t_ssat_usat (1);
11935 Rd = inst.operands[0].reg;
11936 Rn = inst.operands[2].reg;
11938 reject_bad_reg (Rd);
11939 reject_bad_reg (Rn);
11941 inst.instruction |= Rd << 8;
11942 inst.instruction |= inst.operands[1].imm - 1;
11943 inst.instruction |= Rn << 16;
11949 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11950 || inst.operands[2].postind || inst.operands[2].writeback
11951 || inst.operands[2].immisreg || inst.operands[2].shifted
11952 || inst.operands[2].negative,
11955 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11957 inst.instruction |= inst.operands[0].reg << 8;
11958 inst.instruction |= inst.operands[1].reg << 12;
11959 inst.instruction |= inst.operands[2].reg << 16;
11960 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11966 if (!inst.operands[2].present)
11967 inst.operands[2].reg = inst.operands[1].reg + 1;
11969 constraint (inst.operands[0].reg == inst.operands[1].reg
11970 || inst.operands[0].reg == inst.operands[2].reg
11971 || inst.operands[0].reg == inst.operands[3].reg,
11974 inst.instruction |= inst.operands[0].reg;
11975 inst.instruction |= inst.operands[1].reg << 12;
11976 inst.instruction |= inst.operands[2].reg << 8;
11977 inst.instruction |= inst.operands[3].reg << 16;
11983 unsigned Rd, Rn, Rm;
11985 Rd = inst.operands[0].reg;
11986 Rn = inst.operands[1].reg;
11987 Rm = inst.operands[2].reg;
11989 reject_bad_reg (Rd);
11990 reject_bad_reg (Rn);
11991 reject_bad_reg (Rm);
11993 inst.instruction |= Rd << 8;
11994 inst.instruction |= Rn << 16;
11995 inst.instruction |= Rm;
11996 inst.instruction |= inst.operands[3].imm << 4;
12004 Rd = inst.operands[0].reg;
12005 Rm = inst.operands[1].reg;
12007 reject_bad_reg (Rd);
12008 reject_bad_reg (Rm);
12010 if (inst.instruction <= 0xffff
12011 && inst.size_req != 4
12012 && Rd <= 7 && Rm <= 7
12013 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12015 inst.instruction = THUMB_OP16 (inst.instruction);
12016 inst.instruction |= Rd;
12017 inst.instruction |= Rm << 3;
12019 else if (unified_syntax)
12021 if (inst.instruction <= 0xffff)
12022 inst.instruction = THUMB_OP32 (inst.instruction);
12023 inst.instruction |= Rd << 8;
12024 inst.instruction |= Rm;
12025 inst.instruction |= inst.operands[2].imm << 4;
12029 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12030 _("Thumb encoding does not support rotation"));
12031 constraint (1, BAD_HIREG);
12038 /* We have to do the following check manually as ARM_EXT_OS only applies
12040 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12042 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12043 /* This only applies to the v6m howver, not later architectures. */
12044 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12045 as_bad (_("SVC is not permitted on this architecture"));
12046 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12049 inst.reloc.type = BFD_RELOC_ARM_SWI;
12058 half = (inst.instruction & 0x10) != 0;
12059 set_it_insn_type_last ();
12060 constraint (inst.operands[0].immisreg,
12061 _("instruction requires register index"));
12063 Rn = inst.operands[0].reg;
12064 Rm = inst.operands[0].imm;
12066 constraint (Rn == REG_SP, BAD_SP);
12067 reject_bad_reg (Rm);
12069 constraint (!half && inst.operands[0].shifted,
12070 _("instruction does not allow shifted index"));
12071 inst.instruction |= (Rn << 16) | Rm;
12077 do_t_ssat_usat (0);
12085 Rd = inst.operands[0].reg;
12086 Rn = inst.operands[2].reg;
12088 reject_bad_reg (Rd);
12089 reject_bad_reg (Rn);
12091 inst.instruction |= Rd << 8;
12092 inst.instruction |= inst.operands[1].imm;
12093 inst.instruction |= Rn << 16;
12096 /* Neon instruction encoder helpers. */
12098 /* Encodings for the different types for various Neon opcodes. */
12100 /* An "invalid" code for the following tables. */
12103 struct neon_tab_entry
12106 unsigned float_or_poly;
12107 unsigned scalar_or_imm;
12110 /* Map overloaded Neon opcodes to their respective encodings. */
12111 #define NEON_ENC_TAB \
12112 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12113 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12114 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12115 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12116 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12117 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12118 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12119 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12120 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12121 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12122 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12123 /* Register variants of the following two instructions are encoded as
12124 vcge / vcgt with the operands reversed. */ \
12125 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12126 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12127 X(vfma, N_INV, 0x0000c10, N_INV), \
12128 X(vfms, N_INV, 0x0200c10, N_INV), \
12129 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12130 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12131 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12132 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12133 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12134 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12135 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12136 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12137 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12138 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12139 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12140 X(vshl, 0x0000400, N_INV, 0x0800510), \
12141 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12142 X(vand, 0x0000110, N_INV, 0x0800030), \
12143 X(vbic, 0x0100110, N_INV, 0x0800030), \
12144 X(veor, 0x1000110, N_INV, N_INV), \
12145 X(vorn, 0x0300110, N_INV, 0x0800010), \
12146 X(vorr, 0x0200110, N_INV, 0x0800010), \
12147 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12148 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12149 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12150 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12151 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12152 X(vst1, 0x0000000, 0x0800000, N_INV), \
12153 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12154 X(vst2, 0x0000100, 0x0800100, N_INV), \
12155 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12156 X(vst3, 0x0000200, 0x0800200, N_INV), \
12157 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12158 X(vst4, 0x0000300, 0x0800300, N_INV), \
12159 X(vmovn, 0x1b20200, N_INV, N_INV), \
12160 X(vtrn, 0x1b20080, N_INV, N_INV), \
12161 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12162 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12163 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12164 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12165 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12166 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12167 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12168 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12169 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12170 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12171 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12175 #define X(OPC,I,F,S) N_MNEM_##OPC
12180 static const struct neon_tab_entry neon_enc_tab[] =
12182 #define X(OPC,I,F,S) { (I), (F), (S) }
12187 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12188 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12189 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12190 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12191 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12192 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12193 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12194 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12195 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12196 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12197 #define NEON_ENC_SINGLE_(X) \
12198 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12199 #define NEON_ENC_DOUBLE_(X) \
12200 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12202 #define NEON_ENCODE(type, inst) \
12205 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12206 inst.is_neon = 1; \
12210 #define check_neon_suffixes \
12213 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12215 as_bad (_("invalid neon suffix for non neon instruction")); \
12221 /* Define shapes for instruction operands. The following mnemonic characters
12222 are used in this table:
12224 F - VFP S<n> register
12225 D - Neon D<n> register
12226 Q - Neon Q<n> register
12230 L - D<n> register list
12232 This table is used to generate various data:
12233 - enumerations of the form NS_DDR to be used as arguments to
12235 - a table classifying shapes into single, double, quad, mixed.
12236 - a table used to drive neon_select_shape. */
12238 #define NEON_SHAPE_DEF \
12239 X(3, (D, D, D), DOUBLE), \
12240 X(3, (Q, Q, Q), QUAD), \
12241 X(3, (D, D, I), DOUBLE), \
12242 X(3, (Q, Q, I), QUAD), \
12243 X(3, (D, D, S), DOUBLE), \
12244 X(3, (Q, Q, S), QUAD), \
12245 X(2, (D, D), DOUBLE), \
12246 X(2, (Q, Q), QUAD), \
12247 X(2, (D, S), DOUBLE), \
12248 X(2, (Q, S), QUAD), \
12249 X(2, (D, R), DOUBLE), \
12250 X(2, (Q, R), QUAD), \
12251 X(2, (D, I), DOUBLE), \
12252 X(2, (Q, I), QUAD), \
12253 X(3, (D, L, D), DOUBLE), \
12254 X(2, (D, Q), MIXED), \
12255 X(2, (Q, D), MIXED), \
12256 X(3, (D, Q, I), MIXED), \
12257 X(3, (Q, D, I), MIXED), \
12258 X(3, (Q, D, D), MIXED), \
12259 X(3, (D, Q, Q), MIXED), \
12260 X(3, (Q, Q, D), MIXED), \
12261 X(3, (Q, D, S), MIXED), \
12262 X(3, (D, Q, S), MIXED), \
12263 X(4, (D, D, D, I), DOUBLE), \
12264 X(4, (Q, Q, Q, I), QUAD), \
12265 X(2, (F, F), SINGLE), \
12266 X(3, (F, F, F), SINGLE), \
12267 X(2, (F, I), SINGLE), \
12268 X(2, (F, D), MIXED), \
12269 X(2, (D, F), MIXED), \
12270 X(3, (F, F, I), MIXED), \
12271 X(4, (R, R, F, F), SINGLE), \
12272 X(4, (F, F, R, R), SINGLE), \
12273 X(3, (D, R, R), DOUBLE), \
12274 X(3, (R, R, D), DOUBLE), \
12275 X(2, (S, R), SINGLE), \
12276 X(2, (R, S), SINGLE), \
12277 X(2, (F, R), SINGLE), \
12278 X(2, (R, F), SINGLE)
12280 #define S2(A,B) NS_##A##B
12281 #define S3(A,B,C) NS_##A##B##C
12282 #define S4(A,B,C,D) NS_##A##B##C##D
12284 #define X(N, L, C) S##N L
12297 enum neon_shape_class
12305 #define X(N, L, C) SC_##C
12307 static enum neon_shape_class neon_shape_class[] =
12325 /* Register widths of above. */
12326 static unsigned neon_shape_el_size[] =
12337 struct neon_shape_info
12340 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12343 #define S2(A,B) { SE_##A, SE_##B }
12344 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12345 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12347 #define X(N, L, C) { N, S##N L }
12349 static struct neon_shape_info neon_shape_tab[] =
12359 /* Bit masks used in type checking given instructions.
12360 'N_EQK' means the type must be the same as (or based on in some way) the key
12361 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12362 set, various other bits can be set as well in order to modify the meaning of
12363 the type constraint. */
12365 enum neon_type_mask
12388 N_KEY = 0x1000000, /* Key element (main type specifier). */
12389 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12390 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12391 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12392 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12393 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12394 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12395 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12396 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12397 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12399 N_MAX_NONSPECIAL = N_F64
12402 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12404 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12405 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12406 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12407 #define N_SUF_32 (N_SU_32 | N_F32)
12408 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12409 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12411 /* Pass this as the first type argument to neon_check_type to ignore types
12413 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12415 /* Select a "shape" for the current instruction (describing register types or
12416 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12417 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12418 function of operand parsing, so this function doesn't need to be called.
12419 Shapes should be listed in order of decreasing length. */
12421 static enum neon_shape
12422 neon_select_shape (enum neon_shape shape, ...)
12425 enum neon_shape first_shape = shape;
12427 /* Fix missing optional operands. FIXME: we don't know at this point how
12428 many arguments we should have, so this makes the assumption that we have
12429 > 1. This is true of all current Neon opcodes, I think, but may not be
12430 true in the future. */
12431 if (!inst.operands[1].present)
12432 inst.operands[1] = inst.operands[0];
12434 va_start (ap, shape);
12436 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12441 for (j = 0; j < neon_shape_tab[shape].els; j++)
12443 if (!inst.operands[j].present)
12449 switch (neon_shape_tab[shape].el[j])
12452 if (!(inst.operands[j].isreg
12453 && inst.operands[j].isvec
12454 && inst.operands[j].issingle
12455 && !inst.operands[j].isquad))
12460 if (!(inst.operands[j].isreg
12461 && inst.operands[j].isvec
12462 && !inst.operands[j].isquad
12463 && !inst.operands[j].issingle))
12468 if (!(inst.operands[j].isreg
12469 && !inst.operands[j].isvec))
12474 if (!(inst.operands[j].isreg
12475 && inst.operands[j].isvec
12476 && inst.operands[j].isquad
12477 && !inst.operands[j].issingle))
12482 if (!(!inst.operands[j].isreg
12483 && !inst.operands[j].isscalar))
12488 if (!(!inst.operands[j].isreg
12489 && inst.operands[j].isscalar))
12499 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12500 /* We've matched all the entries in the shape table, and we don't
12501 have any left over operands which have not been matched. */
12507 if (shape == NS_NULL && first_shape != NS_NULL)
12508 first_error (_("invalid instruction shape"));
12513 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12514 means the Q bit should be set). */
12517 neon_quad (enum neon_shape shape)
12519 return neon_shape_class[shape] == SC_QUAD;
12523 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12526 /* Allow modification to be made to types which are constrained to be
12527 based on the key element, based on bits set alongside N_EQK. */
12528 if ((typebits & N_EQK) != 0)
12530 if ((typebits & N_HLF) != 0)
12532 else if ((typebits & N_DBL) != 0)
12534 if ((typebits & N_SGN) != 0)
12535 *g_type = NT_signed;
12536 else if ((typebits & N_UNS) != 0)
12537 *g_type = NT_unsigned;
12538 else if ((typebits & N_INT) != 0)
12539 *g_type = NT_integer;
12540 else if ((typebits & N_FLT) != 0)
12541 *g_type = NT_float;
12542 else if ((typebits & N_SIZ) != 0)
12543 *g_type = NT_untyped;
12547 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12548 operand type, i.e. the single type specified in a Neon instruction when it
12549 is the only one given. */
12551 static struct neon_type_el
12552 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12554 struct neon_type_el dest = *key;
12556 gas_assert ((thisarg & N_EQK) != 0);
12558 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12563 /* Convert Neon type and size into compact bitmask representation. */
12565 static enum neon_type_mask
12566 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12573 case 8: return N_8;
12574 case 16: return N_16;
12575 case 32: return N_32;
12576 case 64: return N_64;
12584 case 8: return N_I8;
12585 case 16: return N_I16;
12586 case 32: return N_I32;
12587 case 64: return N_I64;
12595 case 16: return N_F16;
12596 case 32: return N_F32;
12597 case 64: return N_F64;
12605 case 8: return N_P8;
12606 case 16: return N_P16;
12614 case 8: return N_S8;
12615 case 16: return N_S16;
12616 case 32: return N_S32;
12617 case 64: return N_S64;
12625 case 8: return N_U8;
12626 case 16: return N_U16;
12627 case 32: return N_U32;
12628 case 64: return N_U64;
12639 /* Convert compact Neon bitmask type representation to a type and size. Only
12640 handles the case where a single bit is set in the mask. */
12643 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12644 enum neon_type_mask mask)
12646 if ((mask & N_EQK) != 0)
12649 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12651 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12653 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12655 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12660 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12662 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12663 *type = NT_unsigned;
12664 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12665 *type = NT_integer;
12666 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12667 *type = NT_untyped;
12668 else if ((mask & (N_P8 | N_P16)) != 0)
12670 else if ((mask & (N_F32 | N_F64)) != 0)
12678 /* Modify a bitmask of allowed types. This is only needed for type
12682 modify_types_allowed (unsigned allowed, unsigned mods)
12685 enum neon_el_type type;
12691 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12693 if (el_type_of_type_chk (&type, &size,
12694 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12696 neon_modify_type_size (mods, &type, &size);
12697 destmask |= type_chk_of_el_type (type, size);
12704 /* Check type and return type classification.
12705 The manual states (paraphrase): If one datatype is given, it indicates the
12707 - the second operand, if there is one
12708 - the operand, if there is no second operand
12709 - the result, if there are no operands.
12710 This isn't quite good enough though, so we use a concept of a "key" datatype
12711 which is set on a per-instruction basis, which is the one which matters when
12712 only one data type is written.
12713 Note: this function has side-effects (e.g. filling in missing operands). All
12714 Neon instructions should call it before performing bit encoding. */
12716 static struct neon_type_el
12717 neon_check_type (unsigned els, enum neon_shape ns, ...)
12720 unsigned i, pass, key_el = 0;
12721 unsigned types[NEON_MAX_TYPE_ELS];
12722 enum neon_el_type k_type = NT_invtype;
12723 unsigned k_size = -1u;
12724 struct neon_type_el badtype = {NT_invtype, -1};
12725 unsigned key_allowed = 0;
12727 /* Optional registers in Neon instructions are always (not) in operand 1.
12728 Fill in the missing operand here, if it was omitted. */
12729 if (els > 1 && !inst.operands[1].present)
12730 inst.operands[1] = inst.operands[0];
12732 /* Suck up all the varargs. */
12734 for (i = 0; i < els; i++)
12736 unsigned thisarg = va_arg (ap, unsigned);
12737 if (thisarg == N_IGNORE_TYPE)
12742 types[i] = thisarg;
12743 if ((thisarg & N_KEY) != 0)
12748 if (inst.vectype.elems > 0)
12749 for (i = 0; i < els; i++)
12750 if (inst.operands[i].vectype.type != NT_invtype)
12752 first_error (_("types specified in both the mnemonic and operands"));
12756 /* Duplicate inst.vectype elements here as necessary.
12757 FIXME: No idea if this is exactly the same as the ARM assembler,
12758 particularly when an insn takes one register and one non-register
12760 if (inst.vectype.elems == 1 && els > 1)
12763 inst.vectype.elems = els;
12764 inst.vectype.el[key_el] = inst.vectype.el[0];
12765 for (j = 0; j < els; j++)
12767 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12770 else if (inst.vectype.elems == 0 && els > 0)
12773 /* No types were given after the mnemonic, so look for types specified
12774 after each operand. We allow some flexibility here; as long as the
12775 "key" operand has a type, we can infer the others. */
12776 for (j = 0; j < els; j++)
12777 if (inst.operands[j].vectype.type != NT_invtype)
12778 inst.vectype.el[j] = inst.operands[j].vectype;
12780 if (inst.operands[key_el].vectype.type != NT_invtype)
12782 for (j = 0; j < els; j++)
12783 if (inst.operands[j].vectype.type == NT_invtype)
12784 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12789 first_error (_("operand types can't be inferred"));
12793 else if (inst.vectype.elems != els)
12795 first_error (_("type specifier has the wrong number of parts"));
12799 for (pass = 0; pass < 2; pass++)
12801 for (i = 0; i < els; i++)
12803 unsigned thisarg = types[i];
12804 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12805 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12806 enum neon_el_type g_type = inst.vectype.el[i].type;
12807 unsigned g_size = inst.vectype.el[i].size;
12809 /* Decay more-specific signed & unsigned types to sign-insensitive
12810 integer types if sign-specific variants are unavailable. */
12811 if ((g_type == NT_signed || g_type == NT_unsigned)
12812 && (types_allowed & N_SU_ALL) == 0)
12813 g_type = NT_integer;
12815 /* If only untyped args are allowed, decay any more specific types to
12816 them. Some instructions only care about signs for some element
12817 sizes, so handle that properly. */
12818 if ((g_size == 8 && (types_allowed & N_8) != 0)
12819 || (g_size == 16 && (types_allowed & N_16) != 0)
12820 || (g_size == 32 && (types_allowed & N_32) != 0)
12821 || (g_size == 64 && (types_allowed & N_64) != 0))
12822 g_type = NT_untyped;
12826 if ((thisarg & N_KEY) != 0)
12830 key_allowed = thisarg & ~N_KEY;
12835 if ((thisarg & N_VFP) != 0)
12837 enum neon_shape_el regshape;
12838 unsigned regwidth, match;
12840 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12843 first_error (_("invalid instruction shape"));
12846 regshape = neon_shape_tab[ns].el[i];
12847 regwidth = neon_shape_el_size[regshape];
12849 /* In VFP mode, operands must match register widths. If we
12850 have a key operand, use its width, else use the width of
12851 the current operand. */
12857 if (regwidth != match)
12859 first_error (_("operand size must match register width"));
12864 if ((thisarg & N_EQK) == 0)
12866 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12868 if ((given_type & types_allowed) == 0)
12870 first_error (_("bad type in Neon instruction"));
12876 enum neon_el_type mod_k_type = k_type;
12877 unsigned mod_k_size = k_size;
12878 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12879 if (g_type != mod_k_type || g_size != mod_k_size)
12881 first_error (_("inconsistent types in Neon instruction"));
12889 return inst.vectype.el[key_el];
12892 /* Neon-style VFP instruction forwarding. */
12894 /* Thumb VFP instructions have 0xE in the condition field. */
12897 do_vfp_cond_or_thumb (void)
12902 inst.instruction |= 0xe0000000;
12904 inst.instruction |= inst.cond << 28;
12907 /* Look up and encode a simple mnemonic, for use as a helper function for the
12908 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12909 etc. It is assumed that operand parsing has already been done, and that the
12910 operands are in the form expected by the given opcode (this isn't necessarily
12911 the same as the form in which they were parsed, hence some massaging must
12912 take place before this function is called).
12913 Checks current arch version against that in the looked-up opcode. */
12916 do_vfp_nsyn_opcode (const char *opname)
12918 const struct asm_opcode *opcode;
12920 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12925 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12926 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12933 inst.instruction = opcode->tvalue;
12934 opcode->tencode ();
12938 inst.instruction = (inst.cond << 28) | opcode->avalue;
12939 opcode->aencode ();
12944 do_vfp_nsyn_add_sub (enum neon_shape rs)
12946 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12951 do_vfp_nsyn_opcode ("fadds");
12953 do_vfp_nsyn_opcode ("fsubs");
12958 do_vfp_nsyn_opcode ("faddd");
12960 do_vfp_nsyn_opcode ("fsubd");
12964 /* Check operand types to see if this is a VFP instruction, and if so call
12968 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12970 enum neon_shape rs;
12971 struct neon_type_el et;
12976 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12977 et = neon_check_type (2, rs,
12978 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12982 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12983 et = neon_check_type (3, rs,
12984 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12991 if (et.type != NT_invtype)
13002 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13004 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13009 do_vfp_nsyn_opcode ("fmacs");
13011 do_vfp_nsyn_opcode ("fnmacs");
13016 do_vfp_nsyn_opcode ("fmacd");
13018 do_vfp_nsyn_opcode ("fnmacd");
13023 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13025 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13030 do_vfp_nsyn_opcode ("ffmas");
13032 do_vfp_nsyn_opcode ("ffnmas");
13037 do_vfp_nsyn_opcode ("ffmad");
13039 do_vfp_nsyn_opcode ("ffnmad");
13044 do_vfp_nsyn_mul (enum neon_shape rs)
13047 do_vfp_nsyn_opcode ("fmuls");
13049 do_vfp_nsyn_opcode ("fmuld");
13053 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13055 int is_neg = (inst.instruction & 0x80) != 0;
13056 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13061 do_vfp_nsyn_opcode ("fnegs");
13063 do_vfp_nsyn_opcode ("fabss");
13068 do_vfp_nsyn_opcode ("fnegd");
13070 do_vfp_nsyn_opcode ("fabsd");
13074 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13075 insns belong to Neon, and are handled elsewhere. */
13078 do_vfp_nsyn_ldm_stm (int is_dbmode)
13080 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13084 do_vfp_nsyn_opcode ("fldmdbs");
13086 do_vfp_nsyn_opcode ("fldmias");
13091 do_vfp_nsyn_opcode ("fstmdbs");
13093 do_vfp_nsyn_opcode ("fstmias");
13098 do_vfp_nsyn_sqrt (void)
13100 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13101 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13104 do_vfp_nsyn_opcode ("fsqrts");
13106 do_vfp_nsyn_opcode ("fsqrtd");
13110 do_vfp_nsyn_div (void)
13112 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13113 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13114 N_F32 | N_F64 | N_KEY | N_VFP);
13117 do_vfp_nsyn_opcode ("fdivs");
13119 do_vfp_nsyn_opcode ("fdivd");
13123 do_vfp_nsyn_nmul (void)
13125 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13126 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13127 N_F32 | N_F64 | N_KEY | N_VFP);
13131 NEON_ENCODE (SINGLE, inst);
13132 do_vfp_sp_dyadic ();
13136 NEON_ENCODE (DOUBLE, inst);
13137 do_vfp_dp_rd_rn_rm ();
13139 do_vfp_cond_or_thumb ();
13143 do_vfp_nsyn_cmp (void)
13145 if (inst.operands[1].isreg)
13147 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13148 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13152 NEON_ENCODE (SINGLE, inst);
13153 do_vfp_sp_monadic ();
13157 NEON_ENCODE (DOUBLE, inst);
13158 do_vfp_dp_rd_rm ();
13163 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13164 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13166 switch (inst.instruction & 0x0fffffff)
13169 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13172 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13180 NEON_ENCODE (SINGLE, inst);
13181 do_vfp_sp_compare_z ();
13185 NEON_ENCODE (DOUBLE, inst);
13189 do_vfp_cond_or_thumb ();
13193 nsyn_insert_sp (void)
13195 inst.operands[1] = inst.operands[0];
13196 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13197 inst.operands[0].reg = REG_SP;
13198 inst.operands[0].isreg = 1;
13199 inst.operands[0].writeback = 1;
13200 inst.operands[0].present = 1;
13204 do_vfp_nsyn_push (void)
13207 if (inst.operands[1].issingle)
13208 do_vfp_nsyn_opcode ("fstmdbs");
13210 do_vfp_nsyn_opcode ("fstmdbd");
13214 do_vfp_nsyn_pop (void)
13217 if (inst.operands[1].issingle)
13218 do_vfp_nsyn_opcode ("fldmias");
13220 do_vfp_nsyn_opcode ("fldmiad");
13223 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13224 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13227 neon_dp_fixup (struct arm_it* insn)
13229 unsigned int i = insn->instruction;
13234 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13245 insn->instruction = i;
13248 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13252 neon_logbits (unsigned x)
13254 return ffs (x) - 4;
13257 #define LOW4(R) ((R) & 0xf)
13258 #define HI1(R) (((R) >> 4) & 1)
13260 /* Encode insns with bit pattern:
13262 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13263 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13265 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13266 different meaning for some instruction. */
13269 neon_three_same (int isquad, int ubit, int size)
13271 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13272 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13273 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13274 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13275 inst.instruction |= LOW4 (inst.operands[2].reg);
13276 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13277 inst.instruction |= (isquad != 0) << 6;
13278 inst.instruction |= (ubit != 0) << 24;
13280 inst.instruction |= neon_logbits (size) << 20;
13282 neon_dp_fixup (&inst);
13285 /* Encode instructions of the form:
13287 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13288 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13290 Don't write size if SIZE == -1. */
13293 neon_two_same (int qbit, int ubit, int size)
13295 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13296 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13297 inst.instruction |= LOW4 (inst.operands[1].reg);
13298 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13299 inst.instruction |= (qbit != 0) << 6;
13300 inst.instruction |= (ubit != 0) << 24;
13303 inst.instruction |= neon_logbits (size) << 18;
13305 neon_dp_fixup (&inst);
13308 /* Neon instruction encoders, in approximate order of appearance. */
13311 do_neon_dyadic_i_su (void)
13313 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13314 struct neon_type_el et = neon_check_type (3, rs,
13315 N_EQK, N_EQK, N_SU_32 | N_KEY);
13316 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13320 do_neon_dyadic_i64_su (void)
13322 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13323 struct neon_type_el et = neon_check_type (3, rs,
13324 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13325 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13329 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13332 unsigned size = et.size >> 3;
13333 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13334 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13335 inst.instruction |= LOW4 (inst.operands[1].reg);
13336 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13337 inst.instruction |= (isquad != 0) << 6;
13338 inst.instruction |= immbits << 16;
13339 inst.instruction |= (size >> 3) << 7;
13340 inst.instruction |= (size & 0x7) << 19;
13342 inst.instruction |= (uval != 0) << 24;
13344 neon_dp_fixup (&inst);
13348 do_neon_shl_imm (void)
13350 if (!inst.operands[2].isreg)
13352 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13353 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13354 NEON_ENCODE (IMMED, inst);
13355 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13359 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13360 struct neon_type_el et = neon_check_type (3, rs,
13361 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13364 /* VSHL/VQSHL 3-register variants have syntax such as:
13366 whereas other 3-register operations encoded by neon_three_same have
13369 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13371 tmp = inst.operands[2].reg;
13372 inst.operands[2].reg = inst.operands[1].reg;
13373 inst.operands[1].reg = tmp;
13374 NEON_ENCODE (INTEGER, inst);
13375 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13380 do_neon_qshl_imm (void)
13382 if (!inst.operands[2].isreg)
13384 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13385 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13387 NEON_ENCODE (IMMED, inst);
13388 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13389 inst.operands[2].imm);
13393 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13394 struct neon_type_el et = neon_check_type (3, rs,
13395 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13398 /* See note in do_neon_shl_imm. */
13399 tmp = inst.operands[2].reg;
13400 inst.operands[2].reg = inst.operands[1].reg;
13401 inst.operands[1].reg = tmp;
13402 NEON_ENCODE (INTEGER, inst);
13403 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13408 do_neon_rshl (void)
13410 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13411 struct neon_type_el et = neon_check_type (3, rs,
13412 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13415 tmp = inst.operands[2].reg;
13416 inst.operands[2].reg = inst.operands[1].reg;
13417 inst.operands[1].reg = tmp;
13418 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13422 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13424 /* Handle .I8 pseudo-instructions. */
13427 /* Unfortunately, this will make everything apart from zero out-of-range.
13428 FIXME is this the intended semantics? There doesn't seem much point in
13429 accepting .I8 if so. */
13430 immediate |= immediate << 8;
13436 if (immediate == (immediate & 0x000000ff))
13438 *immbits = immediate;
13441 else if (immediate == (immediate & 0x0000ff00))
13443 *immbits = immediate >> 8;
13446 else if (immediate == (immediate & 0x00ff0000))
13448 *immbits = immediate >> 16;
13451 else if (immediate == (immediate & 0xff000000))
13453 *immbits = immediate >> 24;
13456 if ((immediate & 0xffff) != (immediate >> 16))
13457 goto bad_immediate;
13458 immediate &= 0xffff;
13461 if (immediate == (immediate & 0x000000ff))
13463 *immbits = immediate;
13466 else if (immediate == (immediate & 0x0000ff00))
13468 *immbits = immediate >> 8;
13473 first_error (_("immediate value out of range"));
13477 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13481 neon_bits_same_in_bytes (unsigned imm)
13483 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13484 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13485 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13486 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13489 /* For immediate of above form, return 0bABCD. */
13492 neon_squash_bits (unsigned imm)
13494 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13495 | ((imm & 0x01000000) >> 21);
13498 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13501 neon_qfloat_bits (unsigned imm)
13503 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13506 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13507 the instruction. *OP is passed as the initial value of the op field, and
13508 may be set to a different value depending on the constant (i.e.
13509 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13510 MVN). If the immediate looks like a repeated pattern then also
13511 try smaller element sizes. */
13514 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13515 unsigned *immbits, int *op, int size,
13516 enum neon_el_type type)
13518 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13520 if (type == NT_float && !float_p)
13523 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13525 if (size != 32 || *op == 1)
13527 *immbits = neon_qfloat_bits (immlo);
13533 if (neon_bits_same_in_bytes (immhi)
13534 && neon_bits_same_in_bytes (immlo))
13538 *immbits = (neon_squash_bits (immhi) << 4)
13539 | neon_squash_bits (immlo);
13544 if (immhi != immlo)
13550 if (immlo == (immlo & 0x000000ff))
13555 else if (immlo == (immlo & 0x0000ff00))
13557 *immbits = immlo >> 8;
13560 else if (immlo == (immlo & 0x00ff0000))
13562 *immbits = immlo >> 16;
13565 else if (immlo == (immlo & 0xff000000))
13567 *immbits = immlo >> 24;
13570 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13572 *immbits = (immlo >> 8) & 0xff;
13575 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13577 *immbits = (immlo >> 16) & 0xff;
13581 if ((immlo & 0xffff) != (immlo >> 16))
13588 if (immlo == (immlo & 0x000000ff))
13593 else if (immlo == (immlo & 0x0000ff00))
13595 *immbits = immlo >> 8;
13599 if ((immlo & 0xff) != (immlo >> 8))
13604 if (immlo == (immlo & 0x000000ff))
13606 /* Don't allow MVN with 8-bit immediate. */
13616 /* Write immediate bits [7:0] to the following locations:
13618 |28/24|23 19|18 16|15 4|3 0|
13619 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13621 This function is used by VMOV/VMVN/VORR/VBIC. */
13624 neon_write_immbits (unsigned immbits)
13626 inst.instruction |= immbits & 0xf;
13627 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13628 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13631 /* Invert low-order SIZE bits of XHI:XLO. */
13634 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13636 unsigned immlo = xlo ? *xlo : 0;
13637 unsigned immhi = xhi ? *xhi : 0;
13642 immlo = (~immlo) & 0xff;
13646 immlo = (~immlo) & 0xffff;
13650 immhi = (~immhi) & 0xffffffff;
13651 /* fall through. */
13654 immlo = (~immlo) & 0xffffffff;
13669 do_neon_logic (void)
13671 if (inst.operands[2].present && inst.operands[2].isreg)
13673 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13674 neon_check_type (3, rs, N_IGNORE_TYPE);
13675 /* U bit and size field were set as part of the bitmask. */
13676 NEON_ENCODE (INTEGER, inst);
13677 neon_three_same (neon_quad (rs), 0, -1);
13681 const int three_ops_form = (inst.operands[2].present
13682 && !inst.operands[2].isreg);
13683 const int immoperand = (three_ops_form ? 2 : 1);
13684 enum neon_shape rs = (three_ops_form
13685 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13686 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13687 struct neon_type_el et = neon_check_type (2, rs,
13688 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13689 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13693 if (et.type == NT_invtype)
13696 if (three_ops_form)
13697 constraint (inst.operands[0].reg != inst.operands[1].reg,
13698 _("first and second operands shall be the same register"));
13700 NEON_ENCODE (IMMED, inst);
13702 immbits = inst.operands[immoperand].imm;
13705 /* .i64 is a pseudo-op, so the immediate must be a repeating
13707 if (immbits != (inst.operands[immoperand].regisimm ?
13708 inst.operands[immoperand].reg : 0))
13710 /* Set immbits to an invalid constant. */
13711 immbits = 0xdeadbeef;
13718 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13722 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13726 /* Pseudo-instruction for VBIC. */
13727 neon_invert_size (&immbits, 0, et.size);
13728 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13732 /* Pseudo-instruction for VORR. */
13733 neon_invert_size (&immbits, 0, et.size);
13734 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13744 inst.instruction |= neon_quad (rs) << 6;
13745 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13746 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13747 inst.instruction |= cmode << 8;
13748 neon_write_immbits (immbits);
13750 neon_dp_fixup (&inst);
13755 do_neon_bitfield (void)
13757 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13758 neon_check_type (3, rs, N_IGNORE_TYPE);
13759 neon_three_same (neon_quad (rs), 0, -1);
13763 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13766 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13767 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13769 if (et.type == NT_float)
13771 NEON_ENCODE (FLOAT, inst);
13772 neon_three_same (neon_quad (rs), 0, -1);
13776 NEON_ENCODE (INTEGER, inst);
13777 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13782 do_neon_dyadic_if_su (void)
13784 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13788 do_neon_dyadic_if_su_d (void)
13790 /* This version only allow D registers, but that constraint is enforced during
13791 operand parsing so we don't need to do anything extra here. */
13792 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13796 do_neon_dyadic_if_i_d (void)
13798 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13799 affected if we specify unsigned args. */
13800 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13803 enum vfp_or_neon_is_neon_bits
13806 NEON_CHECK_ARCH = 2
13809 /* Call this function if an instruction which may have belonged to the VFP or
13810 Neon instruction sets, but turned out to be a Neon instruction (due to the
13811 operand types involved, etc.). We have to check and/or fix-up a couple of
13814 - Make sure the user hasn't attempted to make a Neon instruction
13816 - Alter the value in the condition code field if necessary.
13817 - Make sure that the arch supports Neon instructions.
13819 Which of these operations take place depends on bits from enum
13820 vfp_or_neon_is_neon_bits.
13822 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13823 current instruction's condition is COND_ALWAYS, the condition field is
13824 changed to inst.uncond_value. This is necessary because instructions shared
13825 between VFP and Neon may be conditional for the VFP variants only, and the
13826 unconditional Neon version must have, e.g., 0xF in the condition field. */
13829 vfp_or_neon_is_neon (unsigned check)
13831 /* Conditions are always legal in Thumb mode (IT blocks). */
13832 if (!thumb_mode && (check & NEON_CHECK_CC))
13834 if (inst.cond != COND_ALWAYS)
13836 first_error (_(BAD_COND));
13839 if (inst.uncond_value != -1)
13840 inst.instruction |= inst.uncond_value << 28;
13843 if ((check & NEON_CHECK_ARCH)
13844 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13846 first_error (_(BAD_FPU));
13854 do_neon_addsub_if_i (void)
13856 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13859 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13862 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13863 affected if we specify unsigned args. */
13864 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13867 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13869 V<op> A,B (A is operand 0, B is operand 2)
13874 so handle that case specially. */
13877 neon_exchange_operands (void)
13879 void *scratch = alloca (sizeof (inst.operands[0]));
13880 if (inst.operands[1].present)
13882 /* Swap operands[1] and operands[2]. */
13883 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13884 inst.operands[1] = inst.operands[2];
13885 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13889 inst.operands[1] = inst.operands[2];
13890 inst.operands[2] = inst.operands[0];
13895 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13897 if (inst.operands[2].isreg)
13900 neon_exchange_operands ();
13901 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13905 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13906 struct neon_type_el et = neon_check_type (2, rs,
13907 N_EQK | N_SIZ, immtypes | N_KEY);
13909 NEON_ENCODE (IMMED, inst);
13910 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13911 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13912 inst.instruction |= LOW4 (inst.operands[1].reg);
13913 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13914 inst.instruction |= neon_quad (rs) << 6;
13915 inst.instruction |= (et.type == NT_float) << 10;
13916 inst.instruction |= neon_logbits (et.size) << 18;
13918 neon_dp_fixup (&inst);
13925 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13929 do_neon_cmp_inv (void)
13931 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13937 neon_compare (N_IF_32, N_IF_32, FALSE);
13940 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13941 scalars, which are encoded in 5 bits, M : Rm.
13942 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13943 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13947 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13949 unsigned regno = NEON_SCALAR_REG (scalar);
13950 unsigned elno = NEON_SCALAR_INDEX (scalar);
13955 if (regno > 7 || elno > 3)
13957 return regno | (elno << 3);
13960 if (regno > 15 || elno > 1)
13962 return regno | (elno << 4);
13966 first_error (_("scalar out of range for multiply instruction"));
13972 /* Encode multiply / multiply-accumulate scalar instructions. */
13975 neon_mul_mac (struct neon_type_el et, int ubit)
13979 /* Give a more helpful error message if we have an invalid type. */
13980 if (et.type == NT_invtype)
13983 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13984 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13985 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13986 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13987 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13988 inst.instruction |= LOW4 (scalar);
13989 inst.instruction |= HI1 (scalar) << 5;
13990 inst.instruction |= (et.type == NT_float) << 8;
13991 inst.instruction |= neon_logbits (et.size) << 20;
13992 inst.instruction |= (ubit != 0) << 24;
13994 neon_dp_fixup (&inst);
13998 do_neon_mac_maybe_scalar (void)
14000 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14003 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14006 if (inst.operands[2].isscalar)
14008 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14009 struct neon_type_el et = neon_check_type (3, rs,
14010 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14011 NEON_ENCODE (SCALAR, inst);
14012 neon_mul_mac (et, neon_quad (rs));
14016 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14017 affected if we specify unsigned args. */
14018 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14023 do_neon_fmac (void)
14025 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14028 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14031 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14037 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14038 struct neon_type_el et = neon_check_type (3, rs,
14039 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14040 neon_three_same (neon_quad (rs), 0, et.size);
14043 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14044 same types as the MAC equivalents. The polynomial type for this instruction
14045 is encoded the same as the integer type. */
14050 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14053 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14056 if (inst.operands[2].isscalar)
14057 do_neon_mac_maybe_scalar ();
14059 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14063 do_neon_qdmulh (void)
14065 if (inst.operands[2].isscalar)
14067 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14068 struct neon_type_el et = neon_check_type (3, rs,
14069 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14070 NEON_ENCODE (SCALAR, inst);
14071 neon_mul_mac (et, neon_quad (rs));
14075 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14076 struct neon_type_el et = neon_check_type (3, rs,
14077 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14078 NEON_ENCODE (INTEGER, inst);
14079 /* The U bit (rounding) comes from bit mask. */
14080 neon_three_same (neon_quad (rs), 0, et.size);
14085 do_neon_fcmp_absolute (void)
14087 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14088 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14089 /* Size field comes from bit mask. */
14090 neon_three_same (neon_quad (rs), 1, -1);
14094 do_neon_fcmp_absolute_inv (void)
14096 neon_exchange_operands ();
14097 do_neon_fcmp_absolute ();
14101 do_neon_step (void)
14103 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14104 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14105 neon_three_same (neon_quad (rs), 0, -1);
14109 do_neon_abs_neg (void)
14111 enum neon_shape rs;
14112 struct neon_type_el et;
14114 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14117 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14120 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14121 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14123 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14124 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14125 inst.instruction |= LOW4 (inst.operands[1].reg);
14126 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14127 inst.instruction |= neon_quad (rs) << 6;
14128 inst.instruction |= (et.type == NT_float) << 10;
14129 inst.instruction |= neon_logbits (et.size) << 18;
14131 neon_dp_fixup (&inst);
14137 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14138 struct neon_type_el et = neon_check_type (2, rs,
14139 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14140 int imm = inst.operands[2].imm;
14141 constraint (imm < 0 || (unsigned)imm >= et.size,
14142 _("immediate out of range for insert"));
14143 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14149 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14150 struct neon_type_el et = neon_check_type (2, rs,
14151 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14152 int imm = inst.operands[2].imm;
14153 constraint (imm < 1 || (unsigned)imm > et.size,
14154 _("immediate out of range for insert"));
14155 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14159 do_neon_qshlu_imm (void)
14161 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14162 struct neon_type_el et = neon_check_type (2, rs,
14163 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14164 int imm = inst.operands[2].imm;
14165 constraint (imm < 0 || (unsigned)imm >= et.size,
14166 _("immediate out of range for shift"));
14167 /* Only encodes the 'U present' variant of the instruction.
14168 In this case, signed types have OP (bit 8) set to 0.
14169 Unsigned types have OP set to 1. */
14170 inst.instruction |= (et.type == NT_unsigned) << 8;
14171 /* The rest of the bits are the same as other immediate shifts. */
14172 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14176 do_neon_qmovn (void)
14178 struct neon_type_el et = neon_check_type (2, NS_DQ,
14179 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14180 /* Saturating move where operands can be signed or unsigned, and the
14181 destination has the same signedness. */
14182 NEON_ENCODE (INTEGER, inst);
14183 if (et.type == NT_unsigned)
14184 inst.instruction |= 0xc0;
14186 inst.instruction |= 0x80;
14187 neon_two_same (0, 1, et.size / 2);
14191 do_neon_qmovun (void)
14193 struct neon_type_el et = neon_check_type (2, NS_DQ,
14194 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14195 /* Saturating move with unsigned results. Operands must be signed. */
14196 NEON_ENCODE (INTEGER, inst);
14197 neon_two_same (0, 1, et.size / 2);
14201 do_neon_rshift_sat_narrow (void)
14203 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14204 or unsigned. If operands are unsigned, results must also be unsigned. */
14205 struct neon_type_el et = neon_check_type (2, NS_DQI,
14206 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14207 int imm = inst.operands[2].imm;
14208 /* This gets the bounds check, size encoding and immediate bits calculation
14212 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14213 VQMOVN.I<size> <Dd>, <Qm>. */
14216 inst.operands[2].present = 0;
14217 inst.instruction = N_MNEM_vqmovn;
14222 constraint (imm < 1 || (unsigned)imm > et.size,
14223 _("immediate out of range"));
14224 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14228 do_neon_rshift_sat_narrow_u (void)
14230 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14231 or unsigned. If operands are unsigned, results must also be unsigned. */
14232 struct neon_type_el et = neon_check_type (2, NS_DQI,
14233 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14234 int imm = inst.operands[2].imm;
14235 /* This gets the bounds check, size encoding and immediate bits calculation
14239 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14240 VQMOVUN.I<size> <Dd>, <Qm>. */
14243 inst.operands[2].present = 0;
14244 inst.instruction = N_MNEM_vqmovun;
14249 constraint (imm < 1 || (unsigned)imm > et.size,
14250 _("immediate out of range"));
14251 /* FIXME: The manual is kind of unclear about what value U should have in
14252 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14254 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14258 do_neon_movn (void)
14260 struct neon_type_el et = neon_check_type (2, NS_DQ,
14261 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14262 NEON_ENCODE (INTEGER, inst);
14263 neon_two_same (0, 1, et.size / 2);
14267 do_neon_rshift_narrow (void)
14269 struct neon_type_el et = neon_check_type (2, NS_DQI,
14270 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14271 int imm = inst.operands[2].imm;
14272 /* This gets the bounds check, size encoding and immediate bits calculation
14276 /* If immediate is zero then we are a pseudo-instruction for
14277 VMOVN.I<size> <Dd>, <Qm> */
14280 inst.operands[2].present = 0;
14281 inst.instruction = N_MNEM_vmovn;
14286 constraint (imm < 1 || (unsigned)imm > et.size,
14287 _("immediate out of range for narrowing operation"));
14288 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14292 do_neon_shll (void)
14294 /* FIXME: Type checking when lengthening. */
14295 struct neon_type_el et = neon_check_type (2, NS_QDI,
14296 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14297 unsigned imm = inst.operands[2].imm;
14299 if (imm == et.size)
14301 /* Maximum shift variant. */
14302 NEON_ENCODE (INTEGER, inst);
14303 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14304 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14305 inst.instruction |= LOW4 (inst.operands[1].reg);
14306 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14307 inst.instruction |= neon_logbits (et.size) << 18;
14309 neon_dp_fixup (&inst);
14313 /* A more-specific type check for non-max versions. */
14314 et = neon_check_type (2, NS_QDI,
14315 N_EQK | N_DBL, N_SU_32 | N_KEY);
14316 NEON_ENCODE (IMMED, inst);
14317 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14321 /* Check the various types for the VCVT instruction, and return which version
14322 the current instruction is. */
14325 neon_cvt_flavour (enum neon_shape rs)
14327 #define CVT_VAR(C,X,Y) \
14328 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14329 if (et.type != NT_invtype) \
14331 inst.error = NULL; \
14334 struct neon_type_el et;
14335 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14336 || rs == NS_FF) ? N_VFP : 0;
14337 /* The instruction versions which take an immediate take one register
14338 argument, which is extended to the width of the full register. Thus the
14339 "source" and "destination" registers must have the same width. Hack that
14340 here by making the size equal to the key (wider, in this case) operand. */
14341 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14343 CVT_VAR (0, N_S32, N_F32);
14344 CVT_VAR (1, N_U32, N_F32);
14345 CVT_VAR (2, N_F32, N_S32);
14346 CVT_VAR (3, N_F32, N_U32);
14347 /* Half-precision conversions. */
14348 CVT_VAR (4, N_F32, N_F16);
14349 CVT_VAR (5, N_F16, N_F32);
14353 /* VFP instructions. */
14354 CVT_VAR (6, N_F32, N_F64);
14355 CVT_VAR (7, N_F64, N_F32);
14356 CVT_VAR (8, N_S32, N_F64 | key);
14357 CVT_VAR (9, N_U32, N_F64 | key);
14358 CVT_VAR (10, N_F64 | key, N_S32);
14359 CVT_VAR (11, N_F64 | key, N_U32);
14360 /* VFP instructions with bitshift. */
14361 CVT_VAR (12, N_F32 | key, N_S16);
14362 CVT_VAR (13, N_F32 | key, N_U16);
14363 CVT_VAR (14, N_F64 | key, N_S16);
14364 CVT_VAR (15, N_F64 | key, N_U16);
14365 CVT_VAR (16, N_S16, N_F32 | key);
14366 CVT_VAR (17, N_U16, N_F32 | key);
14367 CVT_VAR (18, N_S16, N_F64 | key);
14368 CVT_VAR (19, N_U16, N_F64 | key);
14374 /* Neon-syntax VFP conversions. */
14377 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14379 const char *opname = 0;
14381 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14383 /* Conversions with immediate bitshift. */
14384 const char *enc[] =
14408 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14410 opname = enc[flavour];
14411 constraint (inst.operands[0].reg != inst.operands[1].reg,
14412 _("operands 0 and 1 must be the same register"));
14413 inst.operands[1] = inst.operands[2];
14414 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14419 /* Conversions without bitshift. */
14420 const char *enc[] =
14436 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14437 opname = enc[flavour];
14441 do_vfp_nsyn_opcode (opname);
14445 do_vfp_nsyn_cvtz (void)
14447 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14448 int flavour = neon_cvt_flavour (rs);
14449 const char *enc[] =
14463 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14464 do_vfp_nsyn_opcode (enc[flavour]);
14468 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14470 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14471 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14472 int flavour = neon_cvt_flavour (rs);
14474 /* PR11109: Handle round-to-zero for VCVT conversions. */
14476 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14477 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14478 && (rs == NS_FD || rs == NS_FF))
14480 do_vfp_nsyn_cvtz ();
14484 /* VFP rather than Neon conversions. */
14487 do_vfp_nsyn_cvt (rs, flavour);
14497 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14499 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14502 /* Fixed-point conversion with #0 immediate is encoded as an
14503 integer conversion. */
14504 if (inst.operands[2].present && inst.operands[2].imm == 0)
14506 immbits = 32 - inst.operands[2].imm;
14507 NEON_ENCODE (IMMED, inst);
14509 inst.instruction |= enctab[flavour];
14510 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14511 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14512 inst.instruction |= LOW4 (inst.operands[1].reg);
14513 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14514 inst.instruction |= neon_quad (rs) << 6;
14515 inst.instruction |= 1 << 21;
14516 inst.instruction |= immbits << 16;
14518 neon_dp_fixup (&inst);
14526 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14528 NEON_ENCODE (INTEGER, inst);
14530 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14534 inst.instruction |= enctab[flavour];
14536 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14537 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14538 inst.instruction |= LOW4 (inst.operands[1].reg);
14539 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14540 inst.instruction |= neon_quad (rs) << 6;
14541 inst.instruction |= 2 << 18;
14543 neon_dp_fixup (&inst);
14547 /* Half-precision conversions for Advanced SIMD -- neon. */
14552 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14554 as_bad (_("operand size must match register width"));
14559 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14561 as_bad (_("operand size must match register width"));
14566 inst.instruction = 0x3b60600;
14568 inst.instruction = 0x3b60700;
14570 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14571 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14572 inst.instruction |= LOW4 (inst.operands[1].reg);
14573 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14574 neon_dp_fixup (&inst);
14578 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14579 do_vfp_nsyn_cvt (rs, flavour);
14584 do_neon_cvtr (void)
14586 do_neon_cvt_1 (FALSE);
14592 do_neon_cvt_1 (TRUE);
14596 do_neon_cvtb (void)
14598 inst.instruction = 0xeb20a40;
14600 /* The sizes are attached to the mnemonic. */
14601 if (inst.vectype.el[0].type != NT_invtype
14602 && inst.vectype.el[0].size == 16)
14603 inst.instruction |= 0x00010000;
14605 /* Programmer's syntax: the sizes are attached to the operands. */
14606 else if (inst.operands[0].vectype.type != NT_invtype
14607 && inst.operands[0].vectype.size == 16)
14608 inst.instruction |= 0x00010000;
14610 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14611 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14612 do_vfp_cond_or_thumb ();
14617 do_neon_cvtt (void)
14620 inst.instruction |= 0x80;
14624 neon_move_immediate (void)
14626 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14627 struct neon_type_el et = neon_check_type (2, rs,
14628 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14629 unsigned immlo, immhi = 0, immbits;
14630 int op, cmode, float_p;
14632 constraint (et.type == NT_invtype,
14633 _("operand size must be specified for immediate VMOV"));
14635 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14636 op = (inst.instruction & (1 << 5)) != 0;
14638 immlo = inst.operands[1].imm;
14639 if (inst.operands[1].regisimm)
14640 immhi = inst.operands[1].reg;
14642 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14643 _("immediate has bits set outside the operand size"));
14645 float_p = inst.operands[1].immisfloat;
14647 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14648 et.size, et.type)) == FAIL)
14650 /* Invert relevant bits only. */
14651 neon_invert_size (&immlo, &immhi, et.size);
14652 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14653 with one or the other; those cases are caught by
14654 neon_cmode_for_move_imm. */
14656 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14657 &op, et.size, et.type)) == FAIL)
14659 first_error (_("immediate out of range"));
14664 inst.instruction &= ~(1 << 5);
14665 inst.instruction |= op << 5;
14667 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14668 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14669 inst.instruction |= neon_quad (rs) << 6;
14670 inst.instruction |= cmode << 8;
14672 neon_write_immbits (immbits);
14678 if (inst.operands[1].isreg)
14680 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14682 NEON_ENCODE (INTEGER, inst);
14683 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14684 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14685 inst.instruction |= LOW4 (inst.operands[1].reg);
14686 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14687 inst.instruction |= neon_quad (rs) << 6;
14691 NEON_ENCODE (IMMED, inst);
14692 neon_move_immediate ();
14695 neon_dp_fixup (&inst);
14698 /* Encode instructions of form:
14700 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14701 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14704 neon_mixed_length (struct neon_type_el et, unsigned size)
14706 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14707 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14708 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14709 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14710 inst.instruction |= LOW4 (inst.operands[2].reg);
14711 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14712 inst.instruction |= (et.type == NT_unsigned) << 24;
14713 inst.instruction |= neon_logbits (size) << 20;
14715 neon_dp_fixup (&inst);
14719 do_neon_dyadic_long (void)
14721 /* FIXME: Type checking for lengthening op. */
14722 struct neon_type_el et = neon_check_type (3, NS_QDD,
14723 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14724 neon_mixed_length (et, et.size);
14728 do_neon_abal (void)
14730 struct neon_type_el et = neon_check_type (3, NS_QDD,
14731 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14732 neon_mixed_length (et, et.size);
14736 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14738 if (inst.operands[2].isscalar)
14740 struct neon_type_el et = neon_check_type (3, NS_QDS,
14741 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14742 NEON_ENCODE (SCALAR, inst);
14743 neon_mul_mac (et, et.type == NT_unsigned);
14747 struct neon_type_el et = neon_check_type (3, NS_QDD,
14748 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14749 NEON_ENCODE (INTEGER, inst);
14750 neon_mixed_length (et, et.size);
14755 do_neon_mac_maybe_scalar_long (void)
14757 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14761 do_neon_dyadic_wide (void)
14763 struct neon_type_el et = neon_check_type (3, NS_QQD,
14764 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14765 neon_mixed_length (et, et.size);
14769 do_neon_dyadic_narrow (void)
14771 struct neon_type_el et = neon_check_type (3, NS_QDD,
14772 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14773 /* Operand sign is unimportant, and the U bit is part of the opcode,
14774 so force the operand type to integer. */
14775 et.type = NT_integer;
14776 neon_mixed_length (et, et.size / 2);
14780 do_neon_mul_sat_scalar_long (void)
14782 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14786 do_neon_vmull (void)
14788 if (inst.operands[2].isscalar)
14789 do_neon_mac_maybe_scalar_long ();
14792 struct neon_type_el et = neon_check_type (3, NS_QDD,
14793 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14794 if (et.type == NT_poly)
14795 NEON_ENCODE (POLY, inst);
14797 NEON_ENCODE (INTEGER, inst);
14798 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14799 zero. Should be OK as-is. */
14800 neon_mixed_length (et, et.size);
14807 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14808 struct neon_type_el et = neon_check_type (3, rs,
14809 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14810 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14812 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14813 _("shift out of range"));
14814 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14815 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14816 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14817 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14818 inst.instruction |= LOW4 (inst.operands[2].reg);
14819 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14820 inst.instruction |= neon_quad (rs) << 6;
14821 inst.instruction |= imm << 8;
14823 neon_dp_fixup (&inst);
14829 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14830 struct neon_type_el et = neon_check_type (2, rs,
14831 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14832 unsigned op = (inst.instruction >> 7) & 3;
14833 /* N (width of reversed regions) is encoded as part of the bitmask. We
14834 extract it here to check the elements to be reversed are smaller.
14835 Otherwise we'd get a reserved instruction. */
14836 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14837 gas_assert (elsize != 0);
14838 constraint (et.size >= elsize,
14839 _("elements must be smaller than reversal region"));
14840 neon_two_same (neon_quad (rs), 1, et.size);
14846 if (inst.operands[1].isscalar)
14848 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14849 struct neon_type_el et = neon_check_type (2, rs,
14850 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14851 unsigned sizebits = et.size >> 3;
14852 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14853 int logsize = neon_logbits (et.size);
14854 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14856 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14859 NEON_ENCODE (SCALAR, inst);
14860 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14861 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14862 inst.instruction |= LOW4 (dm);
14863 inst.instruction |= HI1 (dm) << 5;
14864 inst.instruction |= neon_quad (rs) << 6;
14865 inst.instruction |= x << 17;
14866 inst.instruction |= sizebits << 16;
14868 neon_dp_fixup (&inst);
14872 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14873 struct neon_type_el et = neon_check_type (2, rs,
14874 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14875 /* Duplicate ARM register to lanes of vector. */
14876 NEON_ENCODE (ARMREG, inst);
14879 case 8: inst.instruction |= 0x400000; break;
14880 case 16: inst.instruction |= 0x000020; break;
14881 case 32: inst.instruction |= 0x000000; break;
14884 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14885 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14886 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14887 inst.instruction |= neon_quad (rs) << 21;
14888 /* The encoding for this instruction is identical for the ARM and Thumb
14889 variants, except for the condition field. */
14890 do_vfp_cond_or_thumb ();
14894 /* VMOV has particularly many variations. It can be one of:
14895 0. VMOV<c><q> <Qd>, <Qm>
14896 1. VMOV<c><q> <Dd>, <Dm>
14897 (Register operations, which are VORR with Rm = Rn.)
14898 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14899 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14901 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14902 (ARM register to scalar.)
14903 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14904 (Two ARM registers to vector.)
14905 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14906 (Scalar to ARM register.)
14907 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14908 (Vector to two ARM registers.)
14909 8. VMOV.F32 <Sd>, <Sm>
14910 9. VMOV.F64 <Dd>, <Dm>
14911 (VFP register moves.)
14912 10. VMOV.F32 <Sd>, #imm
14913 11. VMOV.F64 <Dd>, #imm
14914 (VFP float immediate load.)
14915 12. VMOV <Rd>, <Sm>
14916 (VFP single to ARM reg.)
14917 13. VMOV <Sd>, <Rm>
14918 (ARM reg to VFP single.)
14919 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14920 (Two ARM regs to two VFP singles.)
14921 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14922 (Two VFP singles to two ARM regs.)
14924 These cases can be disambiguated using neon_select_shape, except cases 1/9
14925 and 3/11 which depend on the operand type too.
14927 All the encoded bits are hardcoded by this function.
14929 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14930 Cases 5, 7 may be used with VFPv2 and above.
14932 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14933 can specify a type where it doesn't make sense to, and is ignored). */
14938 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14939 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14941 struct neon_type_el et;
14942 const char *ldconst = 0;
14946 case NS_DD: /* case 1/9. */
14947 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14948 /* It is not an error here if no type is given. */
14950 if (et.type == NT_float && et.size == 64)
14952 do_vfp_nsyn_opcode ("fcpyd");
14955 /* fall through. */
14957 case NS_QQ: /* case 0/1. */
14959 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14961 /* The architecture manual I have doesn't explicitly state which
14962 value the U bit should have for register->register moves, but
14963 the equivalent VORR instruction has U = 0, so do that. */
14964 inst.instruction = 0x0200110;
14965 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14966 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14967 inst.instruction |= LOW4 (inst.operands[1].reg);
14968 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14969 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14970 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14971 inst.instruction |= neon_quad (rs) << 6;
14973 neon_dp_fixup (&inst);
14977 case NS_DI: /* case 3/11. */
14978 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14980 if (et.type == NT_float && et.size == 64)
14982 /* case 11 (fconstd). */
14983 ldconst = "fconstd";
14984 goto encode_fconstd;
14986 /* fall through. */
14988 case NS_QI: /* case 2/3. */
14989 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14991 inst.instruction = 0x0800010;
14992 neon_move_immediate ();
14993 neon_dp_fixup (&inst);
14996 case NS_SR: /* case 4. */
14998 unsigned bcdebits = 0;
15000 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15001 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15003 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15004 logsize = neon_logbits (et.size);
15006 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15008 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15009 && et.size != 32, _(BAD_FPU));
15010 constraint (et.type == NT_invtype, _("bad type for scalar"));
15011 constraint (x >= 64 / et.size, _("scalar index out of range"));
15015 case 8: bcdebits = 0x8; break;
15016 case 16: bcdebits = 0x1; break;
15017 case 32: bcdebits = 0x0; break;
15021 bcdebits |= x << logsize;
15023 inst.instruction = 0xe000b10;
15024 do_vfp_cond_or_thumb ();
15025 inst.instruction |= LOW4 (dn) << 16;
15026 inst.instruction |= HI1 (dn) << 7;
15027 inst.instruction |= inst.operands[1].reg << 12;
15028 inst.instruction |= (bcdebits & 3) << 5;
15029 inst.instruction |= (bcdebits >> 2) << 21;
15033 case NS_DRR: /* case 5 (fmdrr). */
15034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15037 inst.instruction = 0xc400b10;
15038 do_vfp_cond_or_thumb ();
15039 inst.instruction |= LOW4 (inst.operands[0].reg);
15040 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15041 inst.instruction |= inst.operands[1].reg << 12;
15042 inst.instruction |= inst.operands[2].reg << 16;
15045 case NS_RS: /* case 6. */
15048 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15049 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15050 unsigned abcdebits = 0;
15052 et = neon_check_type (2, NS_NULL,
15053 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15054 logsize = neon_logbits (et.size);
15056 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15059 && et.size != 32, _(BAD_FPU));
15060 constraint (et.type == NT_invtype, _("bad type for scalar"));
15061 constraint (x >= 64 / et.size, _("scalar index out of range"));
15065 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15066 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15067 case 32: abcdebits = 0x00; break;
15071 abcdebits |= x << logsize;
15072 inst.instruction = 0xe100b10;
15073 do_vfp_cond_or_thumb ();
15074 inst.instruction |= LOW4 (dn) << 16;
15075 inst.instruction |= HI1 (dn) << 7;
15076 inst.instruction |= inst.operands[0].reg << 12;
15077 inst.instruction |= (abcdebits & 3) << 5;
15078 inst.instruction |= (abcdebits >> 2) << 21;
15082 case NS_RRD: /* case 7 (fmrrd). */
15083 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15086 inst.instruction = 0xc500b10;
15087 do_vfp_cond_or_thumb ();
15088 inst.instruction |= inst.operands[0].reg << 12;
15089 inst.instruction |= inst.operands[1].reg << 16;
15090 inst.instruction |= LOW4 (inst.operands[2].reg);
15091 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15094 case NS_FF: /* case 8 (fcpys). */
15095 do_vfp_nsyn_opcode ("fcpys");
15098 case NS_FI: /* case 10 (fconsts). */
15099 ldconst = "fconsts";
15101 if (is_quarter_float (inst.operands[1].imm))
15103 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15104 do_vfp_nsyn_opcode (ldconst);
15107 first_error (_("immediate out of range"));
15110 case NS_RF: /* case 12 (fmrs). */
15111 do_vfp_nsyn_opcode ("fmrs");
15114 case NS_FR: /* case 13 (fmsr). */
15115 do_vfp_nsyn_opcode ("fmsr");
15118 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15119 (one of which is a list), but we have parsed four. Do some fiddling to
15120 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15122 case NS_RRFF: /* case 14 (fmrrs). */
15123 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15124 _("VFP registers must be adjacent"));
15125 inst.operands[2].imm = 2;
15126 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15127 do_vfp_nsyn_opcode ("fmrrs");
15130 case NS_FFRR: /* case 15 (fmsrr). */
15131 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15132 _("VFP registers must be adjacent"));
15133 inst.operands[1] = inst.operands[2];
15134 inst.operands[2] = inst.operands[3];
15135 inst.operands[0].imm = 2;
15136 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15137 do_vfp_nsyn_opcode ("fmsrr");
15146 do_neon_rshift_round_imm (void)
15148 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15149 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15150 int imm = inst.operands[2].imm;
15152 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15155 inst.operands[2].present = 0;
15160 constraint (imm < 1 || (unsigned)imm > et.size,
15161 _("immediate out of range for shift"));
15162 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15167 do_neon_movl (void)
15169 struct neon_type_el et = neon_check_type (2, NS_QD,
15170 N_EQK | N_DBL, N_SU_32 | N_KEY);
15171 unsigned sizebits = et.size >> 3;
15172 inst.instruction |= sizebits << 19;
15173 neon_two_same (0, et.type == NT_unsigned, -1);
15179 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15180 struct neon_type_el et = neon_check_type (2, rs,
15181 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15182 NEON_ENCODE (INTEGER, inst);
15183 neon_two_same (neon_quad (rs), 1, et.size);
15187 do_neon_zip_uzp (void)
15189 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15190 struct neon_type_el et = neon_check_type (2, rs,
15191 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15192 if (rs == NS_DD && et.size == 32)
15194 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15195 inst.instruction = N_MNEM_vtrn;
15199 neon_two_same (neon_quad (rs), 1, et.size);
15203 do_neon_sat_abs_neg (void)
15205 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15206 struct neon_type_el et = neon_check_type (2, rs,
15207 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15208 neon_two_same (neon_quad (rs), 1, et.size);
15212 do_neon_pair_long (void)
15214 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15215 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15216 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15217 inst.instruction |= (et.type == NT_unsigned) << 7;
15218 neon_two_same (neon_quad (rs), 1, et.size);
15222 do_neon_recip_est (void)
15224 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15225 struct neon_type_el et = neon_check_type (2, rs,
15226 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15227 inst.instruction |= (et.type == NT_float) << 8;
15228 neon_two_same (neon_quad (rs), 1, et.size);
15234 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15235 struct neon_type_el et = neon_check_type (2, rs,
15236 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15237 neon_two_same (neon_quad (rs), 1, et.size);
15243 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15244 struct neon_type_el et = neon_check_type (2, rs,
15245 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15246 neon_two_same (neon_quad (rs), 1, et.size);
15252 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15253 struct neon_type_el et = neon_check_type (2, rs,
15254 N_EQK | N_INT, N_8 | N_KEY);
15255 neon_two_same (neon_quad (rs), 1, et.size);
15261 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15262 neon_two_same (neon_quad (rs), 1, -1);
15266 do_neon_tbl_tbx (void)
15268 unsigned listlenbits;
15269 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15271 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15273 first_error (_("bad list length for table lookup"));
15277 listlenbits = inst.operands[1].imm - 1;
15278 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15279 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15280 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15281 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15282 inst.instruction |= LOW4 (inst.operands[2].reg);
15283 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15284 inst.instruction |= listlenbits << 8;
15286 neon_dp_fixup (&inst);
15290 do_neon_ldm_stm (void)
15292 /* P, U and L bits are part of bitmask. */
15293 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15294 unsigned offsetbits = inst.operands[1].imm * 2;
15296 if (inst.operands[1].issingle)
15298 do_vfp_nsyn_ldm_stm (is_dbmode);
15302 constraint (is_dbmode && !inst.operands[0].writeback,
15303 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15305 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15306 _("register list must contain at least 1 and at most 16 "
15309 inst.instruction |= inst.operands[0].reg << 16;
15310 inst.instruction |= inst.operands[0].writeback << 21;
15311 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15312 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15314 inst.instruction |= offsetbits;
15316 do_vfp_cond_or_thumb ();
15320 do_neon_ldr_str (void)
15322 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15324 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15325 And is UNPREDICTABLE in thumb mode. */
15327 && inst.operands[1].reg == REG_PC
15328 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15330 if (!thumb_mode && warn_on_deprecated)
15331 as_warn (_("Use of PC here is deprecated"));
15333 inst.error = _("Use of PC here is UNPREDICTABLE");
15336 if (inst.operands[0].issingle)
15339 do_vfp_nsyn_opcode ("flds");
15341 do_vfp_nsyn_opcode ("fsts");
15346 do_vfp_nsyn_opcode ("fldd");
15348 do_vfp_nsyn_opcode ("fstd");
15352 /* "interleave" version also handles non-interleaving register VLD1/VST1
15356 do_neon_ld_st_interleave (void)
15358 struct neon_type_el et = neon_check_type (1, NS_NULL,
15359 N_8 | N_16 | N_32 | N_64);
15360 unsigned alignbits = 0;
15362 /* The bits in this table go:
15363 0: register stride of one (0) or two (1)
15364 1,2: register list length, minus one (1, 2, 3, 4).
15365 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15366 We use -1 for invalid entries. */
15367 const int typetable[] =
15369 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15370 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15371 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15372 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15376 if (et.type == NT_invtype)
15379 if (inst.operands[1].immisalign)
15380 switch (inst.operands[1].imm >> 8)
15382 case 64: alignbits = 1; break;
15384 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15385 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15386 goto bad_alignment;
15390 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15391 goto bad_alignment;
15396 first_error (_("bad alignment"));
15400 inst.instruction |= alignbits << 4;
15401 inst.instruction |= neon_logbits (et.size) << 6;
15403 /* Bits [4:6] of the immediate in a list specifier encode register stride
15404 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15405 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15406 up the right value for "type" in a table based on this value and the given
15407 list style, then stick it back. */
15408 idx = ((inst.operands[0].imm >> 4) & 7)
15409 | (((inst.instruction >> 8) & 3) << 3);
15411 typebits = typetable[idx];
15413 constraint (typebits == -1, _("bad list type for instruction"));
15415 inst.instruction &= ~0xf00;
15416 inst.instruction |= typebits << 8;
15419 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15420 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15421 otherwise. The variable arguments are a list of pairs of legal (size, align)
15422 values, terminated with -1. */
15425 neon_alignment_bit (int size, int align, int *do_align, ...)
15428 int result = FAIL, thissize, thisalign;
15430 if (!inst.operands[1].immisalign)
15436 va_start (ap, do_align);
15440 thissize = va_arg (ap, int);
15441 if (thissize == -1)
15443 thisalign = va_arg (ap, int);
15445 if (size == thissize && align == thisalign)
15448 while (result != SUCCESS);
15452 if (result == SUCCESS)
15455 first_error (_("unsupported alignment for instruction"));
15461 do_neon_ld_st_lane (void)
15463 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15464 int align_good, do_align = 0;
15465 int logsize = neon_logbits (et.size);
15466 int align = inst.operands[1].imm >> 8;
15467 int n = (inst.instruction >> 8) & 3;
15468 int max_el = 64 / et.size;
15470 if (et.type == NT_invtype)
15473 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15474 _("bad list length"));
15475 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15476 _("scalar index out of range"));
15477 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15479 _("stride of 2 unavailable when element size is 8"));
15483 case 0: /* VLD1 / VST1. */
15484 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15486 if (align_good == FAIL)
15490 unsigned alignbits = 0;
15493 case 16: alignbits = 0x1; break;
15494 case 32: alignbits = 0x3; break;
15497 inst.instruction |= alignbits << 4;
15501 case 1: /* VLD2 / VST2. */
15502 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15504 if (align_good == FAIL)
15507 inst.instruction |= 1 << 4;
15510 case 2: /* VLD3 / VST3. */
15511 constraint (inst.operands[1].immisalign,
15512 _("can't use alignment with this instruction"));
15515 case 3: /* VLD4 / VST4. */
15516 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15517 16, 64, 32, 64, 32, 128, -1);
15518 if (align_good == FAIL)
15522 unsigned alignbits = 0;
15525 case 8: alignbits = 0x1; break;
15526 case 16: alignbits = 0x1; break;
15527 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15530 inst.instruction |= alignbits << 4;
15537 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15538 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15539 inst.instruction |= 1 << (4 + logsize);
15541 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15542 inst.instruction |= logsize << 10;
15545 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15548 do_neon_ld_dup (void)
15550 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15551 int align_good, do_align = 0;
15553 if (et.type == NT_invtype)
15556 switch ((inst.instruction >> 8) & 3)
15558 case 0: /* VLD1. */
15559 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15560 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15561 &do_align, 16, 16, 32, 32, -1);
15562 if (align_good == FAIL)
15564 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15567 case 2: inst.instruction |= 1 << 5; break;
15568 default: first_error (_("bad list length")); return;
15570 inst.instruction |= neon_logbits (et.size) << 6;
15573 case 1: /* VLD2. */
15574 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15575 &do_align, 8, 16, 16, 32, 32, 64, -1);
15576 if (align_good == FAIL)
15578 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15579 _("bad list length"));
15580 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15581 inst.instruction |= 1 << 5;
15582 inst.instruction |= neon_logbits (et.size) << 6;
15585 case 2: /* VLD3. */
15586 constraint (inst.operands[1].immisalign,
15587 _("can't use alignment with this instruction"));
15588 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15589 _("bad list length"));
15590 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15591 inst.instruction |= 1 << 5;
15592 inst.instruction |= neon_logbits (et.size) << 6;
15595 case 3: /* VLD4. */
15597 int align = inst.operands[1].imm >> 8;
15598 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15599 16, 64, 32, 64, 32, 128, -1);
15600 if (align_good == FAIL)
15602 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15603 _("bad list length"));
15604 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15605 inst.instruction |= 1 << 5;
15606 if (et.size == 32 && align == 128)
15607 inst.instruction |= 0x3 << 6;
15609 inst.instruction |= neon_logbits (et.size) << 6;
15616 inst.instruction |= do_align << 4;
15619 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15620 apart from bits [11:4]. */
15623 do_neon_ldx_stx (void)
15625 if (inst.operands[1].isreg)
15626 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15628 switch (NEON_LANE (inst.operands[0].imm))
15630 case NEON_INTERLEAVE_LANES:
15631 NEON_ENCODE (INTERLV, inst);
15632 do_neon_ld_st_interleave ();
15635 case NEON_ALL_LANES:
15636 NEON_ENCODE (DUP, inst);
15641 NEON_ENCODE (LANE, inst);
15642 do_neon_ld_st_lane ();
15645 /* L bit comes from bit mask. */
15646 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15647 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15648 inst.instruction |= inst.operands[1].reg << 16;
15650 if (inst.operands[1].postind)
15652 int postreg = inst.operands[1].imm & 0xf;
15653 constraint (!inst.operands[1].immisreg,
15654 _("post-index must be a register"));
15655 constraint (postreg == 0xd || postreg == 0xf,
15656 _("bad register for post-index"));
15657 inst.instruction |= postreg;
15659 else if (inst.operands[1].writeback)
15661 inst.instruction |= 0xd;
15664 inst.instruction |= 0xf;
15667 inst.instruction |= 0xf9000000;
15669 inst.instruction |= 0xf4000000;
15672 /* Overall per-instruction processing. */
15674 /* We need to be able to fix up arbitrary expressions in some statements.
15675 This is so that we can handle symbols that are an arbitrary distance from
15676 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15677 which returns part of an address in a form which will be valid for
15678 a data instruction. We do this by pushing the expression into a symbol
15679 in the expr_section, and creating a fix for that. */
15682 fix_new_arm (fragS * frag,
15696 /* Create an absolute valued symbol, so we have something to
15697 refer to in the object file. Unfortunately for us, gas's
15698 generic expression parsing will already have folded out
15699 any use of .set foo/.type foo %function that may have
15700 been used to set type information of the target location,
15701 that's being specified symbolically. We have to presume
15702 the user knows what they are doing. */
15706 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15708 symbol = symbol_find_or_make (name);
15709 S_SET_SEGMENT (symbol, absolute_section);
15710 symbol_set_frag (symbol, &zero_address_frag);
15711 S_SET_VALUE (symbol, exp->X_add_number);
15712 exp->X_op = O_symbol;
15713 exp->X_add_symbol = symbol;
15714 exp->X_add_number = 0;
15720 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15721 (enum bfd_reloc_code_real) reloc);
15725 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15726 pc_rel, (enum bfd_reloc_code_real) reloc);
15730 /* Mark whether the fix is to a THUMB instruction, or an ARM
15732 new_fix->tc_fix_data = thumb_mode;
15735 /* Create a frg for an instruction requiring relaxation. */
15737 output_relax_insn (void)
15743 /* The size of the instruction is unknown, so tie the debug info to the
15744 start of the instruction. */
15745 dwarf2_emit_insn (0);
15747 switch (inst.reloc.exp.X_op)
15750 sym = inst.reloc.exp.X_add_symbol;
15751 offset = inst.reloc.exp.X_add_number;
15755 offset = inst.reloc.exp.X_add_number;
15758 sym = make_expr_symbol (&inst.reloc.exp);
15762 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15763 inst.relax, sym, offset, NULL/*offset, opcode*/);
15764 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15767 /* Write a 32-bit thumb instruction to buf. */
15769 put_thumb32_insn (char * buf, unsigned long insn)
15771 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15772 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15776 output_inst (const char * str)
15782 as_bad ("%s -- `%s'", inst.error, str);
15787 output_relax_insn ();
15790 if (inst.size == 0)
15793 to = frag_more (inst.size);
15794 /* PR 9814: Record the thumb mode into the current frag so that we know
15795 what type of NOP padding to use, if necessary. We override any previous
15796 setting so that if the mode has changed then the NOPS that we use will
15797 match the encoding of the last instruction in the frag. */
15798 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15800 if (thumb_mode && (inst.size > THUMB_SIZE))
15802 gas_assert (inst.size == (2 * THUMB_SIZE));
15803 put_thumb32_insn (to, inst.instruction);
15805 else if (inst.size > INSN_SIZE)
15807 gas_assert (inst.size == (2 * INSN_SIZE));
15808 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15809 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15812 md_number_to_chars (to, inst.instruction, inst.size);
15814 if (inst.reloc.type != BFD_RELOC_UNUSED)
15815 fix_new_arm (frag_now, to - frag_now->fr_literal,
15816 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15819 dwarf2_emit_insn (inst.size);
15823 output_it_inst (int cond, int mask, char * to)
15825 unsigned long instruction = 0xbf00;
15828 instruction |= mask;
15829 instruction |= cond << 4;
15833 to = frag_more (2);
15835 dwarf2_emit_insn (2);
15839 md_number_to_chars (to, instruction, 2);
15844 /* Tag values used in struct asm_opcode's tag field. */
15847 OT_unconditional, /* Instruction cannot be conditionalized.
15848 The ARM condition field is still 0xE. */
15849 OT_unconditionalF, /* Instruction cannot be conditionalized
15850 and carries 0xF in its ARM condition field. */
15851 OT_csuffix, /* Instruction takes a conditional suffix. */
15852 OT_csuffixF, /* Some forms of the instruction take a conditional
15853 suffix, others place 0xF where the condition field
15855 OT_cinfix3, /* Instruction takes a conditional infix,
15856 beginning at character index 3. (In
15857 unified mode, it becomes a suffix.) */
15858 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15859 tsts, cmps, cmns, and teqs. */
15860 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15861 character index 3, even in unified mode. Used for
15862 legacy instructions where suffix and infix forms
15863 may be ambiguous. */
15864 OT_csuf_or_in3, /* Instruction takes either a conditional
15865 suffix or an infix at character index 3. */
15866 OT_odd_infix_unc, /* This is the unconditional variant of an
15867 instruction that takes a conditional infix
15868 at an unusual position. In unified mode,
15869 this variant will accept a suffix. */
15870 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15871 are the conditional variants of instructions that
15872 take conditional infixes in unusual positions.
15873 The infix appears at character index
15874 (tag - OT_odd_infix_0). These are not accepted
15875 in unified mode. */
15878 /* Subroutine of md_assemble, responsible for looking up the primary
15879 opcode from the mnemonic the user wrote. STR points to the
15880 beginning of the mnemonic.
15882 This is not simply a hash table lookup, because of conditional
15883 variants. Most instructions have conditional variants, which are
15884 expressed with a _conditional affix_ to the mnemonic. If we were
15885 to encode each conditional variant as a literal string in the opcode
15886 table, it would have approximately 20,000 entries.
15888 Most mnemonics take this affix as a suffix, and in unified syntax,
15889 'most' is upgraded to 'all'. However, in the divided syntax, some
15890 instructions take the affix as an infix, notably the s-variants of
15891 the arithmetic instructions. Of those instructions, all but six
15892 have the infix appear after the third character of the mnemonic.
15894 Accordingly, the algorithm for looking up primary opcodes given
15897 1. Look up the identifier in the opcode table.
15898 If we find a match, go to step U.
15900 2. Look up the last two characters of the identifier in the
15901 conditions table. If we find a match, look up the first N-2
15902 characters of the identifier in the opcode table. If we
15903 find a match, go to step CE.
15905 3. Look up the fourth and fifth characters of the identifier in
15906 the conditions table. If we find a match, extract those
15907 characters from the identifier, and look up the remaining
15908 characters in the opcode table. If we find a match, go
15913 U. Examine the tag field of the opcode structure, in case this is
15914 one of the six instructions with its conditional infix in an
15915 unusual place. If it is, the tag tells us where to find the
15916 infix; look it up in the conditions table and set inst.cond
15917 accordingly. Otherwise, this is an unconditional instruction.
15918 Again set inst.cond accordingly. Return the opcode structure.
15920 CE. Examine the tag field to make sure this is an instruction that
15921 should receive a conditional suffix. If it is not, fail.
15922 Otherwise, set inst.cond from the suffix we already looked up,
15923 and return the opcode structure.
15925 CM. Examine the tag field to make sure this is an instruction that
15926 should receive a conditional infix after the third character.
15927 If it is not, fail. Otherwise, undo the edits to the current
15928 line of input and proceed as for case CE. */
15930 static const struct asm_opcode *
15931 opcode_lookup (char **str)
15935 const struct asm_opcode *opcode;
15936 const struct asm_cond *cond;
15939 /* Scan up to the end of the mnemonic, which must end in white space,
15940 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15941 for (base = end = *str; *end != '\0'; end++)
15942 if (*end == ' ' || *end == '.')
15948 /* Handle a possible width suffix and/or Neon type suffix. */
15953 /* The .w and .n suffixes are only valid if the unified syntax is in
15955 if (unified_syntax && end[1] == 'w')
15957 else if (unified_syntax && end[1] == 'n')
15962 inst.vectype.elems = 0;
15964 *str = end + offset;
15966 if (end[offset] == '.')
15968 /* See if we have a Neon type suffix (possible in either unified or
15969 non-unified ARM syntax mode). */
15970 if (parse_neon_type (&inst.vectype, str) == FAIL)
15973 else if (end[offset] != '\0' && end[offset] != ' ')
15979 /* Look for unaffixed or special-case affixed mnemonic. */
15980 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15985 if (opcode->tag < OT_odd_infix_0)
15987 inst.cond = COND_ALWAYS;
15991 if (warn_on_deprecated && unified_syntax)
15992 as_warn (_("conditional infixes are deprecated in unified syntax"));
15993 affix = base + (opcode->tag - OT_odd_infix_0);
15994 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15997 inst.cond = cond->value;
16001 /* Cannot have a conditional suffix on a mnemonic of less than two
16003 if (end - base < 3)
16006 /* Look for suffixed mnemonic. */
16008 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16009 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16011 if (opcode && cond)
16014 switch (opcode->tag)
16016 case OT_cinfix3_legacy:
16017 /* Ignore conditional suffixes matched on infix only mnemonics. */
16021 case OT_cinfix3_deprecated:
16022 case OT_odd_infix_unc:
16023 if (!unified_syntax)
16025 /* else fall through */
16029 case OT_csuf_or_in3:
16030 inst.cond = cond->value;
16033 case OT_unconditional:
16034 case OT_unconditionalF:
16036 inst.cond = cond->value;
16039 /* Delayed diagnostic. */
16040 inst.error = BAD_COND;
16041 inst.cond = COND_ALWAYS;
16050 /* Cannot have a usual-position infix on a mnemonic of less than
16051 six characters (five would be a suffix). */
16052 if (end - base < 6)
16055 /* Look for infixed mnemonic in the usual position. */
16057 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16061 memcpy (save, affix, 2);
16062 memmove (affix, affix + 2, (end - affix) - 2);
16063 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16065 memmove (affix + 2, affix, (end - affix) - 2);
16066 memcpy (affix, save, 2);
16069 && (opcode->tag == OT_cinfix3
16070 || opcode->tag == OT_cinfix3_deprecated
16071 || opcode->tag == OT_csuf_or_in3
16072 || opcode->tag == OT_cinfix3_legacy))
16075 if (warn_on_deprecated && unified_syntax
16076 && (opcode->tag == OT_cinfix3
16077 || opcode->tag == OT_cinfix3_deprecated))
16078 as_warn (_("conditional infixes are deprecated in unified syntax"));
16080 inst.cond = cond->value;
16087 /* This function generates an initial IT instruction, leaving its block
16088 virtually open for the new instructions. Eventually,
16089 the mask will be updated by now_it_add_mask () each time
16090 a new instruction needs to be included in the IT block.
16091 Finally, the block is closed with close_automatic_it_block ().
16092 The block closure can be requested either from md_assemble (),
16093 a tencode (), or due to a label hook. */
16096 new_automatic_it_block (int cond)
16098 now_it.state = AUTOMATIC_IT_BLOCK;
16099 now_it.mask = 0x18;
16101 now_it.block_length = 1;
16102 mapping_state (MAP_THUMB);
16103 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16106 /* Close an automatic IT block.
16107 See comments in new_automatic_it_block (). */
16110 close_automatic_it_block (void)
16112 now_it.mask = 0x10;
16113 now_it.block_length = 0;
16116 /* Update the mask of the current automatically-generated IT
16117 instruction. See comments in new_automatic_it_block (). */
16120 now_it_add_mask (int cond)
16122 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16123 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16124 | ((bitvalue) << (nbit)))
16125 const int resulting_bit = (cond & 1);
16127 now_it.mask &= 0xf;
16128 now_it.mask = SET_BIT_VALUE (now_it.mask,
16130 (5 - now_it.block_length));
16131 now_it.mask = SET_BIT_VALUE (now_it.mask,
16133 ((5 - now_it.block_length) - 1) );
16134 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16137 #undef SET_BIT_VALUE
16140 /* The IT blocks handling machinery is accessed through the these functions:
16141 it_fsm_pre_encode () from md_assemble ()
16142 set_it_insn_type () optional, from the tencode functions
16143 set_it_insn_type_last () ditto
16144 in_it_block () ditto
16145 it_fsm_post_encode () from md_assemble ()
16146 force_automatic_it_block_close () from label habdling functions
16149 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16150 initializing the IT insn type with a generic initial value depending
16151 on the inst.condition.
16152 2) During the tencode function, two things may happen:
16153 a) The tencode function overrides the IT insn type by
16154 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16155 b) The tencode function queries the IT block state by
16156 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16158 Both set_it_insn_type and in_it_block run the internal FSM state
16159 handling function (handle_it_state), because: a) setting the IT insn
16160 type may incur in an invalid state (exiting the function),
16161 and b) querying the state requires the FSM to be updated.
16162 Specifically we want to avoid creating an IT block for conditional
16163 branches, so it_fsm_pre_encode is actually a guess and we can't
16164 determine whether an IT block is required until the tencode () routine
16165 has decided what type of instruction this actually it.
16166 Because of this, if set_it_insn_type and in_it_block have to be used,
16167 set_it_insn_type has to be called first.
16169 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16170 determines the insn IT type depending on the inst.cond code.
16171 When a tencode () routine encodes an instruction that can be
16172 either outside an IT block, or, in the case of being inside, has to be
16173 the last one, set_it_insn_type_last () will determine the proper
16174 IT instruction type based on the inst.cond code. Otherwise,
16175 set_it_insn_type can be called for overriding that logic or
16176 for covering other cases.
16178 Calling handle_it_state () may not transition the IT block state to
16179 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16180 still queried. Instead, if the FSM determines that the state should
16181 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16182 after the tencode () function: that's what it_fsm_post_encode () does.
16184 Since in_it_block () calls the state handling function to get an
16185 updated state, an error may occur (due to invalid insns combination).
16186 In that case, inst.error is set.
16187 Therefore, inst.error has to be checked after the execution of
16188 the tencode () routine.
16190 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16191 any pending state change (if any) that didn't take place in
16192 handle_it_state () as explained above. */
16195 it_fsm_pre_encode (void)
16197 if (inst.cond != COND_ALWAYS)
16198 inst.it_insn_type = INSIDE_IT_INSN;
16200 inst.it_insn_type = OUTSIDE_IT_INSN;
16202 now_it.state_handled = 0;
16205 /* IT state FSM handling function. */
16208 handle_it_state (void)
16210 now_it.state_handled = 1;
16212 switch (now_it.state)
16214 case OUTSIDE_IT_BLOCK:
16215 switch (inst.it_insn_type)
16217 case OUTSIDE_IT_INSN:
16220 case INSIDE_IT_INSN:
16221 case INSIDE_IT_LAST_INSN:
16222 if (thumb_mode == 0)
16225 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16226 as_tsktsk (_("Warning: conditional outside an IT block"\
16231 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16232 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16234 /* Automatically generate the IT instruction. */
16235 new_automatic_it_block (inst.cond);
16236 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16237 close_automatic_it_block ();
16241 inst.error = BAD_OUT_IT;
16247 case IF_INSIDE_IT_LAST_INSN:
16248 case NEUTRAL_IT_INSN:
16252 now_it.state = MANUAL_IT_BLOCK;
16253 now_it.block_length = 0;
16258 case AUTOMATIC_IT_BLOCK:
16259 /* Three things may happen now:
16260 a) We should increment current it block size;
16261 b) We should close current it block (closing insn or 4 insns);
16262 c) We should close current it block and start a new one (due
16263 to incompatible conditions or
16264 4 insns-length block reached). */
16266 switch (inst.it_insn_type)
16268 case OUTSIDE_IT_INSN:
16269 /* The closure of the block shall happen immediatelly,
16270 so any in_it_block () call reports the block as closed. */
16271 force_automatic_it_block_close ();
16274 case INSIDE_IT_INSN:
16275 case INSIDE_IT_LAST_INSN:
16276 case IF_INSIDE_IT_LAST_INSN:
16277 now_it.block_length++;
16279 if (now_it.block_length > 4
16280 || !now_it_compatible (inst.cond))
16282 force_automatic_it_block_close ();
16283 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16284 new_automatic_it_block (inst.cond);
16288 now_it_add_mask (inst.cond);
16291 if (now_it.state == AUTOMATIC_IT_BLOCK
16292 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16293 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16294 close_automatic_it_block ();
16297 case NEUTRAL_IT_INSN:
16298 now_it.block_length++;
16300 if (now_it.block_length > 4)
16301 force_automatic_it_block_close ();
16303 now_it_add_mask (now_it.cc & 1);
16307 close_automatic_it_block ();
16308 now_it.state = MANUAL_IT_BLOCK;
16313 case MANUAL_IT_BLOCK:
16315 /* Check conditional suffixes. */
16316 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16319 now_it.mask &= 0x1f;
16320 is_last = (now_it.mask == 0x10);
16322 switch (inst.it_insn_type)
16324 case OUTSIDE_IT_INSN:
16325 inst.error = BAD_NOT_IT;
16328 case INSIDE_IT_INSN:
16329 if (cond != inst.cond)
16331 inst.error = BAD_IT_COND;
16336 case INSIDE_IT_LAST_INSN:
16337 case IF_INSIDE_IT_LAST_INSN:
16338 if (cond != inst.cond)
16340 inst.error = BAD_IT_COND;
16345 inst.error = BAD_BRANCH;
16350 case NEUTRAL_IT_INSN:
16351 /* The BKPT instruction is unconditional even in an IT block. */
16355 inst.error = BAD_IT_IT;
16366 it_fsm_post_encode (void)
16370 if (!now_it.state_handled)
16371 handle_it_state ();
16373 is_last = (now_it.mask == 0x10);
16376 now_it.state = OUTSIDE_IT_BLOCK;
16382 force_automatic_it_block_close (void)
16384 if (now_it.state == AUTOMATIC_IT_BLOCK)
16386 close_automatic_it_block ();
16387 now_it.state = OUTSIDE_IT_BLOCK;
16395 if (!now_it.state_handled)
16396 handle_it_state ();
16398 return now_it.state != OUTSIDE_IT_BLOCK;
16402 md_assemble (char *str)
16405 const struct asm_opcode * opcode;
16407 /* Align the previous label if needed. */
16408 if (last_label_seen != NULL)
16410 symbol_set_frag (last_label_seen, frag_now);
16411 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16412 S_SET_SEGMENT (last_label_seen, now_seg);
16415 memset (&inst, '\0', sizeof (inst));
16416 inst.reloc.type = BFD_RELOC_UNUSED;
16418 opcode = opcode_lookup (&p);
16421 /* It wasn't an instruction, but it might be a register alias of
16422 the form alias .req reg, or a Neon .dn/.qn directive. */
16423 if (! create_register_alias (str, p)
16424 && ! create_neon_reg_alias (str, p))
16425 as_bad (_("bad instruction `%s'"), str);
16430 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16431 as_warn (_("s suffix on comparison instruction is deprecated"));
16433 /* The value which unconditional instructions should have in place of the
16434 condition field. */
16435 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16439 arm_feature_set variant;
16441 variant = cpu_variant;
16442 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16443 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16444 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16445 /* Check that this instruction is supported for this CPU. */
16446 if (!opcode->tvariant
16447 || (thumb_mode == 1
16448 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16450 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16453 if (inst.cond != COND_ALWAYS && !unified_syntax
16454 && opcode->tencode != do_t_branch)
16456 as_bad (_("Thumb does not support conditional execution"));
16460 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16462 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16463 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16464 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16466 /* Two things are addressed here.
16467 1) Implicit require narrow instructions on Thumb-1.
16468 This avoids relaxation accidentally introducing Thumb-2
16470 2) Reject wide instructions in non Thumb-2 cores. */
16471 if (inst.size_req == 0)
16473 else if (inst.size_req == 4)
16475 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16481 inst.instruction = opcode->tvalue;
16483 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16485 /* Prepare the it_insn_type for those encodings that don't set
16487 it_fsm_pre_encode ();
16489 opcode->tencode ();
16491 it_fsm_post_encode ();
16494 if (!(inst.error || inst.relax))
16496 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16497 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16498 if (inst.size_req && inst.size_req != inst.size)
16500 as_bad (_("cannot honor width suffix -- `%s'"), str);
16505 /* Something has gone badly wrong if we try to relax a fixed size
16507 gas_assert (inst.size_req == 0 || !inst.relax);
16509 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16510 *opcode->tvariant);
16511 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16512 set those bits when Thumb-2 32-bit instructions are seen. ie.
16513 anything other than bl/blx and v6-M instructions.
16514 This is overly pessimistic for relaxable instructions. */
16515 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16517 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16518 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16519 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16522 check_neon_suffixes;
16526 mapping_state (MAP_THUMB);
16529 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16533 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16534 is_bx = (opcode->aencode == do_bx);
16536 /* Check that this instruction is supported for this CPU. */
16537 if (!(is_bx && fix_v4bx)
16538 && !(opcode->avariant &&
16539 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16541 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16546 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16550 inst.instruction = opcode->avalue;
16551 if (opcode->tag == OT_unconditionalF)
16552 inst.instruction |= 0xF << 28;
16554 inst.instruction |= inst.cond << 28;
16555 inst.size = INSN_SIZE;
16556 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16558 it_fsm_pre_encode ();
16559 opcode->aencode ();
16560 it_fsm_post_encode ();
16562 /* Arm mode bx is marked as both v4T and v5 because it's still required
16563 on a hypothetical non-thumb v5 core. */
16565 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16567 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16568 *opcode->avariant);
16570 check_neon_suffixes;
16574 mapping_state (MAP_ARM);
16579 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16587 check_it_blocks_finished (void)
16592 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16593 if (seg_info (sect)->tc_segment_info_data.current_it.state
16594 == MANUAL_IT_BLOCK)
16596 as_warn (_("section '%s' finished with an open IT block."),
16600 if (now_it.state == MANUAL_IT_BLOCK)
16601 as_warn (_("file finished with an open IT block."));
16605 /* Various frobbings of labels and their addresses. */
16608 arm_start_line_hook (void)
16610 last_label_seen = NULL;
16614 arm_frob_label (symbolS * sym)
16616 last_label_seen = sym;
16618 ARM_SET_THUMB (sym, thumb_mode);
16620 #if defined OBJ_COFF || defined OBJ_ELF
16621 ARM_SET_INTERWORK (sym, support_interwork);
16624 force_automatic_it_block_close ();
16626 /* Note - do not allow local symbols (.Lxxx) to be labelled
16627 as Thumb functions. This is because these labels, whilst
16628 they exist inside Thumb code, are not the entry points for
16629 possible ARM->Thumb calls. Also, these labels can be used
16630 as part of a computed goto or switch statement. eg gcc
16631 can generate code that looks like this:
16633 ldr r2, [pc, .Laaa]
16643 The first instruction loads the address of the jump table.
16644 The second instruction converts a table index into a byte offset.
16645 The third instruction gets the jump address out of the table.
16646 The fourth instruction performs the jump.
16648 If the address stored at .Laaa is that of a symbol which has the
16649 Thumb_Func bit set, then the linker will arrange for this address
16650 to have the bottom bit set, which in turn would mean that the
16651 address computation performed by the third instruction would end
16652 up with the bottom bit set. Since the ARM is capable of unaligned
16653 word loads, the instruction would then load the incorrect address
16654 out of the jump table, and chaos would ensue. */
16655 if (label_is_thumb_function_name
16656 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16657 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16659 /* When the address of a Thumb function is taken the bottom
16660 bit of that address should be set. This will allow
16661 interworking between Arm and Thumb functions to work
16664 THUMB_SET_FUNC (sym, 1);
16666 label_is_thumb_function_name = FALSE;
16669 dwarf2_emit_label (sym);
16673 arm_data_in_code (void)
16675 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16677 *input_line_pointer = '/';
16678 input_line_pointer += 5;
16679 *input_line_pointer = 0;
16687 arm_canonicalize_symbol_name (char * name)
16691 if (thumb_mode && (len = strlen (name)) > 5
16692 && streq (name + len - 5, "/data"))
16693 *(name + len - 5) = 0;
16698 /* Table of all register names defined by default. The user can
16699 define additional names with .req. Note that all register names
16700 should appear in both upper and lowercase variants. Some registers
16701 also have mixed-case names. */
16703 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16704 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16705 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16706 #define REGSET(p,t) \
16707 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16708 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16709 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16710 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16711 #define REGSETH(p,t) \
16712 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16713 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16714 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16715 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16716 #define REGSET2(p,t) \
16717 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16718 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16719 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16720 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16721 #define SPLRBANK(base,bank,t) \
16722 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16723 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16724 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16725 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16726 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16727 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16729 static const struct reg_entry reg_names[] =
16731 /* ARM integer registers. */
16732 REGSET(r, RN), REGSET(R, RN),
16734 /* ATPCS synonyms. */
16735 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16736 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16737 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16739 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16740 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16741 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16743 /* Well-known aliases. */
16744 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16745 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16747 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16748 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16750 /* Coprocessor numbers. */
16751 REGSET(p, CP), REGSET(P, CP),
16753 /* Coprocessor register numbers. The "cr" variants are for backward
16755 REGSET(c, CN), REGSET(C, CN),
16756 REGSET(cr, CN), REGSET(CR, CN),
16758 /* ARM banked registers. */
16759 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16760 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16761 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16762 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16763 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16764 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16765 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16767 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16768 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16769 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16770 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16771 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16772 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16773 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16774 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16776 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16777 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16778 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16779 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16780 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16781 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16782 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16783 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16784 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16786 /* FPA registers. */
16787 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16788 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16790 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16791 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16793 /* VFP SP registers. */
16794 REGSET(s,VFS), REGSET(S,VFS),
16795 REGSETH(s,VFS), REGSETH(S,VFS),
16797 /* VFP DP Registers. */
16798 REGSET(d,VFD), REGSET(D,VFD),
16799 /* Extra Neon DP registers. */
16800 REGSETH(d,VFD), REGSETH(D,VFD),
16802 /* Neon QP registers. */
16803 REGSET2(q,NQ), REGSET2(Q,NQ),
16805 /* VFP control registers. */
16806 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16807 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16808 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16809 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16810 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16811 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16813 /* Maverick DSP coprocessor registers. */
16814 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16815 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16817 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16818 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16819 REGDEF(dspsc,0,DSPSC),
16821 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16822 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16823 REGDEF(DSPSC,0,DSPSC),
16825 /* iWMMXt data registers - p0, c0-15. */
16826 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16828 /* iWMMXt control registers - p1, c0-3. */
16829 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16830 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16831 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16832 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16834 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16835 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16836 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16837 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16838 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16840 /* XScale accumulator registers. */
16841 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16847 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16848 within psr_required_here. */
16849 static const struct asm_psr psrs[] =
16851 /* Backward compatibility notation. Note that "all" is no longer
16852 truly all possible PSR bits. */
16853 {"all", PSR_c | PSR_f},
16857 /* Individual flags. */
16863 /* Combinations of flags. */
16864 {"fs", PSR_f | PSR_s},
16865 {"fx", PSR_f | PSR_x},
16866 {"fc", PSR_f | PSR_c},
16867 {"sf", PSR_s | PSR_f},
16868 {"sx", PSR_s | PSR_x},
16869 {"sc", PSR_s | PSR_c},
16870 {"xf", PSR_x | PSR_f},
16871 {"xs", PSR_x | PSR_s},
16872 {"xc", PSR_x | PSR_c},
16873 {"cf", PSR_c | PSR_f},
16874 {"cs", PSR_c | PSR_s},
16875 {"cx", PSR_c | PSR_x},
16876 {"fsx", PSR_f | PSR_s | PSR_x},
16877 {"fsc", PSR_f | PSR_s | PSR_c},
16878 {"fxs", PSR_f | PSR_x | PSR_s},
16879 {"fxc", PSR_f | PSR_x | PSR_c},
16880 {"fcs", PSR_f | PSR_c | PSR_s},
16881 {"fcx", PSR_f | PSR_c | PSR_x},
16882 {"sfx", PSR_s | PSR_f | PSR_x},
16883 {"sfc", PSR_s | PSR_f | PSR_c},
16884 {"sxf", PSR_s | PSR_x | PSR_f},
16885 {"sxc", PSR_s | PSR_x | PSR_c},
16886 {"scf", PSR_s | PSR_c | PSR_f},
16887 {"scx", PSR_s | PSR_c | PSR_x},
16888 {"xfs", PSR_x | PSR_f | PSR_s},
16889 {"xfc", PSR_x | PSR_f | PSR_c},
16890 {"xsf", PSR_x | PSR_s | PSR_f},
16891 {"xsc", PSR_x | PSR_s | PSR_c},
16892 {"xcf", PSR_x | PSR_c | PSR_f},
16893 {"xcs", PSR_x | PSR_c | PSR_s},
16894 {"cfs", PSR_c | PSR_f | PSR_s},
16895 {"cfx", PSR_c | PSR_f | PSR_x},
16896 {"csf", PSR_c | PSR_s | PSR_f},
16897 {"csx", PSR_c | PSR_s | PSR_x},
16898 {"cxf", PSR_c | PSR_x | PSR_f},
16899 {"cxs", PSR_c | PSR_x | PSR_s},
16900 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16901 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16902 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16903 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16904 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16905 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16906 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16907 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16908 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16909 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16910 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16911 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16912 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16913 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16914 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16915 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16916 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16917 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16918 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16919 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16920 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16921 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16922 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16923 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16926 /* Table of V7M psr names. */
16927 static const struct asm_psr v7m_psrs[] =
16929 {"apsr", 0 }, {"APSR", 0 },
16930 {"iapsr", 1 }, {"IAPSR", 1 },
16931 {"eapsr", 2 }, {"EAPSR", 2 },
16932 {"psr", 3 }, {"PSR", 3 },
16933 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16934 {"ipsr", 5 }, {"IPSR", 5 },
16935 {"epsr", 6 }, {"EPSR", 6 },
16936 {"iepsr", 7 }, {"IEPSR", 7 },
16937 {"msp", 8 }, {"MSP", 8 },
16938 {"psp", 9 }, {"PSP", 9 },
16939 {"primask", 16}, {"PRIMASK", 16},
16940 {"basepri", 17}, {"BASEPRI", 17},
16941 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16942 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16943 {"faultmask", 19}, {"FAULTMASK", 19},
16944 {"control", 20}, {"CONTROL", 20}
16947 /* Table of all shift-in-operand names. */
16948 static const struct asm_shift_name shift_names [] =
16950 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16951 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16952 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16953 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16954 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16955 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16958 /* Table of all explicit relocation names. */
16960 static struct reloc_entry reloc_names[] =
16962 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16963 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16964 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16965 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16966 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16967 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16968 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16969 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16970 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16971 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16972 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16973 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16974 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16975 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16976 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16977 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16978 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16979 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16983 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16984 static const struct asm_cond conds[] =
16988 {"cs", 0x2}, {"hs", 0x2},
16989 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17003 static struct asm_barrier_opt barrier_opt_names[] =
17005 { "sy", 0xf }, { "SY", 0xf },
17006 { "un", 0x7 }, { "UN", 0x7 },
17007 { "st", 0xe }, { "ST", 0xe },
17008 { "unst", 0x6 }, { "UNST", 0x6 },
17009 { "ish", 0xb }, { "ISH", 0xb },
17010 { "sh", 0xb }, { "SH", 0xb },
17011 { "ishst", 0xa }, { "ISHST", 0xa },
17012 { "shst", 0xa }, { "SHST", 0xa },
17013 { "nsh", 0x7 }, { "NSH", 0x7 },
17014 { "nshst", 0x6 }, { "NSHST", 0x6 },
17015 { "osh", 0x3 }, { "OSH", 0x3 },
17016 { "oshst", 0x2 }, { "OSHST", 0x2 }
17019 /* Table of ARM-format instructions. */
17021 /* Macros for gluing together operand strings. N.B. In all cases
17022 other than OPS0, the trailing OP_stop comes from default
17023 zero-initialization of the unspecified elements of the array. */
17024 #define OPS0() { OP_stop, }
17025 #define OPS1(a) { OP_##a, }
17026 #define OPS2(a,b) { OP_##a,OP_##b, }
17027 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17028 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17029 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17030 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17032 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17033 This is useful when mixing operands for ARM and THUMB, i.e. using the
17034 MIX_ARM_THUMB_OPERANDS macro.
17035 In order to use these macros, prefix the number of operands with _
17037 #define OPS_1(a) { a, }
17038 #define OPS_2(a,b) { a,b, }
17039 #define OPS_3(a,b,c) { a,b,c, }
17040 #define OPS_4(a,b,c,d) { a,b,c,d, }
17041 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17042 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17044 /* These macros abstract out the exact format of the mnemonic table and
17045 save some repeated characters. */
17047 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17048 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17049 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17050 THUMB_VARIANT, do_##ae, do_##te }
17052 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17053 a T_MNEM_xyz enumerator. */
17054 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17055 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17056 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17057 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17059 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17060 infix after the third character. */
17061 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17062 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17063 THUMB_VARIANT, do_##ae, do_##te }
17064 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17065 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17066 THUMB_VARIANT, do_##ae, do_##te }
17067 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17068 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17069 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17070 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17071 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17072 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17073 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17074 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17076 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17077 appear in the condition table. */
17078 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17079 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17080 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17082 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17083 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17084 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17085 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17086 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17087 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17088 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17089 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17090 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17091 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17092 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17093 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17094 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17095 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17096 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17097 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17098 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17099 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17100 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17101 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17103 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17104 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17105 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17106 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17108 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17109 field is still 0xE. Many of the Thumb variants can be executed
17110 conditionally, so this is checked separately. */
17111 #define TUE(mnem, op, top, nops, ops, ae, te) \
17112 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17113 THUMB_VARIANT, do_##ae, do_##te }
17115 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17116 condition code field. */
17117 #define TUF(mnem, op, top, nops, ops, ae, te) \
17118 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17119 THUMB_VARIANT, do_##ae, do_##te }
17121 /* ARM-only variants of all the above. */
17122 #define CE(mnem, op, nops, ops, ae) \
17123 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17125 #define C3(mnem, op, nops, ops, ae) \
17126 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17128 /* Legacy mnemonics that always have conditional infix after the third
17130 #define CL(mnem, op, nops, ops, ae) \
17131 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17132 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17134 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17135 #define cCE(mnem, op, nops, ops, ae) \
17136 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17138 /* Legacy coprocessor instructions where conditional infix and conditional
17139 suffix are ambiguous. For consistency this includes all FPA instructions,
17140 not just the potentially ambiguous ones. */
17141 #define cCL(mnem, op, nops, ops, ae) \
17142 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17143 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17145 /* Coprocessor, takes either a suffix or a position-3 infix
17146 (for an FPA corner case). */
17147 #define C3E(mnem, op, nops, ops, ae) \
17148 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17149 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17151 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17152 { m1 #m2 m3, OPS##nops ops, \
17153 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17154 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17156 #define CM(m1, m2, op, nops, ops, ae) \
17157 xCM_ (m1, , m2, op, nops, ops, ae), \
17158 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17159 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17160 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17161 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17162 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17163 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17164 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17165 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17166 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17167 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17168 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17169 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17170 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17171 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17172 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17173 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17174 xCM_ (m1, le, m2, op, nops, ops, ae), \
17175 xCM_ (m1, al, m2, op, nops, ops, ae)
17177 #define UE(mnem, op, nops, ops, ae) \
17178 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17180 #define UF(mnem, op, nops, ops, ae) \
17181 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17183 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17184 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17185 use the same encoding function for each. */
17186 #define NUF(mnem, op, nops, ops, enc) \
17187 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17188 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17190 /* Neon data processing, version which indirects through neon_enc_tab for
17191 the various overloaded versions of opcodes. */
17192 #define nUF(mnem, op, nops, ops, enc) \
17193 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17194 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17196 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17198 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17199 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17200 THUMB_VARIANT, do_##enc, do_##enc }
17202 #define NCE(mnem, op, nops, ops, enc) \
17203 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17205 #define NCEF(mnem, op, nops, ops, enc) \
17206 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17208 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17209 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17210 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17211 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17213 #define nCE(mnem, op, nops, ops, enc) \
17214 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17216 #define nCEF(mnem, op, nops, ops, enc) \
17217 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17221 static const struct asm_opcode insns[] =
17223 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17224 #define THUMB_VARIANT &arm_ext_v4t
17225 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17226 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17227 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17228 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17229 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17230 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17231 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17232 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17233 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17234 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17235 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17236 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17237 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17238 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17239 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17240 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17242 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17243 for setting PSR flag bits. They are obsolete in V6 and do not
17244 have Thumb equivalents. */
17245 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17246 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17247 CL("tstp", 110f000, 2, (RR, SH), cmp),
17248 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17249 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17250 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17251 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17252 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17253 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17255 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17256 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17257 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17258 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17260 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17261 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17262 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17264 OP_ADDRGLDR),ldst, t_ldst),
17265 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17267 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17268 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17269 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17270 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17271 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17272 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17274 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17275 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17276 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17277 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17280 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17281 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17282 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17284 /* Thumb-compatibility pseudo ops. */
17285 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17286 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17287 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17288 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17289 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17290 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17291 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17292 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17293 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17294 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17295 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17296 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17298 /* These may simplify to neg. */
17299 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17300 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17302 #undef THUMB_VARIANT
17303 #define THUMB_VARIANT & arm_ext_v6
17305 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17307 /* V1 instructions with no Thumb analogue prior to V6T2. */
17308 #undef THUMB_VARIANT
17309 #define THUMB_VARIANT & arm_ext_v6t2
17311 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17312 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17313 CL("teqp", 130f000, 2, (RR, SH), cmp),
17315 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17316 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17317 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17318 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17320 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17321 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17323 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17324 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17326 /* V1 instructions with no Thumb analogue at all. */
17327 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17328 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17330 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17331 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17332 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17333 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17334 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17335 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17336 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17337 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17340 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17341 #undef THUMB_VARIANT
17342 #define THUMB_VARIANT & arm_ext_v4t
17344 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17345 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17347 #undef THUMB_VARIANT
17348 #define THUMB_VARIANT & arm_ext_v6t2
17350 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17351 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17353 /* Generic coprocessor instructions. */
17354 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17355 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17356 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17357 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17358 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17359 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17360 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17363 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17365 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17366 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17369 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17370 #undef THUMB_VARIANT
17371 #define THUMB_VARIANT & arm_ext_msr
17373 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17374 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17377 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17378 #undef THUMB_VARIANT
17379 #define THUMB_VARIANT & arm_ext_v6t2
17381 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17382 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17383 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17384 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17385 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17386 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17387 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17388 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17391 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17392 #undef THUMB_VARIANT
17393 #define THUMB_VARIANT & arm_ext_v4t
17395 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17396 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17397 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17398 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17399 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17400 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17403 #define ARM_VARIANT & arm_ext_v4t_5
17405 /* ARM Architecture 4T. */
17406 /* Note: bx (and blx) are required on V5, even if the processor does
17407 not support Thumb. */
17408 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17411 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17412 #undef THUMB_VARIANT
17413 #define THUMB_VARIANT & arm_ext_v5t
17415 /* Note: blx has 2 variants; the .value coded here is for
17416 BLX(2). Only this variant has conditional execution. */
17417 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17418 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17420 #undef THUMB_VARIANT
17421 #define THUMB_VARIANT & arm_ext_v6t2
17423 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17424 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17425 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17426 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17427 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17428 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17429 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17430 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17433 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17434 #undef THUMB_VARIANT
17435 #define THUMB_VARIANT &arm_ext_v5exp
17437 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17438 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17439 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17440 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17442 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17443 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17445 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17446 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17447 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17448 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17450 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17451 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17452 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17453 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17455 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17456 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17458 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17459 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17460 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17461 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17464 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17465 #undef THUMB_VARIANT
17466 #define THUMB_VARIANT &arm_ext_v6t2
17468 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17469 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17471 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17472 ADDRGLDRS), ldrd, t_ldstd),
17474 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17475 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17478 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17480 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17483 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17484 #undef THUMB_VARIANT
17485 #define THUMB_VARIANT & arm_ext_v6
17487 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17488 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17489 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17490 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17491 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17492 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17493 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17494 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17495 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17496 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17498 #undef THUMB_VARIANT
17499 #define THUMB_VARIANT & arm_ext_v6t2
17501 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17502 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17504 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17505 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17507 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17508 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17510 /* ARM V6 not included in V7M. */
17511 #undef THUMB_VARIANT
17512 #define THUMB_VARIANT & arm_ext_v6_notm
17513 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17514 UF(rfeib, 9900a00, 1, (RRw), rfe),
17515 UF(rfeda, 8100a00, 1, (RRw), rfe),
17516 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17517 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17518 UF(rfefa, 9900a00, 1, (RRw), rfe),
17519 UF(rfeea, 8100a00, 1, (RRw), rfe),
17520 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17521 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17522 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17523 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17524 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17526 /* ARM V6 not included in V7M (eg. integer SIMD). */
17527 #undef THUMB_VARIANT
17528 #define THUMB_VARIANT & arm_ext_v6_dsp
17529 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17530 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17531 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17532 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17533 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17534 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17535 /* Old name for QASX. */
17536 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17537 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17538 /* Old name for QSAX. */
17539 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17540 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17541 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17542 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17543 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17544 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17545 /* Old name for SASX. */
17546 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17547 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17548 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17549 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17550 /* Old name for SHASX. */
17551 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17552 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17553 /* Old name for SHSAX. */
17554 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17555 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17556 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17557 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17558 /* Old name for SSAX. */
17559 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17560 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17561 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17562 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17563 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17564 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17565 /* Old name for UASX. */
17566 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17567 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17568 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17569 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17570 /* Old name for UHASX. */
17571 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17572 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17573 /* Old name for UHSAX. */
17574 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17575 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17576 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17577 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17578 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17579 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17580 /* Old name for UQASX. */
17581 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17582 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17583 /* Old name for UQSAX. */
17584 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17585 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17586 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17587 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17588 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17589 /* Old name for USAX. */
17590 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17591 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17592 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17593 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17594 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17595 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17596 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17597 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17598 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17599 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17600 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17601 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17602 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17603 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17604 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17605 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17606 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17607 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17608 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17609 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17610 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17611 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17612 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17613 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17614 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17615 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17616 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17617 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17618 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17619 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17620 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17621 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17622 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17623 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17626 #define ARM_VARIANT & arm_ext_v6k
17627 #undef THUMB_VARIANT
17628 #define THUMB_VARIANT & arm_ext_v6k
17630 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17631 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17632 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17633 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17635 #undef THUMB_VARIANT
17636 #define THUMB_VARIANT & arm_ext_v6_notm
17637 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17639 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17640 RRnpcb), strexd, t_strexd),
17642 #undef THUMB_VARIANT
17643 #define THUMB_VARIANT & arm_ext_v6t2
17644 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17646 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17648 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17650 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17652 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17655 #define ARM_VARIANT & arm_ext_sec
17656 #undef THUMB_VARIANT
17657 #define THUMB_VARIANT & arm_ext_sec
17659 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17662 #define ARM_VARIANT & arm_ext_virt
17663 #undef THUMB_VARIANT
17664 #define THUMB_VARIANT & arm_ext_virt
17666 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17667 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17670 #define ARM_VARIANT & arm_ext_v6t2
17671 #undef THUMB_VARIANT
17672 #define THUMB_VARIANT & arm_ext_v6t2
17674 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17675 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17676 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17677 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17679 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17680 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17681 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17682 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17684 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17685 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17686 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17687 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17689 /* Thumb-only instructions. */
17691 #define ARM_VARIANT NULL
17692 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17693 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17695 /* ARM does not really have an IT instruction, so always allow it.
17696 The opcode is copied from Thumb in order to allow warnings in
17697 -mimplicit-it=[never | arm] modes. */
17699 #define ARM_VARIANT & arm_ext_v1
17701 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17702 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17703 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17704 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17705 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17706 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17707 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17708 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17709 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17710 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17711 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17712 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17713 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17714 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17715 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17716 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17717 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17718 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17720 /* Thumb2 only instructions. */
17722 #define ARM_VARIANT NULL
17724 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17725 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17726 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17727 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17728 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17729 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17731 /* Hardware division instructions. */
17733 #define ARM_VARIANT & arm_ext_adiv
17734 #undef THUMB_VARIANT
17735 #define THUMB_VARIANT & arm_ext_div
17737 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17738 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17740 /* ARM V6M/V7 instructions. */
17742 #define ARM_VARIANT & arm_ext_barrier
17743 #undef THUMB_VARIANT
17744 #define THUMB_VARIANT & arm_ext_barrier
17746 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17747 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17748 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17750 /* ARM V7 instructions. */
17752 #define ARM_VARIANT & arm_ext_v7
17753 #undef THUMB_VARIANT
17754 #define THUMB_VARIANT & arm_ext_v7
17756 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17757 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17760 #define ARM_VARIANT & arm_ext_mp
17761 #undef THUMB_VARIANT
17762 #define THUMB_VARIANT & arm_ext_mp
17764 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17767 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17769 cCE("wfs", e200110, 1, (RR), rd),
17770 cCE("rfs", e300110, 1, (RR), rd),
17771 cCE("wfc", e400110, 1, (RR), rd),
17772 cCE("rfc", e500110, 1, (RR), rd),
17774 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17775 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17776 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17777 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17779 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17780 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17781 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17782 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17784 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17785 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17786 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17787 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17788 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17789 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17790 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17791 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17792 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17793 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17794 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17795 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17797 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17798 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17799 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17800 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17801 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17802 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17803 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17804 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17805 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17806 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17807 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17808 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17810 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17811 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17812 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17813 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17814 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17815 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17816 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17817 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17818 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17819 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17820 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17821 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17823 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17824 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17825 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17826 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17827 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17828 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17829 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17830 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17831 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17832 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17833 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17834 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17836 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17837 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17838 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17839 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17840 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17841 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17842 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17843 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17844 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17845 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17846 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17847 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17849 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17850 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17851 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17852 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17853 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17854 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17855 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17856 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17857 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17858 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17859 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17860 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17862 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17863 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17864 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17865 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17866 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17867 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17868 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17869 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17870 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17871 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17872 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17873 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17875 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17876 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17877 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17878 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17879 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17880 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17881 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17882 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17883 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17884 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17885 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17886 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17888 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17889 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17890 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17891 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17892 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17893 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17894 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17895 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17896 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17897 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17898 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17899 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17901 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17902 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17903 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17904 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17905 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17906 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17907 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17908 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17909 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17910 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17911 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17912 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17914 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17915 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17916 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17917 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17918 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17919 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17920 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17921 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17922 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17923 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17924 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17925 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17927 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17928 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17929 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17930 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17931 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17932 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17933 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17934 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17935 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17936 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17937 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17938 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17940 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17941 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17942 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17943 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17944 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17945 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17946 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17947 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17948 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17949 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17950 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17951 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17953 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17954 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17955 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17956 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17957 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17958 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17959 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17960 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17961 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17962 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17963 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17964 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17966 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17967 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17968 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17969 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17970 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17971 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17972 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17973 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17974 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17975 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17976 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17977 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17979 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17980 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17981 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17982 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17983 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17984 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17985 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17986 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17987 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17988 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17989 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17990 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17992 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18065 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18067 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18070 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18077 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18078 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18079 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18080 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18083 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18090 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18091 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18092 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18093 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18094 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18096 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18097 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18098 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18099 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18100 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18101 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18102 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18103 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18104 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18105 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18106 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18107 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18109 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18110 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18111 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18112 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18113 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18114 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18115 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18116 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18117 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18118 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18119 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18120 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18122 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18123 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18124 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18125 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18126 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18127 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18128 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18129 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18130 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18131 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18132 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18133 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18135 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18136 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18137 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18138 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18139 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18140 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18141 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18142 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18143 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18144 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18145 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18146 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18148 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18149 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18150 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18151 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18152 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18153 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18154 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18155 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18156 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18157 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18158 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18159 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18161 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18162 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18163 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18164 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18166 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18167 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18168 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18169 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18170 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18171 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18172 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18173 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18174 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18175 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18176 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18177 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18179 /* The implementation of the FIX instruction is broken on some
18180 assemblers, in that it accepts a precision specifier as well as a
18181 rounding specifier, despite the fact that this is meaningless.
18182 To be more compatible, we accept it as well, though of course it
18183 does not set any bits. */
18184 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18185 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18186 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18187 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18188 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18189 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18190 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18191 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18192 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18193 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18194 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18195 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18196 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18198 /* Instructions that were new with the real FPA, call them V2. */
18200 #define ARM_VARIANT & fpu_fpa_ext_v2
18202 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18203 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18204 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18205 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18206 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18207 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18210 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18212 /* Moves and type conversions. */
18213 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18214 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18215 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18216 cCE("fmstat", ef1fa10, 0, (), noargs),
18217 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18218 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18219 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18220 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18221 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18222 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18223 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18224 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18225 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18226 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18228 /* Memory operations. */
18229 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18230 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18231 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18232 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18233 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18234 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18235 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18236 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18237 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18238 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18239 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18240 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18241 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18242 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18243 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18244 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18245 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18246 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18248 /* Monadic operations. */
18249 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18250 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18251 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18253 /* Dyadic operations. */
18254 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18255 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18256 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18257 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18258 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18259 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18260 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18261 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18262 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18265 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18266 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18267 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18268 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18270 /* Double precision load/store are still present on single precision
18271 implementations. */
18272 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18273 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18274 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18275 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18276 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18277 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18278 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18279 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18280 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18281 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18284 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18286 /* Moves and type conversions. */
18287 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18288 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18289 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18290 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18291 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18292 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18293 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18294 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18295 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18296 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18297 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18298 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18299 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18301 /* Monadic operations. */
18302 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18303 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18304 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18306 /* Dyadic operations. */
18307 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18308 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18309 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18310 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18311 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18312 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18313 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18314 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18315 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18318 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18319 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18320 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18321 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18324 #define ARM_VARIANT & fpu_vfp_ext_v2
18326 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18327 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18328 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18329 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18331 /* Instructions which may belong to either the Neon or VFP instruction sets.
18332 Individual encoder functions perform additional architecture checks. */
18334 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18335 #undef THUMB_VARIANT
18336 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18338 /* These mnemonics are unique to VFP. */
18339 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18340 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18341 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18342 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18343 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18344 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18345 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18346 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18347 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18348 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18350 /* Mnemonics shared by Neon and VFP. */
18351 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18352 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18353 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18355 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18356 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18358 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18359 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18361 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18362 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18363 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18364 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18365 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18366 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18367 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18368 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18370 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18371 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18372 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18373 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18376 /* NOTE: All VMOV encoding is special-cased! */
18377 NCE(vmov, 0, 1, (VMOV), neon_mov),
18378 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18380 #undef THUMB_VARIANT
18381 #define THUMB_VARIANT & fpu_neon_ext_v1
18383 #define ARM_VARIANT & fpu_neon_ext_v1
18385 /* Data processing with three registers of the same length. */
18386 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18387 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18388 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18389 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18390 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18391 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18392 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18393 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18394 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18395 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18396 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18397 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18398 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18399 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18400 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18401 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18402 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18403 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18404 /* If not immediate, fall back to neon_dyadic_i64_su.
18405 shl_imm should accept I8 I16 I32 I64,
18406 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18407 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18408 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18409 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18410 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18411 /* Logic ops, types optional & ignored. */
18412 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18413 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18414 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18415 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18416 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18417 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18418 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18419 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18420 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18421 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18422 /* Bitfield ops, untyped. */
18423 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18424 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18425 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18426 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18427 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18428 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18429 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18430 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18431 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18432 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18433 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18434 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18435 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18436 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18437 back to neon_dyadic_if_su. */
18438 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18439 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18440 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18441 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18442 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18443 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18444 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18445 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18446 /* Comparison. Type I8 I16 I32 F32. */
18447 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18448 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18449 /* As above, D registers only. */
18450 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18451 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18452 /* Int and float variants, signedness unimportant. */
18453 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18454 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18455 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18456 /* Add/sub take types I8 I16 I32 I64 F32. */
18457 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18458 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18459 /* vtst takes sizes 8, 16, 32. */
18460 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18461 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18462 /* VMUL takes I8 I16 I32 F32 P8. */
18463 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18464 /* VQD{R}MULH takes S16 S32. */
18465 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18466 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18467 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18468 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18469 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18470 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18471 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18472 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18473 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18474 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18475 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18476 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18477 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18478 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18479 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18480 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18482 /* Two address, int/float. Types S8 S16 S32 F32. */
18483 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18484 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18486 /* Data processing with two registers and a shift amount. */
18487 /* Right shifts, and variants with rounding.
18488 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18489 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18490 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18491 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18492 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18493 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18494 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18495 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18496 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18497 /* Shift and insert. Sizes accepted 8 16 32 64. */
18498 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18499 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18500 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18501 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18502 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18503 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18504 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18505 /* Right shift immediate, saturating & narrowing, with rounding variants.
18506 Types accepted S16 S32 S64 U16 U32 U64. */
18507 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18508 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18509 /* As above, unsigned. Types accepted S16 S32 S64. */
18510 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18511 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18512 /* Right shift narrowing. Types accepted I16 I32 I64. */
18513 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18514 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18515 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18516 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18517 /* CVT with optional immediate for fixed-point variant. */
18518 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18520 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18521 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18523 /* Data processing, three registers of different lengths. */
18524 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18525 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18526 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18527 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18528 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18529 /* If not scalar, fall back to neon_dyadic_long.
18530 Vector types as above, scalar types S16 S32 U16 U32. */
18531 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18532 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18533 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18534 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18535 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18536 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18537 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18538 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18539 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18540 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18541 /* Saturating doubling multiplies. Types S16 S32. */
18542 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18543 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18544 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18545 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18546 S16 S32 U16 U32. */
18547 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18549 /* Extract. Size 8. */
18550 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18551 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18553 /* Two registers, miscellaneous. */
18554 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18555 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18556 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18557 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18558 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18559 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18560 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18561 /* Vector replicate. Sizes 8 16 32. */
18562 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18563 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18564 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18565 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18566 /* VMOVN. Types I16 I32 I64. */
18567 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18568 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18569 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18570 /* VQMOVUN. Types S16 S32 S64. */
18571 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18572 /* VZIP / VUZP. Sizes 8 16 32. */
18573 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18574 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18575 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18576 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18577 /* VQABS / VQNEG. Types S8 S16 S32. */
18578 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18579 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18580 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18581 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18582 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18583 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18584 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18585 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18586 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18587 /* Reciprocal estimates. Types U32 F32. */
18588 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18589 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18590 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18591 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18592 /* VCLS. Types S8 S16 S32. */
18593 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18594 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18595 /* VCLZ. Types I8 I16 I32. */
18596 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18597 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18598 /* VCNT. Size 8. */
18599 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18600 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18601 /* Two address, untyped. */
18602 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18603 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18604 /* VTRN. Sizes 8 16 32. */
18605 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18606 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18608 /* Table lookup. Size 8. */
18609 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18610 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18612 #undef THUMB_VARIANT
18613 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18615 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18617 /* Neon element/structure load/store. */
18618 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18619 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18620 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18621 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18622 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18623 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18624 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18625 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18627 #undef THUMB_VARIANT
18628 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18630 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18631 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18632 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18633 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18634 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18635 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18636 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18637 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18638 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18639 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18641 #undef THUMB_VARIANT
18642 #define THUMB_VARIANT & fpu_vfp_ext_v3
18644 #define ARM_VARIANT & fpu_vfp_ext_v3
18646 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18647 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18648 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18649 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18650 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18651 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18652 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18653 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18654 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18657 #define ARM_VARIANT &fpu_vfp_ext_fma
18658 #undef THUMB_VARIANT
18659 #define THUMB_VARIANT &fpu_vfp_ext_fma
18660 /* Mnemonics shared by Neon and VFP. These are included in the
18661 VFP FMA variant; NEON and VFP FMA always includes the NEON
18662 FMA instructions. */
18663 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18664 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18665 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18666 the v form should always be used. */
18667 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18668 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18669 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18670 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18671 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18672 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18674 #undef THUMB_VARIANT
18676 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18678 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18679 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18680 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18681 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18682 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18683 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18684 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18685 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18688 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18690 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18691 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18692 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18693 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18694 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18695 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18696 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18697 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18698 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18699 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18700 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18701 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18702 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18703 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18704 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18705 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18706 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18707 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18708 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18709 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18710 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18711 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18712 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18713 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18714 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18715 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18716 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18717 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18718 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18719 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18720 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18721 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18722 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18723 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18724 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18725 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18726 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18727 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18728 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18729 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18733 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18734 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18735 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18736 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18737 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18738 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18739 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18740 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18741 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18742 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18743 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18744 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18745 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18746 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18747 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18748 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18749 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18750 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18751 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18752 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18753 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18754 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18755 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18757 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18758 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18759 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18760 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18764 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18775 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18779 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18786 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18787 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18788 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18789 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18790 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18791 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18792 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18793 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18794 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18795 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18796 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18801 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18802 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18803 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18804 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18805 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18806 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18807 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18808 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18809 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18810 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18811 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18812 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18813 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18814 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18815 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18816 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18817 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18818 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18819 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18820 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18821 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18822 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18823 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18829 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18830 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18831 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18832 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18833 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18834 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18835 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18836 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18837 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18838 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18839 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18840 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18841 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18842 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18843 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18844 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18845 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18846 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18847 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18848 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18849 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18850 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18851 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18854 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18856 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18857 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18858 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18859 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18860 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18861 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18862 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18863 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18864 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18865 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18866 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18867 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18868 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18869 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18870 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18871 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18872 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18873 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18874 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18875 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18876 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18877 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18878 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18879 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18880 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18881 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18882 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18883 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18884 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18885 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18886 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18887 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18888 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18889 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18890 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18891 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18892 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18893 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18894 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18895 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18896 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18897 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18898 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18899 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18900 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18901 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18902 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18903 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18904 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18905 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18906 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18907 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18908 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18909 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18910 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18911 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18912 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18915 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18917 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18918 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18919 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18920 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18921 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18922 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18923 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18924 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18925 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18926 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18927 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18928 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18929 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18930 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18931 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18932 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18933 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18934 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18935 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18936 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18937 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18938 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18939 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18940 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18941 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18942 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18943 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18944 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18945 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18946 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18947 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18948 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18949 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18950 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18951 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18952 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18953 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18954 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18955 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18956 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18957 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18958 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18959 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18960 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18961 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18962 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18963 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18964 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18965 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18966 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18967 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18968 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18969 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18970 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18971 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18972 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18973 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18974 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18975 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18976 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18977 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18978 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18979 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18980 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18981 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18982 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18983 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18984 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18985 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18986 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18987 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18988 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18989 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18990 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18991 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18992 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18995 #undef THUMB_VARIANT
19022 /* MD interface: bits in the object file. */
19024 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19025 for use in the a.out file, and stores them in the array pointed to by buf.
19026 This knows about the endian-ness of the target machine and does
19027 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19028 2 (short) and 4 (long) Floating numbers are put out as a series of
19029 LITTLENUMS (shorts, here at least). */
19032 md_number_to_chars (char * buf, valueT val, int n)
19034 if (target_big_endian)
19035 number_to_chars_bigendian (buf, val, n);
19037 number_to_chars_littleendian (buf, val, n);
19041 md_chars_to_number (char * buf, int n)
19044 unsigned char * where = (unsigned char *) buf;
19046 if (target_big_endian)
19051 result |= (*where++ & 255);
19059 result |= (where[n] & 255);
19066 /* MD interface: Sections. */
19068 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19069 that an rs_machine_dependent frag may reach. */
19072 arm_frag_max_var (fragS *fragp)
19074 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19075 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19077 Note that we generate relaxable instructions even for cases that don't
19078 really need it, like an immediate that's a trivial constant. So we're
19079 overestimating the instruction size for some of those cases. Rather
19080 than putting more intelligence here, it would probably be better to
19081 avoid generating a relaxation frag in the first place when it can be
19082 determined up front that a short instruction will suffice. */
19084 gas_assert (fragp->fr_type == rs_machine_dependent);
19088 /* Estimate the size of a frag before relaxing. Assume everything fits in
19092 md_estimate_size_before_relax (fragS * fragp,
19093 segT segtype ATTRIBUTE_UNUSED)
19099 /* Convert a machine dependent frag. */
19102 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19104 unsigned long insn;
19105 unsigned long old_op;
19113 buf = fragp->fr_literal + fragp->fr_fix;
19115 old_op = bfd_get_16(abfd, buf);
19116 if (fragp->fr_symbol)
19118 exp.X_op = O_symbol;
19119 exp.X_add_symbol = fragp->fr_symbol;
19123 exp.X_op = O_constant;
19125 exp.X_add_number = fragp->fr_offset;
19126 opcode = fragp->fr_subtype;
19129 case T_MNEM_ldr_pc:
19130 case T_MNEM_ldr_pc2:
19131 case T_MNEM_ldr_sp:
19132 case T_MNEM_str_sp:
19139 if (fragp->fr_var == 4)
19141 insn = THUMB_OP32 (opcode);
19142 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19144 insn |= (old_op & 0x700) << 4;
19148 insn |= (old_op & 7) << 12;
19149 insn |= (old_op & 0x38) << 13;
19151 insn |= 0x00000c00;
19152 put_thumb32_insn (buf, insn);
19153 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19157 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19159 pc_rel = (opcode == T_MNEM_ldr_pc2);
19162 if (fragp->fr_var == 4)
19164 insn = THUMB_OP32 (opcode);
19165 insn |= (old_op & 0xf0) << 4;
19166 put_thumb32_insn (buf, insn);
19167 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19171 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19172 exp.X_add_number -= 4;
19180 if (fragp->fr_var == 4)
19182 int r0off = (opcode == T_MNEM_mov
19183 || opcode == T_MNEM_movs) ? 0 : 8;
19184 insn = THUMB_OP32 (opcode);
19185 insn = (insn & 0xe1ffffff) | 0x10000000;
19186 insn |= (old_op & 0x700) << r0off;
19187 put_thumb32_insn (buf, insn);
19188 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19192 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19197 if (fragp->fr_var == 4)
19199 insn = THUMB_OP32(opcode);
19200 put_thumb32_insn (buf, insn);
19201 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19204 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19208 if (fragp->fr_var == 4)
19210 insn = THUMB_OP32(opcode);
19211 insn |= (old_op & 0xf00) << 14;
19212 put_thumb32_insn (buf, insn);
19213 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19216 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19219 case T_MNEM_add_sp:
19220 case T_MNEM_add_pc:
19221 case T_MNEM_inc_sp:
19222 case T_MNEM_dec_sp:
19223 if (fragp->fr_var == 4)
19225 /* ??? Choose between add and addw. */
19226 insn = THUMB_OP32 (opcode);
19227 insn |= (old_op & 0xf0) << 4;
19228 put_thumb32_insn (buf, insn);
19229 if (opcode == T_MNEM_add_pc)
19230 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19232 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19235 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19243 if (fragp->fr_var == 4)
19245 insn = THUMB_OP32 (opcode);
19246 insn |= (old_op & 0xf0) << 4;
19247 insn |= (old_op & 0xf) << 16;
19248 put_thumb32_insn (buf, insn);
19249 if (insn & (1 << 20))
19250 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19252 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19255 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19261 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19262 (enum bfd_reloc_code_real) reloc_type);
19263 fixp->fx_file = fragp->fr_file;
19264 fixp->fx_line = fragp->fr_line;
19265 fragp->fr_fix += fragp->fr_var;
19268 /* Return the size of a relaxable immediate operand instruction.
19269 SHIFT and SIZE specify the form of the allowable immediate. */
19271 relax_immediate (fragS *fragp, int size, int shift)
19277 /* ??? Should be able to do better than this. */
19278 if (fragp->fr_symbol)
19281 low = (1 << shift) - 1;
19282 mask = (1 << (shift + size)) - (1 << shift);
19283 offset = fragp->fr_offset;
19284 /* Force misaligned offsets to 32-bit variant. */
19287 if (offset & ~mask)
19292 /* Get the address of a symbol during relaxation. */
19294 relaxed_symbol_addr (fragS *fragp, long stretch)
19300 sym = fragp->fr_symbol;
19301 sym_frag = symbol_get_frag (sym);
19302 know (S_GET_SEGMENT (sym) != absolute_section
19303 || sym_frag == &zero_address_frag);
19304 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19306 /* If frag has yet to be reached on this pass, assume it will
19307 move by STRETCH just as we did. If this is not so, it will
19308 be because some frag between grows, and that will force
19312 && sym_frag->relax_marker != fragp->relax_marker)
19316 /* Adjust stretch for any alignment frag. Note that if have
19317 been expanding the earlier code, the symbol may be
19318 defined in what appears to be an earlier frag. FIXME:
19319 This doesn't handle the fr_subtype field, which specifies
19320 a maximum number of bytes to skip when doing an
19322 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19324 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19327 stretch = - ((- stretch)
19328 & ~ ((1 << (int) f->fr_offset) - 1));
19330 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19342 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19345 relax_adr (fragS *fragp, asection *sec, long stretch)
19350 /* Assume worst case for symbols not known to be in the same section. */
19351 if (fragp->fr_symbol == NULL
19352 || !S_IS_DEFINED (fragp->fr_symbol)
19353 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19354 || S_IS_WEAK (fragp->fr_symbol))
19357 val = relaxed_symbol_addr (fragp, stretch);
19358 addr = fragp->fr_address + fragp->fr_fix;
19359 addr = (addr + 4) & ~3;
19360 /* Force misaligned targets to 32-bit variant. */
19364 if (val < 0 || val > 1020)
19369 /* Return the size of a relaxable add/sub immediate instruction. */
19371 relax_addsub (fragS *fragp, asection *sec)
19376 buf = fragp->fr_literal + fragp->fr_fix;
19377 op = bfd_get_16(sec->owner, buf);
19378 if ((op & 0xf) == ((op >> 4) & 0xf))
19379 return relax_immediate (fragp, 8, 0);
19381 return relax_immediate (fragp, 3, 0);
19385 /* Return the size of a relaxable branch instruction. BITS is the
19386 size of the offset field in the narrow instruction. */
19389 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19395 /* Assume worst case for symbols not known to be in the same section. */
19396 if (!S_IS_DEFINED (fragp->fr_symbol)
19397 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19398 || S_IS_WEAK (fragp->fr_symbol))
19402 if (S_IS_DEFINED (fragp->fr_symbol)
19403 && ARM_IS_FUNC (fragp->fr_symbol))
19406 /* PR 12532. Global symbols with default visibility might
19407 be preempted, so do not relax relocations to them. */
19408 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19409 && (! S_IS_LOCAL (fragp->fr_symbol)))
19413 val = relaxed_symbol_addr (fragp, stretch);
19414 addr = fragp->fr_address + fragp->fr_fix + 4;
19417 /* Offset is a signed value *2 */
19419 if (val >= limit || val < -limit)
19425 /* Relax a machine dependent frag. This returns the amount by which
19426 the current size of the frag should change. */
19429 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19434 oldsize = fragp->fr_var;
19435 switch (fragp->fr_subtype)
19437 case T_MNEM_ldr_pc2:
19438 newsize = relax_adr (fragp, sec, stretch);
19440 case T_MNEM_ldr_pc:
19441 case T_MNEM_ldr_sp:
19442 case T_MNEM_str_sp:
19443 newsize = relax_immediate (fragp, 8, 2);
19447 newsize = relax_immediate (fragp, 5, 2);
19451 newsize = relax_immediate (fragp, 5, 1);
19455 newsize = relax_immediate (fragp, 5, 0);
19458 newsize = relax_adr (fragp, sec, stretch);
19464 newsize = relax_immediate (fragp, 8, 0);
19467 newsize = relax_branch (fragp, sec, 11, stretch);
19470 newsize = relax_branch (fragp, sec, 8, stretch);
19472 case T_MNEM_add_sp:
19473 case T_MNEM_add_pc:
19474 newsize = relax_immediate (fragp, 8, 2);
19476 case T_MNEM_inc_sp:
19477 case T_MNEM_dec_sp:
19478 newsize = relax_immediate (fragp, 7, 2);
19484 newsize = relax_addsub (fragp, sec);
19490 fragp->fr_var = newsize;
19491 /* Freeze wide instructions that are at or before the same location as
19492 in the previous pass. This avoids infinite loops.
19493 Don't freeze them unconditionally because targets may be artificially
19494 misaligned by the expansion of preceding frags. */
19495 if (stretch <= 0 && newsize > 2)
19497 md_convert_frag (sec->owner, sec, fragp);
19501 return newsize - oldsize;
19504 /* Round up a section size to the appropriate boundary. */
19507 md_section_align (segT segment ATTRIBUTE_UNUSED,
19510 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19511 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19513 /* For a.out, force the section size to be aligned. If we don't do
19514 this, BFD will align it for us, but it will not write out the
19515 final bytes of the section. This may be a bug in BFD, but it is
19516 easier to fix it here since that is how the other a.out targets
19520 align = bfd_get_section_alignment (stdoutput, segment);
19521 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19528 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19529 of an rs_align_code fragment. */
19532 arm_handle_align (fragS * fragP)
19534 static char const arm_noop[2][2][4] =
19537 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19538 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19541 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19542 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19545 static char const thumb_noop[2][2][2] =
19548 {0xc0, 0x46}, /* LE */
19549 {0x46, 0xc0}, /* BE */
19552 {0x00, 0xbf}, /* LE */
19553 {0xbf, 0x00} /* BE */
19556 static char const wide_thumb_noop[2][4] =
19557 { /* Wide Thumb-2 */
19558 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19559 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19562 unsigned bytes, fix, noop_size;
19565 const char *narrow_noop = NULL;
19570 if (fragP->fr_type != rs_align_code)
19573 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19574 p = fragP->fr_literal + fragP->fr_fix;
19577 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19578 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19580 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19582 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19584 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19586 narrow_noop = thumb_noop[1][target_big_endian];
19587 noop = wide_thumb_noop[target_big_endian];
19590 noop = thumb_noop[0][target_big_endian];
19598 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19599 [target_big_endian];
19606 fragP->fr_var = noop_size;
19608 if (bytes & (noop_size - 1))
19610 fix = bytes & (noop_size - 1);
19612 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19614 memset (p, 0, fix);
19621 if (bytes & noop_size)
19623 /* Insert a narrow noop. */
19624 memcpy (p, narrow_noop, noop_size);
19626 bytes -= noop_size;
19630 /* Use wide noops for the remainder */
19634 while (bytes >= noop_size)
19636 memcpy (p, noop, noop_size);
19638 bytes -= noop_size;
19642 fragP->fr_fix += fix;
19645 /* Called from md_do_align. Used to create an alignment
19646 frag in a code section. */
19649 arm_frag_align_code (int n, int max)
19653 /* We assume that there will never be a requirement
19654 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19655 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19660 _("alignments greater than %d bytes not supported in .text sections."),
19661 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19662 as_fatal ("%s", err_msg);
19665 p = frag_var (rs_align_code,
19666 MAX_MEM_FOR_RS_ALIGN_CODE,
19668 (relax_substateT) max,
19675 /* Perform target specific initialisation of a frag.
19676 Note - despite the name this initialisation is not done when the frag
19677 is created, but only when its type is assigned. A frag can be created
19678 and used a long time before its type is set, so beware of assuming that
19679 this initialisationis performed first. */
19683 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19685 /* Record whether this frag is in an ARM or a THUMB area. */
19686 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19689 #else /* OBJ_ELF is defined. */
19691 arm_init_frag (fragS * fragP, int max_chars)
19693 /* If the current ARM vs THUMB mode has not already
19694 been recorded into this frag then do so now. */
19695 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19697 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19699 /* Record a mapping symbol for alignment frags. We will delete this
19700 later if the alignment ends up empty. */
19701 switch (fragP->fr_type)
19704 case rs_align_test:
19706 mapping_state_2 (MAP_DATA, max_chars);
19708 case rs_align_code:
19709 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19717 /* When we change sections we need to issue a new mapping symbol. */
19720 arm_elf_change_section (void)
19722 /* Link an unlinked unwind index table section to the .text section. */
19723 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19724 && elf_linked_to_section (now_seg) == NULL)
19725 elf_linked_to_section (now_seg) = text_section;
19729 arm_elf_section_type (const char * str, size_t len)
19731 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19732 return SHT_ARM_EXIDX;
19737 /* Code to deal with unwinding tables. */
19739 static void add_unwind_adjustsp (offsetT);
19741 /* Generate any deferred unwind frame offset. */
19744 flush_pending_unwind (void)
19748 offset = unwind.pending_offset;
19749 unwind.pending_offset = 0;
19751 add_unwind_adjustsp (offset);
19754 /* Add an opcode to this list for this function. Two-byte opcodes should
19755 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19759 add_unwind_opcode (valueT op, int length)
19761 /* Add any deferred stack adjustment. */
19762 if (unwind.pending_offset)
19763 flush_pending_unwind ();
19765 unwind.sp_restored = 0;
19767 if (unwind.opcode_count + length > unwind.opcode_alloc)
19769 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19770 if (unwind.opcodes)
19771 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19772 unwind.opcode_alloc);
19774 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19779 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19781 unwind.opcode_count++;
19785 /* Add unwind opcodes to adjust the stack pointer. */
19788 add_unwind_adjustsp (offsetT offset)
19792 if (offset > 0x200)
19794 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19799 /* Long form: 0xb2, uleb128. */
19800 /* This might not fit in a word so add the individual bytes,
19801 remembering the list is built in reverse order. */
19802 o = (valueT) ((offset - 0x204) >> 2);
19804 add_unwind_opcode (0, 1);
19806 /* Calculate the uleb128 encoding of the offset. */
19810 bytes[n] = o & 0x7f;
19816 /* Add the insn. */
19818 add_unwind_opcode (bytes[n - 1], 1);
19819 add_unwind_opcode (0xb2, 1);
19821 else if (offset > 0x100)
19823 /* Two short opcodes. */
19824 add_unwind_opcode (0x3f, 1);
19825 op = (offset - 0x104) >> 2;
19826 add_unwind_opcode (op, 1);
19828 else if (offset > 0)
19830 /* Short opcode. */
19831 op = (offset - 4) >> 2;
19832 add_unwind_opcode (op, 1);
19834 else if (offset < 0)
19837 while (offset > 0x100)
19839 add_unwind_opcode (0x7f, 1);
19842 op = ((offset - 4) >> 2) | 0x40;
19843 add_unwind_opcode (op, 1);
19847 /* Finish the list of unwind opcodes for this function. */
19849 finish_unwind_opcodes (void)
19853 if (unwind.fp_used)
19855 /* Adjust sp as necessary. */
19856 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19857 flush_pending_unwind ();
19859 /* After restoring sp from the frame pointer. */
19860 op = 0x90 | unwind.fp_reg;
19861 add_unwind_opcode (op, 1);
19864 flush_pending_unwind ();
19868 /* Start an exception table entry. If idx is nonzero this is an index table
19872 start_unwind_section (const segT text_seg, int idx)
19874 const char * text_name;
19875 const char * prefix;
19876 const char * prefix_once;
19877 const char * group_name;
19881 size_t sec_name_len;
19888 prefix = ELF_STRING_ARM_unwind;
19889 prefix_once = ELF_STRING_ARM_unwind_once;
19890 type = SHT_ARM_EXIDX;
19894 prefix = ELF_STRING_ARM_unwind_info;
19895 prefix_once = ELF_STRING_ARM_unwind_info_once;
19896 type = SHT_PROGBITS;
19899 text_name = segment_name (text_seg);
19900 if (streq (text_name, ".text"))
19903 if (strncmp (text_name, ".gnu.linkonce.t.",
19904 strlen (".gnu.linkonce.t.")) == 0)
19906 prefix = prefix_once;
19907 text_name += strlen (".gnu.linkonce.t.");
19910 prefix_len = strlen (prefix);
19911 text_len = strlen (text_name);
19912 sec_name_len = prefix_len + text_len;
19913 sec_name = (char *) xmalloc (sec_name_len + 1);
19914 memcpy (sec_name, prefix, prefix_len);
19915 memcpy (sec_name + prefix_len, text_name, text_len);
19916 sec_name[prefix_len + text_len] = '\0';
19922 /* Handle COMDAT group. */
19923 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19925 group_name = elf_group_name (text_seg);
19926 if (group_name == NULL)
19928 as_bad (_("Group section `%s' has no group signature"),
19929 segment_name (text_seg));
19930 ignore_rest_of_line ();
19933 flags |= SHF_GROUP;
19937 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19939 /* Set the section link for index tables. */
19941 elf_linked_to_section (now_seg) = text_seg;
19945 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19946 personality routine data. Returns zero, or the index table value for
19947 and inline entry. */
19950 create_unwind_entry (int have_data)
19955 /* The current word of data. */
19957 /* The number of bytes left in this word. */
19960 finish_unwind_opcodes ();
19962 /* Remember the current text section. */
19963 unwind.saved_seg = now_seg;
19964 unwind.saved_subseg = now_subseg;
19966 start_unwind_section (now_seg, 0);
19968 if (unwind.personality_routine == NULL)
19970 if (unwind.personality_index == -2)
19973 as_bad (_("handlerdata in cantunwind frame"));
19974 return 1; /* EXIDX_CANTUNWIND. */
19977 /* Use a default personality routine if none is specified. */
19978 if (unwind.personality_index == -1)
19980 if (unwind.opcode_count > 3)
19981 unwind.personality_index = 1;
19983 unwind.personality_index = 0;
19986 /* Space for the personality routine entry. */
19987 if (unwind.personality_index == 0)
19989 if (unwind.opcode_count > 3)
19990 as_bad (_("too many unwind opcodes for personality routine 0"));
19994 /* All the data is inline in the index table. */
19997 while (unwind.opcode_count > 0)
19999 unwind.opcode_count--;
20000 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20004 /* Pad with "finish" opcodes. */
20006 data = (data << 8) | 0xb0;
20013 /* We get two opcodes "free" in the first word. */
20014 size = unwind.opcode_count - 2;
20018 gas_assert (unwind.personality_index == -1);
20020 /* An extra byte is required for the opcode count. */
20021 size = unwind.opcode_count + 1;
20024 size = (size + 3) >> 2;
20026 as_bad (_("too many unwind opcodes"));
20028 frag_align (2, 0, 0);
20029 record_alignment (now_seg, 2);
20030 unwind.table_entry = expr_build_dot ();
20032 /* Allocate the table entry. */
20033 ptr = frag_more ((size << 2) + 4);
20034 /* PR 13449: Zero the table entries in case some of them are not used. */
20035 memset (ptr, 0, (size << 2) + 4);
20036 where = frag_now_fix () - ((size << 2) + 4);
20038 switch (unwind.personality_index)
20041 /* ??? Should this be a PLT generating relocation? */
20042 /* Custom personality routine. */
20043 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20044 BFD_RELOC_ARM_PREL31);
20049 /* Set the first byte to the number of additional words. */
20050 data = size > 0 ? size - 1 : 0;
20054 /* ABI defined personality routines. */
20056 /* Three opcodes bytes are packed into the first word. */
20063 /* The size and first two opcode bytes go in the first word. */
20064 data = ((0x80 + unwind.personality_index) << 8) | size;
20069 /* Should never happen. */
20073 /* Pack the opcodes into words (MSB first), reversing the list at the same
20075 while (unwind.opcode_count > 0)
20079 md_number_to_chars (ptr, data, 4);
20084 unwind.opcode_count--;
20086 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20089 /* Finish off the last word. */
20092 /* Pad with "finish" opcodes. */
20094 data = (data << 8) | 0xb0;
20096 md_number_to_chars (ptr, data, 4);
20101 /* Add an empty descriptor if there is no user-specified data. */
20102 ptr = frag_more (4);
20103 md_number_to_chars (ptr, 0, 4);
20110 /* Initialize the DWARF-2 unwind information for this procedure. */
20113 tc_arm_frame_initial_instructions (void)
20115 cfi_add_CFA_def_cfa (REG_SP, 0);
20117 #endif /* OBJ_ELF */
20119 /* Convert REGNAME to a DWARF-2 register number. */
20122 tc_arm_regname_to_dw2regnum (char *regname)
20124 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20134 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20138 exp.X_op = O_secrel;
20139 exp.X_add_symbol = symbol;
20140 exp.X_add_number = 0;
20141 emit_expr (&exp, size);
20145 /* MD interface: Symbol and relocation handling. */
20147 /* Return the address within the segment that a PC-relative fixup is
20148 relative to. For ARM, PC-relative fixups applied to instructions
20149 are generally relative to the location of the fixup plus 8 bytes.
20150 Thumb branches are offset by 4, and Thumb loads relative to PC
20151 require special handling. */
20154 md_pcrel_from_section (fixS * fixP, segT seg)
20156 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20158 /* If this is pc-relative and we are going to emit a relocation
20159 then we just want to put out any pipeline compensation that the linker
20160 will need. Otherwise we want to use the calculated base.
20161 For WinCE we skip the bias for externals as well, since this
20162 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20164 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20165 || (arm_force_relocation (fixP)
20167 && !S_IS_EXTERNAL (fixP->fx_addsy)
20173 switch (fixP->fx_r_type)
20175 /* PC relative addressing on the Thumb is slightly odd as the
20176 bottom two bits of the PC are forced to zero for the
20177 calculation. This happens *after* application of the
20178 pipeline offset. However, Thumb adrl already adjusts for
20179 this, so we need not do it again. */
20180 case BFD_RELOC_ARM_THUMB_ADD:
20183 case BFD_RELOC_ARM_THUMB_OFFSET:
20184 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20185 case BFD_RELOC_ARM_T32_ADD_PC12:
20186 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20187 return (base + 4) & ~3;
20189 /* Thumb branches are simply offset by +4. */
20190 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20191 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20192 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20193 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20194 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20197 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20199 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20200 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20201 && ARM_IS_FUNC (fixP->fx_addsy)
20202 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20203 base = fixP->fx_where + fixP->fx_frag->fr_address;
20206 /* BLX is like branches above, but forces the low two bits of PC to
20208 case BFD_RELOC_THUMB_PCREL_BLX:
20210 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20211 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20212 && THUMB_IS_FUNC (fixP->fx_addsy)
20213 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20214 base = fixP->fx_where + fixP->fx_frag->fr_address;
20215 return (base + 4) & ~3;
20217 /* ARM mode branches are offset by +8. However, the Windows CE
20218 loader expects the relocation not to take this into account. */
20219 case BFD_RELOC_ARM_PCREL_BLX:
20221 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20222 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20223 && ARM_IS_FUNC (fixP->fx_addsy)
20224 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20225 base = fixP->fx_where + fixP->fx_frag->fr_address;
20228 case BFD_RELOC_ARM_PCREL_CALL:
20230 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20231 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20232 && THUMB_IS_FUNC (fixP->fx_addsy)
20233 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20234 base = fixP->fx_where + fixP->fx_frag->fr_address;
20237 case BFD_RELOC_ARM_PCREL_BRANCH:
20238 case BFD_RELOC_ARM_PCREL_JUMP:
20239 case BFD_RELOC_ARM_PLT32:
20241 /* When handling fixups immediately, because we have already
20242 discovered the value of a symbol, or the address of the frag involved
20243 we must account for the offset by +8, as the OS loader will never see the reloc.
20244 see fixup_segment() in write.c
20245 The S_IS_EXTERNAL test handles the case of global symbols.
20246 Those need the calculated base, not just the pipe compensation the linker will need. */
20248 && fixP->fx_addsy != NULL
20249 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20250 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20258 /* ARM mode loads relative to PC are also offset by +8. Unlike
20259 branches, the Windows CE loader *does* expect the relocation
20260 to take this into account. */
20261 case BFD_RELOC_ARM_OFFSET_IMM:
20262 case BFD_RELOC_ARM_OFFSET_IMM8:
20263 case BFD_RELOC_ARM_HWLITERAL:
20264 case BFD_RELOC_ARM_LITERAL:
20265 case BFD_RELOC_ARM_CP_OFF_IMM:
20269 /* Other PC-relative relocations are un-offset. */
20275 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20276 Otherwise we have no need to default values of symbols. */
20279 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20282 if (name[0] == '_' && name[1] == 'G'
20283 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20287 if (symbol_find (name))
20288 as_bad (_("GOT already in the symbol table"));
20290 GOT_symbol = symbol_new (name, undefined_section,
20291 (valueT) 0, & zero_address_frag);
20301 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20302 computed as two separate immediate values, added together. We
20303 already know that this value cannot be computed by just one ARM
20306 static unsigned int
20307 validate_immediate_twopart (unsigned int val,
20308 unsigned int * highpart)
20313 for (i = 0; i < 32; i += 2)
20314 if (((a = rotate_left (val, i)) & 0xff) != 0)
20320 * highpart = (a >> 8) | ((i + 24) << 7);
20322 else if (a & 0xff0000)
20324 if (a & 0xff000000)
20326 * highpart = (a >> 16) | ((i + 16) << 7);
20330 gas_assert (a & 0xff000000);
20331 * highpart = (a >> 24) | ((i + 8) << 7);
20334 return (a & 0xff) | (i << 7);
20341 validate_offset_imm (unsigned int val, int hwse)
20343 if ((hwse && val > 255) || val > 4095)
20348 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20349 negative immediate constant by altering the instruction. A bit of
20354 by inverting the second operand, and
20357 by negating the second operand. */
20360 negate_data_op (unsigned long * instruction,
20361 unsigned long value)
20364 unsigned long negated, inverted;
20366 negated = encode_arm_immediate (-value);
20367 inverted = encode_arm_immediate (~value);
20369 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20372 /* First negates. */
20373 case OPCODE_SUB: /* ADD <-> SUB */
20374 new_inst = OPCODE_ADD;
20379 new_inst = OPCODE_SUB;
20383 case OPCODE_CMP: /* CMP <-> CMN */
20384 new_inst = OPCODE_CMN;
20389 new_inst = OPCODE_CMP;
20393 /* Now Inverted ops. */
20394 case OPCODE_MOV: /* MOV <-> MVN */
20395 new_inst = OPCODE_MVN;
20400 new_inst = OPCODE_MOV;
20404 case OPCODE_AND: /* AND <-> BIC */
20405 new_inst = OPCODE_BIC;
20410 new_inst = OPCODE_AND;
20414 case OPCODE_ADC: /* ADC <-> SBC */
20415 new_inst = OPCODE_SBC;
20420 new_inst = OPCODE_ADC;
20424 /* We cannot do anything. */
20429 if (value == (unsigned) FAIL)
20432 *instruction &= OPCODE_MASK;
20433 *instruction |= new_inst << DATA_OP_SHIFT;
20437 /* Like negate_data_op, but for Thumb-2. */
20439 static unsigned int
20440 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20444 unsigned int negated, inverted;
20446 negated = encode_thumb32_immediate (-value);
20447 inverted = encode_thumb32_immediate (~value);
20449 rd = (*instruction >> 8) & 0xf;
20450 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20453 /* ADD <-> SUB. Includes CMP <-> CMN. */
20454 case T2_OPCODE_SUB:
20455 new_inst = T2_OPCODE_ADD;
20459 case T2_OPCODE_ADD:
20460 new_inst = T2_OPCODE_SUB;
20464 /* ORR <-> ORN. Includes MOV <-> MVN. */
20465 case T2_OPCODE_ORR:
20466 new_inst = T2_OPCODE_ORN;
20470 case T2_OPCODE_ORN:
20471 new_inst = T2_OPCODE_ORR;
20475 /* AND <-> BIC. TST has no inverted equivalent. */
20476 case T2_OPCODE_AND:
20477 new_inst = T2_OPCODE_BIC;
20484 case T2_OPCODE_BIC:
20485 new_inst = T2_OPCODE_AND;
20490 case T2_OPCODE_ADC:
20491 new_inst = T2_OPCODE_SBC;
20495 case T2_OPCODE_SBC:
20496 new_inst = T2_OPCODE_ADC;
20500 /* We cannot do anything. */
20505 if (value == (unsigned int)FAIL)
20508 *instruction &= T2_OPCODE_MASK;
20509 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20513 /* Read a 32-bit thumb instruction from buf. */
20514 static unsigned long
20515 get_thumb32_insn (char * buf)
20517 unsigned long insn;
20518 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20519 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20525 /* We usually want to set the low bit on the address of thumb function
20526 symbols. In particular .word foo - . should have the low bit set.
20527 Generic code tries to fold the difference of two symbols to
20528 a constant. Prevent this and force a relocation when the first symbols
20529 is a thumb function. */
20532 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20534 if (op == O_subtract
20535 && l->X_op == O_symbol
20536 && r->X_op == O_symbol
20537 && THUMB_IS_FUNC (l->X_add_symbol))
20539 l->X_op = O_subtract;
20540 l->X_op_symbol = r->X_add_symbol;
20541 l->X_add_number -= r->X_add_number;
20545 /* Process as normal. */
20549 /* Encode Thumb2 unconditional branches and calls. The encoding
20550 for the 2 are identical for the immediate values. */
20553 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20555 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20558 addressT S, I1, I2, lo, hi;
20560 S = (value >> 24) & 0x01;
20561 I1 = (value >> 23) & 0x01;
20562 I2 = (value >> 22) & 0x01;
20563 hi = (value >> 12) & 0x3ff;
20564 lo = (value >> 1) & 0x7ff;
20565 newval = md_chars_to_number (buf, THUMB_SIZE);
20566 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20567 newval |= (S << 10) | hi;
20568 newval2 &= ~T2I1I2MASK;
20569 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20570 md_number_to_chars (buf, newval, THUMB_SIZE);
20571 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20575 md_apply_fix (fixS * fixP,
20579 offsetT value = * valP;
20581 unsigned int newimm;
20582 unsigned long temp;
20584 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20586 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20588 /* Note whether this will delete the relocation. */
20590 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20593 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20594 consistency with the behaviour on 32-bit hosts. Remember value
20596 value &= 0xffffffff;
20597 value ^= 0x80000000;
20598 value -= 0x80000000;
20601 fixP->fx_addnumber = value;
20603 /* Same treatment for fixP->fx_offset. */
20604 fixP->fx_offset &= 0xffffffff;
20605 fixP->fx_offset ^= 0x80000000;
20606 fixP->fx_offset -= 0x80000000;
20608 switch (fixP->fx_r_type)
20610 case BFD_RELOC_NONE:
20611 /* This will need to go in the object file. */
20615 case BFD_RELOC_ARM_IMMEDIATE:
20616 /* We claim that this fixup has been processed here,
20617 even if in fact we generate an error because we do
20618 not have a reloc for it, so tc_gen_reloc will reject it. */
20621 if (fixP->fx_addsy)
20623 const char *msg = 0;
20625 if (! S_IS_DEFINED (fixP->fx_addsy))
20626 msg = _("undefined symbol %s used as an immediate value");
20627 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20628 msg = _("symbol %s is in a different section");
20629 else if (S_IS_WEAK (fixP->fx_addsy))
20630 msg = _("symbol %s is weak and may be overridden later");
20634 as_bad_where (fixP->fx_file, fixP->fx_line,
20635 msg, S_GET_NAME (fixP->fx_addsy));
20640 newimm = encode_arm_immediate (value);
20641 temp = md_chars_to_number (buf, INSN_SIZE);
20643 /* If the instruction will fail, see if we can fix things up by
20644 changing the opcode. */
20645 if (newimm == (unsigned int) FAIL
20646 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20648 as_bad_where (fixP->fx_file, fixP->fx_line,
20649 _("invalid constant (%lx) after fixup"),
20650 (unsigned long) value);
20654 newimm |= (temp & 0xfffff000);
20655 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20658 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20660 unsigned int highpart = 0;
20661 unsigned int newinsn = 0xe1a00000; /* nop. */
20663 if (fixP->fx_addsy)
20665 const char *msg = 0;
20667 if (! S_IS_DEFINED (fixP->fx_addsy))
20668 msg = _("undefined symbol %s used as an immediate value");
20669 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20670 msg = _("symbol %s is in a different section");
20671 else if (S_IS_WEAK (fixP->fx_addsy))
20672 msg = _("symbol %s is weak and may be overridden later");
20676 as_bad_where (fixP->fx_file, fixP->fx_line,
20677 msg, S_GET_NAME (fixP->fx_addsy));
20682 newimm = encode_arm_immediate (value);
20683 temp = md_chars_to_number (buf, INSN_SIZE);
20685 /* If the instruction will fail, see if we can fix things up by
20686 changing the opcode. */
20687 if (newimm == (unsigned int) FAIL
20688 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20690 /* No ? OK - try using two ADD instructions to generate
20692 newimm = validate_immediate_twopart (value, & highpart);
20694 /* Yes - then make sure that the second instruction is
20696 if (newimm != (unsigned int) FAIL)
20698 /* Still No ? Try using a negated value. */
20699 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20700 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20701 /* Otherwise - give up. */
20704 as_bad_where (fixP->fx_file, fixP->fx_line,
20705 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20710 /* Replace the first operand in the 2nd instruction (which
20711 is the PC) with the destination register. We have
20712 already added in the PC in the first instruction and we
20713 do not want to do it again. */
20714 newinsn &= ~ 0xf0000;
20715 newinsn |= ((newinsn & 0x0f000) << 4);
20718 newimm |= (temp & 0xfffff000);
20719 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20721 highpart |= (newinsn & 0xfffff000);
20722 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20726 case BFD_RELOC_ARM_OFFSET_IMM:
20727 if (!fixP->fx_done && seg->use_rela_p)
20730 case BFD_RELOC_ARM_LITERAL:
20736 if (validate_offset_imm (value, 0) == FAIL)
20738 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20739 as_bad_where (fixP->fx_file, fixP->fx_line,
20740 _("invalid literal constant: pool needs to be closer"));
20742 as_bad_where (fixP->fx_file, fixP->fx_line,
20743 _("bad immediate value for offset (%ld)"),
20748 newval = md_chars_to_number (buf, INSN_SIZE);
20750 newval &= 0xfffff000;
20753 newval &= 0xff7ff000;
20754 newval |= value | (sign ? INDEX_UP : 0);
20756 md_number_to_chars (buf, newval, INSN_SIZE);
20759 case BFD_RELOC_ARM_OFFSET_IMM8:
20760 case BFD_RELOC_ARM_HWLITERAL:
20766 if (validate_offset_imm (value, 1) == FAIL)
20768 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20769 as_bad_where (fixP->fx_file, fixP->fx_line,
20770 _("invalid literal constant: pool needs to be closer"));
20772 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20777 newval = md_chars_to_number (buf, INSN_SIZE);
20779 newval &= 0xfffff0f0;
20782 newval &= 0xff7ff0f0;
20783 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20785 md_number_to_chars (buf, newval, INSN_SIZE);
20788 case BFD_RELOC_ARM_T32_OFFSET_U8:
20789 if (value < 0 || value > 1020 || value % 4 != 0)
20790 as_bad_where (fixP->fx_file, fixP->fx_line,
20791 _("bad immediate value for offset (%ld)"), (long) value);
20794 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20796 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20799 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20800 /* This is a complicated relocation used for all varieties of Thumb32
20801 load/store instruction with immediate offset:
20803 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20804 *4, optional writeback(W)
20805 (doubleword load/store)
20807 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20808 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20809 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20810 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20811 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20813 Uppercase letters indicate bits that are already encoded at
20814 this point. Lowercase letters are our problem. For the
20815 second block of instructions, the secondary opcode nybble
20816 (bits 8..11) is present, and bit 23 is zero, even if this is
20817 a PC-relative operation. */
20818 newval = md_chars_to_number (buf, THUMB_SIZE);
20820 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20822 if ((newval & 0xf0000000) == 0xe0000000)
20824 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20826 newval |= (1 << 23);
20829 if (value % 4 != 0)
20831 as_bad_where (fixP->fx_file, fixP->fx_line,
20832 _("offset not a multiple of 4"));
20838 as_bad_where (fixP->fx_file, fixP->fx_line,
20839 _("offset out of range"));
20844 else if ((newval & 0x000f0000) == 0x000f0000)
20846 /* PC-relative, 12-bit offset. */
20848 newval |= (1 << 23);
20853 as_bad_where (fixP->fx_file, fixP->fx_line,
20854 _("offset out of range"));
20859 else if ((newval & 0x00000100) == 0x00000100)
20861 /* Writeback: 8-bit, +/- offset. */
20863 newval |= (1 << 9);
20868 as_bad_where (fixP->fx_file, fixP->fx_line,
20869 _("offset out of range"));
20874 else if ((newval & 0x00000f00) == 0x00000e00)
20876 /* T-instruction: positive 8-bit offset. */
20877 if (value < 0 || value > 0xff)
20879 as_bad_where (fixP->fx_file, fixP->fx_line,
20880 _("offset out of range"));
20888 /* Positive 12-bit or negative 8-bit offset. */
20892 newval |= (1 << 23);
20902 as_bad_where (fixP->fx_file, fixP->fx_line,
20903 _("offset out of range"));
20910 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20911 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20914 case BFD_RELOC_ARM_SHIFT_IMM:
20915 newval = md_chars_to_number (buf, INSN_SIZE);
20916 if (((unsigned long) value) > 32
20918 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20920 as_bad_where (fixP->fx_file, fixP->fx_line,
20921 _("shift expression is too large"));
20926 /* Shifts of zero must be done as lsl. */
20928 else if (value == 32)
20930 newval &= 0xfffff07f;
20931 newval |= (value & 0x1f) << 7;
20932 md_number_to_chars (buf, newval, INSN_SIZE);
20935 case BFD_RELOC_ARM_T32_IMMEDIATE:
20936 case BFD_RELOC_ARM_T32_ADD_IMM:
20937 case BFD_RELOC_ARM_T32_IMM12:
20938 case BFD_RELOC_ARM_T32_ADD_PC12:
20939 /* We claim that this fixup has been processed here,
20940 even if in fact we generate an error because we do
20941 not have a reloc for it, so tc_gen_reloc will reject it. */
20945 && ! S_IS_DEFINED (fixP->fx_addsy))
20947 as_bad_where (fixP->fx_file, fixP->fx_line,
20948 _("undefined symbol %s used as an immediate value"),
20949 S_GET_NAME (fixP->fx_addsy));
20953 newval = md_chars_to_number (buf, THUMB_SIZE);
20955 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20958 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20959 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20961 newimm = encode_thumb32_immediate (value);
20962 if (newimm == (unsigned int) FAIL)
20963 newimm = thumb32_negate_data_op (&newval, value);
20965 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20966 && newimm == (unsigned int) FAIL)
20968 /* Turn add/sum into addw/subw. */
20969 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20970 newval = (newval & 0xfeffffff) | 0x02000000;
20971 /* No flat 12-bit imm encoding for addsw/subsw. */
20972 if ((newval & 0x00100000) == 0)
20974 /* 12 bit immediate for addw/subw. */
20978 newval ^= 0x00a00000;
20981 newimm = (unsigned int) FAIL;
20987 if (newimm == (unsigned int)FAIL)
20989 as_bad_where (fixP->fx_file, fixP->fx_line,
20990 _("invalid constant (%lx) after fixup"),
20991 (unsigned long) value);
20995 newval |= (newimm & 0x800) << 15;
20996 newval |= (newimm & 0x700) << 4;
20997 newval |= (newimm & 0x0ff);
20999 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21000 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21003 case BFD_RELOC_ARM_SMC:
21004 if (((unsigned long) value) > 0xffff)
21005 as_bad_where (fixP->fx_file, fixP->fx_line,
21006 _("invalid smc expression"));
21007 newval = md_chars_to_number (buf, INSN_SIZE);
21008 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21009 md_number_to_chars (buf, newval, INSN_SIZE);
21012 case BFD_RELOC_ARM_HVC:
21013 if (((unsigned long) value) > 0xffff)
21014 as_bad_where (fixP->fx_file, fixP->fx_line,
21015 _("invalid hvc expression"));
21016 newval = md_chars_to_number (buf, INSN_SIZE);
21017 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21018 md_number_to_chars (buf, newval, INSN_SIZE);
21021 case BFD_RELOC_ARM_SWI:
21022 if (fixP->tc_fix_data != 0)
21024 if (((unsigned long) value) > 0xff)
21025 as_bad_where (fixP->fx_file, fixP->fx_line,
21026 _("invalid swi expression"));
21027 newval = md_chars_to_number (buf, THUMB_SIZE);
21029 md_number_to_chars (buf, newval, THUMB_SIZE);
21033 if (((unsigned long) value) > 0x00ffffff)
21034 as_bad_where (fixP->fx_file, fixP->fx_line,
21035 _("invalid swi expression"));
21036 newval = md_chars_to_number (buf, INSN_SIZE);
21038 md_number_to_chars (buf, newval, INSN_SIZE);
21042 case BFD_RELOC_ARM_MULTI:
21043 if (((unsigned long) value) > 0xffff)
21044 as_bad_where (fixP->fx_file, fixP->fx_line,
21045 _("invalid expression in load/store multiple"));
21046 newval = value | md_chars_to_number (buf, INSN_SIZE);
21047 md_number_to_chars (buf, newval, INSN_SIZE);
21051 case BFD_RELOC_ARM_PCREL_CALL:
21053 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21055 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21056 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21057 && THUMB_IS_FUNC (fixP->fx_addsy))
21058 /* Flip the bl to blx. This is a simple flip
21059 bit here because we generate PCREL_CALL for
21060 unconditional bls. */
21062 newval = md_chars_to_number (buf, INSN_SIZE);
21063 newval = newval | 0x10000000;
21064 md_number_to_chars (buf, newval, INSN_SIZE);
21070 goto arm_branch_common;
21072 case BFD_RELOC_ARM_PCREL_JUMP:
21073 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21075 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21076 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21077 && THUMB_IS_FUNC (fixP->fx_addsy))
21079 /* This would map to a bl<cond>, b<cond>,
21080 b<always> to a Thumb function. We
21081 need to force a relocation for this particular
21083 newval = md_chars_to_number (buf, INSN_SIZE);
21087 case BFD_RELOC_ARM_PLT32:
21089 case BFD_RELOC_ARM_PCREL_BRANCH:
21091 goto arm_branch_common;
21093 case BFD_RELOC_ARM_PCREL_BLX:
21096 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21098 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21099 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21100 && ARM_IS_FUNC (fixP->fx_addsy))
21102 /* Flip the blx to a bl and warn. */
21103 const char *name = S_GET_NAME (fixP->fx_addsy);
21104 newval = 0xeb000000;
21105 as_warn_where (fixP->fx_file, fixP->fx_line,
21106 _("blx to '%s' an ARM ISA state function changed to bl"),
21108 md_number_to_chars (buf, newval, INSN_SIZE);
21114 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21115 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21119 /* We are going to store value (shifted right by two) in the
21120 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21121 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21122 also be be clear. */
21124 as_bad_where (fixP->fx_file, fixP->fx_line,
21125 _("misaligned branch destination"));
21126 if ((value & (offsetT)0xfe000000) != (offsetT)0
21127 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21128 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21130 if (fixP->fx_done || !seg->use_rela_p)
21132 newval = md_chars_to_number (buf, INSN_SIZE);
21133 newval |= (value >> 2) & 0x00ffffff;
21134 /* Set the H bit on BLX instructions. */
21138 newval |= 0x01000000;
21140 newval &= ~0x01000000;
21142 md_number_to_chars (buf, newval, INSN_SIZE);
21146 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21147 /* CBZ can only branch forward. */
21149 /* Attempts to use CBZ to branch to the next instruction
21150 (which, strictly speaking, are prohibited) will be turned into
21153 FIXME: It may be better to remove the instruction completely and
21154 perform relaxation. */
21157 newval = md_chars_to_number (buf, THUMB_SIZE);
21158 newval = 0xbf00; /* NOP encoding T1 */
21159 md_number_to_chars (buf, newval, THUMB_SIZE);
21164 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21166 if (fixP->fx_done || !seg->use_rela_p)
21168 newval = md_chars_to_number (buf, THUMB_SIZE);
21169 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21170 md_number_to_chars (buf, newval, THUMB_SIZE);
21175 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21176 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21177 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21179 if (fixP->fx_done || !seg->use_rela_p)
21181 newval = md_chars_to_number (buf, THUMB_SIZE);
21182 newval |= (value & 0x1ff) >> 1;
21183 md_number_to_chars (buf, newval, THUMB_SIZE);
21187 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21188 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21189 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21191 if (fixP->fx_done || !seg->use_rela_p)
21193 newval = md_chars_to_number (buf, THUMB_SIZE);
21194 newval |= (value & 0xfff) >> 1;
21195 md_number_to_chars (buf, newval, THUMB_SIZE);
21199 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21201 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21202 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21203 && ARM_IS_FUNC (fixP->fx_addsy)
21204 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21206 /* Force a relocation for a branch 20 bits wide. */
21209 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21210 as_bad_where (fixP->fx_file, fixP->fx_line,
21211 _("conditional branch out of range"));
21213 if (fixP->fx_done || !seg->use_rela_p)
21216 addressT S, J1, J2, lo, hi;
21218 S = (value & 0x00100000) >> 20;
21219 J2 = (value & 0x00080000) >> 19;
21220 J1 = (value & 0x00040000) >> 18;
21221 hi = (value & 0x0003f000) >> 12;
21222 lo = (value & 0x00000ffe) >> 1;
21224 newval = md_chars_to_number (buf, THUMB_SIZE);
21225 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21226 newval |= (S << 10) | hi;
21227 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21228 md_number_to_chars (buf, newval, THUMB_SIZE);
21229 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21233 case BFD_RELOC_THUMB_PCREL_BLX:
21234 /* If there is a blx from a thumb state function to
21235 another thumb function flip this to a bl and warn
21239 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21240 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21241 && THUMB_IS_FUNC (fixP->fx_addsy))
21243 const char *name = S_GET_NAME (fixP->fx_addsy);
21244 as_warn_where (fixP->fx_file, fixP->fx_line,
21245 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21247 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21248 newval = newval | 0x1000;
21249 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21250 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21255 goto thumb_bl_common;
21257 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21258 /* A bl from Thumb state ISA to an internal ARM state function
21259 is converted to a blx. */
21261 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21262 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21263 && ARM_IS_FUNC (fixP->fx_addsy)
21264 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21266 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21267 newval = newval & ~0x1000;
21268 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21269 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21276 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
21277 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21278 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21281 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21282 /* For a BLX instruction, make sure that the relocation is rounded up
21283 to a word boundary. This follows the semantics of the instruction
21284 which specifies that bit 1 of the target address will come from bit
21285 1 of the base address. */
21286 value = (value + 1) & ~ 1;
21288 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21290 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21291 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21292 else if ((value & ~0x1ffffff)
21293 && ((value & ~0x1ffffff) != ~0x1ffffff))
21294 as_bad_where (fixP->fx_file, fixP->fx_line,
21295 _("Thumb2 branch out of range"));
21298 if (fixP->fx_done || !seg->use_rela_p)
21299 encode_thumb2_b_bl_offset (buf, value);
21303 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21304 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21305 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21307 if (fixP->fx_done || !seg->use_rela_p)
21308 encode_thumb2_b_bl_offset (buf, value);
21313 if (fixP->fx_done || !seg->use_rela_p)
21314 md_number_to_chars (buf, value, 1);
21318 if (fixP->fx_done || !seg->use_rela_p)
21319 md_number_to_chars (buf, value, 2);
21323 case BFD_RELOC_ARM_TLS_CALL:
21324 case BFD_RELOC_ARM_THM_TLS_CALL:
21325 case BFD_RELOC_ARM_TLS_DESCSEQ:
21326 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21327 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21330 case BFD_RELOC_ARM_TLS_GOTDESC:
21331 case BFD_RELOC_ARM_TLS_GD32:
21332 case BFD_RELOC_ARM_TLS_LE32:
21333 case BFD_RELOC_ARM_TLS_IE32:
21334 case BFD_RELOC_ARM_TLS_LDM32:
21335 case BFD_RELOC_ARM_TLS_LDO32:
21336 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21339 case BFD_RELOC_ARM_GOT32:
21340 case BFD_RELOC_ARM_GOTOFF:
21341 if (fixP->fx_done || !seg->use_rela_p)
21342 md_number_to_chars (buf, 0, 4);
21345 case BFD_RELOC_ARM_GOT_PREL:
21346 if (fixP->fx_done || !seg->use_rela_p)
21347 md_number_to_chars (buf, value, 4);
21350 case BFD_RELOC_ARM_TARGET2:
21351 /* TARGET2 is not partial-inplace, so we need to write the
21352 addend here for REL targets, because it won't be written out
21353 during reloc processing later. */
21354 if (fixP->fx_done || !seg->use_rela_p)
21355 md_number_to_chars (buf, fixP->fx_offset, 4);
21359 case BFD_RELOC_RVA:
21361 case BFD_RELOC_ARM_TARGET1:
21362 case BFD_RELOC_ARM_ROSEGREL32:
21363 case BFD_RELOC_ARM_SBREL32:
21364 case BFD_RELOC_32_PCREL:
21366 case BFD_RELOC_32_SECREL:
21368 if (fixP->fx_done || !seg->use_rela_p)
21370 /* For WinCE we only do this for pcrel fixups. */
21371 if (fixP->fx_done || fixP->fx_pcrel)
21373 md_number_to_chars (buf, value, 4);
21377 case BFD_RELOC_ARM_PREL31:
21378 if (fixP->fx_done || !seg->use_rela_p)
21380 newval = md_chars_to_number (buf, 4) & 0x80000000;
21381 if ((value ^ (value >> 1)) & 0x40000000)
21383 as_bad_where (fixP->fx_file, fixP->fx_line,
21384 _("rel31 relocation overflow"));
21386 newval |= value & 0x7fffffff;
21387 md_number_to_chars (buf, newval, 4);
21392 case BFD_RELOC_ARM_CP_OFF_IMM:
21393 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21394 if (value < -1023 || value > 1023 || (value & 3))
21395 as_bad_where (fixP->fx_file, fixP->fx_line,
21396 _("co-processor offset out of range"));
21401 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21402 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21403 newval = md_chars_to_number (buf, INSN_SIZE);
21405 newval = get_thumb32_insn (buf);
21407 newval &= 0xffffff00;
21410 newval &= 0xff7fff00;
21411 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21413 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21414 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21415 md_number_to_chars (buf, newval, INSN_SIZE);
21417 put_thumb32_insn (buf, newval);
21420 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21421 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21422 if (value < -255 || value > 255)
21423 as_bad_where (fixP->fx_file, fixP->fx_line,
21424 _("co-processor offset out of range"));
21426 goto cp_off_common;
21428 case BFD_RELOC_ARM_THUMB_OFFSET:
21429 newval = md_chars_to_number (buf, THUMB_SIZE);
21430 /* Exactly what ranges, and where the offset is inserted depends
21431 on the type of instruction, we can establish this from the
21433 switch (newval >> 12)
21435 case 4: /* PC load. */
21436 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21437 forced to zero for these loads; md_pcrel_from has already
21438 compensated for this. */
21440 as_bad_where (fixP->fx_file, fixP->fx_line,
21441 _("invalid offset, target not word aligned (0x%08lX)"),
21442 (((unsigned long) fixP->fx_frag->fr_address
21443 + (unsigned long) fixP->fx_where) & ~3)
21444 + (unsigned long) value);
21446 if (value & ~0x3fc)
21447 as_bad_where (fixP->fx_file, fixP->fx_line,
21448 _("invalid offset, value too big (0x%08lX)"),
21451 newval |= value >> 2;
21454 case 9: /* SP load/store. */
21455 if (value & ~0x3fc)
21456 as_bad_where (fixP->fx_file, fixP->fx_line,
21457 _("invalid offset, value too big (0x%08lX)"),
21459 newval |= value >> 2;
21462 case 6: /* Word load/store. */
21464 as_bad_where (fixP->fx_file, fixP->fx_line,
21465 _("invalid offset, value too big (0x%08lX)"),
21467 newval |= value << 4; /* 6 - 2. */
21470 case 7: /* Byte load/store. */
21472 as_bad_where (fixP->fx_file, fixP->fx_line,
21473 _("invalid offset, value too big (0x%08lX)"),
21475 newval |= value << 6;
21478 case 8: /* Halfword load/store. */
21480 as_bad_where (fixP->fx_file, fixP->fx_line,
21481 _("invalid offset, value too big (0x%08lX)"),
21483 newval |= value << 5; /* 6 - 1. */
21487 as_bad_where (fixP->fx_file, fixP->fx_line,
21488 "Unable to process relocation for thumb opcode: %lx",
21489 (unsigned long) newval);
21492 md_number_to_chars (buf, newval, THUMB_SIZE);
21495 case BFD_RELOC_ARM_THUMB_ADD:
21496 /* This is a complicated relocation, since we use it for all of
21497 the following immediate relocations:
21501 9bit ADD/SUB SP word-aligned
21502 10bit ADD PC/SP word-aligned
21504 The type of instruction being processed is encoded in the
21511 newval = md_chars_to_number (buf, THUMB_SIZE);
21513 int rd = (newval >> 4) & 0xf;
21514 int rs = newval & 0xf;
21515 int subtract = !!(newval & 0x8000);
21517 /* Check for HI regs, only very restricted cases allowed:
21518 Adjusting SP, and using PC or SP to get an address. */
21519 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21520 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21521 as_bad_where (fixP->fx_file, fixP->fx_line,
21522 _("invalid Hi register with immediate"));
21524 /* If value is negative, choose the opposite instruction. */
21528 subtract = !subtract;
21530 as_bad_where (fixP->fx_file, fixP->fx_line,
21531 _("immediate value out of range"));
21536 if (value & ~0x1fc)
21537 as_bad_where (fixP->fx_file, fixP->fx_line,
21538 _("invalid immediate for stack address calculation"));
21539 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21540 newval |= value >> 2;
21542 else if (rs == REG_PC || rs == REG_SP)
21544 if (subtract || value & ~0x3fc)
21545 as_bad_where (fixP->fx_file, fixP->fx_line,
21546 _("invalid immediate for address calculation (value = 0x%08lX)"),
21547 (unsigned long) value);
21548 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21550 newval |= value >> 2;
21555 as_bad_where (fixP->fx_file, fixP->fx_line,
21556 _("immediate value out of range"));
21557 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21558 newval |= (rd << 8) | value;
21563 as_bad_where (fixP->fx_file, fixP->fx_line,
21564 _("immediate value out of range"));
21565 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21566 newval |= rd | (rs << 3) | (value << 6);
21569 md_number_to_chars (buf, newval, THUMB_SIZE);
21572 case BFD_RELOC_ARM_THUMB_IMM:
21573 newval = md_chars_to_number (buf, THUMB_SIZE);
21574 if (value < 0 || value > 255)
21575 as_bad_where (fixP->fx_file, fixP->fx_line,
21576 _("invalid immediate: %ld is out of range"),
21579 md_number_to_chars (buf, newval, THUMB_SIZE);
21582 case BFD_RELOC_ARM_THUMB_SHIFT:
21583 /* 5bit shift value (0..32). LSL cannot take 32. */
21584 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21585 temp = newval & 0xf800;
21586 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21587 as_bad_where (fixP->fx_file, fixP->fx_line,
21588 _("invalid shift value: %ld"), (long) value);
21589 /* Shifts of zero must be encoded as LSL. */
21591 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21592 /* Shifts of 32 are encoded as zero. */
21593 else if (value == 32)
21595 newval |= value << 6;
21596 md_number_to_chars (buf, newval, THUMB_SIZE);
21599 case BFD_RELOC_VTABLE_INHERIT:
21600 case BFD_RELOC_VTABLE_ENTRY:
21604 case BFD_RELOC_ARM_MOVW:
21605 case BFD_RELOC_ARM_MOVT:
21606 case BFD_RELOC_ARM_THUMB_MOVW:
21607 case BFD_RELOC_ARM_THUMB_MOVT:
21608 if (fixP->fx_done || !seg->use_rela_p)
21610 /* REL format relocations are limited to a 16-bit addend. */
21611 if (!fixP->fx_done)
21613 if (value < -0x8000 || value > 0x7fff)
21614 as_bad_where (fixP->fx_file, fixP->fx_line,
21615 _("offset out of range"));
21617 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21618 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21623 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21624 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21626 newval = get_thumb32_insn (buf);
21627 newval &= 0xfbf08f00;
21628 newval |= (value & 0xf000) << 4;
21629 newval |= (value & 0x0800) << 15;
21630 newval |= (value & 0x0700) << 4;
21631 newval |= (value & 0x00ff);
21632 put_thumb32_insn (buf, newval);
21636 newval = md_chars_to_number (buf, 4);
21637 newval &= 0xfff0f000;
21638 newval |= value & 0x0fff;
21639 newval |= (value & 0xf000) << 4;
21640 md_number_to_chars (buf, newval, 4);
21645 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21646 case BFD_RELOC_ARM_ALU_PC_G0:
21647 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21648 case BFD_RELOC_ARM_ALU_PC_G1:
21649 case BFD_RELOC_ARM_ALU_PC_G2:
21650 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21651 case BFD_RELOC_ARM_ALU_SB_G0:
21652 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21653 case BFD_RELOC_ARM_ALU_SB_G1:
21654 case BFD_RELOC_ARM_ALU_SB_G2:
21655 gas_assert (!fixP->fx_done);
21656 if (!seg->use_rela_p)
21659 bfd_vma encoded_addend;
21660 bfd_vma addend_abs = abs (value);
21662 /* Check that the absolute value of the addend can be
21663 expressed as an 8-bit constant plus a rotation. */
21664 encoded_addend = encode_arm_immediate (addend_abs);
21665 if (encoded_addend == (unsigned int) FAIL)
21666 as_bad_where (fixP->fx_file, fixP->fx_line,
21667 _("the offset 0x%08lX is not representable"),
21668 (unsigned long) addend_abs);
21670 /* Extract the instruction. */
21671 insn = md_chars_to_number (buf, INSN_SIZE);
21673 /* If the addend is positive, use an ADD instruction.
21674 Otherwise use a SUB. Take care not to destroy the S bit. */
21675 insn &= 0xff1fffff;
21681 /* Place the encoded addend into the first 12 bits of the
21683 insn &= 0xfffff000;
21684 insn |= encoded_addend;
21686 /* Update the instruction. */
21687 md_number_to_chars (buf, insn, INSN_SIZE);
21691 case BFD_RELOC_ARM_LDR_PC_G0:
21692 case BFD_RELOC_ARM_LDR_PC_G1:
21693 case BFD_RELOC_ARM_LDR_PC_G2:
21694 case BFD_RELOC_ARM_LDR_SB_G0:
21695 case BFD_RELOC_ARM_LDR_SB_G1:
21696 case BFD_RELOC_ARM_LDR_SB_G2:
21697 gas_assert (!fixP->fx_done);
21698 if (!seg->use_rela_p)
21701 bfd_vma addend_abs = abs (value);
21703 /* Check that the absolute value of the addend can be
21704 encoded in 12 bits. */
21705 if (addend_abs >= 0x1000)
21706 as_bad_where (fixP->fx_file, fixP->fx_line,
21707 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21708 (unsigned long) addend_abs);
21710 /* Extract the instruction. */
21711 insn = md_chars_to_number (buf, INSN_SIZE);
21713 /* If the addend is negative, clear bit 23 of the instruction.
21714 Otherwise set it. */
21716 insn &= ~(1 << 23);
21720 /* Place the absolute value of the addend into the first 12 bits
21721 of the instruction. */
21722 insn &= 0xfffff000;
21723 insn |= addend_abs;
21725 /* Update the instruction. */
21726 md_number_to_chars (buf, insn, INSN_SIZE);
21730 case BFD_RELOC_ARM_LDRS_PC_G0:
21731 case BFD_RELOC_ARM_LDRS_PC_G1:
21732 case BFD_RELOC_ARM_LDRS_PC_G2:
21733 case BFD_RELOC_ARM_LDRS_SB_G0:
21734 case BFD_RELOC_ARM_LDRS_SB_G1:
21735 case BFD_RELOC_ARM_LDRS_SB_G2:
21736 gas_assert (!fixP->fx_done);
21737 if (!seg->use_rela_p)
21740 bfd_vma addend_abs = abs (value);
21742 /* Check that the absolute value of the addend can be
21743 encoded in 8 bits. */
21744 if (addend_abs >= 0x100)
21745 as_bad_where (fixP->fx_file, fixP->fx_line,
21746 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21747 (unsigned long) addend_abs);
21749 /* Extract the instruction. */
21750 insn = md_chars_to_number (buf, INSN_SIZE);
21752 /* If the addend is negative, clear bit 23 of the instruction.
21753 Otherwise set it. */
21755 insn &= ~(1 << 23);
21759 /* Place the first four bits of the absolute value of the addend
21760 into the first 4 bits of the instruction, and the remaining
21761 four into bits 8 .. 11. */
21762 insn &= 0xfffff0f0;
21763 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21765 /* Update the instruction. */
21766 md_number_to_chars (buf, insn, INSN_SIZE);
21770 case BFD_RELOC_ARM_LDC_PC_G0:
21771 case BFD_RELOC_ARM_LDC_PC_G1:
21772 case BFD_RELOC_ARM_LDC_PC_G2:
21773 case BFD_RELOC_ARM_LDC_SB_G0:
21774 case BFD_RELOC_ARM_LDC_SB_G1:
21775 case BFD_RELOC_ARM_LDC_SB_G2:
21776 gas_assert (!fixP->fx_done);
21777 if (!seg->use_rela_p)
21780 bfd_vma addend_abs = abs (value);
21782 /* Check that the absolute value of the addend is a multiple of
21783 four and, when divided by four, fits in 8 bits. */
21784 if (addend_abs & 0x3)
21785 as_bad_where (fixP->fx_file, fixP->fx_line,
21786 _("bad offset 0x%08lX (must be word-aligned)"),
21787 (unsigned long) addend_abs);
21789 if ((addend_abs >> 2) > 0xff)
21790 as_bad_where (fixP->fx_file, fixP->fx_line,
21791 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21792 (unsigned long) addend_abs);
21794 /* Extract the instruction. */
21795 insn = md_chars_to_number (buf, INSN_SIZE);
21797 /* If the addend is negative, clear bit 23 of the instruction.
21798 Otherwise set it. */
21800 insn &= ~(1 << 23);
21804 /* Place the addend (divided by four) into the first eight
21805 bits of the instruction. */
21806 insn &= 0xfffffff0;
21807 insn |= addend_abs >> 2;
21809 /* Update the instruction. */
21810 md_number_to_chars (buf, insn, INSN_SIZE);
21814 case BFD_RELOC_ARM_V4BX:
21815 /* This will need to go in the object file. */
21819 case BFD_RELOC_UNUSED:
21821 as_bad_where (fixP->fx_file, fixP->fx_line,
21822 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21826 /* Translate internal representation of relocation info to BFD target
21830 tc_gen_reloc (asection *section, fixS *fixp)
21833 bfd_reloc_code_real_type code;
21835 reloc = (arelent *) xmalloc (sizeof (arelent));
21837 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21838 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21839 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21841 if (fixp->fx_pcrel)
21843 if (section->use_rela_p)
21844 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21846 fixp->fx_offset = reloc->address;
21848 reloc->addend = fixp->fx_offset;
21850 switch (fixp->fx_r_type)
21853 if (fixp->fx_pcrel)
21855 code = BFD_RELOC_8_PCREL;
21860 if (fixp->fx_pcrel)
21862 code = BFD_RELOC_16_PCREL;
21867 if (fixp->fx_pcrel)
21869 code = BFD_RELOC_32_PCREL;
21873 case BFD_RELOC_ARM_MOVW:
21874 if (fixp->fx_pcrel)
21876 code = BFD_RELOC_ARM_MOVW_PCREL;
21880 case BFD_RELOC_ARM_MOVT:
21881 if (fixp->fx_pcrel)
21883 code = BFD_RELOC_ARM_MOVT_PCREL;
21887 case BFD_RELOC_ARM_THUMB_MOVW:
21888 if (fixp->fx_pcrel)
21890 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21894 case BFD_RELOC_ARM_THUMB_MOVT:
21895 if (fixp->fx_pcrel)
21897 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21901 case BFD_RELOC_NONE:
21902 case BFD_RELOC_ARM_PCREL_BRANCH:
21903 case BFD_RELOC_ARM_PCREL_BLX:
21904 case BFD_RELOC_RVA:
21905 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21906 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21907 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21908 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21909 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21910 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21911 case BFD_RELOC_VTABLE_ENTRY:
21912 case BFD_RELOC_VTABLE_INHERIT:
21914 case BFD_RELOC_32_SECREL:
21916 code = fixp->fx_r_type;
21919 case BFD_RELOC_THUMB_PCREL_BLX:
21921 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21922 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21925 code = BFD_RELOC_THUMB_PCREL_BLX;
21928 case BFD_RELOC_ARM_LITERAL:
21929 case BFD_RELOC_ARM_HWLITERAL:
21930 /* If this is called then the a literal has
21931 been referenced across a section boundary. */
21932 as_bad_where (fixp->fx_file, fixp->fx_line,
21933 _("literal referenced across section boundary"));
21937 case BFD_RELOC_ARM_TLS_CALL:
21938 case BFD_RELOC_ARM_THM_TLS_CALL:
21939 case BFD_RELOC_ARM_TLS_DESCSEQ:
21940 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21941 case BFD_RELOC_ARM_GOT32:
21942 case BFD_RELOC_ARM_GOTOFF:
21943 case BFD_RELOC_ARM_GOT_PREL:
21944 case BFD_RELOC_ARM_PLT32:
21945 case BFD_RELOC_ARM_TARGET1:
21946 case BFD_RELOC_ARM_ROSEGREL32:
21947 case BFD_RELOC_ARM_SBREL32:
21948 case BFD_RELOC_ARM_PREL31:
21949 case BFD_RELOC_ARM_TARGET2:
21950 case BFD_RELOC_ARM_TLS_LE32:
21951 case BFD_RELOC_ARM_TLS_LDO32:
21952 case BFD_RELOC_ARM_PCREL_CALL:
21953 case BFD_RELOC_ARM_PCREL_JUMP:
21954 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21955 case BFD_RELOC_ARM_ALU_PC_G0:
21956 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21957 case BFD_RELOC_ARM_ALU_PC_G1:
21958 case BFD_RELOC_ARM_ALU_PC_G2:
21959 case BFD_RELOC_ARM_LDR_PC_G0:
21960 case BFD_RELOC_ARM_LDR_PC_G1:
21961 case BFD_RELOC_ARM_LDR_PC_G2:
21962 case BFD_RELOC_ARM_LDRS_PC_G0:
21963 case BFD_RELOC_ARM_LDRS_PC_G1:
21964 case BFD_RELOC_ARM_LDRS_PC_G2:
21965 case BFD_RELOC_ARM_LDC_PC_G0:
21966 case BFD_RELOC_ARM_LDC_PC_G1:
21967 case BFD_RELOC_ARM_LDC_PC_G2:
21968 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21969 case BFD_RELOC_ARM_ALU_SB_G0:
21970 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21971 case BFD_RELOC_ARM_ALU_SB_G1:
21972 case BFD_RELOC_ARM_ALU_SB_G2:
21973 case BFD_RELOC_ARM_LDR_SB_G0:
21974 case BFD_RELOC_ARM_LDR_SB_G1:
21975 case BFD_RELOC_ARM_LDR_SB_G2:
21976 case BFD_RELOC_ARM_LDRS_SB_G0:
21977 case BFD_RELOC_ARM_LDRS_SB_G1:
21978 case BFD_RELOC_ARM_LDRS_SB_G2:
21979 case BFD_RELOC_ARM_LDC_SB_G0:
21980 case BFD_RELOC_ARM_LDC_SB_G1:
21981 case BFD_RELOC_ARM_LDC_SB_G2:
21982 case BFD_RELOC_ARM_V4BX:
21983 code = fixp->fx_r_type;
21986 case BFD_RELOC_ARM_TLS_GOTDESC:
21987 case BFD_RELOC_ARM_TLS_GD32:
21988 case BFD_RELOC_ARM_TLS_IE32:
21989 case BFD_RELOC_ARM_TLS_LDM32:
21990 /* BFD will include the symbol's address in the addend.
21991 But we don't want that, so subtract it out again here. */
21992 if (!S_IS_COMMON (fixp->fx_addsy))
21993 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21994 code = fixp->fx_r_type;
21998 case BFD_RELOC_ARM_IMMEDIATE:
21999 as_bad_where (fixp->fx_file, fixp->fx_line,
22000 _("internal relocation (type: IMMEDIATE) not fixed up"));
22003 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22004 as_bad_where (fixp->fx_file, fixp->fx_line,
22005 _("ADRL used for a symbol not defined in the same file"));
22008 case BFD_RELOC_ARM_OFFSET_IMM:
22009 if (section->use_rela_p)
22011 code = fixp->fx_r_type;
22015 if (fixp->fx_addsy != NULL
22016 && !S_IS_DEFINED (fixp->fx_addsy)
22017 && S_IS_LOCAL (fixp->fx_addsy))
22019 as_bad_where (fixp->fx_file, fixp->fx_line,
22020 _("undefined local label `%s'"),
22021 S_GET_NAME (fixp->fx_addsy));
22025 as_bad_where (fixp->fx_file, fixp->fx_line,
22026 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22033 switch (fixp->fx_r_type)
22035 case BFD_RELOC_NONE: type = "NONE"; break;
22036 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22037 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22038 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22039 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22040 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22041 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22042 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22043 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22044 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22045 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22046 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22047 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22048 default: type = _("<unknown>"); break;
22050 as_bad_where (fixp->fx_file, fixp->fx_line,
22051 _("cannot represent %s relocation in this object file format"),
22058 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22060 && fixp->fx_addsy == GOT_symbol)
22062 code = BFD_RELOC_ARM_GOTPC;
22063 reloc->addend = fixp->fx_offset = reloc->address;
22067 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22069 if (reloc->howto == NULL)
22071 as_bad_where (fixp->fx_file, fixp->fx_line,
22072 _("cannot represent %s relocation in this object file format"),
22073 bfd_get_reloc_code_name (code));
22077 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22078 vtable entry to be used in the relocation's section offset. */
22079 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22080 reloc->address = fixp->fx_offset;
22085 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22088 cons_fix_new_arm (fragS * frag,
22093 bfd_reloc_code_real_type type;
22097 FIXME: @@ Should look at CPU word size. */
22101 type = BFD_RELOC_8;
22104 type = BFD_RELOC_16;
22108 type = BFD_RELOC_32;
22111 type = BFD_RELOC_64;
22116 if (exp->X_op == O_secrel)
22118 exp->X_op = O_symbol;
22119 type = BFD_RELOC_32_SECREL;
22123 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22126 #if defined (OBJ_COFF)
22128 arm_validate_fix (fixS * fixP)
22130 /* If the destination of the branch is a defined symbol which does not have
22131 the THUMB_FUNC attribute, then we must be calling a function which has
22132 the (interfacearm) attribute. We look for the Thumb entry point to that
22133 function and change the branch to refer to that function instead. */
22134 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22135 && fixP->fx_addsy != NULL
22136 && S_IS_DEFINED (fixP->fx_addsy)
22137 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22139 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22146 arm_force_relocation (struct fix * fixp)
22148 #if defined (OBJ_COFF) && defined (TE_PE)
22149 if (fixp->fx_r_type == BFD_RELOC_RVA)
22153 /* In case we have a call or a branch to a function in ARM ISA mode from
22154 a thumb function or vice-versa force the relocation. These relocations
22155 are cleared off for some cores that might have blx and simple transformations
22159 switch (fixp->fx_r_type)
22161 case BFD_RELOC_ARM_PCREL_JUMP:
22162 case BFD_RELOC_ARM_PCREL_CALL:
22163 case BFD_RELOC_THUMB_PCREL_BLX:
22164 if (THUMB_IS_FUNC (fixp->fx_addsy))
22168 case BFD_RELOC_ARM_PCREL_BLX:
22169 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22170 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22171 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22172 if (ARM_IS_FUNC (fixp->fx_addsy))
22181 /* Resolve these relocations even if the symbol is extern or weak.
22182 Technically this is probably wrong due to symbol preemption.
22183 In practice these relocations do not have enough range to be useful
22184 at dynamic link time, and some code (e.g. in the Linux kernel)
22185 expects these references to be resolved. */
22186 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22187 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22188 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22189 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22190 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22191 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22192 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22193 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22194 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22195 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22196 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22197 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22198 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22199 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22202 /* Always leave these relocations for the linker. */
22203 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22204 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22205 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22208 /* Always generate relocations against function symbols. */
22209 if (fixp->fx_r_type == BFD_RELOC_32
22211 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22214 return generic_force_reloc (fixp);
22217 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22218 /* Relocations against function names must be left unadjusted,
22219 so that the linker can use this information to generate interworking
22220 stubs. The MIPS version of this function
22221 also prevents relocations that are mips-16 specific, but I do not
22222 know why it does this.
22225 There is one other problem that ought to be addressed here, but
22226 which currently is not: Taking the address of a label (rather
22227 than a function) and then later jumping to that address. Such
22228 addresses also ought to have their bottom bit set (assuming that
22229 they reside in Thumb code), but at the moment they will not. */
22232 arm_fix_adjustable (fixS * fixP)
22234 if (fixP->fx_addsy == NULL)
22237 /* Preserve relocations against symbols with function type. */
22238 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22241 if (THUMB_IS_FUNC (fixP->fx_addsy)
22242 && fixP->fx_subsy == NULL)
22245 /* We need the symbol name for the VTABLE entries. */
22246 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22247 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22250 /* Don't allow symbols to be discarded on GOT related relocs. */
22251 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22252 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22253 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22254 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22255 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22256 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22257 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22258 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22259 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22260 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22261 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22262 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22263 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22264 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22267 /* Similarly for group relocations. */
22268 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22269 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22270 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22273 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22274 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22275 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22276 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22277 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22278 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22279 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22280 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22281 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22286 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22291 elf32_arm_target_format (void)
22294 return (target_big_endian
22295 ? "elf32-bigarm-symbian"
22296 : "elf32-littlearm-symbian");
22297 #elif defined (TE_VXWORKS)
22298 return (target_big_endian
22299 ? "elf32-bigarm-vxworks"
22300 : "elf32-littlearm-vxworks");
22301 #elif defined (TE_NACL)
22302 return (target_big_endian
22303 ? "elf32-bigarm-nacl"
22304 : "elf32-littlearm-nacl");
22306 if (target_big_endian)
22307 return "elf32-bigarm";
22309 return "elf32-littlearm";
22314 armelf_frob_symbol (symbolS * symp,
22317 elf_frob_symbol (symp, puntp);
22321 /* MD interface: Finalization. */
22326 literal_pool * pool;
22328 /* Ensure that all the IT blocks are properly closed. */
22329 check_it_blocks_finished ();
22331 for (pool = list_of_pools; pool; pool = pool->next)
22333 /* Put it at the end of the relevant section. */
22334 subseg_set (pool->section, pool->sub_section);
22336 arm_elf_change_section ();
22343 /* Remove any excess mapping symbols generated for alignment frags in
22344 SEC. We may have created a mapping symbol before a zero byte
22345 alignment; remove it if there's a mapping symbol after the
22348 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22349 void *dummy ATTRIBUTE_UNUSED)
22351 segment_info_type *seginfo = seg_info (sec);
22354 if (seginfo == NULL || seginfo->frchainP == NULL)
22357 for (fragp = seginfo->frchainP->frch_root;
22359 fragp = fragp->fr_next)
22361 symbolS *sym = fragp->tc_frag_data.last_map;
22362 fragS *next = fragp->fr_next;
22364 /* Variable-sized frags have been converted to fixed size by
22365 this point. But if this was variable-sized to start with,
22366 there will be a fixed-size frag after it. So don't handle
22368 if (sym == NULL || next == NULL)
22371 if (S_GET_VALUE (sym) < next->fr_address)
22372 /* Not at the end of this frag. */
22374 know (S_GET_VALUE (sym) == next->fr_address);
22378 if (next->tc_frag_data.first_map != NULL)
22380 /* Next frag starts with a mapping symbol. Discard this
22382 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22386 if (next->fr_next == NULL)
22388 /* This mapping symbol is at the end of the section. Discard
22390 know (next->fr_fix == 0 && next->fr_var == 0);
22391 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22395 /* As long as we have empty frags without any mapping symbols,
22397 /* If the next frag is non-empty and does not start with a
22398 mapping symbol, then this mapping symbol is required. */
22399 if (next->fr_address != next->fr_next->fr_address)
22402 next = next->fr_next;
22404 while (next != NULL);
22409 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22413 arm_adjust_symtab (void)
22418 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22420 if (ARM_IS_THUMB (sym))
22422 if (THUMB_IS_FUNC (sym))
22424 /* Mark the symbol as a Thumb function. */
22425 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22426 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22427 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22429 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22430 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22432 as_bad (_("%s: unexpected function type: %d"),
22433 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22435 else switch (S_GET_STORAGE_CLASS (sym))
22438 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22441 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22444 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22452 if (ARM_IS_INTERWORK (sym))
22453 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22460 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22462 if (ARM_IS_THUMB (sym))
22464 elf_symbol_type * elf_sym;
22466 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22467 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22469 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22470 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22472 /* If it's a .thumb_func, declare it as so,
22473 otherwise tag label as .code 16. */
22474 if (THUMB_IS_FUNC (sym))
22475 elf_sym->internal_elf_sym.st_target_internal
22476 = ST_BRANCH_TO_THUMB;
22477 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22478 elf_sym->internal_elf_sym.st_info =
22479 ELF_ST_INFO (bind, STT_ARM_16BIT);
22484 /* Remove any overlapping mapping symbols generated by alignment frags. */
22485 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22486 /* Now do generic ELF adjustments. */
22487 elf_adjust_symtab ();
22491 /* MD interface: Initialization. */
22494 set_constant_flonums (void)
22498 for (i = 0; i < NUM_FLOAT_VALS; i++)
22499 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22503 /* Auto-select Thumb mode if it's the only available instruction set for the
22504 given architecture. */
22507 autoselect_thumb_from_cpu_variant (void)
22509 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22510 opcode_select (16);
22519 if ( (arm_ops_hsh = hash_new ()) == NULL
22520 || (arm_cond_hsh = hash_new ()) == NULL
22521 || (arm_shift_hsh = hash_new ()) == NULL
22522 || (arm_psr_hsh = hash_new ()) == NULL
22523 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22524 || (arm_reg_hsh = hash_new ()) == NULL
22525 || (arm_reloc_hsh = hash_new ()) == NULL
22526 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22527 as_fatal (_("virtual memory exhausted"));
22529 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22530 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22531 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22532 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22533 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22534 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22535 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22536 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22537 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22538 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22539 (void *) (v7m_psrs + i));
22540 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22541 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22543 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22545 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22546 (void *) (barrier_opt_names + i));
22548 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22550 struct reloc_entry * entry = reloc_names + i;
22552 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22553 /* This makes encode_branch() use the EABI versions of this relocation. */
22554 entry->reloc = BFD_RELOC_UNUSED;
22556 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22560 set_constant_flonums ();
22562 /* Set the cpu variant based on the command-line options. We prefer
22563 -mcpu= over -march= if both are set (as for GCC); and we prefer
22564 -mfpu= over any other way of setting the floating point unit.
22565 Use of legacy options with new options are faulted. */
22568 if (mcpu_cpu_opt || march_cpu_opt)
22569 as_bad (_("use of old and new-style options to set CPU type"));
22571 mcpu_cpu_opt = legacy_cpu;
22573 else if (!mcpu_cpu_opt)
22574 mcpu_cpu_opt = march_cpu_opt;
22579 as_bad (_("use of old and new-style options to set FPU type"));
22581 mfpu_opt = legacy_fpu;
22583 else if (!mfpu_opt)
22585 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22586 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22587 /* Some environments specify a default FPU. If they don't, infer it
22588 from the processor. */
22590 mfpu_opt = mcpu_fpu_opt;
22592 mfpu_opt = march_fpu_opt;
22594 mfpu_opt = &fpu_default;
22600 if (mcpu_cpu_opt != NULL)
22601 mfpu_opt = &fpu_default;
22602 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22603 mfpu_opt = &fpu_arch_vfp_v2;
22605 mfpu_opt = &fpu_arch_fpa;
22611 mcpu_cpu_opt = &cpu_default;
22612 selected_cpu = cpu_default;
22616 selected_cpu = *mcpu_cpu_opt;
22618 mcpu_cpu_opt = &arm_arch_any;
22621 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22623 autoselect_thumb_from_cpu_variant ();
22625 arm_arch_used = thumb_arch_used = arm_arch_none;
22627 #if defined OBJ_COFF || defined OBJ_ELF
22629 unsigned int flags = 0;
22631 #if defined OBJ_ELF
22632 flags = meabi_flags;
22634 switch (meabi_flags)
22636 case EF_ARM_EABI_UNKNOWN:
22638 /* Set the flags in the private structure. */
22639 if (uses_apcs_26) flags |= F_APCS26;
22640 if (support_interwork) flags |= F_INTERWORK;
22641 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22642 if (pic_code) flags |= F_PIC;
22643 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22644 flags |= F_SOFT_FLOAT;
22646 switch (mfloat_abi_opt)
22648 case ARM_FLOAT_ABI_SOFT:
22649 case ARM_FLOAT_ABI_SOFTFP:
22650 flags |= F_SOFT_FLOAT;
22653 case ARM_FLOAT_ABI_HARD:
22654 if (flags & F_SOFT_FLOAT)
22655 as_bad (_("hard-float conflicts with specified fpu"));
22659 /* Using pure-endian doubles (even if soft-float). */
22660 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22661 flags |= F_VFP_FLOAT;
22663 #if defined OBJ_ELF
22664 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22665 flags |= EF_ARM_MAVERICK_FLOAT;
22668 case EF_ARM_EABI_VER4:
22669 case EF_ARM_EABI_VER5:
22670 /* No additional flags to set. */
22677 bfd_set_private_flags (stdoutput, flags);
22679 /* We have run out flags in the COFF header to encode the
22680 status of ATPCS support, so instead we create a dummy,
22681 empty, debug section called .arm.atpcs. */
22686 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22690 bfd_set_section_flags
22691 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22692 bfd_set_section_size (stdoutput, sec, 0);
22693 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22699 /* Record the CPU type as well. */
22700 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22701 mach = bfd_mach_arm_iWMMXt2;
22702 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22703 mach = bfd_mach_arm_iWMMXt;
22704 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22705 mach = bfd_mach_arm_XScale;
22706 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22707 mach = bfd_mach_arm_ep9312;
22708 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22709 mach = bfd_mach_arm_5TE;
22710 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22712 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22713 mach = bfd_mach_arm_5T;
22715 mach = bfd_mach_arm_5;
22717 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22719 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22720 mach = bfd_mach_arm_4T;
22722 mach = bfd_mach_arm_4;
22724 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22725 mach = bfd_mach_arm_3M;
22726 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22727 mach = bfd_mach_arm_3;
22728 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22729 mach = bfd_mach_arm_2a;
22730 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22731 mach = bfd_mach_arm_2;
22733 mach = bfd_mach_arm_unknown;
22735 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22738 /* Command line processing. */
22741 Invocation line includes a switch not recognized by the base assembler.
22742 See if it's a processor-specific option.
22744 This routine is somewhat complicated by the need for backwards
22745 compatibility (since older releases of gcc can't be changed).
22746 The new options try to make the interface as compatible as
22749 New options (supported) are:
22751 -mcpu=<cpu name> Assemble for selected processor
22752 -march=<architecture name> Assemble for selected architecture
22753 -mfpu=<fpu architecture> Assemble for selected FPU.
22754 -EB/-mbig-endian Big-endian
22755 -EL/-mlittle-endian Little-endian
22756 -k Generate PIC code
22757 -mthumb Start in Thumb mode
22758 -mthumb-interwork Code supports ARM/Thumb interworking
22760 -m[no-]warn-deprecated Warn about deprecated features
22762 For now we will also provide support for:
22764 -mapcs-32 32-bit Program counter
22765 -mapcs-26 26-bit Program counter
22766 -macps-float Floats passed in FP registers
22767 -mapcs-reentrant Reentrant code
22769 (sometime these will probably be replaced with -mapcs=<list of options>
22770 and -matpcs=<list of options>)
22772 The remaining options are only supported for back-wards compatibility.
22773 Cpu variants, the arm part is optional:
22774 -m[arm]1 Currently not supported.
22775 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22776 -m[arm]3 Arm 3 processor
22777 -m[arm]6[xx], Arm 6 processors
22778 -m[arm]7[xx][t][[d]m] Arm 7 processors
22779 -m[arm]8[10] Arm 8 processors
22780 -m[arm]9[20][tdmi] Arm 9 processors
22781 -mstrongarm[110[0]] StrongARM processors
22782 -mxscale XScale processors
22783 -m[arm]v[2345[t[e]]] Arm architectures
22784 -mall All (except the ARM1)
22786 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22787 -mfpe-old (No float load/store multiples)
22788 -mvfpxd VFP Single precision
22790 -mno-fpu Disable all floating point instructions
22792 The following CPU names are recognized:
22793 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22794 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22795 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22796 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22797 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22798 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22799 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22803 const char * md_shortopts = "m:k";
22805 #ifdef ARM_BI_ENDIAN
22806 #define OPTION_EB (OPTION_MD_BASE + 0)
22807 #define OPTION_EL (OPTION_MD_BASE + 1)
22809 #if TARGET_BYTES_BIG_ENDIAN
22810 #define OPTION_EB (OPTION_MD_BASE + 0)
22812 #define OPTION_EL (OPTION_MD_BASE + 1)
22815 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22817 struct option md_longopts[] =
22820 {"EB", no_argument, NULL, OPTION_EB},
22823 {"EL", no_argument, NULL, OPTION_EL},
22825 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22826 {NULL, no_argument, NULL, 0}
22829 size_t md_longopts_size = sizeof (md_longopts);
22831 struct arm_option_table
22833 char *option; /* Option name to match. */
22834 char *help; /* Help information. */
22835 int *var; /* Variable to change. */
22836 int value; /* What to change it to. */
22837 char *deprecated; /* If non-null, print this message. */
22840 struct arm_option_table arm_opts[] =
22842 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22843 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22844 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22845 &support_interwork, 1, NULL},
22846 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22847 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22848 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22850 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22851 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22852 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22853 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22856 /* These are recognized by the assembler, but have no affect on code. */
22857 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22858 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22860 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22861 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22862 &warn_on_deprecated, 0, NULL},
22863 {NULL, NULL, NULL, 0, NULL}
22866 struct arm_legacy_option_table
22868 char *option; /* Option name to match. */
22869 const arm_feature_set **var; /* Variable to change. */
22870 const arm_feature_set value; /* What to change it to. */
22871 char *deprecated; /* If non-null, print this message. */
22874 const struct arm_legacy_option_table arm_legacy_opts[] =
22876 /* DON'T add any new processors to this list -- we want the whole list
22877 to go away... Add them to the processors table instead. */
22878 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22879 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22880 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22881 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22882 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22883 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22884 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22885 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22886 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22887 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22888 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22889 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22890 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22891 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22892 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22893 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22894 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22895 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22896 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22897 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22898 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22899 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22900 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22901 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22902 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22903 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22904 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22905 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22906 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22907 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22908 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22909 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22910 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22911 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22912 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22913 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22914 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22915 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22916 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22917 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22918 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22919 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22920 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22921 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22922 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22923 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22924 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22925 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22926 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22927 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22928 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22929 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22930 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22931 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22932 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22933 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22934 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22935 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22936 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22937 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22938 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22939 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22940 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22941 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22942 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22943 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22944 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22945 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22946 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22947 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22948 N_("use -mcpu=strongarm110")},
22949 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22950 N_("use -mcpu=strongarm1100")},
22951 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22952 N_("use -mcpu=strongarm1110")},
22953 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22954 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22955 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22957 /* Architecture variants -- don't add any more to this list either. */
22958 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22959 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22960 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22961 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22962 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22963 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22964 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22965 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22966 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22967 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22968 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22969 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22970 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22971 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22972 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22973 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22974 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22975 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22977 /* Floating point variants -- don't add any more to this list either. */
22978 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22979 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22980 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22981 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22982 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22984 {NULL, NULL, ARM_ARCH_NONE, NULL}
22987 struct arm_cpu_option_table
22991 const arm_feature_set value;
22992 /* For some CPUs we assume an FPU unless the user explicitly sets
22994 const arm_feature_set default_fpu;
22995 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22997 const char *canonical_name;
23000 /* This list should, at a minimum, contain all the cpu names
23001 recognized by GCC. */
23002 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23003 static const struct arm_cpu_option_table arm_cpus[] =
23005 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23006 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23007 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23008 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23009 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23010 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23011 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23012 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23013 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23014 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23015 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23016 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23017 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23018 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23019 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23020 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23021 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23022 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23023 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23024 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23025 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23026 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23027 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23028 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23029 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23030 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23031 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23032 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23033 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23034 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23035 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23036 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23037 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23038 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23039 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23040 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23041 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23042 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23043 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23044 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23045 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23046 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23047 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23048 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23049 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23050 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23051 /* For V5 or later processors we default to using VFP; but the user
23052 should really set the FPU type explicitly. */
23053 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23054 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23055 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23056 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23057 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23058 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23059 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23060 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23061 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23062 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23063 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23064 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23065 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23066 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23067 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23068 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23069 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23070 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23071 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23072 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23074 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23075 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23076 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23077 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23078 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23079 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23080 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23081 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23082 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23084 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23085 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23086 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23087 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23088 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23089 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23090 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23091 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23092 FPU_NONE, "Cortex-A5"),
23093 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23094 FPU_ARCH_NEON_VFP_V4,
23096 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23097 ARM_FEATURE (0, FPU_VFP_V3
23098 | FPU_NEON_EXT_V1),
23100 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23101 ARM_FEATURE (0, FPU_VFP_V3
23102 | FPU_NEON_EXT_V1),
23104 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23105 FPU_ARCH_NEON_VFP_V4,
23107 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23108 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23110 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23111 FPU_NONE, "Cortex-R5"),
23112 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23113 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23114 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23115 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23116 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23117 /* ??? XSCALE is really an architecture. */
23118 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23119 /* ??? iwmmxt is not a processor. */
23120 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23121 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23122 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23124 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23127 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23131 struct arm_arch_option_table
23135 const arm_feature_set value;
23136 const arm_feature_set default_fpu;
23139 /* This list should, at a minimum, contain all the architecture names
23140 recognized by GCC. */
23141 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23142 static const struct arm_arch_option_table arm_archs[] =
23144 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23145 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23146 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23147 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23148 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23149 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23150 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23151 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23152 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23153 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23154 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23155 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23156 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23157 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23158 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23159 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23160 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23161 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23162 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23163 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23164 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23165 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23166 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23167 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23168 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23169 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23170 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23171 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23172 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23173 /* The official spelling of the ARMv7 profile variants is the dashed form.
23174 Accept the non-dashed form for compatibility with old toolchains. */
23175 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23176 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23177 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23178 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23179 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23180 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23181 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23182 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23183 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23184 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23185 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23187 #undef ARM_ARCH_OPT
23189 /* ISA extensions in the co-processor and main instruction set space. */
23190 struct arm_option_extension_value_table
23194 const arm_feature_set value;
23195 const arm_feature_set allowed_archs;
23198 /* The following table must be in alphabetical order with a NULL last entry.
23200 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23201 static const struct arm_option_extension_value_table arm_extensions[] =
23203 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23204 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23205 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23206 ARM_EXT_OPT ("iwmmxt2",
23207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23208 ARM_EXT_OPT ("maverick",
23209 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23210 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23211 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23212 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23213 ARM_FEATURE (ARM_EXT_V6M, 0)),
23214 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23215 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23216 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23218 ARM_FEATURE (ARM_EXT_V7A, 0)),
23219 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23220 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23224 /* ISA floating-point and Advanced SIMD extensions. */
23225 struct arm_option_fpu_value_table
23228 const arm_feature_set value;
23231 /* This list should, at a minimum, contain all the fpu names
23232 recognized by GCC. */
23233 static const struct arm_option_fpu_value_table arm_fpus[] =
23235 {"softfpa", FPU_NONE},
23236 {"fpe", FPU_ARCH_FPE},
23237 {"fpe2", FPU_ARCH_FPE},
23238 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23239 {"fpa", FPU_ARCH_FPA},
23240 {"fpa10", FPU_ARCH_FPA},
23241 {"fpa11", FPU_ARCH_FPA},
23242 {"arm7500fe", FPU_ARCH_FPA},
23243 {"softvfp", FPU_ARCH_VFP},
23244 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23245 {"vfp", FPU_ARCH_VFP_V2},
23246 {"vfp9", FPU_ARCH_VFP_V2},
23247 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23248 {"vfp10", FPU_ARCH_VFP_V2},
23249 {"vfp10-r0", FPU_ARCH_VFP_V1},
23250 {"vfpxd", FPU_ARCH_VFP_V1xD},
23251 {"vfpv2", FPU_ARCH_VFP_V2},
23252 {"vfpv3", FPU_ARCH_VFP_V3},
23253 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23254 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23255 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23256 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23257 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23258 {"arm1020t", FPU_ARCH_VFP_V1},
23259 {"arm1020e", FPU_ARCH_VFP_V2},
23260 {"arm1136jfs", FPU_ARCH_VFP_V2},
23261 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23262 {"maverick", FPU_ARCH_MAVERICK},
23263 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23264 {"neon-fp16", FPU_ARCH_NEON_FP16},
23265 {"vfpv4", FPU_ARCH_VFP_V4},
23266 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23267 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23268 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23269 {NULL, ARM_ARCH_NONE}
23272 struct arm_option_value_table
23278 static const struct arm_option_value_table arm_float_abis[] =
23280 {"hard", ARM_FLOAT_ABI_HARD},
23281 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23282 {"soft", ARM_FLOAT_ABI_SOFT},
23287 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23288 static const struct arm_option_value_table arm_eabis[] =
23290 {"gnu", EF_ARM_EABI_UNKNOWN},
23291 {"4", EF_ARM_EABI_VER4},
23292 {"5", EF_ARM_EABI_VER5},
23297 struct arm_long_option_table
23299 char * option; /* Substring to match. */
23300 char * help; /* Help information. */
23301 int (* func) (char * subopt); /* Function to decode sub-option. */
23302 char * deprecated; /* If non-null, print this message. */
23306 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23308 arm_feature_set *ext_set = (arm_feature_set *)
23309 xmalloc (sizeof (arm_feature_set));
23311 /* We insist on extensions being specified in alphabetical order, and with
23312 extensions being added before being removed. We achieve this by having
23313 the global ARM_EXTENSIONS table in alphabetical order, and using the
23314 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23315 or removing it (0) and only allowing it to change in the order
23317 const struct arm_option_extension_value_table * opt = NULL;
23318 int adding_value = -1;
23320 /* Copy the feature set, so that we can modify it. */
23321 *ext_set = **opt_p;
23324 while (str != NULL && *str != 0)
23331 as_bad (_("invalid architectural extension"));
23336 ext = strchr (str, '+');
23341 len = strlen (str);
23343 if (len >= 2 && strncmp (str, "no", 2) == 0)
23345 if (adding_value != 0)
23348 opt = arm_extensions;
23356 if (adding_value == -1)
23359 opt = arm_extensions;
23361 else if (adding_value != 1)
23363 as_bad (_("must specify extensions to add before specifying "
23364 "those to remove"));
23371 as_bad (_("missing architectural extension"));
23375 gas_assert (adding_value != -1);
23376 gas_assert (opt != NULL);
23378 /* Scan over the options table trying to find an exact match. */
23379 for (; opt->name != NULL; opt++)
23380 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23382 /* Check we can apply the extension to this architecture. */
23383 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23385 as_bad (_("extension does not apply to the base architecture"));
23389 /* Add or remove the extension. */
23391 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23393 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23398 if (opt->name == NULL)
23400 /* Did we fail to find an extension because it wasn't specified in
23401 alphabetical order, or because it does not exist? */
23403 for (opt = arm_extensions; opt->name != NULL; opt++)
23404 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23407 if (opt->name == NULL)
23408 as_bad (_("unknown architectural extension `%s'"), str);
23410 as_bad (_("architectural extensions must be specified in "
23411 "alphabetical order"));
23417 /* We should skip the extension we've just matched the next time
23429 arm_parse_cpu (char *str)
23431 const struct arm_cpu_option_table *opt;
23432 char *ext = strchr (str, '+');
23438 len = strlen (str);
23442 as_bad (_("missing cpu name `%s'"), str);
23446 for (opt = arm_cpus; opt->name != NULL; opt++)
23447 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23449 mcpu_cpu_opt = &opt->value;
23450 mcpu_fpu_opt = &opt->default_fpu;
23451 if (opt->canonical_name)
23452 strcpy (selected_cpu_name, opt->canonical_name);
23457 for (i = 0; i < len; i++)
23458 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23459 selected_cpu_name[i] = 0;
23463 return arm_parse_extension (ext, &mcpu_cpu_opt);
23468 as_bad (_("unknown cpu `%s'"), str);
23473 arm_parse_arch (char *str)
23475 const struct arm_arch_option_table *opt;
23476 char *ext = strchr (str, '+');
23482 len = strlen (str);
23486 as_bad (_("missing architecture name `%s'"), str);
23490 for (opt = arm_archs; opt->name != NULL; opt++)
23491 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23493 march_cpu_opt = &opt->value;
23494 march_fpu_opt = &opt->default_fpu;
23495 strcpy (selected_cpu_name, opt->name);
23498 return arm_parse_extension (ext, &march_cpu_opt);
23503 as_bad (_("unknown architecture `%s'\n"), str);
23508 arm_parse_fpu (char * str)
23510 const struct arm_option_fpu_value_table * opt;
23512 for (opt = arm_fpus; opt->name != NULL; opt++)
23513 if (streq (opt->name, str))
23515 mfpu_opt = &opt->value;
23519 as_bad (_("unknown floating point format `%s'\n"), str);
23524 arm_parse_float_abi (char * str)
23526 const struct arm_option_value_table * opt;
23528 for (opt = arm_float_abis; opt->name != NULL; opt++)
23529 if (streq (opt->name, str))
23531 mfloat_abi_opt = opt->value;
23535 as_bad (_("unknown floating point abi `%s'\n"), str);
23541 arm_parse_eabi (char * str)
23543 const struct arm_option_value_table *opt;
23545 for (opt = arm_eabis; opt->name != NULL; opt++)
23546 if (streq (opt->name, str))
23548 meabi_flags = opt->value;
23551 as_bad (_("unknown EABI `%s'\n"), str);
23557 arm_parse_it_mode (char * str)
23559 bfd_boolean ret = TRUE;
23561 if (streq ("arm", str))
23562 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23563 else if (streq ("thumb", str))
23564 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23565 else if (streq ("always", str))
23566 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23567 else if (streq ("never", str))
23568 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23571 as_bad (_("unknown implicit IT mode `%s', should be "\
23572 "arm, thumb, always, or never."), str);
23579 struct arm_long_option_table arm_long_opts[] =
23581 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23582 arm_parse_cpu, NULL},
23583 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23584 arm_parse_arch, NULL},
23585 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23586 arm_parse_fpu, NULL},
23587 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23588 arm_parse_float_abi, NULL},
23590 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23591 arm_parse_eabi, NULL},
23593 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23594 arm_parse_it_mode, NULL},
23595 {NULL, NULL, 0, NULL}
23599 md_parse_option (int c, char * arg)
23601 struct arm_option_table *opt;
23602 const struct arm_legacy_option_table *fopt;
23603 struct arm_long_option_table *lopt;
23609 target_big_endian = 1;
23615 target_big_endian = 0;
23619 case OPTION_FIX_V4BX:
23624 /* Listing option. Just ignore these, we don't support additional
23629 for (opt = arm_opts; opt->option != NULL; opt++)
23631 if (c == opt->option[0]
23632 && ((arg == NULL && opt->option[1] == 0)
23633 || streq (arg, opt->option + 1)))
23635 /* If the option is deprecated, tell the user. */
23636 if (warn_on_deprecated && opt->deprecated != NULL)
23637 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23638 arg ? arg : "", _(opt->deprecated));
23640 if (opt->var != NULL)
23641 *opt->var = opt->value;
23647 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23649 if (c == fopt->option[0]
23650 && ((arg == NULL && fopt->option[1] == 0)
23651 || streq (arg, fopt->option + 1)))
23653 /* If the option is deprecated, tell the user. */
23654 if (warn_on_deprecated && fopt->deprecated != NULL)
23655 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23656 arg ? arg : "", _(fopt->deprecated));
23658 if (fopt->var != NULL)
23659 *fopt->var = &fopt->value;
23665 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23667 /* These options are expected to have an argument. */
23668 if (c == lopt->option[0]
23670 && strncmp (arg, lopt->option + 1,
23671 strlen (lopt->option + 1)) == 0)
23673 /* If the option is deprecated, tell the user. */
23674 if (warn_on_deprecated && lopt->deprecated != NULL)
23675 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23676 _(lopt->deprecated));
23678 /* Call the sup-option parser. */
23679 return lopt->func (arg + strlen (lopt->option) - 1);
23690 md_show_usage (FILE * fp)
23692 struct arm_option_table *opt;
23693 struct arm_long_option_table *lopt;
23695 fprintf (fp, _(" ARM-specific assembler options:\n"));
23697 for (opt = arm_opts; opt->option != NULL; opt++)
23698 if (opt->help != NULL)
23699 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23701 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23702 if (lopt->help != NULL)
23703 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23707 -EB assemble code for a big-endian cpu\n"));
23712 -EL assemble code for a little-endian cpu\n"));
23716 --fix-v4bx Allow BX in ARMv4 code\n"));
23724 arm_feature_set flags;
23725 } cpu_arch_ver_table;
23727 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23728 least features first. */
23729 static const cpu_arch_ver_table cpu_arch_ver[] =
23735 {4, ARM_ARCH_V5TE},
23736 {5, ARM_ARCH_V5TEJ},
23740 {11, ARM_ARCH_V6M},
23741 {12, ARM_ARCH_V6SM},
23742 {8, ARM_ARCH_V6T2},
23743 {10, ARM_ARCH_V7A},
23744 {10, ARM_ARCH_V7R},
23745 {10, ARM_ARCH_V7M},
23749 /* Set an attribute if it has not already been set by the user. */
23751 aeabi_set_attribute_int (int tag, int value)
23754 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23755 || !attributes_set_explicitly[tag])
23756 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23760 aeabi_set_attribute_string (int tag, const char *value)
23763 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23764 || !attributes_set_explicitly[tag])
23765 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23768 /* Set the public EABI object attributes. */
23770 aeabi_set_public_attributes (void)
23775 arm_feature_set flags;
23776 arm_feature_set tmp;
23777 const cpu_arch_ver_table *p;
23779 /* Choose the architecture based on the capabilities of the requested cpu
23780 (if any) and/or the instructions actually used. */
23781 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23782 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23783 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23785 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23786 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23788 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23789 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23791 /* Allow the user to override the reported architecture. */
23794 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23795 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23798 /* We need to make sure that the attributes do not identify us as v6S-M
23799 when the only v6S-M feature in use is the Operating System Extensions. */
23800 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23801 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23802 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23806 for (p = cpu_arch_ver; p->val; p++)
23808 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23811 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23815 /* The table lookup above finds the last architecture to contribute
23816 a new feature. Unfortunately, Tag13 is a subset of the union of
23817 v6T2 and v7-M, so it is never seen as contributing a new feature.
23818 We can not search for the last entry which is entirely used,
23819 because if no CPU is specified we build up only those flags
23820 actually used. Perhaps we should separate out the specified
23821 and implicit cases. Avoid taking this path for -march=all by
23822 checking for contradictory v7-A / v7-M features. */
23824 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23825 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23826 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23829 /* Tag_CPU_name. */
23830 if (selected_cpu_name[0])
23834 q = selected_cpu_name;
23835 if (strncmp (q, "armv", 4) == 0)
23840 for (i = 0; q[i]; i++)
23841 q[i] = TOUPPER (q[i]);
23843 aeabi_set_attribute_string (Tag_CPU_name, q);
23846 /* Tag_CPU_arch. */
23847 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23849 /* Tag_CPU_arch_profile. */
23850 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23852 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23854 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23859 if (profile != '\0')
23860 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
23862 /* Tag_ARM_ISA_use. */
23863 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23865 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23867 /* Tag_THUMB_ISA_use. */
23868 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23870 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23871 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23873 /* Tag_VFP_arch. */
23874 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23875 aeabi_set_attribute_int (Tag_VFP_arch,
23876 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23878 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23879 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23880 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23881 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23882 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23883 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23884 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23885 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23886 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23888 /* Tag_ABI_HardFP_use. */
23889 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23890 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23891 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23893 /* Tag_WMMX_arch. */
23894 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23895 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23896 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23897 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23899 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23900 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23901 aeabi_set_attribute_int
23902 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23905 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23906 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23907 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23911 We set Tag_DIV_use to two when integer divide instructions have been used
23912 in ARM state, or when Thumb integer divide instructions have been used,
23913 but we have no architecture profile set, nor have we any ARM instructions.
23915 For new architectures we will have to check these tests. */
23916 gas_assert (arch <= TAG_CPU_ARCH_V7E_M);
23917 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
23918 || (profile == '\0'
23919 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
23920 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
23921 aeabi_set_attribute_int (Tag_DIV_use, 2);
23923 /* Tag_MP_extension_use. */
23924 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23925 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23927 /* Tag Virtualization_use. */
23928 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23930 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23933 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23936 /* Add the default contents for the .ARM.attributes section. */
23940 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23943 aeabi_set_public_attributes ();
23945 #endif /* OBJ_ELF */
23948 /* Parse a .cpu directive. */
23951 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23953 const struct arm_cpu_option_table *opt;
23957 name = input_line_pointer;
23958 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23959 input_line_pointer++;
23960 saved_char = *input_line_pointer;
23961 *input_line_pointer = 0;
23963 /* Skip the first "all" entry. */
23964 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23965 if (streq (opt->name, name))
23967 mcpu_cpu_opt = &opt->value;
23968 selected_cpu = opt->value;
23969 if (opt->canonical_name)
23970 strcpy (selected_cpu_name, opt->canonical_name);
23974 for (i = 0; opt->name[i]; i++)
23975 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23977 selected_cpu_name[i] = 0;
23979 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23980 *input_line_pointer = saved_char;
23981 demand_empty_rest_of_line ();
23984 as_bad (_("unknown cpu `%s'"), name);
23985 *input_line_pointer = saved_char;
23986 ignore_rest_of_line ();
23990 /* Parse a .arch directive. */
23993 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23995 const struct arm_arch_option_table *opt;
23999 name = input_line_pointer;
24000 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24001 input_line_pointer++;
24002 saved_char = *input_line_pointer;
24003 *input_line_pointer = 0;
24005 /* Skip the first "all" entry. */
24006 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24007 if (streq (opt->name, name))
24009 mcpu_cpu_opt = &opt->value;
24010 selected_cpu = opt->value;
24011 strcpy (selected_cpu_name, opt->name);
24012 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24013 *input_line_pointer = saved_char;
24014 demand_empty_rest_of_line ();
24018 as_bad (_("unknown architecture `%s'\n"), name);
24019 *input_line_pointer = saved_char;
24020 ignore_rest_of_line ();
24024 /* Parse a .object_arch directive. */
24027 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24029 const struct arm_arch_option_table *opt;
24033 name = input_line_pointer;
24034 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24035 input_line_pointer++;
24036 saved_char = *input_line_pointer;
24037 *input_line_pointer = 0;
24039 /* Skip the first "all" entry. */
24040 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24041 if (streq (opt->name, name))
24043 object_arch = &opt->value;
24044 *input_line_pointer = saved_char;
24045 demand_empty_rest_of_line ();
24049 as_bad (_("unknown architecture `%s'\n"), name);
24050 *input_line_pointer = saved_char;
24051 ignore_rest_of_line ();
24054 /* Parse a .arch_extension directive. */
24057 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24059 const struct arm_option_extension_value_table *opt;
24062 int adding_value = 1;
24064 name = input_line_pointer;
24065 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24066 input_line_pointer++;
24067 saved_char = *input_line_pointer;
24068 *input_line_pointer = 0;
24070 if (strlen (name) >= 2
24071 && strncmp (name, "no", 2) == 0)
24077 for (opt = arm_extensions; opt->name != NULL; opt++)
24078 if (streq (opt->name, name))
24080 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24082 as_bad (_("architectural extension `%s' is not allowed for the "
24083 "current base architecture"), name);
24088 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24090 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24092 mcpu_cpu_opt = &selected_cpu;
24093 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24094 *input_line_pointer = saved_char;
24095 demand_empty_rest_of_line ();
24099 if (opt->name == NULL)
24100 as_bad (_("unknown architecture `%s'\n"), name);
24102 *input_line_pointer = saved_char;
24103 ignore_rest_of_line ();
24106 /* Parse a .fpu directive. */
24109 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24111 const struct arm_option_fpu_value_table *opt;
24115 name = input_line_pointer;
24116 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24117 input_line_pointer++;
24118 saved_char = *input_line_pointer;
24119 *input_line_pointer = 0;
24121 for (opt = arm_fpus; opt->name != NULL; opt++)
24122 if (streq (opt->name, name))
24124 mfpu_opt = &opt->value;
24125 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24126 *input_line_pointer = saved_char;
24127 demand_empty_rest_of_line ();
24131 as_bad (_("unknown floating point format `%s'\n"), name);
24132 *input_line_pointer = saved_char;
24133 ignore_rest_of_line ();
24136 /* Copy symbol information. */
24139 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24141 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24145 /* Given a symbolic attribute NAME, return the proper integer value.
24146 Returns -1 if the attribute is not known. */
24149 arm_convert_symbolic_attribute (const char *name)
24151 static const struct
24156 attribute_table[] =
24158 /* When you modify this table you should
24159 also modify the list in doc/c-arm.texi. */
24160 #define T(tag) {#tag, tag}
24161 T (Tag_CPU_raw_name),
24164 T (Tag_CPU_arch_profile),
24165 T (Tag_ARM_ISA_use),
24166 T (Tag_THUMB_ISA_use),
24170 T (Tag_Advanced_SIMD_arch),
24171 T (Tag_PCS_config),
24172 T (Tag_ABI_PCS_R9_use),
24173 T (Tag_ABI_PCS_RW_data),
24174 T (Tag_ABI_PCS_RO_data),
24175 T (Tag_ABI_PCS_GOT_use),
24176 T (Tag_ABI_PCS_wchar_t),
24177 T (Tag_ABI_FP_rounding),
24178 T (Tag_ABI_FP_denormal),
24179 T (Tag_ABI_FP_exceptions),
24180 T (Tag_ABI_FP_user_exceptions),
24181 T (Tag_ABI_FP_number_model),
24182 T (Tag_ABI_align_needed),
24183 T (Tag_ABI_align8_needed),
24184 T (Tag_ABI_align_preserved),
24185 T (Tag_ABI_align8_preserved),
24186 T (Tag_ABI_enum_size),
24187 T (Tag_ABI_HardFP_use),
24188 T (Tag_ABI_VFP_args),
24189 T (Tag_ABI_WMMX_args),
24190 T (Tag_ABI_optimization_goals),
24191 T (Tag_ABI_FP_optimization_goals),
24192 T (Tag_compatibility),
24193 T (Tag_CPU_unaligned_access),
24194 T (Tag_FP_HP_extension),
24195 T (Tag_VFP_HP_extension),
24196 T (Tag_ABI_FP_16bit_format),
24197 T (Tag_MPextension_use),
24199 T (Tag_nodefaults),
24200 T (Tag_also_compatible_with),
24201 T (Tag_conformance),
24203 T (Tag_Virtualization_use),
24204 /* We deliberately do not include Tag_MPextension_use_legacy. */
24212 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24213 if (streq (name, attribute_table[i].name))
24214 return attribute_table[i].tag;
24220 /* Apply sym value for relocations only in the case that
24221 they are for local symbols and you have the respective
24222 architectural feature for blx and simple switches. */
24224 arm_apply_sym_value (struct fix * fixP)
24227 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24228 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24230 switch (fixP->fx_r_type)
24232 case BFD_RELOC_ARM_PCREL_BLX:
24233 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24234 if (ARM_IS_FUNC (fixP->fx_addsy))
24238 case BFD_RELOC_ARM_PCREL_CALL:
24239 case BFD_RELOC_THUMB_PCREL_BLX:
24240 if (THUMB_IS_FUNC (fixP->fx_addsy))
24251 #endif /* OBJ_ELF */