1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used;
136 static arm_feature_set thumb_arch_used;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26 = FALSE;
140 static int atpcs = FALSE;
141 static int support_interwork = FALSE;
142 static int uses_apcs_float = FALSE;
143 static int pic_code = FALSE;
144 static int fix_v4bx = FALSE;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated = TRUE;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax = FALSE;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set *legacy_cpu = NULL;
158 static const arm_feature_set *legacy_fpu = NULL;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set *mcpu_cpu_opt = NULL;
162 static arm_feature_set *mcpu_ext_opt = NULL;
163 static const arm_feature_set *mcpu_fpu_opt = NULL;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set *march_cpu_opt = NULL;
167 static arm_feature_set *march_ext_opt = NULL;
168 static const arm_feature_set *march_fpu_opt = NULL;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set *mfpu_opt = NULL;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default = FPU_DEFAULT;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
176 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
179 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
182 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
184 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
187 static const arm_feature_set cpu_default = CPU_DEFAULT;
190 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
191 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
192 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
198 static const arm_feature_set arm_ext_v4t_5 =
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
210 static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212 static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214 static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216 static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
225 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
226 static const arm_feature_set arm_ext_m =
227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
229 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
234 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
235 static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
236 static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
238 static const arm_feature_set arm_ext_v8_1m_main =
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
243 static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
253 static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
258 static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
260 static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
262 static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
264 static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
266 static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
269 static const arm_feature_set arm_arch_any = ARM_ANY;
271 static const arm_feature_set fpu_any = FPU_ANY;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
277 static const arm_feature_set arm_cext_iwmmxt2 =
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
279 static const arm_feature_set arm_cext_iwmmxt =
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
281 static const arm_feature_set arm_cext_xscale =
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
283 static const arm_feature_set arm_cext_maverick =
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285 static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287 static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
289 static const arm_feature_set fpu_vfp_ext_v1xd =
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291 static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293 static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295 static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297 static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
299 static const arm_feature_set fpu_vfp_ext_d32 =
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301 static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
305 static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307 static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
310 static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312 static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
315 static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
317 static const arm_feature_set fpu_vfp_ext_armv8 =
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
319 static const arm_feature_set fpu_vfp_ext_armv8xd =
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
321 static const arm_feature_set fpu_neon_ext_armv8 =
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
323 static const arm_feature_set fpu_crypto_ext_armv8 =
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
325 static const arm_feature_set crc_ext_armv8 =
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
327 static const arm_feature_set fpu_neon_ext_v8_1 =
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
329 static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
332 static int mfloat_abi_opt = -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch = ARM_ARCH_NONE;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext = ARM_ARCH_NONE;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu = FPU_NONE;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name[20];
350 extern FLONUM_TYPE generic_floating_point_number;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
361 static int meabi_flags = EABI_DEFAULT;
363 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
366 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS * GOT_symbol;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode = 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
398 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax = FALSE;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars[] = "#[]{}";
444 enum neon_el_type type;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type;
500 } relocs[ARM_IT_MAX_RELOCS];
502 enum pred_instruction_type pred_insn_type;
508 struct neon_type_el vectype;
509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad : 1; /* Operand is SIMD quad register. */
524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
525 unsigned iszr : 1; /* Operand is ZR register. */
526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
533 } operands[ARM_IT_MAX_OPERANDS];
536 static struct arm_it inst;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name;
569 #define COND_ALWAYS 0xE
573 const char * template_name;
577 struct asm_barrier_opt
579 const char * template_name;
581 const arm_feature_set arch;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc;
601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined;
618 struct neon_type_el eltype;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs[] =
669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name;
711 /* Parameters to instruction. */
712 unsigned int operands[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control * arm_ops_hsh;
906 static struct hash_control * arm_cond_hsh;
907 static struct hash_control * arm_vcond_hsh;
908 static struct hash_control * arm_shift_hsh;
909 static struct hash_control * arm_psr_hsh;
910 static struct hash_control * arm_v7m_psr_hsh;
911 static struct hash_control * arm_reg_hsh;
912 static struct hash_control * arm_reloc_hsh;
913 static struct hash_control * arm_barrier_opt_hsh;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS * last_label_seen;
925 static int label_is_thumb_function_name = FALSE;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
942 struct literal_pool * next;
943 unsigned int alignment;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool * list_of_pools = NULL;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME,
956 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred;
965 now_pred_compatible (int cond)
967 return (cond & ~1) == (now_pred.cc & ~1);
971 conditional_insn (void)
973 return inst.cond != COND_ALWAYS;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars[] = "#";
1027 char arm_line_separator_chars[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str, char c)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS * sp)
1071 if (symbol_get_value_expression (sp)->X_op == O_big)
1074 if (symbol_get_value_expression (sp)->X_add_symbol)
1076 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1077 || (symbol_get_value_expression (sp)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1084 static bfd_boolean in_my_get_expression = FALSE;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1104 switch (prefix_mode)
1106 case GE_NO_PREFIX: break;
1108 if (!is_immediate_prefix (**str))
1110 inst.error = _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG:
1117 if (is_immediate_prefix (**str))
1124 memset (ep, 0, sizeof (expressionS));
1126 save_in = input_line_pointer;
1127 input_line_pointer = *str;
1128 in_my_get_expression = TRUE;
1130 in_my_get_expression = FALSE;
1132 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str = input_line_pointer;
1136 input_line_pointer = save_in;
1137 if (inst.error == NULL)
1138 inst.error = (ep->X_op == O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode != GE_OPT_PREFIX_BIG
1147 && (ep->X_op == O_big
1148 || (ep->X_add_symbol
1149 && (walk_no_bignums (ep->X_add_symbol)
1151 && walk_no_bignums (ep->X_op_symbol))))))
1153 inst.error = _("invalid constant");
1154 *str = input_line_pointer;
1155 input_line_pointer = save_in;
1159 *str = input_line_pointer;
1160 input_line_pointer = save_in;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type, char * litP, int * sizeP)
1182 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t = atof_ieee (input_line_pointer, type, words);
1219 input_line_pointer = t;
1220 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1222 if (target_big_endian)
1224 for (i = 0; i < prec; i++)
1226 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1227 litP += sizeof (LITTLENUM_TYPE);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1233 for (i = prec - 1; i >= 0; i--)
1235 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1236 litP += sizeof (LITTLENUM_TYPE);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i = 0; i < prec; i += 2)
1243 md_number_to_chars (litP, (valueT) words[i + 1],
1244 sizeof (LITTLENUM_TYPE));
1245 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1246 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1247 litP += 2 * sizeof (LITTLENUM_TYPE);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS * exp)
1260 if (in_my_get_expression)
1261 exp->X_op = O_illegal;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val)
1275 exp.X_op = O_illegal;
1277 if (is_immediate_prefix (*input_line_pointer))
1279 input_line_pointer++;
1283 if (exp.X_op != O_constant)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val = exp.X_add_number;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry *
1302 arm_reg_parse_multi (char **ccp)
1306 struct reg_entry *reg;
1308 skip_whitespace (start);
1310 #ifdef REGISTER_PREFIX
1311 if (*start != REGISTER_PREFIX)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start == OPTIONAL_REGISTER_PREFIX)
1321 if (!ISALPHA (*p) || !is_name_beginner (*p))
1326 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1328 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1338 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1339 enum arm_reg_type type)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg && reg->type == REG_TYPE_CN)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor = strtoul (start, ccp, 10);
1357 if (*ccp != start && processor <= 15)
1362 case REG_TYPE_MMXWC:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg && reg->type == REG_TYPE_MMXWCG)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp, enum arm_reg_type type)
1383 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1390 if (reg && reg->type == type)
1393 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type *type, char **str)
1422 while (type->elems < NEON_MAX_TYPE_ELS)
1424 enum neon_el_type thistype = NT_untyped;
1425 unsigned thissize = -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr))
1438 case 'i': thistype = NT_integer; break;
1439 case 'f': thistype = NT_float; break;
1440 case 'p': thistype = NT_poly; break;
1441 case 's': thistype = NT_signed; break;
1442 case 'u': thistype = NT_unsigned; break;
1444 thistype = NT_float;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype == NT_float && !ISDIGIT (*ptr))
1461 thissize = strtoul (ptr, &ptr, 10);
1463 if (thissize != 8 && thissize != 16 && thissize != 32
1466 as_bad (_("bad size %d in type specifier"), thissize);
1474 type->el[type->elems].type = thistype;
1475 type->el[type->elems].size = thissize;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type->elems == 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1506 struct neon_type optype;
1510 if (parse_neon_type (&optype, &str) == SUCCESS)
1512 if (optype.elems == 1)
1513 *vectype = optype.el[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set *feature)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set *feature)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1559 && ARM_CPU_IS_ANY (cpu_variant))
1561 first_error (BAD_MVE_AUTO);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1582 enum arm_reg_type *rtype,
1583 struct neon_typed_alias *typeinfo)
1586 struct reg_entry *reg = arm_reg_parse_multi (&str);
1587 struct neon_typed_alias atype;
1588 struct neon_type_el parsetype;
1592 atype.eltype.type = NT_invtype;
1593 atype.eltype.size = -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type == REG_TYPE_NDQ
1609 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1610 || (type == REG_TYPE_VFSD
1611 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1612 || (type == REG_TYPE_NSDQ
1613 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1614 || reg->type == REG_TYPE_NQ))
1615 || (type == REG_TYPE_NSD
1616 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1617 || (type == REG_TYPE_MMXWC
1618 && (reg->type == REG_TYPE_MMXWCG)))
1619 type = (enum arm_reg_type) reg->type;
1621 if (type == REG_TYPE_MQ)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1626 if (!reg || reg->type != REG_TYPE_NQ)
1629 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1637 && (type == REG_TYPE_NQ))
1641 if (type != reg->type)
1647 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1649 if ((atype.defined & NTA_HASTYPE) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype.defined |= NTA_HASTYPE;
1655 atype.eltype = parsetype;
1658 if (skip_past_char (&str, '[') == SUCCESS)
1660 if (type != REG_TYPE_VFD
1661 && !(type == REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1663 && !(type == REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype.defined & NTA_HASINDEX) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype.defined |= NTA_HASINDEX;
1681 if (skip_past_char (&str, ']') == SUCCESS)
1682 atype.index = NEON_ALL_LANES;
1687 my_get_expression (&exp, &str, GE_NO_PREFIX);
1689 if (exp.X_op != O_constant)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str, ']') == FAIL)
1698 atype.index = exp.X_add_number;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1722 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1724 struct neon_typed_alias atype;
1726 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype.defined & NTA_HASINDEX) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype = atype.eltype;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1759 arm_reg_type reg_type)
1763 struct neon_typed_alias atype;
1766 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1784 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1787 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
1789 first_error (_("scalar must have an index"));
1792 else if (atype.index >= reg_size / elsize)
1794 first_error (_("scalar index out of range"));
1799 *type = atype.eltype;
1803 return reg * 16 + atype.index;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp, enum reg_list_els etype)
1828 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str);
1846 const char apsr_str[] = "apsr";
1847 int apsr_str_len = strlen (apsr_str);
1849 reg = arm_reg_parse (&str, REGLIST_RN);
1850 if (etype == REGLIST_CLRM)
1852 if (reg == REG_SP || reg == REG_PC)
1854 else if (reg == FAIL
1855 && !strncasecmp (str, apsr_str, apsr_str_len)
1856 && !ISALPHA (*(str + apsr_str_len)))
1859 str += apsr_str_len;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs[REGLIST_RN]));
1883 first_error (_("bad range in register list"));
1887 for (i = cur_reg + 1; i < reg; i++)
1889 if (range & (1 << i))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range & (1 << reg))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg <= cur_reg)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str) != FAIL
1909 || (in_range = 1, *str++ == '-'));
1912 if (skip_past_char (&str, '}') == FAIL)
1914 first_error (_("missing `}'"));
1918 else if (etype == REGLIST_RN)
1922 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1925 if (exp.X_op == O_constant)
1927 if (exp.X_add_number
1928 != (exp.X_add_number & 0x0000ffff))
1930 inst.error = _("invalid register mask");
1934 if ((range & exp.X_add_number) != 0)
1936 int regno = range & exp.X_add_number;
1939 regno = (1 << regno) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range |= exp.X_add_number;
1949 if (inst.relocs[0].type != 0)
1951 inst.error = _("expression too complex");
1955 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1956 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1957 inst.relocs[0].pc_rel = 0;
1961 if (*str == '|' || *str == '+')
1967 while (another_range);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
1990 bfd_boolean *partial_match)
1995 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1999 unsigned long mask = 0;
2001 bfd_boolean vpr_seen = FALSE;
2002 bfd_boolean expect_vpr =
2003 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
2005 if (skip_past_char (&str, '{') == FAIL)
2007 inst.error = _("expecting {");
2014 case REGLIST_VFP_S_VPR:
2015 regtype = REG_TYPE_VFS;
2020 case REGLIST_VFP_D_VPR:
2021 regtype = REG_TYPE_VFD;
2024 case REGLIST_NEON_D:
2025 regtype = REG_TYPE_NDQ;
2032 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2049 base_reg = max_regs;
2050 *partial_match = FALSE;
2054 int setmask = 1, addregs = 1;
2055 const char vpr_str[] = "vpr";
2056 int vpr_str_len = strlen (vpr_str);
2058 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
2062 if (new_base == FAIL
2063 && !strncasecmp (str, vpr_str, vpr_str_len)
2064 && !ISALPHA (*(str + vpr_str_len))
2070 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base == FAIL)
2079 if (regtype == REG_TYPE_VFS)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base == FAIL)
2090 first_error (_(reg_expected_msgs[regtype]));
2094 *partial_match = TRUE;
2098 if (new_base >= max_regs)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype == REG_TYPE_NQ)
2111 if (new_base < base_reg)
2112 base_reg = new_base;
2114 if (mask & (setmask << new_base))
2116 first_error (_("invalid register list"));
2120 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask |= setmask << new_base;
2129 if (*str == '-') /* We have the start of a range expression */
2135 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
2138 inst.error = gettext (reg_expected_msgs[regtype]);
2142 if (high_range >= max_regs)
2144 first_error (_("register out of range in list"));
2148 if (regtype == REG_TYPE_NQ)
2149 high_range = high_range + 1;
2151 if (high_range <= new_base)
2153 inst.error = _("register range not in ascending order");
2157 for (new_base += addregs; new_base <= high_range; new_base += addregs)
2159 if (mask & (setmask << new_base))
2161 inst.error = _("invalid register list");
2165 mask |= setmask << new_base;
2170 while (skip_past_comma (&str) != FAIL);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen && count == 0) || count > max_regs)
2180 if (expect_vpr && !vpr_seen)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i = 0; i < count; i++)
2190 if ((mask & (1u << i)) == 0)
2192 inst.error = _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2213 if (a->defined != b->defined)
2216 if ((a->defined & NTA_HASTYPE) != 0
2217 && (a->eltype.type != b->eltype.type
2218 || a->eltype.size != b->eltype.size))
2221 if ((a->defined & NTA_HASINDEX) != 0
2222 && (a->index != b->index))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str, unsigned *pbase,
2243 struct neon_type_el *eltype)
2250 int leading_brace = 0;
2251 enum arm_reg_type rtype = REG_TYPE_NDQ;
2252 const char *const incr_error = mve ? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error = _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype;
2256 firsttype.defined = 0;
2257 firsttype.eltype.type = NT_invtype;
2258 firsttype.eltype.size = -1;
2259 firsttype.index = -1;
2261 if (skip_past_char (&ptr, '{') == SUCCESS)
2266 struct neon_typed_alias atype;
2268 rtype = REG_TYPE_MQ;
2269 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2273 first_error (_(reg_expected_msgs[rtype]));
2280 if (rtype == REG_TYPE_NQ)
2286 else if (reg_incr == -1)
2288 reg_incr = getreg - base_reg;
2289 if (reg_incr < 1 || reg_incr > 2)
2291 first_error (_(incr_error));
2295 else if (getreg != base_reg + reg_incr * count)
2297 first_error (_(incr_error));
2301 if (! neon_alias_types_same (&atype, &firsttype))
2303 first_error (_(type_error));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype;
2312 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2314 lane = NEON_INTERLEAVE_LANES;
2315 else if (lane != NEON_INTERLEAVE_LANES)
2317 first_error (_(type_error));
2322 else if (reg_incr != 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2331 first_error (_(reg_expected_msgs[rtype]));
2334 if (! neon_alias_types_same (&htype, &firsttype))
2336 first_error (_(type_error));
2339 count += hireg + dregs - getreg;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype == REG_TYPE_NQ)
2350 if ((atype.defined & NTA_HASINDEX) != 0)
2354 else if (lane != atype.index)
2356 first_error (_(type_error));
2360 else if (lane == -1)
2361 lane = NEON_INTERLEAVE_LANES;
2362 else if (lane != NEON_INTERLEAVE_LANES)
2364 first_error (_(type_error));
2369 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane = NEON_INTERLEAVE_LANES;
2376 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
2377 || (count > 1 && reg_incr == -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2385 first_error (_("expected }"));
2393 *eltype = firsttype.eltype;
2398 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str)
2410 struct reloc_entry *r;
2414 return BFD_RELOC_UNUSED;
2419 while (*q && *q != ')' && *q != ',')
2424 if ((r = (struct reloc_entry *)
2425 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2432 /* Directives: register aliases. */
2434 static struct reg_entry *
2435 insert_reg_alias (char *str, unsigned number, int type)
2437 struct reg_entry *new_reg;
2440 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2442 if (new_reg->builtin)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg->number != number || new_reg->type != type)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2453 name = xstrdup (str);
2454 new_reg = XNEW (struct reg_entry);
2456 new_reg->name = name;
2457 new_reg->number = number;
2458 new_reg->type = type;
2459 new_reg->builtin = FALSE;
2460 new_reg->neon = NULL;
2462 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2469 insert_neon_reg_alias (char *str, int number, int type,
2470 struct neon_typed_alias *atype)
2472 struct reg_entry *reg = insert_reg_alias (str, number, type);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg->neon = XNEW (struct neon_typed_alias);
2483 *reg->neon = *atype;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname, char *p)
2497 struct reg_entry *old;
2498 char *oldname, *nbuf;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname, " .req ", 6) != 0)
2508 if (*oldname == '\0')
2511 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname = original_case_string;
2525 nlen = strlen (newname);
2528 nbuf = xmemdup0 (newname, nlen);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2535 for (p = nbuf; *p; p++)
2538 if (strncmp (nbuf, newname, nlen))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2556 for (p = nbuf; *p; p++)
2559 if (strncmp (nbuf, newname, nlen))
2560 insert_reg_alias (nbuf, old->number, old->type);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname, char *p)
2580 enum arm_reg_type basetype;
2581 struct reg_entry *basereg;
2582 struct reg_entry mybasereg;
2583 struct neon_type ntype;
2584 struct neon_typed_alias typeinfo;
2585 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2588 typeinfo.defined = 0;
2589 typeinfo.eltype.type = NT_invtype;
2590 typeinfo.eltype.size = -1;
2591 typeinfo.index = -1;
2595 if (strncmp (p, " .dn ", 5) == 0)
2596 basetype = REG_TYPE_VFD;
2597 else if (strncmp (p, " .qn ", 5) == 0)
2598 basetype = REG_TYPE_NQ;
2607 basereg = arm_reg_parse_multi (&p);
2609 if (basereg && basereg->type != basetype)
2611 as_bad (_("bad type for register"));
2615 if (basereg == NULL)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp, &p, GE_NO_PREFIX);
2620 if (exp.X_op != O_constant)
2622 as_bad (_("expression must be constant"));
2625 basereg = &mybasereg;
2626 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2632 typeinfo = *basereg->neon;
2634 if (parse_neon_type (&ntype, &p) == SUCCESS)
2636 /* We got a type. */
2637 if (typeinfo.defined & NTA_HASTYPE)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo.defined |= NTA_HASTYPE;
2644 if (ntype.elems != 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo.eltype = ntype.el[0];
2652 if (skip_past_char (&p, '[') == SUCCESS)
2655 /* We got a scalar index. */
2657 if (typeinfo.defined & NTA_HASINDEX)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp, &p, GE_NO_PREFIX);
2665 if (exp.X_op != O_constant)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo.defined |= NTA_HASINDEX;
2672 typeinfo.index = exp.X_add_number;
2674 if (skip_past_char (&p, ']') == FAIL)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen = nameend - newname;
2687 newname = original_case_string;
2688 namelen = strlen (newname);
2691 namebuf = xmemdup0 (newname, namelen);
2693 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2694 typeinfo.defined != 0 ? &typeinfo : NULL);
2696 /* Insert name in all uppercase. */
2697 for (p = namebuf; *p; p++)
2700 if (strncmp (namebuf, newname, namelen))
2701 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2702 typeinfo.defined != 0 ? &typeinfo : NULL);
2704 /* Insert name in all lowercase. */
2705 for (p = namebuf; *p; p++)
2708 if (strncmp (namebuf, newname, namelen))
2709 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2710 typeinfo.defined != 0 ? &typeinfo : NULL);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED)
2749 name = input_line_pointer;
2751 while (*input_line_pointer != 0
2752 && *input_line_pointer != ' '
2753 && *input_line_pointer != '\n')
2754 ++input_line_pointer;
2756 saved_char = *input_line_pointer;
2757 *input_line_pointer = 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2767 as_bad (_("unknown register alias '%s'"), name);
2768 else if (reg->builtin)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh, name, FALSE);
2777 free ((char *) reg->name);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf = strdup (name);
2787 for (p = nbuf; *p; p++)
2789 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2792 hash_delete (arm_reg_hsh, nbuf, FALSE);
2793 free ((char *) reg->name);
2799 for (p = nbuf; *p; p++)
2801 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2804 hash_delete (arm_reg_hsh, nbuf, FALSE);
2805 free ((char *) reg->name);
2815 *input_line_pointer = saved_char;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2833 const char * symname;
2840 type = BSF_NO_FLAGS;
2844 type = BSF_NO_FLAGS;
2848 type = BSF_NO_FLAGS;
2854 symbolP = symbol_new (symname, now_seg, value, frag);
2855 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2860 THUMB_SET_FUNC (symbolP, 0);
2861 ARM_SET_THUMB (symbolP, 0);
2862 ARM_SET_INTERWORK (symbolP, support_interwork);
2866 THUMB_SET_FUNC (symbolP, 1);
2867 ARM_SET_THUMB (symbolP, 1);
2868 ARM_SET_INTERWORK (symbolP, support_interwork);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag->tc_frag_data.first_map != NULL)
2889 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2890 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2892 frag->tc_frag_data.first_map = symbolP;
2894 if (frag->tc_frag_data.last_map != NULL)
2896 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2897 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2898 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2900 frag->tc_frag_data.last_map = symbolP;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state,
2909 valueT value, fragS *frag, offsetT bytes)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag->tc_frag_data.last_map != NULL
2913 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2915 symbolS *symp = frag->tc_frag_data.last_map;
2919 know (frag->tc_frag_data.first_map == symp);
2920 frag->tc_frag_data.first_map = NULL;
2922 frag->tc_frag_data.last_map = NULL;
2923 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2926 make_mapping_symbol (MAP_DATA, value, frag);
2927 make_mapping_symbol (state, value + bytes, frag);
2930 static void mapping_state_2 (enum mstate state, int max_chars);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state)
2939 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2941 if (mapstate == state)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state == MAP_ARM || state == MAP_THUMB)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state, int max_chars)
2975 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2977 if (!SEG_NORMAL (now_seg))
2980 if (mapstate == state)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2986 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2988 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2989 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2995 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2996 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS * symbolP)
3011 const char * name = S_GET_NAME (symbolP);
3012 symbolS * new_target;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP) || name[0] == '.')
3028 real_start = concat (STUB_NAME, name, NULL);
3029 new_target = symbol_find (real_start);
3032 if (new_target == NULL)
3034 as_warn (_("Failed to find real start of function: %s\n"), name);
3035 new_target = symbolP;
3043 opcode_select (int width)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width);
3081 s_arm (int ignore ATTRIBUTE_UNUSED)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED)
3099 temp = get_absolute_expression ();
3104 opcode_select (temp);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name = TRUE;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim = get_symbol_name (& name);
3157 end_name = input_line_pointer;
3158 (void) restore_line_pointer (delim);
3160 if (*input_line_pointer != ',')
3163 as_bad (_("expected comma after name \"%s\""), name);
3165 ignore_rest_of_line ();
3169 input_line_pointer++;
3172 if (name[0] == '.' && name[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP = symbol_find (name)) == NULL
3179 && (symbolP = md_undefined_symbol (name)) == NULL)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing & LISTING_SYMBOLS)
3187 extern struct list_info_struct * listing_tail;
3188 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
3190 memset (dummy_frag, 0, sizeof (fragS));
3191 dummy_frag->fr_type = rs_fill;
3192 dummy_frag->line = listing_tail;
3193 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3194 dummy_frag->fr_symbol = symbolP;
3198 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP);
3211 && S_IS_DEFINED (symbolP)
3212 && S_GET_SEGMENT (symbolP) != reg_section)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3215 pseudo_set (symbolP);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP, 1);
3222 ARM_SET_THUMB (symbolP, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP, support_interwork);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED)
3238 delim = get_symbol_name (& name);
3240 if (!strcasecmp (name, "unified"))
3241 unified_syntax = TRUE;
3242 else if (!strcasecmp (name, "divided"))
3243 unified_syntax = FALSE;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name);
3249 (void) restore_line_pointer (delim);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3286 if (codecomposer_syntax)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name)
3297 static const char * last_name = NULL;
3301 gas_assert (last_name == NULL);
3304 if (debug_type == DEBUG_STABS)
3305 stabs_generate_asm_func (name, name);
3309 gas_assert (last_name != NULL);
3311 if (debug_type == DEBUG_STABS)
3312 stabs_generate_asm_endfunc (last_name, last_name);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3321 if (codecomposer_syntax)
3323 switch (asmfunc_state)
3325 case OUTSIDE_ASMFUNC:
3326 asmfunc_state = WAITING_ASMFUNC_NAME;
3329 case WAITING_ASMFUNC_NAME:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3346 if (codecomposer_syntax)
3348 switch (asmfunc_state)
3350 case OUTSIDE_ASMFUNC:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC:
3359 asmfunc_state = OUTSIDE_ASMFUNC;
3360 asmfunc_debug (NULL);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name)
3372 if (codecomposer_syntax)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool *
3381 find_literal_pool (void)
3383 literal_pool * pool;
3385 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3387 if (pool->section == now_seg
3388 && pool->sub_section == now_subseg)
3395 static literal_pool *
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num = 1;
3400 literal_pool * pool;
3402 pool = find_literal_pool ();
3406 /* Create a new pool. */
3407 pool = XNEW (literal_pool);
3411 pool->next_free_entry = 0;
3412 pool->section = now_seg;
3413 pool->sub_section = now_subseg;
3414 pool->next = list_of_pools;
3415 pool->symbol = NULL;
3416 pool->alignment = 2;
3418 /* Add it to the list. */
3419 list_of_pools = pool;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool->symbol == NULL)
3425 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3426 (valueT) 0, &zero_address_frag);
3427 pool->id = latest_pool_num ++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool * pool;
3443 unsigned int entry, pool_size = 0;
3444 bfd_boolean padding_slot_p = FALSE;
3450 imm1 = inst.operands[1].imm;
3451 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3452 : inst.relocs[0].exp.X_unsigned ? 0
3453 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3454 if (target_big_endian)
3457 imm2 = inst.operands[1].imm;
3461 pool = find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry = 0; entry < pool->next_free_entry; entry ++)
3468 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3469 && (inst.relocs[0].exp.X_op == O_constant)
3470 && (pool->literals[entry].X_add_number
3471 == inst.relocs[0].exp.X_add_number)
3472 && (pool->literals[entry].X_md == nbytes)
3473 && (pool->literals[entry].X_unsigned
3474 == inst.relocs[0].exp.X_unsigned))
3477 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3478 && (inst.relocs[0].exp.X_op == O_symbol)
3479 && (pool->literals[entry].X_add_number
3480 == inst.relocs[0].exp.X_add_number)
3481 && (pool->literals[entry].X_add_symbol
3482 == inst.relocs[0].exp.X_add_symbol)
3483 && (pool->literals[entry].X_op_symbol
3484 == inst.relocs[0].exp.X_op_symbol)
3485 && (pool->literals[entry].X_md == nbytes))
3488 else if ((nbytes == 8)
3489 && !(pool_size & 0x7)
3490 && ((entry + 1) != pool->next_free_entry)
3491 && (pool->literals[entry].X_op == O_constant)
3492 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3493 && (pool->literals[entry].X_unsigned
3494 == inst.relocs[0].exp.X_unsigned)
3495 && (pool->literals[entry + 1].X_op == O_constant)
3496 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3497 && (pool->literals[entry + 1].X_unsigned
3498 == inst.relocs[0].exp.X_unsigned))
3501 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3502 if (padding_slot_p && (nbytes == 4))
3508 /* Do we need to create a new entry? */
3509 if (entry == pool->next_free_entry)
3511 if (entry >= MAX_LITERAL_POOL_SIZE)
3513 inst.error = _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst.relocs[0].exp.X_op == O_constant
3531 || inst.relocs[0].exp.X_op == O_big))
3533 inst.error = _("invalid type for literal pool");
3536 else if (pool_size & 0x7)
3538 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3540 inst.error = _("literal pool overflow");
3544 pool->literals[entry] = inst.relocs[0].exp;
3545 pool->literals[entry].X_op = O_constant;
3546 pool->literals[entry].X_add_number = 0;
3547 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3548 pool->next_free_entry += 1;
3551 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3553 inst.error = _("literal pool overflow");
3557 pool->literals[entry] = inst.relocs[0].exp;
3558 pool->literals[entry].X_op = O_constant;
3559 pool->literals[entry].X_add_number = imm1;
3560 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3561 pool->literals[entry++].X_md = 4;
3562 pool->literals[entry] = inst.relocs[0].exp;
3563 pool->literals[entry].X_op = O_constant;
3564 pool->literals[entry].X_add_number = imm2;
3565 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3566 pool->literals[entry].X_md = 4;
3567 pool->alignment = 3;
3568 pool->next_free_entry += 1;
3572 pool->literals[entry] = inst.relocs[0].exp;
3573 pool->literals[entry].X_md = 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type == DEBUG_DWARF2)
3582 dwarf2_where (pool->locs + entry);
3584 pool->next_free_entry += 1;
3586 else if (padding_slot_p)
3588 pool->literals[entry] = inst.relocs[0].exp;
3589 pool->literals[entry].X_md = nbytes;
3592 inst.relocs[0].exp.X_op = O_symbol;
3593 inst.relocs[0].exp.X_add_number = pool_size;
3594 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret = TRUE;
3604 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3606 const char *label = input_line_pointer;
3608 while (!is_end_of_line[(int) label[-1]])
3613 as_bad (_("Invalid label '%s'"), label);
3617 asmfunc_debug (label);
3619 asmfunc_state = WAITING_ENDASMFUNC;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS * symbolP,
3630 const char * name, /* It is copied, the caller can modify. */
3631 segT segment, /* Segment identifier (SEG_<something>). */
3632 valueT valu, /* Symbol value. */
3633 fragS * frag) /* Associated fragment. */
3636 char * preserved_copy_of_name;
3638 name_length = strlen (name) + 1; /* +1 for \0. */
3639 obstack_grow (¬es, name, name_length);
3640 preserved_copy_of_name = (char *) obstack_finish (¬es);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name =
3644 tc_canonicalize_symbol_name (preserved_copy_of_name);
3647 S_SET_NAME (symbolP, preserved_copy_of_name);
3649 S_SET_SEGMENT (symbolP, segment);
3650 S_SET_VALUE (symbolP, valu);
3651 symbol_clear_list_pointers (symbolP);
3653 symbol_set_frag (symbolP, frag);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen;
3659 if (symbol_table_frozen)
3663 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3665 obj_symbol_new_hook (symbolP);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP);
3672 verify_symbol_chain (symbol_rootP, symbol_lastP);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3680 literal_pool * pool;
3683 pool = find_literal_pool ();
3685 || pool->symbol == NULL
3686 || pool->next_free_entry == 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool->alignment, 0, 0);
3694 record_alignment (now_seg, 2);
3697 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3698 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3700 sprintf (sym_name, "$$lit_\002%x", pool->id);
3702 symbol_locate (pool->symbol, sym_name, now_seg,
3703 (valueT) frag_now_fix (), frag_now);
3704 symbol_table_insert (pool->symbol);
3706 ARM_SET_THUMB (pool->symbol, thumb_mode);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3712 for (entry = 0; entry < pool->next_free_entry; entry ++)
3715 if (debug_type == DEBUG_DWARF2)
3716 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool->literals[entry]),
3720 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3723 /* Mark the pool as empty. */
3724 pool->next_free_entry = 0;
3725 pool->symbol = NULL;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3732 static valueT create_unwind_entry (int);
3733 static void start_unwind_section (const segT, int);
3734 static void add_unwind_opcode (valueT, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes);
3758 mapping_state (MAP_DATA);
3762 char *base = input_line_pointer;
3766 if (exp.X_op != O_symbol)
3767 emit_expr (&exp, (unsigned int) nbytes);
3770 char *before_reloc = input_line_pointer;
3771 reloc = parse_reloc (&input_line_pointer);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc == BFD_RELOC_UNUSED)
3779 emit_expr (&exp, (unsigned int) nbytes);
3782 reloc_howto_type *howto = (reloc_howto_type *)
3783 bfd_reloc_type_lookup (stdoutput,
3784 (bfd_reloc_code_real_type) reloc);
3785 int size = bfd_get_reloc_size (howto);
3787 if (reloc == BFD_RELOC_ARM_PLT32)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc = BFD_RELOC_UNUSED;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto->name, nbytes);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p = input_line_pointer;
3807 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3809 memcpy (save_buf, base, input_line_pointer - base);
3810 memmove (base + (input_line_pointer - before_reloc),
3811 base, before_reloc - base);
3813 input_line_pointer = base + (input_line_pointer-before_reloc);
3815 memcpy (base, save_buf, p - base);
3817 offset = nbytes - size;
3818 p = frag_more (nbytes);
3819 memset (p, 0, nbytes);
3820 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3821 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3827 while (*input_line_pointer++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer --;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS * exp)
3840 expressionS exp_high = *exp;
3842 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3843 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3844 exp->X_add_number &= 0xffff;
3845 emit_expr (exp, (unsigned int) THUMB_SIZE);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode)
3853 if ((unsigned int) opcode < 0xe800u)
3855 else if ((unsigned int) opcode >= 0xe8000000u)
3862 emit_insn (expressionS *exp, int nbytes)
3866 if (exp->X_op == O_constant)
3871 size = thumb_insn_size (exp->X_add_number);
3875 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3888 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3889 emit_thumb32_expr (exp);
3891 emit_expr (exp, (unsigned int) size);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM);
3943 if (! emit_insn (& exp, nbytes))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer --;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3966 if (*input_line_pointer == '1')
3967 highbit = 0x80000000;
3968 else if (*input_line_pointer != '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer++;
3972 if (*input_line_pointer != ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA);
3989 md_number_to_chars (p, highbit, 4);
3990 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3991 BFD_RELOC_ARM_PREL31);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4003 demand_empty_rest_of_line ();
4004 if (unwind.proc_start)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind.proc_start = expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind.opcode_count = 0;
4015 unwind.table_entry = NULL;
4016 unwind.personality_routine = NULL;
4017 unwind.personality_index = -1;
4018 unwind.frame_size = 0;
4019 unwind.fp_offset = 0;
4020 unwind.fp_reg = REG_SP;
4022 unwind.sp_restored = 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4032 demand_empty_rest_of_line ();
4033 if (!unwind.proc_start)
4034 as_bad (MISSING_FNSTART);
4036 if (unwind.table_entry)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4050 unsigned int marked_pr_dependency;
4052 demand_empty_rest_of_line ();
4054 if (!unwind.proc_start)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind.table_entry == NULL)
4062 val = create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind.saved_seg, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg, 2);
4071 ptr = frag_more (8);
4073 where = frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4077 BFD_RELOC_ARM_PREL31);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
4083 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4084 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4086 static const char *const name[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4093 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
4094 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
4095 |= 1 << unwind.personality_index;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr + 4, val, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4104 BFD_RELOC_ARM_PREL31);
4106 /* Restore the original section. */
4107 subseg_set (unwind.saved_seg, unwind.saved_subseg);
4109 unwind.proc_start = NULL;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4118 demand_empty_rest_of_line ();
4119 if (!unwind.proc_start)
4120 as_bad (MISSING_FNSTART);
4122 if (unwind.personality_routine || unwind.personality_index != -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind.personality_index = -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4136 if (!unwind.proc_start)
4137 as_bad (MISSING_FNSTART);
4139 if (unwind.personality_routine || unwind.personality_index != -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp.X_op != O_constant
4145 || exp.X_add_number < 0 || exp.X_add_number > 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind.personality_index = exp.X_add_number;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4165 if (!unwind.proc_start)
4166 as_bad (MISSING_FNSTART);
4168 if (unwind.personality_routine || unwind.personality_index != -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c = get_symbol_name (& name);
4172 p = input_line_pointer;
4174 ++ input_line_pointer;
4175 unwind.personality_routine = symbol_find_or_make (name);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind.sp_restored && unwind.fp_reg == 12
4204 && (range & 0x3000) == 0x1000)
4206 unwind.opcode_count--;
4207 unwind.sp_restored = 0;
4208 range = (range | 0x2000) & ~0x1000;
4209 unwind.pending_offset = 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n = 0; n < 8; n++)
4219 /* Break at the first non-saved register. */
4220 if ((range & (1 << (n + 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op = 0x8000 | ((range >> 4) & 0xfff);
4228 add_unwind_opcode (op, 2);
4232 /* Use the short form. */
4234 op = 0xa8; /* Pop r14. */
4236 op = 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op, 1);
4245 op = 0xb100 | (range & 0xf);
4246 add_unwind_opcode (op, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n = 0; n < 16; n++)
4252 if (range & (1 << n))
4253 unwind.frame_size += 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer) != FAIL)
4271 exp.X_op = O_illegal;
4273 if (exp.X_op != O_constant)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs = exp.X_add_number;
4282 if (num_regs < 1 || num_regs > 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op = 0xb4 | (num_regs - 1);
4295 add_unwind_opcode (op, 1);
4300 op = 0xc800 | (reg << 4) | (num_regs - 1);
4301 add_unwind_opcode (op, 2);
4303 unwind.frame_size += num_regs * 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs = 0;
4316 int num_regs_below_16;
4317 bfd_boolean partial_match;
4319 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs = count;
4336 else if (start + count > 16)
4337 num_vfpv3_regs = start + count - 16;
4339 if (num_vfpv3_regs > 0)
4341 int start_offset = start > 16 ? start - 16 : 0;
4342 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4343 add_unwind_opcode (op, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4348 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4349 if (num_regs_below_16 > 0)
4351 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4352 add_unwind_opcode (op, 2);
4355 unwind.frame_size += count * 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match;
4369 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op = 0xb8 | (count - 1);
4384 add_unwind_opcode (op, 1);
4389 op = 0xb300 | (reg << 4) | (count - 1);
4390 add_unwind_opcode (op, 2);
4392 unwind.frame_size += count * 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer == '{')
4408 input_line_pointer++;
4412 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4416 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer == '-')
4426 input_line_pointer++;
4427 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4430 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4433 else if (reg >= hi_reg)
4435 as_bad (_("bad register range"));
4438 for (; reg < hi_reg; reg++)
4442 while (skip_past_comma (&input_line_pointer) != FAIL);
4444 skip_past_char (&input_line_pointer, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i = 0; i < 16; i++)
4454 if (mask & (1 << i))
4455 unwind.frame_size += 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind.opcode_count > 0)
4463 i = unwind.opcodes[unwind.opcode_count - 1];
4464 if ((i & 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask & 0xfe00) == (1 << 9))
4472 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4473 unwind.opcode_count--;
4476 else if (i == 6 && unwind.opcode_count >= 2)
4478 i = unwind.opcodes[unwind.opcode_count - 2];
4482 op = 0xffff << (reg - 1);
4484 && ((mask & op) == (1u << (reg - 1))))
4486 op = (1 << (reg + i + 1)) - 1;
4487 op &= ~((1 << reg) - 1);
4489 unwind.opcode_count -= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg = 15; reg >= -1; reg--)
4500 /* Save registers in blocks. */
4502 || !(mask & (1 << reg)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op = 0xc0 | (hi_reg - 10);
4512 add_unwind_opcode (op, 1);
4517 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4518 add_unwind_opcode (op, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer == '{')
4539 input_line_pointer++;
4541 skip_whitespace (input_line_pointer);
4545 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4549 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer == '-')
4560 input_line_pointer++;
4561 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4564 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4567 else if (reg >= hi_reg)
4569 as_bad (_("bad register range"));
4572 for (; reg < hi_reg; reg++)
4576 while (skip_past_comma (&input_line_pointer) != FAIL);
4578 skip_past_char (&input_line_pointer, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg = 0; reg < 16; reg++)
4588 if (mask & (1 << reg))
4589 unwind.frame_size += 4;
4592 add_unwind_opcode (op, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6)
4606 struct reg_entry *reg;
4607 bfd_boolean had_brace = FALSE;
4609 if (!unwind.proc_start)
4610 as_bad (MISSING_FNSTART);
4612 /* Figure out what sort of save we have. */
4613 peek = input_line_pointer;
4621 reg = arm_reg_parse_multi (&peek);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer = peek;
4640 s_arm_unwind_save_fpa (reg->number);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4678 if (!unwind.proc_start)
4679 as_bad (MISSING_FNSTART);
4681 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4684 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer) != FAIL)
4692 if (immediate_for_directive (&offset) == FAIL)
4698 demand_empty_rest_of_line ();
4700 if (reg == REG_SP || reg == REG_PC)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind.fp_reg != REG_SP)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op, 1);
4713 /* Record the information for later. */
4714 unwind.fp_reg = reg;
4715 unwind.fp_offset = unwind.frame_size - offset;
4716 unwind.sp_restored = 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4726 if (!unwind.proc_start)
4727 as_bad (MISSING_FNSTART);
4729 if (immediate_for_directive (&offset) == FAIL)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind.frame_size += offset;
4741 unwind.pending_offset += offset;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4755 if (!unwind.proc_start)
4756 as_bad (MISSING_FNSTART);
4758 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4759 if (skip_past_comma (&input_line_pointer) == FAIL)
4762 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4764 if (fp_reg == FAIL || sp_reg == FAIL)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer) != FAIL)
4774 if (immediate_for_directive (&offset) == FAIL)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind.fp_reg = fp_reg;
4792 if (sp_reg == REG_SP)
4793 unwind.fp_offset = unwind.frame_size - offset;
4795 unwind.fp_offset -= offset;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4804 /* This is an arbitrary limit. */
4805 unsigned char op[16];
4808 if (!unwind.proc_start)
4809 as_bad (MISSING_FNSTART);
4812 if (exp.X_op == O_constant
4813 && skip_past_comma (&input_line_pointer) != FAIL)
4815 unwind.frame_size += exp.X_add_number;
4819 exp.X_op = O_illegal;
4821 if (exp.X_op != O_constant)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op[count++] = exp.X_add_number;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer) == FAIL)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op[count], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4866 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4868 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4869 attributes_set_explicitly[tag] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p = obstack_next_free (&frchain_now->frch_obstack);
4891 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4892 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4913 if (exp.X_op == O_symbol)
4914 exp.X_op = O_secrel;
4916 emit_expr (&exp, 4);
4918 while (*input_line_pointer++ == ',');
4920 input_line_pointer--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq, 0 },
4939 { "bss", s_bss, 0 },
4940 { "align", s_align_ptwo, 2 },
4941 { "arm", s_arm, 0 },
4942 { "thumb", s_thumb, 0 },
4943 { "code", s_code, 0 },
4944 { "force_thumb", s_force_thumb, 0 },
4945 { "thumb_func", s_thumb_func, 0 },
4946 { "thumb_set", s_thumb_set, 0 },
4947 { "even", s_even, 0 },
4948 { "ltorg", s_ltorg, 0 },
4949 { "pool", s_ltorg, 0 },
4950 { "syntax", s_syntax, 0 },
4951 { "cpu", s_arm_cpu, 0 },
4952 { "arch", s_arm_arch, 0 },
4953 { "object_arch", s_arm_object_arch, 0 },
4954 { "fpu", s_arm_fpu, 0 },
4955 { "arch_extension", s_arm_arch_extension, 0 },
4957 { "word", s_arm_elf_cons, 4 },
4958 { "long", s_arm_elf_cons, 4 },
4959 { "inst.n", s_arm_elf_inst, 2 },
4960 { "inst.w", s_arm_elf_inst, 4 },
4961 { "inst", s_arm_elf_inst, 0 },
4962 { "rel31", s_arm_rel31, 0 },
4963 { "fnstart", s_arm_unwind_fnstart, 0 },
4964 { "fnend", s_arm_unwind_fnend, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4966 { "personality", s_arm_unwind_personality, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4969 { "save", s_arm_unwind_save, 0 },
4970 { "vsave", s_arm_unwind_save, 1 },
4971 { "movsp", s_arm_unwind_movsp, 0 },
4972 { "pad", s_arm_unwind_pad, 0 },
4973 { "setfp", s_arm_unwind_setfp, 0 },
4974 { "unwind_raw", s_arm_unwind_raw, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file, 0 },
4986 { "loc", dwarf2_directive_loc, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4989 { "extend", float_cons, 'x' },
4990 { "ldouble", float_cons, 'x' },
4991 { "packed", float_cons, 'p' },
4993 {"secrel32", pe_directive_secrel, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref, 0},
4998 {"def", s_ccs_def, 0},
4999 {"asmfunc", s_ccs_asmfunc, 0},
5000 {"endasmfunc", s_ccs_endasmfunc, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str, int *val, int min, int max,
5015 bfd_boolean prefix_opt)
5019 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5020 if (exp.X_op != O_constant)
5022 inst.error = _("constant expression required");
5026 if (exp.X_add_number < min || exp.X_add_number > max)
5028 inst.error = _("immediate value out of range");
5032 *val = exp.X_add_number;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str, int i, expressionS *in_exp,
5042 bfd_boolean allow_symbol_p)
5045 expressionS *exp_p = in_exp ? in_exp : &exp;
5048 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5050 if (exp_p->X_op == O_constant)
5052 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5061 inst.operands[i].regisimm = 1;
5064 else if (exp_p->X_op == O_big
5065 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5067 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts != 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
5080 LITTLENUM_TYPE m = -1;
5082 if (generic_bignum[parts * 2] != 0
5083 && generic_bignum[parts * 2] != m)
5086 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
5087 if (generic_bignum[j] != generic_bignum[j-1])
5091 inst.operands[i].imm = 0;
5092 for (j = 0; j < parts; j++, idx++)
5093 inst.operands[i].imm |= generic_bignum[idx]
5094 << (LITTLENUM_NUMBER_OF_BITS * j);
5095 inst.operands[i].reg = 0;
5096 for (j = 0; j < parts; j++, idx++)
5097 inst.operands[i].reg |= generic_bignum[idx]
5098 << (LITTLENUM_NUMBER_OF_BITS * j);
5099 inst.operands[i].regisimm = 1;
5101 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str)
5115 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i = 0; fp_const[i]; i++)
5126 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
5130 *str += strlen (fp_const[i]);
5131 if (is_end_of_line[(unsigned char) **str])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
5144 /* Look for a raw floating point number. */
5145 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5146 && is_end_of_line[(unsigned char) *save_in])
5148 for (i = 0; i < NUM_FLOAT_VALS; i++)
5150 for (j = 0; j < MAX_LITTLENUMS; j++)
5152 if (words[j] != fp_values[i][j])
5156 if (j == MAX_LITTLENUMS)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in = input_line_pointer;
5167 input_line_pointer = *str;
5168 if (expression (&exp) == absolute_section
5169 && exp.X_op == O_big
5170 && exp.X_add_number < 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
5178 for (i = 0; i < NUM_FLOAT_VALS; i++)
5180 for (j = 0; j < MAX_LITTLENUMS; j++)
5182 if (words[j] != fp_values[i][j])
5186 if (j == MAX_LITTLENUMS)
5188 *str = input_line_pointer;
5189 input_line_pointer = save_in;
5196 *str = input_line_pointer;
5197 input_line_pointer = save_in;
5198 inst.error = _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm)
5208 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in)
5221 if (!is_immediate_prefix (**in))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in, "0x", 2) == 0)
5234 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5239 error_code = atof_generic (in, ".", EXP_CHARS,
5240 &generic_floating_point_number);
5243 && generic_floating_point_number.sign == '+'
5244 && (generic_floating_point_number.low
5245 > generic_floating_point_number.leader))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp, int *immed)
5262 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5263 int found_fpchar = 0;
5265 skip_past_char (&str, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum);
5275 if (strncmp (fpnum, "0x", 2) == 0)
5279 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5280 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5290 if ((str = atof_ieee (str, 's', words)) != NULL)
5292 unsigned fpword = 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5298 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5302 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str, int i, enum parse_shift_mode mode)
5351 const struct asm_shift_name *shift_name;
5352 enum shift_kind shift;
5357 for (p = *str; ISALPHA (*p); p++)
5362 inst.error = _("shift expression expected");
5366 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5369 if (shift_name == NULL)
5371 inst.error = _("shift expression expected");
5375 shift = shift_name->kind;
5379 case NO_SHIFT_RESTRICT:
5380 case SHIFT_IMMEDIATE:
5381 if (shift == SHIFT_UXTW)
5383 inst.error = _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5389 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5391 inst.error = _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE:
5397 if (shift != SHIFT_LSL)
5399 inst.error = _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE:
5405 if (shift != SHIFT_ASR)
5407 inst.error = _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE:
5412 if (shift != SHIFT_UXTW)
5414 inst.error = _("'UXTW' required");
5422 if (shift != SHIFT_RRX)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p);
5427 if (mode == NO_SHIFT_RESTRICT
5428 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5430 inst.operands[i].imm = reg;
5431 inst.operands[i].immisreg = 1;
5433 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5436 inst.operands[i].shift_kind = shift;
5437 inst.operands[i].shifted = 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str, int i)
5459 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5461 inst.operands[i].reg = value;
5462 inst.operands[i].isreg = 1;
5464 /* parse_shift will override this if appropriate */
5465 inst.relocs[0].exp.X_op = O_constant;
5466 inst.relocs[0].exp.X_add_number = 0;
5468 if (skip_past_comma (str) == FAIL)
5471 /* Shift operation on register. */
5472 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5475 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5478 if (skip_past_comma (str) == SUCCESS)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5484 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5486 inst.error = _("constant expression expected");
5490 value = exp.X_add_number;
5491 if (value < 0 || value > 30 || value % 2 != 0)
5493 inst.error = _("invalid rotation");
5496 if (inst.relocs[0].exp.X_add_number < 0
5497 || inst.relocs[0].exp.X_add_number > 255)
5499 inst.error = _("invalid constant");
5503 /* Encode as specified. */
5504 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5508 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5509 inst.relocs[0].pc_rel = 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5625 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5627 int length = strlen (group_reloc_table[i].name);
5629 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5630 && (*str)[length] == ':')
5632 *out = &group_reloc_table[i];
5633 *str += (length + 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str, int i)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str)[0] == '#' && (*str)[1] == ':')
5663 || (*str)[0] == ':')
5665 struct group_reloc_table_entry *entry;
5667 if ((*str)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5675 inst.error = _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5686 gas_assert (inst.relocs[0].type != 0);
5688 return PARSE_OPERAND_SUCCESS;
5691 return parse_shifter_operand (str, i) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str, int i)
5707 my_get_expression (&exp, &p, GE_NO_PREFIX);
5709 if (exp.X_op != O_constant)
5711 inst.error = _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL;
5715 inst.operands[i].imm = exp.X_add_number << 8;
5716 inst.operands[i].immisalign = 1;
5717 /* Alignments are not pre-indexes. */
5718 inst.operands[i].preind = 0;
5721 return PARSE_OPERAND_SUCCESS;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str, int i, int group_relocations,
5758 group_reloc_type group_type)
5763 if (skip_past_char (&p, '[') == FAIL)
5765 if (skip_past_char (&p, '=') == FAIL)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst.relocs[0].pc_rel = 1;
5769 inst.operands[i].reg = REG_PC;
5770 inst.operands[i].isreg = 1;
5771 inst.operands[i].preind = 1;
5773 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5774 return PARSE_OPERAND_FAIL;
5776 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5777 /*allow_symbol_p=*/TRUE))
5778 return PARSE_OPERAND_FAIL;
5781 return PARSE_OPERAND_SUCCESS;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p);
5787 if (group_type == GROUP_MVE)
5789 enum arm_reg_type rtype = REG_TYPE_MQ;
5790 struct neon_type_el et;
5791 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5793 inst.operands[i].isquad = 1;
5795 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5797 inst.error = BAD_ADDR_MODE;
5798 return PARSE_OPERAND_FAIL;
5801 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5803 if (group_type == GROUP_MVE)
5804 inst.error = BAD_ADDR_MODE;
5806 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5807 return PARSE_OPERAND_FAIL;
5809 inst.operands[i].reg = reg;
5810 inst.operands[i].isreg = 1;
5812 if (skip_past_comma (&p) == SUCCESS)
5814 inst.operands[i].preind = 1;
5817 else if (*p == '-') p++, inst.operands[i].negative = 1;
5819 enum arm_reg_type rtype = REG_TYPE_MQ;
5820 struct neon_type_el et;
5821 if (group_type == GROUP_MVE
5822 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5824 inst.operands[i].immisreg = 2;
5825 inst.operands[i].imm = reg;
5827 if (skip_past_comma (&p) == SUCCESS)
5829 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5831 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5832 inst.relocs[0].exp.X_add_number = 0;
5835 return PARSE_OPERAND_FAIL;
5838 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5840 inst.operands[i].imm = reg;
5841 inst.operands[i].immisreg = 1;
5843 if (skip_past_comma (&p) == SUCCESS)
5844 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5845 return PARSE_OPERAND_FAIL;
5847 else if (skip_past_char (&p, ':') == SUCCESS)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result = parse_neon_alignment (&p, i);
5854 if (result != PARSE_OPERAND_SUCCESS)
5859 if (inst.operands[i].negative)
5861 inst.operands[i].negative = 0;
5865 if (group_relocations
5866 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5868 struct group_reloc_table_entry *entry;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5880 inst.error = _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type) entry->ldr_code;
5900 = (bfd_reloc_code_real_type) entry->ldrs_code;
5905 = (bfd_reloc_code_real_type) entry->ldc_code;
5912 if (inst.relocs[0].type == 0)
5914 inst.error = _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5922 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5923 return PARSE_OPERAND_FAIL;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst.relocs[0].exp.X_op == O_constant
5926 && inst.relocs[0].exp.X_add_number == 0)
5928 skip_whitespace (q);
5932 skip_whitespace (q);
5935 inst.operands[i].negative = 1;
5940 else if (skip_past_char (&p, ':') == SUCCESS)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result = parse_neon_alignment (&p, i);
5946 if (result != PARSE_OPERAND_SUCCESS)
5950 if (skip_past_char (&p, ']') == FAIL)
5952 inst.error = _("']' expected");
5953 return PARSE_OPERAND_FAIL;
5956 if (skip_past_char (&p, '!') == SUCCESS)
5957 inst.operands[i].writeback = 1;
5959 else if (skip_past_comma (&p) == SUCCESS)
5961 if (skip_past_char (&p, '{') == SUCCESS)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p, &inst.operands[i].imm,
5965 0, 255, TRUE) == FAIL)
5966 return PARSE_OPERAND_FAIL;
5968 if (skip_past_char (&p, '}') == FAIL)
5970 inst.error = _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL;
5973 if (inst.operands[i].preind)
5975 inst.error = _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL;
5979 return PARSE_OPERAND_SUCCESS;
5983 inst.operands[i].postind = 1;
5984 inst.operands[i].writeback = 1;
5986 if (inst.operands[i].preind)
5988 inst.error = _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL;
5993 else if (*p == '-') p++, inst.operands[i].negative = 1;
5995 enum arm_reg_type rtype = REG_TYPE_MQ;
5996 struct neon_type_el et;
5997 if (group_type == GROUP_MVE
5998 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6000 inst.operands[i].immisreg = 2;
6001 inst.operands[i].imm = reg;
6003 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst.operands[i].immisalign)
6008 inst.operands[i].imm |= reg;
6010 inst.operands[i].imm = reg;
6011 inst.operands[i].immisreg = 1;
6013 if (skip_past_comma (&p) == SUCCESS)
6014 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6015 return PARSE_OPERAND_FAIL;
6021 if (inst.operands[i].negative)
6023 inst.operands[i].negative = 0;
6026 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6027 return PARSE_OPERAND_FAIL;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst.relocs[0].exp.X_op == O_constant
6030 && inst.relocs[0].exp.X_add_number == 0)
6032 skip_whitespace (q);
6036 skip_whitespace (q);
6039 inst.operands[i].negative = 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6049 inst.operands[i].preind = 1;
6050 inst.relocs[0].exp.X_op = O_constant;
6051 inst.relocs[0].exp.X_add_number = 0;
6054 return PARSE_OPERAND_SUCCESS;
6058 parse_address (char **str, int i)
6060 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str, int i, group_reloc_type type)
6067 return parse_address_main (str, i, 1, type);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str)
6077 skip_past_char (&p, '#');
6078 if (strncasecmp (p, ":lower16:", 9) == 0)
6079 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6080 else if (strncasecmp (p, ":upper16:", 9) == 0)
6081 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6083 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6086 skip_whitespace (p);
6089 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6092 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6094 if (inst.relocs[0].exp.X_op != O_constant)
6096 inst.error = _("constant expression expected");
6099 if (inst.relocs[0].exp.X_add_number < 0
6100 || inst.relocs[0].exp.X_add_number > 0xffff)
6102 inst.error = _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str, bfd_boolean lhs)
6118 unsigned long psr_field;
6119 const struct asm_psr *psr;
6121 bfd_boolean is_apsr = FALSE;
6122 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p, "SPSR", 4) == 0)
6136 goto unsupported_psr;
6138 psr_field = SPSR_BIT;
6140 else if (strncasecmp (p, "CPSR", 4) == 0)
6143 goto unsupported_psr;
6147 else if (strncasecmp (p, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p) || *p == '_');
6161 if (strncasecmp (start, "iapsr", 5) == 0
6162 || strncasecmp (start, "eapsr", 5) == 0
6163 || strncasecmp (start, "xpsr", 4) == 0
6164 || strncasecmp (start, "psr", 3) == 0)
6165 p = start + strcspn (start, "rR") + 1;
6167 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr->field <= 3)
6177 psr_field = psr->field;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr->field | (lhs ? PSR_f : 0);
6190 goto unsupported_psr;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p) || *p == '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits = 0;
6208 unsigned int g_bit = 0;
6211 for (bit = start; bit != p; bit++)
6213 switch (TOLOWER (*bit))
6216 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6236 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6240 inst.error = _("unexpected bit specified after APSR");
6245 if (nzcvq_bits == 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
6252 inst.error = _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits & 0x20) != 0
6261 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6262 || (g_bit & 0x2) != 0)
6264 inst.error = _("bad bitmask specified after APSR");
6270 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
6275 psr_field |= psr->field;
6281 goto error; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field |= (PSR_c | PSR_f);
6300 inst.error = _("selected processor does not support requested special "
6301 "purpose register");
6305 inst.error = _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end = strchr (*str, ',');
6327 size_t op_strlen = op_end - *str;
6329 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6331 if (!strncmp (*str, sysregs[i].name, op_strlen))
6333 val = sysregs[i].regl | (sysregs[i].regh << 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6359 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6360 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6363 inst.error = _("unrecognized CPS flag");
6368 if (saw_a_flag == 0)
6370 inst.error = _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str)
6387 if (strncasecmp (s, "BE", 2))
6389 else if (strncasecmp (s, "LE", 2))
6393 inst.error = _("valid endian specifiers are be or le");
6397 if (ISALNUM (s[2]) || s[2] == '_')
6399 inst.error = _("valid endian specifiers are be or le");
6404 return little_endian;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str)
6417 if (strncasecmp (s, "ROR", 3) == 0)
6421 inst.error = _("missing rotation field after comma");
6425 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6430 case 0: *str = s; return 0x0;
6431 case 8: *str = s; return 0x1;
6432 case 16: *str = s; return 0x2;
6433 case 24: *str = s; return 0x3;
6436 inst.error = _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str)
6447 const struct asm_cond *c;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q) && n < 3)
6457 cond[n] = TOLOWER (*q);
6462 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6465 inst.error = _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str)
6479 const struct asm_barrier_opt *o;
6482 while (ISALPHA (*q))
6485 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6490 if (!mark_feature_used (&o->arch))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str)
6505 if (skip_past_char (&p, '[') == FAIL)
6507 inst.error = _("'[' expected");
6511 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6513 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6516 inst.operands[0].reg = reg;
6518 if (skip_past_comma (&p) == FAIL)
6520 inst.error = _("',' expected");
6524 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6526 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6529 inst.operands[0].imm = reg;
6531 if (skip_past_comma (&p) == SUCCESS)
6533 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6535 if (inst.relocs[0].exp.X_add_number != 1)
6537 inst.error = _("invalid shift");
6540 inst.operands[0].shifted = 1;
6543 if (skip_past_char (&p, ']') == FAIL)
6545 inst.error = _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str, int *which_operand)
6562 int i = *which_operand, val;
6563 enum arm_reg_type rtype;
6565 struct neon_type_el optype;
6567 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6569 /* Cases 17 or 19. */
6570 inst.operands[i].reg = val;
6571 inst.operands[i].isvec = 1;
6572 inst.operands[i].isscalar = 2;
6573 inst.operands[i].vectype = optype;
6574 inst.operands[i++].present = 1;
6576 if (skip_past_comma (&ptr) == FAIL)
6579 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst.operands[i].reg = val;
6583 inst.operands[i].isreg = 1;
6584 inst.operands[i].present = 1;
6586 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst.operands[i].reg = val;
6590 inst.operands[i].isvec = 1;
6591 inst.operands[i].isscalar = 2;
6592 inst.operands[i].vectype = optype;
6593 inst.operands[i++].present = 1;
6595 if (skip_past_comma (&ptr) == FAIL)
6598 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6601 inst.operands[i].reg = val;
6602 inst.operands[i].isreg = 1;
6603 inst.operands[i++].present = 1;
6605 if (skip_past_comma (&ptr) == FAIL)
6608 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6611 inst.operands[i].reg = val;
6612 inst.operands[i].isreg = 1;
6613 inst.operands[i].present = 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst.operands[i].reg = val;
6625 inst.operands[i].isscalar = 1;
6626 inst.operands[i].vectype = optype;
6627 inst.operands[i++].present = 1;
6629 if (skip_past_comma (&ptr) == FAIL)
6632 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6635 inst.operands[i].reg = val;
6636 inst.operands[i].isreg = 1;
6637 inst.operands[i].present = 1;
6639 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6641 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr) == FAIL)
6648 inst.operands[i].reg = val;
6649 inst.operands[i].isreg = 1;
6650 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6651 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6652 inst.operands[i].isvec = 1;
6653 inst.operands[i].vectype = optype;
6654 inst.operands[i++].present = 1;
6656 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst.operands[i].reg = val;
6661 inst.operands[i].isreg = 1;
6662 inst.operands[i].present = 1;
6664 if (rtype == REG_TYPE_NQ)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype != REG_TYPE_VFS)
6672 if (skip_past_comma (&ptr) == FAIL)
6674 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6681 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst.operands[i].reg = val;
6690 inst.operands[i].isreg = 1;
6691 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6692 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6693 inst.operands[i].isvec = 1;
6694 inst.operands[i].vectype = optype;
6695 inst.operands[i].present = 1;
6697 if (skip_past_comma (&ptr) == SUCCESS)
6702 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6705 inst.operands[i].reg = val;
6706 inst.operands[i].isreg = 1;
6707 inst.operands[i++].present = 1;
6709 if (skip_past_comma (&ptr) == FAIL)
6712 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6715 inst.operands[i].reg = val;
6716 inst.operands[i].isreg = 1;
6717 inst.operands[i].present = 1;
6720 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst.operands[i].immisfloat = 1;
6726 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6739 /* Cases 6, 7, 16, 18. */
6740 inst.operands[i].reg = val;
6741 inst.operands[i].isreg = 1;
6742 inst.operands[i++].present = 1;
6744 if (skip_past_comma (&ptr) == FAIL)
6747 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst.operands[i].reg = val;
6751 inst.operands[i].isscalar = 2;
6752 inst.operands[i].present = 1;
6753 inst.operands[i].vectype = optype;
6755 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst.operands[i].reg = val;
6759 inst.operands[i].isscalar = 1;
6760 inst.operands[i].present = 1;
6761 inst.operands[i].vectype = optype;
6763 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6765 inst.operands[i].reg = val;
6766 inst.operands[i].isreg = 1;
6767 inst.operands[i++].present = 1;
6769 if (skip_past_comma (&ptr) == FAIL)
6772 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst.operands[i].reg = val;
6778 inst.operands[i].isreg = 1;
6779 inst.operands[i].isvec = 1;
6780 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6781 inst.operands[i].vectype = optype;
6782 inst.operands[i].present = 1;
6784 if (rtype == REG_TYPE_VFS)
6788 if (skip_past_comma (&ptr) == FAIL)
6790 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6793 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6796 inst.operands[i].reg = val;
6797 inst.operands[i].isreg = 1;
6798 inst.operands[i].isvec = 1;
6799 inst.operands[i].issingle = 1;
6800 inst.operands[i].vectype = optype;
6801 inst.operands[i].present = 1;
6806 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst.operands[i].reg = val;
6811 inst.operands[i].isvec = 1;
6812 inst.operands[i].isscalar = 2;
6813 inst.operands[i].vectype = optype;
6814 inst.operands[i++].present = 1;
6816 if (skip_past_comma (&ptr) == FAIL)
6819 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6822 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6825 inst.operands[i].reg = val;
6826 inst.operands[i].isvec = 1;
6827 inst.operands[i].isscalar = 2;
6828 inst.operands[i].vectype = optype;
6829 inst.operands[i].present = 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6843 inst.operands[i].reg = val;
6844 inst.operands[i].isreg = 1;
6845 inst.operands[i].isvec = 1;
6846 inst.operands[i].issingle = 1;
6847 inst.operands[i].vectype = optype;
6848 inst.operands[i].present = 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop, /* end of line */
6881 OP_RR, /* ARM register */
6882 OP_RRnpc, /* ARM register, not r15 */
6883 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP, /* Coprocessor number */
6889 OP_RCN, /* Coprocessor register */
6890 OP_RF, /* FPA register */
6891 OP_RVS, /* VFP single precision register */
6892 OP_RVD, /* VFP double precision register (0..15) */
6893 OP_RND, /* Neon double precision register (0..31) */
6894 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ, /* Neon quad precision register */
6898 OP_RNQMQ, /* Neon quad or MVE vector register. */
6899 OP_RVSD, /* VFP single or double precision register */
6900 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD, /* Neon single or double precision register */
6903 OP_RNDQ, /* Neon double or quad precision register */
6904 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ, /* Neon single, double or quad precision register */
6907 OP_RNSC, /* Neon scalar D[X] */
6908 OP_RVC, /* VFP control register */
6909 OP_RMF, /* Maverick F register */
6910 OP_RMD, /* Maverick D register */
6911 OP_RMFX, /* Maverick FX register */
6912 OP_RMDX, /* Maverick DX register */
6913 OP_RMAX, /* Maverick AX register */
6914 OP_RMDS, /* Maverick DSPSC register */
6915 OP_RIWR, /* iWMMXt wR register */
6916 OP_RIWC, /* iWMMXt wC register */
6917 OP_RIWG, /* iWMMXt wCG register */
6918 OP_RXA, /* XScale accumulator register */
6920 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ, /* MVE vector register. */
6925 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
6927 /* New operands for Armv8.1-M Mainline. */
6928 OP_LR, /* ARM LR register */
6929 OP_RRe, /* ARM register, only even numbered. */
6930 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
6931 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
6933 OP_REGLST, /* ARM register list */
6934 OP_CLRMLST, /* CLRM register list */
6935 OP_VRSLST, /* VFP single-precision register list */
6936 OP_VRDLST, /* VFP double-precision register list */
6937 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6938 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6939 OP_NSTRLST, /* Neon element/structure list */
6940 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
6941 OP_MSTRLST2, /* MVE vector list with two elements. */
6942 OP_MSTRLST4, /* MVE vector list with four elements. */
6944 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6945 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6946 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6947 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
6949 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6950 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6954 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6955 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6956 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6957 OP_VMOV, /* Neon VMOV operands. */
6958 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6959 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6961 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6962 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6963 OP_VLDR, /* VLDR operand. */
6965 OP_I0, /* immediate zero */
6966 OP_I7, /* immediate value 0 .. 7 */
6967 OP_I15, /* 0 .. 15 */
6968 OP_I16, /* 1 .. 16 */
6969 OP_I16z, /* 0 .. 16 */
6970 OP_I31, /* 0 .. 31 */
6971 OP_I31w, /* 0 .. 31, optional trailing ! */
6972 OP_I32, /* 1 .. 32 */
6973 OP_I32z, /* 0 .. 32 */
6974 OP_I63, /* 0 .. 63 */
6975 OP_I63s, /* -64 .. 63 */
6976 OP_I64, /* 1 .. 64 */
6977 OP_I64z, /* 0 .. 64 */
6978 OP_I255, /* 0 .. 255 */
6980 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6981 OP_I7b, /* 0 .. 7 */
6982 OP_I15b, /* 0 .. 15 */
6983 OP_I31b, /* 0 .. 31 */
6985 OP_SH, /* shifter operand */
6986 OP_SHG, /* shifter operand with possible group relocation */
6987 OP_ADDR, /* Memory address expression (any mode) */
6988 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
6989 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6990 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6991 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6992 OP_EXP, /* arbitrary expression */
6993 OP_EXPi, /* same, with optional immediate prefix */
6994 OP_EXPr, /* same, with optional relocation suffix */
6995 OP_EXPs, /* same, with optional non-first operand relocation suffix */
6996 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6997 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
6998 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7000 OP_CPSF, /* CPS flags */
7001 OP_ENDI, /* Endianness specifier */
7002 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7003 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
7004 OP_COND, /* conditional code */
7005 OP_TB, /* Table branch. */
7007 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7009 OP_RRnpc_I0, /* ARM register or literal 0 */
7010 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
7011 OP_RR_EXi, /* ARM register or expression with imm prefix */
7012 OP_RF_IF, /* FPA register or immediate */
7013 OP_RIWR_RIWC, /* iWMMXt R or C reg */
7014 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
7016 /* Optional operands. */
7017 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7018 OP_oI31b, /* 0 .. 31 */
7019 OP_oI32b, /* 1 .. 32 */
7020 OP_oI32z, /* 0 .. 32 */
7021 OP_oIffffb, /* 0 .. 65535 */
7022 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7024 OP_oRR, /* ARM register */
7025 OP_oLR, /* ARM LR register */
7026 OP_oRRnpc, /* ARM register, not the PC */
7027 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7028 OP_oRRw, /* ARM register, not r15, optional trailing ! */
7029 OP_oRND, /* Optional Neon double precision register */
7030 OP_oRNQ, /* Optional Neon quad precision register */
7031 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
7032 OP_oRNDQ, /* Optional Neon double or quad precision register */
7033 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
7034 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7036 OP_oSHll, /* LSL immediate */
7037 OP_oSHar, /* ASR immediate */
7038 OP_oSHllar, /* LSL or ASR immediate */
7039 OP_oROR, /* ROR 0/8/16/24 */
7040 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
7042 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7044 /* Some pre-defined mixed (ARM/THUMB) operands. */
7045 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7046 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7047 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7049 OP_FIRST_OPTIONAL = OP_oI7b
7052 /* Generic instruction operand parser. This does no encoding and no
7053 semantic validation; it merely squirrels values away in the inst
7054 structure. Returns SUCCESS or FAIL depending on whether the
7055 specified grammar matched. */
7057 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
7059 unsigned const int *upat = pattern;
7060 char *backtrack_pos = 0;
7061 const char *backtrack_error = 0;
7062 int i, val = 0, backtrack_index = 0;
7063 enum arm_reg_type rtype;
7064 parse_operand_result result;
7065 unsigned int op_parse_code;
7066 bfd_boolean partial_match;
7068 #define po_char_or_fail(chr) \
7071 if (skip_past_char (&str, chr) == FAIL) \
7076 #define po_reg_or_fail(regtype) \
7079 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7080 & inst.operands[i].vectype); \
7083 first_error (_(reg_expected_msgs[regtype])); \
7086 inst.operands[i].reg = val; \
7087 inst.operands[i].isreg = 1; \
7088 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7089 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7090 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7091 || rtype == REG_TYPE_VFD \
7092 || rtype == REG_TYPE_NQ); \
7093 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7097 #define po_reg_or_goto(regtype, label) \
7100 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7101 & inst.operands[i].vectype); \
7105 inst.operands[i].reg = val; \
7106 inst.operands[i].isreg = 1; \
7107 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7108 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7109 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7110 || rtype == REG_TYPE_VFD \
7111 || rtype == REG_TYPE_NQ); \
7112 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7116 #define po_imm_or_fail(min, max, popt) \
7119 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7121 inst.operands[i].imm = val; \
7125 #define po_scalar_or_goto(elsz, label, reg_type) \
7128 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7132 inst.operands[i].reg = val; \
7133 inst.operands[i].isscalar = 1; \
7137 #define po_misc_or_fail(expr) \
7145 #define po_misc_or_fail_no_backtrack(expr) \
7149 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7150 backtrack_pos = 0; \
7151 if (result != PARSE_OPERAND_SUCCESS) \
7156 #define po_barrier_or_imm(str) \
7159 val = parse_barrier (&str); \
7160 if (val == FAIL && ! ISALPHA (*str)) \
7163 /* ISB can only take SY as an option. */ \
7164 || ((inst.instruction & 0xf0) == 0x60 \
7167 inst.error = _("invalid barrier type"); \
7168 backtrack_pos = 0; \
7174 skip_whitespace (str);
7176 for (i = 0; upat[i] != OP_stop; i++)
7178 op_parse_code = upat[i];
7179 if (op_parse_code >= 1<<16)
7180 op_parse_code = thumb ? (op_parse_code >> 16)
7181 : (op_parse_code & ((1<<16)-1));
7183 if (op_parse_code >= OP_FIRST_OPTIONAL)
7185 /* Remember where we are in case we need to backtrack. */
7186 backtrack_pos = str;
7187 backtrack_error = inst.error;
7188 backtrack_index = i;
7191 if (i > 0 && (i > 1 || inst.operands[0].present))
7192 po_char_or_fail (',');
7194 switch (op_parse_code)
7206 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7207 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7208 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7209 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7210 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7211 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
7214 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7218 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7221 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
7223 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7225 /* Also accept generic coprocessor regs for unknown registers. */
7227 po_reg_or_fail (REG_TYPE_CN);
7229 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7230 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7231 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7232 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7233 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7234 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7235 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7236 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7237 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7238 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
7241 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7244 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
7245 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7247 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7252 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7256 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
7258 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7261 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
7263 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7266 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
7268 po_reg_or_goto (REG_TYPE_RN, try_mq);
7273 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7276 po_reg_or_fail (REG_TYPE_NSDQ);
7280 po_reg_or_fail (REG_TYPE_MQ);
7282 /* Neon scalar. Using an element size of 8 means that some invalid
7283 scalars are accepted here, so deal with those in later code. */
7284 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
7288 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7291 po_imm_or_fail (0, 0, TRUE);
7296 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7300 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7305 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7308 if (parse_ifimm_zero (&str))
7309 inst.operands[i].imm = 0;
7313 = _("only floating point zero is allowed as immediate value");
7321 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
7324 po_reg_or_fail (REG_TYPE_RN);
7328 case OP_RNSDQ_RNSC_MQ:
7329 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7334 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7338 po_reg_or_fail (REG_TYPE_NSDQ);
7345 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
7348 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
7351 po_reg_or_fail (REG_TYPE_NSD);
7355 case OP_RNDQMQ_RNSC:
7356 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7361 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
7364 po_reg_or_fail (REG_TYPE_NDQ);
7370 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
7373 po_reg_or_fail (REG_TYPE_VFD);
7378 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7379 not careful then bad things might happen. */
7380 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7383 case OP_RNDQMQ_Ibig:
7384 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7389 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7392 /* There's a possibility of getting a 64-bit immediate here, so
7393 we need special handling. */
7394 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7397 inst.error = _("immediate value is out of range");
7405 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7408 po_imm_or_fail (0, 63, TRUE);
7413 po_char_or_fail ('[');
7414 po_reg_or_fail (REG_TYPE_RN);
7415 po_char_or_fail (']');
7421 po_reg_or_fail (REG_TYPE_RN);
7422 if (skip_past_char (&str, '!') == SUCCESS)
7423 inst.operands[i].writeback = 1;
7427 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7428 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7429 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
7430 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
7431 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7432 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
7433 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
7434 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
7435 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7436 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7437 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
7438 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
7440 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7442 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7443 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7445 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
7446 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7447 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
7448 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7450 /* Immediate variants */
7452 po_char_or_fail ('{');
7453 po_imm_or_fail (0, 255, TRUE);
7454 po_char_or_fail ('}');
7458 /* The expression parser chokes on a trailing !, so we have
7459 to find it first and zap it. */
7462 while (*s && *s != ',')
7467 inst.operands[i].writeback = 1;
7469 po_imm_or_fail (0, 31, TRUE);
7477 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7482 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7487 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7489 if (inst.relocs[0].exp.X_op == O_symbol)
7491 val = parse_reloc (&str);
7494 inst.error = _("unrecognized relocation suffix");
7497 else if (val != BFD_RELOC_UNUSED)
7499 inst.operands[i].imm = val;
7500 inst.operands[i].hasreloc = 1;
7506 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7508 if (inst.relocs[i].exp.X_op == O_symbol)
7510 inst.operands[i].hasreloc = 1;
7512 else if (inst.relocs[i].exp.X_op == O_constant)
7514 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7515 inst.operands[i].hasreloc = 0;
7519 /* Operand for MOVW or MOVT. */
7521 po_misc_or_fail (parse_half (&str));
7524 /* Register or expression. */
7525 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7526 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7528 /* Register or immediate. */
7529 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7530 I0: po_imm_or_fail (0, 0, FALSE); break;
7532 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7534 if (!is_immediate_prefix (*str))
7537 val = parse_fpa_immediate (&str);
7540 /* FPA immediates are encoded as registers 8-15.
7541 parse_fpa_immediate has already applied the offset. */
7542 inst.operands[i].reg = val;
7543 inst.operands[i].isreg = 1;
7546 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7547 I32z: po_imm_or_fail (0, 32, FALSE); break;
7549 /* Two kinds of register. */
7552 struct reg_entry *rege = arm_reg_parse_multi (&str);
7554 || (rege->type != REG_TYPE_MMXWR
7555 && rege->type != REG_TYPE_MMXWC
7556 && rege->type != REG_TYPE_MMXWCG))
7558 inst.error = _("iWMMXt data or control register expected");
7561 inst.operands[i].reg = rege->number;
7562 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7568 struct reg_entry *rege = arm_reg_parse_multi (&str);
7570 || (rege->type != REG_TYPE_MMXWC
7571 && rege->type != REG_TYPE_MMXWCG))
7573 inst.error = _("iWMMXt control register expected");
7576 inst.operands[i].reg = rege->number;
7577 inst.operands[i].isreg = 1;
7582 case OP_CPSF: val = parse_cps_flags (&str); break;
7583 case OP_ENDI: val = parse_endian_specifier (&str); break;
7584 case OP_oROR: val = parse_ror (&str); break;
7586 case OP_COND: val = parse_cond (&str); break;
7587 case OP_oBARRIER_I15:
7588 po_barrier_or_imm (str); break;
7590 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7596 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7597 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7599 inst.error = _("Banked registers are not available with this "
7605 val = parse_psr (&str, op_parse_code == OP_wPSR);
7609 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7612 val = parse_sys_vldr_vstr (&str);
7616 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7619 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7621 if (strncasecmp (str, "APSR_", 5) == 0)
7628 case 'c': found = (found & 1) ? 16 : found | 1; break;
7629 case 'n': found = (found & 2) ? 16 : found | 2; break;
7630 case 'z': found = (found & 4) ? 16 : found | 4; break;
7631 case 'v': found = (found & 8) ? 16 : found | 8; break;
7632 default: found = 16;
7636 inst.operands[i].isvec = 1;
7637 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7638 inst.operands[i].reg = REG_PC;
7645 po_misc_or_fail (parse_tb (&str));
7648 /* Register lists. */
7650 val = parse_reg_list (&str, REGLIST_RN);
7653 inst.operands[i].writeback = 1;
7659 val = parse_reg_list (&str, REGLIST_CLRM);
7663 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7668 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7673 /* Allow Q registers too. */
7674 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7675 REGLIST_NEON_D, &partial_match);
7679 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7680 REGLIST_VFP_S, &partial_match);
7681 inst.operands[i].issingle = 1;
7686 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7687 REGLIST_VFP_D_VPR, &partial_match);
7688 if (val == FAIL && !partial_match)
7691 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7692 REGLIST_VFP_S_VPR, &partial_match);
7693 inst.operands[i].issingle = 1;
7698 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7699 REGLIST_NEON_D, &partial_match);
7704 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7705 1, &inst.operands[i].vectype);
7706 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7710 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7711 0, &inst.operands[i].vectype);
7714 /* Addressing modes */
7716 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7720 po_misc_or_fail (parse_address (&str, i));
7724 po_misc_or_fail_no_backtrack (
7725 parse_address_group_reloc (&str, i, GROUP_LDR));
7729 po_misc_or_fail_no_backtrack (
7730 parse_address_group_reloc (&str, i, GROUP_LDRS));
7734 po_misc_or_fail_no_backtrack (
7735 parse_address_group_reloc (&str, i, GROUP_LDC));
7739 po_misc_or_fail (parse_shifter_operand (&str, i));
7743 po_misc_or_fail_no_backtrack (
7744 parse_shifter_operand_group_reloc (&str, i));
7748 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7752 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7756 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7761 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7764 po_reg_or_goto (REG_TYPE_RN, ZR);
7767 po_reg_or_fail (REG_TYPE_ZR);
7771 as_fatal (_("unhandled operand code %d"), op_parse_code);
7774 /* Various value-based sanity checks and shared operations. We
7775 do not signal immediate failures for the register constraints;
7776 this allows a syntax error to take precedence. */
7777 switch (op_parse_code)
7785 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7786 inst.error = BAD_PC;
7791 if (inst.operands[i].isreg)
7793 if (inst.operands[i].reg == REG_PC)
7794 inst.error = BAD_PC;
7795 else if (inst.operands[i].reg == REG_SP
7796 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7797 relaxed since ARMv8-A. */
7798 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7801 inst.error = BAD_SP;
7807 if (inst.operands[i].isreg
7808 && inst.operands[i].reg == REG_PC
7809 && (inst.operands[i].writeback || thumb))
7810 inst.error = BAD_PC;
7815 if (inst.operands[i].isreg)
7825 case OP_oBARRIER_I15:
7838 inst.operands[i].imm = val;
7843 if (inst.operands[i].reg != REG_LR)
7844 inst.error = _("operand must be LR register");
7849 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7850 inst.error = BAD_PC;
7854 if (inst.operands[i].isreg
7855 && (inst.operands[i].reg & 0x00000001) != 0)
7856 inst.error = BAD_ODD;
7860 if (inst.operands[i].isreg)
7862 if ((inst.operands[i].reg & 0x00000001) != 1)
7863 inst.error = BAD_EVEN;
7864 else if (inst.operands[i].reg == REG_SP)
7865 as_tsktsk (MVE_BAD_SP);
7866 else if (inst.operands[i].reg == REG_PC)
7867 inst.error = BAD_PC;
7875 /* If we get here, this operand was successfully parsed. */
7876 inst.operands[i].present = 1;
7880 inst.error = BAD_ARGS;
7885 /* The parse routine should already have set inst.error, but set a
7886 default here just in case. */
7888 inst.error = BAD_SYNTAX;
7892 /* Do not backtrack over a trailing optional argument that
7893 absorbed some text. We will only fail again, with the
7894 'garbage following instruction' error message, which is
7895 probably less helpful than the current one. */
7896 if (backtrack_index == i && backtrack_pos != str
7897 && upat[i+1] == OP_stop)
7900 inst.error = BAD_SYNTAX;
7904 /* Try again, skipping the optional argument at backtrack_pos. */
7905 str = backtrack_pos;
7906 inst.error = backtrack_error;
7907 inst.operands[backtrack_index].present = 0;
7908 i = backtrack_index;
7912 /* Check that we have parsed all the arguments. */
7913 if (*str != '\0' && !inst.error)
7914 inst.error = _("garbage following instruction");
7916 return inst.error ? FAIL : SUCCESS;
7919 #undef po_char_or_fail
7920 #undef po_reg_or_fail
7921 #undef po_reg_or_goto
7922 #undef po_imm_or_fail
7923 #undef po_scalar_or_fail
7924 #undef po_barrier_or_imm
7926 /* Shorthand macro for instruction encoding functions issuing errors. */
7927 #define constraint(expr, err) \
7938 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7939 instructions are unpredictable if these registers are used. This
7940 is the BadReg predicate in ARM's Thumb-2 documentation.
7942 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7943 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7944 #define reject_bad_reg(reg) \
7946 if (reg == REG_PC) \
7948 inst.error = BAD_PC; \
7951 else if (reg == REG_SP \
7952 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7954 inst.error = BAD_SP; \
7959 /* If REG is R13 (the stack pointer), warn that its use is
7961 #define warn_deprecated_sp(reg) \
7963 if (warn_on_deprecated && reg == REG_SP) \
7964 as_tsktsk (_("use of r13 is deprecated")); \
7967 /* Functions for operand encoding. ARM, then Thumb. */
7969 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7971 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7973 The only binary encoding difference is the Coprocessor number. Coprocessor
7974 9 is used for half-precision calculations or conversions. The format of the
7975 instruction is the same as the equivalent Coprocessor 10 instruction that
7976 exists for Single-Precision operation. */
7979 do_scalar_fp16_v82_encode (void)
7981 if (inst.cond < COND_ALWAYS)
7982 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7983 " the behaviour is UNPREDICTABLE"));
7984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
7987 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
7988 mark_feature_used (&arm_ext_fp16);
7991 /* If VAL can be encoded in the immediate field of an ARM instruction,
7992 return the encoded form. Otherwise, return FAIL. */
7995 encode_arm_immediate (unsigned int val)
8002 for (i = 2; i < 32; i += 2)
8003 if ((a = rotate_left (val, i)) <= 0xff)
8004 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8009 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8010 return the encoded form. Otherwise, return FAIL. */
8012 encode_thumb32_immediate (unsigned int val)
8019 for (i = 1; i <= 24; i++)
8022 if ((val & ~(0xff << i)) == 0)
8023 return ((val >> i) & 0x7f) | ((32 - i) << 7);
8027 if (val == ((a << 16) | a))
8029 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8033 if (val == ((a << 16) | a))
8034 return 0x200 | (a >> 8);
8038 /* Encode a VFP SP or DP register number into inst.instruction. */
8041 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8043 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8046 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
8049 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8052 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8057 first_error (_("D register out of range for selected VFP version"));
8065 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8069 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8073 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8077 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8081 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8085 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8093 /* Encode a <shift> in an ARM-format instruction. The immediate,
8094 if any, is handled by md_apply_fix. */
8096 encode_arm_shift (int i)
8098 /* register-shifted register. */
8099 if (inst.operands[i].immisreg)
8102 for (op_index = 0; op_index <= i; ++op_index)
8104 /* Check the operand only when it's presented. In pre-UAL syntax,
8105 if the destination register is the same as the first operand, two
8106 register form of the instruction can be used. */
8107 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8108 && inst.operands[op_index].reg == REG_PC)
8109 as_warn (UNPRED_REG ("r15"));
8112 if (inst.operands[i].imm == REG_PC)
8113 as_warn (UNPRED_REG ("r15"));
8116 if (inst.operands[i].shift_kind == SHIFT_RRX)
8117 inst.instruction |= SHIFT_ROR << 5;
8120 inst.instruction |= inst.operands[i].shift_kind << 5;
8121 if (inst.operands[i].immisreg)
8123 inst.instruction |= SHIFT_BY_REG;
8124 inst.instruction |= inst.operands[i].imm << 8;
8127 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8132 encode_arm_shifter_operand (int i)
8134 if (inst.operands[i].isreg)
8136 inst.instruction |= inst.operands[i].reg;
8137 encode_arm_shift (i);
8141 inst.instruction |= INST_IMMEDIATE;
8142 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8143 inst.instruction |= inst.operands[i].imm;
8147 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8149 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
8152 Generate an error if the operand is not a register. */
8153 constraint (!inst.operands[i].isreg,
8154 _("Instruction does not support =N addresses"));
8156 inst.instruction |= inst.operands[i].reg << 16;
8158 if (inst.operands[i].preind)
8162 inst.error = _("instruction does not accept preindexed addressing");
8165 inst.instruction |= PRE_INDEX;
8166 if (inst.operands[i].writeback)
8167 inst.instruction |= WRITE_BACK;
8170 else if (inst.operands[i].postind)
8172 gas_assert (inst.operands[i].writeback);
8174 inst.instruction |= WRITE_BACK;
8176 else /* unindexed - only for coprocessor */
8178 inst.error = _("instruction does not accept unindexed addressing");
8182 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8183 && (((inst.instruction & 0x000f0000) >> 16)
8184 == ((inst.instruction & 0x0000f000) >> 12)))
8185 as_warn ((inst.instruction & LOAD_BIT)
8186 ? _("destination register same as write-back base")
8187 : _("source register same as write-back base"));
8190 /* inst.operands[i] was set up by parse_address. Encode it into an
8191 ARM-format mode 2 load or store instruction. If is_t is true,
8192 reject forms that cannot be used with a T instruction (i.e. not
8195 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
8197 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8199 encode_arm_addr_mode_common (i, is_t);
8201 if (inst.operands[i].immisreg)
8203 constraint ((inst.operands[i].imm == REG_PC
8204 || (is_pc && inst.operands[i].writeback)),
8206 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8207 inst.instruction |= inst.operands[i].imm;
8208 if (!inst.operands[i].negative)
8209 inst.instruction |= INDEX_UP;
8210 if (inst.operands[i].shifted)
8212 if (inst.operands[i].shift_kind == SHIFT_RRX)
8213 inst.instruction |= SHIFT_ROR << 5;
8216 inst.instruction |= inst.operands[i].shift_kind << 5;
8217 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8221 else /* immediate offset in inst.relocs[0] */
8223 if (is_pc && !inst.relocs[0].pc_rel)
8225 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
8227 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8228 cannot use PC in addressing.
8229 PC cannot be used in writeback addressing, either. */
8230 constraint ((is_t || inst.operands[i].writeback),
8233 /* Use of PC in str is deprecated for ARMv7. */
8234 if (warn_on_deprecated
8236 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
8237 as_tsktsk (_("use of PC in this instruction is deprecated"));
8240 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8242 /* Prefer + for zero encoded value. */
8243 if (!inst.operands[i].negative)
8244 inst.instruction |= INDEX_UP;
8245 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8250 /* inst.operands[i] was set up by parse_address. Encode it into an
8251 ARM-format mode 3 load or store instruction. Reject forms that
8252 cannot be used with such instructions. If is_t is true, reject
8253 forms that cannot be used with a T instruction (i.e. not
8256 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
8258 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8260 inst.error = _("instruction does not accept scaled register index");
8264 encode_arm_addr_mode_common (i, is_t);
8266 if (inst.operands[i].immisreg)
8268 constraint ((inst.operands[i].imm == REG_PC
8269 || (is_t && inst.operands[i].reg == REG_PC)),
8271 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8273 inst.instruction |= inst.operands[i].imm;
8274 if (!inst.operands[i].negative)
8275 inst.instruction |= INDEX_UP;
8277 else /* immediate offset in inst.relocs[0] */
8279 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8280 && inst.operands[i].writeback),
8282 inst.instruction |= HWOFFSET_IMM;
8283 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8285 /* Prefer + for zero encoded value. */
8286 if (!inst.operands[i].negative)
8287 inst.instruction |= INDEX_UP;
8289 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8294 /* Write immediate bits [7:0] to the following locations:
8296 |28/24|23 19|18 16|15 4|3 0|
8297 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8299 This function is used by VMOV/VMVN/VORR/VBIC. */
8302 neon_write_immbits (unsigned immbits)
8304 inst.instruction |= immbits & 0xf;
8305 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8306 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8309 /* Invert low-order SIZE bits of XHI:XLO. */
8312 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8314 unsigned immlo = xlo ? *xlo : 0;
8315 unsigned immhi = xhi ? *xhi : 0;
8320 immlo = (~immlo) & 0xff;
8324 immlo = (~immlo) & 0xffff;
8328 immhi = (~immhi) & 0xffffffff;
8332 immlo = (~immlo) & 0xffffffff;
8346 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8350 neon_bits_same_in_bytes (unsigned imm)
8352 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8353 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8354 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8355 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8358 /* For immediate of above form, return 0bABCD. */
8361 neon_squash_bits (unsigned imm)
8363 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8364 | ((imm & 0x01000000) >> 21);
8367 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8370 neon_qfloat_bits (unsigned imm)
8372 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8375 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8376 the instruction. *OP is passed as the initial value of the op field, and
8377 may be set to a different value depending on the constant (i.e.
8378 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8379 MVN). If the immediate looks like a repeated pattern then also
8380 try smaller element sizes. */
8383 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8384 unsigned *immbits, int *op, int size,
8385 enum neon_el_type type)
8387 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8389 if (type == NT_float && !float_p)
8392 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
8394 if (size != 32 || *op == 1)
8396 *immbits = neon_qfloat_bits (immlo);
8402 if (neon_bits_same_in_bytes (immhi)
8403 && neon_bits_same_in_bytes (immlo))
8407 *immbits = (neon_squash_bits (immhi) << 4)
8408 | neon_squash_bits (immlo);
8419 if (immlo == (immlo & 0x000000ff))
8424 else if (immlo == (immlo & 0x0000ff00))
8426 *immbits = immlo >> 8;
8429 else if (immlo == (immlo & 0x00ff0000))
8431 *immbits = immlo >> 16;
8434 else if (immlo == (immlo & 0xff000000))
8436 *immbits = immlo >> 24;
8439 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8441 *immbits = (immlo >> 8) & 0xff;
8444 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8446 *immbits = (immlo >> 16) & 0xff;
8450 if ((immlo & 0xffff) != (immlo >> 16))
8457 if (immlo == (immlo & 0x000000ff))
8462 else if (immlo == (immlo & 0x0000ff00))
8464 *immbits = immlo >> 8;
8468 if ((immlo & 0xff) != (immlo >> 8))
8473 if (immlo == (immlo & 0x000000ff))
8475 /* Don't allow MVN with 8-bit immediate. */
8485 #if defined BFD_HOST_64_BIT
8486 /* Returns TRUE if double precision value V may be cast
8487 to single precision without loss of accuracy. */
8490 is_double_a_single (bfd_int64_t v)
8492 int exp = (int)((v >> 52) & 0x7FF);
8493 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8495 return (exp == 0 || exp == 0x7FF
8496 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8497 && (mantissa & 0x1FFFFFFFl) == 0;
8500 /* Returns a double precision value casted to single precision
8501 (ignoring the least significant bits in exponent and mantissa). */
8504 double_to_single (bfd_int64_t v)
8506 int sign = (int) ((v >> 63) & 1l);
8507 int exp = (int) ((v >> 52) & 0x7FF);
8508 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8514 exp = exp - 1023 + 127;
8523 /* No denormalized numbers. */
8529 return (sign << 31) | (exp << 23) | mantissa;
8531 #endif /* BFD_HOST_64_BIT */
8540 static void do_vfp_nsyn_opcode (const char *);
8542 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8543 Determine whether it can be performed with a move instruction; if
8544 it can, convert inst.instruction to that move instruction and
8545 return TRUE; if it can't, convert inst.instruction to a literal-pool
8546 load and return FALSE. If this is not a valid thing to do in the
8547 current context, set inst.error and return TRUE.
8549 inst.operands[i] describes the destination register. */
8552 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
8555 bfd_boolean thumb_p = (t == CONST_THUMB);
8556 bfd_boolean arm_p = (t == CONST_ARM);
8559 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8563 if ((inst.instruction & tbit) == 0)
8565 inst.error = _("invalid pseudo operation");
8569 if (inst.relocs[0].exp.X_op != O_constant
8570 && inst.relocs[0].exp.X_op != O_symbol
8571 && inst.relocs[0].exp.X_op != O_big)
8573 inst.error = _("constant expression expected");
8577 if (inst.relocs[0].exp.X_op == O_constant
8578 || inst.relocs[0].exp.X_op == O_big)
8580 #if defined BFD_HOST_64_BIT
8585 if (inst.relocs[0].exp.X_op == O_big)
8587 LITTLENUM_TYPE w[X_PRECISION];
8590 if (inst.relocs[0].exp.X_add_number == -1)
8592 gen_to_words (w, X_PRECISION, E_PRECISION);
8594 /* FIXME: Should we check words w[2..5] ? */
8599 #if defined BFD_HOST_64_BIT
8601 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8602 << LITTLENUM_NUMBER_OF_BITS)
8603 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8604 << LITTLENUM_NUMBER_OF_BITS)
8605 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8606 << LITTLENUM_NUMBER_OF_BITS)
8607 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8609 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8610 | (l[0] & LITTLENUM_MASK);
8614 v = inst.relocs[0].exp.X_add_number;
8616 if (!inst.operands[i].issingle)
8620 /* LDR should not use lead in a flag-setting instruction being
8621 chosen so we do not check whether movs can be used. */
8623 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8624 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8625 && inst.operands[i].reg != 13
8626 && inst.operands[i].reg != 15)
8628 /* Check if on thumb2 it can be done with a mov.w, mvn or
8629 movw instruction. */
8630 unsigned int newimm;
8631 bfd_boolean isNegated;
8633 newimm = encode_thumb32_immediate (v);
8634 if (newimm != (unsigned int) FAIL)
8638 newimm = encode_thumb32_immediate (~v);
8639 if (newimm != (unsigned int) FAIL)
8643 /* The number can be loaded with a mov.w or mvn
8645 if (newimm != (unsigned int) FAIL
8646 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8648 inst.instruction = (0xf04f0000 /* MOV.W. */
8649 | (inst.operands[i].reg << 8));
8650 /* Change to MOVN. */
8651 inst.instruction |= (isNegated ? 0x200000 : 0);
8652 inst.instruction |= (newimm & 0x800) << 15;
8653 inst.instruction |= (newimm & 0x700) << 4;
8654 inst.instruction |= (newimm & 0x0ff);
8657 /* The number can be loaded with a movw instruction. */
8658 else if ((v & ~0xFFFF) == 0
8659 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8661 int imm = v & 0xFFFF;
8663 inst.instruction = 0xf2400000; /* MOVW. */
8664 inst.instruction |= (inst.operands[i].reg << 8);
8665 inst.instruction |= (imm & 0xf000) << 4;
8666 inst.instruction |= (imm & 0x0800) << 15;
8667 inst.instruction |= (imm & 0x0700) << 4;
8668 inst.instruction |= (imm & 0x00ff);
8675 int value = encode_arm_immediate (v);
8679 /* This can be done with a mov instruction. */
8680 inst.instruction &= LITERAL_MASK;
8681 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8682 inst.instruction |= value & 0xfff;
8686 value = encode_arm_immediate (~ v);
8689 /* This can be done with a mvn instruction. */
8690 inst.instruction &= LITERAL_MASK;
8691 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8692 inst.instruction |= value & 0xfff;
8696 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8699 unsigned immbits = 0;
8700 unsigned immlo = inst.operands[1].imm;
8701 unsigned immhi = inst.operands[1].regisimm
8702 ? inst.operands[1].reg
8703 : inst.relocs[0].exp.X_unsigned
8705 : ((bfd_int64_t)((int) immlo)) >> 32;
8706 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8707 &op, 64, NT_invtype);
8711 neon_invert_size (&immlo, &immhi, 64);
8713 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8714 &op, 64, NT_invtype);
8719 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8725 /* Fill other bits in vmov encoding for both thumb and arm. */
8727 inst.instruction |= (0x7U << 29) | (0xF << 24);
8729 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8730 neon_write_immbits (immbits);
8738 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8739 if (inst.operands[i].issingle
8740 && is_quarter_float (inst.operands[1].imm)
8741 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8743 inst.operands[1].imm =
8744 neon_qfloat_bits (v);
8745 do_vfp_nsyn_opcode ("fconsts");
8749 /* If our host does not support a 64-bit type then we cannot perform
8750 the following optimization. This mean that there will be a
8751 discrepancy between the output produced by an assembler built for
8752 a 32-bit-only host and the output produced from a 64-bit host, but
8753 this cannot be helped. */
8754 #if defined BFD_HOST_64_BIT
8755 else if (!inst.operands[1].issingle
8756 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8758 if (is_double_a_single (v)
8759 && is_quarter_float (double_to_single (v)))
8761 inst.operands[1].imm =
8762 neon_qfloat_bits (double_to_single (v));
8763 do_vfp_nsyn_opcode ("fconstd");
8771 if (add_to_lit_pool ((!inst.operands[i].isvec
8772 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8775 inst.operands[1].reg = REG_PC;
8776 inst.operands[1].isreg = 1;
8777 inst.operands[1].preind = 1;
8778 inst.relocs[0].pc_rel = 1;
8779 inst.relocs[0].type = (thumb_p
8780 ? BFD_RELOC_ARM_THUMB_OFFSET
8782 ? BFD_RELOC_ARM_HWLITERAL
8783 : BFD_RELOC_ARM_LITERAL));
8787 /* inst.operands[i] was set up by parse_address. Encode it into an
8788 ARM-format instruction. Reject all forms which cannot be encoded
8789 into a coprocessor load/store instruction. If wb_ok is false,
8790 reject use of writeback; if unind_ok is false, reject use of
8791 unindexed addressing. If reloc_override is not 0, use it instead
8792 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8793 (in which case it is preserved). */
8796 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8798 if (!inst.operands[i].isreg)
8801 if (! inst.operands[0].isvec)
8803 inst.error = _("invalid co-processor operand");
8806 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8810 inst.instruction |= inst.operands[i].reg << 16;
8812 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8814 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8816 gas_assert (!inst.operands[i].writeback);
8819 inst.error = _("instruction does not support unindexed addressing");
8822 inst.instruction |= inst.operands[i].imm;
8823 inst.instruction |= INDEX_UP;
8827 if (inst.operands[i].preind)
8828 inst.instruction |= PRE_INDEX;
8830 if (inst.operands[i].writeback)
8832 if (inst.operands[i].reg == REG_PC)
8834 inst.error = _("pc may not be used with write-back");
8839 inst.error = _("instruction does not support writeback");
8842 inst.instruction |= WRITE_BACK;
8846 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8847 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8848 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8849 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
8852 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8854 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
8857 /* Prefer + for zero encoded value. */
8858 if (!inst.operands[i].negative)
8859 inst.instruction |= INDEX_UP;
8864 /* Functions for instruction encoding, sorted by sub-architecture.
8865 First some generics; their names are taken from the conventional
8866 bit positions for register arguments in ARM format instructions. */
8876 inst.instruction |= inst.operands[0].reg << 12;
8882 inst.instruction |= inst.operands[0].reg << 16;
8888 inst.instruction |= inst.operands[0].reg << 12;
8889 inst.instruction |= inst.operands[1].reg;
8895 inst.instruction |= inst.operands[0].reg;
8896 inst.instruction |= inst.operands[1].reg << 16;
8902 inst.instruction |= inst.operands[0].reg << 12;
8903 inst.instruction |= inst.operands[1].reg << 16;
8909 inst.instruction |= inst.operands[0].reg << 16;
8910 inst.instruction |= inst.operands[1].reg << 12;
8916 inst.instruction |= inst.operands[0].reg << 8;
8917 inst.instruction |= inst.operands[1].reg << 16;
8921 check_obsolete (const arm_feature_set *feature, const char *msg)
8923 if (ARM_CPU_IS_ANY (cpu_variant))
8925 as_tsktsk ("%s", msg);
8928 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8940 unsigned Rn = inst.operands[2].reg;
8941 /* Enforce restrictions on SWP instruction. */
8942 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8944 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8945 _("Rn must not overlap other operands"));
8947 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8949 if (!check_obsolete (&arm_ext_v8,
8950 _("swp{b} use is obsoleted for ARMv8 and later"))
8951 && warn_on_deprecated
8952 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8953 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8956 inst.instruction |= inst.operands[0].reg << 12;
8957 inst.instruction |= inst.operands[1].reg;
8958 inst.instruction |= Rn << 16;
8964 inst.instruction |= inst.operands[0].reg << 12;
8965 inst.instruction |= inst.operands[1].reg << 16;
8966 inst.instruction |= inst.operands[2].reg;
8972 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8973 constraint (((inst.relocs[0].exp.X_op != O_constant
8974 && inst.relocs[0].exp.X_op != O_illegal)
8975 || inst.relocs[0].exp.X_add_number != 0),
8977 inst.instruction |= inst.operands[0].reg;
8978 inst.instruction |= inst.operands[1].reg << 12;
8979 inst.instruction |= inst.operands[2].reg << 16;
8985 inst.instruction |= inst.operands[0].imm;
8991 inst.instruction |= inst.operands[0].reg << 12;
8992 encode_arm_cp_address (1, TRUE, TRUE, 0);
8995 /* ARM instructions, in alphabetical order by function name (except
8996 that wrapper functions appear immediately after the function they
8999 /* This is a pseudo-op of the form "adr rd, label" to be converted
9000 into a relative address of the form "add rd, pc, #label-.-8". */
9005 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9007 /* Frag hacking will turn this into a sub instruction if the offset turns
9008 out to be negative. */
9009 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9010 inst.relocs[0].pc_rel = 1;
9011 inst.relocs[0].exp.X_add_number -= 8;
9013 if (support_interwork
9014 && inst.relocs[0].exp.X_op == O_symbol
9015 && inst.relocs[0].exp.X_add_symbol != NULL
9016 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9017 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9018 inst.relocs[0].exp.X_add_number |= 1;
9021 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9022 into a relative address of the form:
9023 add rd, pc, #low(label-.-8)"
9024 add rd, rd, #high(label-.-8)" */
9029 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9031 /* Frag hacking will turn this into a sub instruction if the offset turns
9032 out to be negative. */
9033 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9034 inst.relocs[0].pc_rel = 1;
9035 inst.size = INSN_SIZE * 2;
9036 inst.relocs[0].exp.X_add_number -= 8;
9038 if (support_interwork
9039 && inst.relocs[0].exp.X_op == O_symbol
9040 && inst.relocs[0].exp.X_add_symbol != NULL
9041 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9042 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9043 inst.relocs[0].exp.X_add_number |= 1;
9049 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9050 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9052 if (!inst.operands[1].present)
9053 inst.operands[1].reg = inst.operands[0].reg;
9054 inst.instruction |= inst.operands[0].reg << 12;
9055 inst.instruction |= inst.operands[1].reg << 16;
9056 encode_arm_shifter_operand (2);
9062 if (inst.operands[0].present)
9063 inst.instruction |= inst.operands[0].imm;
9065 inst.instruction |= 0xf;
9071 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9072 constraint (msb > 32, _("bit-field extends past end of register"));
9073 /* The instruction encoding stores the LSB and MSB,
9074 not the LSB and width. */
9075 inst.instruction |= inst.operands[0].reg << 12;
9076 inst.instruction |= inst.operands[1].imm << 7;
9077 inst.instruction |= (msb - 1) << 16;
9085 /* #0 in second position is alternative syntax for bfc, which is
9086 the same instruction but with REG_PC in the Rm field. */
9087 if (!inst.operands[1].isreg)
9088 inst.operands[1].reg = REG_PC;
9090 msb = inst.operands[2].imm + inst.operands[3].imm;
9091 constraint (msb > 32, _("bit-field extends past end of register"));
9092 /* The instruction encoding stores the LSB and MSB,
9093 not the LSB and width. */
9094 inst.instruction |= inst.operands[0].reg << 12;
9095 inst.instruction |= inst.operands[1].reg;
9096 inst.instruction |= inst.operands[2].imm << 7;
9097 inst.instruction |= (msb - 1) << 16;
9103 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9104 _("bit-field extends past end of register"));
9105 inst.instruction |= inst.operands[0].reg << 12;
9106 inst.instruction |= inst.operands[1].reg;
9107 inst.instruction |= inst.operands[2].imm << 7;
9108 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9111 /* ARM V5 breakpoint instruction (argument parse)
9112 BKPT <16 bit unsigned immediate>
9113 Instruction is not conditional.
9114 The bit pattern given in insns[] has the COND_ALWAYS condition,
9115 and it is an error if the caller tried to override that. */
9120 /* Top 12 of 16 bits to bits 19:8. */
9121 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9123 /* Bottom 4 of 16 bits to bits 3:0. */
9124 inst.instruction |= inst.operands[0].imm & 0xf;
9128 encode_branch (int default_reloc)
9130 if (inst.operands[0].hasreloc)
9132 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9133 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9134 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9135 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9136 ? BFD_RELOC_ARM_PLT32
9137 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
9140 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9141 inst.relocs[0].pc_rel = 1;
9148 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9149 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9152 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9159 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9161 if (inst.cond == COND_ALWAYS)
9162 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9164 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9168 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9171 /* ARM V5 branch-link-exchange instruction (argument parse)
9172 BLX <target_addr> ie BLX(1)
9173 BLX{<condition>} <Rm> ie BLX(2)
9174 Unfortunately, there are two different opcodes for this mnemonic.
9175 So, the insns[].value is not used, and the code here zaps values
9176 into inst.instruction.
9177 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9182 if (inst.operands[0].isreg)
9184 /* Arg is a register; the opcode provided by insns[] is correct.
9185 It is not illegal to do "blx pc", just useless. */
9186 if (inst.operands[0].reg == REG_PC)
9187 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9189 inst.instruction |= inst.operands[0].reg;
9193 /* Arg is an address; this instruction cannot be executed
9194 conditionally, and the opcode must be adjusted.
9195 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9196 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9197 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9198 inst.instruction = 0xfa000000;
9199 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
9206 bfd_boolean want_reloc;
9208 if (inst.operands[0].reg == REG_PC)
9209 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9211 inst.instruction |= inst.operands[0].reg;
9212 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9213 it is for ARMv4t or earlier. */
9214 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
9215 if (!ARM_FEATURE_ZERO (selected_object_arch)
9216 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
9220 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
9225 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9229 /* ARM v5TEJ. Jump to Jazelle code. */
9234 if (inst.operands[0].reg == REG_PC)
9235 as_tsktsk (_("use of r15 in bxj is not really useful"));
9237 inst.instruction |= inst.operands[0].reg;
9240 /* Co-processor data operation:
9241 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9242 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9246 inst.instruction |= inst.operands[0].reg << 8;
9247 inst.instruction |= inst.operands[1].imm << 20;
9248 inst.instruction |= inst.operands[2].reg << 12;
9249 inst.instruction |= inst.operands[3].reg << 16;
9250 inst.instruction |= inst.operands[4].reg;
9251 inst.instruction |= inst.operands[5].imm << 5;
9257 inst.instruction |= inst.operands[0].reg << 16;
9258 encode_arm_shifter_operand (1);
9261 /* Transfer between coprocessor and ARM registers.
9262 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9267 No special properties. */
9269 struct deprecated_coproc_regs_s
9276 arm_feature_set deprecated;
9277 arm_feature_set obsoleted;
9278 const char *dep_msg;
9279 const char *obs_msg;
9282 #define DEPR_ACCESS_V8 \
9283 N_("This coprocessor register access is deprecated in ARMv8")
9285 /* Table of all deprecated coprocessor registers. */
9286 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9288 {15, 0, 7, 10, 5, /* CP15DMB. */
9289 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9290 DEPR_ACCESS_V8, NULL},
9291 {15, 0, 7, 10, 4, /* CP15DSB. */
9292 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9293 DEPR_ACCESS_V8, NULL},
9294 {15, 0, 7, 5, 4, /* CP15ISB. */
9295 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9296 DEPR_ACCESS_V8, NULL},
9297 {14, 6, 1, 0, 0, /* TEEHBR. */
9298 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9299 DEPR_ACCESS_V8, NULL},
9300 {14, 6, 0, 0, 0, /* TEECR. */
9301 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9302 DEPR_ACCESS_V8, NULL},
9305 #undef DEPR_ACCESS_V8
9307 static const size_t deprecated_coproc_reg_count =
9308 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9316 Rd = inst.operands[2].reg;
9319 if (inst.instruction == 0xee000010
9320 || inst.instruction == 0xfe000010)
9322 reject_bad_reg (Rd);
9323 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9325 constraint (Rd == REG_SP, BAD_SP);
9330 if (inst.instruction == 0xe000010)
9331 constraint (Rd == REG_PC, BAD_PC);
9334 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9336 const struct deprecated_coproc_regs_s *r =
9337 deprecated_coproc_regs + i;
9339 if (inst.operands[0].reg == r->cp
9340 && inst.operands[1].imm == r->opc1
9341 && inst.operands[3].reg == r->crn
9342 && inst.operands[4].reg == r->crm
9343 && inst.operands[5].imm == r->opc2)
9345 if (! ARM_CPU_IS_ANY (cpu_variant)
9346 && warn_on_deprecated
9347 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
9348 as_tsktsk ("%s", r->dep_msg);
9352 inst.instruction |= inst.operands[0].reg << 8;
9353 inst.instruction |= inst.operands[1].imm << 21;
9354 inst.instruction |= Rd << 12;
9355 inst.instruction |= inst.operands[3].reg << 16;
9356 inst.instruction |= inst.operands[4].reg;
9357 inst.instruction |= inst.operands[5].imm << 5;
9360 /* Transfer between coprocessor register and pair of ARM registers.
9361 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9366 Two XScale instructions are special cases of these:
9368 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9369 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9371 Result unpredictable if Rd or Rn is R15. */
9378 Rd = inst.operands[2].reg;
9379 Rn = inst.operands[3].reg;
9383 reject_bad_reg (Rd);
9384 reject_bad_reg (Rn);
9388 constraint (Rd == REG_PC, BAD_PC);
9389 constraint (Rn == REG_PC, BAD_PC);
9392 /* Only check the MRRC{2} variants. */
9393 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9395 /* If Rd == Rn, error that the operation is
9396 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9397 constraint (Rd == Rn, BAD_OVERLAP);
9400 inst.instruction |= inst.operands[0].reg << 8;
9401 inst.instruction |= inst.operands[1].imm << 4;
9402 inst.instruction |= Rd << 12;
9403 inst.instruction |= Rn << 16;
9404 inst.instruction |= inst.operands[4].reg;
9410 inst.instruction |= inst.operands[0].imm << 6;
9411 if (inst.operands[1].present)
9413 inst.instruction |= CPSI_MMOD;
9414 inst.instruction |= inst.operands[1].imm;
9421 inst.instruction |= inst.operands[0].imm;
9427 unsigned Rd, Rn, Rm;
9429 Rd = inst.operands[0].reg;
9430 Rn = (inst.operands[1].present
9431 ? inst.operands[1].reg : Rd);
9432 Rm = inst.operands[2].reg;
9434 constraint ((Rd == REG_PC), BAD_PC);
9435 constraint ((Rn == REG_PC), BAD_PC);
9436 constraint ((Rm == REG_PC), BAD_PC);
9438 inst.instruction |= Rd << 16;
9439 inst.instruction |= Rn << 0;
9440 inst.instruction |= Rm << 8;
9446 /* There is no IT instruction in ARM mode. We
9447 process it to do the validation as if in
9448 thumb mode, just in case the code gets
9449 assembled for thumb using the unified syntax. */
9454 set_pred_insn_type (IT_INSN);
9455 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9456 now_pred.cc = inst.operands[0].imm;
9460 /* If there is only one register in the register list,
9461 then return its register number. Otherwise return -1. */
9463 only_one_reg_in_list (int range)
9465 int i = ffs (range) - 1;
9466 return (i > 15 || range != (1 << i)) ? -1 : i;
9470 encode_ldmstm(int from_push_pop_mnem)
9472 int base_reg = inst.operands[0].reg;
9473 int range = inst.operands[1].imm;
9476 inst.instruction |= base_reg << 16;
9477 inst.instruction |= range;
9479 if (inst.operands[1].writeback)
9480 inst.instruction |= LDM_TYPE_2_OR_3;
9482 if (inst.operands[0].writeback)
9484 inst.instruction |= WRITE_BACK;
9485 /* Check for unpredictable uses of writeback. */
9486 if (inst.instruction & LOAD_BIT)
9488 /* Not allowed in LDM type 2. */
9489 if ((inst.instruction & LDM_TYPE_2_OR_3)
9490 && ((range & (1 << REG_PC)) == 0))
9491 as_warn (_("writeback of base register is UNPREDICTABLE"));
9492 /* Only allowed if base reg not in list for other types. */
9493 else if (range & (1 << base_reg))
9494 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9498 /* Not allowed for type 2. */
9499 if (inst.instruction & LDM_TYPE_2_OR_3)
9500 as_warn (_("writeback of base register is UNPREDICTABLE"));
9501 /* Only allowed if base reg not in list, or first in list. */
9502 else if ((range & (1 << base_reg))
9503 && (range & ((1 << base_reg) - 1)))
9504 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9508 /* If PUSH/POP has only one register, then use the A2 encoding. */
9509 one_reg = only_one_reg_in_list (range);
9510 if (from_push_pop_mnem && one_reg >= 0)
9512 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9514 if (is_push && one_reg == 13 /* SP */)
9515 /* PR 22483: The A2 encoding cannot be used when
9516 pushing the stack pointer as this is UNPREDICTABLE. */
9519 inst.instruction &= A_COND_MASK;
9520 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9521 inst.instruction |= one_reg << 12;
9528 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
9531 /* ARMv5TE load-consecutive (argument parse)
9540 constraint (inst.operands[0].reg % 2 != 0,
9541 _("first transfer register must be even"));
9542 constraint (inst.operands[1].present
9543 && inst.operands[1].reg != inst.operands[0].reg + 1,
9544 _("can only transfer two consecutive registers"));
9545 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9546 constraint (!inst.operands[2].isreg, _("'[' expected"));
9548 if (!inst.operands[1].present)
9549 inst.operands[1].reg = inst.operands[0].reg + 1;
9551 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9552 register and the first register written; we have to diagnose
9553 overlap between the base and the second register written here. */
9555 if (inst.operands[2].reg == inst.operands[1].reg
9556 && (inst.operands[2].writeback || inst.operands[2].postind))
9557 as_warn (_("base register written back, and overlaps "
9558 "second transfer register"));
9560 if (!(inst.instruction & V4_STR_BIT))
9562 /* For an index-register load, the index register must not overlap the
9563 destination (even if not write-back). */
9564 if (inst.operands[2].immisreg
9565 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9566 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9567 as_warn (_("index register overlaps transfer register"));
9569 inst.instruction |= inst.operands[0].reg << 12;
9570 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
9576 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9577 || inst.operands[1].postind || inst.operands[1].writeback
9578 || inst.operands[1].immisreg || inst.operands[1].shifted
9579 || inst.operands[1].negative
9580 /* This can arise if the programmer has written
9582 or if they have mistakenly used a register name as the last
9585 It is very difficult to distinguish between these two cases
9586 because "rX" might actually be a label. ie the register
9587 name has been occluded by a symbol of the same name. So we
9588 just generate a general 'bad addressing mode' type error
9589 message and leave it up to the programmer to discover the
9590 true cause and fix their mistake. */
9591 || (inst.operands[1].reg == REG_PC),
9594 constraint (inst.relocs[0].exp.X_op != O_constant
9595 || inst.relocs[0].exp.X_add_number != 0,
9596 _("offset must be zero in ARM encoding"));
9598 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9600 inst.instruction |= inst.operands[0].reg << 12;
9601 inst.instruction |= inst.operands[1].reg << 16;
9602 inst.relocs[0].type = BFD_RELOC_UNUSED;
9608 constraint (inst.operands[0].reg % 2 != 0,
9609 _("even register required"));
9610 constraint (inst.operands[1].present
9611 && inst.operands[1].reg != inst.operands[0].reg + 1,
9612 _("can only load two consecutive registers"));
9613 /* If op 1 were present and equal to PC, this function wouldn't
9614 have been called in the first place. */
9615 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9617 inst.instruction |= inst.operands[0].reg << 12;
9618 inst.instruction |= inst.operands[2].reg << 16;
9621 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9622 which is not a multiple of four is UNPREDICTABLE. */
9624 check_ldr_r15_aligned (void)
9626 constraint (!(inst.operands[1].immisreg)
9627 && (inst.operands[0].reg == REG_PC
9628 && inst.operands[1].reg == REG_PC
9629 && (inst.relocs[0].exp.X_add_number & 0x3)),
9630 _("ldr to register 15 must be 4-byte aligned"));
9636 inst.instruction |= inst.operands[0].reg << 12;
9637 if (!inst.operands[1].isreg)
9638 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
9640 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
9641 check_ldr_r15_aligned ();
9647 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9649 if (inst.operands[1].preind)
9651 constraint (inst.relocs[0].exp.X_op != O_constant
9652 || inst.relocs[0].exp.X_add_number != 0,
9653 _("this instruction requires a post-indexed address"));
9655 inst.operands[1].preind = 0;
9656 inst.operands[1].postind = 1;
9657 inst.operands[1].writeback = 1;
9659 inst.instruction |= inst.operands[0].reg << 12;
9660 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9663 /* Halfword and signed-byte load/store operations. */
9668 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9669 inst.instruction |= inst.operands[0].reg << 12;
9670 if (!inst.operands[1].isreg)
9671 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
9673 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
9679 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9681 if (inst.operands[1].preind)
9683 constraint (inst.relocs[0].exp.X_op != O_constant
9684 || inst.relocs[0].exp.X_add_number != 0,
9685 _("this instruction requires a post-indexed address"));
9687 inst.operands[1].preind = 0;
9688 inst.operands[1].postind = 1;
9689 inst.operands[1].writeback = 1;
9691 inst.instruction |= inst.operands[0].reg << 12;
9692 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9695 /* Co-processor register load/store.
9696 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9700 inst.instruction |= inst.operands[0].reg << 8;
9701 inst.instruction |= inst.operands[1].reg << 12;
9702 encode_arm_cp_address (2, TRUE, TRUE, 0);
9708 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9709 if (inst.operands[0].reg == inst.operands[1].reg
9710 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
9711 && !(inst.instruction & 0x00400000))
9712 as_tsktsk (_("Rd and Rm should be different in mla"));
9714 inst.instruction |= inst.operands[0].reg << 16;
9715 inst.instruction |= inst.operands[1].reg;
9716 inst.instruction |= inst.operands[2].reg << 8;
9717 inst.instruction |= inst.operands[3].reg << 12;
9723 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9724 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9726 inst.instruction |= inst.operands[0].reg << 12;
9727 encode_arm_shifter_operand (1);
9730 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9737 top = (inst.instruction & 0x00400000) != 0;
9738 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
9739 _(":lower16: not allowed in this instruction"));
9740 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
9741 _(":upper16: not allowed in this instruction"));
9742 inst.instruction |= inst.operands[0].reg << 12;
9743 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
9745 imm = inst.relocs[0].exp.X_add_number;
9746 /* The value is in two pieces: 0:11, 16:19. */
9747 inst.instruction |= (imm & 0x00000fff);
9748 inst.instruction |= (imm & 0x0000f000) << 4;
9753 do_vfp_nsyn_mrs (void)
9755 if (inst.operands[0].isvec)
9757 if (inst.operands[1].reg != 1)
9758 first_error (_("operand 1 must be FPSCR"));
9759 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9760 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9761 do_vfp_nsyn_opcode ("fmstat");
9763 else if (inst.operands[1].isvec)
9764 do_vfp_nsyn_opcode ("fmrx");
9772 do_vfp_nsyn_msr (void)
9774 if (inst.operands[0].isvec)
9775 do_vfp_nsyn_opcode ("fmxr");
9785 unsigned Rt = inst.operands[0].reg;
9787 if (thumb_mode && Rt == REG_SP)
9789 inst.error = BAD_SP;
9793 /* MVFR2 is only valid at ARMv8-A. */
9794 if (inst.operands[1].reg == 5)
9795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9798 /* APSR_ sets isvec. All other refs to PC are illegal. */
9799 if (!inst.operands[0].isvec && Rt == REG_PC)
9801 inst.error = BAD_PC;
9805 /* If we get through parsing the register name, we just insert the number
9806 generated into the instruction without further validation. */
9807 inst.instruction |= (inst.operands[1].reg << 16);
9808 inst.instruction |= (Rt << 12);
9814 unsigned Rt = inst.operands[1].reg;
9817 reject_bad_reg (Rt);
9818 else if (Rt == REG_PC)
9820 inst.error = BAD_PC;
9824 /* MVFR2 is only valid for ARMv8-A. */
9825 if (inst.operands[0].reg == 5)
9826 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9829 /* If we get through parsing the register name, we just insert the number
9830 generated into the instruction without further validation. */
9831 inst.instruction |= (inst.operands[0].reg << 16);
9832 inst.instruction |= (Rt << 12);
9840 if (do_vfp_nsyn_mrs () == SUCCESS)
9843 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9844 inst.instruction |= inst.operands[0].reg << 12;
9846 if (inst.operands[1].isreg)
9848 br = inst.operands[1].reg;
9849 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
9850 as_bad (_("bad register for mrs"));
9854 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9855 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9857 _("'APSR', 'CPSR' or 'SPSR' expected"));
9858 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9861 inst.instruction |= br;
9864 /* Two possible forms:
9865 "{C|S}PSR_<field>, Rm",
9866 "{C|S}PSR_f, #expression". */
9871 if (do_vfp_nsyn_msr () == SUCCESS)
9874 inst.instruction |= inst.operands[0].imm;
9875 if (inst.operands[1].isreg)
9876 inst.instruction |= inst.operands[1].reg;
9879 inst.instruction |= INST_IMMEDIATE;
9880 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9881 inst.relocs[0].pc_rel = 0;
9888 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9890 if (!inst.operands[2].present)
9891 inst.operands[2].reg = inst.operands[0].reg;
9892 inst.instruction |= inst.operands[0].reg << 16;
9893 inst.instruction |= inst.operands[1].reg;
9894 inst.instruction |= inst.operands[2].reg << 8;
9896 if (inst.operands[0].reg == inst.operands[1].reg
9897 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9898 as_tsktsk (_("Rd and Rm should be different in mul"));
9901 /* Long Multiply Parser
9902 UMULL RdLo, RdHi, Rm, Rs
9903 SMULL RdLo, RdHi, Rm, Rs
9904 UMLAL RdLo, RdHi, Rm, Rs
9905 SMLAL RdLo, RdHi, Rm, Rs. */
9910 inst.instruction |= inst.operands[0].reg << 12;
9911 inst.instruction |= inst.operands[1].reg << 16;
9912 inst.instruction |= inst.operands[2].reg;
9913 inst.instruction |= inst.operands[3].reg << 8;
9915 /* rdhi and rdlo must be different. */
9916 if (inst.operands[0].reg == inst.operands[1].reg)
9917 as_tsktsk (_("rdhi and rdlo must be different"));
9919 /* rdhi, rdlo and rm must all be different before armv6. */
9920 if ((inst.operands[0].reg == inst.operands[2].reg
9921 || inst.operands[1].reg == inst.operands[2].reg)
9922 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9923 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9929 if (inst.operands[0].present
9930 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9932 /* Architectural NOP hints are CPSR sets with no bits selected. */
9933 inst.instruction &= 0xf0000000;
9934 inst.instruction |= 0x0320f000;
9935 if (inst.operands[0].present)
9936 inst.instruction |= inst.operands[0].imm;
9940 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9941 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9942 Condition defaults to COND_ALWAYS.
9943 Error if Rd, Rn or Rm are R15. */
9948 inst.instruction |= inst.operands[0].reg << 12;
9949 inst.instruction |= inst.operands[1].reg << 16;
9950 inst.instruction |= inst.operands[2].reg;
9951 if (inst.operands[3].present)
9952 encode_arm_shift (3);
9955 /* ARM V6 PKHTB (Argument Parse). */
9960 if (!inst.operands[3].present)
9962 /* If the shift specifier is omitted, turn the instruction
9963 into pkhbt rd, rm, rn. */
9964 inst.instruction &= 0xfff00010;
9965 inst.instruction |= inst.operands[0].reg << 12;
9966 inst.instruction |= inst.operands[1].reg;
9967 inst.instruction |= inst.operands[2].reg << 16;
9971 inst.instruction |= inst.operands[0].reg << 12;
9972 inst.instruction |= inst.operands[1].reg << 16;
9973 inst.instruction |= inst.operands[2].reg;
9974 encode_arm_shift (3);
9978 /* ARMv5TE: Preload-Cache
9979 MP Extensions: Preload for write
9983 Syntactically, like LDR with B=1, W=0, L=1. */
9988 constraint (!inst.operands[0].isreg,
9989 _("'[' expected after PLD mnemonic"));
9990 constraint (inst.operands[0].postind,
9991 _("post-indexed expression used in preload instruction"));
9992 constraint (inst.operands[0].writeback,
9993 _("writeback used in preload instruction"));
9994 constraint (!inst.operands[0].preind,
9995 _("unindexed addressing used in preload instruction"));
9996 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9999 /* ARMv7: PLI <addr_mode> */
10003 constraint (!inst.operands[0].isreg,
10004 _("'[' expected after PLI mnemonic"));
10005 constraint (inst.operands[0].postind,
10006 _("post-indexed expression used in preload instruction"));
10007 constraint (inst.operands[0].writeback,
10008 _("writeback used in preload instruction"));
10009 constraint (!inst.operands[0].preind,
10010 _("unindexed addressing used in preload instruction"));
10011 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10012 inst.instruction &= ~PRE_INDEX;
10018 constraint (inst.operands[0].writeback,
10019 _("push/pop do not support {reglist}^"));
10020 inst.operands[1] = inst.operands[0];
10021 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10022 inst.operands[0].isreg = 1;
10023 inst.operands[0].writeback = 1;
10024 inst.operands[0].reg = REG_SP;
10025 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
10028 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10029 word at the specified address and the following word
10031 Unconditionally executed.
10032 Error if Rn is R15. */
10037 inst.instruction |= inst.operands[0].reg << 16;
10038 if (inst.operands[0].writeback)
10039 inst.instruction |= WRITE_BACK;
10042 /* ARM V6 ssat (argument parse). */
10047 inst.instruction |= inst.operands[0].reg << 12;
10048 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10049 inst.instruction |= inst.operands[2].reg;
10051 if (inst.operands[3].present)
10052 encode_arm_shift (3);
10055 /* ARM V6 usat (argument parse). */
10060 inst.instruction |= inst.operands[0].reg << 12;
10061 inst.instruction |= inst.operands[1].imm << 16;
10062 inst.instruction |= inst.operands[2].reg;
10064 if (inst.operands[3].present)
10065 encode_arm_shift (3);
10068 /* ARM V6 ssat16 (argument parse). */
10073 inst.instruction |= inst.operands[0].reg << 12;
10074 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10075 inst.instruction |= inst.operands[2].reg;
10081 inst.instruction |= inst.operands[0].reg << 12;
10082 inst.instruction |= inst.operands[1].imm << 16;
10083 inst.instruction |= inst.operands[2].reg;
10086 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10087 preserving the other bits.
10089 setend <endian_specifier>, where <endian_specifier> is either
10095 if (warn_on_deprecated
10096 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10097 as_tsktsk (_("setend use is deprecated for ARMv8"));
10099 if (inst.operands[0].imm)
10100 inst.instruction |= 0x200;
10106 unsigned int Rm = (inst.operands[1].present
10107 ? inst.operands[1].reg
10108 : inst.operands[0].reg);
10110 inst.instruction |= inst.operands[0].reg << 12;
10111 inst.instruction |= Rm;
10112 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10114 inst.instruction |= inst.operands[2].reg << 8;
10115 inst.instruction |= SHIFT_BY_REG;
10116 /* PR 12854: Error on extraneous shifts. */
10117 constraint (inst.operands[2].shifted,
10118 _("extraneous shift as part of operand to shift insn"));
10121 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10127 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10128 inst.relocs[0].pc_rel = 0;
10134 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10135 inst.relocs[0].pc_rel = 0;
10141 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10142 inst.relocs[0].pc_rel = 0;
10148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10149 _("selected processor does not support SETPAN instruction"));
10151 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10157 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10158 _("selected processor does not support SETPAN instruction"));
10160 inst.instruction |= (inst.operands[0].imm << 3);
10163 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10164 SMLAxy{cond} Rd,Rm,Rs,Rn
10165 SMLAWy{cond} Rd,Rm,Rs,Rn
10166 Error if any register is R15. */
10171 inst.instruction |= inst.operands[0].reg << 16;
10172 inst.instruction |= inst.operands[1].reg;
10173 inst.instruction |= inst.operands[2].reg << 8;
10174 inst.instruction |= inst.operands[3].reg << 12;
10177 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10178 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10179 Error if any register is R15.
10180 Warning if Rdlo == Rdhi. */
10185 inst.instruction |= inst.operands[0].reg << 12;
10186 inst.instruction |= inst.operands[1].reg << 16;
10187 inst.instruction |= inst.operands[2].reg;
10188 inst.instruction |= inst.operands[3].reg << 8;
10190 if (inst.operands[0].reg == inst.operands[1].reg)
10191 as_tsktsk (_("rdhi and rdlo must be different"));
10194 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10195 SMULxy{cond} Rd,Rm,Rs
10196 Error if any register is R15. */
10201 inst.instruction |= inst.operands[0].reg << 16;
10202 inst.instruction |= inst.operands[1].reg;
10203 inst.instruction |= inst.operands[2].reg << 8;
10206 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10207 the same for both ARM and Thumb-2. */
10214 if (inst.operands[0].present)
10216 reg = inst.operands[0].reg;
10217 constraint (reg != REG_SP, _("SRS base register must be r13"));
10222 inst.instruction |= reg << 16;
10223 inst.instruction |= inst.operands[1].imm;
10224 if (inst.operands[0].writeback || inst.operands[1].writeback)
10225 inst.instruction |= WRITE_BACK;
10228 /* ARM V6 strex (argument parse). */
10233 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10234 || inst.operands[2].postind || inst.operands[2].writeback
10235 || inst.operands[2].immisreg || inst.operands[2].shifted
10236 || inst.operands[2].negative
10237 /* See comment in do_ldrex(). */
10238 || (inst.operands[2].reg == REG_PC),
10241 constraint (inst.operands[0].reg == inst.operands[1].reg
10242 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10244 constraint (inst.relocs[0].exp.X_op != O_constant
10245 || inst.relocs[0].exp.X_add_number != 0,
10246 _("offset must be zero in ARM encoding"));
10248 inst.instruction |= inst.operands[0].reg << 12;
10249 inst.instruction |= inst.operands[1].reg;
10250 inst.instruction |= inst.operands[2].reg << 16;
10251 inst.relocs[0].type = BFD_RELOC_UNUSED;
10255 do_t_strexbh (void)
10257 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10258 || inst.operands[2].postind || inst.operands[2].writeback
10259 || inst.operands[2].immisreg || inst.operands[2].shifted
10260 || inst.operands[2].negative,
10263 constraint (inst.operands[0].reg == inst.operands[1].reg
10264 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10272 constraint (inst.operands[1].reg % 2 != 0,
10273 _("even register required"));
10274 constraint (inst.operands[2].present
10275 && inst.operands[2].reg != inst.operands[1].reg + 1,
10276 _("can only store two consecutive registers"));
10277 /* If op 2 were present and equal to PC, this function wouldn't
10278 have been called in the first place. */
10279 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10281 constraint (inst.operands[0].reg == inst.operands[1].reg
10282 || inst.operands[0].reg == inst.operands[1].reg + 1
10283 || inst.operands[0].reg == inst.operands[3].reg,
10286 inst.instruction |= inst.operands[0].reg << 12;
10287 inst.instruction |= inst.operands[1].reg;
10288 inst.instruction |= inst.operands[3].reg << 16;
10295 constraint (inst.operands[0].reg == inst.operands[1].reg
10296 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10304 constraint (inst.operands[0].reg == inst.operands[1].reg
10305 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10310 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10311 extends it to 32-bits, and adds the result to a value in another
10312 register. You can specify a rotation by 0, 8, 16, or 24 bits
10313 before extracting the 16-bit value.
10314 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10315 Condition defaults to COND_ALWAYS.
10316 Error if any register uses R15. */
10321 inst.instruction |= inst.operands[0].reg << 12;
10322 inst.instruction |= inst.operands[1].reg << 16;
10323 inst.instruction |= inst.operands[2].reg;
10324 inst.instruction |= inst.operands[3].imm << 10;
10329 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10330 Condition defaults to COND_ALWAYS.
10331 Error if any register uses R15. */
10336 inst.instruction |= inst.operands[0].reg << 12;
10337 inst.instruction |= inst.operands[1].reg;
10338 inst.instruction |= inst.operands[2].imm << 10;
10341 /* VFP instructions. In a logical order: SP variant first, monad
10342 before dyad, arithmetic then move then load/store. */
10345 do_vfp_sp_monadic (void)
10347 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10348 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10351 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10352 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10356 do_vfp_sp_dyadic (void)
10358 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10359 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10360 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10364 do_vfp_sp_compare_z (void)
10366 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10370 do_vfp_dp_sp_cvt (void)
10372 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10373 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10377 do_vfp_sp_dp_cvt (void)
10379 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10380 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10384 do_vfp_reg_from_sp (void)
10386 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10387 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10390 inst.instruction |= inst.operands[0].reg << 12;
10391 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10395 do_vfp_reg2_from_sp2 (void)
10397 constraint (inst.operands[2].imm != 2,
10398 _("only two consecutive VFP SP registers allowed here"));
10399 inst.instruction |= inst.operands[0].reg << 12;
10400 inst.instruction |= inst.operands[1].reg << 16;
10401 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10405 do_vfp_sp_from_reg (void)
10407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10408 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10411 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10412 inst.instruction |= inst.operands[1].reg << 12;
10416 do_vfp_sp2_from_reg2 (void)
10418 constraint (inst.operands[0].imm != 2,
10419 _("only two consecutive VFP SP registers allowed here"));
10420 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10421 inst.instruction |= inst.operands[1].reg << 12;
10422 inst.instruction |= inst.operands[2].reg << 16;
10426 do_vfp_sp_ldst (void)
10428 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10429 encode_arm_cp_address (1, FALSE, TRUE, 0);
10433 do_vfp_dp_ldst (void)
10435 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10436 encode_arm_cp_address (1, FALSE, TRUE, 0);
10441 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
10443 if (inst.operands[0].writeback)
10444 inst.instruction |= WRITE_BACK;
10446 constraint (ldstm_type != VFP_LDSTMIA,
10447 _("this addressing mode requires base-register writeback"));
10448 inst.instruction |= inst.operands[0].reg << 16;
10449 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10450 inst.instruction |= inst.operands[1].imm;
10454 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
10458 if (inst.operands[0].writeback)
10459 inst.instruction |= WRITE_BACK;
10461 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10462 _("this addressing mode requires base-register writeback"));
10464 inst.instruction |= inst.operands[0].reg << 16;
10465 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10467 count = inst.operands[1].imm << 1;
10468 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10471 inst.instruction |= count;
10475 do_vfp_sp_ldstmia (void)
10477 vfp_sp_ldstm (VFP_LDSTMIA);
10481 do_vfp_sp_ldstmdb (void)
10483 vfp_sp_ldstm (VFP_LDSTMDB);
10487 do_vfp_dp_ldstmia (void)
10489 vfp_dp_ldstm (VFP_LDSTMIA);
10493 do_vfp_dp_ldstmdb (void)
10495 vfp_dp_ldstm (VFP_LDSTMDB);
10499 do_vfp_xp_ldstmia (void)
10501 vfp_dp_ldstm (VFP_LDSTMIAX);
10505 do_vfp_xp_ldstmdb (void)
10507 vfp_dp_ldstm (VFP_LDSTMDBX);
10511 do_vfp_dp_rd_rm (void)
10513 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10514 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10517 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10518 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10522 do_vfp_dp_rn_rd (void)
10524 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10525 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10529 do_vfp_dp_rd_rn (void)
10531 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10532 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10536 do_vfp_dp_rd_rn_rm (void)
10538 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10539 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10542 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10543 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10544 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10548 do_vfp_dp_rd (void)
10550 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10554 do_vfp_dp_rm_rd_rn (void)
10556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10557 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10560 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10561 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10562 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10565 /* VFPv3 instructions. */
10567 do_vfp_sp_const (void)
10569 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10570 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10571 inst.instruction |= (inst.operands[1].imm & 0x0f);
10575 do_vfp_dp_const (void)
10577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10578 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10579 inst.instruction |= (inst.operands[1].imm & 0x0f);
10583 vfp_conv (int srcsize)
10585 int immbits = srcsize - inst.operands[1].imm;
10587 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10589 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10590 i.e. immbits must be in range 0 - 16. */
10591 inst.error = _("immediate value out of range, expected range [0, 16]");
10594 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
10596 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10597 i.e. immbits must be in range 0 - 31. */
10598 inst.error = _("immediate value out of range, expected range [1, 32]");
10602 inst.instruction |= (immbits & 1) << 5;
10603 inst.instruction |= (immbits >> 1);
10607 do_vfp_sp_conv_16 (void)
10609 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10614 do_vfp_dp_conv_16 (void)
10616 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10621 do_vfp_sp_conv_32 (void)
10623 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10628 do_vfp_dp_conv_32 (void)
10630 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10634 /* FPA instructions. Also in a logical order. */
10639 inst.instruction |= inst.operands[0].reg << 16;
10640 inst.instruction |= inst.operands[1].reg;
10644 do_fpa_ldmstm (void)
10646 inst.instruction |= inst.operands[0].reg << 12;
10647 switch (inst.operands[1].imm)
10649 case 1: inst.instruction |= CP_T_X; break;
10650 case 2: inst.instruction |= CP_T_Y; break;
10651 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10656 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10658 /* The instruction specified "ea" or "fd", so we can only accept
10659 [Rn]{!}. The instruction does not really support stacking or
10660 unstacking, so we have to emulate these by setting appropriate
10661 bits and offsets. */
10662 constraint (inst.relocs[0].exp.X_op != O_constant
10663 || inst.relocs[0].exp.X_add_number != 0,
10664 _("this instruction does not support indexing"));
10666 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
10667 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
10669 if (!(inst.instruction & INDEX_UP))
10670 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
10672 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10674 inst.operands[2].preind = 0;
10675 inst.operands[2].postind = 1;
10679 encode_arm_cp_address (2, TRUE, TRUE, 0);
10682 /* iWMMXt instructions: strictly in alphabetical order. */
10685 do_iwmmxt_tandorc (void)
10687 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10691 do_iwmmxt_textrc (void)
10693 inst.instruction |= inst.operands[0].reg << 12;
10694 inst.instruction |= inst.operands[1].imm;
10698 do_iwmmxt_textrm (void)
10700 inst.instruction |= inst.operands[0].reg << 12;
10701 inst.instruction |= inst.operands[1].reg << 16;
10702 inst.instruction |= inst.operands[2].imm;
10706 do_iwmmxt_tinsr (void)
10708 inst.instruction |= inst.operands[0].reg << 16;
10709 inst.instruction |= inst.operands[1].reg << 12;
10710 inst.instruction |= inst.operands[2].imm;
10714 do_iwmmxt_tmia (void)
10716 inst.instruction |= inst.operands[0].reg << 5;
10717 inst.instruction |= inst.operands[1].reg;
10718 inst.instruction |= inst.operands[2].reg << 12;
10722 do_iwmmxt_waligni (void)
10724 inst.instruction |= inst.operands[0].reg << 12;
10725 inst.instruction |= inst.operands[1].reg << 16;
10726 inst.instruction |= inst.operands[2].reg;
10727 inst.instruction |= inst.operands[3].imm << 20;
10731 do_iwmmxt_wmerge (void)
10733 inst.instruction |= inst.operands[0].reg << 12;
10734 inst.instruction |= inst.operands[1].reg << 16;
10735 inst.instruction |= inst.operands[2].reg;
10736 inst.instruction |= inst.operands[3].imm << 21;
10740 do_iwmmxt_wmov (void)
10742 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10743 inst.instruction |= inst.operands[0].reg << 12;
10744 inst.instruction |= inst.operands[1].reg << 16;
10745 inst.instruction |= inst.operands[1].reg;
10749 do_iwmmxt_wldstbh (void)
10752 inst.instruction |= inst.operands[0].reg << 12;
10754 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10756 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10757 encode_arm_cp_address (1, TRUE, FALSE, reloc);
10761 do_iwmmxt_wldstw (void)
10763 /* RIWR_RIWC clears .isreg for a control register. */
10764 if (!inst.operands[0].isreg)
10766 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10767 inst.instruction |= 0xf0000000;
10770 inst.instruction |= inst.operands[0].reg << 12;
10771 encode_arm_cp_address (1, TRUE, TRUE, 0);
10775 do_iwmmxt_wldstd (void)
10777 inst.instruction |= inst.operands[0].reg << 12;
10778 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10779 && inst.operands[1].immisreg)
10781 inst.instruction &= ~0x1a000ff;
10782 inst.instruction |= (0xfU << 28);
10783 if (inst.operands[1].preind)
10784 inst.instruction |= PRE_INDEX;
10785 if (!inst.operands[1].negative)
10786 inst.instruction |= INDEX_UP;
10787 if (inst.operands[1].writeback)
10788 inst.instruction |= WRITE_BACK;
10789 inst.instruction |= inst.operands[1].reg << 16;
10790 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
10791 inst.instruction |= inst.operands[1].imm;
10794 encode_arm_cp_address (1, TRUE, FALSE, 0);
10798 do_iwmmxt_wshufh (void)
10800 inst.instruction |= inst.operands[0].reg << 12;
10801 inst.instruction |= inst.operands[1].reg << 16;
10802 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10803 inst.instruction |= (inst.operands[2].imm & 0x0f);
10807 do_iwmmxt_wzero (void)
10809 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10810 inst.instruction |= inst.operands[0].reg;
10811 inst.instruction |= inst.operands[0].reg << 12;
10812 inst.instruction |= inst.operands[0].reg << 16;
10816 do_iwmmxt_wrwrwr_or_imm5 (void)
10818 if (inst.operands[2].isreg)
10821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10822 _("immediate operand requires iWMMXt2"));
10824 if (inst.operands[2].imm == 0)
10826 switch ((inst.instruction >> 20) & 0xf)
10832 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10833 inst.operands[2].imm = 16;
10834 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10840 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10841 inst.operands[2].imm = 32;
10842 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10849 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10851 wrn = (inst.instruction >> 16) & 0xf;
10852 inst.instruction &= 0xff0fff0f;
10853 inst.instruction |= wrn;
10854 /* Bail out here; the instruction is now assembled. */
10859 /* Map 32 -> 0, etc. */
10860 inst.operands[2].imm &= 0x1f;
10861 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10865 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10866 operations first, then control, shift, and load/store. */
10868 /* Insns like "foo X,Y,Z". */
10871 do_mav_triple (void)
10873 inst.instruction |= inst.operands[0].reg << 16;
10874 inst.instruction |= inst.operands[1].reg;
10875 inst.instruction |= inst.operands[2].reg << 12;
10878 /* Insns like "foo W,X,Y,Z".
10879 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10884 inst.instruction |= inst.operands[0].reg << 5;
10885 inst.instruction |= inst.operands[1].reg << 12;
10886 inst.instruction |= inst.operands[2].reg << 16;
10887 inst.instruction |= inst.operands[3].reg;
10890 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10892 do_mav_dspsc (void)
10894 inst.instruction |= inst.operands[1].reg << 12;
10897 /* Maverick shift immediate instructions.
10898 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10899 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10902 do_mav_shift (void)
10904 int imm = inst.operands[2].imm;
10906 inst.instruction |= inst.operands[0].reg << 12;
10907 inst.instruction |= inst.operands[1].reg << 16;
10909 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10910 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10911 Bit 4 should be 0. */
10912 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10914 inst.instruction |= imm;
10917 /* XScale instructions. Also sorted arithmetic before move. */
10919 /* Xscale multiply-accumulate (argument parse)
10922 MIAxycc acc0,Rm,Rs. */
10927 inst.instruction |= inst.operands[1].reg;
10928 inst.instruction |= inst.operands[2].reg << 12;
10931 /* Xscale move-accumulator-register (argument parse)
10933 MARcc acc0,RdLo,RdHi. */
10938 inst.instruction |= inst.operands[1].reg << 12;
10939 inst.instruction |= inst.operands[2].reg << 16;
10942 /* Xscale move-register-accumulator (argument parse)
10944 MRAcc RdLo,RdHi,acc0. */
10949 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10950 inst.instruction |= inst.operands[0].reg << 12;
10951 inst.instruction |= inst.operands[1].reg << 16;
10954 /* Encoding functions relevant only to Thumb. */
10956 /* inst.operands[i] is a shifted-register operand; encode
10957 it into inst.instruction in the format used by Thumb32. */
10960 encode_thumb32_shifted_operand (int i)
10962 unsigned int value = inst.relocs[0].exp.X_add_number;
10963 unsigned int shift = inst.operands[i].shift_kind;
10965 constraint (inst.operands[i].immisreg,
10966 _("shift by register not allowed in thumb mode"));
10967 inst.instruction |= inst.operands[i].reg;
10968 if (shift == SHIFT_RRX)
10969 inst.instruction |= SHIFT_ROR << 4;
10972 constraint (inst.relocs[0].exp.X_op != O_constant,
10973 _("expression too complex"));
10975 constraint (value > 32
10976 || (value == 32 && (shift == SHIFT_LSL
10977 || shift == SHIFT_ROR)),
10978 _("shift expression is too large"));
10982 else if (value == 32)
10985 inst.instruction |= shift << 4;
10986 inst.instruction |= (value & 0x1c) << 10;
10987 inst.instruction |= (value & 0x03) << 6;
10992 /* inst.operands[i] was set up by parse_address. Encode it into a
10993 Thumb32 format load or store instruction. Reject forms that cannot
10994 be used with such instructions. If is_t is true, reject forms that
10995 cannot be used with a T instruction; if is_d is true, reject forms
10996 that cannot be used with a D instruction. If it is a store insn,
10997 reject PC in Rn. */
11000 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11002 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
11004 constraint (!inst.operands[i].isreg,
11005 _("Instruction does not support =N addresses"));
11007 inst.instruction |= inst.operands[i].reg << 16;
11008 if (inst.operands[i].immisreg)
11010 constraint (is_pc, BAD_PC_ADDRESSING);
11011 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11012 constraint (inst.operands[i].negative,
11013 _("Thumb does not support negative register indexing"));
11014 constraint (inst.operands[i].postind,
11015 _("Thumb does not support register post-indexing"));
11016 constraint (inst.operands[i].writeback,
11017 _("Thumb does not support register indexing with writeback"));
11018 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11019 _("Thumb supports only LSL in shifted register indexing"));
11021 inst.instruction |= inst.operands[i].imm;
11022 if (inst.operands[i].shifted)
11024 constraint (inst.relocs[0].exp.X_op != O_constant,
11025 _("expression too complex"));
11026 constraint (inst.relocs[0].exp.X_add_number < 0
11027 || inst.relocs[0].exp.X_add_number > 3,
11028 _("shift out of range"));
11029 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11031 inst.relocs[0].type = BFD_RELOC_UNUSED;
11033 else if (inst.operands[i].preind)
11035 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11036 constraint (is_t && inst.operands[i].writeback,
11037 _("cannot use writeback with this instruction"));
11038 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11039 BAD_PC_ADDRESSING);
11043 inst.instruction |= 0x01000000;
11044 if (inst.operands[i].writeback)
11045 inst.instruction |= 0x00200000;
11049 inst.instruction |= 0x00000c00;
11050 if (inst.operands[i].writeback)
11051 inst.instruction |= 0x00000100;
11053 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11055 else if (inst.operands[i].postind)
11057 gas_assert (inst.operands[i].writeback);
11058 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11059 constraint (is_t, _("cannot use post-indexing with this instruction"));
11062 inst.instruction |= 0x00200000;
11064 inst.instruction |= 0x00000900;
11065 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11067 else /* unindexed - only for coprocessor */
11068 inst.error = _("instruction does not accept unindexed addressing");
11071 /* Table of Thumb instructions which exist in both 16- and 32-bit
11072 encodings (the latter only in post-V6T2 cores). The index is the
11073 value used in the insns table below. When there is more than one
11074 possible 16-bit encoding for the instruction, this table always
11076 Also contains several pseudo-instructions used during relaxation. */
11077 #define T16_32_TAB \
11078 X(_adc, 4140, eb400000), \
11079 X(_adcs, 4140, eb500000), \
11080 X(_add, 1c00, eb000000), \
11081 X(_adds, 1c00, eb100000), \
11082 X(_addi, 0000, f1000000), \
11083 X(_addis, 0000, f1100000), \
11084 X(_add_pc,000f, f20f0000), \
11085 X(_add_sp,000d, f10d0000), \
11086 X(_adr, 000f, f20f0000), \
11087 X(_and, 4000, ea000000), \
11088 X(_ands, 4000, ea100000), \
11089 X(_asr, 1000, fa40f000), \
11090 X(_asrs, 1000, fa50f000), \
11091 X(_b, e000, f000b000), \
11092 X(_bcond, d000, f0008000), \
11093 X(_bf, 0000, f040e001), \
11094 X(_bfcsel,0000, f000e001), \
11095 X(_bfx, 0000, f060e001), \
11096 X(_bfl, 0000, f000c001), \
11097 X(_bflx, 0000, f070e001), \
11098 X(_bic, 4380, ea200000), \
11099 X(_bics, 4380, ea300000), \
11100 X(_cmn, 42c0, eb100f00), \
11101 X(_cmp, 2800, ebb00f00), \
11102 X(_cpsie, b660, f3af8400), \
11103 X(_cpsid, b670, f3af8600), \
11104 X(_cpy, 4600, ea4f0000), \
11105 X(_dec_sp,80dd, f1ad0d00), \
11106 X(_dls, 0000, f040e001), \
11107 X(_eor, 4040, ea800000), \
11108 X(_eors, 4040, ea900000), \
11109 X(_inc_sp,00dd, f10d0d00), \
11110 X(_ldmia, c800, e8900000), \
11111 X(_ldr, 6800, f8500000), \
11112 X(_ldrb, 7800, f8100000), \
11113 X(_ldrh, 8800, f8300000), \
11114 X(_ldrsb, 5600, f9100000), \
11115 X(_ldrsh, 5e00, f9300000), \
11116 X(_ldr_pc,4800, f85f0000), \
11117 X(_ldr_pc2,4800, f85f0000), \
11118 X(_ldr_sp,9800, f85d0000), \
11119 X(_le, 0000, f00fc001), \
11120 X(_lsl, 0000, fa00f000), \
11121 X(_lsls, 0000, fa10f000), \
11122 X(_lsr, 0800, fa20f000), \
11123 X(_lsrs, 0800, fa30f000), \
11124 X(_mov, 2000, ea4f0000), \
11125 X(_movs, 2000, ea5f0000), \
11126 X(_mul, 4340, fb00f000), \
11127 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11128 X(_mvn, 43c0, ea6f0000), \
11129 X(_mvns, 43c0, ea7f0000), \
11130 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11131 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11132 X(_orr, 4300, ea400000), \
11133 X(_orrs, 4300, ea500000), \
11134 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11135 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11136 X(_rev, ba00, fa90f080), \
11137 X(_rev16, ba40, fa90f090), \
11138 X(_revsh, bac0, fa90f0b0), \
11139 X(_ror, 41c0, fa60f000), \
11140 X(_rors, 41c0, fa70f000), \
11141 X(_sbc, 4180, eb600000), \
11142 X(_sbcs, 4180, eb700000), \
11143 X(_stmia, c000, e8800000), \
11144 X(_str, 6000, f8400000), \
11145 X(_strb, 7000, f8000000), \
11146 X(_strh, 8000, f8200000), \
11147 X(_str_sp,9000, f84d0000), \
11148 X(_sub, 1e00, eba00000), \
11149 X(_subs, 1e00, ebb00000), \
11150 X(_subi, 8000, f1a00000), \
11151 X(_subis, 8000, f1b00000), \
11152 X(_sxtb, b240, fa4ff080), \
11153 X(_sxth, b200, fa0ff080), \
11154 X(_tst, 4200, ea100f00), \
11155 X(_uxtb, b2c0, fa5ff080), \
11156 X(_uxth, b280, fa1ff080), \
11157 X(_nop, bf00, f3af8000), \
11158 X(_yield, bf10, f3af8001), \
11159 X(_wfe, bf20, f3af8002), \
11160 X(_wfi, bf30, f3af8003), \
11161 X(_wls, 0000, f040c001), \
11162 X(_sev, bf40, f3af8004), \
11163 X(_sevl, bf50, f3af8005), \
11164 X(_udf, de00, f7f0a000)
11166 /* To catch errors in encoding functions, the codes are all offset by
11167 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11168 as 16-bit instructions. */
11169 #define X(a,b,c) T_MNEM##a
11170 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11173 #define X(a,b,c) 0x##b
11174 static const unsigned short thumb_op16[] = { T16_32_TAB };
11175 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11178 #define X(a,b,c) 0x##c
11179 static const unsigned int thumb_op32[] = { T16_32_TAB };
11180 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11181 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11185 /* Thumb instruction encoders, in alphabetical order. */
11187 /* ADDW or SUBW. */
11190 do_t_add_sub_w (void)
11194 Rd = inst.operands[0].reg;
11195 Rn = inst.operands[1].reg;
11197 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11198 is the SP-{plus,minus}-immediate form of the instruction. */
11200 constraint (Rd == REG_PC, BAD_PC);
11202 reject_bad_reg (Rd);
11204 inst.instruction |= (Rn << 16) | (Rd << 8);
11205 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11208 /* Parse an add or subtract instruction. We get here with inst.instruction
11209 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11212 do_t_add_sub (void)
11216 Rd = inst.operands[0].reg;
11217 Rs = (inst.operands[1].present
11218 ? inst.operands[1].reg /* Rd, Rs, foo */
11219 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11222 set_pred_insn_type_last ();
11224 if (unified_syntax)
11227 bfd_boolean narrow;
11230 flags = (inst.instruction == T_MNEM_adds
11231 || inst.instruction == T_MNEM_subs);
11233 narrow = !in_pred_block ();
11235 narrow = in_pred_block ();
11236 if (!inst.operands[2].isreg)
11240 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11241 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11243 add = (inst.instruction == T_MNEM_add
11244 || inst.instruction == T_MNEM_adds);
11246 if (inst.size_req != 4)
11248 /* Attempt to use a narrow opcode, with relaxation if
11250 if (Rd == REG_SP && Rs == REG_SP && !flags)
11251 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11252 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11253 opcode = T_MNEM_add_sp;
11254 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11255 opcode = T_MNEM_add_pc;
11256 else if (Rd <= 7 && Rs <= 7 && narrow)
11259 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11261 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11265 inst.instruction = THUMB_OP16(opcode);
11266 inst.instruction |= (Rd << 4) | Rs;
11267 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11268 || (inst.relocs[0].type
11269 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
11271 if (inst.size_req == 2)
11272 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11274 inst.relax = opcode;
11278 constraint (inst.size_req == 2, BAD_HIREG);
11280 if (inst.size_req == 4
11281 || (inst.size_req != 2 && !opcode))
11283 constraint ((inst.relocs[0].type
11284 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11285 && (inst.relocs[0].type
11286 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
11287 THUMB1_RELOC_ONLY);
11290 constraint (add, BAD_PC);
11291 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11292 _("only SUBS PC, LR, #const allowed"));
11293 constraint (inst.relocs[0].exp.X_op != O_constant,
11294 _("expression too complex"));
11295 constraint (inst.relocs[0].exp.X_add_number < 0
11296 || inst.relocs[0].exp.X_add_number > 0xff,
11297 _("immediate value out of range"));
11298 inst.instruction = T2_SUBS_PC_LR
11299 | inst.relocs[0].exp.X_add_number;
11300 inst.relocs[0].type = BFD_RELOC_UNUSED;
11303 else if (Rs == REG_PC)
11305 /* Always use addw/subw. */
11306 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11307 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11311 inst.instruction = THUMB_OP32 (inst.instruction);
11312 inst.instruction = (inst.instruction & 0xe1ffffff)
11315 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11317 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11319 inst.instruction |= Rd << 8;
11320 inst.instruction |= Rs << 16;
11325 unsigned int value = inst.relocs[0].exp.X_add_number;
11326 unsigned int shift = inst.operands[2].shift_kind;
11328 Rn = inst.operands[2].reg;
11329 /* See if we can do this with a 16-bit instruction. */
11330 if (!inst.operands[2].shifted && inst.size_req != 4)
11332 if (Rd > 7 || Rs > 7 || Rn > 7)
11337 inst.instruction = ((inst.instruction == T_MNEM_adds
11338 || inst.instruction == T_MNEM_add)
11340 : T_OPCODE_SUB_R3);
11341 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11345 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11347 /* Thumb-1 cores (except v6-M) require at least one high
11348 register in a narrow non flag setting add. */
11349 if (Rd > 7 || Rn > 7
11350 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11351 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
11358 inst.instruction = T_OPCODE_ADD_HI;
11359 inst.instruction |= (Rd & 8) << 4;
11360 inst.instruction |= (Rd & 7);
11361 inst.instruction |= Rn << 3;
11367 constraint (Rd == REG_PC, BAD_PC);
11368 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11369 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11370 constraint (Rs == REG_PC, BAD_PC);
11371 reject_bad_reg (Rn);
11373 /* If we get here, it can't be done in 16 bits. */
11374 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11375 _("shift must be constant"));
11376 inst.instruction = THUMB_OP32 (inst.instruction);
11377 inst.instruction |= Rd << 8;
11378 inst.instruction |= Rs << 16;
11379 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11380 _("shift value over 3 not allowed in thumb mode"));
11381 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11382 _("only LSL shift allowed in thumb mode"));
11383 encode_thumb32_shifted_operand (2);
11388 constraint (inst.instruction == T_MNEM_adds
11389 || inst.instruction == T_MNEM_subs,
11392 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11394 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11395 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11398 inst.instruction = (inst.instruction == T_MNEM_add
11399 ? 0x0000 : 0x8000);
11400 inst.instruction |= (Rd << 4) | Rs;
11401 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11405 Rn = inst.operands[2].reg;
11406 constraint (inst.operands[2].shifted, _("unshifted register required"));
11408 /* We now have Rd, Rs, and Rn set to registers. */
11409 if (Rd > 7 || Rs > 7 || Rn > 7)
11411 /* Can't do this for SUB. */
11412 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11413 inst.instruction = T_OPCODE_ADD_HI;
11414 inst.instruction |= (Rd & 8) << 4;
11415 inst.instruction |= (Rd & 7);
11417 inst.instruction |= Rn << 3;
11419 inst.instruction |= Rs << 3;
11421 constraint (1, _("dest must overlap one source register"));
11425 inst.instruction = (inst.instruction == T_MNEM_add
11426 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11427 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11437 Rd = inst.operands[0].reg;
11438 reject_bad_reg (Rd);
11440 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11442 /* Defer to section relaxation. */
11443 inst.relax = inst.instruction;
11444 inst.instruction = THUMB_OP16 (inst.instruction);
11445 inst.instruction |= Rd << 4;
11447 else if (unified_syntax && inst.size_req != 2)
11449 /* Generate a 32-bit opcode. */
11450 inst.instruction = THUMB_OP32 (inst.instruction);
11451 inst.instruction |= Rd << 8;
11452 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11453 inst.relocs[0].pc_rel = 1;
11457 /* Generate a 16-bit opcode. */
11458 inst.instruction = THUMB_OP16 (inst.instruction);
11459 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11460 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11461 inst.relocs[0].pc_rel = 1;
11462 inst.instruction |= Rd << 4;
11465 if (inst.relocs[0].exp.X_op == O_symbol
11466 && inst.relocs[0].exp.X_add_symbol != NULL
11467 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11468 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11469 inst.relocs[0].exp.X_add_number += 1;
11472 /* Arithmetic instructions for which there is just one 16-bit
11473 instruction encoding, and it allows only two low registers.
11474 For maximal compatibility with ARM syntax, we allow three register
11475 operands even when Thumb-32 instructions are not available, as long
11476 as the first two are identical. For instance, both "sbc r0,r1" and
11477 "sbc r0,r0,r1" are allowed. */
11483 Rd = inst.operands[0].reg;
11484 Rs = (inst.operands[1].present
11485 ? inst.operands[1].reg /* Rd, Rs, foo */
11486 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11487 Rn = inst.operands[2].reg;
11489 reject_bad_reg (Rd);
11490 reject_bad_reg (Rs);
11491 if (inst.operands[2].isreg)
11492 reject_bad_reg (Rn);
11494 if (unified_syntax)
11496 if (!inst.operands[2].isreg)
11498 /* For an immediate, we always generate a 32-bit opcode;
11499 section relaxation will shrink it later if possible. */
11500 inst.instruction = THUMB_OP32 (inst.instruction);
11501 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11502 inst.instruction |= Rd << 8;
11503 inst.instruction |= Rs << 16;
11504 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11508 bfd_boolean narrow;
11510 /* See if we can do this with a 16-bit instruction. */
11511 if (THUMB_SETS_FLAGS (inst.instruction))
11512 narrow = !in_pred_block ();
11514 narrow = in_pred_block ();
11516 if (Rd > 7 || Rn > 7 || Rs > 7)
11518 if (inst.operands[2].shifted)
11520 if (inst.size_req == 4)
11526 inst.instruction = THUMB_OP16 (inst.instruction);
11527 inst.instruction |= Rd;
11528 inst.instruction |= Rn << 3;
11532 /* If we get here, it can't be done in 16 bits. */
11533 constraint (inst.operands[2].shifted
11534 && inst.operands[2].immisreg,
11535 _("shift must be constant"));
11536 inst.instruction = THUMB_OP32 (inst.instruction);
11537 inst.instruction |= Rd << 8;
11538 inst.instruction |= Rs << 16;
11539 encode_thumb32_shifted_operand (2);
11544 /* On its face this is a lie - the instruction does set the
11545 flags. However, the only supported mnemonic in this mode
11546 says it doesn't. */
11547 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11549 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11550 _("unshifted register required"));
11551 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11552 constraint (Rd != Rs,
11553 _("dest and source1 must be the same register"));
11555 inst.instruction = THUMB_OP16 (inst.instruction);
11556 inst.instruction |= Rd;
11557 inst.instruction |= Rn << 3;
11561 /* Similarly, but for instructions where the arithmetic operation is
11562 commutative, so we can allow either of them to be different from
11563 the destination operand in a 16-bit instruction. For instance, all
11564 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11571 Rd = inst.operands[0].reg;
11572 Rs = (inst.operands[1].present
11573 ? inst.operands[1].reg /* Rd, Rs, foo */
11574 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11575 Rn = inst.operands[2].reg;
11577 reject_bad_reg (Rd);
11578 reject_bad_reg (Rs);
11579 if (inst.operands[2].isreg)
11580 reject_bad_reg (Rn);
11582 if (unified_syntax)
11584 if (!inst.operands[2].isreg)
11586 /* For an immediate, we always generate a 32-bit opcode;
11587 section relaxation will shrink it later if possible. */
11588 inst.instruction = THUMB_OP32 (inst.instruction);
11589 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11590 inst.instruction |= Rd << 8;
11591 inst.instruction |= Rs << 16;
11592 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11596 bfd_boolean narrow;
11598 /* See if we can do this with a 16-bit instruction. */
11599 if (THUMB_SETS_FLAGS (inst.instruction))
11600 narrow = !in_pred_block ();
11602 narrow = in_pred_block ();
11604 if (Rd > 7 || Rn > 7 || Rs > 7)
11606 if (inst.operands[2].shifted)
11608 if (inst.size_req == 4)
11615 inst.instruction = THUMB_OP16 (inst.instruction);
11616 inst.instruction |= Rd;
11617 inst.instruction |= Rn << 3;
11622 inst.instruction = THUMB_OP16 (inst.instruction);
11623 inst.instruction |= Rd;
11624 inst.instruction |= Rs << 3;
11629 /* If we get here, it can't be done in 16 bits. */
11630 constraint (inst.operands[2].shifted
11631 && inst.operands[2].immisreg,
11632 _("shift must be constant"));
11633 inst.instruction = THUMB_OP32 (inst.instruction);
11634 inst.instruction |= Rd << 8;
11635 inst.instruction |= Rs << 16;
11636 encode_thumb32_shifted_operand (2);
11641 /* On its face this is a lie - the instruction does set the
11642 flags. However, the only supported mnemonic in this mode
11643 says it doesn't. */
11644 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11646 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11647 _("unshifted register required"));
11648 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11650 inst.instruction = THUMB_OP16 (inst.instruction);
11651 inst.instruction |= Rd;
11654 inst.instruction |= Rn << 3;
11656 inst.instruction |= Rs << 3;
11658 constraint (1, _("dest must overlap one source register"));
11666 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11667 constraint (msb > 32, _("bit-field extends past end of register"));
11668 /* The instruction encoding stores the LSB and MSB,
11669 not the LSB and width. */
11670 Rd = inst.operands[0].reg;
11671 reject_bad_reg (Rd);
11672 inst.instruction |= Rd << 8;
11673 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11674 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11675 inst.instruction |= msb - 1;
11684 Rd = inst.operands[0].reg;
11685 reject_bad_reg (Rd);
11687 /* #0 in second position is alternative syntax for bfc, which is
11688 the same instruction but with REG_PC in the Rm field. */
11689 if (!inst.operands[1].isreg)
11693 Rn = inst.operands[1].reg;
11694 reject_bad_reg (Rn);
11697 msb = inst.operands[2].imm + inst.operands[3].imm;
11698 constraint (msb > 32, _("bit-field extends past end of register"));
11699 /* The instruction encoding stores the LSB and MSB,
11700 not the LSB and width. */
11701 inst.instruction |= Rd << 8;
11702 inst.instruction |= Rn << 16;
11703 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11704 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11705 inst.instruction |= msb - 1;
11713 Rd = inst.operands[0].reg;
11714 Rn = inst.operands[1].reg;
11716 reject_bad_reg (Rd);
11717 reject_bad_reg (Rn);
11719 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11720 _("bit-field extends past end of register"));
11721 inst.instruction |= Rd << 8;
11722 inst.instruction |= Rn << 16;
11723 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11724 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11725 inst.instruction |= inst.operands[3].imm - 1;
11728 /* ARM V5 Thumb BLX (argument parse)
11729 BLX <target_addr> which is BLX(1)
11730 BLX <Rm> which is BLX(2)
11731 Unfortunately, there are two different opcodes for this mnemonic.
11732 So, the insns[].value is not used, and the code here zaps values
11733 into inst.instruction.
11735 ??? How to take advantage of the additional two bits of displacement
11736 available in Thumb32 mode? Need new relocation? */
11741 set_pred_insn_type_last ();
11743 if (inst.operands[0].isreg)
11745 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11746 /* We have a register, so this is BLX(2). */
11747 inst.instruction |= inst.operands[0].reg << 3;
11751 /* No register. This must be BLX(1). */
11752 inst.instruction = 0xf000e800;
11753 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
11762 bfd_reloc_code_real_type reloc;
11765 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
11767 if (in_pred_block ())
11769 /* Conditional branches inside IT blocks are encoded as unconditional
11771 cond = COND_ALWAYS;
11776 if (cond != COND_ALWAYS)
11777 opcode = T_MNEM_bcond;
11779 opcode = inst.instruction;
11782 && (inst.size_req == 4
11783 || (inst.size_req != 2
11784 && (inst.operands[0].hasreloc
11785 || inst.relocs[0].exp.X_op == O_constant))))
11787 inst.instruction = THUMB_OP32(opcode);
11788 if (cond == COND_ALWAYS)
11789 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11792 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11793 _("selected architecture does not support "
11794 "wide conditional branch instruction"));
11796 gas_assert (cond != 0xF);
11797 inst.instruction |= cond << 22;
11798 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11803 inst.instruction = THUMB_OP16(opcode);
11804 if (cond == COND_ALWAYS)
11805 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11808 inst.instruction |= cond << 8;
11809 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11811 /* Allow section relaxation. */
11812 if (unified_syntax && inst.size_req != 2)
11813 inst.relax = opcode;
11815 inst.relocs[0].type = reloc;
11816 inst.relocs[0].pc_rel = 1;
11819 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11820 between the two is the maximum immediate allowed - which is passed in
11823 do_t_bkpt_hlt1 (int range)
11825 constraint (inst.cond != COND_ALWAYS,
11826 _("instruction is always unconditional"));
11827 if (inst.operands[0].present)
11829 constraint (inst.operands[0].imm > range,
11830 _("immediate value out of range"));
11831 inst.instruction |= inst.operands[0].imm;
11834 set_pred_insn_type (NEUTRAL_IT_INSN);
11840 do_t_bkpt_hlt1 (63);
11846 do_t_bkpt_hlt1 (255);
11850 do_t_branch23 (void)
11852 set_pred_insn_type_last ();
11853 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11855 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11856 this file. We used to simply ignore the PLT reloc type here --
11857 the branch encoding is now needed to deal with TLSCALL relocs.
11858 So if we see a PLT reloc now, put it back to how it used to be to
11859 keep the preexisting behaviour. */
11860 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
11861 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11863 #if defined(OBJ_COFF)
11864 /* If the destination of the branch is a defined symbol which does not have
11865 the THUMB_FUNC attribute, then we must be calling a function which has
11866 the (interfacearm) attribute. We look for the Thumb entry point to that
11867 function and change the branch to refer to that function instead. */
11868 if ( inst.relocs[0].exp.X_op == O_symbol
11869 && inst.relocs[0].exp.X_add_symbol != NULL
11870 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11871 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11872 inst.relocs[0].exp.X_add_symbol
11873 = find_real_start (inst.relocs[0].exp.X_add_symbol);
11880 set_pred_insn_type_last ();
11881 inst.instruction |= inst.operands[0].reg << 3;
11882 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11883 should cause the alignment to be checked once it is known. This is
11884 because BX PC only works if the instruction is word aligned. */
11892 set_pred_insn_type_last ();
11893 Rm = inst.operands[0].reg;
11894 reject_bad_reg (Rm);
11895 inst.instruction |= Rm << 16;
11904 Rd = inst.operands[0].reg;
11905 Rm = inst.operands[1].reg;
11907 reject_bad_reg (Rd);
11908 reject_bad_reg (Rm);
11910 inst.instruction |= Rd << 8;
11911 inst.instruction |= Rm << 16;
11912 inst.instruction |= Rm;
11918 set_pred_insn_type (OUTSIDE_PRED_INSN);
11924 set_pred_insn_type (OUTSIDE_PRED_INSN);
11925 inst.instruction |= inst.operands[0].imm;
11931 set_pred_insn_type (OUTSIDE_PRED_INSN);
11933 && (inst.operands[1].present || inst.size_req == 4)
11934 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11936 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11937 inst.instruction = 0xf3af8000;
11938 inst.instruction |= imod << 9;
11939 inst.instruction |= inst.operands[0].imm << 5;
11940 if (inst.operands[1].present)
11941 inst.instruction |= 0x100 | inst.operands[1].imm;
11945 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11946 && (inst.operands[0].imm & 4),
11947 _("selected processor does not support 'A' form "
11948 "of this instruction"));
11949 constraint (inst.operands[1].present || inst.size_req == 4,
11950 _("Thumb does not support the 2-argument "
11951 "form of this instruction"));
11952 inst.instruction |= inst.operands[0].imm;
11956 /* THUMB CPY instruction (argument parse). */
11961 if (inst.size_req == 4)
11963 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11964 inst.instruction |= inst.operands[0].reg << 8;
11965 inst.instruction |= inst.operands[1].reg;
11969 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11970 inst.instruction |= (inst.operands[0].reg & 0x7);
11971 inst.instruction |= inst.operands[1].reg << 3;
11978 set_pred_insn_type (OUTSIDE_PRED_INSN);
11979 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11980 inst.instruction |= inst.operands[0].reg;
11981 inst.relocs[0].pc_rel = 1;
11982 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11988 inst.instruction |= inst.operands[0].imm;
11994 unsigned Rd, Rn, Rm;
11996 Rd = inst.operands[0].reg;
11997 Rn = (inst.operands[1].present
11998 ? inst.operands[1].reg : Rd);
11999 Rm = inst.operands[2].reg;
12001 reject_bad_reg (Rd);
12002 reject_bad_reg (Rn);
12003 reject_bad_reg (Rm);
12005 inst.instruction |= Rd << 8;
12006 inst.instruction |= Rn << 16;
12007 inst.instruction |= Rm;
12013 if (unified_syntax && inst.size_req == 4)
12014 inst.instruction = THUMB_OP32 (inst.instruction);
12016 inst.instruction = THUMB_OP16 (inst.instruction);
12022 unsigned int cond = inst.operands[0].imm;
12024 set_pred_insn_type (IT_INSN);
12025 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12026 now_pred.cc = cond;
12027 now_pred.warn_deprecated = FALSE;
12028 now_pred.type = SCALAR_PRED;
12030 /* If the condition is a negative condition, invert the mask. */
12031 if ((cond & 0x1) == 0x0)
12033 unsigned int mask = inst.instruction & 0x000f;
12035 if ((mask & 0x7) == 0)
12037 /* No conversion needed. */
12038 now_pred.block_length = 1;
12040 else if ((mask & 0x3) == 0)
12043 now_pred.block_length = 2;
12045 else if ((mask & 0x1) == 0)
12048 now_pred.block_length = 3;
12053 now_pred.block_length = 4;
12056 inst.instruction &= 0xfff0;
12057 inst.instruction |= mask;
12060 inst.instruction |= cond << 4;
12063 /* Helper function used for both push/pop and ldm/stm. */
12065 encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12066 bfd_boolean writeback)
12068 bfd_boolean load, store;
12070 gas_assert (base != -1 || !do_io);
12071 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12072 store = do_io && !load;
12074 if (mask & (1 << 13))
12075 inst.error = _("SP not allowed in register list");
12077 if (do_io && (mask & (1 << base)) != 0
12079 inst.error = _("having the base register in the register list when "
12080 "using write back is UNPREDICTABLE");
12084 if (mask & (1 << 15))
12086 if (mask & (1 << 14))
12087 inst.error = _("LR and PC should not both be in register list");
12089 set_pred_insn_type_last ();
12094 if (mask & (1 << 15))
12095 inst.error = _("PC not allowed in register list");
12098 if (do_io && ((mask & (mask - 1)) == 0))
12100 /* Single register transfers implemented as str/ldr. */
12103 if (inst.instruction & (1 << 23))
12104 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12106 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12110 if (inst.instruction & (1 << 23))
12111 inst.instruction = 0x00800000; /* ia -> [base] */
12113 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12116 inst.instruction |= 0xf8400000;
12118 inst.instruction |= 0x00100000;
12120 mask = ffs (mask) - 1;
12123 else if (writeback)
12124 inst.instruction |= WRITE_BACK;
12126 inst.instruction |= mask;
12128 inst.instruction |= base << 16;
12134 /* This really doesn't seem worth it. */
12135 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12136 _("expression too complex"));
12137 constraint (inst.operands[1].writeback,
12138 _("Thumb load/store multiple does not support {reglist}^"));
12140 if (unified_syntax)
12142 bfd_boolean narrow;
12146 /* See if we can use a 16-bit instruction. */
12147 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12148 && inst.size_req != 4
12149 && !(inst.operands[1].imm & ~0xff))
12151 mask = 1 << inst.operands[0].reg;
12153 if (inst.operands[0].reg <= 7)
12155 if (inst.instruction == T_MNEM_stmia
12156 ? inst.operands[0].writeback
12157 : (inst.operands[0].writeback
12158 == !(inst.operands[1].imm & mask)))
12160 if (inst.instruction == T_MNEM_stmia
12161 && (inst.operands[1].imm & mask)
12162 && (inst.operands[1].imm & (mask - 1)))
12163 as_warn (_("value stored for r%d is UNKNOWN"),
12164 inst.operands[0].reg);
12166 inst.instruction = THUMB_OP16 (inst.instruction);
12167 inst.instruction |= inst.operands[0].reg << 8;
12168 inst.instruction |= inst.operands[1].imm;
12171 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12173 /* This means 1 register in reg list one of 3 situations:
12174 1. Instruction is stmia, but without writeback.
12175 2. lmdia without writeback, but with Rn not in
12177 3. ldmia with writeback, but with Rn in reglist.
12178 Case 3 is UNPREDICTABLE behaviour, so we handle
12179 case 1 and 2 which can be converted into a 16-bit
12180 str or ldr. The SP cases are handled below. */
12181 unsigned long opcode;
12182 /* First, record an error for Case 3. */
12183 if (inst.operands[1].imm & mask
12184 && inst.operands[0].writeback)
12186 _("having the base register in the register list when "
12187 "using write back is UNPREDICTABLE");
12189 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
12191 inst.instruction = THUMB_OP16 (opcode);
12192 inst.instruction |= inst.operands[0].reg << 3;
12193 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12197 else if (inst.operands[0] .reg == REG_SP)
12199 if (inst.operands[0].writeback)
12202 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12203 ? T_MNEM_push : T_MNEM_pop);
12204 inst.instruction |= inst.operands[1].imm;
12207 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12210 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12211 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
12212 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
12220 if (inst.instruction < 0xffff)
12221 inst.instruction = THUMB_OP32 (inst.instruction);
12223 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12224 inst.operands[1].imm,
12225 inst.operands[0].writeback);
12230 constraint (inst.operands[0].reg > 7
12231 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12232 constraint (inst.instruction != T_MNEM_ldmia
12233 && inst.instruction != T_MNEM_stmia,
12234 _("Thumb-2 instruction only valid in unified syntax"));
12235 if (inst.instruction == T_MNEM_stmia)
12237 if (!inst.operands[0].writeback)
12238 as_warn (_("this instruction will write back the base register"));
12239 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12240 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12241 as_warn (_("value stored for r%d is UNKNOWN"),
12242 inst.operands[0].reg);
12246 if (!inst.operands[0].writeback
12247 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12248 as_warn (_("this instruction will write back the base register"));
12249 else if (inst.operands[0].writeback
12250 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12251 as_warn (_("this instruction will not write back the base register"));
12254 inst.instruction = THUMB_OP16 (inst.instruction);
12255 inst.instruction |= inst.operands[0].reg << 8;
12256 inst.instruction |= inst.operands[1].imm;
12263 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12264 || inst.operands[1].postind || inst.operands[1].writeback
12265 || inst.operands[1].immisreg || inst.operands[1].shifted
12266 || inst.operands[1].negative,
12269 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12271 inst.instruction |= inst.operands[0].reg << 12;
12272 inst.instruction |= inst.operands[1].reg << 16;
12273 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12279 if (!inst.operands[1].present)
12281 constraint (inst.operands[0].reg == REG_LR,
12282 _("r14 not allowed as first register "
12283 "when second register is omitted"));
12284 inst.operands[1].reg = inst.operands[0].reg + 1;
12286 constraint (inst.operands[0].reg == inst.operands[1].reg,
12289 inst.instruction |= inst.operands[0].reg << 12;
12290 inst.instruction |= inst.operands[1].reg << 8;
12291 inst.instruction |= inst.operands[2].reg << 16;
12297 unsigned long opcode;
12300 if (inst.operands[0].isreg
12301 && !inst.operands[0].preind
12302 && inst.operands[0].reg == REG_PC)
12303 set_pred_insn_type_last ();
12305 opcode = inst.instruction;
12306 if (unified_syntax)
12308 if (!inst.operands[1].isreg)
12310 if (opcode <= 0xffff)
12311 inst.instruction = THUMB_OP32 (opcode);
12312 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12315 if (inst.operands[1].isreg
12316 && !inst.operands[1].writeback
12317 && !inst.operands[1].shifted && !inst.operands[1].postind
12318 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12319 && opcode <= 0xffff
12320 && inst.size_req != 4)
12322 /* Insn may have a 16-bit form. */
12323 Rn = inst.operands[1].reg;
12324 if (inst.operands[1].immisreg)
12326 inst.instruction = THUMB_OP16 (opcode);
12328 if (Rn <= 7 && inst.operands[1].imm <= 7)
12330 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12331 reject_bad_reg (inst.operands[1].imm);
12333 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12334 && opcode != T_MNEM_ldrsb)
12335 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12336 || (Rn == REG_SP && opcode == T_MNEM_str))
12343 if (inst.relocs[0].pc_rel)
12344 opcode = T_MNEM_ldr_pc2;
12346 opcode = T_MNEM_ldr_pc;
12350 if (opcode == T_MNEM_ldr)
12351 opcode = T_MNEM_ldr_sp;
12353 opcode = T_MNEM_str_sp;
12355 inst.instruction = inst.operands[0].reg << 8;
12359 inst.instruction = inst.operands[0].reg;
12360 inst.instruction |= inst.operands[1].reg << 3;
12362 inst.instruction |= THUMB_OP16 (opcode);
12363 if (inst.size_req == 2)
12364 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12366 inst.relax = opcode;
12370 /* Definitely a 32-bit variant. */
12372 /* Warning for Erratum 752419. */
12373 if (opcode == T_MNEM_ldr
12374 && inst.operands[0].reg == REG_SP
12375 && inst.operands[1].writeback == 1
12376 && !inst.operands[1].immisreg)
12378 if (no_cpu_selected ()
12379 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
12380 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12381 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
12382 as_warn (_("This instruction may be unpredictable "
12383 "if executed on M-profile cores "
12384 "with interrupts enabled."));
12387 /* Do some validations regarding addressing modes. */
12388 if (inst.operands[1].immisreg)
12389 reject_bad_reg (inst.operands[1].imm);
12391 constraint (inst.operands[1].writeback == 1
12392 && inst.operands[0].reg == inst.operands[1].reg,
12395 inst.instruction = THUMB_OP32 (opcode);
12396 inst.instruction |= inst.operands[0].reg << 12;
12397 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
12398 check_ldr_r15_aligned ();
12402 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12404 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12406 /* Only [Rn,Rm] is acceptable. */
12407 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12408 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12409 || inst.operands[1].postind || inst.operands[1].shifted
12410 || inst.operands[1].negative,
12411 _("Thumb does not support this addressing mode"));
12412 inst.instruction = THUMB_OP16 (inst.instruction);
12416 inst.instruction = THUMB_OP16 (inst.instruction);
12417 if (!inst.operands[1].isreg)
12418 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12421 constraint (!inst.operands[1].preind
12422 || inst.operands[1].shifted
12423 || inst.operands[1].writeback,
12424 _("Thumb does not support this addressing mode"));
12425 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12427 constraint (inst.instruction & 0x0600,
12428 _("byte or halfword not valid for base register"));
12429 constraint (inst.operands[1].reg == REG_PC
12430 && !(inst.instruction & THUMB_LOAD_BIT),
12431 _("r15 based store not allowed"));
12432 constraint (inst.operands[1].immisreg,
12433 _("invalid base register for register offset"));
12435 if (inst.operands[1].reg == REG_PC)
12436 inst.instruction = T_OPCODE_LDR_PC;
12437 else if (inst.instruction & THUMB_LOAD_BIT)
12438 inst.instruction = T_OPCODE_LDR_SP;
12440 inst.instruction = T_OPCODE_STR_SP;
12442 inst.instruction |= inst.operands[0].reg << 8;
12443 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12447 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12448 if (!inst.operands[1].immisreg)
12450 /* Immediate offset. */
12451 inst.instruction |= inst.operands[0].reg;
12452 inst.instruction |= inst.operands[1].reg << 3;
12453 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12457 /* Register offset. */
12458 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12459 constraint (inst.operands[1].negative,
12460 _("Thumb does not support this addressing mode"));
12463 switch (inst.instruction)
12465 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12466 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12467 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12468 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12469 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12470 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12471 case 0x5600 /* ldrsb */:
12472 case 0x5e00 /* ldrsh */: break;
12476 inst.instruction |= inst.operands[0].reg;
12477 inst.instruction |= inst.operands[1].reg << 3;
12478 inst.instruction |= inst.operands[1].imm << 6;
12484 if (!inst.operands[1].present)
12486 inst.operands[1].reg = inst.operands[0].reg + 1;
12487 constraint (inst.operands[0].reg == REG_LR,
12488 _("r14 not allowed here"));
12489 constraint (inst.operands[0].reg == REG_R12,
12490 _("r12 not allowed here"));
12493 if (inst.operands[2].writeback
12494 && (inst.operands[0].reg == inst.operands[2].reg
12495 || inst.operands[1].reg == inst.operands[2].reg))
12496 as_warn (_("base register written back, and overlaps "
12497 "one of transfer registers"));
12499 inst.instruction |= inst.operands[0].reg << 12;
12500 inst.instruction |= inst.operands[1].reg << 8;
12501 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
12507 inst.instruction |= inst.operands[0].reg << 12;
12508 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12514 unsigned Rd, Rn, Rm, Ra;
12516 Rd = inst.operands[0].reg;
12517 Rn = inst.operands[1].reg;
12518 Rm = inst.operands[2].reg;
12519 Ra = inst.operands[3].reg;
12521 reject_bad_reg (Rd);
12522 reject_bad_reg (Rn);
12523 reject_bad_reg (Rm);
12524 reject_bad_reg (Ra);
12526 inst.instruction |= Rd << 8;
12527 inst.instruction |= Rn << 16;
12528 inst.instruction |= Rm;
12529 inst.instruction |= Ra << 12;
12535 unsigned RdLo, RdHi, Rn, Rm;
12537 RdLo = inst.operands[0].reg;
12538 RdHi = inst.operands[1].reg;
12539 Rn = inst.operands[2].reg;
12540 Rm = inst.operands[3].reg;
12542 reject_bad_reg (RdLo);
12543 reject_bad_reg (RdHi);
12544 reject_bad_reg (Rn);
12545 reject_bad_reg (Rm);
12547 inst.instruction |= RdLo << 12;
12548 inst.instruction |= RdHi << 8;
12549 inst.instruction |= Rn << 16;
12550 inst.instruction |= Rm;
12554 do_t_mov_cmp (void)
12558 Rn = inst.operands[0].reg;
12559 Rm = inst.operands[1].reg;
12562 set_pred_insn_type_last ();
12564 if (unified_syntax)
12566 int r0off = (inst.instruction == T_MNEM_mov
12567 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12568 unsigned long opcode;
12569 bfd_boolean narrow;
12570 bfd_boolean low_regs;
12572 low_regs = (Rn <= 7 && Rm <= 7);
12573 opcode = inst.instruction;
12574 if (in_pred_block ())
12575 narrow = opcode != T_MNEM_movs;
12577 narrow = opcode != T_MNEM_movs || low_regs;
12578 if (inst.size_req == 4
12579 || inst.operands[1].shifted)
12582 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12583 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12584 && !inst.operands[1].shifted
12588 inst.instruction = T2_SUBS_PC_LR;
12592 if (opcode == T_MNEM_cmp)
12594 constraint (Rn == REG_PC, BAD_PC);
12597 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12599 warn_deprecated_sp (Rm);
12600 /* R15 was documented as a valid choice for Rm in ARMv6,
12601 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12602 tools reject R15, so we do too. */
12603 constraint (Rm == REG_PC, BAD_PC);
12606 reject_bad_reg (Rm);
12608 else if (opcode == T_MNEM_mov
12609 || opcode == T_MNEM_movs)
12611 if (inst.operands[1].isreg)
12613 if (opcode == T_MNEM_movs)
12615 reject_bad_reg (Rn);
12616 reject_bad_reg (Rm);
12620 /* This is mov.n. */
12621 if ((Rn == REG_SP || Rn == REG_PC)
12622 && (Rm == REG_SP || Rm == REG_PC))
12624 as_tsktsk (_("Use of r%u as a source register is "
12625 "deprecated when r%u is the destination "
12626 "register."), Rm, Rn);
12631 /* This is mov.w. */
12632 constraint (Rn == REG_PC, BAD_PC);
12633 constraint (Rm == REG_PC, BAD_PC);
12634 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12635 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12639 reject_bad_reg (Rn);
12642 if (!inst.operands[1].isreg)
12644 /* Immediate operand. */
12645 if (!in_pred_block () && opcode == T_MNEM_mov)
12647 if (low_regs && narrow)
12649 inst.instruction = THUMB_OP16 (opcode);
12650 inst.instruction |= Rn << 8;
12651 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12652 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12654 if (inst.size_req == 2)
12655 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12657 inst.relax = opcode;
12662 constraint ((inst.relocs[0].type
12663 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12664 && (inst.relocs[0].type
12665 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
12666 THUMB1_RELOC_ONLY);
12668 inst.instruction = THUMB_OP32 (inst.instruction);
12669 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12670 inst.instruction |= Rn << r0off;
12671 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12674 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12675 && (inst.instruction == T_MNEM_mov
12676 || inst.instruction == T_MNEM_movs))
12678 /* Register shifts are encoded as separate shift instructions. */
12679 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12681 if (in_pred_block ())
12686 if (inst.size_req == 4)
12689 if (!low_regs || inst.operands[1].imm > 7)
12695 switch (inst.operands[1].shift_kind)
12698 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12701 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12704 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12707 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12713 inst.instruction = opcode;
12716 inst.instruction |= Rn;
12717 inst.instruction |= inst.operands[1].imm << 3;
12722 inst.instruction |= CONDS_BIT;
12724 inst.instruction |= Rn << 8;
12725 inst.instruction |= Rm << 16;
12726 inst.instruction |= inst.operands[1].imm;
12731 /* Some mov with immediate shift have narrow variants.
12732 Register shifts are handled above. */
12733 if (low_regs && inst.operands[1].shifted
12734 && (inst.instruction == T_MNEM_mov
12735 || inst.instruction == T_MNEM_movs))
12737 if (in_pred_block ())
12738 narrow = (inst.instruction == T_MNEM_mov);
12740 narrow = (inst.instruction == T_MNEM_movs);
12745 switch (inst.operands[1].shift_kind)
12747 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12748 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12749 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12750 default: narrow = FALSE; break;
12756 inst.instruction |= Rn;
12757 inst.instruction |= Rm << 3;
12758 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
12762 inst.instruction = THUMB_OP32 (inst.instruction);
12763 inst.instruction |= Rn << r0off;
12764 encode_thumb32_shifted_operand (1);
12768 switch (inst.instruction)
12771 /* In v4t or v5t a move of two lowregs produces unpredictable
12772 results. Don't allow this. */
12775 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
12776 "MOV Rd, Rs with two low registers is not "
12777 "permitted on this architecture");
12778 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
12782 inst.instruction = T_OPCODE_MOV_HR;
12783 inst.instruction |= (Rn & 0x8) << 4;
12784 inst.instruction |= (Rn & 0x7);
12785 inst.instruction |= Rm << 3;
12789 /* We know we have low registers at this point.
12790 Generate LSLS Rd, Rs, #0. */
12791 inst.instruction = T_OPCODE_LSL_I;
12792 inst.instruction |= Rn;
12793 inst.instruction |= Rm << 3;
12799 inst.instruction = T_OPCODE_CMP_LR;
12800 inst.instruction |= Rn;
12801 inst.instruction |= Rm << 3;
12805 inst.instruction = T_OPCODE_CMP_HR;
12806 inst.instruction |= (Rn & 0x8) << 4;
12807 inst.instruction |= (Rn & 0x7);
12808 inst.instruction |= Rm << 3;
12815 inst.instruction = THUMB_OP16 (inst.instruction);
12817 /* PR 10443: Do not silently ignore shifted operands. */
12818 constraint (inst.operands[1].shifted,
12819 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12821 if (inst.operands[1].isreg)
12823 if (Rn < 8 && Rm < 8)
12825 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12826 since a MOV instruction produces unpredictable results. */
12827 if (inst.instruction == T_OPCODE_MOV_I8)
12828 inst.instruction = T_OPCODE_ADD_I3;
12830 inst.instruction = T_OPCODE_CMP_LR;
12832 inst.instruction |= Rn;
12833 inst.instruction |= Rm << 3;
12837 if (inst.instruction == T_OPCODE_MOV_I8)
12838 inst.instruction = T_OPCODE_MOV_HR;
12840 inst.instruction = T_OPCODE_CMP_HR;
12846 constraint (Rn > 7,
12847 _("only lo regs allowed with immediate"));
12848 inst.instruction |= Rn << 8;
12849 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12860 top = (inst.instruction & 0x00800000) != 0;
12861 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
12863 constraint (top, _(":lower16: not allowed in this instruction"));
12864 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
12866 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
12868 constraint (!top, _(":upper16: not allowed in this instruction"));
12869 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
12872 Rd = inst.operands[0].reg;
12873 reject_bad_reg (Rd);
12875 inst.instruction |= Rd << 8;
12876 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
12878 imm = inst.relocs[0].exp.X_add_number;
12879 inst.instruction |= (imm & 0xf000) << 4;
12880 inst.instruction |= (imm & 0x0800) << 15;
12881 inst.instruction |= (imm & 0x0700) << 4;
12882 inst.instruction |= (imm & 0x00ff);
12887 do_t_mvn_tst (void)
12891 Rn = inst.operands[0].reg;
12892 Rm = inst.operands[1].reg;
12894 if (inst.instruction == T_MNEM_cmp
12895 || inst.instruction == T_MNEM_cmn)
12896 constraint (Rn == REG_PC, BAD_PC);
12898 reject_bad_reg (Rn);
12899 reject_bad_reg (Rm);
12901 if (unified_syntax)
12903 int r0off = (inst.instruction == T_MNEM_mvn
12904 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12905 bfd_boolean narrow;
12907 if (inst.size_req == 4
12908 || inst.instruction > 0xffff
12909 || inst.operands[1].shifted
12910 || Rn > 7 || Rm > 7)
12912 else if (inst.instruction == T_MNEM_cmn
12913 || inst.instruction == T_MNEM_tst)
12915 else if (THUMB_SETS_FLAGS (inst.instruction))
12916 narrow = !in_pred_block ();
12918 narrow = in_pred_block ();
12920 if (!inst.operands[1].isreg)
12922 /* For an immediate, we always generate a 32-bit opcode;
12923 section relaxation will shrink it later if possible. */
12924 if (inst.instruction < 0xffff)
12925 inst.instruction = THUMB_OP32 (inst.instruction);
12926 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12927 inst.instruction |= Rn << r0off;
12928 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12932 /* See if we can do this with a 16-bit instruction. */
12935 inst.instruction = THUMB_OP16 (inst.instruction);
12936 inst.instruction |= Rn;
12937 inst.instruction |= Rm << 3;
12941 constraint (inst.operands[1].shifted
12942 && inst.operands[1].immisreg,
12943 _("shift must be constant"));
12944 if (inst.instruction < 0xffff)
12945 inst.instruction = THUMB_OP32 (inst.instruction);
12946 inst.instruction |= Rn << r0off;
12947 encode_thumb32_shifted_operand (1);
12953 constraint (inst.instruction > 0xffff
12954 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12955 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12956 _("unshifted register required"));
12957 constraint (Rn > 7 || Rm > 7,
12960 inst.instruction = THUMB_OP16 (inst.instruction);
12961 inst.instruction |= Rn;
12962 inst.instruction |= Rm << 3;
12971 if (do_vfp_nsyn_mrs () == SUCCESS)
12974 Rd = inst.operands[0].reg;
12975 reject_bad_reg (Rd);
12976 inst.instruction |= Rd << 8;
12978 if (inst.operands[1].isreg)
12980 unsigned br = inst.operands[1].reg;
12981 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12982 as_bad (_("bad register for mrs"));
12984 inst.instruction |= br & (0xf << 16);
12985 inst.instruction |= (br & 0x300) >> 4;
12986 inst.instruction |= (br & SPSR_BIT) >> 2;
12990 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12992 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12994 /* PR gas/12698: The constraint is only applied for m_profile.
12995 If the user has specified -march=all, we want to ignore it as
12996 we are building for any CPU type, including non-m variants. */
12997 bfd_boolean m_profile =
12998 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12999 constraint ((flags != 0) && m_profile, _("selected processor does "
13000 "not support requested special purpose register"));
13003 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13005 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13006 _("'APSR', 'CPSR' or 'SPSR' expected"));
13008 inst.instruction |= (flags & SPSR_BIT) >> 2;
13009 inst.instruction |= inst.operands[1].imm & 0xff;
13010 inst.instruction |= 0xf0000;
13020 if (do_vfp_nsyn_msr () == SUCCESS)
13023 constraint (!inst.operands[1].isreg,
13024 _("Thumb encoding does not support an immediate here"));
13026 if (inst.operands[0].isreg)
13027 flags = (int)(inst.operands[0].reg);
13029 flags = inst.operands[0].imm;
13031 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13033 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13035 /* PR gas/12698: The constraint is only applied for m_profile.
13036 If the user has specified -march=all, we want to ignore it as
13037 we are building for any CPU type, including non-m variants. */
13038 bfd_boolean m_profile =
13039 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13040 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13041 && (bits & ~(PSR_s | PSR_f)) != 0)
13042 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13043 && bits != PSR_f)) && m_profile,
13044 _("selected processor does not support requested special "
13045 "purpose register"));
13048 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13049 "requested special purpose register"));
13051 Rn = inst.operands[1].reg;
13052 reject_bad_reg (Rn);
13054 inst.instruction |= (flags & SPSR_BIT) >> 2;
13055 inst.instruction |= (flags & 0xf0000) >> 8;
13056 inst.instruction |= (flags & 0x300) >> 4;
13057 inst.instruction |= (flags & 0xff);
13058 inst.instruction |= Rn << 16;
13064 bfd_boolean narrow;
13065 unsigned Rd, Rn, Rm;
13067 if (!inst.operands[2].present)
13068 inst.operands[2].reg = inst.operands[0].reg;
13070 Rd = inst.operands[0].reg;
13071 Rn = inst.operands[1].reg;
13072 Rm = inst.operands[2].reg;
13074 if (unified_syntax)
13076 if (inst.size_req == 4
13082 else if (inst.instruction == T_MNEM_muls)
13083 narrow = !in_pred_block ();
13085 narrow = in_pred_block ();
13089 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13090 constraint (Rn > 7 || Rm > 7,
13097 /* 16-bit MULS/Conditional MUL. */
13098 inst.instruction = THUMB_OP16 (inst.instruction);
13099 inst.instruction |= Rd;
13102 inst.instruction |= Rm << 3;
13104 inst.instruction |= Rn << 3;
13106 constraint (1, _("dest must overlap one source register"));
13110 constraint (inst.instruction != T_MNEM_mul,
13111 _("Thumb-2 MUL must not set flags"));
13113 inst.instruction = THUMB_OP32 (inst.instruction);
13114 inst.instruction |= Rd << 8;
13115 inst.instruction |= Rn << 16;
13116 inst.instruction |= Rm << 0;
13118 reject_bad_reg (Rd);
13119 reject_bad_reg (Rn);
13120 reject_bad_reg (Rm);
13127 unsigned RdLo, RdHi, Rn, Rm;
13129 RdLo = inst.operands[0].reg;
13130 RdHi = inst.operands[1].reg;
13131 Rn = inst.operands[2].reg;
13132 Rm = inst.operands[3].reg;
13134 reject_bad_reg (RdLo);
13135 reject_bad_reg (RdHi);
13136 reject_bad_reg (Rn);
13137 reject_bad_reg (Rm);
13139 inst.instruction |= RdLo << 12;
13140 inst.instruction |= RdHi << 8;
13141 inst.instruction |= Rn << 16;
13142 inst.instruction |= Rm;
13145 as_tsktsk (_("rdhi and rdlo must be different"));
13151 set_pred_insn_type (NEUTRAL_IT_INSN);
13153 if (unified_syntax)
13155 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13157 inst.instruction = THUMB_OP32 (inst.instruction);
13158 inst.instruction |= inst.operands[0].imm;
13162 /* PR9722: Check for Thumb2 availability before
13163 generating a thumb2 nop instruction. */
13164 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
13166 inst.instruction = THUMB_OP16 (inst.instruction);
13167 inst.instruction |= inst.operands[0].imm << 4;
13170 inst.instruction = 0x46c0;
13175 constraint (inst.operands[0].present,
13176 _("Thumb does not support NOP with hints"));
13177 inst.instruction = 0x46c0;
13184 if (unified_syntax)
13186 bfd_boolean narrow;
13188 if (THUMB_SETS_FLAGS (inst.instruction))
13189 narrow = !in_pred_block ();
13191 narrow = in_pred_block ();
13192 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13194 if (inst.size_req == 4)
13199 inst.instruction = THUMB_OP32 (inst.instruction);
13200 inst.instruction |= inst.operands[0].reg << 8;
13201 inst.instruction |= inst.operands[1].reg << 16;
13205 inst.instruction = THUMB_OP16 (inst.instruction);
13206 inst.instruction |= inst.operands[0].reg;
13207 inst.instruction |= inst.operands[1].reg << 3;
13212 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13214 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13216 inst.instruction = THUMB_OP16 (inst.instruction);
13217 inst.instruction |= inst.operands[0].reg;
13218 inst.instruction |= inst.operands[1].reg << 3;
13227 Rd = inst.operands[0].reg;
13228 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13230 reject_bad_reg (Rd);
13231 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13232 reject_bad_reg (Rn);
13234 inst.instruction |= Rd << 8;
13235 inst.instruction |= Rn << 16;
13237 if (!inst.operands[2].isreg)
13239 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13240 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13246 Rm = inst.operands[2].reg;
13247 reject_bad_reg (Rm);
13249 constraint (inst.operands[2].shifted
13250 && inst.operands[2].immisreg,
13251 _("shift must be constant"));
13252 encode_thumb32_shifted_operand (2);
13259 unsigned Rd, Rn, Rm;
13261 Rd = inst.operands[0].reg;
13262 Rn = inst.operands[1].reg;
13263 Rm = inst.operands[2].reg;
13265 reject_bad_reg (Rd);
13266 reject_bad_reg (Rn);
13267 reject_bad_reg (Rm);
13269 inst.instruction |= Rd << 8;
13270 inst.instruction |= Rn << 16;
13271 inst.instruction |= Rm;
13272 if (inst.operands[3].present)
13274 unsigned int val = inst.relocs[0].exp.X_add_number;
13275 constraint (inst.relocs[0].exp.X_op != O_constant,
13276 _("expression too complex"));
13277 inst.instruction |= (val & 0x1c) << 10;
13278 inst.instruction |= (val & 0x03) << 6;
13285 if (!inst.operands[3].present)
13289 inst.instruction &= ~0x00000020;
13291 /* PR 10168. Swap the Rm and Rn registers. */
13292 Rtmp = inst.operands[1].reg;
13293 inst.operands[1].reg = inst.operands[2].reg;
13294 inst.operands[2].reg = Rtmp;
13302 if (inst.operands[0].immisreg)
13303 reject_bad_reg (inst.operands[0].imm);
13305 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13309 do_t_push_pop (void)
13313 constraint (inst.operands[0].writeback,
13314 _("push/pop do not support {reglist}^"));
13315 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13316 _("expression too complex"));
13318 mask = inst.operands[0].imm;
13319 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13320 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13321 else if (inst.size_req != 4
13322 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13323 ? REG_LR : REG_PC)))
13325 inst.instruction = THUMB_OP16 (inst.instruction);
13326 inst.instruction |= THUMB_PP_PC_LR;
13327 inst.instruction |= mask & 0xff;
13329 else if (unified_syntax)
13331 inst.instruction = THUMB_OP32 (inst.instruction);
13332 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13336 inst.error = _("invalid register list to push/pop instruction");
13344 if (unified_syntax)
13345 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
13348 inst.error = _("invalid register list to push/pop instruction");
13354 do_t_vscclrm (void)
13356 if (inst.operands[0].issingle)
13358 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13359 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13360 inst.instruction |= inst.operands[0].imm;
13364 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13365 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13366 inst.instruction |= 1 << 8;
13367 inst.instruction |= inst.operands[0].imm << 1;
13376 Rd = inst.operands[0].reg;
13377 Rm = inst.operands[1].reg;
13379 reject_bad_reg (Rd);
13380 reject_bad_reg (Rm);
13382 inst.instruction |= Rd << 8;
13383 inst.instruction |= Rm << 16;
13384 inst.instruction |= Rm;
13392 Rd = inst.operands[0].reg;
13393 Rm = inst.operands[1].reg;
13395 reject_bad_reg (Rd);
13396 reject_bad_reg (Rm);
13398 if (Rd <= 7 && Rm <= 7
13399 && inst.size_req != 4)
13401 inst.instruction = THUMB_OP16 (inst.instruction);
13402 inst.instruction |= Rd;
13403 inst.instruction |= Rm << 3;
13405 else if (unified_syntax)
13407 inst.instruction = THUMB_OP32 (inst.instruction);
13408 inst.instruction |= Rd << 8;
13409 inst.instruction |= Rm << 16;
13410 inst.instruction |= Rm;
13413 inst.error = BAD_HIREG;
13421 Rd = inst.operands[0].reg;
13422 Rm = inst.operands[1].reg;
13424 reject_bad_reg (Rd);
13425 reject_bad_reg (Rm);
13427 inst.instruction |= Rd << 8;
13428 inst.instruction |= Rm;
13436 Rd = inst.operands[0].reg;
13437 Rs = (inst.operands[1].present
13438 ? inst.operands[1].reg /* Rd, Rs, foo */
13439 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13441 reject_bad_reg (Rd);
13442 reject_bad_reg (Rs);
13443 if (inst.operands[2].isreg)
13444 reject_bad_reg (inst.operands[2].reg);
13446 inst.instruction |= Rd << 8;
13447 inst.instruction |= Rs << 16;
13448 if (!inst.operands[2].isreg)
13450 bfd_boolean narrow;
13452 if ((inst.instruction & 0x00100000) != 0)
13453 narrow = !in_pred_block ();
13455 narrow = in_pred_block ();
13457 if (Rd > 7 || Rs > 7)
13460 if (inst.size_req == 4 || !unified_syntax)
13463 if (inst.relocs[0].exp.X_op != O_constant
13464 || inst.relocs[0].exp.X_add_number != 0)
13467 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13468 relaxation, but it doesn't seem worth the hassle. */
13471 inst.relocs[0].type = BFD_RELOC_UNUSED;
13472 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13473 inst.instruction |= Rs << 3;
13474 inst.instruction |= Rd;
13478 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13479 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13483 encode_thumb32_shifted_operand (2);
13489 if (warn_on_deprecated
13490 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13491 as_tsktsk (_("setend use is deprecated for ARMv8"));
13493 set_pred_insn_type (OUTSIDE_PRED_INSN);
13494 if (inst.operands[0].imm)
13495 inst.instruction |= 0x8;
13501 if (!inst.operands[1].present)
13502 inst.operands[1].reg = inst.operands[0].reg;
13504 if (unified_syntax)
13506 bfd_boolean narrow;
13509 switch (inst.instruction)
13512 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13514 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13516 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13518 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13522 if (THUMB_SETS_FLAGS (inst.instruction))
13523 narrow = !in_pred_block ();
13525 narrow = in_pred_block ();
13526 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13528 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13530 if (inst.operands[2].isreg
13531 && (inst.operands[1].reg != inst.operands[0].reg
13532 || inst.operands[2].reg > 7))
13534 if (inst.size_req == 4)
13537 reject_bad_reg (inst.operands[0].reg);
13538 reject_bad_reg (inst.operands[1].reg);
13542 if (inst.operands[2].isreg)
13544 reject_bad_reg (inst.operands[2].reg);
13545 inst.instruction = THUMB_OP32 (inst.instruction);
13546 inst.instruction |= inst.operands[0].reg << 8;
13547 inst.instruction |= inst.operands[1].reg << 16;
13548 inst.instruction |= inst.operands[2].reg;
13550 /* PR 12854: Error on extraneous shifts. */
13551 constraint (inst.operands[2].shifted,
13552 _("extraneous shift as part of operand to shift insn"));
13556 inst.operands[1].shifted = 1;
13557 inst.operands[1].shift_kind = shift_kind;
13558 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13559 ? T_MNEM_movs : T_MNEM_mov);
13560 inst.instruction |= inst.operands[0].reg << 8;
13561 encode_thumb32_shifted_operand (1);
13562 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13563 inst.relocs[0].type = BFD_RELOC_UNUSED;
13568 if (inst.operands[2].isreg)
13570 switch (shift_kind)
13572 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13573 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13574 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13575 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13579 inst.instruction |= inst.operands[0].reg;
13580 inst.instruction |= inst.operands[2].reg << 3;
13582 /* PR 12854: Error on extraneous shifts. */
13583 constraint (inst.operands[2].shifted,
13584 _("extraneous shift as part of operand to shift insn"));
13588 switch (shift_kind)
13590 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13591 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13592 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13595 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13596 inst.instruction |= inst.operands[0].reg;
13597 inst.instruction |= inst.operands[1].reg << 3;
13603 constraint (inst.operands[0].reg > 7
13604 || inst.operands[1].reg > 7, BAD_HIREG);
13605 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13607 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13609 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13610 constraint (inst.operands[0].reg != inst.operands[1].reg,
13611 _("source1 and dest must be same register"));
13613 switch (inst.instruction)
13615 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13616 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13617 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13618 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13622 inst.instruction |= inst.operands[0].reg;
13623 inst.instruction |= inst.operands[2].reg << 3;
13625 /* PR 12854: Error on extraneous shifts. */
13626 constraint (inst.operands[2].shifted,
13627 _("extraneous shift as part of operand to shift insn"));
13631 switch (inst.instruction)
13633 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13634 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13635 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13636 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13639 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13640 inst.instruction |= inst.operands[0].reg;
13641 inst.instruction |= inst.operands[1].reg << 3;
13649 unsigned Rd, Rn, Rm;
13651 Rd = inst.operands[0].reg;
13652 Rn = inst.operands[1].reg;
13653 Rm = inst.operands[2].reg;
13655 reject_bad_reg (Rd);
13656 reject_bad_reg (Rn);
13657 reject_bad_reg (Rm);
13659 inst.instruction |= Rd << 8;
13660 inst.instruction |= Rn << 16;
13661 inst.instruction |= Rm;
13667 unsigned Rd, Rn, Rm;
13669 Rd = inst.operands[0].reg;
13670 Rm = inst.operands[1].reg;
13671 Rn = inst.operands[2].reg;
13673 reject_bad_reg (Rd);
13674 reject_bad_reg (Rn);
13675 reject_bad_reg (Rm);
13677 inst.instruction |= Rd << 8;
13678 inst.instruction |= Rn << 16;
13679 inst.instruction |= Rm;
13685 unsigned int value = inst.relocs[0].exp.X_add_number;
13686 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13687 _("SMC is not permitted on this architecture"));
13688 constraint (inst.relocs[0].exp.X_op != O_constant,
13689 _("expression too complex"));
13690 inst.relocs[0].type = BFD_RELOC_UNUSED;
13691 inst.instruction |= (value & 0xf000) >> 12;
13692 inst.instruction |= (value & 0x0ff0);
13693 inst.instruction |= (value & 0x000f) << 16;
13694 /* PR gas/15623: SMC instructions must be last in an IT block. */
13695 set_pred_insn_type_last ();
13701 unsigned int value = inst.relocs[0].exp.X_add_number;
13703 inst.relocs[0].type = BFD_RELOC_UNUSED;
13704 inst.instruction |= (value & 0x0fff);
13705 inst.instruction |= (value & 0xf000) << 4;
13709 do_t_ssat_usat (int bias)
13713 Rd = inst.operands[0].reg;
13714 Rn = inst.operands[2].reg;
13716 reject_bad_reg (Rd);
13717 reject_bad_reg (Rn);
13719 inst.instruction |= Rd << 8;
13720 inst.instruction |= inst.operands[1].imm - bias;
13721 inst.instruction |= Rn << 16;
13723 if (inst.operands[3].present)
13725 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
13727 inst.relocs[0].type = BFD_RELOC_UNUSED;
13729 constraint (inst.relocs[0].exp.X_op != O_constant,
13730 _("expression too complex"));
13732 if (shift_amount != 0)
13734 constraint (shift_amount > 31,
13735 _("shift expression is too large"));
13737 if (inst.operands[3].shift_kind == SHIFT_ASR)
13738 inst.instruction |= 0x00200000; /* sh bit. */
13740 inst.instruction |= (shift_amount & 0x1c) << 10;
13741 inst.instruction |= (shift_amount & 0x03) << 6;
13749 do_t_ssat_usat (1);
13757 Rd = inst.operands[0].reg;
13758 Rn = inst.operands[2].reg;
13760 reject_bad_reg (Rd);
13761 reject_bad_reg (Rn);
13763 inst.instruction |= Rd << 8;
13764 inst.instruction |= inst.operands[1].imm - 1;
13765 inst.instruction |= Rn << 16;
13771 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
13772 || inst.operands[2].postind || inst.operands[2].writeback
13773 || inst.operands[2].immisreg || inst.operands[2].shifted
13774 || inst.operands[2].negative,
13777 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
13779 inst.instruction |= inst.operands[0].reg << 8;
13780 inst.instruction |= inst.operands[1].reg << 12;
13781 inst.instruction |= inst.operands[2].reg << 16;
13782 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
13788 if (!inst.operands[2].present)
13789 inst.operands[2].reg = inst.operands[1].reg + 1;
13791 constraint (inst.operands[0].reg == inst.operands[1].reg
13792 || inst.operands[0].reg == inst.operands[2].reg
13793 || inst.operands[0].reg == inst.operands[3].reg,
13796 inst.instruction |= inst.operands[0].reg;
13797 inst.instruction |= inst.operands[1].reg << 12;
13798 inst.instruction |= inst.operands[2].reg << 8;
13799 inst.instruction |= inst.operands[3].reg << 16;
13805 unsigned Rd, Rn, Rm;
13807 Rd = inst.operands[0].reg;
13808 Rn = inst.operands[1].reg;
13809 Rm = inst.operands[2].reg;
13811 reject_bad_reg (Rd);
13812 reject_bad_reg (Rn);
13813 reject_bad_reg (Rm);
13815 inst.instruction |= Rd << 8;
13816 inst.instruction |= Rn << 16;
13817 inst.instruction |= Rm;
13818 inst.instruction |= inst.operands[3].imm << 4;
13826 Rd = inst.operands[0].reg;
13827 Rm = inst.operands[1].reg;
13829 reject_bad_reg (Rd);
13830 reject_bad_reg (Rm);
13832 if (inst.instruction <= 0xffff
13833 && inst.size_req != 4
13834 && Rd <= 7 && Rm <= 7
13835 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13837 inst.instruction = THUMB_OP16 (inst.instruction);
13838 inst.instruction |= Rd;
13839 inst.instruction |= Rm << 3;
13841 else if (unified_syntax)
13843 if (inst.instruction <= 0xffff)
13844 inst.instruction = THUMB_OP32 (inst.instruction);
13845 inst.instruction |= Rd << 8;
13846 inst.instruction |= Rm;
13847 inst.instruction |= inst.operands[2].imm << 4;
13851 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13852 _("Thumb encoding does not support rotation"));
13853 constraint (1, BAD_HIREG);
13860 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
13869 half = (inst.instruction & 0x10) != 0;
13870 set_pred_insn_type_last ();
13871 constraint (inst.operands[0].immisreg,
13872 _("instruction requires register index"));
13874 Rn = inst.operands[0].reg;
13875 Rm = inst.operands[0].imm;
13877 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13878 constraint (Rn == REG_SP, BAD_SP);
13879 reject_bad_reg (Rm);
13881 constraint (!half && inst.operands[0].shifted,
13882 _("instruction does not allow shifted index"));
13883 inst.instruction |= (Rn << 16) | Rm;
13889 if (!inst.operands[0].present)
13890 inst.operands[0].imm = 0;
13892 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13894 constraint (inst.size_req == 2,
13895 _("immediate value out of range"));
13896 inst.instruction = THUMB_OP32 (inst.instruction);
13897 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13898 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13902 inst.instruction = THUMB_OP16 (inst.instruction);
13903 inst.instruction |= inst.operands[0].imm;
13906 set_pred_insn_type (NEUTRAL_IT_INSN);
13913 do_t_ssat_usat (0);
13921 Rd = inst.operands[0].reg;
13922 Rn = inst.operands[2].reg;
13924 reject_bad_reg (Rd);
13925 reject_bad_reg (Rn);
13927 inst.instruction |= Rd << 8;
13928 inst.instruction |= inst.operands[1].imm;
13929 inst.instruction |= Rn << 16;
13932 /* Checking the range of the branch offset (VAL) with NBITS bits
13933 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13935 v8_1_branch_value_check (int val, int nbits, int is_signed)
13937 gas_assert (nbits > 0 && nbits <= 32);
13940 int cmp = (1 << (nbits - 1));
13941 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
13946 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
13952 /* For branches in Armv8.1-M Mainline. */
13954 do_t_branch_future (void)
13956 unsigned long insn = inst.instruction;
13958 inst.instruction = THUMB_OP32 (inst.instruction);
13959 if (inst.operands[0].hasreloc == 0)
13961 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
13962 as_bad (BAD_BRANCH_OFF);
13964 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
13968 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
13969 inst.relocs[0].pc_rel = 1;
13975 if (inst.operands[1].hasreloc == 0)
13977 int val = inst.operands[1].imm;
13978 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
13979 as_bad (BAD_BRANCH_OFF);
13981 int immA = (val & 0x0001f000) >> 12;
13982 int immB = (val & 0x00000ffc) >> 2;
13983 int immC = (val & 0x00000002) >> 1;
13984 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
13988 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
13989 inst.relocs[1].pc_rel = 1;
13994 if (inst.operands[1].hasreloc == 0)
13996 int val = inst.operands[1].imm;
13997 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
13998 as_bad (BAD_BRANCH_OFF);
14000 int immA = (val & 0x0007f000) >> 12;
14001 int immB = (val & 0x00000ffc) >> 2;
14002 int immC = (val & 0x00000002) >> 1;
14003 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14007 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14008 inst.relocs[1].pc_rel = 1;
14012 case T_MNEM_bfcsel:
14014 if (inst.operands[1].hasreloc == 0)
14016 int val = inst.operands[1].imm;
14017 int immA = (val & 0x00001000) >> 12;
14018 int immB = (val & 0x00000ffc) >> 2;
14019 int immC = (val & 0x00000002) >> 1;
14020 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14024 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14025 inst.relocs[1].pc_rel = 1;
14029 if (inst.operands[2].hasreloc == 0)
14031 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14032 int val2 = inst.operands[2].imm;
14033 int val0 = inst.operands[0].imm & 0x1f;
14034 int diff = val2 - val0;
14036 inst.instruction |= 1 << 17; /* T bit. */
14037 else if (diff != 2)
14038 as_bad (_("out of range label-relative fixup value"));
14042 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14043 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14044 inst.relocs[2].pc_rel = 1;
14048 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14049 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14054 inst.instruction |= inst.operands[1].reg << 16;
14061 /* Helper function for do_t_loloop to handle relocations. */
14063 v8_1_loop_reloc (int is_le)
14065 if (inst.relocs[0].exp.X_op == O_constant)
14067 int value = inst.relocs[0].exp.X_add_number;
14068 value = (is_le) ? -value : value;
14070 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14071 as_bad (BAD_BRANCH_OFF);
14075 immh = (value & 0x00000ffc) >> 2;
14076 imml = (value & 0x00000002) >> 1;
14078 inst.instruction |= (imml << 11) | (immh << 1);
14082 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14083 inst.relocs[0].pc_rel = 1;
14087 /* To handle the Scalar Low Overhead Loop instructions
14088 in Armv8.1-M Mainline. */
14092 unsigned long insn = inst.instruction;
14094 set_pred_insn_type (OUTSIDE_PRED_INSN);
14095 inst.instruction = THUMB_OP32 (inst.instruction);
14101 if (!inst.operands[0].present)
14102 inst.instruction |= 1 << 21;
14104 v8_1_loop_reloc (TRUE);
14108 v8_1_loop_reloc (FALSE);
14109 /* Fall through. */
14111 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
14112 inst.instruction |= (inst.operands[1].reg << 16);
14119 /* MVE instruction encoder helpers. */
14120 #define M_MNEM_vabav 0xee800f01
14121 #define M_MNEM_vmladav 0xeef00e00
14122 #define M_MNEM_vmladava 0xeef00e20
14123 #define M_MNEM_vmladavx 0xeef01e00
14124 #define M_MNEM_vmladavax 0xeef01e20
14125 #define M_MNEM_vmlsdav 0xeef00e01
14126 #define M_MNEM_vmlsdava 0xeef00e21
14127 #define M_MNEM_vmlsdavx 0xeef01e01
14128 #define M_MNEM_vmlsdavax 0xeef01e21
14129 #define M_MNEM_vmullt 0xee011e00
14130 #define M_MNEM_vmullb 0xee010e00
14131 #define M_MNEM_vst20 0xfc801e00
14132 #define M_MNEM_vst21 0xfc801e20
14133 #define M_MNEM_vst40 0xfc801e01
14134 #define M_MNEM_vst41 0xfc801e21
14135 #define M_MNEM_vst42 0xfc801e41
14136 #define M_MNEM_vst43 0xfc801e61
14137 #define M_MNEM_vld20 0xfc901e00
14138 #define M_MNEM_vld21 0xfc901e20
14139 #define M_MNEM_vld40 0xfc901e01
14140 #define M_MNEM_vld41 0xfc901e21
14141 #define M_MNEM_vld42 0xfc901e41
14142 #define M_MNEM_vld43 0xfc901e61
14143 #define M_MNEM_vstrb 0xec000e00
14144 #define M_MNEM_vstrh 0xec000e10
14145 #define M_MNEM_vstrw 0xec000e40
14146 #define M_MNEM_vstrd 0xec000e50
14147 #define M_MNEM_vldrb 0xec100e00
14148 #define M_MNEM_vldrh 0xec100e10
14149 #define M_MNEM_vldrw 0xec100e40
14150 #define M_MNEM_vldrd 0xec100e50
14151 #define M_MNEM_vmovlt 0xeea01f40
14152 #define M_MNEM_vmovlb 0xeea00f40
14153 #define M_MNEM_vmovnt 0xfe311e81
14154 #define M_MNEM_vmovnb 0xfe310e81
14155 #define M_MNEM_vadc 0xee300f00
14156 #define M_MNEM_vadci 0xee301f00
14157 #define M_MNEM_vbrsr 0xfe011e60
14158 #define M_MNEM_vaddlv 0xee890f00
14159 #define M_MNEM_vaddlva 0xee890f20
14160 #define M_MNEM_vaddv 0xeef10f00
14161 #define M_MNEM_vaddva 0xeef10f20
14162 #define M_MNEM_vddup 0xee011f6e
14163 #define M_MNEM_vdwdup 0xee011f60
14164 #define M_MNEM_vidup 0xee010f6e
14165 #define M_MNEM_viwdup 0xee010f60
14166 #define M_MNEM_vmaxv 0xeee20f00
14167 #define M_MNEM_vmaxav 0xeee00f00
14168 #define M_MNEM_vminv 0xeee20f80
14169 #define M_MNEM_vminav 0xeee00f80
14170 #define M_MNEM_vmlaldav 0xee800e00
14171 #define M_MNEM_vmlaldava 0xee800e20
14172 #define M_MNEM_vmlaldavx 0xee801e00
14173 #define M_MNEM_vmlaldavax 0xee801e20
14174 #define M_MNEM_vmlsldav 0xee800e01
14175 #define M_MNEM_vmlsldava 0xee800e21
14176 #define M_MNEM_vmlsldavx 0xee801e01
14177 #define M_MNEM_vmlsldavax 0xee801e21
14178 #define M_MNEM_vrmlaldavhx 0xee801f00
14179 #define M_MNEM_vrmlaldavhax 0xee801f20
14180 #define M_MNEM_vrmlsldavh 0xfe800e01
14181 #define M_MNEM_vrmlsldavha 0xfe800e21
14182 #define M_MNEM_vrmlsldavhx 0xfe801e01
14183 #define M_MNEM_vrmlsldavhax 0xfe801e21
14185 /* Neon instruction encoder helpers. */
14187 /* Encodings for the different types for various Neon opcodes. */
14189 /* An "invalid" code for the following tables. */
14192 struct neon_tab_entry
14195 unsigned float_or_poly;
14196 unsigned scalar_or_imm;
14199 /* Map overloaded Neon opcodes to their respective encodings. */
14200 #define NEON_ENC_TAB \
14201 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14202 X(vabdl, 0x0800700, N_INV, N_INV), \
14203 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14204 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14205 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14206 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14207 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14208 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14209 X(vaddl, 0x0800000, N_INV, N_INV), \
14210 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14211 X(vsubl, 0x0800200, N_INV, N_INV), \
14212 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14213 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14214 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14215 /* Register variants of the following two instructions are encoded as
14216 vcge / vcgt with the operands reversed. */ \
14217 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14218 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14219 X(vfma, N_INV, 0x0000c10, N_INV), \
14220 X(vfms, N_INV, 0x0200c10, N_INV), \
14221 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14222 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14223 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14224 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14225 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14226 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14227 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14228 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14229 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14230 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14231 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14232 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14233 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14234 X(vshl, 0x0000400, N_INV, 0x0800510), \
14235 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14236 X(vand, 0x0000110, N_INV, 0x0800030), \
14237 X(vbic, 0x0100110, N_INV, 0x0800030), \
14238 X(veor, 0x1000110, N_INV, N_INV), \
14239 X(vorn, 0x0300110, N_INV, 0x0800010), \
14240 X(vorr, 0x0200110, N_INV, 0x0800010), \
14241 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14242 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14243 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14244 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14245 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14246 X(vst1, 0x0000000, 0x0800000, N_INV), \
14247 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14248 X(vst2, 0x0000100, 0x0800100, N_INV), \
14249 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14250 X(vst3, 0x0000200, 0x0800200, N_INV), \
14251 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14252 X(vst4, 0x0000300, 0x0800300, N_INV), \
14253 X(vmovn, 0x1b20200, N_INV, N_INV), \
14254 X(vtrn, 0x1b20080, N_INV, N_INV), \
14255 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14256 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14257 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14258 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14259 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14260 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14261 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14262 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14263 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14264 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14265 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14266 X(vseleq, 0xe000a00, N_INV, N_INV), \
14267 X(vselvs, 0xe100a00, N_INV, N_INV), \
14268 X(vselge, 0xe200a00, N_INV, N_INV), \
14269 X(vselgt, 0xe300a00, N_INV, N_INV), \
14270 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14271 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14272 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14273 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14274 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14275 X(aes, 0x3b00300, N_INV, N_INV), \
14276 X(sha3op, 0x2000c00, N_INV, N_INV), \
14277 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14278 X(sha2op, 0x3ba0380, N_INV, N_INV)
14282 #define X(OPC,I,F,S) N_MNEM_##OPC
14287 static const struct neon_tab_entry neon_enc_tab[] =
14289 #define X(OPC,I,F,S) { (I), (F), (S) }
14294 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14295 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14296 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14297 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14298 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14299 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14300 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14301 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14302 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14303 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14304 #define NEON_ENC_SINGLE_(X) \
14305 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14306 #define NEON_ENC_DOUBLE_(X) \
14307 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14308 #define NEON_ENC_FPV8_(X) \
14309 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14311 #define NEON_ENCODE(type, inst) \
14314 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14315 inst.is_neon = 1; \
14319 #define check_neon_suffixes \
14322 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14324 as_bad (_("invalid neon suffix for non neon instruction")); \
14330 /* Define shapes for instruction operands. The following mnemonic characters
14331 are used in this table:
14333 F - VFP S<n> register
14334 D - Neon D<n> register
14335 Q - Neon Q<n> register
14339 L - D<n> register list
14341 This table is used to generate various data:
14342 - enumerations of the form NS_DDR to be used as arguments to
14344 - a table classifying shapes into single, double, quad, mixed.
14345 - a table used to drive neon_select_shape. */
14347 #define NEON_SHAPE_DEF \
14348 X(4, (R, R, Q, Q), QUAD), \
14349 X(4, (Q, R, R, I), QUAD), \
14350 X(4, (R, R, S, S), QUAD), \
14351 X(4, (S, S, R, R), QUAD), \
14352 X(3, (Q, R, I), QUAD), \
14353 X(3, (I, Q, Q), QUAD), \
14354 X(3, (I, Q, R), QUAD), \
14355 X(3, (R, Q, Q), QUAD), \
14356 X(3, (D, D, D), DOUBLE), \
14357 X(3, (Q, Q, Q), QUAD), \
14358 X(3, (D, D, I), DOUBLE), \
14359 X(3, (Q, Q, I), QUAD), \
14360 X(3, (D, D, S), DOUBLE), \
14361 X(3, (Q, Q, S), QUAD), \
14362 X(3, (Q, Q, R), QUAD), \
14363 X(3, (R, R, Q), QUAD), \
14364 X(2, (R, Q), QUAD), \
14365 X(2, (D, D), DOUBLE), \
14366 X(2, (Q, Q), QUAD), \
14367 X(2, (D, S), DOUBLE), \
14368 X(2, (Q, S), QUAD), \
14369 X(2, (D, R), DOUBLE), \
14370 X(2, (Q, R), QUAD), \
14371 X(2, (D, I), DOUBLE), \
14372 X(2, (Q, I), QUAD), \
14373 X(3, (D, L, D), DOUBLE), \
14374 X(2, (D, Q), MIXED), \
14375 X(2, (Q, D), MIXED), \
14376 X(3, (D, Q, I), MIXED), \
14377 X(3, (Q, D, I), MIXED), \
14378 X(3, (Q, D, D), MIXED), \
14379 X(3, (D, Q, Q), MIXED), \
14380 X(3, (Q, Q, D), MIXED), \
14381 X(3, (Q, D, S), MIXED), \
14382 X(3, (D, Q, S), MIXED), \
14383 X(4, (D, D, D, I), DOUBLE), \
14384 X(4, (Q, Q, Q, I), QUAD), \
14385 X(4, (D, D, S, I), DOUBLE), \
14386 X(4, (Q, Q, S, I), QUAD), \
14387 X(2, (F, F), SINGLE), \
14388 X(3, (F, F, F), SINGLE), \
14389 X(2, (F, I), SINGLE), \
14390 X(2, (F, D), MIXED), \
14391 X(2, (D, F), MIXED), \
14392 X(3, (F, F, I), MIXED), \
14393 X(4, (R, R, F, F), SINGLE), \
14394 X(4, (F, F, R, R), SINGLE), \
14395 X(3, (D, R, R), DOUBLE), \
14396 X(3, (R, R, D), DOUBLE), \
14397 X(2, (S, R), SINGLE), \
14398 X(2, (R, S), SINGLE), \
14399 X(2, (F, R), SINGLE), \
14400 X(2, (R, F), SINGLE), \
14401 /* Half float shape supported so far. */\
14402 X (2, (H, D), MIXED), \
14403 X (2, (D, H), MIXED), \
14404 X (2, (H, F), MIXED), \
14405 X (2, (F, H), MIXED), \
14406 X (2, (H, H), HALF), \
14407 X (2, (H, R), HALF), \
14408 X (2, (R, H), HALF), \
14409 X (2, (H, I), HALF), \
14410 X (3, (H, H, H), HALF), \
14411 X (3, (H, F, I), MIXED), \
14412 X (3, (F, H, I), MIXED), \
14413 X (3, (D, H, H), MIXED), \
14414 X (3, (D, H, S), MIXED)
14416 #define S2(A,B) NS_##A##B
14417 #define S3(A,B,C) NS_##A##B##C
14418 #define S4(A,B,C,D) NS_##A##B##C##D
14420 #define X(N, L, C) S##N L
14433 enum neon_shape_class
14442 #define X(N, L, C) SC_##C
14444 static enum neon_shape_class neon_shape_class[] =
14463 /* Register widths of above. */
14464 static unsigned neon_shape_el_size[] =
14476 struct neon_shape_info
14479 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14482 #define S2(A,B) { SE_##A, SE_##B }
14483 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14484 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14486 #define X(N, L, C) { N, S##N L }
14488 static struct neon_shape_info neon_shape_tab[] =
14498 /* Bit masks used in type checking given instructions.
14499 'N_EQK' means the type must be the same as (or based on in some way) the key
14500 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14501 set, various other bits can be set as well in order to modify the meaning of
14502 the type constraint. */
14504 enum neon_type_mask
14528 N_KEY = 0x1000000, /* Key element (main type specifier). */
14529 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
14530 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
14531 N_UNT = 0x8000000, /* Must be explicitly untyped. */
14532 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14533 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14534 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14535 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14536 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14537 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14538 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14540 N_MAX_NONSPECIAL = N_P64
14543 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14545 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14546 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14547 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14548 #define N_S_32 (N_S8 | N_S16 | N_S32)
14549 #define N_F_16_32 (N_F16 | N_F32)
14550 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14551 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14552 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14553 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14554 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14555 #define N_F_MVE (N_F16 | N_F32)
14556 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14558 /* Pass this as the first type argument to neon_check_type to ignore types
14560 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14562 /* Select a "shape" for the current instruction (describing register types or
14563 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14564 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14565 function of operand parsing, so this function doesn't need to be called.
14566 Shapes should be listed in order of decreasing length. */
14568 static enum neon_shape
14569 neon_select_shape (enum neon_shape shape, ...)
14572 enum neon_shape first_shape = shape;
14574 /* Fix missing optional operands. FIXME: we don't know at this point how
14575 many arguments we should have, so this makes the assumption that we have
14576 > 1. This is true of all current Neon opcodes, I think, but may not be
14577 true in the future. */
14578 if (!inst.operands[1].present)
14579 inst.operands[1] = inst.operands[0];
14581 va_start (ap, shape);
14583 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
14588 for (j = 0; j < neon_shape_tab[shape].els; j++)
14590 if (!inst.operands[j].present)
14596 switch (neon_shape_tab[shape].el[j])
14598 /* If a .f16, .16, .u16, .s16 type specifier is given over
14599 a VFP single precision register operand, it's essentially
14600 means only half of the register is used.
14602 If the type specifier is given after the mnemonics, the
14603 information is stored in inst.vectype. If the type specifier
14604 is given after register operand, the information is stored
14605 in inst.operands[].vectype.
14607 When there is only one type specifier, and all the register
14608 operands are the same type of hardware register, the type
14609 specifier applies to all register operands.
14611 If no type specifier is given, the shape is inferred from
14612 operand information.
14615 vadd.f16 s0, s1, s2: NS_HHH
14616 vabs.f16 s0, s1: NS_HH
14617 vmov.f16 s0, r1: NS_HR
14618 vmov.f16 r0, s1: NS_RH
14619 vcvt.f16 r0, s1: NS_RH
14620 vcvt.f16.s32 s2, s2, #29: NS_HFI
14621 vcvt.f16.s32 s2, s2: NS_HF
14624 if (!(inst.operands[j].isreg
14625 && inst.operands[j].isvec
14626 && inst.operands[j].issingle
14627 && !inst.operands[j].isquad
14628 && ((inst.vectype.elems == 1
14629 && inst.vectype.el[0].size == 16)
14630 || (inst.vectype.elems > 1
14631 && inst.vectype.el[j].size == 16)
14632 || (inst.vectype.elems == 0
14633 && inst.operands[j].vectype.type != NT_invtype
14634 && inst.operands[j].vectype.size == 16))))
14639 if (!(inst.operands[j].isreg
14640 && inst.operands[j].isvec
14641 && inst.operands[j].issingle
14642 && !inst.operands[j].isquad
14643 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14644 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14645 || (inst.vectype.elems == 0
14646 && (inst.operands[j].vectype.size == 32
14647 || inst.operands[j].vectype.type == NT_invtype)))))
14652 if (!(inst.operands[j].isreg
14653 && inst.operands[j].isvec
14654 && !inst.operands[j].isquad
14655 && !inst.operands[j].issingle))
14660 if (!(inst.operands[j].isreg
14661 && !inst.operands[j].isvec))
14666 if (!(inst.operands[j].isreg
14667 && inst.operands[j].isvec
14668 && inst.operands[j].isquad
14669 && !inst.operands[j].issingle))
14674 if (!(!inst.operands[j].isreg
14675 && !inst.operands[j].isscalar))
14680 if (!(!inst.operands[j].isreg
14681 && inst.operands[j].isscalar))
14691 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
14692 /* We've matched all the entries in the shape table, and we don't
14693 have any left over operands which have not been matched. */
14699 if (shape == NS_NULL && first_shape != NS_NULL)
14700 first_error (_("invalid instruction shape"));
14705 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14706 means the Q bit should be set). */
14709 neon_quad (enum neon_shape shape)
14711 return neon_shape_class[shape] == SC_QUAD;
14715 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
14718 /* Allow modification to be made to types which are constrained to be
14719 based on the key element, based on bits set alongside N_EQK. */
14720 if ((typebits & N_EQK) != 0)
14722 if ((typebits & N_HLF) != 0)
14724 else if ((typebits & N_DBL) != 0)
14726 if ((typebits & N_SGN) != 0)
14727 *g_type = NT_signed;
14728 else if ((typebits & N_UNS) != 0)
14729 *g_type = NT_unsigned;
14730 else if ((typebits & N_INT) != 0)
14731 *g_type = NT_integer;
14732 else if ((typebits & N_FLT) != 0)
14733 *g_type = NT_float;
14734 else if ((typebits & N_SIZ) != 0)
14735 *g_type = NT_untyped;
14739 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14740 operand type, i.e. the single type specified in a Neon instruction when it
14741 is the only one given. */
14743 static struct neon_type_el
14744 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
14746 struct neon_type_el dest = *key;
14748 gas_assert ((thisarg & N_EQK) != 0);
14750 neon_modify_type_size (thisarg, &dest.type, &dest.size);
14755 /* Convert Neon type and size into compact bitmask representation. */
14757 static enum neon_type_mask
14758 type_chk_of_el_type (enum neon_el_type type, unsigned size)
14765 case 8: return N_8;
14766 case 16: return N_16;
14767 case 32: return N_32;
14768 case 64: return N_64;
14776 case 8: return N_I8;
14777 case 16: return N_I16;
14778 case 32: return N_I32;
14779 case 64: return N_I64;
14787 case 16: return N_F16;
14788 case 32: return N_F32;
14789 case 64: return N_F64;
14797 case 8: return N_P8;
14798 case 16: return N_P16;
14799 case 64: return N_P64;
14807 case 8: return N_S8;
14808 case 16: return N_S16;
14809 case 32: return N_S32;
14810 case 64: return N_S64;
14818 case 8: return N_U8;
14819 case 16: return N_U16;
14820 case 32: return N_U32;
14821 case 64: return N_U64;
14832 /* Convert compact Neon bitmask type representation to a type and size. Only
14833 handles the case where a single bit is set in the mask. */
14836 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
14837 enum neon_type_mask mask)
14839 if ((mask & N_EQK) != 0)
14842 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
14844 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
14846 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
14848 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
14853 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
14855 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
14856 *type = NT_unsigned;
14857 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
14858 *type = NT_integer;
14859 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
14860 *type = NT_untyped;
14861 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
14863 else if ((mask & (N_F_ALL)) != 0)
14871 /* Modify a bitmask of allowed types. This is only needed for type
14875 modify_types_allowed (unsigned allowed, unsigned mods)
14878 enum neon_el_type type;
14884 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
14886 if (el_type_of_type_chk (&type, &size,
14887 (enum neon_type_mask) (allowed & i)) == SUCCESS)
14889 neon_modify_type_size (mods, &type, &size);
14890 destmask |= type_chk_of_el_type (type, size);
14897 /* Check type and return type classification.
14898 The manual states (paraphrase): If one datatype is given, it indicates the
14900 - the second operand, if there is one
14901 - the operand, if there is no second operand
14902 - the result, if there are no operands.
14903 This isn't quite good enough though, so we use a concept of a "key" datatype
14904 which is set on a per-instruction basis, which is the one which matters when
14905 only one data type is written.
14906 Note: this function has side-effects (e.g. filling in missing operands). All
14907 Neon instructions should call it before performing bit encoding. */
14909 static struct neon_type_el
14910 neon_check_type (unsigned els, enum neon_shape ns, ...)
14913 unsigned i, pass, key_el = 0;
14914 unsigned types[NEON_MAX_TYPE_ELS];
14915 enum neon_el_type k_type = NT_invtype;
14916 unsigned k_size = -1u;
14917 struct neon_type_el badtype = {NT_invtype, -1};
14918 unsigned key_allowed = 0;
14920 /* Optional registers in Neon instructions are always (not) in operand 1.
14921 Fill in the missing operand here, if it was omitted. */
14922 if (els > 1 && !inst.operands[1].present)
14923 inst.operands[1] = inst.operands[0];
14925 /* Suck up all the varargs. */
14927 for (i = 0; i < els; i++)
14929 unsigned thisarg = va_arg (ap, unsigned);
14930 if (thisarg == N_IGNORE_TYPE)
14935 types[i] = thisarg;
14936 if ((thisarg & N_KEY) != 0)
14941 if (inst.vectype.elems > 0)
14942 for (i = 0; i < els; i++)
14943 if (inst.operands[i].vectype.type != NT_invtype)
14945 first_error (_("types specified in both the mnemonic and operands"));
14949 /* Duplicate inst.vectype elements here as necessary.
14950 FIXME: No idea if this is exactly the same as the ARM assembler,
14951 particularly when an insn takes one register and one non-register
14953 if (inst.vectype.elems == 1 && els > 1)
14956 inst.vectype.elems = els;
14957 inst.vectype.el[key_el] = inst.vectype.el[0];
14958 for (j = 0; j < els; j++)
14960 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14963 else if (inst.vectype.elems == 0 && els > 0)
14966 /* No types were given after the mnemonic, so look for types specified
14967 after each operand. We allow some flexibility here; as long as the
14968 "key" operand has a type, we can infer the others. */
14969 for (j = 0; j < els; j++)
14970 if (inst.operands[j].vectype.type != NT_invtype)
14971 inst.vectype.el[j] = inst.operands[j].vectype;
14973 if (inst.operands[key_el].vectype.type != NT_invtype)
14975 for (j = 0; j < els; j++)
14976 if (inst.operands[j].vectype.type == NT_invtype)
14977 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14982 first_error (_("operand types can't be inferred"));
14986 else if (inst.vectype.elems != els)
14988 first_error (_("type specifier has the wrong number of parts"));
14992 for (pass = 0; pass < 2; pass++)
14994 for (i = 0; i < els; i++)
14996 unsigned thisarg = types[i];
14997 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
14998 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
14999 enum neon_el_type g_type = inst.vectype.el[i].type;
15000 unsigned g_size = inst.vectype.el[i].size;
15002 /* Decay more-specific signed & unsigned types to sign-insensitive
15003 integer types if sign-specific variants are unavailable. */
15004 if ((g_type == NT_signed || g_type == NT_unsigned)
15005 && (types_allowed & N_SU_ALL) == 0)
15006 g_type = NT_integer;
15008 /* If only untyped args are allowed, decay any more specific types to
15009 them. Some instructions only care about signs for some element
15010 sizes, so handle that properly. */
15011 if (((types_allowed & N_UNT) == 0)
15012 && ((g_size == 8 && (types_allowed & N_8) != 0)
15013 || (g_size == 16 && (types_allowed & N_16) != 0)
15014 || (g_size == 32 && (types_allowed & N_32) != 0)
15015 || (g_size == 64 && (types_allowed & N_64) != 0)))
15016 g_type = NT_untyped;
15020 if ((thisarg & N_KEY) != 0)
15024 key_allowed = thisarg & ~N_KEY;
15026 /* Check architecture constraint on FP16 extension. */
15028 && k_type == NT_float
15029 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15031 inst.error = _(BAD_FP16);
15038 if ((thisarg & N_VFP) != 0)
15040 enum neon_shape_el regshape;
15041 unsigned regwidth, match;
15043 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15046 first_error (_("invalid instruction shape"));
15049 regshape = neon_shape_tab[ns].el[i];
15050 regwidth = neon_shape_el_size[regshape];
15052 /* In VFP mode, operands must match register widths. If we
15053 have a key operand, use its width, else use the width of
15054 the current operand. */
15060 /* FP16 will use a single precision register. */
15061 if (regwidth == 32 && match == 16)
15063 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15067 inst.error = _(BAD_FP16);
15072 if (regwidth != match)
15074 first_error (_("operand size must match register width"));
15079 if ((thisarg & N_EQK) == 0)
15081 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15083 if ((given_type & types_allowed) == 0)
15085 first_error (BAD_SIMD_TYPE);
15091 enum neon_el_type mod_k_type = k_type;
15092 unsigned mod_k_size = k_size;
15093 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15094 if (g_type != mod_k_type || g_size != mod_k_size)
15096 first_error (_("inconsistent types in Neon instruction"));
15104 return inst.vectype.el[key_el];
15107 /* Neon-style VFP instruction forwarding. */
15109 /* Thumb VFP instructions have 0xE in the condition field. */
15112 do_vfp_cond_or_thumb (void)
15117 inst.instruction |= 0xe0000000;
15119 inst.instruction |= inst.cond << 28;
15122 /* Look up and encode a simple mnemonic, for use as a helper function for the
15123 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15124 etc. It is assumed that operand parsing has already been done, and that the
15125 operands are in the form expected by the given opcode (this isn't necessarily
15126 the same as the form in which they were parsed, hence some massaging must
15127 take place before this function is called).
15128 Checks current arch version against that in the looked-up opcode. */
15131 do_vfp_nsyn_opcode (const char *opname)
15133 const struct asm_opcode *opcode;
15135 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
15140 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
15141 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15148 inst.instruction = opcode->tvalue;
15149 opcode->tencode ();
15153 inst.instruction = (inst.cond << 28) | opcode->avalue;
15154 opcode->aencode ();
15159 do_vfp_nsyn_add_sub (enum neon_shape rs)
15161 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15163 if (rs == NS_FFF || rs == NS_HHH)
15166 do_vfp_nsyn_opcode ("fadds");
15168 do_vfp_nsyn_opcode ("fsubs");
15170 /* ARMv8.2 fp16 instruction. */
15172 do_scalar_fp16_v82_encode ();
15177 do_vfp_nsyn_opcode ("faddd");
15179 do_vfp_nsyn_opcode ("fsubd");
15183 /* Check operand types to see if this is a VFP instruction, and if so call
15187 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15189 enum neon_shape rs;
15190 struct neon_type_el et;
15195 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15196 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15200 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15201 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15202 N_F_ALL | N_KEY | N_VFP);
15209 if (et.type != NT_invtype)
15220 do_vfp_nsyn_mla_mls (enum neon_shape rs)
15222 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15224 if (rs == NS_FFF || rs == NS_HHH)
15227 do_vfp_nsyn_opcode ("fmacs");
15229 do_vfp_nsyn_opcode ("fnmacs");
15231 /* ARMv8.2 fp16 instruction. */
15233 do_scalar_fp16_v82_encode ();
15238 do_vfp_nsyn_opcode ("fmacd");
15240 do_vfp_nsyn_opcode ("fnmacd");
15245 do_vfp_nsyn_fma_fms (enum neon_shape rs)
15247 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15249 if (rs == NS_FFF || rs == NS_HHH)
15252 do_vfp_nsyn_opcode ("ffmas");
15254 do_vfp_nsyn_opcode ("ffnmas");
15256 /* ARMv8.2 fp16 instruction. */
15258 do_scalar_fp16_v82_encode ();
15263 do_vfp_nsyn_opcode ("ffmad");
15265 do_vfp_nsyn_opcode ("ffnmad");
15270 do_vfp_nsyn_mul (enum neon_shape rs)
15272 if (rs == NS_FFF || rs == NS_HHH)
15274 do_vfp_nsyn_opcode ("fmuls");
15276 /* ARMv8.2 fp16 instruction. */
15278 do_scalar_fp16_v82_encode ();
15281 do_vfp_nsyn_opcode ("fmuld");
15285 do_vfp_nsyn_abs_neg (enum neon_shape rs)
15287 int is_neg = (inst.instruction & 0x80) != 0;
15288 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
15290 if (rs == NS_FF || rs == NS_HH)
15293 do_vfp_nsyn_opcode ("fnegs");
15295 do_vfp_nsyn_opcode ("fabss");
15297 /* ARMv8.2 fp16 instruction. */
15299 do_scalar_fp16_v82_encode ();
15304 do_vfp_nsyn_opcode ("fnegd");
15306 do_vfp_nsyn_opcode ("fabsd");
15310 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15311 insns belong to Neon, and are handled elsewhere. */
15314 do_vfp_nsyn_ldm_stm (int is_dbmode)
15316 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15320 do_vfp_nsyn_opcode ("fldmdbs");
15322 do_vfp_nsyn_opcode ("fldmias");
15327 do_vfp_nsyn_opcode ("fstmdbs");
15329 do_vfp_nsyn_opcode ("fstmias");
15334 do_vfp_nsyn_sqrt (void)
15336 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15337 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15339 if (rs == NS_FF || rs == NS_HH)
15341 do_vfp_nsyn_opcode ("fsqrts");
15343 /* ARMv8.2 fp16 instruction. */
15345 do_scalar_fp16_v82_encode ();
15348 do_vfp_nsyn_opcode ("fsqrtd");
15352 do_vfp_nsyn_div (void)
15354 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15355 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15356 N_F_ALL | N_KEY | N_VFP);
15358 if (rs == NS_FFF || rs == NS_HHH)
15360 do_vfp_nsyn_opcode ("fdivs");
15362 /* ARMv8.2 fp16 instruction. */
15364 do_scalar_fp16_v82_encode ();
15367 do_vfp_nsyn_opcode ("fdivd");
15371 do_vfp_nsyn_nmul (void)
15373 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15374 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15375 N_F_ALL | N_KEY | N_VFP);
15377 if (rs == NS_FFF || rs == NS_HHH)
15379 NEON_ENCODE (SINGLE, inst);
15380 do_vfp_sp_dyadic ();
15382 /* ARMv8.2 fp16 instruction. */
15384 do_scalar_fp16_v82_encode ();
15388 NEON_ENCODE (DOUBLE, inst);
15389 do_vfp_dp_rd_rn_rm ();
15391 do_vfp_cond_or_thumb ();
15395 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15399 neon_logbits (unsigned x)
15401 return ffs (x) - 4;
15404 #define LOW4(R) ((R) & 0xf)
15405 #define HI1(R) (((R) >> 4) & 1)
15408 mve_get_vcmp_vpt_cond (struct neon_type_el et)
15413 first_error (BAD_EL_TYPE);
15416 switch (inst.operands[0].imm)
15419 first_error (_("invalid condition"));
15441 /* only accept eq and ne. */
15442 if (inst.operands[0].imm > 1)
15444 first_error (_("invalid condition"));
15447 return inst.operands[0].imm;
15449 if (inst.operands[0].imm == 0x2)
15451 else if (inst.operands[0].imm == 0x8)
15455 first_error (_("invalid condition"));
15459 switch (inst.operands[0].imm)
15462 first_error (_("invalid condition"));
15478 /* Should be unreachable. */
15485 /* We are dealing with a vector predicated block. */
15486 if (inst.operands[0].present)
15488 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15489 struct neon_type_el et
15490 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15493 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15495 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15497 if (et.type == NT_invtype)
15500 if (et.type == NT_float)
15502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15504 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15505 inst.instruction |= (et.size == 16) << 28;
15506 inst.instruction |= 0x3 << 20;
15510 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15512 inst.instruction |= 1 << 28;
15513 inst.instruction |= neon_logbits (et.size) << 20;
15516 if (inst.operands[2].isquad)
15518 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15519 inst.instruction |= LOW4 (inst.operands[2].reg);
15520 inst.instruction |= (fcond & 0x2) >> 1;
15524 if (inst.operands[2].reg == REG_SP)
15525 as_tsktsk (MVE_BAD_SP);
15526 inst.instruction |= 1 << 6;
15527 inst.instruction |= (fcond & 0x2) << 4;
15528 inst.instruction |= inst.operands[2].reg;
15530 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15531 inst.instruction |= (fcond & 0x4) << 10;
15532 inst.instruction |= (fcond & 0x1) << 7;
15535 set_pred_insn_type (VPT_INSN);
15537 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15538 | ((inst.instruction & 0xe000) >> 13);
15539 now_pred.warn_deprecated = FALSE;
15540 now_pred.type = VECTOR_PRED;
15547 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15548 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15549 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15550 if (!inst.operands[2].present)
15551 first_error (_("MVE vector or ARM register expected"));
15552 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15554 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15555 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15556 && inst.operands[1].isquad)
15558 inst.instruction = N_MNEM_vcmp;
15562 if (inst.cond > COND_ALWAYS)
15563 inst.pred_insn_type = INSIDE_VPT_INSN;
15565 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15567 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15568 struct neon_type_el et
15569 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15572 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15573 && !inst.operands[2].iszr, BAD_PC);
15575 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15577 inst.instruction = 0xee010f00;
15578 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15579 inst.instruction |= (fcond & 0x4) << 10;
15580 inst.instruction |= (fcond & 0x1) << 7;
15581 if (et.type == NT_float)
15583 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15585 inst.instruction |= (et.size == 16) << 28;
15586 inst.instruction |= 0x3 << 20;
15590 inst.instruction |= 1 << 28;
15591 inst.instruction |= neon_logbits (et.size) << 20;
15593 if (inst.operands[2].isquad)
15595 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15596 inst.instruction |= (fcond & 0x2) >> 1;
15597 inst.instruction |= LOW4 (inst.operands[2].reg);
15601 if (inst.operands[2].reg == REG_SP)
15602 as_tsktsk (MVE_BAD_SP);
15603 inst.instruction |= 1 << 6;
15604 inst.instruction |= (fcond & 0x2) << 4;
15605 inst.instruction |= inst.operands[2].reg;
15613 do_mve_vmaxa_vmina (void)
15615 if (inst.cond > COND_ALWAYS)
15616 inst.pred_insn_type = INSIDE_VPT_INSN;
15618 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15620 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15621 struct neon_type_el et
15622 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15624 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15625 inst.instruction |= neon_logbits (et.size) << 18;
15626 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15627 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15628 inst.instruction |= LOW4 (inst.operands[1].reg);
15633 do_mve_vfmas (void)
15635 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15636 struct neon_type_el et
15637 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15639 if (inst.cond > COND_ALWAYS)
15640 inst.pred_insn_type = INSIDE_VPT_INSN;
15642 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15644 if (inst.operands[2].reg == REG_SP)
15645 as_tsktsk (MVE_BAD_SP);
15646 else if (inst.operands[2].reg == REG_PC)
15647 as_tsktsk (MVE_BAD_PC);
15649 inst.instruction |= (et.size == 16) << 28;
15650 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15651 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15652 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15653 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15654 inst.instruction |= inst.operands[2].reg;
15659 do_mve_viddup (void)
15661 if (inst.cond > COND_ALWAYS)
15662 inst.pred_insn_type = INSIDE_VPT_INSN;
15664 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15666 unsigned imm = inst.relocs[0].exp.X_add_number;
15667 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
15668 _("immediate must be either 1, 2, 4 or 8"));
15670 enum neon_shape rs;
15671 struct neon_type_el et;
15673 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
15675 rs = neon_select_shape (NS_QRI, NS_NULL);
15676 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
15681 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
15682 if (inst.operands[2].reg == REG_SP)
15683 as_tsktsk (MVE_BAD_SP);
15684 else if (inst.operands[2].reg == REG_PC)
15685 first_error (BAD_PC);
15687 rs = neon_select_shape (NS_QRRI, NS_NULL);
15688 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
15689 Rm = inst.operands[2].reg >> 1;
15691 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15692 inst.instruction |= neon_logbits (et.size) << 20;
15693 inst.instruction |= inst.operands[1].reg << 16;
15694 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15695 inst.instruction |= (imm > 2) << 7;
15696 inst.instruction |= Rm << 1;
15697 inst.instruction |= (imm == 2 || imm == 8);
15702 do_mve_vmaxnma_vminnma (void)
15704 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15705 struct neon_type_el et
15706 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
15708 if (inst.cond > COND_ALWAYS)
15709 inst.pred_insn_type = INSIDE_VPT_INSN;
15711 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15713 inst.instruction |= (et.size == 16) << 28;
15714 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15715 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15716 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15717 inst.instruction |= LOW4 (inst.operands[1].reg);
15722 do_mve_vcmul (void)
15724 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
15725 struct neon_type_el et
15726 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
15728 if (inst.cond > COND_ALWAYS)
15729 inst.pred_insn_type = INSIDE_VPT_INSN;
15731 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15733 unsigned rot = inst.relocs[0].exp.X_add_number;
15734 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
15735 _("immediate out of range"));
15737 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
15738 || inst.operands[0].reg == inst.operands[2].reg))
15739 as_tsktsk (BAD_MVE_SRCDEST);
15741 inst.instruction |= (et.size == 32) << 28;
15742 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15743 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15744 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15745 inst.instruction |= (rot > 90) << 12;
15746 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15747 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15748 inst.instruction |= LOW4 (inst.operands[2].reg);
15749 inst.instruction |= (rot == 90 || rot == 270);
15754 do_vfp_nsyn_cmp (void)
15756 enum neon_shape rs;
15757 if (!inst.operands[0].isreg)
15764 constraint (inst.operands[2].present, BAD_SYNTAX);
15765 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
15769 if (inst.operands[1].isreg)
15771 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15772 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15774 if (rs == NS_FF || rs == NS_HH)
15776 NEON_ENCODE (SINGLE, inst);
15777 do_vfp_sp_monadic ();
15781 NEON_ENCODE (DOUBLE, inst);
15782 do_vfp_dp_rd_rm ();
15787 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
15788 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
15790 switch (inst.instruction & 0x0fffffff)
15793 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
15796 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
15802 if (rs == NS_FI || rs == NS_HI)
15804 NEON_ENCODE (SINGLE, inst);
15805 do_vfp_sp_compare_z ();
15809 NEON_ENCODE (DOUBLE, inst);
15813 do_vfp_cond_or_thumb ();
15815 /* ARMv8.2 fp16 instruction. */
15816 if (rs == NS_HI || rs == NS_HH)
15817 do_scalar_fp16_v82_encode ();
15821 nsyn_insert_sp (void)
15823 inst.operands[1] = inst.operands[0];
15824 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
15825 inst.operands[0].reg = REG_SP;
15826 inst.operands[0].isreg = 1;
15827 inst.operands[0].writeback = 1;
15828 inst.operands[0].present = 1;
15832 do_vfp_nsyn_push (void)
15836 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15837 _("register list must contain at least 1 and at most 16 "
15840 if (inst.operands[1].issingle)
15841 do_vfp_nsyn_opcode ("fstmdbs");
15843 do_vfp_nsyn_opcode ("fstmdbd");
15847 do_vfp_nsyn_pop (void)
15851 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15852 _("register list must contain at least 1 and at most 16 "
15855 if (inst.operands[1].issingle)
15856 do_vfp_nsyn_opcode ("fldmias");
15858 do_vfp_nsyn_opcode ("fldmiad");
15861 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15862 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15865 neon_dp_fixup (struct arm_it* insn)
15867 unsigned int i = insn->instruction;
15872 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15883 insn->instruction = i;
15887 mve_encode_qqr (int size, int U, int fp)
15889 if (inst.operands[2].reg == REG_SP)
15890 as_tsktsk (MVE_BAD_SP);
15891 else if (inst.operands[2].reg == REG_PC)
15892 as_tsktsk (MVE_BAD_PC);
15897 if (((unsigned)inst.instruction) == 0xd00)
15898 inst.instruction = 0xee300f40;
15900 else if (((unsigned)inst.instruction) == 0x200d00)
15901 inst.instruction = 0xee301f40;
15903 /* Setting size which is 1 for F16 and 0 for F32. */
15904 inst.instruction |= (size == 16) << 28;
15909 if (((unsigned)inst.instruction) == 0x800)
15910 inst.instruction = 0xee010f40;
15912 else if (((unsigned)inst.instruction) == 0x1000800)
15913 inst.instruction = 0xee011f40;
15915 else if (((unsigned)inst.instruction) == 0)
15916 inst.instruction = 0xee000f40;
15918 else if (((unsigned)inst.instruction) == 0x200)
15919 inst.instruction = 0xee001f40;
15922 inst.instruction |= U << 28;
15924 /* Setting bits for size. */
15925 inst.instruction |= neon_logbits (size) << 20;
15927 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15928 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15929 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15930 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15931 inst.instruction |= inst.operands[2].reg;
15936 mve_encode_rqq (unsigned bit28, unsigned size)
15938 inst.instruction |= bit28 << 28;
15939 inst.instruction |= neon_logbits (size) << 20;
15940 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15941 inst.instruction |= inst.operands[0].reg << 12;
15942 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15943 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15944 inst.instruction |= LOW4 (inst.operands[2].reg);
15949 mve_encode_qqq (int ubit, int size)
15952 inst.instruction |= (ubit != 0) << 28;
15953 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15954 inst.instruction |= neon_logbits (size) << 20;
15955 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15956 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15957 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15958 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15959 inst.instruction |= LOW4 (inst.operands[2].reg);
15965 mve_encode_rq (unsigned bit28, unsigned size)
15967 inst.instruction |= bit28 << 28;
15968 inst.instruction |= neon_logbits (size) << 18;
15969 inst.instruction |= inst.operands[0].reg << 12;
15970 inst.instruction |= LOW4 (inst.operands[1].reg);
15975 mve_encode_rrqq (unsigned U, unsigned size)
15977 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
15979 inst.instruction |= U << 28;
15980 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
15981 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
15982 inst.instruction |= (size == 32) << 16;
15983 inst.instruction |= inst.operands[0].reg << 12;
15984 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
15985 inst.instruction |= inst.operands[3].reg;
15989 /* Encode insns with bit pattern:
15991 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15992 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15994 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15995 different meaning for some instruction. */
15998 neon_three_same (int isquad, int ubit, int size)
16000 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16001 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16002 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16003 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16004 inst.instruction |= LOW4 (inst.operands[2].reg);
16005 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16006 inst.instruction |= (isquad != 0) << 6;
16007 inst.instruction |= (ubit != 0) << 24;
16009 inst.instruction |= neon_logbits (size) << 20;
16011 neon_dp_fixup (&inst);
16014 /* Encode instructions of the form:
16016 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16017 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16019 Don't write size if SIZE == -1. */
16022 neon_two_same (int qbit, int ubit, int size)
16024 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16025 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16026 inst.instruction |= LOW4 (inst.operands[1].reg);
16027 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16028 inst.instruction |= (qbit != 0) << 6;
16029 inst.instruction |= (ubit != 0) << 24;
16032 inst.instruction |= neon_logbits (size) << 18;
16034 neon_dp_fixup (&inst);
16037 enum vfp_or_neon_is_neon_bits
16040 NEON_CHECK_ARCH = 2,
16041 NEON_CHECK_ARCH8 = 4
16044 /* Call this function if an instruction which may have belonged to the VFP or
16045 Neon instruction sets, but turned out to be a Neon instruction (due to the
16046 operand types involved, etc.). We have to check and/or fix-up a couple of
16049 - Make sure the user hasn't attempted to make a Neon instruction
16051 - Alter the value in the condition code field if necessary.
16052 - Make sure that the arch supports Neon instructions.
16054 Which of these operations take place depends on bits from enum
16055 vfp_or_neon_is_neon_bits.
16057 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16058 current instruction's condition is COND_ALWAYS, the condition field is
16059 changed to inst.uncond_value. This is necessary because instructions shared
16060 between VFP and Neon may be conditional for the VFP variants only, and the
16061 unconditional Neon version must have, e.g., 0xF in the condition field. */
16064 vfp_or_neon_is_neon (unsigned check)
16066 /* Conditions are always legal in Thumb mode (IT blocks). */
16067 if (!thumb_mode && (check & NEON_CHECK_CC))
16069 if (inst.cond != COND_ALWAYS)
16071 first_error (_(BAD_COND));
16074 if (inst.uncond_value != -1)
16075 inst.instruction |= inst.uncond_value << 28;
16079 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16080 || ((check & NEON_CHECK_ARCH8)
16081 && !mark_feature_used (&fpu_neon_ext_armv8)))
16083 first_error (_(BAD_FPU));
16091 check_simd_pred_availability (int fp, unsigned check)
16093 if (inst.cond > COND_ALWAYS)
16095 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16097 inst.error = BAD_FPU;
16100 inst.pred_insn_type = INSIDE_VPT_INSN;
16102 else if (inst.cond < COND_ALWAYS)
16104 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16105 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16106 else if (vfp_or_neon_is_neon (check) == FAIL)
16111 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16112 && vfp_or_neon_is_neon (check) == FAIL)
16115 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16116 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16121 /* Neon instruction encoders, in approximate order of appearance. */
16124 do_neon_dyadic_i_su (void)
16126 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16129 enum neon_shape rs;
16130 struct neon_type_el et;
16131 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16132 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16134 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16136 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16140 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16142 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16146 do_neon_dyadic_i64_su (void)
16148 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16149 struct neon_type_el et = neon_check_type (3, rs,
16150 N_EQK, N_EQK, N_SU_ALL | N_KEY);
16151 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16155 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
16158 unsigned size = et.size >> 3;
16159 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16160 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16161 inst.instruction |= LOW4 (inst.operands[1].reg);
16162 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16163 inst.instruction |= (isquad != 0) << 6;
16164 inst.instruction |= immbits << 16;
16165 inst.instruction |= (size >> 3) << 7;
16166 inst.instruction |= (size & 0x7) << 19;
16168 inst.instruction |= (uval != 0) << 24;
16170 neon_dp_fixup (&inst);
16174 do_neon_shl_imm (void)
16176 if (!inst.operands[2].isreg)
16178 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16179 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16180 int imm = inst.operands[2].imm;
16182 constraint (imm < 0 || (unsigned)imm >= et.size,
16183 _("immediate out of range for shift"));
16184 NEON_ENCODE (IMMED, inst);
16185 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
16189 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16190 struct neon_type_el et = neon_check_type (3, rs,
16191 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16194 /* VSHL/VQSHL 3-register variants have syntax such as:
16196 whereas other 3-register operations encoded by neon_three_same have
16199 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
16201 tmp = inst.operands[2].reg;
16202 inst.operands[2].reg = inst.operands[1].reg;
16203 inst.operands[1].reg = tmp;
16204 NEON_ENCODE (INTEGER, inst);
16205 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16210 do_neon_qshl_imm (void)
16212 if (!inst.operands[2].isreg)
16214 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16215 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16216 int imm = inst.operands[2].imm;
16218 constraint (imm < 0 || (unsigned)imm >= et.size,
16219 _("immediate out of range for shift"));
16220 NEON_ENCODE (IMMED, inst);
16221 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
16225 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16226 struct neon_type_el et = neon_check_type (3, rs,
16227 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16230 /* See note in do_neon_shl_imm. */
16231 tmp = inst.operands[2].reg;
16232 inst.operands[2].reg = inst.operands[1].reg;
16233 inst.operands[1].reg = tmp;
16234 NEON_ENCODE (INTEGER, inst);
16235 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16240 do_neon_rshl (void)
16242 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16243 struct neon_type_el et = neon_check_type (3, rs,
16244 N_EQK, N_EQK, N_SU_ALL | N_KEY);
16247 tmp = inst.operands[2].reg;
16248 inst.operands[2].reg = inst.operands[1].reg;
16249 inst.operands[1].reg = tmp;
16250 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16254 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
16256 /* Handle .I8 pseudo-instructions. */
16259 /* Unfortunately, this will make everything apart from zero out-of-range.
16260 FIXME is this the intended semantics? There doesn't seem much point in
16261 accepting .I8 if so. */
16262 immediate |= immediate << 8;
16268 if (immediate == (immediate & 0x000000ff))
16270 *immbits = immediate;
16273 else if (immediate == (immediate & 0x0000ff00))
16275 *immbits = immediate >> 8;
16278 else if (immediate == (immediate & 0x00ff0000))
16280 *immbits = immediate >> 16;
16283 else if (immediate == (immediate & 0xff000000))
16285 *immbits = immediate >> 24;
16288 if ((immediate & 0xffff) != (immediate >> 16))
16289 goto bad_immediate;
16290 immediate &= 0xffff;
16293 if (immediate == (immediate & 0x000000ff))
16295 *immbits = immediate;
16298 else if (immediate == (immediate & 0x0000ff00))
16300 *immbits = immediate >> 8;
16305 first_error (_("immediate value out of range"));
16310 do_neon_logic (void)
16312 if (inst.operands[2].present && inst.operands[2].isreg)
16314 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16316 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16319 else if (rs != NS_QQQ
16320 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16321 first_error (BAD_FPU);
16323 neon_check_type (3, rs, N_IGNORE_TYPE);
16324 /* U bit and size field were set as part of the bitmask. */
16325 NEON_ENCODE (INTEGER, inst);
16326 neon_three_same (neon_quad (rs), 0, -1);
16330 const int three_ops_form = (inst.operands[2].present
16331 && !inst.operands[2].isreg);
16332 const int immoperand = (three_ops_form ? 2 : 1);
16333 enum neon_shape rs = (three_ops_form
16334 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
16335 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
16336 /* Because neon_select_shape makes the second operand a copy of the first
16337 if the second operand is not present. */
16339 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16342 else if (rs != NS_QQI
16343 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16344 first_error (BAD_FPU);
16346 struct neon_type_el et;
16347 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16348 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
16350 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
16353 if (et.type == NT_invtype)
16355 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
16360 if (three_ops_form)
16361 constraint (inst.operands[0].reg != inst.operands[1].reg,
16362 _("first and second operands shall be the same register"));
16364 NEON_ENCODE (IMMED, inst);
16366 immbits = inst.operands[immoperand].imm;
16369 /* .i64 is a pseudo-op, so the immediate must be a repeating
16371 if (immbits != (inst.operands[immoperand].regisimm ?
16372 inst.operands[immoperand].reg : 0))
16374 /* Set immbits to an invalid constant. */
16375 immbits = 0xdeadbeef;
16382 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16386 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16390 /* Pseudo-instruction for VBIC. */
16391 neon_invert_size (&immbits, 0, et.size);
16392 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16396 /* Pseudo-instruction for VORR. */
16397 neon_invert_size (&immbits, 0, et.size);
16398 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16408 inst.instruction |= neon_quad (rs) << 6;
16409 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16410 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16411 inst.instruction |= cmode << 8;
16412 neon_write_immbits (immbits);
16414 neon_dp_fixup (&inst);
16419 do_neon_bitfield (void)
16421 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16422 neon_check_type (3, rs, N_IGNORE_TYPE);
16423 neon_three_same (neon_quad (rs), 0, -1);
16427 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
16430 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16431 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
16433 if (et.type == NT_float)
16435 NEON_ENCODE (FLOAT, inst);
16437 mve_encode_qqr (et.size, 0, 1);
16439 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
16443 NEON_ENCODE (INTEGER, inst);
16445 mve_encode_qqr (et.size, 0, 0);
16447 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
16453 do_neon_dyadic_if_su_d (void)
16455 /* This version only allow D registers, but that constraint is enforced during
16456 operand parsing so we don't need to do anything extra here. */
16457 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
16461 do_neon_dyadic_if_i_d (void)
16463 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16464 affected if we specify unsigned args. */
16465 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
16469 do_mve_vstr_vldr_QI (int size, int elsize, int load)
16471 constraint (size < 32, BAD_ADDR_MODE);
16472 constraint (size != elsize, BAD_EL_TYPE);
16473 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16474 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
16475 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
16476 _("destination register and offset register may not be the"
16479 int imm = inst.relocs[0].exp.X_add_number;
16486 constraint ((imm % (size / 8) != 0)
16487 || imm > (0x7f << neon_logbits (size)),
16488 (size == 32) ? _("immediate must be a multiple of 4 in the"
16489 " range of +/-[0,508]")
16490 : _("immediate must be a multiple of 8 in the"
16491 " range of +/-[0,1016]"));
16492 inst.instruction |= 0x11 << 24;
16493 inst.instruction |= add << 23;
16494 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16495 inst.instruction |= inst.operands[1].writeback << 21;
16496 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16497 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16498 inst.instruction |= 1 << 12;
16499 inst.instruction |= (size == 64) << 8;
16500 inst.instruction &= 0xffffff00;
16501 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16502 inst.instruction |= imm >> neon_logbits (size);
16506 do_mve_vstr_vldr_RQ (int size, int elsize, int load)
16508 unsigned os = inst.operands[1].imm >> 5;
16509 constraint (os != 0 && size == 8,
16510 _("can not shift offsets when accessing less than half-word"));
16511 constraint (os && os != neon_logbits (size),
16512 _("shift immediate must be 1, 2 or 3 for half-word, word"
16513 " or double-word accesses respectively"));
16514 if (inst.operands[1].reg == REG_PC)
16515 as_tsktsk (MVE_BAD_PC);
16520 constraint (elsize >= 64, BAD_EL_TYPE);
16523 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16527 constraint (elsize != size, BAD_EL_TYPE);
16532 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
16536 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
16537 _("destination register and offset register may not be"
16539 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
16541 constraint (inst.vectype.el[0].type != NT_unsigned
16542 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
16543 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
16547 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
16550 inst.instruction |= 1 << 23;
16551 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16552 inst.instruction |= inst.operands[1].reg << 16;
16553 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16554 inst.instruction |= neon_logbits (elsize) << 7;
16555 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
16556 inst.instruction |= LOW4 (inst.operands[1].imm);
16557 inst.instruction |= !!os;
16561 do_mve_vstr_vldr_RI (int size, int elsize, int load)
16563 enum neon_el_type type = inst.vectype.el[0].type;
16565 constraint (size >= 64, BAD_ADDR_MODE);
16569 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16572 constraint (elsize != size, BAD_EL_TYPE);
16579 constraint (elsize != size && type != NT_unsigned
16580 && type != NT_signed, BAD_EL_TYPE);
16584 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
16587 int imm = inst.relocs[0].exp.X_add_number;
16595 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
16600 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16603 constraint (1, _("immediate must be a multiple of 2 in the"
16604 " range of +/-[0,254]"));
16607 constraint (1, _("immediate must be a multiple of 4 in the"
16608 " range of +/-[0,508]"));
16613 if (size != elsize)
16615 constraint (inst.operands[1].reg > 7, BAD_HIREG);
16616 constraint (inst.operands[0].reg > 14,
16617 _("MVE vector register in the range [Q0..Q7] expected"));
16618 inst.instruction |= (load && type == NT_unsigned) << 28;
16619 inst.instruction |= (size == 16) << 19;
16620 inst.instruction |= neon_logbits (elsize) << 7;
16624 if (inst.operands[1].reg == REG_PC)
16625 as_tsktsk (MVE_BAD_PC);
16626 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
16627 as_tsktsk (MVE_BAD_SP);
16628 inst.instruction |= 1 << 12;
16629 inst.instruction |= neon_logbits (size) << 7;
16631 inst.instruction |= inst.operands[1].preind << 24;
16632 inst.instruction |= add << 23;
16633 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16634 inst.instruction |= inst.operands[1].writeback << 21;
16635 inst.instruction |= inst.operands[1].reg << 16;
16636 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16637 inst.instruction &= 0xffffff80;
16638 inst.instruction |= imm >> neon_logbits (size);
16643 do_mve_vstr_vldr (void)
16648 if (inst.cond > COND_ALWAYS)
16649 inst.pred_insn_type = INSIDE_VPT_INSN;
16651 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16653 switch (inst.instruction)
16660 /* fall through. */
16666 /* fall through. */
16672 /* fall through. */
16678 /* fall through. */
16683 unsigned elsize = inst.vectype.el[0].size;
16685 if (inst.operands[1].isquad)
16687 /* We are dealing with [Q, imm]{!} cases. */
16688 do_mve_vstr_vldr_QI (size, elsize, load);
16692 if (inst.operands[1].immisreg == 2)
16694 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16695 do_mve_vstr_vldr_RQ (size, elsize, load);
16697 else if (!inst.operands[1].immisreg)
16699 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16700 do_mve_vstr_vldr_RI (size, elsize, load);
16703 constraint (1, BAD_ADDR_MODE);
16710 do_mve_vst_vld (void)
16712 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16715 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
16716 || inst.relocs[0].exp.X_add_number != 0
16717 || inst.operands[1].immisreg != 0,
16719 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
16720 if (inst.operands[1].reg == REG_PC)
16721 as_tsktsk (MVE_BAD_PC);
16722 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
16723 as_tsktsk (MVE_BAD_SP);
16726 /* These instructions are one of the "exceptions" mentioned in
16727 handle_pred_state. They are MVE instructions that are not VPT compatible
16728 and do not accept a VPT code, thus appending such a code is a syntax
16730 if (inst.cond > COND_ALWAYS)
16731 first_error (BAD_SYNTAX);
16732 /* If we append a scalar condition code we can set this to
16733 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16734 else if (inst.cond < COND_ALWAYS)
16735 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16737 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
16739 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16740 inst.instruction |= inst.operands[1].writeback << 21;
16741 inst.instruction |= inst.operands[1].reg << 16;
16742 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16743 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
16748 do_mve_vaddlv (void)
16750 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
16751 struct neon_type_el et
16752 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
16754 if (et.type == NT_invtype)
16755 first_error (BAD_EL_TYPE);
16757 if (inst.cond > COND_ALWAYS)
16758 inst.pred_insn_type = INSIDE_VPT_INSN;
16760 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16762 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16764 inst.instruction |= (et.type == NT_unsigned) << 28;
16765 inst.instruction |= inst.operands[1].reg << 19;
16766 inst.instruction |= inst.operands[0].reg << 12;
16767 inst.instruction |= inst.operands[2].reg;
16772 do_neon_dyadic_if_su (void)
16774 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16775 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
16778 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
16779 || inst.instruction == ((unsigned) N_MNEM_vmin))
16780 && et.type == NT_float
16781 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
16783 if (check_simd_pred_availability (et.type == NT_float,
16784 NEON_CHECK_ARCH | NEON_CHECK_CC))
16787 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
16791 do_neon_addsub_if_i (void)
16793 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
16794 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
16797 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16798 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
16799 N_EQK, N_IF_32 | N_I64 | N_KEY);
16801 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
16802 /* If we are parsing Q registers and the element types match MVE, which NEON
16803 also supports, then we must check whether this is an instruction that can
16804 be used by both MVE/NEON. This distinction can be made based on whether
16805 they are predicated or not. */
16806 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
16808 if (check_simd_pred_availability (et.type == NT_float,
16809 NEON_CHECK_ARCH | NEON_CHECK_CC))
16814 /* If they are either in a D register or are using an unsupported. */
16816 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16820 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16821 affected if we specify unsigned args. */
16822 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
16825 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16827 V<op> A,B (A is operand 0, B is operand 2)
16832 so handle that case specially. */
16835 neon_exchange_operands (void)
16837 if (inst.operands[1].present)
16839 void *scratch = xmalloc (sizeof (inst.operands[0]));
16841 /* Swap operands[1] and operands[2]. */
16842 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
16843 inst.operands[1] = inst.operands[2];
16844 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
16849 inst.operands[1] = inst.operands[2];
16850 inst.operands[2] = inst.operands[0];
16855 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
16857 if (inst.operands[2].isreg)
16860 neon_exchange_operands ();
16861 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
16865 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16866 struct neon_type_el et = neon_check_type (2, rs,
16867 N_EQK | N_SIZ, immtypes | N_KEY);
16869 NEON_ENCODE (IMMED, inst);
16870 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16871 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16872 inst.instruction |= LOW4 (inst.operands[1].reg);
16873 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16874 inst.instruction |= neon_quad (rs) << 6;
16875 inst.instruction |= (et.type == NT_float) << 10;
16876 inst.instruction |= neon_logbits (et.size) << 18;
16878 neon_dp_fixup (&inst);
16885 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
16889 do_neon_cmp_inv (void)
16891 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
16897 neon_compare (N_IF_32, N_IF_32, FALSE);
16900 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16901 scalars, which are encoded in 5 bits, M : Rm.
16902 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16903 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16906 Dot Product instructions are similar to multiply instructions except elsize
16907 should always be 32.
16909 This function translates SCALAR, which is GAS's internal encoding of indexed
16910 scalar register, to raw encoding. There is also register and index range
16911 check based on ELSIZE. */
16914 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
16916 unsigned regno = NEON_SCALAR_REG (scalar);
16917 unsigned elno = NEON_SCALAR_INDEX (scalar);
16922 if (regno > 7 || elno > 3)
16924 return regno | (elno << 3);
16927 if (regno > 15 || elno > 1)
16929 return regno | (elno << 4);
16933 first_error (_("scalar out of range for multiply instruction"));
16939 /* Encode multiply / multiply-accumulate scalar instructions. */
16942 neon_mul_mac (struct neon_type_el et, int ubit)
16946 /* Give a more helpful error message if we have an invalid type. */
16947 if (et.type == NT_invtype)
16950 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
16951 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16952 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16953 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16954 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16955 inst.instruction |= LOW4 (scalar);
16956 inst.instruction |= HI1 (scalar) << 5;
16957 inst.instruction |= (et.type == NT_float) << 8;
16958 inst.instruction |= neon_logbits (et.size) << 20;
16959 inst.instruction |= (ubit != 0) << 24;
16961 neon_dp_fixup (&inst);
16965 do_neon_mac_maybe_scalar (void)
16967 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
16970 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16973 if (inst.operands[2].isscalar)
16975 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
16976 struct neon_type_el et = neon_check_type (3, rs,
16977 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
16978 NEON_ENCODE (SCALAR, inst);
16979 neon_mul_mac (et, neon_quad (rs));
16983 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16984 affected if we specify unsigned args. */
16985 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
16990 do_neon_fmac (void)
16992 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
16993 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
16996 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
16999 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17001 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17002 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17007 if (inst.operands[2].reg == REG_SP)
17008 as_tsktsk (MVE_BAD_SP);
17009 else if (inst.operands[2].reg == REG_PC)
17010 as_tsktsk (MVE_BAD_PC);
17012 inst.instruction = 0xee310e40;
17013 inst.instruction |= (et.size == 16) << 28;
17014 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17015 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17016 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17017 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17018 inst.instruction |= inst.operands[2].reg;
17025 constraint (!inst.operands[2].isvec, BAD_FPU);
17028 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17034 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17035 struct neon_type_el et = neon_check_type (3, rs,
17036 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17037 neon_three_same (neon_quad (rs), 0, et.size);
17040 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17041 same types as the MAC equivalents. The polynomial type for this instruction
17042 is encoded the same as the integer type. */
17047 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17050 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17053 if (inst.operands[2].isscalar)
17054 do_neon_mac_maybe_scalar ();
17056 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17060 do_neon_qdmulh (void)
17062 if (inst.operands[2].isscalar)
17064 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17065 struct neon_type_el et = neon_check_type (3, rs,
17066 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17067 NEON_ENCODE (SCALAR, inst);
17068 neon_mul_mac (et, neon_quad (rs));
17072 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17073 struct neon_type_el et = neon_check_type (3, rs,
17074 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17075 NEON_ENCODE (INTEGER, inst);
17076 /* The U bit (rounding) comes from bit mask. */
17077 neon_three_same (neon_quad (rs), 0, et.size);
17082 do_mve_vaddv (void)
17084 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17085 struct neon_type_el et
17086 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17088 if (et.type == NT_invtype)
17089 first_error (BAD_EL_TYPE);
17091 if (inst.cond > COND_ALWAYS)
17092 inst.pred_insn_type = INSIDE_VPT_INSN;
17094 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17096 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17098 mve_encode_rq (et.type == NT_unsigned, et.size);
17102 do_mve_vhcadd (void)
17104 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17105 struct neon_type_el et
17106 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17108 if (inst.cond > COND_ALWAYS)
17109 inst.pred_insn_type = INSIDE_VPT_INSN;
17111 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17113 unsigned rot = inst.relocs[0].exp.X_add_number;
17114 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17116 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17117 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17118 "operand makes instruction UNPREDICTABLE"));
17120 mve_encode_qqq (0, et.size);
17121 inst.instruction |= (rot == 270) << 12;
17128 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17129 struct neon_type_el et
17130 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17132 if (et.type == NT_invtype)
17133 first_error (BAD_EL_TYPE);
17135 if (inst.cond > COND_ALWAYS)
17136 inst.pred_insn_type = INSIDE_VPT_INSN;
17138 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17140 mve_encode_qqq (0, 64);
17144 do_mve_vbrsr (void)
17146 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17147 struct neon_type_el et
17148 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17150 if (inst.cond > COND_ALWAYS)
17151 inst.pred_insn_type = INSIDE_VPT_INSN;
17153 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17155 mve_encode_qqr (et.size, 0, 0);
17161 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
17163 if (inst.cond > COND_ALWAYS)
17164 inst.pred_insn_type = INSIDE_VPT_INSN;
17166 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17168 mve_encode_qqq (1, 64);
17172 do_mve_vmull (void)
17175 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
17176 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
17177 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
17178 && inst.cond == COND_ALWAYS
17179 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
17184 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17185 N_SUF_32 | N_F64 | N_P8
17186 | N_P16 | N_I_MVE | N_KEY);
17187 if (((et.type == NT_poly) && et.size == 8
17188 && ARM_CPU_IS_ANY (cpu_variant))
17189 || (et.type == NT_integer) || (et.type == NT_float))
17196 constraint (rs != NS_QQQ, BAD_FPU);
17197 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17198 N_SU_32 | N_P8 | N_P16 | N_KEY);
17200 /* We are dealing with MVE's vmullt. */
17202 && (inst.operands[0].reg == inst.operands[1].reg
17203 || inst.operands[0].reg == inst.operands[2].reg))
17204 as_tsktsk (BAD_MVE_SRCDEST);
17206 if (inst.cond > COND_ALWAYS)
17207 inst.pred_insn_type = INSIDE_VPT_INSN;
17209 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17211 if (et.type == NT_poly)
17212 mve_encode_qqq (neon_logbits (et.size), 64);
17214 mve_encode_qqq (et.type == NT_unsigned, et.size);
17219 inst.instruction = N_MNEM_vmul;
17222 inst.pred_insn_type = INSIDE_IT_INSN;
17227 do_mve_vabav (void)
17229 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17234 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17237 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
17238 | N_S16 | N_S32 | N_U8 | N_U16
17241 if (inst.cond > COND_ALWAYS)
17242 inst.pred_insn_type = INSIDE_VPT_INSN;
17244 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17246 mve_encode_rqq (et.type == NT_unsigned, et.size);
17250 do_mve_vmladav (void)
17252 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17253 struct neon_type_el et = neon_check_type (3, rs,
17254 N_EQK, N_EQK, N_SU_MVE | N_KEY);
17256 if (et.type == NT_unsigned
17257 && (inst.instruction == M_MNEM_vmladavx
17258 || inst.instruction == M_MNEM_vmladavax
17259 || inst.instruction == M_MNEM_vmlsdav
17260 || inst.instruction == M_MNEM_vmlsdava
17261 || inst.instruction == M_MNEM_vmlsdavx
17262 || inst.instruction == M_MNEM_vmlsdavax))
17263 first_error (BAD_SIMD_TYPE);
17265 constraint (inst.operands[2].reg > 14,
17266 _("MVE vector register in the range [Q0..Q7] expected"));
17268 if (inst.cond > COND_ALWAYS)
17269 inst.pred_insn_type = INSIDE_VPT_INSN;
17271 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17273 if (inst.instruction == M_MNEM_vmlsdav
17274 || inst.instruction == M_MNEM_vmlsdava
17275 || inst.instruction == M_MNEM_vmlsdavx
17276 || inst.instruction == M_MNEM_vmlsdavax)
17277 inst.instruction |= (et.size == 8) << 28;
17279 inst.instruction |= (et.size == 8) << 8;
17281 mve_encode_rqq (et.type == NT_unsigned, 64);
17282 inst.instruction |= (et.size == 32) << 16;
17286 do_mve_vmlaldav (void)
17288 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
17289 struct neon_type_el et
17290 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
17291 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
17293 if (et.type == NT_unsigned
17294 && (inst.instruction == M_MNEM_vmlsldav
17295 || inst.instruction == M_MNEM_vmlsldava
17296 || inst.instruction == M_MNEM_vmlsldavx
17297 || inst.instruction == M_MNEM_vmlsldavax))
17298 first_error (BAD_SIMD_TYPE);
17300 if (inst.cond > COND_ALWAYS)
17301 inst.pred_insn_type = INSIDE_VPT_INSN;
17303 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17305 mve_encode_rrqq (et.type == NT_unsigned, et.size);
17309 do_mve_vrmlaldavh (void)
17311 struct neon_type_el et;
17312 if (inst.instruction == M_MNEM_vrmlsldavh
17313 || inst.instruction == M_MNEM_vrmlsldavha
17314 || inst.instruction == M_MNEM_vrmlsldavhx
17315 || inst.instruction == M_MNEM_vrmlsldavhax)
17317 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17318 if (inst.operands[1].reg == REG_SP)
17319 as_tsktsk (MVE_BAD_SP);
17323 if (inst.instruction == M_MNEM_vrmlaldavhx
17324 || inst.instruction == M_MNEM_vrmlaldavhax)
17325 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17327 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
17328 N_U32 | N_S32 | N_KEY);
17329 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17330 with vmax/min instructions, making the use of SP in assembly really
17331 nonsensical, so instead of issuing a warning like we do for other uses
17332 of SP for the odd register operand we error out. */
17333 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
17336 /* Make sure we still check the second operand is an odd one and that PC is
17337 disallowed. This because we are parsing for any GPR operand, to be able
17338 to distinguish between giving a warning or an error for SP as described
17340 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
17341 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
17343 if (inst.cond > COND_ALWAYS)
17344 inst.pred_insn_type = INSIDE_VPT_INSN;
17346 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17348 mve_encode_rrqq (et.type == NT_unsigned, 0);
17353 do_mve_vmaxnmv (void)
17355 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17356 struct neon_type_el et
17357 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
17359 if (inst.cond > COND_ALWAYS)
17360 inst.pred_insn_type = INSIDE_VPT_INSN;
17362 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17364 if (inst.operands[0].reg == REG_SP)
17365 as_tsktsk (MVE_BAD_SP);
17366 else if (inst.operands[0].reg == REG_PC)
17367 as_tsktsk (MVE_BAD_PC);
17369 mve_encode_rq (et.size == 16, 64);
17373 do_mve_vmaxv (void)
17375 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17376 struct neon_type_el et;
17378 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
17379 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
17381 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17383 if (inst.cond > COND_ALWAYS)
17384 inst.pred_insn_type = INSIDE_VPT_INSN;
17386 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17388 if (inst.operands[0].reg == REG_SP)
17389 as_tsktsk (MVE_BAD_SP);
17390 else if (inst.operands[0].reg == REG_PC)
17391 as_tsktsk (MVE_BAD_PC);
17393 mve_encode_rq (et.type == NT_unsigned, et.size);
17398 do_neon_qrdmlah (void)
17400 /* Check we're on the correct architecture. */
17401 if (!mark_feature_used (&fpu_neon_ext_armv8))
17403 _("instruction form not available on this architecture.");
17404 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
17406 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17407 record_feature_use (&fpu_neon_ext_v8_1);
17410 if (inst.operands[2].isscalar)
17412 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17413 struct neon_type_el et = neon_check_type (3, rs,
17414 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17415 NEON_ENCODE (SCALAR, inst);
17416 neon_mul_mac (et, neon_quad (rs));
17420 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17421 struct neon_type_el et = neon_check_type (3, rs,
17422 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17423 NEON_ENCODE (INTEGER, inst);
17424 /* The U bit (rounding) comes from bit mask. */
17425 neon_three_same (neon_quad (rs), 0, et.size);
17430 do_neon_fcmp_absolute (void)
17432 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17433 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17434 N_F_16_32 | N_KEY);
17435 /* Size field comes from bit mask. */
17436 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
17440 do_neon_fcmp_absolute_inv (void)
17442 neon_exchange_operands ();
17443 do_neon_fcmp_absolute ();
17447 do_neon_step (void)
17449 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17450 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17451 N_F_16_32 | N_KEY);
17452 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
17456 do_neon_abs_neg (void)
17458 enum neon_shape rs;
17459 struct neon_type_el et;
17461 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
17464 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
17465 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
17467 if (check_simd_pred_availability (et.type == NT_float,
17468 NEON_CHECK_ARCH | NEON_CHECK_CC))
17471 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17472 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17473 inst.instruction |= LOW4 (inst.operands[1].reg);
17474 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17475 inst.instruction |= neon_quad (rs) << 6;
17476 inst.instruction |= (et.type == NT_float) << 10;
17477 inst.instruction |= neon_logbits (et.size) << 18;
17479 neon_dp_fixup (&inst);
17485 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17486 struct neon_type_el et = neon_check_type (2, rs,
17487 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
17488 int imm = inst.operands[2].imm;
17489 constraint (imm < 0 || (unsigned)imm >= et.size,
17490 _("immediate out of range for insert"));
17491 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
17497 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17498 struct neon_type_el et = neon_check_type (2, rs,
17499 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
17500 int imm = inst.operands[2].imm;
17501 constraint (imm < 1 || (unsigned)imm > et.size,
17502 _("immediate out of range for insert"));
17503 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
17507 do_neon_qshlu_imm (void)
17509 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17510 struct neon_type_el et = neon_check_type (2, rs,
17511 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
17512 int imm = inst.operands[2].imm;
17513 constraint (imm < 0 || (unsigned)imm >= et.size,
17514 _("immediate out of range for shift"));
17515 /* Only encodes the 'U present' variant of the instruction.
17516 In this case, signed types have OP (bit 8) set to 0.
17517 Unsigned types have OP set to 1. */
17518 inst.instruction |= (et.type == NT_unsigned) << 8;
17519 /* The rest of the bits are the same as other immediate shifts. */
17520 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
17524 do_neon_qmovn (void)
17526 struct neon_type_el et = neon_check_type (2, NS_DQ,
17527 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
17528 /* Saturating move where operands can be signed or unsigned, and the
17529 destination has the same signedness. */
17530 NEON_ENCODE (INTEGER, inst);
17531 if (et.type == NT_unsigned)
17532 inst.instruction |= 0xc0;
17534 inst.instruction |= 0x80;
17535 neon_two_same (0, 1, et.size / 2);
17539 do_neon_qmovun (void)
17541 struct neon_type_el et = neon_check_type (2, NS_DQ,
17542 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
17543 /* Saturating move with unsigned results. Operands must be signed. */
17544 NEON_ENCODE (INTEGER, inst);
17545 neon_two_same (0, 1, et.size / 2);
17549 do_neon_rshift_sat_narrow (void)
17551 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17552 or unsigned. If operands are unsigned, results must also be unsigned. */
17553 struct neon_type_el et = neon_check_type (2, NS_DQI,
17554 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
17555 int imm = inst.operands[2].imm;
17556 /* This gets the bounds check, size encoding and immediate bits calculation
17560 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17561 VQMOVN.I<size> <Dd>, <Qm>. */
17564 inst.operands[2].present = 0;
17565 inst.instruction = N_MNEM_vqmovn;
17570 constraint (imm < 1 || (unsigned)imm > et.size,
17571 _("immediate out of range"));
17572 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
17576 do_neon_rshift_sat_narrow_u (void)
17578 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17579 or unsigned. If operands are unsigned, results must also be unsigned. */
17580 struct neon_type_el et = neon_check_type (2, NS_DQI,
17581 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
17582 int imm = inst.operands[2].imm;
17583 /* This gets the bounds check, size encoding and immediate bits calculation
17587 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17588 VQMOVUN.I<size> <Dd>, <Qm>. */
17591 inst.operands[2].present = 0;
17592 inst.instruction = N_MNEM_vqmovun;
17597 constraint (imm < 1 || (unsigned)imm > et.size,
17598 _("immediate out of range"));
17599 /* FIXME: The manual is kind of unclear about what value U should have in
17600 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17602 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
17606 do_neon_movn (void)
17608 struct neon_type_el et = neon_check_type (2, NS_DQ,
17609 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
17610 NEON_ENCODE (INTEGER, inst);
17611 neon_two_same (0, 1, et.size / 2);
17615 do_neon_rshift_narrow (void)
17617 struct neon_type_el et = neon_check_type (2, NS_DQI,
17618 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
17619 int imm = inst.operands[2].imm;
17620 /* This gets the bounds check, size encoding and immediate bits calculation
17624 /* If immediate is zero then we are a pseudo-instruction for
17625 VMOVN.I<size> <Dd>, <Qm> */
17628 inst.operands[2].present = 0;
17629 inst.instruction = N_MNEM_vmovn;
17634 constraint (imm < 1 || (unsigned)imm > et.size,
17635 _("immediate out of range for narrowing operation"));
17636 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
17640 do_neon_shll (void)
17642 /* FIXME: Type checking when lengthening. */
17643 struct neon_type_el et = neon_check_type (2, NS_QDI,
17644 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
17645 unsigned imm = inst.operands[2].imm;
17647 if (imm == et.size)
17649 /* Maximum shift variant. */
17650 NEON_ENCODE (INTEGER, inst);
17651 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17652 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17653 inst.instruction |= LOW4 (inst.operands[1].reg);
17654 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17655 inst.instruction |= neon_logbits (et.size) << 18;
17657 neon_dp_fixup (&inst);
17661 /* A more-specific type check for non-max versions. */
17662 et = neon_check_type (2, NS_QDI,
17663 N_EQK | N_DBL, N_SU_32 | N_KEY);
17664 NEON_ENCODE (IMMED, inst);
17665 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
17669 /* Check the various types for the VCVT instruction, and return which version
17670 the current instruction is. */
17672 #define CVT_FLAVOUR_VAR \
17673 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17674 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17675 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17676 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17677 /* Half-precision conversions. */ \
17678 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17679 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17680 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17681 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17682 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17683 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17684 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17685 Compared with single/double precision variants, only the co-processor \
17686 field is different, so the encoding flow is reused here. */ \
17687 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17688 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17689 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17690 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17691 /* VFP instructions. */ \
17692 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17693 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17694 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17695 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17696 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17697 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17698 /* VFP instructions with bitshift. */ \
17699 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17700 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17701 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17702 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17703 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17704 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17705 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17706 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17708 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17709 neon_cvt_flavour_##C,
17711 /* The different types of conversions we can do. */
17712 enum neon_cvt_flavour
17715 neon_cvt_flavour_invalid,
17716 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
17721 static enum neon_cvt_flavour
17722 get_neon_cvt_flavour (enum neon_shape rs)
17724 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17725 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17726 if (et.type != NT_invtype) \
17728 inst.error = NULL; \
17729 return (neon_cvt_flavour_##C); \
17732 struct neon_type_el et;
17733 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
17734 || rs == NS_FF) ? N_VFP : 0;
17735 /* The instruction versions which take an immediate take one register
17736 argument, which is extended to the width of the full register. Thus the
17737 "source" and "destination" registers must have the same width. Hack that
17738 here by making the size equal to the key (wider, in this case) operand. */
17739 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
17743 return neon_cvt_flavour_invalid;
17758 /* Neon-syntax VFP conversions. */
17761 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
17763 const char *opname = 0;
17765 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
17766 || rs == NS_FHI || rs == NS_HFI)
17768 /* Conversions with immediate bitshift. */
17769 const char *enc[] =
17771 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17777 if (flavour < (int) ARRAY_SIZE (enc))
17779 opname = enc[flavour];
17780 constraint (inst.operands[0].reg != inst.operands[1].reg,
17781 _("operands 0 and 1 must be the same register"));
17782 inst.operands[1] = inst.operands[2];
17783 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
17788 /* Conversions without bitshift. */
17789 const char *enc[] =
17791 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17797 if (flavour < (int) ARRAY_SIZE (enc))
17798 opname = enc[flavour];
17802 do_vfp_nsyn_opcode (opname);
17804 /* ARMv8.2 fp16 VCVT instruction. */
17805 if (flavour == neon_cvt_flavour_s32_f16
17806 || flavour == neon_cvt_flavour_u32_f16
17807 || flavour == neon_cvt_flavour_f16_u32
17808 || flavour == neon_cvt_flavour_f16_s32)
17809 do_scalar_fp16_v82_encode ();
17813 do_vfp_nsyn_cvtz (void)
17815 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
17816 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
17817 const char *enc[] =
17819 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17825 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
17826 do_vfp_nsyn_opcode (enc[flavour]);
17830 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
17831 enum neon_cvt_mode mode)
17836 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17837 D register operands. */
17838 if (flavour == neon_cvt_flavour_s32_f64
17839 || flavour == neon_cvt_flavour_u32_f64)
17840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17843 if (flavour == neon_cvt_flavour_s32_f16
17844 || flavour == neon_cvt_flavour_u32_f16)
17845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
17848 set_pred_insn_type (OUTSIDE_PRED_INSN);
17852 case neon_cvt_flavour_s32_f64:
17856 case neon_cvt_flavour_s32_f32:
17860 case neon_cvt_flavour_s32_f16:
17864 case neon_cvt_flavour_u32_f64:
17868 case neon_cvt_flavour_u32_f32:
17872 case neon_cvt_flavour_u32_f16:
17877 first_error (_("invalid instruction shape"));
17883 case neon_cvt_mode_a: rm = 0; break;
17884 case neon_cvt_mode_n: rm = 1; break;
17885 case neon_cvt_mode_p: rm = 2; break;
17886 case neon_cvt_mode_m: rm = 3; break;
17887 default: first_error (_("invalid rounding mode")); return;
17890 NEON_ENCODE (FPV8, inst);
17891 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
17892 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
17893 inst.instruction |= sz << 8;
17895 /* ARMv8.2 fp16 VCVT instruction. */
17896 if (flavour == neon_cvt_flavour_s32_f16
17897 ||flavour == neon_cvt_flavour_u32_f16)
17898 do_scalar_fp16_v82_encode ();
17899 inst.instruction |= op << 7;
17900 inst.instruction |= rm << 16;
17901 inst.instruction |= 0xf0000000;
17902 inst.is_neon = TRUE;
17906 do_neon_cvt_1 (enum neon_cvt_mode mode)
17908 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
17909 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
17910 NS_FH, NS_HF, NS_FHI, NS_HFI,
17912 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
17914 if (flavour == neon_cvt_flavour_invalid)
17917 /* PR11109: Handle round-to-zero for VCVT conversions. */
17918 if (mode == neon_cvt_mode_z
17919 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
17920 && (flavour == neon_cvt_flavour_s16_f16
17921 || flavour == neon_cvt_flavour_u16_f16
17922 || flavour == neon_cvt_flavour_s32_f32
17923 || flavour == neon_cvt_flavour_u32_f32
17924 || flavour == neon_cvt_flavour_s32_f64
17925 || flavour == neon_cvt_flavour_u32_f64)
17926 && (rs == NS_FD || rs == NS_FF))
17928 do_vfp_nsyn_cvtz ();
17932 /* ARMv8.2 fp16 VCVT conversions. */
17933 if (mode == neon_cvt_mode_z
17934 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
17935 && (flavour == neon_cvt_flavour_s32_f16
17936 || flavour == neon_cvt_flavour_u32_f16)
17939 do_vfp_nsyn_cvtz ();
17940 do_scalar_fp16_v82_encode ();
17944 /* VFP rather than Neon conversions. */
17945 if (flavour >= neon_cvt_flavour_first_fp)
17947 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
17948 do_vfp_nsyn_cvt (rs, flavour);
17950 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
17958 if (mode == neon_cvt_mode_z
17959 && (flavour == neon_cvt_flavour_f16_s16
17960 || flavour == neon_cvt_flavour_f16_u16
17961 || flavour == neon_cvt_flavour_s16_f16
17962 || flavour == neon_cvt_flavour_u16_f16
17963 || flavour == neon_cvt_flavour_f32_u32
17964 || flavour == neon_cvt_flavour_f32_s32
17965 || flavour == neon_cvt_flavour_s32_f32
17966 || flavour == neon_cvt_flavour_u32_f32))
17968 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
17971 else if (mode == neon_cvt_mode_n)
17973 /* We are dealing with vcvt with the 'ne' condition. */
17975 inst.instruction = N_MNEM_vcvt;
17976 do_neon_cvt_1 (neon_cvt_mode_z);
17979 /* fall through. */
17983 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17984 0x0000100, 0x1000100, 0x0, 0x1000000};
17986 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17987 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17990 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17992 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
17993 _("immediate value out of range"));
17996 case neon_cvt_flavour_f16_s16:
17997 case neon_cvt_flavour_f16_u16:
17998 case neon_cvt_flavour_s16_f16:
17999 case neon_cvt_flavour_u16_f16:
18000 constraint (inst.operands[2].imm > 16,
18001 _("immediate value out of range"));
18003 case neon_cvt_flavour_f32_u32:
18004 case neon_cvt_flavour_f32_s32:
18005 case neon_cvt_flavour_s32_f32:
18006 case neon_cvt_flavour_u32_f32:
18007 constraint (inst.operands[2].imm > 32,
18008 _("immediate value out of range"));
18011 inst.error = BAD_FPU;
18016 /* Fixed-point conversion with #0 immediate is encoded as an
18017 integer conversion. */
18018 if (inst.operands[2].present && inst.operands[2].imm == 0)
18020 NEON_ENCODE (IMMED, inst);
18021 if (flavour != neon_cvt_flavour_invalid)
18022 inst.instruction |= enctab[flavour];
18023 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18024 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18025 inst.instruction |= LOW4 (inst.operands[1].reg);
18026 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18027 inst.instruction |= neon_quad (rs) << 6;
18028 inst.instruction |= 1 << 21;
18029 if (flavour < neon_cvt_flavour_s16_f16)
18031 inst.instruction |= 1 << 21;
18032 immbits = 32 - inst.operands[2].imm;
18033 inst.instruction |= immbits << 16;
18037 inst.instruction |= 3 << 20;
18038 immbits = 16 - inst.operands[2].imm;
18039 inst.instruction |= immbits << 16;
18040 inst.instruction &= ~(1 << 9);
18043 neon_dp_fixup (&inst);
18048 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
18049 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
18050 && (flavour == neon_cvt_flavour_s16_f16
18051 || flavour == neon_cvt_flavour_u16_f16
18052 || flavour == neon_cvt_flavour_s32_f32
18053 || flavour == neon_cvt_flavour_u32_f32))
18055 if (check_simd_pred_availability (1,
18056 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18059 else if (mode == neon_cvt_mode_z
18060 && (flavour == neon_cvt_flavour_f16_s16
18061 || flavour == neon_cvt_flavour_f16_u16
18062 || flavour == neon_cvt_flavour_s16_f16
18063 || flavour == neon_cvt_flavour_u16_f16
18064 || flavour == neon_cvt_flavour_f32_u32
18065 || flavour == neon_cvt_flavour_f32_s32
18066 || flavour == neon_cvt_flavour_s32_f32
18067 || flavour == neon_cvt_flavour_u32_f32))
18069 if (check_simd_pred_availability (1,
18070 NEON_CHECK_CC | NEON_CHECK_ARCH))
18073 /* fall through. */
18075 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
18078 NEON_ENCODE (FLOAT, inst);
18079 if (check_simd_pred_availability (1,
18080 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18083 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18084 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18085 inst.instruction |= LOW4 (inst.operands[1].reg);
18086 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18087 inst.instruction |= neon_quad (rs) << 6;
18088 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
18089 || flavour == neon_cvt_flavour_u32_f32) << 7;
18090 inst.instruction |= mode << 8;
18091 if (flavour == neon_cvt_flavour_u16_f16
18092 || flavour == neon_cvt_flavour_s16_f16)
18093 /* Mask off the original size bits and reencode them. */
18094 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
18097 inst.instruction |= 0xfc000000;
18099 inst.instruction |= 0xf0000000;
18105 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
18106 0x100, 0x180, 0x0, 0x080};
18108 NEON_ENCODE (INTEGER, inst);
18110 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18112 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18116 if (flavour != neon_cvt_flavour_invalid)
18117 inst.instruction |= enctab[flavour];
18119 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18120 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18121 inst.instruction |= LOW4 (inst.operands[1].reg);
18122 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18123 inst.instruction |= neon_quad (rs) << 6;
18124 if (flavour >= neon_cvt_flavour_s16_f16
18125 && flavour <= neon_cvt_flavour_f16_u16)
18126 /* Half precision. */
18127 inst.instruction |= 1 << 18;
18129 inst.instruction |= 2 << 18;
18131 neon_dp_fixup (&inst);
18136 /* Half-precision conversions for Advanced SIMD -- neon. */
18139 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18143 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
18145 as_bad (_("operand size must match register width"));
18150 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
18152 as_bad (_("operand size must match register width"));
18157 inst.instruction = 0x3b60600;
18159 inst.instruction = 0x3b60700;
18161 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18162 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18163 inst.instruction |= LOW4 (inst.operands[1].reg);
18164 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18165 neon_dp_fixup (&inst);
18169 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18170 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18171 do_vfp_nsyn_cvt (rs, flavour);
18173 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18178 do_neon_cvtr (void)
18180 do_neon_cvt_1 (neon_cvt_mode_x);
18186 do_neon_cvt_1 (neon_cvt_mode_z);
18190 do_neon_cvta (void)
18192 do_neon_cvt_1 (neon_cvt_mode_a);
18196 do_neon_cvtn (void)
18198 do_neon_cvt_1 (neon_cvt_mode_n);
18202 do_neon_cvtp (void)
18204 do_neon_cvt_1 (neon_cvt_mode_p);
18208 do_neon_cvtm (void)
18210 do_neon_cvt_1 (neon_cvt_mode_m);
18214 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
18217 mark_feature_used (&fpu_vfp_ext_armv8);
18219 encode_arm_vfp_reg (inst.operands[0].reg,
18220 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
18221 encode_arm_vfp_reg (inst.operands[1].reg,
18222 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
18223 inst.instruction |= to ? 0x10000 : 0;
18224 inst.instruction |= t ? 0x80 : 0;
18225 inst.instruction |= is_double ? 0x100 : 0;
18226 do_vfp_cond_or_thumb ();
18230 do_neon_cvttb_1 (bfd_boolean t)
18232 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
18233 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
18237 else if (rs == NS_QQ || rs == NS_QQI)
18239 int single_to_half = 0;
18240 if (check_simd_pred_availability (1, NEON_CHECK_ARCH))
18243 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18245 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18246 && (flavour == neon_cvt_flavour_u16_f16
18247 || flavour == neon_cvt_flavour_s16_f16
18248 || flavour == neon_cvt_flavour_f16_s16
18249 || flavour == neon_cvt_flavour_f16_u16
18250 || flavour == neon_cvt_flavour_u32_f32
18251 || flavour == neon_cvt_flavour_s32_f32
18252 || flavour == neon_cvt_flavour_f32_s32
18253 || flavour == neon_cvt_flavour_f32_u32))
18256 inst.instruction = N_MNEM_vcvt;
18257 set_pred_insn_type (INSIDE_VPT_INSN);
18258 do_neon_cvt_1 (neon_cvt_mode_z);
18261 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
18262 single_to_half = 1;
18263 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
18265 first_error (BAD_FPU);
18269 inst.instruction = 0xee3f0e01;
18270 inst.instruction |= single_to_half << 28;
18271 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18272 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
18273 inst.instruction |= t << 12;
18274 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18275 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
18278 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
18281 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
18283 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
18286 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
18288 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
18290 /* The VCVTB and VCVTT instructions with D-register operands
18291 don't work for SP only targets. */
18292 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18296 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
18298 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
18300 /* The VCVTB and VCVTT instructions with D-register operands
18301 don't work for SP only targets. */
18302 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18306 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
18313 do_neon_cvtb (void)
18315 do_neon_cvttb_1 (FALSE);
18320 do_neon_cvtt (void)
18322 do_neon_cvttb_1 (TRUE);
18326 neon_move_immediate (void)
18328 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
18329 struct neon_type_el et = neon_check_type (2, rs,
18330 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
18331 unsigned immlo, immhi = 0, immbits;
18332 int op, cmode, float_p;
18334 constraint (et.type == NT_invtype,
18335 _("operand size must be specified for immediate VMOV"));
18337 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18338 op = (inst.instruction & (1 << 5)) != 0;
18340 immlo = inst.operands[1].imm;
18341 if (inst.operands[1].regisimm)
18342 immhi = inst.operands[1].reg;
18344 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
18345 _("immediate has bits set outside the operand size"));
18347 float_p = inst.operands[1].immisfloat;
18349 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
18350 et.size, et.type)) == FAIL)
18352 /* Invert relevant bits only. */
18353 neon_invert_size (&immlo, &immhi, et.size);
18354 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18355 with one or the other; those cases are caught by
18356 neon_cmode_for_move_imm. */
18358 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
18359 &op, et.size, et.type)) == FAIL)
18361 first_error (_("immediate out of range"));
18366 inst.instruction &= ~(1 << 5);
18367 inst.instruction |= op << 5;
18369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18370 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18371 inst.instruction |= neon_quad (rs) << 6;
18372 inst.instruction |= cmode << 8;
18374 neon_write_immbits (immbits);
18380 if (inst.operands[1].isreg)
18382 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18384 NEON_ENCODE (INTEGER, inst);
18385 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18386 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18387 inst.instruction |= LOW4 (inst.operands[1].reg);
18388 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18389 inst.instruction |= neon_quad (rs) << 6;
18393 NEON_ENCODE (IMMED, inst);
18394 neon_move_immediate ();
18397 neon_dp_fixup (&inst);
18400 /* Encode instructions of form:
18402 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18403 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18406 neon_mixed_length (struct neon_type_el et, unsigned size)
18408 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18409 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18410 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18411 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18412 inst.instruction |= LOW4 (inst.operands[2].reg);
18413 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
18414 inst.instruction |= (et.type == NT_unsigned) << 24;
18415 inst.instruction |= neon_logbits (size) << 20;
18417 neon_dp_fixup (&inst);
18421 do_neon_dyadic_long (void)
18423 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
18426 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
18429 NEON_ENCODE (INTEGER, inst);
18430 /* FIXME: Type checking for lengthening op. */
18431 struct neon_type_el et = neon_check_type (3, NS_QDD,
18432 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
18433 neon_mixed_length (et, et.size);
18435 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18436 && (inst.cond == 0xf || inst.cond == 0x10))
18438 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18439 in an IT block with le/lt conditions. */
18441 if (inst.cond == 0xf)
18443 else if (inst.cond == 0x10)
18446 inst.pred_insn_type = INSIDE_IT_INSN;
18448 if (inst.instruction == N_MNEM_vaddl)
18450 inst.instruction = N_MNEM_vadd;
18451 do_neon_addsub_if_i ();
18453 else if (inst.instruction == N_MNEM_vsubl)
18455 inst.instruction = N_MNEM_vsub;
18456 do_neon_addsub_if_i ();
18458 else if (inst.instruction == N_MNEM_vabdl)
18460 inst.instruction = N_MNEM_vabd;
18461 do_neon_dyadic_if_su ();
18465 first_error (BAD_FPU);
18469 do_neon_abal (void)
18471 struct neon_type_el et = neon_check_type (3, NS_QDD,
18472 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
18473 neon_mixed_length (et, et.size);
18477 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
18479 if (inst.operands[2].isscalar)
18481 struct neon_type_el et = neon_check_type (3, NS_QDS,
18482 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
18483 NEON_ENCODE (SCALAR, inst);
18484 neon_mul_mac (et, et.type == NT_unsigned);
18488 struct neon_type_el et = neon_check_type (3, NS_QDD,
18489 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
18490 NEON_ENCODE (INTEGER, inst);
18491 neon_mixed_length (et, et.size);
18496 do_neon_mac_maybe_scalar_long (void)
18498 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
18501 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18502 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18505 neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
18507 unsigned regno = NEON_SCALAR_REG (scalar);
18508 unsigned elno = NEON_SCALAR_INDEX (scalar);
18512 if (regno > 7 || elno > 3)
18515 return ((regno & 0x7)
18516 | ((elno & 0x1) << 3)
18517 | (((elno >> 1) & 0x1) << 5));
18521 if (regno > 15 || elno > 1)
18524 return (((regno & 0x1) << 5)
18525 | ((regno >> 1) & 0x7)
18526 | ((elno & 0x1) << 3));
18530 first_error (_("scalar out of range for multiply instruction"));
18535 do_neon_fmac_maybe_scalar_long (int subtype)
18537 enum neon_shape rs;
18539 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18540 field (bits[21:20]) has different meaning. For scalar index variant, it's
18541 used to differentiate add and subtract, otherwise it's with fixed value
18545 if (inst.cond != COND_ALWAYS)
18546 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18547 "behaviour is UNPREDICTABLE"));
18549 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
18552 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
18555 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18556 be a scalar index register. */
18557 if (inst.operands[2].isscalar)
18559 high8 = 0xfe000000;
18562 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
18566 high8 = 0xfc000000;
18569 inst.instruction |= (0x1 << 23);
18570 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
18573 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
18575 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18576 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18577 so we simply pass -1 as size. */
18578 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
18579 neon_three_same (quad_p, 0, size);
18581 /* Undo neon_dp_fixup. Redo the high eight bits. */
18582 inst.instruction &= 0x00ffffff;
18583 inst.instruction |= high8;
18585 #define LOW1(R) ((R) & 0x1)
18586 #define HI4(R) (((R) >> 1) & 0xf)
18587 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18588 whether the instruction is in Q form and whether Vm is a scalar indexed
18590 if (inst.operands[2].isscalar)
18593 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
18594 inst.instruction &= 0xffffffd0;
18595 inst.instruction |= rm;
18599 /* Redo Rn as well. */
18600 inst.instruction &= 0xfff0ff7f;
18601 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
18602 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
18607 /* Redo Rn and Rm. */
18608 inst.instruction &= 0xfff0ff50;
18609 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
18610 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
18611 inst.instruction |= HI4 (inst.operands[2].reg);
18612 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
18617 do_neon_vfmal (void)
18619 return do_neon_fmac_maybe_scalar_long (0);
18623 do_neon_vfmsl (void)
18625 return do_neon_fmac_maybe_scalar_long (1);
18629 do_neon_dyadic_wide (void)
18631 struct neon_type_el et = neon_check_type (3, NS_QQD,
18632 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
18633 neon_mixed_length (et, et.size);
18637 do_neon_dyadic_narrow (void)
18639 struct neon_type_el et = neon_check_type (3, NS_QDD,
18640 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
18641 /* Operand sign is unimportant, and the U bit is part of the opcode,
18642 so force the operand type to integer. */
18643 et.type = NT_integer;
18644 neon_mixed_length (et, et.size / 2);
18648 do_neon_mul_sat_scalar_long (void)
18650 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
18654 do_neon_vmull (void)
18656 if (inst.operands[2].isscalar)
18657 do_neon_mac_maybe_scalar_long ();
18660 struct neon_type_el et = neon_check_type (3, NS_QDD,
18661 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
18663 if (et.type == NT_poly)
18664 NEON_ENCODE (POLY, inst);
18666 NEON_ENCODE (INTEGER, inst);
18668 /* For polynomial encoding the U bit must be zero, and the size must
18669 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18670 obviously, as 0b10). */
18673 /* Check we're on the correct architecture. */
18674 if (!mark_feature_used (&fpu_crypto_ext_armv8))
18676 _("Instruction form not available on this architecture.");
18681 neon_mixed_length (et, et.size);
18688 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
18689 struct neon_type_el et = neon_check_type (3, rs,
18690 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18691 unsigned imm = (inst.operands[3].imm * et.size) / 8;
18693 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
18694 _("shift out of range"));
18695 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18696 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18697 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18698 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18699 inst.instruction |= LOW4 (inst.operands[2].reg);
18700 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
18701 inst.instruction |= neon_quad (rs) << 6;
18702 inst.instruction |= imm << 8;
18704 neon_dp_fixup (&inst);
18710 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18711 struct neon_type_el et = neon_check_type (2, rs,
18712 N_EQK, N_8 | N_16 | N_32 | N_KEY);
18713 unsigned op = (inst.instruction >> 7) & 3;
18714 /* N (width of reversed regions) is encoded as part of the bitmask. We
18715 extract it here to check the elements to be reversed are smaller.
18716 Otherwise we'd get a reserved instruction. */
18717 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
18718 gas_assert (elsize != 0);
18719 constraint (et.size >= elsize,
18720 _("elements must be smaller than reversal region"));
18721 neon_two_same (neon_quad (rs), 1, et.size);
18727 if (inst.operands[1].isscalar)
18729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
18731 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
18732 struct neon_type_el et = neon_check_type (2, rs,
18733 N_EQK, N_8 | N_16 | N_32 | N_KEY);
18734 unsigned sizebits = et.size >> 3;
18735 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
18736 int logsize = neon_logbits (et.size);
18737 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
18739 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
18742 NEON_ENCODE (SCALAR, inst);
18743 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18744 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18745 inst.instruction |= LOW4 (dm);
18746 inst.instruction |= HI1 (dm) << 5;
18747 inst.instruction |= neon_quad (rs) << 6;
18748 inst.instruction |= x << 17;
18749 inst.instruction |= sizebits << 16;
18751 neon_dp_fixup (&inst);
18755 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
18756 struct neon_type_el et = neon_check_type (2, rs,
18757 N_8 | N_16 | N_32 | N_KEY, N_EQK);
18760 if (check_simd_pred_availability (0, NEON_CHECK_ARCH))
18764 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
18767 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18769 if (inst.operands[1].reg == REG_SP)
18770 as_tsktsk (MVE_BAD_SP);
18771 else if (inst.operands[1].reg == REG_PC)
18772 as_tsktsk (MVE_BAD_PC);
18775 /* Duplicate ARM register to lanes of vector. */
18776 NEON_ENCODE (ARMREG, inst);
18779 case 8: inst.instruction |= 0x400000; break;
18780 case 16: inst.instruction |= 0x000020; break;
18781 case 32: inst.instruction |= 0x000000; break;
18784 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
18785 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
18786 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
18787 inst.instruction |= neon_quad (rs) << 21;
18788 /* The encoding for this instruction is identical for the ARM and Thumb
18789 variants, except for the condition field. */
18790 do_vfp_cond_or_thumb ();
18795 do_mve_mov (int toQ)
18797 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18799 if (inst.cond > COND_ALWAYS)
18800 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
18802 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
18811 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
18812 _("Index one must be [2,3] and index two must be two less than"
18814 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
18815 _("General purpose registers may not be the same"));
18816 constraint (inst.operands[Rt].reg == REG_SP
18817 || inst.operands[Rt2].reg == REG_SP,
18819 constraint (inst.operands[Rt].reg == REG_PC
18820 || inst.operands[Rt2].reg == REG_PC,
18823 inst.instruction = 0xec000f00;
18824 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
18825 inst.instruction |= !!toQ << 20;
18826 inst.instruction |= inst.operands[Rt2].reg << 16;
18827 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
18828 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
18829 inst.instruction |= inst.operands[Rt].reg;
18835 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18838 if (inst.cond > COND_ALWAYS)
18839 inst.pred_insn_type = INSIDE_VPT_INSN;
18841 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18843 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
18846 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18847 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
18848 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18849 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18850 inst.instruction |= LOW4 (inst.operands[1].reg);
18855 /* VMOV has particularly many variations. It can be one of:
18856 0. VMOV<c><q> <Qd>, <Qm>
18857 1. VMOV<c><q> <Dd>, <Dm>
18858 (Register operations, which are VORR with Rm = Rn.)
18859 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18860 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18862 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18863 (ARM register to scalar.)
18864 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18865 (Two ARM registers to vector.)
18866 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18867 (Scalar to ARM register.)
18868 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18869 (Vector to two ARM registers.)
18870 8. VMOV.F32 <Sd>, <Sm>
18871 9. VMOV.F64 <Dd>, <Dm>
18872 (VFP register moves.)
18873 10. VMOV.F32 <Sd>, #imm
18874 11. VMOV.F64 <Dd>, #imm
18875 (VFP float immediate load.)
18876 12. VMOV <Rd>, <Sm>
18877 (VFP single to ARM reg.)
18878 13. VMOV <Sd>, <Rm>
18879 (ARM reg to VFP single.)
18880 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18881 (Two ARM regs to two VFP singles.)
18882 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18883 (Two VFP singles to two ARM regs.)
18884 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18885 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18886 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18887 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18889 These cases can be disambiguated using neon_select_shape, except cases 1/9
18890 and 3/11 which depend on the operand type too.
18892 All the encoded bits are hardcoded by this function.
18894 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18895 Cases 5, 7 may be used with VFPv2 and above.
18897 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18898 can specify a type where it doesn't make sense to, and is ignored). */
18903 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
18904 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
18905 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
18906 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
18908 struct neon_type_el et;
18909 const char *ldconst = 0;
18913 case NS_DD: /* case 1/9. */
18914 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
18915 /* It is not an error here if no type is given. */
18917 if (et.type == NT_float && et.size == 64)
18919 do_vfp_nsyn_opcode ("fcpyd");
18922 /* fall through. */
18924 case NS_QQ: /* case 0/1. */
18926 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
18928 /* The architecture manual I have doesn't explicitly state which
18929 value the U bit should have for register->register moves, but
18930 the equivalent VORR instruction has U = 0, so do that. */
18931 inst.instruction = 0x0200110;
18932 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18933 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18934 inst.instruction |= LOW4 (inst.operands[1].reg);
18935 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18936 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18937 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18938 inst.instruction |= neon_quad (rs) << 6;
18940 neon_dp_fixup (&inst);
18944 case NS_DI: /* case 3/11. */
18945 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
18947 if (et.type == NT_float && et.size == 64)
18949 /* case 11 (fconstd). */
18950 ldconst = "fconstd";
18951 goto encode_fconstd;
18953 /* fall through. */
18955 case NS_QI: /* case 2/3. */
18956 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
18958 inst.instruction = 0x0800010;
18959 neon_move_immediate ();
18960 neon_dp_fixup (&inst);
18963 case NS_SR: /* case 4. */
18965 unsigned bcdebits = 0;
18967 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
18968 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
18970 /* .<size> is optional here, defaulting to .32. */
18971 if (inst.vectype.elems == 0
18972 && inst.operands[0].vectype.type == NT_invtype
18973 && inst.operands[1].vectype.type == NT_invtype)
18975 inst.vectype.el[0].type = NT_untyped;
18976 inst.vectype.el[0].size = 32;
18977 inst.vectype.elems = 1;
18980 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
18981 logsize = neon_logbits (et.size);
18985 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18986 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
18991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
18992 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
18996 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18998 if (inst.operands[1].reg == REG_SP)
18999 as_tsktsk (MVE_BAD_SP);
19000 else if (inst.operands[1].reg == REG_PC)
19001 as_tsktsk (MVE_BAD_PC);
19003 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19005 constraint (et.type == NT_invtype, _("bad type for scalar"));
19006 constraint (x >= size / et.size, _("scalar index out of range"));
19011 case 8: bcdebits = 0x8; break;
19012 case 16: bcdebits = 0x1; break;
19013 case 32: bcdebits = 0x0; break;
19017 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19019 inst.instruction = 0xe000b10;
19020 do_vfp_cond_or_thumb ();
19021 inst.instruction |= LOW4 (dn) << 16;
19022 inst.instruction |= HI1 (dn) << 7;
19023 inst.instruction |= inst.operands[1].reg << 12;
19024 inst.instruction |= (bcdebits & 3) << 5;
19025 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
19026 inst.instruction |= (x >> (3-logsize)) << 16;
19030 case NS_DRR: /* case 5 (fmdrr). */
19031 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19032 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19035 inst.instruction = 0xc400b10;
19036 do_vfp_cond_or_thumb ();
19037 inst.instruction |= LOW4 (inst.operands[0].reg);
19038 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
19039 inst.instruction |= inst.operands[1].reg << 12;
19040 inst.instruction |= inst.operands[2].reg << 16;
19043 case NS_RS: /* case 6. */
19046 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
19047 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
19048 unsigned abcdebits = 0;
19050 /* .<dt> is optional here, defaulting to .32. */
19051 if (inst.vectype.elems == 0
19052 && inst.operands[0].vectype.type == NT_invtype
19053 && inst.operands[1].vectype.type == NT_invtype)
19055 inst.vectype.el[0].type = NT_untyped;
19056 inst.vectype.el[0].size = 32;
19057 inst.vectype.elems = 1;
19060 et = neon_check_type (2, NS_NULL,
19061 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
19062 logsize = neon_logbits (et.size);
19066 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19067 && vfp_or_neon_is_neon (NEON_CHECK_CC
19068 | NEON_CHECK_ARCH) == FAIL)
19073 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19074 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19078 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19080 if (inst.operands[0].reg == REG_SP)
19081 as_tsktsk (MVE_BAD_SP);
19082 else if (inst.operands[0].reg == REG_PC)
19083 as_tsktsk (MVE_BAD_PC);
19086 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
19088 constraint (et.type == NT_invtype, _("bad type for scalar"));
19089 constraint (x >= size / et.size, _("scalar index out of range"));
19093 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
19094 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
19095 case 32: abcdebits = 0x00; break;
19099 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19100 inst.instruction = 0xe100b10;
19101 do_vfp_cond_or_thumb ();
19102 inst.instruction |= LOW4 (dn) << 16;
19103 inst.instruction |= HI1 (dn) << 7;
19104 inst.instruction |= inst.operands[0].reg << 12;
19105 inst.instruction |= (abcdebits & 3) << 5;
19106 inst.instruction |= (abcdebits >> 2) << 21;
19107 inst.instruction |= (x >> (3-logsize)) << 16;
19111 case NS_RRD: /* case 7 (fmrrd). */
19112 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19113 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19116 inst.instruction = 0xc500b10;
19117 do_vfp_cond_or_thumb ();
19118 inst.instruction |= inst.operands[0].reg << 12;
19119 inst.instruction |= inst.operands[1].reg << 16;
19120 inst.instruction |= LOW4 (inst.operands[2].reg);
19121 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19124 case NS_FF: /* case 8 (fcpys). */
19125 do_vfp_nsyn_opcode ("fcpys");
19129 case NS_FI: /* case 10 (fconsts). */
19130 ldconst = "fconsts";
19132 if (!inst.operands[1].immisfloat)
19135 /* Immediate has to fit in 8 bits so float is enough. */
19136 float imm = (float) inst.operands[1].imm;
19137 memcpy (&new_imm, &imm, sizeof (float));
19138 /* But the assembly may have been written to provide an integer
19139 bit pattern that equates to a float, so check that the
19140 conversion has worked. */
19141 if (is_quarter_float (new_imm))
19143 if (is_quarter_float (inst.operands[1].imm))
19144 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19146 inst.operands[1].imm = new_imm;
19147 inst.operands[1].immisfloat = 1;
19151 if (is_quarter_float (inst.operands[1].imm))
19153 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
19154 do_vfp_nsyn_opcode (ldconst);
19156 /* ARMv8.2 fp16 vmov.f16 instruction. */
19158 do_scalar_fp16_v82_encode ();
19161 first_error (_("immediate out of range"));
19165 case NS_RF: /* case 12 (fmrs). */
19166 do_vfp_nsyn_opcode ("fmrs");
19167 /* ARMv8.2 fp16 vmov.f16 instruction. */
19169 do_scalar_fp16_v82_encode ();
19173 case NS_FR: /* case 13 (fmsr). */
19174 do_vfp_nsyn_opcode ("fmsr");
19175 /* ARMv8.2 fp16 vmov.f16 instruction. */
19177 do_scalar_fp16_v82_encode ();
19187 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19188 (one of which is a list), but we have parsed four. Do some fiddling to
19189 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19191 case NS_RRFF: /* case 14 (fmrrs). */
19192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19193 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19195 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
19196 _("VFP registers must be adjacent"));
19197 inst.operands[2].imm = 2;
19198 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19199 do_vfp_nsyn_opcode ("fmrrs");
19202 case NS_FFRR: /* case 15 (fmsrr). */
19203 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19204 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19206 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
19207 _("VFP registers must be adjacent"));
19208 inst.operands[1] = inst.operands[2];
19209 inst.operands[2] = inst.operands[3];
19210 inst.operands[0].imm = 2;
19211 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19212 do_vfp_nsyn_opcode ("fmsrr");
19216 /* neon_select_shape has determined that the instruction
19217 shape is wrong and has already set the error message. */
19228 if (!(inst.operands[0].present && inst.operands[0].isquad
19229 && inst.operands[1].present && inst.operands[1].isquad
19230 && !inst.operands[2].present))
19232 inst.instruction = 0;
19235 set_pred_insn_type (INSIDE_IT_INSN);
19240 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19243 if (inst.cond != COND_ALWAYS)
19244 inst.pred_insn_type = INSIDE_VPT_INSN;
19246 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
19247 | N_S16 | N_U16 | N_KEY);
19249 inst.instruction |= (et.type == NT_unsigned) << 28;
19250 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19251 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
19252 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19253 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19254 inst.instruction |= LOW4 (inst.operands[1].reg);
19259 do_neon_rshift_round_imm (void)
19261 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
19262 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
19263 int imm = inst.operands[2].imm;
19265 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19268 inst.operands[2].present = 0;
19273 constraint (imm < 1 || (unsigned)imm > et.size,
19274 _("immediate out of range for shift"));
19275 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
19280 do_neon_movhf (void)
19282 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
19283 constraint (rs != NS_HH, _("invalid suffix"));
19285 if (inst.cond != COND_ALWAYS)
19289 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19290 " the behaviour is UNPREDICTABLE"));
19294 inst.error = BAD_COND;
19299 do_vfp_sp_monadic ();
19302 inst.instruction |= 0xf0000000;
19306 do_neon_movl (void)
19308 struct neon_type_el et = neon_check_type (2, NS_QD,
19309 N_EQK | N_DBL, N_SU_32 | N_KEY);
19310 unsigned sizebits = et.size >> 3;
19311 inst.instruction |= sizebits << 19;
19312 neon_two_same (0, et.type == NT_unsigned, -1);
19318 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19319 struct neon_type_el et = neon_check_type (2, rs,
19320 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19321 NEON_ENCODE (INTEGER, inst);
19322 neon_two_same (neon_quad (rs), 1, et.size);
19326 do_neon_zip_uzp (void)
19328 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19329 struct neon_type_el et = neon_check_type (2, rs,
19330 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19331 if (rs == NS_DD && et.size == 32)
19333 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19334 inst.instruction = N_MNEM_vtrn;
19338 neon_two_same (neon_quad (rs), 1, et.size);
19342 do_neon_sat_abs_neg (void)
19344 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19345 struct neon_type_el et = neon_check_type (2, rs,
19346 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19347 neon_two_same (neon_quad (rs), 1, et.size);
19351 do_neon_pair_long (void)
19353 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19354 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
19355 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19356 inst.instruction |= (et.type == NT_unsigned) << 7;
19357 neon_two_same (neon_quad (rs), 1, et.size);
19361 do_neon_recip_est (void)
19363 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19364 struct neon_type_el et = neon_check_type (2, rs,
19365 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
19366 inst.instruction |= (et.type == NT_float) << 8;
19367 neon_two_same (neon_quad (rs), 1, et.size);
19373 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19376 enum neon_shape rs;
19377 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19378 rs = neon_select_shape (NS_QQ, NS_NULL);
19380 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19382 struct neon_type_el et = neon_check_type (2, rs,
19383 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19384 neon_two_same (neon_quad (rs), 1, et.size);
19390 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19393 enum neon_shape rs;
19394 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19395 rs = neon_select_shape (NS_QQ, NS_NULL);
19397 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19399 struct neon_type_el et = neon_check_type (2, rs,
19400 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
19401 neon_two_same (neon_quad (rs), 1, et.size);
19407 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19408 struct neon_type_el et = neon_check_type (2, rs,
19409 N_EQK | N_INT, N_8 | N_KEY);
19410 neon_two_same (neon_quad (rs), 1, et.size);
19416 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19417 neon_two_same (neon_quad (rs), 1, -1);
19421 do_neon_tbl_tbx (void)
19423 unsigned listlenbits;
19424 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
19426 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
19428 first_error (_("bad list length for table lookup"));
19432 listlenbits = inst.operands[1].imm - 1;
19433 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19434 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19435 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19436 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19437 inst.instruction |= LOW4 (inst.operands[2].reg);
19438 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19439 inst.instruction |= listlenbits << 8;
19441 neon_dp_fixup (&inst);
19445 do_neon_ldm_stm (void)
19447 /* P, U and L bits are part of bitmask. */
19448 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
19449 unsigned offsetbits = inst.operands[1].imm * 2;
19451 if (inst.operands[1].issingle)
19453 do_vfp_nsyn_ldm_stm (is_dbmode);
19457 constraint (is_dbmode && !inst.operands[0].writeback,
19458 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19460 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
19461 _("register list must contain at least 1 and at most 16 "
19464 inst.instruction |= inst.operands[0].reg << 16;
19465 inst.instruction |= inst.operands[0].writeback << 21;
19466 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19467 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
19469 inst.instruction |= offsetbits;
19471 do_vfp_cond_or_thumb ();
19475 do_neon_ldr_str (void)
19477 int is_ldr = (inst.instruction & (1 << 20)) != 0;
19479 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19480 And is UNPREDICTABLE in thumb mode. */
19482 && inst.operands[1].reg == REG_PC
19483 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
19486 inst.error = _("Use of PC here is UNPREDICTABLE");
19487 else if (warn_on_deprecated)
19488 as_tsktsk (_("Use of PC here is deprecated"));
19491 if (inst.operands[0].issingle)
19494 do_vfp_nsyn_opcode ("flds");
19496 do_vfp_nsyn_opcode ("fsts");
19498 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19499 if (inst.vectype.el[0].size == 16)
19500 do_scalar_fp16_v82_encode ();
19505 do_vfp_nsyn_opcode ("fldd");
19507 do_vfp_nsyn_opcode ("fstd");
19512 do_t_vldr_vstr_sysreg (void)
19514 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
19515 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
19517 /* Use of PC is UNPREDICTABLE. */
19518 if (inst.operands[1].reg == REG_PC)
19519 inst.error = _("Use of PC here is UNPREDICTABLE");
19521 if (inst.operands[1].immisreg)
19522 inst.error = _("instruction does not accept register index");
19524 if (!inst.operands[1].isreg)
19525 inst.error = _("instruction does not accept PC-relative addressing");
19527 if (abs (inst.operands[1].imm) >= (1 << 7))
19528 inst.error = _("immediate value out of range");
19530 inst.instruction = 0xec000f80;
19532 inst.instruction |= 1 << sysreg_vldr_bitno;
19533 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
19534 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
19535 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
19539 do_vldr_vstr (void)
19541 bfd_boolean sysreg_op = !inst.operands[0].isreg;
19543 /* VLDR/VSTR (System Register). */
19546 if (!mark_feature_used (&arm_ext_v8_1m_main))
19547 as_bad (_("Instruction not permitted on this architecture"));
19549 do_t_vldr_vstr_sysreg ();
19554 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
19555 as_bad (_("Instruction not permitted on this architecture"));
19556 do_neon_ldr_str ();
19560 /* "interleave" version also handles non-interleaving register VLD1/VST1
19564 do_neon_ld_st_interleave (void)
19566 struct neon_type_el et = neon_check_type (1, NS_NULL,
19567 N_8 | N_16 | N_32 | N_64);
19568 unsigned alignbits = 0;
19570 /* The bits in this table go:
19571 0: register stride of one (0) or two (1)
19572 1,2: register list length, minus one (1, 2, 3, 4).
19573 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19574 We use -1 for invalid entries. */
19575 const int typetable[] =
19577 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19578 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19579 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19580 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19584 if (et.type == NT_invtype)
19587 if (inst.operands[1].immisalign)
19588 switch (inst.operands[1].imm >> 8)
19590 case 64: alignbits = 1; break;
19592 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
19593 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
19594 goto bad_alignment;
19598 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
19599 goto bad_alignment;
19604 first_error (_("bad alignment"));
19608 inst.instruction |= alignbits << 4;
19609 inst.instruction |= neon_logbits (et.size) << 6;
19611 /* Bits [4:6] of the immediate in a list specifier encode register stride
19612 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19613 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19614 up the right value for "type" in a table based on this value and the given
19615 list style, then stick it back. */
19616 idx = ((inst.operands[0].imm >> 4) & 7)
19617 | (((inst.instruction >> 8) & 3) << 3);
19619 typebits = typetable[idx];
19621 constraint (typebits == -1, _("bad list type for instruction"));
19622 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
19625 inst.instruction &= ~0xf00;
19626 inst.instruction |= typebits << 8;
19629 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19630 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19631 otherwise. The variable arguments are a list of pairs of legal (size, align)
19632 values, terminated with -1. */
19635 neon_alignment_bit (int size, int align, int *do_alignment, ...)
19638 int result = FAIL, thissize, thisalign;
19640 if (!inst.operands[1].immisalign)
19646 va_start (ap, do_alignment);
19650 thissize = va_arg (ap, int);
19651 if (thissize == -1)
19653 thisalign = va_arg (ap, int);
19655 if (size == thissize && align == thisalign)
19658 while (result != SUCCESS);
19662 if (result == SUCCESS)
19665 first_error (_("unsupported alignment for instruction"));
19671 do_neon_ld_st_lane (void)
19673 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
19674 int align_good, do_alignment = 0;
19675 int logsize = neon_logbits (et.size);
19676 int align = inst.operands[1].imm >> 8;
19677 int n = (inst.instruction >> 8) & 3;
19678 int max_el = 64 / et.size;
19680 if (et.type == NT_invtype)
19683 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
19684 _("bad list length"));
19685 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
19686 _("scalar index out of range"));
19687 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
19689 _("stride of 2 unavailable when element size is 8"));
19693 case 0: /* VLD1 / VST1. */
19694 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
19696 if (align_good == FAIL)
19700 unsigned alignbits = 0;
19703 case 16: alignbits = 0x1; break;
19704 case 32: alignbits = 0x3; break;
19707 inst.instruction |= alignbits << 4;
19711 case 1: /* VLD2 / VST2. */
19712 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
19713 16, 32, 32, 64, -1);
19714 if (align_good == FAIL)
19717 inst.instruction |= 1 << 4;
19720 case 2: /* VLD3 / VST3. */
19721 constraint (inst.operands[1].immisalign,
19722 _("can't use alignment with this instruction"));
19725 case 3: /* VLD4 / VST4. */
19726 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
19727 16, 64, 32, 64, 32, 128, -1);
19728 if (align_good == FAIL)
19732 unsigned alignbits = 0;
19735 case 8: alignbits = 0x1; break;
19736 case 16: alignbits = 0x1; break;
19737 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
19740 inst.instruction |= alignbits << 4;
19747 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19748 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19749 inst.instruction |= 1 << (4 + logsize);
19751 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
19752 inst.instruction |= logsize << 10;
19755 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19758 do_neon_ld_dup (void)
19760 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
19761 int align_good, do_alignment = 0;
19763 if (et.type == NT_invtype)
19766 switch ((inst.instruction >> 8) & 3)
19768 case 0: /* VLD1. */
19769 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
19770 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
19771 &do_alignment, 16, 16, 32, 32, -1);
19772 if (align_good == FAIL)
19774 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
19777 case 2: inst.instruction |= 1 << 5; break;
19778 default: first_error (_("bad list length")); return;
19780 inst.instruction |= neon_logbits (et.size) << 6;
19783 case 1: /* VLD2. */
19784 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
19785 &do_alignment, 8, 16, 16, 32, 32, 64,
19787 if (align_good == FAIL)
19789 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
19790 _("bad list length"));
19791 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19792 inst.instruction |= 1 << 5;
19793 inst.instruction |= neon_logbits (et.size) << 6;
19796 case 2: /* VLD3. */
19797 constraint (inst.operands[1].immisalign,
19798 _("can't use alignment with this instruction"));
19799 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
19800 _("bad list length"));
19801 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19802 inst.instruction |= 1 << 5;
19803 inst.instruction |= neon_logbits (et.size) << 6;
19806 case 3: /* VLD4. */
19808 int align = inst.operands[1].imm >> 8;
19809 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
19810 16, 64, 32, 64, 32, 128, -1);
19811 if (align_good == FAIL)
19813 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
19814 _("bad list length"));
19815 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
19816 inst.instruction |= 1 << 5;
19817 if (et.size == 32 && align == 128)
19818 inst.instruction |= 0x3 << 6;
19820 inst.instruction |= neon_logbits (et.size) << 6;
19827 inst.instruction |= do_alignment << 4;
19830 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19831 apart from bits [11:4]. */
19834 do_neon_ldx_stx (void)
19836 if (inst.operands[1].isreg)
19837 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
19839 switch (NEON_LANE (inst.operands[0].imm))
19841 case NEON_INTERLEAVE_LANES:
19842 NEON_ENCODE (INTERLV, inst);
19843 do_neon_ld_st_interleave ();
19846 case NEON_ALL_LANES:
19847 NEON_ENCODE (DUP, inst);
19848 if (inst.instruction == N_INV)
19850 first_error ("only loads support such operands");
19857 NEON_ENCODE (LANE, inst);
19858 do_neon_ld_st_lane ();
19861 /* L bit comes from bit mask. */
19862 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19863 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19864 inst.instruction |= inst.operands[1].reg << 16;
19866 if (inst.operands[1].postind)
19868 int postreg = inst.operands[1].imm & 0xf;
19869 constraint (!inst.operands[1].immisreg,
19870 _("post-index must be a register"));
19871 constraint (postreg == 0xd || postreg == 0xf,
19872 _("bad register for post-index"));
19873 inst.instruction |= postreg;
19877 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
19878 constraint (inst.relocs[0].exp.X_op != O_constant
19879 || inst.relocs[0].exp.X_add_number != 0,
19882 if (inst.operands[1].writeback)
19884 inst.instruction |= 0xd;
19887 inst.instruction |= 0xf;
19891 inst.instruction |= 0xf9000000;
19893 inst.instruction |= 0xf4000000;
19898 do_vfp_nsyn_fpv8 (enum neon_shape rs)
19900 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19901 D register operands. */
19902 if (neon_shape_class[rs] == SC_DOUBLE)
19903 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19906 NEON_ENCODE (FPV8, inst);
19908 if (rs == NS_FFF || rs == NS_HHH)
19910 do_vfp_sp_dyadic ();
19912 /* ARMv8.2 fp16 instruction. */
19914 do_scalar_fp16_v82_encode ();
19917 do_vfp_dp_rd_rn_rm ();
19920 inst.instruction |= 0x100;
19922 inst.instruction |= 0xf0000000;
19928 set_pred_insn_type (OUTSIDE_PRED_INSN);
19930 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
19931 first_error (_("invalid instruction shape"));
19937 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19938 set_pred_insn_type (OUTSIDE_PRED_INSN);
19940 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
19943 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
19946 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
19950 do_vrint_1 (enum neon_cvt_mode mode)
19952 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
19953 struct neon_type_el et;
19958 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19959 D register operands. */
19960 if (neon_shape_class[rs] == SC_DOUBLE)
19961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19964 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
19966 if (et.type != NT_invtype)
19968 /* VFP encodings. */
19969 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
19970 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
19971 set_pred_insn_type (OUTSIDE_PRED_INSN);
19973 NEON_ENCODE (FPV8, inst);
19974 if (rs == NS_FF || rs == NS_HH)
19975 do_vfp_sp_monadic ();
19977 do_vfp_dp_rd_rm ();
19981 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
19982 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
19983 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
19984 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
19985 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
19986 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
19987 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
19991 inst.instruction |= (rs == NS_DD) << 8;
19992 do_vfp_cond_or_thumb ();
19994 /* ARMv8.2 fp16 vrint instruction. */
19996 do_scalar_fp16_v82_encode ();
20000 /* Neon encodings (or something broken...). */
20002 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
20004 if (et.type == NT_invtype)
20007 set_pred_insn_type (OUTSIDE_PRED_INSN);
20008 NEON_ENCODE (FLOAT, inst);
20010 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
20013 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20014 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20015 inst.instruction |= LOW4 (inst.operands[1].reg);
20016 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20017 inst.instruction |= neon_quad (rs) << 6;
20018 /* Mask off the original size bits and reencode them. */
20019 inst.instruction = ((inst.instruction & 0xfff3ffff)
20020 | neon_logbits (et.size) << 18);
20024 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
20025 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
20026 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
20027 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
20028 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
20029 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
20030 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
20035 inst.instruction |= 0xfc000000;
20037 inst.instruction |= 0xf0000000;
20044 do_vrint_1 (neon_cvt_mode_x);
20050 do_vrint_1 (neon_cvt_mode_z);
20056 do_vrint_1 (neon_cvt_mode_r);
20062 do_vrint_1 (neon_cvt_mode_a);
20068 do_vrint_1 (neon_cvt_mode_n);
20074 do_vrint_1 (neon_cvt_mode_p);
20080 do_vrint_1 (neon_cvt_mode_m);
20084 neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
20086 unsigned regno = NEON_SCALAR_REG (opnd);
20087 unsigned elno = NEON_SCALAR_INDEX (opnd);
20089 if (elsize == 16 && elno < 2 && regno < 16)
20090 return regno | (elno << 4);
20091 else if (elsize == 32 && elno == 0)
20094 first_error (_("scalar out of range"));
20101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
20102 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20103 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20104 constraint (inst.relocs[0].exp.X_op != O_constant,
20105 _("expression too complex"));
20106 unsigned rot = inst.relocs[0].exp.X_add_number;
20107 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
20108 _("immediate out of range"));
20111 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC))
20114 if (inst.operands[2].isscalar)
20116 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20117 first_error (_("invalid instruction shape"));
20118 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
20119 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20120 N_KEY | N_F16 | N_F32).size;
20121 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
20123 inst.instruction = 0xfe000800;
20124 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20125 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20126 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20127 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20128 inst.instruction |= LOW4 (m);
20129 inst.instruction |= HI1 (m) << 5;
20130 inst.instruction |= neon_quad (rs) << 6;
20131 inst.instruction |= rot << 20;
20132 inst.instruction |= (size == 32) << 23;
20136 enum neon_shape rs;
20137 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20138 rs = neon_select_shape (NS_QQQI, NS_NULL);
20140 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20142 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20143 N_KEY | N_F16 | N_F32).size;
20144 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
20145 && (inst.operands[0].reg == inst.operands[1].reg
20146 || inst.operands[0].reg == inst.operands[2].reg))
20147 as_tsktsk (BAD_MVE_SRCDEST);
20149 neon_three_same (neon_quad (rs), 0, -1);
20150 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20151 inst.instruction |= 0xfc200800;
20152 inst.instruction |= rot << 23;
20153 inst.instruction |= (size == 32) << 20;
20160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20161 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20162 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20163 constraint (inst.relocs[0].exp.X_op != O_constant,
20164 _("expression too complex"));
20166 unsigned rot = inst.relocs[0].exp.X_add_number;
20167 constraint (rot != 90 && rot != 270, _("immediate out of range"));
20168 enum neon_shape rs;
20169 struct neon_type_el et;
20170 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20172 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20173 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
20177 rs = neon_select_shape (NS_QQQI, NS_NULL);
20178 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
20180 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
20181 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20182 "operand makes instruction UNPREDICTABLE"));
20185 if (et.type == NT_invtype)
20188 if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8
20192 if (et.type == NT_float)
20194 neon_three_same (neon_quad (rs), 0, -1);
20195 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20196 inst.instruction |= 0xfc800800;
20197 inst.instruction |= (rot == 270) << 24;
20198 inst.instruction |= (et.size == 32) << 20;
20202 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
20203 inst.instruction = 0xfe000f00;
20204 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20205 inst.instruction |= neon_logbits (et.size) << 20;
20206 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20207 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20208 inst.instruction |= (rot == 270) << 12;
20209 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20210 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20211 inst.instruction |= LOW4 (inst.operands[2].reg);
20216 /* Dot Product instructions encoding support. */
20219 do_neon_dotproduct (int unsigned_p)
20221 enum neon_shape rs;
20222 unsigned scalar_oprd2 = 0;
20225 if (inst.cond != COND_ALWAYS)
20226 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20227 "is UNPREDICTABLE"));
20229 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
20232 /* Dot Product instructions are in three-same D/Q register format or the third
20233 operand can be a scalar index register. */
20234 if (inst.operands[2].isscalar)
20236 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
20237 high8 = 0xfe000000;
20238 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
20242 high8 = 0xfc000000;
20243 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
20247 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
20249 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
20251 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20252 Product instruction, so we pass 0 as the "ubit" parameter. And the
20253 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20254 neon_three_same (neon_quad (rs), 0, 32);
20256 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20257 different NEON three-same encoding. */
20258 inst.instruction &= 0x00ffffff;
20259 inst.instruction |= high8;
20260 /* Encode 'U' bit which indicates signedness. */
20261 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
20262 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20263 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20264 the instruction encoding. */
20265 if (inst.operands[2].isscalar)
20267 inst.instruction &= 0xffffffd0;
20268 inst.instruction |= LOW4 (scalar_oprd2);
20269 inst.instruction |= HI1 (scalar_oprd2) << 5;
20273 /* Dot Product instructions for signed integer. */
20276 do_neon_dotproduct_s (void)
20278 return do_neon_dotproduct (0);
20281 /* Dot Product instructions for unsigned integer. */
20284 do_neon_dotproduct_u (void)
20286 return do_neon_dotproduct (1);
20289 /* Crypto v1 instructions. */
20291 do_crypto_2op_1 (unsigned elttype, int op)
20293 set_pred_insn_type (OUTSIDE_PRED_INSN);
20295 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
20301 NEON_ENCODE (INTEGER, inst);
20302 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20303 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20304 inst.instruction |= LOW4 (inst.operands[1].reg);
20305 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20307 inst.instruction |= op << 6;
20310 inst.instruction |= 0xfc000000;
20312 inst.instruction |= 0xf0000000;
20316 do_crypto_3op_1 (int u, int op)
20318 set_pred_insn_type (OUTSIDE_PRED_INSN);
20320 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
20321 N_32 | N_UNT | N_KEY).type == NT_invtype)
20326 NEON_ENCODE (INTEGER, inst);
20327 neon_three_same (1, u, 8 << op);
20333 do_crypto_2op_1 (N_8, 0);
20339 do_crypto_2op_1 (N_8, 1);
20345 do_crypto_2op_1 (N_8, 2);
20351 do_crypto_2op_1 (N_8, 3);
20357 do_crypto_3op_1 (0, 0);
20363 do_crypto_3op_1 (0, 1);
20369 do_crypto_3op_1 (0, 2);
20375 do_crypto_3op_1 (0, 3);
20381 do_crypto_3op_1 (1, 0);
20387 do_crypto_3op_1 (1, 1);
20391 do_sha256su1 (void)
20393 do_crypto_3op_1 (1, 2);
20399 do_crypto_2op_1 (N_32, -1);
20405 do_crypto_2op_1 (N_32, 0);
20409 do_sha256su0 (void)
20411 do_crypto_2op_1 (N_32, 1);
20415 do_crc32_1 (unsigned int poly, unsigned int sz)
20417 unsigned int Rd = inst.operands[0].reg;
20418 unsigned int Rn = inst.operands[1].reg;
20419 unsigned int Rm = inst.operands[2].reg;
20421 set_pred_insn_type (OUTSIDE_PRED_INSN);
20422 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
20423 inst.instruction |= LOW4 (Rn) << 16;
20424 inst.instruction |= LOW4 (Rm);
20425 inst.instruction |= sz << (thumb_mode ? 4 : 21);
20426 inst.instruction |= poly << (thumb_mode ? 20 : 9);
20428 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
20429 as_warn (UNPRED_REG ("r15"));
20471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20473 neon_check_type (2, NS_FD, N_S32, N_F64);
20474 do_vfp_sp_dp_cvt ();
20475 do_vfp_cond_or_thumb ();
20479 /* Overall per-instruction processing. */
20481 /* We need to be able to fix up arbitrary expressions in some statements.
20482 This is so that we can handle symbols that are an arbitrary distance from
20483 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20484 which returns part of an address in a form which will be valid for
20485 a data instruction. We do this by pushing the expression into a symbol
20486 in the expr_section, and creating a fix for that. */
20489 fix_new_arm (fragS * frag,
20503 /* Create an absolute valued symbol, so we have something to
20504 refer to in the object file. Unfortunately for us, gas's
20505 generic expression parsing will already have folded out
20506 any use of .set foo/.type foo %function that may have
20507 been used to set type information of the target location,
20508 that's being specified symbolically. We have to presume
20509 the user knows what they are doing. */
20513 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
20515 symbol = symbol_find_or_make (name);
20516 S_SET_SEGMENT (symbol, absolute_section);
20517 symbol_set_frag (symbol, &zero_address_frag);
20518 S_SET_VALUE (symbol, exp->X_add_number);
20519 exp->X_op = O_symbol;
20520 exp->X_add_symbol = symbol;
20521 exp->X_add_number = 0;
20527 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
20528 (enum bfd_reloc_code_real) reloc);
20532 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
20533 pc_rel, (enum bfd_reloc_code_real) reloc);
20537 /* Mark whether the fix is to a THUMB instruction, or an ARM
20539 new_fix->tc_fix_data = thumb_mode;
20542 /* Create a frg for an instruction requiring relaxation. */
20544 output_relax_insn (void)
20550 /* The size of the instruction is unknown, so tie the debug info to the
20551 start of the instruction. */
20552 dwarf2_emit_insn (0);
20554 switch (inst.relocs[0].exp.X_op)
20557 sym = inst.relocs[0].exp.X_add_symbol;
20558 offset = inst.relocs[0].exp.X_add_number;
20562 offset = inst.relocs[0].exp.X_add_number;
20565 sym = make_expr_symbol (&inst.relocs[0].exp);
20569 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
20570 inst.relax, sym, offset, NULL/*offset, opcode*/);
20571 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
20574 /* Write a 32-bit thumb instruction to buf. */
20576 put_thumb32_insn (char * buf, unsigned long insn)
20578 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
20579 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
20583 output_inst (const char * str)
20589 as_bad ("%s -- `%s'", inst.error, str);
20594 output_relax_insn ();
20597 if (inst.size == 0)
20600 to = frag_more (inst.size);
20601 /* PR 9814: Record the thumb mode into the current frag so that we know
20602 what type of NOP padding to use, if necessary. We override any previous
20603 setting so that if the mode has changed then the NOPS that we use will
20604 match the encoding of the last instruction in the frag. */
20605 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20607 if (thumb_mode && (inst.size > THUMB_SIZE))
20609 gas_assert (inst.size == (2 * THUMB_SIZE));
20610 put_thumb32_insn (to, inst.instruction);
20612 else if (inst.size > INSN_SIZE)
20614 gas_assert (inst.size == (2 * INSN_SIZE));
20615 md_number_to_chars (to, inst.instruction, INSN_SIZE);
20616 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
20619 md_number_to_chars (to, inst.instruction, inst.size);
20622 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
20624 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
20625 fix_new_arm (frag_now, to - frag_now->fr_literal,
20626 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
20627 inst.relocs[r].type);
20630 dwarf2_emit_insn (inst.size);
20634 output_it_inst (int cond, int mask, char * to)
20636 unsigned long instruction = 0xbf00;
20639 instruction |= mask;
20640 instruction |= cond << 4;
20644 to = frag_more (2);
20646 dwarf2_emit_insn (2);
20650 md_number_to_chars (to, instruction, 2);
20655 /* Tag values used in struct asm_opcode's tag field. */
20658 OT_unconditional, /* Instruction cannot be conditionalized.
20659 The ARM condition field is still 0xE. */
20660 OT_unconditionalF, /* Instruction cannot be conditionalized
20661 and carries 0xF in its ARM condition field. */
20662 OT_csuffix, /* Instruction takes a conditional suffix. */
20663 OT_csuffixF, /* Some forms of the instruction take a scalar
20664 conditional suffix, others place 0xF where the
20665 condition field would be, others take a vector
20666 conditional suffix. */
20667 OT_cinfix3, /* Instruction takes a conditional infix,
20668 beginning at character index 3. (In
20669 unified mode, it becomes a suffix.) */
20670 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
20671 tsts, cmps, cmns, and teqs. */
20672 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
20673 character index 3, even in unified mode. Used for
20674 legacy instructions where suffix and infix forms
20675 may be ambiguous. */
20676 OT_csuf_or_in3, /* Instruction takes either a conditional
20677 suffix or an infix at character index 3. */
20678 OT_odd_infix_unc, /* This is the unconditional variant of an
20679 instruction that takes a conditional infix
20680 at an unusual position. In unified mode,
20681 this variant will accept a suffix. */
20682 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
20683 are the conditional variants of instructions that
20684 take conditional infixes in unusual positions.
20685 The infix appears at character index
20686 (tag - OT_odd_infix_0). These are not accepted
20687 in unified mode. */
20690 /* Subroutine of md_assemble, responsible for looking up the primary
20691 opcode from the mnemonic the user wrote. STR points to the
20692 beginning of the mnemonic.
20694 This is not simply a hash table lookup, because of conditional
20695 variants. Most instructions have conditional variants, which are
20696 expressed with a _conditional affix_ to the mnemonic. If we were
20697 to encode each conditional variant as a literal string in the opcode
20698 table, it would have approximately 20,000 entries.
20700 Most mnemonics take this affix as a suffix, and in unified syntax,
20701 'most' is upgraded to 'all'. However, in the divided syntax, some
20702 instructions take the affix as an infix, notably the s-variants of
20703 the arithmetic instructions. Of those instructions, all but six
20704 have the infix appear after the third character of the mnemonic.
20706 Accordingly, the algorithm for looking up primary opcodes given
20709 1. Look up the identifier in the opcode table.
20710 If we find a match, go to step U.
20712 2. Look up the last two characters of the identifier in the
20713 conditions table. If we find a match, look up the first N-2
20714 characters of the identifier in the opcode table. If we
20715 find a match, go to step CE.
20717 3. Look up the fourth and fifth characters of the identifier in
20718 the conditions table. If we find a match, extract those
20719 characters from the identifier, and look up the remaining
20720 characters in the opcode table. If we find a match, go
20725 U. Examine the tag field of the opcode structure, in case this is
20726 one of the six instructions with its conditional infix in an
20727 unusual place. If it is, the tag tells us where to find the
20728 infix; look it up in the conditions table and set inst.cond
20729 accordingly. Otherwise, this is an unconditional instruction.
20730 Again set inst.cond accordingly. Return the opcode structure.
20732 CE. Examine the tag field to make sure this is an instruction that
20733 should receive a conditional suffix. If it is not, fail.
20734 Otherwise, set inst.cond from the suffix we already looked up,
20735 and return the opcode structure.
20737 CM. Examine the tag field to make sure this is an instruction that
20738 should receive a conditional infix after the third character.
20739 If it is not, fail. Otherwise, undo the edits to the current
20740 line of input and proceed as for case CE. */
20742 static const struct asm_opcode *
20743 opcode_lookup (char **str)
20747 const struct asm_opcode *opcode;
20748 const struct asm_cond *cond;
20751 /* Scan up to the end of the mnemonic, which must end in white space,
20752 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20753 for (base = end = *str; *end != '\0'; end++)
20754 if (*end == ' ' || *end == '.')
20760 /* Handle a possible width suffix and/or Neon type suffix. */
20765 /* The .w and .n suffixes are only valid if the unified syntax is in
20767 if (unified_syntax && end[1] == 'w')
20769 else if (unified_syntax && end[1] == 'n')
20774 inst.vectype.elems = 0;
20776 *str = end + offset;
20778 if (end[offset] == '.')
20780 /* See if we have a Neon type suffix (possible in either unified or
20781 non-unified ARM syntax mode). */
20782 if (parse_neon_type (&inst.vectype, str) == FAIL)
20785 else if (end[offset] != '\0' && end[offset] != ' ')
20791 /* Look for unaffixed or special-case affixed mnemonic. */
20792 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20797 if (opcode->tag < OT_odd_infix_0)
20799 inst.cond = COND_ALWAYS;
20803 if (warn_on_deprecated && unified_syntax)
20804 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20805 affix = base + (opcode->tag - OT_odd_infix_0);
20806 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20809 inst.cond = cond->value;
20812 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20814 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20816 if (end - base < 2)
20819 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
20820 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20822 /* If this opcode can not be vector predicated then don't accept it with a
20823 vector predication code. */
20824 if (opcode && !opcode->mayBeVecPred)
20827 if (!opcode || !cond)
20829 /* Cannot have a conditional suffix on a mnemonic of less than two
20831 if (end - base < 3)
20834 /* Look for suffixed mnemonic. */
20836 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20837 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20841 if (opcode && cond)
20844 switch (opcode->tag)
20846 case OT_cinfix3_legacy:
20847 /* Ignore conditional suffixes matched on infix only mnemonics. */
20851 case OT_cinfix3_deprecated:
20852 case OT_odd_infix_unc:
20853 if (!unified_syntax)
20855 /* Fall through. */
20859 case OT_csuf_or_in3:
20860 inst.cond = cond->value;
20863 case OT_unconditional:
20864 case OT_unconditionalF:
20866 inst.cond = cond->value;
20869 /* Delayed diagnostic. */
20870 inst.error = BAD_COND;
20871 inst.cond = COND_ALWAYS;
20880 /* Cannot have a usual-position infix on a mnemonic of less than
20881 six characters (five would be a suffix). */
20882 if (end - base < 6)
20885 /* Look for infixed mnemonic in the usual position. */
20887 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
20891 memcpy (save, affix, 2);
20892 memmove (affix, affix + 2, (end - affix) - 2);
20893 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
20895 memmove (affix + 2, affix, (end - affix) - 2);
20896 memcpy (affix, save, 2);
20899 && (opcode->tag == OT_cinfix3
20900 || opcode->tag == OT_cinfix3_deprecated
20901 || opcode->tag == OT_csuf_or_in3
20902 || opcode->tag == OT_cinfix3_legacy))
20905 if (warn_on_deprecated && unified_syntax
20906 && (opcode->tag == OT_cinfix3
20907 || opcode->tag == OT_cinfix3_deprecated))
20908 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20910 inst.cond = cond->value;
20917 /* This function generates an initial IT instruction, leaving its block
20918 virtually open for the new instructions. Eventually,
20919 the mask will be updated by now_pred_add_mask () each time
20920 a new instruction needs to be included in the IT block.
20921 Finally, the block is closed with close_automatic_it_block ().
20922 The block closure can be requested either from md_assemble (),
20923 a tencode (), or due to a label hook. */
20926 new_automatic_it_block (int cond)
20928 now_pred.state = AUTOMATIC_PRED_BLOCK;
20929 now_pred.mask = 0x18;
20930 now_pred.cc = cond;
20931 now_pred.block_length = 1;
20932 mapping_state (MAP_THUMB);
20933 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
20934 now_pred.warn_deprecated = FALSE;
20935 now_pred.insn_cond = TRUE;
20938 /* Close an automatic IT block.
20939 See comments in new_automatic_it_block (). */
20942 close_automatic_it_block (void)
20944 now_pred.mask = 0x10;
20945 now_pred.block_length = 0;
20948 /* Update the mask of the current automatically-generated IT
20949 instruction. See comments in new_automatic_it_block (). */
20952 now_pred_add_mask (int cond)
20954 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20955 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20956 | ((bitvalue) << (nbit)))
20957 const int resulting_bit = (cond & 1);
20959 now_pred.mask &= 0xf;
20960 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
20962 (5 - now_pred.block_length));
20963 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
20965 ((5 - now_pred.block_length) - 1));
20966 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
20969 #undef SET_BIT_VALUE
20972 /* The IT blocks handling machinery is accessed through the these functions:
20973 it_fsm_pre_encode () from md_assemble ()
20974 set_pred_insn_type () optional, from the tencode functions
20975 set_pred_insn_type_last () ditto
20976 in_pred_block () ditto
20977 it_fsm_post_encode () from md_assemble ()
20978 force_automatic_it_block_close () from label handling functions
20981 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20982 initializing the IT insn type with a generic initial value depending
20983 on the inst.condition.
20984 2) During the tencode function, two things may happen:
20985 a) The tencode function overrides the IT insn type by
20986 calling either set_pred_insn_type (type) or
20987 set_pred_insn_type_last ().
20988 b) The tencode function queries the IT block state by
20989 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20991 Both set_pred_insn_type and in_pred_block run the internal FSM state
20992 handling function (handle_pred_state), because: a) setting the IT insn
20993 type may incur in an invalid state (exiting the function),
20994 and b) querying the state requires the FSM to be updated.
20995 Specifically we want to avoid creating an IT block for conditional
20996 branches, so it_fsm_pre_encode is actually a guess and we can't
20997 determine whether an IT block is required until the tencode () routine
20998 has decided what type of instruction this actually it.
20999 Because of this, if set_pred_insn_type and in_pred_block have to be
21000 used, set_pred_insn_type has to be called first.
21002 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21003 that determines the insn IT type depending on the inst.cond code.
21004 When a tencode () routine encodes an instruction that can be
21005 either outside an IT block, or, in the case of being inside, has to be
21006 the last one, set_pred_insn_type_last () will determine the proper
21007 IT instruction type based on the inst.cond code. Otherwise,
21008 set_pred_insn_type can be called for overriding that logic or
21009 for covering other cases.
21011 Calling handle_pred_state () may not transition the IT block state to
21012 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21013 still queried. Instead, if the FSM determines that the state should
21014 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21015 after the tencode () function: that's what it_fsm_post_encode () does.
21017 Since in_pred_block () calls the state handling function to get an
21018 updated state, an error may occur (due to invalid insns combination).
21019 In that case, inst.error is set.
21020 Therefore, inst.error has to be checked after the execution of
21021 the tencode () routine.
21023 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21024 any pending state change (if any) that didn't take place in
21025 handle_pred_state () as explained above. */
21028 it_fsm_pre_encode (void)
21030 if (inst.cond != COND_ALWAYS)
21031 inst.pred_insn_type = INSIDE_IT_INSN;
21033 inst.pred_insn_type = OUTSIDE_PRED_INSN;
21035 now_pred.state_handled = 0;
21038 /* IT state FSM handling function. */
21039 /* MVE instructions and non-MVE instructions are handled differently because of
21040 the introduction of VPT blocks.
21041 Specifications say that any non-MVE instruction inside a VPT block is
21042 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21043 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21044 few exceptions we have MVE_UNPREDICABLE_INSN.
21045 The error messages provided depending on the different combinations possible
21046 are described in the cases below:
21047 For 'most' MVE instructions:
21048 1) In an IT block, with an IT code: syntax error
21049 2) In an IT block, with a VPT code: error: must be in a VPT block
21050 3) In an IT block, with no code: warning: UNPREDICTABLE
21051 4) In a VPT block, with an IT code: syntax error
21052 5) In a VPT block, with a VPT code: OK!
21053 6) In a VPT block, with no code: error: missing code
21054 7) Outside a pred block, with an IT code: error: syntax error
21055 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21056 9) Outside a pred block, with no code: OK!
21057 For non-MVE instructions:
21058 10) In an IT block, with an IT code: OK!
21059 11) In an IT block, with a VPT code: syntax error
21060 12) In an IT block, with no code: error: missing code
21061 13) In a VPT block, with an IT code: error: should be in an IT block
21062 14) In a VPT block, with a VPT code: syntax error
21063 15) In a VPT block, with no code: UNPREDICTABLE
21064 16) Outside a pred block, with an IT code: error: should be in an IT block
21065 17) Outside a pred block, with a VPT code: syntax error
21066 18) Outside a pred block, with no code: OK!
21071 handle_pred_state (void)
21073 now_pred.state_handled = 1;
21074 now_pred.insn_cond = FALSE;
21076 switch (now_pred.state)
21078 case OUTSIDE_PRED_BLOCK:
21079 switch (inst.pred_insn_type)
21081 case MVE_UNPREDICABLE_INSN:
21082 case MVE_OUTSIDE_PRED_INSN:
21083 if (inst.cond < COND_ALWAYS)
21085 /* Case 7: Outside a pred block, with an IT code: error: syntax
21087 inst.error = BAD_SYNTAX;
21090 /* Case 9: Outside a pred block, with no code: OK! */
21092 case OUTSIDE_PRED_INSN:
21093 if (inst.cond > COND_ALWAYS)
21095 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21097 inst.error = BAD_SYNTAX;
21100 /* Case 18: Outside a pred block, with no code: OK! */
21103 case INSIDE_VPT_INSN:
21104 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21106 inst.error = BAD_OUT_VPT;
21109 case INSIDE_IT_INSN:
21110 case INSIDE_IT_LAST_INSN:
21111 if (inst.cond < COND_ALWAYS)
21113 /* Case 16: Outside a pred block, with an IT code: error: should
21114 be in an IT block. */
21115 if (thumb_mode == 0)
21118 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
21119 as_tsktsk (_("Warning: conditional outside an IT block"\
21124 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
21125 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
21127 /* Automatically generate the IT instruction. */
21128 new_automatic_it_block (inst.cond);
21129 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
21130 close_automatic_it_block ();
21134 inst.error = BAD_OUT_IT;
21140 else if (inst.cond > COND_ALWAYS)
21142 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21144 inst.error = BAD_SYNTAX;
21149 case IF_INSIDE_IT_LAST_INSN:
21150 case NEUTRAL_IT_INSN:
21154 if (inst.cond != COND_ALWAYS)
21155 first_error (BAD_SYNTAX);
21156 now_pred.state = MANUAL_PRED_BLOCK;
21157 now_pred.block_length = 0;
21158 now_pred.type = VECTOR_PRED;
21162 now_pred.state = MANUAL_PRED_BLOCK;
21163 now_pred.block_length = 0;
21164 now_pred.type = SCALAR_PRED;
21169 case AUTOMATIC_PRED_BLOCK:
21170 /* Three things may happen now:
21171 a) We should increment current it block size;
21172 b) We should close current it block (closing insn or 4 insns);
21173 c) We should close current it block and start a new one (due
21174 to incompatible conditions or
21175 4 insns-length block reached). */
21177 switch (inst.pred_insn_type)
21179 case INSIDE_VPT_INSN:
21181 case MVE_UNPREDICABLE_INSN:
21182 case MVE_OUTSIDE_PRED_INSN:
21184 case OUTSIDE_PRED_INSN:
21185 /* The closure of the block shall happen immediately,
21186 so any in_pred_block () call reports the block as closed. */
21187 force_automatic_it_block_close ();
21190 case INSIDE_IT_INSN:
21191 case INSIDE_IT_LAST_INSN:
21192 case IF_INSIDE_IT_LAST_INSN:
21193 now_pred.block_length++;
21195 if (now_pred.block_length > 4
21196 || !now_pred_compatible (inst.cond))
21198 force_automatic_it_block_close ();
21199 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
21200 new_automatic_it_block (inst.cond);
21204 now_pred.insn_cond = TRUE;
21205 now_pred_add_mask (inst.cond);
21208 if (now_pred.state == AUTOMATIC_PRED_BLOCK
21209 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
21210 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
21211 close_automatic_it_block ();
21214 case NEUTRAL_IT_INSN:
21215 now_pred.block_length++;
21216 now_pred.insn_cond = TRUE;
21218 if (now_pred.block_length > 4)
21219 force_automatic_it_block_close ();
21221 now_pred_add_mask (now_pred.cc & 1);
21225 close_automatic_it_block ();
21226 now_pred.state = MANUAL_PRED_BLOCK;
21231 case MANUAL_PRED_BLOCK:
21234 if (now_pred.type == SCALAR_PRED)
21236 /* Check conditional suffixes. */
21237 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
21238 now_pred.mask <<= 1;
21239 now_pred.mask &= 0x1f;
21240 is_last = (now_pred.mask == 0x10);
21244 now_pred.cc ^= (now_pred.mask >> 4);
21245 cond = now_pred.cc + 0xf;
21246 now_pred.mask <<= 1;
21247 now_pred.mask &= 0x1f;
21248 is_last = now_pred.mask == 0x10;
21250 now_pred.insn_cond = TRUE;
21252 switch (inst.pred_insn_type)
21254 case OUTSIDE_PRED_INSN:
21255 if (now_pred.type == SCALAR_PRED)
21257 if (inst.cond == COND_ALWAYS)
21259 /* Case 12: In an IT block, with no code: error: missing
21261 inst.error = BAD_NOT_IT;
21264 else if (inst.cond > COND_ALWAYS)
21266 /* Case 11: In an IT block, with a VPT code: syntax error.
21268 inst.error = BAD_SYNTAX;
21271 else if (thumb_mode)
21273 /* This is for some special cases where a non-MVE
21274 instruction is not allowed in an IT block, such as cbz,
21275 but are put into one with a condition code.
21276 You could argue this should be a syntax error, but we
21277 gave the 'not allowed in IT block' diagnostic in the
21278 past so we will keep doing so. */
21279 inst.error = BAD_NOT_IT;
21286 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21287 as_tsktsk (MVE_NOT_VPT);
21290 case MVE_OUTSIDE_PRED_INSN:
21291 if (now_pred.type == SCALAR_PRED)
21293 if (inst.cond == COND_ALWAYS)
21295 /* Case 3: In an IT block, with no code: warning:
21297 as_tsktsk (MVE_NOT_IT);
21300 else if (inst.cond < COND_ALWAYS)
21302 /* Case 1: In an IT block, with an IT code: syntax error.
21304 inst.error = BAD_SYNTAX;
21312 if (inst.cond < COND_ALWAYS)
21314 /* Case 4: In a VPT block, with an IT code: syntax error.
21316 inst.error = BAD_SYNTAX;
21319 else if (inst.cond == COND_ALWAYS)
21321 /* Case 6: In a VPT block, with no code: error: missing
21323 inst.error = BAD_NOT_VPT;
21331 case MVE_UNPREDICABLE_INSN:
21332 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
21334 case INSIDE_IT_INSN:
21335 if (inst.cond > COND_ALWAYS)
21337 /* Case 11: In an IT block, with a VPT code: syntax error. */
21338 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21339 inst.error = BAD_SYNTAX;
21342 else if (now_pred.type == SCALAR_PRED)
21344 /* Case 10: In an IT block, with an IT code: OK! */
21345 if (cond != inst.cond)
21347 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
21354 /* Case 13: In a VPT block, with an IT code: error: should be
21356 inst.error = BAD_OUT_IT;
21361 case INSIDE_VPT_INSN:
21362 if (now_pred.type == SCALAR_PRED)
21364 /* Case 2: In an IT block, with a VPT code: error: must be in a
21366 inst.error = BAD_OUT_VPT;
21369 /* Case 5: In a VPT block, with a VPT code: OK! */
21370 else if (cond != inst.cond)
21372 inst.error = BAD_VPT_COND;
21376 case INSIDE_IT_LAST_INSN:
21377 case IF_INSIDE_IT_LAST_INSN:
21378 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
21380 /* Case 4: In a VPT block, with an IT code: syntax error. */
21381 /* Case 11: In an IT block, with a VPT code: syntax error. */
21382 inst.error = BAD_SYNTAX;
21385 else if (cond != inst.cond)
21387 inst.error = BAD_IT_COND;
21392 inst.error = BAD_BRANCH;
21397 case NEUTRAL_IT_INSN:
21398 /* The BKPT instruction is unconditional even in a IT or VPT
21403 if (now_pred.type == SCALAR_PRED)
21405 inst.error = BAD_IT_IT;
21408 /* fall through. */
21410 if (inst.cond == COND_ALWAYS)
21412 /* Executing a VPT/VPST instruction inside an IT block or a
21413 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21415 if (now_pred.type == SCALAR_PRED)
21416 as_tsktsk (MVE_NOT_IT);
21418 as_tsktsk (MVE_NOT_VPT);
21423 /* VPT/VPST do not accept condition codes. */
21424 inst.error = BAD_SYNTAX;
21435 struct depr_insn_mask
21437 unsigned long pattern;
21438 unsigned long mask;
21439 const char* description;
21442 /* List of 16-bit instruction patterns deprecated in an IT block in
21444 static const struct depr_insn_mask depr_it_insns[] = {
21445 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21446 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21447 { 0xa000, 0xb800, N_("ADR") },
21448 { 0x4800, 0xf800, N_("Literal loads") },
21449 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21450 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21451 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21452 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21453 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21458 it_fsm_post_encode (void)
21462 if (!now_pred.state_handled)
21463 handle_pred_state ();
21465 if (now_pred.insn_cond
21466 && !now_pred.warn_deprecated
21467 && warn_on_deprecated
21468 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
21469 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
21471 if (inst.instruction >= 0x10000)
21473 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21474 "performance deprecated in ARMv8-A and ARMv8-R"));
21475 now_pred.warn_deprecated = TRUE;
21479 const struct depr_insn_mask *p = depr_it_insns;
21481 while (p->mask != 0)
21483 if ((inst.instruction & p->mask) == p->pattern)
21485 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21486 "instructions of the following class are "
21487 "performance deprecated in ARMv8-A and "
21488 "ARMv8-R: %s"), p->description);
21489 now_pred.warn_deprecated = TRUE;
21497 if (now_pred.block_length > 1)
21499 as_tsktsk (_("IT blocks containing more than one conditional "
21500 "instruction are performance deprecated in ARMv8-A and "
21502 now_pred.warn_deprecated = TRUE;
21506 is_last = (now_pred.mask == 0x10);
21509 now_pred.state = OUTSIDE_PRED_BLOCK;
21515 force_automatic_it_block_close (void)
21517 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
21519 close_automatic_it_block ();
21520 now_pred.state = OUTSIDE_PRED_BLOCK;
21526 in_pred_block (void)
21528 if (!now_pred.state_handled)
21529 handle_pred_state ();
21531 return now_pred.state != OUTSIDE_PRED_BLOCK;
21534 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21535 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21536 here, hence the "known" in the function name. */
21539 known_t32_only_insn (const struct asm_opcode *opcode)
21541 /* Original Thumb-1 wide instruction. */
21542 if (opcode->tencode == do_t_blx
21543 || opcode->tencode == do_t_branch23
21544 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
21545 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
21548 /* Wide-only instruction added to ARMv8-M Baseline. */
21549 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
21550 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
21551 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
21552 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
21558 /* Whether wide instruction variant can be used if available for a valid OPCODE
21562 t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
21564 if (known_t32_only_insn (opcode))
21567 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21568 of variant T3 of B.W is checked in do_t_branch. */
21569 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
21570 && opcode->tencode == do_t_branch)
21573 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21574 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
21575 && opcode->tencode == do_t_mov_cmp
21576 /* Make sure CMP instruction is not affected. */
21577 && opcode->aencode == do_mov)
21580 /* Wide instruction variants of all instructions with narrow *and* wide
21581 variants become available with ARMv6t2. Other opcodes are either
21582 narrow-only or wide-only and are thus available if OPCODE is valid. */
21583 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
21586 /* OPCODE with narrow only instruction variant or wide variant not
21592 md_assemble (char *str)
21595 const struct asm_opcode * opcode;
21597 /* Align the previous label if needed. */
21598 if (last_label_seen != NULL)
21600 symbol_set_frag (last_label_seen, frag_now);
21601 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
21602 S_SET_SEGMENT (last_label_seen, now_seg);
21605 memset (&inst, '\0', sizeof (inst));
21607 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21608 inst.relocs[r].type = BFD_RELOC_UNUSED;
21610 opcode = opcode_lookup (&p);
21613 /* It wasn't an instruction, but it might be a register alias of
21614 the form alias .req reg, or a Neon .dn/.qn directive. */
21615 if (! create_register_alias (str, p)
21616 && ! create_neon_reg_alias (str, p))
21617 as_bad (_("bad instruction `%s'"), str);
21622 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
21623 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21625 /* The value which unconditional instructions should have in place of the
21626 condition field. */
21627 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
21631 arm_feature_set variant;
21633 variant = cpu_variant;
21634 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21635 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
21636 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
21637 /* Check that this instruction is supported for this CPU. */
21638 if (!opcode->tvariant
21639 || (thumb_mode == 1
21640 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
21642 if (opcode->tencode == do_t_swi)
21643 as_bad (_("SVC is not permitted on this architecture"));
21645 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
21648 if (inst.cond != COND_ALWAYS && !unified_syntax
21649 && opcode->tencode != do_t_branch)
21651 as_bad (_("Thumb does not support conditional execution"));
21655 /* Two things are addressed here:
21656 1) Implicit require narrow instructions on Thumb-1.
21657 This avoids relaxation accidentally introducing Thumb-2
21659 2) Reject wide instructions in non Thumb-2 cores.
21661 Only instructions with narrow and wide variants need to be handled
21662 but selecting all non wide-only instructions is easier. */
21663 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
21664 && !t32_insn_ok (variant, opcode))
21666 if (inst.size_req == 0)
21668 else if (inst.size_req == 4)
21670 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
21671 as_bad (_("selected processor does not support 32bit wide "
21672 "variant of instruction `%s'"), str);
21674 as_bad (_("selected processor does not support `%s' in "
21675 "Thumb-2 mode"), str);
21680 inst.instruction = opcode->tvalue;
21682 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
21684 /* Prepare the pred_insn_type for those encodings that don't set
21686 it_fsm_pre_encode ();
21688 opcode->tencode ();
21690 it_fsm_post_encode ();
21693 if (!(inst.error || inst.relax))
21695 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
21696 inst.size = (inst.instruction > 0xffff ? 4 : 2);
21697 if (inst.size_req && inst.size_req != inst.size)
21699 as_bad (_("cannot honor width suffix -- `%s'"), str);
21704 /* Something has gone badly wrong if we try to relax a fixed size
21706 gas_assert (inst.size_req == 0 || !inst.relax);
21708 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
21709 *opcode->tvariant);
21710 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21711 set those bits when Thumb-2 32-bit instructions are seen. The impact
21712 of relaxable instructions will be considered later after we finish all
21714 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
21715 variant = arm_arch_none;
21717 variant = cpu_variant;
21718 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
21719 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
21722 check_neon_suffixes;
21726 mapping_state (MAP_THUMB);
21729 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
21733 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21734 is_bx = (opcode->aencode == do_bx);
21736 /* Check that this instruction is supported for this CPU. */
21737 if (!(is_bx && fix_v4bx)
21738 && !(opcode->avariant &&
21739 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
21741 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
21746 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
21750 inst.instruction = opcode->avalue;
21751 if (opcode->tag == OT_unconditionalF)
21752 inst.instruction |= 0xFU << 28;
21754 inst.instruction |= inst.cond << 28;
21755 inst.size = INSN_SIZE;
21756 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
21758 it_fsm_pre_encode ();
21759 opcode->aencode ();
21760 it_fsm_post_encode ();
21762 /* Arm mode bx is marked as both v4T and v5 because it's still required
21763 on a hypothetical non-thumb v5 core. */
21765 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
21767 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
21768 *opcode->avariant);
21770 check_neon_suffixes;
21774 mapping_state (MAP_ARM);
21779 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21787 check_pred_blocks_finished (void)
21792 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
21793 if (seg_info (sect)->tc_segment_info_data.current_pred.state
21794 == MANUAL_PRED_BLOCK)
21796 if (now_pred.type == SCALAR_PRED)
21797 as_warn (_("section '%s' finished with an open IT block."),
21800 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21804 if (now_pred.state == MANUAL_PRED_BLOCK)
21806 if (now_pred.type == SCALAR_PRED)
21807 as_warn (_("file finished with an open IT block."));
21809 as_warn (_("file finished with an open VPT/VPST block."));
21814 /* Various frobbings of labels and their addresses. */
21817 arm_start_line_hook (void)
21819 last_label_seen = NULL;
21823 arm_frob_label (symbolS * sym)
21825 last_label_seen = sym;
21827 ARM_SET_THUMB (sym, thumb_mode);
21829 #if defined OBJ_COFF || defined OBJ_ELF
21830 ARM_SET_INTERWORK (sym, support_interwork);
21833 force_automatic_it_block_close ();
21835 /* Note - do not allow local symbols (.Lxxx) to be labelled
21836 as Thumb functions. This is because these labels, whilst
21837 they exist inside Thumb code, are not the entry points for
21838 possible ARM->Thumb calls. Also, these labels can be used
21839 as part of a computed goto or switch statement. eg gcc
21840 can generate code that looks like this:
21842 ldr r2, [pc, .Laaa]
21852 The first instruction loads the address of the jump table.
21853 The second instruction converts a table index into a byte offset.
21854 The third instruction gets the jump address out of the table.
21855 The fourth instruction performs the jump.
21857 If the address stored at .Laaa is that of a symbol which has the
21858 Thumb_Func bit set, then the linker will arrange for this address
21859 to have the bottom bit set, which in turn would mean that the
21860 address computation performed by the third instruction would end
21861 up with the bottom bit set. Since the ARM is capable of unaligned
21862 word loads, the instruction would then load the incorrect address
21863 out of the jump table, and chaos would ensue. */
21864 if (label_is_thumb_function_name
21865 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
21866 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
21868 /* When the address of a Thumb function is taken the bottom
21869 bit of that address should be set. This will allow
21870 interworking between Arm and Thumb functions to work
21873 THUMB_SET_FUNC (sym, 1);
21875 label_is_thumb_function_name = FALSE;
21878 dwarf2_emit_label (sym);
21882 arm_data_in_code (void)
21884 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
21886 *input_line_pointer = '/';
21887 input_line_pointer += 5;
21888 *input_line_pointer = 0;
21896 arm_canonicalize_symbol_name (char * name)
21900 if (thumb_mode && (len = strlen (name)) > 5
21901 && streq (name + len - 5, "/data"))
21902 *(name + len - 5) = 0;
21907 /* Table of all register names defined by default. The user can
21908 define additional names with .req. Note that all register names
21909 should appear in both upper and lowercase variants. Some registers
21910 also have mixed-case names. */
21912 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21913 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21914 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21915 #define REGSET(p,t) \
21916 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21917 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21918 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21919 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21920 #define REGSETH(p,t) \
21921 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21922 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21923 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21924 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21925 #define REGSET2(p,t) \
21926 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21927 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21928 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21929 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21930 #define SPLRBANK(base,bank,t) \
21931 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21932 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21933 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21934 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21935 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21936 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21938 static const struct reg_entry reg_names[] =
21940 /* ARM integer registers. */
21941 REGSET(r, RN), REGSET(R, RN),
21943 /* ATPCS synonyms. */
21944 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
21945 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
21946 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
21948 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
21949 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
21950 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
21952 /* Well-known aliases. */
21953 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
21954 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
21956 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
21957 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
21959 /* Defining the new Zero register from ARMv8.1-M. */
21963 /* Coprocessor numbers. */
21964 REGSET(p, CP), REGSET(P, CP),
21966 /* Coprocessor register numbers. The "cr" variants are for backward
21968 REGSET(c, CN), REGSET(C, CN),
21969 REGSET(cr, CN), REGSET(CR, CN),
21971 /* ARM banked registers. */
21972 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
21973 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
21974 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
21975 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
21976 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
21977 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
21978 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
21980 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
21981 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
21982 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
21983 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
21984 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
21985 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
21986 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
21987 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
21989 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
21990 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
21991 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
21992 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
21993 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
21994 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
21995 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
21996 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
21997 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
21999 /* FPA registers. */
22000 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
22001 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
22003 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
22004 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
22006 /* VFP SP registers. */
22007 REGSET(s,VFS), REGSET(S,VFS),
22008 REGSETH(s,VFS), REGSETH(S,VFS),
22010 /* VFP DP Registers. */
22011 REGSET(d,VFD), REGSET(D,VFD),
22012 /* Extra Neon DP registers. */
22013 REGSETH(d,VFD), REGSETH(D,VFD),
22015 /* Neon QP registers. */
22016 REGSET2(q,NQ), REGSET2(Q,NQ),
22018 /* VFP control registers. */
22019 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
22020 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
22021 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
22022 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
22023 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
22024 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
22025 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
22027 /* Maverick DSP coprocessor registers. */
22028 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
22029 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
22031 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
22032 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
22033 REGDEF(dspsc,0,DSPSC),
22035 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
22036 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
22037 REGDEF(DSPSC,0,DSPSC),
22039 /* iWMMXt data registers - p0, c0-15. */
22040 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
22042 /* iWMMXt control registers - p1, c0-3. */
22043 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
22044 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
22045 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
22046 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
22048 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22049 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
22050 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
22051 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
22052 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
22054 /* XScale accumulator registers. */
22055 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
22061 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22062 within psr_required_here. */
22063 static const struct asm_psr psrs[] =
22065 /* Backward compatibility notation. Note that "all" is no longer
22066 truly all possible PSR bits. */
22067 {"all", PSR_c | PSR_f},
22071 /* Individual flags. */
22077 /* Combinations of flags. */
22078 {"fs", PSR_f | PSR_s},
22079 {"fx", PSR_f | PSR_x},
22080 {"fc", PSR_f | PSR_c},
22081 {"sf", PSR_s | PSR_f},
22082 {"sx", PSR_s | PSR_x},
22083 {"sc", PSR_s | PSR_c},
22084 {"xf", PSR_x | PSR_f},
22085 {"xs", PSR_x | PSR_s},
22086 {"xc", PSR_x | PSR_c},
22087 {"cf", PSR_c | PSR_f},
22088 {"cs", PSR_c | PSR_s},
22089 {"cx", PSR_c | PSR_x},
22090 {"fsx", PSR_f | PSR_s | PSR_x},
22091 {"fsc", PSR_f | PSR_s | PSR_c},
22092 {"fxs", PSR_f | PSR_x | PSR_s},
22093 {"fxc", PSR_f | PSR_x | PSR_c},
22094 {"fcs", PSR_f | PSR_c | PSR_s},
22095 {"fcx", PSR_f | PSR_c | PSR_x},
22096 {"sfx", PSR_s | PSR_f | PSR_x},
22097 {"sfc", PSR_s | PSR_f | PSR_c},
22098 {"sxf", PSR_s | PSR_x | PSR_f},
22099 {"sxc", PSR_s | PSR_x | PSR_c},
22100 {"scf", PSR_s | PSR_c | PSR_f},
22101 {"scx", PSR_s | PSR_c | PSR_x},
22102 {"xfs", PSR_x | PSR_f | PSR_s},
22103 {"xfc", PSR_x | PSR_f | PSR_c},
22104 {"xsf", PSR_x | PSR_s | PSR_f},
22105 {"xsc", PSR_x | PSR_s | PSR_c},
22106 {"xcf", PSR_x | PSR_c | PSR_f},
22107 {"xcs", PSR_x | PSR_c | PSR_s},
22108 {"cfs", PSR_c | PSR_f | PSR_s},
22109 {"cfx", PSR_c | PSR_f | PSR_x},
22110 {"csf", PSR_c | PSR_s | PSR_f},
22111 {"csx", PSR_c | PSR_s | PSR_x},
22112 {"cxf", PSR_c | PSR_x | PSR_f},
22113 {"cxs", PSR_c | PSR_x | PSR_s},
22114 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
22115 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
22116 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
22117 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
22118 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
22119 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
22120 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
22121 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
22122 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
22123 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
22124 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
22125 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
22126 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
22127 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
22128 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
22129 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
22130 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
22131 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
22132 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
22133 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
22134 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
22135 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
22136 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
22137 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
22140 /* Table of V7M psr names. */
22141 static const struct asm_psr v7m_psrs[] =
22143 {"apsr", 0x0 }, {"APSR", 0x0 },
22144 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22145 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22146 {"psr", 0x3 }, {"PSR", 0x3 },
22147 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22148 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22149 {"epsr", 0x6 }, {"EPSR", 0x6 },
22150 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22151 {"msp", 0x8 }, {"MSP", 0x8 },
22152 {"psp", 0x9 }, {"PSP", 0x9 },
22153 {"msplim", 0xa }, {"MSPLIM", 0xa },
22154 {"psplim", 0xb }, {"PSPLIM", 0xb },
22155 {"primask", 0x10}, {"PRIMASK", 0x10},
22156 {"basepri", 0x11}, {"BASEPRI", 0x11},
22157 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22158 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22159 {"control", 0x14}, {"CONTROL", 0x14},
22160 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22161 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22162 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22163 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22164 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22165 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22166 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22167 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22168 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22171 /* Table of all shift-in-operand names. */
22172 static const struct asm_shift_name shift_names [] =
22174 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
22175 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
22176 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
22177 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
22178 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
22179 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
22180 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
22183 /* Table of all explicit relocation names. */
22185 static struct reloc_entry reloc_names[] =
22187 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
22188 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
22189 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
22190 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
22191 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
22192 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
22193 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
22194 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
22195 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
22196 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
22197 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
22198 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
22199 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
22200 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
22201 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
22202 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
22203 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
22204 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
22205 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
22206 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
22207 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22208 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22209 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
22210 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
22211 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
22212 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
22213 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
22217 /* Table of all conditional affixes. */
22218 static const struct asm_cond conds[] =
22222 {"cs", 0x2}, {"hs", 0x2},
22223 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22236 static const struct asm_cond vconds[] =
22242 #define UL_BARRIER(L,U,CODE,FEAT) \
22243 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22244 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22246 static struct asm_barrier_opt barrier_opt_names[] =
22248 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
22249 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
22250 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
22251 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
22252 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
22253 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
22254 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
22255 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
22256 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
22257 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
22258 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
22259 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
22260 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
22261 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
22262 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
22263 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
22268 /* Table of ARM-format instructions. */
22270 /* Macros for gluing together operand strings. N.B. In all cases
22271 other than OPS0, the trailing OP_stop comes from default
22272 zero-initialization of the unspecified elements of the array. */
22273 #define OPS0() { OP_stop, }
22274 #define OPS1(a) { OP_##a, }
22275 #define OPS2(a,b) { OP_##a,OP_##b, }
22276 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22277 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22278 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22279 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22281 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22282 This is useful when mixing operands for ARM and THUMB, i.e. using the
22283 MIX_ARM_THUMB_OPERANDS macro.
22284 In order to use these macros, prefix the number of operands with _
22286 #define OPS_1(a) { a, }
22287 #define OPS_2(a,b) { a,b, }
22288 #define OPS_3(a,b,c) { a,b,c, }
22289 #define OPS_4(a,b,c,d) { a,b,c,d, }
22290 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22291 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22293 /* These macros abstract out the exact format of the mnemonic table and
22294 save some repeated characters. */
22296 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22297 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22298 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22299 THUMB_VARIANT, do_##ae, do_##te, 0 }
22301 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22302 a T_MNEM_xyz enumerator. */
22303 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22304 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22305 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22306 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22308 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22309 infix after the third character. */
22310 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22311 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22312 THUMB_VARIANT, do_##ae, do_##te, 0 }
22313 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22314 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22315 THUMB_VARIANT, do_##ae, do_##te, 0 }
22316 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22317 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22318 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22319 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22320 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22321 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22322 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22323 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22325 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22326 field is still 0xE. Many of the Thumb variants can be executed
22327 conditionally, so this is checked separately. */
22328 #define TUE(mnem, op, top, nops, ops, ae, te) \
22329 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22330 THUMB_VARIANT, do_##ae, do_##te, 0 }
22332 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22333 Used by mnemonics that have very minimal differences in the encoding for
22334 ARM and Thumb variants and can be handled in a common function. */
22335 #define TUEc(mnem, op, top, nops, ops, en) \
22336 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22337 THUMB_VARIANT, do_##en, do_##en, 0 }
22339 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22340 condition code field. */
22341 #define TUF(mnem, op, top, nops, ops, ae, te) \
22342 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22343 THUMB_VARIANT, do_##ae, do_##te, 0 }
22345 /* ARM-only variants of all the above. */
22346 #define CE(mnem, op, nops, ops, ae) \
22347 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22349 #define C3(mnem, op, nops, ops, ae) \
22350 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22352 /* Thumb-only variants of TCE and TUE. */
22353 #define ToC(mnem, top, nops, ops, te) \
22354 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22357 #define ToU(mnem, top, nops, ops, te) \
22358 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22361 /* T_MNEM_xyz enumerator variants of ToC. */
22362 #define toC(mnem, top, nops, ops, te) \
22363 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22366 /* T_MNEM_xyz enumerator variants of ToU. */
22367 #define toU(mnem, top, nops, ops, te) \
22368 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22371 /* Legacy mnemonics that always have conditional infix after the third
22373 #define CL(mnem, op, nops, ops, ae) \
22374 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22375 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22377 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22378 #define cCE(mnem, op, nops, ops, ae) \
22379 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22381 /* mov instructions that are shared between coprocessor and MVE. */
22382 #define mcCE(mnem, op, nops, ops, ae) \
22383 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22385 /* Legacy coprocessor instructions where conditional infix and conditional
22386 suffix are ambiguous. For consistency this includes all FPA instructions,
22387 not just the potentially ambiguous ones. */
22388 #define cCL(mnem, op, nops, ops, ae) \
22389 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22390 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22392 /* Coprocessor, takes either a suffix or a position-3 infix
22393 (for an FPA corner case). */
22394 #define C3E(mnem, op, nops, ops, ae) \
22395 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22396 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22398 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22399 { m1 #m2 m3, OPS##nops ops, \
22400 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22401 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22403 #define CM(m1, m2, op, nops, ops, ae) \
22404 xCM_ (m1, , m2, op, nops, ops, ae), \
22405 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22406 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22407 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22408 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22409 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22410 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22411 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22412 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22413 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22414 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22415 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22416 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22417 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22418 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22419 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22420 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22421 xCM_ (m1, le, m2, op, nops, ops, ae), \
22422 xCM_ (m1, al, m2, op, nops, ops, ae)
22424 #define UE(mnem, op, nops, ops, ae) \
22425 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22427 #define UF(mnem, op, nops, ops, ae) \
22428 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22430 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22431 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22432 use the same encoding function for each. */
22433 #define NUF(mnem, op, nops, ops, enc) \
22434 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22435 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22437 /* Neon data processing, version which indirects through neon_enc_tab for
22438 the various overloaded versions of opcodes. */
22439 #define nUF(mnem, op, nops, ops, enc) \
22440 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22441 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22443 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22445 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22446 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22447 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22449 #define NCE(mnem, op, nops, ops, enc) \
22450 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22452 #define NCEF(mnem, op, nops, ops, enc) \
22453 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22455 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22456 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22457 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22458 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22460 #define nCE(mnem, op, nops, ops, enc) \
22461 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22463 #define nCEF(mnem, op, nops, ops, enc) \
22464 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22467 #define mCEF(mnem, op, nops, ops, enc) \
22468 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22469 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22472 /* nCEF but for MVE predicated instructions. */
22473 #define mnCEF(mnem, op, nops, ops, enc) \
22474 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22476 /* nCE but for MVE predicated instructions. */
22477 #define mnCE(mnem, op, nops, ops, enc) \
22478 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22480 /* NUF but for potentially MVE predicated instructions. */
22481 #define MNUF(mnem, op, nops, ops, enc) \
22482 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22483 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22485 /* nUF but for potentially MVE predicated instructions. */
22486 #define mnUF(mnem, op, nops, ops, enc) \
22487 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22488 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22490 /* ToC but for potentially MVE predicated instructions. */
22491 #define mToC(mnem, top, nops, ops, te) \
22492 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22495 /* NCE but for MVE predicated instructions. */
22496 #define MNCE(mnem, op, nops, ops, enc) \
22497 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22499 /* NCEF but for MVE predicated instructions. */
22500 #define MNCEF(mnem, op, nops, ops, enc) \
22501 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22504 static const struct asm_opcode insns[] =
22506 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22507 #define THUMB_VARIANT & arm_ext_v4t
22508 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
22509 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
22510 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
22511 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
22512 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
22513 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
22514 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
22515 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
22516 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
22517 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
22518 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
22519 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
22520 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
22521 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
22522 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
22523 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
22525 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22526 for setting PSR flag bits. They are obsolete in V6 and do not
22527 have Thumb equivalents. */
22528 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
22529 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
22530 CL("tstp", 110f000, 2, (RR, SH), cmp),
22531 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
22532 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
22533 CL("cmpp", 150f000, 2, (RR, SH), cmp),
22534 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
22535 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
22536 CL("cmnp", 170f000, 2, (RR, SH), cmp),
22538 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
22539 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
22540 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
22541 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
22543 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
22544 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
22545 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
22547 OP_ADDRGLDR),ldst, t_ldst),
22548 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
22550 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22551 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22552 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22553 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22554 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22555 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22557 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
22558 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
22561 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
22562 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
22563 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
22564 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
22566 /* Thumb-compatibility pseudo ops. */
22567 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
22568 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
22569 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
22570 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
22571 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
22572 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
22573 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
22574 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
22575 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
22576 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
22577 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
22578 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
22580 /* These may simplify to neg. */
22581 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
22582 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
22584 #undef THUMB_VARIANT
22585 #define THUMB_VARIANT & arm_ext_os
22587 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
22588 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
22590 #undef THUMB_VARIANT
22591 #define THUMB_VARIANT & arm_ext_v6
22593 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
22595 /* V1 instructions with no Thumb analogue prior to V6T2. */
22596 #undef THUMB_VARIANT
22597 #define THUMB_VARIANT & arm_ext_v6t2
22599 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
22600 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
22601 CL("teqp", 130f000, 2, (RR, SH), cmp),
22603 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22604 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22605 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
22606 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
22608 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22609 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22611 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22612 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
22614 /* V1 instructions with no Thumb analogue at all. */
22615 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
22616 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
22618 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
22619 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
22620 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
22621 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
22622 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
22623 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
22624 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
22625 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
22628 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22629 #undef THUMB_VARIANT
22630 #define THUMB_VARIANT & arm_ext_v4t
22632 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
22633 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
22635 #undef THUMB_VARIANT
22636 #define THUMB_VARIANT & arm_ext_v6t2
22638 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
22639 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
22641 /* Generic coprocessor instructions. */
22642 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
22643 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22644 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22645 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22646 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22647 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22648 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
22651 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22653 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
22654 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
22657 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22658 #undef THUMB_VARIANT
22659 #define THUMB_VARIANT & arm_ext_msr
22661 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
22662 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
22665 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22666 #undef THUMB_VARIANT
22667 #define THUMB_VARIANT & arm_ext_v6t2
22669 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22670 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22671 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22672 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22673 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22674 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22675 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
22676 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
22679 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22680 #undef THUMB_VARIANT
22681 #define THUMB_VARIANT & arm_ext_v4t
22683 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22684 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22685 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22686 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22687 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22688 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
22691 #define ARM_VARIANT & arm_ext_v4t_5
22693 /* ARM Architecture 4T. */
22694 /* Note: bx (and blx) are required on V5, even if the processor does
22695 not support Thumb. */
22696 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
22699 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22700 #undef THUMB_VARIANT
22701 #define THUMB_VARIANT & arm_ext_v5t
22703 /* Note: blx has 2 variants; the .value coded here is for
22704 BLX(2). Only this variant has conditional execution. */
22705 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
22706 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
22708 #undef THUMB_VARIANT
22709 #define THUMB_VARIANT & arm_ext_v6t2
22711 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
22712 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22713 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22714 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22715 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
22716 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
22717 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22718 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
22721 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22722 #undef THUMB_VARIANT
22723 #define THUMB_VARIANT & arm_ext_v5exp
22725 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22726 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22727 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22728 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22730 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22731 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
22733 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22734 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22735 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22736 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
22738 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22739 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22740 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22741 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22743 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22744 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22746 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22747 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22748 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22749 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
22752 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22753 #undef THUMB_VARIANT
22754 #define THUMB_VARIANT & arm_ext_v6t2
22756 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
22757 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
22759 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
22760 ADDRGLDRS), ldrd, t_ldstd),
22762 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22763 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22766 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22768 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
22771 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22772 #undef THUMB_VARIANT
22773 #define THUMB_VARIANT & arm_ext_v6
22775 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
22776 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
22777 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22778 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22779 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
22780 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22781 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22782 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22783 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22784 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
22786 #undef THUMB_VARIANT
22787 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22789 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
22790 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
22792 #undef THUMB_VARIANT
22793 #define THUMB_VARIANT & arm_ext_v6t2
22795 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22796 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
22798 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
22799 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
22801 /* ARM V6 not included in V7M. */
22802 #undef THUMB_VARIANT
22803 #define THUMB_VARIANT & arm_ext_v6_notm
22804 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22805 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22806 UF(rfeib, 9900a00, 1, (RRw), rfe),
22807 UF(rfeda, 8100a00, 1, (RRw), rfe),
22808 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
22809 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
22810 UF(rfefa, 8100a00, 1, (RRw), rfe),
22811 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
22812 UF(rfeed, 9900a00, 1, (RRw), rfe),
22813 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22814 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22815 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
22816 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
22817 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
22818 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
22819 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
22820 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
22821 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
22822 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
22824 /* ARM V6 not included in V7M (eg. integer SIMD). */
22825 #undef THUMB_VARIANT
22826 #define THUMB_VARIANT & arm_ext_v6_dsp
22827 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
22828 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
22829 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22830 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22831 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22832 /* Old name for QASX. */
22833 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22834 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22835 /* Old name for QSAX. */
22836 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22837 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22838 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22839 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22840 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22841 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22842 /* Old name for SASX. */
22843 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22844 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22845 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22846 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22847 /* Old name for SHASX. */
22848 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22849 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22850 /* Old name for SHSAX. */
22851 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22852 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22853 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22854 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22855 /* Old name for SSAX. */
22856 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22857 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22858 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22859 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22860 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22861 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22862 /* Old name for UASX. */
22863 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22864 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22865 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22866 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22867 /* Old name for UHASX. */
22868 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22869 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22870 /* Old name for UHSAX. */
22871 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22872 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22873 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22874 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22875 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22876 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22877 /* Old name for UQASX. */
22878 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22879 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22880 /* Old name for UQSAX. */
22881 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22882 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22883 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22884 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22885 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22886 /* Old name for USAX. */
22887 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22888 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22889 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22890 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22891 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22892 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22893 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22894 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22895 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
22896 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
22897 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
22898 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22899 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22900 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22901 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22902 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22903 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22904 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22905 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
22906 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22907 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22908 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22909 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22910 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22911 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22912 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22913 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22914 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22915 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22916 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
22917 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
22918 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
22919 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
22920 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
22923 #define ARM_VARIANT & arm_ext_v6k_v6t2
22924 #undef THUMB_VARIANT
22925 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22927 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
22928 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
22929 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
22930 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
22932 #undef THUMB_VARIANT
22933 #define THUMB_VARIANT & arm_ext_v6_notm
22934 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
22936 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
22937 RRnpcb), strexd, t_strexd),
22939 #undef THUMB_VARIANT
22940 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22941 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
22943 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
22945 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
22947 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
22949 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
22952 #define ARM_VARIANT & arm_ext_sec
22953 #undef THUMB_VARIANT
22954 #define THUMB_VARIANT & arm_ext_sec
22956 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
22959 #define ARM_VARIANT & arm_ext_virt
22960 #undef THUMB_VARIANT
22961 #define THUMB_VARIANT & arm_ext_virt
22963 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
22964 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
22967 #define ARM_VARIANT & arm_ext_pan
22968 #undef THUMB_VARIANT
22969 #define THUMB_VARIANT & arm_ext_pan
22971 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
22974 #define ARM_VARIANT & arm_ext_v6t2
22975 #undef THUMB_VARIANT
22976 #define THUMB_VARIANT & arm_ext_v6t2
22978 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
22979 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
22980 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
22981 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
22983 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
22984 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
22986 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
22987 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
22988 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
22989 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
22992 #define ARM_VARIANT & arm_ext_v3
22993 #undef THUMB_VARIANT
22994 #define THUMB_VARIANT & arm_ext_v6t2
22996 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
22997 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
22998 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
23001 #define ARM_VARIANT & arm_ext_v6t2
23002 #undef THUMB_VARIANT
23003 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23004 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
23005 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
23007 /* Thumb-only instructions. */
23009 #define ARM_VARIANT NULL
23010 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
23011 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
23013 /* ARM does not really have an IT instruction, so always allow it.
23014 The opcode is copied from Thumb in order to allow warnings in
23015 -mimplicit-it=[never | arm] modes. */
23017 #define ARM_VARIANT & arm_ext_v1
23018 #undef THUMB_VARIANT
23019 #define THUMB_VARIANT & arm_ext_v6t2
23021 TUE("it", bf08, bf08, 1, (COND), it, t_it),
23022 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
23023 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
23024 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
23025 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
23026 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
23027 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
23028 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
23029 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
23030 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
23031 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
23032 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
23033 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
23034 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
23035 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
23036 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23037 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
23038 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
23040 /* Thumb2 only instructions. */
23042 #define ARM_VARIANT NULL
23044 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23045 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23046 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
23047 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
23048 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
23049 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
23051 /* Hardware division instructions. */
23053 #define ARM_VARIANT & arm_ext_adiv
23054 #undef THUMB_VARIANT
23055 #define THUMB_VARIANT & arm_ext_div
23057 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
23058 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
23060 /* ARM V6M/V7 instructions. */
23062 #define ARM_VARIANT & arm_ext_barrier
23063 #undef THUMB_VARIANT
23064 #define THUMB_VARIANT & arm_ext_barrier
23066 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
23067 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
23068 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
23070 /* ARM V7 instructions. */
23072 #define ARM_VARIANT & arm_ext_v7
23073 #undef THUMB_VARIANT
23074 #define THUMB_VARIANT & arm_ext_v7
23076 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
23077 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
23080 #define ARM_VARIANT & arm_ext_mp
23081 #undef THUMB_VARIANT
23082 #define THUMB_VARIANT & arm_ext_mp
23084 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
23086 /* AArchv8 instructions. */
23088 #define ARM_VARIANT & arm_ext_v8
23090 /* Instructions shared between armv8-a and armv8-m. */
23091 #undef THUMB_VARIANT
23092 #define THUMB_VARIANT & arm_ext_atomics
23094 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23095 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23096 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23097 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23098 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23099 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23100 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23101 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
23102 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23103 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
23105 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
23107 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
23109 #undef THUMB_VARIANT
23110 #define THUMB_VARIANT & arm_ext_v8
23112 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
23113 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
23115 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
23118 /* Defined in V8 but is in undefined encoding space for earlier
23119 architectures. However earlier architectures are required to treat
23120 this instuction as a semihosting trap as well. Hence while not explicitly
23121 defined as such, it is in fact correct to define the instruction for all
23123 #undef THUMB_VARIANT
23124 #define THUMB_VARIANT & arm_ext_v1
23126 #define ARM_VARIANT & arm_ext_v1
23127 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
23129 /* ARMv8 T32 only. */
23131 #define ARM_VARIANT NULL
23132 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
23133 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
23134 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
23136 /* FP for ARMv8. */
23138 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23139 #undef THUMB_VARIANT
23140 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23142 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
23143 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
23144 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
23145 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
23146 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
23147 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
23148 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
23149 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
23150 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
23151 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
23152 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
23154 /* Crypto v1 extensions. */
23156 #define ARM_VARIANT & fpu_crypto_ext_armv8
23157 #undef THUMB_VARIANT
23158 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23160 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
23161 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
23162 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
23163 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
23164 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
23165 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
23166 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
23167 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
23168 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
23169 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
23170 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
23171 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
23172 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
23173 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
23176 #define ARM_VARIANT & crc_ext_armv8
23177 #undef THUMB_VARIANT
23178 #define THUMB_VARIANT & crc_ext_armv8
23179 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
23180 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
23181 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
23182 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
23183 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
23184 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
23186 /* ARMv8.2 RAS extension. */
23188 #define ARM_VARIANT & arm_ext_ras
23189 #undef THUMB_VARIANT
23190 #define THUMB_VARIANT & arm_ext_ras
23191 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
23194 #define ARM_VARIANT & arm_ext_v8_3
23195 #undef THUMB_VARIANT
23196 #define THUMB_VARIANT & arm_ext_v8_3
23197 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
23200 #define ARM_VARIANT & fpu_neon_ext_dotprod
23201 #undef THUMB_VARIANT
23202 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23203 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
23204 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
23207 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23208 #undef THUMB_VARIANT
23209 #define THUMB_VARIANT NULL
23211 cCE("wfs", e200110, 1, (RR), rd),
23212 cCE("rfs", e300110, 1, (RR), rd),
23213 cCE("wfc", e400110, 1, (RR), rd),
23214 cCE("rfc", e500110, 1, (RR), rd),
23216 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
23217 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
23218 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
23219 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
23221 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
23222 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
23223 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
23224 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
23226 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
23227 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
23228 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
23229 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
23230 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
23231 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
23232 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
23233 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
23234 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
23235 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
23236 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
23237 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
23239 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
23240 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
23241 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
23242 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
23243 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
23244 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
23245 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
23246 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
23247 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
23248 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
23249 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
23250 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
23252 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
23253 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
23254 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
23255 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
23256 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
23257 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
23258 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
23259 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
23260 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
23261 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
23262 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
23263 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
23265 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
23266 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
23267 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
23268 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
23269 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
23270 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
23271 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
23272 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
23273 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
23274 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
23275 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
23276 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
23278 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
23279 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
23280 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
23281 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
23282 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
23283 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
23284 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
23285 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
23286 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
23287 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
23288 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
23289 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
23291 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
23292 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
23293 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
23294 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
23295 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
23296 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
23297 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
23298 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
23299 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
23300 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
23301 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
23302 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
23304 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
23305 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
23306 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
23307 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
23308 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
23309 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
23310 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
23311 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
23312 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
23313 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
23314 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
23315 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
23317 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
23318 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
23319 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
23320 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
23321 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
23322 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
23323 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
23324 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
23325 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
23326 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
23327 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
23328 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
23330 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
23331 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
23332 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
23333 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
23334 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
23335 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
23336 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
23337 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
23338 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
23339 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
23340 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
23341 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
23343 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
23344 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
23345 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
23346 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
23347 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
23348 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
23349 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
23350 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
23351 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
23352 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
23353 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
23354 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
23356 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
23357 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
23358 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
23359 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
23360 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
23361 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
23362 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
23363 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
23364 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
23365 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
23366 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
23367 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
23369 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
23370 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
23371 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
23372 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
23373 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
23374 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
23375 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
23376 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
23377 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
23378 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
23379 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
23380 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
23382 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
23383 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
23384 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
23385 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
23386 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
23387 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
23388 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
23389 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
23390 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
23391 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
23392 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
23393 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
23395 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
23396 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
23397 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
23398 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
23399 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
23400 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
23401 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
23402 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
23403 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
23404 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
23405 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
23406 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
23408 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
23409 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
23410 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
23411 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
23412 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
23413 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
23414 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
23415 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
23416 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
23417 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
23418 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
23419 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
23421 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
23422 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
23423 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
23424 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
23425 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
23426 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
23427 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
23428 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
23429 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
23430 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
23431 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
23432 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
23434 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
23435 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
23436 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
23437 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
23438 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
23439 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23440 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23441 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23442 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
23443 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
23444 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
23445 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
23447 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
23448 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
23449 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
23450 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
23451 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
23452 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23453 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23454 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23455 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
23456 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
23457 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
23458 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
23460 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
23461 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
23462 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
23463 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
23464 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
23465 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23466 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23467 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23468 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
23469 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
23470 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
23471 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
23473 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
23474 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
23475 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
23476 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
23477 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
23478 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23479 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23480 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23481 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
23482 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
23483 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
23484 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
23486 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
23487 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
23488 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
23489 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
23490 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
23491 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23492 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23493 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23494 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
23495 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
23496 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
23497 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
23499 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
23500 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
23501 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
23502 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
23503 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
23504 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23505 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23506 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23507 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
23508 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
23509 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
23510 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
23512 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
23513 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
23514 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
23515 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
23516 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
23517 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23518 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23519 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23520 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
23521 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
23522 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
23523 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
23525 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
23526 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
23527 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
23528 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
23529 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
23530 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23531 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23532 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23533 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
23534 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
23535 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
23536 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
23538 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
23539 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
23540 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
23541 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
23542 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
23543 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23544 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23545 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23546 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
23547 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
23548 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
23549 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
23551 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
23552 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
23553 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
23554 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
23555 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
23556 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23557 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23558 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23559 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
23560 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
23561 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
23562 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
23564 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23565 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23566 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23567 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23568 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23569 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23570 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23571 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23572 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23573 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23574 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23575 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23577 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23578 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23579 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23580 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23581 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23582 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23583 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23584 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23585 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23586 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23587 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23588 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23590 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
23591 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
23592 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
23593 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
23594 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
23595 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
23596 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
23597 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
23598 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
23599 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
23600 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
23601 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
23603 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
23604 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
23605 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
23606 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
23608 cCL("flts", e000110, 2, (RF, RR), rn_rd),
23609 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
23610 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
23611 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
23612 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
23613 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
23614 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
23615 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
23616 cCL("flte", e080110, 2, (RF, RR), rn_rd),
23617 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
23618 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
23619 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
23621 /* The implementation of the FIX instruction is broken on some
23622 assemblers, in that it accepts a precision specifier as well as a
23623 rounding specifier, despite the fact that this is meaningless.
23624 To be more compatible, we accept it as well, though of course it
23625 does not set any bits. */
23626 cCE("fix", e100110, 2, (RR, RF), rd_rm),
23627 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
23628 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
23629 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
23630 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
23631 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
23632 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
23633 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
23634 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
23635 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
23636 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
23637 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
23638 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
23640 /* Instructions that were new with the real FPA, call them V2. */
23642 #define ARM_VARIANT & fpu_fpa_ext_v2
23644 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23645 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23646 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23647 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23648 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23649 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
23652 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23654 /* Moves and type conversions. */
23655 cCE("fmstat", ef1fa10, 0, (), noargs),
23656 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
23657 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
23658 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
23659 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
23660 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
23661 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
23662 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
23663 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
23664 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
23665 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
23667 /* Memory operations. */
23668 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
23669 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
23670 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23671 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23672 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23673 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23674 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23675 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23676 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23677 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23678 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23679 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
23680 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23681 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
23682 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23683 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
23684 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23685 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
23687 /* Monadic operations. */
23688 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
23689 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
23690 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
23692 /* Dyadic operations. */
23693 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23694 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23695 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23696 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23697 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23698 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23699 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23700 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23701 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
23704 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
23705 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
23706 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
23707 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
23709 /* Double precision load/store are still present on single precision
23710 implementations. */
23711 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
23712 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
23713 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23714 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23715 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23716 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23717 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23718 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
23719 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23720 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
23723 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23725 /* Moves and type conversions. */
23726 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
23727 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23728 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
23729 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
23730 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
23731 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
23732 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
23733 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
23734 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
23735 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23736 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
23737 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
23739 /* Monadic operations. */
23740 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23741 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
23742 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23744 /* Dyadic operations. */
23745 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23746 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23747 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23748 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23749 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23750 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23751 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23752 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23753 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
23756 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
23757 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
23758 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
23759 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
23761 /* Instructions which may belong to either the Neon or VFP instruction sets.
23762 Individual encoder functions perform additional architecture checks. */
23764 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23765 #undef THUMB_VARIANT
23766 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23768 /* These mnemonics are unique to VFP. */
23769 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
23770 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
23771 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23772 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23773 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
23774 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
23775 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
23776 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
23778 /* Mnemonics shared by Neon and VFP. */
23779 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
23780 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
23781 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
23783 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23784 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23785 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23786 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23787 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23788 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
23790 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
23791 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
23792 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
23793 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
23796 /* NOTE: All VMOV encoding is special-cased! */
23797 NCE(vmovq, 0, 1, (VMOV), neon_mov),
23799 #undef THUMB_VARIANT
23800 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23801 by different feature bits. Since we are setting the Thumb guard, we can
23802 require Thumb-1 which makes it a nop guard and set the right feature bit in
23803 do_vldr_vstr (). */
23804 #define THUMB_VARIANT & arm_ext_v4t
23805 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
23806 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
23809 #define ARM_VARIANT & arm_ext_fp16
23810 #undef THUMB_VARIANT
23811 #define THUMB_VARIANT & arm_ext_fp16
23812 /* New instructions added from v8.2, allowing the extraction and insertion of
23813 the upper 16 bits of a 32-bit vector register. */
23814 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
23815 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
23817 /* New backported fma/fms instructions optional in v8.2. */
23818 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
23819 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
23821 #undef THUMB_VARIANT
23822 #define THUMB_VARIANT & fpu_neon_ext_v1
23824 #define ARM_VARIANT & fpu_neon_ext_v1
23826 /* Data processing with three registers of the same length. */
23827 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23828 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
23829 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
23830 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23831 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23832 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
23833 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23834 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
23835 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
23836 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
23837 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
23838 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
23839 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
23840 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
23841 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
23842 /* If not immediate, fall back to neon_dyadic_i64_su.
23843 shl_imm should accept I8 I16 I32 I64,
23844 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23845 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
23846 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
23847 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
23848 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
23849 /* Logic ops, types optional & ignored. */
23850 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23851 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23852 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23853 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
23854 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
23855 /* Bitfield ops, untyped. */
23856 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23857 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23858 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23859 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23860 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
23861 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
23862 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23863 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23864 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23865 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
23866 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23867 back to neon_dyadic_if_su. */
23868 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
23869 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
23870 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
23871 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
23872 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
23873 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
23874 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
23875 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
23876 /* Comparison. Type I8 I16 I32 F32. */
23877 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
23878 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
23879 /* As above, D registers only. */
23880 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
23881 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
23882 /* Int and float variants, signedness unimportant. */
23883 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
23884 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
23885 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
23886 /* Add/sub take types I8 I16 I32 I64 F32. */
23887 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
23888 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
23889 /* vtst takes sizes 8, 16, 32. */
23890 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
23891 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
23892 /* VMUL takes I8 I16 I32 F32 P8. */
23893 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
23894 /* VQD{R}MULH takes S16 S32. */
23895 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
23896 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
23897 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
23898 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
23899 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
23900 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
23901 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
23902 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
23903 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
23904 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
23905 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
23906 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
23907 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
23908 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
23909 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
23910 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
23911 /* ARM v8.1 extension. */
23912 nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
23913 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
23914 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
23915 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
23917 /* Two address, int/float. Types S8 S16 S32 F32. */
23918 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
23919 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
23921 /* Data processing with two registers and a shift amount. */
23922 /* Right shifts, and variants with rounding.
23923 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23924 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
23925 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
23926 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
23927 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
23928 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
23929 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
23930 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
23931 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
23932 /* Shift and insert. Sizes accepted 8 16 32 64. */
23933 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
23934 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
23935 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
23936 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
23937 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23938 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
23939 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
23940 /* Right shift immediate, saturating & narrowing, with rounding variants.
23941 Types accepted S16 S32 S64 U16 U32 U64. */
23942 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
23943 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
23944 /* As above, unsigned. Types accepted S16 S32 S64. */
23945 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
23946 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
23947 /* Right shift narrowing. Types accepted I16 I32 I64. */
23948 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
23949 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
23950 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23951 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
23952 /* CVT with optional immediate for fixed-point variant. */
23953 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
23955 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
23956 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
23958 /* Data processing, three registers of different lengths. */
23959 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23960 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
23961 /* If not scalar, fall back to neon_dyadic_long.
23962 Vector types as above, scalar types S16 S32 U16 U32. */
23963 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
23964 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
23965 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23966 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
23967 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
23968 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23969 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
23970 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
23971 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
23972 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
23973 /* Saturating doubling multiplies. Types S16 S32. */
23974 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
23975 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
23976 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
23977 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23978 S16 S32 U16 U32. */
23979 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
23981 /* Extract. Size 8. */
23982 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
23983 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
23985 /* Two registers, miscellaneous. */
23986 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23987 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
23988 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
23989 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
23990 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
23991 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
23992 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
23993 /* Vector replicate. Sizes 8 16 32. */
23994 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
23995 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23996 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
23997 /* VMOVN. Types I16 I32 I64. */
23998 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
23999 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24000 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
24001 /* VQMOVUN. Types S16 S32 S64. */
24002 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
24003 /* VZIP / VUZP. Sizes 8 16 32. */
24004 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
24005 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
24006 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
24007 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
24008 /* VQABS / VQNEG. Types S8 S16 S32. */
24009 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
24010 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
24011 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
24012 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
24013 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24014 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
24015 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
24016 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
24017 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
24018 /* Reciprocal estimates. Types U32 F16 F32. */
24019 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
24020 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
24021 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
24022 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
24023 /* VCLS. Types S8 S16 S32. */
24024 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
24025 /* VCLZ. Types I8 I16 I32. */
24026 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
24027 /* VCNT. Size 8. */
24028 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
24029 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
24030 /* Two address, untyped. */
24031 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
24032 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
24033 /* VTRN. Sizes 8 16 32. */
24034 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
24035 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
24037 /* Table lookup. Size 8. */
24038 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24039 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24041 #undef THUMB_VARIANT
24042 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24044 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24046 /* Neon element/structure load/store. */
24047 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24048 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24049 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24050 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24051 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24052 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24053 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24054 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24056 #undef THUMB_VARIANT
24057 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24059 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24060 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
24061 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24062 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24063 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24064 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24065 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24066 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24067 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24068 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24070 #undef THUMB_VARIANT
24071 #define THUMB_VARIANT & fpu_vfp_ext_v3
24073 #define ARM_VARIANT & fpu_vfp_ext_v3
24075 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
24076 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24077 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24078 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24079 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24080 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24081 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24082 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24083 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24086 #define ARM_VARIANT & fpu_vfp_ext_fma
24087 #undef THUMB_VARIANT
24088 #define THUMB_VARIANT & fpu_vfp_ext_fma
24089 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24090 VFP FMA variant; NEON and VFP FMA always includes the NEON
24091 FMA instructions. */
24092 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
24093 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
24095 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24096 the v form should always be used. */
24097 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24098 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24099 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24100 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24101 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24102 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24104 #undef THUMB_VARIANT
24106 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24108 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24109 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24110 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24111 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24112 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24113 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24114 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
24115 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
24118 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24120 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
24121 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
24122 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
24123 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
24124 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
24125 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
24126 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
24127 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
24128 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
24129 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24130 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24131 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24132 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24133 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24134 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24135 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24136 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24137 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24138 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
24139 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
24140 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24141 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24142 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24143 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24144 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24145 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24146 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
24147 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
24148 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
24149 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
24150 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
24151 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
24152 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
24153 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
24154 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
24155 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
24156 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
24157 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24158 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24159 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24160 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24161 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24162 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24163 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24164 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24165 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24166 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
24167 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24168 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24169 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24170 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24171 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24172 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24173 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24174 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24175 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24176 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24177 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24178 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24179 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24180 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24181 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24182 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24183 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24184 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24185 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24186 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24187 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24188 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24189 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24190 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24191 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24192 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24193 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24194 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24195 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24196 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24197 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24198 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24199 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24200 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24201 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24202 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24203 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24204 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24205 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24206 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24207 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24208 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
24209 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24210 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24211 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24212 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24213 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24214 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24215 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24216 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24217 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24218 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24219 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24220 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24221 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24222 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24223 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24224 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24225 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24226 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24227 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24228 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24229 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24230 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
24231 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24232 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24233 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24234 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24235 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24236 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24237 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24238 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24239 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24240 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24241 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24242 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24243 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24244 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24245 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24246 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24247 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24248 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24249 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24250 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24251 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24252 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24253 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24254 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24255 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24256 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24257 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24258 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24259 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24260 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24261 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24262 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
24263 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
24264 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
24265 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
24266 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
24267 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
24268 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24269 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24270 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24271 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
24272 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
24273 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
24274 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
24275 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
24276 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
24277 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24278 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24279 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24280 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24281 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
24284 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24286 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
24287 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
24288 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
24289 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
24290 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
24291 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
24292 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24293 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24294 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24295 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24296 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24297 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24298 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24299 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24300 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24301 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24302 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24303 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24304 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24305 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24306 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
24307 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24308 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24309 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24310 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24311 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24312 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24313 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24314 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24315 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24316 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24317 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24318 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24319 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24320 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24321 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24322 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24323 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24324 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24325 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24326 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24327 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24328 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24329 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24330 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24331 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24332 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24333 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24334 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24335 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24336 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24337 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24338 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24339 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24340 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24341 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24342 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24345 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24347 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24348 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24349 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24350 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24351 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24352 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24353 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24354 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24355 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
24356 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
24357 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
24358 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
24359 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
24360 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
24361 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
24362 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
24363 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
24364 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
24365 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
24366 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
24367 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
24368 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
24369 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
24370 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
24371 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
24372 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
24373 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
24374 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
24375 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
24376 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
24377 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
24378 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
24379 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
24380 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
24381 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
24382 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
24383 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
24384 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
24385 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
24386 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
24387 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
24388 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
24389 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
24390 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
24391 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
24392 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
24393 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
24394 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
24395 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
24396 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
24397 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
24398 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
24399 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
24400 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
24401 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
24402 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
24403 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
24404 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
24405 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
24406 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
24407 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
24408 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
24409 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
24410 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
24411 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24412 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24413 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24414 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24415 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24416 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24417 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24418 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24419 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24420 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24421 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24422 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24424 /* ARMv8.5-A instructions. */
24426 #define ARM_VARIANT & arm_ext_sb
24427 #undef THUMB_VARIANT
24428 #define THUMB_VARIANT & arm_ext_sb
24429 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
24432 #define ARM_VARIANT & arm_ext_predres
24433 #undef THUMB_VARIANT
24434 #define THUMB_VARIANT & arm_ext_predres
24435 CE("cfprctx", e070f93, 1, (RRnpc), rd),
24436 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
24437 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
24439 /* ARMv8-M instructions. */
24441 #define ARM_VARIANT NULL
24442 #undef THUMB_VARIANT
24443 #define THUMB_VARIANT & arm_ext_v8m
24444 ToU("sg", e97fe97f, 0, (), noargs),
24445 ToC("blxns", 4784, 1, (RRnpc), t_blx),
24446 ToC("bxns", 4704, 1, (RRnpc), t_bx),
24447 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
24448 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
24449 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
24450 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
24452 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24453 instructions behave as nop if no VFP is present. */
24454 #undef THUMB_VARIANT
24455 #define THUMB_VARIANT & arm_ext_v8m_main
24456 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
24457 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
24459 /* Armv8.1-M Mainline instructions. */
24460 #undef THUMB_VARIANT
24461 #define THUMB_VARIANT & arm_ext_v8_1m_main
24462 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
24463 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
24464 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
24465 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
24466 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
24468 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
24469 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
24470 toU("le", _le, 2, (oLR, EXP), t_loloop),
24472 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
24473 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
24475 #undef THUMB_VARIANT
24476 #define THUMB_VARIANT & mve_ext
24478 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24479 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24480 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24481 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24482 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24483 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24484 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24485 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24486 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24487 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24488 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24489 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24490 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24491 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24492 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
24494 ToC("vpst", fe710f4d, 0, (), mve_vpt),
24495 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
24496 ToC("vpste", fe718f4d, 0, (), mve_vpt),
24497 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
24498 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
24499 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
24500 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
24501 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
24502 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
24503 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
24504 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
24505 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
24506 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
24507 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
24508 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
24510 /* MVE and MVE FP only. */
24511 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
24512 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
24513 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
24514 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
24515 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
24516 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
24517 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
24518 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24519 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24520 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
24521 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
24522 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24523 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24524 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
24525 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
24526 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
24527 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
24529 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24530 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24531 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24532 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24533 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24534 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24535 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24536 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
24537 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24538 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24539 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24540 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
24541 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24542 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24543 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24544 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24545 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24546 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24547 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24548 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
24550 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
24551 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
24552 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
24553 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
24554 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
24555 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
24556 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
24557 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
24558 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
24559 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
24560 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
24561 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
24562 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
24563 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
24564 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
24565 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
24566 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
24568 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24569 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24570 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24571 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24572 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24573 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24574 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24575 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24576 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24577 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
24578 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24579 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24580 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24581 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24582 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24583 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24584 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24585 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24586 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24587 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
24589 #undef THUMB_VARIANT
24590 #define THUMB_VARIANT & mve_fp_ext
24591 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
24592 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
24593 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
24594 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
24595 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
24596 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
24597 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
24598 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
24601 #define ARM_VARIANT & fpu_vfp_ext_v1
24602 #undef THUMB_VARIANT
24603 #define THUMB_VARIANT & arm_ext_v6t2
24605 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24608 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24610 MNCE(vmov, 0, 1, (VMOV), neon_mov),
24611 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
24612 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
24613 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
24615 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
24616 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
24617 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
24619 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
24620 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
24622 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
24623 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
24625 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
24626 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
24629 #define ARM_VARIANT & fpu_vfp_ext_v2
24631 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
24632 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
24633 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
24634 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
24637 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24638 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
24639 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
24640 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
24641 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
24642 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
24643 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
24646 #define ARM_VARIANT & fpu_neon_ext_v1
24647 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24648 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
24649 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
24650 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
24651 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24652 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24653 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24654 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
24655 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
24656 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
24657 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
24658 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
24659 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
24660 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
24661 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
24662 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24663 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
24666 #define ARM_VARIANT & arm_ext_v8_3
24667 #undef THUMB_VARIANT
24668 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24669 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
24670 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
24673 #undef THUMB_VARIANT
24705 /* MD interface: bits in the object file. */
24707 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24708 for use in the a.out file, and stores them in the array pointed to by buf.
24709 This knows about the endian-ness of the target machine and does
24710 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24711 2 (short) and 4 (long) Floating numbers are put out as a series of
24712 LITTLENUMS (shorts, here at least). */
24715 md_number_to_chars (char * buf, valueT val, int n)
24717 if (target_big_endian)
24718 number_to_chars_bigendian (buf, val, n);
24720 number_to_chars_littleendian (buf, val, n);
24724 md_chars_to_number (char * buf, int n)
24727 unsigned char * where = (unsigned char *) buf;
24729 if (target_big_endian)
24734 result |= (*where++ & 255);
24742 result |= (where[n] & 255);
24749 /* MD interface: Sections. */
24751 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24752 that an rs_machine_dependent frag may reach. */
24755 arm_frag_max_var (fragS *fragp)
24757 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24758 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24760 Note that we generate relaxable instructions even for cases that don't
24761 really need it, like an immediate that's a trivial constant. So we're
24762 overestimating the instruction size for some of those cases. Rather
24763 than putting more intelligence here, it would probably be better to
24764 avoid generating a relaxation frag in the first place when it can be
24765 determined up front that a short instruction will suffice. */
24767 gas_assert (fragp->fr_type == rs_machine_dependent);
24771 /* Estimate the size of a frag before relaxing. Assume everything fits in
24775 md_estimate_size_before_relax (fragS * fragp,
24776 segT segtype ATTRIBUTE_UNUSED)
24782 /* Convert a machine dependent frag. */
24785 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
24787 unsigned long insn;
24788 unsigned long old_op;
24796 buf = fragp->fr_literal + fragp->fr_fix;
24798 old_op = bfd_get_16(abfd, buf);
24799 if (fragp->fr_symbol)
24801 exp.X_op = O_symbol;
24802 exp.X_add_symbol = fragp->fr_symbol;
24806 exp.X_op = O_constant;
24808 exp.X_add_number = fragp->fr_offset;
24809 opcode = fragp->fr_subtype;
24812 case T_MNEM_ldr_pc:
24813 case T_MNEM_ldr_pc2:
24814 case T_MNEM_ldr_sp:
24815 case T_MNEM_str_sp:
24822 if (fragp->fr_var == 4)
24824 insn = THUMB_OP32 (opcode);
24825 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
24827 insn |= (old_op & 0x700) << 4;
24831 insn |= (old_op & 7) << 12;
24832 insn |= (old_op & 0x38) << 13;
24834 insn |= 0x00000c00;
24835 put_thumb32_insn (buf, insn);
24836 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
24840 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
24842 pc_rel = (opcode == T_MNEM_ldr_pc2);
24845 if (fragp->fr_var == 4)
24847 insn = THUMB_OP32 (opcode);
24848 insn |= (old_op & 0xf0) << 4;
24849 put_thumb32_insn (buf, insn);
24850 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
24854 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
24855 exp.X_add_number -= 4;
24863 if (fragp->fr_var == 4)
24865 int r0off = (opcode == T_MNEM_mov
24866 || opcode == T_MNEM_movs) ? 0 : 8;
24867 insn = THUMB_OP32 (opcode);
24868 insn = (insn & 0xe1ffffff) | 0x10000000;
24869 insn |= (old_op & 0x700) << r0off;
24870 put_thumb32_insn (buf, insn);
24871 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
24875 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
24880 if (fragp->fr_var == 4)
24882 insn = THUMB_OP32(opcode);
24883 put_thumb32_insn (buf, insn);
24884 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
24887 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
24891 if (fragp->fr_var == 4)
24893 insn = THUMB_OP32(opcode);
24894 insn |= (old_op & 0xf00) << 14;
24895 put_thumb32_insn (buf, insn);
24896 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
24899 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
24902 case T_MNEM_add_sp:
24903 case T_MNEM_add_pc:
24904 case T_MNEM_inc_sp:
24905 case T_MNEM_dec_sp:
24906 if (fragp->fr_var == 4)
24908 /* ??? Choose between add and addw. */
24909 insn = THUMB_OP32 (opcode);
24910 insn |= (old_op & 0xf0) << 4;
24911 put_thumb32_insn (buf, insn);
24912 if (opcode == T_MNEM_add_pc)
24913 reloc_type = BFD_RELOC_ARM_T32_IMM12;
24915 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
24918 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
24926 if (fragp->fr_var == 4)
24928 insn = THUMB_OP32 (opcode);
24929 insn |= (old_op & 0xf0) << 4;
24930 insn |= (old_op & 0xf) << 16;
24931 put_thumb32_insn (buf, insn);
24932 if (insn & (1 << 20))
24933 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
24935 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
24938 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
24944 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
24945 (enum bfd_reloc_code_real) reloc_type);
24946 fixp->fx_file = fragp->fr_file;
24947 fixp->fx_line = fragp->fr_line;
24948 fragp->fr_fix += fragp->fr_var;
24950 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24951 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
24952 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
24953 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
24956 /* Return the size of a relaxable immediate operand instruction.
24957 SHIFT and SIZE specify the form of the allowable immediate. */
24959 relax_immediate (fragS *fragp, int size, int shift)
24965 /* ??? Should be able to do better than this. */
24966 if (fragp->fr_symbol)
24969 low = (1 << shift) - 1;
24970 mask = (1 << (shift + size)) - (1 << shift);
24971 offset = fragp->fr_offset;
24972 /* Force misaligned offsets to 32-bit variant. */
24975 if (offset & ~mask)
24980 /* Get the address of a symbol during relaxation. */
24982 relaxed_symbol_addr (fragS *fragp, long stretch)
24988 sym = fragp->fr_symbol;
24989 sym_frag = symbol_get_frag (sym);
24990 know (S_GET_SEGMENT (sym) != absolute_section
24991 || sym_frag == &zero_address_frag);
24992 addr = S_GET_VALUE (sym) + fragp->fr_offset;
24994 /* If frag has yet to be reached on this pass, assume it will
24995 move by STRETCH just as we did. If this is not so, it will
24996 be because some frag between grows, and that will force
25000 && sym_frag->relax_marker != fragp->relax_marker)
25004 /* Adjust stretch for any alignment frag. Note that if have
25005 been expanding the earlier code, the symbol may be
25006 defined in what appears to be an earlier frag. FIXME:
25007 This doesn't handle the fr_subtype field, which specifies
25008 a maximum number of bytes to skip when doing an
25010 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
25012 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
25015 stretch = - ((- stretch)
25016 & ~ ((1 << (int) f->fr_offset) - 1));
25018 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
25030 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25033 relax_adr (fragS *fragp, asection *sec, long stretch)
25038 /* Assume worst case for symbols not known to be in the same section. */
25039 if (fragp->fr_symbol == NULL
25040 || !S_IS_DEFINED (fragp->fr_symbol)
25041 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25042 || S_IS_WEAK (fragp->fr_symbol))
25045 val = relaxed_symbol_addr (fragp, stretch);
25046 addr = fragp->fr_address + fragp->fr_fix;
25047 addr = (addr + 4) & ~3;
25048 /* Force misaligned targets to 32-bit variant. */
25052 if (val < 0 || val > 1020)
25057 /* Return the size of a relaxable add/sub immediate instruction. */
25059 relax_addsub (fragS *fragp, asection *sec)
25064 buf = fragp->fr_literal + fragp->fr_fix;
25065 op = bfd_get_16(sec->owner, buf);
25066 if ((op & 0xf) == ((op >> 4) & 0xf))
25067 return relax_immediate (fragp, 8, 0);
25069 return relax_immediate (fragp, 3, 0);
25072 /* Return TRUE iff the definition of symbol S could be pre-empted
25073 (overridden) at link or load time. */
25075 symbol_preemptible (symbolS *s)
25077 /* Weak symbols can always be pre-empted. */
25081 /* Non-global symbols cannot be pre-empted. */
25082 if (! S_IS_EXTERNAL (s))
25086 /* In ELF, a global symbol can be marked protected, or private. In that
25087 case it can't be pre-empted (other definitions in the same link unit
25088 would violate the ODR). */
25089 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
25093 /* Other global symbols might be pre-empted. */
25097 /* Return the size of a relaxable branch instruction. BITS is the
25098 size of the offset field in the narrow instruction. */
25101 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
25107 /* Assume worst case for symbols not known to be in the same section. */
25108 if (!S_IS_DEFINED (fragp->fr_symbol)
25109 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25110 || S_IS_WEAK (fragp->fr_symbol))
25114 /* A branch to a function in ARM state will require interworking. */
25115 if (S_IS_DEFINED (fragp->fr_symbol)
25116 && ARM_IS_FUNC (fragp->fr_symbol))
25120 if (symbol_preemptible (fragp->fr_symbol))
25123 val = relaxed_symbol_addr (fragp, stretch);
25124 addr = fragp->fr_address + fragp->fr_fix + 4;
25127 /* Offset is a signed value *2 */
25129 if (val >= limit || val < -limit)
25135 /* Relax a machine dependent frag. This returns the amount by which
25136 the current size of the frag should change. */
25139 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
25144 oldsize = fragp->fr_var;
25145 switch (fragp->fr_subtype)
25147 case T_MNEM_ldr_pc2:
25148 newsize = relax_adr (fragp, sec, stretch);
25150 case T_MNEM_ldr_pc:
25151 case T_MNEM_ldr_sp:
25152 case T_MNEM_str_sp:
25153 newsize = relax_immediate (fragp, 8, 2);
25157 newsize = relax_immediate (fragp, 5, 2);
25161 newsize = relax_immediate (fragp, 5, 1);
25165 newsize = relax_immediate (fragp, 5, 0);
25168 newsize = relax_adr (fragp, sec, stretch);
25174 newsize = relax_immediate (fragp, 8, 0);
25177 newsize = relax_branch (fragp, sec, 11, stretch);
25180 newsize = relax_branch (fragp, sec, 8, stretch);
25182 case T_MNEM_add_sp:
25183 case T_MNEM_add_pc:
25184 newsize = relax_immediate (fragp, 8, 2);
25186 case T_MNEM_inc_sp:
25187 case T_MNEM_dec_sp:
25188 newsize = relax_immediate (fragp, 7, 2);
25194 newsize = relax_addsub (fragp, sec);
25200 fragp->fr_var = newsize;
25201 /* Freeze wide instructions that are at or before the same location as
25202 in the previous pass. This avoids infinite loops.
25203 Don't freeze them unconditionally because targets may be artificially
25204 misaligned by the expansion of preceding frags. */
25205 if (stretch <= 0 && newsize > 2)
25207 md_convert_frag (sec->owner, sec, fragp);
25211 return newsize - oldsize;
25214 /* Round up a section size to the appropriate boundary. */
25217 md_section_align (segT segment ATTRIBUTE_UNUSED,
25223 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25224 of an rs_align_code fragment. */
25227 arm_handle_align (fragS * fragP)
25229 static unsigned char const arm_noop[2][2][4] =
25232 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25233 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25236 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25237 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25240 static unsigned char const thumb_noop[2][2][2] =
25243 {0xc0, 0x46}, /* LE */
25244 {0x46, 0xc0}, /* BE */
25247 {0x00, 0xbf}, /* LE */
25248 {0xbf, 0x00} /* BE */
25251 static unsigned char const wide_thumb_noop[2][4] =
25252 { /* Wide Thumb-2 */
25253 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25254 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25257 unsigned bytes, fix, noop_size;
25259 const unsigned char * noop;
25260 const unsigned char *narrow_noop = NULL;
25265 if (fragP->fr_type != rs_align_code)
25268 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
25269 p = fragP->fr_literal + fragP->fr_fix;
25272 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
25273 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
25275 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
25277 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
25279 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25280 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
25282 narrow_noop = thumb_noop[1][target_big_endian];
25283 noop = wide_thumb_noop[target_big_endian];
25286 noop = thumb_noop[0][target_big_endian];
25294 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25295 ? selected_cpu : arm_arch_none,
25297 [target_big_endian];
25304 fragP->fr_var = noop_size;
25306 if (bytes & (noop_size - 1))
25308 fix = bytes & (noop_size - 1);
25310 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
25312 memset (p, 0, fix);
25319 if (bytes & noop_size)
25321 /* Insert a narrow noop. */
25322 memcpy (p, narrow_noop, noop_size);
25324 bytes -= noop_size;
25328 /* Use wide noops for the remainder */
25332 while (bytes >= noop_size)
25334 memcpy (p, noop, noop_size);
25336 bytes -= noop_size;
25340 fragP->fr_fix += fix;
25343 /* Called from md_do_align. Used to create an alignment
25344 frag in a code section. */
25347 arm_frag_align_code (int n, int max)
25351 /* We assume that there will never be a requirement
25352 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25353 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
25358 _("alignments greater than %d bytes not supported in .text sections."),
25359 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
25360 as_fatal ("%s", err_msg);
25363 p = frag_var (rs_align_code,
25364 MAX_MEM_FOR_RS_ALIGN_CODE,
25366 (relax_substateT) max,
25373 /* Perform target specific initialisation of a frag.
25374 Note - despite the name this initialisation is not done when the frag
25375 is created, but only when its type is assigned. A frag can be created
25376 and used a long time before its type is set, so beware of assuming that
25377 this initialisation is performed first. */
25381 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
25383 /* Record whether this frag is in an ARM or a THUMB area. */
25384 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
25387 #else /* OBJ_ELF is defined. */
25389 arm_init_frag (fragS * fragP, int max_chars)
25391 bfd_boolean frag_thumb_mode;
25393 /* If the current ARM vs THUMB mode has not already
25394 been recorded into this frag then do so now. */
25395 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
25396 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
25398 /* PR 21809: Do not set a mapping state for debug sections
25399 - it just confuses other tools. */
25400 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
25403 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
25405 /* Record a mapping symbol for alignment frags. We will delete this
25406 later if the alignment ends up empty. */
25407 switch (fragP->fr_type)
25410 case rs_align_test:
25412 mapping_state_2 (MAP_DATA, max_chars);
25414 case rs_align_code:
25415 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
25422 /* When we change sections we need to issue a new mapping symbol. */
25425 arm_elf_change_section (void)
25427 /* Link an unlinked unwind index table section to the .text section. */
25428 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
25429 && elf_linked_to_section (now_seg) == NULL)
25430 elf_linked_to_section (now_seg) = text_section;
25434 arm_elf_section_type (const char * str, size_t len)
25436 if (len == 5 && strncmp (str, "exidx", 5) == 0)
25437 return SHT_ARM_EXIDX;
25442 /* Code to deal with unwinding tables. */
25444 static void add_unwind_adjustsp (offsetT);
25446 /* Generate any deferred unwind frame offset. */
25449 flush_pending_unwind (void)
25453 offset = unwind.pending_offset;
25454 unwind.pending_offset = 0;
25456 add_unwind_adjustsp (offset);
25459 /* Add an opcode to this list for this function. Two-byte opcodes should
25460 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25464 add_unwind_opcode (valueT op, int length)
25466 /* Add any deferred stack adjustment. */
25467 if (unwind.pending_offset)
25468 flush_pending_unwind ();
25470 unwind.sp_restored = 0;
25472 if (unwind.opcode_count + length > unwind.opcode_alloc)
25474 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
25475 if (unwind.opcodes)
25476 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
25477 unwind.opcode_alloc);
25479 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
25484 unwind.opcodes[unwind.opcode_count] = op & 0xff;
25486 unwind.opcode_count++;
25490 /* Add unwind opcodes to adjust the stack pointer. */
25493 add_unwind_adjustsp (offsetT offset)
25497 if (offset > 0x200)
25499 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
25504 /* Long form: 0xb2, uleb128. */
25505 /* This might not fit in a word so add the individual bytes,
25506 remembering the list is built in reverse order. */
25507 o = (valueT) ((offset - 0x204) >> 2);
25509 add_unwind_opcode (0, 1);
25511 /* Calculate the uleb128 encoding of the offset. */
25515 bytes[n] = o & 0x7f;
25521 /* Add the insn. */
25523 add_unwind_opcode (bytes[n - 1], 1);
25524 add_unwind_opcode (0xb2, 1);
25526 else if (offset > 0x100)
25528 /* Two short opcodes. */
25529 add_unwind_opcode (0x3f, 1);
25530 op = (offset - 0x104) >> 2;
25531 add_unwind_opcode (op, 1);
25533 else if (offset > 0)
25535 /* Short opcode. */
25536 op = (offset - 4) >> 2;
25537 add_unwind_opcode (op, 1);
25539 else if (offset < 0)
25542 while (offset > 0x100)
25544 add_unwind_opcode (0x7f, 1);
25547 op = ((offset - 4) >> 2) | 0x40;
25548 add_unwind_opcode (op, 1);
25552 /* Finish the list of unwind opcodes for this function. */
25555 finish_unwind_opcodes (void)
25559 if (unwind.fp_used)
25561 /* Adjust sp as necessary. */
25562 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
25563 flush_pending_unwind ();
25565 /* After restoring sp from the frame pointer. */
25566 op = 0x90 | unwind.fp_reg;
25567 add_unwind_opcode (op, 1);
25570 flush_pending_unwind ();
25574 /* Start an exception table entry. If idx is nonzero this is an index table
25578 start_unwind_section (const segT text_seg, int idx)
25580 const char * text_name;
25581 const char * prefix;
25582 const char * prefix_once;
25583 const char * group_name;
25591 prefix = ELF_STRING_ARM_unwind;
25592 prefix_once = ELF_STRING_ARM_unwind_once;
25593 type = SHT_ARM_EXIDX;
25597 prefix = ELF_STRING_ARM_unwind_info;
25598 prefix_once = ELF_STRING_ARM_unwind_info_once;
25599 type = SHT_PROGBITS;
25602 text_name = segment_name (text_seg);
25603 if (streq (text_name, ".text"))
25606 if (strncmp (text_name, ".gnu.linkonce.t.",
25607 strlen (".gnu.linkonce.t.")) == 0)
25609 prefix = prefix_once;
25610 text_name += strlen (".gnu.linkonce.t.");
25613 sec_name = concat (prefix, text_name, (char *) NULL);
25619 /* Handle COMDAT group. */
25620 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
25622 group_name = elf_group_name (text_seg);
25623 if (group_name == NULL)
25625 as_bad (_("Group section `%s' has no group signature"),
25626 segment_name (text_seg));
25627 ignore_rest_of_line ();
25630 flags |= SHF_GROUP;
25634 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
25637 /* Set the section link for index tables. */
25639 elf_linked_to_section (now_seg) = text_seg;
25643 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25644 personality routine data. Returns zero, or the index table value for
25645 an inline entry. */
25648 create_unwind_entry (int have_data)
25653 /* The current word of data. */
25655 /* The number of bytes left in this word. */
25658 finish_unwind_opcodes ();
25660 /* Remember the current text section. */
25661 unwind.saved_seg = now_seg;
25662 unwind.saved_subseg = now_subseg;
25664 start_unwind_section (now_seg, 0);
25666 if (unwind.personality_routine == NULL)
25668 if (unwind.personality_index == -2)
25671 as_bad (_("handlerdata in cantunwind frame"));
25672 return 1; /* EXIDX_CANTUNWIND. */
25675 /* Use a default personality routine if none is specified. */
25676 if (unwind.personality_index == -1)
25678 if (unwind.opcode_count > 3)
25679 unwind.personality_index = 1;
25681 unwind.personality_index = 0;
25684 /* Space for the personality routine entry. */
25685 if (unwind.personality_index == 0)
25687 if (unwind.opcode_count > 3)
25688 as_bad (_("too many unwind opcodes for personality routine 0"));
25692 /* All the data is inline in the index table. */
25695 while (unwind.opcode_count > 0)
25697 unwind.opcode_count--;
25698 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
25702 /* Pad with "finish" opcodes. */
25704 data = (data << 8) | 0xb0;
25711 /* We get two opcodes "free" in the first word. */
25712 size = unwind.opcode_count - 2;
25716 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25717 if (unwind.personality_index != -1)
25719 as_bad (_("attempt to recreate an unwind entry"));
25723 /* An extra byte is required for the opcode count. */
25724 size = unwind.opcode_count + 1;
25727 size = (size + 3) >> 2;
25729 as_bad (_("too many unwind opcodes"));
25731 frag_align (2, 0, 0);
25732 record_alignment (now_seg, 2);
25733 unwind.table_entry = expr_build_dot ();
25735 /* Allocate the table entry. */
25736 ptr = frag_more ((size << 2) + 4);
25737 /* PR 13449: Zero the table entries in case some of them are not used. */
25738 memset (ptr, 0, (size << 2) + 4);
25739 where = frag_now_fix () - ((size << 2) + 4);
25741 switch (unwind.personality_index)
25744 /* ??? Should this be a PLT generating relocation? */
25745 /* Custom personality routine. */
25746 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
25747 BFD_RELOC_ARM_PREL31);
25752 /* Set the first byte to the number of additional words. */
25753 data = size > 0 ? size - 1 : 0;
25757 /* ABI defined personality routines. */
25759 /* Three opcodes bytes are packed into the first word. */
25766 /* The size and first two opcode bytes go in the first word. */
25767 data = ((0x80 + unwind.personality_index) << 8) | size;
25772 /* Should never happen. */
25776 /* Pack the opcodes into words (MSB first), reversing the list at the same
25778 while (unwind.opcode_count > 0)
25782 md_number_to_chars (ptr, data, 4);
25787 unwind.opcode_count--;
25789 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
25792 /* Finish off the last word. */
25795 /* Pad with "finish" opcodes. */
25797 data = (data << 8) | 0xb0;
25799 md_number_to_chars (ptr, data, 4);
25804 /* Add an empty descriptor if there is no user-specified data. */
25805 ptr = frag_more (4);
25806 md_number_to_chars (ptr, 0, 4);
25813 /* Initialize the DWARF-2 unwind information for this procedure. */
25816 tc_arm_frame_initial_instructions (void)
25818 cfi_add_CFA_def_cfa (REG_SP, 0);
25820 #endif /* OBJ_ELF */
25822 /* Convert REGNAME to a DWARF-2 register number. */
25825 tc_arm_regname_to_dw2regnum (char *regname)
25827 int reg = arm_reg_parse (®name, REG_TYPE_RN);
25831 /* PR 16694: Allow VFP registers as well. */
25832 reg = arm_reg_parse (®name, REG_TYPE_VFS);
25836 reg = arm_reg_parse (®name, REG_TYPE_VFD);
25845 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
25849 exp.X_op = O_secrel;
25850 exp.X_add_symbol = symbol;
25851 exp.X_add_number = 0;
25852 emit_expr (&exp, size);
25856 /* MD interface: Symbol and relocation handling. */
25858 /* Return the address within the segment that a PC-relative fixup is
25859 relative to. For ARM, PC-relative fixups applied to instructions
25860 are generally relative to the location of the fixup plus 8 bytes.
25861 Thumb branches are offset by 4, and Thumb loads relative to PC
25862 require special handling. */
25865 md_pcrel_from_section (fixS * fixP, segT seg)
25867 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
25869 /* If this is pc-relative and we are going to emit a relocation
25870 then we just want to put out any pipeline compensation that the linker
25871 will need. Otherwise we want to use the calculated base.
25872 For WinCE we skip the bias for externals as well, since this
25873 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25875 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
25876 || (arm_force_relocation (fixP)
25878 && !S_IS_EXTERNAL (fixP->fx_addsy)
25884 switch (fixP->fx_r_type)
25886 /* PC relative addressing on the Thumb is slightly odd as the
25887 bottom two bits of the PC are forced to zero for the
25888 calculation. This happens *after* application of the
25889 pipeline offset. However, Thumb adrl already adjusts for
25890 this, so we need not do it again. */
25891 case BFD_RELOC_ARM_THUMB_ADD:
25894 case BFD_RELOC_ARM_THUMB_OFFSET:
25895 case BFD_RELOC_ARM_T32_OFFSET_IMM:
25896 case BFD_RELOC_ARM_T32_ADD_PC12:
25897 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
25898 return (base + 4) & ~3;
25900 /* Thumb branches are simply offset by +4. */
25901 case BFD_RELOC_THUMB_PCREL_BRANCH5:
25902 case BFD_RELOC_THUMB_PCREL_BRANCH7:
25903 case BFD_RELOC_THUMB_PCREL_BRANCH9:
25904 case BFD_RELOC_THUMB_PCREL_BRANCH12:
25905 case BFD_RELOC_THUMB_PCREL_BRANCH20:
25906 case BFD_RELOC_THUMB_PCREL_BRANCH25:
25907 case BFD_RELOC_THUMB_PCREL_BFCSEL:
25908 case BFD_RELOC_ARM_THUMB_BF17:
25909 case BFD_RELOC_ARM_THUMB_BF19:
25910 case BFD_RELOC_ARM_THUMB_BF13:
25911 case BFD_RELOC_ARM_THUMB_LOOP12:
25914 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25916 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25917 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25918 && ARM_IS_FUNC (fixP->fx_addsy)
25919 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25920 base = fixP->fx_where + fixP->fx_frag->fr_address;
25923 /* BLX is like branches above, but forces the low two bits of PC to
25925 case BFD_RELOC_THUMB_PCREL_BLX:
25927 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25928 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25929 && THUMB_IS_FUNC (fixP->fx_addsy)
25930 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25931 base = fixP->fx_where + fixP->fx_frag->fr_address;
25932 return (base + 4) & ~3;
25934 /* ARM mode branches are offset by +8. However, the Windows CE
25935 loader expects the relocation not to take this into account. */
25936 case BFD_RELOC_ARM_PCREL_BLX:
25938 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25939 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25940 && ARM_IS_FUNC (fixP->fx_addsy)
25941 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25942 base = fixP->fx_where + fixP->fx_frag->fr_address;
25945 case BFD_RELOC_ARM_PCREL_CALL:
25947 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25948 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
25949 && THUMB_IS_FUNC (fixP->fx_addsy)
25950 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
25951 base = fixP->fx_where + fixP->fx_frag->fr_address;
25954 case BFD_RELOC_ARM_PCREL_BRANCH:
25955 case BFD_RELOC_ARM_PCREL_JUMP:
25956 case BFD_RELOC_ARM_PLT32:
25958 /* When handling fixups immediately, because we have already
25959 discovered the value of a symbol, or the address of the frag involved
25960 we must account for the offset by +8, as the OS loader will never see the reloc.
25961 see fixup_segment() in write.c
25962 The S_IS_EXTERNAL test handles the case of global symbols.
25963 Those need the calculated base, not just the pipe compensation the linker will need. */
25965 && fixP->fx_addsy != NULL
25966 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
25967 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
25975 /* ARM mode loads relative to PC are also offset by +8. Unlike
25976 branches, the Windows CE loader *does* expect the relocation
25977 to take this into account. */
25978 case BFD_RELOC_ARM_OFFSET_IMM:
25979 case BFD_RELOC_ARM_OFFSET_IMM8:
25980 case BFD_RELOC_ARM_HWLITERAL:
25981 case BFD_RELOC_ARM_LITERAL:
25982 case BFD_RELOC_ARM_CP_OFF_IMM:
25986 /* Other PC-relative relocations are un-offset. */
25992 static bfd_boolean flag_warn_syms = TRUE;
25995 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
25997 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25998 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25999 does mean that the resulting code might be very confusing to the reader.
26000 Also this warning can be triggered if the user omits an operand before
26001 an immediate address, eg:
26005 GAS treats this as an assignment of the value of the symbol foo to a
26006 symbol LDR, and so (without this code) it will not issue any kind of
26007 warning or error message.
26009 Note - ARM instructions are case-insensitive but the strings in the hash
26010 table are all stored in lower case, so we must first ensure that name is
26012 if (flag_warn_syms && arm_ops_hsh)
26014 char * nbuf = strdup (name);
26017 for (p = nbuf; *p; p++)
26019 if (hash_find (arm_ops_hsh, nbuf) != NULL)
26021 static struct hash_control * already_warned = NULL;
26023 if (already_warned == NULL)
26024 already_warned = hash_new ();
26025 /* Only warn about the symbol once. To keep the code
26026 simple we let hash_insert do the lookup for us. */
26027 if (hash_insert (already_warned, nbuf, NULL) == NULL)
26028 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
26037 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26038 Otherwise we have no need to default values of symbols. */
26041 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
26044 if (name[0] == '_' && name[1] == 'G'
26045 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
26049 if (symbol_find (name))
26050 as_bad (_("GOT already in the symbol table"));
26052 GOT_symbol = symbol_new (name, undefined_section,
26053 (valueT) 0, & zero_address_frag);
26063 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26064 computed as two separate immediate values, added together. We
26065 already know that this value cannot be computed by just one ARM
26068 static unsigned int
26069 validate_immediate_twopart (unsigned int val,
26070 unsigned int * highpart)
26075 for (i = 0; i < 32; i += 2)
26076 if (((a = rotate_left (val, i)) & 0xff) != 0)
26082 * highpart = (a >> 8) | ((i + 24) << 7);
26084 else if (a & 0xff0000)
26086 if (a & 0xff000000)
26088 * highpart = (a >> 16) | ((i + 16) << 7);
26092 gas_assert (a & 0xff000000);
26093 * highpart = (a >> 24) | ((i + 8) << 7);
26096 return (a & 0xff) | (i << 7);
26103 validate_offset_imm (unsigned int val, int hwse)
26105 if ((hwse && val > 255) || val > 4095)
26110 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26111 negative immediate constant by altering the instruction. A bit of
26116 by inverting the second operand, and
26119 by negating the second operand. */
26122 negate_data_op (unsigned long * instruction,
26123 unsigned long value)
26126 unsigned long negated, inverted;
26128 negated = encode_arm_immediate (-value);
26129 inverted = encode_arm_immediate (~value);
26131 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
26134 /* First negates. */
26135 case OPCODE_SUB: /* ADD <-> SUB */
26136 new_inst = OPCODE_ADD;
26141 new_inst = OPCODE_SUB;
26145 case OPCODE_CMP: /* CMP <-> CMN */
26146 new_inst = OPCODE_CMN;
26151 new_inst = OPCODE_CMP;
26155 /* Now Inverted ops. */
26156 case OPCODE_MOV: /* MOV <-> MVN */
26157 new_inst = OPCODE_MVN;
26162 new_inst = OPCODE_MOV;
26166 case OPCODE_AND: /* AND <-> BIC */
26167 new_inst = OPCODE_BIC;
26172 new_inst = OPCODE_AND;
26176 case OPCODE_ADC: /* ADC <-> SBC */
26177 new_inst = OPCODE_SBC;
26182 new_inst = OPCODE_ADC;
26186 /* We cannot do anything. */
26191 if (value == (unsigned) FAIL)
26194 *instruction &= OPCODE_MASK;
26195 *instruction |= new_inst << DATA_OP_SHIFT;
26199 /* Like negate_data_op, but for Thumb-2. */
26201 static unsigned int
26202 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
26206 unsigned int negated, inverted;
26208 negated = encode_thumb32_immediate (-value);
26209 inverted = encode_thumb32_immediate (~value);
26211 rd = (*instruction >> 8) & 0xf;
26212 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
26215 /* ADD <-> SUB. Includes CMP <-> CMN. */
26216 case T2_OPCODE_SUB:
26217 new_inst = T2_OPCODE_ADD;
26221 case T2_OPCODE_ADD:
26222 new_inst = T2_OPCODE_SUB;
26226 /* ORR <-> ORN. Includes MOV <-> MVN. */
26227 case T2_OPCODE_ORR:
26228 new_inst = T2_OPCODE_ORN;
26232 case T2_OPCODE_ORN:
26233 new_inst = T2_OPCODE_ORR;
26237 /* AND <-> BIC. TST has no inverted equivalent. */
26238 case T2_OPCODE_AND:
26239 new_inst = T2_OPCODE_BIC;
26246 case T2_OPCODE_BIC:
26247 new_inst = T2_OPCODE_AND;
26252 case T2_OPCODE_ADC:
26253 new_inst = T2_OPCODE_SBC;
26257 case T2_OPCODE_SBC:
26258 new_inst = T2_OPCODE_ADC;
26262 /* We cannot do anything. */
26267 if (value == (unsigned int)FAIL)
26270 *instruction &= T2_OPCODE_MASK;
26271 *instruction |= new_inst << T2_DATA_OP_SHIFT;
26275 /* Read a 32-bit thumb instruction from buf. */
26277 static unsigned long
26278 get_thumb32_insn (char * buf)
26280 unsigned long insn;
26281 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
26282 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26287 /* We usually want to set the low bit on the address of thumb function
26288 symbols. In particular .word foo - . should have the low bit set.
26289 Generic code tries to fold the difference of two symbols to
26290 a constant. Prevent this and force a relocation when the first symbols
26291 is a thumb function. */
26294 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
26296 if (op == O_subtract
26297 && l->X_op == O_symbol
26298 && r->X_op == O_symbol
26299 && THUMB_IS_FUNC (l->X_add_symbol))
26301 l->X_op = O_subtract;
26302 l->X_op_symbol = r->X_add_symbol;
26303 l->X_add_number -= r->X_add_number;
26307 /* Process as normal. */
26311 /* Encode Thumb2 unconditional branches and calls. The encoding
26312 for the 2 are identical for the immediate values. */
26315 encode_thumb2_b_bl_offset (char * buf, offsetT value)
26317 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26320 addressT S, I1, I2, lo, hi;
26322 S = (value >> 24) & 0x01;
26323 I1 = (value >> 23) & 0x01;
26324 I2 = (value >> 22) & 0x01;
26325 hi = (value >> 12) & 0x3ff;
26326 lo = (value >> 1) & 0x7ff;
26327 newval = md_chars_to_number (buf, THUMB_SIZE);
26328 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26329 newval |= (S << 10) | hi;
26330 newval2 &= ~T2I1I2MASK;
26331 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
26332 md_number_to_chars (buf, newval, THUMB_SIZE);
26333 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
26337 md_apply_fix (fixS * fixP,
26341 offsetT value = * valP;
26343 unsigned int newimm;
26344 unsigned long temp;
26346 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
26348 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
26350 /* Note whether this will delete the relocation. */
26352 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
26355 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26356 consistency with the behaviour on 32-bit hosts. Remember value
26358 value &= 0xffffffff;
26359 value ^= 0x80000000;
26360 value -= 0x80000000;
26363 fixP->fx_addnumber = value;
26365 /* Same treatment for fixP->fx_offset. */
26366 fixP->fx_offset &= 0xffffffff;
26367 fixP->fx_offset ^= 0x80000000;
26368 fixP->fx_offset -= 0x80000000;
26370 switch (fixP->fx_r_type)
26372 case BFD_RELOC_NONE:
26373 /* This will need to go in the object file. */
26377 case BFD_RELOC_ARM_IMMEDIATE:
26378 /* We claim that this fixup has been processed here,
26379 even if in fact we generate an error because we do
26380 not have a reloc for it, so tc_gen_reloc will reject it. */
26383 if (fixP->fx_addsy)
26385 const char *msg = 0;
26387 if (! S_IS_DEFINED (fixP->fx_addsy))
26388 msg = _("undefined symbol %s used as an immediate value");
26389 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
26390 msg = _("symbol %s is in a different section");
26391 else if (S_IS_WEAK (fixP->fx_addsy))
26392 msg = _("symbol %s is weak and may be overridden later");
26396 as_bad_where (fixP->fx_file, fixP->fx_line,
26397 msg, S_GET_NAME (fixP->fx_addsy));
26402 temp = md_chars_to_number (buf, INSN_SIZE);
26404 /* If the offset is negative, we should use encoding A2 for ADR. */
26405 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
26406 newimm = negate_data_op (&temp, value);
26409 newimm = encode_arm_immediate (value);
26411 /* If the instruction will fail, see if we can fix things up by
26412 changing the opcode. */
26413 if (newimm == (unsigned int) FAIL)
26414 newimm = negate_data_op (&temp, value);
26415 /* MOV accepts both ARM modified immediate (A1 encoding) and
26416 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
26417 When disassembling, MOV is preferred when there is no encoding
26419 if (newimm == (unsigned int) FAIL
26420 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
26421 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
26422 && !((temp >> SBIT_SHIFT) & 0x1)
26423 && value >= 0 && value <= 0xffff)
26425 /* Clear bits[23:20] to change encoding from A1 to A2. */
26426 temp &= 0xff0fffff;
26427 /* Encoding high 4bits imm. Code below will encode the remaining
26429 temp |= (value & 0x0000f000) << 4;
26430 newimm = value & 0x00000fff;
26434 if (newimm == (unsigned int) FAIL)
26436 as_bad_where (fixP->fx_file, fixP->fx_line,
26437 _("invalid constant (%lx) after fixup"),
26438 (unsigned long) value);
26442 newimm |= (temp & 0xfffff000);
26443 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
26446 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
26448 unsigned int highpart = 0;
26449 unsigned int newinsn = 0xe1a00000; /* nop. */
26451 if (fixP->fx_addsy)
26453 const char *msg = 0;
26455 if (! S_IS_DEFINED (fixP->fx_addsy))
26456 msg = _("undefined symbol %s used as an immediate value");
26457 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
26458 msg = _("symbol %s is in a different section");
26459 else if (S_IS_WEAK (fixP->fx_addsy))
26460 msg = _("symbol %s is weak and may be overridden later");
26464 as_bad_where (fixP->fx_file, fixP->fx_line,
26465 msg, S_GET_NAME (fixP->fx_addsy));
26470 newimm = encode_arm_immediate (value);
26471 temp = md_chars_to_number (buf, INSN_SIZE);
26473 /* If the instruction will fail, see if we can fix things up by
26474 changing the opcode. */
26475 if (newimm == (unsigned int) FAIL
26476 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
26478 /* No ? OK - try using two ADD instructions to generate
26480 newimm = validate_immediate_twopart (value, & highpart);
26482 /* Yes - then make sure that the second instruction is
26484 if (newimm != (unsigned int) FAIL)
26486 /* Still No ? Try using a negated value. */
26487 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
26488 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
26489 /* Otherwise - give up. */
26492 as_bad_where (fixP->fx_file, fixP->fx_line,
26493 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
26498 /* Replace the first operand in the 2nd instruction (which
26499 is the PC) with the destination register. We have
26500 already added in the PC in the first instruction and we
26501 do not want to do it again. */
26502 newinsn &= ~ 0xf0000;
26503 newinsn |= ((newinsn & 0x0f000) << 4);
26506 newimm |= (temp & 0xfffff000);
26507 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
26509 highpart |= (newinsn & 0xfffff000);
26510 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
26514 case BFD_RELOC_ARM_OFFSET_IMM:
26515 if (!fixP->fx_done && seg->use_rela_p)
26517 /* Fall through. */
26519 case BFD_RELOC_ARM_LITERAL:
26525 if (validate_offset_imm (value, 0) == FAIL)
26527 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
26528 as_bad_where (fixP->fx_file, fixP->fx_line,
26529 _("invalid literal constant: pool needs to be closer"));
26531 as_bad_where (fixP->fx_file, fixP->fx_line,
26532 _("bad immediate value for offset (%ld)"),
26537 newval = md_chars_to_number (buf, INSN_SIZE);
26539 newval &= 0xfffff000;
26542 newval &= 0xff7ff000;
26543 newval |= value | (sign ? INDEX_UP : 0);
26545 md_number_to_chars (buf, newval, INSN_SIZE);
26548 case BFD_RELOC_ARM_OFFSET_IMM8:
26549 case BFD_RELOC_ARM_HWLITERAL:
26555 if (validate_offset_imm (value, 1) == FAIL)
26557 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
26558 as_bad_where (fixP->fx_file, fixP->fx_line,
26559 _("invalid literal constant: pool needs to be closer"));
26561 as_bad_where (fixP->fx_file, fixP->fx_line,
26562 _("bad immediate value for 8-bit offset (%ld)"),
26567 newval = md_chars_to_number (buf, INSN_SIZE);
26569 newval &= 0xfffff0f0;
26572 newval &= 0xff7ff0f0;
26573 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
26575 md_number_to_chars (buf, newval, INSN_SIZE);
26578 case BFD_RELOC_ARM_T32_OFFSET_U8:
26579 if (value < 0 || value > 1020 || value % 4 != 0)
26580 as_bad_where (fixP->fx_file, fixP->fx_line,
26581 _("bad immediate value for offset (%ld)"), (long) value);
26584 newval = md_chars_to_number (buf+2, THUMB_SIZE);
26586 md_number_to_chars (buf+2, newval, THUMB_SIZE);
26589 case BFD_RELOC_ARM_T32_OFFSET_IMM:
26590 /* This is a complicated relocation used for all varieties of Thumb32
26591 load/store instruction with immediate offset:
26593 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26594 *4, optional writeback(W)
26595 (doubleword load/store)
26597 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26598 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26599 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26600 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26601 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26603 Uppercase letters indicate bits that are already encoded at
26604 this point. Lowercase letters are our problem. For the
26605 second block of instructions, the secondary opcode nybble
26606 (bits 8..11) is present, and bit 23 is zero, even if this is
26607 a PC-relative operation. */
26608 newval = md_chars_to_number (buf, THUMB_SIZE);
26610 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
26612 if ((newval & 0xf0000000) == 0xe0000000)
26614 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26616 newval |= (1 << 23);
26619 if (value % 4 != 0)
26621 as_bad_where (fixP->fx_file, fixP->fx_line,
26622 _("offset not a multiple of 4"));
26628 as_bad_where (fixP->fx_file, fixP->fx_line,
26629 _("offset out of range"));
26634 else if ((newval & 0x000f0000) == 0x000f0000)
26636 /* PC-relative, 12-bit offset. */
26638 newval |= (1 << 23);
26643 as_bad_where (fixP->fx_file, fixP->fx_line,
26644 _("offset out of range"));
26649 else if ((newval & 0x00000100) == 0x00000100)
26651 /* Writeback: 8-bit, +/- offset. */
26653 newval |= (1 << 9);
26658 as_bad_where (fixP->fx_file, fixP->fx_line,
26659 _("offset out of range"));
26664 else if ((newval & 0x00000f00) == 0x00000e00)
26666 /* T-instruction: positive 8-bit offset. */
26667 if (value < 0 || value > 0xff)
26669 as_bad_where (fixP->fx_file, fixP->fx_line,
26670 _("offset out of range"));
26678 /* Positive 12-bit or negative 8-bit offset. */
26682 newval |= (1 << 23);
26692 as_bad_where (fixP->fx_file, fixP->fx_line,
26693 _("offset out of range"));
26700 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
26701 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
26704 case BFD_RELOC_ARM_SHIFT_IMM:
26705 newval = md_chars_to_number (buf, INSN_SIZE);
26706 if (((unsigned long) value) > 32
26708 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
26710 as_bad_where (fixP->fx_file, fixP->fx_line,
26711 _("shift expression is too large"));
26716 /* Shifts of zero must be done as lsl. */
26718 else if (value == 32)
26720 newval &= 0xfffff07f;
26721 newval |= (value & 0x1f) << 7;
26722 md_number_to_chars (buf, newval, INSN_SIZE);
26725 case BFD_RELOC_ARM_T32_IMMEDIATE:
26726 case BFD_RELOC_ARM_T32_ADD_IMM:
26727 case BFD_RELOC_ARM_T32_IMM12:
26728 case BFD_RELOC_ARM_T32_ADD_PC12:
26729 /* We claim that this fixup has been processed here,
26730 even if in fact we generate an error because we do
26731 not have a reloc for it, so tc_gen_reloc will reject it. */
26735 && ! S_IS_DEFINED (fixP->fx_addsy))
26737 as_bad_where (fixP->fx_file, fixP->fx_line,
26738 _("undefined symbol %s used as an immediate value"),
26739 S_GET_NAME (fixP->fx_addsy));
26743 newval = md_chars_to_number (buf, THUMB_SIZE);
26745 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
26748 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
26749 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26750 Thumb2 modified immediate encoding (T2). */
26751 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
26752 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
26754 newimm = encode_thumb32_immediate (value);
26755 if (newimm == (unsigned int) FAIL)
26756 newimm = thumb32_negate_data_op (&newval, value);
26758 if (newimm == (unsigned int) FAIL)
26760 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
26762 /* Turn add/sum into addw/subw. */
26763 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
26764 newval = (newval & 0xfeffffff) | 0x02000000;
26765 /* No flat 12-bit imm encoding for addsw/subsw. */
26766 if ((newval & 0x00100000) == 0)
26768 /* 12 bit immediate for addw/subw. */
26772 newval ^= 0x00a00000;
26775 newimm = (unsigned int) FAIL;
26782 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26783 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26784 disassembling, MOV is preferred when there is no encoding
26786 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
26787 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26788 but with the Rn field [19:16] set to 1111. */
26789 && (((newval >> 16) & 0xf) == 0xf)
26790 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
26791 && !((newval >> T2_SBIT_SHIFT) & 0x1)
26792 && value >= 0 && value <= 0xffff)
26794 /* Toggle bit[25] to change encoding from T2 to T3. */
26796 /* Clear bits[19:16]. */
26797 newval &= 0xfff0ffff;
26798 /* Encoding high 4bits imm. Code below will encode the
26799 remaining low 12bits. */
26800 newval |= (value & 0x0000f000) << 4;
26801 newimm = value & 0x00000fff;
26806 if (newimm == (unsigned int)FAIL)
26808 as_bad_where (fixP->fx_file, fixP->fx_line,
26809 _("invalid constant (%lx) after fixup"),
26810 (unsigned long) value);
26814 newval |= (newimm & 0x800) << 15;
26815 newval |= (newimm & 0x700) << 4;
26816 newval |= (newimm & 0x0ff);
26818 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
26819 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
26822 case BFD_RELOC_ARM_SMC:
26823 if (((unsigned long) value) > 0xffff)
26824 as_bad_where (fixP->fx_file, fixP->fx_line,
26825 _("invalid smc expression"));
26826 newval = md_chars_to_number (buf, INSN_SIZE);
26827 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
26828 md_number_to_chars (buf, newval, INSN_SIZE);
26831 case BFD_RELOC_ARM_HVC:
26832 if (((unsigned long) value) > 0xffff)
26833 as_bad_where (fixP->fx_file, fixP->fx_line,
26834 _("invalid hvc expression"));
26835 newval = md_chars_to_number (buf, INSN_SIZE);
26836 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
26837 md_number_to_chars (buf, newval, INSN_SIZE);
26840 case BFD_RELOC_ARM_SWI:
26841 if (fixP->tc_fix_data != 0)
26843 if (((unsigned long) value) > 0xff)
26844 as_bad_where (fixP->fx_file, fixP->fx_line,
26845 _("invalid swi expression"));
26846 newval = md_chars_to_number (buf, THUMB_SIZE);
26848 md_number_to_chars (buf, newval, THUMB_SIZE);
26852 if (((unsigned long) value) > 0x00ffffff)
26853 as_bad_where (fixP->fx_file, fixP->fx_line,
26854 _("invalid swi expression"));
26855 newval = md_chars_to_number (buf, INSN_SIZE);
26857 md_number_to_chars (buf, newval, INSN_SIZE);
26861 case BFD_RELOC_ARM_MULTI:
26862 if (((unsigned long) value) > 0xffff)
26863 as_bad_where (fixP->fx_file, fixP->fx_line,
26864 _("invalid expression in load/store multiple"));
26865 newval = value | md_chars_to_number (buf, INSN_SIZE);
26866 md_number_to_chars (buf, newval, INSN_SIZE);
26870 case BFD_RELOC_ARM_PCREL_CALL:
26872 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26874 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26875 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26876 && THUMB_IS_FUNC (fixP->fx_addsy))
26877 /* Flip the bl to blx. This is a simple flip
26878 bit here because we generate PCREL_CALL for
26879 unconditional bls. */
26881 newval = md_chars_to_number (buf, INSN_SIZE);
26882 newval = newval | 0x10000000;
26883 md_number_to_chars (buf, newval, INSN_SIZE);
26889 goto arm_branch_common;
26891 case BFD_RELOC_ARM_PCREL_JUMP:
26892 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26894 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26895 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26896 && THUMB_IS_FUNC (fixP->fx_addsy))
26898 /* This would map to a bl<cond>, b<cond>,
26899 b<always> to a Thumb function. We
26900 need to force a relocation for this particular
26902 newval = md_chars_to_number (buf, INSN_SIZE);
26905 /* Fall through. */
26907 case BFD_RELOC_ARM_PLT32:
26909 case BFD_RELOC_ARM_PCREL_BRANCH:
26911 goto arm_branch_common;
26913 case BFD_RELOC_ARM_PCREL_BLX:
26916 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26918 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26919 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26920 && ARM_IS_FUNC (fixP->fx_addsy))
26922 /* Flip the blx to a bl and warn. */
26923 const char *name = S_GET_NAME (fixP->fx_addsy);
26924 newval = 0xeb000000;
26925 as_warn_where (fixP->fx_file, fixP->fx_line,
26926 _("blx to '%s' an ARM ISA state function changed to bl"),
26928 md_number_to_chars (buf, newval, INSN_SIZE);
26934 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
26935 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
26939 /* We are going to store value (shifted right by two) in the
26940 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26941 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26944 as_bad_where (fixP->fx_file, fixP->fx_line,
26945 _("misaligned branch destination"));
26946 if ((value & (offsetT)0xfe000000) != (offsetT)0
26947 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
26948 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
26950 if (fixP->fx_done || !seg->use_rela_p)
26952 newval = md_chars_to_number (buf, INSN_SIZE);
26953 newval |= (value >> 2) & 0x00ffffff;
26954 /* Set the H bit on BLX instructions. */
26958 newval |= 0x01000000;
26960 newval &= ~0x01000000;
26962 md_number_to_chars (buf, newval, INSN_SIZE);
26966 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
26967 /* CBZ can only branch forward. */
26969 /* Attempts to use CBZ to branch to the next instruction
26970 (which, strictly speaking, are prohibited) will be turned into
26973 FIXME: It may be better to remove the instruction completely and
26974 perform relaxation. */
26977 newval = md_chars_to_number (buf, THUMB_SIZE);
26978 newval = 0xbf00; /* NOP encoding T1 */
26979 md_number_to_chars (buf, newval, THUMB_SIZE);
26984 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
26986 if (fixP->fx_done || !seg->use_rela_p)
26988 newval = md_chars_to_number (buf, THUMB_SIZE);
26989 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
26990 md_number_to_chars (buf, newval, THUMB_SIZE);
26995 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
26996 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
26997 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
26999 if (fixP->fx_done || !seg->use_rela_p)
27001 newval = md_chars_to_number (buf, THUMB_SIZE);
27002 newval |= (value & 0x1ff) >> 1;
27003 md_number_to_chars (buf, newval, THUMB_SIZE);
27007 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
27008 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
27009 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27011 if (fixP->fx_done || !seg->use_rela_p)
27013 newval = md_chars_to_number (buf, THUMB_SIZE);
27014 newval |= (value & 0xfff) >> 1;
27015 md_number_to_chars (buf, newval, THUMB_SIZE);
27019 case BFD_RELOC_THUMB_PCREL_BRANCH20:
27021 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27022 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27023 && ARM_IS_FUNC (fixP->fx_addsy)
27024 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27026 /* Force a relocation for a branch 20 bits wide. */
27029 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
27030 as_bad_where (fixP->fx_file, fixP->fx_line,
27031 _("conditional branch out of range"));
27033 if (fixP->fx_done || !seg->use_rela_p)
27036 addressT S, J1, J2, lo, hi;
27038 S = (value & 0x00100000) >> 20;
27039 J2 = (value & 0x00080000) >> 19;
27040 J1 = (value & 0x00040000) >> 18;
27041 hi = (value & 0x0003f000) >> 12;
27042 lo = (value & 0x00000ffe) >> 1;
27044 newval = md_chars_to_number (buf, THUMB_SIZE);
27045 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27046 newval |= (S << 10) | hi;
27047 newval2 |= (J1 << 13) | (J2 << 11) | lo;
27048 md_number_to_chars (buf, newval, THUMB_SIZE);
27049 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27053 case BFD_RELOC_THUMB_PCREL_BLX:
27054 /* If there is a blx from a thumb state function to
27055 another thumb function flip this to a bl and warn
27059 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27060 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27061 && THUMB_IS_FUNC (fixP->fx_addsy))
27063 const char *name = S_GET_NAME (fixP->fx_addsy);
27064 as_warn_where (fixP->fx_file, fixP->fx_line,
27065 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27067 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27068 newval = newval | 0x1000;
27069 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27070 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27075 goto thumb_bl_common;
27077 case BFD_RELOC_THUMB_PCREL_BRANCH23:
27078 /* A bl from Thumb state ISA to an internal ARM state function
27079 is converted to a blx. */
27081 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27082 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27083 && ARM_IS_FUNC (fixP->fx_addsy)
27084 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27086 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27087 newval = newval & ~0x1000;
27088 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27089 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
27095 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27096 /* For a BLX instruction, make sure that the relocation is rounded up
27097 to a word boundary. This follows the semantics of the instruction
27098 which specifies that bit 1 of the target address will come from bit
27099 1 of the base address. */
27100 value = (value + 3) & ~ 3;
27103 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
27104 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27105 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27108 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
27110 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
27111 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27112 else if ((value & ~0x1ffffff)
27113 && ((value & ~0x1ffffff) != ~0x1ffffff))
27114 as_bad_where (fixP->fx_file, fixP->fx_line,
27115 _("Thumb2 branch out of range"));
27118 if (fixP->fx_done || !seg->use_rela_p)
27119 encode_thumb2_b_bl_offset (buf, value);
27123 case BFD_RELOC_THUMB_PCREL_BRANCH25:
27124 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
27125 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27127 if (fixP->fx_done || !seg->use_rela_p)
27128 encode_thumb2_b_bl_offset (buf, value);
27133 if (fixP->fx_done || !seg->use_rela_p)
27138 if (fixP->fx_done || !seg->use_rela_p)
27139 md_number_to_chars (buf, value, 2);
27143 case BFD_RELOC_ARM_TLS_CALL:
27144 case BFD_RELOC_ARM_THM_TLS_CALL:
27145 case BFD_RELOC_ARM_TLS_DESCSEQ:
27146 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
27147 case BFD_RELOC_ARM_TLS_GOTDESC:
27148 case BFD_RELOC_ARM_TLS_GD32:
27149 case BFD_RELOC_ARM_TLS_LE32:
27150 case BFD_RELOC_ARM_TLS_IE32:
27151 case BFD_RELOC_ARM_TLS_LDM32:
27152 case BFD_RELOC_ARM_TLS_LDO32:
27153 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27156 /* Same handling as above, but with the arm_fdpic guard. */
27157 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
27158 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
27159 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
27162 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27166 as_bad_where (fixP->fx_file, fixP->fx_line,
27167 _("Relocation supported only in FDPIC mode"));
27171 case BFD_RELOC_ARM_GOT32:
27172 case BFD_RELOC_ARM_GOTOFF:
27175 case BFD_RELOC_ARM_GOT_PREL:
27176 if (fixP->fx_done || !seg->use_rela_p)
27177 md_number_to_chars (buf, value, 4);
27180 case BFD_RELOC_ARM_TARGET2:
27181 /* TARGET2 is not partial-inplace, so we need to write the
27182 addend here for REL targets, because it won't be written out
27183 during reloc processing later. */
27184 if (fixP->fx_done || !seg->use_rela_p)
27185 md_number_to_chars (buf, fixP->fx_offset, 4);
27188 /* Relocations for FDPIC. */
27189 case BFD_RELOC_ARM_GOTFUNCDESC:
27190 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
27191 case BFD_RELOC_ARM_FUNCDESC:
27194 if (fixP->fx_done || !seg->use_rela_p)
27195 md_number_to_chars (buf, 0, 4);
27199 as_bad_where (fixP->fx_file, fixP->fx_line,
27200 _("Relocation supported only in FDPIC mode"));
27205 case BFD_RELOC_RVA:
27207 case BFD_RELOC_ARM_TARGET1:
27208 case BFD_RELOC_ARM_ROSEGREL32:
27209 case BFD_RELOC_ARM_SBREL32:
27210 case BFD_RELOC_32_PCREL:
27212 case BFD_RELOC_32_SECREL:
27214 if (fixP->fx_done || !seg->use_rela_p)
27216 /* For WinCE we only do this for pcrel fixups. */
27217 if (fixP->fx_done || fixP->fx_pcrel)
27219 md_number_to_chars (buf, value, 4);
27223 case BFD_RELOC_ARM_PREL31:
27224 if (fixP->fx_done || !seg->use_rela_p)
27226 newval = md_chars_to_number (buf, 4) & 0x80000000;
27227 if ((value ^ (value >> 1)) & 0x40000000)
27229 as_bad_where (fixP->fx_file, fixP->fx_line,
27230 _("rel31 relocation overflow"));
27232 newval |= value & 0x7fffffff;
27233 md_number_to_chars (buf, newval, 4);
27238 case BFD_RELOC_ARM_CP_OFF_IMM:
27239 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
27240 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
27241 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
27242 newval = md_chars_to_number (buf, INSN_SIZE);
27244 newval = get_thumb32_insn (buf);
27245 if ((newval & 0x0f200f00) == 0x0d000900)
27247 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27248 has permitted values that are multiples of 2, in the range 0
27250 if (value < -510 || value > 510 || (value & 1))
27251 as_bad_where (fixP->fx_file, fixP->fx_line,
27252 _("co-processor offset out of range"));
27254 else if ((newval & 0xfe001f80) == 0xec000f80)
27256 if (value < -511 || value > 512 || (value & 3))
27257 as_bad_where (fixP->fx_file, fixP->fx_line,
27258 _("co-processor offset out of range"));
27260 else if (value < -1023 || value > 1023 || (value & 3))
27261 as_bad_where (fixP->fx_file, fixP->fx_line,
27262 _("co-processor offset out of range"));
27267 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27268 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27269 newval = md_chars_to_number (buf, INSN_SIZE);
27271 newval = get_thumb32_insn (buf);
27274 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27275 newval &= 0xffffff80;
27277 newval &= 0xffffff00;
27281 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27282 newval &= 0xff7fff80;
27284 newval &= 0xff7fff00;
27285 if ((newval & 0x0f200f00) == 0x0d000900)
27287 /* This is a fp16 vstr/vldr.
27289 It requires the immediate offset in the instruction is shifted
27290 left by 1 to be a half-word offset.
27292 Here, left shift by 1 first, and later right shift by 2
27293 should get the right offset. */
27296 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
27298 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27299 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27300 md_number_to_chars (buf, newval, INSN_SIZE);
27302 put_thumb32_insn (buf, newval);
27305 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
27306 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
27307 if (value < -255 || value > 255)
27308 as_bad_where (fixP->fx_file, fixP->fx_line,
27309 _("co-processor offset out of range"));
27311 goto cp_off_common;
27313 case BFD_RELOC_ARM_THUMB_OFFSET:
27314 newval = md_chars_to_number (buf, THUMB_SIZE);
27315 /* Exactly what ranges, and where the offset is inserted depends
27316 on the type of instruction, we can establish this from the
27318 switch (newval >> 12)
27320 case 4: /* PC load. */
27321 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27322 forced to zero for these loads; md_pcrel_from has already
27323 compensated for this. */
27325 as_bad_where (fixP->fx_file, fixP->fx_line,
27326 _("invalid offset, target not word aligned (0x%08lX)"),
27327 (((unsigned long) fixP->fx_frag->fr_address
27328 + (unsigned long) fixP->fx_where) & ~3)
27329 + (unsigned long) value);
27331 if (value & ~0x3fc)
27332 as_bad_where (fixP->fx_file, fixP->fx_line,
27333 _("invalid offset, value too big (0x%08lX)"),
27336 newval |= value >> 2;
27339 case 9: /* SP load/store. */
27340 if (value & ~0x3fc)
27341 as_bad_where (fixP->fx_file, fixP->fx_line,
27342 _("invalid offset, value too big (0x%08lX)"),
27344 newval |= value >> 2;
27347 case 6: /* Word load/store. */
27349 as_bad_where (fixP->fx_file, fixP->fx_line,
27350 _("invalid offset, value too big (0x%08lX)"),
27352 newval |= value << 4; /* 6 - 2. */
27355 case 7: /* Byte load/store. */
27357 as_bad_where (fixP->fx_file, fixP->fx_line,
27358 _("invalid offset, value too big (0x%08lX)"),
27360 newval |= value << 6;
27363 case 8: /* Halfword load/store. */
27365 as_bad_where (fixP->fx_file, fixP->fx_line,
27366 _("invalid offset, value too big (0x%08lX)"),
27368 newval |= value << 5; /* 6 - 1. */
27372 as_bad_where (fixP->fx_file, fixP->fx_line,
27373 "Unable to process relocation for thumb opcode: %lx",
27374 (unsigned long) newval);
27377 md_number_to_chars (buf, newval, THUMB_SIZE);
27380 case BFD_RELOC_ARM_THUMB_ADD:
27381 /* This is a complicated relocation, since we use it for all of
27382 the following immediate relocations:
27386 9bit ADD/SUB SP word-aligned
27387 10bit ADD PC/SP word-aligned
27389 The type of instruction being processed is encoded in the
27396 newval = md_chars_to_number (buf, THUMB_SIZE);
27398 int rd = (newval >> 4) & 0xf;
27399 int rs = newval & 0xf;
27400 int subtract = !!(newval & 0x8000);
27402 /* Check for HI regs, only very restricted cases allowed:
27403 Adjusting SP, and using PC or SP to get an address. */
27404 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
27405 || (rs > 7 && rs != REG_SP && rs != REG_PC))
27406 as_bad_where (fixP->fx_file, fixP->fx_line,
27407 _("invalid Hi register with immediate"));
27409 /* If value is negative, choose the opposite instruction. */
27413 subtract = !subtract;
27415 as_bad_where (fixP->fx_file, fixP->fx_line,
27416 _("immediate value out of range"));
27421 if (value & ~0x1fc)
27422 as_bad_where (fixP->fx_file, fixP->fx_line,
27423 _("invalid immediate for stack address calculation"));
27424 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
27425 newval |= value >> 2;
27427 else if (rs == REG_PC || rs == REG_SP)
27429 /* PR gas/18541. If the addition is for a defined symbol
27430 within range of an ADR instruction then accept it. */
27433 && fixP->fx_addsy != NULL)
27437 if (! S_IS_DEFINED (fixP->fx_addsy)
27438 || S_GET_SEGMENT (fixP->fx_addsy) != seg
27439 || S_IS_WEAK (fixP->fx_addsy))
27441 as_bad_where (fixP->fx_file, fixP->fx_line,
27442 _("address calculation needs a strongly defined nearby symbol"));
27446 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
27448 /* Round up to the next 4-byte boundary. */
27453 v = S_GET_VALUE (fixP->fx_addsy) - v;
27457 as_bad_where (fixP->fx_file, fixP->fx_line,
27458 _("symbol too far away"));
27468 if (subtract || value & ~0x3fc)
27469 as_bad_where (fixP->fx_file, fixP->fx_line,
27470 _("invalid immediate for address calculation (value = 0x%08lX)"),
27471 (unsigned long) (subtract ? - value : value));
27472 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
27474 newval |= value >> 2;
27479 as_bad_where (fixP->fx_file, fixP->fx_line,
27480 _("immediate value out of range"));
27481 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
27482 newval |= (rd << 8) | value;
27487 as_bad_where (fixP->fx_file, fixP->fx_line,
27488 _("immediate value out of range"));
27489 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
27490 newval |= rd | (rs << 3) | (value << 6);
27493 md_number_to_chars (buf, newval, THUMB_SIZE);
27496 case BFD_RELOC_ARM_THUMB_IMM:
27497 newval = md_chars_to_number (buf, THUMB_SIZE);
27498 if (value < 0 || value > 255)
27499 as_bad_where (fixP->fx_file, fixP->fx_line,
27500 _("invalid immediate: %ld is out of range"),
27503 md_number_to_chars (buf, newval, THUMB_SIZE);
27506 case BFD_RELOC_ARM_THUMB_SHIFT:
27507 /* 5bit shift value (0..32). LSL cannot take 32. */
27508 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
27509 temp = newval & 0xf800;
27510 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
27511 as_bad_where (fixP->fx_file, fixP->fx_line,
27512 _("invalid shift value: %ld"), (long) value);
27513 /* Shifts of zero must be encoded as LSL. */
27515 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
27516 /* Shifts of 32 are encoded as zero. */
27517 else if (value == 32)
27519 newval |= value << 6;
27520 md_number_to_chars (buf, newval, THUMB_SIZE);
27523 case BFD_RELOC_VTABLE_INHERIT:
27524 case BFD_RELOC_VTABLE_ENTRY:
27528 case BFD_RELOC_ARM_MOVW:
27529 case BFD_RELOC_ARM_MOVT:
27530 case BFD_RELOC_ARM_THUMB_MOVW:
27531 case BFD_RELOC_ARM_THUMB_MOVT:
27532 if (fixP->fx_done || !seg->use_rela_p)
27534 /* REL format relocations are limited to a 16-bit addend. */
27535 if (!fixP->fx_done)
27537 if (value < -0x8000 || value > 0x7fff)
27538 as_bad_where (fixP->fx_file, fixP->fx_line,
27539 _("offset out of range"));
27541 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
27542 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
27547 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
27548 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
27550 newval = get_thumb32_insn (buf);
27551 newval &= 0xfbf08f00;
27552 newval |= (value & 0xf000) << 4;
27553 newval |= (value & 0x0800) << 15;
27554 newval |= (value & 0x0700) << 4;
27555 newval |= (value & 0x00ff);
27556 put_thumb32_insn (buf, newval);
27560 newval = md_chars_to_number (buf, 4);
27561 newval &= 0xfff0f000;
27562 newval |= value & 0x0fff;
27563 newval |= (value & 0xf000) << 4;
27564 md_number_to_chars (buf, newval, 4);
27569 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
27570 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
27571 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
27572 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
27573 gas_assert (!fixP->fx_done);
27576 bfd_boolean is_mov;
27577 bfd_vma encoded_addend = value;
27579 /* Check that addend can be encoded in instruction. */
27580 if (!seg->use_rela_p && (value < 0 || value > 255))
27581 as_bad_where (fixP->fx_file, fixP->fx_line,
27582 _("the offset 0x%08lX is not representable"),
27583 (unsigned long) encoded_addend);
27585 /* Extract the instruction. */
27586 insn = md_chars_to_number (buf, THUMB_SIZE);
27587 is_mov = (insn & 0xf800) == 0x2000;
27592 if (!seg->use_rela_p)
27593 insn |= encoded_addend;
27599 /* Extract the instruction. */
27600 /* Encoding is the following
27605 /* The following conditions must be true :
27610 rd = (insn >> 4) & 0xf;
27612 if ((insn & 0x8000) || (rd != rs) || rd > 7)
27613 as_bad_where (fixP->fx_file, fixP->fx_line,
27614 _("Unable to process relocation for thumb opcode: %lx"),
27615 (unsigned long) insn);
27617 /* Encode as ADD immediate8 thumb 1 code. */
27618 insn = 0x3000 | (rd << 8);
27620 /* Place the encoded addend into the first 8 bits of the
27622 if (!seg->use_rela_p)
27623 insn |= encoded_addend;
27626 /* Update the instruction. */
27627 md_number_to_chars (buf, insn, THUMB_SIZE);
27631 case BFD_RELOC_ARM_ALU_PC_G0_NC:
27632 case BFD_RELOC_ARM_ALU_PC_G0:
27633 case BFD_RELOC_ARM_ALU_PC_G1_NC:
27634 case BFD_RELOC_ARM_ALU_PC_G1:
27635 case BFD_RELOC_ARM_ALU_PC_G2:
27636 case BFD_RELOC_ARM_ALU_SB_G0_NC:
27637 case BFD_RELOC_ARM_ALU_SB_G0:
27638 case BFD_RELOC_ARM_ALU_SB_G1_NC:
27639 case BFD_RELOC_ARM_ALU_SB_G1:
27640 case BFD_RELOC_ARM_ALU_SB_G2:
27641 gas_assert (!fixP->fx_done);
27642 if (!seg->use_rela_p)
27645 bfd_vma encoded_addend;
27646 bfd_vma addend_abs = llabs (value);
27648 /* Check that the absolute value of the addend can be
27649 expressed as an 8-bit constant plus a rotation. */
27650 encoded_addend = encode_arm_immediate (addend_abs);
27651 if (encoded_addend == (unsigned int) FAIL)
27652 as_bad_where (fixP->fx_file, fixP->fx_line,
27653 _("the offset 0x%08lX is not representable"),
27654 (unsigned long) addend_abs);
27656 /* Extract the instruction. */
27657 insn = md_chars_to_number (buf, INSN_SIZE);
27659 /* If the addend is positive, use an ADD instruction.
27660 Otherwise use a SUB. Take care not to destroy the S bit. */
27661 insn &= 0xff1fffff;
27667 /* Place the encoded addend into the first 12 bits of the
27669 insn &= 0xfffff000;
27670 insn |= encoded_addend;
27672 /* Update the instruction. */
27673 md_number_to_chars (buf, insn, INSN_SIZE);
27677 case BFD_RELOC_ARM_LDR_PC_G0:
27678 case BFD_RELOC_ARM_LDR_PC_G1:
27679 case BFD_RELOC_ARM_LDR_PC_G2:
27680 case BFD_RELOC_ARM_LDR_SB_G0:
27681 case BFD_RELOC_ARM_LDR_SB_G1:
27682 case BFD_RELOC_ARM_LDR_SB_G2:
27683 gas_assert (!fixP->fx_done);
27684 if (!seg->use_rela_p)
27687 bfd_vma addend_abs = llabs (value);
27689 /* Check that the absolute value of the addend can be
27690 encoded in 12 bits. */
27691 if (addend_abs >= 0x1000)
27692 as_bad_where (fixP->fx_file, fixP->fx_line,
27693 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27694 (unsigned long) addend_abs);
27696 /* Extract the instruction. */
27697 insn = md_chars_to_number (buf, INSN_SIZE);
27699 /* If the addend is negative, clear bit 23 of the instruction.
27700 Otherwise set it. */
27702 insn &= ~(1 << 23);
27706 /* Place the absolute value of the addend into the first 12 bits
27707 of the instruction. */
27708 insn &= 0xfffff000;
27709 insn |= addend_abs;
27711 /* Update the instruction. */
27712 md_number_to_chars (buf, insn, INSN_SIZE);
27716 case BFD_RELOC_ARM_LDRS_PC_G0:
27717 case BFD_RELOC_ARM_LDRS_PC_G1:
27718 case BFD_RELOC_ARM_LDRS_PC_G2:
27719 case BFD_RELOC_ARM_LDRS_SB_G0:
27720 case BFD_RELOC_ARM_LDRS_SB_G1:
27721 case BFD_RELOC_ARM_LDRS_SB_G2:
27722 gas_assert (!fixP->fx_done);
27723 if (!seg->use_rela_p)
27726 bfd_vma addend_abs = llabs (value);
27728 /* Check that the absolute value of the addend can be
27729 encoded in 8 bits. */
27730 if (addend_abs >= 0x100)
27731 as_bad_where (fixP->fx_file, fixP->fx_line,
27732 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27733 (unsigned long) addend_abs);
27735 /* Extract the instruction. */
27736 insn = md_chars_to_number (buf, INSN_SIZE);
27738 /* If the addend is negative, clear bit 23 of the instruction.
27739 Otherwise set it. */
27741 insn &= ~(1 << 23);
27745 /* Place the first four bits of the absolute value of the addend
27746 into the first 4 bits of the instruction, and the remaining
27747 four into bits 8 .. 11. */
27748 insn &= 0xfffff0f0;
27749 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
27751 /* Update the instruction. */
27752 md_number_to_chars (buf, insn, INSN_SIZE);
27756 case BFD_RELOC_ARM_LDC_PC_G0:
27757 case BFD_RELOC_ARM_LDC_PC_G1:
27758 case BFD_RELOC_ARM_LDC_PC_G2:
27759 case BFD_RELOC_ARM_LDC_SB_G0:
27760 case BFD_RELOC_ARM_LDC_SB_G1:
27761 case BFD_RELOC_ARM_LDC_SB_G2:
27762 gas_assert (!fixP->fx_done);
27763 if (!seg->use_rela_p)
27766 bfd_vma addend_abs = llabs (value);
27768 /* Check that the absolute value of the addend is a multiple of
27769 four and, when divided by four, fits in 8 bits. */
27770 if (addend_abs & 0x3)
27771 as_bad_where (fixP->fx_file, fixP->fx_line,
27772 _("bad offset 0x%08lX (must be word-aligned)"),
27773 (unsigned long) addend_abs);
27775 if ((addend_abs >> 2) > 0xff)
27776 as_bad_where (fixP->fx_file, fixP->fx_line,
27777 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27778 (unsigned long) addend_abs);
27780 /* Extract the instruction. */
27781 insn = md_chars_to_number (buf, INSN_SIZE);
27783 /* If the addend is negative, clear bit 23 of the instruction.
27784 Otherwise set it. */
27786 insn &= ~(1 << 23);
27790 /* Place the addend (divided by four) into the first eight
27791 bits of the instruction. */
27792 insn &= 0xfffffff0;
27793 insn |= addend_abs >> 2;
27795 /* Update the instruction. */
27796 md_number_to_chars (buf, insn, INSN_SIZE);
27800 case BFD_RELOC_THUMB_PCREL_BRANCH5:
27802 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27803 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27804 && ARM_IS_FUNC (fixP->fx_addsy)
27805 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27807 /* Force a relocation for a branch 5 bits wide. */
27810 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
27811 as_bad_where (fixP->fx_file, fixP->fx_line,
27814 if (fixP->fx_done || !seg->use_rela_p)
27816 addressT boff = value >> 1;
27818 newval = md_chars_to_number (buf, THUMB_SIZE);
27819 newval |= (boff << 7);
27820 md_number_to_chars (buf, newval, THUMB_SIZE);
27824 case BFD_RELOC_THUMB_PCREL_BFCSEL:
27826 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27827 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27828 && ARM_IS_FUNC (fixP->fx_addsy)
27829 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27833 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
27834 as_bad_where (fixP->fx_file, fixP->fx_line,
27835 _("branch out of range"));
27837 if (fixP->fx_done || !seg->use_rela_p)
27839 newval = md_chars_to_number (buf, THUMB_SIZE);
27841 addressT boff = ((newval & 0x0780) >> 7) << 1;
27842 addressT diff = value - boff;
27846 newval |= 1 << 1; /* T bit. */
27848 else if (diff != 2)
27850 as_bad_where (fixP->fx_file, fixP->fx_line,
27851 _("out of range label-relative fixup value"));
27853 md_number_to_chars (buf, newval, THUMB_SIZE);
27857 case BFD_RELOC_ARM_THUMB_BF17:
27859 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27860 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27861 && ARM_IS_FUNC (fixP->fx_addsy)
27862 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27864 /* Force a relocation for a branch 17 bits wide. */
27868 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
27869 as_bad_where (fixP->fx_file, fixP->fx_line,
27872 if (fixP->fx_done || !seg->use_rela_p)
27875 addressT immA, immB, immC;
27877 immA = (value & 0x0001f000) >> 12;
27878 immB = (value & 0x00000ffc) >> 2;
27879 immC = (value & 0x00000002) >> 1;
27881 newval = md_chars_to_number (buf, THUMB_SIZE);
27882 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27884 newval2 |= (immC << 11) | (immB << 1);
27885 md_number_to_chars (buf, newval, THUMB_SIZE);
27886 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27890 case BFD_RELOC_ARM_THUMB_BF19:
27892 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27893 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27894 && ARM_IS_FUNC (fixP->fx_addsy)
27895 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27897 /* Force a relocation for a branch 19 bits wide. */
27901 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
27902 as_bad_where (fixP->fx_file, fixP->fx_line,
27905 if (fixP->fx_done || !seg->use_rela_p)
27908 addressT immA, immB, immC;
27910 immA = (value & 0x0007f000) >> 12;
27911 immB = (value & 0x00000ffc) >> 2;
27912 immC = (value & 0x00000002) >> 1;
27914 newval = md_chars_to_number (buf, THUMB_SIZE);
27915 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27917 newval2 |= (immC << 11) | (immB << 1);
27918 md_number_to_chars (buf, newval, THUMB_SIZE);
27919 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27923 case BFD_RELOC_ARM_THUMB_BF13:
27925 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27926 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27927 && ARM_IS_FUNC (fixP->fx_addsy)
27928 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27930 /* Force a relocation for a branch 13 bits wide. */
27934 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
27935 as_bad_where (fixP->fx_file, fixP->fx_line,
27938 if (fixP->fx_done || !seg->use_rela_p)
27941 addressT immA, immB, immC;
27943 immA = (value & 0x00001000) >> 12;
27944 immB = (value & 0x00000ffc) >> 2;
27945 immC = (value & 0x00000002) >> 1;
27947 newval = md_chars_to_number (buf, THUMB_SIZE);
27948 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27950 newval2 |= (immC << 11) | (immB << 1);
27951 md_number_to_chars (buf, newval, THUMB_SIZE);
27952 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27956 case BFD_RELOC_ARM_THUMB_LOOP12:
27958 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27959 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27960 && ARM_IS_FUNC (fixP->fx_addsy)
27961 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
27963 /* Force a relocation for a branch 12 bits wide. */
27967 bfd_vma insn = get_thumb32_insn (buf);
27968 /* le lr, <label> or le <label> */
27969 if (((insn & 0xffffffff) == 0xf00fc001)
27970 || ((insn & 0xffffffff) == 0xf02fc001))
27973 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
27974 as_bad_where (fixP->fx_file, fixP->fx_line,
27976 if (fixP->fx_done || !seg->use_rela_p)
27978 addressT imml, immh;
27980 immh = (value & 0x00000ffc) >> 2;
27981 imml = (value & 0x00000002) >> 1;
27983 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27984 newval |= (imml << 11) | (immh << 1);
27985 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
27989 case BFD_RELOC_ARM_V4BX:
27990 /* This will need to go in the object file. */
27994 case BFD_RELOC_UNUSED:
27996 as_bad_where (fixP->fx_file, fixP->fx_line,
27997 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
28001 /* Translate internal representation of relocation info to BFD target
28005 tc_gen_reloc (asection *section, fixS *fixp)
28008 bfd_reloc_code_real_type code;
28010 reloc = XNEW (arelent);
28012 reloc->sym_ptr_ptr = XNEW (asymbol *);
28013 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
28014 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
28016 if (fixp->fx_pcrel)
28018 if (section->use_rela_p)
28019 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
28021 fixp->fx_offset = reloc->address;
28023 reloc->addend = fixp->fx_offset;
28025 switch (fixp->fx_r_type)
28028 if (fixp->fx_pcrel)
28030 code = BFD_RELOC_8_PCREL;
28033 /* Fall through. */
28036 if (fixp->fx_pcrel)
28038 code = BFD_RELOC_16_PCREL;
28041 /* Fall through. */
28044 if (fixp->fx_pcrel)
28046 code = BFD_RELOC_32_PCREL;
28049 /* Fall through. */
28051 case BFD_RELOC_ARM_MOVW:
28052 if (fixp->fx_pcrel)
28054 code = BFD_RELOC_ARM_MOVW_PCREL;
28057 /* Fall through. */
28059 case BFD_RELOC_ARM_MOVT:
28060 if (fixp->fx_pcrel)
28062 code = BFD_RELOC_ARM_MOVT_PCREL;
28065 /* Fall through. */
28067 case BFD_RELOC_ARM_THUMB_MOVW:
28068 if (fixp->fx_pcrel)
28070 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
28073 /* Fall through. */
28075 case BFD_RELOC_ARM_THUMB_MOVT:
28076 if (fixp->fx_pcrel)
28078 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
28081 /* Fall through. */
28083 case BFD_RELOC_NONE:
28084 case BFD_RELOC_ARM_PCREL_BRANCH:
28085 case BFD_RELOC_ARM_PCREL_BLX:
28086 case BFD_RELOC_RVA:
28087 case BFD_RELOC_THUMB_PCREL_BRANCH7:
28088 case BFD_RELOC_THUMB_PCREL_BRANCH9:
28089 case BFD_RELOC_THUMB_PCREL_BRANCH12:
28090 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28091 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28092 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28093 case BFD_RELOC_VTABLE_ENTRY:
28094 case BFD_RELOC_VTABLE_INHERIT:
28096 case BFD_RELOC_32_SECREL:
28098 code = fixp->fx_r_type;
28101 case BFD_RELOC_THUMB_PCREL_BLX:
28103 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
28104 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
28107 code = BFD_RELOC_THUMB_PCREL_BLX;
28110 case BFD_RELOC_ARM_LITERAL:
28111 case BFD_RELOC_ARM_HWLITERAL:
28112 /* If this is called then the a literal has
28113 been referenced across a section boundary. */
28114 as_bad_where (fixp->fx_file, fixp->fx_line,
28115 _("literal referenced across section boundary"));
28119 case BFD_RELOC_ARM_TLS_CALL:
28120 case BFD_RELOC_ARM_THM_TLS_CALL:
28121 case BFD_RELOC_ARM_TLS_DESCSEQ:
28122 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
28123 case BFD_RELOC_ARM_GOT32:
28124 case BFD_RELOC_ARM_GOTOFF:
28125 case BFD_RELOC_ARM_GOT_PREL:
28126 case BFD_RELOC_ARM_PLT32:
28127 case BFD_RELOC_ARM_TARGET1:
28128 case BFD_RELOC_ARM_ROSEGREL32:
28129 case BFD_RELOC_ARM_SBREL32:
28130 case BFD_RELOC_ARM_PREL31:
28131 case BFD_RELOC_ARM_TARGET2:
28132 case BFD_RELOC_ARM_TLS_LDO32:
28133 case BFD_RELOC_ARM_PCREL_CALL:
28134 case BFD_RELOC_ARM_PCREL_JUMP:
28135 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28136 case BFD_RELOC_ARM_ALU_PC_G0:
28137 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28138 case BFD_RELOC_ARM_ALU_PC_G1:
28139 case BFD_RELOC_ARM_ALU_PC_G2:
28140 case BFD_RELOC_ARM_LDR_PC_G0:
28141 case BFD_RELOC_ARM_LDR_PC_G1:
28142 case BFD_RELOC_ARM_LDR_PC_G2:
28143 case BFD_RELOC_ARM_LDRS_PC_G0:
28144 case BFD_RELOC_ARM_LDRS_PC_G1:
28145 case BFD_RELOC_ARM_LDRS_PC_G2:
28146 case BFD_RELOC_ARM_LDC_PC_G0:
28147 case BFD_RELOC_ARM_LDC_PC_G1:
28148 case BFD_RELOC_ARM_LDC_PC_G2:
28149 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28150 case BFD_RELOC_ARM_ALU_SB_G0:
28151 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28152 case BFD_RELOC_ARM_ALU_SB_G1:
28153 case BFD_RELOC_ARM_ALU_SB_G2:
28154 case BFD_RELOC_ARM_LDR_SB_G0:
28155 case BFD_RELOC_ARM_LDR_SB_G1:
28156 case BFD_RELOC_ARM_LDR_SB_G2:
28157 case BFD_RELOC_ARM_LDRS_SB_G0:
28158 case BFD_RELOC_ARM_LDRS_SB_G1:
28159 case BFD_RELOC_ARM_LDRS_SB_G2:
28160 case BFD_RELOC_ARM_LDC_SB_G0:
28161 case BFD_RELOC_ARM_LDC_SB_G1:
28162 case BFD_RELOC_ARM_LDC_SB_G2:
28163 case BFD_RELOC_ARM_V4BX:
28164 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28165 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28166 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28167 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28168 case BFD_RELOC_ARM_GOTFUNCDESC:
28169 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28170 case BFD_RELOC_ARM_FUNCDESC:
28171 case BFD_RELOC_ARM_THUMB_BF17:
28172 case BFD_RELOC_ARM_THUMB_BF19:
28173 case BFD_RELOC_ARM_THUMB_BF13:
28174 code = fixp->fx_r_type;
28177 case BFD_RELOC_ARM_TLS_GOTDESC:
28178 case BFD_RELOC_ARM_TLS_GD32:
28179 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28180 case BFD_RELOC_ARM_TLS_LE32:
28181 case BFD_RELOC_ARM_TLS_IE32:
28182 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28183 case BFD_RELOC_ARM_TLS_LDM32:
28184 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28185 /* BFD will include the symbol's address in the addend.
28186 But we don't want that, so subtract it out again here. */
28187 if (!S_IS_COMMON (fixp->fx_addsy))
28188 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
28189 code = fixp->fx_r_type;
28193 case BFD_RELOC_ARM_IMMEDIATE:
28194 as_bad_where (fixp->fx_file, fixp->fx_line,
28195 _("internal relocation (type: IMMEDIATE) not fixed up"));
28198 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28199 as_bad_where (fixp->fx_file, fixp->fx_line,
28200 _("ADRL used for a symbol not defined in the same file"));
28203 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28204 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28205 case BFD_RELOC_ARM_THUMB_LOOP12:
28206 as_bad_where (fixp->fx_file, fixp->fx_line,
28207 _("%s used for a symbol not defined in the same file"),
28208 bfd_get_reloc_code_name (fixp->fx_r_type));
28211 case BFD_RELOC_ARM_OFFSET_IMM:
28212 if (section->use_rela_p)
28214 code = fixp->fx_r_type;
28218 if (fixp->fx_addsy != NULL
28219 && !S_IS_DEFINED (fixp->fx_addsy)
28220 && S_IS_LOCAL (fixp->fx_addsy))
28222 as_bad_where (fixp->fx_file, fixp->fx_line,
28223 _("undefined local label `%s'"),
28224 S_GET_NAME (fixp->fx_addsy));
28228 as_bad_where (fixp->fx_file, fixp->fx_line,
28229 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28236 switch (fixp->fx_r_type)
28238 case BFD_RELOC_NONE: type = "NONE"; break;
28239 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
28240 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
28241 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
28242 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
28243 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
28244 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
28245 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
28246 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
28247 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
28248 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
28249 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
28250 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
28251 default: type = _("<unknown>"); break;
28253 as_bad_where (fixp->fx_file, fixp->fx_line,
28254 _("cannot represent %s relocation in this object file format"),
28261 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
28263 && fixp->fx_addsy == GOT_symbol)
28265 code = BFD_RELOC_ARM_GOTPC;
28266 reloc->addend = fixp->fx_offset = reloc->address;
28270 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
28272 if (reloc->howto == NULL)
28274 as_bad_where (fixp->fx_file, fixp->fx_line,
28275 _("cannot represent %s relocation in this object file format"),
28276 bfd_get_reloc_code_name (code));
28280 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28281 vtable entry to be used in the relocation's section offset. */
28282 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
28283 reloc->address = fixp->fx_offset;
28288 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28291 cons_fix_new_arm (fragS * frag,
28295 bfd_reloc_code_real_type reloc)
28300 FIXME: @@ Should look at CPU word size. */
28304 reloc = BFD_RELOC_8;
28307 reloc = BFD_RELOC_16;
28311 reloc = BFD_RELOC_32;
28314 reloc = BFD_RELOC_64;
28319 if (exp->X_op == O_secrel)
28321 exp->X_op = O_symbol;
28322 reloc = BFD_RELOC_32_SECREL;
28326 fix_new_exp (frag, where, size, exp, pcrel, reloc);
28329 #if defined (OBJ_COFF)
28331 arm_validate_fix (fixS * fixP)
28333 /* If the destination of the branch is a defined symbol which does not have
28334 the THUMB_FUNC attribute, then we must be calling a function which has
28335 the (interfacearm) attribute. We look for the Thumb entry point to that
28336 function and change the branch to refer to that function instead. */
28337 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
28338 && fixP->fx_addsy != NULL
28339 && S_IS_DEFINED (fixP->fx_addsy)
28340 && ! THUMB_IS_FUNC (fixP->fx_addsy))
28342 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
28349 arm_force_relocation (struct fix * fixp)
28351 #if defined (OBJ_COFF) && defined (TE_PE)
28352 if (fixp->fx_r_type == BFD_RELOC_RVA)
28356 /* In case we have a call or a branch to a function in ARM ISA mode from
28357 a thumb function or vice-versa force the relocation. These relocations
28358 are cleared off for some cores that might have blx and simple transformations
28362 switch (fixp->fx_r_type)
28364 case BFD_RELOC_ARM_PCREL_JUMP:
28365 case BFD_RELOC_ARM_PCREL_CALL:
28366 case BFD_RELOC_THUMB_PCREL_BLX:
28367 if (THUMB_IS_FUNC (fixp->fx_addsy))
28371 case BFD_RELOC_ARM_PCREL_BLX:
28372 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28373 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28374 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28375 if (ARM_IS_FUNC (fixp->fx_addsy))
28384 /* Resolve these relocations even if the symbol is extern or weak.
28385 Technically this is probably wrong due to symbol preemption.
28386 In practice these relocations do not have enough range to be useful
28387 at dynamic link time, and some code (e.g. in the Linux kernel)
28388 expects these references to be resolved. */
28389 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
28390 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
28391 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
28392 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
28393 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28394 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
28395 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
28396 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
28397 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
28398 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
28399 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
28400 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
28401 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
28402 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
28405 /* Always leave these relocations for the linker. */
28406 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
28407 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
28408 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
28411 /* Always generate relocations against function symbols. */
28412 if (fixp->fx_r_type == BFD_RELOC_32
28414 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
28417 return generic_force_reloc (fixp);
28420 #if defined (OBJ_ELF) || defined (OBJ_COFF)
28421 /* Relocations against function names must be left unadjusted,
28422 so that the linker can use this information to generate interworking
28423 stubs. The MIPS version of this function
28424 also prevents relocations that are mips-16 specific, but I do not
28425 know why it does this.
28428 There is one other problem that ought to be addressed here, but
28429 which currently is not: Taking the address of a label (rather
28430 than a function) and then later jumping to that address. Such
28431 addresses also ought to have their bottom bit set (assuming that
28432 they reside in Thumb code), but at the moment they will not. */
28435 arm_fix_adjustable (fixS * fixP)
28437 if (fixP->fx_addsy == NULL)
28440 /* Preserve relocations against symbols with function type. */
28441 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
28444 if (THUMB_IS_FUNC (fixP->fx_addsy)
28445 && fixP->fx_subsy == NULL)
28448 /* We need the symbol name for the VTABLE entries. */
28449 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
28450 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
28453 /* Don't allow symbols to be discarded on GOT related relocs. */
28454 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
28455 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
28456 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
28457 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
28458 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
28459 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
28460 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
28461 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
28462 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
28463 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
28464 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
28465 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
28466 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
28467 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
28468 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
28469 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
28470 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
28473 /* Similarly for group relocations. */
28474 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
28475 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
28476 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
28479 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28480 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
28481 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28482 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
28483 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
28484 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28485 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
28486 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
28487 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
28490 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28491 offsets, so keep these symbols. */
28492 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28493 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
28498 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
28502 elf32_arm_target_format (void)
28505 return (target_big_endian
28506 ? "elf32-bigarm-symbian"
28507 : "elf32-littlearm-symbian");
28508 #elif defined (TE_VXWORKS)
28509 return (target_big_endian
28510 ? "elf32-bigarm-vxworks"
28511 : "elf32-littlearm-vxworks");
28512 #elif defined (TE_NACL)
28513 return (target_big_endian
28514 ? "elf32-bigarm-nacl"
28515 : "elf32-littlearm-nacl");
28519 if (target_big_endian)
28520 return "elf32-bigarm-fdpic";
28522 return "elf32-littlearm-fdpic";
28526 if (target_big_endian)
28527 return "elf32-bigarm";
28529 return "elf32-littlearm";
28535 armelf_frob_symbol (symbolS * symp,
28538 elf_frob_symbol (symp, puntp);
28542 /* MD interface: Finalization. */
28547 literal_pool * pool;
28549 /* Ensure that all the predication blocks are properly closed. */
28550 check_pred_blocks_finished ();
28552 for (pool = list_of_pools; pool; pool = pool->next)
28554 /* Put it at the end of the relevant section. */
28555 subseg_set (pool->section, pool->sub_section);
28557 arm_elf_change_section ();
28564 /* Remove any excess mapping symbols generated for alignment frags in
28565 SEC. We may have created a mapping symbol before a zero byte
28566 alignment; remove it if there's a mapping symbol after the
28569 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
28570 void *dummy ATTRIBUTE_UNUSED)
28572 segment_info_type *seginfo = seg_info (sec);
28575 if (seginfo == NULL || seginfo->frchainP == NULL)
28578 for (fragp = seginfo->frchainP->frch_root;
28580 fragp = fragp->fr_next)
28582 symbolS *sym = fragp->tc_frag_data.last_map;
28583 fragS *next = fragp->fr_next;
28585 /* Variable-sized frags have been converted to fixed size by
28586 this point. But if this was variable-sized to start with,
28587 there will be a fixed-size frag after it. So don't handle
28589 if (sym == NULL || next == NULL)
28592 if (S_GET_VALUE (sym) < next->fr_address)
28593 /* Not at the end of this frag. */
28595 know (S_GET_VALUE (sym) == next->fr_address);
28599 if (next->tc_frag_data.first_map != NULL)
28601 /* Next frag starts with a mapping symbol. Discard this
28603 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
28607 if (next->fr_next == NULL)
28609 /* This mapping symbol is at the end of the section. Discard
28611 know (next->fr_fix == 0 && next->fr_var == 0);
28612 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
28616 /* As long as we have empty frags without any mapping symbols,
28618 /* If the next frag is non-empty and does not start with a
28619 mapping symbol, then this mapping symbol is required. */
28620 if (next->fr_address != next->fr_next->fr_address)
28623 next = next->fr_next;
28625 while (next != NULL);
28630 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28634 arm_adjust_symtab (void)
28639 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
28641 if (ARM_IS_THUMB (sym))
28643 if (THUMB_IS_FUNC (sym))
28645 /* Mark the symbol as a Thumb function. */
28646 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
28647 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
28648 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
28650 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
28651 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
28653 as_bad (_("%s: unexpected function type: %d"),
28654 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
28656 else switch (S_GET_STORAGE_CLASS (sym))
28659 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
28662 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
28665 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
28673 if (ARM_IS_INTERWORK (sym))
28674 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
28681 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
28683 if (ARM_IS_THUMB (sym))
28685 elf_symbol_type * elf_sym;
28687 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
28688 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
28690 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
28691 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
28693 /* If it's a .thumb_func, declare it as so,
28694 otherwise tag label as .code 16. */
28695 if (THUMB_IS_FUNC (sym))
28696 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
28697 ST_BRANCH_TO_THUMB);
28698 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
28699 elf_sym->internal_elf_sym.st_info =
28700 ELF_ST_INFO (bind, STT_ARM_16BIT);
28705 /* Remove any overlapping mapping symbols generated by alignment frags. */
28706 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
28707 /* Now do generic ELF adjustments. */
28708 elf_adjust_symtab ();
28712 /* MD interface: Initialization. */
28715 set_constant_flonums (void)
28719 for (i = 0; i < NUM_FLOAT_VALS; i++)
28720 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
28724 /* Auto-select Thumb mode if it's the only available instruction set for the
28725 given architecture. */
28728 autoselect_thumb_from_cpu_variant (void)
28730 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
28731 opcode_select (16);
28740 if ( (arm_ops_hsh = hash_new ()) == NULL
28741 || (arm_cond_hsh = hash_new ()) == NULL
28742 || (arm_vcond_hsh = hash_new ()) == NULL
28743 || (arm_shift_hsh = hash_new ()) == NULL
28744 || (arm_psr_hsh = hash_new ()) == NULL
28745 || (arm_v7m_psr_hsh = hash_new ()) == NULL
28746 || (arm_reg_hsh = hash_new ()) == NULL
28747 || (arm_reloc_hsh = hash_new ()) == NULL
28748 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
28749 as_fatal (_("virtual memory exhausted"));
28751 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
28752 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
28753 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
28754 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
28755 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
28756 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
28757 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
28758 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
28759 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
28760 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
28761 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
28762 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
28763 (void *) (v7m_psrs + i));
28764 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
28765 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
28767 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
28769 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
28770 (void *) (barrier_opt_names + i));
28772 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
28774 struct reloc_entry * entry = reloc_names + i;
28776 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
28777 /* This makes encode_branch() use the EABI versions of this relocation. */
28778 entry->reloc = BFD_RELOC_UNUSED;
28780 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
28784 set_constant_flonums ();
28786 /* Set the cpu variant based on the command-line options. We prefer
28787 -mcpu= over -march= if both are set (as for GCC); and we prefer
28788 -mfpu= over any other way of setting the floating point unit.
28789 Use of legacy options with new options are faulted. */
28792 if (mcpu_cpu_opt || march_cpu_opt)
28793 as_bad (_("use of old and new-style options to set CPU type"));
28795 selected_arch = *legacy_cpu;
28797 else if (mcpu_cpu_opt)
28799 selected_arch = *mcpu_cpu_opt;
28800 selected_ext = *mcpu_ext_opt;
28802 else if (march_cpu_opt)
28804 selected_arch = *march_cpu_opt;
28805 selected_ext = *march_ext_opt;
28807 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
28812 as_bad (_("use of old and new-style options to set FPU type"));
28814 selected_fpu = *legacy_fpu;
28817 selected_fpu = *mfpu_opt;
28820 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28821 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28822 /* Some environments specify a default FPU. If they don't, infer it
28823 from the processor. */
28825 selected_fpu = *mcpu_fpu_opt;
28826 else if (march_fpu_opt)
28827 selected_fpu = *march_fpu_opt;
28829 selected_fpu = fpu_default;
28833 if (ARM_FEATURE_ZERO (selected_fpu))
28835 if (!no_cpu_selected ())
28836 selected_fpu = fpu_default;
28838 selected_fpu = fpu_arch_fpa;
28842 if (ARM_FEATURE_ZERO (selected_arch))
28844 selected_arch = cpu_default;
28845 selected_cpu = selected_arch;
28847 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
28849 /* Autodection of feature mode: allow all features in cpu_variant but leave
28850 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28851 after all instruction have been processed and we can decide what CPU
28852 should be selected. */
28853 if (ARM_FEATURE_ZERO (selected_arch))
28854 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
28856 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
28859 autoselect_thumb_from_cpu_variant ();
28861 arm_arch_used = thumb_arch_used = arm_arch_none;
28863 #if defined OBJ_COFF || defined OBJ_ELF
28865 unsigned int flags = 0;
28867 #if defined OBJ_ELF
28868 flags = meabi_flags;
28870 switch (meabi_flags)
28872 case EF_ARM_EABI_UNKNOWN:
28874 /* Set the flags in the private structure. */
28875 if (uses_apcs_26) flags |= F_APCS26;
28876 if (support_interwork) flags |= F_INTERWORK;
28877 if (uses_apcs_float) flags |= F_APCS_FLOAT;
28878 if (pic_code) flags |= F_PIC;
28879 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
28880 flags |= F_SOFT_FLOAT;
28882 switch (mfloat_abi_opt)
28884 case ARM_FLOAT_ABI_SOFT:
28885 case ARM_FLOAT_ABI_SOFTFP:
28886 flags |= F_SOFT_FLOAT;
28889 case ARM_FLOAT_ABI_HARD:
28890 if (flags & F_SOFT_FLOAT)
28891 as_bad (_("hard-float conflicts with specified fpu"));
28895 /* Using pure-endian doubles (even if soft-float). */
28896 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
28897 flags |= F_VFP_FLOAT;
28899 #if defined OBJ_ELF
28900 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
28901 flags |= EF_ARM_MAVERICK_FLOAT;
28904 case EF_ARM_EABI_VER4:
28905 case EF_ARM_EABI_VER5:
28906 /* No additional flags to set. */
28913 bfd_set_private_flags (stdoutput, flags);
28915 /* We have run out flags in the COFF header to encode the
28916 status of ATPCS support, so instead we create a dummy,
28917 empty, debug section called .arm.atpcs. */
28922 sec = bfd_make_section (stdoutput, ".arm.atpcs");
28926 bfd_set_section_flags
28927 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
28928 bfd_set_section_size (stdoutput, sec, 0);
28929 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
28935 /* Record the CPU type as well. */
28936 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
28937 mach = bfd_mach_arm_iWMMXt2;
28938 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
28939 mach = bfd_mach_arm_iWMMXt;
28940 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
28941 mach = bfd_mach_arm_XScale;
28942 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
28943 mach = bfd_mach_arm_ep9312;
28944 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
28945 mach = bfd_mach_arm_5TE;
28946 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
28948 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
28949 mach = bfd_mach_arm_5T;
28951 mach = bfd_mach_arm_5;
28953 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
28955 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
28956 mach = bfd_mach_arm_4T;
28958 mach = bfd_mach_arm_4;
28960 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
28961 mach = bfd_mach_arm_3M;
28962 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
28963 mach = bfd_mach_arm_3;
28964 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
28965 mach = bfd_mach_arm_2a;
28966 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
28967 mach = bfd_mach_arm_2;
28969 mach = bfd_mach_arm_unknown;
28971 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
28974 /* Command line processing. */
28977 Invocation line includes a switch not recognized by the base assembler.
28978 See if it's a processor-specific option.
28980 This routine is somewhat complicated by the need for backwards
28981 compatibility (since older releases of gcc can't be changed).
28982 The new options try to make the interface as compatible as
28985 New options (supported) are:
28987 -mcpu=<cpu name> Assemble for selected processor
28988 -march=<architecture name> Assemble for selected architecture
28989 -mfpu=<fpu architecture> Assemble for selected FPU.
28990 -EB/-mbig-endian Big-endian
28991 -EL/-mlittle-endian Little-endian
28992 -k Generate PIC code
28993 -mthumb Start in Thumb mode
28994 -mthumb-interwork Code supports ARM/Thumb interworking
28996 -m[no-]warn-deprecated Warn about deprecated features
28997 -m[no-]warn-syms Warn when symbols match instructions
28999 For now we will also provide support for:
29001 -mapcs-32 32-bit Program counter
29002 -mapcs-26 26-bit Program counter
29003 -macps-float Floats passed in FP registers
29004 -mapcs-reentrant Reentrant code
29006 (sometime these will probably be replaced with -mapcs=<list of options>
29007 and -matpcs=<list of options>)
29009 The remaining options are only supported for back-wards compatibility.
29010 Cpu variants, the arm part is optional:
29011 -m[arm]1 Currently not supported.
29012 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29013 -m[arm]3 Arm 3 processor
29014 -m[arm]6[xx], Arm 6 processors
29015 -m[arm]7[xx][t][[d]m] Arm 7 processors
29016 -m[arm]8[10] Arm 8 processors
29017 -m[arm]9[20][tdmi] Arm 9 processors
29018 -mstrongarm[110[0]] StrongARM processors
29019 -mxscale XScale processors
29020 -m[arm]v[2345[t[e]]] Arm architectures
29021 -mall All (except the ARM1)
29023 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29024 -mfpe-old (No float load/store multiples)
29025 -mvfpxd VFP Single precision
29027 -mno-fpu Disable all floating point instructions
29029 The following CPU names are recognized:
29030 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29031 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29032 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29033 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29034 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29035 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29036 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29040 const char * md_shortopts = "m:k";
29042 #ifdef ARM_BI_ENDIAN
29043 #define OPTION_EB (OPTION_MD_BASE + 0)
29044 #define OPTION_EL (OPTION_MD_BASE + 1)
29046 #if TARGET_BYTES_BIG_ENDIAN
29047 #define OPTION_EB (OPTION_MD_BASE + 0)
29049 #define OPTION_EL (OPTION_MD_BASE + 1)
29052 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29053 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29055 struct option md_longopts[] =
29058 {"EB", no_argument, NULL, OPTION_EB},
29061 {"EL", no_argument, NULL, OPTION_EL},
29063 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
29065 {"fdpic", no_argument, NULL, OPTION_FDPIC},
29067 {NULL, no_argument, NULL, 0}
29070 size_t md_longopts_size = sizeof (md_longopts);
29072 struct arm_option_table
29074 const char * option; /* Option name to match. */
29075 const char * help; /* Help information. */
29076 int * var; /* Variable to change. */
29077 int value; /* What to change it to. */
29078 const char * deprecated; /* If non-null, print this message. */
29081 struct arm_option_table arm_opts[] =
29083 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
29084 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
29085 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29086 &support_interwork, 1, NULL},
29087 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
29088 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
29089 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
29091 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
29092 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
29093 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
29094 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
29097 /* These are recognized by the assembler, but have no affect on code. */
29098 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
29099 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
29101 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
29102 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29103 &warn_on_deprecated, 0, NULL},
29104 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
29105 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
29106 {NULL, NULL, NULL, 0, NULL}
29109 struct arm_legacy_option_table
29111 const char * option; /* Option name to match. */
29112 const arm_feature_set ** var; /* Variable to change. */
29113 const arm_feature_set value; /* What to change it to. */
29114 const char * deprecated; /* If non-null, print this message. */
29117 const struct arm_legacy_option_table arm_legacy_opts[] =
29119 /* DON'T add any new processors to this list -- we want the whole list
29120 to go away... Add them to the processors table instead. */
29121 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29122 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29123 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29124 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29125 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29126 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29127 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29128 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29129 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29130 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29131 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29132 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29133 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29134 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29135 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29136 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29137 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29138 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29139 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29140 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29141 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29142 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29143 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29144 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29145 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29146 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29147 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29148 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29149 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29150 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29151 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29152 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29153 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29154 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29155 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29156 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29157 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29158 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29159 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29160 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29161 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29162 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29163 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29164 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29165 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29166 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29167 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29168 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29169 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29170 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29171 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29172 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29173 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29174 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29175 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29176 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29177 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29178 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29179 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29180 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29181 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29182 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29183 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29184 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29185 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29186 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29187 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29188 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29189 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
29190 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
29191 N_("use -mcpu=strongarm110")},
29192 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
29193 N_("use -mcpu=strongarm1100")},
29194 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
29195 N_("use -mcpu=strongarm1110")},
29196 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
29197 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
29198 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
29200 /* Architecture variants -- don't add any more to this list either. */
29201 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29202 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29203 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29204 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29205 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29206 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29207 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29208 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29209 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29210 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29211 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29212 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29213 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29214 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29215 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29216 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29217 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29218 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29220 /* Floating point variants -- don't add any more to this list either. */
29221 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
29222 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
29223 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
29224 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
29225 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29227 {NULL, NULL, ARM_ARCH_NONE, NULL}
29230 struct arm_cpu_option_table
29234 const arm_feature_set value;
29235 const arm_feature_set ext;
29236 /* For some CPUs we assume an FPU unless the user explicitly sets
29238 const arm_feature_set default_fpu;
29239 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29241 const char * canonical_name;
29244 /* This list should, at a minimum, contain all the cpu names
29245 recognized by GCC. */
29246 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29248 static const struct arm_cpu_option_table arm_cpus[] =
29250 ARM_CPU_OPT ("all", NULL, ARM_ANY,
29253 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
29256 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
29259 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
29262 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
29265 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
29268 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
29271 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
29274 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
29277 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
29280 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
29283 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
29286 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
29289 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
29292 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
29295 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
29298 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
29301 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
29304 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
29307 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
29310 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
29313 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
29316 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
29319 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
29322 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
29325 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
29328 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
29331 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
29334 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
29337 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
29340 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
29343 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
29346 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
29349 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
29352 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
29355 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
29358 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
29361 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
29364 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
29367 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
29370 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
29373 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
29376 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
29379 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
29382 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
29385 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
29389 /* For V5 or later processors we default to using VFP; but the user
29390 should really set the FPU type explicitly. */
29391 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
29394 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
29397 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
29400 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
29403 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
29406 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
29409 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
29412 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
29415 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
29418 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
29421 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
29424 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
29427 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
29430 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
29433 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
29436 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
29439 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
29442 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
29445 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
29448 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
29451 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
29454 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
29457 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
29460 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
29463 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
29466 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
29469 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
29472 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
29475 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
29478 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
29481 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
29484 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
29487 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
29490 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
29493 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
29496 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
29499 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
29500 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29502 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
29504 FPU_ARCH_NEON_VFP_V4),
29505 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
29506 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
29507 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
29508 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
29509 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29510 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
29511 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
29513 FPU_ARCH_NEON_VFP_V4),
29514 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
29516 FPU_ARCH_NEON_VFP_V4),
29517 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
29519 FPU_ARCH_NEON_VFP_V4),
29520 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
29521 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29522 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29523 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
29524 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29525 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29526 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
29527 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29528 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29529 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
29530 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29531 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29532 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
29533 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29534 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29535 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
29536 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29537 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29538 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
29539 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29540 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29541 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
29542 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29543 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29544 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
29545 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29546 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29547 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
29548 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29549 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29550 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
29553 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
29555 FPU_ARCH_VFP_V3D16),
29556 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
29557 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29559 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
29560 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29561 FPU_ARCH_VFP_V3D16),
29562 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
29563 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
29564 FPU_ARCH_VFP_V3D16),
29565 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
29566 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29567 FPU_ARCH_NEON_VFP_ARMV8),
29568 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
29569 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29571 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
29574 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
29577 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
29580 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
29583 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
29586 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
29589 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
29592 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
29593 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29594 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29595 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
29596 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29597 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
29598 /* ??? XSCALE is really an architecture. */
29599 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
29603 /* ??? iwmmxt is not a processor. */
29604 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
29607 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
29610 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
29615 ARM_CPU_OPT ("ep9312", "ARM920T",
29616 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
29617 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
29619 /* Marvell processors. */
29620 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
29621 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29622 FPU_ARCH_VFP_V3D16),
29623 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
29624 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
29625 FPU_ARCH_NEON_VFP_V4),
29627 /* APM X-Gene family. */
29628 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
29630 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29631 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
29632 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29633 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
29635 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
29639 struct arm_ext_table
29643 const arm_feature_set merge;
29644 const arm_feature_set clear;
29647 struct arm_arch_option_table
29651 const arm_feature_set value;
29652 const arm_feature_set default_fpu;
29653 const struct arm_ext_table * ext_table;
29656 /* Used to add support for +E and +noE extension. */
29657 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29658 /* Used to add support for a +E extension. */
29659 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29660 /* Used to add support for a +noE extension. */
29661 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29663 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29664 ~0 & ~FPU_ENDIAN_PURE)
29666 static const struct arm_ext_table armv5te_ext_table[] =
29668 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
29669 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29672 static const struct arm_ext_table armv7_ext_table[] =
29674 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29675 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29678 static const struct arm_ext_table armv7ve_ext_table[] =
29680 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
29681 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
29682 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
29683 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29684 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
29685 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
29686 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
29688 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
29689 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
29691 /* Aliases for +simd. */
29692 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
29694 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29695 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29696 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
29698 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29701 static const struct arm_ext_table armv7a_ext_table[] =
29703 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29704 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
29705 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
29706 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29707 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
29708 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
29709 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
29711 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
29712 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
29714 /* Aliases for +simd. */
29715 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29716 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
29718 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
29719 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
29721 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
29722 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
29723 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29726 static const struct arm_ext_table armv7r_ext_table[] =
29728 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
29729 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
29730 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
29731 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
29732 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
29733 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
29734 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
29735 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
29736 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29739 static const struct arm_ext_table armv7em_ext_table[] =
29741 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
29742 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29743 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
29744 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
29745 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
29746 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
29747 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29750 static const struct arm_ext_table armv8a_ext_table[] =
29752 ARM_ADD ("crc", ARCH_CRC_ARMV8),
29753 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
29754 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
29755 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29757 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29758 should use the +simd option to turn on FP. */
29759 ARM_REMOVE ("fp", ALL_FP),
29760 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29761 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29762 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29766 static const struct arm_ext_table armv81a_ext_table[] =
29768 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
29769 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
29770 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29772 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29773 should use the +simd option to turn on FP. */
29774 ARM_REMOVE ("fp", ALL_FP),
29775 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29776 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29777 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29780 static const struct arm_ext_table armv82a_ext_table[] =
29782 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
29783 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
29784 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
29785 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
29786 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29787 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29789 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29790 should use the +simd option to turn on FP. */
29791 ARM_REMOVE ("fp", ALL_FP),
29792 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29793 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29794 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29797 static const struct arm_ext_table armv84a_ext_table[] =
29799 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29800 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
29801 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
29802 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29804 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29805 should use the +simd option to turn on FP. */
29806 ARM_REMOVE ("fp", ALL_FP),
29807 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
29808 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
29809 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29812 static const struct arm_ext_table armv85a_ext_table[] =
29814 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
29815 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
29816 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
29817 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29819 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29820 should use the +simd option to turn on FP. */
29821 ARM_REMOVE ("fp", ALL_FP),
29822 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29825 static const struct arm_ext_table armv8m_main_ext_table[] =
29827 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29828 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
29829 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
29830 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
29831 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29834 static const struct arm_ext_table armv8_1m_main_ext_table[] =
29836 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29837 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
29839 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29840 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
29843 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29844 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
29845 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
29846 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
29848 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
29849 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
29850 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
29851 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29854 static const struct arm_ext_table armv8r_ext_table[] =
29856 ARM_ADD ("crc", ARCH_CRC_ARMV8),
29857 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
29858 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
29859 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
29860 ARM_REMOVE ("fp", ALL_FP),
29861 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
29862 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
29865 /* This list should, at a minimum, contain all the architecture names
29866 recognized by GCC. */
29867 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29868 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29869 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29871 static const struct arm_arch_option_table arm_archs[] =
29873 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
29874 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
29875 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
29876 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
29877 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
29878 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
29879 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
29880 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
29881 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
29882 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
29883 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
29884 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
29885 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
29886 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
29887 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
29888 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
29889 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
29890 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
29891 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
29892 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
29893 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
29894 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29895 kept to preserve existing behaviour. */
29896 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
29897 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
29898 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
29899 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
29900 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
29901 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29902 kept to preserve existing behaviour. */
29903 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
29904 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
29905 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
29906 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
29907 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
29908 /* The official spelling of the ARMv7 profile variants is the dashed form.
29909 Accept the non-dashed form for compatibility with old toolchains. */
29910 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
29911 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
29912 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
29913 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
29914 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
29915 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
29916 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
29917 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
29918 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
29919 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
29921 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
29923 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
29924 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
29925 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
29926 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
29927 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
29928 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
29929 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
29930 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
29931 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
29932 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
29933 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
29935 #undef ARM_ARCH_OPT
29937 /* ISA extensions in the co-processor and main instruction set space. */
29939 struct arm_option_extension_value_table
29943 const arm_feature_set merge_value;
29944 const arm_feature_set clear_value;
29945 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29946 indicates that an extension is available for all architectures while
29947 ARM_ANY marks an empty entry. */
29948 const arm_feature_set allowed_archs[2];
29951 /* The following table must be in alphabetical order with a NULL last entry. */
29953 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29954 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29956 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29957 use the context sensitive approach using arm_ext_table's. */
29958 static const struct arm_option_extension_value_table arm_extensions[] =
29960 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
29961 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
29962 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
29963 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
29964 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
29965 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
29966 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
29968 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29969 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
29970 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
29971 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
29972 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
29973 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29974 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
29976 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29977 | ARM_EXT2_FP16_FML),
29978 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29979 | ARM_EXT2_FP16_FML),
29981 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
29982 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
29983 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
29984 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
29985 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29986 Thumb divide instruction. Due to this having the same name as the
29987 previous entry, this will be ignored when doing command-line parsing and
29988 only considered by build attribute selection code. */
29989 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
29990 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
29991 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
29992 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
29993 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
29994 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
29995 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
29996 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
29997 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
29998 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
29999 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
30000 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30001 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
30002 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30003 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30004 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
30005 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
30006 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
30007 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30008 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30009 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30011 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
30012 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
30013 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30014 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
30015 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
30016 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30017 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30018 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30020 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30021 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30022 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
30023 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30024 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
30025 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
30026 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30027 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
30029 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
30030 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30031 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
30032 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
30033 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
30037 /* ISA floating-point and Advanced SIMD extensions. */
30038 struct arm_option_fpu_value_table
30041 const arm_feature_set value;
30044 /* This list should, at a minimum, contain all the fpu names
30045 recognized by GCC. */
30046 static const struct arm_option_fpu_value_table arm_fpus[] =
30048 {"softfpa", FPU_NONE},
30049 {"fpe", FPU_ARCH_FPE},
30050 {"fpe2", FPU_ARCH_FPE},
30051 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
30052 {"fpa", FPU_ARCH_FPA},
30053 {"fpa10", FPU_ARCH_FPA},
30054 {"fpa11", FPU_ARCH_FPA},
30055 {"arm7500fe", FPU_ARCH_FPA},
30056 {"softvfp", FPU_ARCH_VFP},
30057 {"softvfp+vfp", FPU_ARCH_VFP_V2},
30058 {"vfp", FPU_ARCH_VFP_V2},
30059 {"vfp9", FPU_ARCH_VFP_V2},
30060 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
30061 {"vfp10", FPU_ARCH_VFP_V2},
30062 {"vfp10-r0", FPU_ARCH_VFP_V1},
30063 {"vfpxd", FPU_ARCH_VFP_V1xD},
30064 {"vfpv2", FPU_ARCH_VFP_V2},
30065 {"vfpv3", FPU_ARCH_VFP_V3},
30066 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
30067 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
30068 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
30069 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
30070 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
30071 {"arm1020t", FPU_ARCH_VFP_V1},
30072 {"arm1020e", FPU_ARCH_VFP_V2},
30073 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
30074 {"arm1136jf-s", FPU_ARCH_VFP_V2},
30075 {"maverick", FPU_ARCH_MAVERICK},
30076 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30077 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30078 {"neon-fp16", FPU_ARCH_NEON_FP16},
30079 {"vfpv4", FPU_ARCH_VFP_V4},
30080 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
30081 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
30082 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
30083 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
30084 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
30085 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
30086 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
30087 {"crypto-neon-fp-armv8",
30088 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
30089 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
30090 {"crypto-neon-fp-armv8.1",
30091 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
30092 {NULL, ARM_ARCH_NONE}
30095 struct arm_option_value_table
30101 static const struct arm_option_value_table arm_float_abis[] =
30103 {"hard", ARM_FLOAT_ABI_HARD},
30104 {"softfp", ARM_FLOAT_ABI_SOFTFP},
30105 {"soft", ARM_FLOAT_ABI_SOFT},
30110 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30111 static const struct arm_option_value_table arm_eabis[] =
30113 {"gnu", EF_ARM_EABI_UNKNOWN},
30114 {"4", EF_ARM_EABI_VER4},
30115 {"5", EF_ARM_EABI_VER5},
30120 struct arm_long_option_table
30122 const char * option; /* Substring to match. */
30123 const char * help; /* Help information. */
30124 int (* func) (const char * subopt); /* Function to decode sub-option. */
30125 const char * deprecated; /* If non-null, print this message. */
30129 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
30130 arm_feature_set *ext_set,
30131 const struct arm_ext_table *ext_table)
30133 /* We insist on extensions being specified in alphabetical order, and with
30134 extensions being added before being removed. We achieve this by having
30135 the global ARM_EXTENSIONS table in alphabetical order, and using the
30136 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30137 or removing it (0) and only allowing it to change in the order
30139 const struct arm_option_extension_value_table * opt = NULL;
30140 const arm_feature_set arm_any = ARM_ANY;
30141 int adding_value = -1;
30143 while (str != NULL && *str != 0)
30150 as_bad (_("invalid architectural extension"));
30155 ext = strchr (str, '+');
30160 len = strlen (str);
30162 if (len >= 2 && strncmp (str, "no", 2) == 0)
30164 if (adding_value != 0)
30167 opt = arm_extensions;
30175 if (adding_value == -1)
30178 opt = arm_extensions;
30180 else if (adding_value != 1)
30182 as_bad (_("must specify extensions to add before specifying "
30183 "those to remove"));
30190 as_bad (_("missing architectural extension"));
30194 gas_assert (adding_value != -1);
30195 gas_assert (opt != NULL);
30197 if (ext_table != NULL)
30199 const struct arm_ext_table * ext_opt = ext_table;
30200 bfd_boolean found = FALSE;
30201 for (; ext_opt->name != NULL; ext_opt++)
30202 if (ext_opt->name_len == len
30203 && strncmp (ext_opt->name, str, len) == 0)
30207 if (ARM_FEATURE_ZERO (ext_opt->merge))
30208 /* TODO: Option not supported. When we remove the
30209 legacy table this case should error out. */
30212 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
30216 if (ARM_FEATURE_ZERO (ext_opt->clear))
30217 /* TODO: Option not supported. When we remove the
30218 legacy table this case should error out. */
30220 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
30232 /* Scan over the options table trying to find an exact match. */
30233 for (; opt->name != NULL; opt++)
30234 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30236 int i, nb_allowed_archs =
30237 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
30238 /* Check we can apply the extension to this architecture. */
30239 for (i = 0; i < nb_allowed_archs; i++)
30242 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
30244 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
30247 if (i == nb_allowed_archs)
30249 as_bad (_("extension does not apply to the base architecture"));
30253 /* Add or remove the extension. */
30255 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
30257 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
30259 /* Allowing Thumb division instructions for ARMv7 in autodetection
30260 rely on this break so that duplicate extensions (extensions
30261 with the same name as a previous extension in the list) are not
30262 considered for command-line parsing. */
30266 if (opt->name == NULL)
30268 /* Did we fail to find an extension because it wasn't specified in
30269 alphabetical order, or because it does not exist? */
30271 for (opt = arm_extensions; opt->name != NULL; opt++)
30272 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30275 if (opt->name == NULL)
30276 as_bad (_("unknown architectural extension `%s'"), str);
30278 as_bad (_("architectural extensions must be specified in "
30279 "alphabetical order"));
30285 /* We should skip the extension we've just matched the next time
30297 arm_parse_cpu (const char *str)
30299 const struct arm_cpu_option_table *opt;
30300 const char *ext = strchr (str, '+');
30306 len = strlen (str);
30310 as_bad (_("missing cpu name `%s'"), str);
30314 for (opt = arm_cpus; opt->name != NULL; opt++)
30315 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30317 mcpu_cpu_opt = &opt->value;
30318 if (mcpu_ext_opt == NULL)
30319 mcpu_ext_opt = XNEW (arm_feature_set);
30320 *mcpu_ext_opt = opt->ext;
30321 mcpu_fpu_opt = &opt->default_fpu;
30322 if (opt->canonical_name)
30324 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
30325 strcpy (selected_cpu_name, opt->canonical_name);
30331 if (len >= sizeof selected_cpu_name)
30332 len = (sizeof selected_cpu_name) - 1;
30334 for (i = 0; i < len; i++)
30335 selected_cpu_name[i] = TOUPPER (opt->name[i]);
30336 selected_cpu_name[i] = 0;
30340 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
30345 as_bad (_("unknown cpu `%s'"), str);
30350 arm_parse_arch (const char *str)
30352 const struct arm_arch_option_table *opt;
30353 const char *ext = strchr (str, '+');
30359 len = strlen (str);
30363 as_bad (_("missing architecture name `%s'"), str);
30367 for (opt = arm_archs; opt->name != NULL; opt++)
30368 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30370 march_cpu_opt = &opt->value;
30371 if (march_ext_opt == NULL)
30372 march_ext_opt = XNEW (arm_feature_set);
30373 *march_ext_opt = arm_arch_none;
30374 march_fpu_opt = &opt->default_fpu;
30375 strcpy (selected_cpu_name, opt->name);
30378 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
30384 as_bad (_("unknown architecture `%s'\n"), str);
30389 arm_parse_fpu (const char * str)
30391 const struct arm_option_fpu_value_table * opt;
30393 for (opt = arm_fpus; opt->name != NULL; opt++)
30394 if (streq (opt->name, str))
30396 mfpu_opt = &opt->value;
30400 as_bad (_("unknown floating point format `%s'\n"), str);
30405 arm_parse_float_abi (const char * str)
30407 const struct arm_option_value_table * opt;
30409 for (opt = arm_float_abis; opt->name != NULL; opt++)
30410 if (streq (opt->name, str))
30412 mfloat_abi_opt = opt->value;
30416 as_bad (_("unknown floating point abi `%s'\n"), str);
30422 arm_parse_eabi (const char * str)
30424 const struct arm_option_value_table *opt;
30426 for (opt = arm_eabis; opt->name != NULL; opt++)
30427 if (streq (opt->name, str))
30429 meabi_flags = opt->value;
30432 as_bad (_("unknown EABI `%s'\n"), str);
30438 arm_parse_it_mode (const char * str)
30440 bfd_boolean ret = TRUE;
30442 if (streq ("arm", str))
30443 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
30444 else if (streq ("thumb", str))
30445 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
30446 else if (streq ("always", str))
30447 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
30448 else if (streq ("never", str))
30449 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
30452 as_bad (_("unknown implicit IT mode `%s', should be "\
30453 "arm, thumb, always, or never."), str);
30461 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
30463 codecomposer_syntax = TRUE;
30464 arm_comment_chars[0] = ';';
30465 arm_line_separator_chars[0] = 0;
30469 struct arm_long_option_table arm_long_opts[] =
30471 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30472 arm_parse_cpu, NULL},
30473 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30474 arm_parse_arch, NULL},
30475 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30476 arm_parse_fpu, NULL},
30477 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30478 arm_parse_float_abi, NULL},
30480 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30481 arm_parse_eabi, NULL},
30483 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30484 arm_parse_it_mode, NULL},
30485 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30486 arm_ccs_mode, NULL},
30487 {NULL, NULL, 0, NULL}
30491 md_parse_option (int c, const char * arg)
30493 struct arm_option_table *opt;
30494 const struct arm_legacy_option_table *fopt;
30495 struct arm_long_option_table *lopt;
30501 target_big_endian = 1;
30507 target_big_endian = 0;
30511 case OPTION_FIX_V4BX:
30519 #endif /* OBJ_ELF */
30522 /* Listing option. Just ignore these, we don't support additional
30527 for (opt = arm_opts; opt->option != NULL; opt++)
30529 if (c == opt->option[0]
30530 && ((arg == NULL && opt->option[1] == 0)
30531 || streq (arg, opt->option + 1)))
30533 /* If the option is deprecated, tell the user. */
30534 if (warn_on_deprecated && opt->deprecated != NULL)
30535 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
30536 arg ? arg : "", _(opt->deprecated));
30538 if (opt->var != NULL)
30539 *opt->var = opt->value;
30545 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
30547 if (c == fopt->option[0]
30548 && ((arg == NULL && fopt->option[1] == 0)
30549 || streq (arg, fopt->option + 1)))
30551 /* If the option is deprecated, tell the user. */
30552 if (warn_on_deprecated && fopt->deprecated != NULL)
30553 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
30554 arg ? arg : "", _(fopt->deprecated));
30556 if (fopt->var != NULL)
30557 *fopt->var = &fopt->value;
30563 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
30565 /* These options are expected to have an argument. */
30566 if (c == lopt->option[0]
30568 && strncmp (arg, lopt->option + 1,
30569 strlen (lopt->option + 1)) == 0)
30571 /* If the option is deprecated, tell the user. */
30572 if (warn_on_deprecated && lopt->deprecated != NULL)
30573 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
30574 _(lopt->deprecated));
30576 /* Call the sup-option parser. */
30577 return lopt->func (arg + strlen (lopt->option) - 1);
30588 md_show_usage (FILE * fp)
30590 struct arm_option_table *opt;
30591 struct arm_long_option_table *lopt;
30593 fprintf (fp, _(" ARM-specific assembler options:\n"));
30595 for (opt = arm_opts; opt->option != NULL; opt++)
30596 if (opt->help != NULL)
30597 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
30599 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
30600 if (lopt->help != NULL)
30601 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
30605 -EB assemble code for a big-endian cpu\n"));
30610 -EL assemble code for a little-endian cpu\n"));
30614 --fix-v4bx Allow BX in ARMv4 code\n"));
30618 --fdpic generate an FDPIC object file\n"));
30619 #endif /* OBJ_ELF */
30627 arm_feature_set flags;
30628 } cpu_arch_ver_table;
30630 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30631 chronologically for architectures, with an exception for ARMv6-M and
30632 ARMv6S-M due to legacy reasons. No new architecture should have a
30633 special case. This allows for build attribute selection results to be
30634 stable when new architectures are added. */
30635 static const cpu_arch_ver_table cpu_arch_ver[] =
30637 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
30638 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
30639 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
30640 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
30641 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
30642 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
30643 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
30644 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
30645 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
30646 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
30647 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
30648 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
30649 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
30650 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
30651 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
30652 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
30653 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
30654 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
30655 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
30656 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
30657 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
30658 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
30659 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
30660 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
30662 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30663 always selected build attributes to match those of ARMv6-M
30664 (resp. ARMv6S-M). However, due to these architectures being a strict
30665 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30666 would be selected when fully respecting chronology of architectures.
30667 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30668 move them before ARMv7 architectures. */
30669 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
30670 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
30672 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
30673 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
30674 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
30675 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
30676 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
30677 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
30678 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
30679 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
30680 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
30681 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
30682 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
30683 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
30684 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
30685 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
30686 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
30687 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
30688 {-1, ARM_ARCH_NONE}
30691 /* Set an attribute if it has not already been set by the user. */
30694 aeabi_set_attribute_int (int tag, int value)
30697 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
30698 || !attributes_set_explicitly[tag])
30699 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
30703 aeabi_set_attribute_string (int tag, const char *value)
30706 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
30707 || !attributes_set_explicitly[tag])
30708 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
30711 /* Return whether features in the *NEEDED feature set are available via
30712 extensions for the architecture whose feature set is *ARCH_FSET. */
30715 have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
30716 const arm_feature_set *needed)
30718 int i, nb_allowed_archs;
30719 arm_feature_set ext_fset;
30720 const struct arm_option_extension_value_table *opt;
30722 ext_fset = arm_arch_none;
30723 for (opt = arm_extensions; opt->name != NULL; opt++)
30725 /* Extension does not provide any feature we need. */
30726 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
30730 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
30731 for (i = 0; i < nb_allowed_archs; i++)
30734 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
30737 /* Extension is available, add it. */
30738 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
30739 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
30743 /* Can we enable all features in *needed? */
30744 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
30747 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30748 a given architecture feature set *ARCH_EXT_FSET including extension feature
30749 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30750 - if true, check for an exact match of the architecture modulo extensions;
30751 - otherwise, select build attribute value of the first superset
30752 architecture released so that results remains stable when new architectures
30754 For -march/-mcpu=all the build attribute value of the most featureful
30755 architecture is returned. Tag_CPU_arch_profile result is returned in
30759 get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
30760 const arm_feature_set *ext_fset,
30761 char *profile, int exact_match)
30763 arm_feature_set arch_fset;
30764 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
30766 /* Select most featureful architecture with all its extensions if building
30767 for -march=all as the feature sets used to set build attributes. */
30768 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
30770 /* Force revisiting of decision for each new architecture. */
30771 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
30773 return TAG_CPU_ARCH_V8;
30776 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
30778 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
30780 arm_feature_set known_arch_fset;
30782 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
30785 /* Base architecture match user-specified architecture and
30786 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30787 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
30792 /* Base architecture match user-specified architecture only
30793 (eg. ARMv6-M in the same case as above). Record it in case we
30794 find a match with above condition. */
30795 else if (p_ver_ret == NULL
30796 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
30802 /* Architecture has all features wanted. */
30803 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
30805 arm_feature_set added_fset;
30807 /* Compute features added by this architecture over the one
30808 recorded in p_ver_ret. */
30809 if (p_ver_ret != NULL)
30810 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
30812 /* First architecture that match incl. with extensions, or the
30813 only difference in features over the recorded match is
30814 features that were optional and are now mandatory. */
30815 if (p_ver_ret == NULL
30816 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
30822 else if (p_ver_ret == NULL)
30824 arm_feature_set needed_ext_fset;
30826 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
30828 /* Architecture has all features needed when using some
30829 extensions. Record it and continue searching in case there
30830 exist an architecture providing all needed features without
30831 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30833 if (have_ext_for_needed_feat_p (&known_arch_fset,
30840 if (p_ver_ret == NULL)
30844 /* Tag_CPU_arch_profile. */
30845 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
30846 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
30847 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
30848 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
30850 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
30852 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
30856 return p_ver_ret->val;
30859 /* Set the public EABI object attributes. */
30862 aeabi_set_public_attributes (void)
30864 char profile = '\0';
30867 int fp16_optional = 0;
30868 int skip_exact_match = 0;
30869 arm_feature_set flags, flags_arch, flags_ext;
30871 /* Autodetection mode, choose the architecture based the instructions
30873 if (no_cpu_selected ())
30875 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
30877 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
30878 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
30880 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
30881 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
30883 /* Code run during relaxation relies on selected_cpu being set. */
30884 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
30885 flags_ext = arm_arch_none;
30886 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
30887 selected_ext = flags_ext;
30888 selected_cpu = flags;
30890 /* Otherwise, choose the architecture based on the capabilities of the
30894 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
30895 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
30896 flags_ext = selected_ext;
30897 flags = selected_cpu;
30899 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
30901 /* Allow the user to override the reported architecture. */
30902 if (!ARM_FEATURE_ZERO (selected_object_arch))
30904 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
30905 flags_ext = arm_arch_none;
30908 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
30910 /* When this function is run again after relaxation has happened there is no
30911 way to determine whether an architecture or CPU was specified by the user:
30912 - selected_cpu is set above for relaxation to work;
30913 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30914 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30915 Therefore, if not in -march=all case we first try an exact match and fall
30916 back to autodetection. */
30917 if (!skip_exact_match)
30918 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
30920 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
30922 as_bad (_("no architecture contains all the instructions used\n"));
30924 /* Tag_CPU_name. */
30925 if (selected_cpu_name[0])
30929 q = selected_cpu_name;
30930 if (strncmp (q, "armv", 4) == 0)
30935 for (i = 0; q[i]; i++)
30936 q[i] = TOUPPER (q[i]);
30938 aeabi_set_attribute_string (Tag_CPU_name, q);
30941 /* Tag_CPU_arch. */
30942 aeabi_set_attribute_int (Tag_CPU_arch, arch);
30944 /* Tag_CPU_arch_profile. */
30945 if (profile != '\0')
30946 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
30948 /* Tag_DSP_extension. */
30949 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
30950 aeabi_set_attribute_int (Tag_DSP_extension, 1);
30952 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
30953 /* Tag_ARM_ISA_use. */
30954 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
30955 || ARM_FEATURE_ZERO (flags_arch))
30956 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
30958 /* Tag_THUMB_ISA_use. */
30959 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
30960 || ARM_FEATURE_ZERO (flags_arch))
30964 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
30965 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
30967 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
30971 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
30974 /* Tag_VFP_arch. */
30975 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
30976 aeabi_set_attribute_int (Tag_VFP_arch,
30977 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
30979 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
30980 aeabi_set_attribute_int (Tag_VFP_arch,
30981 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
30983 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
30986 aeabi_set_attribute_int (Tag_VFP_arch, 3);
30988 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
30990 aeabi_set_attribute_int (Tag_VFP_arch, 4);
30993 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
30994 aeabi_set_attribute_int (Tag_VFP_arch, 2);
30995 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
30996 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
30997 aeabi_set_attribute_int (Tag_VFP_arch, 1);
30999 /* Tag_ABI_HardFP_use. */
31000 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
31001 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
31002 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
31004 /* Tag_WMMX_arch. */
31005 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
31006 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
31007 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
31008 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
31010 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31011 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
31012 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
31013 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
31014 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
31015 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
31017 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
31019 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
31023 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
31028 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
31029 aeabi_set_attribute_int (Tag_MVE_arch, 2);
31030 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
31031 aeabi_set_attribute_int (Tag_MVE_arch, 1);
31033 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31034 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
31035 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
31039 We set Tag_DIV_use to two when integer divide instructions have been used
31040 in ARM state, or when Thumb integer divide instructions have been used,
31041 but we have no architecture profile set, nor have we any ARM instructions.
31043 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31044 by the base architecture.
31046 For new architectures we will have to check these tests. */
31047 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
31048 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31049 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
31050 aeabi_set_attribute_int (Tag_DIV_use, 0);
31051 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
31052 || (profile == '\0'
31053 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
31054 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
31055 aeabi_set_attribute_int (Tag_DIV_use, 2);
31057 /* Tag_MP_extension_use. */
31058 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
31059 aeabi_set_attribute_int (Tag_MPextension_use, 1);
31061 /* Tag Virtualization_use. */
31062 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
31064 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
31067 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
31070 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31071 finished and free extension feature bits which will not be used anymore. */
31074 arm_md_post_relax (void)
31076 aeabi_set_public_attributes ();
31077 XDELETE (mcpu_ext_opt);
31078 mcpu_ext_opt = NULL;
31079 XDELETE (march_ext_opt);
31080 march_ext_opt = NULL;
31083 /* Add the default contents for the .ARM.attributes section. */
31088 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
31091 aeabi_set_public_attributes ();
31093 #endif /* OBJ_ELF */
31095 /* Parse a .cpu directive. */
31098 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
31100 const struct arm_cpu_option_table *opt;
31104 name = input_line_pointer;
31105 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31106 input_line_pointer++;
31107 saved_char = *input_line_pointer;
31108 *input_line_pointer = 0;
31110 /* Skip the first "all" entry. */
31111 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
31112 if (streq (opt->name, name))
31114 selected_arch = opt->value;
31115 selected_ext = opt->ext;
31116 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31117 if (opt->canonical_name)
31118 strcpy (selected_cpu_name, opt->canonical_name);
31122 for (i = 0; opt->name[i]; i++)
31123 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31125 selected_cpu_name[i] = 0;
31127 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31129 *input_line_pointer = saved_char;
31130 demand_empty_rest_of_line ();
31133 as_bad (_("unknown cpu `%s'"), name);
31134 *input_line_pointer = saved_char;
31135 ignore_rest_of_line ();
31138 /* Parse a .arch directive. */
31141 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
31143 const struct arm_arch_option_table *opt;
31147 name = input_line_pointer;
31148 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31149 input_line_pointer++;
31150 saved_char = *input_line_pointer;
31151 *input_line_pointer = 0;
31153 /* Skip the first "all" entry. */
31154 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31155 if (streq (opt->name, name))
31157 selected_arch = opt->value;
31158 selected_ext = arm_arch_none;
31159 selected_cpu = selected_arch;
31160 strcpy (selected_cpu_name, opt->name);
31161 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31162 *input_line_pointer = saved_char;
31163 demand_empty_rest_of_line ();
31167 as_bad (_("unknown architecture `%s'\n"), name);
31168 *input_line_pointer = saved_char;
31169 ignore_rest_of_line ();
31172 /* Parse a .object_arch directive. */
31175 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
31177 const struct arm_arch_option_table *opt;
31181 name = input_line_pointer;
31182 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31183 input_line_pointer++;
31184 saved_char = *input_line_pointer;
31185 *input_line_pointer = 0;
31187 /* Skip the first "all" entry. */
31188 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31189 if (streq (opt->name, name))
31191 selected_object_arch = opt->value;
31192 *input_line_pointer = saved_char;
31193 demand_empty_rest_of_line ();
31197 as_bad (_("unknown architecture `%s'\n"), name);
31198 *input_line_pointer = saved_char;
31199 ignore_rest_of_line ();
31202 /* Parse a .arch_extension directive. */
31205 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
31207 const struct arm_option_extension_value_table *opt;
31210 int adding_value = 1;
31212 name = input_line_pointer;
31213 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31214 input_line_pointer++;
31215 saved_char = *input_line_pointer;
31216 *input_line_pointer = 0;
31218 if (strlen (name) >= 2
31219 && strncmp (name, "no", 2) == 0)
31225 for (opt = arm_extensions; opt->name != NULL; opt++)
31226 if (streq (opt->name, name))
31228 int i, nb_allowed_archs =
31229 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
31230 for (i = 0; i < nb_allowed_archs; i++)
31233 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
31235 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
31239 if (i == nb_allowed_archs)
31241 as_bad (_("architectural extension `%s' is not allowed for the "
31242 "current base architecture"), name);
31247 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
31250 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
31252 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31253 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31254 *input_line_pointer = saved_char;
31255 demand_empty_rest_of_line ();
31256 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31257 on this return so that duplicate extensions (extensions with the
31258 same name as a previous extension in the list) are not considered
31259 for command-line parsing. */
31263 if (opt->name == NULL)
31264 as_bad (_("unknown architecture extension `%s'\n"), name);
31266 *input_line_pointer = saved_char;
31267 ignore_rest_of_line ();
31270 /* Parse a .fpu directive. */
31273 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
31275 const struct arm_option_fpu_value_table *opt;
31279 name = input_line_pointer;
31280 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31281 input_line_pointer++;
31282 saved_char = *input_line_pointer;
31283 *input_line_pointer = 0;
31285 for (opt = arm_fpus; opt->name != NULL; opt++)
31286 if (streq (opt->name, name))
31288 selected_fpu = opt->value;
31289 #ifndef CPU_DEFAULT
31290 if (no_cpu_selected ())
31291 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
31294 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31295 *input_line_pointer = saved_char;
31296 demand_empty_rest_of_line ();
31300 as_bad (_("unknown floating point format `%s'\n"), name);
31301 *input_line_pointer = saved_char;
31302 ignore_rest_of_line ();
31305 /* Copy symbol information. */
31308 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
31310 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
31314 /* Given a symbolic attribute NAME, return the proper integer value.
31315 Returns -1 if the attribute is not known. */
31318 arm_convert_symbolic_attribute (const char *name)
31320 static const struct
31325 attribute_table[] =
31327 /* When you modify this table you should
31328 also modify the list in doc/c-arm.texi. */
31329 #define T(tag) {#tag, tag}
31330 T (Tag_CPU_raw_name),
31333 T (Tag_CPU_arch_profile),
31334 T (Tag_ARM_ISA_use),
31335 T (Tag_THUMB_ISA_use),
31339 T (Tag_Advanced_SIMD_arch),
31340 T (Tag_PCS_config),
31341 T (Tag_ABI_PCS_R9_use),
31342 T (Tag_ABI_PCS_RW_data),
31343 T (Tag_ABI_PCS_RO_data),
31344 T (Tag_ABI_PCS_GOT_use),
31345 T (Tag_ABI_PCS_wchar_t),
31346 T (Tag_ABI_FP_rounding),
31347 T (Tag_ABI_FP_denormal),
31348 T (Tag_ABI_FP_exceptions),
31349 T (Tag_ABI_FP_user_exceptions),
31350 T (Tag_ABI_FP_number_model),
31351 T (Tag_ABI_align_needed),
31352 T (Tag_ABI_align8_needed),
31353 T (Tag_ABI_align_preserved),
31354 T (Tag_ABI_align8_preserved),
31355 T (Tag_ABI_enum_size),
31356 T (Tag_ABI_HardFP_use),
31357 T (Tag_ABI_VFP_args),
31358 T (Tag_ABI_WMMX_args),
31359 T (Tag_ABI_optimization_goals),
31360 T (Tag_ABI_FP_optimization_goals),
31361 T (Tag_compatibility),
31362 T (Tag_CPU_unaligned_access),
31363 T (Tag_FP_HP_extension),
31364 T (Tag_VFP_HP_extension),
31365 T (Tag_ABI_FP_16bit_format),
31366 T (Tag_MPextension_use),
31368 T (Tag_nodefaults),
31369 T (Tag_also_compatible_with),
31370 T (Tag_conformance),
31372 T (Tag_Virtualization_use),
31373 T (Tag_DSP_extension),
31375 /* We deliberately do not include Tag_MPextension_use_legacy. */
31383 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
31384 if (streq (name, attribute_table[i].name))
31385 return attribute_table[i].tag;
31390 /* Apply sym value for relocations only in the case that they are for
31391 local symbols in the same segment as the fixup and you have the
31392 respective architectural feature for blx and simple switches. */
31395 arm_apply_sym_value (struct fix * fixP, segT this_seg)
31398 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
31399 /* PR 17444: If the local symbol is in a different section then a reloc
31400 will always be generated for it, so applying the symbol value now
31401 will result in a double offset being stored in the relocation. */
31402 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
31403 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
31405 switch (fixP->fx_r_type)
31407 case BFD_RELOC_ARM_PCREL_BLX:
31408 case BFD_RELOC_THUMB_PCREL_BRANCH23:
31409 if (ARM_IS_FUNC (fixP->fx_addsy))
31413 case BFD_RELOC_ARM_PCREL_CALL:
31414 case BFD_RELOC_THUMB_PCREL_BLX:
31415 if (THUMB_IS_FUNC (fixP->fx_addsy))
31426 #endif /* OBJ_ELF */