1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld.
327 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
328 const char arm_symbol_chars[] = "#[]{}";
343 enum neon_el_type type;
347 #define NEON_MAX_TYPE_ELS 4
351 struct neon_type_el el[NEON_MAX_TYPE_ELS];
355 enum it_instruction_type
360 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
361 if inside, should be the last one. */
362 NEUTRAL_IT_INSN, /* This could be either inside or outside,
363 i.e. BKPT and NOP. */
364 IT_INSN /* The IT insn has been parsed. */
367 /* The maximum number of operands we need. */
368 #define ARM_IT_MAX_OPERANDS 6
373 unsigned long instruction;
377 /* "uncond_value" is set to the value in place of the conditional field in
378 unconditional versions of the instruction, or -1 if nothing is
381 struct neon_type vectype;
382 /* This does not indicate an actual NEON instruction, only that
383 the mnemonic accepts neon-style type suffixes. */
385 /* Set to the opcode if the instruction needs relaxation.
386 Zero if the instruction is not relaxed. */
390 bfd_reloc_code_real_type type;
395 enum it_instruction_type it_insn_type;
401 struct neon_type_el vectype;
402 unsigned present : 1; /* Operand present. */
403 unsigned isreg : 1; /* Operand was a register. */
404 unsigned immisreg : 1; /* .imm field is a second register. */
405 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
406 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
407 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
408 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
409 instructions. This allows us to disambiguate ARM <-> vector insns. */
410 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
411 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
412 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
413 unsigned issingle : 1; /* Operand is VFP single-precision register. */
414 unsigned hasreloc : 1; /* Operand has relocation suffix. */
415 unsigned writeback : 1; /* Operand has trailing ! */
416 unsigned preind : 1; /* Preindexed address. */
417 unsigned postind : 1; /* Postindexed address. */
418 unsigned negative : 1; /* Index register was negated. */
419 unsigned shifted : 1; /* Shift applied to operation. */
420 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
421 } operands[ARM_IT_MAX_OPERANDS];
424 static struct arm_it inst;
426 #define NUM_FLOAT_VALS 8
428 const char * fp_const[] =
430 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
433 /* Number of littlenums required to hold an extended precision number. */
434 #define MAX_LITTLENUMS 6
436 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
446 #define CP_T_X 0x00008000
447 #define CP_T_Y 0x00400000
449 #define CONDS_BIT 0x00100000
450 #define LOAD_BIT 0x00100000
452 #define DOUBLE_LOAD_FLAG 0x00000001
456 const char * template_name;
460 #define COND_ALWAYS 0xE
464 const char * template_name;
468 struct asm_barrier_opt
470 const char * template_name;
472 const arm_feature_set arch;
475 /* The bit that distinguishes CPSR and SPSR. */
476 #define SPSR_BIT (1 << 22)
478 /* The individual PSR flag bits. */
479 #define PSR_c (1 << 16)
480 #define PSR_x (1 << 17)
481 #define PSR_s (1 << 18)
482 #define PSR_f (1 << 19)
487 bfd_reloc_code_real_type reloc;
492 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
493 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
498 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
501 /* Bits for DEFINED field in neon_typed_alias. */
502 #define NTA_HASTYPE 1
503 #define NTA_HASINDEX 2
505 struct neon_typed_alias
507 unsigned char defined;
509 struct neon_type_el eltype;
512 /* ARM register categories. This includes coprocessor numbers and various
513 architecture extensions' registers. */
540 /* Structure for a hash table entry for a register.
541 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
542 information which states whether a vector type or index is specified (for a
543 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
549 unsigned char builtin;
550 struct neon_typed_alias * neon;
553 /* Diagnostics used when we don't get a register of the expected type. */
554 const char * const reg_expected_msgs[] =
556 N_("ARM register expected"),
557 N_("bad or missing co-processor number"),
558 N_("co-processor register expected"),
559 N_("FPA register expected"),
560 N_("VFP single precision register expected"),
561 N_("VFP/Neon double precision register expected"),
562 N_("Neon quad precision register expected"),
563 N_("VFP single or double precision register expected"),
564 N_("Neon double or quad precision register expected"),
565 N_("VFP single, double or Neon quad precision register expected"),
566 N_("VFP system register expected"),
567 N_("Maverick MVF register expected"),
568 N_("Maverick MVD register expected"),
569 N_("Maverick MVFX register expected"),
570 N_("Maverick MVDX register expected"),
571 N_("Maverick MVAX register expected"),
572 N_("Maverick DSPSC register expected"),
573 N_("iWMMXt data register expected"),
574 N_("iWMMXt control register expected"),
575 N_("iWMMXt scalar register expected"),
576 N_("XScale accumulator register expected"),
579 /* Some well known registers that we refer to directly elsewhere. */
585 /* ARM instructions take 4bytes in the object file, Thumb instructions
591 /* Basic string to match. */
592 const char * template_name;
594 /* Parameters to instruction. */
595 unsigned int operands[8];
597 /* Conditional tag - see opcode_lookup. */
598 unsigned int tag : 4;
600 /* Basic instruction code. */
601 unsigned int avalue : 28;
603 /* Thumb-format instruction code. */
606 /* Which architecture variant provides this instruction. */
607 const arm_feature_set * avariant;
608 const arm_feature_set * tvariant;
610 /* Function to call to encode instruction in ARM format. */
611 void (* aencode) (void);
613 /* Function to call to encode instruction in Thumb format. */
614 void (* tencode) (void);
617 /* Defines for various bits that we will want to toggle. */
618 #define INST_IMMEDIATE 0x02000000
619 #define OFFSET_REG 0x02000000
620 #define HWOFFSET_IMM 0x00400000
621 #define SHIFT_BY_REG 0x00000010
622 #define PRE_INDEX 0x01000000
623 #define INDEX_UP 0x00800000
624 #define WRITE_BACK 0x00200000
625 #define LDM_TYPE_2_OR_3 0x00400000
626 #define CPSI_MMOD 0x00020000
628 #define LITERAL_MASK 0xf000f000
629 #define OPCODE_MASK 0xfe1fffff
630 #define V4_STR_BIT 0x00000020
632 #define T2_SUBS_PC_LR 0xf3de8f00
634 #define DATA_OP_SHIFT 21
636 #define T2_OPCODE_MASK 0xfe1fffff
637 #define T2_DATA_OP_SHIFT 21
639 #define A_COND_MASK 0xf0000000
640 #define A_PUSH_POP_OP_MASK 0x0fff0000
642 /* Opcodes for pushing/poping registers to/from the stack. */
643 #define A1_OPCODE_PUSH 0x092d0000
644 #define A2_OPCODE_PUSH 0x052d0004
645 #define A2_OPCODE_POP 0x049d0004
647 /* Codes to distinguish the arithmetic instructions. */
658 #define OPCODE_CMP 10
659 #define OPCODE_CMN 11
660 #define OPCODE_ORR 12
661 #define OPCODE_MOV 13
662 #define OPCODE_BIC 14
663 #define OPCODE_MVN 15
665 #define T2_OPCODE_AND 0
666 #define T2_OPCODE_BIC 1
667 #define T2_OPCODE_ORR 2
668 #define T2_OPCODE_ORN 3
669 #define T2_OPCODE_EOR 4
670 #define T2_OPCODE_ADD 8
671 #define T2_OPCODE_ADC 10
672 #define T2_OPCODE_SBC 11
673 #define T2_OPCODE_SUB 13
674 #define T2_OPCODE_RSB 14
676 #define T_OPCODE_MUL 0x4340
677 #define T_OPCODE_TST 0x4200
678 #define T_OPCODE_CMN 0x42c0
679 #define T_OPCODE_NEG 0x4240
680 #define T_OPCODE_MVN 0x43c0
682 #define T_OPCODE_ADD_R3 0x1800
683 #define T_OPCODE_SUB_R3 0x1a00
684 #define T_OPCODE_ADD_HI 0x4400
685 #define T_OPCODE_ADD_ST 0xb000
686 #define T_OPCODE_SUB_ST 0xb080
687 #define T_OPCODE_ADD_SP 0xa800
688 #define T_OPCODE_ADD_PC 0xa000
689 #define T_OPCODE_ADD_I8 0x3000
690 #define T_OPCODE_SUB_I8 0x3800
691 #define T_OPCODE_ADD_I3 0x1c00
692 #define T_OPCODE_SUB_I3 0x1e00
694 #define T_OPCODE_ASR_R 0x4100
695 #define T_OPCODE_LSL_R 0x4080
696 #define T_OPCODE_LSR_R 0x40c0
697 #define T_OPCODE_ROR_R 0x41c0
698 #define T_OPCODE_ASR_I 0x1000
699 #define T_OPCODE_LSL_I 0x0000
700 #define T_OPCODE_LSR_I 0x0800
702 #define T_OPCODE_MOV_I8 0x2000
703 #define T_OPCODE_CMP_I8 0x2800
704 #define T_OPCODE_CMP_LR 0x4280
705 #define T_OPCODE_MOV_HR 0x4600
706 #define T_OPCODE_CMP_HR 0x4500
708 #define T_OPCODE_LDR_PC 0x4800
709 #define T_OPCODE_LDR_SP 0x9800
710 #define T_OPCODE_STR_SP 0x9000
711 #define T_OPCODE_LDR_IW 0x6800
712 #define T_OPCODE_STR_IW 0x6000
713 #define T_OPCODE_LDR_IH 0x8800
714 #define T_OPCODE_STR_IH 0x8000
715 #define T_OPCODE_LDR_IB 0x7800
716 #define T_OPCODE_STR_IB 0x7000
717 #define T_OPCODE_LDR_RW 0x5800
718 #define T_OPCODE_STR_RW 0x5000
719 #define T_OPCODE_LDR_RH 0x5a00
720 #define T_OPCODE_STR_RH 0x5200
721 #define T_OPCODE_LDR_RB 0x5c00
722 #define T_OPCODE_STR_RB 0x5400
724 #define T_OPCODE_PUSH 0xb400
725 #define T_OPCODE_POP 0xbc00
727 #define T_OPCODE_BRANCH 0xe000
729 #define THUMB_SIZE 2 /* Size of thumb instruction. */
730 #define THUMB_PP_PC_LR 0x0100
731 #define THUMB_LOAD_BIT 0x0800
732 #define THUMB2_LOAD_BIT 0x00100000
734 #define BAD_ARGS _("bad arguments to instruction")
735 #define BAD_SP _("r13 not allowed here")
736 #define BAD_PC _("r15 not allowed here")
737 #define BAD_COND _("instruction cannot be conditional")
738 #define BAD_OVERLAP _("registers may not be the same")
739 #define BAD_HIREG _("lo register required")
740 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
741 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
742 #define BAD_BRANCH _("branch must be last instruction in IT block")
743 #define BAD_NOT_IT _("instruction not allowed in IT block")
744 #define BAD_FPU _("selected FPU does not support instruction")
745 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
746 #define BAD_IT_COND _("incorrect condition in IT block")
747 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
748 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
749 #define BAD_PC_ADDRESSING \
750 _("cannot use register index with PC-relative addressing")
751 #define BAD_PC_WRITEBACK \
752 _("cannot use writeback with PC-relative addressing")
753 #define BAD_RANGE _("branch out of range")
754 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
756 static struct hash_control * arm_ops_hsh;
757 static struct hash_control * arm_cond_hsh;
758 static struct hash_control * arm_shift_hsh;
759 static struct hash_control * arm_psr_hsh;
760 static struct hash_control * arm_v7m_psr_hsh;
761 static struct hash_control * arm_reg_hsh;
762 static struct hash_control * arm_reloc_hsh;
763 static struct hash_control * arm_barrier_opt_hsh;
765 /* Stuff needed to resolve the label ambiguity
774 symbolS * last_label_seen;
775 static int label_is_thumb_function_name = FALSE;
777 /* Literal pool structure. Held on a per-section
778 and per-sub-section basis. */
780 #define MAX_LITERAL_POOL_SIZE 1024
781 typedef struct literal_pool
783 expressionS literals [MAX_LITERAL_POOL_SIZE];
784 unsigned int next_free_entry;
790 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
792 struct literal_pool * next;
795 /* Pointer to a linked list of literal pools. */
796 literal_pool * list_of_pools = NULL;
799 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
801 static struct current_it now_it;
805 now_it_compatible (int cond)
807 return (cond & ~1) == (now_it.cc & ~1);
811 conditional_insn (void)
813 return inst.cond != COND_ALWAYS;
816 static int in_it_block (void);
818 static int handle_it_state (void);
820 static void force_automatic_it_block_close (void);
822 static void it_fsm_post_encode (void);
824 #define set_it_insn_type(type) \
827 inst.it_insn_type = type; \
828 if (handle_it_state () == FAIL) \
833 #define set_it_insn_type_nonvoid(type, failret) \
836 inst.it_insn_type = type; \
837 if (handle_it_state () == FAIL) \
842 #define set_it_insn_type_last() \
845 if (inst.cond == COND_ALWAYS) \
846 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
848 set_it_insn_type (INSIDE_IT_LAST_INSN); \
854 /* This array holds the chars that always start a comment. If the
855 pre-processor is disabled, these aren't very useful. */
856 const char comment_chars[] = "@";
858 /* This array holds the chars that only start a comment at the beginning of
859 a line. If the line seems to have the form '# 123 filename'
860 .line and .file directives will appear in the pre-processed output. */
861 /* Note that input_file.c hand checks for '#' at the beginning of the
862 first line of the input file. This is because the compiler outputs
863 #NO_APP at the beginning of its output. */
864 /* Also note that comments like this one will always work. */
865 const char line_comment_chars[] = "#";
867 const char line_separator_chars[] = ";";
869 /* Chars that can be used to separate mant
870 from exp in floating point numbers. */
871 const char EXP_CHARS[] = "eE";
873 /* Chars that mean this number is a floating point constant. */
877 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
879 /* Prefix characters that indicate the start of an immediate
881 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
883 /* Separator character handling. */
885 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
888 skip_past_char (char ** str, char c)
890 /* PR gas/14987: Allow for whitespace before the expected character. */
891 skip_whitespace (*str);
902 #define skip_past_comma(str) skip_past_char (str, ',')
904 /* Arithmetic expressions (possibly involving symbols). */
906 /* Return TRUE if anything in the expression is a bignum. */
909 walk_no_bignums (symbolS * sp)
911 if (symbol_get_value_expression (sp)->X_op == O_big)
914 if (symbol_get_value_expression (sp)->X_add_symbol)
916 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
917 || (symbol_get_value_expression (sp)->X_op_symbol
918 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
924 static int in_my_get_expression = 0;
926 /* Third argument to my_get_expression. */
927 #define GE_NO_PREFIX 0
928 #define GE_IMM_PREFIX 1
929 #define GE_OPT_PREFIX 2
930 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
931 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
932 #define GE_OPT_PREFIX_BIG 3
935 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
940 /* In unified syntax, all prefixes are optional. */
942 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
947 case GE_NO_PREFIX: break;
949 if (!is_immediate_prefix (**str))
951 inst.error = _("immediate expression requires a # prefix");
957 case GE_OPT_PREFIX_BIG:
958 if (is_immediate_prefix (**str))
964 memset (ep, 0, sizeof (expressionS));
966 save_in = input_line_pointer;
967 input_line_pointer = *str;
968 in_my_get_expression = 1;
969 seg = expression (ep);
970 in_my_get_expression = 0;
972 if (ep->X_op == O_illegal || ep->X_op == O_absent)
974 /* We found a bad or missing expression in md_operand(). */
975 *str = input_line_pointer;
976 input_line_pointer = save_in;
977 if (inst.error == NULL)
978 inst.error = (ep->X_op == O_absent
979 ? _("missing expression") :_("bad expression"));
984 if (seg != absolute_section
985 && seg != text_section
986 && seg != data_section
987 && seg != bss_section
988 && seg != undefined_section)
990 inst.error = _("bad segment");
991 *str = input_line_pointer;
992 input_line_pointer = save_in;
999 /* Get rid of any bignums now, so that we don't generate an error for which
1000 we can't establish a line number later on. Big numbers are never valid
1001 in instructions, which is where this routine is always called. */
1002 if (prefix_mode != GE_OPT_PREFIX_BIG
1003 && (ep->X_op == O_big
1004 || (ep->X_add_symbol
1005 && (walk_no_bignums (ep->X_add_symbol)
1007 && walk_no_bignums (ep->X_op_symbol))))))
1009 inst.error = _("invalid constant");
1010 *str = input_line_pointer;
1011 input_line_pointer = save_in;
1015 *str = input_line_pointer;
1016 input_line_pointer = save_in;
1020 /* Turn a string in input_line_pointer into a floating point constant
1021 of type TYPE, and store the appropriate bytes in *LITP. The number
1022 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1023 returned, or NULL on OK.
1025 Note that fp constants aren't represent in the normal way on the ARM.
1026 In big endian mode, things are as expected. However, in little endian
1027 mode fp constants are big-endian word-wise, and little-endian byte-wise
1028 within the words. For example, (double) 1.1 in big endian mode is
1029 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1030 the byte sequence 99 99 f1 3f 9a 99 99 99.
1032 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1035 md_atof (int type, char * litP, int * sizeP)
1038 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1070 return _("Unrecognized or unsupported floating point constant");
1073 t = atof_ieee (input_line_pointer, type, words);
1075 input_line_pointer = t;
1076 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1078 if (target_big_endian)
1080 for (i = 0; i < prec; i++)
1082 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1083 litP += sizeof (LITTLENUM_TYPE);
1088 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1089 for (i = prec - 1; i >= 0; i--)
1091 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += sizeof (LITTLENUM_TYPE);
1095 /* For a 4 byte float the order of elements in `words' is 1 0.
1096 For an 8 byte float the order is 1 0 3 2. */
1097 for (i = 0; i < prec; i += 2)
1099 md_number_to_chars (litP, (valueT) words[i + 1],
1100 sizeof (LITTLENUM_TYPE));
1101 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1102 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1103 litP += 2 * sizeof (LITTLENUM_TYPE);
1110 /* We handle all bad expressions here, so that we can report the faulty
1111 instruction in the error message. */
1113 md_operand (expressionS * exp)
1115 if (in_my_get_expression)
1116 exp->X_op = O_illegal;
1119 /* Immediate values. */
1121 /* Generic immediate-value read function for use in directives.
1122 Accepts anything that 'expression' can fold to a constant.
1123 *val receives the number. */
1126 immediate_for_directive (int *val)
1129 exp.X_op = O_illegal;
1131 if (is_immediate_prefix (*input_line_pointer))
1133 input_line_pointer++;
1137 if (exp.X_op != O_constant)
1139 as_bad (_("expected #constant"));
1140 ignore_rest_of_line ();
1143 *val = exp.X_add_number;
1148 /* Register parsing. */
1150 /* Generic register parser. CCP points to what should be the
1151 beginning of a register name. If it is indeed a valid register
1152 name, advance CCP over it and return the reg_entry structure;
1153 otherwise return NULL. Does not issue diagnostics. */
1155 static struct reg_entry *
1156 arm_reg_parse_multi (char **ccp)
1160 struct reg_entry *reg;
1162 skip_whitespace (start);
1164 #ifdef REGISTER_PREFIX
1165 if (*start != REGISTER_PREFIX)
1169 #ifdef OPTIONAL_REGISTER_PREFIX
1170 if (*start == OPTIONAL_REGISTER_PREFIX)
1175 if (!ISALPHA (*p) || !is_name_beginner (*p))
1180 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1182 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1192 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1193 enum arm_reg_type type)
1195 /* Alternative syntaxes are accepted for a few register classes. */
1202 /* Generic coprocessor register names are allowed for these. */
1203 if (reg && reg->type == REG_TYPE_CN)
1208 /* For backward compatibility, a bare number is valid here. */
1210 unsigned long processor = strtoul (start, ccp, 10);
1211 if (*ccp != start && processor <= 15)
1215 case REG_TYPE_MMXWC:
1216 /* WC includes WCG. ??? I'm not sure this is true for all
1217 instructions that take WC registers. */
1218 if (reg && reg->type == REG_TYPE_MMXWCG)
1229 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1230 return value is the register number or FAIL. */
1233 arm_reg_parse (char **ccp, enum arm_reg_type type)
1236 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1239 /* Do not allow a scalar (reg+index) to parse as a register. */
1240 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1243 if (reg && reg->type == type)
1246 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1253 /* Parse a Neon type specifier. *STR should point at the leading '.'
1254 character. Does no verification at this stage that the type fits the opcode
1261 Can all be legally parsed by this function.
1263 Fills in neon_type struct pointer with parsed information, and updates STR
1264 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1265 type, FAIL if not. */
1268 parse_neon_type (struct neon_type *type, char **str)
1275 while (type->elems < NEON_MAX_TYPE_ELS)
1277 enum neon_el_type thistype = NT_untyped;
1278 unsigned thissize = -1u;
1285 /* Just a size without an explicit type. */
1289 switch (TOLOWER (*ptr))
1291 case 'i': thistype = NT_integer; break;
1292 case 'f': thistype = NT_float; break;
1293 case 'p': thistype = NT_poly; break;
1294 case 's': thistype = NT_signed; break;
1295 case 'u': thistype = NT_unsigned; break;
1297 thistype = NT_float;
1302 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1308 /* .f is an abbreviation for .f32. */
1309 if (thistype == NT_float && !ISDIGIT (*ptr))
1314 thissize = strtoul (ptr, &ptr, 10);
1316 if (thissize != 8 && thissize != 16 && thissize != 32
1319 as_bad (_("bad size %d in type specifier"), thissize);
1327 type->el[type->elems].type = thistype;
1328 type->el[type->elems].size = thissize;
1333 /* Empty/missing type is not a successful parse. */
1334 if (type->elems == 0)
1342 /* Errors may be set multiple times during parsing or bit encoding
1343 (particularly in the Neon bits), but usually the earliest error which is set
1344 will be the most meaningful. Avoid overwriting it with later (cascading)
1345 errors by calling this function. */
1348 first_error (const char *err)
1354 /* Parse a single type, e.g. ".s32", leading period included. */
1356 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1359 struct neon_type optype;
1363 if (parse_neon_type (&optype, &str) == SUCCESS)
1365 if (optype.elems == 1)
1366 *vectype = optype.el[0];
1369 first_error (_("only one type should be specified for operand"));
1375 first_error (_("vector type expected"));
1387 /* Special meanings for indices (which have a range of 0-7), which will fit into
1390 #define NEON_ALL_LANES 15
1391 #define NEON_INTERLEAVE_LANES 14
1393 /* Parse either a register or a scalar, with an optional type. Return the
1394 register number, and optionally fill in the actual type of the register
1395 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1396 type/index information in *TYPEINFO. */
1399 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1400 enum arm_reg_type *rtype,
1401 struct neon_typed_alias *typeinfo)
1404 struct reg_entry *reg = arm_reg_parse_multi (&str);
1405 struct neon_typed_alias atype;
1406 struct neon_type_el parsetype;
1410 atype.eltype.type = NT_invtype;
1411 atype.eltype.size = -1;
1413 /* Try alternate syntax for some types of register. Note these are mutually
1414 exclusive with the Neon syntax extensions. */
1417 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1425 /* Undo polymorphism when a set of register types may be accepted. */
1426 if ((type == REG_TYPE_NDQ
1427 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1428 || (type == REG_TYPE_VFSD
1429 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1430 || (type == REG_TYPE_NSDQ
1431 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1432 || reg->type == REG_TYPE_NQ))
1433 || (type == REG_TYPE_MMXWC
1434 && (reg->type == REG_TYPE_MMXWCG)))
1435 type = (enum arm_reg_type) reg->type;
1437 if (type != reg->type)
1443 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1445 if ((atype.defined & NTA_HASTYPE) != 0)
1447 first_error (_("can't redefine type for operand"));
1450 atype.defined |= NTA_HASTYPE;
1451 atype.eltype = parsetype;
1454 if (skip_past_char (&str, '[') == SUCCESS)
1456 if (type != REG_TYPE_VFD)
1458 first_error (_("only D registers may be indexed"));
1462 if ((atype.defined & NTA_HASINDEX) != 0)
1464 first_error (_("can't change index for operand"));
1468 atype.defined |= NTA_HASINDEX;
1470 if (skip_past_char (&str, ']') == SUCCESS)
1471 atype.index = NEON_ALL_LANES;
1476 my_get_expression (&exp, &str, GE_NO_PREFIX);
1478 if (exp.X_op != O_constant)
1480 first_error (_("constant expression required"));
1484 if (skip_past_char (&str, ']') == FAIL)
1487 atype.index = exp.X_add_number;
1502 /* Like arm_reg_parse, but allow allow the following extra features:
1503 - If RTYPE is non-zero, return the (possibly restricted) type of the
1504 register (e.g. Neon double or quad reg when either has been requested).
1505 - If this is a Neon vector type with additional type information, fill
1506 in the struct pointed to by VECTYPE (if non-NULL).
1507 This function will fault on encountering a scalar. */
1510 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1511 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1513 struct neon_typed_alias atype;
1515 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1520 /* Do not allow regname(... to parse as a register. */
1524 /* Do not allow a scalar (reg+index) to parse as a register. */
1525 if ((atype.defined & NTA_HASINDEX) != 0)
1527 first_error (_("register operand expected, but got scalar"));
1532 *vectype = atype.eltype;
1539 #define NEON_SCALAR_REG(X) ((X) >> 4)
1540 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1542 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1543 have enough information to be able to do a good job bounds-checking. So, we
1544 just do easy checks here, and do further checks later. */
1547 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1551 struct neon_typed_alias atype;
1553 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1555 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1558 if (atype.index == NEON_ALL_LANES)
1560 first_error (_("scalar must have an index"));
1563 else if (atype.index >= 64 / elsize)
1565 first_error (_("scalar index out of range"));
1570 *type = atype.eltype;
1574 return reg * 16 + atype.index;
1577 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1580 parse_reg_list (char ** strp)
1582 char * str = * strp;
1586 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 skip_whitespace (str);
1603 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1605 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1615 first_error (_("bad range in register list"));
1619 for (i = cur_reg + 1; i < reg; i++)
1621 if (range & (1 << i))
1623 (_("Warning: duplicated register (r%d) in register list"),
1631 if (range & (1 << reg))
1632 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1634 else if (reg <= cur_reg)
1635 as_tsktsk (_("Warning: register range not in ascending order"));
1640 while (skip_past_comma (&str) != FAIL
1641 || (in_range = 1, *str++ == '-'));
1644 if (skip_past_char (&str, '}') == FAIL)
1646 first_error (_("missing `}'"));
1654 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1657 if (exp.X_op == O_constant)
1659 if (exp.X_add_number
1660 != (exp.X_add_number & 0x0000ffff))
1662 inst.error = _("invalid register mask");
1666 if ((range & exp.X_add_number) != 0)
1668 int regno = range & exp.X_add_number;
1671 regno = (1 << regno) - 1;
1673 (_("Warning: duplicated register (r%d) in register list"),
1677 range |= exp.X_add_number;
1681 if (inst.reloc.type != 0)
1683 inst.error = _("expression too complex");
1687 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1688 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1689 inst.reloc.pc_rel = 0;
1693 if (*str == '|' || *str == '+')
1699 while (another_range);
1705 /* Types of registers in a list. */
1714 /* Parse a VFP register list. If the string is invalid return FAIL.
1715 Otherwise return the number of registers, and set PBASE to the first
1716 register. Parses registers of type ETYPE.
1717 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1718 - Q registers can be used to specify pairs of D registers
1719 - { } can be omitted from around a singleton register list
1720 FIXME: This is not implemented, as it would require backtracking in
1723 This could be done (the meaning isn't really ambiguous), but doesn't
1724 fit in well with the current parsing framework.
1725 - 32 D registers may be used (also true for VFPv3).
1726 FIXME: Types are ignored in these register lists, which is probably a
1730 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1735 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1739 unsigned long mask = 0;
1742 if (skip_past_char (&str, '{') == FAIL)
1744 inst.error = _("expecting {");
1751 regtype = REG_TYPE_VFS;
1756 regtype = REG_TYPE_VFD;
1759 case REGLIST_NEON_D:
1760 regtype = REG_TYPE_NDQ;
1764 if (etype != REGLIST_VFP_S)
1766 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1767 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1771 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1774 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1781 base_reg = max_regs;
1785 int setmask = 1, addregs = 1;
1787 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1789 if (new_base == FAIL)
1791 first_error (_(reg_expected_msgs[regtype]));
1795 if (new_base >= max_regs)
1797 first_error (_("register out of range in list"));
1801 /* Note: a value of 2 * n is returned for the register Q<n>. */
1802 if (regtype == REG_TYPE_NQ)
1808 if (new_base < base_reg)
1809 base_reg = new_base;
1811 if (mask & (setmask << new_base))
1813 first_error (_("invalid register list"));
1817 if ((mask >> new_base) != 0 && ! warned)
1819 as_tsktsk (_("register list not in ascending order"));
1823 mask |= setmask << new_base;
1826 if (*str == '-') /* We have the start of a range expression */
1832 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1835 inst.error = gettext (reg_expected_msgs[regtype]);
1839 if (high_range >= max_regs)
1841 first_error (_("register out of range in list"));
1845 if (regtype == REG_TYPE_NQ)
1846 high_range = high_range + 1;
1848 if (high_range <= new_base)
1850 inst.error = _("register range not in ascending order");
1854 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1856 if (mask & (setmask << new_base))
1858 inst.error = _("invalid register list");
1862 mask |= setmask << new_base;
1867 while (skip_past_comma (&str) != FAIL);
1871 /* Sanity check -- should have raised a parse error above. */
1872 if (count == 0 || count > max_regs)
1877 /* Final test -- the registers must be consecutive. */
1879 for (i = 0; i < count; i++)
1881 if ((mask & (1u << i)) == 0)
1883 inst.error = _("non-contiguous register range");
1893 /* True if two alias types are the same. */
1896 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1904 if (a->defined != b->defined)
1907 if ((a->defined & NTA_HASTYPE) != 0
1908 && (a->eltype.type != b->eltype.type
1909 || a->eltype.size != b->eltype.size))
1912 if ((a->defined & NTA_HASINDEX) != 0
1913 && (a->index != b->index))
1919 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1920 The base register is put in *PBASE.
1921 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1923 The register stride (minus one) is put in bit 4 of the return value.
1924 Bits [6:5] encode the list length (minus one).
1925 The type of the list elements is put in *ELTYPE, if non-NULL. */
1927 #define NEON_LANE(X) ((X) & 0xf)
1928 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1929 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1932 parse_neon_el_struct_list (char **str, unsigned *pbase,
1933 struct neon_type_el *eltype)
1940 int leading_brace = 0;
1941 enum arm_reg_type rtype = REG_TYPE_NDQ;
1942 const char *const incr_error = _("register stride must be 1 or 2");
1943 const char *const type_error = _("mismatched element/structure types in list");
1944 struct neon_typed_alias firsttype;
1946 if (skip_past_char (&ptr, '{') == SUCCESS)
1951 struct neon_typed_alias atype;
1952 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1956 first_error (_(reg_expected_msgs[rtype]));
1963 if (rtype == REG_TYPE_NQ)
1969 else if (reg_incr == -1)
1971 reg_incr = getreg - base_reg;
1972 if (reg_incr < 1 || reg_incr > 2)
1974 first_error (_(incr_error));
1978 else if (getreg != base_reg + reg_incr * count)
1980 first_error (_(incr_error));
1984 if (! neon_alias_types_same (&atype, &firsttype))
1986 first_error (_(type_error));
1990 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1994 struct neon_typed_alias htype;
1995 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1997 lane = NEON_INTERLEAVE_LANES;
1998 else if (lane != NEON_INTERLEAVE_LANES)
2000 first_error (_(type_error));
2005 else if (reg_incr != 1)
2007 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2011 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2014 first_error (_(reg_expected_msgs[rtype]));
2017 if (! neon_alias_types_same (&htype, &firsttype))
2019 first_error (_(type_error));
2022 count += hireg + dregs - getreg;
2026 /* If we're using Q registers, we can't use [] or [n] syntax. */
2027 if (rtype == REG_TYPE_NQ)
2033 if ((atype.defined & NTA_HASINDEX) != 0)
2037 else if (lane != atype.index)
2039 first_error (_(type_error));
2043 else if (lane == -1)
2044 lane = NEON_INTERLEAVE_LANES;
2045 else if (lane != NEON_INTERLEAVE_LANES)
2047 first_error (_(type_error));
2052 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2054 /* No lane set by [x]. We must be interleaving structures. */
2056 lane = NEON_INTERLEAVE_LANES;
2059 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2060 || (count > 1 && reg_incr == -1))
2062 first_error (_("error parsing element/structure list"));
2066 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2068 first_error (_("expected }"));
2076 *eltype = firsttype.eltype;
2081 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2084 /* Parse an explicit relocation suffix on an expression. This is
2085 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2086 arm_reloc_hsh contains no entries, so this function can only
2087 succeed if there is no () after the word. Returns -1 on error,
2088 BFD_RELOC_UNUSED if there wasn't any suffix. */
2091 parse_reloc (char **str)
2093 struct reloc_entry *r;
2097 return BFD_RELOC_UNUSED;
2102 while (*q && *q != ')' && *q != ',')
2107 if ((r = (struct reloc_entry *)
2108 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2115 /* Directives: register aliases. */
2117 static struct reg_entry *
2118 insert_reg_alias (char *str, unsigned number, int type)
2120 struct reg_entry *new_reg;
2123 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2125 if (new_reg->builtin)
2126 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2128 /* Only warn about a redefinition if it's not defined as the
2130 else if (new_reg->number != number || new_reg->type != type)
2131 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2136 name = xstrdup (str);
2137 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2139 new_reg->name = name;
2140 new_reg->number = number;
2141 new_reg->type = type;
2142 new_reg->builtin = FALSE;
2143 new_reg->neon = NULL;
2145 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2152 insert_neon_reg_alias (char *str, int number, int type,
2153 struct neon_typed_alias *atype)
2155 struct reg_entry *reg = insert_reg_alias (str, number, type);
2159 first_error (_("attempt to redefine typed alias"));
2165 reg->neon = (struct neon_typed_alias *)
2166 xmalloc (sizeof (struct neon_typed_alias));
2167 *reg->neon = *atype;
2171 /* Look for the .req directive. This is of the form:
2173 new_register_name .req existing_register_name
2175 If we find one, or if it looks sufficiently like one that we want to
2176 handle any error here, return TRUE. Otherwise return FALSE. */
2179 create_register_alias (char * newname, char *p)
2181 struct reg_entry *old;
2182 char *oldname, *nbuf;
2185 /* The input scrubber ensures that whitespace after the mnemonic is
2186 collapsed to single spaces. */
2188 if (strncmp (oldname, " .req ", 6) != 0)
2192 if (*oldname == '\0')
2195 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2198 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2202 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2203 the desired alias name, and p points to its end. If not, then
2204 the desired alias name is in the global original_case_string. */
2205 #ifdef TC_CASE_SENSITIVE
2208 newname = original_case_string;
2209 nlen = strlen (newname);
2212 nbuf = (char *) alloca (nlen + 1);
2213 memcpy (nbuf, newname, nlen);
2216 /* Create aliases under the new name as stated; an all-lowercase
2217 version of the new name; and an all-uppercase version of the new
2219 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2221 for (p = nbuf; *p; p++)
2224 if (strncmp (nbuf, newname, nlen))
2226 /* If this attempt to create an additional alias fails, do not bother
2227 trying to create the all-lower case alias. We will fail and issue
2228 a second, duplicate error message. This situation arises when the
2229 programmer does something like:
2232 The second .req creates the "Foo" alias but then fails to create
2233 the artificial FOO alias because it has already been created by the
2235 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2239 for (p = nbuf; *p; p++)
2242 if (strncmp (nbuf, newname, nlen))
2243 insert_reg_alias (nbuf, old->number, old->type);
2249 /* Create a Neon typed/indexed register alias using directives, e.g.:
2254 These typed registers can be used instead of the types specified after the
2255 Neon mnemonic, so long as all operands given have types. Types can also be
2256 specified directly, e.g.:
2257 vadd d0.s32, d1.s32, d2.s32 */
2260 create_neon_reg_alias (char *newname, char *p)
2262 enum arm_reg_type basetype;
2263 struct reg_entry *basereg;
2264 struct reg_entry mybasereg;
2265 struct neon_type ntype;
2266 struct neon_typed_alias typeinfo;
2267 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2270 typeinfo.defined = 0;
2271 typeinfo.eltype.type = NT_invtype;
2272 typeinfo.eltype.size = -1;
2273 typeinfo.index = -1;
2277 if (strncmp (p, " .dn ", 5) == 0)
2278 basetype = REG_TYPE_VFD;
2279 else if (strncmp (p, " .qn ", 5) == 0)
2280 basetype = REG_TYPE_NQ;
2289 basereg = arm_reg_parse_multi (&p);
2291 if (basereg && basereg->type != basetype)
2293 as_bad (_("bad type for register"));
2297 if (basereg == NULL)
2300 /* Try parsing as an integer. */
2301 my_get_expression (&exp, &p, GE_NO_PREFIX);
2302 if (exp.X_op != O_constant)
2304 as_bad (_("expression must be constant"));
2307 basereg = &mybasereg;
2308 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2314 typeinfo = *basereg->neon;
2316 if (parse_neon_type (&ntype, &p) == SUCCESS)
2318 /* We got a type. */
2319 if (typeinfo.defined & NTA_HASTYPE)
2321 as_bad (_("can't redefine the type of a register alias"));
2325 typeinfo.defined |= NTA_HASTYPE;
2326 if (ntype.elems != 1)
2328 as_bad (_("you must specify a single type only"));
2331 typeinfo.eltype = ntype.el[0];
2334 if (skip_past_char (&p, '[') == SUCCESS)
2337 /* We got a scalar index. */
2339 if (typeinfo.defined & NTA_HASINDEX)
2341 as_bad (_("can't redefine the index of a scalar alias"));
2345 my_get_expression (&exp, &p, GE_NO_PREFIX);
2347 if (exp.X_op != O_constant)
2349 as_bad (_("scalar index must be constant"));
2353 typeinfo.defined |= NTA_HASINDEX;
2354 typeinfo.index = exp.X_add_number;
2356 if (skip_past_char (&p, ']') == FAIL)
2358 as_bad (_("expecting ]"));
2363 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2364 the desired alias name, and p points to its end. If not, then
2365 the desired alias name is in the global original_case_string. */
2366 #ifdef TC_CASE_SENSITIVE
2367 namelen = nameend - newname;
2369 newname = original_case_string;
2370 namelen = strlen (newname);
2373 namebuf = (char *) alloca (namelen + 1);
2374 strncpy (namebuf, newname, namelen);
2375 namebuf[namelen] = '\0';
2377 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2378 typeinfo.defined != 0 ? &typeinfo : NULL);
2380 /* Insert name in all uppercase. */
2381 for (p = namebuf; *p; p++)
2384 if (strncmp (namebuf, newname, namelen))
2385 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2386 typeinfo.defined != 0 ? &typeinfo : NULL);
2388 /* Insert name in all lowercase. */
2389 for (p = namebuf; *p; p++)
2392 if (strncmp (namebuf, newname, namelen))
2393 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2394 typeinfo.defined != 0 ? &typeinfo : NULL);
2399 /* Should never be called, as .req goes between the alias and the
2400 register name, not at the beginning of the line. */
2403 s_req (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .req directive"));
2409 s_dn (int a ATTRIBUTE_UNUSED)
2411 as_bad (_("invalid syntax for .dn directive"));
2415 s_qn (int a ATTRIBUTE_UNUSED)
2417 as_bad (_("invalid syntax for .qn directive"));
2420 /* The .unreq directive deletes an alias which was previously defined
2421 by .req. For example:
2427 s_unreq (int a ATTRIBUTE_UNUSED)
2432 name = input_line_pointer;
2434 while (*input_line_pointer != 0
2435 && *input_line_pointer != ' '
2436 && *input_line_pointer != '\n')
2437 ++input_line_pointer;
2439 saved_char = *input_line_pointer;
2440 *input_line_pointer = 0;
2443 as_bad (_("invalid syntax for .unreq directive"));
2446 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2450 as_bad (_("unknown register alias '%s'"), name);
2451 else if (reg->builtin)
2452 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2459 hash_delete (arm_reg_hsh, name, FALSE);
2460 free ((char *) reg->name);
2465 /* Also locate the all upper case and all lower case versions.
2466 Do not complain if we cannot find one or the other as it
2467 was probably deleted above. */
2469 nbuf = strdup (name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2482 for (p = nbuf; *p; p++)
2484 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2487 hash_delete (arm_reg_hsh, nbuf, FALSE);
2488 free ((char *) reg->name);
2498 *input_line_pointer = saved_char;
2499 demand_empty_rest_of_line ();
2502 /* Directives: Instruction set selection. */
2505 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2506 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2507 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2508 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2510 /* Create a new mapping symbol for the transition to STATE. */
2513 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2516 const char * symname;
2523 type = BSF_NO_FLAGS;
2527 type = BSF_NO_FLAGS;
2531 type = BSF_NO_FLAGS;
2537 symbolP = symbol_new (symname, now_seg, value, frag);
2538 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2543 THUMB_SET_FUNC (symbolP, 0);
2544 ARM_SET_THUMB (symbolP, 0);
2545 ARM_SET_INTERWORK (symbolP, support_interwork);
2549 THUMB_SET_FUNC (symbolP, 1);
2550 ARM_SET_THUMB (symbolP, 1);
2551 ARM_SET_INTERWORK (symbolP, support_interwork);
2559 /* Save the mapping symbols for future reference. Also check that
2560 we do not place two mapping symbols at the same offset within a
2561 frag. We'll handle overlap between frags in
2562 check_mapping_symbols.
2564 If .fill or other data filling directive generates zero sized data,
2565 the mapping symbol for the following code will have the same value
2566 as the one generated for the data filling directive. In this case,
2567 we replace the old symbol with the new one at the same address. */
2570 if (frag->tc_frag_data.first_map != NULL)
2572 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2573 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2575 frag->tc_frag_data.first_map = symbolP;
2577 if (frag->tc_frag_data.last_map != NULL)
2579 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2580 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2581 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2583 frag->tc_frag_data.last_map = symbolP;
2586 /* We must sometimes convert a region marked as code to data during
2587 code alignment, if an odd number of bytes have to be padded. The
2588 code mapping symbol is pushed to an aligned address. */
2591 insert_data_mapping_symbol (enum mstate state,
2592 valueT value, fragS *frag, offsetT bytes)
2594 /* If there was already a mapping symbol, remove it. */
2595 if (frag->tc_frag_data.last_map != NULL
2596 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2598 symbolS *symp = frag->tc_frag_data.last_map;
2602 know (frag->tc_frag_data.first_map == symp);
2603 frag->tc_frag_data.first_map = NULL;
2605 frag->tc_frag_data.last_map = NULL;
2606 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2609 make_mapping_symbol (MAP_DATA, value, frag);
2610 make_mapping_symbol (state, value + bytes, frag);
2613 static void mapping_state_2 (enum mstate state, int max_chars);
2615 /* Set the mapping state to STATE. Only call this when about to
2616 emit some STATE bytes to the file. */
2619 mapping_state (enum mstate state)
2621 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2623 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2625 if (mapstate == state)
2626 /* The mapping symbol has already been emitted.
2627 There is nothing else to do. */
2630 if (state == MAP_ARM || state == MAP_THUMB)
2632 All ARM instructions require 4-byte alignment.
2633 (Almost) all Thumb instructions require 2-byte alignment.
2635 When emitting instructions into any section, mark the section
2638 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2639 but themselves require 2-byte alignment; this applies to some
2640 PC- relative forms. However, these cases will invovle implicit
2641 literal pool generation or an explicit .align >=2, both of
2642 which will cause the section to me marked with sufficient
2643 alignment. Thus, we don't handle those cases here. */
2644 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2646 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2647 /* This case will be evaluated later in the next else. */
2649 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2650 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2652 /* Only add the symbol if the offset is > 0:
2653 if we're at the first frag, check it's size > 0;
2654 if we're not at the first frag, then for sure
2655 the offset is > 0. */
2656 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2657 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2660 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2663 mapping_state_2 (state, 0);
2667 /* Same as mapping_state, but MAX_CHARS bytes have already been
2668 allocated. Put the mapping symbol that far back. */
2671 mapping_state_2 (enum mstate state, int max_chars)
2673 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2675 if (!SEG_NORMAL (now_seg))
2678 if (mapstate == state)
2679 /* The mapping symbol has already been emitted.
2680 There is nothing else to do. */
2683 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2684 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2687 #define mapping_state(x) ((void)0)
2688 #define mapping_state_2(x, y) ((void)0)
2691 /* Find the real, Thumb encoded start of a Thumb function. */
2695 find_real_start (symbolS * symbolP)
2698 const char * name = S_GET_NAME (symbolP);
2699 symbolS * new_target;
2701 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2702 #define STUB_NAME ".real_start_of"
2707 /* The compiler may generate BL instructions to local labels because
2708 it needs to perform a branch to a far away location. These labels
2709 do not have a corresponding ".real_start_of" label. We check
2710 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2711 the ".real_start_of" convention for nonlocal branches. */
2712 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2715 real_start = ACONCAT ((STUB_NAME, name, NULL));
2716 new_target = symbol_find (real_start);
2718 if (new_target == NULL)
2720 as_warn (_("Failed to find real start of function: %s\n"), name);
2721 new_target = symbolP;
2729 opcode_select (int width)
2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2737 as_bad (_("selected processor does not support THUMB opcodes"));
2740 /* No need to force the alignment, since we will have been
2741 coming from ARM mode, which is word-aligned. */
2742 record_alignment (now_seg, 1);
2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2750 as_bad (_("selected processor does not support ARM opcodes"));
2755 frag_align (2, 0, 0);
2757 record_alignment (now_seg, 1);
2762 as_bad (_("invalid instruction size selected (%d)"), width);
2767 s_arm (int ignore ATTRIBUTE_UNUSED)
2770 demand_empty_rest_of_line ();
2774 s_thumb (int ignore ATTRIBUTE_UNUSED)
2777 demand_empty_rest_of_line ();
2781 s_code (int unused ATTRIBUTE_UNUSED)
2785 temp = get_absolute_expression ();
2790 opcode_select (temp);
2794 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2799 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2801 /* If we are not already in thumb mode go into it, EVEN if
2802 the target processor does not support thumb instructions.
2803 This is used by gcc/config/arm/lib1funcs.asm for example
2804 to compile interworking support functions even if the
2805 target processor should not support interworking. */
2809 record_alignment (now_seg, 1);
2812 demand_empty_rest_of_line ();
2816 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2820 /* The following label is the name/address of the start of a Thumb function.
2821 We need to know this for the interworking support. */
2822 label_is_thumb_function_name = TRUE;
2825 /* Perform a .set directive, but also mark the alias as
2826 being a thumb function. */
2829 s_thumb_set (int equiv)
2831 /* XXX the following is a duplicate of the code for s_set() in read.c
2832 We cannot just call that code as we need to get at the symbol that
2839 /* Especial apologies for the random logic:
2840 This just grew, and could be parsed much more simply!
2842 name = input_line_pointer;
2843 delim = get_symbol_end ();
2844 end_name = input_line_pointer;
2847 if (*input_line_pointer != ',')
2850 as_bad (_("expected comma after name \"%s\""), name);
2852 ignore_rest_of_line ();
2856 input_line_pointer++;
2859 if (name[0] == '.' && name[1] == '\0')
2861 /* XXX - this should not happen to .thumb_set. */
2865 if ((symbolP = symbol_find (name)) == NULL
2866 && (symbolP = md_undefined_symbol (name)) == NULL)
2869 /* When doing symbol listings, play games with dummy fragments living
2870 outside the normal fragment chain to record the file and line info
2872 if (listing & LISTING_SYMBOLS)
2874 extern struct list_info_struct * listing_tail;
2875 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2877 memset (dummy_frag, 0, sizeof (fragS));
2878 dummy_frag->fr_type = rs_fill;
2879 dummy_frag->line = listing_tail;
2880 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2881 dummy_frag->fr_symbol = symbolP;
2885 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2888 /* "set" symbols are local unless otherwise specified. */
2889 SF_SET_LOCAL (symbolP);
2890 #endif /* OBJ_COFF */
2891 } /* Make a new symbol. */
2893 symbol_table_insert (symbolP);
2898 && S_IS_DEFINED (symbolP)
2899 && S_GET_SEGMENT (symbolP) != reg_section)
2900 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2902 pseudo_set (symbolP);
2904 demand_empty_rest_of_line ();
2906 /* XXX Now we come to the Thumb specific bit of code. */
2908 THUMB_SET_FUNC (symbolP, 1);
2909 ARM_SET_THUMB (symbolP, 1);
2910 #if defined OBJ_ELF || defined OBJ_COFF
2911 ARM_SET_INTERWORK (symbolP, support_interwork);
2915 /* Directives: Mode selection. */
2917 /* .syntax [unified|divided] - choose the new unified syntax
2918 (same for Arm and Thumb encoding, modulo slight differences in what
2919 can be represented) or the old divergent syntax for each mode. */
2921 s_syntax (int unused ATTRIBUTE_UNUSED)
2925 name = input_line_pointer;
2926 delim = get_symbol_end ();
2928 if (!strcasecmp (name, "unified"))
2929 unified_syntax = TRUE;
2930 else if (!strcasecmp (name, "divided"))
2931 unified_syntax = FALSE;
2934 as_bad (_("unrecognized syntax mode \"%s\""), name);
2937 *input_line_pointer = delim;
2938 demand_empty_rest_of_line ();
2941 /* Directives: sectioning and alignment. */
2943 /* Same as s_align_ptwo but align 0 => align 2. */
2946 s_align (int unused ATTRIBUTE_UNUSED)
2951 long max_alignment = 15;
2953 temp = get_absolute_expression ();
2954 if (temp > max_alignment)
2955 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2958 as_bad (_("alignment negative. 0 assumed."));
2962 if (*input_line_pointer == ',')
2964 input_line_pointer++;
2965 temp_fill = get_absolute_expression ();
2977 /* Only make a frag if we HAVE to. */
2978 if (temp && !need_pass_2)
2980 if (!fill_p && subseg_text_p (now_seg))
2981 frag_align_code (temp, 0);
2983 frag_align (temp, (int) temp_fill, 0);
2985 demand_empty_rest_of_line ();
2987 record_alignment (now_seg, temp);
2991 s_bss (int ignore ATTRIBUTE_UNUSED)
2993 /* We don't support putting frags in the BSS segment, we fake it by
2994 marking in_bss, then looking at s_skip for clues. */
2995 subseg_set (bss_section, 0);
2996 demand_empty_rest_of_line ();
2998 #ifdef md_elf_section_change_hook
2999 md_elf_section_change_hook ();
3004 s_even (int ignore ATTRIBUTE_UNUSED)
3006 /* Never make frag if expect extra pass. */
3008 frag_align (1, 0, 0);
3010 record_alignment (now_seg, 1);
3012 demand_empty_rest_of_line ();
3015 /* Directives: Literal pools. */
3017 static literal_pool *
3018 find_literal_pool (void)
3020 literal_pool * pool;
3022 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3024 if (pool->section == now_seg
3025 && pool->sub_section == now_subseg)
3032 static literal_pool *
3033 find_or_make_literal_pool (void)
3035 /* Next literal pool ID number. */
3036 static unsigned int latest_pool_num = 1;
3037 literal_pool * pool;
3039 pool = find_literal_pool ();
3043 /* Create a new pool. */
3044 pool = (literal_pool *) xmalloc (sizeof (* pool));
3048 pool->next_free_entry = 0;
3049 pool->section = now_seg;
3050 pool->sub_section = now_subseg;
3051 pool->next = list_of_pools;
3052 pool->symbol = NULL;
3054 /* Add it to the list. */
3055 list_of_pools = pool;
3058 /* New pools, and emptied pools, will have a NULL symbol. */
3059 if (pool->symbol == NULL)
3061 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3062 (valueT) 0, &zero_address_frag);
3063 pool->id = latest_pool_num ++;
3070 /* Add the literal in the global 'inst'
3071 structure to the relevant literal pool. */
3074 add_to_lit_pool (void)
3076 literal_pool * pool;
3079 pool = find_or_make_literal_pool ();
3081 /* Check if this literal value is already in the pool. */
3082 for (entry = 0; entry < pool->next_free_entry; entry ++)
3084 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3085 && (inst.reloc.exp.X_op == O_constant)
3086 && (pool->literals[entry].X_add_number
3087 == inst.reloc.exp.X_add_number)
3088 && (pool->literals[entry].X_unsigned
3089 == inst.reloc.exp.X_unsigned))
3092 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3093 && (inst.reloc.exp.X_op == O_symbol)
3094 && (pool->literals[entry].X_add_number
3095 == inst.reloc.exp.X_add_number)
3096 && (pool->literals[entry].X_add_symbol
3097 == inst.reloc.exp.X_add_symbol)
3098 && (pool->literals[entry].X_op_symbol
3099 == inst.reloc.exp.X_op_symbol))
3103 /* Do we need to create a new entry? */
3104 if (entry == pool->next_free_entry)
3106 if (entry >= MAX_LITERAL_POOL_SIZE)
3108 inst.error = _("literal pool overflow");
3112 pool->literals[entry] = inst.reloc.exp;
3114 /* PR ld/12974: Record the location of the first source line to reference
3115 this entry in the literal pool. If it turns out during linking that the
3116 symbol does not exist we will be able to give an accurate line number for
3117 the (first use of the) missing reference. */
3118 if (debug_type == DEBUG_DWARF2)
3119 dwarf2_where (pool->locs + entry);
3121 pool->next_free_entry += 1;
3124 inst.reloc.exp.X_op = O_symbol;
3125 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3126 inst.reloc.exp.X_add_symbol = pool->symbol;
3131 /* Can't use symbol_new here, so have to create a symbol and then at
3132 a later date assign it a value. Thats what these functions do. */
3135 symbol_locate (symbolS * symbolP,
3136 const char * name, /* It is copied, the caller can modify. */
3137 segT segment, /* Segment identifier (SEG_<something>). */
3138 valueT valu, /* Symbol value. */
3139 fragS * frag) /* Associated fragment. */
3141 unsigned int name_length;
3142 char * preserved_copy_of_name;
3144 name_length = strlen (name) + 1; /* +1 for \0. */
3145 obstack_grow (¬es, name, name_length);
3146 preserved_copy_of_name = (char *) obstack_finish (¬es);
3148 #ifdef tc_canonicalize_symbol_name
3149 preserved_copy_of_name =
3150 tc_canonicalize_symbol_name (preserved_copy_of_name);
3153 S_SET_NAME (symbolP, preserved_copy_of_name);
3155 S_SET_SEGMENT (symbolP, segment);
3156 S_SET_VALUE (symbolP, valu);
3157 symbol_clear_list_pointers (symbolP);
3159 symbol_set_frag (symbolP, frag);
3161 /* Link to end of symbol chain. */
3163 extern int symbol_table_frozen;
3165 if (symbol_table_frozen)
3169 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3171 obj_symbol_new_hook (symbolP);
3173 #ifdef tc_symbol_new_hook
3174 tc_symbol_new_hook (symbolP);
3178 verify_symbol_chain (symbol_rootP, symbol_lastP);
3179 #endif /* DEBUG_SYMS */
3184 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3187 literal_pool * pool;
3190 pool = find_literal_pool ();
3192 || pool->symbol == NULL
3193 || pool->next_free_entry == 0)
3196 mapping_state (MAP_DATA);
3198 /* Align pool as you have word accesses.
3199 Only make a frag if we have to. */
3201 frag_align (2, 0, 0);
3203 record_alignment (now_seg, 2);
3205 sprintf (sym_name, "$$lit_\002%x", pool->id);
3207 symbol_locate (pool->symbol, sym_name, now_seg,
3208 (valueT) frag_now_fix (), frag_now);
3209 symbol_table_insert (pool->symbol);
3211 ARM_SET_THUMB (pool->symbol, thumb_mode);
3213 #if defined OBJ_COFF || defined OBJ_ELF
3214 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3217 for (entry = 0; entry < pool->next_free_entry; entry ++)
3220 if (debug_type == DEBUG_DWARF2)
3221 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3223 /* First output the expression in the instruction to the pool. */
3224 emit_expr (&(pool->literals[entry]), 4); /* .word */
3227 /* Mark the pool as empty. */
3228 pool->next_free_entry = 0;
3229 pool->symbol = NULL;
3233 /* Forward declarations for functions below, in the MD interface
3235 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3236 static valueT create_unwind_entry (int);
3237 static void start_unwind_section (const segT, int);
3238 static void add_unwind_opcode (valueT, int);
3239 static void flush_pending_unwind (void);
3241 /* Directives: Data. */
3244 s_arm_elf_cons (int nbytes)
3248 #ifdef md_flush_pending_output
3249 md_flush_pending_output ();
3252 if (is_it_end_of_statement ())
3254 demand_empty_rest_of_line ();
3258 #ifdef md_cons_align
3259 md_cons_align (nbytes);
3262 mapping_state (MAP_DATA);
3266 char *base = input_line_pointer;
3270 if (exp.X_op != O_symbol)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 char *before_reloc = input_line_pointer;
3275 reloc = parse_reloc (&input_line_pointer);
3278 as_bad (_("unrecognized relocation suffix"));
3279 ignore_rest_of_line ();
3282 else if (reloc == BFD_RELOC_UNUSED)
3283 emit_expr (&exp, (unsigned int) nbytes);
3286 reloc_howto_type *howto = (reloc_howto_type *)
3287 bfd_reloc_type_lookup (stdoutput,
3288 (bfd_reloc_code_real_type) reloc);
3289 int size = bfd_get_reloc_size (howto);
3291 if (reloc == BFD_RELOC_ARM_PLT32)
3293 as_bad (_("(plt) is only valid on branch targets"));
3294 reloc = BFD_RELOC_UNUSED;
3299 as_bad (_("%s relocations do not fit in %d bytes"),
3300 howto->name, nbytes);
3303 /* We've parsed an expression stopping at O_symbol.
3304 But there may be more expression left now that we
3305 have parsed the relocation marker. Parse it again.
3306 XXX Surely there is a cleaner way to do this. */
3307 char *p = input_line_pointer;
3309 char *save_buf = (char *) alloca (input_line_pointer - base);
3310 memcpy (save_buf, base, input_line_pointer - base);
3311 memmove (base + (input_line_pointer - before_reloc),
3312 base, before_reloc - base);
3314 input_line_pointer = base + (input_line_pointer-before_reloc);
3316 memcpy (base, save_buf, p - base);
3318 offset = nbytes - size;
3319 p = frag_more ((int) nbytes);
3320 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3321 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3326 while (*input_line_pointer++ == ',');
3328 /* Put terminator back into stream. */
3329 input_line_pointer --;
3330 demand_empty_rest_of_line ();
3333 /* Emit an expression containing a 32-bit thumb instruction.
3334 Implementation based on put_thumb32_insn. */
3337 emit_thumb32_expr (expressionS * exp)
3339 expressionS exp_high = *exp;
3341 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3342 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3343 exp->X_add_number &= 0xffff;
3344 emit_expr (exp, (unsigned int) THUMB_SIZE);
3347 /* Guess the instruction size based on the opcode. */
3350 thumb_insn_size (int opcode)
3352 if ((unsigned int) opcode < 0xe800u)
3354 else if ((unsigned int) opcode >= 0xe8000000u)
3361 emit_insn (expressionS *exp, int nbytes)
3365 if (exp->X_op == O_constant)
3370 size = thumb_insn_size (exp->X_add_number);
3374 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3376 as_bad (_(".inst.n operand too big. "\
3377 "Use .inst.w instead"));
3382 if (now_it.state == AUTOMATIC_IT_BLOCK)
3383 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3385 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3387 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3388 emit_thumb32_expr (exp);
3390 emit_expr (exp, (unsigned int) size);
3392 it_fsm_post_encode ();
3396 as_bad (_("cannot determine Thumb instruction size. " \
3397 "Use .inst.n/.inst.w instead"));
3400 as_bad (_("constant expression required"));
3405 /* Like s_arm_elf_cons but do not use md_cons_align and
3406 set the mapping state to MAP_ARM/MAP_THUMB. */
3409 s_arm_elf_inst (int nbytes)
3411 if (is_it_end_of_statement ())
3413 demand_empty_rest_of_line ();
3417 /* Calling mapping_state () here will not change ARM/THUMB,
3418 but will ensure not to be in DATA state. */
3421 mapping_state (MAP_THUMB);
3426 as_bad (_("width suffixes are invalid in ARM mode"));
3427 ignore_rest_of_line ();
3433 mapping_state (MAP_ARM);
3442 if (! emit_insn (& exp, nbytes))
3444 ignore_rest_of_line ();
3448 while (*input_line_pointer++ == ',');
3450 /* Put terminator back into stream. */
3451 input_line_pointer --;
3452 demand_empty_rest_of_line ();
3455 /* Parse a .rel31 directive. */
3458 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3465 if (*input_line_pointer == '1')
3466 highbit = 0x80000000;
3467 else if (*input_line_pointer != '0')
3468 as_bad (_("expected 0 or 1"));
3470 input_line_pointer++;
3471 if (*input_line_pointer != ',')
3472 as_bad (_("missing comma"));
3473 input_line_pointer++;
3475 #ifdef md_flush_pending_output
3476 md_flush_pending_output ();
3479 #ifdef md_cons_align
3483 mapping_state (MAP_DATA);
3488 md_number_to_chars (p, highbit, 4);
3489 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3490 BFD_RELOC_ARM_PREL31);
3492 demand_empty_rest_of_line ();
3495 /* Directives: AEABI stack-unwind tables. */
3497 /* Parse an unwind_fnstart directive. Simply records the current location. */
3500 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3502 demand_empty_rest_of_line ();
3503 if (unwind.proc_start)
3505 as_bad (_("duplicate .fnstart directive"));
3509 /* Mark the start of the function. */
3510 unwind.proc_start = expr_build_dot ();
3512 /* Reset the rest of the unwind info. */
3513 unwind.opcode_count = 0;
3514 unwind.table_entry = NULL;
3515 unwind.personality_routine = NULL;
3516 unwind.personality_index = -1;
3517 unwind.frame_size = 0;
3518 unwind.fp_offset = 0;
3519 unwind.fp_reg = REG_SP;
3521 unwind.sp_restored = 0;
3525 /* Parse a handlerdata directive. Creates the exception handling table entry
3526 for the function. */
3529 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3531 demand_empty_rest_of_line ();
3532 if (!unwind.proc_start)
3533 as_bad (MISSING_FNSTART);
3535 if (unwind.table_entry)
3536 as_bad (_("duplicate .handlerdata directive"));
3538 create_unwind_entry (1);
3541 /* Parse an unwind_fnend directive. Generates the index table entry. */
3544 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3549 unsigned int marked_pr_dependency;
3551 demand_empty_rest_of_line ();
3553 if (!unwind.proc_start)
3555 as_bad (_(".fnend directive without .fnstart"));
3559 /* Add eh table entry. */
3560 if (unwind.table_entry == NULL)
3561 val = create_unwind_entry (0);
3565 /* Add index table entry. This is two words. */
3566 start_unwind_section (unwind.saved_seg, 1);
3567 frag_align (2, 0, 0);
3568 record_alignment (now_seg, 2);
3570 ptr = frag_more (8);
3572 where = frag_now_fix () - 8;
3574 /* Self relative offset of the function start. */
3575 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3576 BFD_RELOC_ARM_PREL31);
3578 /* Indicate dependency on EHABI-defined personality routines to the
3579 linker, if it hasn't been done already. */
3580 marked_pr_dependency
3581 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3582 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3583 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3585 static const char *const name[] =
3587 "__aeabi_unwind_cpp_pr0",
3588 "__aeabi_unwind_cpp_pr1",
3589 "__aeabi_unwind_cpp_pr2"
3591 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3592 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3593 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3594 |= 1 << unwind.personality_index;
3598 /* Inline exception table entry. */
3599 md_number_to_chars (ptr + 4, val, 4);
3601 /* Self relative offset of the table entry. */
3602 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3603 BFD_RELOC_ARM_PREL31);
3605 /* Restore the original section. */
3606 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3608 unwind.proc_start = NULL;
3612 /* Parse an unwind_cantunwind directive. */
3615 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3617 demand_empty_rest_of_line ();
3618 if (!unwind.proc_start)
3619 as_bad (MISSING_FNSTART);
3621 if (unwind.personality_routine || unwind.personality_index != -1)
3622 as_bad (_("personality routine specified for cantunwind frame"));
3624 unwind.personality_index = -2;
3628 /* Parse a personalityindex directive. */
3631 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3635 if (!unwind.proc_start)
3636 as_bad (MISSING_FNSTART);
3638 if (unwind.personality_routine || unwind.personality_index != -1)
3639 as_bad (_("duplicate .personalityindex directive"));
3643 if (exp.X_op != O_constant
3644 || exp.X_add_number < 0 || exp.X_add_number > 15)
3646 as_bad (_("bad personality routine number"));
3647 ignore_rest_of_line ();
3651 unwind.personality_index = exp.X_add_number;
3653 demand_empty_rest_of_line ();
3657 /* Parse a personality directive. */
3660 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3664 if (!unwind.proc_start)
3665 as_bad (MISSING_FNSTART);
3667 if (unwind.personality_routine || unwind.personality_index != -1)
3668 as_bad (_("duplicate .personality directive"));
3670 name = input_line_pointer;
3671 c = get_symbol_end ();
3672 p = input_line_pointer;
3673 unwind.personality_routine = symbol_find_or_make (name);
3675 demand_empty_rest_of_line ();
3679 /* Parse a directive saving core registers. */
3682 s_arm_unwind_save_core (void)
3688 range = parse_reg_list (&input_line_pointer);
3691 as_bad (_("expected register list"));
3692 ignore_rest_of_line ();
3696 demand_empty_rest_of_line ();
3698 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3699 into .unwind_save {..., sp...}. We aren't bothered about the value of
3700 ip because it is clobbered by calls. */
3701 if (unwind.sp_restored && unwind.fp_reg == 12
3702 && (range & 0x3000) == 0x1000)
3704 unwind.opcode_count--;
3705 unwind.sp_restored = 0;
3706 range = (range | 0x2000) & ~0x1000;
3707 unwind.pending_offset = 0;
3713 /* See if we can use the short opcodes. These pop a block of up to 8
3714 registers starting with r4, plus maybe r14. */
3715 for (n = 0; n < 8; n++)
3717 /* Break at the first non-saved register. */
3718 if ((range & (1 << (n + 4))) == 0)
3721 /* See if there are any other bits set. */
3722 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3724 /* Use the long form. */
3725 op = 0x8000 | ((range >> 4) & 0xfff);
3726 add_unwind_opcode (op, 2);
3730 /* Use the short form. */
3732 op = 0xa8; /* Pop r14. */
3734 op = 0xa0; /* Do not pop r14. */
3736 add_unwind_opcode (op, 1);
3743 op = 0xb100 | (range & 0xf);
3744 add_unwind_opcode (op, 2);
3747 /* Record the number of bytes pushed. */
3748 for (n = 0; n < 16; n++)
3750 if (range & (1 << n))
3751 unwind.frame_size += 4;
3756 /* Parse a directive saving FPA registers. */
3759 s_arm_unwind_save_fpa (int reg)
3765 /* Get Number of registers to transfer. */
3766 if (skip_past_comma (&input_line_pointer) != FAIL)
3769 exp.X_op = O_illegal;
3771 if (exp.X_op != O_constant)
3773 as_bad (_("expected , <constant>"));
3774 ignore_rest_of_line ();
3778 num_regs = exp.X_add_number;
3780 if (num_regs < 1 || num_regs > 4)
3782 as_bad (_("number of registers must be in the range [1:4]"));
3783 ignore_rest_of_line ();
3787 demand_empty_rest_of_line ();
3792 op = 0xb4 | (num_regs - 1);
3793 add_unwind_opcode (op, 1);
3798 op = 0xc800 | (reg << 4) | (num_regs - 1);
3799 add_unwind_opcode (op, 2);
3801 unwind.frame_size += num_regs * 12;
3805 /* Parse a directive saving VFP registers for ARMv6 and above. */
3808 s_arm_unwind_save_vfp_armv6 (void)
3813 int num_vfpv3_regs = 0;
3814 int num_regs_below_16;
3816 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3819 as_bad (_("expected register list"));
3820 ignore_rest_of_line ();
3824 demand_empty_rest_of_line ();
3826 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3827 than FSTMX/FLDMX-style ones). */
3829 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3831 num_vfpv3_regs = count;
3832 else if (start + count > 16)
3833 num_vfpv3_regs = start + count - 16;
3835 if (num_vfpv3_regs > 0)
3837 int start_offset = start > 16 ? start - 16 : 0;
3838 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3839 add_unwind_opcode (op, 2);
3842 /* Generate opcode for registers numbered in the range 0 .. 15. */
3843 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3844 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3845 if (num_regs_below_16 > 0)
3847 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3848 add_unwind_opcode (op, 2);
3851 unwind.frame_size += count * 8;
3855 /* Parse a directive saving VFP registers for pre-ARMv6. */
3858 s_arm_unwind_save_vfp (void)
3864 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3867 as_bad (_("expected register list"));
3868 ignore_rest_of_line ();
3872 demand_empty_rest_of_line ();
3877 op = 0xb8 | (count - 1);
3878 add_unwind_opcode (op, 1);
3883 op = 0xb300 | (reg << 4) | (count - 1);
3884 add_unwind_opcode (op, 2);
3886 unwind.frame_size += count * 8 + 4;
3890 /* Parse a directive saving iWMMXt data registers. */
3893 s_arm_unwind_save_mmxwr (void)
3901 if (*input_line_pointer == '{')
3902 input_line_pointer++;
3906 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3910 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 as_tsktsk (_("register list not in ascending order"));
3918 if (*input_line_pointer == '-')
3920 input_line_pointer++;
3921 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3924 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3927 else if (reg >= hi_reg)
3929 as_bad (_("bad register range"));
3932 for (; reg < hi_reg; reg++)
3936 while (skip_past_comma (&input_line_pointer) != FAIL);
3938 skip_past_char (&input_line_pointer, '}');
3940 demand_empty_rest_of_line ();
3942 /* Generate any deferred opcodes because we're going to be looking at
3944 flush_pending_unwind ();
3946 for (i = 0; i < 16; i++)
3948 if (mask & (1 << i))
3949 unwind.frame_size += 8;
3952 /* Attempt to combine with a previous opcode. We do this because gcc
3953 likes to output separate unwind directives for a single block of
3955 if (unwind.opcode_count > 0)
3957 i = unwind.opcodes[unwind.opcode_count - 1];
3958 if ((i & 0xf8) == 0xc0)
3961 /* Only merge if the blocks are contiguous. */
3964 if ((mask & 0xfe00) == (1 << 9))
3966 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3967 unwind.opcode_count--;
3970 else if (i == 6 && unwind.opcode_count >= 2)
3972 i = unwind.opcodes[unwind.opcode_count - 2];
3976 op = 0xffff << (reg - 1);
3978 && ((mask & op) == (1u << (reg - 1))))
3980 op = (1 << (reg + i + 1)) - 1;
3981 op &= ~((1 << reg) - 1);
3983 unwind.opcode_count -= 2;
3990 /* We want to generate opcodes in the order the registers have been
3991 saved, ie. descending order. */
3992 for (reg = 15; reg >= -1; reg--)
3994 /* Save registers in blocks. */
3996 || !(mask & (1 << reg)))
3998 /* We found an unsaved reg. Generate opcodes to save the
4005 op = 0xc0 | (hi_reg - 10);
4006 add_unwind_opcode (op, 1);
4011 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4012 add_unwind_opcode (op, 2);
4021 ignore_rest_of_line ();
4025 s_arm_unwind_save_mmxwcg (void)
4032 if (*input_line_pointer == '{')
4033 input_line_pointer++;
4035 skip_whitespace (input_line_pointer);
4039 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4043 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4049 as_tsktsk (_("register list not in ascending order"));
4052 if (*input_line_pointer == '-')
4054 input_line_pointer++;
4055 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4058 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4061 else if (reg >= hi_reg)
4063 as_bad (_("bad register range"));
4066 for (; reg < hi_reg; reg++)
4070 while (skip_past_comma (&input_line_pointer) != FAIL);
4072 skip_past_char (&input_line_pointer, '}');
4074 demand_empty_rest_of_line ();
4076 /* Generate any deferred opcodes because we're going to be looking at
4078 flush_pending_unwind ();
4080 for (reg = 0; reg < 16; reg++)
4082 if (mask & (1 << reg))
4083 unwind.frame_size += 4;
4086 add_unwind_opcode (op, 2);
4089 ignore_rest_of_line ();
4093 /* Parse an unwind_save directive.
4094 If the argument is non-zero, this is a .vsave directive. */
4097 s_arm_unwind_save (int arch_v6)
4100 struct reg_entry *reg;
4101 bfd_boolean had_brace = FALSE;
4103 if (!unwind.proc_start)
4104 as_bad (MISSING_FNSTART);
4106 /* Figure out what sort of save we have. */
4107 peek = input_line_pointer;
4115 reg = arm_reg_parse_multi (&peek);
4119 as_bad (_("register expected"));
4120 ignore_rest_of_line ();
4129 as_bad (_("FPA .unwind_save does not take a register list"));
4130 ignore_rest_of_line ();
4133 input_line_pointer = peek;
4134 s_arm_unwind_save_fpa (reg->number);
4137 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4140 s_arm_unwind_save_vfp_armv6 ();
4142 s_arm_unwind_save_vfp ();
4144 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4145 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4148 as_bad (_(".unwind_save does not support this kind of register"));
4149 ignore_rest_of_line ();
4154 /* Parse an unwind_movsp directive. */
4157 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4163 if (!unwind.proc_start)
4164 as_bad (MISSING_FNSTART);
4166 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4169 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4170 ignore_rest_of_line ();
4174 /* Optional constant. */
4175 if (skip_past_comma (&input_line_pointer) != FAIL)
4177 if (immediate_for_directive (&offset) == FAIL)
4183 demand_empty_rest_of_line ();
4185 if (reg == REG_SP || reg == REG_PC)
4187 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4191 if (unwind.fp_reg != REG_SP)
4192 as_bad (_("unexpected .unwind_movsp directive"));
4194 /* Generate opcode to restore the value. */
4196 add_unwind_opcode (op, 1);
4198 /* Record the information for later. */
4199 unwind.fp_reg = reg;
4200 unwind.fp_offset = unwind.frame_size - offset;
4201 unwind.sp_restored = 1;
4204 /* Parse an unwind_pad directive. */
4207 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4211 if (!unwind.proc_start)
4212 as_bad (MISSING_FNSTART);
4214 if (immediate_for_directive (&offset) == FAIL)
4219 as_bad (_("stack increment must be multiple of 4"));
4220 ignore_rest_of_line ();
4224 /* Don't generate any opcodes, just record the details for later. */
4225 unwind.frame_size += offset;
4226 unwind.pending_offset += offset;
4228 demand_empty_rest_of_line ();
4231 /* Parse an unwind_setfp directive. */
4234 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4240 if (!unwind.proc_start)
4241 as_bad (MISSING_FNSTART);
4243 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4244 if (skip_past_comma (&input_line_pointer) == FAIL)
4247 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4249 if (fp_reg == FAIL || sp_reg == FAIL)
4251 as_bad (_("expected <reg>, <reg>"));
4252 ignore_rest_of_line ();
4256 /* Optional constant. */
4257 if (skip_past_comma (&input_line_pointer) != FAIL)
4259 if (immediate_for_directive (&offset) == FAIL)
4265 demand_empty_rest_of_line ();
4267 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4269 as_bad (_("register must be either sp or set by a previous"
4270 "unwind_movsp directive"));
4274 /* Don't generate any opcodes, just record the information for later. */
4275 unwind.fp_reg = fp_reg;
4277 if (sp_reg == REG_SP)
4278 unwind.fp_offset = unwind.frame_size - offset;
4280 unwind.fp_offset -= offset;
4283 /* Parse an unwind_raw directive. */
4286 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4289 /* This is an arbitrary limit. */
4290 unsigned char op[16];
4293 if (!unwind.proc_start)
4294 as_bad (MISSING_FNSTART);
4297 if (exp.X_op == O_constant
4298 && skip_past_comma (&input_line_pointer) != FAIL)
4300 unwind.frame_size += exp.X_add_number;
4304 exp.X_op = O_illegal;
4306 if (exp.X_op != O_constant)
4308 as_bad (_("expected <offset>, <opcode>"));
4309 ignore_rest_of_line ();
4315 /* Parse the opcode. */
4320 as_bad (_("unwind opcode too long"));
4321 ignore_rest_of_line ();
4323 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4325 as_bad (_("invalid unwind opcode"));
4326 ignore_rest_of_line ();
4329 op[count++] = exp.X_add_number;
4331 /* Parse the next byte. */
4332 if (skip_past_comma (&input_line_pointer) == FAIL)
4338 /* Add the opcode bytes in reverse order. */
4340 add_unwind_opcode (op[count], 1);
4342 demand_empty_rest_of_line ();
4346 /* Parse a .eabi_attribute directive. */
4349 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4351 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4353 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4354 attributes_set_explicitly[tag] = 1;
4357 /* Emit a tls fix for the symbol. */
4360 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4364 #ifdef md_flush_pending_output
4365 md_flush_pending_output ();
4368 #ifdef md_cons_align
4372 /* Since we're just labelling the code, there's no need to define a
4375 p = obstack_next_free (&frchain_now->frch_obstack);
4376 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4377 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4378 : BFD_RELOC_ARM_TLS_DESCSEQ);
4380 #endif /* OBJ_ELF */
4382 static void s_arm_arch (int);
4383 static void s_arm_object_arch (int);
4384 static void s_arm_cpu (int);
4385 static void s_arm_fpu (int);
4386 static void s_arm_arch_extension (int);
4391 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4398 if (exp.X_op == O_symbol)
4399 exp.X_op = O_secrel;
4401 emit_expr (&exp, 4);
4403 while (*input_line_pointer++ == ',');
4405 input_line_pointer--;
4406 demand_empty_rest_of_line ();
4410 /* This table describes all the machine specific pseudo-ops the assembler
4411 has to support. The fields are:
4412 pseudo-op name without dot
4413 function to call to execute this pseudo-op
4414 Integer arg to pass to the function. */
4416 const pseudo_typeS md_pseudo_table[] =
4418 /* Never called because '.req' does not start a line. */
4419 { "req", s_req, 0 },
4420 /* Following two are likewise never called. */
4423 { "unreq", s_unreq, 0 },
4424 { "bss", s_bss, 0 },
4425 { "align", s_align, 0 },
4426 { "arm", s_arm, 0 },
4427 { "thumb", s_thumb, 0 },
4428 { "code", s_code, 0 },
4429 { "force_thumb", s_force_thumb, 0 },
4430 { "thumb_func", s_thumb_func, 0 },
4431 { "thumb_set", s_thumb_set, 0 },
4432 { "even", s_even, 0 },
4433 { "ltorg", s_ltorg, 0 },
4434 { "pool", s_ltorg, 0 },
4435 { "syntax", s_syntax, 0 },
4436 { "cpu", s_arm_cpu, 0 },
4437 { "arch", s_arm_arch, 0 },
4438 { "object_arch", s_arm_object_arch, 0 },
4439 { "fpu", s_arm_fpu, 0 },
4440 { "arch_extension", s_arm_arch_extension, 0 },
4442 { "word", s_arm_elf_cons, 4 },
4443 { "long", s_arm_elf_cons, 4 },
4444 { "inst.n", s_arm_elf_inst, 2 },
4445 { "inst.w", s_arm_elf_inst, 4 },
4446 { "inst", s_arm_elf_inst, 0 },
4447 { "rel31", s_arm_rel31, 0 },
4448 { "fnstart", s_arm_unwind_fnstart, 0 },
4449 { "fnend", s_arm_unwind_fnend, 0 },
4450 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4451 { "personality", s_arm_unwind_personality, 0 },
4452 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4453 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4454 { "save", s_arm_unwind_save, 0 },
4455 { "vsave", s_arm_unwind_save, 1 },
4456 { "movsp", s_arm_unwind_movsp, 0 },
4457 { "pad", s_arm_unwind_pad, 0 },
4458 { "setfp", s_arm_unwind_setfp, 0 },
4459 { "unwind_raw", s_arm_unwind_raw, 0 },
4460 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4461 { "tlsdescseq", s_arm_tls_descseq, 0 },
4465 /* These are used for dwarf. */
4469 /* These are used for dwarf2. */
4470 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4471 { "loc", dwarf2_directive_loc, 0 },
4472 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4474 { "extend", float_cons, 'x' },
4475 { "ldouble", float_cons, 'x' },
4476 { "packed", float_cons, 'p' },
4478 {"secrel32", pe_directive_secrel, 0},
4483 /* Parser functions used exclusively in instruction operands. */
4485 /* Generic immediate-value read function for use in insn parsing.
4486 STR points to the beginning of the immediate (the leading #);
4487 VAL receives the value; if the value is outside [MIN, MAX]
4488 issue an error. PREFIX_OPT is true if the immediate prefix is
4492 parse_immediate (char **str, int *val, int min, int max,
4493 bfd_boolean prefix_opt)
4496 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4497 if (exp.X_op != O_constant)
4499 inst.error = _("constant expression required");
4503 if (exp.X_add_number < min || exp.X_add_number > max)
4505 inst.error = _("immediate value out of range");
4509 *val = exp.X_add_number;
4513 /* Less-generic immediate-value read function with the possibility of loading a
4514 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4515 instructions. Puts the result directly in inst.operands[i]. */
4518 parse_big_immediate (char **str, int i)
4523 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4525 if (exp.X_op == O_constant)
4527 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4528 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4529 O_constant. We have to be careful not to break compilation for
4530 32-bit X_add_number, though. */
4531 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4533 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4534 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4535 inst.operands[i].regisimm = 1;
4538 else if (exp.X_op == O_big
4539 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4541 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4543 /* Bignums have their least significant bits in
4544 generic_bignum[0]. Make sure we put 32 bits in imm and
4545 32 bits in reg, in a (hopefully) portable way. */
4546 gas_assert (parts != 0);
4548 /* Make sure that the number is not too big.
4549 PR 11972: Bignums can now be sign-extended to the
4550 size of a .octa so check that the out of range bits
4551 are all zero or all one. */
4552 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4554 LITTLENUM_TYPE m = -1;
4556 if (generic_bignum[parts * 2] != 0
4557 && generic_bignum[parts * 2] != m)
4560 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4561 if (generic_bignum[j] != generic_bignum[j-1])
4565 inst.operands[i].imm = 0;
4566 for (j = 0; j < parts; j++, idx++)
4567 inst.operands[i].imm |= generic_bignum[idx]
4568 << (LITTLENUM_NUMBER_OF_BITS * j);
4569 inst.operands[i].reg = 0;
4570 for (j = 0; j < parts; j++, idx++)
4571 inst.operands[i].reg |= generic_bignum[idx]
4572 << (LITTLENUM_NUMBER_OF_BITS * j);
4573 inst.operands[i].regisimm = 1;
4583 /* Returns the pseudo-register number of an FPA immediate constant,
4584 or FAIL if there isn't a valid constant here. */
4587 parse_fpa_immediate (char ** str)
4589 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4595 /* First try and match exact strings, this is to guarantee
4596 that some formats will work even for cross assembly. */
4598 for (i = 0; fp_const[i]; i++)
4600 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4604 *str += strlen (fp_const[i]);
4605 if (is_end_of_line[(unsigned char) **str])
4611 /* Just because we didn't get a match doesn't mean that the constant
4612 isn't valid, just that it is in a format that we don't
4613 automatically recognize. Try parsing it with the standard
4614 expression routines. */
4616 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4618 /* Look for a raw floating point number. */
4619 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4620 && is_end_of_line[(unsigned char) *save_in])
4622 for (i = 0; i < NUM_FLOAT_VALS; i++)
4624 for (j = 0; j < MAX_LITTLENUMS; j++)
4626 if (words[j] != fp_values[i][j])
4630 if (j == MAX_LITTLENUMS)
4638 /* Try and parse a more complex expression, this will probably fail
4639 unless the code uses a floating point prefix (eg "0f"). */
4640 save_in = input_line_pointer;
4641 input_line_pointer = *str;
4642 if (expression (&exp) == absolute_section
4643 && exp.X_op == O_big
4644 && exp.X_add_number < 0)
4646 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4648 if (gen_to_words (words, 5, (long) 15) == 0)
4650 for (i = 0; i < NUM_FLOAT_VALS; i++)
4652 for (j = 0; j < MAX_LITTLENUMS; j++)
4654 if (words[j] != fp_values[i][j])
4658 if (j == MAX_LITTLENUMS)
4660 *str = input_line_pointer;
4661 input_line_pointer = save_in;
4668 *str = input_line_pointer;
4669 input_line_pointer = save_in;
4670 inst.error = _("invalid FPA immediate expression");
4674 /* Returns 1 if a number has "quarter-precision" float format
4675 0baBbbbbbc defgh000 00000000 00000000. */
4678 is_quarter_float (unsigned imm)
4680 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4681 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4684 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4685 0baBbbbbbc defgh000 00000000 00000000.
4686 The zero and minus-zero cases need special handling, since they can't be
4687 encoded in the "quarter-precision" float format, but can nonetheless be
4688 loaded as integer constants. */
4691 parse_qfloat_immediate (char **ccp, int *immed)
4695 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4696 int found_fpchar = 0;
4698 skip_past_char (&str, '#');
4700 /* We must not accidentally parse an integer as a floating-point number. Make
4701 sure that the value we parse is not an integer by checking for special
4702 characters '.' or 'e'.
4703 FIXME: This is a horrible hack, but doing better is tricky because type
4704 information isn't in a very usable state at parse time. */
4706 skip_whitespace (fpnum);
4708 if (strncmp (fpnum, "0x", 2) == 0)
4712 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4713 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4723 if ((str = atof_ieee (str, 's', words)) != NULL)
4725 unsigned fpword = 0;
4728 /* Our FP word must be 32 bits (single-precision FP). */
4729 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4731 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4735 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4748 /* Shift operands. */
4751 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4754 struct asm_shift_name
4757 enum shift_kind kind;
4760 /* Third argument to parse_shift. */
4761 enum parse_shift_mode
4763 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4764 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4765 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4766 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4767 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4770 /* Parse a <shift> specifier on an ARM data processing instruction.
4771 This has three forms:
4773 (LSL|LSR|ASL|ASR|ROR) Rs
4774 (LSL|LSR|ASL|ASR|ROR) #imm
4777 Note that ASL is assimilated to LSL in the instruction encoding, and
4778 RRX to ROR #0 (which cannot be written as such). */
4781 parse_shift (char **str, int i, enum parse_shift_mode mode)
4783 const struct asm_shift_name *shift_name;
4784 enum shift_kind shift;
4789 for (p = *str; ISALPHA (*p); p++)
4794 inst.error = _("shift expression expected");
4798 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4801 if (shift_name == NULL)
4803 inst.error = _("shift expression expected");
4807 shift = shift_name->kind;
4811 case NO_SHIFT_RESTRICT:
4812 case SHIFT_IMMEDIATE: break;
4814 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4815 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4817 inst.error = _("'LSL' or 'ASR' required");
4822 case SHIFT_LSL_IMMEDIATE:
4823 if (shift != SHIFT_LSL)
4825 inst.error = _("'LSL' required");
4830 case SHIFT_ASR_IMMEDIATE:
4831 if (shift != SHIFT_ASR)
4833 inst.error = _("'ASR' required");
4841 if (shift != SHIFT_RRX)
4843 /* Whitespace can appear here if the next thing is a bare digit. */
4844 skip_whitespace (p);
4846 if (mode == NO_SHIFT_RESTRICT
4847 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4849 inst.operands[i].imm = reg;
4850 inst.operands[i].immisreg = 1;
4852 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4855 inst.operands[i].shift_kind = shift;
4856 inst.operands[i].shifted = 1;
4861 /* Parse a <shifter_operand> for an ARM data processing instruction:
4864 #<immediate>, <rotate>
4868 where <shift> is defined by parse_shift above, and <rotate> is a
4869 multiple of 2 between 0 and 30. Validation of immediate operands
4870 is deferred to md_apply_fix. */
4873 parse_shifter_operand (char **str, int i)
4878 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4880 inst.operands[i].reg = value;
4881 inst.operands[i].isreg = 1;
4883 /* parse_shift will override this if appropriate */
4884 inst.reloc.exp.X_op = O_constant;
4885 inst.reloc.exp.X_add_number = 0;
4887 if (skip_past_comma (str) == FAIL)
4890 /* Shift operation on register. */
4891 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4894 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4897 if (skip_past_comma (str) == SUCCESS)
4899 /* #x, y -- ie explicit rotation by Y. */
4900 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4903 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4905 inst.error = _("constant expression expected");
4909 value = exp.X_add_number;
4910 if (value < 0 || value > 30 || value % 2 != 0)
4912 inst.error = _("invalid rotation");
4915 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4917 inst.error = _("invalid constant");
4921 /* Encode as specified. */
4922 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4926 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4927 inst.reloc.pc_rel = 0;
4931 /* Group relocation information. Each entry in the table contains the
4932 textual name of the relocation as may appear in assembler source
4933 and must end with a colon.
4934 Along with this textual name are the relocation codes to be used if
4935 the corresponding instruction is an ALU instruction (ADD or SUB only),
4936 an LDR, an LDRS, or an LDC. */
4938 struct group_reloc_table_entry
4949 /* Varieties of non-ALU group relocation. */
4956 static struct group_reloc_table_entry group_reloc_table[] =
4957 { /* Program counter relative: */
4959 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4964 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4965 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4966 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4967 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4969 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4974 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4975 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4976 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4977 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4979 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4980 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4981 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4982 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4983 /* Section base relative */
4985 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4990 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4991 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4992 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4993 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4995 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5000 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5001 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5002 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5003 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5005 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5006 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5007 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5008 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5010 /* Given the address of a pointer pointing to the textual name of a group
5011 relocation as may appear in assembler source, attempt to find its details
5012 in group_reloc_table. The pointer will be updated to the character after
5013 the trailing colon. On failure, FAIL will be returned; SUCCESS
5014 otherwise. On success, *entry will be updated to point at the relevant
5015 group_reloc_table entry. */
5018 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5021 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5023 int length = strlen (group_reloc_table[i].name);
5025 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5026 && (*str)[length] == ':')
5028 *out = &group_reloc_table[i];
5029 *str += (length + 1);
5037 /* Parse a <shifter_operand> for an ARM data processing instruction
5038 (as for parse_shifter_operand) where group relocations are allowed:
5041 #<immediate>, <rotate>
5042 #:<group_reloc>:<expression>
5046 where <group_reloc> is one of the strings defined in group_reloc_table.
5047 The hashes are optional.
5049 Everything else is as for parse_shifter_operand. */
5051 static parse_operand_result
5052 parse_shifter_operand_group_reloc (char **str, int i)
5054 /* Determine if we have the sequence of characters #: or just :
5055 coming next. If we do, then we check for a group relocation.
5056 If we don't, punt the whole lot to parse_shifter_operand. */
5058 if (((*str)[0] == '#' && (*str)[1] == ':')
5059 || (*str)[0] == ':')
5061 struct group_reloc_table_entry *entry;
5063 if ((*str)[0] == '#')
5068 /* Try to parse a group relocation. Anything else is an error. */
5069 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5071 inst.error = _("unknown group relocation");
5072 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5075 /* We now have the group relocation table entry corresponding to
5076 the name in the assembler source. Next, we parse the expression. */
5077 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5078 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5080 /* Record the relocation type (always the ALU variant here). */
5081 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5082 gas_assert (inst.reloc.type != 0);
5084 return PARSE_OPERAND_SUCCESS;
5087 return parse_shifter_operand (str, i) == SUCCESS
5088 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5090 /* Never reached. */
5093 /* Parse a Neon alignment expression. Information is written to
5094 inst.operands[i]. We assume the initial ':' has been skipped.
5096 align .imm = align << 8, .immisalign=1, .preind=0 */
5097 static parse_operand_result
5098 parse_neon_alignment (char **str, int i)
5103 my_get_expression (&exp, &p, GE_NO_PREFIX);
5105 if (exp.X_op != O_constant)
5107 inst.error = _("alignment must be constant");
5108 return PARSE_OPERAND_FAIL;
5111 inst.operands[i].imm = exp.X_add_number << 8;
5112 inst.operands[i].immisalign = 1;
5113 /* Alignments are not pre-indexes. */
5114 inst.operands[i].preind = 0;
5117 return PARSE_OPERAND_SUCCESS;
5120 /* Parse all forms of an ARM address expression. Information is written
5121 to inst.operands[i] and/or inst.reloc.
5123 Preindexed addressing (.preind=1):
5125 [Rn, #offset] .reg=Rn .reloc.exp=offset
5126 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5127 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5128 .shift_kind=shift .reloc.exp=shift_imm
5130 These three may have a trailing ! which causes .writeback to be set also.
5132 Postindexed addressing (.postind=1, .writeback=1):
5134 [Rn], #offset .reg=Rn .reloc.exp=offset
5135 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5136 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5137 .shift_kind=shift .reloc.exp=shift_imm
5139 Unindexed addressing (.preind=0, .postind=0):
5141 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5145 [Rn]{!} shorthand for [Rn,#0]{!}
5146 =immediate .isreg=0 .reloc.exp=immediate
5147 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5149 It is the caller's responsibility to check for addressing modes not
5150 supported by the instruction, and to set inst.reloc.type. */
5152 static parse_operand_result
5153 parse_address_main (char **str, int i, int group_relocations,
5154 group_reloc_type group_type)
5159 if (skip_past_char (&p, '[') == FAIL)
5161 if (skip_past_char (&p, '=') == FAIL)
5163 /* Bare address - translate to PC-relative offset. */
5164 inst.reloc.pc_rel = 1;
5165 inst.operands[i].reg = REG_PC;
5166 inst.operands[i].isreg = 1;
5167 inst.operands[i].preind = 1;
5169 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5171 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5172 return PARSE_OPERAND_FAIL;
5175 return PARSE_OPERAND_SUCCESS;
5178 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5179 skip_whitespace (p);
5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5183 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5184 return PARSE_OPERAND_FAIL;
5186 inst.operands[i].reg = reg;
5187 inst.operands[i].isreg = 1;
5189 if (skip_past_comma (&p) == SUCCESS)
5191 inst.operands[i].preind = 1;
5194 else if (*p == '-') p++, inst.operands[i].negative = 1;
5196 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5198 inst.operands[i].imm = reg;
5199 inst.operands[i].immisreg = 1;
5201 if (skip_past_comma (&p) == SUCCESS)
5202 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5203 return PARSE_OPERAND_FAIL;
5205 else if (skip_past_char (&p, ':') == SUCCESS)
5207 /* FIXME: '@' should be used here, but it's filtered out by generic
5208 code before we get to see it here. This may be subject to
5210 parse_operand_result result = parse_neon_alignment (&p, i);
5212 if (result != PARSE_OPERAND_SUCCESS)
5217 if (inst.operands[i].negative)
5219 inst.operands[i].negative = 0;
5223 if (group_relocations
5224 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5226 struct group_reloc_table_entry *entry;
5228 /* Skip over the #: or : sequence. */
5234 /* Try to parse a group relocation. Anything else is an
5236 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5238 inst.error = _("unknown group relocation");
5239 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5242 /* We now have the group relocation table entry corresponding to
5243 the name in the assembler source. Next, we parse the
5245 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5246 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5248 /* Record the relocation type. */
5252 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5256 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5260 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5267 if (inst.reloc.type == 0)
5269 inst.error = _("this group relocation is not allowed on this instruction");
5270 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5276 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5277 return PARSE_OPERAND_FAIL;
5278 /* If the offset is 0, find out if it's a +0 or -0. */
5279 if (inst.reloc.exp.X_op == O_constant
5280 && inst.reloc.exp.X_add_number == 0)
5282 skip_whitespace (q);
5286 skip_whitespace (q);
5289 inst.operands[i].negative = 1;
5294 else if (skip_past_char (&p, ':') == SUCCESS)
5296 /* FIXME: '@' should be used here, but it's filtered out by generic code
5297 before we get to see it here. This may be subject to change. */
5298 parse_operand_result result = parse_neon_alignment (&p, i);
5300 if (result != PARSE_OPERAND_SUCCESS)
5304 if (skip_past_char (&p, ']') == FAIL)
5306 inst.error = _("']' expected");
5307 return PARSE_OPERAND_FAIL;
5310 if (skip_past_char (&p, '!') == SUCCESS)
5311 inst.operands[i].writeback = 1;
5313 else if (skip_past_comma (&p) == SUCCESS)
5315 if (skip_past_char (&p, '{') == SUCCESS)
5317 /* [Rn], {expr} - unindexed, with option */
5318 if (parse_immediate (&p, &inst.operands[i].imm,
5319 0, 255, TRUE) == FAIL)
5320 return PARSE_OPERAND_FAIL;
5322 if (skip_past_char (&p, '}') == FAIL)
5324 inst.error = _("'}' expected at end of 'option' field");
5325 return PARSE_OPERAND_FAIL;
5327 if (inst.operands[i].preind)
5329 inst.error = _("cannot combine index with option");
5330 return PARSE_OPERAND_FAIL;
5333 return PARSE_OPERAND_SUCCESS;
5337 inst.operands[i].postind = 1;
5338 inst.operands[i].writeback = 1;
5340 if (inst.operands[i].preind)
5342 inst.error = _("cannot combine pre- and post-indexing");
5343 return PARSE_OPERAND_FAIL;
5347 else if (*p == '-') p++, inst.operands[i].negative = 1;
5349 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5351 /* We might be using the immediate for alignment already. If we
5352 are, OR the register number into the low-order bits. */
5353 if (inst.operands[i].immisalign)
5354 inst.operands[i].imm |= reg;
5356 inst.operands[i].imm = reg;
5357 inst.operands[i].immisreg = 1;
5359 if (skip_past_comma (&p) == SUCCESS)
5360 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5361 return PARSE_OPERAND_FAIL;
5366 if (inst.operands[i].negative)
5368 inst.operands[i].negative = 0;
5371 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5372 return PARSE_OPERAND_FAIL;
5373 /* If the offset is 0, find out if it's a +0 or -0. */
5374 if (inst.reloc.exp.X_op == O_constant
5375 && inst.reloc.exp.X_add_number == 0)
5377 skip_whitespace (q);
5381 skip_whitespace (q);
5384 inst.operands[i].negative = 1;
5390 /* If at this point neither .preind nor .postind is set, we have a
5391 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5392 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5394 inst.operands[i].preind = 1;
5395 inst.reloc.exp.X_op = O_constant;
5396 inst.reloc.exp.X_add_number = 0;
5399 return PARSE_OPERAND_SUCCESS;
5403 parse_address (char **str, int i)
5405 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5409 static parse_operand_result
5410 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5412 return parse_address_main (str, i, 1, type);
5415 /* Parse an operand for a MOVW or MOVT instruction. */
5417 parse_half (char **str)
5422 skip_past_char (&p, '#');
5423 if (strncasecmp (p, ":lower16:", 9) == 0)
5424 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5425 else if (strncasecmp (p, ":upper16:", 9) == 0)
5426 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5428 if (inst.reloc.type != BFD_RELOC_UNUSED)
5431 skip_whitespace (p);
5434 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5437 if (inst.reloc.type == BFD_RELOC_UNUSED)
5439 if (inst.reloc.exp.X_op != O_constant)
5441 inst.error = _("constant expression expected");
5444 if (inst.reloc.exp.X_add_number < 0
5445 || inst.reloc.exp.X_add_number > 0xffff)
5447 inst.error = _("immediate value out of range");
5455 /* Miscellaneous. */
5457 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5458 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5460 parse_psr (char **str, bfd_boolean lhs)
5463 unsigned long psr_field;
5464 const struct asm_psr *psr;
5466 bfd_boolean is_apsr = FALSE;
5467 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5469 /* PR gas/12698: If the user has specified -march=all then m_profile will
5470 be TRUE, but we want to ignore it in this case as we are building for any
5471 CPU type, including non-m variants. */
5472 if (selected_cpu.core == arm_arch_any.core)
5475 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5476 feature for ease of use and backwards compatibility. */
5478 if (strncasecmp (p, "SPSR", 4) == 0)
5481 goto unsupported_psr;
5483 psr_field = SPSR_BIT;
5485 else if (strncasecmp (p, "CPSR", 4) == 0)
5488 goto unsupported_psr;
5492 else if (strncasecmp (p, "APSR", 4) == 0)
5494 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5495 and ARMv7-R architecture CPUs. */
5504 while (ISALNUM (*p) || *p == '_');
5506 if (strncasecmp (start, "iapsr", 5) == 0
5507 || strncasecmp (start, "eapsr", 5) == 0
5508 || strncasecmp (start, "xpsr", 4) == 0
5509 || strncasecmp (start, "psr", 3) == 0)
5510 p = start + strcspn (start, "rR") + 1;
5512 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5518 /* If APSR is being written, a bitfield may be specified. Note that
5519 APSR itself is handled above. */
5520 if (psr->field <= 3)
5522 psr_field = psr->field;
5528 /* M-profile MSR instructions have the mask field set to "10", except
5529 *PSR variants which modify APSR, which may use a different mask (and
5530 have been handled already). Do that by setting the PSR_f field
5532 return psr->field | (lhs ? PSR_f : 0);
5535 goto unsupported_psr;
5541 /* A suffix follows. */
5547 while (ISALNUM (*p) || *p == '_');
5551 /* APSR uses a notation for bits, rather than fields. */
5552 unsigned int nzcvq_bits = 0;
5553 unsigned int g_bit = 0;
5556 for (bit = start; bit != p; bit++)
5558 switch (TOLOWER (*bit))
5561 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5565 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5569 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5573 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5577 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5581 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5585 inst.error = _("unexpected bit specified after APSR");
5590 if (nzcvq_bits == 0x1f)
5595 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5597 inst.error = _("selected processor does not "
5598 "support DSP extension");
5605 if ((nzcvq_bits & 0x20) != 0
5606 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5607 || (g_bit & 0x2) != 0)
5609 inst.error = _("bad bitmask specified after APSR");
5615 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5620 psr_field |= psr->field;
5626 goto error; /* Garbage after "[CS]PSR". */
5628 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5629 is deprecated, but allow it anyway. */
5633 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5636 else if (!m_profile)
5637 /* These bits are never right for M-profile devices: don't set them
5638 (only code paths which read/write APSR reach here). */
5639 psr_field |= (PSR_c | PSR_f);
5645 inst.error = _("selected processor does not support requested special "
5646 "purpose register");
5650 inst.error = _("flag for {c}psr instruction expected");
5654 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5655 value suitable for splatting into the AIF field of the instruction. */
5658 parse_cps_flags (char **str)
5667 case '\0': case ',':
5670 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5671 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5672 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5675 inst.error = _("unrecognized CPS flag");
5680 if (saw_a_flag == 0)
5682 inst.error = _("missing CPS flags");
5690 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5691 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5694 parse_endian_specifier (char **str)
5699 if (strncasecmp (s, "BE", 2))
5701 else if (strncasecmp (s, "LE", 2))
5705 inst.error = _("valid endian specifiers are be or le");
5709 if (ISALNUM (s[2]) || s[2] == '_')
5711 inst.error = _("valid endian specifiers are be or le");
5716 return little_endian;
5719 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5720 value suitable for poking into the rotate field of an sxt or sxta
5721 instruction, or FAIL on error. */
5724 parse_ror (char **str)
5729 if (strncasecmp (s, "ROR", 3) == 0)
5733 inst.error = _("missing rotation field after comma");
5737 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5742 case 0: *str = s; return 0x0;
5743 case 8: *str = s; return 0x1;
5744 case 16: *str = s; return 0x2;
5745 case 24: *str = s; return 0x3;
5748 inst.error = _("rotation can only be 0, 8, 16, or 24");
5753 /* Parse a conditional code (from conds[] below). The value returned is in the
5754 range 0 .. 14, or FAIL. */
5756 parse_cond (char **str)
5759 const struct asm_cond *c;
5761 /* Condition codes are always 2 characters, so matching up to
5762 3 characters is sufficient. */
5767 while (ISALPHA (*q) && n < 3)
5769 cond[n] = TOLOWER (*q);
5774 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5777 inst.error = _("condition required");
5785 /* If the given feature available in the selected CPU, mark it as used.
5786 Returns TRUE iff feature is available. */
5788 mark_feature_used (const arm_feature_set *feature)
5790 /* Ensure the option is valid on the current architecture. */
5791 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5794 /* Add the appropriate architecture feature for the barrier option used.
5797 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5799 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5804 /* Parse an option for a barrier instruction. Returns the encoding for the
5807 parse_barrier (char **str)
5810 const struct asm_barrier_opt *o;
5813 while (ISALPHA (*q))
5816 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5821 if (!mark_feature_used (&o->arch))
5828 /* Parse the operands of a table branch instruction. Similar to a memory
5831 parse_tb (char **str)
5836 if (skip_past_char (&p, '[') == FAIL)
5838 inst.error = _("'[' expected");
5842 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5844 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5847 inst.operands[0].reg = reg;
5849 if (skip_past_comma (&p) == FAIL)
5851 inst.error = _("',' expected");
5855 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5857 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5860 inst.operands[0].imm = reg;
5862 if (skip_past_comma (&p) == SUCCESS)
5864 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5866 if (inst.reloc.exp.X_add_number != 1)
5868 inst.error = _("invalid shift");
5871 inst.operands[0].shifted = 1;
5874 if (skip_past_char (&p, ']') == FAIL)
5876 inst.error = _("']' expected");
5883 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5884 information on the types the operands can take and how they are encoded.
5885 Up to four operands may be read; this function handles setting the
5886 ".present" field for each read operand itself.
5887 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5888 else returns FAIL. */
5891 parse_neon_mov (char **str, int *which_operand)
5893 int i = *which_operand, val;
5894 enum arm_reg_type rtype;
5896 struct neon_type_el optype;
5898 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5900 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5901 inst.operands[i].reg = val;
5902 inst.operands[i].isscalar = 1;
5903 inst.operands[i].vectype = optype;
5904 inst.operands[i++].present = 1;
5906 if (skip_past_comma (&ptr) == FAIL)
5909 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5912 inst.operands[i].reg = val;
5913 inst.operands[i].isreg = 1;
5914 inst.operands[i].present = 1;
5916 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5919 /* Cases 0, 1, 2, 3, 5 (D only). */
5920 if (skip_past_comma (&ptr) == FAIL)
5923 inst.operands[i].reg = val;
5924 inst.operands[i].isreg = 1;
5925 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5926 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5927 inst.operands[i].isvec = 1;
5928 inst.operands[i].vectype = optype;
5929 inst.operands[i++].present = 1;
5931 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5933 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5934 Case 13: VMOV <Sd>, <Rm> */
5935 inst.operands[i].reg = val;
5936 inst.operands[i].isreg = 1;
5937 inst.operands[i].present = 1;
5939 if (rtype == REG_TYPE_NQ)
5941 first_error (_("can't use Neon quad register here"));
5944 else if (rtype != REG_TYPE_VFS)
5947 if (skip_past_comma (&ptr) == FAIL)
5949 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5951 inst.operands[i].reg = val;
5952 inst.operands[i].isreg = 1;
5953 inst.operands[i].present = 1;
5956 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5959 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5960 Case 1: VMOV<c><q> <Dd>, <Dm>
5961 Case 8: VMOV.F32 <Sd>, <Sm>
5962 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5964 inst.operands[i].reg = val;
5965 inst.operands[i].isreg = 1;
5966 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5967 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5968 inst.operands[i].isvec = 1;
5969 inst.operands[i].vectype = optype;
5970 inst.operands[i].present = 1;
5972 if (skip_past_comma (&ptr) == SUCCESS)
5977 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5980 inst.operands[i].reg = val;
5981 inst.operands[i].isreg = 1;
5982 inst.operands[i++].present = 1;
5984 if (skip_past_comma (&ptr) == FAIL)
5987 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5990 inst.operands[i].reg = val;
5991 inst.operands[i].isreg = 1;
5992 inst.operands[i].present = 1;
5995 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5996 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5997 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5998 Case 10: VMOV.F32 <Sd>, #<imm>
5999 Case 11: VMOV.F64 <Dd>, #<imm> */
6000 inst.operands[i].immisfloat = 1;
6001 else if (parse_big_immediate (&ptr, i) == SUCCESS)
6002 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6003 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6007 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6011 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6014 inst.operands[i].reg = val;
6015 inst.operands[i].isreg = 1;
6016 inst.operands[i++].present = 1;
6018 if (skip_past_comma (&ptr) == FAIL)
6021 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6023 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6024 inst.operands[i].reg = val;
6025 inst.operands[i].isscalar = 1;
6026 inst.operands[i].present = 1;
6027 inst.operands[i].vectype = optype;
6029 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6031 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6032 inst.operands[i].reg = val;
6033 inst.operands[i].isreg = 1;
6034 inst.operands[i++].present = 1;
6036 if (skip_past_comma (&ptr) == FAIL)
6039 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6042 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6046 inst.operands[i].reg = val;
6047 inst.operands[i].isreg = 1;
6048 inst.operands[i].isvec = 1;
6049 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6050 inst.operands[i].vectype = optype;
6051 inst.operands[i].present = 1;
6053 if (rtype == REG_TYPE_VFS)
6057 if (skip_past_comma (&ptr) == FAIL)
6059 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6062 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6065 inst.operands[i].reg = val;
6066 inst.operands[i].isreg = 1;
6067 inst.operands[i].isvec = 1;
6068 inst.operands[i].issingle = 1;
6069 inst.operands[i].vectype = optype;
6070 inst.operands[i].present = 1;
6073 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6077 inst.operands[i].reg = val;
6078 inst.operands[i].isreg = 1;
6079 inst.operands[i].isvec = 1;
6080 inst.operands[i].issingle = 1;
6081 inst.operands[i].vectype = optype;
6082 inst.operands[i].present = 1;
6087 first_error (_("parse error"));
6091 /* Successfully parsed the operands. Update args. */
6097 first_error (_("expected comma"));
6101 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6105 /* Use this macro when the operand constraints are different
6106 for ARM and THUMB (e.g. ldrd). */
6107 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6108 ((arm_operand) | ((thumb_operand) << 16))
6110 /* Matcher codes for parse_operands. */
6111 enum operand_parse_code
6113 OP_stop, /* end of line */
6115 OP_RR, /* ARM register */
6116 OP_RRnpc, /* ARM register, not r15 */
6117 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6118 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6119 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6120 optional trailing ! */
6121 OP_RRw, /* ARM register, not r15, optional trailing ! */
6122 OP_RCP, /* Coprocessor number */
6123 OP_RCN, /* Coprocessor register */
6124 OP_RF, /* FPA register */
6125 OP_RVS, /* VFP single precision register */
6126 OP_RVD, /* VFP double precision register (0..15) */
6127 OP_RND, /* Neon double precision register (0..31) */
6128 OP_RNQ, /* Neon quad precision register */
6129 OP_RVSD, /* VFP single or double precision register */
6130 OP_RNDQ, /* Neon double or quad precision register */
6131 OP_RNSDQ, /* Neon single, double or quad precision register */
6132 OP_RNSC, /* Neon scalar D[X] */
6133 OP_RVC, /* VFP control register */
6134 OP_RMF, /* Maverick F register */
6135 OP_RMD, /* Maverick D register */
6136 OP_RMFX, /* Maverick FX register */
6137 OP_RMDX, /* Maverick DX register */
6138 OP_RMAX, /* Maverick AX register */
6139 OP_RMDS, /* Maverick DSPSC register */
6140 OP_RIWR, /* iWMMXt wR register */
6141 OP_RIWC, /* iWMMXt wC register */
6142 OP_RIWG, /* iWMMXt wCG register */
6143 OP_RXA, /* XScale accumulator register */
6145 OP_REGLST, /* ARM register list */
6146 OP_VRSLST, /* VFP single-precision register list */
6147 OP_VRDLST, /* VFP double-precision register list */
6148 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6149 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6150 OP_NSTRLST, /* Neon element/structure list */
6152 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6153 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6154 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6155 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6156 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6157 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6158 OP_VMOV, /* Neon VMOV operands. */
6159 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6160 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6161 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6163 OP_I0, /* immediate zero */
6164 OP_I7, /* immediate value 0 .. 7 */
6165 OP_I15, /* 0 .. 15 */
6166 OP_I16, /* 1 .. 16 */
6167 OP_I16z, /* 0 .. 16 */
6168 OP_I31, /* 0 .. 31 */
6169 OP_I31w, /* 0 .. 31, optional trailing ! */
6170 OP_I32, /* 1 .. 32 */
6171 OP_I32z, /* 0 .. 32 */
6172 OP_I63, /* 0 .. 63 */
6173 OP_I63s, /* -64 .. 63 */
6174 OP_I64, /* 1 .. 64 */
6175 OP_I64z, /* 0 .. 64 */
6176 OP_I255, /* 0 .. 255 */
6178 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6179 OP_I7b, /* 0 .. 7 */
6180 OP_I15b, /* 0 .. 15 */
6181 OP_I31b, /* 0 .. 31 */
6183 OP_SH, /* shifter operand */
6184 OP_SHG, /* shifter operand with possible group relocation */
6185 OP_ADDR, /* Memory address expression (any mode) */
6186 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6187 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6188 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6189 OP_EXP, /* arbitrary expression */
6190 OP_EXPi, /* same, with optional immediate prefix */
6191 OP_EXPr, /* same, with optional relocation suffix */
6192 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6194 OP_CPSF, /* CPS flags */
6195 OP_ENDI, /* Endianness specifier */
6196 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6197 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6198 OP_COND, /* conditional code */
6199 OP_TB, /* Table branch. */
6201 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6203 OP_RRnpc_I0, /* ARM register or literal 0 */
6204 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6205 OP_RR_EXi, /* ARM register or expression with imm prefix */
6206 OP_RF_IF, /* FPA register or immediate */
6207 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6208 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6210 /* Optional operands. */
6211 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6212 OP_oI31b, /* 0 .. 31 */
6213 OP_oI32b, /* 1 .. 32 */
6214 OP_oI32z, /* 0 .. 32 */
6215 OP_oIffffb, /* 0 .. 65535 */
6216 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6218 OP_oRR, /* ARM register */
6219 OP_oRRnpc, /* ARM register, not the PC */
6220 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6221 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6222 OP_oRND, /* Optional Neon double precision register */
6223 OP_oRNQ, /* Optional Neon quad precision register */
6224 OP_oRNDQ, /* Optional Neon double or quad precision register */
6225 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6226 OP_oSHll, /* LSL immediate */
6227 OP_oSHar, /* ASR immediate */
6228 OP_oSHllar, /* LSL or ASR immediate */
6229 OP_oROR, /* ROR 0/8/16/24 */
6230 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6232 /* Some pre-defined mixed (ARM/THUMB) operands. */
6233 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6234 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6235 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6237 OP_FIRST_OPTIONAL = OP_oI7b
6240 /* Generic instruction operand parser. This does no encoding and no
6241 semantic validation; it merely squirrels values away in the inst
6242 structure. Returns SUCCESS or FAIL depending on whether the
6243 specified grammar matched. */
6245 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6247 unsigned const int *upat = pattern;
6248 char *backtrack_pos = 0;
6249 const char *backtrack_error = 0;
6250 int i, val = 0, backtrack_index = 0;
6251 enum arm_reg_type rtype;
6252 parse_operand_result result;
6253 unsigned int op_parse_code;
6255 #define po_char_or_fail(chr) \
6258 if (skip_past_char (&str, chr) == FAIL) \
6263 #define po_reg_or_fail(regtype) \
6266 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6267 & inst.operands[i].vectype); \
6270 first_error (_(reg_expected_msgs[regtype])); \
6273 inst.operands[i].reg = val; \
6274 inst.operands[i].isreg = 1; \
6275 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6276 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6277 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6278 || rtype == REG_TYPE_VFD \
6279 || rtype == REG_TYPE_NQ); \
6283 #define po_reg_or_goto(regtype, label) \
6286 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6287 & inst.operands[i].vectype); \
6291 inst.operands[i].reg = val; \
6292 inst.operands[i].isreg = 1; \
6293 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6294 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6295 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6296 || rtype == REG_TYPE_VFD \
6297 || rtype == REG_TYPE_NQ); \
6301 #define po_imm_or_fail(min, max, popt) \
6304 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6306 inst.operands[i].imm = val; \
6310 #define po_scalar_or_goto(elsz, label) \
6313 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6316 inst.operands[i].reg = val; \
6317 inst.operands[i].isscalar = 1; \
6321 #define po_misc_or_fail(expr) \
6329 #define po_misc_or_fail_no_backtrack(expr) \
6333 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6334 backtrack_pos = 0; \
6335 if (result != PARSE_OPERAND_SUCCESS) \
6340 #define po_barrier_or_imm(str) \
6343 val = parse_barrier (&str); \
6344 if (val == FAIL && ! ISALPHA (*str)) \
6347 /* ISB can only take SY as an option. */ \
6348 || ((inst.instruction & 0xf0) == 0x60 \
6351 inst.error = _("invalid barrier type"); \
6352 backtrack_pos = 0; \
6358 skip_whitespace (str);
6360 for (i = 0; upat[i] != OP_stop; i++)
6362 op_parse_code = upat[i];
6363 if (op_parse_code >= 1<<16)
6364 op_parse_code = thumb ? (op_parse_code >> 16)
6365 : (op_parse_code & ((1<<16)-1));
6367 if (op_parse_code >= OP_FIRST_OPTIONAL)
6369 /* Remember where we are in case we need to backtrack. */
6370 gas_assert (!backtrack_pos);
6371 backtrack_pos = str;
6372 backtrack_error = inst.error;
6373 backtrack_index = i;
6376 if (i > 0 && (i > 1 || inst.operands[0].present))
6377 po_char_or_fail (',');
6379 switch (op_parse_code)
6387 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6388 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6389 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6390 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6391 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6392 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6394 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6396 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6398 /* Also accept generic coprocessor regs for unknown registers. */
6400 po_reg_or_fail (REG_TYPE_CN);
6402 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6403 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6404 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6405 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6406 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6407 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6408 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6409 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6410 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6411 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6413 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6415 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6416 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6418 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6420 /* Neon scalar. Using an element size of 8 means that some invalid
6421 scalars are accepted here, so deal with those in later code. */
6422 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6426 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6429 po_imm_or_fail (0, 0, TRUE);
6434 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6439 po_scalar_or_goto (8, try_rr);
6442 po_reg_or_fail (REG_TYPE_RN);
6448 po_scalar_or_goto (8, try_nsdq);
6451 po_reg_or_fail (REG_TYPE_NSDQ);
6457 po_scalar_or_goto (8, try_ndq);
6460 po_reg_or_fail (REG_TYPE_NDQ);
6466 po_scalar_or_goto (8, try_vfd);
6469 po_reg_or_fail (REG_TYPE_VFD);
6474 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6475 not careful then bad things might happen. */
6476 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6481 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6484 /* There's a possibility of getting a 64-bit immediate here, so
6485 we need special handling. */
6486 if (parse_big_immediate (&str, i) == FAIL)
6488 inst.error = _("immediate value is out of range");
6496 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6499 po_imm_or_fail (0, 63, TRUE);
6504 po_char_or_fail ('[');
6505 po_reg_or_fail (REG_TYPE_RN);
6506 po_char_or_fail (']');
6512 po_reg_or_fail (REG_TYPE_RN);
6513 if (skip_past_char (&str, '!') == SUCCESS)
6514 inst.operands[i].writeback = 1;
6518 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6519 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6520 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6521 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6522 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6523 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6524 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6525 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6526 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6527 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6528 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6529 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6531 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6533 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6534 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6536 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6537 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6538 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6539 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6541 /* Immediate variants */
6543 po_char_or_fail ('{');
6544 po_imm_or_fail (0, 255, TRUE);
6545 po_char_or_fail ('}');
6549 /* The expression parser chokes on a trailing !, so we have
6550 to find it first and zap it. */
6553 while (*s && *s != ',')
6558 inst.operands[i].writeback = 1;
6560 po_imm_or_fail (0, 31, TRUE);
6568 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6573 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6578 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6580 if (inst.reloc.exp.X_op == O_symbol)
6582 val = parse_reloc (&str);
6585 inst.error = _("unrecognized relocation suffix");
6588 else if (val != BFD_RELOC_UNUSED)
6590 inst.operands[i].imm = val;
6591 inst.operands[i].hasreloc = 1;
6596 /* Operand for MOVW or MOVT. */
6598 po_misc_or_fail (parse_half (&str));
6601 /* Register or expression. */
6602 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6603 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6605 /* Register or immediate. */
6606 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6607 I0: po_imm_or_fail (0, 0, FALSE); break;
6609 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6611 if (!is_immediate_prefix (*str))
6614 val = parse_fpa_immediate (&str);
6617 /* FPA immediates are encoded as registers 8-15.
6618 parse_fpa_immediate has already applied the offset. */
6619 inst.operands[i].reg = val;
6620 inst.operands[i].isreg = 1;
6623 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6624 I32z: po_imm_or_fail (0, 32, FALSE); break;
6626 /* Two kinds of register. */
6629 struct reg_entry *rege = arm_reg_parse_multi (&str);
6631 || (rege->type != REG_TYPE_MMXWR
6632 && rege->type != REG_TYPE_MMXWC
6633 && rege->type != REG_TYPE_MMXWCG))
6635 inst.error = _("iWMMXt data or control register expected");
6638 inst.operands[i].reg = rege->number;
6639 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6645 struct reg_entry *rege = arm_reg_parse_multi (&str);
6647 || (rege->type != REG_TYPE_MMXWC
6648 && rege->type != REG_TYPE_MMXWCG))
6650 inst.error = _("iWMMXt control register expected");
6653 inst.operands[i].reg = rege->number;
6654 inst.operands[i].isreg = 1;
6659 case OP_CPSF: val = parse_cps_flags (&str); break;
6660 case OP_ENDI: val = parse_endian_specifier (&str); break;
6661 case OP_oROR: val = parse_ror (&str); break;
6662 case OP_COND: val = parse_cond (&str); break;
6663 case OP_oBARRIER_I15:
6664 po_barrier_or_imm (str); break;
6666 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6672 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6673 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6675 inst.error = _("Banked registers are not available with this "
6681 val = parse_psr (&str, op_parse_code == OP_wPSR);
6685 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6688 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6690 if (strncasecmp (str, "APSR_", 5) == 0)
6697 case 'c': found = (found & 1) ? 16 : found | 1; break;
6698 case 'n': found = (found & 2) ? 16 : found | 2; break;
6699 case 'z': found = (found & 4) ? 16 : found | 4; break;
6700 case 'v': found = (found & 8) ? 16 : found | 8; break;
6701 default: found = 16;
6705 inst.operands[i].isvec = 1;
6706 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6707 inst.operands[i].reg = REG_PC;
6714 po_misc_or_fail (parse_tb (&str));
6717 /* Register lists. */
6719 val = parse_reg_list (&str);
6722 inst.operands[1].writeback = 1;
6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6732 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6736 /* Allow Q registers too. */
6737 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6742 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6744 inst.operands[i].issingle = 1;
6749 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6754 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6755 &inst.operands[i].vectype);
6758 /* Addressing modes */
6760 po_misc_or_fail (parse_address (&str, i));
6764 po_misc_or_fail_no_backtrack (
6765 parse_address_group_reloc (&str, i, GROUP_LDR));
6769 po_misc_or_fail_no_backtrack (
6770 parse_address_group_reloc (&str, i, GROUP_LDRS));
6774 po_misc_or_fail_no_backtrack (
6775 parse_address_group_reloc (&str, i, GROUP_LDC));
6779 po_misc_or_fail (parse_shifter_operand (&str, i));
6783 po_misc_or_fail_no_backtrack (
6784 parse_shifter_operand_group_reloc (&str, i));
6788 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6792 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6796 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6800 as_fatal (_("unhandled operand code %d"), op_parse_code);
6803 /* Various value-based sanity checks and shared operations. We
6804 do not signal immediate failures for the register constraints;
6805 this allows a syntax error to take precedence. */
6806 switch (op_parse_code)
6814 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6815 inst.error = BAD_PC;
6820 if (inst.operands[i].isreg)
6822 if (inst.operands[i].reg == REG_PC)
6823 inst.error = BAD_PC;
6824 else if (inst.operands[i].reg == REG_SP)
6825 inst.error = BAD_SP;
6830 if (inst.operands[i].isreg
6831 && inst.operands[i].reg == REG_PC
6832 && (inst.operands[i].writeback || thumb))
6833 inst.error = BAD_PC;
6842 case OP_oBARRIER_I15:
6851 inst.operands[i].imm = val;
6858 /* If we get here, this operand was successfully parsed. */
6859 inst.operands[i].present = 1;
6863 inst.error = BAD_ARGS;
6868 /* The parse routine should already have set inst.error, but set a
6869 default here just in case. */
6871 inst.error = _("syntax error");
6875 /* Do not backtrack over a trailing optional argument that
6876 absorbed some text. We will only fail again, with the
6877 'garbage following instruction' error message, which is
6878 probably less helpful than the current one. */
6879 if (backtrack_index == i && backtrack_pos != str
6880 && upat[i+1] == OP_stop)
6883 inst.error = _("syntax error");
6887 /* Try again, skipping the optional argument at backtrack_pos. */
6888 str = backtrack_pos;
6889 inst.error = backtrack_error;
6890 inst.operands[backtrack_index].present = 0;
6891 i = backtrack_index;
6895 /* Check that we have parsed all the arguments. */
6896 if (*str != '\0' && !inst.error)
6897 inst.error = _("garbage following instruction");
6899 return inst.error ? FAIL : SUCCESS;
6902 #undef po_char_or_fail
6903 #undef po_reg_or_fail
6904 #undef po_reg_or_goto
6905 #undef po_imm_or_fail
6906 #undef po_scalar_or_fail
6907 #undef po_barrier_or_imm
6909 /* Shorthand macro for instruction encoding functions issuing errors. */
6910 #define constraint(expr, err) \
6921 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6922 instructions are unpredictable if these registers are used. This
6923 is the BadReg predicate in ARM's Thumb-2 documentation. */
6924 #define reject_bad_reg(reg) \
6926 if (reg == REG_SP || reg == REG_PC) \
6928 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6933 /* If REG is R13 (the stack pointer), warn that its use is
6935 #define warn_deprecated_sp(reg) \
6937 if (warn_on_deprecated && reg == REG_SP) \
6938 as_warn (_("use of r13 is deprecated")); \
6941 /* Functions for operand encoding. ARM, then Thumb. */
6943 #define rotate_left(v, n) (v << n | v >> (32 - n))
6945 /* If VAL can be encoded in the immediate field of an ARM instruction,
6946 return the encoded form. Otherwise, return FAIL. */
6949 encode_arm_immediate (unsigned int val)
6953 for (i = 0; i < 32; i += 2)
6954 if ((a = rotate_left (val, i)) <= 0xff)
6955 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6960 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6961 return the encoded form. Otherwise, return FAIL. */
6963 encode_thumb32_immediate (unsigned int val)
6970 for (i = 1; i <= 24; i++)
6973 if ((val & ~(0xff << i)) == 0)
6974 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6978 if (val == ((a << 16) | a))
6980 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6984 if (val == ((a << 16) | a))
6985 return 0x200 | (a >> 8);
6989 /* Encode a VFP SP or DP register number into inst.instruction. */
6992 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6994 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6997 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7000 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7003 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7008 first_error (_("D register out of range for selected VFP version"));
7016 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7020 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7024 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7028 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7032 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7036 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7044 /* Encode a <shift> in an ARM-format instruction. The immediate,
7045 if any, is handled by md_apply_fix. */
7047 encode_arm_shift (int i)
7049 if (inst.operands[i].shift_kind == SHIFT_RRX)
7050 inst.instruction |= SHIFT_ROR << 5;
7053 inst.instruction |= inst.operands[i].shift_kind << 5;
7054 if (inst.operands[i].immisreg)
7056 inst.instruction |= SHIFT_BY_REG;
7057 inst.instruction |= inst.operands[i].imm << 8;
7060 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7065 encode_arm_shifter_operand (int i)
7067 if (inst.operands[i].isreg)
7069 inst.instruction |= inst.operands[i].reg;
7070 encode_arm_shift (i);
7074 inst.instruction |= INST_IMMEDIATE;
7075 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7076 inst.instruction |= inst.operands[i].imm;
7080 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7082 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7085 Generate an error if the operand is not a register. */
7086 constraint (!inst.operands[i].isreg,
7087 _("Instruction does not support =N addresses"));
7089 inst.instruction |= inst.operands[i].reg << 16;
7091 if (inst.operands[i].preind)
7095 inst.error = _("instruction does not accept preindexed addressing");
7098 inst.instruction |= PRE_INDEX;
7099 if (inst.operands[i].writeback)
7100 inst.instruction |= WRITE_BACK;
7103 else if (inst.operands[i].postind)
7105 gas_assert (inst.operands[i].writeback);
7107 inst.instruction |= WRITE_BACK;
7109 else /* unindexed - only for coprocessor */
7111 inst.error = _("instruction does not accept unindexed addressing");
7115 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7116 && (((inst.instruction & 0x000f0000) >> 16)
7117 == ((inst.instruction & 0x0000f000) >> 12)))
7118 as_warn ((inst.instruction & LOAD_BIT)
7119 ? _("destination register same as write-back base")
7120 : _("source register same as write-back base"));
7123 /* inst.operands[i] was set up by parse_address. Encode it into an
7124 ARM-format mode 2 load or store instruction. If is_t is true,
7125 reject forms that cannot be used with a T instruction (i.e. not
7128 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7130 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7132 encode_arm_addr_mode_common (i, is_t);
7134 if (inst.operands[i].immisreg)
7136 constraint ((inst.operands[i].imm == REG_PC
7137 || (is_pc && inst.operands[i].writeback)),
7139 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7140 inst.instruction |= inst.operands[i].imm;
7141 if (!inst.operands[i].negative)
7142 inst.instruction |= INDEX_UP;
7143 if (inst.operands[i].shifted)
7145 if (inst.operands[i].shift_kind == SHIFT_RRX)
7146 inst.instruction |= SHIFT_ROR << 5;
7149 inst.instruction |= inst.operands[i].shift_kind << 5;
7150 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7154 else /* immediate offset in inst.reloc */
7156 if (is_pc && !inst.reloc.pc_rel)
7158 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7160 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7161 cannot use PC in addressing.
7162 PC cannot be used in writeback addressing, either. */
7163 constraint ((is_t || inst.operands[i].writeback),
7166 /* Use of PC in str is deprecated for ARMv7. */
7167 if (warn_on_deprecated
7169 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7170 as_warn (_("use of PC in this instruction is deprecated"));
7173 if (inst.reloc.type == BFD_RELOC_UNUSED)
7175 /* Prefer + for zero encoded value. */
7176 if (!inst.operands[i].negative)
7177 inst.instruction |= INDEX_UP;
7178 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7183 /* inst.operands[i] was set up by parse_address. Encode it into an
7184 ARM-format mode 3 load or store instruction. Reject forms that
7185 cannot be used with such instructions. If is_t is true, reject
7186 forms that cannot be used with a T instruction (i.e. not
7189 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7191 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7193 inst.error = _("instruction does not accept scaled register index");
7197 encode_arm_addr_mode_common (i, is_t);
7199 if (inst.operands[i].immisreg)
7201 constraint ((inst.operands[i].imm == REG_PC
7202 || (is_t && inst.operands[i].reg == REG_PC)),
7204 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7206 inst.instruction |= inst.operands[i].imm;
7207 if (!inst.operands[i].negative)
7208 inst.instruction |= INDEX_UP;
7210 else /* immediate offset in inst.reloc */
7212 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7213 && inst.operands[i].writeback),
7215 inst.instruction |= HWOFFSET_IMM;
7216 if (inst.reloc.type == BFD_RELOC_UNUSED)
7218 /* Prefer + for zero encoded value. */
7219 if (!inst.operands[i].negative)
7220 inst.instruction |= INDEX_UP;
7222 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7227 /* inst.operands[i] was set up by parse_address. Encode it into an
7228 ARM-format instruction. Reject all forms which cannot be encoded
7229 into a coprocessor load/store instruction. If wb_ok is false,
7230 reject use of writeback; if unind_ok is false, reject use of
7231 unindexed addressing. If reloc_override is not 0, use it instead
7232 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7233 (in which case it is preserved). */
7236 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7238 inst.instruction |= inst.operands[i].reg << 16;
7240 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7242 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7244 gas_assert (!inst.operands[i].writeback);
7247 inst.error = _("instruction does not support unindexed addressing");
7250 inst.instruction |= inst.operands[i].imm;
7251 inst.instruction |= INDEX_UP;
7255 if (inst.operands[i].preind)
7256 inst.instruction |= PRE_INDEX;
7258 if (inst.operands[i].writeback)
7260 if (inst.operands[i].reg == REG_PC)
7262 inst.error = _("pc may not be used with write-back");
7267 inst.error = _("instruction does not support writeback");
7270 inst.instruction |= WRITE_BACK;
7274 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7275 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7276 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7277 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7280 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7282 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7285 /* Prefer + for zero encoded value. */
7286 if (!inst.operands[i].negative)
7287 inst.instruction |= INDEX_UP;
7292 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7293 Determine whether it can be performed with a move instruction; if
7294 it can, convert inst.instruction to that move instruction and
7295 return TRUE; if it can't, convert inst.instruction to a literal-pool
7296 load and return FALSE. If this is not a valid thing to do in the
7297 current context, set inst.error and return TRUE.
7299 inst.operands[i] describes the destination register. */
7302 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7307 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7311 if ((inst.instruction & tbit) == 0)
7313 inst.error = _("invalid pseudo operation");
7316 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7318 inst.error = _("constant expression expected");
7321 if (inst.reloc.exp.X_op == O_constant)
7325 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7327 /* This can be done with a mov(1) instruction. */
7328 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7329 inst.instruction |= inst.reloc.exp.X_add_number;
7335 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7338 /* This can be done with a mov instruction. */
7339 inst.instruction &= LITERAL_MASK;
7340 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7341 inst.instruction |= value & 0xfff;
7345 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7348 /* This can be done with a mvn instruction. */
7349 inst.instruction &= LITERAL_MASK;
7350 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7351 inst.instruction |= value & 0xfff;
7357 if (add_to_lit_pool () == FAIL)
7359 inst.error = _("literal pool insertion failed");
7362 inst.operands[1].reg = REG_PC;
7363 inst.operands[1].isreg = 1;
7364 inst.operands[1].preind = 1;
7365 inst.reloc.pc_rel = 1;
7366 inst.reloc.type = (thumb_p
7367 ? BFD_RELOC_ARM_THUMB_OFFSET
7369 ? BFD_RELOC_ARM_HWLITERAL
7370 : BFD_RELOC_ARM_LITERAL));
7374 /* Functions for instruction encoding, sorted by sub-architecture.
7375 First some generics; their names are taken from the conventional
7376 bit positions for register arguments in ARM format instructions. */
7386 inst.instruction |= inst.operands[0].reg << 12;
7392 inst.instruction |= inst.operands[0].reg << 12;
7393 inst.instruction |= inst.operands[1].reg;
7399 inst.instruction |= inst.operands[0].reg;
7400 inst.instruction |= inst.operands[1].reg << 16;
7406 inst.instruction |= inst.operands[0].reg << 12;
7407 inst.instruction |= inst.operands[1].reg << 16;
7413 inst.instruction |= inst.operands[0].reg << 16;
7414 inst.instruction |= inst.operands[1].reg << 12;
7418 check_obsolete (const arm_feature_set *feature, const char *msg)
7420 if (ARM_CPU_IS_ANY (cpu_variant))
7422 as_warn ("%s", msg);
7425 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7437 unsigned Rn = inst.operands[2].reg;
7438 /* Enforce restrictions on SWP instruction. */
7439 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7441 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7442 _("Rn must not overlap other operands"));
7444 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7446 if (!check_obsolete (&arm_ext_v8,
7447 _("swp{b} use is obsoleted for ARMv8 and later"))
7448 && warn_on_deprecated
7449 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7450 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7453 inst.instruction |= inst.operands[0].reg << 12;
7454 inst.instruction |= inst.operands[1].reg;
7455 inst.instruction |= Rn << 16;
7461 inst.instruction |= inst.operands[0].reg << 12;
7462 inst.instruction |= inst.operands[1].reg << 16;
7463 inst.instruction |= inst.operands[2].reg;
7469 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7470 constraint (((inst.reloc.exp.X_op != O_constant
7471 && inst.reloc.exp.X_op != O_illegal)
7472 || inst.reloc.exp.X_add_number != 0),
7474 inst.instruction |= inst.operands[0].reg;
7475 inst.instruction |= inst.operands[1].reg << 12;
7476 inst.instruction |= inst.operands[2].reg << 16;
7482 inst.instruction |= inst.operands[0].imm;
7488 inst.instruction |= inst.operands[0].reg << 12;
7489 encode_arm_cp_address (1, TRUE, TRUE, 0);
7492 /* ARM instructions, in alphabetical order by function name (except
7493 that wrapper functions appear immediately after the function they
7496 /* This is a pseudo-op of the form "adr rd, label" to be converted
7497 into a relative address of the form "add rd, pc, #label-.-8". */
7502 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7504 /* Frag hacking will turn this into a sub instruction if the offset turns
7505 out to be negative. */
7506 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7507 inst.reloc.pc_rel = 1;
7508 inst.reloc.exp.X_add_number -= 8;
7511 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7512 into a relative address of the form:
7513 add rd, pc, #low(label-.-8)"
7514 add rd, rd, #high(label-.-8)" */
7519 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7521 /* Frag hacking will turn this into a sub instruction if the offset turns
7522 out to be negative. */
7523 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7524 inst.reloc.pc_rel = 1;
7525 inst.size = INSN_SIZE * 2;
7526 inst.reloc.exp.X_add_number -= 8;
7532 if (!inst.operands[1].present)
7533 inst.operands[1].reg = inst.operands[0].reg;
7534 inst.instruction |= inst.operands[0].reg << 12;
7535 inst.instruction |= inst.operands[1].reg << 16;
7536 encode_arm_shifter_operand (2);
7542 if (inst.operands[0].present)
7543 inst.instruction |= inst.operands[0].imm;
7545 inst.instruction |= 0xf;
7551 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7552 constraint (msb > 32, _("bit-field extends past end of register"));
7553 /* The instruction encoding stores the LSB and MSB,
7554 not the LSB and width. */
7555 inst.instruction |= inst.operands[0].reg << 12;
7556 inst.instruction |= inst.operands[1].imm << 7;
7557 inst.instruction |= (msb - 1) << 16;
7565 /* #0 in second position is alternative syntax for bfc, which is
7566 the same instruction but with REG_PC in the Rm field. */
7567 if (!inst.operands[1].isreg)
7568 inst.operands[1].reg = REG_PC;
7570 msb = inst.operands[2].imm + inst.operands[3].imm;
7571 constraint (msb > 32, _("bit-field extends past end of register"));
7572 /* The instruction encoding stores the LSB and MSB,
7573 not the LSB and width. */
7574 inst.instruction |= inst.operands[0].reg << 12;
7575 inst.instruction |= inst.operands[1].reg;
7576 inst.instruction |= inst.operands[2].imm << 7;
7577 inst.instruction |= (msb - 1) << 16;
7583 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7584 _("bit-field extends past end of register"));
7585 inst.instruction |= inst.operands[0].reg << 12;
7586 inst.instruction |= inst.operands[1].reg;
7587 inst.instruction |= inst.operands[2].imm << 7;
7588 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7591 /* ARM V5 breakpoint instruction (argument parse)
7592 BKPT <16 bit unsigned immediate>
7593 Instruction is not conditional.
7594 The bit pattern given in insns[] has the COND_ALWAYS condition,
7595 and it is an error if the caller tried to override that. */
7600 /* Top 12 of 16 bits to bits 19:8. */
7601 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7603 /* Bottom 4 of 16 bits to bits 3:0. */
7604 inst.instruction |= inst.operands[0].imm & 0xf;
7608 encode_branch (int default_reloc)
7610 if (inst.operands[0].hasreloc)
7612 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7613 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7614 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7615 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7616 ? BFD_RELOC_ARM_PLT32
7617 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7620 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7621 inst.reloc.pc_rel = 1;
7628 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7629 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7632 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7639 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7641 if (inst.cond == COND_ALWAYS)
7642 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7644 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7648 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7651 /* ARM V5 branch-link-exchange instruction (argument parse)
7652 BLX <target_addr> ie BLX(1)
7653 BLX{<condition>} <Rm> ie BLX(2)
7654 Unfortunately, there are two different opcodes for this mnemonic.
7655 So, the insns[].value is not used, and the code here zaps values
7656 into inst.instruction.
7657 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7662 if (inst.operands[0].isreg)
7664 /* Arg is a register; the opcode provided by insns[] is correct.
7665 It is not illegal to do "blx pc", just useless. */
7666 if (inst.operands[0].reg == REG_PC)
7667 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7669 inst.instruction |= inst.operands[0].reg;
7673 /* Arg is an address; this instruction cannot be executed
7674 conditionally, and the opcode must be adjusted.
7675 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7676 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7677 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7678 inst.instruction = 0xfa000000;
7679 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7686 bfd_boolean want_reloc;
7688 if (inst.operands[0].reg == REG_PC)
7689 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7691 inst.instruction |= inst.operands[0].reg;
7692 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7693 it is for ARMv4t or earlier. */
7694 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7695 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7699 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7704 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7708 /* ARM v5TEJ. Jump to Jazelle code. */
7713 if (inst.operands[0].reg == REG_PC)
7714 as_tsktsk (_("use of r15 in bxj is not really useful"));
7716 inst.instruction |= inst.operands[0].reg;
7719 /* Co-processor data operation:
7720 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7721 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7725 inst.instruction |= inst.operands[0].reg << 8;
7726 inst.instruction |= inst.operands[1].imm << 20;
7727 inst.instruction |= inst.operands[2].reg << 12;
7728 inst.instruction |= inst.operands[3].reg << 16;
7729 inst.instruction |= inst.operands[4].reg;
7730 inst.instruction |= inst.operands[5].imm << 5;
7736 inst.instruction |= inst.operands[0].reg << 16;
7737 encode_arm_shifter_operand (1);
7740 /* Transfer between coprocessor and ARM registers.
7741 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7746 No special properties. */
7748 struct deprecated_coproc_regs_s
7755 arm_feature_set deprecated;
7756 arm_feature_set obsoleted;
7757 const char *dep_msg;
7758 const char *obs_msg;
7761 #define DEPR_ACCESS_V8 \
7762 N_("This coprocessor register access is deprecated in ARMv8")
7764 /* Table of all deprecated coprocessor registers. */
7765 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7767 {15, 0, 7, 10, 5, /* CP15DMB. */
7768 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7769 DEPR_ACCESS_V8, NULL},
7770 {15, 0, 7, 10, 4, /* CP15DSB. */
7771 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7772 DEPR_ACCESS_V8, NULL},
7773 {15, 0, 7, 5, 4, /* CP15ISB. */
7774 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7775 DEPR_ACCESS_V8, NULL},
7776 {14, 6, 1, 0, 0, /* TEEHBR. */
7777 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8, NULL},
7779 {14, 6, 0, 0, 0, /* TEECR. */
7780 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8, NULL},
7784 #undef DEPR_ACCESS_V8
7786 static const size_t deprecated_coproc_reg_count =
7787 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7795 Rd = inst.operands[2].reg;
7798 if (inst.instruction == 0xee000010
7799 || inst.instruction == 0xfe000010)
7801 reject_bad_reg (Rd);
7804 constraint (Rd == REG_SP, BAD_SP);
7809 if (inst.instruction == 0xe000010)
7810 constraint (Rd == REG_PC, BAD_PC);
7813 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7815 const struct deprecated_coproc_regs_s *r =
7816 deprecated_coproc_regs + i;
7818 if (inst.operands[0].reg == r->cp
7819 && inst.operands[1].imm == r->opc1
7820 && inst.operands[3].reg == r->crn
7821 && inst.operands[4].reg == r->crm
7822 && inst.operands[5].imm == r->opc2)
7824 if (! ARM_CPU_IS_ANY (cpu_variant)
7825 && warn_on_deprecated
7826 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7827 as_warn ("%s", r->dep_msg);
7831 inst.instruction |= inst.operands[0].reg << 8;
7832 inst.instruction |= inst.operands[1].imm << 21;
7833 inst.instruction |= Rd << 12;
7834 inst.instruction |= inst.operands[3].reg << 16;
7835 inst.instruction |= inst.operands[4].reg;
7836 inst.instruction |= inst.operands[5].imm << 5;
7839 /* Transfer between coprocessor register and pair of ARM registers.
7840 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7845 Two XScale instructions are special cases of these:
7847 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7848 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7850 Result unpredictable if Rd or Rn is R15. */
7857 Rd = inst.operands[2].reg;
7858 Rn = inst.operands[3].reg;
7862 reject_bad_reg (Rd);
7863 reject_bad_reg (Rn);
7867 constraint (Rd == REG_PC, BAD_PC);
7868 constraint (Rn == REG_PC, BAD_PC);
7871 inst.instruction |= inst.operands[0].reg << 8;
7872 inst.instruction |= inst.operands[1].imm << 4;
7873 inst.instruction |= Rd << 12;
7874 inst.instruction |= Rn << 16;
7875 inst.instruction |= inst.operands[4].reg;
7881 inst.instruction |= inst.operands[0].imm << 6;
7882 if (inst.operands[1].present)
7884 inst.instruction |= CPSI_MMOD;
7885 inst.instruction |= inst.operands[1].imm;
7892 inst.instruction |= inst.operands[0].imm;
7898 unsigned Rd, Rn, Rm;
7900 Rd = inst.operands[0].reg;
7901 Rn = (inst.operands[1].present
7902 ? inst.operands[1].reg : Rd);
7903 Rm = inst.operands[2].reg;
7905 constraint ((Rd == REG_PC), BAD_PC);
7906 constraint ((Rn == REG_PC), BAD_PC);
7907 constraint ((Rm == REG_PC), BAD_PC);
7909 inst.instruction |= Rd << 16;
7910 inst.instruction |= Rn << 0;
7911 inst.instruction |= Rm << 8;
7917 /* There is no IT instruction in ARM mode. We
7918 process it to do the validation as if in
7919 thumb mode, just in case the code gets
7920 assembled for thumb using the unified syntax. */
7925 set_it_insn_type (IT_INSN);
7926 now_it.mask = (inst.instruction & 0xf) | 0x10;
7927 now_it.cc = inst.operands[0].imm;
7931 /* If there is only one register in the register list,
7932 then return its register number. Otherwise return -1. */
7934 only_one_reg_in_list (int range)
7936 int i = ffs (range) - 1;
7937 return (i > 15 || range != (1 << i)) ? -1 : i;
7941 encode_ldmstm(int from_push_pop_mnem)
7943 int base_reg = inst.operands[0].reg;
7944 int range = inst.operands[1].imm;
7947 inst.instruction |= base_reg << 16;
7948 inst.instruction |= range;
7950 if (inst.operands[1].writeback)
7951 inst.instruction |= LDM_TYPE_2_OR_3;
7953 if (inst.operands[0].writeback)
7955 inst.instruction |= WRITE_BACK;
7956 /* Check for unpredictable uses of writeback. */
7957 if (inst.instruction & LOAD_BIT)
7959 /* Not allowed in LDM type 2. */
7960 if ((inst.instruction & LDM_TYPE_2_OR_3)
7961 && ((range & (1 << REG_PC)) == 0))
7962 as_warn (_("writeback of base register is UNPREDICTABLE"));
7963 /* Only allowed if base reg not in list for other types. */
7964 else if (range & (1 << base_reg))
7965 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7969 /* Not allowed for type 2. */
7970 if (inst.instruction & LDM_TYPE_2_OR_3)
7971 as_warn (_("writeback of base register is UNPREDICTABLE"));
7972 /* Only allowed if base reg not in list, or first in list. */
7973 else if ((range & (1 << base_reg))
7974 && (range & ((1 << base_reg) - 1)))
7975 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7979 /* If PUSH/POP has only one register, then use the A2 encoding. */
7980 one_reg = only_one_reg_in_list (range);
7981 if (from_push_pop_mnem && one_reg >= 0)
7983 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7985 inst.instruction &= A_COND_MASK;
7986 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7987 inst.instruction |= one_reg << 12;
7994 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7997 /* ARMv5TE load-consecutive (argument parse)
8006 constraint (inst.operands[0].reg % 2 != 0,
8007 _("first transfer register must be even"));
8008 constraint (inst.operands[1].present
8009 && inst.operands[1].reg != inst.operands[0].reg + 1,
8010 _("can only transfer two consecutive registers"));
8011 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8012 constraint (!inst.operands[2].isreg, _("'[' expected"));
8014 if (!inst.operands[1].present)
8015 inst.operands[1].reg = inst.operands[0].reg + 1;
8017 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8018 register and the first register written; we have to diagnose
8019 overlap between the base and the second register written here. */
8021 if (inst.operands[2].reg == inst.operands[1].reg
8022 && (inst.operands[2].writeback || inst.operands[2].postind))
8023 as_warn (_("base register written back, and overlaps "
8024 "second transfer register"));
8026 if (!(inst.instruction & V4_STR_BIT))
8028 /* For an index-register load, the index register must not overlap the
8029 destination (even if not write-back). */
8030 if (inst.operands[2].immisreg
8031 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8032 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8033 as_warn (_("index register overlaps transfer register"));
8035 inst.instruction |= inst.operands[0].reg << 12;
8036 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8042 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8043 || inst.operands[1].postind || inst.operands[1].writeback
8044 || inst.operands[1].immisreg || inst.operands[1].shifted
8045 || inst.operands[1].negative
8046 /* This can arise if the programmer has written
8048 or if they have mistakenly used a register name as the last
8051 It is very difficult to distinguish between these two cases
8052 because "rX" might actually be a label. ie the register
8053 name has been occluded by a symbol of the same name. So we
8054 just generate a general 'bad addressing mode' type error
8055 message and leave it up to the programmer to discover the
8056 true cause and fix their mistake. */
8057 || (inst.operands[1].reg == REG_PC),
8060 constraint (inst.reloc.exp.X_op != O_constant
8061 || inst.reloc.exp.X_add_number != 0,
8062 _("offset must be zero in ARM encoding"));
8064 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8066 inst.instruction |= inst.operands[0].reg << 12;
8067 inst.instruction |= inst.operands[1].reg << 16;
8068 inst.reloc.type = BFD_RELOC_UNUSED;
8074 constraint (inst.operands[0].reg % 2 != 0,
8075 _("even register required"));
8076 constraint (inst.operands[1].present
8077 && inst.operands[1].reg != inst.operands[0].reg + 1,
8078 _("can only load two consecutive registers"));
8079 /* If op 1 were present and equal to PC, this function wouldn't
8080 have been called in the first place. */
8081 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8083 inst.instruction |= inst.operands[0].reg << 12;
8084 inst.instruction |= inst.operands[2].reg << 16;
8087 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8088 which is not a multiple of four is UNPREDICTABLE. */
8090 check_ldr_r15_aligned (void)
8092 constraint (!(inst.operands[1].immisreg)
8093 && (inst.operands[0].reg == REG_PC
8094 && inst.operands[1].reg == REG_PC
8095 && (inst.reloc.exp.X_add_number & 0x3)),
8096 _("ldr to register 15 must be 4-byte alligned"));
8102 inst.instruction |= inst.operands[0].reg << 12;
8103 if (!inst.operands[1].isreg)
8104 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8106 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8107 check_ldr_r15_aligned ();
8113 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8115 if (inst.operands[1].preind)
8117 constraint (inst.reloc.exp.X_op != O_constant
8118 || inst.reloc.exp.X_add_number != 0,
8119 _("this instruction requires a post-indexed address"));
8121 inst.operands[1].preind = 0;
8122 inst.operands[1].postind = 1;
8123 inst.operands[1].writeback = 1;
8125 inst.instruction |= inst.operands[0].reg << 12;
8126 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8129 /* Halfword and signed-byte load/store operations. */
8134 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8135 inst.instruction |= inst.operands[0].reg << 12;
8136 if (!inst.operands[1].isreg)
8137 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8139 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8145 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8147 if (inst.operands[1].preind)
8149 constraint (inst.reloc.exp.X_op != O_constant
8150 || inst.reloc.exp.X_add_number != 0,
8151 _("this instruction requires a post-indexed address"));
8153 inst.operands[1].preind = 0;
8154 inst.operands[1].postind = 1;
8155 inst.operands[1].writeback = 1;
8157 inst.instruction |= inst.operands[0].reg << 12;
8158 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8161 /* Co-processor register load/store.
8162 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8166 inst.instruction |= inst.operands[0].reg << 8;
8167 inst.instruction |= inst.operands[1].reg << 12;
8168 encode_arm_cp_address (2, TRUE, TRUE, 0);
8174 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8175 if (inst.operands[0].reg == inst.operands[1].reg
8176 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8177 && !(inst.instruction & 0x00400000))
8178 as_tsktsk (_("Rd and Rm should be different in mla"));
8180 inst.instruction |= inst.operands[0].reg << 16;
8181 inst.instruction |= inst.operands[1].reg;
8182 inst.instruction |= inst.operands[2].reg << 8;
8183 inst.instruction |= inst.operands[3].reg << 12;
8189 inst.instruction |= inst.operands[0].reg << 12;
8190 encode_arm_shifter_operand (1);
8193 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8200 top = (inst.instruction & 0x00400000) != 0;
8201 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8202 _(":lower16: not allowed this instruction"));
8203 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8204 _(":upper16: not allowed instruction"));
8205 inst.instruction |= inst.operands[0].reg << 12;
8206 if (inst.reloc.type == BFD_RELOC_UNUSED)
8208 imm = inst.reloc.exp.X_add_number;
8209 /* The value is in two pieces: 0:11, 16:19. */
8210 inst.instruction |= (imm & 0x00000fff);
8211 inst.instruction |= (imm & 0x0000f000) << 4;
8215 static void do_vfp_nsyn_opcode (const char *);
8218 do_vfp_nsyn_mrs (void)
8220 if (inst.operands[0].isvec)
8222 if (inst.operands[1].reg != 1)
8223 first_error (_("operand 1 must be FPSCR"));
8224 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8225 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8226 do_vfp_nsyn_opcode ("fmstat");
8228 else if (inst.operands[1].isvec)
8229 do_vfp_nsyn_opcode ("fmrx");
8237 do_vfp_nsyn_msr (void)
8239 if (inst.operands[0].isvec)
8240 do_vfp_nsyn_opcode ("fmxr");
8250 unsigned Rt = inst.operands[0].reg;
8252 if (thumb_mode && Rt == REG_SP)
8254 inst.error = BAD_SP;
8258 /* APSR_ sets isvec. All other refs to PC are illegal. */
8259 if (!inst.operands[0].isvec && Rt == REG_PC)
8261 inst.error = BAD_PC;
8265 /* If we get through parsing the register name, we just insert the number
8266 generated into the instruction without further validation. */
8267 inst.instruction |= (inst.operands[1].reg << 16);
8268 inst.instruction |= (Rt << 12);
8274 unsigned Rt = inst.operands[1].reg;
8277 reject_bad_reg (Rt);
8278 else if (Rt == REG_PC)
8280 inst.error = BAD_PC;
8284 /* If we get through parsing the register name, we just insert the number
8285 generated into the instruction without further validation. */
8286 inst.instruction |= (inst.operands[0].reg << 16);
8287 inst.instruction |= (Rt << 12);
8295 if (do_vfp_nsyn_mrs () == SUCCESS)
8298 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8299 inst.instruction |= inst.operands[0].reg << 12;
8301 if (inst.operands[1].isreg)
8303 br = inst.operands[1].reg;
8304 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8305 as_bad (_("bad register for mrs"));
8309 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8310 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8312 _("'APSR', 'CPSR' or 'SPSR' expected"));
8313 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8316 inst.instruction |= br;
8319 /* Two possible forms:
8320 "{C|S}PSR_<field>, Rm",
8321 "{C|S}PSR_f, #expression". */
8326 if (do_vfp_nsyn_msr () == SUCCESS)
8329 inst.instruction |= inst.operands[0].imm;
8330 if (inst.operands[1].isreg)
8331 inst.instruction |= inst.operands[1].reg;
8334 inst.instruction |= INST_IMMEDIATE;
8335 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8336 inst.reloc.pc_rel = 0;
8343 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8345 if (!inst.operands[2].present)
8346 inst.operands[2].reg = inst.operands[0].reg;
8347 inst.instruction |= inst.operands[0].reg << 16;
8348 inst.instruction |= inst.operands[1].reg;
8349 inst.instruction |= inst.operands[2].reg << 8;
8351 if (inst.operands[0].reg == inst.operands[1].reg
8352 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8353 as_tsktsk (_("Rd and Rm should be different in mul"));
8356 /* Long Multiply Parser
8357 UMULL RdLo, RdHi, Rm, Rs
8358 SMULL RdLo, RdHi, Rm, Rs
8359 UMLAL RdLo, RdHi, Rm, Rs
8360 SMLAL RdLo, RdHi, Rm, Rs. */
8365 inst.instruction |= inst.operands[0].reg << 12;
8366 inst.instruction |= inst.operands[1].reg << 16;
8367 inst.instruction |= inst.operands[2].reg;
8368 inst.instruction |= inst.operands[3].reg << 8;
8370 /* rdhi and rdlo must be different. */
8371 if (inst.operands[0].reg == inst.operands[1].reg)
8372 as_tsktsk (_("rdhi and rdlo must be different"));
8374 /* rdhi, rdlo and rm must all be different before armv6. */
8375 if ((inst.operands[0].reg == inst.operands[2].reg
8376 || inst.operands[1].reg == inst.operands[2].reg)
8377 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8378 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8384 if (inst.operands[0].present
8385 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8387 /* Architectural NOP hints are CPSR sets with no bits selected. */
8388 inst.instruction &= 0xf0000000;
8389 inst.instruction |= 0x0320f000;
8390 if (inst.operands[0].present)
8391 inst.instruction |= inst.operands[0].imm;
8395 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8396 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8397 Condition defaults to COND_ALWAYS.
8398 Error if Rd, Rn or Rm are R15. */
8403 inst.instruction |= inst.operands[0].reg << 12;
8404 inst.instruction |= inst.operands[1].reg << 16;
8405 inst.instruction |= inst.operands[2].reg;
8406 if (inst.operands[3].present)
8407 encode_arm_shift (3);
8410 /* ARM V6 PKHTB (Argument Parse). */
8415 if (!inst.operands[3].present)
8417 /* If the shift specifier is omitted, turn the instruction
8418 into pkhbt rd, rm, rn. */
8419 inst.instruction &= 0xfff00010;
8420 inst.instruction |= inst.operands[0].reg << 12;
8421 inst.instruction |= inst.operands[1].reg;
8422 inst.instruction |= inst.operands[2].reg << 16;
8426 inst.instruction |= inst.operands[0].reg << 12;
8427 inst.instruction |= inst.operands[1].reg << 16;
8428 inst.instruction |= inst.operands[2].reg;
8429 encode_arm_shift (3);
8433 /* ARMv5TE: Preload-Cache
8434 MP Extensions: Preload for write
8438 Syntactically, like LDR with B=1, W=0, L=1. */
8443 constraint (!inst.operands[0].isreg,
8444 _("'[' expected after PLD mnemonic"));
8445 constraint (inst.operands[0].postind,
8446 _("post-indexed expression used in preload instruction"));
8447 constraint (inst.operands[0].writeback,
8448 _("writeback used in preload instruction"));
8449 constraint (!inst.operands[0].preind,
8450 _("unindexed addressing used in preload instruction"));
8451 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8454 /* ARMv7: PLI <addr_mode> */
8458 constraint (!inst.operands[0].isreg,
8459 _("'[' expected after PLI mnemonic"));
8460 constraint (inst.operands[0].postind,
8461 _("post-indexed expression used in preload instruction"));
8462 constraint (inst.operands[0].writeback,
8463 _("writeback used in preload instruction"));
8464 constraint (!inst.operands[0].preind,
8465 _("unindexed addressing used in preload instruction"));
8466 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 inst.instruction &= ~PRE_INDEX;
8473 inst.operands[1] = inst.operands[0];
8474 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8475 inst.operands[0].isreg = 1;
8476 inst.operands[0].writeback = 1;
8477 inst.operands[0].reg = REG_SP;
8478 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8481 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8482 word at the specified address and the following word
8484 Unconditionally executed.
8485 Error if Rn is R15. */
8490 inst.instruction |= inst.operands[0].reg << 16;
8491 if (inst.operands[0].writeback)
8492 inst.instruction |= WRITE_BACK;
8495 /* ARM V6 ssat (argument parse). */
8500 inst.instruction |= inst.operands[0].reg << 12;
8501 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8502 inst.instruction |= inst.operands[2].reg;
8504 if (inst.operands[3].present)
8505 encode_arm_shift (3);
8508 /* ARM V6 usat (argument parse). */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= inst.operands[1].imm << 16;
8515 inst.instruction |= inst.operands[2].reg;
8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
8521 /* ARM V6 ssat16 (argument parse). */
8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8528 inst.instruction |= inst.operands[2].reg;
8534 inst.instruction |= inst.operands[0].reg << 12;
8535 inst.instruction |= inst.operands[1].imm << 16;
8536 inst.instruction |= inst.operands[2].reg;
8539 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8540 preserving the other bits.
8542 setend <endian_specifier>, where <endian_specifier> is either
8548 if (warn_on_deprecated
8549 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8550 as_warn (_("setend use is deprecated for ARMv8"));
8552 if (inst.operands[0].imm)
8553 inst.instruction |= 0x200;
8559 unsigned int Rm = (inst.operands[1].present
8560 ? inst.operands[1].reg
8561 : inst.operands[0].reg);
8563 inst.instruction |= inst.operands[0].reg << 12;
8564 inst.instruction |= Rm;
8565 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8567 inst.instruction |= inst.operands[2].reg << 8;
8568 inst.instruction |= SHIFT_BY_REG;
8569 /* PR 12854: Error on extraneous shifts. */
8570 constraint (inst.operands[2].shifted,
8571 _("extraneous shift as part of operand to shift insn"));
8574 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8580 inst.reloc.type = BFD_RELOC_ARM_SMC;
8581 inst.reloc.pc_rel = 0;
8587 inst.reloc.type = BFD_RELOC_ARM_HVC;
8588 inst.reloc.pc_rel = 0;
8594 inst.reloc.type = BFD_RELOC_ARM_SWI;
8595 inst.reloc.pc_rel = 0;
8598 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8599 SMLAxy{cond} Rd,Rm,Rs,Rn
8600 SMLAWy{cond} Rd,Rm,Rs,Rn
8601 Error if any register is R15. */
8606 inst.instruction |= inst.operands[0].reg << 16;
8607 inst.instruction |= inst.operands[1].reg;
8608 inst.instruction |= inst.operands[2].reg << 8;
8609 inst.instruction |= inst.operands[3].reg << 12;
8612 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8613 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8614 Error if any register is R15.
8615 Warning if Rdlo == Rdhi. */
8620 inst.instruction |= inst.operands[0].reg << 12;
8621 inst.instruction |= inst.operands[1].reg << 16;
8622 inst.instruction |= inst.operands[2].reg;
8623 inst.instruction |= inst.operands[3].reg << 8;
8625 if (inst.operands[0].reg == inst.operands[1].reg)
8626 as_tsktsk (_("rdhi and rdlo must be different"));
8629 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8630 SMULxy{cond} Rd,Rm,Rs
8631 Error if any register is R15. */
8636 inst.instruction |= inst.operands[0].reg << 16;
8637 inst.instruction |= inst.operands[1].reg;
8638 inst.instruction |= inst.operands[2].reg << 8;
8641 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8642 the same for both ARM and Thumb-2. */
8649 if (inst.operands[0].present)
8651 reg = inst.operands[0].reg;
8652 constraint (reg != REG_SP, _("SRS base register must be r13"));
8657 inst.instruction |= reg << 16;
8658 inst.instruction |= inst.operands[1].imm;
8659 if (inst.operands[0].writeback || inst.operands[1].writeback)
8660 inst.instruction |= WRITE_BACK;
8663 /* ARM V6 strex (argument parse). */
8668 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8669 || inst.operands[2].postind || inst.operands[2].writeback
8670 || inst.operands[2].immisreg || inst.operands[2].shifted
8671 || inst.operands[2].negative
8672 /* See comment in do_ldrex(). */
8673 || (inst.operands[2].reg == REG_PC),
8676 constraint (inst.operands[0].reg == inst.operands[1].reg
8677 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8679 constraint (inst.reloc.exp.X_op != O_constant
8680 || inst.reloc.exp.X_add_number != 0,
8681 _("offset must be zero in ARM encoding"));
8683 inst.instruction |= inst.operands[0].reg << 12;
8684 inst.instruction |= inst.operands[1].reg;
8685 inst.instruction |= inst.operands[2].reg << 16;
8686 inst.reloc.type = BFD_RELOC_UNUSED;
8692 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8693 || inst.operands[2].postind || inst.operands[2].writeback
8694 || inst.operands[2].immisreg || inst.operands[2].shifted
8695 || inst.operands[2].negative,
8698 constraint (inst.operands[0].reg == inst.operands[1].reg
8699 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8707 constraint (inst.operands[1].reg % 2 != 0,
8708 _("even register required"));
8709 constraint (inst.operands[2].present
8710 && inst.operands[2].reg != inst.operands[1].reg + 1,
8711 _("can only store two consecutive registers"));
8712 /* If op 2 were present and equal to PC, this function wouldn't
8713 have been called in the first place. */
8714 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8716 constraint (inst.operands[0].reg == inst.operands[1].reg
8717 || inst.operands[0].reg == inst.operands[1].reg + 1
8718 || inst.operands[0].reg == inst.operands[3].reg,
8721 inst.instruction |= inst.operands[0].reg << 12;
8722 inst.instruction |= inst.operands[1].reg;
8723 inst.instruction |= inst.operands[3].reg << 16;
8730 constraint (inst.operands[0].reg == inst.operands[1].reg
8731 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8739 constraint (inst.operands[0].reg == inst.operands[1].reg
8740 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8745 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8746 extends it to 32-bits, and adds the result to a value in another
8747 register. You can specify a rotation by 0, 8, 16, or 24 bits
8748 before extracting the 16-bit value.
8749 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8750 Condition defaults to COND_ALWAYS.
8751 Error if any register uses R15. */
8756 inst.instruction |= inst.operands[0].reg << 12;
8757 inst.instruction |= inst.operands[1].reg << 16;
8758 inst.instruction |= inst.operands[2].reg;
8759 inst.instruction |= inst.operands[3].imm << 10;
8764 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8765 Condition defaults to COND_ALWAYS.
8766 Error if any register uses R15. */
8771 inst.instruction |= inst.operands[0].reg << 12;
8772 inst.instruction |= inst.operands[1].reg;
8773 inst.instruction |= inst.operands[2].imm << 10;
8776 /* VFP instructions. In a logical order: SP variant first, monad
8777 before dyad, arithmetic then move then load/store. */
8780 do_vfp_sp_monadic (void)
8782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8783 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8787 do_vfp_sp_dyadic (void)
8789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8790 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8791 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8795 do_vfp_sp_compare_z (void)
8797 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8801 do_vfp_dp_sp_cvt (void)
8803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8804 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8808 do_vfp_sp_dp_cvt (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8815 do_vfp_reg_from_sp (void)
8817 inst.instruction |= inst.operands[0].reg << 12;
8818 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8822 do_vfp_reg2_from_sp2 (void)
8824 constraint (inst.operands[2].imm != 2,
8825 _("only two consecutive VFP SP registers allowed here"));
8826 inst.instruction |= inst.operands[0].reg << 12;
8827 inst.instruction |= inst.operands[1].reg << 16;
8828 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8832 do_vfp_sp_from_reg (void)
8834 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8835 inst.instruction |= inst.operands[1].reg << 12;
8839 do_vfp_sp2_from_reg2 (void)
8841 constraint (inst.operands[0].imm != 2,
8842 _("only two consecutive VFP SP registers allowed here"));
8843 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8844 inst.instruction |= inst.operands[1].reg << 12;
8845 inst.instruction |= inst.operands[2].reg << 16;
8849 do_vfp_sp_ldst (void)
8851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8852 encode_arm_cp_address (1, FALSE, TRUE, 0);
8856 do_vfp_dp_ldst (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8859 encode_arm_cp_address (1, FALSE, TRUE, 0);
8864 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8866 if (inst.operands[0].writeback)
8867 inst.instruction |= WRITE_BACK;
8869 constraint (ldstm_type != VFP_LDSTMIA,
8870 _("this addressing mode requires base-register writeback"));
8871 inst.instruction |= inst.operands[0].reg << 16;
8872 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8873 inst.instruction |= inst.operands[1].imm;
8877 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8881 if (inst.operands[0].writeback)
8882 inst.instruction |= WRITE_BACK;
8884 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8885 _("this addressing mode requires base-register writeback"));
8887 inst.instruction |= inst.operands[0].reg << 16;
8888 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8890 count = inst.operands[1].imm << 1;
8891 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8894 inst.instruction |= count;
8898 do_vfp_sp_ldstmia (void)
8900 vfp_sp_ldstm (VFP_LDSTMIA);
8904 do_vfp_sp_ldstmdb (void)
8906 vfp_sp_ldstm (VFP_LDSTMDB);
8910 do_vfp_dp_ldstmia (void)
8912 vfp_dp_ldstm (VFP_LDSTMIA);
8916 do_vfp_dp_ldstmdb (void)
8918 vfp_dp_ldstm (VFP_LDSTMDB);
8922 do_vfp_xp_ldstmia (void)
8924 vfp_dp_ldstm (VFP_LDSTMIAX);
8928 do_vfp_xp_ldstmdb (void)
8930 vfp_dp_ldstm (VFP_LDSTMDBX);
8934 do_vfp_dp_rd_rm (void)
8936 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8937 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8941 do_vfp_dp_rn_rd (void)
8943 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8944 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8948 do_vfp_dp_rd_rn (void)
8950 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8951 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8955 do_vfp_dp_rd_rn_rm (void)
8957 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8958 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8959 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8965 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8969 do_vfp_dp_rm_rd_rn (void)
8971 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8972 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8973 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8976 /* VFPv3 instructions. */
8978 do_vfp_sp_const (void)
8980 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8981 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8982 inst.instruction |= (inst.operands[1].imm & 0x0f);
8986 do_vfp_dp_const (void)
8988 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8989 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8990 inst.instruction |= (inst.operands[1].imm & 0x0f);
8994 vfp_conv (int srcsize)
8996 int immbits = srcsize - inst.operands[1].imm;
8998 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9000 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9001 i.e. immbits must be in range 0 - 16. */
9002 inst.error = _("immediate value out of range, expected range [0, 16]");
9005 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9007 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9008 i.e. immbits must be in range 0 - 31. */
9009 inst.error = _("immediate value out of range, expected range [1, 32]");
9013 inst.instruction |= (immbits & 1) << 5;
9014 inst.instruction |= (immbits >> 1);
9018 do_vfp_sp_conv_16 (void)
9020 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9025 do_vfp_dp_conv_16 (void)
9027 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9032 do_vfp_sp_conv_32 (void)
9034 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9039 do_vfp_dp_conv_32 (void)
9041 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9045 /* FPA instructions. Also in a logical order. */
9050 inst.instruction |= inst.operands[0].reg << 16;
9051 inst.instruction |= inst.operands[1].reg;
9055 do_fpa_ldmstm (void)
9057 inst.instruction |= inst.operands[0].reg << 12;
9058 switch (inst.operands[1].imm)
9060 case 1: inst.instruction |= CP_T_X; break;
9061 case 2: inst.instruction |= CP_T_Y; break;
9062 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9067 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9069 /* The instruction specified "ea" or "fd", so we can only accept
9070 [Rn]{!}. The instruction does not really support stacking or
9071 unstacking, so we have to emulate these by setting appropriate
9072 bits and offsets. */
9073 constraint (inst.reloc.exp.X_op != O_constant
9074 || inst.reloc.exp.X_add_number != 0,
9075 _("this instruction does not support indexing"));
9077 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9078 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9080 if (!(inst.instruction & INDEX_UP))
9081 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9083 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9085 inst.operands[2].preind = 0;
9086 inst.operands[2].postind = 1;
9090 encode_arm_cp_address (2, TRUE, TRUE, 0);
9093 /* iWMMXt instructions: strictly in alphabetical order. */
9096 do_iwmmxt_tandorc (void)
9098 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9102 do_iwmmxt_textrc (void)
9104 inst.instruction |= inst.operands[0].reg << 12;
9105 inst.instruction |= inst.operands[1].imm;
9109 do_iwmmxt_textrm (void)
9111 inst.instruction |= inst.operands[0].reg << 12;
9112 inst.instruction |= inst.operands[1].reg << 16;
9113 inst.instruction |= inst.operands[2].imm;
9117 do_iwmmxt_tinsr (void)
9119 inst.instruction |= inst.operands[0].reg << 16;
9120 inst.instruction |= inst.operands[1].reg << 12;
9121 inst.instruction |= inst.operands[2].imm;
9125 do_iwmmxt_tmia (void)
9127 inst.instruction |= inst.operands[0].reg << 5;
9128 inst.instruction |= inst.operands[1].reg;
9129 inst.instruction |= inst.operands[2].reg << 12;
9133 do_iwmmxt_waligni (void)
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 inst.instruction |= inst.operands[1].reg << 16;
9137 inst.instruction |= inst.operands[2].reg;
9138 inst.instruction |= inst.operands[3].imm << 20;
9142 do_iwmmxt_wmerge (void)
9144 inst.instruction |= inst.operands[0].reg << 12;
9145 inst.instruction |= inst.operands[1].reg << 16;
9146 inst.instruction |= inst.operands[2].reg;
9147 inst.instruction |= inst.operands[3].imm << 21;
9151 do_iwmmxt_wmov (void)
9153 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9154 inst.instruction |= inst.operands[0].reg << 12;
9155 inst.instruction |= inst.operands[1].reg << 16;
9156 inst.instruction |= inst.operands[1].reg;
9160 do_iwmmxt_wldstbh (void)
9163 inst.instruction |= inst.operands[0].reg << 12;
9165 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9167 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9168 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9172 do_iwmmxt_wldstw (void)
9174 /* RIWR_RIWC clears .isreg for a control register. */
9175 if (!inst.operands[0].isreg)
9177 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9178 inst.instruction |= 0xf0000000;
9181 inst.instruction |= inst.operands[0].reg << 12;
9182 encode_arm_cp_address (1, TRUE, TRUE, 0);
9186 do_iwmmxt_wldstd (void)
9188 inst.instruction |= inst.operands[0].reg << 12;
9189 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9190 && inst.operands[1].immisreg)
9192 inst.instruction &= ~0x1a000ff;
9193 inst.instruction |= (0xf << 28);
9194 if (inst.operands[1].preind)
9195 inst.instruction |= PRE_INDEX;
9196 if (!inst.operands[1].negative)
9197 inst.instruction |= INDEX_UP;
9198 if (inst.operands[1].writeback)
9199 inst.instruction |= WRITE_BACK;
9200 inst.instruction |= inst.operands[1].reg << 16;
9201 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9202 inst.instruction |= inst.operands[1].imm;
9205 encode_arm_cp_address (1, TRUE, FALSE, 0);
9209 do_iwmmxt_wshufh (void)
9211 inst.instruction |= inst.operands[0].reg << 12;
9212 inst.instruction |= inst.operands[1].reg << 16;
9213 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9214 inst.instruction |= (inst.operands[2].imm & 0x0f);
9218 do_iwmmxt_wzero (void)
9220 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9221 inst.instruction |= inst.operands[0].reg;
9222 inst.instruction |= inst.operands[0].reg << 12;
9223 inst.instruction |= inst.operands[0].reg << 16;
9227 do_iwmmxt_wrwrwr_or_imm5 (void)
9229 if (inst.operands[2].isreg)
9232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9233 _("immediate operand requires iWMMXt2"));
9235 if (inst.operands[2].imm == 0)
9237 switch ((inst.instruction >> 20) & 0xf)
9243 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9244 inst.operands[2].imm = 16;
9245 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9251 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9252 inst.operands[2].imm = 32;
9253 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9260 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9262 wrn = (inst.instruction >> 16) & 0xf;
9263 inst.instruction &= 0xff0fff0f;
9264 inst.instruction |= wrn;
9265 /* Bail out here; the instruction is now assembled. */
9270 /* Map 32 -> 0, etc. */
9271 inst.operands[2].imm &= 0x1f;
9272 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9276 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9277 operations first, then control, shift, and load/store. */
9279 /* Insns like "foo X,Y,Z". */
9282 do_mav_triple (void)
9284 inst.instruction |= inst.operands[0].reg << 16;
9285 inst.instruction |= inst.operands[1].reg;
9286 inst.instruction |= inst.operands[2].reg << 12;
9289 /* Insns like "foo W,X,Y,Z".
9290 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9295 inst.instruction |= inst.operands[0].reg << 5;
9296 inst.instruction |= inst.operands[1].reg << 12;
9297 inst.instruction |= inst.operands[2].reg << 16;
9298 inst.instruction |= inst.operands[3].reg;
9301 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9305 inst.instruction |= inst.operands[1].reg << 12;
9308 /* Maverick shift immediate instructions.
9309 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9310 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9315 int imm = inst.operands[2].imm;
9317 inst.instruction |= inst.operands[0].reg << 12;
9318 inst.instruction |= inst.operands[1].reg << 16;
9320 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9321 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9322 Bit 4 should be 0. */
9323 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9325 inst.instruction |= imm;
9328 /* XScale instructions. Also sorted arithmetic before move. */
9330 /* Xscale multiply-accumulate (argument parse)
9333 MIAxycc acc0,Rm,Rs. */
9338 inst.instruction |= inst.operands[1].reg;
9339 inst.instruction |= inst.operands[2].reg << 12;
9342 /* Xscale move-accumulator-register (argument parse)
9344 MARcc acc0,RdLo,RdHi. */
9349 inst.instruction |= inst.operands[1].reg << 12;
9350 inst.instruction |= inst.operands[2].reg << 16;
9353 /* Xscale move-register-accumulator (argument parse)
9355 MRAcc RdLo,RdHi,acc0. */
9360 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9361 inst.instruction |= inst.operands[0].reg << 12;
9362 inst.instruction |= inst.operands[1].reg << 16;
9365 /* Encoding functions relevant only to Thumb. */
9367 /* inst.operands[i] is a shifted-register operand; encode
9368 it into inst.instruction in the format used by Thumb32. */
9371 encode_thumb32_shifted_operand (int i)
9373 unsigned int value = inst.reloc.exp.X_add_number;
9374 unsigned int shift = inst.operands[i].shift_kind;
9376 constraint (inst.operands[i].immisreg,
9377 _("shift by register not allowed in thumb mode"));
9378 inst.instruction |= inst.operands[i].reg;
9379 if (shift == SHIFT_RRX)
9380 inst.instruction |= SHIFT_ROR << 4;
9383 constraint (inst.reloc.exp.X_op != O_constant,
9384 _("expression too complex"));
9386 constraint (value > 32
9387 || (value == 32 && (shift == SHIFT_LSL
9388 || shift == SHIFT_ROR)),
9389 _("shift expression is too large"));
9393 else if (value == 32)
9396 inst.instruction |= shift << 4;
9397 inst.instruction |= (value & 0x1c) << 10;
9398 inst.instruction |= (value & 0x03) << 6;
9403 /* inst.operands[i] was set up by parse_address. Encode it into a
9404 Thumb32 format load or store instruction. Reject forms that cannot
9405 be used with such instructions. If is_t is true, reject forms that
9406 cannot be used with a T instruction; if is_d is true, reject forms
9407 that cannot be used with a D instruction. If it is a store insn,
9411 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9413 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9415 constraint (!inst.operands[i].isreg,
9416 _("Instruction does not support =N addresses"));
9418 inst.instruction |= inst.operands[i].reg << 16;
9419 if (inst.operands[i].immisreg)
9421 constraint (is_pc, BAD_PC_ADDRESSING);
9422 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9423 constraint (inst.operands[i].negative,
9424 _("Thumb does not support negative register indexing"));
9425 constraint (inst.operands[i].postind,
9426 _("Thumb does not support register post-indexing"));
9427 constraint (inst.operands[i].writeback,
9428 _("Thumb does not support register indexing with writeback"));
9429 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9430 _("Thumb supports only LSL in shifted register indexing"));
9432 inst.instruction |= inst.operands[i].imm;
9433 if (inst.operands[i].shifted)
9435 constraint (inst.reloc.exp.X_op != O_constant,
9436 _("expression too complex"));
9437 constraint (inst.reloc.exp.X_add_number < 0
9438 || inst.reloc.exp.X_add_number > 3,
9439 _("shift out of range"));
9440 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9442 inst.reloc.type = BFD_RELOC_UNUSED;
9444 else if (inst.operands[i].preind)
9446 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9447 constraint (is_t && inst.operands[i].writeback,
9448 _("cannot use writeback with this instruction"));
9449 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9454 inst.instruction |= 0x01000000;
9455 if (inst.operands[i].writeback)
9456 inst.instruction |= 0x00200000;
9460 inst.instruction |= 0x00000c00;
9461 if (inst.operands[i].writeback)
9462 inst.instruction |= 0x00000100;
9464 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9466 else if (inst.operands[i].postind)
9468 gas_assert (inst.operands[i].writeback);
9469 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9470 constraint (is_t, _("cannot use post-indexing with this instruction"));
9473 inst.instruction |= 0x00200000;
9475 inst.instruction |= 0x00000900;
9476 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9478 else /* unindexed - only for coprocessor */
9479 inst.error = _("instruction does not accept unindexed addressing");
9482 /* Table of Thumb instructions which exist in both 16- and 32-bit
9483 encodings (the latter only in post-V6T2 cores). The index is the
9484 value used in the insns table below. When there is more than one
9485 possible 16-bit encoding for the instruction, this table always
9487 Also contains several pseudo-instructions used during relaxation. */
9488 #define T16_32_TAB \
9489 X(_adc, 4140, eb400000), \
9490 X(_adcs, 4140, eb500000), \
9491 X(_add, 1c00, eb000000), \
9492 X(_adds, 1c00, eb100000), \
9493 X(_addi, 0000, f1000000), \
9494 X(_addis, 0000, f1100000), \
9495 X(_add_pc,000f, f20f0000), \
9496 X(_add_sp,000d, f10d0000), \
9497 X(_adr, 000f, f20f0000), \
9498 X(_and, 4000, ea000000), \
9499 X(_ands, 4000, ea100000), \
9500 X(_asr, 1000, fa40f000), \
9501 X(_asrs, 1000, fa50f000), \
9502 X(_b, e000, f000b000), \
9503 X(_bcond, d000, f0008000), \
9504 X(_bic, 4380, ea200000), \
9505 X(_bics, 4380, ea300000), \
9506 X(_cmn, 42c0, eb100f00), \
9507 X(_cmp, 2800, ebb00f00), \
9508 X(_cpsie, b660, f3af8400), \
9509 X(_cpsid, b670, f3af8600), \
9510 X(_cpy, 4600, ea4f0000), \
9511 X(_dec_sp,80dd, f1ad0d00), \
9512 X(_eor, 4040, ea800000), \
9513 X(_eors, 4040, ea900000), \
9514 X(_inc_sp,00dd, f10d0d00), \
9515 X(_ldmia, c800, e8900000), \
9516 X(_ldr, 6800, f8500000), \
9517 X(_ldrb, 7800, f8100000), \
9518 X(_ldrh, 8800, f8300000), \
9519 X(_ldrsb, 5600, f9100000), \
9520 X(_ldrsh, 5e00, f9300000), \
9521 X(_ldr_pc,4800, f85f0000), \
9522 X(_ldr_pc2,4800, f85f0000), \
9523 X(_ldr_sp,9800, f85d0000), \
9524 X(_lsl, 0000, fa00f000), \
9525 X(_lsls, 0000, fa10f000), \
9526 X(_lsr, 0800, fa20f000), \
9527 X(_lsrs, 0800, fa30f000), \
9528 X(_mov, 2000, ea4f0000), \
9529 X(_movs, 2000, ea5f0000), \
9530 X(_mul, 4340, fb00f000), \
9531 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9532 X(_mvn, 43c0, ea6f0000), \
9533 X(_mvns, 43c0, ea7f0000), \
9534 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9535 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9536 X(_orr, 4300, ea400000), \
9537 X(_orrs, 4300, ea500000), \
9538 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9539 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9540 X(_rev, ba00, fa90f080), \
9541 X(_rev16, ba40, fa90f090), \
9542 X(_revsh, bac0, fa90f0b0), \
9543 X(_ror, 41c0, fa60f000), \
9544 X(_rors, 41c0, fa70f000), \
9545 X(_sbc, 4180, eb600000), \
9546 X(_sbcs, 4180, eb700000), \
9547 X(_stmia, c000, e8800000), \
9548 X(_str, 6000, f8400000), \
9549 X(_strb, 7000, f8000000), \
9550 X(_strh, 8000, f8200000), \
9551 X(_str_sp,9000, f84d0000), \
9552 X(_sub, 1e00, eba00000), \
9553 X(_subs, 1e00, ebb00000), \
9554 X(_subi, 8000, f1a00000), \
9555 X(_subis, 8000, f1b00000), \
9556 X(_sxtb, b240, fa4ff080), \
9557 X(_sxth, b200, fa0ff080), \
9558 X(_tst, 4200, ea100f00), \
9559 X(_uxtb, b2c0, fa5ff080), \
9560 X(_uxth, b280, fa1ff080), \
9561 X(_nop, bf00, f3af8000), \
9562 X(_yield, bf10, f3af8001), \
9563 X(_wfe, bf20, f3af8002), \
9564 X(_wfi, bf30, f3af8003), \
9565 X(_sev, bf40, f3af8004), \
9566 X(_sevl, bf50, f3af8005), \
9567 X(_udf, de00, f7f0a000)
9569 /* To catch errors in encoding functions, the codes are all offset by
9570 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9571 as 16-bit instructions. */
9572 #define X(a,b,c) T_MNEM##a
9573 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9576 #define X(a,b,c) 0x##b
9577 static const unsigned short thumb_op16[] = { T16_32_TAB };
9578 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9581 #define X(a,b,c) 0x##c
9582 static const unsigned int thumb_op32[] = { T16_32_TAB };
9583 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9584 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9588 /* Thumb instruction encoders, in alphabetical order. */
9593 do_t_add_sub_w (void)
9597 Rd = inst.operands[0].reg;
9598 Rn = inst.operands[1].reg;
9600 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9601 is the SP-{plus,minus}-immediate form of the instruction. */
9603 constraint (Rd == REG_PC, BAD_PC);
9605 reject_bad_reg (Rd);
9607 inst.instruction |= (Rn << 16) | (Rd << 8);
9608 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9611 /* Parse an add or subtract instruction. We get here with inst.instruction
9612 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9619 Rd = inst.operands[0].reg;
9620 Rs = (inst.operands[1].present
9621 ? inst.operands[1].reg /* Rd, Rs, foo */
9622 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9625 set_it_insn_type_last ();
9633 flags = (inst.instruction == T_MNEM_adds
9634 || inst.instruction == T_MNEM_subs);
9636 narrow = !in_it_block ();
9638 narrow = in_it_block ();
9639 if (!inst.operands[2].isreg)
9643 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9645 add = (inst.instruction == T_MNEM_add
9646 || inst.instruction == T_MNEM_adds);
9648 if (inst.size_req != 4)
9650 /* Attempt to use a narrow opcode, with relaxation if
9652 if (Rd == REG_SP && Rs == REG_SP && !flags)
9653 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9654 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9655 opcode = T_MNEM_add_sp;
9656 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9657 opcode = T_MNEM_add_pc;
9658 else if (Rd <= 7 && Rs <= 7 && narrow)
9661 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9663 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9667 inst.instruction = THUMB_OP16(opcode);
9668 inst.instruction |= (Rd << 4) | Rs;
9669 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9670 if (inst.size_req != 2)
9671 inst.relax = opcode;
9674 constraint (inst.size_req == 2, BAD_HIREG);
9676 if (inst.size_req == 4
9677 || (inst.size_req != 2 && !opcode))
9681 constraint (add, BAD_PC);
9682 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9683 _("only SUBS PC, LR, #const allowed"));
9684 constraint (inst.reloc.exp.X_op != O_constant,
9685 _("expression too complex"));
9686 constraint (inst.reloc.exp.X_add_number < 0
9687 || inst.reloc.exp.X_add_number > 0xff,
9688 _("immediate value out of range"));
9689 inst.instruction = T2_SUBS_PC_LR
9690 | inst.reloc.exp.X_add_number;
9691 inst.reloc.type = BFD_RELOC_UNUSED;
9694 else if (Rs == REG_PC)
9696 /* Always use addw/subw. */
9697 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9698 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9702 inst.instruction = THUMB_OP32 (inst.instruction);
9703 inst.instruction = (inst.instruction & 0xe1ffffff)
9706 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9708 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9710 inst.instruction |= Rd << 8;
9711 inst.instruction |= Rs << 16;
9716 unsigned int value = inst.reloc.exp.X_add_number;
9717 unsigned int shift = inst.operands[2].shift_kind;
9719 Rn = inst.operands[2].reg;
9720 /* See if we can do this with a 16-bit instruction. */
9721 if (!inst.operands[2].shifted && inst.size_req != 4)
9723 if (Rd > 7 || Rs > 7 || Rn > 7)
9728 inst.instruction = ((inst.instruction == T_MNEM_adds
9729 || inst.instruction == T_MNEM_add)
9732 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9736 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9738 /* Thumb-1 cores (except v6-M) require at least one high
9739 register in a narrow non flag setting add. */
9740 if (Rd > 7 || Rn > 7
9741 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9742 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9749 inst.instruction = T_OPCODE_ADD_HI;
9750 inst.instruction |= (Rd & 8) << 4;
9751 inst.instruction |= (Rd & 7);
9752 inst.instruction |= Rn << 3;
9758 constraint (Rd == REG_PC, BAD_PC);
9759 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9760 constraint (Rs == REG_PC, BAD_PC);
9761 reject_bad_reg (Rn);
9763 /* If we get here, it can't be done in 16 bits. */
9764 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9765 _("shift must be constant"));
9766 inst.instruction = THUMB_OP32 (inst.instruction);
9767 inst.instruction |= Rd << 8;
9768 inst.instruction |= Rs << 16;
9769 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9770 _("shift value over 3 not allowed in thumb mode"));
9771 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9772 _("only LSL shift allowed in thumb mode"));
9773 encode_thumb32_shifted_operand (2);
9778 constraint (inst.instruction == T_MNEM_adds
9779 || inst.instruction == T_MNEM_subs,
9782 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9784 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9785 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9788 inst.instruction = (inst.instruction == T_MNEM_add
9790 inst.instruction |= (Rd << 4) | Rs;
9791 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9795 Rn = inst.operands[2].reg;
9796 constraint (inst.operands[2].shifted, _("unshifted register required"));
9798 /* We now have Rd, Rs, and Rn set to registers. */
9799 if (Rd > 7 || Rs > 7 || Rn > 7)
9801 /* Can't do this for SUB. */
9802 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9803 inst.instruction = T_OPCODE_ADD_HI;
9804 inst.instruction |= (Rd & 8) << 4;
9805 inst.instruction |= (Rd & 7);
9807 inst.instruction |= Rn << 3;
9809 inst.instruction |= Rs << 3;
9811 constraint (1, _("dest must overlap one source register"));
9815 inst.instruction = (inst.instruction == T_MNEM_add
9816 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9817 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9827 Rd = inst.operands[0].reg;
9828 reject_bad_reg (Rd);
9830 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9832 /* Defer to section relaxation. */
9833 inst.relax = inst.instruction;
9834 inst.instruction = THUMB_OP16 (inst.instruction);
9835 inst.instruction |= Rd << 4;
9837 else if (unified_syntax && inst.size_req != 2)
9839 /* Generate a 32-bit opcode. */
9840 inst.instruction = THUMB_OP32 (inst.instruction);
9841 inst.instruction |= Rd << 8;
9842 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9843 inst.reloc.pc_rel = 1;
9847 /* Generate a 16-bit opcode. */
9848 inst.instruction = THUMB_OP16 (inst.instruction);
9849 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9850 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9851 inst.reloc.pc_rel = 1;
9853 inst.instruction |= Rd << 4;
9857 /* Arithmetic instructions for which there is just one 16-bit
9858 instruction encoding, and it allows only two low registers.
9859 For maximal compatibility with ARM syntax, we allow three register
9860 operands even when Thumb-32 instructions are not available, as long
9861 as the first two are identical. For instance, both "sbc r0,r1" and
9862 "sbc r0,r0,r1" are allowed. */
9868 Rd = inst.operands[0].reg;
9869 Rs = (inst.operands[1].present
9870 ? inst.operands[1].reg /* Rd, Rs, foo */
9871 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9872 Rn = inst.operands[2].reg;
9874 reject_bad_reg (Rd);
9875 reject_bad_reg (Rs);
9876 if (inst.operands[2].isreg)
9877 reject_bad_reg (Rn);
9881 if (!inst.operands[2].isreg)
9883 /* For an immediate, we always generate a 32-bit opcode;
9884 section relaxation will shrink it later if possible. */
9885 inst.instruction = THUMB_OP32 (inst.instruction);
9886 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9887 inst.instruction |= Rd << 8;
9888 inst.instruction |= Rs << 16;
9889 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9895 /* See if we can do this with a 16-bit instruction. */
9896 if (THUMB_SETS_FLAGS (inst.instruction))
9897 narrow = !in_it_block ();
9899 narrow = in_it_block ();
9901 if (Rd > 7 || Rn > 7 || Rs > 7)
9903 if (inst.operands[2].shifted)
9905 if (inst.size_req == 4)
9911 inst.instruction = THUMB_OP16 (inst.instruction);
9912 inst.instruction |= Rd;
9913 inst.instruction |= Rn << 3;
9917 /* If we get here, it can't be done in 16 bits. */
9918 constraint (inst.operands[2].shifted
9919 && inst.operands[2].immisreg,
9920 _("shift must be constant"));
9921 inst.instruction = THUMB_OP32 (inst.instruction);
9922 inst.instruction |= Rd << 8;
9923 inst.instruction |= Rs << 16;
9924 encode_thumb32_shifted_operand (2);
9929 /* On its face this is a lie - the instruction does set the
9930 flags. However, the only supported mnemonic in this mode
9932 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9934 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9935 _("unshifted register required"));
9936 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9937 constraint (Rd != Rs,
9938 _("dest and source1 must be the same register"));
9940 inst.instruction = THUMB_OP16 (inst.instruction);
9941 inst.instruction |= Rd;
9942 inst.instruction |= Rn << 3;
9946 /* Similarly, but for instructions where the arithmetic operation is
9947 commutative, so we can allow either of them to be different from
9948 the destination operand in a 16-bit instruction. For instance, all
9949 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9956 Rd = inst.operands[0].reg;
9957 Rs = (inst.operands[1].present
9958 ? inst.operands[1].reg /* Rd, Rs, foo */
9959 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9960 Rn = inst.operands[2].reg;
9962 reject_bad_reg (Rd);
9963 reject_bad_reg (Rs);
9964 if (inst.operands[2].isreg)
9965 reject_bad_reg (Rn);
9969 if (!inst.operands[2].isreg)
9971 /* For an immediate, we always generate a 32-bit opcode;
9972 section relaxation will shrink it later if possible. */
9973 inst.instruction = THUMB_OP32 (inst.instruction);
9974 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9975 inst.instruction |= Rd << 8;
9976 inst.instruction |= Rs << 16;
9977 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9983 /* See if we can do this with a 16-bit instruction. */
9984 if (THUMB_SETS_FLAGS (inst.instruction))
9985 narrow = !in_it_block ();
9987 narrow = in_it_block ();
9989 if (Rd > 7 || Rn > 7 || Rs > 7)
9991 if (inst.operands[2].shifted)
9993 if (inst.size_req == 4)
10000 inst.instruction = THUMB_OP16 (inst.instruction);
10001 inst.instruction |= Rd;
10002 inst.instruction |= Rn << 3;
10007 inst.instruction = THUMB_OP16 (inst.instruction);
10008 inst.instruction |= Rd;
10009 inst.instruction |= Rs << 3;
10014 /* If we get here, it can't be done in 16 bits. */
10015 constraint (inst.operands[2].shifted
10016 && inst.operands[2].immisreg,
10017 _("shift must be constant"));
10018 inst.instruction = THUMB_OP32 (inst.instruction);
10019 inst.instruction |= Rd << 8;
10020 inst.instruction |= Rs << 16;
10021 encode_thumb32_shifted_operand (2);
10026 /* On its face this is a lie - the instruction does set the
10027 flags. However, the only supported mnemonic in this mode
10028 says it doesn't. */
10029 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10031 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10032 _("unshifted register required"));
10033 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10035 inst.instruction = THUMB_OP16 (inst.instruction);
10036 inst.instruction |= Rd;
10039 inst.instruction |= Rn << 3;
10041 inst.instruction |= Rs << 3;
10043 constraint (1, _("dest must overlap one source register"));
10051 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10052 constraint (msb > 32, _("bit-field extends past end of register"));
10053 /* The instruction encoding stores the LSB and MSB,
10054 not the LSB and width. */
10055 Rd = inst.operands[0].reg;
10056 reject_bad_reg (Rd);
10057 inst.instruction |= Rd << 8;
10058 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10059 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10060 inst.instruction |= msb - 1;
10069 Rd = inst.operands[0].reg;
10070 reject_bad_reg (Rd);
10072 /* #0 in second position is alternative syntax for bfc, which is
10073 the same instruction but with REG_PC in the Rm field. */
10074 if (!inst.operands[1].isreg)
10078 Rn = inst.operands[1].reg;
10079 reject_bad_reg (Rn);
10082 msb = inst.operands[2].imm + inst.operands[3].imm;
10083 constraint (msb > 32, _("bit-field extends past end of register"));
10084 /* The instruction encoding stores the LSB and MSB,
10085 not the LSB and width. */
10086 inst.instruction |= Rd << 8;
10087 inst.instruction |= Rn << 16;
10088 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10089 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10090 inst.instruction |= msb - 1;
10098 Rd = inst.operands[0].reg;
10099 Rn = inst.operands[1].reg;
10101 reject_bad_reg (Rd);
10102 reject_bad_reg (Rn);
10104 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10105 _("bit-field extends past end of register"));
10106 inst.instruction |= Rd << 8;
10107 inst.instruction |= Rn << 16;
10108 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10109 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10110 inst.instruction |= inst.operands[3].imm - 1;
10113 /* ARM V5 Thumb BLX (argument parse)
10114 BLX <target_addr> which is BLX(1)
10115 BLX <Rm> which is BLX(2)
10116 Unfortunately, there are two different opcodes for this mnemonic.
10117 So, the insns[].value is not used, and the code here zaps values
10118 into inst.instruction.
10120 ??? How to take advantage of the additional two bits of displacement
10121 available in Thumb32 mode? Need new relocation? */
10126 set_it_insn_type_last ();
10128 if (inst.operands[0].isreg)
10130 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10131 /* We have a register, so this is BLX(2). */
10132 inst.instruction |= inst.operands[0].reg << 3;
10136 /* No register. This must be BLX(1). */
10137 inst.instruction = 0xf000e800;
10138 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10150 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10152 if (in_it_block ())
10154 /* Conditional branches inside IT blocks are encoded as unconditional
10156 cond = COND_ALWAYS;
10161 if (cond != COND_ALWAYS)
10162 opcode = T_MNEM_bcond;
10164 opcode = inst.instruction;
10167 && (inst.size_req == 4
10168 || (inst.size_req != 2
10169 && (inst.operands[0].hasreloc
10170 || inst.reloc.exp.X_op == O_constant))))
10172 inst.instruction = THUMB_OP32(opcode);
10173 if (cond == COND_ALWAYS)
10174 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10177 gas_assert (cond != 0xF);
10178 inst.instruction |= cond << 22;
10179 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10184 inst.instruction = THUMB_OP16(opcode);
10185 if (cond == COND_ALWAYS)
10186 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10189 inst.instruction |= cond << 8;
10190 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10192 /* Allow section relaxation. */
10193 if (unified_syntax && inst.size_req != 2)
10194 inst.relax = opcode;
10196 inst.reloc.type = reloc;
10197 inst.reloc.pc_rel = 1;
10200 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10201 between the two is the maximum immediate allowed - which is passed in
10204 do_t_bkpt_hlt1 (int range)
10206 constraint (inst.cond != COND_ALWAYS,
10207 _("instruction is always unconditional"));
10208 if (inst.operands[0].present)
10210 constraint (inst.operands[0].imm > range,
10211 _("immediate value out of range"));
10212 inst.instruction |= inst.operands[0].imm;
10215 set_it_insn_type (NEUTRAL_IT_INSN);
10221 do_t_bkpt_hlt1 (63);
10227 do_t_bkpt_hlt1 (255);
10231 do_t_branch23 (void)
10233 set_it_insn_type_last ();
10234 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10236 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10237 this file. We used to simply ignore the PLT reloc type here --
10238 the branch encoding is now needed to deal with TLSCALL relocs.
10239 So if we see a PLT reloc now, put it back to how it used to be to
10240 keep the preexisting behaviour. */
10241 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10242 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10244 #if defined(OBJ_COFF)
10245 /* If the destination of the branch is a defined symbol which does not have
10246 the THUMB_FUNC attribute, then we must be calling a function which has
10247 the (interfacearm) attribute. We look for the Thumb entry point to that
10248 function and change the branch to refer to that function instead. */
10249 if ( inst.reloc.exp.X_op == O_symbol
10250 && inst.reloc.exp.X_add_symbol != NULL
10251 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10252 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10253 inst.reloc.exp.X_add_symbol =
10254 find_real_start (inst.reloc.exp.X_add_symbol);
10261 set_it_insn_type_last ();
10262 inst.instruction |= inst.operands[0].reg << 3;
10263 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10264 should cause the alignment to be checked once it is known. This is
10265 because BX PC only works if the instruction is word aligned. */
10273 set_it_insn_type_last ();
10274 Rm = inst.operands[0].reg;
10275 reject_bad_reg (Rm);
10276 inst.instruction |= Rm << 16;
10285 Rd = inst.operands[0].reg;
10286 Rm = inst.operands[1].reg;
10288 reject_bad_reg (Rd);
10289 reject_bad_reg (Rm);
10291 inst.instruction |= Rd << 8;
10292 inst.instruction |= Rm << 16;
10293 inst.instruction |= Rm;
10299 set_it_insn_type (OUTSIDE_IT_INSN);
10300 inst.instruction |= inst.operands[0].imm;
10306 set_it_insn_type (OUTSIDE_IT_INSN);
10308 && (inst.operands[1].present || inst.size_req == 4)
10309 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10311 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10312 inst.instruction = 0xf3af8000;
10313 inst.instruction |= imod << 9;
10314 inst.instruction |= inst.operands[0].imm << 5;
10315 if (inst.operands[1].present)
10316 inst.instruction |= 0x100 | inst.operands[1].imm;
10320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10321 && (inst.operands[0].imm & 4),
10322 _("selected processor does not support 'A' form "
10323 "of this instruction"));
10324 constraint (inst.operands[1].present || inst.size_req == 4,
10325 _("Thumb does not support the 2-argument "
10326 "form of this instruction"));
10327 inst.instruction |= inst.operands[0].imm;
10331 /* THUMB CPY instruction (argument parse). */
10336 if (inst.size_req == 4)
10338 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10339 inst.instruction |= inst.operands[0].reg << 8;
10340 inst.instruction |= inst.operands[1].reg;
10344 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10345 inst.instruction |= (inst.operands[0].reg & 0x7);
10346 inst.instruction |= inst.operands[1].reg << 3;
10353 set_it_insn_type (OUTSIDE_IT_INSN);
10354 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10355 inst.instruction |= inst.operands[0].reg;
10356 inst.reloc.pc_rel = 1;
10357 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10363 inst.instruction |= inst.operands[0].imm;
10369 unsigned Rd, Rn, Rm;
10371 Rd = inst.operands[0].reg;
10372 Rn = (inst.operands[1].present
10373 ? inst.operands[1].reg : Rd);
10374 Rm = inst.operands[2].reg;
10376 reject_bad_reg (Rd);
10377 reject_bad_reg (Rn);
10378 reject_bad_reg (Rm);
10380 inst.instruction |= Rd << 8;
10381 inst.instruction |= Rn << 16;
10382 inst.instruction |= Rm;
10388 if (unified_syntax && inst.size_req == 4)
10389 inst.instruction = THUMB_OP32 (inst.instruction);
10391 inst.instruction = THUMB_OP16 (inst.instruction);
10397 unsigned int cond = inst.operands[0].imm;
10399 set_it_insn_type (IT_INSN);
10400 now_it.mask = (inst.instruction & 0xf) | 0x10;
10402 now_it.warn_deprecated = FALSE;
10404 /* If the condition is a negative condition, invert the mask. */
10405 if ((cond & 0x1) == 0x0)
10407 unsigned int mask = inst.instruction & 0x000f;
10409 if ((mask & 0x7) == 0)
10411 /* No conversion needed. */
10412 now_it.block_length = 1;
10414 else if ((mask & 0x3) == 0)
10417 now_it.block_length = 2;
10419 else if ((mask & 0x1) == 0)
10422 now_it.block_length = 3;
10427 now_it.block_length = 4;
10430 inst.instruction &= 0xfff0;
10431 inst.instruction |= mask;
10434 inst.instruction |= cond << 4;
10437 /* Helper function used for both push/pop and ldm/stm. */
10439 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10443 load = (inst.instruction & (1 << 20)) != 0;
10445 if (mask & (1 << 13))
10446 inst.error = _("SP not allowed in register list");
10448 if ((mask & (1 << base)) != 0
10450 inst.error = _("having the base register in the register list when "
10451 "using write back is UNPREDICTABLE");
10455 if (mask & (1 << 15))
10457 if (mask & (1 << 14))
10458 inst.error = _("LR and PC should not both be in register list");
10460 set_it_insn_type_last ();
10465 if (mask & (1 << 15))
10466 inst.error = _("PC not allowed in register list");
10469 if ((mask & (mask - 1)) == 0)
10471 /* Single register transfers implemented as str/ldr. */
10474 if (inst.instruction & (1 << 23))
10475 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10477 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10481 if (inst.instruction & (1 << 23))
10482 inst.instruction = 0x00800000; /* ia -> [base] */
10484 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10487 inst.instruction |= 0xf8400000;
10489 inst.instruction |= 0x00100000;
10491 mask = ffs (mask) - 1;
10494 else if (writeback)
10495 inst.instruction |= WRITE_BACK;
10497 inst.instruction |= mask;
10498 inst.instruction |= base << 16;
10504 /* This really doesn't seem worth it. */
10505 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10506 _("expression too complex"));
10507 constraint (inst.operands[1].writeback,
10508 _("Thumb load/store multiple does not support {reglist}^"));
10510 if (unified_syntax)
10512 bfd_boolean narrow;
10516 /* See if we can use a 16-bit instruction. */
10517 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10518 && inst.size_req != 4
10519 && !(inst.operands[1].imm & ~0xff))
10521 mask = 1 << inst.operands[0].reg;
10523 if (inst.operands[0].reg <= 7)
10525 if (inst.instruction == T_MNEM_stmia
10526 ? inst.operands[0].writeback
10527 : (inst.operands[0].writeback
10528 == !(inst.operands[1].imm & mask)))
10530 if (inst.instruction == T_MNEM_stmia
10531 && (inst.operands[1].imm & mask)
10532 && (inst.operands[1].imm & (mask - 1)))
10533 as_warn (_("value stored for r%d is UNKNOWN"),
10534 inst.operands[0].reg);
10536 inst.instruction = THUMB_OP16 (inst.instruction);
10537 inst.instruction |= inst.operands[0].reg << 8;
10538 inst.instruction |= inst.operands[1].imm;
10541 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10543 /* This means 1 register in reg list one of 3 situations:
10544 1. Instruction is stmia, but without writeback.
10545 2. lmdia without writeback, but with Rn not in
10547 3. ldmia with writeback, but with Rn in reglist.
10548 Case 3 is UNPREDICTABLE behaviour, so we handle
10549 case 1 and 2 which can be converted into a 16-bit
10550 str or ldr. The SP cases are handled below. */
10551 unsigned long opcode;
10552 /* First, record an error for Case 3. */
10553 if (inst.operands[1].imm & mask
10554 && inst.operands[0].writeback)
10556 _("having the base register in the register list when "
10557 "using write back is UNPREDICTABLE");
10559 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10561 inst.instruction = THUMB_OP16 (opcode);
10562 inst.instruction |= inst.operands[0].reg << 3;
10563 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10567 else if (inst.operands[0] .reg == REG_SP)
10569 if (inst.operands[0].writeback)
10572 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10573 ? T_MNEM_push : T_MNEM_pop);
10574 inst.instruction |= inst.operands[1].imm;
10577 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10580 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10581 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10582 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10590 if (inst.instruction < 0xffff)
10591 inst.instruction = THUMB_OP32 (inst.instruction);
10593 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10594 inst.operands[0].writeback);
10599 constraint (inst.operands[0].reg > 7
10600 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10601 constraint (inst.instruction != T_MNEM_ldmia
10602 && inst.instruction != T_MNEM_stmia,
10603 _("Thumb-2 instruction only valid in unified syntax"));
10604 if (inst.instruction == T_MNEM_stmia)
10606 if (!inst.operands[0].writeback)
10607 as_warn (_("this instruction will write back the base register"));
10608 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10609 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10610 as_warn (_("value stored for r%d is UNKNOWN"),
10611 inst.operands[0].reg);
10615 if (!inst.operands[0].writeback
10616 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10617 as_warn (_("this instruction will write back the base register"));
10618 else if (inst.operands[0].writeback
10619 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10620 as_warn (_("this instruction will not write back the base register"));
10623 inst.instruction = THUMB_OP16 (inst.instruction);
10624 inst.instruction |= inst.operands[0].reg << 8;
10625 inst.instruction |= inst.operands[1].imm;
10632 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10633 || inst.operands[1].postind || inst.operands[1].writeback
10634 || inst.operands[1].immisreg || inst.operands[1].shifted
10635 || inst.operands[1].negative,
10638 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10640 inst.instruction |= inst.operands[0].reg << 12;
10641 inst.instruction |= inst.operands[1].reg << 16;
10642 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10648 if (!inst.operands[1].present)
10650 constraint (inst.operands[0].reg == REG_LR,
10651 _("r14 not allowed as first register "
10652 "when second register is omitted"));
10653 inst.operands[1].reg = inst.operands[0].reg + 1;
10655 constraint (inst.operands[0].reg == inst.operands[1].reg,
10658 inst.instruction |= inst.operands[0].reg << 12;
10659 inst.instruction |= inst.operands[1].reg << 8;
10660 inst.instruction |= inst.operands[2].reg << 16;
10666 unsigned long opcode;
10669 if (inst.operands[0].isreg
10670 && !inst.operands[0].preind
10671 && inst.operands[0].reg == REG_PC)
10672 set_it_insn_type_last ();
10674 opcode = inst.instruction;
10675 if (unified_syntax)
10677 if (!inst.operands[1].isreg)
10679 if (opcode <= 0xffff)
10680 inst.instruction = THUMB_OP32 (opcode);
10681 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10684 if (inst.operands[1].isreg
10685 && !inst.operands[1].writeback
10686 && !inst.operands[1].shifted && !inst.operands[1].postind
10687 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10688 && opcode <= 0xffff
10689 && inst.size_req != 4)
10691 /* Insn may have a 16-bit form. */
10692 Rn = inst.operands[1].reg;
10693 if (inst.operands[1].immisreg)
10695 inst.instruction = THUMB_OP16 (opcode);
10697 if (Rn <= 7 && inst.operands[1].imm <= 7)
10699 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10700 reject_bad_reg (inst.operands[1].imm);
10702 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10703 && opcode != T_MNEM_ldrsb)
10704 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10705 || (Rn == REG_SP && opcode == T_MNEM_str))
10712 if (inst.reloc.pc_rel)
10713 opcode = T_MNEM_ldr_pc2;
10715 opcode = T_MNEM_ldr_pc;
10719 if (opcode == T_MNEM_ldr)
10720 opcode = T_MNEM_ldr_sp;
10722 opcode = T_MNEM_str_sp;
10724 inst.instruction = inst.operands[0].reg << 8;
10728 inst.instruction = inst.operands[0].reg;
10729 inst.instruction |= inst.operands[1].reg << 3;
10731 inst.instruction |= THUMB_OP16 (opcode);
10732 if (inst.size_req == 2)
10733 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10735 inst.relax = opcode;
10739 /* Definitely a 32-bit variant. */
10741 /* Warning for Erratum 752419. */
10742 if (opcode == T_MNEM_ldr
10743 && inst.operands[0].reg == REG_SP
10744 && inst.operands[1].writeback == 1
10745 && !inst.operands[1].immisreg)
10747 if (no_cpu_selected ()
10748 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10749 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10751 as_warn (_("This instruction may be unpredictable "
10752 "if executed on M-profile cores "
10753 "with interrupts enabled."));
10756 /* Do some validations regarding addressing modes. */
10757 if (inst.operands[1].immisreg)
10758 reject_bad_reg (inst.operands[1].imm);
10760 constraint (inst.operands[1].writeback == 1
10761 && inst.operands[0].reg == inst.operands[1].reg,
10764 inst.instruction = THUMB_OP32 (opcode);
10765 inst.instruction |= inst.operands[0].reg << 12;
10766 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10767 check_ldr_r15_aligned ();
10771 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10773 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10775 /* Only [Rn,Rm] is acceptable. */
10776 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10777 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10778 || inst.operands[1].postind || inst.operands[1].shifted
10779 || inst.operands[1].negative,
10780 _("Thumb does not support this addressing mode"));
10781 inst.instruction = THUMB_OP16 (inst.instruction);
10785 inst.instruction = THUMB_OP16 (inst.instruction);
10786 if (!inst.operands[1].isreg)
10787 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10790 constraint (!inst.operands[1].preind
10791 || inst.operands[1].shifted
10792 || inst.operands[1].writeback,
10793 _("Thumb does not support this addressing mode"));
10794 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10796 constraint (inst.instruction & 0x0600,
10797 _("byte or halfword not valid for base register"));
10798 constraint (inst.operands[1].reg == REG_PC
10799 && !(inst.instruction & THUMB_LOAD_BIT),
10800 _("r15 based store not allowed"));
10801 constraint (inst.operands[1].immisreg,
10802 _("invalid base register for register offset"));
10804 if (inst.operands[1].reg == REG_PC)
10805 inst.instruction = T_OPCODE_LDR_PC;
10806 else if (inst.instruction & THUMB_LOAD_BIT)
10807 inst.instruction = T_OPCODE_LDR_SP;
10809 inst.instruction = T_OPCODE_STR_SP;
10811 inst.instruction |= inst.operands[0].reg << 8;
10812 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10816 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10817 if (!inst.operands[1].immisreg)
10819 /* Immediate offset. */
10820 inst.instruction |= inst.operands[0].reg;
10821 inst.instruction |= inst.operands[1].reg << 3;
10822 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10826 /* Register offset. */
10827 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10828 constraint (inst.operands[1].negative,
10829 _("Thumb does not support this addressing mode"));
10832 switch (inst.instruction)
10834 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10835 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10836 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10837 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10838 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10839 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10840 case 0x5600 /* ldrsb */:
10841 case 0x5e00 /* ldrsh */: break;
10845 inst.instruction |= inst.operands[0].reg;
10846 inst.instruction |= inst.operands[1].reg << 3;
10847 inst.instruction |= inst.operands[1].imm << 6;
10853 if (!inst.operands[1].present)
10855 inst.operands[1].reg = inst.operands[0].reg + 1;
10856 constraint (inst.operands[0].reg == REG_LR,
10857 _("r14 not allowed here"));
10858 constraint (inst.operands[0].reg == REG_R12,
10859 _("r12 not allowed here"));
10862 if (inst.operands[2].writeback
10863 && (inst.operands[0].reg == inst.operands[2].reg
10864 || inst.operands[1].reg == inst.operands[2].reg))
10865 as_warn (_("base register written back, and overlaps "
10866 "one of transfer registers"));
10868 inst.instruction |= inst.operands[0].reg << 12;
10869 inst.instruction |= inst.operands[1].reg << 8;
10870 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10876 inst.instruction |= inst.operands[0].reg << 12;
10877 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10883 unsigned Rd, Rn, Rm, Ra;
10885 Rd = inst.operands[0].reg;
10886 Rn = inst.operands[1].reg;
10887 Rm = inst.operands[2].reg;
10888 Ra = inst.operands[3].reg;
10890 reject_bad_reg (Rd);
10891 reject_bad_reg (Rn);
10892 reject_bad_reg (Rm);
10893 reject_bad_reg (Ra);
10895 inst.instruction |= Rd << 8;
10896 inst.instruction |= Rn << 16;
10897 inst.instruction |= Rm;
10898 inst.instruction |= Ra << 12;
10904 unsigned RdLo, RdHi, Rn, Rm;
10906 RdLo = inst.operands[0].reg;
10907 RdHi = inst.operands[1].reg;
10908 Rn = inst.operands[2].reg;
10909 Rm = inst.operands[3].reg;
10911 reject_bad_reg (RdLo);
10912 reject_bad_reg (RdHi);
10913 reject_bad_reg (Rn);
10914 reject_bad_reg (Rm);
10916 inst.instruction |= RdLo << 12;
10917 inst.instruction |= RdHi << 8;
10918 inst.instruction |= Rn << 16;
10919 inst.instruction |= Rm;
10923 do_t_mov_cmp (void)
10927 Rn = inst.operands[0].reg;
10928 Rm = inst.operands[1].reg;
10931 set_it_insn_type_last ();
10933 if (unified_syntax)
10935 int r0off = (inst.instruction == T_MNEM_mov
10936 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10937 unsigned long opcode;
10938 bfd_boolean narrow;
10939 bfd_boolean low_regs;
10941 low_regs = (Rn <= 7 && Rm <= 7);
10942 opcode = inst.instruction;
10943 if (in_it_block ())
10944 narrow = opcode != T_MNEM_movs;
10946 narrow = opcode != T_MNEM_movs || low_regs;
10947 if (inst.size_req == 4
10948 || inst.operands[1].shifted)
10951 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10952 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10953 && !inst.operands[1].shifted
10957 inst.instruction = T2_SUBS_PC_LR;
10961 if (opcode == T_MNEM_cmp)
10963 constraint (Rn == REG_PC, BAD_PC);
10966 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10968 warn_deprecated_sp (Rm);
10969 /* R15 was documented as a valid choice for Rm in ARMv6,
10970 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10971 tools reject R15, so we do too. */
10972 constraint (Rm == REG_PC, BAD_PC);
10975 reject_bad_reg (Rm);
10977 else if (opcode == T_MNEM_mov
10978 || opcode == T_MNEM_movs)
10980 if (inst.operands[1].isreg)
10982 if (opcode == T_MNEM_movs)
10984 reject_bad_reg (Rn);
10985 reject_bad_reg (Rm);
10989 /* This is mov.n. */
10990 if ((Rn == REG_SP || Rn == REG_PC)
10991 && (Rm == REG_SP || Rm == REG_PC))
10993 as_warn (_("Use of r%u as a source register is "
10994 "deprecated when r%u is the destination "
10995 "register."), Rm, Rn);
11000 /* This is mov.w. */
11001 constraint (Rn == REG_PC, BAD_PC);
11002 constraint (Rm == REG_PC, BAD_PC);
11003 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11007 reject_bad_reg (Rn);
11010 if (!inst.operands[1].isreg)
11012 /* Immediate operand. */
11013 if (!in_it_block () && opcode == T_MNEM_mov)
11015 if (low_regs && narrow)
11017 inst.instruction = THUMB_OP16 (opcode);
11018 inst.instruction |= Rn << 8;
11019 if (inst.size_req == 2)
11020 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11022 inst.relax = opcode;
11026 inst.instruction = THUMB_OP32 (inst.instruction);
11027 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11028 inst.instruction |= Rn << r0off;
11029 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11032 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11033 && (inst.instruction == T_MNEM_mov
11034 || inst.instruction == T_MNEM_movs))
11036 /* Register shifts are encoded as separate shift instructions. */
11037 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11039 if (in_it_block ())
11044 if (inst.size_req == 4)
11047 if (!low_regs || inst.operands[1].imm > 7)
11053 switch (inst.operands[1].shift_kind)
11056 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11059 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11062 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11065 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11071 inst.instruction = opcode;
11074 inst.instruction |= Rn;
11075 inst.instruction |= inst.operands[1].imm << 3;
11080 inst.instruction |= CONDS_BIT;
11082 inst.instruction |= Rn << 8;
11083 inst.instruction |= Rm << 16;
11084 inst.instruction |= inst.operands[1].imm;
11089 /* Some mov with immediate shift have narrow variants.
11090 Register shifts are handled above. */
11091 if (low_regs && inst.operands[1].shifted
11092 && (inst.instruction == T_MNEM_mov
11093 || inst.instruction == T_MNEM_movs))
11095 if (in_it_block ())
11096 narrow = (inst.instruction == T_MNEM_mov);
11098 narrow = (inst.instruction == T_MNEM_movs);
11103 switch (inst.operands[1].shift_kind)
11105 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11106 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11107 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11108 default: narrow = FALSE; break;
11114 inst.instruction |= Rn;
11115 inst.instruction |= Rm << 3;
11116 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11120 inst.instruction = THUMB_OP32 (inst.instruction);
11121 inst.instruction |= Rn << r0off;
11122 encode_thumb32_shifted_operand (1);
11126 switch (inst.instruction)
11129 /* In v4t or v5t a move of two lowregs produces unpredictable
11130 results. Don't allow this. */
11133 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11134 "MOV Rd, Rs with two low registers is not "
11135 "permitted on this architecture");
11136 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11140 inst.instruction = T_OPCODE_MOV_HR;
11141 inst.instruction |= (Rn & 0x8) << 4;
11142 inst.instruction |= (Rn & 0x7);
11143 inst.instruction |= Rm << 3;
11147 /* We know we have low registers at this point.
11148 Generate LSLS Rd, Rs, #0. */
11149 inst.instruction = T_OPCODE_LSL_I;
11150 inst.instruction |= Rn;
11151 inst.instruction |= Rm << 3;
11157 inst.instruction = T_OPCODE_CMP_LR;
11158 inst.instruction |= Rn;
11159 inst.instruction |= Rm << 3;
11163 inst.instruction = T_OPCODE_CMP_HR;
11164 inst.instruction |= (Rn & 0x8) << 4;
11165 inst.instruction |= (Rn & 0x7);
11166 inst.instruction |= Rm << 3;
11173 inst.instruction = THUMB_OP16 (inst.instruction);
11175 /* PR 10443: Do not silently ignore shifted operands. */
11176 constraint (inst.operands[1].shifted,
11177 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11179 if (inst.operands[1].isreg)
11181 if (Rn < 8 && Rm < 8)
11183 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11184 since a MOV instruction produces unpredictable results. */
11185 if (inst.instruction == T_OPCODE_MOV_I8)
11186 inst.instruction = T_OPCODE_ADD_I3;
11188 inst.instruction = T_OPCODE_CMP_LR;
11190 inst.instruction |= Rn;
11191 inst.instruction |= Rm << 3;
11195 if (inst.instruction == T_OPCODE_MOV_I8)
11196 inst.instruction = T_OPCODE_MOV_HR;
11198 inst.instruction = T_OPCODE_CMP_HR;
11204 constraint (Rn > 7,
11205 _("only lo regs allowed with immediate"));
11206 inst.instruction |= Rn << 8;
11207 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11218 top = (inst.instruction & 0x00800000) != 0;
11219 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11221 constraint (top, _(":lower16: not allowed this instruction"));
11222 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11224 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11226 constraint (!top, _(":upper16: not allowed this instruction"));
11227 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11230 Rd = inst.operands[0].reg;
11231 reject_bad_reg (Rd);
11233 inst.instruction |= Rd << 8;
11234 if (inst.reloc.type == BFD_RELOC_UNUSED)
11236 imm = inst.reloc.exp.X_add_number;
11237 inst.instruction |= (imm & 0xf000) << 4;
11238 inst.instruction |= (imm & 0x0800) << 15;
11239 inst.instruction |= (imm & 0x0700) << 4;
11240 inst.instruction |= (imm & 0x00ff);
11245 do_t_mvn_tst (void)
11249 Rn = inst.operands[0].reg;
11250 Rm = inst.operands[1].reg;
11252 if (inst.instruction == T_MNEM_cmp
11253 || inst.instruction == T_MNEM_cmn)
11254 constraint (Rn == REG_PC, BAD_PC);
11256 reject_bad_reg (Rn);
11257 reject_bad_reg (Rm);
11259 if (unified_syntax)
11261 int r0off = (inst.instruction == T_MNEM_mvn
11262 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11263 bfd_boolean narrow;
11265 if (inst.size_req == 4
11266 || inst.instruction > 0xffff
11267 || inst.operands[1].shifted
11268 || Rn > 7 || Rm > 7)
11270 else if (inst.instruction == T_MNEM_cmn)
11272 else if (THUMB_SETS_FLAGS (inst.instruction))
11273 narrow = !in_it_block ();
11275 narrow = in_it_block ();
11277 if (!inst.operands[1].isreg)
11279 /* For an immediate, we always generate a 32-bit opcode;
11280 section relaxation will shrink it later if possible. */
11281 if (inst.instruction < 0xffff)
11282 inst.instruction = THUMB_OP32 (inst.instruction);
11283 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11284 inst.instruction |= Rn << r0off;
11285 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11289 /* See if we can do this with a 16-bit instruction. */
11292 inst.instruction = THUMB_OP16 (inst.instruction);
11293 inst.instruction |= Rn;
11294 inst.instruction |= Rm << 3;
11298 constraint (inst.operands[1].shifted
11299 && inst.operands[1].immisreg,
11300 _("shift must be constant"));
11301 if (inst.instruction < 0xffff)
11302 inst.instruction = THUMB_OP32 (inst.instruction);
11303 inst.instruction |= Rn << r0off;
11304 encode_thumb32_shifted_operand (1);
11310 constraint (inst.instruction > 0xffff
11311 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11312 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11313 _("unshifted register required"));
11314 constraint (Rn > 7 || Rm > 7,
11317 inst.instruction = THUMB_OP16 (inst.instruction);
11318 inst.instruction |= Rn;
11319 inst.instruction |= Rm << 3;
11328 if (do_vfp_nsyn_mrs () == SUCCESS)
11331 Rd = inst.operands[0].reg;
11332 reject_bad_reg (Rd);
11333 inst.instruction |= Rd << 8;
11335 if (inst.operands[1].isreg)
11337 unsigned br = inst.operands[1].reg;
11338 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11339 as_bad (_("bad register for mrs"));
11341 inst.instruction |= br & (0xf << 16);
11342 inst.instruction |= (br & 0x300) >> 4;
11343 inst.instruction |= (br & SPSR_BIT) >> 2;
11347 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11349 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11351 /* PR gas/12698: The constraint is only applied for m_profile.
11352 If the user has specified -march=all, we want to ignore it as
11353 we are building for any CPU type, including non-m variants. */
11354 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11355 constraint ((flags != 0) && m_profile, _("selected processor does "
11356 "not support requested special purpose register"));
11359 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11361 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11362 _("'APSR', 'CPSR' or 'SPSR' expected"));
11364 inst.instruction |= (flags & SPSR_BIT) >> 2;
11365 inst.instruction |= inst.operands[1].imm & 0xff;
11366 inst.instruction |= 0xf0000;
11376 if (do_vfp_nsyn_msr () == SUCCESS)
11379 constraint (!inst.operands[1].isreg,
11380 _("Thumb encoding does not support an immediate here"));
11382 if (inst.operands[0].isreg)
11383 flags = (int)(inst.operands[0].reg);
11385 flags = inst.operands[0].imm;
11387 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11389 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11391 /* PR gas/12698: The constraint is only applied for m_profile.
11392 If the user has specified -march=all, we want to ignore it as
11393 we are building for any CPU type, including non-m variants. */
11394 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11395 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11396 && (bits & ~(PSR_s | PSR_f)) != 0)
11397 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11398 && bits != PSR_f)) && m_profile,
11399 _("selected processor does not support requested special "
11400 "purpose register"));
11403 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11404 "requested special purpose register"));
11406 Rn = inst.operands[1].reg;
11407 reject_bad_reg (Rn);
11409 inst.instruction |= (flags & SPSR_BIT) >> 2;
11410 inst.instruction |= (flags & 0xf0000) >> 8;
11411 inst.instruction |= (flags & 0x300) >> 4;
11412 inst.instruction |= (flags & 0xff);
11413 inst.instruction |= Rn << 16;
11419 bfd_boolean narrow;
11420 unsigned Rd, Rn, Rm;
11422 if (!inst.operands[2].present)
11423 inst.operands[2].reg = inst.operands[0].reg;
11425 Rd = inst.operands[0].reg;
11426 Rn = inst.operands[1].reg;
11427 Rm = inst.operands[2].reg;
11429 if (unified_syntax)
11431 if (inst.size_req == 4
11437 else if (inst.instruction == T_MNEM_muls)
11438 narrow = !in_it_block ();
11440 narrow = in_it_block ();
11444 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11445 constraint (Rn > 7 || Rm > 7,
11452 /* 16-bit MULS/Conditional MUL. */
11453 inst.instruction = THUMB_OP16 (inst.instruction);
11454 inst.instruction |= Rd;
11457 inst.instruction |= Rm << 3;
11459 inst.instruction |= Rn << 3;
11461 constraint (1, _("dest must overlap one source register"));
11465 constraint (inst.instruction != T_MNEM_mul,
11466 _("Thumb-2 MUL must not set flags"));
11468 inst.instruction = THUMB_OP32 (inst.instruction);
11469 inst.instruction |= Rd << 8;
11470 inst.instruction |= Rn << 16;
11471 inst.instruction |= Rm << 0;
11473 reject_bad_reg (Rd);
11474 reject_bad_reg (Rn);
11475 reject_bad_reg (Rm);
11482 unsigned RdLo, RdHi, Rn, Rm;
11484 RdLo = inst.operands[0].reg;
11485 RdHi = inst.operands[1].reg;
11486 Rn = inst.operands[2].reg;
11487 Rm = inst.operands[3].reg;
11489 reject_bad_reg (RdLo);
11490 reject_bad_reg (RdHi);
11491 reject_bad_reg (Rn);
11492 reject_bad_reg (Rm);
11494 inst.instruction |= RdLo << 12;
11495 inst.instruction |= RdHi << 8;
11496 inst.instruction |= Rn << 16;
11497 inst.instruction |= Rm;
11500 as_tsktsk (_("rdhi and rdlo must be different"));
11506 set_it_insn_type (NEUTRAL_IT_INSN);
11508 if (unified_syntax)
11510 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11512 inst.instruction = THUMB_OP32 (inst.instruction);
11513 inst.instruction |= inst.operands[0].imm;
11517 /* PR9722: Check for Thumb2 availability before
11518 generating a thumb2 nop instruction. */
11519 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11521 inst.instruction = THUMB_OP16 (inst.instruction);
11522 inst.instruction |= inst.operands[0].imm << 4;
11525 inst.instruction = 0x46c0;
11530 constraint (inst.operands[0].present,
11531 _("Thumb does not support NOP with hints"));
11532 inst.instruction = 0x46c0;
11539 if (unified_syntax)
11541 bfd_boolean narrow;
11543 if (THUMB_SETS_FLAGS (inst.instruction))
11544 narrow = !in_it_block ();
11546 narrow = in_it_block ();
11547 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11549 if (inst.size_req == 4)
11554 inst.instruction = THUMB_OP32 (inst.instruction);
11555 inst.instruction |= inst.operands[0].reg << 8;
11556 inst.instruction |= inst.operands[1].reg << 16;
11560 inst.instruction = THUMB_OP16 (inst.instruction);
11561 inst.instruction |= inst.operands[0].reg;
11562 inst.instruction |= inst.operands[1].reg << 3;
11567 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11569 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11571 inst.instruction = THUMB_OP16 (inst.instruction);
11572 inst.instruction |= inst.operands[0].reg;
11573 inst.instruction |= inst.operands[1].reg << 3;
11582 Rd = inst.operands[0].reg;
11583 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11585 reject_bad_reg (Rd);
11586 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11587 reject_bad_reg (Rn);
11589 inst.instruction |= Rd << 8;
11590 inst.instruction |= Rn << 16;
11592 if (!inst.operands[2].isreg)
11594 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11595 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11601 Rm = inst.operands[2].reg;
11602 reject_bad_reg (Rm);
11604 constraint (inst.operands[2].shifted
11605 && inst.operands[2].immisreg,
11606 _("shift must be constant"));
11607 encode_thumb32_shifted_operand (2);
11614 unsigned Rd, Rn, Rm;
11616 Rd = inst.operands[0].reg;
11617 Rn = inst.operands[1].reg;
11618 Rm = inst.operands[2].reg;
11620 reject_bad_reg (Rd);
11621 reject_bad_reg (Rn);
11622 reject_bad_reg (Rm);
11624 inst.instruction |= Rd << 8;
11625 inst.instruction |= Rn << 16;
11626 inst.instruction |= Rm;
11627 if (inst.operands[3].present)
11629 unsigned int val = inst.reloc.exp.X_add_number;
11630 constraint (inst.reloc.exp.X_op != O_constant,
11631 _("expression too complex"));
11632 inst.instruction |= (val & 0x1c) << 10;
11633 inst.instruction |= (val & 0x03) << 6;
11640 if (!inst.operands[3].present)
11644 inst.instruction &= ~0x00000020;
11646 /* PR 10168. Swap the Rm and Rn registers. */
11647 Rtmp = inst.operands[1].reg;
11648 inst.operands[1].reg = inst.operands[2].reg;
11649 inst.operands[2].reg = Rtmp;
11657 if (inst.operands[0].immisreg)
11658 reject_bad_reg (inst.operands[0].imm);
11660 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11664 do_t_push_pop (void)
11668 constraint (inst.operands[0].writeback,
11669 _("push/pop do not support {reglist}^"));
11670 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11671 _("expression too complex"));
11673 mask = inst.operands[0].imm;
11674 if ((mask & ~0xff) == 0)
11675 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11676 else if ((inst.instruction == T_MNEM_push
11677 && (mask & ~0xff) == 1 << REG_LR)
11678 || (inst.instruction == T_MNEM_pop
11679 && (mask & ~0xff) == 1 << REG_PC))
11681 inst.instruction = THUMB_OP16 (inst.instruction);
11682 inst.instruction |= THUMB_PP_PC_LR;
11683 inst.instruction |= mask & 0xff;
11685 else if (unified_syntax)
11687 inst.instruction = THUMB_OP32 (inst.instruction);
11688 encode_thumb2_ldmstm (13, mask, TRUE);
11692 inst.error = _("invalid register list to push/pop instruction");
11702 Rd = inst.operands[0].reg;
11703 Rm = inst.operands[1].reg;
11705 reject_bad_reg (Rd);
11706 reject_bad_reg (Rm);
11708 inst.instruction |= Rd << 8;
11709 inst.instruction |= Rm << 16;
11710 inst.instruction |= Rm;
11718 Rd = inst.operands[0].reg;
11719 Rm = inst.operands[1].reg;
11721 reject_bad_reg (Rd);
11722 reject_bad_reg (Rm);
11724 if (Rd <= 7 && Rm <= 7
11725 && inst.size_req != 4)
11727 inst.instruction = THUMB_OP16 (inst.instruction);
11728 inst.instruction |= Rd;
11729 inst.instruction |= Rm << 3;
11731 else if (unified_syntax)
11733 inst.instruction = THUMB_OP32 (inst.instruction);
11734 inst.instruction |= Rd << 8;
11735 inst.instruction |= Rm << 16;
11736 inst.instruction |= Rm;
11739 inst.error = BAD_HIREG;
11747 Rd = inst.operands[0].reg;
11748 Rm = inst.operands[1].reg;
11750 reject_bad_reg (Rd);
11751 reject_bad_reg (Rm);
11753 inst.instruction |= Rd << 8;
11754 inst.instruction |= Rm;
11762 Rd = inst.operands[0].reg;
11763 Rs = (inst.operands[1].present
11764 ? inst.operands[1].reg /* Rd, Rs, foo */
11765 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11767 reject_bad_reg (Rd);
11768 reject_bad_reg (Rs);
11769 if (inst.operands[2].isreg)
11770 reject_bad_reg (inst.operands[2].reg);
11772 inst.instruction |= Rd << 8;
11773 inst.instruction |= Rs << 16;
11774 if (!inst.operands[2].isreg)
11776 bfd_boolean narrow;
11778 if ((inst.instruction & 0x00100000) != 0)
11779 narrow = !in_it_block ();
11781 narrow = in_it_block ();
11783 if (Rd > 7 || Rs > 7)
11786 if (inst.size_req == 4 || !unified_syntax)
11789 if (inst.reloc.exp.X_op != O_constant
11790 || inst.reloc.exp.X_add_number != 0)
11793 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11794 relaxation, but it doesn't seem worth the hassle. */
11797 inst.reloc.type = BFD_RELOC_UNUSED;
11798 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11799 inst.instruction |= Rs << 3;
11800 inst.instruction |= Rd;
11804 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11805 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11809 encode_thumb32_shifted_operand (2);
11815 if (warn_on_deprecated
11816 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11817 as_warn (_("setend use is deprecated for ARMv8"));
11819 set_it_insn_type (OUTSIDE_IT_INSN);
11820 if (inst.operands[0].imm)
11821 inst.instruction |= 0x8;
11827 if (!inst.operands[1].present)
11828 inst.operands[1].reg = inst.operands[0].reg;
11830 if (unified_syntax)
11832 bfd_boolean narrow;
11835 switch (inst.instruction)
11838 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11840 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11842 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11844 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11848 if (THUMB_SETS_FLAGS (inst.instruction))
11849 narrow = !in_it_block ();
11851 narrow = in_it_block ();
11852 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11854 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11856 if (inst.operands[2].isreg
11857 && (inst.operands[1].reg != inst.operands[0].reg
11858 || inst.operands[2].reg > 7))
11860 if (inst.size_req == 4)
11863 reject_bad_reg (inst.operands[0].reg);
11864 reject_bad_reg (inst.operands[1].reg);
11868 if (inst.operands[2].isreg)
11870 reject_bad_reg (inst.operands[2].reg);
11871 inst.instruction = THUMB_OP32 (inst.instruction);
11872 inst.instruction |= inst.operands[0].reg << 8;
11873 inst.instruction |= inst.operands[1].reg << 16;
11874 inst.instruction |= inst.operands[2].reg;
11876 /* PR 12854: Error on extraneous shifts. */
11877 constraint (inst.operands[2].shifted,
11878 _("extraneous shift as part of operand to shift insn"));
11882 inst.operands[1].shifted = 1;
11883 inst.operands[1].shift_kind = shift_kind;
11884 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11885 ? T_MNEM_movs : T_MNEM_mov);
11886 inst.instruction |= inst.operands[0].reg << 8;
11887 encode_thumb32_shifted_operand (1);
11888 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11889 inst.reloc.type = BFD_RELOC_UNUSED;
11894 if (inst.operands[2].isreg)
11896 switch (shift_kind)
11898 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11899 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11900 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11901 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11905 inst.instruction |= inst.operands[0].reg;
11906 inst.instruction |= inst.operands[2].reg << 3;
11908 /* PR 12854: Error on extraneous shifts. */
11909 constraint (inst.operands[2].shifted,
11910 _("extraneous shift as part of operand to shift insn"));
11914 switch (shift_kind)
11916 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11917 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11918 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11921 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11922 inst.instruction |= inst.operands[0].reg;
11923 inst.instruction |= inst.operands[1].reg << 3;
11929 constraint (inst.operands[0].reg > 7
11930 || inst.operands[1].reg > 7, BAD_HIREG);
11931 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11933 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11935 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11936 constraint (inst.operands[0].reg != inst.operands[1].reg,
11937 _("source1 and dest must be same register"));
11939 switch (inst.instruction)
11941 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11942 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11943 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11944 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11948 inst.instruction |= inst.operands[0].reg;
11949 inst.instruction |= inst.operands[2].reg << 3;
11951 /* PR 12854: Error on extraneous shifts. */
11952 constraint (inst.operands[2].shifted,
11953 _("extraneous shift as part of operand to shift insn"));
11957 switch (inst.instruction)
11959 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11960 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11961 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11962 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11965 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11966 inst.instruction |= inst.operands[0].reg;
11967 inst.instruction |= inst.operands[1].reg << 3;
11975 unsigned Rd, Rn, Rm;
11977 Rd = inst.operands[0].reg;
11978 Rn = inst.operands[1].reg;
11979 Rm = inst.operands[2].reg;
11981 reject_bad_reg (Rd);
11982 reject_bad_reg (Rn);
11983 reject_bad_reg (Rm);
11985 inst.instruction |= Rd << 8;
11986 inst.instruction |= Rn << 16;
11987 inst.instruction |= Rm;
11993 unsigned Rd, Rn, Rm;
11995 Rd = inst.operands[0].reg;
11996 Rm = inst.operands[1].reg;
11997 Rn = inst.operands[2].reg;
11999 reject_bad_reg (Rd);
12000 reject_bad_reg (Rn);
12001 reject_bad_reg (Rm);
12003 inst.instruction |= Rd << 8;
12004 inst.instruction |= Rn << 16;
12005 inst.instruction |= Rm;
12011 unsigned int value = inst.reloc.exp.X_add_number;
12012 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12013 _("SMC is not permitted on this architecture"));
12014 constraint (inst.reloc.exp.X_op != O_constant,
12015 _("expression too complex"));
12016 inst.reloc.type = BFD_RELOC_UNUSED;
12017 inst.instruction |= (value & 0xf000) >> 12;
12018 inst.instruction |= (value & 0x0ff0);
12019 inst.instruction |= (value & 0x000f) << 16;
12020 /* PR gas/15623: SMC instructions must be last in an IT block. */
12021 set_it_insn_type_last ();
12027 unsigned int value = inst.reloc.exp.X_add_number;
12029 inst.reloc.type = BFD_RELOC_UNUSED;
12030 inst.instruction |= (value & 0x0fff);
12031 inst.instruction |= (value & 0xf000) << 4;
12035 do_t_ssat_usat (int bias)
12039 Rd = inst.operands[0].reg;
12040 Rn = inst.operands[2].reg;
12042 reject_bad_reg (Rd);
12043 reject_bad_reg (Rn);
12045 inst.instruction |= Rd << 8;
12046 inst.instruction |= inst.operands[1].imm - bias;
12047 inst.instruction |= Rn << 16;
12049 if (inst.operands[3].present)
12051 offsetT shift_amount = inst.reloc.exp.X_add_number;
12053 inst.reloc.type = BFD_RELOC_UNUSED;
12055 constraint (inst.reloc.exp.X_op != O_constant,
12056 _("expression too complex"));
12058 if (shift_amount != 0)
12060 constraint (shift_amount > 31,
12061 _("shift expression is too large"));
12063 if (inst.operands[3].shift_kind == SHIFT_ASR)
12064 inst.instruction |= 0x00200000; /* sh bit. */
12066 inst.instruction |= (shift_amount & 0x1c) << 10;
12067 inst.instruction |= (shift_amount & 0x03) << 6;
12075 do_t_ssat_usat (1);
12083 Rd = inst.operands[0].reg;
12084 Rn = inst.operands[2].reg;
12086 reject_bad_reg (Rd);
12087 reject_bad_reg (Rn);
12089 inst.instruction |= Rd << 8;
12090 inst.instruction |= inst.operands[1].imm - 1;
12091 inst.instruction |= Rn << 16;
12097 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12098 || inst.operands[2].postind || inst.operands[2].writeback
12099 || inst.operands[2].immisreg || inst.operands[2].shifted
12100 || inst.operands[2].negative,
12103 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12105 inst.instruction |= inst.operands[0].reg << 8;
12106 inst.instruction |= inst.operands[1].reg << 12;
12107 inst.instruction |= inst.operands[2].reg << 16;
12108 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12114 if (!inst.operands[2].present)
12115 inst.operands[2].reg = inst.operands[1].reg + 1;
12117 constraint (inst.operands[0].reg == inst.operands[1].reg
12118 || inst.operands[0].reg == inst.operands[2].reg
12119 || inst.operands[0].reg == inst.operands[3].reg,
12122 inst.instruction |= inst.operands[0].reg;
12123 inst.instruction |= inst.operands[1].reg << 12;
12124 inst.instruction |= inst.operands[2].reg << 8;
12125 inst.instruction |= inst.operands[3].reg << 16;
12131 unsigned Rd, Rn, Rm;
12133 Rd = inst.operands[0].reg;
12134 Rn = inst.operands[1].reg;
12135 Rm = inst.operands[2].reg;
12137 reject_bad_reg (Rd);
12138 reject_bad_reg (Rn);
12139 reject_bad_reg (Rm);
12141 inst.instruction |= Rd << 8;
12142 inst.instruction |= Rn << 16;
12143 inst.instruction |= Rm;
12144 inst.instruction |= inst.operands[3].imm << 4;
12152 Rd = inst.operands[0].reg;
12153 Rm = inst.operands[1].reg;
12155 reject_bad_reg (Rd);
12156 reject_bad_reg (Rm);
12158 if (inst.instruction <= 0xffff
12159 && inst.size_req != 4
12160 && Rd <= 7 && Rm <= 7
12161 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12163 inst.instruction = THUMB_OP16 (inst.instruction);
12164 inst.instruction |= Rd;
12165 inst.instruction |= Rm << 3;
12167 else if (unified_syntax)
12169 if (inst.instruction <= 0xffff)
12170 inst.instruction = THUMB_OP32 (inst.instruction);
12171 inst.instruction |= Rd << 8;
12172 inst.instruction |= Rm;
12173 inst.instruction |= inst.operands[2].imm << 4;
12177 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12178 _("Thumb encoding does not support rotation"));
12179 constraint (1, BAD_HIREG);
12186 /* We have to do the following check manually as ARM_EXT_OS only applies
12188 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12190 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12191 /* This only applies to the v6m howver, not later architectures. */
12192 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12193 as_bad (_("SVC is not permitted on this architecture"));
12194 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12197 inst.reloc.type = BFD_RELOC_ARM_SWI;
12206 half = (inst.instruction & 0x10) != 0;
12207 set_it_insn_type_last ();
12208 constraint (inst.operands[0].immisreg,
12209 _("instruction requires register index"));
12211 Rn = inst.operands[0].reg;
12212 Rm = inst.operands[0].imm;
12214 constraint (Rn == REG_SP, BAD_SP);
12215 reject_bad_reg (Rm);
12217 constraint (!half && inst.operands[0].shifted,
12218 _("instruction does not allow shifted index"));
12219 inst.instruction |= (Rn << 16) | Rm;
12225 if (!inst.operands[0].present)
12226 inst.operands[0].imm = 0;
12228 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
12230 constraint (inst.size_req == 2,
12231 _("immediate value out of range"));
12232 inst.instruction = THUMB_OP32 (inst.instruction);
12233 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
12234 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
12238 inst.instruction = THUMB_OP16 (inst.instruction);
12239 inst.instruction |= inst.operands[0].imm;
12242 set_it_insn_type (NEUTRAL_IT_INSN);
12249 do_t_ssat_usat (0);
12257 Rd = inst.operands[0].reg;
12258 Rn = inst.operands[2].reg;
12260 reject_bad_reg (Rd);
12261 reject_bad_reg (Rn);
12263 inst.instruction |= Rd << 8;
12264 inst.instruction |= inst.operands[1].imm;
12265 inst.instruction |= Rn << 16;
12268 /* Neon instruction encoder helpers. */
12270 /* Encodings for the different types for various Neon opcodes. */
12272 /* An "invalid" code for the following tables. */
12275 struct neon_tab_entry
12278 unsigned float_or_poly;
12279 unsigned scalar_or_imm;
12282 /* Map overloaded Neon opcodes to their respective encodings. */
12283 #define NEON_ENC_TAB \
12284 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12285 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12286 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12287 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12288 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12289 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12290 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12291 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12292 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12293 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12294 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12295 /* Register variants of the following two instructions are encoded as
12296 vcge / vcgt with the operands reversed. */ \
12297 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12298 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12299 X(vfma, N_INV, 0x0000c10, N_INV), \
12300 X(vfms, N_INV, 0x0200c10, N_INV), \
12301 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12302 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12303 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12304 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12305 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12306 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12307 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12308 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12309 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12310 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12311 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12312 X(vshl, 0x0000400, N_INV, 0x0800510), \
12313 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12314 X(vand, 0x0000110, N_INV, 0x0800030), \
12315 X(vbic, 0x0100110, N_INV, 0x0800030), \
12316 X(veor, 0x1000110, N_INV, N_INV), \
12317 X(vorn, 0x0300110, N_INV, 0x0800010), \
12318 X(vorr, 0x0200110, N_INV, 0x0800010), \
12319 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12320 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12321 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12322 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12323 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12324 X(vst1, 0x0000000, 0x0800000, N_INV), \
12325 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12326 X(vst2, 0x0000100, 0x0800100, N_INV), \
12327 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12328 X(vst3, 0x0000200, 0x0800200, N_INV), \
12329 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12330 X(vst4, 0x0000300, 0x0800300, N_INV), \
12331 X(vmovn, 0x1b20200, N_INV, N_INV), \
12332 X(vtrn, 0x1b20080, N_INV, N_INV), \
12333 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12334 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12335 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12336 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12337 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12338 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12339 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12340 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12341 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12342 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12343 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12344 X(vseleq, 0xe000a00, N_INV, N_INV), \
12345 X(vselvs, 0xe100a00, N_INV, N_INV), \
12346 X(vselge, 0xe200a00, N_INV, N_INV), \
12347 X(vselgt, 0xe300a00, N_INV, N_INV), \
12348 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12349 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12350 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12351 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12352 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12353 X(aes, 0x3b00300, N_INV, N_INV), \
12354 X(sha3op, 0x2000c00, N_INV, N_INV), \
12355 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12356 X(sha2op, 0x3ba0380, N_INV, N_INV)
12360 #define X(OPC,I,F,S) N_MNEM_##OPC
12365 static const struct neon_tab_entry neon_enc_tab[] =
12367 #define X(OPC,I,F,S) { (I), (F), (S) }
12372 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12373 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12374 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12375 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12376 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12377 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12378 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12379 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12380 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12381 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12382 #define NEON_ENC_SINGLE_(X) \
12383 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12384 #define NEON_ENC_DOUBLE_(X) \
12385 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12386 #define NEON_ENC_FPV8_(X) \
12387 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12389 #define NEON_ENCODE(type, inst) \
12392 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12393 inst.is_neon = 1; \
12397 #define check_neon_suffixes \
12400 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12402 as_bad (_("invalid neon suffix for non neon instruction")); \
12408 /* Define shapes for instruction operands. The following mnemonic characters
12409 are used in this table:
12411 F - VFP S<n> register
12412 D - Neon D<n> register
12413 Q - Neon Q<n> register
12417 L - D<n> register list
12419 This table is used to generate various data:
12420 - enumerations of the form NS_DDR to be used as arguments to
12422 - a table classifying shapes into single, double, quad, mixed.
12423 - a table used to drive neon_select_shape. */
12425 #define NEON_SHAPE_DEF \
12426 X(3, (D, D, D), DOUBLE), \
12427 X(3, (Q, Q, Q), QUAD), \
12428 X(3, (D, D, I), DOUBLE), \
12429 X(3, (Q, Q, I), QUAD), \
12430 X(3, (D, D, S), DOUBLE), \
12431 X(3, (Q, Q, S), QUAD), \
12432 X(2, (D, D), DOUBLE), \
12433 X(2, (Q, Q), QUAD), \
12434 X(2, (D, S), DOUBLE), \
12435 X(2, (Q, S), QUAD), \
12436 X(2, (D, R), DOUBLE), \
12437 X(2, (Q, R), QUAD), \
12438 X(2, (D, I), DOUBLE), \
12439 X(2, (Q, I), QUAD), \
12440 X(3, (D, L, D), DOUBLE), \
12441 X(2, (D, Q), MIXED), \
12442 X(2, (Q, D), MIXED), \
12443 X(3, (D, Q, I), MIXED), \
12444 X(3, (Q, D, I), MIXED), \
12445 X(3, (Q, D, D), MIXED), \
12446 X(3, (D, Q, Q), MIXED), \
12447 X(3, (Q, Q, D), MIXED), \
12448 X(3, (Q, D, S), MIXED), \
12449 X(3, (D, Q, S), MIXED), \
12450 X(4, (D, D, D, I), DOUBLE), \
12451 X(4, (Q, Q, Q, I), QUAD), \
12452 X(2, (F, F), SINGLE), \
12453 X(3, (F, F, F), SINGLE), \
12454 X(2, (F, I), SINGLE), \
12455 X(2, (F, D), MIXED), \
12456 X(2, (D, F), MIXED), \
12457 X(3, (F, F, I), MIXED), \
12458 X(4, (R, R, F, F), SINGLE), \
12459 X(4, (F, F, R, R), SINGLE), \
12460 X(3, (D, R, R), DOUBLE), \
12461 X(3, (R, R, D), DOUBLE), \
12462 X(2, (S, R), SINGLE), \
12463 X(2, (R, S), SINGLE), \
12464 X(2, (F, R), SINGLE), \
12465 X(2, (R, F), SINGLE)
12467 #define S2(A,B) NS_##A##B
12468 #define S3(A,B,C) NS_##A##B##C
12469 #define S4(A,B,C,D) NS_##A##B##C##D
12471 #define X(N, L, C) S##N L
12484 enum neon_shape_class
12492 #define X(N, L, C) SC_##C
12494 static enum neon_shape_class neon_shape_class[] =
12512 /* Register widths of above. */
12513 static unsigned neon_shape_el_size[] =
12524 struct neon_shape_info
12527 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12530 #define S2(A,B) { SE_##A, SE_##B }
12531 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12532 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12534 #define X(N, L, C) { N, S##N L }
12536 static struct neon_shape_info neon_shape_tab[] =
12546 /* Bit masks used in type checking given instructions.
12547 'N_EQK' means the type must be the same as (or based on in some way) the key
12548 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12549 set, various other bits can be set as well in order to modify the meaning of
12550 the type constraint. */
12552 enum neon_type_mask
12576 N_KEY = 0x1000000, /* Key element (main type specifier). */
12577 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12578 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12579 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12580 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12581 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12582 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12583 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12584 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12585 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12586 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12588 N_MAX_NONSPECIAL = N_P64
12591 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12593 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12594 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12595 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12596 #define N_SUF_32 (N_SU_32 | N_F32)
12597 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12598 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12600 /* Pass this as the first type argument to neon_check_type to ignore types
12602 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12604 /* Select a "shape" for the current instruction (describing register types or
12605 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12606 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12607 function of operand parsing, so this function doesn't need to be called.
12608 Shapes should be listed in order of decreasing length. */
12610 static enum neon_shape
12611 neon_select_shape (enum neon_shape shape, ...)
12614 enum neon_shape first_shape = shape;
12616 /* Fix missing optional operands. FIXME: we don't know at this point how
12617 many arguments we should have, so this makes the assumption that we have
12618 > 1. This is true of all current Neon opcodes, I think, but may not be
12619 true in the future. */
12620 if (!inst.operands[1].present)
12621 inst.operands[1] = inst.operands[0];
12623 va_start (ap, shape);
12625 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12630 for (j = 0; j < neon_shape_tab[shape].els; j++)
12632 if (!inst.operands[j].present)
12638 switch (neon_shape_tab[shape].el[j])
12641 if (!(inst.operands[j].isreg
12642 && inst.operands[j].isvec
12643 && inst.operands[j].issingle
12644 && !inst.operands[j].isquad))
12649 if (!(inst.operands[j].isreg
12650 && inst.operands[j].isvec
12651 && !inst.operands[j].isquad
12652 && !inst.operands[j].issingle))
12657 if (!(inst.operands[j].isreg
12658 && !inst.operands[j].isvec))
12663 if (!(inst.operands[j].isreg
12664 && inst.operands[j].isvec
12665 && inst.operands[j].isquad
12666 && !inst.operands[j].issingle))
12671 if (!(!inst.operands[j].isreg
12672 && !inst.operands[j].isscalar))
12677 if (!(!inst.operands[j].isreg
12678 && inst.operands[j].isscalar))
12688 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12689 /* We've matched all the entries in the shape table, and we don't
12690 have any left over operands which have not been matched. */
12696 if (shape == NS_NULL && first_shape != NS_NULL)
12697 first_error (_("invalid instruction shape"));
12702 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12703 means the Q bit should be set). */
12706 neon_quad (enum neon_shape shape)
12708 return neon_shape_class[shape] == SC_QUAD;
12712 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12715 /* Allow modification to be made to types which are constrained to be
12716 based on the key element, based on bits set alongside N_EQK. */
12717 if ((typebits & N_EQK) != 0)
12719 if ((typebits & N_HLF) != 0)
12721 else if ((typebits & N_DBL) != 0)
12723 if ((typebits & N_SGN) != 0)
12724 *g_type = NT_signed;
12725 else if ((typebits & N_UNS) != 0)
12726 *g_type = NT_unsigned;
12727 else if ((typebits & N_INT) != 0)
12728 *g_type = NT_integer;
12729 else if ((typebits & N_FLT) != 0)
12730 *g_type = NT_float;
12731 else if ((typebits & N_SIZ) != 0)
12732 *g_type = NT_untyped;
12736 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12737 operand type, i.e. the single type specified in a Neon instruction when it
12738 is the only one given. */
12740 static struct neon_type_el
12741 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12743 struct neon_type_el dest = *key;
12745 gas_assert ((thisarg & N_EQK) != 0);
12747 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12752 /* Convert Neon type and size into compact bitmask representation. */
12754 static enum neon_type_mask
12755 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12762 case 8: return N_8;
12763 case 16: return N_16;
12764 case 32: return N_32;
12765 case 64: return N_64;
12773 case 8: return N_I8;
12774 case 16: return N_I16;
12775 case 32: return N_I32;
12776 case 64: return N_I64;
12784 case 16: return N_F16;
12785 case 32: return N_F32;
12786 case 64: return N_F64;
12794 case 8: return N_P8;
12795 case 16: return N_P16;
12796 case 64: return N_P64;
12804 case 8: return N_S8;
12805 case 16: return N_S16;
12806 case 32: return N_S32;
12807 case 64: return N_S64;
12815 case 8: return N_U8;
12816 case 16: return N_U16;
12817 case 32: return N_U32;
12818 case 64: return N_U64;
12829 /* Convert compact Neon bitmask type representation to a type and size. Only
12830 handles the case where a single bit is set in the mask. */
12833 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12834 enum neon_type_mask mask)
12836 if ((mask & N_EQK) != 0)
12839 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12841 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12843 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12845 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12850 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12852 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12853 *type = NT_unsigned;
12854 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12855 *type = NT_integer;
12856 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12857 *type = NT_untyped;
12858 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12860 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12868 /* Modify a bitmask of allowed types. This is only needed for type
12872 modify_types_allowed (unsigned allowed, unsigned mods)
12875 enum neon_el_type type;
12881 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12883 if (el_type_of_type_chk (&type, &size,
12884 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12886 neon_modify_type_size (mods, &type, &size);
12887 destmask |= type_chk_of_el_type (type, size);
12894 /* Check type and return type classification.
12895 The manual states (paraphrase): If one datatype is given, it indicates the
12897 - the second operand, if there is one
12898 - the operand, if there is no second operand
12899 - the result, if there are no operands.
12900 This isn't quite good enough though, so we use a concept of a "key" datatype
12901 which is set on a per-instruction basis, which is the one which matters when
12902 only one data type is written.
12903 Note: this function has side-effects (e.g. filling in missing operands). All
12904 Neon instructions should call it before performing bit encoding. */
12906 static struct neon_type_el
12907 neon_check_type (unsigned els, enum neon_shape ns, ...)
12910 unsigned i, pass, key_el = 0;
12911 unsigned types[NEON_MAX_TYPE_ELS];
12912 enum neon_el_type k_type = NT_invtype;
12913 unsigned k_size = -1u;
12914 struct neon_type_el badtype = {NT_invtype, -1};
12915 unsigned key_allowed = 0;
12917 /* Optional registers in Neon instructions are always (not) in operand 1.
12918 Fill in the missing operand here, if it was omitted. */
12919 if (els > 1 && !inst.operands[1].present)
12920 inst.operands[1] = inst.operands[0];
12922 /* Suck up all the varargs. */
12924 for (i = 0; i < els; i++)
12926 unsigned thisarg = va_arg (ap, unsigned);
12927 if (thisarg == N_IGNORE_TYPE)
12932 types[i] = thisarg;
12933 if ((thisarg & N_KEY) != 0)
12938 if (inst.vectype.elems > 0)
12939 for (i = 0; i < els; i++)
12940 if (inst.operands[i].vectype.type != NT_invtype)
12942 first_error (_("types specified in both the mnemonic and operands"));
12946 /* Duplicate inst.vectype elements here as necessary.
12947 FIXME: No idea if this is exactly the same as the ARM assembler,
12948 particularly when an insn takes one register and one non-register
12950 if (inst.vectype.elems == 1 && els > 1)
12953 inst.vectype.elems = els;
12954 inst.vectype.el[key_el] = inst.vectype.el[0];
12955 for (j = 0; j < els; j++)
12957 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12960 else if (inst.vectype.elems == 0 && els > 0)
12963 /* No types were given after the mnemonic, so look for types specified
12964 after each operand. We allow some flexibility here; as long as the
12965 "key" operand has a type, we can infer the others. */
12966 for (j = 0; j < els; j++)
12967 if (inst.operands[j].vectype.type != NT_invtype)
12968 inst.vectype.el[j] = inst.operands[j].vectype;
12970 if (inst.operands[key_el].vectype.type != NT_invtype)
12972 for (j = 0; j < els; j++)
12973 if (inst.operands[j].vectype.type == NT_invtype)
12974 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12979 first_error (_("operand types can't be inferred"));
12983 else if (inst.vectype.elems != els)
12985 first_error (_("type specifier has the wrong number of parts"));
12989 for (pass = 0; pass < 2; pass++)
12991 for (i = 0; i < els; i++)
12993 unsigned thisarg = types[i];
12994 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12995 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12996 enum neon_el_type g_type = inst.vectype.el[i].type;
12997 unsigned g_size = inst.vectype.el[i].size;
12999 /* Decay more-specific signed & unsigned types to sign-insensitive
13000 integer types if sign-specific variants are unavailable. */
13001 if ((g_type == NT_signed || g_type == NT_unsigned)
13002 && (types_allowed & N_SU_ALL) == 0)
13003 g_type = NT_integer;
13005 /* If only untyped args are allowed, decay any more specific types to
13006 them. Some instructions only care about signs for some element
13007 sizes, so handle that properly. */
13008 if (((types_allowed & N_UNT) == 0)
13009 && ((g_size == 8 && (types_allowed & N_8) != 0)
13010 || (g_size == 16 && (types_allowed & N_16) != 0)
13011 || (g_size == 32 && (types_allowed & N_32) != 0)
13012 || (g_size == 64 && (types_allowed & N_64) != 0)))
13013 g_type = NT_untyped;
13017 if ((thisarg & N_KEY) != 0)
13021 key_allowed = thisarg & ~N_KEY;
13026 if ((thisarg & N_VFP) != 0)
13028 enum neon_shape_el regshape;
13029 unsigned regwidth, match;
13031 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13034 first_error (_("invalid instruction shape"));
13037 regshape = neon_shape_tab[ns].el[i];
13038 regwidth = neon_shape_el_size[regshape];
13040 /* In VFP mode, operands must match register widths. If we
13041 have a key operand, use its width, else use the width of
13042 the current operand. */
13048 if (regwidth != match)
13050 first_error (_("operand size must match register width"));
13055 if ((thisarg & N_EQK) == 0)
13057 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13059 if ((given_type & types_allowed) == 0)
13061 first_error (_("bad type in Neon instruction"));
13067 enum neon_el_type mod_k_type = k_type;
13068 unsigned mod_k_size = k_size;
13069 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13070 if (g_type != mod_k_type || g_size != mod_k_size)
13072 first_error (_("inconsistent types in Neon instruction"));
13080 return inst.vectype.el[key_el];
13083 /* Neon-style VFP instruction forwarding. */
13085 /* Thumb VFP instructions have 0xE in the condition field. */
13088 do_vfp_cond_or_thumb (void)
13093 inst.instruction |= 0xe0000000;
13095 inst.instruction |= inst.cond << 28;
13098 /* Look up and encode a simple mnemonic, for use as a helper function for the
13099 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13100 etc. It is assumed that operand parsing has already been done, and that the
13101 operands are in the form expected by the given opcode (this isn't necessarily
13102 the same as the form in which they were parsed, hence some massaging must
13103 take place before this function is called).
13104 Checks current arch version against that in the looked-up opcode. */
13107 do_vfp_nsyn_opcode (const char *opname)
13109 const struct asm_opcode *opcode;
13111 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13116 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13117 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13124 inst.instruction = opcode->tvalue;
13125 opcode->tencode ();
13129 inst.instruction = (inst.cond << 28) | opcode->avalue;
13130 opcode->aencode ();
13135 do_vfp_nsyn_add_sub (enum neon_shape rs)
13137 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13142 do_vfp_nsyn_opcode ("fadds");
13144 do_vfp_nsyn_opcode ("fsubs");
13149 do_vfp_nsyn_opcode ("faddd");
13151 do_vfp_nsyn_opcode ("fsubd");
13155 /* Check operand types to see if this is a VFP instruction, and if so call
13159 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13161 enum neon_shape rs;
13162 struct neon_type_el et;
13167 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13168 et = neon_check_type (2, rs,
13169 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13173 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13174 et = neon_check_type (3, rs,
13175 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13182 if (et.type != NT_invtype)
13193 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13195 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13200 do_vfp_nsyn_opcode ("fmacs");
13202 do_vfp_nsyn_opcode ("fnmacs");
13207 do_vfp_nsyn_opcode ("fmacd");
13209 do_vfp_nsyn_opcode ("fnmacd");
13214 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13216 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13221 do_vfp_nsyn_opcode ("ffmas");
13223 do_vfp_nsyn_opcode ("ffnmas");
13228 do_vfp_nsyn_opcode ("ffmad");
13230 do_vfp_nsyn_opcode ("ffnmad");
13235 do_vfp_nsyn_mul (enum neon_shape rs)
13238 do_vfp_nsyn_opcode ("fmuls");
13240 do_vfp_nsyn_opcode ("fmuld");
13244 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13246 int is_neg = (inst.instruction & 0x80) != 0;
13247 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13252 do_vfp_nsyn_opcode ("fnegs");
13254 do_vfp_nsyn_opcode ("fabss");
13259 do_vfp_nsyn_opcode ("fnegd");
13261 do_vfp_nsyn_opcode ("fabsd");
13265 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13266 insns belong to Neon, and are handled elsewhere. */
13269 do_vfp_nsyn_ldm_stm (int is_dbmode)
13271 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13275 do_vfp_nsyn_opcode ("fldmdbs");
13277 do_vfp_nsyn_opcode ("fldmias");
13282 do_vfp_nsyn_opcode ("fstmdbs");
13284 do_vfp_nsyn_opcode ("fstmias");
13289 do_vfp_nsyn_sqrt (void)
13291 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13292 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13295 do_vfp_nsyn_opcode ("fsqrts");
13297 do_vfp_nsyn_opcode ("fsqrtd");
13301 do_vfp_nsyn_div (void)
13303 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13304 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13305 N_F32 | N_F64 | N_KEY | N_VFP);
13308 do_vfp_nsyn_opcode ("fdivs");
13310 do_vfp_nsyn_opcode ("fdivd");
13314 do_vfp_nsyn_nmul (void)
13316 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13317 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13318 N_F32 | N_F64 | N_KEY | N_VFP);
13322 NEON_ENCODE (SINGLE, inst);
13323 do_vfp_sp_dyadic ();
13327 NEON_ENCODE (DOUBLE, inst);
13328 do_vfp_dp_rd_rn_rm ();
13330 do_vfp_cond_or_thumb ();
13334 do_vfp_nsyn_cmp (void)
13336 if (inst.operands[1].isreg)
13338 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13339 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13343 NEON_ENCODE (SINGLE, inst);
13344 do_vfp_sp_monadic ();
13348 NEON_ENCODE (DOUBLE, inst);
13349 do_vfp_dp_rd_rm ();
13354 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13355 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13357 switch (inst.instruction & 0x0fffffff)
13360 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13363 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13371 NEON_ENCODE (SINGLE, inst);
13372 do_vfp_sp_compare_z ();
13376 NEON_ENCODE (DOUBLE, inst);
13380 do_vfp_cond_or_thumb ();
13384 nsyn_insert_sp (void)
13386 inst.operands[1] = inst.operands[0];
13387 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13388 inst.operands[0].reg = REG_SP;
13389 inst.operands[0].isreg = 1;
13390 inst.operands[0].writeback = 1;
13391 inst.operands[0].present = 1;
13395 do_vfp_nsyn_push (void)
13398 if (inst.operands[1].issingle)
13399 do_vfp_nsyn_opcode ("fstmdbs");
13401 do_vfp_nsyn_opcode ("fstmdbd");
13405 do_vfp_nsyn_pop (void)
13408 if (inst.operands[1].issingle)
13409 do_vfp_nsyn_opcode ("fldmias");
13411 do_vfp_nsyn_opcode ("fldmiad");
13414 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13415 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13418 neon_dp_fixup (struct arm_it* insn)
13420 unsigned int i = insn->instruction;
13425 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13436 insn->instruction = i;
13439 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13443 neon_logbits (unsigned x)
13445 return ffs (x) - 4;
13448 #define LOW4(R) ((R) & 0xf)
13449 #define HI1(R) (((R) >> 4) & 1)
13451 /* Encode insns with bit pattern:
13453 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13454 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13456 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13457 different meaning for some instruction. */
13460 neon_three_same (int isquad, int ubit, int size)
13462 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13463 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13464 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13465 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13466 inst.instruction |= LOW4 (inst.operands[2].reg);
13467 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13468 inst.instruction |= (isquad != 0) << 6;
13469 inst.instruction |= (ubit != 0) << 24;
13471 inst.instruction |= neon_logbits (size) << 20;
13473 neon_dp_fixup (&inst);
13476 /* Encode instructions of the form:
13478 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13479 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13481 Don't write size if SIZE == -1. */
13484 neon_two_same (int qbit, int ubit, int size)
13486 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13487 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13488 inst.instruction |= LOW4 (inst.operands[1].reg);
13489 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13490 inst.instruction |= (qbit != 0) << 6;
13491 inst.instruction |= (ubit != 0) << 24;
13494 inst.instruction |= neon_logbits (size) << 18;
13496 neon_dp_fixup (&inst);
13499 /* Neon instruction encoders, in approximate order of appearance. */
13502 do_neon_dyadic_i_su (void)
13504 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13505 struct neon_type_el et = neon_check_type (3, rs,
13506 N_EQK, N_EQK, N_SU_32 | N_KEY);
13507 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13511 do_neon_dyadic_i64_su (void)
13513 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13514 struct neon_type_el et = neon_check_type (3, rs,
13515 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13516 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13520 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13523 unsigned size = et.size >> 3;
13524 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13525 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13526 inst.instruction |= LOW4 (inst.operands[1].reg);
13527 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13528 inst.instruction |= (isquad != 0) << 6;
13529 inst.instruction |= immbits << 16;
13530 inst.instruction |= (size >> 3) << 7;
13531 inst.instruction |= (size & 0x7) << 19;
13533 inst.instruction |= (uval != 0) << 24;
13535 neon_dp_fixup (&inst);
13539 do_neon_shl_imm (void)
13541 if (!inst.operands[2].isreg)
13543 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13544 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13545 NEON_ENCODE (IMMED, inst);
13546 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13550 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13551 struct neon_type_el et = neon_check_type (3, rs,
13552 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13555 /* VSHL/VQSHL 3-register variants have syntax such as:
13557 whereas other 3-register operations encoded by neon_three_same have
13560 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13562 tmp = inst.operands[2].reg;
13563 inst.operands[2].reg = inst.operands[1].reg;
13564 inst.operands[1].reg = tmp;
13565 NEON_ENCODE (INTEGER, inst);
13566 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13571 do_neon_qshl_imm (void)
13573 if (!inst.operands[2].isreg)
13575 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13576 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13578 NEON_ENCODE (IMMED, inst);
13579 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13580 inst.operands[2].imm);
13584 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13585 struct neon_type_el et = neon_check_type (3, rs,
13586 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13589 /* See note in do_neon_shl_imm. */
13590 tmp = inst.operands[2].reg;
13591 inst.operands[2].reg = inst.operands[1].reg;
13592 inst.operands[1].reg = tmp;
13593 NEON_ENCODE (INTEGER, inst);
13594 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13599 do_neon_rshl (void)
13601 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13602 struct neon_type_el et = neon_check_type (3, rs,
13603 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13606 tmp = inst.operands[2].reg;
13607 inst.operands[2].reg = inst.operands[1].reg;
13608 inst.operands[1].reg = tmp;
13609 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13613 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13615 /* Handle .I8 pseudo-instructions. */
13618 /* Unfortunately, this will make everything apart from zero out-of-range.
13619 FIXME is this the intended semantics? There doesn't seem much point in
13620 accepting .I8 if so. */
13621 immediate |= immediate << 8;
13627 if (immediate == (immediate & 0x000000ff))
13629 *immbits = immediate;
13632 else if (immediate == (immediate & 0x0000ff00))
13634 *immbits = immediate >> 8;
13637 else if (immediate == (immediate & 0x00ff0000))
13639 *immbits = immediate >> 16;
13642 else if (immediate == (immediate & 0xff000000))
13644 *immbits = immediate >> 24;
13647 if ((immediate & 0xffff) != (immediate >> 16))
13648 goto bad_immediate;
13649 immediate &= 0xffff;
13652 if (immediate == (immediate & 0x000000ff))
13654 *immbits = immediate;
13657 else if (immediate == (immediate & 0x0000ff00))
13659 *immbits = immediate >> 8;
13664 first_error (_("immediate value out of range"));
13668 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13672 neon_bits_same_in_bytes (unsigned imm)
13674 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13675 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13676 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13677 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13680 /* For immediate of above form, return 0bABCD. */
13683 neon_squash_bits (unsigned imm)
13685 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13686 | ((imm & 0x01000000) >> 21);
13689 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13692 neon_qfloat_bits (unsigned imm)
13694 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13697 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13698 the instruction. *OP is passed as the initial value of the op field, and
13699 may be set to a different value depending on the constant (i.e.
13700 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13701 MVN). If the immediate looks like a repeated pattern then also
13702 try smaller element sizes. */
13705 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13706 unsigned *immbits, int *op, int size,
13707 enum neon_el_type type)
13709 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13711 if (type == NT_float && !float_p)
13714 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13716 if (size != 32 || *op == 1)
13718 *immbits = neon_qfloat_bits (immlo);
13724 if (neon_bits_same_in_bytes (immhi)
13725 && neon_bits_same_in_bytes (immlo))
13729 *immbits = (neon_squash_bits (immhi) << 4)
13730 | neon_squash_bits (immlo);
13735 if (immhi != immlo)
13741 if (immlo == (immlo & 0x000000ff))
13746 else if (immlo == (immlo & 0x0000ff00))
13748 *immbits = immlo >> 8;
13751 else if (immlo == (immlo & 0x00ff0000))
13753 *immbits = immlo >> 16;
13756 else if (immlo == (immlo & 0xff000000))
13758 *immbits = immlo >> 24;
13761 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13763 *immbits = (immlo >> 8) & 0xff;
13766 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13768 *immbits = (immlo >> 16) & 0xff;
13772 if ((immlo & 0xffff) != (immlo >> 16))
13779 if (immlo == (immlo & 0x000000ff))
13784 else if (immlo == (immlo & 0x0000ff00))
13786 *immbits = immlo >> 8;
13790 if ((immlo & 0xff) != (immlo >> 8))
13795 if (immlo == (immlo & 0x000000ff))
13797 /* Don't allow MVN with 8-bit immediate. */
13807 /* Write immediate bits [7:0] to the following locations:
13809 |28/24|23 19|18 16|15 4|3 0|
13810 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13812 This function is used by VMOV/VMVN/VORR/VBIC. */
13815 neon_write_immbits (unsigned immbits)
13817 inst.instruction |= immbits & 0xf;
13818 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13819 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13822 /* Invert low-order SIZE bits of XHI:XLO. */
13825 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13827 unsigned immlo = xlo ? *xlo : 0;
13828 unsigned immhi = xhi ? *xhi : 0;
13833 immlo = (~immlo) & 0xff;
13837 immlo = (~immlo) & 0xffff;
13841 immhi = (~immhi) & 0xffffffff;
13842 /* fall through. */
13845 immlo = (~immlo) & 0xffffffff;
13860 do_neon_logic (void)
13862 if (inst.operands[2].present && inst.operands[2].isreg)
13864 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13865 neon_check_type (3, rs, N_IGNORE_TYPE);
13866 /* U bit and size field were set as part of the bitmask. */
13867 NEON_ENCODE (INTEGER, inst);
13868 neon_three_same (neon_quad (rs), 0, -1);
13872 const int three_ops_form = (inst.operands[2].present
13873 && !inst.operands[2].isreg);
13874 const int immoperand = (three_ops_form ? 2 : 1);
13875 enum neon_shape rs = (three_ops_form
13876 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13877 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13878 struct neon_type_el et = neon_check_type (2, rs,
13879 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13880 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13884 if (et.type == NT_invtype)
13887 if (three_ops_form)
13888 constraint (inst.operands[0].reg != inst.operands[1].reg,
13889 _("first and second operands shall be the same register"));
13891 NEON_ENCODE (IMMED, inst);
13893 immbits = inst.operands[immoperand].imm;
13896 /* .i64 is a pseudo-op, so the immediate must be a repeating
13898 if (immbits != (inst.operands[immoperand].regisimm ?
13899 inst.operands[immoperand].reg : 0))
13901 /* Set immbits to an invalid constant. */
13902 immbits = 0xdeadbeef;
13909 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13913 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13917 /* Pseudo-instruction for VBIC. */
13918 neon_invert_size (&immbits, 0, et.size);
13919 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13923 /* Pseudo-instruction for VORR. */
13924 neon_invert_size (&immbits, 0, et.size);
13925 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13935 inst.instruction |= neon_quad (rs) << 6;
13936 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13937 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13938 inst.instruction |= cmode << 8;
13939 neon_write_immbits (immbits);
13941 neon_dp_fixup (&inst);
13946 do_neon_bitfield (void)
13948 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13949 neon_check_type (3, rs, N_IGNORE_TYPE);
13950 neon_three_same (neon_quad (rs), 0, -1);
13954 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13957 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13958 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13960 if (et.type == NT_float)
13962 NEON_ENCODE (FLOAT, inst);
13963 neon_three_same (neon_quad (rs), 0, -1);
13967 NEON_ENCODE (INTEGER, inst);
13968 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13973 do_neon_dyadic_if_su (void)
13975 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13979 do_neon_dyadic_if_su_d (void)
13981 /* This version only allow D registers, but that constraint is enforced during
13982 operand parsing so we don't need to do anything extra here. */
13983 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13987 do_neon_dyadic_if_i_d (void)
13989 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13990 affected if we specify unsigned args. */
13991 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13994 enum vfp_or_neon_is_neon_bits
13997 NEON_CHECK_ARCH = 2,
13998 NEON_CHECK_ARCH8 = 4
14001 /* Call this function if an instruction which may have belonged to the VFP or
14002 Neon instruction sets, but turned out to be a Neon instruction (due to the
14003 operand types involved, etc.). We have to check and/or fix-up a couple of
14006 - Make sure the user hasn't attempted to make a Neon instruction
14008 - Alter the value in the condition code field if necessary.
14009 - Make sure that the arch supports Neon instructions.
14011 Which of these operations take place depends on bits from enum
14012 vfp_or_neon_is_neon_bits.
14014 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14015 current instruction's condition is COND_ALWAYS, the condition field is
14016 changed to inst.uncond_value. This is necessary because instructions shared
14017 between VFP and Neon may be conditional for the VFP variants only, and the
14018 unconditional Neon version must have, e.g., 0xF in the condition field. */
14021 vfp_or_neon_is_neon (unsigned check)
14023 /* Conditions are always legal in Thumb mode (IT blocks). */
14024 if (!thumb_mode && (check & NEON_CHECK_CC))
14026 if (inst.cond != COND_ALWAYS)
14028 first_error (_(BAD_COND));
14031 if (inst.uncond_value != -1)
14032 inst.instruction |= inst.uncond_value << 28;
14035 if ((check & NEON_CHECK_ARCH)
14036 && !mark_feature_used (&fpu_neon_ext_v1))
14038 first_error (_(BAD_FPU));
14042 if ((check & NEON_CHECK_ARCH8)
14043 && !mark_feature_used (&fpu_neon_ext_armv8))
14045 first_error (_(BAD_FPU));
14053 do_neon_addsub_if_i (void)
14055 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14058 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14061 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14062 affected if we specify unsigned args. */
14063 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14066 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14068 V<op> A,B (A is operand 0, B is operand 2)
14073 so handle that case specially. */
14076 neon_exchange_operands (void)
14078 void *scratch = alloca (sizeof (inst.operands[0]));
14079 if (inst.operands[1].present)
14081 /* Swap operands[1] and operands[2]. */
14082 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14083 inst.operands[1] = inst.operands[2];
14084 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14088 inst.operands[1] = inst.operands[2];
14089 inst.operands[2] = inst.operands[0];
14094 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14096 if (inst.operands[2].isreg)
14099 neon_exchange_operands ();
14100 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14104 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14105 struct neon_type_el et = neon_check_type (2, rs,
14106 N_EQK | N_SIZ, immtypes | N_KEY);
14108 NEON_ENCODE (IMMED, inst);
14109 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14110 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14111 inst.instruction |= LOW4 (inst.operands[1].reg);
14112 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14113 inst.instruction |= neon_quad (rs) << 6;
14114 inst.instruction |= (et.type == NT_float) << 10;
14115 inst.instruction |= neon_logbits (et.size) << 18;
14117 neon_dp_fixup (&inst);
14124 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14128 do_neon_cmp_inv (void)
14130 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14136 neon_compare (N_IF_32, N_IF_32, FALSE);
14139 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14140 scalars, which are encoded in 5 bits, M : Rm.
14141 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14142 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14146 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14148 unsigned regno = NEON_SCALAR_REG (scalar);
14149 unsigned elno = NEON_SCALAR_INDEX (scalar);
14154 if (regno > 7 || elno > 3)
14156 return regno | (elno << 3);
14159 if (regno > 15 || elno > 1)
14161 return regno | (elno << 4);
14165 first_error (_("scalar out of range for multiply instruction"));
14171 /* Encode multiply / multiply-accumulate scalar instructions. */
14174 neon_mul_mac (struct neon_type_el et, int ubit)
14178 /* Give a more helpful error message if we have an invalid type. */
14179 if (et.type == NT_invtype)
14182 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14183 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14184 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14185 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14186 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14187 inst.instruction |= LOW4 (scalar);
14188 inst.instruction |= HI1 (scalar) << 5;
14189 inst.instruction |= (et.type == NT_float) << 8;
14190 inst.instruction |= neon_logbits (et.size) << 20;
14191 inst.instruction |= (ubit != 0) << 24;
14193 neon_dp_fixup (&inst);
14197 do_neon_mac_maybe_scalar (void)
14199 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14202 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14205 if (inst.operands[2].isscalar)
14207 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14208 struct neon_type_el et = neon_check_type (3, rs,
14209 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14210 NEON_ENCODE (SCALAR, inst);
14211 neon_mul_mac (et, neon_quad (rs));
14215 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14216 affected if we specify unsigned args. */
14217 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14222 do_neon_fmac (void)
14224 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14227 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14230 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14236 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14237 struct neon_type_el et = neon_check_type (3, rs,
14238 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14239 neon_three_same (neon_quad (rs), 0, et.size);
14242 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14243 same types as the MAC equivalents. The polynomial type for this instruction
14244 is encoded the same as the integer type. */
14249 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14252 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14255 if (inst.operands[2].isscalar)
14256 do_neon_mac_maybe_scalar ();
14258 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14262 do_neon_qdmulh (void)
14264 if (inst.operands[2].isscalar)
14266 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14267 struct neon_type_el et = neon_check_type (3, rs,
14268 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14269 NEON_ENCODE (SCALAR, inst);
14270 neon_mul_mac (et, neon_quad (rs));
14274 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14275 struct neon_type_el et = neon_check_type (3, rs,
14276 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14277 NEON_ENCODE (INTEGER, inst);
14278 /* The U bit (rounding) comes from bit mask. */
14279 neon_three_same (neon_quad (rs), 0, et.size);
14284 do_neon_fcmp_absolute (void)
14286 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14287 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14288 /* Size field comes from bit mask. */
14289 neon_three_same (neon_quad (rs), 1, -1);
14293 do_neon_fcmp_absolute_inv (void)
14295 neon_exchange_operands ();
14296 do_neon_fcmp_absolute ();
14300 do_neon_step (void)
14302 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14303 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14304 neon_three_same (neon_quad (rs), 0, -1);
14308 do_neon_abs_neg (void)
14310 enum neon_shape rs;
14311 struct neon_type_el et;
14313 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14316 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14319 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14320 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14322 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14323 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14324 inst.instruction |= LOW4 (inst.operands[1].reg);
14325 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14326 inst.instruction |= neon_quad (rs) << 6;
14327 inst.instruction |= (et.type == NT_float) << 10;
14328 inst.instruction |= neon_logbits (et.size) << 18;
14330 neon_dp_fixup (&inst);
14336 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14337 struct neon_type_el et = neon_check_type (2, rs,
14338 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14339 int imm = inst.operands[2].imm;
14340 constraint (imm < 0 || (unsigned)imm >= et.size,
14341 _("immediate out of range for insert"));
14342 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14348 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14349 struct neon_type_el et = neon_check_type (2, rs,
14350 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14351 int imm = inst.operands[2].imm;
14352 constraint (imm < 1 || (unsigned)imm > et.size,
14353 _("immediate out of range for insert"));
14354 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14358 do_neon_qshlu_imm (void)
14360 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14361 struct neon_type_el et = neon_check_type (2, rs,
14362 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14363 int imm = inst.operands[2].imm;
14364 constraint (imm < 0 || (unsigned)imm >= et.size,
14365 _("immediate out of range for shift"));
14366 /* Only encodes the 'U present' variant of the instruction.
14367 In this case, signed types have OP (bit 8) set to 0.
14368 Unsigned types have OP set to 1. */
14369 inst.instruction |= (et.type == NT_unsigned) << 8;
14370 /* The rest of the bits are the same as other immediate shifts. */
14371 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14375 do_neon_qmovn (void)
14377 struct neon_type_el et = neon_check_type (2, NS_DQ,
14378 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14379 /* Saturating move where operands can be signed or unsigned, and the
14380 destination has the same signedness. */
14381 NEON_ENCODE (INTEGER, inst);
14382 if (et.type == NT_unsigned)
14383 inst.instruction |= 0xc0;
14385 inst.instruction |= 0x80;
14386 neon_two_same (0, 1, et.size / 2);
14390 do_neon_qmovun (void)
14392 struct neon_type_el et = neon_check_type (2, NS_DQ,
14393 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14394 /* Saturating move with unsigned results. Operands must be signed. */
14395 NEON_ENCODE (INTEGER, inst);
14396 neon_two_same (0, 1, et.size / 2);
14400 do_neon_rshift_sat_narrow (void)
14402 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14403 or unsigned. If operands are unsigned, results must also be unsigned. */
14404 struct neon_type_el et = neon_check_type (2, NS_DQI,
14405 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14406 int imm = inst.operands[2].imm;
14407 /* This gets the bounds check, size encoding and immediate bits calculation
14411 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14412 VQMOVN.I<size> <Dd>, <Qm>. */
14415 inst.operands[2].present = 0;
14416 inst.instruction = N_MNEM_vqmovn;
14421 constraint (imm < 1 || (unsigned)imm > et.size,
14422 _("immediate out of range"));
14423 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14427 do_neon_rshift_sat_narrow_u (void)
14429 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14430 or unsigned. If operands are unsigned, results must also be unsigned. */
14431 struct neon_type_el et = neon_check_type (2, NS_DQI,
14432 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14433 int imm = inst.operands[2].imm;
14434 /* This gets the bounds check, size encoding and immediate bits calculation
14438 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14439 VQMOVUN.I<size> <Dd>, <Qm>. */
14442 inst.operands[2].present = 0;
14443 inst.instruction = N_MNEM_vqmovun;
14448 constraint (imm < 1 || (unsigned)imm > et.size,
14449 _("immediate out of range"));
14450 /* FIXME: The manual is kind of unclear about what value U should have in
14451 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14453 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14457 do_neon_movn (void)
14459 struct neon_type_el et = neon_check_type (2, NS_DQ,
14460 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14461 NEON_ENCODE (INTEGER, inst);
14462 neon_two_same (0, 1, et.size / 2);
14466 do_neon_rshift_narrow (void)
14468 struct neon_type_el et = neon_check_type (2, NS_DQI,
14469 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14470 int imm = inst.operands[2].imm;
14471 /* This gets the bounds check, size encoding and immediate bits calculation
14475 /* If immediate is zero then we are a pseudo-instruction for
14476 VMOVN.I<size> <Dd>, <Qm> */
14479 inst.operands[2].present = 0;
14480 inst.instruction = N_MNEM_vmovn;
14485 constraint (imm < 1 || (unsigned)imm > et.size,
14486 _("immediate out of range for narrowing operation"));
14487 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14491 do_neon_shll (void)
14493 /* FIXME: Type checking when lengthening. */
14494 struct neon_type_el et = neon_check_type (2, NS_QDI,
14495 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14496 unsigned imm = inst.operands[2].imm;
14498 if (imm == et.size)
14500 /* Maximum shift variant. */
14501 NEON_ENCODE (INTEGER, inst);
14502 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14503 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14504 inst.instruction |= LOW4 (inst.operands[1].reg);
14505 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14506 inst.instruction |= neon_logbits (et.size) << 18;
14508 neon_dp_fixup (&inst);
14512 /* A more-specific type check for non-max versions. */
14513 et = neon_check_type (2, NS_QDI,
14514 N_EQK | N_DBL, N_SU_32 | N_KEY);
14515 NEON_ENCODE (IMMED, inst);
14516 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14520 /* Check the various types for the VCVT instruction, and return which version
14521 the current instruction is. */
14523 #define CVT_FLAVOUR_VAR \
14524 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14525 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14526 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14527 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14528 /* Half-precision conversions. */ \
14529 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14530 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14531 /* VFP instructions. */ \
14532 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14533 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14534 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14535 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14536 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14537 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14538 /* VFP instructions with bitshift. */ \
14539 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14540 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14541 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14542 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14543 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14544 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14545 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14546 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14548 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14549 neon_cvt_flavour_##C,
14551 /* The different types of conversions we can do. */
14552 enum neon_cvt_flavour
14555 neon_cvt_flavour_invalid,
14556 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14561 static enum neon_cvt_flavour
14562 get_neon_cvt_flavour (enum neon_shape rs)
14564 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14565 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14566 if (et.type != NT_invtype) \
14568 inst.error = NULL; \
14569 return (neon_cvt_flavour_##C); \
14572 struct neon_type_el et;
14573 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14574 || rs == NS_FF) ? N_VFP : 0;
14575 /* The instruction versions which take an immediate take one register
14576 argument, which is extended to the width of the full register. Thus the
14577 "source" and "destination" registers must have the same width. Hack that
14578 here by making the size equal to the key (wider, in this case) operand. */
14579 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14583 return neon_cvt_flavour_invalid;
14598 /* Neon-syntax VFP conversions. */
14601 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14603 const char *opname = 0;
14605 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14607 /* Conversions with immediate bitshift. */
14608 const char *enc[] =
14610 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14616 if (flavour < (int) ARRAY_SIZE (enc))
14618 opname = enc[flavour];
14619 constraint (inst.operands[0].reg != inst.operands[1].reg,
14620 _("operands 0 and 1 must be the same register"));
14621 inst.operands[1] = inst.operands[2];
14622 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14627 /* Conversions without bitshift. */
14628 const char *enc[] =
14630 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14636 if (flavour < (int) ARRAY_SIZE (enc))
14637 opname = enc[flavour];
14641 do_vfp_nsyn_opcode (opname);
14645 do_vfp_nsyn_cvtz (void)
14647 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14648 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14649 const char *enc[] =
14651 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14657 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14658 do_vfp_nsyn_opcode (enc[flavour]);
14662 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14663 enum neon_cvt_mode mode)
14668 set_it_insn_type (OUTSIDE_IT_INSN);
14672 case neon_cvt_flavour_s32_f64:
14676 case neon_cvt_flavour_s32_f32:
14680 case neon_cvt_flavour_u32_f64:
14684 case neon_cvt_flavour_u32_f32:
14689 first_error (_("invalid instruction shape"));
14695 case neon_cvt_mode_a: rm = 0; break;
14696 case neon_cvt_mode_n: rm = 1; break;
14697 case neon_cvt_mode_p: rm = 2; break;
14698 case neon_cvt_mode_m: rm = 3; break;
14699 default: first_error (_("invalid rounding mode")); return;
14702 NEON_ENCODE (FPV8, inst);
14703 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14704 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14705 inst.instruction |= sz << 8;
14706 inst.instruction |= op << 7;
14707 inst.instruction |= rm << 16;
14708 inst.instruction |= 0xf0000000;
14709 inst.is_neon = TRUE;
14713 do_neon_cvt_1 (enum neon_cvt_mode mode)
14715 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14716 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14717 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14719 /* PR11109: Handle round-to-zero for VCVT conversions. */
14720 if (mode == neon_cvt_mode_z
14721 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14722 && (flavour == neon_cvt_flavour_s32_f32
14723 || flavour == neon_cvt_flavour_u32_f32
14724 || flavour == neon_cvt_flavour_s32_f64
14725 || flavour == neon_cvt_flavour_u32_f64)
14726 && (rs == NS_FD || rs == NS_FF))
14728 do_vfp_nsyn_cvtz ();
14732 /* VFP rather than Neon conversions. */
14733 if (flavour >= neon_cvt_flavour_first_fp)
14735 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14736 do_vfp_nsyn_cvt (rs, flavour);
14738 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14749 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14751 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14754 /* Fixed-point conversion with #0 immediate is encoded as an
14755 integer conversion. */
14756 if (inst.operands[2].present && inst.operands[2].imm == 0)
14758 immbits = 32 - inst.operands[2].imm;
14759 NEON_ENCODE (IMMED, inst);
14760 if (flavour != neon_cvt_flavour_invalid)
14761 inst.instruction |= enctab[flavour];
14762 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14763 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14764 inst.instruction |= LOW4 (inst.operands[1].reg);
14765 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14766 inst.instruction |= neon_quad (rs) << 6;
14767 inst.instruction |= 1 << 21;
14768 inst.instruction |= immbits << 16;
14770 neon_dp_fixup (&inst);
14776 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14778 NEON_ENCODE (FLOAT, inst);
14779 set_it_insn_type (OUTSIDE_IT_INSN);
14781 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14784 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14785 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14786 inst.instruction |= LOW4 (inst.operands[1].reg);
14787 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14788 inst.instruction |= neon_quad (rs) << 6;
14789 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14790 inst.instruction |= mode << 8;
14792 inst.instruction |= 0xfc000000;
14794 inst.instruction |= 0xf0000000;
14800 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14802 NEON_ENCODE (INTEGER, inst);
14804 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14807 if (flavour != neon_cvt_flavour_invalid)
14808 inst.instruction |= enctab[flavour];
14810 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14811 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14812 inst.instruction |= LOW4 (inst.operands[1].reg);
14813 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14814 inst.instruction |= neon_quad (rs) << 6;
14815 inst.instruction |= 2 << 18;
14817 neon_dp_fixup (&inst);
14822 /* Half-precision conversions for Advanced SIMD -- neon. */
14827 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14829 as_bad (_("operand size must match register width"));
14834 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14836 as_bad (_("operand size must match register width"));
14841 inst.instruction = 0x3b60600;
14843 inst.instruction = 0x3b60700;
14845 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14846 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14847 inst.instruction |= LOW4 (inst.operands[1].reg);
14848 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14849 neon_dp_fixup (&inst);
14853 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14854 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14855 do_vfp_nsyn_cvt (rs, flavour);
14857 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14862 do_neon_cvtr (void)
14864 do_neon_cvt_1 (neon_cvt_mode_x);
14870 do_neon_cvt_1 (neon_cvt_mode_z);
14874 do_neon_cvta (void)
14876 do_neon_cvt_1 (neon_cvt_mode_a);
14880 do_neon_cvtn (void)
14882 do_neon_cvt_1 (neon_cvt_mode_n);
14886 do_neon_cvtp (void)
14888 do_neon_cvt_1 (neon_cvt_mode_p);
14892 do_neon_cvtm (void)
14894 do_neon_cvt_1 (neon_cvt_mode_m);
14898 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14901 mark_feature_used (&fpu_vfp_ext_armv8);
14903 encode_arm_vfp_reg (inst.operands[0].reg,
14904 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14905 encode_arm_vfp_reg (inst.operands[1].reg,
14906 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14907 inst.instruction |= to ? 0x10000 : 0;
14908 inst.instruction |= t ? 0x80 : 0;
14909 inst.instruction |= is_double ? 0x100 : 0;
14910 do_vfp_cond_or_thumb ();
14914 do_neon_cvttb_1 (bfd_boolean t)
14916 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14920 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14923 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14925 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14928 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14930 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14933 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14935 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14938 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14945 do_neon_cvtb (void)
14947 do_neon_cvttb_1 (FALSE);
14952 do_neon_cvtt (void)
14954 do_neon_cvttb_1 (TRUE);
14958 neon_move_immediate (void)
14960 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14961 struct neon_type_el et = neon_check_type (2, rs,
14962 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14963 unsigned immlo, immhi = 0, immbits;
14964 int op, cmode, float_p;
14966 constraint (et.type == NT_invtype,
14967 _("operand size must be specified for immediate VMOV"));
14969 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14970 op = (inst.instruction & (1 << 5)) != 0;
14972 immlo = inst.operands[1].imm;
14973 if (inst.operands[1].regisimm)
14974 immhi = inst.operands[1].reg;
14976 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14977 _("immediate has bits set outside the operand size"));
14979 float_p = inst.operands[1].immisfloat;
14981 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14982 et.size, et.type)) == FAIL)
14984 /* Invert relevant bits only. */
14985 neon_invert_size (&immlo, &immhi, et.size);
14986 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14987 with one or the other; those cases are caught by
14988 neon_cmode_for_move_imm. */
14990 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14991 &op, et.size, et.type)) == FAIL)
14993 first_error (_("immediate out of range"));
14998 inst.instruction &= ~(1 << 5);
14999 inst.instruction |= op << 5;
15001 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15002 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15003 inst.instruction |= neon_quad (rs) << 6;
15004 inst.instruction |= cmode << 8;
15006 neon_write_immbits (immbits);
15012 if (inst.operands[1].isreg)
15014 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15016 NEON_ENCODE (INTEGER, inst);
15017 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15018 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15019 inst.instruction |= LOW4 (inst.operands[1].reg);
15020 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15021 inst.instruction |= neon_quad (rs) << 6;
15025 NEON_ENCODE (IMMED, inst);
15026 neon_move_immediate ();
15029 neon_dp_fixup (&inst);
15032 /* Encode instructions of form:
15034 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15035 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15038 neon_mixed_length (struct neon_type_el et, unsigned size)
15040 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15041 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15042 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15043 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15044 inst.instruction |= LOW4 (inst.operands[2].reg);
15045 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15046 inst.instruction |= (et.type == NT_unsigned) << 24;
15047 inst.instruction |= neon_logbits (size) << 20;
15049 neon_dp_fixup (&inst);
15053 do_neon_dyadic_long (void)
15055 /* FIXME: Type checking for lengthening op. */
15056 struct neon_type_el et = neon_check_type (3, NS_QDD,
15057 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15058 neon_mixed_length (et, et.size);
15062 do_neon_abal (void)
15064 struct neon_type_el et = neon_check_type (3, NS_QDD,
15065 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15066 neon_mixed_length (et, et.size);
15070 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15072 if (inst.operands[2].isscalar)
15074 struct neon_type_el et = neon_check_type (3, NS_QDS,
15075 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15076 NEON_ENCODE (SCALAR, inst);
15077 neon_mul_mac (et, et.type == NT_unsigned);
15081 struct neon_type_el et = neon_check_type (3, NS_QDD,
15082 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15083 NEON_ENCODE (INTEGER, inst);
15084 neon_mixed_length (et, et.size);
15089 do_neon_mac_maybe_scalar_long (void)
15091 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15095 do_neon_dyadic_wide (void)
15097 struct neon_type_el et = neon_check_type (3, NS_QQD,
15098 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15099 neon_mixed_length (et, et.size);
15103 do_neon_dyadic_narrow (void)
15105 struct neon_type_el et = neon_check_type (3, NS_QDD,
15106 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15107 /* Operand sign is unimportant, and the U bit is part of the opcode,
15108 so force the operand type to integer. */
15109 et.type = NT_integer;
15110 neon_mixed_length (et, et.size / 2);
15114 do_neon_mul_sat_scalar_long (void)
15116 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15120 do_neon_vmull (void)
15122 if (inst.operands[2].isscalar)
15123 do_neon_mac_maybe_scalar_long ();
15126 struct neon_type_el et = neon_check_type (3, NS_QDD,
15127 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15129 if (et.type == NT_poly)
15130 NEON_ENCODE (POLY, inst);
15132 NEON_ENCODE (INTEGER, inst);
15134 /* For polynomial encoding the U bit must be zero, and the size must
15135 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15136 obviously, as 0b10). */
15139 /* Check we're on the correct architecture. */
15140 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15142 _("Instruction form not available on this architecture.");
15147 neon_mixed_length (et, et.size);
15154 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15155 struct neon_type_el et = neon_check_type (3, rs,
15156 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15157 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15159 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15160 _("shift out of range"));
15161 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15162 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15163 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15164 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15165 inst.instruction |= LOW4 (inst.operands[2].reg);
15166 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15167 inst.instruction |= neon_quad (rs) << 6;
15168 inst.instruction |= imm << 8;
15170 neon_dp_fixup (&inst);
15176 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15177 struct neon_type_el et = neon_check_type (2, rs,
15178 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15179 unsigned op = (inst.instruction >> 7) & 3;
15180 /* N (width of reversed regions) is encoded as part of the bitmask. We
15181 extract it here to check the elements to be reversed are smaller.
15182 Otherwise we'd get a reserved instruction. */
15183 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15184 gas_assert (elsize != 0);
15185 constraint (et.size >= elsize,
15186 _("elements must be smaller than reversal region"));
15187 neon_two_same (neon_quad (rs), 1, et.size);
15193 if (inst.operands[1].isscalar)
15195 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15196 struct neon_type_el et = neon_check_type (2, rs,
15197 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15198 unsigned sizebits = et.size >> 3;
15199 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15200 int logsize = neon_logbits (et.size);
15201 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15203 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15206 NEON_ENCODE (SCALAR, inst);
15207 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15208 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15209 inst.instruction |= LOW4 (dm);
15210 inst.instruction |= HI1 (dm) << 5;
15211 inst.instruction |= neon_quad (rs) << 6;
15212 inst.instruction |= x << 17;
15213 inst.instruction |= sizebits << 16;
15215 neon_dp_fixup (&inst);
15219 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15220 struct neon_type_el et = neon_check_type (2, rs,
15221 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15222 /* Duplicate ARM register to lanes of vector. */
15223 NEON_ENCODE (ARMREG, inst);
15226 case 8: inst.instruction |= 0x400000; break;
15227 case 16: inst.instruction |= 0x000020; break;
15228 case 32: inst.instruction |= 0x000000; break;
15231 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15232 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15233 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15234 inst.instruction |= neon_quad (rs) << 21;
15235 /* The encoding for this instruction is identical for the ARM and Thumb
15236 variants, except for the condition field. */
15237 do_vfp_cond_or_thumb ();
15241 /* VMOV has particularly many variations. It can be one of:
15242 0. VMOV<c><q> <Qd>, <Qm>
15243 1. VMOV<c><q> <Dd>, <Dm>
15244 (Register operations, which are VORR with Rm = Rn.)
15245 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15246 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15248 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15249 (ARM register to scalar.)
15250 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15251 (Two ARM registers to vector.)
15252 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15253 (Scalar to ARM register.)
15254 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15255 (Vector to two ARM registers.)
15256 8. VMOV.F32 <Sd>, <Sm>
15257 9. VMOV.F64 <Dd>, <Dm>
15258 (VFP register moves.)
15259 10. VMOV.F32 <Sd>, #imm
15260 11. VMOV.F64 <Dd>, #imm
15261 (VFP float immediate load.)
15262 12. VMOV <Rd>, <Sm>
15263 (VFP single to ARM reg.)
15264 13. VMOV <Sd>, <Rm>
15265 (ARM reg to VFP single.)
15266 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15267 (Two ARM regs to two VFP singles.)
15268 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15269 (Two VFP singles to two ARM regs.)
15271 These cases can be disambiguated using neon_select_shape, except cases 1/9
15272 and 3/11 which depend on the operand type too.
15274 All the encoded bits are hardcoded by this function.
15276 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15277 Cases 5, 7 may be used with VFPv2 and above.
15279 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15280 can specify a type where it doesn't make sense to, and is ignored). */
15285 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15286 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15288 struct neon_type_el et;
15289 const char *ldconst = 0;
15293 case NS_DD: /* case 1/9. */
15294 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15295 /* It is not an error here if no type is given. */
15297 if (et.type == NT_float && et.size == 64)
15299 do_vfp_nsyn_opcode ("fcpyd");
15302 /* fall through. */
15304 case NS_QQ: /* case 0/1. */
15306 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15308 /* The architecture manual I have doesn't explicitly state which
15309 value the U bit should have for register->register moves, but
15310 the equivalent VORR instruction has U = 0, so do that. */
15311 inst.instruction = 0x0200110;
15312 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15313 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15314 inst.instruction |= LOW4 (inst.operands[1].reg);
15315 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15316 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15317 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15318 inst.instruction |= neon_quad (rs) << 6;
15320 neon_dp_fixup (&inst);
15324 case NS_DI: /* case 3/11. */
15325 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15327 if (et.type == NT_float && et.size == 64)
15329 /* case 11 (fconstd). */
15330 ldconst = "fconstd";
15331 goto encode_fconstd;
15333 /* fall through. */
15335 case NS_QI: /* case 2/3. */
15336 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15338 inst.instruction = 0x0800010;
15339 neon_move_immediate ();
15340 neon_dp_fixup (&inst);
15343 case NS_SR: /* case 4. */
15345 unsigned bcdebits = 0;
15347 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15348 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15350 /* .<size> is optional here, defaulting to .32. */
15351 if (inst.vectype.elems == 0
15352 && inst.operands[0].vectype.type == NT_invtype
15353 && inst.operands[1].vectype.type == NT_invtype)
15355 inst.vectype.el[0].type = NT_untyped;
15356 inst.vectype.el[0].size = 32;
15357 inst.vectype.elems = 1;
15360 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15361 logsize = neon_logbits (et.size);
15363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15366 && et.size != 32, _(BAD_FPU));
15367 constraint (et.type == NT_invtype, _("bad type for scalar"));
15368 constraint (x >= 64 / et.size, _("scalar index out of range"));
15372 case 8: bcdebits = 0x8; break;
15373 case 16: bcdebits = 0x1; break;
15374 case 32: bcdebits = 0x0; break;
15378 bcdebits |= x << logsize;
15380 inst.instruction = 0xe000b10;
15381 do_vfp_cond_or_thumb ();
15382 inst.instruction |= LOW4 (dn) << 16;
15383 inst.instruction |= HI1 (dn) << 7;
15384 inst.instruction |= inst.operands[1].reg << 12;
15385 inst.instruction |= (bcdebits & 3) << 5;
15386 inst.instruction |= (bcdebits >> 2) << 21;
15390 case NS_DRR: /* case 5 (fmdrr). */
15391 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15394 inst.instruction = 0xc400b10;
15395 do_vfp_cond_or_thumb ();
15396 inst.instruction |= LOW4 (inst.operands[0].reg);
15397 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15398 inst.instruction |= inst.operands[1].reg << 12;
15399 inst.instruction |= inst.operands[2].reg << 16;
15402 case NS_RS: /* case 6. */
15405 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15406 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15407 unsigned abcdebits = 0;
15409 /* .<dt> is optional here, defaulting to .32. */
15410 if (inst.vectype.elems == 0
15411 && inst.operands[0].vectype.type == NT_invtype
15412 && inst.operands[1].vectype.type == NT_invtype)
15414 inst.vectype.el[0].type = NT_untyped;
15415 inst.vectype.el[0].size = 32;
15416 inst.vectype.elems = 1;
15419 et = neon_check_type (2, NS_NULL,
15420 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15421 logsize = neon_logbits (et.size);
15423 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15426 && et.size != 32, _(BAD_FPU));
15427 constraint (et.type == NT_invtype, _("bad type for scalar"));
15428 constraint (x >= 64 / et.size, _("scalar index out of range"));
15432 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15433 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15434 case 32: abcdebits = 0x00; break;
15438 abcdebits |= x << logsize;
15439 inst.instruction = 0xe100b10;
15440 do_vfp_cond_or_thumb ();
15441 inst.instruction |= LOW4 (dn) << 16;
15442 inst.instruction |= HI1 (dn) << 7;
15443 inst.instruction |= inst.operands[0].reg << 12;
15444 inst.instruction |= (abcdebits & 3) << 5;
15445 inst.instruction |= (abcdebits >> 2) << 21;
15449 case NS_RRD: /* case 7 (fmrrd). */
15450 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15453 inst.instruction = 0xc500b10;
15454 do_vfp_cond_or_thumb ();
15455 inst.instruction |= inst.operands[0].reg << 12;
15456 inst.instruction |= inst.operands[1].reg << 16;
15457 inst.instruction |= LOW4 (inst.operands[2].reg);
15458 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15461 case NS_FF: /* case 8 (fcpys). */
15462 do_vfp_nsyn_opcode ("fcpys");
15465 case NS_FI: /* case 10 (fconsts). */
15466 ldconst = "fconsts";
15468 if (is_quarter_float (inst.operands[1].imm))
15470 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15471 do_vfp_nsyn_opcode (ldconst);
15474 first_error (_("immediate out of range"));
15477 case NS_RF: /* case 12 (fmrs). */
15478 do_vfp_nsyn_opcode ("fmrs");
15481 case NS_FR: /* case 13 (fmsr). */
15482 do_vfp_nsyn_opcode ("fmsr");
15485 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15486 (one of which is a list), but we have parsed four. Do some fiddling to
15487 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15489 case NS_RRFF: /* case 14 (fmrrs). */
15490 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15491 _("VFP registers must be adjacent"));
15492 inst.operands[2].imm = 2;
15493 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15494 do_vfp_nsyn_opcode ("fmrrs");
15497 case NS_FFRR: /* case 15 (fmsrr). */
15498 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15499 _("VFP registers must be adjacent"));
15500 inst.operands[1] = inst.operands[2];
15501 inst.operands[2] = inst.operands[3];
15502 inst.operands[0].imm = 2;
15503 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15504 do_vfp_nsyn_opcode ("fmsrr");
15508 /* neon_select_shape has determined that the instruction
15509 shape is wrong and has already set the error message. */
15518 do_neon_rshift_round_imm (void)
15520 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15521 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15522 int imm = inst.operands[2].imm;
15524 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15527 inst.operands[2].present = 0;
15532 constraint (imm < 1 || (unsigned)imm > et.size,
15533 _("immediate out of range for shift"));
15534 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15539 do_neon_movl (void)
15541 struct neon_type_el et = neon_check_type (2, NS_QD,
15542 N_EQK | N_DBL, N_SU_32 | N_KEY);
15543 unsigned sizebits = et.size >> 3;
15544 inst.instruction |= sizebits << 19;
15545 neon_two_same (0, et.type == NT_unsigned, -1);
15551 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15552 struct neon_type_el et = neon_check_type (2, rs,
15553 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15554 NEON_ENCODE (INTEGER, inst);
15555 neon_two_same (neon_quad (rs), 1, et.size);
15559 do_neon_zip_uzp (void)
15561 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15562 struct neon_type_el et = neon_check_type (2, rs,
15563 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15564 if (rs == NS_DD && et.size == 32)
15566 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15567 inst.instruction = N_MNEM_vtrn;
15571 neon_two_same (neon_quad (rs), 1, et.size);
15575 do_neon_sat_abs_neg (void)
15577 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15578 struct neon_type_el et = neon_check_type (2, rs,
15579 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15580 neon_two_same (neon_quad (rs), 1, et.size);
15584 do_neon_pair_long (void)
15586 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15587 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15588 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15589 inst.instruction |= (et.type == NT_unsigned) << 7;
15590 neon_two_same (neon_quad (rs), 1, et.size);
15594 do_neon_recip_est (void)
15596 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15597 struct neon_type_el et = neon_check_type (2, rs,
15598 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15599 inst.instruction |= (et.type == NT_float) << 8;
15600 neon_two_same (neon_quad (rs), 1, et.size);
15606 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15607 struct neon_type_el et = neon_check_type (2, rs,
15608 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15609 neon_two_same (neon_quad (rs), 1, et.size);
15615 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15616 struct neon_type_el et = neon_check_type (2, rs,
15617 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15618 neon_two_same (neon_quad (rs), 1, et.size);
15624 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15625 struct neon_type_el et = neon_check_type (2, rs,
15626 N_EQK | N_INT, N_8 | N_KEY);
15627 neon_two_same (neon_quad (rs), 1, et.size);
15633 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15634 neon_two_same (neon_quad (rs), 1, -1);
15638 do_neon_tbl_tbx (void)
15640 unsigned listlenbits;
15641 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15643 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15645 first_error (_("bad list length for table lookup"));
15649 listlenbits = inst.operands[1].imm - 1;
15650 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15651 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15652 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15653 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15654 inst.instruction |= LOW4 (inst.operands[2].reg);
15655 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15656 inst.instruction |= listlenbits << 8;
15658 neon_dp_fixup (&inst);
15662 do_neon_ldm_stm (void)
15664 /* P, U and L bits are part of bitmask. */
15665 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15666 unsigned offsetbits = inst.operands[1].imm * 2;
15668 if (inst.operands[1].issingle)
15670 do_vfp_nsyn_ldm_stm (is_dbmode);
15674 constraint (is_dbmode && !inst.operands[0].writeback,
15675 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15677 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15678 _("register list must contain at least 1 and at most 16 "
15681 inst.instruction |= inst.operands[0].reg << 16;
15682 inst.instruction |= inst.operands[0].writeback << 21;
15683 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15684 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15686 inst.instruction |= offsetbits;
15688 do_vfp_cond_or_thumb ();
15692 do_neon_ldr_str (void)
15694 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15696 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15697 And is UNPREDICTABLE in thumb mode. */
15699 && inst.operands[1].reg == REG_PC
15700 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15703 inst.error = _("Use of PC here is UNPREDICTABLE");
15704 else if (warn_on_deprecated)
15705 as_warn (_("Use of PC here is deprecated"));
15708 if (inst.operands[0].issingle)
15711 do_vfp_nsyn_opcode ("flds");
15713 do_vfp_nsyn_opcode ("fsts");
15718 do_vfp_nsyn_opcode ("fldd");
15720 do_vfp_nsyn_opcode ("fstd");
15724 /* "interleave" version also handles non-interleaving register VLD1/VST1
15728 do_neon_ld_st_interleave (void)
15730 struct neon_type_el et = neon_check_type (1, NS_NULL,
15731 N_8 | N_16 | N_32 | N_64);
15732 unsigned alignbits = 0;
15734 /* The bits in this table go:
15735 0: register stride of one (0) or two (1)
15736 1,2: register list length, minus one (1, 2, 3, 4).
15737 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15738 We use -1 for invalid entries. */
15739 const int typetable[] =
15741 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15742 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15743 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15744 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15748 if (et.type == NT_invtype)
15751 if (inst.operands[1].immisalign)
15752 switch (inst.operands[1].imm >> 8)
15754 case 64: alignbits = 1; break;
15756 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15757 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15758 goto bad_alignment;
15762 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15763 goto bad_alignment;
15768 first_error (_("bad alignment"));
15772 inst.instruction |= alignbits << 4;
15773 inst.instruction |= neon_logbits (et.size) << 6;
15775 /* Bits [4:6] of the immediate in a list specifier encode register stride
15776 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15777 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15778 up the right value for "type" in a table based on this value and the given
15779 list style, then stick it back. */
15780 idx = ((inst.operands[0].imm >> 4) & 7)
15781 | (((inst.instruction >> 8) & 3) << 3);
15783 typebits = typetable[idx];
15785 constraint (typebits == -1, _("bad list type for instruction"));
15787 inst.instruction &= ~0xf00;
15788 inst.instruction |= typebits << 8;
15791 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15792 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15793 otherwise. The variable arguments are a list of pairs of legal (size, align)
15794 values, terminated with -1. */
15797 neon_alignment_bit (int size, int align, int *do_align, ...)
15800 int result = FAIL, thissize, thisalign;
15802 if (!inst.operands[1].immisalign)
15808 va_start (ap, do_align);
15812 thissize = va_arg (ap, int);
15813 if (thissize == -1)
15815 thisalign = va_arg (ap, int);
15817 if (size == thissize && align == thisalign)
15820 while (result != SUCCESS);
15824 if (result == SUCCESS)
15827 first_error (_("unsupported alignment for instruction"));
15833 do_neon_ld_st_lane (void)
15835 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15836 int align_good, do_align = 0;
15837 int logsize = neon_logbits (et.size);
15838 int align = inst.operands[1].imm >> 8;
15839 int n = (inst.instruction >> 8) & 3;
15840 int max_el = 64 / et.size;
15842 if (et.type == NT_invtype)
15845 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15846 _("bad list length"));
15847 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15848 _("scalar index out of range"));
15849 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15851 _("stride of 2 unavailable when element size is 8"));
15855 case 0: /* VLD1 / VST1. */
15856 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15858 if (align_good == FAIL)
15862 unsigned alignbits = 0;
15865 case 16: alignbits = 0x1; break;
15866 case 32: alignbits = 0x3; break;
15869 inst.instruction |= alignbits << 4;
15873 case 1: /* VLD2 / VST2. */
15874 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15876 if (align_good == FAIL)
15879 inst.instruction |= 1 << 4;
15882 case 2: /* VLD3 / VST3. */
15883 constraint (inst.operands[1].immisalign,
15884 _("can't use alignment with this instruction"));
15887 case 3: /* VLD4 / VST4. */
15888 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15889 16, 64, 32, 64, 32, 128, -1);
15890 if (align_good == FAIL)
15894 unsigned alignbits = 0;
15897 case 8: alignbits = 0x1; break;
15898 case 16: alignbits = 0x1; break;
15899 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15902 inst.instruction |= alignbits << 4;
15909 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15910 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15911 inst.instruction |= 1 << (4 + logsize);
15913 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15914 inst.instruction |= logsize << 10;
15917 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15920 do_neon_ld_dup (void)
15922 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15923 int align_good, do_align = 0;
15925 if (et.type == NT_invtype)
15928 switch ((inst.instruction >> 8) & 3)
15930 case 0: /* VLD1. */
15931 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15932 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15933 &do_align, 16, 16, 32, 32, -1);
15934 if (align_good == FAIL)
15936 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15939 case 2: inst.instruction |= 1 << 5; break;
15940 default: first_error (_("bad list length")); return;
15942 inst.instruction |= neon_logbits (et.size) << 6;
15945 case 1: /* VLD2. */
15946 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15947 &do_align, 8, 16, 16, 32, 32, 64, -1);
15948 if (align_good == FAIL)
15950 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15951 _("bad list length"));
15952 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15953 inst.instruction |= 1 << 5;
15954 inst.instruction |= neon_logbits (et.size) << 6;
15957 case 2: /* VLD3. */
15958 constraint (inst.operands[1].immisalign,
15959 _("can't use alignment with this instruction"));
15960 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15961 _("bad list length"));
15962 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15963 inst.instruction |= 1 << 5;
15964 inst.instruction |= neon_logbits (et.size) << 6;
15967 case 3: /* VLD4. */
15969 int align = inst.operands[1].imm >> 8;
15970 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15971 16, 64, 32, 64, 32, 128, -1);
15972 if (align_good == FAIL)
15974 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15975 _("bad list length"));
15976 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15977 inst.instruction |= 1 << 5;
15978 if (et.size == 32 && align == 128)
15979 inst.instruction |= 0x3 << 6;
15981 inst.instruction |= neon_logbits (et.size) << 6;
15988 inst.instruction |= do_align << 4;
15991 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15992 apart from bits [11:4]. */
15995 do_neon_ldx_stx (void)
15997 if (inst.operands[1].isreg)
15998 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16000 switch (NEON_LANE (inst.operands[0].imm))
16002 case NEON_INTERLEAVE_LANES:
16003 NEON_ENCODE (INTERLV, inst);
16004 do_neon_ld_st_interleave ();
16007 case NEON_ALL_LANES:
16008 NEON_ENCODE (DUP, inst);
16009 if (inst.instruction == N_INV)
16011 first_error ("only loads support such operands");
16018 NEON_ENCODE (LANE, inst);
16019 do_neon_ld_st_lane ();
16022 /* L bit comes from bit mask. */
16023 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16024 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16025 inst.instruction |= inst.operands[1].reg << 16;
16027 if (inst.operands[1].postind)
16029 int postreg = inst.operands[1].imm & 0xf;
16030 constraint (!inst.operands[1].immisreg,
16031 _("post-index must be a register"));
16032 constraint (postreg == 0xd || postreg == 0xf,
16033 _("bad register for post-index"));
16034 inst.instruction |= postreg;
16038 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16039 constraint (inst.reloc.exp.X_op != O_constant
16040 || inst.reloc.exp.X_add_number != 0,
16043 if (inst.operands[1].writeback)
16045 inst.instruction |= 0xd;
16048 inst.instruction |= 0xf;
16052 inst.instruction |= 0xf9000000;
16054 inst.instruction |= 0xf4000000;
16059 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16061 NEON_ENCODE (FPV8, inst);
16064 do_vfp_sp_dyadic ();
16066 do_vfp_dp_rd_rn_rm ();
16069 inst.instruction |= 0x100;
16071 inst.instruction |= 0xf0000000;
16077 set_it_insn_type (OUTSIDE_IT_INSN);
16079 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16080 first_error (_("invalid instruction shape"));
16086 set_it_insn_type (OUTSIDE_IT_INSN);
16088 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16091 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16094 neon_dyadic_misc (NT_untyped, N_F32, 0);
16098 do_vrint_1 (enum neon_cvt_mode mode)
16100 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16101 struct neon_type_el et;
16106 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16107 if (et.type != NT_invtype)
16109 /* VFP encodings. */
16110 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16111 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16112 set_it_insn_type (OUTSIDE_IT_INSN);
16114 NEON_ENCODE (FPV8, inst);
16116 do_vfp_sp_monadic ();
16118 do_vfp_dp_rd_rm ();
16122 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16123 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16124 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16125 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16126 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16127 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16128 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16132 inst.instruction |= (rs == NS_DD) << 8;
16133 do_vfp_cond_or_thumb ();
16137 /* Neon encodings (or something broken...). */
16139 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16141 if (et.type == NT_invtype)
16144 set_it_insn_type (OUTSIDE_IT_INSN);
16145 NEON_ENCODE (FLOAT, inst);
16147 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16150 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16151 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16152 inst.instruction |= LOW4 (inst.operands[1].reg);
16153 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16154 inst.instruction |= neon_quad (rs) << 6;
16157 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16158 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16159 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16160 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16161 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16162 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16163 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16168 inst.instruction |= 0xfc000000;
16170 inst.instruction |= 0xf0000000;
16177 do_vrint_1 (neon_cvt_mode_x);
16183 do_vrint_1 (neon_cvt_mode_z);
16189 do_vrint_1 (neon_cvt_mode_r);
16195 do_vrint_1 (neon_cvt_mode_a);
16201 do_vrint_1 (neon_cvt_mode_n);
16207 do_vrint_1 (neon_cvt_mode_p);
16213 do_vrint_1 (neon_cvt_mode_m);
16216 /* Crypto v1 instructions. */
16218 do_crypto_2op_1 (unsigned elttype, int op)
16220 set_it_insn_type (OUTSIDE_IT_INSN);
16222 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16228 NEON_ENCODE (INTEGER, inst);
16229 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16230 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16231 inst.instruction |= LOW4 (inst.operands[1].reg);
16232 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16234 inst.instruction |= op << 6;
16237 inst.instruction |= 0xfc000000;
16239 inst.instruction |= 0xf0000000;
16243 do_crypto_3op_1 (int u, int op)
16245 set_it_insn_type (OUTSIDE_IT_INSN);
16247 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16248 N_32 | N_UNT | N_KEY).type == NT_invtype)
16253 NEON_ENCODE (INTEGER, inst);
16254 neon_three_same (1, u, 8 << op);
16260 do_crypto_2op_1 (N_8, 0);
16266 do_crypto_2op_1 (N_8, 1);
16272 do_crypto_2op_1 (N_8, 2);
16278 do_crypto_2op_1 (N_8, 3);
16284 do_crypto_3op_1 (0, 0);
16290 do_crypto_3op_1 (0, 1);
16296 do_crypto_3op_1 (0, 2);
16302 do_crypto_3op_1 (0, 3);
16308 do_crypto_3op_1 (1, 0);
16314 do_crypto_3op_1 (1, 1);
16318 do_sha256su1 (void)
16320 do_crypto_3op_1 (1, 2);
16326 do_crypto_2op_1 (N_32, -1);
16332 do_crypto_2op_1 (N_32, 0);
16336 do_sha256su0 (void)
16338 do_crypto_2op_1 (N_32, 1);
16342 do_crc32_1 (unsigned int poly, unsigned int sz)
16344 unsigned int Rd = inst.operands[0].reg;
16345 unsigned int Rn = inst.operands[1].reg;
16346 unsigned int Rm = inst.operands[2].reg;
16348 set_it_insn_type (OUTSIDE_IT_INSN);
16349 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16350 inst.instruction |= LOW4 (Rn) << 16;
16351 inst.instruction |= LOW4 (Rm);
16352 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16353 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16355 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16356 as_warn (UNPRED_REG ("r15"));
16357 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16358 as_warn (UNPRED_REG ("r13"));
16398 /* Overall per-instruction processing. */
16400 /* We need to be able to fix up arbitrary expressions in some statements.
16401 This is so that we can handle symbols that are an arbitrary distance from
16402 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16403 which returns part of an address in a form which will be valid for
16404 a data instruction. We do this by pushing the expression into a symbol
16405 in the expr_section, and creating a fix for that. */
16408 fix_new_arm (fragS * frag,
16422 /* Create an absolute valued symbol, so we have something to
16423 refer to in the object file. Unfortunately for us, gas's
16424 generic expression parsing will already have folded out
16425 any use of .set foo/.type foo %function that may have
16426 been used to set type information of the target location,
16427 that's being specified symbolically. We have to presume
16428 the user knows what they are doing. */
16432 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16434 symbol = symbol_find_or_make (name);
16435 S_SET_SEGMENT (symbol, absolute_section);
16436 symbol_set_frag (symbol, &zero_address_frag);
16437 S_SET_VALUE (symbol, exp->X_add_number);
16438 exp->X_op = O_symbol;
16439 exp->X_add_symbol = symbol;
16440 exp->X_add_number = 0;
16446 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16447 (enum bfd_reloc_code_real) reloc);
16451 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16452 pc_rel, (enum bfd_reloc_code_real) reloc);
16456 /* Mark whether the fix is to a THUMB instruction, or an ARM
16458 new_fix->tc_fix_data = thumb_mode;
16461 /* Create a frg for an instruction requiring relaxation. */
16463 output_relax_insn (void)
16469 /* The size of the instruction is unknown, so tie the debug info to the
16470 start of the instruction. */
16471 dwarf2_emit_insn (0);
16473 switch (inst.reloc.exp.X_op)
16476 sym = inst.reloc.exp.X_add_symbol;
16477 offset = inst.reloc.exp.X_add_number;
16481 offset = inst.reloc.exp.X_add_number;
16484 sym = make_expr_symbol (&inst.reloc.exp);
16488 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16489 inst.relax, sym, offset, NULL/*offset, opcode*/);
16490 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16493 /* Write a 32-bit thumb instruction to buf. */
16495 put_thumb32_insn (char * buf, unsigned long insn)
16497 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16498 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16502 output_inst (const char * str)
16508 as_bad ("%s -- `%s'", inst.error, str);
16513 output_relax_insn ();
16516 if (inst.size == 0)
16519 to = frag_more (inst.size);
16520 /* PR 9814: Record the thumb mode into the current frag so that we know
16521 what type of NOP padding to use, if necessary. We override any previous
16522 setting so that if the mode has changed then the NOPS that we use will
16523 match the encoding of the last instruction in the frag. */
16524 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16526 if (thumb_mode && (inst.size > THUMB_SIZE))
16528 gas_assert (inst.size == (2 * THUMB_SIZE));
16529 put_thumb32_insn (to, inst.instruction);
16531 else if (inst.size > INSN_SIZE)
16533 gas_assert (inst.size == (2 * INSN_SIZE));
16534 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16535 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16538 md_number_to_chars (to, inst.instruction, inst.size);
16540 if (inst.reloc.type != BFD_RELOC_UNUSED)
16541 fix_new_arm (frag_now, to - frag_now->fr_literal,
16542 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16545 dwarf2_emit_insn (inst.size);
16549 output_it_inst (int cond, int mask, char * to)
16551 unsigned long instruction = 0xbf00;
16554 instruction |= mask;
16555 instruction |= cond << 4;
16559 to = frag_more (2);
16561 dwarf2_emit_insn (2);
16565 md_number_to_chars (to, instruction, 2);
16570 /* Tag values used in struct asm_opcode's tag field. */
16573 OT_unconditional, /* Instruction cannot be conditionalized.
16574 The ARM condition field is still 0xE. */
16575 OT_unconditionalF, /* Instruction cannot be conditionalized
16576 and carries 0xF in its ARM condition field. */
16577 OT_csuffix, /* Instruction takes a conditional suffix. */
16578 OT_csuffixF, /* Some forms of the instruction take a conditional
16579 suffix, others place 0xF where the condition field
16581 OT_cinfix3, /* Instruction takes a conditional infix,
16582 beginning at character index 3. (In
16583 unified mode, it becomes a suffix.) */
16584 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16585 tsts, cmps, cmns, and teqs. */
16586 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16587 character index 3, even in unified mode. Used for
16588 legacy instructions where suffix and infix forms
16589 may be ambiguous. */
16590 OT_csuf_or_in3, /* Instruction takes either a conditional
16591 suffix or an infix at character index 3. */
16592 OT_odd_infix_unc, /* This is the unconditional variant of an
16593 instruction that takes a conditional infix
16594 at an unusual position. In unified mode,
16595 this variant will accept a suffix. */
16596 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16597 are the conditional variants of instructions that
16598 take conditional infixes in unusual positions.
16599 The infix appears at character index
16600 (tag - OT_odd_infix_0). These are not accepted
16601 in unified mode. */
16604 /* Subroutine of md_assemble, responsible for looking up the primary
16605 opcode from the mnemonic the user wrote. STR points to the
16606 beginning of the mnemonic.
16608 This is not simply a hash table lookup, because of conditional
16609 variants. Most instructions have conditional variants, which are
16610 expressed with a _conditional affix_ to the mnemonic. If we were
16611 to encode each conditional variant as a literal string in the opcode
16612 table, it would have approximately 20,000 entries.
16614 Most mnemonics take this affix as a suffix, and in unified syntax,
16615 'most' is upgraded to 'all'. However, in the divided syntax, some
16616 instructions take the affix as an infix, notably the s-variants of
16617 the arithmetic instructions. Of those instructions, all but six
16618 have the infix appear after the third character of the mnemonic.
16620 Accordingly, the algorithm for looking up primary opcodes given
16623 1. Look up the identifier in the opcode table.
16624 If we find a match, go to step U.
16626 2. Look up the last two characters of the identifier in the
16627 conditions table. If we find a match, look up the first N-2
16628 characters of the identifier in the opcode table. If we
16629 find a match, go to step CE.
16631 3. Look up the fourth and fifth characters of the identifier in
16632 the conditions table. If we find a match, extract those
16633 characters from the identifier, and look up the remaining
16634 characters in the opcode table. If we find a match, go
16639 U. Examine the tag field of the opcode structure, in case this is
16640 one of the six instructions with its conditional infix in an
16641 unusual place. If it is, the tag tells us where to find the
16642 infix; look it up in the conditions table and set inst.cond
16643 accordingly. Otherwise, this is an unconditional instruction.
16644 Again set inst.cond accordingly. Return the opcode structure.
16646 CE. Examine the tag field to make sure this is an instruction that
16647 should receive a conditional suffix. If it is not, fail.
16648 Otherwise, set inst.cond from the suffix we already looked up,
16649 and return the opcode structure.
16651 CM. Examine the tag field to make sure this is an instruction that
16652 should receive a conditional infix after the third character.
16653 If it is not, fail. Otherwise, undo the edits to the current
16654 line of input and proceed as for case CE. */
16656 static const struct asm_opcode *
16657 opcode_lookup (char **str)
16661 const struct asm_opcode *opcode;
16662 const struct asm_cond *cond;
16665 /* Scan up to the end of the mnemonic, which must end in white space,
16666 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16667 for (base = end = *str; *end != '\0'; end++)
16668 if (*end == ' ' || *end == '.')
16674 /* Handle a possible width suffix and/or Neon type suffix. */
16679 /* The .w and .n suffixes are only valid if the unified syntax is in
16681 if (unified_syntax && end[1] == 'w')
16683 else if (unified_syntax && end[1] == 'n')
16688 inst.vectype.elems = 0;
16690 *str = end + offset;
16692 if (end[offset] == '.')
16694 /* See if we have a Neon type suffix (possible in either unified or
16695 non-unified ARM syntax mode). */
16696 if (parse_neon_type (&inst.vectype, str) == FAIL)
16699 else if (end[offset] != '\0' && end[offset] != ' ')
16705 /* Look for unaffixed or special-case affixed mnemonic. */
16706 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16711 if (opcode->tag < OT_odd_infix_0)
16713 inst.cond = COND_ALWAYS;
16717 if (warn_on_deprecated && unified_syntax)
16718 as_warn (_("conditional infixes are deprecated in unified syntax"));
16719 affix = base + (opcode->tag - OT_odd_infix_0);
16720 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16723 inst.cond = cond->value;
16727 /* Cannot have a conditional suffix on a mnemonic of less than two
16729 if (end - base < 3)
16732 /* Look for suffixed mnemonic. */
16734 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16735 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16737 if (opcode && cond)
16740 switch (opcode->tag)
16742 case OT_cinfix3_legacy:
16743 /* Ignore conditional suffixes matched on infix only mnemonics. */
16747 case OT_cinfix3_deprecated:
16748 case OT_odd_infix_unc:
16749 if (!unified_syntax)
16751 /* else fall through */
16755 case OT_csuf_or_in3:
16756 inst.cond = cond->value;
16759 case OT_unconditional:
16760 case OT_unconditionalF:
16762 inst.cond = cond->value;
16765 /* Delayed diagnostic. */
16766 inst.error = BAD_COND;
16767 inst.cond = COND_ALWAYS;
16776 /* Cannot have a usual-position infix on a mnemonic of less than
16777 six characters (five would be a suffix). */
16778 if (end - base < 6)
16781 /* Look for infixed mnemonic in the usual position. */
16783 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16787 memcpy (save, affix, 2);
16788 memmove (affix, affix + 2, (end - affix) - 2);
16789 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16791 memmove (affix + 2, affix, (end - affix) - 2);
16792 memcpy (affix, save, 2);
16795 && (opcode->tag == OT_cinfix3
16796 || opcode->tag == OT_cinfix3_deprecated
16797 || opcode->tag == OT_csuf_or_in3
16798 || opcode->tag == OT_cinfix3_legacy))
16801 if (warn_on_deprecated && unified_syntax
16802 && (opcode->tag == OT_cinfix3
16803 || opcode->tag == OT_cinfix3_deprecated))
16804 as_warn (_("conditional infixes are deprecated in unified syntax"));
16806 inst.cond = cond->value;
16813 /* This function generates an initial IT instruction, leaving its block
16814 virtually open for the new instructions. Eventually,
16815 the mask will be updated by now_it_add_mask () each time
16816 a new instruction needs to be included in the IT block.
16817 Finally, the block is closed with close_automatic_it_block ().
16818 The block closure can be requested either from md_assemble (),
16819 a tencode (), or due to a label hook. */
16822 new_automatic_it_block (int cond)
16824 now_it.state = AUTOMATIC_IT_BLOCK;
16825 now_it.mask = 0x18;
16827 now_it.block_length = 1;
16828 mapping_state (MAP_THUMB);
16829 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16830 now_it.warn_deprecated = FALSE;
16831 now_it.insn_cond = TRUE;
16834 /* Close an automatic IT block.
16835 See comments in new_automatic_it_block (). */
16838 close_automatic_it_block (void)
16840 now_it.mask = 0x10;
16841 now_it.block_length = 0;
16844 /* Update the mask of the current automatically-generated IT
16845 instruction. See comments in new_automatic_it_block (). */
16848 now_it_add_mask (int cond)
16850 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16851 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16852 | ((bitvalue) << (nbit)))
16853 const int resulting_bit = (cond & 1);
16855 now_it.mask &= 0xf;
16856 now_it.mask = SET_BIT_VALUE (now_it.mask,
16858 (5 - now_it.block_length));
16859 now_it.mask = SET_BIT_VALUE (now_it.mask,
16861 ((5 - now_it.block_length) - 1) );
16862 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16865 #undef SET_BIT_VALUE
16868 /* The IT blocks handling machinery is accessed through the these functions:
16869 it_fsm_pre_encode () from md_assemble ()
16870 set_it_insn_type () optional, from the tencode functions
16871 set_it_insn_type_last () ditto
16872 in_it_block () ditto
16873 it_fsm_post_encode () from md_assemble ()
16874 force_automatic_it_block_close () from label habdling functions
16877 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16878 initializing the IT insn type with a generic initial value depending
16879 on the inst.condition.
16880 2) During the tencode function, two things may happen:
16881 a) The tencode function overrides the IT insn type by
16882 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16883 b) The tencode function queries the IT block state by
16884 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16886 Both set_it_insn_type and in_it_block run the internal FSM state
16887 handling function (handle_it_state), because: a) setting the IT insn
16888 type may incur in an invalid state (exiting the function),
16889 and b) querying the state requires the FSM to be updated.
16890 Specifically we want to avoid creating an IT block for conditional
16891 branches, so it_fsm_pre_encode is actually a guess and we can't
16892 determine whether an IT block is required until the tencode () routine
16893 has decided what type of instruction this actually it.
16894 Because of this, if set_it_insn_type and in_it_block have to be used,
16895 set_it_insn_type has to be called first.
16897 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16898 determines the insn IT type depending on the inst.cond code.
16899 When a tencode () routine encodes an instruction that can be
16900 either outside an IT block, or, in the case of being inside, has to be
16901 the last one, set_it_insn_type_last () will determine the proper
16902 IT instruction type based on the inst.cond code. Otherwise,
16903 set_it_insn_type can be called for overriding that logic or
16904 for covering other cases.
16906 Calling handle_it_state () may not transition the IT block state to
16907 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16908 still queried. Instead, if the FSM determines that the state should
16909 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16910 after the tencode () function: that's what it_fsm_post_encode () does.
16912 Since in_it_block () calls the state handling function to get an
16913 updated state, an error may occur (due to invalid insns combination).
16914 In that case, inst.error is set.
16915 Therefore, inst.error has to be checked after the execution of
16916 the tencode () routine.
16918 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16919 any pending state change (if any) that didn't take place in
16920 handle_it_state () as explained above. */
16923 it_fsm_pre_encode (void)
16925 if (inst.cond != COND_ALWAYS)
16926 inst.it_insn_type = INSIDE_IT_INSN;
16928 inst.it_insn_type = OUTSIDE_IT_INSN;
16930 now_it.state_handled = 0;
16933 /* IT state FSM handling function. */
16936 handle_it_state (void)
16938 now_it.state_handled = 1;
16939 now_it.insn_cond = FALSE;
16941 switch (now_it.state)
16943 case OUTSIDE_IT_BLOCK:
16944 switch (inst.it_insn_type)
16946 case OUTSIDE_IT_INSN:
16949 case INSIDE_IT_INSN:
16950 case INSIDE_IT_LAST_INSN:
16951 if (thumb_mode == 0)
16954 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16955 as_tsktsk (_("Warning: conditional outside an IT block"\
16960 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16961 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16963 /* Automatically generate the IT instruction. */
16964 new_automatic_it_block (inst.cond);
16965 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16966 close_automatic_it_block ();
16970 inst.error = BAD_OUT_IT;
16976 case IF_INSIDE_IT_LAST_INSN:
16977 case NEUTRAL_IT_INSN:
16981 now_it.state = MANUAL_IT_BLOCK;
16982 now_it.block_length = 0;
16987 case AUTOMATIC_IT_BLOCK:
16988 /* Three things may happen now:
16989 a) We should increment current it block size;
16990 b) We should close current it block (closing insn or 4 insns);
16991 c) We should close current it block and start a new one (due
16992 to incompatible conditions or
16993 4 insns-length block reached). */
16995 switch (inst.it_insn_type)
16997 case OUTSIDE_IT_INSN:
16998 /* The closure of the block shall happen immediatelly,
16999 so any in_it_block () call reports the block as closed. */
17000 force_automatic_it_block_close ();
17003 case INSIDE_IT_INSN:
17004 case INSIDE_IT_LAST_INSN:
17005 case IF_INSIDE_IT_LAST_INSN:
17006 now_it.block_length++;
17008 if (now_it.block_length > 4
17009 || !now_it_compatible (inst.cond))
17011 force_automatic_it_block_close ();
17012 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17013 new_automatic_it_block (inst.cond);
17017 now_it.insn_cond = TRUE;
17018 now_it_add_mask (inst.cond);
17021 if (now_it.state == AUTOMATIC_IT_BLOCK
17022 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17023 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17024 close_automatic_it_block ();
17027 case NEUTRAL_IT_INSN:
17028 now_it.block_length++;
17029 now_it.insn_cond = TRUE;
17031 if (now_it.block_length > 4)
17032 force_automatic_it_block_close ();
17034 now_it_add_mask (now_it.cc & 1);
17038 close_automatic_it_block ();
17039 now_it.state = MANUAL_IT_BLOCK;
17044 case MANUAL_IT_BLOCK:
17046 /* Check conditional suffixes. */
17047 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17050 now_it.mask &= 0x1f;
17051 is_last = (now_it.mask == 0x10);
17052 now_it.insn_cond = TRUE;
17054 switch (inst.it_insn_type)
17056 case OUTSIDE_IT_INSN:
17057 inst.error = BAD_NOT_IT;
17060 case INSIDE_IT_INSN:
17061 if (cond != inst.cond)
17063 inst.error = BAD_IT_COND;
17068 case INSIDE_IT_LAST_INSN:
17069 case IF_INSIDE_IT_LAST_INSN:
17070 if (cond != inst.cond)
17072 inst.error = BAD_IT_COND;
17077 inst.error = BAD_BRANCH;
17082 case NEUTRAL_IT_INSN:
17083 /* The BKPT instruction is unconditional even in an IT block. */
17087 inst.error = BAD_IT_IT;
17097 struct depr_insn_mask
17099 unsigned long pattern;
17100 unsigned long mask;
17101 const char* description;
17104 /* List of 16-bit instruction patterns deprecated in an IT block in
17106 static const struct depr_insn_mask depr_it_insns[] = {
17107 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17108 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17109 { 0xa000, 0xb800, N_("ADR") },
17110 { 0x4800, 0xf800, N_("Literal loads") },
17111 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17112 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17117 it_fsm_post_encode (void)
17121 if (!now_it.state_handled)
17122 handle_it_state ();
17124 if (now_it.insn_cond
17125 && !now_it.warn_deprecated
17126 && warn_on_deprecated
17127 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17129 if (inst.instruction >= 0x10000)
17131 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17132 "deprecated in ARMv8"));
17133 now_it.warn_deprecated = TRUE;
17137 const struct depr_insn_mask *p = depr_it_insns;
17139 while (p->mask != 0)
17141 if ((inst.instruction & p->mask) == p->pattern)
17143 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17144 "of the following class are deprecated in ARMv8: "
17145 "%s"), p->description);
17146 now_it.warn_deprecated = TRUE;
17154 if (now_it.block_length > 1)
17156 as_warn (_("IT blocks containing more than one conditional "
17157 "instruction are deprecated in ARMv8"));
17158 now_it.warn_deprecated = TRUE;
17162 is_last = (now_it.mask == 0x10);
17165 now_it.state = OUTSIDE_IT_BLOCK;
17171 force_automatic_it_block_close (void)
17173 if (now_it.state == AUTOMATIC_IT_BLOCK)
17175 close_automatic_it_block ();
17176 now_it.state = OUTSIDE_IT_BLOCK;
17184 if (!now_it.state_handled)
17185 handle_it_state ();
17187 return now_it.state != OUTSIDE_IT_BLOCK;
17191 md_assemble (char *str)
17194 const struct asm_opcode * opcode;
17196 /* Align the previous label if needed. */
17197 if (last_label_seen != NULL)
17199 symbol_set_frag (last_label_seen, frag_now);
17200 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17201 S_SET_SEGMENT (last_label_seen, now_seg);
17204 memset (&inst, '\0', sizeof (inst));
17205 inst.reloc.type = BFD_RELOC_UNUSED;
17207 opcode = opcode_lookup (&p);
17210 /* It wasn't an instruction, but it might be a register alias of
17211 the form alias .req reg, or a Neon .dn/.qn directive. */
17212 if (! create_register_alias (str, p)
17213 && ! create_neon_reg_alias (str, p))
17214 as_bad (_("bad instruction `%s'"), str);
17219 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17220 as_warn (_("s suffix on comparison instruction is deprecated"));
17222 /* The value which unconditional instructions should have in place of the
17223 condition field. */
17224 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17228 arm_feature_set variant;
17230 variant = cpu_variant;
17231 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17232 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17233 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17234 /* Check that this instruction is supported for this CPU. */
17235 if (!opcode->tvariant
17236 || (thumb_mode == 1
17237 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17239 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17242 if (inst.cond != COND_ALWAYS && !unified_syntax
17243 && opcode->tencode != do_t_branch)
17245 as_bad (_("Thumb does not support conditional execution"));
17249 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17251 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17252 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17253 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17255 /* Two things are addressed here.
17256 1) Implicit require narrow instructions on Thumb-1.
17257 This avoids relaxation accidentally introducing Thumb-2
17259 2) Reject wide instructions in non Thumb-2 cores. */
17260 if (inst.size_req == 0)
17262 else if (inst.size_req == 4)
17264 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17270 inst.instruction = opcode->tvalue;
17272 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17274 /* Prepare the it_insn_type for those encodings that don't set
17276 it_fsm_pre_encode ();
17278 opcode->tencode ();
17280 it_fsm_post_encode ();
17283 if (!(inst.error || inst.relax))
17285 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17286 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17287 if (inst.size_req && inst.size_req != inst.size)
17289 as_bad (_("cannot honor width suffix -- `%s'"), str);
17294 /* Something has gone badly wrong if we try to relax a fixed size
17296 gas_assert (inst.size_req == 0 || !inst.relax);
17298 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17299 *opcode->tvariant);
17300 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17301 set those bits when Thumb-2 32-bit instructions are seen. ie.
17302 anything other than bl/blx and v6-M instructions.
17303 This is overly pessimistic for relaxable instructions. */
17304 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17306 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17307 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17308 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17311 check_neon_suffixes;
17315 mapping_state (MAP_THUMB);
17318 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17322 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17323 is_bx = (opcode->aencode == do_bx);
17325 /* Check that this instruction is supported for this CPU. */
17326 if (!(is_bx && fix_v4bx)
17327 && !(opcode->avariant &&
17328 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17330 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17335 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17339 inst.instruction = opcode->avalue;
17340 if (opcode->tag == OT_unconditionalF)
17341 inst.instruction |= 0xF << 28;
17343 inst.instruction |= inst.cond << 28;
17344 inst.size = INSN_SIZE;
17345 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17347 it_fsm_pre_encode ();
17348 opcode->aencode ();
17349 it_fsm_post_encode ();
17351 /* Arm mode bx is marked as both v4T and v5 because it's still required
17352 on a hypothetical non-thumb v5 core. */
17354 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17356 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17357 *opcode->avariant);
17359 check_neon_suffixes;
17363 mapping_state (MAP_ARM);
17368 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17376 check_it_blocks_finished (void)
17381 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17382 if (seg_info (sect)->tc_segment_info_data.current_it.state
17383 == MANUAL_IT_BLOCK)
17385 as_warn (_("section '%s' finished with an open IT block."),
17389 if (now_it.state == MANUAL_IT_BLOCK)
17390 as_warn (_("file finished with an open IT block."));
17394 /* Various frobbings of labels and their addresses. */
17397 arm_start_line_hook (void)
17399 last_label_seen = NULL;
17403 arm_frob_label (symbolS * sym)
17405 last_label_seen = sym;
17407 ARM_SET_THUMB (sym, thumb_mode);
17409 #if defined OBJ_COFF || defined OBJ_ELF
17410 ARM_SET_INTERWORK (sym, support_interwork);
17413 force_automatic_it_block_close ();
17415 /* Note - do not allow local symbols (.Lxxx) to be labelled
17416 as Thumb functions. This is because these labels, whilst
17417 they exist inside Thumb code, are not the entry points for
17418 possible ARM->Thumb calls. Also, these labels can be used
17419 as part of a computed goto or switch statement. eg gcc
17420 can generate code that looks like this:
17422 ldr r2, [pc, .Laaa]
17432 The first instruction loads the address of the jump table.
17433 The second instruction converts a table index into a byte offset.
17434 The third instruction gets the jump address out of the table.
17435 The fourth instruction performs the jump.
17437 If the address stored at .Laaa is that of a symbol which has the
17438 Thumb_Func bit set, then the linker will arrange for this address
17439 to have the bottom bit set, which in turn would mean that the
17440 address computation performed by the third instruction would end
17441 up with the bottom bit set. Since the ARM is capable of unaligned
17442 word loads, the instruction would then load the incorrect address
17443 out of the jump table, and chaos would ensue. */
17444 if (label_is_thumb_function_name
17445 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17446 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17448 /* When the address of a Thumb function is taken the bottom
17449 bit of that address should be set. This will allow
17450 interworking between Arm and Thumb functions to work
17453 THUMB_SET_FUNC (sym, 1);
17455 label_is_thumb_function_name = FALSE;
17458 dwarf2_emit_label (sym);
17462 arm_data_in_code (void)
17464 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17466 *input_line_pointer = '/';
17467 input_line_pointer += 5;
17468 *input_line_pointer = 0;
17476 arm_canonicalize_symbol_name (char * name)
17480 if (thumb_mode && (len = strlen (name)) > 5
17481 && streq (name + len - 5, "/data"))
17482 *(name + len - 5) = 0;
17487 /* Table of all register names defined by default. The user can
17488 define additional names with .req. Note that all register names
17489 should appear in both upper and lowercase variants. Some registers
17490 also have mixed-case names. */
17492 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17493 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17494 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17495 #define REGSET(p,t) \
17496 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17497 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17498 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17499 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17500 #define REGSETH(p,t) \
17501 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17502 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17503 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17504 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17505 #define REGSET2(p,t) \
17506 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17507 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17508 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17509 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17510 #define SPLRBANK(base,bank,t) \
17511 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17512 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17513 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17514 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17515 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17516 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17518 static const struct reg_entry reg_names[] =
17520 /* ARM integer registers. */
17521 REGSET(r, RN), REGSET(R, RN),
17523 /* ATPCS synonyms. */
17524 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17525 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17526 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17528 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17529 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17530 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17532 /* Well-known aliases. */
17533 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17534 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17536 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17537 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17539 /* Coprocessor numbers. */
17540 REGSET(p, CP), REGSET(P, CP),
17542 /* Coprocessor register numbers. The "cr" variants are for backward
17544 REGSET(c, CN), REGSET(C, CN),
17545 REGSET(cr, CN), REGSET(CR, CN),
17547 /* ARM banked registers. */
17548 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17549 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17550 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17551 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17552 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17553 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17554 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17556 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17557 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17558 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17559 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17560 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17561 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17562 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17563 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17565 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17566 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17567 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17568 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17569 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17570 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17571 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17572 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17573 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17575 /* FPA registers. */
17576 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17577 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17579 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17580 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17582 /* VFP SP registers. */
17583 REGSET(s,VFS), REGSET(S,VFS),
17584 REGSETH(s,VFS), REGSETH(S,VFS),
17586 /* VFP DP Registers. */
17587 REGSET(d,VFD), REGSET(D,VFD),
17588 /* Extra Neon DP registers. */
17589 REGSETH(d,VFD), REGSETH(D,VFD),
17591 /* Neon QP registers. */
17592 REGSET2(q,NQ), REGSET2(Q,NQ),
17594 /* VFP control registers. */
17595 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17596 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17597 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17598 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17599 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17600 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17602 /* Maverick DSP coprocessor registers. */
17603 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17604 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17606 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17607 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17608 REGDEF(dspsc,0,DSPSC),
17610 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17611 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17612 REGDEF(DSPSC,0,DSPSC),
17614 /* iWMMXt data registers - p0, c0-15. */
17615 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17617 /* iWMMXt control registers - p1, c0-3. */
17618 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17619 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17620 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17621 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17623 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17624 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17625 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17626 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17627 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17629 /* XScale accumulator registers. */
17630 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17636 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17637 within psr_required_here. */
17638 static const struct asm_psr psrs[] =
17640 /* Backward compatibility notation. Note that "all" is no longer
17641 truly all possible PSR bits. */
17642 {"all", PSR_c | PSR_f},
17646 /* Individual flags. */
17652 /* Combinations of flags. */
17653 {"fs", PSR_f | PSR_s},
17654 {"fx", PSR_f | PSR_x},
17655 {"fc", PSR_f | PSR_c},
17656 {"sf", PSR_s | PSR_f},
17657 {"sx", PSR_s | PSR_x},
17658 {"sc", PSR_s | PSR_c},
17659 {"xf", PSR_x | PSR_f},
17660 {"xs", PSR_x | PSR_s},
17661 {"xc", PSR_x | PSR_c},
17662 {"cf", PSR_c | PSR_f},
17663 {"cs", PSR_c | PSR_s},
17664 {"cx", PSR_c | PSR_x},
17665 {"fsx", PSR_f | PSR_s | PSR_x},
17666 {"fsc", PSR_f | PSR_s | PSR_c},
17667 {"fxs", PSR_f | PSR_x | PSR_s},
17668 {"fxc", PSR_f | PSR_x | PSR_c},
17669 {"fcs", PSR_f | PSR_c | PSR_s},
17670 {"fcx", PSR_f | PSR_c | PSR_x},
17671 {"sfx", PSR_s | PSR_f | PSR_x},
17672 {"sfc", PSR_s | PSR_f | PSR_c},
17673 {"sxf", PSR_s | PSR_x | PSR_f},
17674 {"sxc", PSR_s | PSR_x | PSR_c},
17675 {"scf", PSR_s | PSR_c | PSR_f},
17676 {"scx", PSR_s | PSR_c | PSR_x},
17677 {"xfs", PSR_x | PSR_f | PSR_s},
17678 {"xfc", PSR_x | PSR_f | PSR_c},
17679 {"xsf", PSR_x | PSR_s | PSR_f},
17680 {"xsc", PSR_x | PSR_s | PSR_c},
17681 {"xcf", PSR_x | PSR_c | PSR_f},
17682 {"xcs", PSR_x | PSR_c | PSR_s},
17683 {"cfs", PSR_c | PSR_f | PSR_s},
17684 {"cfx", PSR_c | PSR_f | PSR_x},
17685 {"csf", PSR_c | PSR_s | PSR_f},
17686 {"csx", PSR_c | PSR_s | PSR_x},
17687 {"cxf", PSR_c | PSR_x | PSR_f},
17688 {"cxs", PSR_c | PSR_x | PSR_s},
17689 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17690 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17691 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17692 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17693 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17694 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17695 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17696 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17697 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17698 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17699 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17700 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17701 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17702 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17703 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17704 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17705 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17706 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17707 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17708 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17709 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17710 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17711 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17712 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17715 /* Table of V7M psr names. */
17716 static const struct asm_psr v7m_psrs[] =
17718 {"apsr", 0 }, {"APSR", 0 },
17719 {"iapsr", 1 }, {"IAPSR", 1 },
17720 {"eapsr", 2 }, {"EAPSR", 2 },
17721 {"psr", 3 }, {"PSR", 3 },
17722 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17723 {"ipsr", 5 }, {"IPSR", 5 },
17724 {"epsr", 6 }, {"EPSR", 6 },
17725 {"iepsr", 7 }, {"IEPSR", 7 },
17726 {"msp", 8 }, {"MSP", 8 },
17727 {"psp", 9 }, {"PSP", 9 },
17728 {"primask", 16}, {"PRIMASK", 16},
17729 {"basepri", 17}, {"BASEPRI", 17},
17730 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17731 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17732 {"faultmask", 19}, {"FAULTMASK", 19},
17733 {"control", 20}, {"CONTROL", 20}
17736 /* Table of all shift-in-operand names. */
17737 static const struct asm_shift_name shift_names [] =
17739 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17740 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17741 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17742 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17743 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17744 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17747 /* Table of all explicit relocation names. */
17749 static struct reloc_entry reloc_names[] =
17751 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17752 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17753 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17754 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17755 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17756 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17757 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17758 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17759 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17760 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17761 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17762 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17763 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17764 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17765 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17766 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17767 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17768 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17772 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17773 static const struct asm_cond conds[] =
17777 {"cs", 0x2}, {"hs", 0x2},
17778 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17792 #define UL_BARRIER(L,U,CODE,FEAT) \
17793 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17794 { U, CODE, ARM_FEATURE (FEAT, 0) }
17796 static struct asm_barrier_opt barrier_opt_names[] =
17798 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17799 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17800 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17801 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17802 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17803 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17804 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17805 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17806 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17807 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17808 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17809 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17810 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17811 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17812 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17813 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17818 /* Table of ARM-format instructions. */
17820 /* Macros for gluing together operand strings. N.B. In all cases
17821 other than OPS0, the trailing OP_stop comes from default
17822 zero-initialization of the unspecified elements of the array. */
17823 #define OPS0() { OP_stop, }
17824 #define OPS1(a) { OP_##a, }
17825 #define OPS2(a,b) { OP_##a,OP_##b, }
17826 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17827 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17828 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17829 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17831 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17832 This is useful when mixing operands for ARM and THUMB, i.e. using the
17833 MIX_ARM_THUMB_OPERANDS macro.
17834 In order to use these macros, prefix the number of operands with _
17836 #define OPS_1(a) { a, }
17837 #define OPS_2(a,b) { a,b, }
17838 #define OPS_3(a,b,c) { a,b,c, }
17839 #define OPS_4(a,b,c,d) { a,b,c,d, }
17840 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17841 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17843 /* These macros abstract out the exact format of the mnemonic table and
17844 save some repeated characters. */
17846 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17847 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17848 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17849 THUMB_VARIANT, do_##ae, do_##te }
17851 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17852 a T_MNEM_xyz enumerator. */
17853 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17854 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17855 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17856 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17858 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17859 infix after the third character. */
17860 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17861 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17862 THUMB_VARIANT, do_##ae, do_##te }
17863 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17864 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17865 THUMB_VARIANT, do_##ae, do_##te }
17866 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17867 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17868 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17869 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17870 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17871 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17872 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17873 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17875 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17876 field is still 0xE. Many of the Thumb variants can be executed
17877 conditionally, so this is checked separately. */
17878 #define TUE(mnem, op, top, nops, ops, ae, te) \
17879 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17880 THUMB_VARIANT, do_##ae, do_##te }
17882 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17883 Used by mnemonics that have very minimal differences in the encoding for
17884 ARM and Thumb variants and can be handled in a common function. */
17885 #define TUEc(mnem, op, top, nops, ops, en) \
17886 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17887 THUMB_VARIANT, do_##en, do_##en }
17889 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17890 condition code field. */
17891 #define TUF(mnem, op, top, nops, ops, ae, te) \
17892 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17893 THUMB_VARIANT, do_##ae, do_##te }
17895 /* ARM-only variants of all the above. */
17896 #define CE(mnem, op, nops, ops, ae) \
17897 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17899 #define C3(mnem, op, nops, ops, ae) \
17900 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17902 /* Legacy mnemonics that always have conditional infix after the third
17904 #define CL(mnem, op, nops, ops, ae) \
17905 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17906 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17908 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17909 #define cCE(mnem, op, nops, ops, ae) \
17910 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17912 /* Legacy coprocessor instructions where conditional infix and conditional
17913 suffix are ambiguous. For consistency this includes all FPA instructions,
17914 not just the potentially ambiguous ones. */
17915 #define cCL(mnem, op, nops, ops, ae) \
17916 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17917 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17919 /* Coprocessor, takes either a suffix or a position-3 infix
17920 (for an FPA corner case). */
17921 #define C3E(mnem, op, nops, ops, ae) \
17922 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17923 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17925 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17926 { m1 #m2 m3, OPS##nops ops, \
17927 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17928 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17930 #define CM(m1, m2, op, nops, ops, ae) \
17931 xCM_ (m1, , m2, op, nops, ops, ae), \
17932 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17933 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17934 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17935 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17936 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17937 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17938 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17939 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17940 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17941 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17942 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17943 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17944 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17945 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17946 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17947 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17948 xCM_ (m1, le, m2, op, nops, ops, ae), \
17949 xCM_ (m1, al, m2, op, nops, ops, ae)
17951 #define UE(mnem, op, nops, ops, ae) \
17952 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17954 #define UF(mnem, op, nops, ops, ae) \
17955 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17957 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17958 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17959 use the same encoding function for each. */
17960 #define NUF(mnem, op, nops, ops, enc) \
17961 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17962 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17964 /* Neon data processing, version which indirects through neon_enc_tab for
17965 the various overloaded versions of opcodes. */
17966 #define nUF(mnem, op, nops, ops, enc) \
17967 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17968 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17970 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17972 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17973 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17974 THUMB_VARIANT, do_##enc, do_##enc }
17976 #define NCE(mnem, op, nops, ops, enc) \
17977 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17979 #define NCEF(mnem, op, nops, ops, enc) \
17980 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17982 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17983 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17984 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17985 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17987 #define nCE(mnem, op, nops, ops, enc) \
17988 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17990 #define nCEF(mnem, op, nops, ops, enc) \
17991 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17995 static const struct asm_opcode insns[] =
17997 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
17998 #define THUMB_VARIANT & arm_ext_v4t
17999 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18000 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18001 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18002 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18003 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18004 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18005 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18006 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18007 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18008 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18009 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18010 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18011 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18012 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18013 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18014 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
18016 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18017 for setting PSR flag bits. They are obsolete in V6 and do not
18018 have Thumb equivalents. */
18019 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18020 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18021 CL("tstp", 110f000, 2, (RR, SH), cmp),
18022 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18023 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18024 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18025 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18026 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18027 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18029 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18030 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18031 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18032 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18034 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18035 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18036 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18038 OP_ADDRGLDR),ldst, t_ldst),
18039 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18041 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18042 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18043 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18044 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18045 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18046 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18048 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18049 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18050 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18051 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18054 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18055 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18056 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18057 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
18059 /* Thumb-compatibility pseudo ops. */
18060 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18061 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18062 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18063 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18064 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18065 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18066 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18067 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18068 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18069 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18070 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18071 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18073 /* These may simplify to neg. */
18074 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18075 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18077 #undef THUMB_VARIANT
18078 #define THUMB_VARIANT & arm_ext_v6
18080 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18082 /* V1 instructions with no Thumb analogue prior to V6T2. */
18083 #undef THUMB_VARIANT
18084 #define THUMB_VARIANT & arm_ext_v6t2
18086 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18087 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18088 CL("teqp", 130f000, 2, (RR, SH), cmp),
18090 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18091 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18092 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18093 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18095 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18096 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18098 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18099 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18101 /* V1 instructions with no Thumb analogue at all. */
18102 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18103 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18105 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18106 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18107 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18108 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18109 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18110 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18111 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18112 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18115 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18116 #undef THUMB_VARIANT
18117 #define THUMB_VARIANT & arm_ext_v4t
18119 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18120 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18122 #undef THUMB_VARIANT
18123 #define THUMB_VARIANT & arm_ext_v6t2
18125 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18126 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18128 /* Generic coprocessor instructions. */
18129 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18130 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18131 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18132 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18133 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18134 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18135 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18138 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18140 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18141 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18144 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18145 #undef THUMB_VARIANT
18146 #define THUMB_VARIANT & arm_ext_msr
18148 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18149 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18152 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18153 #undef THUMB_VARIANT
18154 #define THUMB_VARIANT & arm_ext_v6t2
18156 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18157 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18158 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18159 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18160 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18161 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18162 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18163 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18166 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18167 #undef THUMB_VARIANT
18168 #define THUMB_VARIANT & arm_ext_v4t
18170 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18171 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18172 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18173 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18174 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18175 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18178 #define ARM_VARIANT & arm_ext_v4t_5
18180 /* ARM Architecture 4T. */
18181 /* Note: bx (and blx) are required on V5, even if the processor does
18182 not support Thumb. */
18183 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18186 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18187 #undef THUMB_VARIANT
18188 #define THUMB_VARIANT & arm_ext_v5t
18190 /* Note: blx has 2 variants; the .value coded here is for
18191 BLX(2). Only this variant has conditional execution. */
18192 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18193 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18195 #undef THUMB_VARIANT
18196 #define THUMB_VARIANT & arm_ext_v6t2
18198 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18199 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18200 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18201 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18202 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18203 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18204 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18205 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18208 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18209 #undef THUMB_VARIANT
18210 #define THUMB_VARIANT & arm_ext_v5exp
18212 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18213 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18214 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18215 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18217 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18218 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18220 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18221 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18222 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18223 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18225 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18226 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18227 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18228 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18230 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18231 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18233 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18234 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18235 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18236 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18239 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18240 #undef THUMB_VARIANT
18241 #define THUMB_VARIANT & arm_ext_v6t2
18243 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18244 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18246 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18247 ADDRGLDRS), ldrd, t_ldstd),
18249 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18250 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18253 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18255 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18258 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18259 #undef THUMB_VARIANT
18260 #define THUMB_VARIANT & arm_ext_v6
18262 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18263 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18264 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18265 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18266 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18267 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18268 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18269 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18270 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18271 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18273 #undef THUMB_VARIANT
18274 #define THUMB_VARIANT & arm_ext_v6t2
18276 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18277 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18279 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18280 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18282 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18283 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18285 /* ARM V6 not included in V7M. */
18286 #undef THUMB_VARIANT
18287 #define THUMB_VARIANT & arm_ext_v6_notm
18288 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18289 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18290 UF(rfeib, 9900a00, 1, (RRw), rfe),
18291 UF(rfeda, 8100a00, 1, (RRw), rfe),
18292 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18293 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18294 UF(rfefa, 8100a00, 1, (RRw), rfe),
18295 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18296 UF(rfeed, 9900a00, 1, (RRw), rfe),
18297 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18298 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18299 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18300 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18301 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18302 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18303 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18304 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18305 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18307 /* ARM V6 not included in V7M (eg. integer SIMD). */
18308 #undef THUMB_VARIANT
18309 #define THUMB_VARIANT & arm_ext_v6_dsp
18310 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18311 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18312 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18313 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18314 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18315 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18316 /* Old name for QASX. */
18317 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18318 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 /* Old name for QSAX. */
18320 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18321 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18324 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18326 /* Old name for SASX. */
18327 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18328 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18330 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18331 /* Old name for SHASX. */
18332 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18333 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 /* Old name for SHSAX. */
18335 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18336 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18337 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18338 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18339 /* Old name for SSAX. */
18340 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18341 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18342 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18343 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18344 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18345 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18346 /* Old name for UASX. */
18347 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18348 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18349 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18350 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18351 /* Old name for UHASX. */
18352 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18353 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18354 /* Old name for UHSAX. */
18355 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18356 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18357 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18358 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18359 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18360 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18361 /* Old name for UQASX. */
18362 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18363 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18364 /* Old name for UQSAX. */
18365 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18366 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18367 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18368 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18369 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18370 /* Old name for USAX. */
18371 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18372 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18373 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18374 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18375 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18376 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18377 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18378 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18379 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18380 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18381 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18382 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18383 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18384 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18385 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18386 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18387 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18388 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18389 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18390 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18391 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18392 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18393 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18394 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18395 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18396 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18397 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18398 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18399 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18400 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18401 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18402 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18403 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18404 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18407 #define ARM_VARIANT & arm_ext_v6k
18408 #undef THUMB_VARIANT
18409 #define THUMB_VARIANT & arm_ext_v6k
18411 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18412 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18413 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18414 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18416 #undef THUMB_VARIANT
18417 #define THUMB_VARIANT & arm_ext_v6_notm
18418 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18420 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18421 RRnpcb), strexd, t_strexd),
18423 #undef THUMB_VARIANT
18424 #define THUMB_VARIANT & arm_ext_v6t2
18425 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18427 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18429 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18431 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18433 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18436 #define ARM_VARIANT & arm_ext_sec
18437 #undef THUMB_VARIANT
18438 #define THUMB_VARIANT & arm_ext_sec
18440 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18443 #define ARM_VARIANT & arm_ext_virt
18444 #undef THUMB_VARIANT
18445 #define THUMB_VARIANT & arm_ext_virt
18447 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18448 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18451 #define ARM_VARIANT & arm_ext_v6t2
18452 #undef THUMB_VARIANT
18453 #define THUMB_VARIANT & arm_ext_v6t2
18455 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18456 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18457 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18458 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18460 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18461 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18462 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18463 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18465 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18466 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18467 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18468 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18470 /* Thumb-only instructions. */
18472 #define ARM_VARIANT NULL
18473 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18474 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18476 /* ARM does not really have an IT instruction, so always allow it.
18477 The opcode is copied from Thumb in order to allow warnings in
18478 -mimplicit-it=[never | arm] modes. */
18480 #define ARM_VARIANT & arm_ext_v1
18482 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18483 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18484 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18485 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18486 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18487 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18488 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18489 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18490 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18491 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18492 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18493 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18494 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18495 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18496 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18497 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18498 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18499 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18501 /* Thumb2 only instructions. */
18503 #define ARM_VARIANT NULL
18505 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18506 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18507 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18508 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18509 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18510 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18512 /* Hardware division instructions. */
18514 #define ARM_VARIANT & arm_ext_adiv
18515 #undef THUMB_VARIANT
18516 #define THUMB_VARIANT & arm_ext_div
18518 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18519 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18521 /* ARM V6M/V7 instructions. */
18523 #define ARM_VARIANT & arm_ext_barrier
18524 #undef THUMB_VARIANT
18525 #define THUMB_VARIANT & arm_ext_barrier
18527 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18528 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18529 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
18531 /* ARM V7 instructions. */
18533 #define ARM_VARIANT & arm_ext_v7
18534 #undef THUMB_VARIANT
18535 #define THUMB_VARIANT & arm_ext_v7
18537 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18538 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18541 #define ARM_VARIANT & arm_ext_mp
18542 #undef THUMB_VARIANT
18543 #define THUMB_VARIANT & arm_ext_mp
18545 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18547 /* AArchv8 instructions. */
18549 #define ARM_VARIANT & arm_ext_v8
18550 #undef THUMB_VARIANT
18551 #define THUMB_VARIANT & arm_ext_v8
18553 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18554 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18555 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18556 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18558 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18559 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18560 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18562 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18564 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18566 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18568 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18569 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18570 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18571 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18572 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18573 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18575 /* ARMv8 T32 only. */
18577 #define ARM_VARIANT NULL
18578 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18579 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18580 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18582 /* FP for ARMv8. */
18584 #define ARM_VARIANT & fpu_vfp_ext_armv8
18585 #undef THUMB_VARIANT
18586 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18588 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18589 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18590 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18591 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18592 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18593 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18594 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18595 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18596 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18597 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18598 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18599 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18600 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18601 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18602 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18603 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18604 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18606 /* Crypto v1 extensions. */
18608 #define ARM_VARIANT & fpu_crypto_ext_armv8
18609 #undef THUMB_VARIANT
18610 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18612 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18613 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18614 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18615 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18616 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18617 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18618 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18619 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18620 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18621 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18622 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18623 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18624 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18625 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18628 #define ARM_VARIANT & crc_ext_armv8
18629 #undef THUMB_VARIANT
18630 #define THUMB_VARIANT & crc_ext_armv8
18631 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18632 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18633 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18634 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18635 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18636 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18639 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18640 #undef THUMB_VARIANT
18641 #define THUMB_VARIANT NULL
18643 cCE("wfs", e200110, 1, (RR), rd),
18644 cCE("rfs", e300110, 1, (RR), rd),
18645 cCE("wfc", e400110, 1, (RR), rd),
18646 cCE("rfc", e500110, 1, (RR), rd),
18648 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18649 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18650 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18651 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18653 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18654 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18655 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18656 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18658 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18659 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18660 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18661 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18662 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18663 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18664 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18665 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18666 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18667 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18668 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18669 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18671 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18672 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18673 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18674 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18675 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18676 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18677 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18678 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18679 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18680 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18681 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18682 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18684 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18685 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18686 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18687 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18688 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18689 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18690 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18691 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18692 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18693 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18694 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18695 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18697 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18698 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18699 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18700 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18701 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18702 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18703 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18704 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18705 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18706 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18707 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18708 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18710 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18711 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18712 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18713 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18714 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18715 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18716 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18717 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18718 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18719 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18720 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18721 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18723 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18724 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18725 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18726 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18727 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18728 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18729 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18730 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18731 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18732 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18733 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18734 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18736 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18737 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18738 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18739 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18740 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18741 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18742 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18743 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18744 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18745 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18746 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18747 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18749 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18750 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18751 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18752 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18753 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18754 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18755 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18756 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18757 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18758 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18759 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18760 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18762 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18763 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18764 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18765 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18766 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18767 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18768 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18769 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18770 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18771 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18772 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18773 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18775 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18776 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18777 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18778 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18779 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18780 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18781 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18782 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18783 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18784 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18785 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18786 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18788 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18789 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18790 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18791 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18792 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18793 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18794 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18795 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18796 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18797 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18798 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18799 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18801 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18802 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18803 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18804 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18805 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18806 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18807 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18808 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18809 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18810 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18811 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18812 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18814 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18815 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18816 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18817 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18818 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18819 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18820 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18821 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18822 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18823 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18824 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18825 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18827 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18828 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18829 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18830 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18831 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18832 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18833 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18834 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18835 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18836 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18837 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18838 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18840 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18841 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18842 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18843 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18844 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18845 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18846 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18847 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18848 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18849 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18850 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18851 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18853 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18854 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18855 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18856 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18857 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18858 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18859 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18860 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18861 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18862 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18863 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18864 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18866 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18941 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18954 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18967 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18980 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18993 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18999 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19000 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19001 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19002 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19003 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19004 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19005 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19006 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19007 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19009 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19010 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19011 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19012 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19013 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19014 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19015 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19016 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19017 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19018 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19019 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19020 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19022 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19023 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19024 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19025 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19026 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19027 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19028 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19029 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19030 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19031 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19032 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19033 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19035 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19036 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19037 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19038 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19040 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19041 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19042 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19043 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19044 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19045 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19046 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19047 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19048 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19049 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19050 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19051 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19053 /* The implementation of the FIX instruction is broken on some
19054 assemblers, in that it accepts a precision specifier as well as a
19055 rounding specifier, despite the fact that this is meaningless.
19056 To be more compatible, we accept it as well, though of course it
19057 does not set any bits. */
19058 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19059 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19060 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19061 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19062 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19063 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19064 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19065 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19066 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19067 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19068 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19069 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19070 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19072 /* Instructions that were new with the real FPA, call them V2. */
19074 #define ARM_VARIANT & fpu_fpa_ext_v2
19076 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19077 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19078 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19079 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19080 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19081 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19084 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19086 /* Moves and type conversions. */
19087 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19088 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19089 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19090 cCE("fmstat", ef1fa10, 0, (), noargs),
19091 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19092 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19093 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19094 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19095 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19096 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19097 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19098 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19099 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19100 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19102 /* Memory operations. */
19103 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19104 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19105 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19106 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19107 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19108 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19109 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19110 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19111 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19112 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19113 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19114 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19115 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19116 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19117 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19118 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19119 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19120 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19122 /* Monadic operations. */
19123 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19124 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19125 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19127 /* Dyadic operations. */
19128 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19129 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19130 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19131 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19132 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19133 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19134 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19135 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19136 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19139 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19140 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19141 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19142 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19144 /* Double precision load/store are still present on single precision
19145 implementations. */
19146 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19147 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19148 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19149 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19150 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19151 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19152 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19153 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19154 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19155 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19158 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19160 /* Moves and type conversions. */
19161 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19162 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19163 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19164 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19165 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19166 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19167 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19168 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19169 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19170 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19171 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19172 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19173 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19175 /* Monadic operations. */
19176 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19177 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19178 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19180 /* Dyadic operations. */
19181 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19182 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19183 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19184 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19185 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19186 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19187 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19188 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19189 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19192 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19193 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19194 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19195 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19198 #define ARM_VARIANT & fpu_vfp_ext_v2
19200 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19201 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19202 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19203 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19205 /* Instructions which may belong to either the Neon or VFP instruction sets.
19206 Individual encoder functions perform additional architecture checks. */
19208 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19209 #undef THUMB_VARIANT
19210 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19212 /* These mnemonics are unique to VFP. */
19213 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19214 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19215 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19216 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19217 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19218 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19219 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19220 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19221 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19222 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19224 /* Mnemonics shared by Neon and VFP. */
19225 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19226 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19227 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19229 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19230 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19232 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19233 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19235 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19236 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19237 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19238 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19239 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19240 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19241 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19242 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19244 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19245 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19246 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19247 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19250 /* NOTE: All VMOV encoding is special-cased! */
19251 NCE(vmov, 0, 1, (VMOV), neon_mov),
19252 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19254 #undef THUMB_VARIANT
19255 #define THUMB_VARIANT & fpu_neon_ext_v1
19257 #define ARM_VARIANT & fpu_neon_ext_v1
19259 /* Data processing with three registers of the same length. */
19260 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19261 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19262 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19263 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19264 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19265 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19266 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19267 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19268 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19269 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19270 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19271 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19272 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19273 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19274 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19275 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19276 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19277 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19278 /* If not immediate, fall back to neon_dyadic_i64_su.
19279 shl_imm should accept I8 I16 I32 I64,
19280 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19281 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19282 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19283 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19284 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19285 /* Logic ops, types optional & ignored. */
19286 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19287 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19288 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19289 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19290 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19291 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19292 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19293 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19294 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19295 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19296 /* Bitfield ops, untyped. */
19297 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19298 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19299 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19300 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19301 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19302 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19303 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19304 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19305 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19306 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19307 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19308 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19309 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19310 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19311 back to neon_dyadic_if_su. */
19312 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19313 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19314 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19315 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19316 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19317 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19318 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19319 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19320 /* Comparison. Type I8 I16 I32 F32. */
19321 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19322 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19323 /* As above, D registers only. */
19324 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19325 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19326 /* Int and float variants, signedness unimportant. */
19327 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19328 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19329 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19330 /* Add/sub take types I8 I16 I32 I64 F32. */
19331 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19332 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19333 /* vtst takes sizes 8, 16, 32. */
19334 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19335 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19336 /* VMUL takes I8 I16 I32 F32 P8. */
19337 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19338 /* VQD{R}MULH takes S16 S32. */
19339 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19340 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19341 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19342 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19343 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19344 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19345 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19346 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19347 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19348 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19349 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19350 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19351 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19352 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19353 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19354 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19356 /* Two address, int/float. Types S8 S16 S32 F32. */
19357 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19358 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19360 /* Data processing with two registers and a shift amount. */
19361 /* Right shifts, and variants with rounding.
19362 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19363 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19364 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19365 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19366 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19367 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19368 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19369 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19370 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19371 /* Shift and insert. Sizes accepted 8 16 32 64. */
19372 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19373 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19374 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19375 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19376 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19377 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19378 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19379 /* Right shift immediate, saturating & narrowing, with rounding variants.
19380 Types accepted S16 S32 S64 U16 U32 U64. */
19381 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19382 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19383 /* As above, unsigned. Types accepted S16 S32 S64. */
19384 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19385 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19386 /* Right shift narrowing. Types accepted I16 I32 I64. */
19387 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19388 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19389 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19390 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19391 /* CVT with optional immediate for fixed-point variant. */
19392 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19394 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19395 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19397 /* Data processing, three registers of different lengths. */
19398 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19399 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19400 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19401 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19402 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19403 /* If not scalar, fall back to neon_dyadic_long.
19404 Vector types as above, scalar types S16 S32 U16 U32. */
19405 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19406 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19407 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19408 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19409 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19410 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19411 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19412 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19413 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19414 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19415 /* Saturating doubling multiplies. Types S16 S32. */
19416 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19417 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19418 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19419 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19420 S16 S32 U16 U32. */
19421 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19423 /* Extract. Size 8. */
19424 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19425 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19427 /* Two registers, miscellaneous. */
19428 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19429 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19430 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19431 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19432 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19433 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19434 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19435 /* Vector replicate. Sizes 8 16 32. */
19436 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19437 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19438 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19439 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19440 /* VMOVN. Types I16 I32 I64. */
19441 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19442 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19443 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19444 /* VQMOVUN. Types S16 S32 S64. */
19445 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19446 /* VZIP / VUZP. Sizes 8 16 32. */
19447 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19448 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19449 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19450 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19451 /* VQABS / VQNEG. Types S8 S16 S32. */
19452 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19453 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19454 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19455 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19456 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19457 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19458 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19459 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19460 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19461 /* Reciprocal estimates. Types U32 F32. */
19462 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19463 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19464 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19465 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19466 /* VCLS. Types S8 S16 S32. */
19467 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19468 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19469 /* VCLZ. Types I8 I16 I32. */
19470 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19471 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19472 /* VCNT. Size 8. */
19473 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19474 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19475 /* Two address, untyped. */
19476 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19477 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19478 /* VTRN. Sizes 8 16 32. */
19479 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19480 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19482 /* Table lookup. Size 8. */
19483 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19484 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19486 #undef THUMB_VARIANT
19487 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19489 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19491 /* Neon element/structure load/store. */
19492 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19493 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19494 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19495 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19496 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19497 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19498 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19499 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19504 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19505 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19506 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19507 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19508 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19509 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19510 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19511 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19512 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19513 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19515 #undef THUMB_VARIANT
19516 #define THUMB_VARIANT & fpu_vfp_ext_v3
19518 #define ARM_VARIANT & fpu_vfp_ext_v3
19520 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19521 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19522 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19523 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19524 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19525 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19526 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19527 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19528 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19531 #define ARM_VARIANT & fpu_vfp_ext_fma
19532 #undef THUMB_VARIANT
19533 #define THUMB_VARIANT & fpu_vfp_ext_fma
19534 /* Mnemonics shared by Neon and VFP. These are included in the
19535 VFP FMA variant; NEON and VFP FMA always includes the NEON
19536 FMA instructions. */
19537 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19538 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19539 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19540 the v form should always be used. */
19541 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19542 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19543 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19544 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19545 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19546 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19548 #undef THUMB_VARIANT
19550 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19552 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19553 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19554 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19555 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19556 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19557 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19558 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19559 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19562 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19564 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19565 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19566 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19567 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19568 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19569 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19570 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19571 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19572 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19573 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19574 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19575 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19576 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19577 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19578 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19579 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19580 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19581 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19582 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19583 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19584 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19585 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19586 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19587 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19588 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19589 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19590 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
19591 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
19592 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
19593 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19594 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19595 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19596 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19597 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19598 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19599 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19600 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19601 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19602 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19605 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19606 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19607 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19611 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19631 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19632 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19633 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19634 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19641 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19642 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19643 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19644 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19651 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19652 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19653 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19654 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19655 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19656 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19665 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19666 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19667 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19668 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19669 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19670 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19671 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19675 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19676 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19677 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19678 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19679 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19680 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19681 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19682 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19683 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19684 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19685 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19686 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19687 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19688 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19689 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19690 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19691 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19692 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19693 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19694 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19695 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19696 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19697 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19698 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19699 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19700 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19701 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19702 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19703 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19704 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19705 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19706 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19707 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19708 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19709 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19710 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19711 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19712 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19713 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19714 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19715 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19716 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19717 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19718 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19719 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19720 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19721 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19722 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19723 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19725 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19728 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19730 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19731 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19732 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19733 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19734 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19735 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19736 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19737 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19738 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19739 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19740 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19746 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19747 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19751 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19753 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19754 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19755 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19756 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19757 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19758 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19759 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19760 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19761 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19762 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19763 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19764 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19765 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19766 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19767 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19768 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19769 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19770 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19771 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19772 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19773 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19774 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19775 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19776 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19777 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19778 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19779 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19780 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19781 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19782 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19783 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19784 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19785 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19786 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19789 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19791 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19792 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19793 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19794 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19795 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19796 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19797 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19798 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19799 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19800 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19801 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19802 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19803 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19804 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19805 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
19806 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
19807 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
19808 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
19809 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
19810 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
19811 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
19812 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
19813 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
19814 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
19815 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19816 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19817 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19818 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19819 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19820 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
19821 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19822 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19823 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19824 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19825 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
19826 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
19827 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
19828 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
19829 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
19830 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
19831 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19832 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19833 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
19834 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
19835 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19836 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19837 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19838 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19839 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19840 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19841 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19842 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19843 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19844 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19845 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19846 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19847 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19848 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19849 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19850 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19851 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19852 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19853 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19854 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19855 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19856 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19857 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19858 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19859 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19860 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19861 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19862 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19863 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19864 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19865 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19866 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19869 #undef THUMB_VARIANT
19895 /* MD interface: bits in the object file. */
19897 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19898 for use in the a.out file, and stores them in the array pointed to by buf.
19899 This knows about the endian-ness of the target machine and does
19900 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19901 2 (short) and 4 (long) Floating numbers are put out as a series of
19902 LITTLENUMS (shorts, here at least). */
19905 md_number_to_chars (char * buf, valueT val, int n)
19907 if (target_big_endian)
19908 number_to_chars_bigendian (buf, val, n);
19910 number_to_chars_littleendian (buf, val, n);
19914 md_chars_to_number (char * buf, int n)
19917 unsigned char * where = (unsigned char *) buf;
19919 if (target_big_endian)
19924 result |= (*where++ & 255);
19932 result |= (where[n] & 255);
19939 /* MD interface: Sections. */
19941 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19942 that an rs_machine_dependent frag may reach. */
19945 arm_frag_max_var (fragS *fragp)
19947 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19948 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19950 Note that we generate relaxable instructions even for cases that don't
19951 really need it, like an immediate that's a trivial constant. So we're
19952 overestimating the instruction size for some of those cases. Rather
19953 than putting more intelligence here, it would probably be better to
19954 avoid generating a relaxation frag in the first place when it can be
19955 determined up front that a short instruction will suffice. */
19957 gas_assert (fragp->fr_type == rs_machine_dependent);
19961 /* Estimate the size of a frag before relaxing. Assume everything fits in
19965 md_estimate_size_before_relax (fragS * fragp,
19966 segT segtype ATTRIBUTE_UNUSED)
19972 /* Convert a machine dependent frag. */
19975 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19977 unsigned long insn;
19978 unsigned long old_op;
19986 buf = fragp->fr_literal + fragp->fr_fix;
19988 old_op = bfd_get_16(abfd, buf);
19989 if (fragp->fr_symbol)
19991 exp.X_op = O_symbol;
19992 exp.X_add_symbol = fragp->fr_symbol;
19996 exp.X_op = O_constant;
19998 exp.X_add_number = fragp->fr_offset;
19999 opcode = fragp->fr_subtype;
20002 case T_MNEM_ldr_pc:
20003 case T_MNEM_ldr_pc2:
20004 case T_MNEM_ldr_sp:
20005 case T_MNEM_str_sp:
20012 if (fragp->fr_var == 4)
20014 insn = THUMB_OP32 (opcode);
20015 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20017 insn |= (old_op & 0x700) << 4;
20021 insn |= (old_op & 7) << 12;
20022 insn |= (old_op & 0x38) << 13;
20024 insn |= 0x00000c00;
20025 put_thumb32_insn (buf, insn);
20026 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20030 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20032 pc_rel = (opcode == T_MNEM_ldr_pc2);
20035 if (fragp->fr_var == 4)
20037 insn = THUMB_OP32 (opcode);
20038 insn |= (old_op & 0xf0) << 4;
20039 put_thumb32_insn (buf, insn);
20040 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20044 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20045 exp.X_add_number -= 4;
20053 if (fragp->fr_var == 4)
20055 int r0off = (opcode == T_MNEM_mov
20056 || opcode == T_MNEM_movs) ? 0 : 8;
20057 insn = THUMB_OP32 (opcode);
20058 insn = (insn & 0xe1ffffff) | 0x10000000;
20059 insn |= (old_op & 0x700) << r0off;
20060 put_thumb32_insn (buf, insn);
20061 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20065 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20070 if (fragp->fr_var == 4)
20072 insn = THUMB_OP32(opcode);
20073 put_thumb32_insn (buf, insn);
20074 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20077 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20081 if (fragp->fr_var == 4)
20083 insn = THUMB_OP32(opcode);
20084 insn |= (old_op & 0xf00) << 14;
20085 put_thumb32_insn (buf, insn);
20086 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20089 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20092 case T_MNEM_add_sp:
20093 case T_MNEM_add_pc:
20094 case T_MNEM_inc_sp:
20095 case T_MNEM_dec_sp:
20096 if (fragp->fr_var == 4)
20098 /* ??? Choose between add and addw. */
20099 insn = THUMB_OP32 (opcode);
20100 insn |= (old_op & 0xf0) << 4;
20101 put_thumb32_insn (buf, insn);
20102 if (opcode == T_MNEM_add_pc)
20103 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20105 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20108 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20116 if (fragp->fr_var == 4)
20118 insn = THUMB_OP32 (opcode);
20119 insn |= (old_op & 0xf0) << 4;
20120 insn |= (old_op & 0xf) << 16;
20121 put_thumb32_insn (buf, insn);
20122 if (insn & (1 << 20))
20123 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20125 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20128 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20134 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20135 (enum bfd_reloc_code_real) reloc_type);
20136 fixp->fx_file = fragp->fr_file;
20137 fixp->fx_line = fragp->fr_line;
20138 fragp->fr_fix += fragp->fr_var;
20141 /* Return the size of a relaxable immediate operand instruction.
20142 SHIFT and SIZE specify the form of the allowable immediate. */
20144 relax_immediate (fragS *fragp, int size, int shift)
20150 /* ??? Should be able to do better than this. */
20151 if (fragp->fr_symbol)
20154 low = (1 << shift) - 1;
20155 mask = (1 << (shift + size)) - (1 << shift);
20156 offset = fragp->fr_offset;
20157 /* Force misaligned offsets to 32-bit variant. */
20160 if (offset & ~mask)
20165 /* Get the address of a symbol during relaxation. */
20167 relaxed_symbol_addr (fragS *fragp, long stretch)
20173 sym = fragp->fr_symbol;
20174 sym_frag = symbol_get_frag (sym);
20175 know (S_GET_SEGMENT (sym) != absolute_section
20176 || sym_frag == &zero_address_frag);
20177 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20179 /* If frag has yet to be reached on this pass, assume it will
20180 move by STRETCH just as we did. If this is not so, it will
20181 be because some frag between grows, and that will force
20185 && sym_frag->relax_marker != fragp->relax_marker)
20189 /* Adjust stretch for any alignment frag. Note that if have
20190 been expanding the earlier code, the symbol may be
20191 defined in what appears to be an earlier frag. FIXME:
20192 This doesn't handle the fr_subtype field, which specifies
20193 a maximum number of bytes to skip when doing an
20195 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20197 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20200 stretch = - ((- stretch)
20201 & ~ ((1 << (int) f->fr_offset) - 1));
20203 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20215 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20218 relax_adr (fragS *fragp, asection *sec, long stretch)
20223 /* Assume worst case for symbols not known to be in the same section. */
20224 if (fragp->fr_symbol == NULL
20225 || !S_IS_DEFINED (fragp->fr_symbol)
20226 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20227 || S_IS_WEAK (fragp->fr_symbol))
20230 val = relaxed_symbol_addr (fragp, stretch);
20231 addr = fragp->fr_address + fragp->fr_fix;
20232 addr = (addr + 4) & ~3;
20233 /* Force misaligned targets to 32-bit variant. */
20237 if (val < 0 || val > 1020)
20242 /* Return the size of a relaxable add/sub immediate instruction. */
20244 relax_addsub (fragS *fragp, asection *sec)
20249 buf = fragp->fr_literal + fragp->fr_fix;
20250 op = bfd_get_16(sec->owner, buf);
20251 if ((op & 0xf) == ((op >> 4) & 0xf))
20252 return relax_immediate (fragp, 8, 0);
20254 return relax_immediate (fragp, 3, 0);
20257 /* Return TRUE iff the definition of symbol S could be pre-empted
20258 (overridden) at link or load time. */
20260 symbol_preemptible (symbolS *s)
20262 /* Weak symbols can always be pre-empted. */
20266 /* Non-global symbols cannot be pre-empted. */
20267 if (! S_IS_EXTERNAL (s))
20271 /* In ELF, a global symbol can be marked protected, or private. In that
20272 case it can't be pre-empted (other definitions in the same link unit
20273 would violate the ODR). */
20274 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20278 /* Other global symbols might be pre-empted. */
20282 /* Return the size of a relaxable branch instruction. BITS is the
20283 size of the offset field in the narrow instruction. */
20286 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20292 /* Assume worst case for symbols not known to be in the same section. */
20293 if (!S_IS_DEFINED (fragp->fr_symbol)
20294 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20295 || S_IS_WEAK (fragp->fr_symbol))
20299 /* A branch to a function in ARM state will require interworking. */
20300 if (S_IS_DEFINED (fragp->fr_symbol)
20301 && ARM_IS_FUNC (fragp->fr_symbol))
20305 if (symbol_preemptible (fragp->fr_symbol))
20308 val = relaxed_symbol_addr (fragp, stretch);
20309 addr = fragp->fr_address + fragp->fr_fix + 4;
20312 /* Offset is a signed value *2 */
20314 if (val >= limit || val < -limit)
20320 /* Relax a machine dependent frag. This returns the amount by which
20321 the current size of the frag should change. */
20324 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20329 oldsize = fragp->fr_var;
20330 switch (fragp->fr_subtype)
20332 case T_MNEM_ldr_pc2:
20333 newsize = relax_adr (fragp, sec, stretch);
20335 case T_MNEM_ldr_pc:
20336 case T_MNEM_ldr_sp:
20337 case T_MNEM_str_sp:
20338 newsize = relax_immediate (fragp, 8, 2);
20342 newsize = relax_immediate (fragp, 5, 2);
20346 newsize = relax_immediate (fragp, 5, 1);
20350 newsize = relax_immediate (fragp, 5, 0);
20353 newsize = relax_adr (fragp, sec, stretch);
20359 newsize = relax_immediate (fragp, 8, 0);
20362 newsize = relax_branch (fragp, sec, 11, stretch);
20365 newsize = relax_branch (fragp, sec, 8, stretch);
20367 case T_MNEM_add_sp:
20368 case T_MNEM_add_pc:
20369 newsize = relax_immediate (fragp, 8, 2);
20371 case T_MNEM_inc_sp:
20372 case T_MNEM_dec_sp:
20373 newsize = relax_immediate (fragp, 7, 2);
20379 newsize = relax_addsub (fragp, sec);
20385 fragp->fr_var = newsize;
20386 /* Freeze wide instructions that are at or before the same location as
20387 in the previous pass. This avoids infinite loops.
20388 Don't freeze them unconditionally because targets may be artificially
20389 misaligned by the expansion of preceding frags. */
20390 if (stretch <= 0 && newsize > 2)
20392 md_convert_frag (sec->owner, sec, fragp);
20396 return newsize - oldsize;
20399 /* Round up a section size to the appropriate boundary. */
20402 md_section_align (segT segment ATTRIBUTE_UNUSED,
20405 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20406 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20408 /* For a.out, force the section size to be aligned. If we don't do
20409 this, BFD will align it for us, but it will not write out the
20410 final bytes of the section. This may be a bug in BFD, but it is
20411 easier to fix it here since that is how the other a.out targets
20415 align = bfd_get_section_alignment (stdoutput, segment);
20416 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20423 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20424 of an rs_align_code fragment. */
20427 arm_handle_align (fragS * fragP)
20429 static char const arm_noop[2][2][4] =
20432 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20433 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20436 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20437 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20440 static char const thumb_noop[2][2][2] =
20443 {0xc0, 0x46}, /* LE */
20444 {0x46, 0xc0}, /* BE */
20447 {0x00, 0xbf}, /* LE */
20448 {0xbf, 0x00} /* BE */
20451 static char const wide_thumb_noop[2][4] =
20452 { /* Wide Thumb-2 */
20453 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20454 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20457 unsigned bytes, fix, noop_size;
20460 const char *narrow_noop = NULL;
20465 if (fragP->fr_type != rs_align_code)
20468 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20469 p = fragP->fr_literal + fragP->fr_fix;
20472 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20473 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20475 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20477 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20479 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20481 narrow_noop = thumb_noop[1][target_big_endian];
20482 noop = wide_thumb_noop[target_big_endian];
20485 noop = thumb_noop[0][target_big_endian];
20493 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20494 [target_big_endian];
20501 fragP->fr_var = noop_size;
20503 if (bytes & (noop_size - 1))
20505 fix = bytes & (noop_size - 1);
20507 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20509 memset (p, 0, fix);
20516 if (bytes & noop_size)
20518 /* Insert a narrow noop. */
20519 memcpy (p, narrow_noop, noop_size);
20521 bytes -= noop_size;
20525 /* Use wide noops for the remainder */
20529 while (bytes >= noop_size)
20531 memcpy (p, noop, noop_size);
20533 bytes -= noop_size;
20537 fragP->fr_fix += fix;
20540 /* Called from md_do_align. Used to create an alignment
20541 frag in a code section. */
20544 arm_frag_align_code (int n, int max)
20548 /* We assume that there will never be a requirement
20549 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20550 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20555 _("alignments greater than %d bytes not supported in .text sections."),
20556 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20557 as_fatal ("%s", err_msg);
20560 p = frag_var (rs_align_code,
20561 MAX_MEM_FOR_RS_ALIGN_CODE,
20563 (relax_substateT) max,
20570 /* Perform target specific initialisation of a frag.
20571 Note - despite the name this initialisation is not done when the frag
20572 is created, but only when its type is assigned. A frag can be created
20573 and used a long time before its type is set, so beware of assuming that
20574 this initialisationis performed first. */
20578 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20580 /* Record whether this frag is in an ARM or a THUMB area. */
20581 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20584 #else /* OBJ_ELF is defined. */
20586 arm_init_frag (fragS * fragP, int max_chars)
20588 /* If the current ARM vs THUMB mode has not already
20589 been recorded into this frag then do so now. */
20590 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20592 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20594 /* Record a mapping symbol for alignment frags. We will delete this
20595 later if the alignment ends up empty. */
20596 switch (fragP->fr_type)
20599 case rs_align_test:
20601 mapping_state_2 (MAP_DATA, max_chars);
20603 case rs_align_code:
20604 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20612 /* When we change sections we need to issue a new mapping symbol. */
20615 arm_elf_change_section (void)
20617 /* Link an unlinked unwind index table section to the .text section. */
20618 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20619 && elf_linked_to_section (now_seg) == NULL)
20620 elf_linked_to_section (now_seg) = text_section;
20624 arm_elf_section_type (const char * str, size_t len)
20626 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20627 return SHT_ARM_EXIDX;
20632 /* Code to deal with unwinding tables. */
20634 static void add_unwind_adjustsp (offsetT);
20636 /* Generate any deferred unwind frame offset. */
20639 flush_pending_unwind (void)
20643 offset = unwind.pending_offset;
20644 unwind.pending_offset = 0;
20646 add_unwind_adjustsp (offset);
20649 /* Add an opcode to this list for this function. Two-byte opcodes should
20650 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20654 add_unwind_opcode (valueT op, int length)
20656 /* Add any deferred stack adjustment. */
20657 if (unwind.pending_offset)
20658 flush_pending_unwind ();
20660 unwind.sp_restored = 0;
20662 if (unwind.opcode_count + length > unwind.opcode_alloc)
20664 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20665 if (unwind.opcodes)
20666 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20667 unwind.opcode_alloc);
20669 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20674 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20676 unwind.opcode_count++;
20680 /* Add unwind opcodes to adjust the stack pointer. */
20683 add_unwind_adjustsp (offsetT offset)
20687 if (offset > 0x200)
20689 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20694 /* Long form: 0xb2, uleb128. */
20695 /* This might not fit in a word so add the individual bytes,
20696 remembering the list is built in reverse order. */
20697 o = (valueT) ((offset - 0x204) >> 2);
20699 add_unwind_opcode (0, 1);
20701 /* Calculate the uleb128 encoding of the offset. */
20705 bytes[n] = o & 0x7f;
20711 /* Add the insn. */
20713 add_unwind_opcode (bytes[n - 1], 1);
20714 add_unwind_opcode (0xb2, 1);
20716 else if (offset > 0x100)
20718 /* Two short opcodes. */
20719 add_unwind_opcode (0x3f, 1);
20720 op = (offset - 0x104) >> 2;
20721 add_unwind_opcode (op, 1);
20723 else if (offset > 0)
20725 /* Short opcode. */
20726 op = (offset - 4) >> 2;
20727 add_unwind_opcode (op, 1);
20729 else if (offset < 0)
20732 while (offset > 0x100)
20734 add_unwind_opcode (0x7f, 1);
20737 op = ((offset - 4) >> 2) | 0x40;
20738 add_unwind_opcode (op, 1);
20742 /* Finish the list of unwind opcodes for this function. */
20744 finish_unwind_opcodes (void)
20748 if (unwind.fp_used)
20750 /* Adjust sp as necessary. */
20751 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20752 flush_pending_unwind ();
20754 /* After restoring sp from the frame pointer. */
20755 op = 0x90 | unwind.fp_reg;
20756 add_unwind_opcode (op, 1);
20759 flush_pending_unwind ();
20763 /* Start an exception table entry. If idx is nonzero this is an index table
20767 start_unwind_section (const segT text_seg, int idx)
20769 const char * text_name;
20770 const char * prefix;
20771 const char * prefix_once;
20772 const char * group_name;
20776 size_t sec_name_len;
20783 prefix = ELF_STRING_ARM_unwind;
20784 prefix_once = ELF_STRING_ARM_unwind_once;
20785 type = SHT_ARM_EXIDX;
20789 prefix = ELF_STRING_ARM_unwind_info;
20790 prefix_once = ELF_STRING_ARM_unwind_info_once;
20791 type = SHT_PROGBITS;
20794 text_name = segment_name (text_seg);
20795 if (streq (text_name, ".text"))
20798 if (strncmp (text_name, ".gnu.linkonce.t.",
20799 strlen (".gnu.linkonce.t.")) == 0)
20801 prefix = prefix_once;
20802 text_name += strlen (".gnu.linkonce.t.");
20805 prefix_len = strlen (prefix);
20806 text_len = strlen (text_name);
20807 sec_name_len = prefix_len + text_len;
20808 sec_name = (char *) xmalloc (sec_name_len + 1);
20809 memcpy (sec_name, prefix, prefix_len);
20810 memcpy (sec_name + prefix_len, text_name, text_len);
20811 sec_name[prefix_len + text_len] = '\0';
20817 /* Handle COMDAT group. */
20818 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20820 group_name = elf_group_name (text_seg);
20821 if (group_name == NULL)
20823 as_bad (_("Group section `%s' has no group signature"),
20824 segment_name (text_seg));
20825 ignore_rest_of_line ();
20828 flags |= SHF_GROUP;
20832 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20834 /* Set the section link for index tables. */
20836 elf_linked_to_section (now_seg) = text_seg;
20840 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20841 personality routine data. Returns zero, or the index table value for
20842 and inline entry. */
20845 create_unwind_entry (int have_data)
20850 /* The current word of data. */
20852 /* The number of bytes left in this word. */
20855 finish_unwind_opcodes ();
20857 /* Remember the current text section. */
20858 unwind.saved_seg = now_seg;
20859 unwind.saved_subseg = now_subseg;
20861 start_unwind_section (now_seg, 0);
20863 if (unwind.personality_routine == NULL)
20865 if (unwind.personality_index == -2)
20868 as_bad (_("handlerdata in cantunwind frame"));
20869 return 1; /* EXIDX_CANTUNWIND. */
20872 /* Use a default personality routine if none is specified. */
20873 if (unwind.personality_index == -1)
20875 if (unwind.opcode_count > 3)
20876 unwind.personality_index = 1;
20878 unwind.personality_index = 0;
20881 /* Space for the personality routine entry. */
20882 if (unwind.personality_index == 0)
20884 if (unwind.opcode_count > 3)
20885 as_bad (_("too many unwind opcodes for personality routine 0"));
20889 /* All the data is inline in the index table. */
20892 while (unwind.opcode_count > 0)
20894 unwind.opcode_count--;
20895 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20899 /* Pad with "finish" opcodes. */
20901 data = (data << 8) | 0xb0;
20908 /* We get two opcodes "free" in the first word. */
20909 size = unwind.opcode_count - 2;
20913 gas_assert (unwind.personality_index == -1);
20915 /* An extra byte is required for the opcode count. */
20916 size = unwind.opcode_count + 1;
20919 size = (size + 3) >> 2;
20921 as_bad (_("too many unwind opcodes"));
20923 frag_align (2, 0, 0);
20924 record_alignment (now_seg, 2);
20925 unwind.table_entry = expr_build_dot ();
20927 /* Allocate the table entry. */
20928 ptr = frag_more ((size << 2) + 4);
20929 /* PR 13449: Zero the table entries in case some of them are not used. */
20930 memset (ptr, 0, (size << 2) + 4);
20931 where = frag_now_fix () - ((size << 2) + 4);
20933 switch (unwind.personality_index)
20936 /* ??? Should this be a PLT generating relocation? */
20937 /* Custom personality routine. */
20938 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20939 BFD_RELOC_ARM_PREL31);
20944 /* Set the first byte to the number of additional words. */
20945 data = size > 0 ? size - 1 : 0;
20949 /* ABI defined personality routines. */
20951 /* Three opcodes bytes are packed into the first word. */
20958 /* The size and first two opcode bytes go in the first word. */
20959 data = ((0x80 + unwind.personality_index) << 8) | size;
20964 /* Should never happen. */
20968 /* Pack the opcodes into words (MSB first), reversing the list at the same
20970 while (unwind.opcode_count > 0)
20974 md_number_to_chars (ptr, data, 4);
20979 unwind.opcode_count--;
20981 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20984 /* Finish off the last word. */
20987 /* Pad with "finish" opcodes. */
20989 data = (data << 8) | 0xb0;
20991 md_number_to_chars (ptr, data, 4);
20996 /* Add an empty descriptor if there is no user-specified data. */
20997 ptr = frag_more (4);
20998 md_number_to_chars (ptr, 0, 4);
21005 /* Initialize the DWARF-2 unwind information for this procedure. */
21008 tc_arm_frame_initial_instructions (void)
21010 cfi_add_CFA_def_cfa (REG_SP, 0);
21012 #endif /* OBJ_ELF */
21014 /* Convert REGNAME to a DWARF-2 register number. */
21017 tc_arm_regname_to_dw2regnum (char *regname)
21019 int reg = arm_reg_parse (®name, REG_TYPE_RN);
21029 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
21033 exp.X_op = O_secrel;
21034 exp.X_add_symbol = symbol;
21035 exp.X_add_number = 0;
21036 emit_expr (&exp, size);
21040 /* MD interface: Symbol and relocation handling. */
21042 /* Return the address within the segment that a PC-relative fixup is
21043 relative to. For ARM, PC-relative fixups applied to instructions
21044 are generally relative to the location of the fixup plus 8 bytes.
21045 Thumb branches are offset by 4, and Thumb loads relative to PC
21046 require special handling. */
21049 md_pcrel_from_section (fixS * fixP, segT seg)
21051 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21053 /* If this is pc-relative and we are going to emit a relocation
21054 then we just want to put out any pipeline compensation that the linker
21055 will need. Otherwise we want to use the calculated base.
21056 For WinCE we skip the bias for externals as well, since this
21057 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21059 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21060 || (arm_force_relocation (fixP)
21062 && !S_IS_EXTERNAL (fixP->fx_addsy)
21068 switch (fixP->fx_r_type)
21070 /* PC relative addressing on the Thumb is slightly odd as the
21071 bottom two bits of the PC are forced to zero for the
21072 calculation. This happens *after* application of the
21073 pipeline offset. However, Thumb adrl already adjusts for
21074 this, so we need not do it again. */
21075 case BFD_RELOC_ARM_THUMB_ADD:
21078 case BFD_RELOC_ARM_THUMB_OFFSET:
21079 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21080 case BFD_RELOC_ARM_T32_ADD_PC12:
21081 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21082 return (base + 4) & ~3;
21084 /* Thumb branches are simply offset by +4. */
21085 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21086 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21087 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21088 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21089 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21092 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21094 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21095 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21096 && ARM_IS_FUNC (fixP->fx_addsy)
21097 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21098 base = fixP->fx_where + fixP->fx_frag->fr_address;
21101 /* BLX is like branches above, but forces the low two bits of PC to
21103 case BFD_RELOC_THUMB_PCREL_BLX:
21105 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21106 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21107 && THUMB_IS_FUNC (fixP->fx_addsy)
21108 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21109 base = fixP->fx_where + fixP->fx_frag->fr_address;
21110 return (base + 4) & ~3;
21112 /* ARM mode branches are offset by +8. However, the Windows CE
21113 loader expects the relocation not to take this into account. */
21114 case BFD_RELOC_ARM_PCREL_BLX:
21116 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21117 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21118 && ARM_IS_FUNC (fixP->fx_addsy)
21119 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21120 base = fixP->fx_where + fixP->fx_frag->fr_address;
21123 case BFD_RELOC_ARM_PCREL_CALL:
21125 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21126 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21127 && THUMB_IS_FUNC (fixP->fx_addsy)
21128 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21129 base = fixP->fx_where + fixP->fx_frag->fr_address;
21132 case BFD_RELOC_ARM_PCREL_BRANCH:
21133 case BFD_RELOC_ARM_PCREL_JUMP:
21134 case BFD_RELOC_ARM_PLT32:
21136 /* When handling fixups immediately, because we have already
21137 discovered the value of a symbol, or the address of the frag involved
21138 we must account for the offset by +8, as the OS loader will never see the reloc.
21139 see fixup_segment() in write.c
21140 The S_IS_EXTERNAL test handles the case of global symbols.
21141 Those need the calculated base, not just the pipe compensation the linker will need. */
21143 && fixP->fx_addsy != NULL
21144 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21145 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21153 /* ARM mode loads relative to PC are also offset by +8. Unlike
21154 branches, the Windows CE loader *does* expect the relocation
21155 to take this into account. */
21156 case BFD_RELOC_ARM_OFFSET_IMM:
21157 case BFD_RELOC_ARM_OFFSET_IMM8:
21158 case BFD_RELOC_ARM_HWLITERAL:
21159 case BFD_RELOC_ARM_LITERAL:
21160 case BFD_RELOC_ARM_CP_OFF_IMM:
21164 /* Other PC-relative relocations are un-offset. */
21170 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21171 Otherwise we have no need to default values of symbols. */
21174 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21177 if (name[0] == '_' && name[1] == 'G'
21178 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21182 if (symbol_find (name))
21183 as_bad (_("GOT already in the symbol table"));
21185 GOT_symbol = symbol_new (name, undefined_section,
21186 (valueT) 0, & zero_address_frag);
21196 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21197 computed as two separate immediate values, added together. We
21198 already know that this value cannot be computed by just one ARM
21201 static unsigned int
21202 validate_immediate_twopart (unsigned int val,
21203 unsigned int * highpart)
21208 for (i = 0; i < 32; i += 2)
21209 if (((a = rotate_left (val, i)) & 0xff) != 0)
21215 * highpart = (a >> 8) | ((i + 24) << 7);
21217 else if (a & 0xff0000)
21219 if (a & 0xff000000)
21221 * highpart = (a >> 16) | ((i + 16) << 7);
21225 gas_assert (a & 0xff000000);
21226 * highpart = (a >> 24) | ((i + 8) << 7);
21229 return (a & 0xff) | (i << 7);
21236 validate_offset_imm (unsigned int val, int hwse)
21238 if ((hwse && val > 255) || val > 4095)
21243 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21244 negative immediate constant by altering the instruction. A bit of
21249 by inverting the second operand, and
21252 by negating the second operand. */
21255 negate_data_op (unsigned long * instruction,
21256 unsigned long value)
21259 unsigned long negated, inverted;
21261 negated = encode_arm_immediate (-value);
21262 inverted = encode_arm_immediate (~value);
21264 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21267 /* First negates. */
21268 case OPCODE_SUB: /* ADD <-> SUB */
21269 new_inst = OPCODE_ADD;
21274 new_inst = OPCODE_SUB;
21278 case OPCODE_CMP: /* CMP <-> CMN */
21279 new_inst = OPCODE_CMN;
21284 new_inst = OPCODE_CMP;
21288 /* Now Inverted ops. */
21289 case OPCODE_MOV: /* MOV <-> MVN */
21290 new_inst = OPCODE_MVN;
21295 new_inst = OPCODE_MOV;
21299 case OPCODE_AND: /* AND <-> BIC */
21300 new_inst = OPCODE_BIC;
21305 new_inst = OPCODE_AND;
21309 case OPCODE_ADC: /* ADC <-> SBC */
21310 new_inst = OPCODE_SBC;
21315 new_inst = OPCODE_ADC;
21319 /* We cannot do anything. */
21324 if (value == (unsigned) FAIL)
21327 *instruction &= OPCODE_MASK;
21328 *instruction |= new_inst << DATA_OP_SHIFT;
21332 /* Like negate_data_op, but for Thumb-2. */
21334 static unsigned int
21335 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21339 unsigned int negated, inverted;
21341 negated = encode_thumb32_immediate (-value);
21342 inverted = encode_thumb32_immediate (~value);
21344 rd = (*instruction >> 8) & 0xf;
21345 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21348 /* ADD <-> SUB. Includes CMP <-> CMN. */
21349 case T2_OPCODE_SUB:
21350 new_inst = T2_OPCODE_ADD;
21354 case T2_OPCODE_ADD:
21355 new_inst = T2_OPCODE_SUB;
21359 /* ORR <-> ORN. Includes MOV <-> MVN. */
21360 case T2_OPCODE_ORR:
21361 new_inst = T2_OPCODE_ORN;
21365 case T2_OPCODE_ORN:
21366 new_inst = T2_OPCODE_ORR;
21370 /* AND <-> BIC. TST has no inverted equivalent. */
21371 case T2_OPCODE_AND:
21372 new_inst = T2_OPCODE_BIC;
21379 case T2_OPCODE_BIC:
21380 new_inst = T2_OPCODE_AND;
21385 case T2_OPCODE_ADC:
21386 new_inst = T2_OPCODE_SBC;
21390 case T2_OPCODE_SBC:
21391 new_inst = T2_OPCODE_ADC;
21395 /* We cannot do anything. */
21400 if (value == (unsigned int)FAIL)
21403 *instruction &= T2_OPCODE_MASK;
21404 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21408 /* Read a 32-bit thumb instruction from buf. */
21409 static unsigned long
21410 get_thumb32_insn (char * buf)
21412 unsigned long insn;
21413 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21414 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21420 /* We usually want to set the low bit on the address of thumb function
21421 symbols. In particular .word foo - . should have the low bit set.
21422 Generic code tries to fold the difference of two symbols to
21423 a constant. Prevent this and force a relocation when the first symbols
21424 is a thumb function. */
21427 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21429 if (op == O_subtract
21430 && l->X_op == O_symbol
21431 && r->X_op == O_symbol
21432 && THUMB_IS_FUNC (l->X_add_symbol))
21434 l->X_op = O_subtract;
21435 l->X_op_symbol = r->X_add_symbol;
21436 l->X_add_number -= r->X_add_number;
21440 /* Process as normal. */
21444 /* Encode Thumb2 unconditional branches and calls. The encoding
21445 for the 2 are identical for the immediate values. */
21448 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21450 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21453 addressT S, I1, I2, lo, hi;
21455 S = (value >> 24) & 0x01;
21456 I1 = (value >> 23) & 0x01;
21457 I2 = (value >> 22) & 0x01;
21458 hi = (value >> 12) & 0x3ff;
21459 lo = (value >> 1) & 0x7ff;
21460 newval = md_chars_to_number (buf, THUMB_SIZE);
21461 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21462 newval |= (S << 10) | hi;
21463 newval2 &= ~T2I1I2MASK;
21464 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21465 md_number_to_chars (buf, newval, THUMB_SIZE);
21466 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21470 md_apply_fix (fixS * fixP,
21474 offsetT value = * valP;
21476 unsigned int newimm;
21477 unsigned long temp;
21479 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21481 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21483 /* Note whether this will delete the relocation. */
21485 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21488 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21489 consistency with the behaviour on 32-bit hosts. Remember value
21491 value &= 0xffffffff;
21492 value ^= 0x80000000;
21493 value -= 0x80000000;
21496 fixP->fx_addnumber = value;
21498 /* Same treatment for fixP->fx_offset. */
21499 fixP->fx_offset &= 0xffffffff;
21500 fixP->fx_offset ^= 0x80000000;
21501 fixP->fx_offset -= 0x80000000;
21503 switch (fixP->fx_r_type)
21505 case BFD_RELOC_NONE:
21506 /* This will need to go in the object file. */
21510 case BFD_RELOC_ARM_IMMEDIATE:
21511 /* We claim that this fixup has been processed here,
21512 even if in fact we generate an error because we do
21513 not have a reloc for it, so tc_gen_reloc will reject it. */
21516 if (fixP->fx_addsy)
21518 const char *msg = 0;
21520 if (! S_IS_DEFINED (fixP->fx_addsy))
21521 msg = _("undefined symbol %s used as an immediate value");
21522 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21523 msg = _("symbol %s is in a different section");
21524 else if (S_IS_WEAK (fixP->fx_addsy))
21525 msg = _("symbol %s is weak and may be overridden later");
21529 as_bad_where (fixP->fx_file, fixP->fx_line,
21530 msg, S_GET_NAME (fixP->fx_addsy));
21535 temp = md_chars_to_number (buf, INSN_SIZE);
21537 /* If the offset is negative, we should use encoding A2 for ADR. */
21538 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21539 newimm = negate_data_op (&temp, value);
21542 newimm = encode_arm_immediate (value);
21544 /* If the instruction will fail, see if we can fix things up by
21545 changing the opcode. */
21546 if (newimm == (unsigned int) FAIL)
21547 newimm = negate_data_op (&temp, value);
21550 if (newimm == (unsigned int) FAIL)
21552 as_bad_where (fixP->fx_file, fixP->fx_line,
21553 _("invalid constant (%lx) after fixup"),
21554 (unsigned long) value);
21558 newimm |= (temp & 0xfffff000);
21559 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21562 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21564 unsigned int highpart = 0;
21565 unsigned int newinsn = 0xe1a00000; /* nop. */
21567 if (fixP->fx_addsy)
21569 const char *msg = 0;
21571 if (! S_IS_DEFINED (fixP->fx_addsy))
21572 msg = _("undefined symbol %s used as an immediate value");
21573 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21574 msg = _("symbol %s is in a different section");
21575 else if (S_IS_WEAK (fixP->fx_addsy))
21576 msg = _("symbol %s is weak and may be overridden later");
21580 as_bad_where (fixP->fx_file, fixP->fx_line,
21581 msg, S_GET_NAME (fixP->fx_addsy));
21586 newimm = encode_arm_immediate (value);
21587 temp = md_chars_to_number (buf, INSN_SIZE);
21589 /* If the instruction will fail, see if we can fix things up by
21590 changing the opcode. */
21591 if (newimm == (unsigned int) FAIL
21592 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21594 /* No ? OK - try using two ADD instructions to generate
21596 newimm = validate_immediate_twopart (value, & highpart);
21598 /* Yes - then make sure that the second instruction is
21600 if (newimm != (unsigned int) FAIL)
21602 /* Still No ? Try using a negated value. */
21603 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21604 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21605 /* Otherwise - give up. */
21608 as_bad_where (fixP->fx_file, fixP->fx_line,
21609 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21614 /* Replace the first operand in the 2nd instruction (which
21615 is the PC) with the destination register. We have
21616 already added in the PC in the first instruction and we
21617 do not want to do it again. */
21618 newinsn &= ~ 0xf0000;
21619 newinsn |= ((newinsn & 0x0f000) << 4);
21622 newimm |= (temp & 0xfffff000);
21623 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21625 highpart |= (newinsn & 0xfffff000);
21626 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21630 case BFD_RELOC_ARM_OFFSET_IMM:
21631 if (!fixP->fx_done && seg->use_rela_p)
21634 case BFD_RELOC_ARM_LITERAL:
21640 if (validate_offset_imm (value, 0) == FAIL)
21642 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21643 as_bad_where (fixP->fx_file, fixP->fx_line,
21644 _("invalid literal constant: pool needs to be closer"));
21646 as_bad_where (fixP->fx_file, fixP->fx_line,
21647 _("bad immediate value for offset (%ld)"),
21652 newval = md_chars_to_number (buf, INSN_SIZE);
21654 newval &= 0xfffff000;
21657 newval &= 0xff7ff000;
21658 newval |= value | (sign ? INDEX_UP : 0);
21660 md_number_to_chars (buf, newval, INSN_SIZE);
21663 case BFD_RELOC_ARM_OFFSET_IMM8:
21664 case BFD_RELOC_ARM_HWLITERAL:
21670 if (validate_offset_imm (value, 1) == FAIL)
21672 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21673 as_bad_where (fixP->fx_file, fixP->fx_line,
21674 _("invalid literal constant: pool needs to be closer"));
21676 as_bad_where (fixP->fx_file, fixP->fx_line,
21677 _("bad immediate value for 8-bit offset (%ld)"),
21682 newval = md_chars_to_number (buf, INSN_SIZE);
21684 newval &= 0xfffff0f0;
21687 newval &= 0xff7ff0f0;
21688 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21690 md_number_to_chars (buf, newval, INSN_SIZE);
21693 case BFD_RELOC_ARM_T32_OFFSET_U8:
21694 if (value < 0 || value > 1020 || value % 4 != 0)
21695 as_bad_where (fixP->fx_file, fixP->fx_line,
21696 _("bad immediate value for offset (%ld)"), (long) value);
21699 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21701 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21704 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21705 /* This is a complicated relocation used for all varieties of Thumb32
21706 load/store instruction with immediate offset:
21708 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21709 *4, optional writeback(W)
21710 (doubleword load/store)
21712 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21713 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21714 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21715 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21716 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21718 Uppercase letters indicate bits that are already encoded at
21719 this point. Lowercase letters are our problem. For the
21720 second block of instructions, the secondary opcode nybble
21721 (bits 8..11) is present, and bit 23 is zero, even if this is
21722 a PC-relative operation. */
21723 newval = md_chars_to_number (buf, THUMB_SIZE);
21725 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21727 if ((newval & 0xf0000000) == 0xe0000000)
21729 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21731 newval |= (1 << 23);
21734 if (value % 4 != 0)
21736 as_bad_where (fixP->fx_file, fixP->fx_line,
21737 _("offset not a multiple of 4"));
21743 as_bad_where (fixP->fx_file, fixP->fx_line,
21744 _("offset out of range"));
21749 else if ((newval & 0x000f0000) == 0x000f0000)
21751 /* PC-relative, 12-bit offset. */
21753 newval |= (1 << 23);
21758 as_bad_where (fixP->fx_file, fixP->fx_line,
21759 _("offset out of range"));
21764 else if ((newval & 0x00000100) == 0x00000100)
21766 /* Writeback: 8-bit, +/- offset. */
21768 newval |= (1 << 9);
21773 as_bad_where (fixP->fx_file, fixP->fx_line,
21774 _("offset out of range"));
21779 else if ((newval & 0x00000f00) == 0x00000e00)
21781 /* T-instruction: positive 8-bit offset. */
21782 if (value < 0 || value > 0xff)
21784 as_bad_where (fixP->fx_file, fixP->fx_line,
21785 _("offset out of range"));
21793 /* Positive 12-bit or negative 8-bit offset. */
21797 newval |= (1 << 23);
21807 as_bad_where (fixP->fx_file, fixP->fx_line,
21808 _("offset out of range"));
21815 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21816 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21819 case BFD_RELOC_ARM_SHIFT_IMM:
21820 newval = md_chars_to_number (buf, INSN_SIZE);
21821 if (((unsigned long) value) > 32
21823 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21825 as_bad_where (fixP->fx_file, fixP->fx_line,
21826 _("shift expression is too large"));
21831 /* Shifts of zero must be done as lsl. */
21833 else if (value == 32)
21835 newval &= 0xfffff07f;
21836 newval |= (value & 0x1f) << 7;
21837 md_number_to_chars (buf, newval, INSN_SIZE);
21840 case BFD_RELOC_ARM_T32_IMMEDIATE:
21841 case BFD_RELOC_ARM_T32_ADD_IMM:
21842 case BFD_RELOC_ARM_T32_IMM12:
21843 case BFD_RELOC_ARM_T32_ADD_PC12:
21844 /* We claim that this fixup has been processed here,
21845 even if in fact we generate an error because we do
21846 not have a reloc for it, so tc_gen_reloc will reject it. */
21850 && ! S_IS_DEFINED (fixP->fx_addsy))
21852 as_bad_where (fixP->fx_file, fixP->fx_line,
21853 _("undefined symbol %s used as an immediate value"),
21854 S_GET_NAME (fixP->fx_addsy));
21858 newval = md_chars_to_number (buf, THUMB_SIZE);
21860 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21863 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21864 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21866 newimm = encode_thumb32_immediate (value);
21867 if (newimm == (unsigned int) FAIL)
21868 newimm = thumb32_negate_data_op (&newval, value);
21870 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21871 && newimm == (unsigned int) FAIL)
21873 /* Turn add/sum into addw/subw. */
21874 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21875 newval = (newval & 0xfeffffff) | 0x02000000;
21876 /* No flat 12-bit imm encoding for addsw/subsw. */
21877 if ((newval & 0x00100000) == 0)
21879 /* 12 bit immediate for addw/subw. */
21883 newval ^= 0x00a00000;
21886 newimm = (unsigned int) FAIL;
21892 if (newimm == (unsigned int)FAIL)
21894 as_bad_where (fixP->fx_file, fixP->fx_line,
21895 _("invalid constant (%lx) after fixup"),
21896 (unsigned long) value);
21900 newval |= (newimm & 0x800) << 15;
21901 newval |= (newimm & 0x700) << 4;
21902 newval |= (newimm & 0x0ff);
21904 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21905 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21908 case BFD_RELOC_ARM_SMC:
21909 if (((unsigned long) value) > 0xffff)
21910 as_bad_where (fixP->fx_file, fixP->fx_line,
21911 _("invalid smc expression"));
21912 newval = md_chars_to_number (buf, INSN_SIZE);
21913 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21914 md_number_to_chars (buf, newval, INSN_SIZE);
21917 case BFD_RELOC_ARM_HVC:
21918 if (((unsigned long) value) > 0xffff)
21919 as_bad_where (fixP->fx_file, fixP->fx_line,
21920 _("invalid hvc expression"));
21921 newval = md_chars_to_number (buf, INSN_SIZE);
21922 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21923 md_number_to_chars (buf, newval, INSN_SIZE);
21926 case BFD_RELOC_ARM_SWI:
21927 if (fixP->tc_fix_data != 0)
21929 if (((unsigned long) value) > 0xff)
21930 as_bad_where (fixP->fx_file, fixP->fx_line,
21931 _("invalid swi expression"));
21932 newval = md_chars_to_number (buf, THUMB_SIZE);
21934 md_number_to_chars (buf, newval, THUMB_SIZE);
21938 if (((unsigned long) value) > 0x00ffffff)
21939 as_bad_where (fixP->fx_file, fixP->fx_line,
21940 _("invalid swi expression"));
21941 newval = md_chars_to_number (buf, INSN_SIZE);
21943 md_number_to_chars (buf, newval, INSN_SIZE);
21947 case BFD_RELOC_ARM_MULTI:
21948 if (((unsigned long) value) > 0xffff)
21949 as_bad_where (fixP->fx_file, fixP->fx_line,
21950 _("invalid expression in load/store multiple"));
21951 newval = value | md_chars_to_number (buf, INSN_SIZE);
21952 md_number_to_chars (buf, newval, INSN_SIZE);
21956 case BFD_RELOC_ARM_PCREL_CALL:
21958 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21960 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21961 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21962 && THUMB_IS_FUNC (fixP->fx_addsy))
21963 /* Flip the bl to blx. This is a simple flip
21964 bit here because we generate PCREL_CALL for
21965 unconditional bls. */
21967 newval = md_chars_to_number (buf, INSN_SIZE);
21968 newval = newval | 0x10000000;
21969 md_number_to_chars (buf, newval, INSN_SIZE);
21975 goto arm_branch_common;
21977 case BFD_RELOC_ARM_PCREL_JUMP:
21978 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21980 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21981 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21982 && THUMB_IS_FUNC (fixP->fx_addsy))
21984 /* This would map to a bl<cond>, b<cond>,
21985 b<always> to a Thumb function. We
21986 need to force a relocation for this particular
21988 newval = md_chars_to_number (buf, INSN_SIZE);
21992 case BFD_RELOC_ARM_PLT32:
21994 case BFD_RELOC_ARM_PCREL_BRANCH:
21996 goto arm_branch_common;
21998 case BFD_RELOC_ARM_PCREL_BLX:
22001 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22003 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22004 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22005 && ARM_IS_FUNC (fixP->fx_addsy))
22007 /* Flip the blx to a bl and warn. */
22008 const char *name = S_GET_NAME (fixP->fx_addsy);
22009 newval = 0xeb000000;
22010 as_warn_where (fixP->fx_file, fixP->fx_line,
22011 _("blx to '%s' an ARM ISA state function changed to bl"),
22013 md_number_to_chars (buf, newval, INSN_SIZE);
22019 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22020 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
22024 /* We are going to store value (shifted right by two) in the
22025 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22026 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22027 also be be clear. */
22029 as_bad_where (fixP->fx_file, fixP->fx_line,
22030 _("misaligned branch destination"));
22031 if ((value & (offsetT)0xfe000000) != (offsetT)0
22032 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
22033 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22035 if (fixP->fx_done || !seg->use_rela_p)
22037 newval = md_chars_to_number (buf, INSN_SIZE);
22038 newval |= (value >> 2) & 0x00ffffff;
22039 /* Set the H bit on BLX instructions. */
22043 newval |= 0x01000000;
22045 newval &= ~0x01000000;
22047 md_number_to_chars (buf, newval, INSN_SIZE);
22051 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22052 /* CBZ can only branch forward. */
22054 /* Attempts to use CBZ to branch to the next instruction
22055 (which, strictly speaking, are prohibited) will be turned into
22058 FIXME: It may be better to remove the instruction completely and
22059 perform relaxation. */
22062 newval = md_chars_to_number (buf, THUMB_SIZE);
22063 newval = 0xbf00; /* NOP encoding T1 */
22064 md_number_to_chars (buf, newval, THUMB_SIZE);
22069 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22071 if (fixP->fx_done || !seg->use_rela_p)
22073 newval = md_chars_to_number (buf, THUMB_SIZE);
22074 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22075 md_number_to_chars (buf, newval, THUMB_SIZE);
22080 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22081 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22082 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22084 if (fixP->fx_done || !seg->use_rela_p)
22086 newval = md_chars_to_number (buf, THUMB_SIZE);
22087 newval |= (value & 0x1ff) >> 1;
22088 md_number_to_chars (buf, newval, THUMB_SIZE);
22092 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22093 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22094 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22096 if (fixP->fx_done || !seg->use_rela_p)
22098 newval = md_chars_to_number (buf, THUMB_SIZE);
22099 newval |= (value & 0xfff) >> 1;
22100 md_number_to_chars (buf, newval, THUMB_SIZE);
22104 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22106 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22107 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22108 && ARM_IS_FUNC (fixP->fx_addsy)
22109 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22111 /* Force a relocation for a branch 20 bits wide. */
22114 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22115 as_bad_where (fixP->fx_file, fixP->fx_line,
22116 _("conditional branch out of range"));
22118 if (fixP->fx_done || !seg->use_rela_p)
22121 addressT S, J1, J2, lo, hi;
22123 S = (value & 0x00100000) >> 20;
22124 J2 = (value & 0x00080000) >> 19;
22125 J1 = (value & 0x00040000) >> 18;
22126 hi = (value & 0x0003f000) >> 12;
22127 lo = (value & 0x00000ffe) >> 1;
22129 newval = md_chars_to_number (buf, THUMB_SIZE);
22130 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22131 newval |= (S << 10) | hi;
22132 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22133 md_number_to_chars (buf, newval, THUMB_SIZE);
22134 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22138 case BFD_RELOC_THUMB_PCREL_BLX:
22139 /* If there is a blx from a thumb state function to
22140 another thumb function flip this to a bl and warn
22144 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22145 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22146 && THUMB_IS_FUNC (fixP->fx_addsy))
22148 const char *name = S_GET_NAME (fixP->fx_addsy);
22149 as_warn_where (fixP->fx_file, fixP->fx_line,
22150 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22152 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22153 newval = newval | 0x1000;
22154 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22155 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22160 goto thumb_bl_common;
22162 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22163 /* A bl from Thumb state ISA to an internal ARM state function
22164 is converted to a blx. */
22166 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22167 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22168 && ARM_IS_FUNC (fixP->fx_addsy)
22169 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22171 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22172 newval = newval & ~0x1000;
22173 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22174 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22180 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22181 /* For a BLX instruction, make sure that the relocation is rounded up
22182 to a word boundary. This follows the semantics of the instruction
22183 which specifies that bit 1 of the target address will come from bit
22184 1 of the base address. */
22185 value = (value + 3) & ~ 3;
22188 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22189 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22190 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22193 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22195 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22196 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22197 else if ((value & ~0x1ffffff)
22198 && ((value & ~0x1ffffff) != ~0x1ffffff))
22199 as_bad_where (fixP->fx_file, fixP->fx_line,
22200 _("Thumb2 branch out of range"));
22203 if (fixP->fx_done || !seg->use_rela_p)
22204 encode_thumb2_b_bl_offset (buf, value);
22208 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22209 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22210 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22212 if (fixP->fx_done || !seg->use_rela_p)
22213 encode_thumb2_b_bl_offset (buf, value);
22218 if (fixP->fx_done || !seg->use_rela_p)
22219 md_number_to_chars (buf, value, 1);
22223 if (fixP->fx_done || !seg->use_rela_p)
22224 md_number_to_chars (buf, value, 2);
22228 case BFD_RELOC_ARM_TLS_CALL:
22229 case BFD_RELOC_ARM_THM_TLS_CALL:
22230 case BFD_RELOC_ARM_TLS_DESCSEQ:
22231 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22232 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22235 case BFD_RELOC_ARM_TLS_GOTDESC:
22236 case BFD_RELOC_ARM_TLS_GD32:
22237 case BFD_RELOC_ARM_TLS_LE32:
22238 case BFD_RELOC_ARM_TLS_IE32:
22239 case BFD_RELOC_ARM_TLS_LDM32:
22240 case BFD_RELOC_ARM_TLS_LDO32:
22241 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22244 case BFD_RELOC_ARM_GOT32:
22245 case BFD_RELOC_ARM_GOTOFF:
22246 if (fixP->fx_done || !seg->use_rela_p)
22247 md_number_to_chars (buf, 0, 4);
22250 case BFD_RELOC_ARM_GOT_PREL:
22251 if (fixP->fx_done || !seg->use_rela_p)
22252 md_number_to_chars (buf, value, 4);
22255 case BFD_RELOC_ARM_TARGET2:
22256 /* TARGET2 is not partial-inplace, so we need to write the
22257 addend here for REL targets, because it won't be written out
22258 during reloc processing later. */
22259 if (fixP->fx_done || !seg->use_rela_p)
22260 md_number_to_chars (buf, fixP->fx_offset, 4);
22264 case BFD_RELOC_RVA:
22266 case BFD_RELOC_ARM_TARGET1:
22267 case BFD_RELOC_ARM_ROSEGREL32:
22268 case BFD_RELOC_ARM_SBREL32:
22269 case BFD_RELOC_32_PCREL:
22271 case BFD_RELOC_32_SECREL:
22273 if (fixP->fx_done || !seg->use_rela_p)
22275 /* For WinCE we only do this for pcrel fixups. */
22276 if (fixP->fx_done || fixP->fx_pcrel)
22278 md_number_to_chars (buf, value, 4);
22282 case BFD_RELOC_ARM_PREL31:
22283 if (fixP->fx_done || !seg->use_rela_p)
22285 newval = md_chars_to_number (buf, 4) & 0x80000000;
22286 if ((value ^ (value >> 1)) & 0x40000000)
22288 as_bad_where (fixP->fx_file, fixP->fx_line,
22289 _("rel31 relocation overflow"));
22291 newval |= value & 0x7fffffff;
22292 md_number_to_chars (buf, newval, 4);
22297 case BFD_RELOC_ARM_CP_OFF_IMM:
22298 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22299 if (value < -1023 || value > 1023 || (value & 3))
22300 as_bad_where (fixP->fx_file, fixP->fx_line,
22301 _("co-processor offset out of range"));
22306 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22307 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22308 newval = md_chars_to_number (buf, INSN_SIZE);
22310 newval = get_thumb32_insn (buf);
22312 newval &= 0xffffff00;
22315 newval &= 0xff7fff00;
22316 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22318 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22319 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22320 md_number_to_chars (buf, newval, INSN_SIZE);
22322 put_thumb32_insn (buf, newval);
22325 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22326 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22327 if (value < -255 || value > 255)
22328 as_bad_where (fixP->fx_file, fixP->fx_line,
22329 _("co-processor offset out of range"));
22331 goto cp_off_common;
22333 case BFD_RELOC_ARM_THUMB_OFFSET:
22334 newval = md_chars_to_number (buf, THUMB_SIZE);
22335 /* Exactly what ranges, and where the offset is inserted depends
22336 on the type of instruction, we can establish this from the
22338 switch (newval >> 12)
22340 case 4: /* PC load. */
22341 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22342 forced to zero for these loads; md_pcrel_from has already
22343 compensated for this. */
22345 as_bad_where (fixP->fx_file, fixP->fx_line,
22346 _("invalid offset, target not word aligned (0x%08lX)"),
22347 (((unsigned long) fixP->fx_frag->fr_address
22348 + (unsigned long) fixP->fx_where) & ~3)
22349 + (unsigned long) value);
22351 if (value & ~0x3fc)
22352 as_bad_where (fixP->fx_file, fixP->fx_line,
22353 _("invalid offset, value too big (0x%08lX)"),
22356 newval |= value >> 2;
22359 case 9: /* SP load/store. */
22360 if (value & ~0x3fc)
22361 as_bad_where (fixP->fx_file, fixP->fx_line,
22362 _("invalid offset, value too big (0x%08lX)"),
22364 newval |= value >> 2;
22367 case 6: /* Word load/store. */
22369 as_bad_where (fixP->fx_file, fixP->fx_line,
22370 _("invalid offset, value too big (0x%08lX)"),
22372 newval |= value << 4; /* 6 - 2. */
22375 case 7: /* Byte load/store. */
22377 as_bad_where (fixP->fx_file, fixP->fx_line,
22378 _("invalid offset, value too big (0x%08lX)"),
22380 newval |= value << 6;
22383 case 8: /* Halfword load/store. */
22385 as_bad_where (fixP->fx_file, fixP->fx_line,
22386 _("invalid offset, value too big (0x%08lX)"),
22388 newval |= value << 5; /* 6 - 1. */
22392 as_bad_where (fixP->fx_file, fixP->fx_line,
22393 "Unable to process relocation for thumb opcode: %lx",
22394 (unsigned long) newval);
22397 md_number_to_chars (buf, newval, THUMB_SIZE);
22400 case BFD_RELOC_ARM_THUMB_ADD:
22401 /* This is a complicated relocation, since we use it for all of
22402 the following immediate relocations:
22406 9bit ADD/SUB SP word-aligned
22407 10bit ADD PC/SP word-aligned
22409 The type of instruction being processed is encoded in the
22416 newval = md_chars_to_number (buf, THUMB_SIZE);
22418 int rd = (newval >> 4) & 0xf;
22419 int rs = newval & 0xf;
22420 int subtract = !!(newval & 0x8000);
22422 /* Check for HI regs, only very restricted cases allowed:
22423 Adjusting SP, and using PC or SP to get an address. */
22424 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22425 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22426 as_bad_where (fixP->fx_file, fixP->fx_line,
22427 _("invalid Hi register with immediate"));
22429 /* If value is negative, choose the opposite instruction. */
22433 subtract = !subtract;
22435 as_bad_where (fixP->fx_file, fixP->fx_line,
22436 _("immediate value out of range"));
22441 if (value & ~0x1fc)
22442 as_bad_where (fixP->fx_file, fixP->fx_line,
22443 _("invalid immediate for stack address calculation"));
22444 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22445 newval |= value >> 2;
22447 else if (rs == REG_PC || rs == REG_SP)
22449 if (subtract || value & ~0x3fc)
22450 as_bad_where (fixP->fx_file, fixP->fx_line,
22451 _("invalid immediate for address calculation (value = 0x%08lX)"),
22452 (unsigned long) value);
22453 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22455 newval |= value >> 2;
22460 as_bad_where (fixP->fx_file, fixP->fx_line,
22461 _("immediate value out of range"));
22462 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22463 newval |= (rd << 8) | value;
22468 as_bad_where (fixP->fx_file, fixP->fx_line,
22469 _("immediate value out of range"));
22470 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22471 newval |= rd | (rs << 3) | (value << 6);
22474 md_number_to_chars (buf, newval, THUMB_SIZE);
22477 case BFD_RELOC_ARM_THUMB_IMM:
22478 newval = md_chars_to_number (buf, THUMB_SIZE);
22479 if (value < 0 || value > 255)
22480 as_bad_where (fixP->fx_file, fixP->fx_line,
22481 _("invalid immediate: %ld is out of range"),
22484 md_number_to_chars (buf, newval, THUMB_SIZE);
22487 case BFD_RELOC_ARM_THUMB_SHIFT:
22488 /* 5bit shift value (0..32). LSL cannot take 32. */
22489 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22490 temp = newval & 0xf800;
22491 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22492 as_bad_where (fixP->fx_file, fixP->fx_line,
22493 _("invalid shift value: %ld"), (long) value);
22494 /* Shifts of zero must be encoded as LSL. */
22496 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22497 /* Shifts of 32 are encoded as zero. */
22498 else if (value == 32)
22500 newval |= value << 6;
22501 md_number_to_chars (buf, newval, THUMB_SIZE);
22504 case BFD_RELOC_VTABLE_INHERIT:
22505 case BFD_RELOC_VTABLE_ENTRY:
22509 case BFD_RELOC_ARM_MOVW:
22510 case BFD_RELOC_ARM_MOVT:
22511 case BFD_RELOC_ARM_THUMB_MOVW:
22512 case BFD_RELOC_ARM_THUMB_MOVT:
22513 if (fixP->fx_done || !seg->use_rela_p)
22515 /* REL format relocations are limited to a 16-bit addend. */
22516 if (!fixP->fx_done)
22518 if (value < -0x8000 || value > 0x7fff)
22519 as_bad_where (fixP->fx_file, fixP->fx_line,
22520 _("offset out of range"));
22522 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22523 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22528 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22529 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22531 newval = get_thumb32_insn (buf);
22532 newval &= 0xfbf08f00;
22533 newval |= (value & 0xf000) << 4;
22534 newval |= (value & 0x0800) << 15;
22535 newval |= (value & 0x0700) << 4;
22536 newval |= (value & 0x00ff);
22537 put_thumb32_insn (buf, newval);
22541 newval = md_chars_to_number (buf, 4);
22542 newval &= 0xfff0f000;
22543 newval |= value & 0x0fff;
22544 newval |= (value & 0xf000) << 4;
22545 md_number_to_chars (buf, newval, 4);
22550 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22551 case BFD_RELOC_ARM_ALU_PC_G0:
22552 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22553 case BFD_RELOC_ARM_ALU_PC_G1:
22554 case BFD_RELOC_ARM_ALU_PC_G2:
22555 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22556 case BFD_RELOC_ARM_ALU_SB_G0:
22557 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22558 case BFD_RELOC_ARM_ALU_SB_G1:
22559 case BFD_RELOC_ARM_ALU_SB_G2:
22560 gas_assert (!fixP->fx_done);
22561 if (!seg->use_rela_p)
22564 bfd_vma encoded_addend;
22565 bfd_vma addend_abs = abs (value);
22567 /* Check that the absolute value of the addend can be
22568 expressed as an 8-bit constant plus a rotation. */
22569 encoded_addend = encode_arm_immediate (addend_abs);
22570 if (encoded_addend == (unsigned int) FAIL)
22571 as_bad_where (fixP->fx_file, fixP->fx_line,
22572 _("the offset 0x%08lX is not representable"),
22573 (unsigned long) addend_abs);
22575 /* Extract the instruction. */
22576 insn = md_chars_to_number (buf, INSN_SIZE);
22578 /* If the addend is positive, use an ADD instruction.
22579 Otherwise use a SUB. Take care not to destroy the S bit. */
22580 insn &= 0xff1fffff;
22586 /* Place the encoded addend into the first 12 bits of the
22588 insn &= 0xfffff000;
22589 insn |= encoded_addend;
22591 /* Update the instruction. */
22592 md_number_to_chars (buf, insn, INSN_SIZE);
22596 case BFD_RELOC_ARM_LDR_PC_G0:
22597 case BFD_RELOC_ARM_LDR_PC_G1:
22598 case BFD_RELOC_ARM_LDR_PC_G2:
22599 case BFD_RELOC_ARM_LDR_SB_G0:
22600 case BFD_RELOC_ARM_LDR_SB_G1:
22601 case BFD_RELOC_ARM_LDR_SB_G2:
22602 gas_assert (!fixP->fx_done);
22603 if (!seg->use_rela_p)
22606 bfd_vma addend_abs = abs (value);
22608 /* Check that the absolute value of the addend can be
22609 encoded in 12 bits. */
22610 if (addend_abs >= 0x1000)
22611 as_bad_where (fixP->fx_file, fixP->fx_line,
22612 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22613 (unsigned long) addend_abs);
22615 /* Extract the instruction. */
22616 insn = md_chars_to_number (buf, INSN_SIZE);
22618 /* If the addend is negative, clear bit 23 of the instruction.
22619 Otherwise set it. */
22621 insn &= ~(1 << 23);
22625 /* Place the absolute value of the addend into the first 12 bits
22626 of the instruction. */
22627 insn &= 0xfffff000;
22628 insn |= addend_abs;
22630 /* Update the instruction. */
22631 md_number_to_chars (buf, insn, INSN_SIZE);
22635 case BFD_RELOC_ARM_LDRS_PC_G0:
22636 case BFD_RELOC_ARM_LDRS_PC_G1:
22637 case BFD_RELOC_ARM_LDRS_PC_G2:
22638 case BFD_RELOC_ARM_LDRS_SB_G0:
22639 case BFD_RELOC_ARM_LDRS_SB_G1:
22640 case BFD_RELOC_ARM_LDRS_SB_G2:
22641 gas_assert (!fixP->fx_done);
22642 if (!seg->use_rela_p)
22645 bfd_vma addend_abs = abs (value);
22647 /* Check that the absolute value of the addend can be
22648 encoded in 8 bits. */
22649 if (addend_abs >= 0x100)
22650 as_bad_where (fixP->fx_file, fixP->fx_line,
22651 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22652 (unsigned long) addend_abs);
22654 /* Extract the instruction. */
22655 insn = md_chars_to_number (buf, INSN_SIZE);
22657 /* If the addend is negative, clear bit 23 of the instruction.
22658 Otherwise set it. */
22660 insn &= ~(1 << 23);
22664 /* Place the first four bits of the absolute value of the addend
22665 into the first 4 bits of the instruction, and the remaining
22666 four into bits 8 .. 11. */
22667 insn &= 0xfffff0f0;
22668 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22670 /* Update the instruction. */
22671 md_number_to_chars (buf, insn, INSN_SIZE);
22675 case BFD_RELOC_ARM_LDC_PC_G0:
22676 case BFD_RELOC_ARM_LDC_PC_G1:
22677 case BFD_RELOC_ARM_LDC_PC_G2:
22678 case BFD_RELOC_ARM_LDC_SB_G0:
22679 case BFD_RELOC_ARM_LDC_SB_G1:
22680 case BFD_RELOC_ARM_LDC_SB_G2:
22681 gas_assert (!fixP->fx_done);
22682 if (!seg->use_rela_p)
22685 bfd_vma addend_abs = abs (value);
22687 /* Check that the absolute value of the addend is a multiple of
22688 four and, when divided by four, fits in 8 bits. */
22689 if (addend_abs & 0x3)
22690 as_bad_where (fixP->fx_file, fixP->fx_line,
22691 _("bad offset 0x%08lX (must be word-aligned)"),
22692 (unsigned long) addend_abs);
22694 if ((addend_abs >> 2) > 0xff)
22695 as_bad_where (fixP->fx_file, fixP->fx_line,
22696 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22697 (unsigned long) addend_abs);
22699 /* Extract the instruction. */
22700 insn = md_chars_to_number (buf, INSN_SIZE);
22702 /* If the addend is negative, clear bit 23 of the instruction.
22703 Otherwise set it. */
22705 insn &= ~(1 << 23);
22709 /* Place the addend (divided by four) into the first eight
22710 bits of the instruction. */
22711 insn &= 0xfffffff0;
22712 insn |= addend_abs >> 2;
22714 /* Update the instruction. */
22715 md_number_to_chars (buf, insn, INSN_SIZE);
22719 case BFD_RELOC_ARM_V4BX:
22720 /* This will need to go in the object file. */
22724 case BFD_RELOC_UNUSED:
22726 as_bad_where (fixP->fx_file, fixP->fx_line,
22727 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22731 /* Translate internal representation of relocation info to BFD target
22735 tc_gen_reloc (asection *section, fixS *fixp)
22738 bfd_reloc_code_real_type code;
22740 reloc = (arelent *) xmalloc (sizeof (arelent));
22742 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22743 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22744 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22746 if (fixp->fx_pcrel)
22748 if (section->use_rela_p)
22749 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22751 fixp->fx_offset = reloc->address;
22753 reloc->addend = fixp->fx_offset;
22755 switch (fixp->fx_r_type)
22758 if (fixp->fx_pcrel)
22760 code = BFD_RELOC_8_PCREL;
22765 if (fixp->fx_pcrel)
22767 code = BFD_RELOC_16_PCREL;
22772 if (fixp->fx_pcrel)
22774 code = BFD_RELOC_32_PCREL;
22778 case BFD_RELOC_ARM_MOVW:
22779 if (fixp->fx_pcrel)
22781 code = BFD_RELOC_ARM_MOVW_PCREL;
22785 case BFD_RELOC_ARM_MOVT:
22786 if (fixp->fx_pcrel)
22788 code = BFD_RELOC_ARM_MOVT_PCREL;
22792 case BFD_RELOC_ARM_THUMB_MOVW:
22793 if (fixp->fx_pcrel)
22795 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22799 case BFD_RELOC_ARM_THUMB_MOVT:
22800 if (fixp->fx_pcrel)
22802 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22806 case BFD_RELOC_NONE:
22807 case BFD_RELOC_ARM_PCREL_BRANCH:
22808 case BFD_RELOC_ARM_PCREL_BLX:
22809 case BFD_RELOC_RVA:
22810 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22811 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22812 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22813 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22814 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22815 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22816 case BFD_RELOC_VTABLE_ENTRY:
22817 case BFD_RELOC_VTABLE_INHERIT:
22819 case BFD_RELOC_32_SECREL:
22821 code = fixp->fx_r_type;
22824 case BFD_RELOC_THUMB_PCREL_BLX:
22826 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22827 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22830 code = BFD_RELOC_THUMB_PCREL_BLX;
22833 case BFD_RELOC_ARM_LITERAL:
22834 case BFD_RELOC_ARM_HWLITERAL:
22835 /* If this is called then the a literal has
22836 been referenced across a section boundary. */
22837 as_bad_where (fixp->fx_file, fixp->fx_line,
22838 _("literal referenced across section boundary"));
22842 case BFD_RELOC_ARM_TLS_CALL:
22843 case BFD_RELOC_ARM_THM_TLS_CALL:
22844 case BFD_RELOC_ARM_TLS_DESCSEQ:
22845 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22846 case BFD_RELOC_ARM_GOT32:
22847 case BFD_RELOC_ARM_GOTOFF:
22848 case BFD_RELOC_ARM_GOT_PREL:
22849 case BFD_RELOC_ARM_PLT32:
22850 case BFD_RELOC_ARM_TARGET1:
22851 case BFD_RELOC_ARM_ROSEGREL32:
22852 case BFD_RELOC_ARM_SBREL32:
22853 case BFD_RELOC_ARM_PREL31:
22854 case BFD_RELOC_ARM_TARGET2:
22855 case BFD_RELOC_ARM_TLS_LE32:
22856 case BFD_RELOC_ARM_TLS_LDO32:
22857 case BFD_RELOC_ARM_PCREL_CALL:
22858 case BFD_RELOC_ARM_PCREL_JUMP:
22859 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22860 case BFD_RELOC_ARM_ALU_PC_G0:
22861 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22862 case BFD_RELOC_ARM_ALU_PC_G1:
22863 case BFD_RELOC_ARM_ALU_PC_G2:
22864 case BFD_RELOC_ARM_LDR_PC_G0:
22865 case BFD_RELOC_ARM_LDR_PC_G1:
22866 case BFD_RELOC_ARM_LDR_PC_G2:
22867 case BFD_RELOC_ARM_LDRS_PC_G0:
22868 case BFD_RELOC_ARM_LDRS_PC_G1:
22869 case BFD_RELOC_ARM_LDRS_PC_G2:
22870 case BFD_RELOC_ARM_LDC_PC_G0:
22871 case BFD_RELOC_ARM_LDC_PC_G1:
22872 case BFD_RELOC_ARM_LDC_PC_G2:
22873 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22874 case BFD_RELOC_ARM_ALU_SB_G0:
22875 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22876 case BFD_RELOC_ARM_ALU_SB_G1:
22877 case BFD_RELOC_ARM_ALU_SB_G2:
22878 case BFD_RELOC_ARM_LDR_SB_G0:
22879 case BFD_RELOC_ARM_LDR_SB_G1:
22880 case BFD_RELOC_ARM_LDR_SB_G2:
22881 case BFD_RELOC_ARM_LDRS_SB_G0:
22882 case BFD_RELOC_ARM_LDRS_SB_G1:
22883 case BFD_RELOC_ARM_LDRS_SB_G2:
22884 case BFD_RELOC_ARM_LDC_SB_G0:
22885 case BFD_RELOC_ARM_LDC_SB_G1:
22886 case BFD_RELOC_ARM_LDC_SB_G2:
22887 case BFD_RELOC_ARM_V4BX:
22888 code = fixp->fx_r_type;
22891 case BFD_RELOC_ARM_TLS_GOTDESC:
22892 case BFD_RELOC_ARM_TLS_GD32:
22893 case BFD_RELOC_ARM_TLS_IE32:
22894 case BFD_RELOC_ARM_TLS_LDM32:
22895 /* BFD will include the symbol's address in the addend.
22896 But we don't want that, so subtract it out again here. */
22897 if (!S_IS_COMMON (fixp->fx_addsy))
22898 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22899 code = fixp->fx_r_type;
22903 case BFD_RELOC_ARM_IMMEDIATE:
22904 as_bad_where (fixp->fx_file, fixp->fx_line,
22905 _("internal relocation (type: IMMEDIATE) not fixed up"));
22908 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22909 as_bad_where (fixp->fx_file, fixp->fx_line,
22910 _("ADRL used for a symbol not defined in the same file"));
22913 case BFD_RELOC_ARM_OFFSET_IMM:
22914 if (section->use_rela_p)
22916 code = fixp->fx_r_type;
22920 if (fixp->fx_addsy != NULL
22921 && !S_IS_DEFINED (fixp->fx_addsy)
22922 && S_IS_LOCAL (fixp->fx_addsy))
22924 as_bad_where (fixp->fx_file, fixp->fx_line,
22925 _("undefined local label `%s'"),
22926 S_GET_NAME (fixp->fx_addsy));
22930 as_bad_where (fixp->fx_file, fixp->fx_line,
22931 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22938 switch (fixp->fx_r_type)
22940 case BFD_RELOC_NONE: type = "NONE"; break;
22941 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22942 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22943 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22944 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22945 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22946 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22947 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22948 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22949 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22950 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22951 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22952 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22953 default: type = _("<unknown>"); break;
22955 as_bad_where (fixp->fx_file, fixp->fx_line,
22956 _("cannot represent %s relocation in this object file format"),
22963 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22965 && fixp->fx_addsy == GOT_symbol)
22967 code = BFD_RELOC_ARM_GOTPC;
22968 reloc->addend = fixp->fx_offset = reloc->address;
22972 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22974 if (reloc->howto == NULL)
22976 as_bad_where (fixp->fx_file, fixp->fx_line,
22977 _("cannot represent %s relocation in this object file format"),
22978 bfd_get_reloc_code_name (code));
22982 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22983 vtable entry to be used in the relocation's section offset. */
22984 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22985 reloc->address = fixp->fx_offset;
22990 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22993 cons_fix_new_arm (fragS * frag,
22998 bfd_reloc_code_real_type type;
23002 FIXME: @@ Should look at CPU word size. */
23006 type = BFD_RELOC_8;
23009 type = BFD_RELOC_16;
23013 type = BFD_RELOC_32;
23016 type = BFD_RELOC_64;
23021 if (exp->X_op == O_secrel)
23023 exp->X_op = O_symbol;
23024 type = BFD_RELOC_32_SECREL;
23028 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
23031 #if defined (OBJ_COFF)
23033 arm_validate_fix (fixS * fixP)
23035 /* If the destination of the branch is a defined symbol which does not have
23036 the THUMB_FUNC attribute, then we must be calling a function which has
23037 the (interfacearm) attribute. We look for the Thumb entry point to that
23038 function and change the branch to refer to that function instead. */
23039 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23040 && fixP->fx_addsy != NULL
23041 && S_IS_DEFINED (fixP->fx_addsy)
23042 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23044 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23051 arm_force_relocation (struct fix * fixp)
23053 #if defined (OBJ_COFF) && defined (TE_PE)
23054 if (fixp->fx_r_type == BFD_RELOC_RVA)
23058 /* In case we have a call or a branch to a function in ARM ISA mode from
23059 a thumb function or vice-versa force the relocation. These relocations
23060 are cleared off for some cores that might have blx and simple transformations
23064 switch (fixp->fx_r_type)
23066 case BFD_RELOC_ARM_PCREL_JUMP:
23067 case BFD_RELOC_ARM_PCREL_CALL:
23068 case BFD_RELOC_THUMB_PCREL_BLX:
23069 if (THUMB_IS_FUNC (fixp->fx_addsy))
23073 case BFD_RELOC_ARM_PCREL_BLX:
23074 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23075 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23076 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23077 if (ARM_IS_FUNC (fixp->fx_addsy))
23086 /* Resolve these relocations even if the symbol is extern or weak.
23087 Technically this is probably wrong due to symbol preemption.
23088 In practice these relocations do not have enough range to be useful
23089 at dynamic link time, and some code (e.g. in the Linux kernel)
23090 expects these references to be resolved. */
23091 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23092 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23093 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23094 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23095 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23096 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23097 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23098 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23099 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23100 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23101 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23102 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23103 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23104 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23107 /* Always leave these relocations for the linker. */
23108 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23109 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23110 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23113 /* Always generate relocations against function symbols. */
23114 if (fixp->fx_r_type == BFD_RELOC_32
23116 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23119 return generic_force_reloc (fixp);
23122 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23123 /* Relocations against function names must be left unadjusted,
23124 so that the linker can use this information to generate interworking
23125 stubs. The MIPS version of this function
23126 also prevents relocations that are mips-16 specific, but I do not
23127 know why it does this.
23130 There is one other problem that ought to be addressed here, but
23131 which currently is not: Taking the address of a label (rather
23132 than a function) and then later jumping to that address. Such
23133 addresses also ought to have their bottom bit set (assuming that
23134 they reside in Thumb code), but at the moment they will not. */
23137 arm_fix_adjustable (fixS * fixP)
23139 if (fixP->fx_addsy == NULL)
23142 /* Preserve relocations against symbols with function type. */
23143 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23146 if (THUMB_IS_FUNC (fixP->fx_addsy)
23147 && fixP->fx_subsy == NULL)
23150 /* We need the symbol name for the VTABLE entries. */
23151 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23152 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23155 /* Don't allow symbols to be discarded on GOT related relocs. */
23156 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23157 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23158 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23159 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23160 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23161 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23162 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23163 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23164 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23165 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23166 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23167 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23168 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23169 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23172 /* Similarly for group relocations. */
23173 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23174 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23175 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23178 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23179 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23180 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23181 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23182 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23183 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23184 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23185 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23186 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23191 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23196 elf32_arm_target_format (void)
23199 return (target_big_endian
23200 ? "elf32-bigarm-symbian"
23201 : "elf32-littlearm-symbian");
23202 #elif defined (TE_VXWORKS)
23203 return (target_big_endian
23204 ? "elf32-bigarm-vxworks"
23205 : "elf32-littlearm-vxworks");
23206 #elif defined (TE_NACL)
23207 return (target_big_endian
23208 ? "elf32-bigarm-nacl"
23209 : "elf32-littlearm-nacl");
23211 if (target_big_endian)
23212 return "elf32-bigarm";
23214 return "elf32-littlearm";
23219 armelf_frob_symbol (symbolS * symp,
23222 elf_frob_symbol (symp, puntp);
23226 /* MD interface: Finalization. */
23231 literal_pool * pool;
23233 /* Ensure that all the IT blocks are properly closed. */
23234 check_it_blocks_finished ();
23236 for (pool = list_of_pools; pool; pool = pool->next)
23238 /* Put it at the end of the relevant section. */
23239 subseg_set (pool->section, pool->sub_section);
23241 arm_elf_change_section ();
23248 /* Remove any excess mapping symbols generated for alignment frags in
23249 SEC. We may have created a mapping symbol before a zero byte
23250 alignment; remove it if there's a mapping symbol after the
23253 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23254 void *dummy ATTRIBUTE_UNUSED)
23256 segment_info_type *seginfo = seg_info (sec);
23259 if (seginfo == NULL || seginfo->frchainP == NULL)
23262 for (fragp = seginfo->frchainP->frch_root;
23264 fragp = fragp->fr_next)
23266 symbolS *sym = fragp->tc_frag_data.last_map;
23267 fragS *next = fragp->fr_next;
23269 /* Variable-sized frags have been converted to fixed size by
23270 this point. But if this was variable-sized to start with,
23271 there will be a fixed-size frag after it. So don't handle
23273 if (sym == NULL || next == NULL)
23276 if (S_GET_VALUE (sym) < next->fr_address)
23277 /* Not at the end of this frag. */
23279 know (S_GET_VALUE (sym) == next->fr_address);
23283 if (next->tc_frag_data.first_map != NULL)
23285 /* Next frag starts with a mapping symbol. Discard this
23287 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23291 if (next->fr_next == NULL)
23293 /* This mapping symbol is at the end of the section. Discard
23295 know (next->fr_fix == 0 && next->fr_var == 0);
23296 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23300 /* As long as we have empty frags without any mapping symbols,
23302 /* If the next frag is non-empty and does not start with a
23303 mapping symbol, then this mapping symbol is required. */
23304 if (next->fr_address != next->fr_next->fr_address)
23307 next = next->fr_next;
23309 while (next != NULL);
23314 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23318 arm_adjust_symtab (void)
23323 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23325 if (ARM_IS_THUMB (sym))
23327 if (THUMB_IS_FUNC (sym))
23329 /* Mark the symbol as a Thumb function. */
23330 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23331 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23332 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23334 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23335 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23337 as_bad (_("%s: unexpected function type: %d"),
23338 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23340 else switch (S_GET_STORAGE_CLASS (sym))
23343 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23346 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23349 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23357 if (ARM_IS_INTERWORK (sym))
23358 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23365 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23367 if (ARM_IS_THUMB (sym))
23369 elf_symbol_type * elf_sym;
23371 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23372 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23374 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23375 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23377 /* If it's a .thumb_func, declare it as so,
23378 otherwise tag label as .code 16. */
23379 if (THUMB_IS_FUNC (sym))
23380 elf_sym->internal_elf_sym.st_target_internal
23381 = ST_BRANCH_TO_THUMB;
23382 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23383 elf_sym->internal_elf_sym.st_info =
23384 ELF_ST_INFO (bind, STT_ARM_16BIT);
23389 /* Remove any overlapping mapping symbols generated by alignment frags. */
23390 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23391 /* Now do generic ELF adjustments. */
23392 elf_adjust_symtab ();
23396 /* MD interface: Initialization. */
23399 set_constant_flonums (void)
23403 for (i = 0; i < NUM_FLOAT_VALS; i++)
23404 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23408 /* Auto-select Thumb mode if it's the only available instruction set for the
23409 given architecture. */
23412 autoselect_thumb_from_cpu_variant (void)
23414 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23415 opcode_select (16);
23424 if ( (arm_ops_hsh = hash_new ()) == NULL
23425 || (arm_cond_hsh = hash_new ()) == NULL
23426 || (arm_shift_hsh = hash_new ()) == NULL
23427 || (arm_psr_hsh = hash_new ()) == NULL
23428 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23429 || (arm_reg_hsh = hash_new ()) == NULL
23430 || (arm_reloc_hsh = hash_new ()) == NULL
23431 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23432 as_fatal (_("virtual memory exhausted"));
23434 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23435 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23436 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23437 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23438 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23439 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23440 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23441 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23442 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23443 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23444 (void *) (v7m_psrs + i));
23445 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23446 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23448 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23450 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23451 (void *) (barrier_opt_names + i));
23453 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23455 struct reloc_entry * entry = reloc_names + i;
23457 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23458 /* This makes encode_branch() use the EABI versions of this relocation. */
23459 entry->reloc = BFD_RELOC_UNUSED;
23461 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23465 set_constant_flonums ();
23467 /* Set the cpu variant based on the command-line options. We prefer
23468 -mcpu= over -march= if both are set (as for GCC); and we prefer
23469 -mfpu= over any other way of setting the floating point unit.
23470 Use of legacy options with new options are faulted. */
23473 if (mcpu_cpu_opt || march_cpu_opt)
23474 as_bad (_("use of old and new-style options to set CPU type"));
23476 mcpu_cpu_opt = legacy_cpu;
23478 else if (!mcpu_cpu_opt)
23479 mcpu_cpu_opt = march_cpu_opt;
23484 as_bad (_("use of old and new-style options to set FPU type"));
23486 mfpu_opt = legacy_fpu;
23488 else if (!mfpu_opt)
23490 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23491 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23492 /* Some environments specify a default FPU. If they don't, infer it
23493 from the processor. */
23495 mfpu_opt = mcpu_fpu_opt;
23497 mfpu_opt = march_fpu_opt;
23499 mfpu_opt = &fpu_default;
23505 if (mcpu_cpu_opt != NULL)
23506 mfpu_opt = &fpu_default;
23507 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23508 mfpu_opt = &fpu_arch_vfp_v2;
23510 mfpu_opt = &fpu_arch_fpa;
23516 mcpu_cpu_opt = &cpu_default;
23517 selected_cpu = cpu_default;
23521 selected_cpu = *mcpu_cpu_opt;
23523 mcpu_cpu_opt = &arm_arch_any;
23526 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23528 autoselect_thumb_from_cpu_variant ();
23530 arm_arch_used = thumb_arch_used = arm_arch_none;
23532 #if defined OBJ_COFF || defined OBJ_ELF
23534 unsigned int flags = 0;
23536 #if defined OBJ_ELF
23537 flags = meabi_flags;
23539 switch (meabi_flags)
23541 case EF_ARM_EABI_UNKNOWN:
23543 /* Set the flags in the private structure. */
23544 if (uses_apcs_26) flags |= F_APCS26;
23545 if (support_interwork) flags |= F_INTERWORK;
23546 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23547 if (pic_code) flags |= F_PIC;
23548 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23549 flags |= F_SOFT_FLOAT;
23551 switch (mfloat_abi_opt)
23553 case ARM_FLOAT_ABI_SOFT:
23554 case ARM_FLOAT_ABI_SOFTFP:
23555 flags |= F_SOFT_FLOAT;
23558 case ARM_FLOAT_ABI_HARD:
23559 if (flags & F_SOFT_FLOAT)
23560 as_bad (_("hard-float conflicts with specified fpu"));
23564 /* Using pure-endian doubles (even if soft-float). */
23565 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23566 flags |= F_VFP_FLOAT;
23568 #if defined OBJ_ELF
23569 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23570 flags |= EF_ARM_MAVERICK_FLOAT;
23573 case EF_ARM_EABI_VER4:
23574 case EF_ARM_EABI_VER5:
23575 /* No additional flags to set. */
23582 bfd_set_private_flags (stdoutput, flags);
23584 /* We have run out flags in the COFF header to encode the
23585 status of ATPCS support, so instead we create a dummy,
23586 empty, debug section called .arm.atpcs. */
23591 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23595 bfd_set_section_flags
23596 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23597 bfd_set_section_size (stdoutput, sec, 0);
23598 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23604 /* Record the CPU type as well. */
23605 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23606 mach = bfd_mach_arm_iWMMXt2;
23607 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23608 mach = bfd_mach_arm_iWMMXt;
23609 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23610 mach = bfd_mach_arm_XScale;
23611 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23612 mach = bfd_mach_arm_ep9312;
23613 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23614 mach = bfd_mach_arm_5TE;
23615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23617 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23618 mach = bfd_mach_arm_5T;
23620 mach = bfd_mach_arm_5;
23622 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23624 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23625 mach = bfd_mach_arm_4T;
23627 mach = bfd_mach_arm_4;
23629 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23630 mach = bfd_mach_arm_3M;
23631 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23632 mach = bfd_mach_arm_3;
23633 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23634 mach = bfd_mach_arm_2a;
23635 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23636 mach = bfd_mach_arm_2;
23638 mach = bfd_mach_arm_unknown;
23640 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23643 /* Command line processing. */
23646 Invocation line includes a switch not recognized by the base assembler.
23647 See if it's a processor-specific option.
23649 This routine is somewhat complicated by the need for backwards
23650 compatibility (since older releases of gcc can't be changed).
23651 The new options try to make the interface as compatible as
23654 New options (supported) are:
23656 -mcpu=<cpu name> Assemble for selected processor
23657 -march=<architecture name> Assemble for selected architecture
23658 -mfpu=<fpu architecture> Assemble for selected FPU.
23659 -EB/-mbig-endian Big-endian
23660 -EL/-mlittle-endian Little-endian
23661 -k Generate PIC code
23662 -mthumb Start in Thumb mode
23663 -mthumb-interwork Code supports ARM/Thumb interworking
23665 -m[no-]warn-deprecated Warn about deprecated features
23667 For now we will also provide support for:
23669 -mapcs-32 32-bit Program counter
23670 -mapcs-26 26-bit Program counter
23671 -macps-float Floats passed in FP registers
23672 -mapcs-reentrant Reentrant code
23674 (sometime these will probably be replaced with -mapcs=<list of options>
23675 and -matpcs=<list of options>)
23677 The remaining options are only supported for back-wards compatibility.
23678 Cpu variants, the arm part is optional:
23679 -m[arm]1 Currently not supported.
23680 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23681 -m[arm]3 Arm 3 processor
23682 -m[arm]6[xx], Arm 6 processors
23683 -m[arm]7[xx][t][[d]m] Arm 7 processors
23684 -m[arm]8[10] Arm 8 processors
23685 -m[arm]9[20][tdmi] Arm 9 processors
23686 -mstrongarm[110[0]] StrongARM processors
23687 -mxscale XScale processors
23688 -m[arm]v[2345[t[e]]] Arm architectures
23689 -mall All (except the ARM1)
23691 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23692 -mfpe-old (No float load/store multiples)
23693 -mvfpxd VFP Single precision
23695 -mno-fpu Disable all floating point instructions
23697 The following CPU names are recognized:
23698 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23699 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23700 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23701 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23702 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23703 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23704 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23708 const char * md_shortopts = "m:k";
23710 #ifdef ARM_BI_ENDIAN
23711 #define OPTION_EB (OPTION_MD_BASE + 0)
23712 #define OPTION_EL (OPTION_MD_BASE + 1)
23714 #if TARGET_BYTES_BIG_ENDIAN
23715 #define OPTION_EB (OPTION_MD_BASE + 0)
23717 #define OPTION_EL (OPTION_MD_BASE + 1)
23720 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23722 struct option md_longopts[] =
23725 {"EB", no_argument, NULL, OPTION_EB},
23728 {"EL", no_argument, NULL, OPTION_EL},
23730 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23731 {NULL, no_argument, NULL, 0}
23734 size_t md_longopts_size = sizeof (md_longopts);
23736 struct arm_option_table
23738 char *option; /* Option name to match. */
23739 char *help; /* Help information. */
23740 int *var; /* Variable to change. */
23741 int value; /* What to change it to. */
23742 char *deprecated; /* If non-null, print this message. */
23745 struct arm_option_table arm_opts[] =
23747 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23748 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23749 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23750 &support_interwork, 1, NULL},
23751 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23752 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23753 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23755 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23756 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23757 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23758 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23761 /* These are recognized by the assembler, but have no affect on code. */
23762 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23763 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23765 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23766 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23767 &warn_on_deprecated, 0, NULL},
23768 {NULL, NULL, NULL, 0, NULL}
23771 struct arm_legacy_option_table
23773 char *option; /* Option name to match. */
23774 const arm_feature_set **var; /* Variable to change. */
23775 const arm_feature_set value; /* What to change it to. */
23776 char *deprecated; /* If non-null, print this message. */
23779 const struct arm_legacy_option_table arm_legacy_opts[] =
23781 /* DON'T add any new processors to this list -- we want the whole list
23782 to go away... Add them to the processors table instead. */
23783 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23784 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23785 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23786 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23787 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23788 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23789 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23790 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23791 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23792 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23793 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23794 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23795 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23796 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23797 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23798 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23799 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23800 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23801 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23802 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23803 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23804 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23805 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23806 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23807 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23808 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23809 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23810 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23811 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23812 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23813 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23814 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23815 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23816 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23817 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23818 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23819 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23820 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23821 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23822 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23823 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23824 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23825 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23826 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23827 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23828 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23829 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23830 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23831 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23832 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23833 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23834 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23835 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23836 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23837 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23838 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23839 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23840 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23841 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23842 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23843 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23844 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23845 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23846 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23847 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23848 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23849 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23850 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23851 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23852 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23853 N_("use -mcpu=strongarm110")},
23854 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23855 N_("use -mcpu=strongarm1100")},
23856 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23857 N_("use -mcpu=strongarm1110")},
23858 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23859 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23860 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23862 /* Architecture variants -- don't add any more to this list either. */
23863 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23864 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23865 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23866 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23867 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23868 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23869 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23870 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23871 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23872 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23873 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23874 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23875 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23876 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23877 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23878 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23879 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23880 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23882 /* Floating point variants -- don't add any more to this list either. */
23883 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23884 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23885 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23886 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23887 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23889 {NULL, NULL, ARM_ARCH_NONE, NULL}
23892 struct arm_cpu_option_table
23896 const arm_feature_set value;
23897 /* For some CPUs we assume an FPU unless the user explicitly sets
23899 const arm_feature_set default_fpu;
23900 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23902 const char *canonical_name;
23905 /* This list should, at a minimum, contain all the cpu names
23906 recognized by GCC. */
23907 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23908 static const struct arm_cpu_option_table arm_cpus[] =
23910 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23911 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23912 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23913 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23914 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23915 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23916 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23917 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23918 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23919 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23920 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23921 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23922 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23923 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23924 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23925 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23926 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23927 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23928 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23929 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23930 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23931 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23932 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23933 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23934 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23935 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23936 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23937 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23938 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23939 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23940 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23941 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23942 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23943 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23944 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23945 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23946 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23947 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23948 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23949 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23950 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23951 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23952 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23953 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23954 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23955 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23956 /* For V5 or later processors we default to using VFP; but the user
23957 should really set the FPU type explicitly. */
23958 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23959 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23960 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23961 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23962 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23963 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23964 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23965 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23966 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23967 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23968 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23969 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23970 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23971 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23972 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23973 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23974 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23975 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23976 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23977 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23979 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23980 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23981 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23982 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23983 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23984 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23985 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23986 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23987 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23989 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23990 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23991 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23992 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23993 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23994 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23995 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23996 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23997 FPU_NONE, "Cortex-A5"),
23998 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23999 FPU_ARCH_NEON_VFP_V4,
24001 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
24002 ARM_FEATURE (0, FPU_VFP_V3
24003 | FPU_NEON_EXT_V1),
24005 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
24006 ARM_FEATURE (0, FPU_VFP_V3
24007 | FPU_NEON_EXT_V1),
24009 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
24010 FPU_ARCH_NEON_VFP_V4,
24012 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
24013 FPU_ARCH_NEON_VFP_V4,
24015 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24017 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24019 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
24020 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24022 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24023 FPU_NONE, "Cortex-R5"),
24024 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24025 FPU_ARCH_VFP_V3D16,
24027 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24028 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24029 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24030 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
24031 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
24032 /* ??? XSCALE is really an architecture. */
24033 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24034 /* ??? iwmmxt is not a processor. */
24035 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24036 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24037 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24039 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24040 FPU_ARCH_MAVERICK, "ARM920T"),
24041 /* Marvell processors. */
24042 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
24043 FPU_ARCH_VFP_V3D16, NULL),
24045 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24049 struct arm_arch_option_table
24053 const arm_feature_set value;
24054 const arm_feature_set default_fpu;
24057 /* This list should, at a minimum, contain all the architecture names
24058 recognized by GCC. */
24059 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24060 static const struct arm_arch_option_table arm_archs[] =
24062 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24063 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24064 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24065 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24066 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24067 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24068 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24069 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24070 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24071 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24072 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24073 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24074 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24075 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24076 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24077 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24078 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24079 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24080 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24081 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24082 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24083 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24084 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24085 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24086 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24087 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24088 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24089 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24090 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24091 /* The official spelling of the ARMv7 profile variants is the dashed form.
24092 Accept the non-dashed form for compatibility with old toolchains. */
24093 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24094 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24095 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24096 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24097 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24098 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24099 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24100 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24101 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24102 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24103 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24104 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24106 #undef ARM_ARCH_OPT
24108 /* ISA extensions in the co-processor and main instruction set space. */
24109 struct arm_option_extension_value_table
24113 const arm_feature_set value;
24114 const arm_feature_set allowed_archs;
24117 /* The following table must be in alphabetical order with a NULL last entry.
24119 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24120 static const struct arm_option_extension_value_table arm_extensions[] =
24122 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24123 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24124 ARM_FEATURE (ARM_EXT_V8, 0)),
24125 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24126 ARM_FEATURE (ARM_EXT_V8, 0)),
24127 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24128 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24129 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24130 ARM_EXT_OPT ("iwmmxt2",
24131 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24132 ARM_EXT_OPT ("maverick",
24133 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24134 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24135 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24136 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24137 ARM_FEATURE (ARM_EXT_V8, 0)),
24138 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24139 ARM_FEATURE (ARM_EXT_V6M, 0)),
24140 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24141 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24142 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24144 ARM_FEATURE (ARM_EXT_V7A, 0)),
24145 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24146 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24150 /* ISA floating-point and Advanced SIMD extensions. */
24151 struct arm_option_fpu_value_table
24154 const arm_feature_set value;
24157 /* This list should, at a minimum, contain all the fpu names
24158 recognized by GCC. */
24159 static const struct arm_option_fpu_value_table arm_fpus[] =
24161 {"softfpa", FPU_NONE},
24162 {"fpe", FPU_ARCH_FPE},
24163 {"fpe2", FPU_ARCH_FPE},
24164 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24165 {"fpa", FPU_ARCH_FPA},
24166 {"fpa10", FPU_ARCH_FPA},
24167 {"fpa11", FPU_ARCH_FPA},
24168 {"arm7500fe", FPU_ARCH_FPA},
24169 {"softvfp", FPU_ARCH_VFP},
24170 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24171 {"vfp", FPU_ARCH_VFP_V2},
24172 {"vfp9", FPU_ARCH_VFP_V2},
24173 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24174 {"vfp10", FPU_ARCH_VFP_V2},
24175 {"vfp10-r0", FPU_ARCH_VFP_V1},
24176 {"vfpxd", FPU_ARCH_VFP_V1xD},
24177 {"vfpv2", FPU_ARCH_VFP_V2},
24178 {"vfpv3", FPU_ARCH_VFP_V3},
24179 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24180 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24181 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24182 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24183 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24184 {"arm1020t", FPU_ARCH_VFP_V1},
24185 {"arm1020e", FPU_ARCH_VFP_V2},
24186 {"arm1136jfs", FPU_ARCH_VFP_V2},
24187 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24188 {"maverick", FPU_ARCH_MAVERICK},
24189 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24190 {"neon-fp16", FPU_ARCH_NEON_FP16},
24191 {"vfpv4", FPU_ARCH_VFP_V4},
24192 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24193 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24194 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24195 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24196 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24197 {"crypto-neon-fp-armv8",
24198 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24199 {NULL, ARM_ARCH_NONE}
24202 struct arm_option_value_table
24208 static const struct arm_option_value_table arm_float_abis[] =
24210 {"hard", ARM_FLOAT_ABI_HARD},
24211 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24212 {"soft", ARM_FLOAT_ABI_SOFT},
24217 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24218 static const struct arm_option_value_table arm_eabis[] =
24220 {"gnu", EF_ARM_EABI_UNKNOWN},
24221 {"4", EF_ARM_EABI_VER4},
24222 {"5", EF_ARM_EABI_VER5},
24227 struct arm_long_option_table
24229 char * option; /* Substring to match. */
24230 char * help; /* Help information. */
24231 int (* func) (char * subopt); /* Function to decode sub-option. */
24232 char * deprecated; /* If non-null, print this message. */
24236 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24238 arm_feature_set *ext_set = (arm_feature_set *)
24239 xmalloc (sizeof (arm_feature_set));
24241 /* We insist on extensions being specified in alphabetical order, and with
24242 extensions being added before being removed. We achieve this by having
24243 the global ARM_EXTENSIONS table in alphabetical order, and using the
24244 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24245 or removing it (0) and only allowing it to change in the order
24247 const struct arm_option_extension_value_table * opt = NULL;
24248 int adding_value = -1;
24250 /* Copy the feature set, so that we can modify it. */
24251 *ext_set = **opt_p;
24254 while (str != NULL && *str != 0)
24261 as_bad (_("invalid architectural extension"));
24266 ext = strchr (str, '+');
24271 len = strlen (str);
24273 if (len >= 2 && strncmp (str, "no", 2) == 0)
24275 if (adding_value != 0)
24278 opt = arm_extensions;
24286 if (adding_value == -1)
24289 opt = arm_extensions;
24291 else if (adding_value != 1)
24293 as_bad (_("must specify extensions to add before specifying "
24294 "those to remove"));
24301 as_bad (_("missing architectural extension"));
24305 gas_assert (adding_value != -1);
24306 gas_assert (opt != NULL);
24308 /* Scan over the options table trying to find an exact match. */
24309 for (; opt->name != NULL; opt++)
24310 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24312 /* Check we can apply the extension to this architecture. */
24313 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24315 as_bad (_("extension does not apply to the base architecture"));
24319 /* Add or remove the extension. */
24321 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24323 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24328 if (opt->name == NULL)
24330 /* Did we fail to find an extension because it wasn't specified in
24331 alphabetical order, or because it does not exist? */
24333 for (opt = arm_extensions; opt->name != NULL; opt++)
24334 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24337 if (opt->name == NULL)
24338 as_bad (_("unknown architectural extension `%s'"), str);
24340 as_bad (_("architectural extensions must be specified in "
24341 "alphabetical order"));
24347 /* We should skip the extension we've just matched the next time
24359 arm_parse_cpu (char *str)
24361 const struct arm_cpu_option_table *opt;
24362 char *ext = strchr (str, '+');
24368 len = strlen (str);
24372 as_bad (_("missing cpu name `%s'"), str);
24376 for (opt = arm_cpus; opt->name != NULL; opt++)
24377 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24379 mcpu_cpu_opt = &opt->value;
24380 mcpu_fpu_opt = &opt->default_fpu;
24381 if (opt->canonical_name)
24382 strcpy (selected_cpu_name, opt->canonical_name);
24387 for (i = 0; i < len; i++)
24388 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24389 selected_cpu_name[i] = 0;
24393 return arm_parse_extension (ext, &mcpu_cpu_opt);
24398 as_bad (_("unknown cpu `%s'"), str);
24403 arm_parse_arch (char *str)
24405 const struct arm_arch_option_table *opt;
24406 char *ext = strchr (str, '+');
24412 len = strlen (str);
24416 as_bad (_("missing architecture name `%s'"), str);
24420 for (opt = arm_archs; opt->name != NULL; opt++)
24421 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24423 march_cpu_opt = &opt->value;
24424 march_fpu_opt = &opt->default_fpu;
24425 strcpy (selected_cpu_name, opt->name);
24428 return arm_parse_extension (ext, &march_cpu_opt);
24433 as_bad (_("unknown architecture `%s'\n"), str);
24438 arm_parse_fpu (char * str)
24440 const struct arm_option_fpu_value_table * opt;
24442 for (opt = arm_fpus; opt->name != NULL; opt++)
24443 if (streq (opt->name, str))
24445 mfpu_opt = &opt->value;
24449 as_bad (_("unknown floating point format `%s'\n"), str);
24454 arm_parse_float_abi (char * str)
24456 const struct arm_option_value_table * opt;
24458 for (opt = arm_float_abis; opt->name != NULL; opt++)
24459 if (streq (opt->name, str))
24461 mfloat_abi_opt = opt->value;
24465 as_bad (_("unknown floating point abi `%s'\n"), str);
24471 arm_parse_eabi (char * str)
24473 const struct arm_option_value_table *opt;
24475 for (opt = arm_eabis; opt->name != NULL; opt++)
24476 if (streq (opt->name, str))
24478 meabi_flags = opt->value;
24481 as_bad (_("unknown EABI `%s'\n"), str);
24487 arm_parse_it_mode (char * str)
24489 bfd_boolean ret = TRUE;
24491 if (streq ("arm", str))
24492 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24493 else if (streq ("thumb", str))
24494 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24495 else if (streq ("always", str))
24496 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24497 else if (streq ("never", str))
24498 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24501 as_bad (_("unknown implicit IT mode `%s', should be "\
24502 "arm, thumb, always, or never."), str);
24509 struct arm_long_option_table arm_long_opts[] =
24511 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24512 arm_parse_cpu, NULL},
24513 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24514 arm_parse_arch, NULL},
24515 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24516 arm_parse_fpu, NULL},
24517 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24518 arm_parse_float_abi, NULL},
24520 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24521 arm_parse_eabi, NULL},
24523 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24524 arm_parse_it_mode, NULL},
24525 {NULL, NULL, 0, NULL}
24529 md_parse_option (int c, char * arg)
24531 struct arm_option_table *opt;
24532 const struct arm_legacy_option_table *fopt;
24533 struct arm_long_option_table *lopt;
24539 target_big_endian = 1;
24545 target_big_endian = 0;
24549 case OPTION_FIX_V4BX:
24554 /* Listing option. Just ignore these, we don't support additional
24559 for (opt = arm_opts; opt->option != NULL; opt++)
24561 if (c == opt->option[0]
24562 && ((arg == NULL && opt->option[1] == 0)
24563 || streq (arg, opt->option + 1)))
24565 /* If the option is deprecated, tell the user. */
24566 if (warn_on_deprecated && opt->deprecated != NULL)
24567 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24568 arg ? arg : "", _(opt->deprecated));
24570 if (opt->var != NULL)
24571 *opt->var = opt->value;
24577 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24579 if (c == fopt->option[0]
24580 && ((arg == NULL && fopt->option[1] == 0)
24581 || streq (arg, fopt->option + 1)))
24583 /* If the option is deprecated, tell the user. */
24584 if (warn_on_deprecated && fopt->deprecated != NULL)
24585 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24586 arg ? arg : "", _(fopt->deprecated));
24588 if (fopt->var != NULL)
24589 *fopt->var = &fopt->value;
24595 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24597 /* These options are expected to have an argument. */
24598 if (c == lopt->option[0]
24600 && strncmp (arg, lopt->option + 1,
24601 strlen (lopt->option + 1)) == 0)
24603 /* If the option is deprecated, tell the user. */
24604 if (warn_on_deprecated && lopt->deprecated != NULL)
24605 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24606 _(lopt->deprecated));
24608 /* Call the sup-option parser. */
24609 return lopt->func (arg + strlen (lopt->option) - 1);
24620 md_show_usage (FILE * fp)
24622 struct arm_option_table *opt;
24623 struct arm_long_option_table *lopt;
24625 fprintf (fp, _(" ARM-specific assembler options:\n"));
24627 for (opt = arm_opts; opt->option != NULL; opt++)
24628 if (opt->help != NULL)
24629 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24631 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24632 if (lopt->help != NULL)
24633 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24637 -EB assemble code for a big-endian cpu\n"));
24642 -EL assemble code for a little-endian cpu\n"));
24646 --fix-v4bx Allow BX in ARMv4 code\n"));
24654 arm_feature_set flags;
24655 } cpu_arch_ver_table;
24657 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24658 least features first. */
24659 static const cpu_arch_ver_table cpu_arch_ver[] =
24665 {4, ARM_ARCH_V5TE},
24666 {5, ARM_ARCH_V5TEJ},
24670 {11, ARM_ARCH_V6M},
24671 {12, ARM_ARCH_V6SM},
24672 {8, ARM_ARCH_V6T2},
24673 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24674 {10, ARM_ARCH_V7R},
24675 {10, ARM_ARCH_V7M},
24676 {14, ARM_ARCH_V8A},
24680 /* Set an attribute if it has not already been set by the user. */
24682 aeabi_set_attribute_int (int tag, int value)
24685 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24686 || !attributes_set_explicitly[tag])
24687 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24691 aeabi_set_attribute_string (int tag, const char *value)
24694 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24695 || !attributes_set_explicitly[tag])
24696 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24699 /* Set the public EABI object attributes. */
24701 aeabi_set_public_attributes (void)
24706 int fp16_optional = 0;
24707 arm_feature_set flags;
24708 arm_feature_set tmp;
24709 const cpu_arch_ver_table *p;
24711 /* Choose the architecture based on the capabilities of the requested cpu
24712 (if any) and/or the instructions actually used. */
24713 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24714 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24715 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24717 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24718 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24720 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24721 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24723 /* Allow the user to override the reported architecture. */
24726 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24727 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24730 /* We need to make sure that the attributes do not identify us as v6S-M
24731 when the only v6S-M feature in use is the Operating System Extensions. */
24732 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24733 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24734 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24738 for (p = cpu_arch_ver; p->val; p++)
24740 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24743 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24747 /* The table lookup above finds the last architecture to contribute
24748 a new feature. Unfortunately, Tag13 is a subset of the union of
24749 v6T2 and v7-M, so it is never seen as contributing a new feature.
24750 We can not search for the last entry which is entirely used,
24751 because if no CPU is specified we build up only those flags
24752 actually used. Perhaps we should separate out the specified
24753 and implicit cases. Avoid taking this path for -march=all by
24754 checking for contradictory v7-A / v7-M features. */
24756 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24757 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24758 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24761 /* Tag_CPU_name. */
24762 if (selected_cpu_name[0])
24766 q = selected_cpu_name;
24767 if (strncmp (q, "armv", 4) == 0)
24772 for (i = 0; q[i]; i++)
24773 q[i] = TOUPPER (q[i]);
24775 aeabi_set_attribute_string (Tag_CPU_name, q);
24778 /* Tag_CPU_arch. */
24779 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24781 /* Tag_CPU_arch_profile. */
24782 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24784 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24786 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24791 if (profile != '\0')
24792 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24794 /* Tag_ARM_ISA_use. */
24795 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24797 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24799 /* Tag_THUMB_ISA_use. */
24800 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24802 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24803 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24805 /* Tag_VFP_arch. */
24806 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24807 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24808 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24809 aeabi_set_attribute_int (Tag_VFP_arch,
24810 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24812 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24815 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24817 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24819 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24822 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24823 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24824 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24825 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24826 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24828 /* Tag_ABI_HardFP_use. */
24829 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24830 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24831 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24833 /* Tag_WMMX_arch. */
24834 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24835 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24836 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24837 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24839 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24840 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24841 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24842 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24844 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24846 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24850 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24855 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24856 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24857 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24861 We set Tag_DIV_use to two when integer divide instructions have been used
24862 in ARM state, or when Thumb integer divide instructions have been used,
24863 but we have no architecture profile set, nor have we any ARM instructions.
24865 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24868 For new architectures we will have to check these tests. */
24869 gas_assert (arch <= TAG_CPU_ARCH_V8);
24870 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24871 aeabi_set_attribute_int (Tag_DIV_use, 0);
24872 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24873 || (profile == '\0'
24874 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24875 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24876 aeabi_set_attribute_int (Tag_DIV_use, 2);
24878 /* Tag_MP_extension_use. */
24879 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24880 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24882 /* Tag Virtualization_use. */
24883 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24885 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24888 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24891 /* Add the default contents for the .ARM.attributes section. */
24895 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24898 aeabi_set_public_attributes ();
24900 #endif /* OBJ_ELF */
24903 /* Parse a .cpu directive. */
24906 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24908 const struct arm_cpu_option_table *opt;
24912 name = input_line_pointer;
24913 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24914 input_line_pointer++;
24915 saved_char = *input_line_pointer;
24916 *input_line_pointer = 0;
24918 /* Skip the first "all" entry. */
24919 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24920 if (streq (opt->name, name))
24922 mcpu_cpu_opt = &opt->value;
24923 selected_cpu = opt->value;
24924 if (opt->canonical_name)
24925 strcpy (selected_cpu_name, opt->canonical_name);
24929 for (i = 0; opt->name[i]; i++)
24930 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24932 selected_cpu_name[i] = 0;
24934 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24935 *input_line_pointer = saved_char;
24936 demand_empty_rest_of_line ();
24939 as_bad (_("unknown cpu `%s'"), name);
24940 *input_line_pointer = saved_char;
24941 ignore_rest_of_line ();
24945 /* Parse a .arch directive. */
24948 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24950 const struct arm_arch_option_table *opt;
24954 name = input_line_pointer;
24955 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24956 input_line_pointer++;
24957 saved_char = *input_line_pointer;
24958 *input_line_pointer = 0;
24960 /* Skip the first "all" entry. */
24961 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24962 if (streq (opt->name, name))
24964 mcpu_cpu_opt = &opt->value;
24965 selected_cpu = opt->value;
24966 strcpy (selected_cpu_name, opt->name);
24967 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24968 *input_line_pointer = saved_char;
24969 demand_empty_rest_of_line ();
24973 as_bad (_("unknown architecture `%s'\n"), name);
24974 *input_line_pointer = saved_char;
24975 ignore_rest_of_line ();
24979 /* Parse a .object_arch directive. */
24982 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24984 const struct arm_arch_option_table *opt;
24988 name = input_line_pointer;
24989 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24990 input_line_pointer++;
24991 saved_char = *input_line_pointer;
24992 *input_line_pointer = 0;
24994 /* Skip the first "all" entry. */
24995 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24996 if (streq (opt->name, name))
24998 object_arch = &opt->value;
24999 *input_line_pointer = saved_char;
25000 demand_empty_rest_of_line ();
25004 as_bad (_("unknown architecture `%s'\n"), name);
25005 *input_line_pointer = saved_char;
25006 ignore_rest_of_line ();
25009 /* Parse a .arch_extension directive. */
25012 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
25014 const struct arm_option_extension_value_table *opt;
25017 int adding_value = 1;
25019 name = input_line_pointer;
25020 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25021 input_line_pointer++;
25022 saved_char = *input_line_pointer;
25023 *input_line_pointer = 0;
25025 if (strlen (name) >= 2
25026 && strncmp (name, "no", 2) == 0)
25032 for (opt = arm_extensions; opt->name != NULL; opt++)
25033 if (streq (opt->name, name))
25035 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25037 as_bad (_("architectural extension `%s' is not allowed for the "
25038 "current base architecture"), name);
25043 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25045 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25047 mcpu_cpu_opt = &selected_cpu;
25048 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25049 *input_line_pointer = saved_char;
25050 demand_empty_rest_of_line ();
25054 if (opt->name == NULL)
25055 as_bad (_("unknown architecture extension `%s'\n"), name);
25057 *input_line_pointer = saved_char;
25058 ignore_rest_of_line ();
25061 /* Parse a .fpu directive. */
25064 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25066 const struct arm_option_fpu_value_table *opt;
25070 name = input_line_pointer;
25071 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25072 input_line_pointer++;
25073 saved_char = *input_line_pointer;
25074 *input_line_pointer = 0;
25076 for (opt = arm_fpus; opt->name != NULL; opt++)
25077 if (streq (opt->name, name))
25079 mfpu_opt = &opt->value;
25080 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25081 *input_line_pointer = saved_char;
25082 demand_empty_rest_of_line ();
25086 as_bad (_("unknown floating point format `%s'\n"), name);
25087 *input_line_pointer = saved_char;
25088 ignore_rest_of_line ();
25091 /* Copy symbol information. */
25094 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25096 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25100 /* Given a symbolic attribute NAME, return the proper integer value.
25101 Returns -1 if the attribute is not known. */
25104 arm_convert_symbolic_attribute (const char *name)
25106 static const struct
25111 attribute_table[] =
25113 /* When you modify this table you should
25114 also modify the list in doc/c-arm.texi. */
25115 #define T(tag) {#tag, tag}
25116 T (Tag_CPU_raw_name),
25119 T (Tag_CPU_arch_profile),
25120 T (Tag_ARM_ISA_use),
25121 T (Tag_THUMB_ISA_use),
25125 T (Tag_Advanced_SIMD_arch),
25126 T (Tag_PCS_config),
25127 T (Tag_ABI_PCS_R9_use),
25128 T (Tag_ABI_PCS_RW_data),
25129 T (Tag_ABI_PCS_RO_data),
25130 T (Tag_ABI_PCS_GOT_use),
25131 T (Tag_ABI_PCS_wchar_t),
25132 T (Tag_ABI_FP_rounding),
25133 T (Tag_ABI_FP_denormal),
25134 T (Tag_ABI_FP_exceptions),
25135 T (Tag_ABI_FP_user_exceptions),
25136 T (Tag_ABI_FP_number_model),
25137 T (Tag_ABI_align_needed),
25138 T (Tag_ABI_align8_needed),
25139 T (Tag_ABI_align_preserved),
25140 T (Tag_ABI_align8_preserved),
25141 T (Tag_ABI_enum_size),
25142 T (Tag_ABI_HardFP_use),
25143 T (Tag_ABI_VFP_args),
25144 T (Tag_ABI_WMMX_args),
25145 T (Tag_ABI_optimization_goals),
25146 T (Tag_ABI_FP_optimization_goals),
25147 T (Tag_compatibility),
25148 T (Tag_CPU_unaligned_access),
25149 T (Tag_FP_HP_extension),
25150 T (Tag_VFP_HP_extension),
25151 T (Tag_ABI_FP_16bit_format),
25152 T (Tag_MPextension_use),
25154 T (Tag_nodefaults),
25155 T (Tag_also_compatible_with),
25156 T (Tag_conformance),
25158 T (Tag_Virtualization_use),
25159 /* We deliberately do not include Tag_MPextension_use_legacy. */
25167 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25168 if (streq (name, attribute_table[i].name))
25169 return attribute_table[i].tag;
25175 /* Apply sym value for relocations only in the case that
25176 they are for local symbols and you have the respective
25177 architectural feature for blx and simple switches. */
25179 arm_apply_sym_value (struct fix * fixP)
25182 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25183 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25185 switch (fixP->fx_r_type)
25187 case BFD_RELOC_ARM_PCREL_BLX:
25188 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25189 if (ARM_IS_FUNC (fixP->fx_addsy))
25193 case BFD_RELOC_ARM_PCREL_CALL:
25194 case BFD_RELOC_THUMB_PCREL_BLX:
25195 if (THUMB_IS_FUNC (fixP->fx_addsy))
25206 #endif /* OBJ_ELF */