1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
337 enum neon_el_type type;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el[NEON_MAX_TYPE_ELS];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN /* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type;
389 enum it_instruction_type it_insn_type;
395 struct neon_type_el vectype;
396 unsigned present : 1; /* Operand present. */
397 unsigned isreg : 1; /* Operand was a register. */
398 unsigned immisreg : 1; /* .imm field is a second register. */
399 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle : 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc : 1; /* Operand has relocation suffix. */
409 unsigned writeback : 1; /* Operand has trailing ! */
410 unsigned preind : 1; /* Preindexed address. */
411 unsigned postind : 1; /* Postindexed address. */
412 unsigned negative : 1; /* Index register was negated. */
413 unsigned shifted : 1; /* Shift applied to operation. */
414 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
415 } operands[ARM_IT_MAX_OPERANDS];
418 static struct arm_it inst;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name;
454 #define COND_ALWAYS 0xE
458 const char * template_name;
462 struct asm_barrier_opt
464 const char * template_name;
466 const arm_feature_set arch;
469 /* The bit that distinguishes CPSR and SPSR. */
470 #define SPSR_BIT (1 << 22)
472 /* The individual PSR flag bits. */
473 #define PSR_c (1 << 16)
474 #define PSR_x (1 << 17)
475 #define PSR_s (1 << 18)
476 #define PSR_f (1 << 19)
481 bfd_reloc_code_real_type reloc;
486 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
487 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
492 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
495 /* Bits for DEFINED field in neon_typed_alias. */
496 #define NTA_HASTYPE 1
497 #define NTA_HASINDEX 2
499 struct neon_typed_alias
501 unsigned char defined;
503 struct neon_type_el eltype;
506 /* ARM register categories. This includes coprocessor numbers and various
507 architecture extensions' registers. */
534 /* Structure for a hash table entry for a register.
535 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
536 information which states whether a vector type or index is specified (for a
537 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
543 unsigned char builtin;
544 struct neon_typed_alias * neon;
547 /* Diagnostics used when we don't get a register of the expected type. */
548 const char * const reg_expected_msgs[] =
550 N_("ARM register expected"),
551 N_("bad or missing co-processor number"),
552 N_("co-processor register expected"),
553 N_("FPA register expected"),
554 N_("VFP single precision register expected"),
555 N_("VFP/Neon double precision register expected"),
556 N_("Neon quad precision register expected"),
557 N_("VFP single or double precision register expected"),
558 N_("Neon double or quad precision register expected"),
559 N_("VFP single, double or Neon quad precision register expected"),
560 N_("VFP system register expected"),
561 N_("Maverick MVF register expected"),
562 N_("Maverick MVD register expected"),
563 N_("Maverick MVFX register expected"),
564 N_("Maverick MVDX register expected"),
565 N_("Maverick MVAX register expected"),
566 N_("Maverick DSPSC register expected"),
567 N_("iWMMXt data register expected"),
568 N_("iWMMXt control register expected"),
569 N_("iWMMXt scalar register expected"),
570 N_("XScale accumulator register expected"),
573 /* Some well known registers that we refer to directly elsewhere. */
579 /* ARM instructions take 4bytes in the object file, Thumb instructions
585 /* Basic string to match. */
586 const char * template_name;
588 /* Parameters to instruction. */
589 unsigned int operands[8];
591 /* Conditional tag - see opcode_lookup. */
592 unsigned int tag : 4;
594 /* Basic instruction code. */
595 unsigned int avalue : 28;
597 /* Thumb-format instruction code. */
600 /* Which architecture variant provides this instruction. */
601 const arm_feature_set * avariant;
602 const arm_feature_set * tvariant;
604 /* Function to call to encode instruction in ARM format. */
605 void (* aencode) (void);
607 /* Function to call to encode instruction in Thumb format. */
608 void (* tencode) (void);
611 /* Defines for various bits that we will want to toggle. */
612 #define INST_IMMEDIATE 0x02000000
613 #define OFFSET_REG 0x02000000
614 #define HWOFFSET_IMM 0x00400000
615 #define SHIFT_BY_REG 0x00000010
616 #define PRE_INDEX 0x01000000
617 #define INDEX_UP 0x00800000
618 #define WRITE_BACK 0x00200000
619 #define LDM_TYPE_2_OR_3 0x00400000
620 #define CPSI_MMOD 0x00020000
622 #define LITERAL_MASK 0xf000f000
623 #define OPCODE_MASK 0xfe1fffff
624 #define V4_STR_BIT 0x00000020
626 #define T2_SUBS_PC_LR 0xf3de8f00
628 #define DATA_OP_SHIFT 21
630 #define T2_OPCODE_MASK 0xfe1fffff
631 #define T2_DATA_OP_SHIFT 21
633 #define A_COND_MASK 0xf0000000
634 #define A_PUSH_POP_OP_MASK 0x0fff0000
636 /* Opcodes for pushing/poping registers to/from the stack. */
637 #define A1_OPCODE_PUSH 0x092d0000
638 #define A2_OPCODE_PUSH 0x052d0004
639 #define A2_OPCODE_POP 0x049d0004
641 /* Codes to distinguish the arithmetic instructions. */
652 #define OPCODE_CMP 10
653 #define OPCODE_CMN 11
654 #define OPCODE_ORR 12
655 #define OPCODE_MOV 13
656 #define OPCODE_BIC 14
657 #define OPCODE_MVN 15
659 #define T2_OPCODE_AND 0
660 #define T2_OPCODE_BIC 1
661 #define T2_OPCODE_ORR 2
662 #define T2_OPCODE_ORN 3
663 #define T2_OPCODE_EOR 4
664 #define T2_OPCODE_ADD 8
665 #define T2_OPCODE_ADC 10
666 #define T2_OPCODE_SBC 11
667 #define T2_OPCODE_SUB 13
668 #define T2_OPCODE_RSB 14
670 #define T_OPCODE_MUL 0x4340
671 #define T_OPCODE_TST 0x4200
672 #define T_OPCODE_CMN 0x42c0
673 #define T_OPCODE_NEG 0x4240
674 #define T_OPCODE_MVN 0x43c0
676 #define T_OPCODE_ADD_R3 0x1800
677 #define T_OPCODE_SUB_R3 0x1a00
678 #define T_OPCODE_ADD_HI 0x4400
679 #define T_OPCODE_ADD_ST 0xb000
680 #define T_OPCODE_SUB_ST 0xb080
681 #define T_OPCODE_ADD_SP 0xa800
682 #define T_OPCODE_ADD_PC 0xa000
683 #define T_OPCODE_ADD_I8 0x3000
684 #define T_OPCODE_SUB_I8 0x3800
685 #define T_OPCODE_ADD_I3 0x1c00
686 #define T_OPCODE_SUB_I3 0x1e00
688 #define T_OPCODE_ASR_R 0x4100
689 #define T_OPCODE_LSL_R 0x4080
690 #define T_OPCODE_LSR_R 0x40c0
691 #define T_OPCODE_ROR_R 0x41c0
692 #define T_OPCODE_ASR_I 0x1000
693 #define T_OPCODE_LSL_I 0x0000
694 #define T_OPCODE_LSR_I 0x0800
696 #define T_OPCODE_MOV_I8 0x2000
697 #define T_OPCODE_CMP_I8 0x2800
698 #define T_OPCODE_CMP_LR 0x4280
699 #define T_OPCODE_MOV_HR 0x4600
700 #define T_OPCODE_CMP_HR 0x4500
702 #define T_OPCODE_LDR_PC 0x4800
703 #define T_OPCODE_LDR_SP 0x9800
704 #define T_OPCODE_STR_SP 0x9000
705 #define T_OPCODE_LDR_IW 0x6800
706 #define T_OPCODE_STR_IW 0x6000
707 #define T_OPCODE_LDR_IH 0x8800
708 #define T_OPCODE_STR_IH 0x8000
709 #define T_OPCODE_LDR_IB 0x7800
710 #define T_OPCODE_STR_IB 0x7000
711 #define T_OPCODE_LDR_RW 0x5800
712 #define T_OPCODE_STR_RW 0x5000
713 #define T_OPCODE_LDR_RH 0x5a00
714 #define T_OPCODE_STR_RH 0x5200
715 #define T_OPCODE_LDR_RB 0x5c00
716 #define T_OPCODE_STR_RB 0x5400
718 #define T_OPCODE_PUSH 0xb400
719 #define T_OPCODE_POP 0xbc00
721 #define T_OPCODE_BRANCH 0xe000
723 #define THUMB_SIZE 2 /* Size of thumb instruction. */
724 #define THUMB_PP_PC_LR 0x0100
725 #define THUMB_LOAD_BIT 0x0800
726 #define THUMB2_LOAD_BIT 0x00100000
728 #define BAD_ARGS _("bad arguments to instruction")
729 #define BAD_SP _("r13 not allowed here")
730 #define BAD_PC _("r15 not allowed here")
731 #define BAD_COND _("instruction cannot be conditional")
732 #define BAD_OVERLAP _("registers may not be the same")
733 #define BAD_HIREG _("lo register required")
734 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
735 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
736 #define BAD_BRANCH _("branch must be last instruction in IT block")
737 #define BAD_NOT_IT _("instruction not allowed in IT block")
738 #define BAD_FPU _("selected FPU does not support instruction")
739 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
740 #define BAD_IT_COND _("incorrect condition in IT block")
741 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
742 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
743 #define BAD_PC_ADDRESSING \
744 _("cannot use register index with PC-relative addressing")
745 #define BAD_PC_WRITEBACK \
746 _("cannot use writeback with PC-relative addressing")
747 #define BAD_RANGE _("branch out of range")
749 static struct hash_control * arm_ops_hsh;
750 static struct hash_control * arm_cond_hsh;
751 static struct hash_control * arm_shift_hsh;
752 static struct hash_control * arm_psr_hsh;
753 static struct hash_control * arm_v7m_psr_hsh;
754 static struct hash_control * arm_reg_hsh;
755 static struct hash_control * arm_reloc_hsh;
756 static struct hash_control * arm_barrier_opt_hsh;
758 /* Stuff needed to resolve the label ambiguity
767 symbolS * last_label_seen;
768 static int label_is_thumb_function_name = FALSE;
770 /* Literal pool structure. Held on a per-section
771 and per-sub-section basis. */
773 #define MAX_LITERAL_POOL_SIZE 1024
774 typedef struct literal_pool
776 expressionS literals [MAX_LITERAL_POOL_SIZE];
777 unsigned int next_free_entry;
783 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
785 struct literal_pool * next;
788 /* Pointer to a linked list of literal pools. */
789 literal_pool * list_of_pools = NULL;
792 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
794 static struct current_it now_it;
798 now_it_compatible (int cond)
800 return (cond & ~1) == (now_it.cc & ~1);
804 conditional_insn (void)
806 return inst.cond != COND_ALWAYS;
809 static int in_it_block (void);
811 static int handle_it_state (void);
813 static void force_automatic_it_block_close (void);
815 static void it_fsm_post_encode (void);
817 #define set_it_insn_type(type) \
820 inst.it_insn_type = type; \
821 if (handle_it_state () == FAIL) \
826 #define set_it_insn_type_nonvoid(type, failret) \
829 inst.it_insn_type = type; \
830 if (handle_it_state () == FAIL) \
835 #define set_it_insn_type_last() \
838 if (inst.cond == COND_ALWAYS) \
839 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
841 set_it_insn_type (INSIDE_IT_LAST_INSN); \
847 /* This array holds the chars that always start a comment. If the
848 pre-processor is disabled, these aren't very useful. */
849 const char comment_chars[] = "@";
851 /* This array holds the chars that only start a comment at the beginning of
852 a line. If the line seems to have the form '# 123 filename'
853 .line and .file directives will appear in the pre-processed output. */
854 /* Note that input_file.c hand checks for '#' at the beginning of the
855 first line of the input file. This is because the compiler outputs
856 #NO_APP at the beginning of its output. */
857 /* Also note that comments like this one will always work. */
858 const char line_comment_chars[] = "#";
860 const char line_separator_chars[] = ";";
862 /* Chars that can be used to separate mant
863 from exp in floating point numbers. */
864 const char EXP_CHARS[] = "eE";
866 /* Chars that mean this number is a floating point constant. */
870 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
872 /* Prefix characters that indicate the start of an immediate
874 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
876 /* Separator character handling. */
878 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
881 skip_past_char (char ** str, char c)
892 #define skip_past_comma(str) skip_past_char (str, ',')
894 /* Arithmetic expressions (possibly involving symbols). */
896 /* Return TRUE if anything in the expression is a bignum. */
899 walk_no_bignums (symbolS * sp)
901 if (symbol_get_value_expression (sp)->X_op == O_big)
904 if (symbol_get_value_expression (sp)->X_add_symbol)
906 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
907 || (symbol_get_value_expression (sp)->X_op_symbol
908 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
914 static int in_my_get_expression = 0;
916 /* Third argument to my_get_expression. */
917 #define GE_NO_PREFIX 0
918 #define GE_IMM_PREFIX 1
919 #define GE_OPT_PREFIX 2
920 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
921 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
922 #define GE_OPT_PREFIX_BIG 3
925 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
930 /* In unified syntax, all prefixes are optional. */
932 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
937 case GE_NO_PREFIX: break;
939 if (!is_immediate_prefix (**str))
941 inst.error = _("immediate expression requires a # prefix");
947 case GE_OPT_PREFIX_BIG:
948 if (is_immediate_prefix (**str))
954 memset (ep, 0, sizeof (expressionS));
956 save_in = input_line_pointer;
957 input_line_pointer = *str;
958 in_my_get_expression = 1;
959 seg = expression (ep);
960 in_my_get_expression = 0;
962 if (ep->X_op == O_illegal || ep->X_op == O_absent)
964 /* We found a bad or missing expression in md_operand(). */
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
967 if (inst.error == NULL)
968 inst.error = (ep->X_op == O_absent
969 ? _("missing expression") :_("bad expression"));
974 if (seg != absolute_section
975 && seg != text_section
976 && seg != data_section
977 && seg != bss_section
978 && seg != undefined_section)
980 inst.error = _("bad segment");
981 *str = input_line_pointer;
982 input_line_pointer = save_in;
989 /* Get rid of any bignums now, so that we don't generate an error for which
990 we can't establish a line number later on. Big numbers are never valid
991 in instructions, which is where this routine is always called. */
992 if (prefix_mode != GE_OPT_PREFIX_BIG
993 && (ep->X_op == O_big
995 && (walk_no_bignums (ep->X_add_symbol)
997 && walk_no_bignums (ep->X_op_symbol))))))
999 inst.error = _("invalid constant");
1000 *str = input_line_pointer;
1001 input_line_pointer = save_in;
1005 *str = input_line_pointer;
1006 input_line_pointer = save_in;
1010 /* Turn a string in input_line_pointer into a floating point constant
1011 of type TYPE, and store the appropriate bytes in *LITP. The number
1012 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1013 returned, or NULL on OK.
1015 Note that fp constants aren't represent in the normal way on the ARM.
1016 In big endian mode, things are as expected. However, in little endian
1017 mode fp constants are big-endian word-wise, and little-endian byte-wise
1018 within the words. For example, (double) 1.1 in big endian mode is
1019 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1020 the byte sequence 99 99 f1 3f 9a 99 99 99.
1022 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1025 md_atof (int type, char * litP, int * sizeP)
1028 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1060 return _("Unrecognized or unsupported floating point constant");
1063 t = atof_ieee (input_line_pointer, type, words);
1065 input_line_pointer = t;
1066 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1068 if (target_big_endian)
1070 for (i = 0; i < prec; i++)
1072 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += sizeof (LITTLENUM_TYPE);
1078 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1079 for (i = prec - 1; i >= 0; i--)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1085 /* For a 4 byte float the order of elements in `words' is 1 0.
1086 For an 8 byte float the order is 1 0 3 2. */
1087 for (i = 0; i < prec; i += 2)
1089 md_number_to_chars (litP, (valueT) words[i + 1],
1090 sizeof (LITTLENUM_TYPE));
1091 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1092 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1093 litP += 2 * sizeof (LITTLENUM_TYPE);
1100 /* We handle all bad expressions here, so that we can report the faulty
1101 instruction in the error message. */
1103 md_operand (expressionS * exp)
1105 if (in_my_get_expression)
1106 exp->X_op = O_illegal;
1109 /* Immediate values. */
1111 /* Generic immediate-value read function for use in directives.
1112 Accepts anything that 'expression' can fold to a constant.
1113 *val receives the number. */
1116 immediate_for_directive (int *val)
1119 exp.X_op = O_illegal;
1121 if (is_immediate_prefix (*input_line_pointer))
1123 input_line_pointer++;
1127 if (exp.X_op != O_constant)
1129 as_bad (_("expected #constant"));
1130 ignore_rest_of_line ();
1133 *val = exp.X_add_number;
1138 /* Register parsing. */
1140 /* Generic register parser. CCP points to what should be the
1141 beginning of a register name. If it is indeed a valid register
1142 name, advance CCP over it and return the reg_entry structure;
1143 otherwise return NULL. Does not issue diagnostics. */
1145 static struct reg_entry *
1146 arm_reg_parse_multi (char **ccp)
1150 struct reg_entry *reg;
1152 #ifdef REGISTER_PREFIX
1153 if (*start != REGISTER_PREFIX)
1157 #ifdef OPTIONAL_REGISTER_PREFIX
1158 if (*start == OPTIONAL_REGISTER_PREFIX)
1163 if (!ISALPHA (*p) || !is_name_beginner (*p))
1168 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1170 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1180 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1181 enum arm_reg_type type)
1183 /* Alternative syntaxes are accepted for a few register classes. */
1190 /* Generic coprocessor register names are allowed for these. */
1191 if (reg && reg->type == REG_TYPE_CN)
1196 /* For backward compatibility, a bare number is valid here. */
1198 unsigned long processor = strtoul (start, ccp, 10);
1199 if (*ccp != start && processor <= 15)
1203 case REG_TYPE_MMXWC:
1204 /* WC includes WCG. ??? I'm not sure this is true for all
1205 instructions that take WC registers. */
1206 if (reg && reg->type == REG_TYPE_MMXWCG)
1217 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1218 return value is the register number or FAIL. */
1221 arm_reg_parse (char **ccp, enum arm_reg_type type)
1224 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1227 /* Do not allow a scalar (reg+index) to parse as a register. */
1228 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1231 if (reg && reg->type == type)
1234 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1241 /* Parse a Neon type specifier. *STR should point at the leading '.'
1242 character. Does no verification at this stage that the type fits the opcode
1249 Can all be legally parsed by this function.
1251 Fills in neon_type struct pointer with parsed information, and updates STR
1252 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1253 type, FAIL if not. */
1256 parse_neon_type (struct neon_type *type, char **str)
1263 while (type->elems < NEON_MAX_TYPE_ELS)
1265 enum neon_el_type thistype = NT_untyped;
1266 unsigned thissize = -1u;
1273 /* Just a size without an explicit type. */
1277 switch (TOLOWER (*ptr))
1279 case 'i': thistype = NT_integer; break;
1280 case 'f': thistype = NT_float; break;
1281 case 'p': thistype = NT_poly; break;
1282 case 's': thistype = NT_signed; break;
1283 case 'u': thistype = NT_unsigned; break;
1285 thistype = NT_float;
1290 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1296 /* .f is an abbreviation for .f32. */
1297 if (thistype == NT_float && !ISDIGIT (*ptr))
1302 thissize = strtoul (ptr, &ptr, 10);
1304 if (thissize != 8 && thissize != 16 && thissize != 32
1307 as_bad (_("bad size %d in type specifier"), thissize);
1315 type->el[type->elems].type = thistype;
1316 type->el[type->elems].size = thissize;
1321 /* Empty/missing type is not a successful parse. */
1322 if (type->elems == 0)
1330 /* Errors may be set multiple times during parsing or bit encoding
1331 (particularly in the Neon bits), but usually the earliest error which is set
1332 will be the most meaningful. Avoid overwriting it with later (cascading)
1333 errors by calling this function. */
1336 first_error (const char *err)
1342 /* Parse a single type, e.g. ".s32", leading period included. */
1344 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1347 struct neon_type optype;
1351 if (parse_neon_type (&optype, &str) == SUCCESS)
1353 if (optype.elems == 1)
1354 *vectype = optype.el[0];
1357 first_error (_("only one type should be specified for operand"));
1363 first_error (_("vector type expected"));
1375 /* Special meanings for indices (which have a range of 0-7), which will fit into
1378 #define NEON_ALL_LANES 15
1379 #define NEON_INTERLEAVE_LANES 14
1381 /* Parse either a register or a scalar, with an optional type. Return the
1382 register number, and optionally fill in the actual type of the register
1383 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1384 type/index information in *TYPEINFO. */
1387 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1388 enum arm_reg_type *rtype,
1389 struct neon_typed_alias *typeinfo)
1392 struct reg_entry *reg = arm_reg_parse_multi (&str);
1393 struct neon_typed_alias atype;
1394 struct neon_type_el parsetype;
1398 atype.eltype.type = NT_invtype;
1399 atype.eltype.size = -1;
1401 /* Try alternate syntax for some types of register. Note these are mutually
1402 exclusive with the Neon syntax extensions. */
1405 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1413 /* Undo polymorphism when a set of register types may be accepted. */
1414 if ((type == REG_TYPE_NDQ
1415 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1416 || (type == REG_TYPE_VFSD
1417 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1418 || (type == REG_TYPE_NSDQ
1419 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1420 || reg->type == REG_TYPE_NQ))
1421 || (type == REG_TYPE_MMXWC
1422 && (reg->type == REG_TYPE_MMXWCG)))
1423 type = (enum arm_reg_type) reg->type;
1425 if (type != reg->type)
1431 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1433 if ((atype.defined & NTA_HASTYPE) != 0)
1435 first_error (_("can't redefine type for operand"));
1438 atype.defined |= NTA_HASTYPE;
1439 atype.eltype = parsetype;
1442 if (skip_past_char (&str, '[') == SUCCESS)
1444 if (type != REG_TYPE_VFD)
1446 first_error (_("only D registers may be indexed"));
1450 if ((atype.defined & NTA_HASINDEX) != 0)
1452 first_error (_("can't change index for operand"));
1456 atype.defined |= NTA_HASINDEX;
1458 if (skip_past_char (&str, ']') == SUCCESS)
1459 atype.index = NEON_ALL_LANES;
1464 my_get_expression (&exp, &str, GE_NO_PREFIX);
1466 if (exp.X_op != O_constant)
1468 first_error (_("constant expression required"));
1472 if (skip_past_char (&str, ']') == FAIL)
1475 atype.index = exp.X_add_number;
1490 /* Like arm_reg_parse, but allow allow the following extra features:
1491 - If RTYPE is non-zero, return the (possibly restricted) type of the
1492 register (e.g. Neon double or quad reg when either has been requested).
1493 - If this is a Neon vector type with additional type information, fill
1494 in the struct pointed to by VECTYPE (if non-NULL).
1495 This function will fault on encountering a scalar. */
1498 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1499 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1501 struct neon_typed_alias atype;
1503 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1508 /* Do not allow regname(... to parse as a register. */
1512 /* Do not allow a scalar (reg+index) to parse as a register. */
1513 if ((atype.defined & NTA_HASINDEX) != 0)
1515 first_error (_("register operand expected, but got scalar"));
1520 *vectype = atype.eltype;
1527 #define NEON_SCALAR_REG(X) ((X) >> 4)
1528 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1530 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1531 have enough information to be able to do a good job bounds-checking. So, we
1532 just do easy checks here, and do further checks later. */
1535 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1539 struct neon_typed_alias atype;
1541 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1543 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1546 if (atype.index == NEON_ALL_LANES)
1548 first_error (_("scalar must have an index"));
1551 else if (atype.index >= 64 / elsize)
1553 first_error (_("scalar index out of range"));
1558 *type = atype.eltype;
1562 return reg * 16 + atype.index;
1565 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1568 parse_reg_list (char ** strp)
1570 char * str = * strp;
1574 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1591 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1601 first_error (_("bad range in register list"));
1605 for (i = cur_reg + 1; i < reg; i++)
1607 if (range & (1 << i))
1609 (_("Warning: duplicated register (r%d) in register list"),
1617 if (range & (1 << reg))
1618 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1620 else if (reg <= cur_reg)
1621 as_tsktsk (_("Warning: register range not in ascending order"));
1626 while (skip_past_comma (&str) != FAIL
1627 || (in_range = 1, *str++ == '-'));
1632 first_error (_("missing `}'"));
1640 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1643 if (exp.X_op == O_constant)
1645 if (exp.X_add_number
1646 != (exp.X_add_number & 0x0000ffff))
1648 inst.error = _("invalid register mask");
1652 if ((range & exp.X_add_number) != 0)
1654 int regno = range & exp.X_add_number;
1657 regno = (1 << regno) - 1;
1659 (_("Warning: duplicated register (r%d) in register list"),
1663 range |= exp.X_add_number;
1667 if (inst.reloc.type != 0)
1669 inst.error = _("expression too complex");
1673 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1674 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1675 inst.reloc.pc_rel = 0;
1679 if (*str == '|' || *str == '+')
1685 while (another_range);
1691 /* Types of registers in a list. */
1700 /* Parse a VFP register list. If the string is invalid return FAIL.
1701 Otherwise return the number of registers, and set PBASE to the first
1702 register. Parses registers of type ETYPE.
1703 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1704 - Q registers can be used to specify pairs of D registers
1705 - { } can be omitted from around a singleton register list
1706 FIXME: This is not implemented, as it would require backtracking in
1709 This could be done (the meaning isn't really ambiguous), but doesn't
1710 fit in well with the current parsing framework.
1711 - 32 D registers may be used (also true for VFPv3).
1712 FIXME: Types are ignored in these register lists, which is probably a
1716 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1721 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1725 unsigned long mask = 0;
1730 inst.error = _("expecting {");
1739 regtype = REG_TYPE_VFS;
1744 regtype = REG_TYPE_VFD;
1747 case REGLIST_NEON_D:
1748 regtype = REG_TYPE_NDQ;
1752 if (etype != REGLIST_VFP_S)
1754 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1755 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1759 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1762 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1769 base_reg = max_regs;
1773 int setmask = 1, addregs = 1;
1775 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1777 if (new_base == FAIL)
1779 first_error (_(reg_expected_msgs[regtype]));
1783 if (new_base >= max_regs)
1785 first_error (_("register out of range in list"));
1789 /* Note: a value of 2 * n is returned for the register Q<n>. */
1790 if (regtype == REG_TYPE_NQ)
1796 if (new_base < base_reg)
1797 base_reg = new_base;
1799 if (mask & (setmask << new_base))
1801 first_error (_("invalid register list"));
1805 if ((mask >> new_base) != 0 && ! warned)
1807 as_tsktsk (_("register list not in ascending order"));
1811 mask |= setmask << new_base;
1814 if (*str == '-') /* We have the start of a range expression */
1820 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1823 inst.error = gettext (reg_expected_msgs[regtype]);
1827 if (high_range >= max_regs)
1829 first_error (_("register out of range in list"));
1833 if (regtype == REG_TYPE_NQ)
1834 high_range = high_range + 1;
1836 if (high_range <= new_base)
1838 inst.error = _("register range not in ascending order");
1842 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1844 if (mask & (setmask << new_base))
1846 inst.error = _("invalid register list");
1850 mask |= setmask << new_base;
1855 while (skip_past_comma (&str) != FAIL);
1859 /* Sanity check -- should have raised a parse error above. */
1860 if (count == 0 || count > max_regs)
1865 /* Final test -- the registers must be consecutive. */
1867 for (i = 0; i < count; i++)
1869 if ((mask & (1u << i)) == 0)
1871 inst.error = _("non-contiguous register range");
1881 /* True if two alias types are the same. */
1884 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1892 if (a->defined != b->defined)
1895 if ((a->defined & NTA_HASTYPE) != 0
1896 && (a->eltype.type != b->eltype.type
1897 || a->eltype.size != b->eltype.size))
1900 if ((a->defined & NTA_HASINDEX) != 0
1901 && (a->index != b->index))
1907 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1908 The base register is put in *PBASE.
1909 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1911 The register stride (minus one) is put in bit 4 of the return value.
1912 Bits [6:5] encode the list length (minus one).
1913 The type of the list elements is put in *ELTYPE, if non-NULL. */
1915 #define NEON_LANE(X) ((X) & 0xf)
1916 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1917 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1920 parse_neon_el_struct_list (char **str, unsigned *pbase,
1921 struct neon_type_el *eltype)
1928 int leading_brace = 0;
1929 enum arm_reg_type rtype = REG_TYPE_NDQ;
1930 const char *const incr_error = _("register stride must be 1 or 2");
1931 const char *const type_error = _("mismatched element/structure types in list");
1932 struct neon_typed_alias firsttype;
1934 if (skip_past_char (&ptr, '{') == SUCCESS)
1939 struct neon_typed_alias atype;
1940 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1944 first_error (_(reg_expected_msgs[rtype]));
1951 if (rtype == REG_TYPE_NQ)
1957 else if (reg_incr == -1)
1959 reg_incr = getreg - base_reg;
1960 if (reg_incr < 1 || reg_incr > 2)
1962 first_error (_(incr_error));
1966 else if (getreg != base_reg + reg_incr * count)
1968 first_error (_(incr_error));
1972 if (! neon_alias_types_same (&atype, &firsttype))
1974 first_error (_(type_error));
1978 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1982 struct neon_typed_alias htype;
1983 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1985 lane = NEON_INTERLEAVE_LANES;
1986 else if (lane != NEON_INTERLEAVE_LANES)
1988 first_error (_(type_error));
1993 else if (reg_incr != 1)
1995 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1999 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2002 first_error (_(reg_expected_msgs[rtype]));
2005 if (! neon_alias_types_same (&htype, &firsttype))
2007 first_error (_(type_error));
2010 count += hireg + dregs - getreg;
2014 /* If we're using Q registers, we can't use [] or [n] syntax. */
2015 if (rtype == REG_TYPE_NQ)
2021 if ((atype.defined & NTA_HASINDEX) != 0)
2025 else if (lane != atype.index)
2027 first_error (_(type_error));
2031 else if (lane == -1)
2032 lane = NEON_INTERLEAVE_LANES;
2033 else if (lane != NEON_INTERLEAVE_LANES)
2035 first_error (_(type_error));
2040 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2042 /* No lane set by [x]. We must be interleaving structures. */
2044 lane = NEON_INTERLEAVE_LANES;
2047 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2048 || (count > 1 && reg_incr == -1))
2050 first_error (_("error parsing element/structure list"));
2054 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2056 first_error (_("expected }"));
2064 *eltype = firsttype.eltype;
2069 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2072 /* Parse an explicit relocation suffix on an expression. This is
2073 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2074 arm_reloc_hsh contains no entries, so this function can only
2075 succeed if there is no () after the word. Returns -1 on error,
2076 BFD_RELOC_UNUSED if there wasn't any suffix. */
2079 parse_reloc (char **str)
2081 struct reloc_entry *r;
2085 return BFD_RELOC_UNUSED;
2090 while (*q && *q != ')' && *q != ',')
2095 if ((r = (struct reloc_entry *)
2096 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2103 /* Directives: register aliases. */
2105 static struct reg_entry *
2106 insert_reg_alias (char *str, unsigned number, int type)
2108 struct reg_entry *new_reg;
2111 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2113 if (new_reg->builtin)
2114 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2116 /* Only warn about a redefinition if it's not defined as the
2118 else if (new_reg->number != number || new_reg->type != type)
2119 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2124 name = xstrdup (str);
2125 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2127 new_reg->name = name;
2128 new_reg->number = number;
2129 new_reg->type = type;
2130 new_reg->builtin = FALSE;
2131 new_reg->neon = NULL;
2133 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2140 insert_neon_reg_alias (char *str, int number, int type,
2141 struct neon_typed_alias *atype)
2143 struct reg_entry *reg = insert_reg_alias (str, number, type);
2147 first_error (_("attempt to redefine typed alias"));
2153 reg->neon = (struct neon_typed_alias *)
2154 xmalloc (sizeof (struct neon_typed_alias));
2155 *reg->neon = *atype;
2159 /* Look for the .req directive. This is of the form:
2161 new_register_name .req existing_register_name
2163 If we find one, or if it looks sufficiently like one that we want to
2164 handle any error here, return TRUE. Otherwise return FALSE. */
2167 create_register_alias (char * newname, char *p)
2169 struct reg_entry *old;
2170 char *oldname, *nbuf;
2173 /* The input scrubber ensures that whitespace after the mnemonic is
2174 collapsed to single spaces. */
2176 if (strncmp (oldname, " .req ", 6) != 0)
2180 if (*oldname == '\0')
2183 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2186 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2190 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2191 the desired alias name, and p points to its end. If not, then
2192 the desired alias name is in the global original_case_string. */
2193 #ifdef TC_CASE_SENSITIVE
2196 newname = original_case_string;
2197 nlen = strlen (newname);
2200 nbuf = (char *) alloca (nlen + 1);
2201 memcpy (nbuf, newname, nlen);
2204 /* Create aliases under the new name as stated; an all-lowercase
2205 version of the new name; and an all-uppercase version of the new
2207 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2209 for (p = nbuf; *p; p++)
2212 if (strncmp (nbuf, newname, nlen))
2214 /* If this attempt to create an additional alias fails, do not bother
2215 trying to create the all-lower case alias. We will fail and issue
2216 a second, duplicate error message. This situation arises when the
2217 programmer does something like:
2220 The second .req creates the "Foo" alias but then fails to create
2221 the artificial FOO alias because it has already been created by the
2223 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2227 for (p = nbuf; *p; p++)
2230 if (strncmp (nbuf, newname, nlen))
2231 insert_reg_alias (nbuf, old->number, old->type);
2237 /* Create a Neon typed/indexed register alias using directives, e.g.:
2242 These typed registers can be used instead of the types specified after the
2243 Neon mnemonic, so long as all operands given have types. Types can also be
2244 specified directly, e.g.:
2245 vadd d0.s32, d1.s32, d2.s32 */
2248 create_neon_reg_alias (char *newname, char *p)
2250 enum arm_reg_type basetype;
2251 struct reg_entry *basereg;
2252 struct reg_entry mybasereg;
2253 struct neon_type ntype;
2254 struct neon_typed_alias typeinfo;
2255 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2258 typeinfo.defined = 0;
2259 typeinfo.eltype.type = NT_invtype;
2260 typeinfo.eltype.size = -1;
2261 typeinfo.index = -1;
2265 if (strncmp (p, " .dn ", 5) == 0)
2266 basetype = REG_TYPE_VFD;
2267 else if (strncmp (p, " .qn ", 5) == 0)
2268 basetype = REG_TYPE_NQ;
2277 basereg = arm_reg_parse_multi (&p);
2279 if (basereg && basereg->type != basetype)
2281 as_bad (_("bad type for register"));
2285 if (basereg == NULL)
2288 /* Try parsing as an integer. */
2289 my_get_expression (&exp, &p, GE_NO_PREFIX);
2290 if (exp.X_op != O_constant)
2292 as_bad (_("expression must be constant"));
2295 basereg = &mybasereg;
2296 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2302 typeinfo = *basereg->neon;
2304 if (parse_neon_type (&ntype, &p) == SUCCESS)
2306 /* We got a type. */
2307 if (typeinfo.defined & NTA_HASTYPE)
2309 as_bad (_("can't redefine the type of a register alias"));
2313 typeinfo.defined |= NTA_HASTYPE;
2314 if (ntype.elems != 1)
2316 as_bad (_("you must specify a single type only"));
2319 typeinfo.eltype = ntype.el[0];
2322 if (skip_past_char (&p, '[') == SUCCESS)
2325 /* We got a scalar index. */
2327 if (typeinfo.defined & NTA_HASINDEX)
2329 as_bad (_("can't redefine the index of a scalar alias"));
2333 my_get_expression (&exp, &p, GE_NO_PREFIX);
2335 if (exp.X_op != O_constant)
2337 as_bad (_("scalar index must be constant"));
2341 typeinfo.defined |= NTA_HASINDEX;
2342 typeinfo.index = exp.X_add_number;
2344 if (skip_past_char (&p, ']') == FAIL)
2346 as_bad (_("expecting ]"));
2351 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2352 the desired alias name, and p points to its end. If not, then
2353 the desired alias name is in the global original_case_string. */
2354 #ifdef TC_CASE_SENSITIVE
2355 namelen = nameend - newname;
2357 newname = original_case_string;
2358 namelen = strlen (newname);
2361 namebuf = (char *) alloca (namelen + 1);
2362 strncpy (namebuf, newname, namelen);
2363 namebuf[namelen] = '\0';
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2368 /* Insert name in all uppercase. */
2369 for (p = namebuf; *p; p++)
2372 if (strncmp (namebuf, newname, namelen))
2373 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2374 typeinfo.defined != 0 ? &typeinfo : NULL);
2376 /* Insert name in all lowercase. */
2377 for (p = namebuf; *p; p++)
2380 if (strncmp (namebuf, newname, namelen))
2381 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2382 typeinfo.defined != 0 ? &typeinfo : NULL);
2387 /* Should never be called, as .req goes between the alias and the
2388 register name, not at the beginning of the line. */
2391 s_req (int a ATTRIBUTE_UNUSED)
2393 as_bad (_("invalid syntax for .req directive"));
2397 s_dn (int a ATTRIBUTE_UNUSED)
2399 as_bad (_("invalid syntax for .dn directive"));
2403 s_qn (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .qn directive"));
2408 /* The .unreq directive deletes an alias which was previously defined
2409 by .req. For example:
2415 s_unreq (int a ATTRIBUTE_UNUSED)
2420 name = input_line_pointer;
2422 while (*input_line_pointer != 0
2423 && *input_line_pointer != ' '
2424 && *input_line_pointer != '\n')
2425 ++input_line_pointer;
2427 saved_char = *input_line_pointer;
2428 *input_line_pointer = 0;
2431 as_bad (_("invalid syntax for .unreq directive"));
2434 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2438 as_bad (_("unknown register alias '%s'"), name);
2439 else if (reg->builtin)
2440 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2447 hash_delete (arm_reg_hsh, name, FALSE);
2448 free ((char *) reg->name);
2453 /* Also locate the all upper case and all lower case versions.
2454 Do not complain if we cannot find one or the other as it
2455 was probably deleted above. */
2457 nbuf = strdup (name);
2458 for (p = nbuf; *p; p++)
2460 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2463 hash_delete (arm_reg_hsh, nbuf, FALSE);
2464 free ((char *) reg->name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2486 *input_line_pointer = saved_char;
2487 demand_empty_rest_of_line ();
2490 /* Directives: Instruction set selection. */
2493 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2494 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2495 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2496 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2498 /* Create a new mapping symbol for the transition to STATE. */
2501 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2504 const char * symname;
2511 type = BSF_NO_FLAGS;
2515 type = BSF_NO_FLAGS;
2519 type = BSF_NO_FLAGS;
2525 symbolP = symbol_new (symname, now_seg, value, frag);
2526 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2531 THUMB_SET_FUNC (symbolP, 0);
2532 ARM_SET_THUMB (symbolP, 0);
2533 ARM_SET_INTERWORK (symbolP, support_interwork);
2537 THUMB_SET_FUNC (symbolP, 1);
2538 ARM_SET_THUMB (symbolP, 1);
2539 ARM_SET_INTERWORK (symbolP, support_interwork);
2547 /* Save the mapping symbols for future reference. Also check that
2548 we do not place two mapping symbols at the same offset within a
2549 frag. We'll handle overlap between frags in
2550 check_mapping_symbols.
2552 If .fill or other data filling directive generates zero sized data,
2553 the mapping symbol for the following code will have the same value
2554 as the one generated for the data filling directive. In this case,
2555 we replace the old symbol with the new one at the same address. */
2558 if (frag->tc_frag_data.first_map != NULL)
2560 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2561 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2563 frag->tc_frag_data.first_map = symbolP;
2565 if (frag->tc_frag_data.last_map != NULL)
2567 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2568 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2569 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2571 frag->tc_frag_data.last_map = symbolP;
2574 /* We must sometimes convert a region marked as code to data during
2575 code alignment, if an odd number of bytes have to be padded. The
2576 code mapping symbol is pushed to an aligned address. */
2579 insert_data_mapping_symbol (enum mstate state,
2580 valueT value, fragS *frag, offsetT bytes)
2582 /* If there was already a mapping symbol, remove it. */
2583 if (frag->tc_frag_data.last_map != NULL
2584 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2586 symbolS *symp = frag->tc_frag_data.last_map;
2590 know (frag->tc_frag_data.first_map == symp);
2591 frag->tc_frag_data.first_map = NULL;
2593 frag->tc_frag_data.last_map = NULL;
2594 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2597 make_mapping_symbol (MAP_DATA, value, frag);
2598 make_mapping_symbol (state, value + bytes, frag);
2601 static void mapping_state_2 (enum mstate state, int max_chars);
2603 /* Set the mapping state to STATE. Only call this when about to
2604 emit some STATE bytes to the file. */
2607 mapping_state (enum mstate state)
2609 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2611 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2613 if (mapstate == state)
2614 /* The mapping symbol has already been emitted.
2615 There is nothing else to do. */
2618 if (state == MAP_ARM || state == MAP_THUMB)
2620 All ARM instructions require 4-byte alignment.
2621 (Almost) all Thumb instructions require 2-byte alignment.
2623 When emitting instructions into any section, mark the section
2626 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2627 but themselves require 2-byte alignment; this applies to some
2628 PC- relative forms. However, these cases will invovle implicit
2629 literal pool generation or an explicit .align >=2, both of
2630 which will cause the section to me marked with sufficient
2631 alignment. Thus, we don't handle those cases here. */
2632 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2634 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2635 /* This case will be evaluated later in the next else. */
2637 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2638 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2640 /* Only add the symbol if the offset is > 0:
2641 if we're at the first frag, check it's size > 0;
2642 if we're not at the first frag, then for sure
2643 the offset is > 0. */
2644 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2645 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2648 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2651 mapping_state_2 (state, 0);
2655 /* Same as mapping_state, but MAX_CHARS bytes have already been
2656 allocated. Put the mapping symbol that far back. */
2659 mapping_state_2 (enum mstate state, int max_chars)
2661 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2663 if (!SEG_NORMAL (now_seg))
2666 if (mapstate == state)
2667 /* The mapping symbol has already been emitted.
2668 There is nothing else to do. */
2671 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2672 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2675 #define mapping_state(x) ((void)0)
2676 #define mapping_state_2(x, y) ((void)0)
2679 /* Find the real, Thumb encoded start of a Thumb function. */
2683 find_real_start (symbolS * symbolP)
2686 const char * name = S_GET_NAME (symbolP);
2687 symbolS * new_target;
2689 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2690 #define STUB_NAME ".real_start_of"
2695 /* The compiler may generate BL instructions to local labels because
2696 it needs to perform a branch to a far away location. These labels
2697 do not have a corresponding ".real_start_of" label. We check
2698 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2699 the ".real_start_of" convention for nonlocal branches. */
2700 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2703 real_start = ACONCAT ((STUB_NAME, name, NULL));
2704 new_target = symbol_find (real_start);
2706 if (new_target == NULL)
2708 as_warn (_("Failed to find real start of function: %s\n"), name);
2709 new_target = symbolP;
2717 opcode_select (int width)
2724 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2725 as_bad (_("selected processor does not support THUMB opcodes"));
2728 /* No need to force the alignment, since we will have been
2729 coming from ARM mode, which is word-aligned. */
2730 record_alignment (now_seg, 1);
2737 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2738 as_bad (_("selected processor does not support ARM opcodes"));
2743 frag_align (2, 0, 0);
2745 record_alignment (now_seg, 1);
2750 as_bad (_("invalid instruction size selected (%d)"), width);
2755 s_arm (int ignore ATTRIBUTE_UNUSED)
2758 demand_empty_rest_of_line ();
2762 s_thumb (int ignore ATTRIBUTE_UNUSED)
2765 demand_empty_rest_of_line ();
2769 s_code (int unused ATTRIBUTE_UNUSED)
2773 temp = get_absolute_expression ();
2778 opcode_select (temp);
2782 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2787 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2789 /* If we are not already in thumb mode go into it, EVEN if
2790 the target processor does not support thumb instructions.
2791 This is used by gcc/config/arm/lib1funcs.asm for example
2792 to compile interworking support functions even if the
2793 target processor should not support interworking. */
2797 record_alignment (now_seg, 1);
2800 demand_empty_rest_of_line ();
2804 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2808 /* The following label is the name/address of the start of a Thumb function.
2809 We need to know this for the interworking support. */
2810 label_is_thumb_function_name = TRUE;
2813 /* Perform a .set directive, but also mark the alias as
2814 being a thumb function. */
2817 s_thumb_set (int equiv)
2819 /* XXX the following is a duplicate of the code for s_set() in read.c
2820 We cannot just call that code as we need to get at the symbol that
2827 /* Especial apologies for the random logic:
2828 This just grew, and could be parsed much more simply!
2830 name = input_line_pointer;
2831 delim = get_symbol_end ();
2832 end_name = input_line_pointer;
2835 if (*input_line_pointer != ',')
2838 as_bad (_("expected comma after name \"%s\""), name);
2840 ignore_rest_of_line ();
2844 input_line_pointer++;
2847 if (name[0] == '.' && name[1] == '\0')
2849 /* XXX - this should not happen to .thumb_set. */
2853 if ((symbolP = symbol_find (name)) == NULL
2854 && (symbolP = md_undefined_symbol (name)) == NULL)
2857 /* When doing symbol listings, play games with dummy fragments living
2858 outside the normal fragment chain to record the file and line info
2860 if (listing & LISTING_SYMBOLS)
2862 extern struct list_info_struct * listing_tail;
2863 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2865 memset (dummy_frag, 0, sizeof (fragS));
2866 dummy_frag->fr_type = rs_fill;
2867 dummy_frag->line = listing_tail;
2868 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2869 dummy_frag->fr_symbol = symbolP;
2873 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2876 /* "set" symbols are local unless otherwise specified. */
2877 SF_SET_LOCAL (symbolP);
2878 #endif /* OBJ_COFF */
2879 } /* Make a new symbol. */
2881 symbol_table_insert (symbolP);
2886 && S_IS_DEFINED (symbolP)
2887 && S_GET_SEGMENT (symbolP) != reg_section)
2888 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2890 pseudo_set (symbolP);
2892 demand_empty_rest_of_line ();
2894 /* XXX Now we come to the Thumb specific bit of code. */
2896 THUMB_SET_FUNC (symbolP, 1);
2897 ARM_SET_THUMB (symbolP, 1);
2898 #if defined OBJ_ELF || defined OBJ_COFF
2899 ARM_SET_INTERWORK (symbolP, support_interwork);
2903 /* Directives: Mode selection. */
2905 /* .syntax [unified|divided] - choose the new unified syntax
2906 (same for Arm and Thumb encoding, modulo slight differences in what
2907 can be represented) or the old divergent syntax for each mode. */
2909 s_syntax (int unused ATTRIBUTE_UNUSED)
2913 name = input_line_pointer;
2914 delim = get_symbol_end ();
2916 if (!strcasecmp (name, "unified"))
2917 unified_syntax = TRUE;
2918 else if (!strcasecmp (name, "divided"))
2919 unified_syntax = FALSE;
2922 as_bad (_("unrecognized syntax mode \"%s\""), name);
2925 *input_line_pointer = delim;
2926 demand_empty_rest_of_line ();
2929 /* Directives: sectioning and alignment. */
2931 /* Same as s_align_ptwo but align 0 => align 2. */
2934 s_align (int unused ATTRIBUTE_UNUSED)
2939 long max_alignment = 15;
2941 temp = get_absolute_expression ();
2942 if (temp > max_alignment)
2943 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2946 as_bad (_("alignment negative. 0 assumed."));
2950 if (*input_line_pointer == ',')
2952 input_line_pointer++;
2953 temp_fill = get_absolute_expression ();
2965 /* Only make a frag if we HAVE to. */
2966 if (temp && !need_pass_2)
2968 if (!fill_p && subseg_text_p (now_seg))
2969 frag_align_code (temp, 0);
2971 frag_align (temp, (int) temp_fill, 0);
2973 demand_empty_rest_of_line ();
2975 record_alignment (now_seg, temp);
2979 s_bss (int ignore ATTRIBUTE_UNUSED)
2981 /* We don't support putting frags in the BSS segment, we fake it by
2982 marking in_bss, then looking at s_skip for clues. */
2983 subseg_set (bss_section, 0);
2984 demand_empty_rest_of_line ();
2986 #ifdef md_elf_section_change_hook
2987 md_elf_section_change_hook ();
2992 s_even (int ignore ATTRIBUTE_UNUSED)
2994 /* Never make frag if expect extra pass. */
2996 frag_align (1, 0, 0);
2998 record_alignment (now_seg, 1);
3000 demand_empty_rest_of_line ();
3003 /* Directives: Literal pools. */
3005 static literal_pool *
3006 find_literal_pool (void)
3008 literal_pool * pool;
3010 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3012 if (pool->section == now_seg
3013 && pool->sub_section == now_subseg)
3020 static literal_pool *
3021 find_or_make_literal_pool (void)
3023 /* Next literal pool ID number. */
3024 static unsigned int latest_pool_num = 1;
3025 literal_pool * pool;
3027 pool = find_literal_pool ();
3031 /* Create a new pool. */
3032 pool = (literal_pool *) xmalloc (sizeof (* pool));
3036 pool->next_free_entry = 0;
3037 pool->section = now_seg;
3038 pool->sub_section = now_subseg;
3039 pool->next = list_of_pools;
3040 pool->symbol = NULL;
3042 /* Add it to the list. */
3043 list_of_pools = pool;
3046 /* New pools, and emptied pools, will have a NULL symbol. */
3047 if (pool->symbol == NULL)
3049 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3050 (valueT) 0, &zero_address_frag);
3051 pool->id = latest_pool_num ++;
3058 /* Add the literal in the global 'inst'
3059 structure to the relevant literal pool. */
3062 add_to_lit_pool (void)
3064 literal_pool * pool;
3067 pool = find_or_make_literal_pool ();
3069 /* Check if this literal value is already in the pool. */
3070 for (entry = 0; entry < pool->next_free_entry; entry ++)
3072 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3073 && (inst.reloc.exp.X_op == O_constant)
3074 && (pool->literals[entry].X_add_number
3075 == inst.reloc.exp.X_add_number)
3076 && (pool->literals[entry].X_unsigned
3077 == inst.reloc.exp.X_unsigned))
3080 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3081 && (inst.reloc.exp.X_op == O_symbol)
3082 && (pool->literals[entry].X_add_number
3083 == inst.reloc.exp.X_add_number)
3084 && (pool->literals[entry].X_add_symbol
3085 == inst.reloc.exp.X_add_symbol)
3086 && (pool->literals[entry].X_op_symbol
3087 == inst.reloc.exp.X_op_symbol))
3091 /* Do we need to create a new entry? */
3092 if (entry == pool->next_free_entry)
3094 if (entry >= MAX_LITERAL_POOL_SIZE)
3096 inst.error = _("literal pool overflow");
3100 pool->literals[entry] = inst.reloc.exp;
3102 /* PR ld/12974: Record the location of the first source line to reference
3103 this entry in the literal pool. If it turns out during linking that the
3104 symbol does not exist we will be able to give an accurate line number for
3105 the (first use of the) missing reference. */
3106 if (debug_type == DEBUG_DWARF2)
3107 dwarf2_where (pool->locs + entry);
3109 pool->next_free_entry += 1;
3112 inst.reloc.exp.X_op = O_symbol;
3113 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3114 inst.reloc.exp.X_add_symbol = pool->symbol;
3119 /* Can't use symbol_new here, so have to create a symbol and then at
3120 a later date assign it a value. Thats what these functions do. */
3123 symbol_locate (symbolS * symbolP,
3124 const char * name, /* It is copied, the caller can modify. */
3125 segT segment, /* Segment identifier (SEG_<something>). */
3126 valueT valu, /* Symbol value. */
3127 fragS * frag) /* Associated fragment. */
3129 unsigned int name_length;
3130 char * preserved_copy_of_name;
3132 name_length = strlen (name) + 1; /* +1 for \0. */
3133 obstack_grow (¬es, name, name_length);
3134 preserved_copy_of_name = (char *) obstack_finish (¬es);
3136 #ifdef tc_canonicalize_symbol_name
3137 preserved_copy_of_name =
3138 tc_canonicalize_symbol_name (preserved_copy_of_name);
3141 S_SET_NAME (symbolP, preserved_copy_of_name);
3143 S_SET_SEGMENT (symbolP, segment);
3144 S_SET_VALUE (symbolP, valu);
3145 symbol_clear_list_pointers (symbolP);
3147 symbol_set_frag (symbolP, frag);
3149 /* Link to end of symbol chain. */
3151 extern int symbol_table_frozen;
3153 if (symbol_table_frozen)
3157 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3159 obj_symbol_new_hook (symbolP);
3161 #ifdef tc_symbol_new_hook
3162 tc_symbol_new_hook (symbolP);
3166 verify_symbol_chain (symbol_rootP, symbol_lastP);
3167 #endif /* DEBUG_SYMS */
3172 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3175 literal_pool * pool;
3178 pool = find_literal_pool ();
3180 || pool->symbol == NULL
3181 || pool->next_free_entry == 0)
3184 mapping_state (MAP_DATA);
3186 /* Align pool as you have word accesses.
3187 Only make a frag if we have to. */
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg, 2);
3193 sprintf (sym_name, "$$lit_\002%x", pool->id);
3195 symbol_locate (pool->symbol, sym_name, now_seg,
3196 (valueT) frag_now_fix (), frag_now);
3197 symbol_table_insert (pool->symbol);
3199 ARM_SET_THUMB (pool->symbol, thumb_mode);
3201 #if defined OBJ_COFF || defined OBJ_ELF
3202 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3205 for (entry = 0; entry < pool->next_free_entry; entry ++)
3208 if (debug_type == DEBUG_DWARF2)
3209 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3211 /* First output the expression in the instruction to the pool. */
3212 emit_expr (&(pool->literals[entry]), 4); /* .word */
3215 /* Mark the pool as empty. */
3216 pool->next_free_entry = 0;
3217 pool->symbol = NULL;
3221 /* Forward declarations for functions below, in the MD interface
3223 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3224 static valueT create_unwind_entry (int);
3225 static void start_unwind_section (const segT, int);
3226 static void add_unwind_opcode (valueT, int);
3227 static void flush_pending_unwind (void);
3229 /* Directives: Data. */
3232 s_arm_elf_cons (int nbytes)
3236 #ifdef md_flush_pending_output
3237 md_flush_pending_output ();
3240 if (is_it_end_of_statement ())
3242 demand_empty_rest_of_line ();
3246 #ifdef md_cons_align
3247 md_cons_align (nbytes);
3250 mapping_state (MAP_DATA);
3254 char *base = input_line_pointer;
3258 if (exp.X_op != O_symbol)
3259 emit_expr (&exp, (unsigned int) nbytes);
3262 char *before_reloc = input_line_pointer;
3263 reloc = parse_reloc (&input_line_pointer);
3266 as_bad (_("unrecognized relocation suffix"));
3267 ignore_rest_of_line ();
3270 else if (reloc == BFD_RELOC_UNUSED)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 reloc_howto_type *howto = (reloc_howto_type *)
3275 bfd_reloc_type_lookup (stdoutput,
3276 (bfd_reloc_code_real_type) reloc);
3277 int size = bfd_get_reloc_size (howto);
3279 if (reloc == BFD_RELOC_ARM_PLT32)
3281 as_bad (_("(plt) is only valid on branch targets"));
3282 reloc = BFD_RELOC_UNUSED;
3287 as_bad (_("%s relocations do not fit in %d bytes"),
3288 howto->name, nbytes);
3291 /* We've parsed an expression stopping at O_symbol.
3292 But there may be more expression left now that we
3293 have parsed the relocation marker. Parse it again.
3294 XXX Surely there is a cleaner way to do this. */
3295 char *p = input_line_pointer;
3297 char *save_buf = (char *) alloca (input_line_pointer - base);
3298 memcpy (save_buf, base, input_line_pointer - base);
3299 memmove (base + (input_line_pointer - before_reloc),
3300 base, before_reloc - base);
3302 input_line_pointer = base + (input_line_pointer-before_reloc);
3304 memcpy (base, save_buf, p - base);
3306 offset = nbytes - size;
3307 p = frag_more ((int) nbytes);
3308 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3309 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3314 while (*input_line_pointer++ == ',');
3316 /* Put terminator back into stream. */
3317 input_line_pointer --;
3318 demand_empty_rest_of_line ();
3321 /* Emit an expression containing a 32-bit thumb instruction.
3322 Implementation based on put_thumb32_insn. */
3325 emit_thumb32_expr (expressionS * exp)
3327 expressionS exp_high = *exp;
3329 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3330 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3331 exp->X_add_number &= 0xffff;
3332 emit_expr (exp, (unsigned int) THUMB_SIZE);
3335 /* Guess the instruction size based on the opcode. */
3338 thumb_insn_size (int opcode)
3340 if ((unsigned int) opcode < 0xe800u)
3342 else if ((unsigned int) opcode >= 0xe8000000u)
3349 emit_insn (expressionS *exp, int nbytes)
3353 if (exp->X_op == O_constant)
3358 size = thumb_insn_size (exp->X_add_number);
3362 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3364 as_bad (_(".inst.n operand too big. "\
3365 "Use .inst.w instead"));
3370 if (now_it.state == AUTOMATIC_IT_BLOCK)
3371 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3373 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3375 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3376 emit_thumb32_expr (exp);
3378 emit_expr (exp, (unsigned int) size);
3380 it_fsm_post_encode ();
3384 as_bad (_("cannot determine Thumb instruction size. " \
3385 "Use .inst.n/.inst.w instead"));
3388 as_bad (_("constant expression required"));
3393 /* Like s_arm_elf_cons but do not use md_cons_align and
3394 set the mapping state to MAP_ARM/MAP_THUMB. */
3397 s_arm_elf_inst (int nbytes)
3399 if (is_it_end_of_statement ())
3401 demand_empty_rest_of_line ();
3405 /* Calling mapping_state () here will not change ARM/THUMB,
3406 but will ensure not to be in DATA state. */
3409 mapping_state (MAP_THUMB);
3414 as_bad (_("width suffixes are invalid in ARM mode"));
3415 ignore_rest_of_line ();
3421 mapping_state (MAP_ARM);
3430 if (! emit_insn (& exp, nbytes))
3432 ignore_rest_of_line ();
3436 while (*input_line_pointer++ == ',');
3438 /* Put terminator back into stream. */
3439 input_line_pointer --;
3440 demand_empty_rest_of_line ();
3443 /* Parse a .rel31 directive. */
3446 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3453 if (*input_line_pointer == '1')
3454 highbit = 0x80000000;
3455 else if (*input_line_pointer != '0')
3456 as_bad (_("expected 0 or 1"));
3458 input_line_pointer++;
3459 if (*input_line_pointer != ',')
3460 as_bad (_("missing comma"));
3461 input_line_pointer++;
3463 #ifdef md_flush_pending_output
3464 md_flush_pending_output ();
3467 #ifdef md_cons_align
3471 mapping_state (MAP_DATA);
3476 md_number_to_chars (p, highbit, 4);
3477 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3478 BFD_RELOC_ARM_PREL31);
3480 demand_empty_rest_of_line ();
3483 /* Directives: AEABI stack-unwind tables. */
3485 /* Parse an unwind_fnstart directive. Simply records the current location. */
3488 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3490 demand_empty_rest_of_line ();
3491 if (unwind.proc_start)
3493 as_bad (_("duplicate .fnstart directive"));
3497 /* Mark the start of the function. */
3498 unwind.proc_start = expr_build_dot ();
3500 /* Reset the rest of the unwind info. */
3501 unwind.opcode_count = 0;
3502 unwind.table_entry = NULL;
3503 unwind.personality_routine = NULL;
3504 unwind.personality_index = -1;
3505 unwind.frame_size = 0;
3506 unwind.fp_offset = 0;
3507 unwind.fp_reg = REG_SP;
3509 unwind.sp_restored = 0;
3513 /* Parse a handlerdata directive. Creates the exception handling table entry
3514 for the function. */
3517 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3519 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3521 as_bad (MISSING_FNSTART);
3523 if (unwind.table_entry)
3524 as_bad (_("duplicate .handlerdata directive"));
3526 create_unwind_entry (1);
3529 /* Parse an unwind_fnend directive. Generates the index table entry. */
3532 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3537 unsigned int marked_pr_dependency;
3539 demand_empty_rest_of_line ();
3541 if (!unwind.proc_start)
3543 as_bad (_(".fnend directive without .fnstart"));
3547 /* Add eh table entry. */
3548 if (unwind.table_entry == NULL)
3549 val = create_unwind_entry (0);
3553 /* Add index table entry. This is two words. */
3554 start_unwind_section (unwind.saved_seg, 1);
3555 frag_align (2, 0, 0);
3556 record_alignment (now_seg, 2);
3558 ptr = frag_more (8);
3560 where = frag_now_fix () - 8;
3562 /* Self relative offset of the function start. */
3563 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3564 BFD_RELOC_ARM_PREL31);
3566 /* Indicate dependency on EHABI-defined personality routines to the
3567 linker, if it hasn't been done already. */
3568 marked_pr_dependency
3569 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3570 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3571 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3573 static const char *const name[] =
3575 "__aeabi_unwind_cpp_pr0",
3576 "__aeabi_unwind_cpp_pr1",
3577 "__aeabi_unwind_cpp_pr2"
3579 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3580 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3581 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3582 |= 1 << unwind.personality_index;
3586 /* Inline exception table entry. */
3587 md_number_to_chars (ptr + 4, val, 4);
3589 /* Self relative offset of the table entry. */
3590 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3591 BFD_RELOC_ARM_PREL31);
3593 /* Restore the original section. */
3594 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3596 unwind.proc_start = NULL;
3600 /* Parse an unwind_cantunwind directive. */
3603 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3605 demand_empty_rest_of_line ();
3606 if (!unwind.proc_start)
3607 as_bad (MISSING_FNSTART);
3609 if (unwind.personality_routine || unwind.personality_index != -1)
3610 as_bad (_("personality routine specified for cantunwind frame"));
3612 unwind.personality_index = -2;
3616 /* Parse a personalityindex directive. */
3619 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3623 if (!unwind.proc_start)
3624 as_bad (MISSING_FNSTART);
3626 if (unwind.personality_routine || unwind.personality_index != -1)
3627 as_bad (_("duplicate .personalityindex directive"));
3631 if (exp.X_op != O_constant
3632 || exp.X_add_number < 0 || exp.X_add_number > 15)
3634 as_bad (_("bad personality routine number"));
3635 ignore_rest_of_line ();
3639 unwind.personality_index = exp.X_add_number;
3641 demand_empty_rest_of_line ();
3645 /* Parse a personality directive. */
3648 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3652 if (!unwind.proc_start)
3653 as_bad (MISSING_FNSTART);
3655 if (unwind.personality_routine || unwind.personality_index != -1)
3656 as_bad (_("duplicate .personality directive"));
3658 name = input_line_pointer;
3659 c = get_symbol_end ();
3660 p = input_line_pointer;
3661 unwind.personality_routine = symbol_find_or_make (name);
3663 demand_empty_rest_of_line ();
3667 /* Parse a directive saving core registers. */
3670 s_arm_unwind_save_core (void)
3676 range = parse_reg_list (&input_line_pointer);
3679 as_bad (_("expected register list"));
3680 ignore_rest_of_line ();
3684 demand_empty_rest_of_line ();
3686 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3687 into .unwind_save {..., sp...}. We aren't bothered about the value of
3688 ip because it is clobbered by calls. */
3689 if (unwind.sp_restored && unwind.fp_reg == 12
3690 && (range & 0x3000) == 0x1000)
3692 unwind.opcode_count--;
3693 unwind.sp_restored = 0;
3694 range = (range | 0x2000) & ~0x1000;
3695 unwind.pending_offset = 0;
3701 /* See if we can use the short opcodes. These pop a block of up to 8
3702 registers starting with r4, plus maybe r14. */
3703 for (n = 0; n < 8; n++)
3705 /* Break at the first non-saved register. */
3706 if ((range & (1 << (n + 4))) == 0)
3709 /* See if there are any other bits set. */
3710 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3712 /* Use the long form. */
3713 op = 0x8000 | ((range >> 4) & 0xfff);
3714 add_unwind_opcode (op, 2);
3718 /* Use the short form. */
3720 op = 0xa8; /* Pop r14. */
3722 op = 0xa0; /* Do not pop r14. */
3724 add_unwind_opcode (op, 1);
3731 op = 0xb100 | (range & 0xf);
3732 add_unwind_opcode (op, 2);
3735 /* Record the number of bytes pushed. */
3736 for (n = 0; n < 16; n++)
3738 if (range & (1 << n))
3739 unwind.frame_size += 4;
3744 /* Parse a directive saving FPA registers. */
3747 s_arm_unwind_save_fpa (int reg)
3753 /* Get Number of registers to transfer. */
3754 if (skip_past_comma (&input_line_pointer) != FAIL)
3757 exp.X_op = O_illegal;
3759 if (exp.X_op != O_constant)
3761 as_bad (_("expected , <constant>"));
3762 ignore_rest_of_line ();
3766 num_regs = exp.X_add_number;
3768 if (num_regs < 1 || num_regs > 4)
3770 as_bad (_("number of registers must be in the range [1:4]"));
3771 ignore_rest_of_line ();
3775 demand_empty_rest_of_line ();
3780 op = 0xb4 | (num_regs - 1);
3781 add_unwind_opcode (op, 1);
3786 op = 0xc800 | (reg << 4) | (num_regs - 1);
3787 add_unwind_opcode (op, 2);
3789 unwind.frame_size += num_regs * 12;
3793 /* Parse a directive saving VFP registers for ARMv6 and above. */
3796 s_arm_unwind_save_vfp_armv6 (void)
3801 int num_vfpv3_regs = 0;
3802 int num_regs_below_16;
3804 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3807 as_bad (_("expected register list"));
3808 ignore_rest_of_line ();
3812 demand_empty_rest_of_line ();
3814 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3815 than FSTMX/FLDMX-style ones). */
3817 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3819 num_vfpv3_regs = count;
3820 else if (start + count > 16)
3821 num_vfpv3_regs = start + count - 16;
3823 if (num_vfpv3_regs > 0)
3825 int start_offset = start > 16 ? start - 16 : 0;
3826 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3827 add_unwind_opcode (op, 2);
3830 /* Generate opcode for registers numbered in the range 0 .. 15. */
3831 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3832 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3833 if (num_regs_below_16 > 0)
3835 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3836 add_unwind_opcode (op, 2);
3839 unwind.frame_size += count * 8;
3843 /* Parse a directive saving VFP registers for pre-ARMv6. */
3846 s_arm_unwind_save_vfp (void)
3852 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3855 as_bad (_("expected register list"));
3856 ignore_rest_of_line ();
3860 demand_empty_rest_of_line ();
3865 op = 0xb8 | (count - 1);
3866 add_unwind_opcode (op, 1);
3871 op = 0xb300 | (reg << 4) | (count - 1);
3872 add_unwind_opcode (op, 2);
3874 unwind.frame_size += count * 8 + 4;
3878 /* Parse a directive saving iWMMXt data registers. */
3881 s_arm_unwind_save_mmxwr (void)
3889 if (*input_line_pointer == '{')
3890 input_line_pointer++;
3894 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3898 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3903 as_tsktsk (_("register list not in ascending order"));
3906 if (*input_line_pointer == '-')
3908 input_line_pointer++;
3909 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3912 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 else if (reg >= hi_reg)
3917 as_bad (_("bad register range"));
3920 for (; reg < hi_reg; reg++)
3924 while (skip_past_comma (&input_line_pointer) != FAIL);
3926 if (*input_line_pointer == '}')
3927 input_line_pointer++;
3929 demand_empty_rest_of_line ();
3931 /* Generate any deferred opcodes because we're going to be looking at
3933 flush_pending_unwind ();
3935 for (i = 0; i < 16; i++)
3937 if (mask & (1 << i))
3938 unwind.frame_size += 8;
3941 /* Attempt to combine with a previous opcode. We do this because gcc
3942 likes to output separate unwind directives for a single block of
3944 if (unwind.opcode_count > 0)
3946 i = unwind.opcodes[unwind.opcode_count - 1];
3947 if ((i & 0xf8) == 0xc0)
3950 /* Only merge if the blocks are contiguous. */
3953 if ((mask & 0xfe00) == (1 << 9))
3955 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3956 unwind.opcode_count--;
3959 else if (i == 6 && unwind.opcode_count >= 2)
3961 i = unwind.opcodes[unwind.opcode_count - 2];
3965 op = 0xffff << (reg - 1);
3967 && ((mask & op) == (1u << (reg - 1))))
3969 op = (1 << (reg + i + 1)) - 1;
3970 op &= ~((1 << reg) - 1);
3972 unwind.opcode_count -= 2;
3979 /* We want to generate opcodes in the order the registers have been
3980 saved, ie. descending order. */
3981 for (reg = 15; reg >= -1; reg--)
3983 /* Save registers in blocks. */
3985 || !(mask & (1 << reg)))
3987 /* We found an unsaved reg. Generate opcodes to save the
3994 op = 0xc0 | (hi_reg - 10);
3995 add_unwind_opcode (op, 1);
4000 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4001 add_unwind_opcode (op, 2);
4010 ignore_rest_of_line ();
4014 s_arm_unwind_save_mmxwcg (void)
4021 if (*input_line_pointer == '{')
4022 input_line_pointer++;
4026 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4030 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4036 as_tsktsk (_("register list not in ascending order"));
4039 if (*input_line_pointer == '-')
4041 input_line_pointer++;
4042 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4045 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4048 else if (reg >= hi_reg)
4050 as_bad (_("bad register range"));
4053 for (; reg < hi_reg; reg++)
4057 while (skip_past_comma (&input_line_pointer) != FAIL);
4059 if (*input_line_pointer == '}')
4060 input_line_pointer++;
4062 demand_empty_rest_of_line ();
4064 /* Generate any deferred opcodes because we're going to be looking at
4066 flush_pending_unwind ();
4068 for (reg = 0; reg < 16; reg++)
4070 if (mask & (1 << reg))
4071 unwind.frame_size += 4;
4074 add_unwind_opcode (op, 2);
4077 ignore_rest_of_line ();
4081 /* Parse an unwind_save directive.
4082 If the argument is non-zero, this is a .vsave directive. */
4085 s_arm_unwind_save (int arch_v6)
4088 struct reg_entry *reg;
4089 bfd_boolean had_brace = FALSE;
4091 if (!unwind.proc_start)
4092 as_bad (MISSING_FNSTART);
4094 /* Figure out what sort of save we have. */
4095 peek = input_line_pointer;
4103 reg = arm_reg_parse_multi (&peek);
4107 as_bad (_("register expected"));
4108 ignore_rest_of_line ();
4117 as_bad (_("FPA .unwind_save does not take a register list"));
4118 ignore_rest_of_line ();
4121 input_line_pointer = peek;
4122 s_arm_unwind_save_fpa (reg->number);
4125 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4128 s_arm_unwind_save_vfp_armv6 ();
4130 s_arm_unwind_save_vfp ();
4132 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4133 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4136 as_bad (_(".unwind_save does not support this kind of register"));
4137 ignore_rest_of_line ();
4142 /* Parse an unwind_movsp directive. */
4145 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4151 if (!unwind.proc_start)
4152 as_bad (MISSING_FNSTART);
4154 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4157 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4158 ignore_rest_of_line ();
4162 /* Optional constant. */
4163 if (skip_past_comma (&input_line_pointer) != FAIL)
4165 if (immediate_for_directive (&offset) == FAIL)
4171 demand_empty_rest_of_line ();
4173 if (reg == REG_SP || reg == REG_PC)
4175 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4179 if (unwind.fp_reg != REG_SP)
4180 as_bad (_("unexpected .unwind_movsp directive"));
4182 /* Generate opcode to restore the value. */
4184 add_unwind_opcode (op, 1);
4186 /* Record the information for later. */
4187 unwind.fp_reg = reg;
4188 unwind.fp_offset = unwind.frame_size - offset;
4189 unwind.sp_restored = 1;
4192 /* Parse an unwind_pad directive. */
4195 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4199 if (!unwind.proc_start)
4200 as_bad (MISSING_FNSTART);
4202 if (immediate_for_directive (&offset) == FAIL)
4207 as_bad (_("stack increment must be multiple of 4"));
4208 ignore_rest_of_line ();
4212 /* Don't generate any opcodes, just record the details for later. */
4213 unwind.frame_size += offset;
4214 unwind.pending_offset += offset;
4216 demand_empty_rest_of_line ();
4219 /* Parse an unwind_setfp directive. */
4222 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4228 if (!unwind.proc_start)
4229 as_bad (MISSING_FNSTART);
4231 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4232 if (skip_past_comma (&input_line_pointer) == FAIL)
4235 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4237 if (fp_reg == FAIL || sp_reg == FAIL)
4239 as_bad (_("expected <reg>, <reg>"));
4240 ignore_rest_of_line ();
4244 /* Optional constant. */
4245 if (skip_past_comma (&input_line_pointer) != FAIL)
4247 if (immediate_for_directive (&offset) == FAIL)
4253 demand_empty_rest_of_line ();
4255 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4257 as_bad (_("register must be either sp or set by a previous"
4258 "unwind_movsp directive"));
4262 /* Don't generate any opcodes, just record the information for later. */
4263 unwind.fp_reg = fp_reg;
4265 if (sp_reg == REG_SP)
4266 unwind.fp_offset = unwind.frame_size - offset;
4268 unwind.fp_offset -= offset;
4271 /* Parse an unwind_raw directive. */
4274 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4277 /* This is an arbitrary limit. */
4278 unsigned char op[16];
4281 if (!unwind.proc_start)
4282 as_bad (MISSING_FNSTART);
4285 if (exp.X_op == O_constant
4286 && skip_past_comma (&input_line_pointer) != FAIL)
4288 unwind.frame_size += exp.X_add_number;
4292 exp.X_op = O_illegal;
4294 if (exp.X_op != O_constant)
4296 as_bad (_("expected <offset>, <opcode>"));
4297 ignore_rest_of_line ();
4303 /* Parse the opcode. */
4308 as_bad (_("unwind opcode too long"));
4309 ignore_rest_of_line ();
4311 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4313 as_bad (_("invalid unwind opcode"));
4314 ignore_rest_of_line ();
4317 op[count++] = exp.X_add_number;
4319 /* Parse the next byte. */
4320 if (skip_past_comma (&input_line_pointer) == FAIL)
4326 /* Add the opcode bytes in reverse order. */
4328 add_unwind_opcode (op[count], 1);
4330 demand_empty_rest_of_line ();
4334 /* Parse a .eabi_attribute directive. */
4337 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4339 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4341 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4342 attributes_set_explicitly[tag] = 1;
4345 /* Emit a tls fix for the symbol. */
4348 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4352 #ifdef md_flush_pending_output
4353 md_flush_pending_output ();
4356 #ifdef md_cons_align
4360 /* Since we're just labelling the code, there's no need to define a
4363 p = obstack_next_free (&frchain_now->frch_obstack);
4364 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4365 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4366 : BFD_RELOC_ARM_TLS_DESCSEQ);
4368 #endif /* OBJ_ELF */
4370 static void s_arm_arch (int);
4371 static void s_arm_object_arch (int);
4372 static void s_arm_cpu (int);
4373 static void s_arm_fpu (int);
4374 static void s_arm_arch_extension (int);
4379 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4386 if (exp.X_op == O_symbol)
4387 exp.X_op = O_secrel;
4389 emit_expr (&exp, 4);
4391 while (*input_line_pointer++ == ',');
4393 input_line_pointer--;
4394 demand_empty_rest_of_line ();
4398 /* This table describes all the machine specific pseudo-ops the assembler
4399 has to support. The fields are:
4400 pseudo-op name without dot
4401 function to call to execute this pseudo-op
4402 Integer arg to pass to the function. */
4404 const pseudo_typeS md_pseudo_table[] =
4406 /* Never called because '.req' does not start a line. */
4407 { "req", s_req, 0 },
4408 /* Following two are likewise never called. */
4411 { "unreq", s_unreq, 0 },
4412 { "bss", s_bss, 0 },
4413 { "align", s_align, 0 },
4414 { "arm", s_arm, 0 },
4415 { "thumb", s_thumb, 0 },
4416 { "code", s_code, 0 },
4417 { "force_thumb", s_force_thumb, 0 },
4418 { "thumb_func", s_thumb_func, 0 },
4419 { "thumb_set", s_thumb_set, 0 },
4420 { "even", s_even, 0 },
4421 { "ltorg", s_ltorg, 0 },
4422 { "pool", s_ltorg, 0 },
4423 { "syntax", s_syntax, 0 },
4424 { "cpu", s_arm_cpu, 0 },
4425 { "arch", s_arm_arch, 0 },
4426 { "object_arch", s_arm_object_arch, 0 },
4427 { "fpu", s_arm_fpu, 0 },
4428 { "arch_extension", s_arm_arch_extension, 0 },
4430 { "word", s_arm_elf_cons, 4 },
4431 { "long", s_arm_elf_cons, 4 },
4432 { "inst.n", s_arm_elf_inst, 2 },
4433 { "inst.w", s_arm_elf_inst, 4 },
4434 { "inst", s_arm_elf_inst, 0 },
4435 { "rel31", s_arm_rel31, 0 },
4436 { "fnstart", s_arm_unwind_fnstart, 0 },
4437 { "fnend", s_arm_unwind_fnend, 0 },
4438 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4439 { "personality", s_arm_unwind_personality, 0 },
4440 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4441 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4442 { "save", s_arm_unwind_save, 0 },
4443 { "vsave", s_arm_unwind_save, 1 },
4444 { "movsp", s_arm_unwind_movsp, 0 },
4445 { "pad", s_arm_unwind_pad, 0 },
4446 { "setfp", s_arm_unwind_setfp, 0 },
4447 { "unwind_raw", s_arm_unwind_raw, 0 },
4448 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4449 { "tlsdescseq", s_arm_tls_descseq, 0 },
4453 /* These are used for dwarf. */
4457 /* These are used for dwarf2. */
4458 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4459 { "loc", dwarf2_directive_loc, 0 },
4460 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4462 { "extend", float_cons, 'x' },
4463 { "ldouble", float_cons, 'x' },
4464 { "packed", float_cons, 'p' },
4466 {"secrel32", pe_directive_secrel, 0},
4471 /* Parser functions used exclusively in instruction operands. */
4473 /* Generic immediate-value read function for use in insn parsing.
4474 STR points to the beginning of the immediate (the leading #);
4475 VAL receives the value; if the value is outside [MIN, MAX]
4476 issue an error. PREFIX_OPT is true if the immediate prefix is
4480 parse_immediate (char **str, int *val, int min, int max,
4481 bfd_boolean prefix_opt)
4484 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4485 if (exp.X_op != O_constant)
4487 inst.error = _("constant expression required");
4491 if (exp.X_add_number < min || exp.X_add_number > max)
4493 inst.error = _("immediate value out of range");
4497 *val = exp.X_add_number;
4501 /* Less-generic immediate-value read function with the possibility of loading a
4502 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4503 instructions. Puts the result directly in inst.operands[i]. */
4506 parse_big_immediate (char **str, int i)
4511 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4513 if (exp.X_op == O_constant)
4515 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4516 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4517 O_constant. We have to be careful not to break compilation for
4518 32-bit X_add_number, though. */
4519 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4521 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4522 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4523 inst.operands[i].regisimm = 1;
4526 else if (exp.X_op == O_big
4527 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4529 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4531 /* Bignums have their least significant bits in
4532 generic_bignum[0]. Make sure we put 32 bits in imm and
4533 32 bits in reg, in a (hopefully) portable way. */
4534 gas_assert (parts != 0);
4536 /* Make sure that the number is not too big.
4537 PR 11972: Bignums can now be sign-extended to the
4538 size of a .octa so check that the out of range bits
4539 are all zero or all one. */
4540 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4542 LITTLENUM_TYPE m = -1;
4544 if (generic_bignum[parts * 2] != 0
4545 && generic_bignum[parts * 2] != m)
4548 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4549 if (generic_bignum[j] != generic_bignum[j-1])
4553 inst.operands[i].imm = 0;
4554 for (j = 0; j < parts; j++, idx++)
4555 inst.operands[i].imm |= generic_bignum[idx]
4556 << (LITTLENUM_NUMBER_OF_BITS * j);
4557 inst.operands[i].reg = 0;
4558 for (j = 0; j < parts; j++, idx++)
4559 inst.operands[i].reg |= generic_bignum[idx]
4560 << (LITTLENUM_NUMBER_OF_BITS * j);
4561 inst.operands[i].regisimm = 1;
4571 /* Returns the pseudo-register number of an FPA immediate constant,
4572 or FAIL if there isn't a valid constant here. */
4575 parse_fpa_immediate (char ** str)
4577 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4583 /* First try and match exact strings, this is to guarantee
4584 that some formats will work even for cross assembly. */
4586 for (i = 0; fp_const[i]; i++)
4588 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4592 *str += strlen (fp_const[i]);
4593 if (is_end_of_line[(unsigned char) **str])
4599 /* Just because we didn't get a match doesn't mean that the constant
4600 isn't valid, just that it is in a format that we don't
4601 automatically recognize. Try parsing it with the standard
4602 expression routines. */
4604 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4606 /* Look for a raw floating point number. */
4607 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4608 && is_end_of_line[(unsigned char) *save_in])
4610 for (i = 0; i < NUM_FLOAT_VALS; i++)
4612 for (j = 0; j < MAX_LITTLENUMS; j++)
4614 if (words[j] != fp_values[i][j])
4618 if (j == MAX_LITTLENUMS)
4626 /* Try and parse a more complex expression, this will probably fail
4627 unless the code uses a floating point prefix (eg "0f"). */
4628 save_in = input_line_pointer;
4629 input_line_pointer = *str;
4630 if (expression (&exp) == absolute_section
4631 && exp.X_op == O_big
4632 && exp.X_add_number < 0)
4634 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4636 if (gen_to_words (words, 5, (long) 15) == 0)
4638 for (i = 0; i < NUM_FLOAT_VALS; i++)
4640 for (j = 0; j < MAX_LITTLENUMS; j++)
4642 if (words[j] != fp_values[i][j])
4646 if (j == MAX_LITTLENUMS)
4648 *str = input_line_pointer;
4649 input_line_pointer = save_in;
4656 *str = input_line_pointer;
4657 input_line_pointer = save_in;
4658 inst.error = _("invalid FPA immediate expression");
4662 /* Returns 1 if a number has "quarter-precision" float format
4663 0baBbbbbbc defgh000 00000000 00000000. */
4666 is_quarter_float (unsigned imm)
4668 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4669 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4672 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4673 0baBbbbbbc defgh000 00000000 00000000.
4674 The zero and minus-zero cases need special handling, since they can't be
4675 encoded in the "quarter-precision" float format, but can nonetheless be
4676 loaded as integer constants. */
4679 parse_qfloat_immediate (char **ccp, int *immed)
4683 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4684 int found_fpchar = 0;
4686 skip_past_char (&str, '#');
4688 /* We must not accidentally parse an integer as a floating-point number. Make
4689 sure that the value we parse is not an integer by checking for special
4690 characters '.' or 'e'.
4691 FIXME: This is a horrible hack, but doing better is tricky because type
4692 information isn't in a very usable state at parse time. */
4694 skip_whitespace (fpnum);
4696 if (strncmp (fpnum, "0x", 2) == 0)
4700 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4701 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4711 if ((str = atof_ieee (str, 's', words)) != NULL)
4713 unsigned fpword = 0;
4716 /* Our FP word must be 32 bits (single-precision FP). */
4717 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4719 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4723 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4736 /* Shift operands. */
4739 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4742 struct asm_shift_name
4745 enum shift_kind kind;
4748 /* Third argument to parse_shift. */
4749 enum parse_shift_mode
4751 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4752 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4753 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4754 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4755 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4758 /* Parse a <shift> specifier on an ARM data processing instruction.
4759 This has three forms:
4761 (LSL|LSR|ASL|ASR|ROR) Rs
4762 (LSL|LSR|ASL|ASR|ROR) #imm
4765 Note that ASL is assimilated to LSL in the instruction encoding, and
4766 RRX to ROR #0 (which cannot be written as such). */
4769 parse_shift (char **str, int i, enum parse_shift_mode mode)
4771 const struct asm_shift_name *shift_name;
4772 enum shift_kind shift;
4777 for (p = *str; ISALPHA (*p); p++)
4782 inst.error = _("shift expression expected");
4786 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4789 if (shift_name == NULL)
4791 inst.error = _("shift expression expected");
4795 shift = shift_name->kind;
4799 case NO_SHIFT_RESTRICT:
4800 case SHIFT_IMMEDIATE: break;
4802 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4803 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4805 inst.error = _("'LSL' or 'ASR' required");
4810 case SHIFT_LSL_IMMEDIATE:
4811 if (shift != SHIFT_LSL)
4813 inst.error = _("'LSL' required");
4818 case SHIFT_ASR_IMMEDIATE:
4819 if (shift != SHIFT_ASR)
4821 inst.error = _("'ASR' required");
4829 if (shift != SHIFT_RRX)
4831 /* Whitespace can appear here if the next thing is a bare digit. */
4832 skip_whitespace (p);
4834 if (mode == NO_SHIFT_RESTRICT
4835 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4837 inst.operands[i].imm = reg;
4838 inst.operands[i].immisreg = 1;
4840 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4843 inst.operands[i].shift_kind = shift;
4844 inst.operands[i].shifted = 1;
4849 /* Parse a <shifter_operand> for an ARM data processing instruction:
4852 #<immediate>, <rotate>
4856 where <shift> is defined by parse_shift above, and <rotate> is a
4857 multiple of 2 between 0 and 30. Validation of immediate operands
4858 is deferred to md_apply_fix. */
4861 parse_shifter_operand (char **str, int i)
4866 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4868 inst.operands[i].reg = value;
4869 inst.operands[i].isreg = 1;
4871 /* parse_shift will override this if appropriate */
4872 inst.reloc.exp.X_op = O_constant;
4873 inst.reloc.exp.X_add_number = 0;
4875 if (skip_past_comma (str) == FAIL)
4878 /* Shift operation on register. */
4879 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4882 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4885 if (skip_past_comma (str) == SUCCESS)
4887 /* #x, y -- ie explicit rotation by Y. */
4888 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4891 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4893 inst.error = _("constant expression expected");
4897 value = exp.X_add_number;
4898 if (value < 0 || value > 30 || value % 2 != 0)
4900 inst.error = _("invalid rotation");
4903 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4905 inst.error = _("invalid constant");
4909 /* Encode as specified. */
4910 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4914 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4915 inst.reloc.pc_rel = 0;
4919 /* Group relocation information. Each entry in the table contains the
4920 textual name of the relocation as may appear in assembler source
4921 and must end with a colon.
4922 Along with this textual name are the relocation codes to be used if
4923 the corresponding instruction is an ALU instruction (ADD or SUB only),
4924 an LDR, an LDRS, or an LDC. */
4926 struct group_reloc_table_entry
4937 /* Varieties of non-ALU group relocation. */
4944 static struct group_reloc_table_entry group_reloc_table[] =
4945 { /* Program counter relative: */
4947 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4952 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4953 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4954 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4955 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4957 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4962 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4963 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4964 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4965 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4967 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4968 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4969 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4970 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4971 /* Section base relative */
4973 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4978 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4979 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4980 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4981 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4983 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4988 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4989 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4990 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4991 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4993 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4994 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4995 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4996 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4998 /* Given the address of a pointer pointing to the textual name of a group
4999 relocation as may appear in assembler source, attempt to find its details
5000 in group_reloc_table. The pointer will be updated to the character after
5001 the trailing colon. On failure, FAIL will be returned; SUCCESS
5002 otherwise. On success, *entry will be updated to point at the relevant
5003 group_reloc_table entry. */
5006 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5009 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5011 int length = strlen (group_reloc_table[i].name);
5013 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5014 && (*str)[length] == ':')
5016 *out = &group_reloc_table[i];
5017 *str += (length + 1);
5025 /* Parse a <shifter_operand> for an ARM data processing instruction
5026 (as for parse_shifter_operand) where group relocations are allowed:
5029 #<immediate>, <rotate>
5030 #:<group_reloc>:<expression>
5034 where <group_reloc> is one of the strings defined in group_reloc_table.
5035 The hashes are optional.
5037 Everything else is as for parse_shifter_operand. */
5039 static parse_operand_result
5040 parse_shifter_operand_group_reloc (char **str, int i)
5042 /* Determine if we have the sequence of characters #: or just :
5043 coming next. If we do, then we check for a group relocation.
5044 If we don't, punt the whole lot to parse_shifter_operand. */
5046 if (((*str)[0] == '#' && (*str)[1] == ':')
5047 || (*str)[0] == ':')
5049 struct group_reloc_table_entry *entry;
5051 if ((*str)[0] == '#')
5056 /* Try to parse a group relocation. Anything else is an error. */
5057 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5059 inst.error = _("unknown group relocation");
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5063 /* We now have the group relocation table entry corresponding to
5064 the name in the assembler source. Next, we parse the expression. */
5065 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5066 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5068 /* Record the relocation type (always the ALU variant here). */
5069 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5070 gas_assert (inst.reloc.type != 0);
5072 return PARSE_OPERAND_SUCCESS;
5075 return parse_shifter_operand (str, i) == SUCCESS
5076 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5078 /* Never reached. */
5081 /* Parse a Neon alignment expression. Information is written to
5082 inst.operands[i]. We assume the initial ':' has been skipped.
5084 align .imm = align << 8, .immisalign=1, .preind=0 */
5085 static parse_operand_result
5086 parse_neon_alignment (char **str, int i)
5091 my_get_expression (&exp, &p, GE_NO_PREFIX);
5093 if (exp.X_op != O_constant)
5095 inst.error = _("alignment must be constant");
5096 return PARSE_OPERAND_FAIL;
5099 inst.operands[i].imm = exp.X_add_number << 8;
5100 inst.operands[i].immisalign = 1;
5101 /* Alignments are not pre-indexes. */
5102 inst.operands[i].preind = 0;
5105 return PARSE_OPERAND_SUCCESS;
5108 /* Parse all forms of an ARM address expression. Information is written
5109 to inst.operands[i] and/or inst.reloc.
5111 Preindexed addressing (.preind=1):
5113 [Rn, #offset] .reg=Rn .reloc.exp=offset
5114 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 .shift_kind=shift .reloc.exp=shift_imm
5118 These three may have a trailing ! which causes .writeback to be set also.
5120 Postindexed addressing (.postind=1, .writeback=1):
5122 [Rn], #offset .reg=Rn .reloc.exp=offset
5123 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 Unindexed addressing (.preind=0, .postind=0):
5129 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5133 [Rn]{!} shorthand for [Rn,#0]{!}
5134 =immediate .isreg=0 .reloc.exp=immediate
5135 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5137 It is the caller's responsibility to check for addressing modes not
5138 supported by the instruction, and to set inst.reloc.type. */
5140 static parse_operand_result
5141 parse_address_main (char **str, int i, int group_relocations,
5142 group_reloc_type group_type)
5147 if (skip_past_char (&p, '[') == FAIL)
5149 if (skip_past_char (&p, '=') == FAIL)
5151 /* Bare address - translate to PC-relative offset. */
5152 inst.reloc.pc_rel = 1;
5153 inst.operands[i].reg = REG_PC;
5154 inst.operands[i].isreg = 1;
5155 inst.operands[i].preind = 1;
5157 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5159 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5160 return PARSE_OPERAND_FAIL;
5163 return PARSE_OPERAND_SUCCESS;
5166 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5168 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5169 return PARSE_OPERAND_FAIL;
5171 inst.operands[i].reg = reg;
5172 inst.operands[i].isreg = 1;
5174 if (skip_past_comma (&p) == SUCCESS)
5176 inst.operands[i].preind = 1;
5179 else if (*p == '-') p++, inst.operands[i].negative = 1;
5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5183 inst.operands[i].imm = reg;
5184 inst.operands[i].immisreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5187 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5188 return PARSE_OPERAND_FAIL;
5190 else if (skip_past_char (&p, ':') == SUCCESS)
5192 /* FIXME: '@' should be used here, but it's filtered out by generic
5193 code before we get to see it here. This may be subject to
5195 parse_operand_result result = parse_neon_alignment (&p, i);
5197 if (result != PARSE_OPERAND_SUCCESS)
5202 if (inst.operands[i].negative)
5204 inst.operands[i].negative = 0;
5208 if (group_relocations
5209 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5211 struct group_reloc_table_entry *entry;
5213 /* Skip over the #: or : sequence. */
5219 /* Try to parse a group relocation. Anything else is an
5221 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5223 inst.error = _("unknown group relocation");
5224 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5227 /* We now have the group relocation table entry corresponding to
5228 the name in the assembler source. Next, we parse the
5230 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5231 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5233 /* Record the relocation type. */
5237 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5241 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5245 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5252 if (inst.reloc.type == 0)
5254 inst.error = _("this group relocation is not allowed on this instruction");
5255 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5261 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5262 return PARSE_OPERAND_FAIL;
5263 /* If the offset is 0, find out if it's a +0 or -0. */
5264 if (inst.reloc.exp.X_op == O_constant
5265 && inst.reloc.exp.X_add_number == 0)
5267 skip_whitespace (q);
5271 skip_whitespace (q);
5274 inst.operands[i].negative = 1;
5279 else if (skip_past_char (&p, ':') == SUCCESS)
5281 /* FIXME: '@' should be used here, but it's filtered out by generic code
5282 before we get to see it here. This may be subject to change. */
5283 parse_operand_result result = parse_neon_alignment (&p, i);
5285 if (result != PARSE_OPERAND_SUCCESS)
5289 if (skip_past_char (&p, ']') == FAIL)
5291 inst.error = _("']' expected");
5292 return PARSE_OPERAND_FAIL;
5295 if (skip_past_char (&p, '!') == SUCCESS)
5296 inst.operands[i].writeback = 1;
5298 else if (skip_past_comma (&p) == SUCCESS)
5300 if (skip_past_char (&p, '{') == SUCCESS)
5302 /* [Rn], {expr} - unindexed, with option */
5303 if (parse_immediate (&p, &inst.operands[i].imm,
5304 0, 255, TRUE) == FAIL)
5305 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '}') == FAIL)
5309 inst.error = _("'}' expected at end of 'option' field");
5310 return PARSE_OPERAND_FAIL;
5312 if (inst.operands[i].preind)
5314 inst.error = _("cannot combine index with option");
5315 return PARSE_OPERAND_FAIL;
5318 return PARSE_OPERAND_SUCCESS;
5322 inst.operands[i].postind = 1;
5323 inst.operands[i].writeback = 1;
5325 if (inst.operands[i].preind)
5327 inst.error = _("cannot combine pre- and post-indexing");
5328 return PARSE_OPERAND_FAIL;
5332 else if (*p == '-') p++, inst.operands[i].negative = 1;
5334 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5336 /* We might be using the immediate for alignment already. If we
5337 are, OR the register number into the low-order bits. */
5338 if (inst.operands[i].immisalign)
5339 inst.operands[i].imm |= reg;
5341 inst.operands[i].imm = reg;
5342 inst.operands[i].immisreg = 1;
5344 if (skip_past_comma (&p) == SUCCESS)
5345 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5346 return PARSE_OPERAND_FAIL;
5351 if (inst.operands[i].negative)
5353 inst.operands[i].negative = 0;
5356 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5357 return PARSE_OPERAND_FAIL;
5358 /* If the offset is 0, find out if it's a +0 or -0. */
5359 if (inst.reloc.exp.X_op == O_constant
5360 && inst.reloc.exp.X_add_number == 0)
5362 skip_whitespace (q);
5366 skip_whitespace (q);
5369 inst.operands[i].negative = 1;
5375 /* If at this point neither .preind nor .postind is set, we have a
5376 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5377 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5379 inst.operands[i].preind = 1;
5380 inst.reloc.exp.X_op = O_constant;
5381 inst.reloc.exp.X_add_number = 0;
5384 return PARSE_OPERAND_SUCCESS;
5388 parse_address (char **str, int i)
5390 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5394 static parse_operand_result
5395 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5397 return parse_address_main (str, i, 1, type);
5400 /* Parse an operand for a MOVW or MOVT instruction. */
5402 parse_half (char **str)
5407 skip_past_char (&p, '#');
5408 if (strncasecmp (p, ":lower16:", 9) == 0)
5409 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5410 else if (strncasecmp (p, ":upper16:", 9) == 0)
5411 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5413 if (inst.reloc.type != BFD_RELOC_UNUSED)
5416 skip_whitespace (p);
5419 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5422 if (inst.reloc.type == BFD_RELOC_UNUSED)
5424 if (inst.reloc.exp.X_op != O_constant)
5426 inst.error = _("constant expression expected");
5429 if (inst.reloc.exp.X_add_number < 0
5430 || inst.reloc.exp.X_add_number > 0xffff)
5432 inst.error = _("immediate value out of range");
5440 /* Miscellaneous. */
5442 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5443 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5445 parse_psr (char **str, bfd_boolean lhs)
5448 unsigned long psr_field;
5449 const struct asm_psr *psr;
5451 bfd_boolean is_apsr = FALSE;
5452 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5454 /* PR gas/12698: If the user has specified -march=all then m_profile will
5455 be TRUE, but we want to ignore it in this case as we are building for any
5456 CPU type, including non-m variants. */
5457 if (selected_cpu.core == arm_arch_any.core)
5460 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5461 feature for ease of use and backwards compatibility. */
5463 if (strncasecmp (p, "SPSR", 4) == 0)
5466 goto unsupported_psr;
5468 psr_field = SPSR_BIT;
5470 else if (strncasecmp (p, "CPSR", 4) == 0)
5473 goto unsupported_psr;
5477 else if (strncasecmp (p, "APSR", 4) == 0)
5479 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5480 and ARMv7-R architecture CPUs. */
5489 while (ISALNUM (*p) || *p == '_');
5491 if (strncasecmp (start, "iapsr", 5) == 0
5492 || strncasecmp (start, "eapsr", 5) == 0
5493 || strncasecmp (start, "xpsr", 4) == 0
5494 || strncasecmp (start, "psr", 3) == 0)
5495 p = start + strcspn (start, "rR") + 1;
5497 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5503 /* If APSR is being written, a bitfield may be specified. Note that
5504 APSR itself is handled above. */
5505 if (psr->field <= 3)
5507 psr_field = psr->field;
5513 /* M-profile MSR instructions have the mask field set to "10", except
5514 *PSR variants which modify APSR, which may use a different mask (and
5515 have been handled already). Do that by setting the PSR_f field
5517 return psr->field | (lhs ? PSR_f : 0);
5520 goto unsupported_psr;
5526 /* A suffix follows. */
5532 while (ISALNUM (*p) || *p == '_');
5536 /* APSR uses a notation for bits, rather than fields. */
5537 unsigned int nzcvq_bits = 0;
5538 unsigned int g_bit = 0;
5541 for (bit = start; bit != p; bit++)
5543 switch (TOLOWER (*bit))
5546 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5550 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5554 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5558 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5562 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5566 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5570 inst.error = _("unexpected bit specified after APSR");
5575 if (nzcvq_bits == 0x1f)
5580 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5582 inst.error = _("selected processor does not "
5583 "support DSP extension");
5590 if ((nzcvq_bits & 0x20) != 0
5591 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5592 || (g_bit & 0x2) != 0)
5594 inst.error = _("bad bitmask specified after APSR");
5600 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5605 psr_field |= psr->field;
5611 goto error; /* Garbage after "[CS]PSR". */
5613 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5614 is deprecated, but allow it anyway. */
5618 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5621 else if (!m_profile)
5622 /* These bits are never right for M-profile devices: don't set them
5623 (only code paths which read/write APSR reach here). */
5624 psr_field |= (PSR_c | PSR_f);
5630 inst.error = _("selected processor does not support requested special "
5631 "purpose register");
5635 inst.error = _("flag for {c}psr instruction expected");
5639 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5640 value suitable for splatting into the AIF field of the instruction. */
5643 parse_cps_flags (char **str)
5652 case '\0': case ',':
5655 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5656 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5657 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5660 inst.error = _("unrecognized CPS flag");
5665 if (saw_a_flag == 0)
5667 inst.error = _("missing CPS flags");
5675 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5676 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5679 parse_endian_specifier (char **str)
5684 if (strncasecmp (s, "BE", 2))
5686 else if (strncasecmp (s, "LE", 2))
5690 inst.error = _("valid endian specifiers are be or le");
5694 if (ISALNUM (s[2]) || s[2] == '_')
5696 inst.error = _("valid endian specifiers are be or le");
5701 return little_endian;
5704 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5705 value suitable for poking into the rotate field of an sxt or sxta
5706 instruction, or FAIL on error. */
5709 parse_ror (char **str)
5714 if (strncasecmp (s, "ROR", 3) == 0)
5718 inst.error = _("missing rotation field after comma");
5722 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5727 case 0: *str = s; return 0x0;
5728 case 8: *str = s; return 0x1;
5729 case 16: *str = s; return 0x2;
5730 case 24: *str = s; return 0x3;
5733 inst.error = _("rotation can only be 0, 8, 16, or 24");
5738 /* Parse a conditional code (from conds[] below). The value returned is in the
5739 range 0 .. 14, or FAIL. */
5741 parse_cond (char **str)
5744 const struct asm_cond *c;
5746 /* Condition codes are always 2 characters, so matching up to
5747 3 characters is sufficient. */
5752 while (ISALPHA (*q) && n < 3)
5754 cond[n] = TOLOWER (*q);
5759 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5762 inst.error = _("condition required");
5770 /* If the given feature available in the selected CPU, mark it as used.
5771 Returns TRUE iff feature is available. */
5773 mark_feature_used (const arm_feature_set *feature)
5775 /* Ensure the option is valid on the current architecture. */
5776 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5779 /* Add the appropriate architecture feature for the barrier option used.
5782 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5784 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5789 /* Parse an option for a barrier instruction. Returns the encoding for the
5792 parse_barrier (char **str)
5795 const struct asm_barrier_opt *o;
5798 while (ISALPHA (*q))
5801 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5806 if (!mark_feature_used (&o->arch))
5813 /* Parse the operands of a table branch instruction. Similar to a memory
5816 parse_tb (char **str)
5821 if (skip_past_char (&p, '[') == FAIL)
5823 inst.error = _("'[' expected");
5827 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5829 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5832 inst.operands[0].reg = reg;
5834 if (skip_past_comma (&p) == FAIL)
5836 inst.error = _("',' expected");
5840 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5842 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5845 inst.operands[0].imm = reg;
5847 if (skip_past_comma (&p) == SUCCESS)
5849 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5851 if (inst.reloc.exp.X_add_number != 1)
5853 inst.error = _("invalid shift");
5856 inst.operands[0].shifted = 1;
5859 if (skip_past_char (&p, ']') == FAIL)
5861 inst.error = _("']' expected");
5868 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5869 information on the types the operands can take and how they are encoded.
5870 Up to four operands may be read; this function handles setting the
5871 ".present" field for each read operand itself.
5872 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5873 else returns FAIL. */
5876 parse_neon_mov (char **str, int *which_operand)
5878 int i = *which_operand, val;
5879 enum arm_reg_type rtype;
5881 struct neon_type_el optype;
5883 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5885 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5886 inst.operands[i].reg = val;
5887 inst.operands[i].isscalar = 1;
5888 inst.operands[i].vectype = optype;
5889 inst.operands[i++].present = 1;
5891 if (skip_past_comma (&ptr) == FAIL)
5894 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5901 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5904 /* Cases 0, 1, 2, 3, 5 (D only). */
5905 if (skip_past_comma (&ptr) == FAIL)
5908 inst.operands[i].reg = val;
5909 inst.operands[i].isreg = 1;
5910 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5911 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5912 inst.operands[i].isvec = 1;
5913 inst.operands[i].vectype = optype;
5914 inst.operands[i++].present = 1;
5916 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5918 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5919 Case 13: VMOV <Sd>, <Rm> */
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].present = 1;
5924 if (rtype == REG_TYPE_NQ)
5926 first_error (_("can't use Neon quad register here"));
5929 else if (rtype != REG_TYPE_VFS)
5932 if (skip_past_comma (&ptr) == FAIL)
5934 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5936 inst.operands[i].reg = val;
5937 inst.operands[i].isreg = 1;
5938 inst.operands[i].present = 1;
5941 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5944 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5945 Case 1: VMOV<c><q> <Dd>, <Dm>
5946 Case 8: VMOV.F32 <Sd>, <Sm>
5947 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5949 inst.operands[i].reg = val;
5950 inst.operands[i].isreg = 1;
5951 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5952 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5953 inst.operands[i].isvec = 1;
5954 inst.operands[i].vectype = optype;
5955 inst.operands[i].present = 1;
5957 if (skip_past_comma (&ptr) == SUCCESS)
5962 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5965 inst.operands[i].reg = val;
5966 inst.operands[i].isreg = 1;
5967 inst.operands[i++].present = 1;
5969 if (skip_past_comma (&ptr) == FAIL)
5972 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5975 inst.operands[i].reg = val;
5976 inst.operands[i].isreg = 1;
5977 inst.operands[i].present = 1;
5980 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5981 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5982 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5983 Case 10: VMOV.F32 <Sd>, #<imm>
5984 Case 11: VMOV.F64 <Dd>, #<imm> */
5985 inst.operands[i].immisfloat = 1;
5986 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5987 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5988 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5992 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5996 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5999 inst.operands[i].reg = val;
6000 inst.operands[i].isreg = 1;
6001 inst.operands[i++].present = 1;
6003 if (skip_past_comma (&ptr) == FAIL)
6006 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6008 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6009 inst.operands[i].reg = val;
6010 inst.operands[i].isscalar = 1;
6011 inst.operands[i].present = 1;
6012 inst.operands[i].vectype = optype;
6014 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6016 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6017 inst.operands[i].reg = val;
6018 inst.operands[i].isreg = 1;
6019 inst.operands[i++].present = 1;
6021 if (skip_past_comma (&ptr) == FAIL)
6024 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6027 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6031 inst.operands[i].reg = val;
6032 inst.operands[i].isreg = 1;
6033 inst.operands[i].isvec = 1;
6034 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6035 inst.operands[i].vectype = optype;
6036 inst.operands[i].present = 1;
6038 if (rtype == REG_TYPE_VFS)
6042 if (skip_past_comma (&ptr) == FAIL)
6044 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6047 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6050 inst.operands[i].reg = val;
6051 inst.operands[i].isreg = 1;
6052 inst.operands[i].isvec = 1;
6053 inst.operands[i].issingle = 1;
6054 inst.operands[i].vectype = optype;
6055 inst.operands[i].present = 1;
6058 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6072 first_error (_("parse error"));
6076 /* Successfully parsed the operands. Update args. */
6082 first_error (_("expected comma"));
6086 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6090 /* Use this macro when the operand constraints are different
6091 for ARM and THUMB (e.g. ldrd). */
6092 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6093 ((arm_operand) | ((thumb_operand) << 16))
6095 /* Matcher codes for parse_operands. */
6096 enum operand_parse_code
6098 OP_stop, /* end of line */
6100 OP_RR, /* ARM register */
6101 OP_RRnpc, /* ARM register, not r15 */
6102 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6103 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6104 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6105 optional trailing ! */
6106 OP_RRw, /* ARM register, not r15, optional trailing ! */
6107 OP_RCP, /* Coprocessor number */
6108 OP_RCN, /* Coprocessor register */
6109 OP_RF, /* FPA register */
6110 OP_RVS, /* VFP single precision register */
6111 OP_RVD, /* VFP double precision register (0..15) */
6112 OP_RND, /* Neon double precision register (0..31) */
6113 OP_RNQ, /* Neon quad precision register */
6114 OP_RVSD, /* VFP single or double precision register */
6115 OP_RNDQ, /* Neon double or quad precision register */
6116 OP_RNSDQ, /* Neon single, double or quad precision register */
6117 OP_RNSC, /* Neon scalar D[X] */
6118 OP_RVC, /* VFP control register */
6119 OP_RMF, /* Maverick F register */
6120 OP_RMD, /* Maverick D register */
6121 OP_RMFX, /* Maverick FX register */
6122 OP_RMDX, /* Maverick DX register */
6123 OP_RMAX, /* Maverick AX register */
6124 OP_RMDS, /* Maverick DSPSC register */
6125 OP_RIWR, /* iWMMXt wR register */
6126 OP_RIWC, /* iWMMXt wC register */
6127 OP_RIWG, /* iWMMXt wCG register */
6128 OP_RXA, /* XScale accumulator register */
6130 OP_REGLST, /* ARM register list */
6131 OP_VRSLST, /* VFP single-precision register list */
6132 OP_VRDLST, /* VFP double-precision register list */
6133 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6134 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6135 OP_NSTRLST, /* Neon element/structure list */
6137 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6138 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6139 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6140 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6141 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6142 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6143 OP_VMOV, /* Neon VMOV operands. */
6144 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6145 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6146 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6148 OP_I0, /* immediate zero */
6149 OP_I7, /* immediate value 0 .. 7 */
6150 OP_I15, /* 0 .. 15 */
6151 OP_I16, /* 1 .. 16 */
6152 OP_I16z, /* 0 .. 16 */
6153 OP_I31, /* 0 .. 31 */
6154 OP_I31w, /* 0 .. 31, optional trailing ! */
6155 OP_I32, /* 1 .. 32 */
6156 OP_I32z, /* 0 .. 32 */
6157 OP_I63, /* 0 .. 63 */
6158 OP_I63s, /* -64 .. 63 */
6159 OP_I64, /* 1 .. 64 */
6160 OP_I64z, /* 0 .. 64 */
6161 OP_I255, /* 0 .. 255 */
6163 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6164 OP_I7b, /* 0 .. 7 */
6165 OP_I15b, /* 0 .. 15 */
6166 OP_I31b, /* 0 .. 31 */
6168 OP_SH, /* shifter operand */
6169 OP_SHG, /* shifter operand with possible group relocation */
6170 OP_ADDR, /* Memory address expression (any mode) */
6171 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6172 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6173 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6174 OP_EXP, /* arbitrary expression */
6175 OP_EXPi, /* same, with optional immediate prefix */
6176 OP_EXPr, /* same, with optional relocation suffix */
6177 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6179 OP_CPSF, /* CPS flags */
6180 OP_ENDI, /* Endianness specifier */
6181 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6182 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6183 OP_COND, /* conditional code */
6184 OP_TB, /* Table branch. */
6186 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6188 OP_RRnpc_I0, /* ARM register or literal 0 */
6189 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6190 OP_RR_EXi, /* ARM register or expression with imm prefix */
6191 OP_RF_IF, /* FPA register or immediate */
6192 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6193 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6195 /* Optional operands. */
6196 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6197 OP_oI31b, /* 0 .. 31 */
6198 OP_oI32b, /* 1 .. 32 */
6199 OP_oI32z, /* 0 .. 32 */
6200 OP_oIffffb, /* 0 .. 65535 */
6201 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6203 OP_oRR, /* ARM register */
6204 OP_oRRnpc, /* ARM register, not the PC */
6205 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6206 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6207 OP_oRND, /* Optional Neon double precision register */
6208 OP_oRNQ, /* Optional Neon quad precision register */
6209 OP_oRNDQ, /* Optional Neon double or quad precision register */
6210 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6211 OP_oSHll, /* LSL immediate */
6212 OP_oSHar, /* ASR immediate */
6213 OP_oSHllar, /* LSL or ASR immediate */
6214 OP_oROR, /* ROR 0/8/16/24 */
6215 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6217 /* Some pre-defined mixed (ARM/THUMB) operands. */
6218 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6219 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6220 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6222 OP_FIRST_OPTIONAL = OP_oI7b
6225 /* Generic instruction operand parser. This does no encoding and no
6226 semantic validation; it merely squirrels values away in the inst
6227 structure. Returns SUCCESS or FAIL depending on whether the
6228 specified grammar matched. */
6230 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6232 unsigned const int *upat = pattern;
6233 char *backtrack_pos = 0;
6234 const char *backtrack_error = 0;
6235 int i, val = 0, backtrack_index = 0;
6236 enum arm_reg_type rtype;
6237 parse_operand_result result;
6238 unsigned int op_parse_code;
6240 #define po_char_or_fail(chr) \
6243 if (skip_past_char (&str, chr) == FAIL) \
6248 #define po_reg_or_fail(regtype) \
6251 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6252 & inst.operands[i].vectype); \
6255 first_error (_(reg_expected_msgs[regtype])); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isreg = 1; \
6260 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6261 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6262 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6263 || rtype == REG_TYPE_VFD \
6264 || rtype == REG_TYPE_NQ); \
6268 #define po_reg_or_goto(regtype, label) \
6271 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6272 & inst.operands[i].vectype); \
6276 inst.operands[i].reg = val; \
6277 inst.operands[i].isreg = 1; \
6278 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6279 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6280 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6281 || rtype == REG_TYPE_VFD \
6282 || rtype == REG_TYPE_NQ); \
6286 #define po_imm_or_fail(min, max, popt) \
6289 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6291 inst.operands[i].imm = val; \
6295 #define po_scalar_or_goto(elsz, label) \
6298 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6301 inst.operands[i].reg = val; \
6302 inst.operands[i].isscalar = 1; \
6306 #define po_misc_or_fail(expr) \
6314 #define po_misc_or_fail_no_backtrack(expr) \
6318 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6319 backtrack_pos = 0; \
6320 if (result != PARSE_OPERAND_SUCCESS) \
6325 #define po_barrier_or_imm(str) \
6328 val = parse_barrier (&str); \
6331 if (ISALPHA (*str)) \
6338 if ((inst.instruction & 0xf0) == 0x60 \
6341 /* ISB can only take SY as an option. */ \
6342 inst.error = _("invalid barrier type"); \
6349 skip_whitespace (str);
6351 for (i = 0; upat[i] != OP_stop; i++)
6353 op_parse_code = upat[i];
6354 if (op_parse_code >= 1<<16)
6355 op_parse_code = thumb ? (op_parse_code >> 16)
6356 : (op_parse_code & ((1<<16)-1));
6358 if (op_parse_code >= OP_FIRST_OPTIONAL)
6360 /* Remember where we are in case we need to backtrack. */
6361 gas_assert (!backtrack_pos);
6362 backtrack_pos = str;
6363 backtrack_error = inst.error;
6364 backtrack_index = i;
6367 if (i > 0 && (i > 1 || inst.operands[0].present))
6368 po_char_or_fail (',');
6370 switch (op_parse_code)
6378 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6379 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6380 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6381 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6382 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6383 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6385 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6387 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6389 /* Also accept generic coprocessor regs for unknown registers. */
6391 po_reg_or_fail (REG_TYPE_CN);
6393 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6394 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6395 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6396 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6397 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6398 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6399 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6400 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6401 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6402 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6404 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6406 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6407 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6409 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6411 /* Neon scalar. Using an element size of 8 means that some invalid
6412 scalars are accepted here, so deal with those in later code. */
6413 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6417 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6420 po_imm_or_fail (0, 0, TRUE);
6425 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6430 po_scalar_or_goto (8, try_rr);
6433 po_reg_or_fail (REG_TYPE_RN);
6439 po_scalar_or_goto (8, try_nsdq);
6442 po_reg_or_fail (REG_TYPE_NSDQ);
6448 po_scalar_or_goto (8, try_ndq);
6451 po_reg_or_fail (REG_TYPE_NDQ);
6457 po_scalar_or_goto (8, try_vfd);
6460 po_reg_or_fail (REG_TYPE_VFD);
6465 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6466 not careful then bad things might happen. */
6467 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6472 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6475 /* There's a possibility of getting a 64-bit immediate here, so
6476 we need special handling. */
6477 if (parse_big_immediate (&str, i) == FAIL)
6479 inst.error = _("immediate value is out of range");
6487 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6490 po_imm_or_fail (0, 63, TRUE);
6495 po_char_or_fail ('[');
6496 po_reg_or_fail (REG_TYPE_RN);
6497 po_char_or_fail (']');
6503 po_reg_or_fail (REG_TYPE_RN);
6504 if (skip_past_char (&str, '!') == SUCCESS)
6505 inst.operands[i].writeback = 1;
6509 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6510 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6511 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6512 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6513 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6514 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6515 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6516 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6517 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6518 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6519 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6520 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6522 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6524 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6525 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6527 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6528 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6529 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6530 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6532 /* Immediate variants */
6534 po_char_or_fail ('{');
6535 po_imm_or_fail (0, 255, TRUE);
6536 po_char_or_fail ('}');
6540 /* The expression parser chokes on a trailing !, so we have
6541 to find it first and zap it. */
6544 while (*s && *s != ',')
6549 inst.operands[i].writeback = 1;
6551 po_imm_or_fail (0, 31, TRUE);
6559 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6564 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6569 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6571 if (inst.reloc.exp.X_op == O_symbol)
6573 val = parse_reloc (&str);
6576 inst.error = _("unrecognized relocation suffix");
6579 else if (val != BFD_RELOC_UNUSED)
6581 inst.operands[i].imm = val;
6582 inst.operands[i].hasreloc = 1;
6587 /* Operand for MOVW or MOVT. */
6589 po_misc_or_fail (parse_half (&str));
6592 /* Register or expression. */
6593 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6594 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6596 /* Register or immediate. */
6597 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6598 I0: po_imm_or_fail (0, 0, FALSE); break;
6600 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6602 if (!is_immediate_prefix (*str))
6605 val = parse_fpa_immediate (&str);
6608 /* FPA immediates are encoded as registers 8-15.
6609 parse_fpa_immediate has already applied the offset. */
6610 inst.operands[i].reg = val;
6611 inst.operands[i].isreg = 1;
6614 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6615 I32z: po_imm_or_fail (0, 32, FALSE); break;
6617 /* Two kinds of register. */
6620 struct reg_entry *rege = arm_reg_parse_multi (&str);
6622 || (rege->type != REG_TYPE_MMXWR
6623 && rege->type != REG_TYPE_MMXWC
6624 && rege->type != REG_TYPE_MMXWCG))
6626 inst.error = _("iWMMXt data or control register expected");
6629 inst.operands[i].reg = rege->number;
6630 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6636 struct reg_entry *rege = arm_reg_parse_multi (&str);
6638 || (rege->type != REG_TYPE_MMXWC
6639 && rege->type != REG_TYPE_MMXWCG))
6641 inst.error = _("iWMMXt control register expected");
6644 inst.operands[i].reg = rege->number;
6645 inst.operands[i].isreg = 1;
6650 case OP_CPSF: val = parse_cps_flags (&str); break;
6651 case OP_ENDI: val = parse_endian_specifier (&str); break;
6652 case OP_oROR: val = parse_ror (&str); break;
6653 case OP_COND: val = parse_cond (&str); break;
6654 case OP_oBARRIER_I15:
6655 po_barrier_or_imm (str); break;
6657 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6663 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6664 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6666 inst.error = _("Banked registers are not available with this "
6672 val = parse_psr (&str, op_parse_code == OP_wPSR);
6676 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6679 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6681 if (strncasecmp (str, "APSR_", 5) == 0)
6688 case 'c': found = (found & 1) ? 16 : found | 1; break;
6689 case 'n': found = (found & 2) ? 16 : found | 2; break;
6690 case 'z': found = (found & 4) ? 16 : found | 4; break;
6691 case 'v': found = (found & 8) ? 16 : found | 8; break;
6692 default: found = 16;
6696 inst.operands[i].isvec = 1;
6697 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6698 inst.operands[i].reg = REG_PC;
6705 po_misc_or_fail (parse_tb (&str));
6708 /* Register lists. */
6710 val = parse_reg_list (&str);
6713 inst.operands[1].writeback = 1;
6719 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6723 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6727 /* Allow Q registers too. */
6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6733 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6735 inst.operands[i].issingle = 1;
6740 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6745 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6746 &inst.operands[i].vectype);
6749 /* Addressing modes */
6751 po_misc_or_fail (parse_address (&str, i));
6755 po_misc_or_fail_no_backtrack (
6756 parse_address_group_reloc (&str, i, GROUP_LDR));
6760 po_misc_or_fail_no_backtrack (
6761 parse_address_group_reloc (&str, i, GROUP_LDRS));
6765 po_misc_or_fail_no_backtrack (
6766 parse_address_group_reloc (&str, i, GROUP_LDC));
6770 po_misc_or_fail (parse_shifter_operand (&str, i));
6774 po_misc_or_fail_no_backtrack (
6775 parse_shifter_operand_group_reloc (&str, i));
6779 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6783 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6787 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6791 as_fatal (_("unhandled operand code %d"), op_parse_code);
6794 /* Various value-based sanity checks and shared operations. We
6795 do not signal immediate failures for the register constraints;
6796 this allows a syntax error to take precedence. */
6797 switch (op_parse_code)
6805 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6806 inst.error = BAD_PC;
6811 if (inst.operands[i].isreg)
6813 if (inst.operands[i].reg == REG_PC)
6814 inst.error = BAD_PC;
6815 else if (inst.operands[i].reg == REG_SP)
6816 inst.error = BAD_SP;
6821 if (inst.operands[i].isreg
6822 && inst.operands[i].reg == REG_PC
6823 && (inst.operands[i].writeback || thumb))
6824 inst.error = BAD_PC;
6833 case OP_oBARRIER_I15:
6842 inst.operands[i].imm = val;
6849 /* If we get here, this operand was successfully parsed. */
6850 inst.operands[i].present = 1;
6854 inst.error = BAD_ARGS;
6859 /* The parse routine should already have set inst.error, but set a
6860 default here just in case. */
6862 inst.error = _("syntax error");
6866 /* Do not backtrack over a trailing optional argument that
6867 absorbed some text. We will only fail again, with the
6868 'garbage following instruction' error message, which is
6869 probably less helpful than the current one. */
6870 if (backtrack_index == i && backtrack_pos != str
6871 && upat[i+1] == OP_stop)
6874 inst.error = _("syntax error");
6878 /* Try again, skipping the optional argument at backtrack_pos. */
6879 str = backtrack_pos;
6880 inst.error = backtrack_error;
6881 inst.operands[backtrack_index].present = 0;
6882 i = backtrack_index;
6886 /* Check that we have parsed all the arguments. */
6887 if (*str != '\0' && !inst.error)
6888 inst.error = _("garbage following instruction");
6890 return inst.error ? FAIL : SUCCESS;
6893 #undef po_char_or_fail
6894 #undef po_reg_or_fail
6895 #undef po_reg_or_goto
6896 #undef po_imm_or_fail
6897 #undef po_scalar_or_fail
6898 #undef po_barrier_or_imm
6900 /* Shorthand macro for instruction encoding functions issuing errors. */
6901 #define constraint(expr, err) \
6912 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6913 instructions are unpredictable if these registers are used. This
6914 is the BadReg predicate in ARM's Thumb-2 documentation. */
6915 #define reject_bad_reg(reg) \
6917 if (reg == REG_SP || reg == REG_PC) \
6919 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6924 /* If REG is R13 (the stack pointer), warn that its use is
6926 #define warn_deprecated_sp(reg) \
6928 if (warn_on_deprecated && reg == REG_SP) \
6929 as_warn (_("use of r13 is deprecated")); \
6932 /* Functions for operand encoding. ARM, then Thumb. */
6934 #define rotate_left(v, n) (v << n | v >> (32 - n))
6936 /* If VAL can be encoded in the immediate field of an ARM instruction,
6937 return the encoded form. Otherwise, return FAIL. */
6940 encode_arm_immediate (unsigned int val)
6944 for (i = 0; i < 32; i += 2)
6945 if ((a = rotate_left (val, i)) <= 0xff)
6946 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6951 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6952 return the encoded form. Otherwise, return FAIL. */
6954 encode_thumb32_immediate (unsigned int val)
6961 for (i = 1; i <= 24; i++)
6964 if ((val & ~(0xff << i)) == 0)
6965 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6969 if (val == ((a << 16) | a))
6971 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6975 if (val == ((a << 16) | a))
6976 return 0x200 | (a >> 8);
6980 /* Encode a VFP SP or DP register number into inst.instruction. */
6983 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6985 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6988 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6991 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6994 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6999 first_error (_("D register out of range for selected VFP version"));
7007 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7011 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7015 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7019 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7023 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7027 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7035 /* Encode a <shift> in an ARM-format instruction. The immediate,
7036 if any, is handled by md_apply_fix. */
7038 encode_arm_shift (int i)
7040 if (inst.operands[i].shift_kind == SHIFT_RRX)
7041 inst.instruction |= SHIFT_ROR << 5;
7044 inst.instruction |= inst.operands[i].shift_kind << 5;
7045 if (inst.operands[i].immisreg)
7047 inst.instruction |= SHIFT_BY_REG;
7048 inst.instruction |= inst.operands[i].imm << 8;
7051 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7056 encode_arm_shifter_operand (int i)
7058 if (inst.operands[i].isreg)
7060 inst.instruction |= inst.operands[i].reg;
7061 encode_arm_shift (i);
7065 inst.instruction |= INST_IMMEDIATE;
7066 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7067 inst.instruction |= inst.operands[i].imm;
7071 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7073 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7076 Generate an error if the operand is not a register. */
7077 constraint (!inst.operands[i].isreg,
7078 _("Instruction does not support =N addresses"));
7080 inst.instruction |= inst.operands[i].reg << 16;
7082 if (inst.operands[i].preind)
7086 inst.error = _("instruction does not accept preindexed addressing");
7089 inst.instruction |= PRE_INDEX;
7090 if (inst.operands[i].writeback)
7091 inst.instruction |= WRITE_BACK;
7094 else if (inst.operands[i].postind)
7096 gas_assert (inst.operands[i].writeback);
7098 inst.instruction |= WRITE_BACK;
7100 else /* unindexed - only for coprocessor */
7102 inst.error = _("instruction does not accept unindexed addressing");
7106 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7107 && (((inst.instruction & 0x000f0000) >> 16)
7108 == ((inst.instruction & 0x0000f000) >> 12)))
7109 as_warn ((inst.instruction & LOAD_BIT)
7110 ? _("destination register same as write-back base")
7111 : _("source register same as write-back base"));
7114 /* inst.operands[i] was set up by parse_address. Encode it into an
7115 ARM-format mode 2 load or store instruction. If is_t is true,
7116 reject forms that cannot be used with a T instruction (i.e. not
7119 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7121 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7123 encode_arm_addr_mode_common (i, is_t);
7125 if (inst.operands[i].immisreg)
7127 constraint ((inst.operands[i].imm == REG_PC
7128 || (is_pc && inst.operands[i].writeback)),
7130 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7131 inst.instruction |= inst.operands[i].imm;
7132 if (!inst.operands[i].negative)
7133 inst.instruction |= INDEX_UP;
7134 if (inst.operands[i].shifted)
7136 if (inst.operands[i].shift_kind == SHIFT_RRX)
7137 inst.instruction |= SHIFT_ROR << 5;
7140 inst.instruction |= inst.operands[i].shift_kind << 5;
7141 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7145 else /* immediate offset in inst.reloc */
7147 if (is_pc && !inst.reloc.pc_rel)
7149 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7151 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7152 cannot use PC in addressing.
7153 PC cannot be used in writeback addressing, either. */
7154 constraint ((is_t || inst.operands[i].writeback),
7157 /* Use of PC in str is deprecated for ARMv7. */
7158 if (warn_on_deprecated
7160 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7161 as_warn (_("use of PC in this instruction is deprecated"));
7164 if (inst.reloc.type == BFD_RELOC_UNUSED)
7166 /* Prefer + for zero encoded value. */
7167 if (!inst.operands[i].negative)
7168 inst.instruction |= INDEX_UP;
7169 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7174 /* inst.operands[i] was set up by parse_address. Encode it into an
7175 ARM-format mode 3 load or store instruction. Reject forms that
7176 cannot be used with such instructions. If is_t is true, reject
7177 forms that cannot be used with a T instruction (i.e. not
7180 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7182 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7184 inst.error = _("instruction does not accept scaled register index");
7188 encode_arm_addr_mode_common (i, is_t);
7190 if (inst.operands[i].immisreg)
7192 constraint ((inst.operands[i].imm == REG_PC
7193 || inst.operands[i].reg == REG_PC),
7195 inst.instruction |= inst.operands[i].imm;
7196 if (!inst.operands[i].negative)
7197 inst.instruction |= INDEX_UP;
7199 else /* immediate offset in inst.reloc */
7201 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7202 && inst.operands[i].writeback),
7204 inst.instruction |= HWOFFSET_IMM;
7205 if (inst.reloc.type == BFD_RELOC_UNUSED)
7207 /* Prefer + for zero encoded value. */
7208 if (!inst.operands[i].negative)
7209 inst.instruction |= INDEX_UP;
7211 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7216 /* inst.operands[i] was set up by parse_address. Encode it into an
7217 ARM-format instruction. Reject all forms which cannot be encoded
7218 into a coprocessor load/store instruction. If wb_ok is false,
7219 reject use of writeback; if unind_ok is false, reject use of
7220 unindexed addressing. If reloc_override is not 0, use it instead
7221 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7222 (in which case it is preserved). */
7225 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7227 inst.instruction |= inst.operands[i].reg << 16;
7229 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7231 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7233 gas_assert (!inst.operands[i].writeback);
7236 inst.error = _("instruction does not support unindexed addressing");
7239 inst.instruction |= inst.operands[i].imm;
7240 inst.instruction |= INDEX_UP;
7244 if (inst.operands[i].preind)
7245 inst.instruction |= PRE_INDEX;
7247 if (inst.operands[i].writeback)
7249 if (inst.operands[i].reg == REG_PC)
7251 inst.error = _("pc may not be used with write-back");
7256 inst.error = _("instruction does not support writeback");
7259 inst.instruction |= WRITE_BACK;
7263 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7264 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7265 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7266 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7269 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7271 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7274 /* Prefer + for zero encoded value. */
7275 if (!inst.operands[i].negative)
7276 inst.instruction |= INDEX_UP;
7281 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7282 Determine whether it can be performed with a move instruction; if
7283 it can, convert inst.instruction to that move instruction and
7284 return TRUE; if it can't, convert inst.instruction to a literal-pool
7285 load and return FALSE. If this is not a valid thing to do in the
7286 current context, set inst.error and return TRUE.
7288 inst.operands[i] describes the destination register. */
7291 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7296 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7300 if ((inst.instruction & tbit) == 0)
7302 inst.error = _("invalid pseudo operation");
7305 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7307 inst.error = _("constant expression expected");
7310 if (inst.reloc.exp.X_op == O_constant)
7314 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7316 /* This can be done with a mov(1) instruction. */
7317 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7318 inst.instruction |= inst.reloc.exp.X_add_number;
7324 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7327 /* This can be done with a mov instruction. */
7328 inst.instruction &= LITERAL_MASK;
7329 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7330 inst.instruction |= value & 0xfff;
7334 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7337 /* This can be done with a mvn instruction. */
7338 inst.instruction &= LITERAL_MASK;
7339 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7340 inst.instruction |= value & 0xfff;
7346 if (add_to_lit_pool () == FAIL)
7348 inst.error = _("literal pool insertion failed");
7351 inst.operands[1].reg = REG_PC;
7352 inst.operands[1].isreg = 1;
7353 inst.operands[1].preind = 1;
7354 inst.reloc.pc_rel = 1;
7355 inst.reloc.type = (thumb_p
7356 ? BFD_RELOC_ARM_THUMB_OFFSET
7358 ? BFD_RELOC_ARM_HWLITERAL
7359 : BFD_RELOC_ARM_LITERAL));
7363 /* Functions for instruction encoding, sorted by sub-architecture.
7364 First some generics; their names are taken from the conventional
7365 bit positions for register arguments in ARM format instructions. */
7375 inst.instruction |= inst.operands[0].reg << 12;
7381 inst.instruction |= inst.operands[0].reg << 12;
7382 inst.instruction |= inst.operands[1].reg;
7388 inst.instruction |= inst.operands[0].reg;
7389 inst.instruction |= inst.operands[1].reg << 16;
7395 inst.instruction |= inst.operands[0].reg << 12;
7396 inst.instruction |= inst.operands[1].reg << 16;
7402 inst.instruction |= inst.operands[0].reg << 16;
7403 inst.instruction |= inst.operands[1].reg << 12;
7407 check_obsolete (const arm_feature_set *feature, const char *msg)
7409 if (ARM_CPU_IS_ANY (cpu_variant))
7411 as_warn ("%s", msg);
7414 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7426 unsigned Rn = inst.operands[2].reg;
7427 /* Enforce restrictions on SWP instruction. */
7428 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7430 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7431 _("Rn must not overlap other operands"));
7433 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7435 if (!check_obsolete (&arm_ext_v8,
7436 _("swp{b} use is obsoleted for ARMv8 and later"))
7437 && warn_on_deprecated
7438 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7439 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7442 inst.instruction |= inst.operands[0].reg << 12;
7443 inst.instruction |= inst.operands[1].reg;
7444 inst.instruction |= Rn << 16;
7450 inst.instruction |= inst.operands[0].reg << 12;
7451 inst.instruction |= inst.operands[1].reg << 16;
7452 inst.instruction |= inst.operands[2].reg;
7458 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7459 constraint (((inst.reloc.exp.X_op != O_constant
7460 && inst.reloc.exp.X_op != O_illegal)
7461 || inst.reloc.exp.X_add_number != 0),
7463 inst.instruction |= inst.operands[0].reg;
7464 inst.instruction |= inst.operands[1].reg << 12;
7465 inst.instruction |= inst.operands[2].reg << 16;
7471 inst.instruction |= inst.operands[0].imm;
7477 inst.instruction |= inst.operands[0].reg << 12;
7478 encode_arm_cp_address (1, TRUE, TRUE, 0);
7481 /* ARM instructions, in alphabetical order by function name (except
7482 that wrapper functions appear immediately after the function they
7485 /* This is a pseudo-op of the form "adr rd, label" to be converted
7486 into a relative address of the form "add rd, pc, #label-.-8". */
7491 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7493 /* Frag hacking will turn this into a sub instruction if the offset turns
7494 out to be negative. */
7495 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7496 inst.reloc.pc_rel = 1;
7497 inst.reloc.exp.X_add_number -= 8;
7500 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7501 into a relative address of the form:
7502 add rd, pc, #low(label-.-8)"
7503 add rd, rd, #high(label-.-8)" */
7508 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7510 /* Frag hacking will turn this into a sub instruction if the offset turns
7511 out to be negative. */
7512 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7513 inst.reloc.pc_rel = 1;
7514 inst.size = INSN_SIZE * 2;
7515 inst.reloc.exp.X_add_number -= 8;
7521 if (!inst.operands[1].present)
7522 inst.operands[1].reg = inst.operands[0].reg;
7523 inst.instruction |= inst.operands[0].reg << 12;
7524 inst.instruction |= inst.operands[1].reg << 16;
7525 encode_arm_shifter_operand (2);
7531 if (inst.operands[0].present)
7533 constraint ((inst.instruction & 0xf0) != 0x40
7534 && inst.operands[0].imm > 0xf
7535 && inst.operands[0].imm < 0x0,
7536 _("bad barrier type"));
7537 inst.instruction |= inst.operands[0].imm;
7540 inst.instruction |= 0xf;
7546 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7547 constraint (msb > 32, _("bit-field extends past end of register"));
7548 /* The instruction encoding stores the LSB and MSB,
7549 not the LSB and width. */
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].imm << 7;
7552 inst.instruction |= (msb - 1) << 16;
7560 /* #0 in second position is alternative syntax for bfc, which is
7561 the same instruction but with REG_PC in the Rm field. */
7562 if (!inst.operands[1].isreg)
7563 inst.operands[1].reg = REG_PC;
7565 msb = inst.operands[2].imm + inst.operands[3].imm;
7566 constraint (msb > 32, _("bit-field extends past end of register"));
7567 /* The instruction encoding stores the LSB and MSB,
7568 not the LSB and width. */
7569 inst.instruction |= inst.operands[0].reg << 12;
7570 inst.instruction |= inst.operands[1].reg;
7571 inst.instruction |= inst.operands[2].imm << 7;
7572 inst.instruction |= (msb - 1) << 16;
7578 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7579 _("bit-field extends past end of register"));
7580 inst.instruction |= inst.operands[0].reg << 12;
7581 inst.instruction |= inst.operands[1].reg;
7582 inst.instruction |= inst.operands[2].imm << 7;
7583 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7586 /* ARM V5 breakpoint instruction (argument parse)
7587 BKPT <16 bit unsigned immediate>
7588 Instruction is not conditional.
7589 The bit pattern given in insns[] has the COND_ALWAYS condition,
7590 and it is an error if the caller tried to override that. */
7595 /* Top 12 of 16 bits to bits 19:8. */
7596 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7598 /* Bottom 4 of 16 bits to bits 3:0. */
7599 inst.instruction |= inst.operands[0].imm & 0xf;
7603 encode_branch (int default_reloc)
7605 if (inst.operands[0].hasreloc)
7607 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7608 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7609 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7610 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7611 ? BFD_RELOC_ARM_PLT32
7612 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7615 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7616 inst.reloc.pc_rel = 1;
7623 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7624 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7627 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7634 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 if (inst.cond == COND_ALWAYS)
7637 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7639 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7643 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 /* ARM V5 branch-link-exchange instruction (argument parse)
7647 BLX <target_addr> ie BLX(1)
7648 BLX{<condition>} <Rm> ie BLX(2)
7649 Unfortunately, there are two different opcodes for this mnemonic.
7650 So, the insns[].value is not used, and the code here zaps values
7651 into inst.instruction.
7652 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7657 if (inst.operands[0].isreg)
7659 /* Arg is a register; the opcode provided by insns[] is correct.
7660 It is not illegal to do "blx pc", just useless. */
7661 if (inst.operands[0].reg == REG_PC)
7662 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7664 inst.instruction |= inst.operands[0].reg;
7668 /* Arg is an address; this instruction cannot be executed
7669 conditionally, and the opcode must be adjusted.
7670 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7671 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7672 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7673 inst.instruction = 0xfa000000;
7674 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7681 bfd_boolean want_reloc;
7683 if (inst.operands[0].reg == REG_PC)
7684 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7686 inst.instruction |= inst.operands[0].reg;
7687 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7688 it is for ARMv4t or earlier. */
7689 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7690 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7694 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7699 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7703 /* ARM v5TEJ. Jump to Jazelle code. */
7708 if (inst.operands[0].reg == REG_PC)
7709 as_tsktsk (_("use of r15 in bxj is not really useful"));
7711 inst.instruction |= inst.operands[0].reg;
7714 /* Co-processor data operation:
7715 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7716 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7720 inst.instruction |= inst.operands[0].reg << 8;
7721 inst.instruction |= inst.operands[1].imm << 20;
7722 inst.instruction |= inst.operands[2].reg << 12;
7723 inst.instruction |= inst.operands[3].reg << 16;
7724 inst.instruction |= inst.operands[4].reg;
7725 inst.instruction |= inst.operands[5].imm << 5;
7731 inst.instruction |= inst.operands[0].reg << 16;
7732 encode_arm_shifter_operand (1);
7735 /* Transfer between coprocessor and ARM registers.
7736 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7741 No special properties. */
7743 struct deprecated_coproc_regs_s
7750 arm_feature_set deprecated;
7751 arm_feature_set obsoleted;
7752 const char *dep_msg;
7753 const char *obs_msg;
7756 #define DEPR_ACCESS_V8 \
7757 N_("This coprocessor register access is deprecated in ARMv8")
7759 /* Table of all deprecated coprocessor registers. */
7760 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7762 {15, 0, 7, 10, 5, /* CP15DMB. */
7763 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7764 DEPR_ACCESS_V8, NULL},
7765 {15, 0, 7, 10, 4, /* CP15DSB. */
7766 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7767 DEPR_ACCESS_V8, NULL},
7768 {15, 0, 7, 5, 4, /* CP15ISB. */
7769 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7770 DEPR_ACCESS_V8, NULL},
7771 {14, 6, 1, 0, 0, /* TEEHBR. */
7772 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7773 DEPR_ACCESS_V8, NULL},
7774 {14, 6, 0, 0, 0, /* TEECR. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7779 #undef DEPR_ACCESS_V8
7781 static const size_t deprecated_coproc_reg_count =
7782 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7790 Rd = inst.operands[2].reg;
7793 if (inst.instruction == 0xee000010
7794 || inst.instruction == 0xfe000010)
7796 reject_bad_reg (Rd);
7799 constraint (Rd == REG_SP, BAD_SP);
7804 if (inst.instruction == 0xe000010)
7805 constraint (Rd == REG_PC, BAD_PC);
7808 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7810 const struct deprecated_coproc_regs_s *r =
7811 deprecated_coproc_regs + i;
7813 if (inst.operands[0].reg == r->cp
7814 && inst.operands[1].imm == r->opc1
7815 && inst.operands[3].reg == r->crn
7816 && inst.operands[4].reg == r->crm
7817 && inst.operands[5].imm == r->opc2)
7819 if (!check_obsolete (&r->obsoleted, r->obs_msg)
7820 && warn_on_deprecated
7821 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7822 as_warn ("%s", r->dep_msg);
7826 inst.instruction |= inst.operands[0].reg << 8;
7827 inst.instruction |= inst.operands[1].imm << 21;
7828 inst.instruction |= Rd << 12;
7829 inst.instruction |= inst.operands[3].reg << 16;
7830 inst.instruction |= inst.operands[4].reg;
7831 inst.instruction |= inst.operands[5].imm << 5;
7834 /* Transfer between coprocessor register and pair of ARM registers.
7835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7840 Two XScale instructions are special cases of these:
7842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7845 Result unpredictable if Rd or Rn is R15. */
7852 Rd = inst.operands[2].reg;
7853 Rn = inst.operands[3].reg;
7857 reject_bad_reg (Rd);
7858 reject_bad_reg (Rn);
7862 constraint (Rd == REG_PC, BAD_PC);
7863 constraint (Rn == REG_PC, BAD_PC);
7866 inst.instruction |= inst.operands[0].reg << 8;
7867 inst.instruction |= inst.operands[1].imm << 4;
7868 inst.instruction |= Rd << 12;
7869 inst.instruction |= Rn << 16;
7870 inst.instruction |= inst.operands[4].reg;
7876 inst.instruction |= inst.operands[0].imm << 6;
7877 if (inst.operands[1].present)
7879 inst.instruction |= CPSI_MMOD;
7880 inst.instruction |= inst.operands[1].imm;
7887 inst.instruction |= inst.operands[0].imm;
7893 unsigned Rd, Rn, Rm;
7895 Rd = inst.operands[0].reg;
7896 Rn = (inst.operands[1].present
7897 ? inst.operands[1].reg : Rd);
7898 Rm = inst.operands[2].reg;
7900 constraint ((Rd == REG_PC), BAD_PC);
7901 constraint ((Rn == REG_PC), BAD_PC);
7902 constraint ((Rm == REG_PC), BAD_PC);
7904 inst.instruction |= Rd << 16;
7905 inst.instruction |= Rn << 0;
7906 inst.instruction |= Rm << 8;
7912 /* There is no IT instruction in ARM mode. We
7913 process it to do the validation as if in
7914 thumb mode, just in case the code gets
7915 assembled for thumb using the unified syntax. */
7920 set_it_insn_type (IT_INSN);
7921 now_it.mask = (inst.instruction & 0xf) | 0x10;
7922 now_it.cc = inst.operands[0].imm;
7926 /* If there is only one register in the register list,
7927 then return its register number. Otherwise return -1. */
7929 only_one_reg_in_list (int range)
7931 int i = ffs (range) - 1;
7932 return (i > 15 || range != (1 << i)) ? -1 : i;
7936 encode_ldmstm(int from_push_pop_mnem)
7938 int base_reg = inst.operands[0].reg;
7939 int range = inst.operands[1].imm;
7942 inst.instruction |= base_reg << 16;
7943 inst.instruction |= range;
7945 if (inst.operands[1].writeback)
7946 inst.instruction |= LDM_TYPE_2_OR_3;
7948 if (inst.operands[0].writeback)
7950 inst.instruction |= WRITE_BACK;
7951 /* Check for unpredictable uses of writeback. */
7952 if (inst.instruction & LOAD_BIT)
7954 /* Not allowed in LDM type 2. */
7955 if ((inst.instruction & LDM_TYPE_2_OR_3)
7956 && ((range & (1 << REG_PC)) == 0))
7957 as_warn (_("writeback of base register is UNPREDICTABLE"));
7958 /* Only allowed if base reg not in list for other types. */
7959 else if (range & (1 << base_reg))
7960 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7964 /* Not allowed for type 2. */
7965 if (inst.instruction & LDM_TYPE_2_OR_3)
7966 as_warn (_("writeback of base register is UNPREDICTABLE"));
7967 /* Only allowed if base reg not in list, or first in list. */
7968 else if ((range & (1 << base_reg))
7969 && (range & ((1 << base_reg) - 1)))
7970 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7974 /* If PUSH/POP has only one register, then use the A2 encoding. */
7975 one_reg = only_one_reg_in_list (range);
7976 if (from_push_pop_mnem && one_reg >= 0)
7978 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7980 inst.instruction &= A_COND_MASK;
7981 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7982 inst.instruction |= one_reg << 12;
7989 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7992 /* ARMv5TE load-consecutive (argument parse)
8001 constraint (inst.operands[0].reg % 2 != 0,
8002 _("first transfer register must be even"));
8003 constraint (inst.operands[1].present
8004 && inst.operands[1].reg != inst.operands[0].reg + 1,
8005 _("can only transfer two consecutive registers"));
8006 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8007 constraint (!inst.operands[2].isreg, _("'[' expected"));
8009 if (!inst.operands[1].present)
8010 inst.operands[1].reg = inst.operands[0].reg + 1;
8012 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8013 register and the first register written; we have to diagnose
8014 overlap between the base and the second register written here. */
8016 if (inst.operands[2].reg == inst.operands[1].reg
8017 && (inst.operands[2].writeback || inst.operands[2].postind))
8018 as_warn (_("base register written back, and overlaps "
8019 "second transfer register"));
8021 if (!(inst.instruction & V4_STR_BIT))
8023 /* For an index-register load, the index register must not overlap the
8024 destination (even if not write-back). */
8025 if (inst.operands[2].immisreg
8026 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8027 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8028 as_warn (_("index register overlaps transfer register"));
8030 inst.instruction |= inst.operands[0].reg << 12;
8031 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8037 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8038 || inst.operands[1].postind || inst.operands[1].writeback
8039 || inst.operands[1].immisreg || inst.operands[1].shifted
8040 || inst.operands[1].negative
8041 /* This can arise if the programmer has written
8043 or if they have mistakenly used a register name as the last
8046 It is very difficult to distinguish between these two cases
8047 because "rX" might actually be a label. ie the register
8048 name has been occluded by a symbol of the same name. So we
8049 just generate a general 'bad addressing mode' type error
8050 message and leave it up to the programmer to discover the
8051 true cause and fix their mistake. */
8052 || (inst.operands[1].reg == REG_PC),
8055 constraint (inst.reloc.exp.X_op != O_constant
8056 || inst.reloc.exp.X_add_number != 0,
8057 _("offset must be zero in ARM encoding"));
8059 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8061 inst.instruction |= inst.operands[0].reg << 12;
8062 inst.instruction |= inst.operands[1].reg << 16;
8063 inst.reloc.type = BFD_RELOC_UNUSED;
8069 constraint (inst.operands[0].reg % 2 != 0,
8070 _("even register required"));
8071 constraint (inst.operands[1].present
8072 && inst.operands[1].reg != inst.operands[0].reg + 1,
8073 _("can only load two consecutive registers"));
8074 /* If op 1 were present and equal to PC, this function wouldn't
8075 have been called in the first place. */
8076 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8078 inst.instruction |= inst.operands[0].reg << 12;
8079 inst.instruction |= inst.operands[2].reg << 16;
8082 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8083 which is not a multiple of four is UNPREDICTABLE. */
8085 check_ldr_r15_aligned (void)
8087 constraint (!(inst.operands[1].immisreg)
8088 && (inst.operands[0].reg == REG_PC
8089 && inst.operands[1].reg == REG_PC
8090 && (inst.reloc.exp.X_add_number & 0x3)),
8091 _("ldr to register 15 must be 4-byte alligned"));
8097 inst.instruction |= inst.operands[0].reg << 12;
8098 if (!inst.operands[1].isreg)
8099 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8101 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8102 check_ldr_r15_aligned ();
8108 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8110 if (inst.operands[1].preind)
8112 constraint (inst.reloc.exp.X_op != O_constant
8113 || inst.reloc.exp.X_add_number != 0,
8114 _("this instruction requires a post-indexed address"));
8116 inst.operands[1].preind = 0;
8117 inst.operands[1].postind = 1;
8118 inst.operands[1].writeback = 1;
8120 inst.instruction |= inst.operands[0].reg << 12;
8121 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8124 /* Halfword and signed-byte load/store operations. */
8129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8130 inst.instruction |= inst.operands[0].reg << 12;
8131 if (!inst.operands[1].isreg)
8132 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8134 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8140 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8142 if (inst.operands[1].preind)
8144 constraint (inst.reloc.exp.X_op != O_constant
8145 || inst.reloc.exp.X_add_number != 0,
8146 _("this instruction requires a post-indexed address"));
8148 inst.operands[1].preind = 0;
8149 inst.operands[1].postind = 1;
8150 inst.operands[1].writeback = 1;
8152 inst.instruction |= inst.operands[0].reg << 12;
8153 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8156 /* Co-processor register load/store.
8157 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8161 inst.instruction |= inst.operands[0].reg << 8;
8162 inst.instruction |= inst.operands[1].reg << 12;
8163 encode_arm_cp_address (2, TRUE, TRUE, 0);
8169 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8170 if (inst.operands[0].reg == inst.operands[1].reg
8171 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8172 && !(inst.instruction & 0x00400000))
8173 as_tsktsk (_("Rd and Rm should be different in mla"));
8175 inst.instruction |= inst.operands[0].reg << 16;
8176 inst.instruction |= inst.operands[1].reg;
8177 inst.instruction |= inst.operands[2].reg << 8;
8178 inst.instruction |= inst.operands[3].reg << 12;
8184 inst.instruction |= inst.operands[0].reg << 12;
8185 encode_arm_shifter_operand (1);
8188 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8195 top = (inst.instruction & 0x00400000) != 0;
8196 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8197 _(":lower16: not allowed this instruction"));
8198 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8199 _(":upper16: not allowed instruction"));
8200 inst.instruction |= inst.operands[0].reg << 12;
8201 if (inst.reloc.type == BFD_RELOC_UNUSED)
8203 imm = inst.reloc.exp.X_add_number;
8204 /* The value is in two pieces: 0:11, 16:19. */
8205 inst.instruction |= (imm & 0x00000fff);
8206 inst.instruction |= (imm & 0x0000f000) << 4;
8210 static void do_vfp_nsyn_opcode (const char *);
8213 do_vfp_nsyn_mrs (void)
8215 if (inst.operands[0].isvec)
8217 if (inst.operands[1].reg != 1)
8218 first_error (_("operand 1 must be FPSCR"));
8219 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8220 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8221 do_vfp_nsyn_opcode ("fmstat");
8223 else if (inst.operands[1].isvec)
8224 do_vfp_nsyn_opcode ("fmrx");
8232 do_vfp_nsyn_msr (void)
8234 if (inst.operands[0].isvec)
8235 do_vfp_nsyn_opcode ("fmxr");
8245 unsigned Rt = inst.operands[0].reg;
8247 if (thumb_mode && inst.operands[0].reg == REG_SP)
8249 inst.error = BAD_SP;
8253 /* APSR_ sets isvec. All other refs to PC are illegal. */
8254 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8256 inst.error = BAD_PC;
8260 switch (inst.operands[1].reg)
8267 inst.instruction |= (inst.operands[1].reg << 16);
8270 first_error (_("operand 1 must be a VFP extension System Register"));
8273 inst.instruction |= (Rt << 12);
8279 unsigned Rt = inst.operands[1].reg;
8282 reject_bad_reg (Rt);
8283 else if (Rt == REG_PC)
8285 inst.error = BAD_PC;
8289 switch (inst.operands[0].reg)
8294 inst.instruction |= (inst.operands[0].reg << 16);
8297 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8300 inst.instruction |= (Rt << 12);
8308 if (do_vfp_nsyn_mrs () == SUCCESS)
8311 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8312 inst.instruction |= inst.operands[0].reg << 12;
8314 if (inst.operands[1].isreg)
8316 br = inst.operands[1].reg;
8317 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8318 as_bad (_("bad register for mrs"));
8322 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8323 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8325 _("'APSR', 'CPSR' or 'SPSR' expected"));
8326 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8329 inst.instruction |= br;
8332 /* Two possible forms:
8333 "{C|S}PSR_<field>, Rm",
8334 "{C|S}PSR_f, #expression". */
8339 if (do_vfp_nsyn_msr () == SUCCESS)
8342 inst.instruction |= inst.operands[0].imm;
8343 if (inst.operands[1].isreg)
8344 inst.instruction |= inst.operands[1].reg;
8347 inst.instruction |= INST_IMMEDIATE;
8348 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8349 inst.reloc.pc_rel = 0;
8356 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8358 if (!inst.operands[2].present)
8359 inst.operands[2].reg = inst.operands[0].reg;
8360 inst.instruction |= inst.operands[0].reg << 16;
8361 inst.instruction |= inst.operands[1].reg;
8362 inst.instruction |= inst.operands[2].reg << 8;
8364 if (inst.operands[0].reg == inst.operands[1].reg
8365 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8366 as_tsktsk (_("Rd and Rm should be different in mul"));
8369 /* Long Multiply Parser
8370 UMULL RdLo, RdHi, Rm, Rs
8371 SMULL RdLo, RdHi, Rm, Rs
8372 UMLAL RdLo, RdHi, Rm, Rs
8373 SMLAL RdLo, RdHi, Rm, Rs. */
8378 inst.instruction |= inst.operands[0].reg << 12;
8379 inst.instruction |= inst.operands[1].reg << 16;
8380 inst.instruction |= inst.operands[2].reg;
8381 inst.instruction |= inst.operands[3].reg << 8;
8383 /* rdhi and rdlo must be different. */
8384 if (inst.operands[0].reg == inst.operands[1].reg)
8385 as_tsktsk (_("rdhi and rdlo must be different"));
8387 /* rdhi, rdlo and rm must all be different before armv6. */
8388 if ((inst.operands[0].reg == inst.operands[2].reg
8389 || inst.operands[1].reg == inst.operands[2].reg)
8390 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8391 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8397 if (inst.operands[0].present
8398 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8400 /* Architectural NOP hints are CPSR sets with no bits selected. */
8401 inst.instruction &= 0xf0000000;
8402 inst.instruction |= 0x0320f000;
8403 if (inst.operands[0].present)
8404 inst.instruction |= inst.operands[0].imm;
8408 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8409 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8410 Condition defaults to COND_ALWAYS.
8411 Error if Rd, Rn or Rm are R15. */
8416 inst.instruction |= inst.operands[0].reg << 12;
8417 inst.instruction |= inst.operands[1].reg << 16;
8418 inst.instruction |= inst.operands[2].reg;
8419 if (inst.operands[3].present)
8420 encode_arm_shift (3);
8423 /* ARM V6 PKHTB (Argument Parse). */
8428 if (!inst.operands[3].present)
8430 /* If the shift specifier is omitted, turn the instruction
8431 into pkhbt rd, rm, rn. */
8432 inst.instruction &= 0xfff00010;
8433 inst.instruction |= inst.operands[0].reg << 12;
8434 inst.instruction |= inst.operands[1].reg;
8435 inst.instruction |= inst.operands[2].reg << 16;
8439 inst.instruction |= inst.operands[0].reg << 12;
8440 inst.instruction |= inst.operands[1].reg << 16;
8441 inst.instruction |= inst.operands[2].reg;
8442 encode_arm_shift (3);
8446 /* ARMv5TE: Preload-Cache
8447 MP Extensions: Preload for write
8451 Syntactically, like LDR with B=1, W=0, L=1. */
8456 constraint (!inst.operands[0].isreg,
8457 _("'[' expected after PLD mnemonic"));
8458 constraint (inst.operands[0].postind,
8459 _("post-indexed expression used in preload instruction"));
8460 constraint (inst.operands[0].writeback,
8461 _("writeback used in preload instruction"));
8462 constraint (!inst.operands[0].preind,
8463 _("unindexed addressing used in preload instruction"));
8464 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 /* ARMv7: PLI <addr_mode> */
8471 constraint (!inst.operands[0].isreg,
8472 _("'[' expected after PLI mnemonic"));
8473 constraint (inst.operands[0].postind,
8474 _("post-indexed expression used in preload instruction"));
8475 constraint (inst.operands[0].writeback,
8476 _("writeback used in preload instruction"));
8477 constraint (!inst.operands[0].preind,
8478 _("unindexed addressing used in preload instruction"));
8479 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8480 inst.instruction &= ~PRE_INDEX;
8486 inst.operands[1] = inst.operands[0];
8487 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8488 inst.operands[0].isreg = 1;
8489 inst.operands[0].writeback = 1;
8490 inst.operands[0].reg = REG_SP;
8491 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8494 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8495 word at the specified address and the following word
8497 Unconditionally executed.
8498 Error if Rn is R15. */
8503 inst.instruction |= inst.operands[0].reg << 16;
8504 if (inst.operands[0].writeback)
8505 inst.instruction |= WRITE_BACK;
8508 /* ARM V6 ssat (argument parse). */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8515 inst.instruction |= inst.operands[2].reg;
8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
8521 /* ARM V6 usat (argument parse). */
8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= inst.operands[1].imm << 16;
8528 inst.instruction |= inst.operands[2].reg;
8530 if (inst.operands[3].present)
8531 encode_arm_shift (3);
8534 /* ARM V6 ssat16 (argument parse). */
8539 inst.instruction |= inst.operands[0].reg << 12;
8540 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8541 inst.instruction |= inst.operands[2].reg;
8547 inst.instruction |= inst.operands[0].reg << 12;
8548 inst.instruction |= inst.operands[1].imm << 16;
8549 inst.instruction |= inst.operands[2].reg;
8552 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8553 preserving the other bits.
8555 setend <endian_specifier>, where <endian_specifier> is either
8561 if (warn_on_deprecated
8562 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8563 as_warn (_("setend use is deprecated for ARMv8"));
8565 if (inst.operands[0].imm)
8566 inst.instruction |= 0x200;
8572 unsigned int Rm = (inst.operands[1].present
8573 ? inst.operands[1].reg
8574 : inst.operands[0].reg);
8576 inst.instruction |= inst.operands[0].reg << 12;
8577 inst.instruction |= Rm;
8578 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8580 inst.instruction |= inst.operands[2].reg << 8;
8581 inst.instruction |= SHIFT_BY_REG;
8582 /* PR 12854: Error on extraneous shifts. */
8583 constraint (inst.operands[2].shifted,
8584 _("extraneous shift as part of operand to shift insn"));
8587 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8593 inst.reloc.type = BFD_RELOC_ARM_SMC;
8594 inst.reloc.pc_rel = 0;
8600 inst.reloc.type = BFD_RELOC_ARM_HVC;
8601 inst.reloc.pc_rel = 0;
8607 inst.reloc.type = BFD_RELOC_ARM_SWI;
8608 inst.reloc.pc_rel = 0;
8611 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8612 SMLAxy{cond} Rd,Rm,Rs,Rn
8613 SMLAWy{cond} Rd,Rm,Rs,Rn
8614 Error if any register is R15. */
8619 inst.instruction |= inst.operands[0].reg << 16;
8620 inst.instruction |= inst.operands[1].reg;
8621 inst.instruction |= inst.operands[2].reg << 8;
8622 inst.instruction |= inst.operands[3].reg << 12;
8625 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8626 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8627 Error if any register is R15.
8628 Warning if Rdlo == Rdhi. */
8633 inst.instruction |= inst.operands[0].reg << 12;
8634 inst.instruction |= inst.operands[1].reg << 16;
8635 inst.instruction |= inst.operands[2].reg;
8636 inst.instruction |= inst.operands[3].reg << 8;
8638 if (inst.operands[0].reg == inst.operands[1].reg)
8639 as_tsktsk (_("rdhi and rdlo must be different"));
8642 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8643 SMULxy{cond} Rd,Rm,Rs
8644 Error if any register is R15. */
8649 inst.instruction |= inst.operands[0].reg << 16;
8650 inst.instruction |= inst.operands[1].reg;
8651 inst.instruction |= inst.operands[2].reg << 8;
8654 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8655 the same for both ARM and Thumb-2. */
8662 if (inst.operands[0].present)
8664 reg = inst.operands[0].reg;
8665 constraint (reg != REG_SP, _("SRS base register must be r13"));
8670 inst.instruction |= reg << 16;
8671 inst.instruction |= inst.operands[1].imm;
8672 if (inst.operands[0].writeback || inst.operands[1].writeback)
8673 inst.instruction |= WRITE_BACK;
8676 /* ARM V6 strex (argument parse). */
8681 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8682 || inst.operands[2].postind || inst.operands[2].writeback
8683 || inst.operands[2].immisreg || inst.operands[2].shifted
8684 || inst.operands[2].negative
8685 /* See comment in do_ldrex(). */
8686 || (inst.operands[2].reg == REG_PC),
8689 constraint (inst.operands[0].reg == inst.operands[1].reg
8690 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8692 constraint (inst.reloc.exp.X_op != O_constant
8693 || inst.reloc.exp.X_add_number != 0,
8694 _("offset must be zero in ARM encoding"));
8696 inst.instruction |= inst.operands[0].reg << 12;
8697 inst.instruction |= inst.operands[1].reg;
8698 inst.instruction |= inst.operands[2].reg << 16;
8699 inst.reloc.type = BFD_RELOC_UNUSED;
8705 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8706 || inst.operands[2].postind || inst.operands[2].writeback
8707 || inst.operands[2].immisreg || inst.operands[2].shifted
8708 || inst.operands[2].negative,
8711 constraint (inst.operands[0].reg == inst.operands[1].reg
8712 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8720 constraint (inst.operands[1].reg % 2 != 0,
8721 _("even register required"));
8722 constraint (inst.operands[2].present
8723 && inst.operands[2].reg != inst.operands[1].reg + 1,
8724 _("can only store two consecutive registers"));
8725 /* If op 2 were present and equal to PC, this function wouldn't
8726 have been called in the first place. */
8727 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8729 constraint (inst.operands[0].reg == inst.operands[1].reg
8730 || inst.operands[0].reg == inst.operands[1].reg + 1
8731 || inst.operands[0].reg == inst.operands[3].reg,
8734 inst.instruction |= inst.operands[0].reg << 12;
8735 inst.instruction |= inst.operands[1].reg;
8736 inst.instruction |= inst.operands[3].reg << 16;
8743 constraint (inst.operands[0].reg == inst.operands[1].reg
8744 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8752 constraint (inst.operands[0].reg == inst.operands[1].reg
8753 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8758 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8759 extends it to 32-bits, and adds the result to a value in another
8760 register. You can specify a rotation by 0, 8, 16, or 24 bits
8761 before extracting the 16-bit value.
8762 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8763 Condition defaults to COND_ALWAYS.
8764 Error if any register uses R15. */
8769 inst.instruction |= inst.operands[0].reg << 12;
8770 inst.instruction |= inst.operands[1].reg << 16;
8771 inst.instruction |= inst.operands[2].reg;
8772 inst.instruction |= inst.operands[3].imm << 10;
8777 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8778 Condition defaults to COND_ALWAYS.
8779 Error if any register uses R15. */
8784 inst.instruction |= inst.operands[0].reg << 12;
8785 inst.instruction |= inst.operands[1].reg;
8786 inst.instruction |= inst.operands[2].imm << 10;
8789 /* VFP instructions. In a logical order: SP variant first, monad
8790 before dyad, arithmetic then move then load/store. */
8793 do_vfp_sp_monadic (void)
8795 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8796 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8800 do_vfp_sp_dyadic (void)
8802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8803 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8804 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8808 do_vfp_sp_compare_z (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8814 do_vfp_dp_sp_cvt (void)
8816 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8817 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8821 do_vfp_sp_dp_cvt (void)
8823 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8824 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8828 do_vfp_reg_from_sp (void)
8830 inst.instruction |= inst.operands[0].reg << 12;
8831 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8835 do_vfp_reg2_from_sp2 (void)
8837 constraint (inst.operands[2].imm != 2,
8838 _("only two consecutive VFP SP registers allowed here"));
8839 inst.instruction |= inst.operands[0].reg << 12;
8840 inst.instruction |= inst.operands[1].reg << 16;
8841 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8845 do_vfp_sp_from_reg (void)
8847 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8848 inst.instruction |= inst.operands[1].reg << 12;
8852 do_vfp_sp2_from_reg2 (void)
8854 constraint (inst.operands[0].imm != 2,
8855 _("only two consecutive VFP SP registers allowed here"));
8856 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8857 inst.instruction |= inst.operands[1].reg << 12;
8858 inst.instruction |= inst.operands[2].reg << 16;
8862 do_vfp_sp_ldst (void)
8864 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8865 encode_arm_cp_address (1, FALSE, TRUE, 0);
8869 do_vfp_dp_ldst (void)
8871 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8872 encode_arm_cp_address (1, FALSE, TRUE, 0);
8877 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8879 if (inst.operands[0].writeback)
8880 inst.instruction |= WRITE_BACK;
8882 constraint (ldstm_type != VFP_LDSTMIA,
8883 _("this addressing mode requires base-register writeback"));
8884 inst.instruction |= inst.operands[0].reg << 16;
8885 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8886 inst.instruction |= inst.operands[1].imm;
8890 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8894 if (inst.operands[0].writeback)
8895 inst.instruction |= WRITE_BACK;
8897 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8898 _("this addressing mode requires base-register writeback"));
8900 inst.instruction |= inst.operands[0].reg << 16;
8901 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8903 count = inst.operands[1].imm << 1;
8904 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8907 inst.instruction |= count;
8911 do_vfp_sp_ldstmia (void)
8913 vfp_sp_ldstm (VFP_LDSTMIA);
8917 do_vfp_sp_ldstmdb (void)
8919 vfp_sp_ldstm (VFP_LDSTMDB);
8923 do_vfp_dp_ldstmia (void)
8925 vfp_dp_ldstm (VFP_LDSTMIA);
8929 do_vfp_dp_ldstmdb (void)
8931 vfp_dp_ldstm (VFP_LDSTMDB);
8935 do_vfp_xp_ldstmia (void)
8937 vfp_dp_ldstm (VFP_LDSTMIAX);
8941 do_vfp_xp_ldstmdb (void)
8943 vfp_dp_ldstm (VFP_LDSTMDBX);
8947 do_vfp_dp_rd_rm (void)
8949 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8950 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8954 do_vfp_dp_rn_rd (void)
8956 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8957 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8961 do_vfp_dp_rd_rn (void)
8963 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8964 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8968 do_vfp_dp_rd_rn_rm (void)
8970 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8971 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8972 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8978 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8982 do_vfp_dp_rm_rd_rn (void)
8984 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8985 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8986 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8989 /* VFPv3 instructions. */
8991 do_vfp_sp_const (void)
8993 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8994 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8995 inst.instruction |= (inst.operands[1].imm & 0x0f);
8999 do_vfp_dp_const (void)
9001 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9002 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9003 inst.instruction |= (inst.operands[1].imm & 0x0f);
9007 vfp_conv (int srcsize)
9009 int immbits = srcsize - inst.operands[1].imm;
9011 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9013 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9014 i.e. immbits must be in range 0 - 16. */
9015 inst.error = _("immediate value out of range, expected range [0, 16]");
9018 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9020 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9021 i.e. immbits must be in range 0 - 31. */
9022 inst.error = _("immediate value out of range, expected range [1, 32]");
9026 inst.instruction |= (immbits & 1) << 5;
9027 inst.instruction |= (immbits >> 1);
9031 do_vfp_sp_conv_16 (void)
9033 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9038 do_vfp_dp_conv_16 (void)
9040 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9045 do_vfp_sp_conv_32 (void)
9047 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9052 do_vfp_dp_conv_32 (void)
9054 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9058 /* FPA instructions. Also in a logical order. */
9063 inst.instruction |= inst.operands[0].reg << 16;
9064 inst.instruction |= inst.operands[1].reg;
9068 do_fpa_ldmstm (void)
9070 inst.instruction |= inst.operands[0].reg << 12;
9071 switch (inst.operands[1].imm)
9073 case 1: inst.instruction |= CP_T_X; break;
9074 case 2: inst.instruction |= CP_T_Y; break;
9075 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9080 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9082 /* The instruction specified "ea" or "fd", so we can only accept
9083 [Rn]{!}. The instruction does not really support stacking or
9084 unstacking, so we have to emulate these by setting appropriate
9085 bits and offsets. */
9086 constraint (inst.reloc.exp.X_op != O_constant
9087 || inst.reloc.exp.X_add_number != 0,
9088 _("this instruction does not support indexing"));
9090 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9091 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9093 if (!(inst.instruction & INDEX_UP))
9094 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9096 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9098 inst.operands[2].preind = 0;
9099 inst.operands[2].postind = 1;
9103 encode_arm_cp_address (2, TRUE, TRUE, 0);
9106 /* iWMMXt instructions: strictly in alphabetical order. */
9109 do_iwmmxt_tandorc (void)
9111 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9115 do_iwmmxt_textrc (void)
9117 inst.instruction |= inst.operands[0].reg << 12;
9118 inst.instruction |= inst.operands[1].imm;
9122 do_iwmmxt_textrm (void)
9124 inst.instruction |= inst.operands[0].reg << 12;
9125 inst.instruction |= inst.operands[1].reg << 16;
9126 inst.instruction |= inst.operands[2].imm;
9130 do_iwmmxt_tinsr (void)
9132 inst.instruction |= inst.operands[0].reg << 16;
9133 inst.instruction |= inst.operands[1].reg << 12;
9134 inst.instruction |= inst.operands[2].imm;
9138 do_iwmmxt_tmia (void)
9140 inst.instruction |= inst.operands[0].reg << 5;
9141 inst.instruction |= inst.operands[1].reg;
9142 inst.instruction |= inst.operands[2].reg << 12;
9146 do_iwmmxt_waligni (void)
9148 inst.instruction |= inst.operands[0].reg << 12;
9149 inst.instruction |= inst.operands[1].reg << 16;
9150 inst.instruction |= inst.operands[2].reg;
9151 inst.instruction |= inst.operands[3].imm << 20;
9155 do_iwmmxt_wmerge (void)
9157 inst.instruction |= inst.operands[0].reg << 12;
9158 inst.instruction |= inst.operands[1].reg << 16;
9159 inst.instruction |= inst.operands[2].reg;
9160 inst.instruction |= inst.operands[3].imm << 21;
9164 do_iwmmxt_wmov (void)
9166 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9167 inst.instruction |= inst.operands[0].reg << 12;
9168 inst.instruction |= inst.operands[1].reg << 16;
9169 inst.instruction |= inst.operands[1].reg;
9173 do_iwmmxt_wldstbh (void)
9176 inst.instruction |= inst.operands[0].reg << 12;
9178 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9180 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9181 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9185 do_iwmmxt_wldstw (void)
9187 /* RIWR_RIWC clears .isreg for a control register. */
9188 if (!inst.operands[0].isreg)
9190 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9191 inst.instruction |= 0xf0000000;
9194 inst.instruction |= inst.operands[0].reg << 12;
9195 encode_arm_cp_address (1, TRUE, TRUE, 0);
9199 do_iwmmxt_wldstd (void)
9201 inst.instruction |= inst.operands[0].reg << 12;
9202 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9203 && inst.operands[1].immisreg)
9205 inst.instruction &= ~0x1a000ff;
9206 inst.instruction |= (0xf << 28);
9207 if (inst.operands[1].preind)
9208 inst.instruction |= PRE_INDEX;
9209 if (!inst.operands[1].negative)
9210 inst.instruction |= INDEX_UP;
9211 if (inst.operands[1].writeback)
9212 inst.instruction |= WRITE_BACK;
9213 inst.instruction |= inst.operands[1].reg << 16;
9214 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9215 inst.instruction |= inst.operands[1].imm;
9218 encode_arm_cp_address (1, TRUE, FALSE, 0);
9222 do_iwmmxt_wshufh (void)
9224 inst.instruction |= inst.operands[0].reg << 12;
9225 inst.instruction |= inst.operands[1].reg << 16;
9226 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9227 inst.instruction |= (inst.operands[2].imm & 0x0f);
9231 do_iwmmxt_wzero (void)
9233 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9234 inst.instruction |= inst.operands[0].reg;
9235 inst.instruction |= inst.operands[0].reg << 12;
9236 inst.instruction |= inst.operands[0].reg << 16;
9240 do_iwmmxt_wrwrwr_or_imm5 (void)
9242 if (inst.operands[2].isreg)
9245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9246 _("immediate operand requires iWMMXt2"));
9248 if (inst.operands[2].imm == 0)
9250 switch ((inst.instruction >> 20) & 0xf)
9256 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9257 inst.operands[2].imm = 16;
9258 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9264 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9265 inst.operands[2].imm = 32;
9266 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9273 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9275 wrn = (inst.instruction >> 16) & 0xf;
9276 inst.instruction &= 0xff0fff0f;
9277 inst.instruction |= wrn;
9278 /* Bail out here; the instruction is now assembled. */
9283 /* Map 32 -> 0, etc. */
9284 inst.operands[2].imm &= 0x1f;
9285 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9289 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9290 operations first, then control, shift, and load/store. */
9292 /* Insns like "foo X,Y,Z". */
9295 do_mav_triple (void)
9297 inst.instruction |= inst.operands[0].reg << 16;
9298 inst.instruction |= inst.operands[1].reg;
9299 inst.instruction |= inst.operands[2].reg << 12;
9302 /* Insns like "foo W,X,Y,Z".
9303 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9308 inst.instruction |= inst.operands[0].reg << 5;
9309 inst.instruction |= inst.operands[1].reg << 12;
9310 inst.instruction |= inst.operands[2].reg << 16;
9311 inst.instruction |= inst.operands[3].reg;
9314 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9318 inst.instruction |= inst.operands[1].reg << 12;
9321 /* Maverick shift immediate instructions.
9322 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9323 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9328 int imm = inst.operands[2].imm;
9330 inst.instruction |= inst.operands[0].reg << 12;
9331 inst.instruction |= inst.operands[1].reg << 16;
9333 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9334 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9335 Bit 4 should be 0. */
9336 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9338 inst.instruction |= imm;
9341 /* XScale instructions. Also sorted arithmetic before move. */
9343 /* Xscale multiply-accumulate (argument parse)
9346 MIAxycc acc0,Rm,Rs. */
9351 inst.instruction |= inst.operands[1].reg;
9352 inst.instruction |= inst.operands[2].reg << 12;
9355 /* Xscale move-accumulator-register (argument parse)
9357 MARcc acc0,RdLo,RdHi. */
9362 inst.instruction |= inst.operands[1].reg << 12;
9363 inst.instruction |= inst.operands[2].reg << 16;
9366 /* Xscale move-register-accumulator (argument parse)
9368 MRAcc RdLo,RdHi,acc0. */
9373 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9374 inst.instruction |= inst.operands[0].reg << 12;
9375 inst.instruction |= inst.operands[1].reg << 16;
9378 /* Encoding functions relevant only to Thumb. */
9380 /* inst.operands[i] is a shifted-register operand; encode
9381 it into inst.instruction in the format used by Thumb32. */
9384 encode_thumb32_shifted_operand (int i)
9386 unsigned int value = inst.reloc.exp.X_add_number;
9387 unsigned int shift = inst.operands[i].shift_kind;
9389 constraint (inst.operands[i].immisreg,
9390 _("shift by register not allowed in thumb mode"));
9391 inst.instruction |= inst.operands[i].reg;
9392 if (shift == SHIFT_RRX)
9393 inst.instruction |= SHIFT_ROR << 4;
9396 constraint (inst.reloc.exp.X_op != O_constant,
9397 _("expression too complex"));
9399 constraint (value > 32
9400 || (value == 32 && (shift == SHIFT_LSL
9401 || shift == SHIFT_ROR)),
9402 _("shift expression is too large"));
9406 else if (value == 32)
9409 inst.instruction |= shift << 4;
9410 inst.instruction |= (value & 0x1c) << 10;
9411 inst.instruction |= (value & 0x03) << 6;
9416 /* inst.operands[i] was set up by parse_address. Encode it into a
9417 Thumb32 format load or store instruction. Reject forms that cannot
9418 be used with such instructions. If is_t is true, reject forms that
9419 cannot be used with a T instruction; if is_d is true, reject forms
9420 that cannot be used with a D instruction. If it is a store insn,
9424 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9426 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9428 constraint (!inst.operands[i].isreg,
9429 _("Instruction does not support =N addresses"));
9431 inst.instruction |= inst.operands[i].reg << 16;
9432 if (inst.operands[i].immisreg)
9434 constraint (is_pc, BAD_PC_ADDRESSING);
9435 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9436 constraint (inst.operands[i].negative,
9437 _("Thumb does not support negative register indexing"));
9438 constraint (inst.operands[i].postind,
9439 _("Thumb does not support register post-indexing"));
9440 constraint (inst.operands[i].writeback,
9441 _("Thumb does not support register indexing with writeback"));
9442 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9443 _("Thumb supports only LSL in shifted register indexing"));
9445 inst.instruction |= inst.operands[i].imm;
9446 if (inst.operands[i].shifted)
9448 constraint (inst.reloc.exp.X_op != O_constant,
9449 _("expression too complex"));
9450 constraint (inst.reloc.exp.X_add_number < 0
9451 || inst.reloc.exp.X_add_number > 3,
9452 _("shift out of range"));
9453 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9455 inst.reloc.type = BFD_RELOC_UNUSED;
9457 else if (inst.operands[i].preind)
9459 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9460 constraint (is_t && inst.operands[i].writeback,
9461 _("cannot use writeback with this instruction"));
9462 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9463 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9467 inst.instruction |= 0x01000000;
9468 if (inst.operands[i].writeback)
9469 inst.instruction |= 0x00200000;
9473 inst.instruction |= 0x00000c00;
9474 if (inst.operands[i].writeback)
9475 inst.instruction |= 0x00000100;
9477 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9479 else if (inst.operands[i].postind)
9481 gas_assert (inst.operands[i].writeback);
9482 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9483 constraint (is_t, _("cannot use post-indexing with this instruction"));
9486 inst.instruction |= 0x00200000;
9488 inst.instruction |= 0x00000900;
9489 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9491 else /* unindexed - only for coprocessor */
9492 inst.error = _("instruction does not accept unindexed addressing");
9495 /* Table of Thumb instructions which exist in both 16- and 32-bit
9496 encodings (the latter only in post-V6T2 cores). The index is the
9497 value used in the insns table below. When there is more than one
9498 possible 16-bit encoding for the instruction, this table always
9500 Also contains several pseudo-instructions used during relaxation. */
9501 #define T16_32_TAB \
9502 X(_adc, 4140, eb400000), \
9503 X(_adcs, 4140, eb500000), \
9504 X(_add, 1c00, eb000000), \
9505 X(_adds, 1c00, eb100000), \
9506 X(_addi, 0000, f1000000), \
9507 X(_addis, 0000, f1100000), \
9508 X(_add_pc,000f, f20f0000), \
9509 X(_add_sp,000d, f10d0000), \
9510 X(_adr, 000f, f20f0000), \
9511 X(_and, 4000, ea000000), \
9512 X(_ands, 4000, ea100000), \
9513 X(_asr, 1000, fa40f000), \
9514 X(_asrs, 1000, fa50f000), \
9515 X(_b, e000, f000b000), \
9516 X(_bcond, d000, f0008000), \
9517 X(_bic, 4380, ea200000), \
9518 X(_bics, 4380, ea300000), \
9519 X(_cmn, 42c0, eb100f00), \
9520 X(_cmp, 2800, ebb00f00), \
9521 X(_cpsie, b660, f3af8400), \
9522 X(_cpsid, b670, f3af8600), \
9523 X(_cpy, 4600, ea4f0000), \
9524 X(_dec_sp,80dd, f1ad0d00), \
9525 X(_eor, 4040, ea800000), \
9526 X(_eors, 4040, ea900000), \
9527 X(_inc_sp,00dd, f10d0d00), \
9528 X(_ldmia, c800, e8900000), \
9529 X(_ldr, 6800, f8500000), \
9530 X(_ldrb, 7800, f8100000), \
9531 X(_ldrh, 8800, f8300000), \
9532 X(_ldrsb, 5600, f9100000), \
9533 X(_ldrsh, 5e00, f9300000), \
9534 X(_ldr_pc,4800, f85f0000), \
9535 X(_ldr_pc2,4800, f85f0000), \
9536 X(_ldr_sp,9800, f85d0000), \
9537 X(_lsl, 0000, fa00f000), \
9538 X(_lsls, 0000, fa10f000), \
9539 X(_lsr, 0800, fa20f000), \
9540 X(_lsrs, 0800, fa30f000), \
9541 X(_mov, 2000, ea4f0000), \
9542 X(_movs, 2000, ea5f0000), \
9543 X(_mul, 4340, fb00f000), \
9544 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9545 X(_mvn, 43c0, ea6f0000), \
9546 X(_mvns, 43c0, ea7f0000), \
9547 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9548 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9549 X(_orr, 4300, ea400000), \
9550 X(_orrs, 4300, ea500000), \
9551 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9552 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9553 X(_rev, ba00, fa90f080), \
9554 X(_rev16, ba40, fa90f090), \
9555 X(_revsh, bac0, fa90f0b0), \
9556 X(_ror, 41c0, fa60f000), \
9557 X(_rors, 41c0, fa70f000), \
9558 X(_sbc, 4180, eb600000), \
9559 X(_sbcs, 4180, eb700000), \
9560 X(_stmia, c000, e8800000), \
9561 X(_str, 6000, f8400000), \
9562 X(_strb, 7000, f8000000), \
9563 X(_strh, 8000, f8200000), \
9564 X(_str_sp,9000, f84d0000), \
9565 X(_sub, 1e00, eba00000), \
9566 X(_subs, 1e00, ebb00000), \
9567 X(_subi, 8000, f1a00000), \
9568 X(_subis, 8000, f1b00000), \
9569 X(_sxtb, b240, fa4ff080), \
9570 X(_sxth, b200, fa0ff080), \
9571 X(_tst, 4200, ea100f00), \
9572 X(_uxtb, b2c0, fa5ff080), \
9573 X(_uxth, b280, fa1ff080), \
9574 X(_nop, bf00, f3af8000), \
9575 X(_yield, bf10, f3af8001), \
9576 X(_wfe, bf20, f3af8002), \
9577 X(_wfi, bf30, f3af8003), \
9578 X(_sev, bf40, f3af8004), \
9579 X(_sevl, bf50, f3af8005)
9581 /* To catch errors in encoding functions, the codes are all offset by
9582 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9583 as 16-bit instructions. */
9584 #define X(a,b,c) T_MNEM##a
9585 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9588 #define X(a,b,c) 0x##b
9589 static const unsigned short thumb_op16[] = { T16_32_TAB };
9590 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9593 #define X(a,b,c) 0x##c
9594 static const unsigned int thumb_op32[] = { T16_32_TAB };
9595 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9596 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9600 /* Thumb instruction encoders, in alphabetical order. */
9605 do_t_add_sub_w (void)
9609 Rd = inst.operands[0].reg;
9610 Rn = inst.operands[1].reg;
9612 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9613 is the SP-{plus,minus}-immediate form of the instruction. */
9615 constraint (Rd == REG_PC, BAD_PC);
9617 reject_bad_reg (Rd);
9619 inst.instruction |= (Rn << 16) | (Rd << 8);
9620 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9623 /* Parse an add or subtract instruction. We get here with inst.instruction
9624 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9631 Rd = inst.operands[0].reg;
9632 Rs = (inst.operands[1].present
9633 ? inst.operands[1].reg /* Rd, Rs, foo */
9634 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9637 set_it_insn_type_last ();
9645 flags = (inst.instruction == T_MNEM_adds
9646 || inst.instruction == T_MNEM_subs);
9648 narrow = !in_it_block ();
9650 narrow = in_it_block ();
9651 if (!inst.operands[2].isreg)
9655 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9657 add = (inst.instruction == T_MNEM_add
9658 || inst.instruction == T_MNEM_adds);
9660 if (inst.size_req != 4)
9662 /* Attempt to use a narrow opcode, with relaxation if
9664 if (Rd == REG_SP && Rs == REG_SP && !flags)
9665 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9666 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9667 opcode = T_MNEM_add_sp;
9668 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9669 opcode = T_MNEM_add_pc;
9670 else if (Rd <= 7 && Rs <= 7 && narrow)
9673 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9675 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9679 inst.instruction = THUMB_OP16(opcode);
9680 inst.instruction |= (Rd << 4) | Rs;
9681 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9682 if (inst.size_req != 2)
9683 inst.relax = opcode;
9686 constraint (inst.size_req == 2, BAD_HIREG);
9688 if (inst.size_req == 4
9689 || (inst.size_req != 2 && !opcode))
9693 constraint (add, BAD_PC);
9694 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9695 _("only SUBS PC, LR, #const allowed"));
9696 constraint (inst.reloc.exp.X_op != O_constant,
9697 _("expression too complex"));
9698 constraint (inst.reloc.exp.X_add_number < 0
9699 || inst.reloc.exp.X_add_number > 0xff,
9700 _("immediate value out of range"));
9701 inst.instruction = T2_SUBS_PC_LR
9702 | inst.reloc.exp.X_add_number;
9703 inst.reloc.type = BFD_RELOC_UNUSED;
9706 else if (Rs == REG_PC)
9708 /* Always use addw/subw. */
9709 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9710 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9714 inst.instruction = THUMB_OP32 (inst.instruction);
9715 inst.instruction = (inst.instruction & 0xe1ffffff)
9718 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9720 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9722 inst.instruction |= Rd << 8;
9723 inst.instruction |= Rs << 16;
9728 unsigned int value = inst.reloc.exp.X_add_number;
9729 unsigned int shift = inst.operands[2].shift_kind;
9731 Rn = inst.operands[2].reg;
9732 /* See if we can do this with a 16-bit instruction. */
9733 if (!inst.operands[2].shifted && inst.size_req != 4)
9735 if (Rd > 7 || Rs > 7 || Rn > 7)
9740 inst.instruction = ((inst.instruction == T_MNEM_adds
9741 || inst.instruction == T_MNEM_add)
9744 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9748 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9750 /* Thumb-1 cores (except v6-M) require at least one high
9751 register in a narrow non flag setting add. */
9752 if (Rd > 7 || Rn > 7
9753 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9754 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9761 inst.instruction = T_OPCODE_ADD_HI;
9762 inst.instruction |= (Rd & 8) << 4;
9763 inst.instruction |= (Rd & 7);
9764 inst.instruction |= Rn << 3;
9770 constraint (Rd == REG_PC, BAD_PC);
9771 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9772 constraint (Rs == REG_PC, BAD_PC);
9773 reject_bad_reg (Rn);
9775 /* If we get here, it can't be done in 16 bits. */
9776 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9777 _("shift must be constant"));
9778 inst.instruction = THUMB_OP32 (inst.instruction);
9779 inst.instruction |= Rd << 8;
9780 inst.instruction |= Rs << 16;
9781 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9782 _("shift value over 3 not allowed in thumb mode"));
9783 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9784 _("only LSL shift allowed in thumb mode"));
9785 encode_thumb32_shifted_operand (2);
9790 constraint (inst.instruction == T_MNEM_adds
9791 || inst.instruction == T_MNEM_subs,
9794 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9796 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9797 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9800 inst.instruction = (inst.instruction == T_MNEM_add
9802 inst.instruction |= (Rd << 4) | Rs;
9803 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9807 Rn = inst.operands[2].reg;
9808 constraint (inst.operands[2].shifted, _("unshifted register required"));
9810 /* We now have Rd, Rs, and Rn set to registers. */
9811 if (Rd > 7 || Rs > 7 || Rn > 7)
9813 /* Can't do this for SUB. */
9814 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9815 inst.instruction = T_OPCODE_ADD_HI;
9816 inst.instruction |= (Rd & 8) << 4;
9817 inst.instruction |= (Rd & 7);
9819 inst.instruction |= Rn << 3;
9821 inst.instruction |= Rs << 3;
9823 constraint (1, _("dest must overlap one source register"));
9827 inst.instruction = (inst.instruction == T_MNEM_add
9828 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9829 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9839 Rd = inst.operands[0].reg;
9840 reject_bad_reg (Rd);
9842 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9844 /* Defer to section relaxation. */
9845 inst.relax = inst.instruction;
9846 inst.instruction = THUMB_OP16 (inst.instruction);
9847 inst.instruction |= Rd << 4;
9849 else if (unified_syntax && inst.size_req != 2)
9851 /* Generate a 32-bit opcode. */
9852 inst.instruction = THUMB_OP32 (inst.instruction);
9853 inst.instruction |= Rd << 8;
9854 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9855 inst.reloc.pc_rel = 1;
9859 /* Generate a 16-bit opcode. */
9860 inst.instruction = THUMB_OP16 (inst.instruction);
9861 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9862 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9863 inst.reloc.pc_rel = 1;
9865 inst.instruction |= Rd << 4;
9869 /* Arithmetic instructions for which there is just one 16-bit
9870 instruction encoding, and it allows only two low registers.
9871 For maximal compatibility with ARM syntax, we allow three register
9872 operands even when Thumb-32 instructions are not available, as long
9873 as the first two are identical. For instance, both "sbc r0,r1" and
9874 "sbc r0,r0,r1" are allowed. */
9880 Rd = inst.operands[0].reg;
9881 Rs = (inst.operands[1].present
9882 ? inst.operands[1].reg /* Rd, Rs, foo */
9883 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9884 Rn = inst.operands[2].reg;
9886 reject_bad_reg (Rd);
9887 reject_bad_reg (Rs);
9888 if (inst.operands[2].isreg)
9889 reject_bad_reg (Rn);
9893 if (!inst.operands[2].isreg)
9895 /* For an immediate, we always generate a 32-bit opcode;
9896 section relaxation will shrink it later if possible. */
9897 inst.instruction = THUMB_OP32 (inst.instruction);
9898 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9899 inst.instruction |= Rd << 8;
9900 inst.instruction |= Rs << 16;
9901 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9907 /* See if we can do this with a 16-bit instruction. */
9908 if (THUMB_SETS_FLAGS (inst.instruction))
9909 narrow = !in_it_block ();
9911 narrow = in_it_block ();
9913 if (Rd > 7 || Rn > 7 || Rs > 7)
9915 if (inst.operands[2].shifted)
9917 if (inst.size_req == 4)
9923 inst.instruction = THUMB_OP16 (inst.instruction);
9924 inst.instruction |= Rd;
9925 inst.instruction |= Rn << 3;
9929 /* If we get here, it can't be done in 16 bits. */
9930 constraint (inst.operands[2].shifted
9931 && inst.operands[2].immisreg,
9932 _("shift must be constant"));
9933 inst.instruction = THUMB_OP32 (inst.instruction);
9934 inst.instruction |= Rd << 8;
9935 inst.instruction |= Rs << 16;
9936 encode_thumb32_shifted_operand (2);
9941 /* On its face this is a lie - the instruction does set the
9942 flags. However, the only supported mnemonic in this mode
9944 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9946 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9947 _("unshifted register required"));
9948 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9949 constraint (Rd != Rs,
9950 _("dest and source1 must be the same register"));
9952 inst.instruction = THUMB_OP16 (inst.instruction);
9953 inst.instruction |= Rd;
9954 inst.instruction |= Rn << 3;
9958 /* Similarly, but for instructions where the arithmetic operation is
9959 commutative, so we can allow either of them to be different from
9960 the destination operand in a 16-bit instruction. For instance, all
9961 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9968 Rd = inst.operands[0].reg;
9969 Rs = (inst.operands[1].present
9970 ? inst.operands[1].reg /* Rd, Rs, foo */
9971 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9972 Rn = inst.operands[2].reg;
9974 reject_bad_reg (Rd);
9975 reject_bad_reg (Rs);
9976 if (inst.operands[2].isreg)
9977 reject_bad_reg (Rn);
9981 if (!inst.operands[2].isreg)
9983 /* For an immediate, we always generate a 32-bit opcode;
9984 section relaxation will shrink it later if possible. */
9985 inst.instruction = THUMB_OP32 (inst.instruction);
9986 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9987 inst.instruction |= Rd << 8;
9988 inst.instruction |= Rs << 16;
9989 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9995 /* See if we can do this with a 16-bit instruction. */
9996 if (THUMB_SETS_FLAGS (inst.instruction))
9997 narrow = !in_it_block ();
9999 narrow = in_it_block ();
10001 if (Rd > 7 || Rn > 7 || Rs > 7)
10003 if (inst.operands[2].shifted)
10005 if (inst.size_req == 4)
10012 inst.instruction = THUMB_OP16 (inst.instruction);
10013 inst.instruction |= Rd;
10014 inst.instruction |= Rn << 3;
10019 inst.instruction = THUMB_OP16 (inst.instruction);
10020 inst.instruction |= Rd;
10021 inst.instruction |= Rs << 3;
10026 /* If we get here, it can't be done in 16 bits. */
10027 constraint (inst.operands[2].shifted
10028 && inst.operands[2].immisreg,
10029 _("shift must be constant"));
10030 inst.instruction = THUMB_OP32 (inst.instruction);
10031 inst.instruction |= Rd << 8;
10032 inst.instruction |= Rs << 16;
10033 encode_thumb32_shifted_operand (2);
10038 /* On its face this is a lie - the instruction does set the
10039 flags. However, the only supported mnemonic in this mode
10040 says it doesn't. */
10041 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10043 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10044 _("unshifted register required"));
10045 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10047 inst.instruction = THUMB_OP16 (inst.instruction);
10048 inst.instruction |= Rd;
10051 inst.instruction |= Rn << 3;
10053 inst.instruction |= Rs << 3;
10055 constraint (1, _("dest must overlap one source register"));
10060 do_t_barrier (void)
10062 if (inst.operands[0].present)
10064 constraint ((inst.instruction & 0xf0) != 0x40
10065 && inst.operands[0].imm > 0xf
10066 && inst.operands[0].imm < 0x0,
10067 _("bad barrier type"));
10068 inst.instruction |= inst.operands[0].imm;
10071 inst.instruction |= 0xf;
10078 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10079 constraint (msb > 32, _("bit-field extends past end of register"));
10080 /* The instruction encoding stores the LSB and MSB,
10081 not the LSB and width. */
10082 Rd = inst.operands[0].reg;
10083 reject_bad_reg (Rd);
10084 inst.instruction |= Rd << 8;
10085 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10086 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10087 inst.instruction |= msb - 1;
10096 Rd = inst.operands[0].reg;
10097 reject_bad_reg (Rd);
10099 /* #0 in second position is alternative syntax for bfc, which is
10100 the same instruction but with REG_PC in the Rm field. */
10101 if (!inst.operands[1].isreg)
10105 Rn = inst.operands[1].reg;
10106 reject_bad_reg (Rn);
10109 msb = inst.operands[2].imm + inst.operands[3].imm;
10110 constraint (msb > 32, _("bit-field extends past end of register"));
10111 /* The instruction encoding stores the LSB and MSB,
10112 not the LSB and width. */
10113 inst.instruction |= Rd << 8;
10114 inst.instruction |= Rn << 16;
10115 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10116 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10117 inst.instruction |= msb - 1;
10125 Rd = inst.operands[0].reg;
10126 Rn = inst.operands[1].reg;
10128 reject_bad_reg (Rd);
10129 reject_bad_reg (Rn);
10131 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10132 _("bit-field extends past end of register"));
10133 inst.instruction |= Rd << 8;
10134 inst.instruction |= Rn << 16;
10135 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10136 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10137 inst.instruction |= inst.operands[3].imm - 1;
10140 /* ARM V5 Thumb BLX (argument parse)
10141 BLX <target_addr> which is BLX(1)
10142 BLX <Rm> which is BLX(2)
10143 Unfortunately, there are two different opcodes for this mnemonic.
10144 So, the insns[].value is not used, and the code here zaps values
10145 into inst.instruction.
10147 ??? How to take advantage of the additional two bits of displacement
10148 available in Thumb32 mode? Need new relocation? */
10153 set_it_insn_type_last ();
10155 if (inst.operands[0].isreg)
10157 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10158 /* We have a register, so this is BLX(2). */
10159 inst.instruction |= inst.operands[0].reg << 3;
10163 /* No register. This must be BLX(1). */
10164 inst.instruction = 0xf000e800;
10165 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10177 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10179 if (in_it_block ())
10181 /* Conditional branches inside IT blocks are encoded as unconditional
10183 cond = COND_ALWAYS;
10188 if (cond != COND_ALWAYS)
10189 opcode = T_MNEM_bcond;
10191 opcode = inst.instruction;
10194 && (inst.size_req == 4
10195 || (inst.size_req != 2
10196 && (inst.operands[0].hasreloc
10197 || inst.reloc.exp.X_op == O_constant))))
10199 inst.instruction = THUMB_OP32(opcode);
10200 if (cond == COND_ALWAYS)
10201 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10204 gas_assert (cond != 0xF);
10205 inst.instruction |= cond << 22;
10206 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10211 inst.instruction = THUMB_OP16(opcode);
10212 if (cond == COND_ALWAYS)
10213 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10216 inst.instruction |= cond << 8;
10217 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10219 /* Allow section relaxation. */
10220 if (unified_syntax && inst.size_req != 2)
10221 inst.relax = opcode;
10223 inst.reloc.type = reloc;
10224 inst.reloc.pc_rel = 1;
10227 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10228 between the two is the maximum immediate allowed - which is passed in
10231 do_t_bkpt_hlt1 (int range)
10233 constraint (inst.cond != COND_ALWAYS,
10234 _("instruction is always unconditional"));
10235 if (inst.operands[0].present)
10237 constraint (inst.operands[0].imm > range,
10238 _("immediate value out of range"));
10239 inst.instruction |= inst.operands[0].imm;
10242 set_it_insn_type (NEUTRAL_IT_INSN);
10248 do_t_bkpt_hlt1 (63);
10254 do_t_bkpt_hlt1 (255);
10258 do_t_branch23 (void)
10260 set_it_insn_type_last ();
10261 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10263 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10264 this file. We used to simply ignore the PLT reloc type here --
10265 the branch encoding is now needed to deal with TLSCALL relocs.
10266 So if we see a PLT reloc now, put it back to how it used to be to
10267 keep the preexisting behaviour. */
10268 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10269 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10271 #if defined(OBJ_COFF)
10272 /* If the destination of the branch is a defined symbol which does not have
10273 the THUMB_FUNC attribute, then we must be calling a function which has
10274 the (interfacearm) attribute. We look for the Thumb entry point to that
10275 function and change the branch to refer to that function instead. */
10276 if ( inst.reloc.exp.X_op == O_symbol
10277 && inst.reloc.exp.X_add_symbol != NULL
10278 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10279 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10280 inst.reloc.exp.X_add_symbol =
10281 find_real_start (inst.reloc.exp.X_add_symbol);
10288 set_it_insn_type_last ();
10289 inst.instruction |= inst.operands[0].reg << 3;
10290 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10291 should cause the alignment to be checked once it is known. This is
10292 because BX PC only works if the instruction is word aligned. */
10300 set_it_insn_type_last ();
10301 Rm = inst.operands[0].reg;
10302 reject_bad_reg (Rm);
10303 inst.instruction |= Rm << 16;
10312 Rd = inst.operands[0].reg;
10313 Rm = inst.operands[1].reg;
10315 reject_bad_reg (Rd);
10316 reject_bad_reg (Rm);
10318 inst.instruction |= Rd << 8;
10319 inst.instruction |= Rm << 16;
10320 inst.instruction |= Rm;
10326 set_it_insn_type (OUTSIDE_IT_INSN);
10327 inst.instruction |= inst.operands[0].imm;
10333 set_it_insn_type (OUTSIDE_IT_INSN);
10335 && (inst.operands[1].present || inst.size_req == 4)
10336 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10338 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10339 inst.instruction = 0xf3af8000;
10340 inst.instruction |= imod << 9;
10341 inst.instruction |= inst.operands[0].imm << 5;
10342 if (inst.operands[1].present)
10343 inst.instruction |= 0x100 | inst.operands[1].imm;
10347 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10348 && (inst.operands[0].imm & 4),
10349 _("selected processor does not support 'A' form "
10350 "of this instruction"));
10351 constraint (inst.operands[1].present || inst.size_req == 4,
10352 _("Thumb does not support the 2-argument "
10353 "form of this instruction"));
10354 inst.instruction |= inst.operands[0].imm;
10358 /* THUMB CPY instruction (argument parse). */
10363 if (inst.size_req == 4)
10365 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10366 inst.instruction |= inst.operands[0].reg << 8;
10367 inst.instruction |= inst.operands[1].reg;
10371 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10372 inst.instruction |= (inst.operands[0].reg & 0x7);
10373 inst.instruction |= inst.operands[1].reg << 3;
10380 set_it_insn_type (OUTSIDE_IT_INSN);
10381 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10382 inst.instruction |= inst.operands[0].reg;
10383 inst.reloc.pc_rel = 1;
10384 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10390 inst.instruction |= inst.operands[0].imm;
10396 unsigned Rd, Rn, Rm;
10398 Rd = inst.operands[0].reg;
10399 Rn = (inst.operands[1].present
10400 ? inst.operands[1].reg : Rd);
10401 Rm = inst.operands[2].reg;
10403 reject_bad_reg (Rd);
10404 reject_bad_reg (Rn);
10405 reject_bad_reg (Rm);
10407 inst.instruction |= Rd << 8;
10408 inst.instruction |= Rn << 16;
10409 inst.instruction |= Rm;
10415 if (unified_syntax && inst.size_req == 4)
10416 inst.instruction = THUMB_OP32 (inst.instruction);
10418 inst.instruction = THUMB_OP16 (inst.instruction);
10424 unsigned int cond = inst.operands[0].imm;
10426 set_it_insn_type (IT_INSN);
10427 now_it.mask = (inst.instruction & 0xf) | 0x10;
10429 now_it.warn_deprecated = FALSE;
10431 /* If the condition is a negative condition, invert the mask. */
10432 if ((cond & 0x1) == 0x0)
10434 unsigned int mask = inst.instruction & 0x000f;
10436 if ((mask & 0x7) == 0)
10438 /* No conversion needed. */
10439 now_it.block_length = 1;
10441 else if ((mask & 0x3) == 0)
10444 now_it.block_length = 2;
10446 else if ((mask & 0x1) == 0)
10449 now_it.block_length = 3;
10454 now_it.block_length = 4;
10457 inst.instruction &= 0xfff0;
10458 inst.instruction |= mask;
10461 inst.instruction |= cond << 4;
10464 /* Helper function used for both push/pop and ldm/stm. */
10466 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10470 load = (inst.instruction & (1 << 20)) != 0;
10472 if (mask & (1 << 13))
10473 inst.error = _("SP not allowed in register list");
10475 if ((mask & (1 << base)) != 0
10477 inst.error = _("having the base register in the register list when "
10478 "using write back is UNPREDICTABLE");
10482 if (mask & (1 << 15))
10484 if (mask & (1 << 14))
10485 inst.error = _("LR and PC should not both be in register list");
10487 set_it_insn_type_last ();
10492 if (mask & (1 << 15))
10493 inst.error = _("PC not allowed in register list");
10496 if ((mask & (mask - 1)) == 0)
10498 /* Single register transfers implemented as str/ldr. */
10501 if (inst.instruction & (1 << 23))
10502 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10504 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10508 if (inst.instruction & (1 << 23))
10509 inst.instruction = 0x00800000; /* ia -> [base] */
10511 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10514 inst.instruction |= 0xf8400000;
10516 inst.instruction |= 0x00100000;
10518 mask = ffs (mask) - 1;
10521 else if (writeback)
10522 inst.instruction |= WRITE_BACK;
10524 inst.instruction |= mask;
10525 inst.instruction |= base << 16;
10531 /* This really doesn't seem worth it. */
10532 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10533 _("expression too complex"));
10534 constraint (inst.operands[1].writeback,
10535 _("Thumb load/store multiple does not support {reglist}^"));
10537 if (unified_syntax)
10539 bfd_boolean narrow;
10543 /* See if we can use a 16-bit instruction. */
10544 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10545 && inst.size_req != 4
10546 && !(inst.operands[1].imm & ~0xff))
10548 mask = 1 << inst.operands[0].reg;
10550 if (inst.operands[0].reg <= 7)
10552 if (inst.instruction == T_MNEM_stmia
10553 ? inst.operands[0].writeback
10554 : (inst.operands[0].writeback
10555 == !(inst.operands[1].imm & mask)))
10557 if (inst.instruction == T_MNEM_stmia
10558 && (inst.operands[1].imm & mask)
10559 && (inst.operands[1].imm & (mask - 1)))
10560 as_warn (_("value stored for r%d is UNKNOWN"),
10561 inst.operands[0].reg);
10563 inst.instruction = THUMB_OP16 (inst.instruction);
10564 inst.instruction |= inst.operands[0].reg << 8;
10565 inst.instruction |= inst.operands[1].imm;
10568 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10570 /* This means 1 register in reg list one of 3 situations:
10571 1. Instruction is stmia, but without writeback.
10572 2. lmdia without writeback, but with Rn not in
10574 3. ldmia with writeback, but with Rn in reglist.
10575 Case 3 is UNPREDICTABLE behaviour, so we handle
10576 case 1 and 2 which can be converted into a 16-bit
10577 str or ldr. The SP cases are handled below. */
10578 unsigned long opcode;
10579 /* First, record an error for Case 3. */
10580 if (inst.operands[1].imm & mask
10581 && inst.operands[0].writeback)
10583 _("having the base register in the register list when "
10584 "using write back is UNPREDICTABLE");
10586 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10588 inst.instruction = THUMB_OP16 (opcode);
10589 inst.instruction |= inst.operands[0].reg << 3;
10590 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10594 else if (inst.operands[0] .reg == REG_SP)
10596 if (inst.operands[0].writeback)
10599 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10600 ? T_MNEM_push : T_MNEM_pop);
10601 inst.instruction |= inst.operands[1].imm;
10604 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10607 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10608 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10609 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10617 if (inst.instruction < 0xffff)
10618 inst.instruction = THUMB_OP32 (inst.instruction);
10620 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10621 inst.operands[0].writeback);
10626 constraint (inst.operands[0].reg > 7
10627 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10628 constraint (inst.instruction != T_MNEM_ldmia
10629 && inst.instruction != T_MNEM_stmia,
10630 _("Thumb-2 instruction only valid in unified syntax"));
10631 if (inst.instruction == T_MNEM_stmia)
10633 if (!inst.operands[0].writeback)
10634 as_warn (_("this instruction will write back the base register"));
10635 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10636 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10637 as_warn (_("value stored for r%d is UNKNOWN"),
10638 inst.operands[0].reg);
10642 if (!inst.operands[0].writeback
10643 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10644 as_warn (_("this instruction will write back the base register"));
10645 else if (inst.operands[0].writeback
10646 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10647 as_warn (_("this instruction will not write back the base register"));
10650 inst.instruction = THUMB_OP16 (inst.instruction);
10651 inst.instruction |= inst.operands[0].reg << 8;
10652 inst.instruction |= inst.operands[1].imm;
10659 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10660 || inst.operands[1].postind || inst.operands[1].writeback
10661 || inst.operands[1].immisreg || inst.operands[1].shifted
10662 || inst.operands[1].negative,
10665 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10667 inst.instruction |= inst.operands[0].reg << 12;
10668 inst.instruction |= inst.operands[1].reg << 16;
10669 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10675 if (!inst.operands[1].present)
10677 constraint (inst.operands[0].reg == REG_LR,
10678 _("r14 not allowed as first register "
10679 "when second register is omitted"));
10680 inst.operands[1].reg = inst.operands[0].reg + 1;
10682 constraint (inst.operands[0].reg == inst.operands[1].reg,
10685 inst.instruction |= inst.operands[0].reg << 12;
10686 inst.instruction |= inst.operands[1].reg << 8;
10687 inst.instruction |= inst.operands[2].reg << 16;
10693 unsigned long opcode;
10696 if (inst.operands[0].isreg
10697 && !inst.operands[0].preind
10698 && inst.operands[0].reg == REG_PC)
10699 set_it_insn_type_last ();
10701 opcode = inst.instruction;
10702 if (unified_syntax)
10704 if (!inst.operands[1].isreg)
10706 if (opcode <= 0xffff)
10707 inst.instruction = THUMB_OP32 (opcode);
10708 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10711 if (inst.operands[1].isreg
10712 && !inst.operands[1].writeback
10713 && !inst.operands[1].shifted && !inst.operands[1].postind
10714 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10715 && opcode <= 0xffff
10716 && inst.size_req != 4)
10718 /* Insn may have a 16-bit form. */
10719 Rn = inst.operands[1].reg;
10720 if (inst.operands[1].immisreg)
10722 inst.instruction = THUMB_OP16 (opcode);
10724 if (Rn <= 7 && inst.operands[1].imm <= 7)
10726 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10727 reject_bad_reg (inst.operands[1].imm);
10729 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10730 && opcode != T_MNEM_ldrsb)
10731 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10732 || (Rn == REG_SP && opcode == T_MNEM_str))
10739 if (inst.reloc.pc_rel)
10740 opcode = T_MNEM_ldr_pc2;
10742 opcode = T_MNEM_ldr_pc;
10746 if (opcode == T_MNEM_ldr)
10747 opcode = T_MNEM_ldr_sp;
10749 opcode = T_MNEM_str_sp;
10751 inst.instruction = inst.operands[0].reg << 8;
10755 inst.instruction = inst.operands[0].reg;
10756 inst.instruction |= inst.operands[1].reg << 3;
10758 inst.instruction |= THUMB_OP16 (opcode);
10759 if (inst.size_req == 2)
10760 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10762 inst.relax = opcode;
10766 /* Definitely a 32-bit variant. */
10768 /* Warning for Erratum 752419. */
10769 if (opcode == T_MNEM_ldr
10770 && inst.operands[0].reg == REG_SP
10771 && inst.operands[1].writeback == 1
10772 && !inst.operands[1].immisreg)
10774 if (no_cpu_selected ()
10775 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10776 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10777 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10778 as_warn (_("This instruction may be unpredictable "
10779 "if executed on M-profile cores "
10780 "with interrupts enabled."));
10783 /* Do some validations regarding addressing modes. */
10784 if (inst.operands[1].immisreg)
10785 reject_bad_reg (inst.operands[1].imm);
10787 constraint (inst.operands[1].writeback == 1
10788 && inst.operands[0].reg == inst.operands[1].reg,
10791 inst.instruction = THUMB_OP32 (opcode);
10792 inst.instruction |= inst.operands[0].reg << 12;
10793 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10794 check_ldr_r15_aligned ();
10798 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10800 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10802 /* Only [Rn,Rm] is acceptable. */
10803 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10804 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10805 || inst.operands[1].postind || inst.operands[1].shifted
10806 || inst.operands[1].negative,
10807 _("Thumb does not support this addressing mode"));
10808 inst.instruction = THUMB_OP16 (inst.instruction);
10812 inst.instruction = THUMB_OP16 (inst.instruction);
10813 if (!inst.operands[1].isreg)
10814 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10817 constraint (!inst.operands[1].preind
10818 || inst.operands[1].shifted
10819 || inst.operands[1].writeback,
10820 _("Thumb does not support this addressing mode"));
10821 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10823 constraint (inst.instruction & 0x0600,
10824 _("byte or halfword not valid for base register"));
10825 constraint (inst.operands[1].reg == REG_PC
10826 && !(inst.instruction & THUMB_LOAD_BIT),
10827 _("r15 based store not allowed"));
10828 constraint (inst.operands[1].immisreg,
10829 _("invalid base register for register offset"));
10831 if (inst.operands[1].reg == REG_PC)
10832 inst.instruction = T_OPCODE_LDR_PC;
10833 else if (inst.instruction & THUMB_LOAD_BIT)
10834 inst.instruction = T_OPCODE_LDR_SP;
10836 inst.instruction = T_OPCODE_STR_SP;
10838 inst.instruction |= inst.operands[0].reg << 8;
10839 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10843 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10844 if (!inst.operands[1].immisreg)
10846 /* Immediate offset. */
10847 inst.instruction |= inst.operands[0].reg;
10848 inst.instruction |= inst.operands[1].reg << 3;
10849 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10853 /* Register offset. */
10854 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10855 constraint (inst.operands[1].negative,
10856 _("Thumb does not support this addressing mode"));
10859 switch (inst.instruction)
10861 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10862 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10863 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10864 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10865 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10866 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10867 case 0x5600 /* ldrsb */:
10868 case 0x5e00 /* ldrsh */: break;
10872 inst.instruction |= inst.operands[0].reg;
10873 inst.instruction |= inst.operands[1].reg << 3;
10874 inst.instruction |= inst.operands[1].imm << 6;
10880 if (!inst.operands[1].present)
10882 inst.operands[1].reg = inst.operands[0].reg + 1;
10883 constraint (inst.operands[0].reg == REG_LR,
10884 _("r14 not allowed here"));
10885 constraint (inst.operands[0].reg == REG_R12,
10886 _("r12 not allowed here"));
10889 if (inst.operands[2].writeback
10890 && (inst.operands[0].reg == inst.operands[2].reg
10891 || inst.operands[1].reg == inst.operands[2].reg))
10892 as_warn (_("base register written back, and overlaps "
10893 "one of transfer registers"));
10895 inst.instruction |= inst.operands[0].reg << 12;
10896 inst.instruction |= inst.operands[1].reg << 8;
10897 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10903 inst.instruction |= inst.operands[0].reg << 12;
10904 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10910 unsigned Rd, Rn, Rm, Ra;
10912 Rd = inst.operands[0].reg;
10913 Rn = inst.operands[1].reg;
10914 Rm = inst.operands[2].reg;
10915 Ra = inst.operands[3].reg;
10917 reject_bad_reg (Rd);
10918 reject_bad_reg (Rn);
10919 reject_bad_reg (Rm);
10920 reject_bad_reg (Ra);
10922 inst.instruction |= Rd << 8;
10923 inst.instruction |= Rn << 16;
10924 inst.instruction |= Rm;
10925 inst.instruction |= Ra << 12;
10931 unsigned RdLo, RdHi, Rn, Rm;
10933 RdLo = inst.operands[0].reg;
10934 RdHi = inst.operands[1].reg;
10935 Rn = inst.operands[2].reg;
10936 Rm = inst.operands[3].reg;
10938 reject_bad_reg (RdLo);
10939 reject_bad_reg (RdHi);
10940 reject_bad_reg (Rn);
10941 reject_bad_reg (Rm);
10943 inst.instruction |= RdLo << 12;
10944 inst.instruction |= RdHi << 8;
10945 inst.instruction |= Rn << 16;
10946 inst.instruction |= Rm;
10950 do_t_mov_cmp (void)
10954 Rn = inst.operands[0].reg;
10955 Rm = inst.operands[1].reg;
10958 set_it_insn_type_last ();
10960 if (unified_syntax)
10962 int r0off = (inst.instruction == T_MNEM_mov
10963 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10964 unsigned long opcode;
10965 bfd_boolean narrow;
10966 bfd_boolean low_regs;
10968 low_regs = (Rn <= 7 && Rm <= 7);
10969 opcode = inst.instruction;
10970 if (in_it_block ())
10971 narrow = opcode != T_MNEM_movs;
10973 narrow = opcode != T_MNEM_movs || low_regs;
10974 if (inst.size_req == 4
10975 || inst.operands[1].shifted)
10978 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10979 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10980 && !inst.operands[1].shifted
10984 inst.instruction = T2_SUBS_PC_LR;
10988 if (opcode == T_MNEM_cmp)
10990 constraint (Rn == REG_PC, BAD_PC);
10993 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10995 warn_deprecated_sp (Rm);
10996 /* R15 was documented as a valid choice for Rm in ARMv6,
10997 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10998 tools reject R15, so we do too. */
10999 constraint (Rm == REG_PC, BAD_PC);
11002 reject_bad_reg (Rm);
11004 else if (opcode == T_MNEM_mov
11005 || opcode == T_MNEM_movs)
11007 if (inst.operands[1].isreg)
11009 if (opcode == T_MNEM_movs)
11011 reject_bad_reg (Rn);
11012 reject_bad_reg (Rm);
11016 /* This is mov.n. */
11017 if ((Rn == REG_SP || Rn == REG_PC)
11018 && (Rm == REG_SP || Rm == REG_PC))
11020 as_warn (_("Use of r%u as a source register is "
11021 "deprecated when r%u is the destination "
11022 "register."), Rm, Rn);
11027 /* This is mov.w. */
11028 constraint (Rn == REG_PC, BAD_PC);
11029 constraint (Rm == REG_PC, BAD_PC);
11030 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11034 reject_bad_reg (Rn);
11037 if (!inst.operands[1].isreg)
11039 /* Immediate operand. */
11040 if (!in_it_block () && opcode == T_MNEM_mov)
11042 if (low_regs && narrow)
11044 inst.instruction = THUMB_OP16 (opcode);
11045 inst.instruction |= Rn << 8;
11046 if (inst.size_req == 2)
11047 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11049 inst.relax = opcode;
11053 inst.instruction = THUMB_OP32 (inst.instruction);
11054 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11055 inst.instruction |= Rn << r0off;
11056 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11059 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11060 && (inst.instruction == T_MNEM_mov
11061 || inst.instruction == T_MNEM_movs))
11063 /* Register shifts are encoded as separate shift instructions. */
11064 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11066 if (in_it_block ())
11071 if (inst.size_req == 4)
11074 if (!low_regs || inst.operands[1].imm > 7)
11080 switch (inst.operands[1].shift_kind)
11083 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11086 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11089 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11092 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11098 inst.instruction = opcode;
11101 inst.instruction |= Rn;
11102 inst.instruction |= inst.operands[1].imm << 3;
11107 inst.instruction |= CONDS_BIT;
11109 inst.instruction |= Rn << 8;
11110 inst.instruction |= Rm << 16;
11111 inst.instruction |= inst.operands[1].imm;
11116 /* Some mov with immediate shift have narrow variants.
11117 Register shifts are handled above. */
11118 if (low_regs && inst.operands[1].shifted
11119 && (inst.instruction == T_MNEM_mov
11120 || inst.instruction == T_MNEM_movs))
11122 if (in_it_block ())
11123 narrow = (inst.instruction == T_MNEM_mov);
11125 narrow = (inst.instruction == T_MNEM_movs);
11130 switch (inst.operands[1].shift_kind)
11132 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11133 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11134 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11135 default: narrow = FALSE; break;
11141 inst.instruction |= Rn;
11142 inst.instruction |= Rm << 3;
11143 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11147 inst.instruction = THUMB_OP32 (inst.instruction);
11148 inst.instruction |= Rn << r0off;
11149 encode_thumb32_shifted_operand (1);
11153 switch (inst.instruction)
11156 /* In v4t or v5t a move of two lowregs produces unpredictable
11157 results. Don't allow this. */
11160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11161 "MOV Rd, Rs with two low registers is not "
11162 "permitted on this architecture");
11163 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11167 inst.instruction = T_OPCODE_MOV_HR;
11168 inst.instruction |= (Rn & 0x8) << 4;
11169 inst.instruction |= (Rn & 0x7);
11170 inst.instruction |= Rm << 3;
11174 /* We know we have low registers at this point.
11175 Generate LSLS Rd, Rs, #0. */
11176 inst.instruction = T_OPCODE_LSL_I;
11177 inst.instruction |= Rn;
11178 inst.instruction |= Rm << 3;
11184 inst.instruction = T_OPCODE_CMP_LR;
11185 inst.instruction |= Rn;
11186 inst.instruction |= Rm << 3;
11190 inst.instruction = T_OPCODE_CMP_HR;
11191 inst.instruction |= (Rn & 0x8) << 4;
11192 inst.instruction |= (Rn & 0x7);
11193 inst.instruction |= Rm << 3;
11200 inst.instruction = THUMB_OP16 (inst.instruction);
11202 /* PR 10443: Do not silently ignore shifted operands. */
11203 constraint (inst.operands[1].shifted,
11204 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11206 if (inst.operands[1].isreg)
11208 if (Rn < 8 && Rm < 8)
11210 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11211 since a MOV instruction produces unpredictable results. */
11212 if (inst.instruction == T_OPCODE_MOV_I8)
11213 inst.instruction = T_OPCODE_ADD_I3;
11215 inst.instruction = T_OPCODE_CMP_LR;
11217 inst.instruction |= Rn;
11218 inst.instruction |= Rm << 3;
11222 if (inst.instruction == T_OPCODE_MOV_I8)
11223 inst.instruction = T_OPCODE_MOV_HR;
11225 inst.instruction = T_OPCODE_CMP_HR;
11231 constraint (Rn > 7,
11232 _("only lo regs allowed with immediate"));
11233 inst.instruction |= Rn << 8;
11234 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11245 top = (inst.instruction & 0x00800000) != 0;
11246 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11248 constraint (top, _(":lower16: not allowed this instruction"));
11249 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11251 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11253 constraint (!top, _(":upper16: not allowed this instruction"));
11254 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11257 Rd = inst.operands[0].reg;
11258 reject_bad_reg (Rd);
11260 inst.instruction |= Rd << 8;
11261 if (inst.reloc.type == BFD_RELOC_UNUSED)
11263 imm = inst.reloc.exp.X_add_number;
11264 inst.instruction |= (imm & 0xf000) << 4;
11265 inst.instruction |= (imm & 0x0800) << 15;
11266 inst.instruction |= (imm & 0x0700) << 4;
11267 inst.instruction |= (imm & 0x00ff);
11272 do_t_mvn_tst (void)
11276 Rn = inst.operands[0].reg;
11277 Rm = inst.operands[1].reg;
11279 if (inst.instruction == T_MNEM_cmp
11280 || inst.instruction == T_MNEM_cmn)
11281 constraint (Rn == REG_PC, BAD_PC);
11283 reject_bad_reg (Rn);
11284 reject_bad_reg (Rm);
11286 if (unified_syntax)
11288 int r0off = (inst.instruction == T_MNEM_mvn
11289 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11290 bfd_boolean narrow;
11292 if (inst.size_req == 4
11293 || inst.instruction > 0xffff
11294 || inst.operands[1].shifted
11295 || Rn > 7 || Rm > 7)
11297 else if (inst.instruction == T_MNEM_cmn)
11299 else if (THUMB_SETS_FLAGS (inst.instruction))
11300 narrow = !in_it_block ();
11302 narrow = in_it_block ();
11304 if (!inst.operands[1].isreg)
11306 /* For an immediate, we always generate a 32-bit opcode;
11307 section relaxation will shrink it later if possible. */
11308 if (inst.instruction < 0xffff)
11309 inst.instruction = THUMB_OP32 (inst.instruction);
11310 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11311 inst.instruction |= Rn << r0off;
11312 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11316 /* See if we can do this with a 16-bit instruction. */
11319 inst.instruction = THUMB_OP16 (inst.instruction);
11320 inst.instruction |= Rn;
11321 inst.instruction |= Rm << 3;
11325 constraint (inst.operands[1].shifted
11326 && inst.operands[1].immisreg,
11327 _("shift must be constant"));
11328 if (inst.instruction < 0xffff)
11329 inst.instruction = THUMB_OP32 (inst.instruction);
11330 inst.instruction |= Rn << r0off;
11331 encode_thumb32_shifted_operand (1);
11337 constraint (inst.instruction > 0xffff
11338 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11339 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11340 _("unshifted register required"));
11341 constraint (Rn > 7 || Rm > 7,
11344 inst.instruction = THUMB_OP16 (inst.instruction);
11345 inst.instruction |= Rn;
11346 inst.instruction |= Rm << 3;
11355 if (do_vfp_nsyn_mrs () == SUCCESS)
11358 Rd = inst.operands[0].reg;
11359 reject_bad_reg (Rd);
11360 inst.instruction |= Rd << 8;
11362 if (inst.operands[1].isreg)
11364 unsigned br = inst.operands[1].reg;
11365 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11366 as_bad (_("bad register for mrs"));
11368 inst.instruction |= br & (0xf << 16);
11369 inst.instruction |= (br & 0x300) >> 4;
11370 inst.instruction |= (br & SPSR_BIT) >> 2;
11374 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11376 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11378 /* PR gas/12698: The constraint is only applied for m_profile.
11379 If the user has specified -march=all, we want to ignore it as
11380 we are building for any CPU type, including non-m variants. */
11381 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11382 constraint ((flags != 0) && m_profile, _("selected processor does "
11383 "not support requested special purpose register"));
11386 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11388 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11389 _("'APSR', 'CPSR' or 'SPSR' expected"));
11391 inst.instruction |= (flags & SPSR_BIT) >> 2;
11392 inst.instruction |= inst.operands[1].imm & 0xff;
11393 inst.instruction |= 0xf0000;
11403 if (do_vfp_nsyn_msr () == SUCCESS)
11406 constraint (!inst.operands[1].isreg,
11407 _("Thumb encoding does not support an immediate here"));
11409 if (inst.operands[0].isreg)
11410 flags = (int)(inst.operands[0].reg);
11412 flags = inst.operands[0].imm;
11414 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11416 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11418 /* PR gas/12698: The constraint is only applied for m_profile.
11419 If the user has specified -march=all, we want to ignore it as
11420 we are building for any CPU type, including non-m variants. */
11421 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11422 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11423 && (bits & ~(PSR_s | PSR_f)) != 0)
11424 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11425 && bits != PSR_f)) && m_profile,
11426 _("selected processor does not support requested special "
11427 "purpose register"));
11430 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11431 "requested special purpose register"));
11433 Rn = inst.operands[1].reg;
11434 reject_bad_reg (Rn);
11436 inst.instruction |= (flags & SPSR_BIT) >> 2;
11437 inst.instruction |= (flags & 0xf0000) >> 8;
11438 inst.instruction |= (flags & 0x300) >> 4;
11439 inst.instruction |= (flags & 0xff);
11440 inst.instruction |= Rn << 16;
11446 bfd_boolean narrow;
11447 unsigned Rd, Rn, Rm;
11449 if (!inst.operands[2].present)
11450 inst.operands[2].reg = inst.operands[0].reg;
11452 Rd = inst.operands[0].reg;
11453 Rn = inst.operands[1].reg;
11454 Rm = inst.operands[2].reg;
11456 if (unified_syntax)
11458 if (inst.size_req == 4
11464 else if (inst.instruction == T_MNEM_muls)
11465 narrow = !in_it_block ();
11467 narrow = in_it_block ();
11471 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11472 constraint (Rn > 7 || Rm > 7,
11479 /* 16-bit MULS/Conditional MUL. */
11480 inst.instruction = THUMB_OP16 (inst.instruction);
11481 inst.instruction |= Rd;
11484 inst.instruction |= Rm << 3;
11486 inst.instruction |= Rn << 3;
11488 constraint (1, _("dest must overlap one source register"));
11492 constraint (inst.instruction != T_MNEM_mul,
11493 _("Thumb-2 MUL must not set flags"));
11495 inst.instruction = THUMB_OP32 (inst.instruction);
11496 inst.instruction |= Rd << 8;
11497 inst.instruction |= Rn << 16;
11498 inst.instruction |= Rm << 0;
11500 reject_bad_reg (Rd);
11501 reject_bad_reg (Rn);
11502 reject_bad_reg (Rm);
11509 unsigned RdLo, RdHi, Rn, Rm;
11511 RdLo = inst.operands[0].reg;
11512 RdHi = inst.operands[1].reg;
11513 Rn = inst.operands[2].reg;
11514 Rm = inst.operands[3].reg;
11516 reject_bad_reg (RdLo);
11517 reject_bad_reg (RdHi);
11518 reject_bad_reg (Rn);
11519 reject_bad_reg (Rm);
11521 inst.instruction |= RdLo << 12;
11522 inst.instruction |= RdHi << 8;
11523 inst.instruction |= Rn << 16;
11524 inst.instruction |= Rm;
11527 as_tsktsk (_("rdhi and rdlo must be different"));
11533 set_it_insn_type (NEUTRAL_IT_INSN);
11535 if (unified_syntax)
11537 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11539 inst.instruction = THUMB_OP32 (inst.instruction);
11540 inst.instruction |= inst.operands[0].imm;
11544 /* PR9722: Check for Thumb2 availability before
11545 generating a thumb2 nop instruction. */
11546 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11548 inst.instruction = THUMB_OP16 (inst.instruction);
11549 inst.instruction |= inst.operands[0].imm << 4;
11552 inst.instruction = 0x46c0;
11557 constraint (inst.operands[0].present,
11558 _("Thumb does not support NOP with hints"));
11559 inst.instruction = 0x46c0;
11566 if (unified_syntax)
11568 bfd_boolean narrow;
11570 if (THUMB_SETS_FLAGS (inst.instruction))
11571 narrow = !in_it_block ();
11573 narrow = in_it_block ();
11574 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11576 if (inst.size_req == 4)
11581 inst.instruction = THUMB_OP32 (inst.instruction);
11582 inst.instruction |= inst.operands[0].reg << 8;
11583 inst.instruction |= inst.operands[1].reg << 16;
11587 inst.instruction = THUMB_OP16 (inst.instruction);
11588 inst.instruction |= inst.operands[0].reg;
11589 inst.instruction |= inst.operands[1].reg << 3;
11594 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11596 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11598 inst.instruction = THUMB_OP16 (inst.instruction);
11599 inst.instruction |= inst.operands[0].reg;
11600 inst.instruction |= inst.operands[1].reg << 3;
11609 Rd = inst.operands[0].reg;
11610 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11612 reject_bad_reg (Rd);
11613 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11614 reject_bad_reg (Rn);
11616 inst.instruction |= Rd << 8;
11617 inst.instruction |= Rn << 16;
11619 if (!inst.operands[2].isreg)
11621 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11622 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11628 Rm = inst.operands[2].reg;
11629 reject_bad_reg (Rm);
11631 constraint (inst.operands[2].shifted
11632 && inst.operands[2].immisreg,
11633 _("shift must be constant"));
11634 encode_thumb32_shifted_operand (2);
11641 unsigned Rd, Rn, Rm;
11643 Rd = inst.operands[0].reg;
11644 Rn = inst.operands[1].reg;
11645 Rm = inst.operands[2].reg;
11647 reject_bad_reg (Rd);
11648 reject_bad_reg (Rn);
11649 reject_bad_reg (Rm);
11651 inst.instruction |= Rd << 8;
11652 inst.instruction |= Rn << 16;
11653 inst.instruction |= Rm;
11654 if (inst.operands[3].present)
11656 unsigned int val = inst.reloc.exp.X_add_number;
11657 constraint (inst.reloc.exp.X_op != O_constant,
11658 _("expression too complex"));
11659 inst.instruction |= (val & 0x1c) << 10;
11660 inst.instruction |= (val & 0x03) << 6;
11667 if (!inst.operands[3].present)
11671 inst.instruction &= ~0x00000020;
11673 /* PR 10168. Swap the Rm and Rn registers. */
11674 Rtmp = inst.operands[1].reg;
11675 inst.operands[1].reg = inst.operands[2].reg;
11676 inst.operands[2].reg = Rtmp;
11684 if (inst.operands[0].immisreg)
11685 reject_bad_reg (inst.operands[0].imm);
11687 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11691 do_t_push_pop (void)
11695 constraint (inst.operands[0].writeback,
11696 _("push/pop do not support {reglist}^"));
11697 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11698 _("expression too complex"));
11700 mask = inst.operands[0].imm;
11701 if ((mask & ~0xff) == 0)
11702 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11703 else if ((inst.instruction == T_MNEM_push
11704 && (mask & ~0xff) == 1 << REG_LR)
11705 || (inst.instruction == T_MNEM_pop
11706 && (mask & ~0xff) == 1 << REG_PC))
11708 inst.instruction = THUMB_OP16 (inst.instruction);
11709 inst.instruction |= THUMB_PP_PC_LR;
11710 inst.instruction |= mask & 0xff;
11712 else if (unified_syntax)
11714 inst.instruction = THUMB_OP32 (inst.instruction);
11715 encode_thumb2_ldmstm (13, mask, TRUE);
11719 inst.error = _("invalid register list to push/pop instruction");
11729 Rd = inst.operands[0].reg;
11730 Rm = inst.operands[1].reg;
11732 reject_bad_reg (Rd);
11733 reject_bad_reg (Rm);
11735 inst.instruction |= Rd << 8;
11736 inst.instruction |= Rm << 16;
11737 inst.instruction |= Rm;
11745 Rd = inst.operands[0].reg;
11746 Rm = inst.operands[1].reg;
11748 reject_bad_reg (Rd);
11749 reject_bad_reg (Rm);
11751 if (Rd <= 7 && Rm <= 7
11752 && inst.size_req != 4)
11754 inst.instruction = THUMB_OP16 (inst.instruction);
11755 inst.instruction |= Rd;
11756 inst.instruction |= Rm << 3;
11758 else if (unified_syntax)
11760 inst.instruction = THUMB_OP32 (inst.instruction);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rm << 16;
11763 inst.instruction |= Rm;
11766 inst.error = BAD_HIREG;
11774 Rd = inst.operands[0].reg;
11775 Rm = inst.operands[1].reg;
11777 reject_bad_reg (Rd);
11778 reject_bad_reg (Rm);
11780 inst.instruction |= Rd << 8;
11781 inst.instruction |= Rm;
11789 Rd = inst.operands[0].reg;
11790 Rs = (inst.operands[1].present
11791 ? inst.operands[1].reg /* Rd, Rs, foo */
11792 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11794 reject_bad_reg (Rd);
11795 reject_bad_reg (Rs);
11796 if (inst.operands[2].isreg)
11797 reject_bad_reg (inst.operands[2].reg);
11799 inst.instruction |= Rd << 8;
11800 inst.instruction |= Rs << 16;
11801 if (!inst.operands[2].isreg)
11803 bfd_boolean narrow;
11805 if ((inst.instruction & 0x00100000) != 0)
11806 narrow = !in_it_block ();
11808 narrow = in_it_block ();
11810 if (Rd > 7 || Rs > 7)
11813 if (inst.size_req == 4 || !unified_syntax)
11816 if (inst.reloc.exp.X_op != O_constant
11817 || inst.reloc.exp.X_add_number != 0)
11820 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11821 relaxation, but it doesn't seem worth the hassle. */
11824 inst.reloc.type = BFD_RELOC_UNUSED;
11825 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11826 inst.instruction |= Rs << 3;
11827 inst.instruction |= Rd;
11831 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11832 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11836 encode_thumb32_shifted_operand (2);
11842 if (warn_on_deprecated
11843 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11844 as_warn (_("setend use is deprecated for ARMv8"));
11846 set_it_insn_type (OUTSIDE_IT_INSN);
11847 if (inst.operands[0].imm)
11848 inst.instruction |= 0x8;
11854 if (!inst.operands[1].present)
11855 inst.operands[1].reg = inst.operands[0].reg;
11857 if (unified_syntax)
11859 bfd_boolean narrow;
11862 switch (inst.instruction)
11865 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11867 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11869 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11871 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11875 if (THUMB_SETS_FLAGS (inst.instruction))
11876 narrow = !in_it_block ();
11878 narrow = in_it_block ();
11879 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11881 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11883 if (inst.operands[2].isreg
11884 && (inst.operands[1].reg != inst.operands[0].reg
11885 || inst.operands[2].reg > 7))
11887 if (inst.size_req == 4)
11890 reject_bad_reg (inst.operands[0].reg);
11891 reject_bad_reg (inst.operands[1].reg);
11895 if (inst.operands[2].isreg)
11897 reject_bad_reg (inst.operands[2].reg);
11898 inst.instruction = THUMB_OP32 (inst.instruction);
11899 inst.instruction |= inst.operands[0].reg << 8;
11900 inst.instruction |= inst.operands[1].reg << 16;
11901 inst.instruction |= inst.operands[2].reg;
11903 /* PR 12854: Error on extraneous shifts. */
11904 constraint (inst.operands[2].shifted,
11905 _("extraneous shift as part of operand to shift insn"));
11909 inst.operands[1].shifted = 1;
11910 inst.operands[1].shift_kind = shift_kind;
11911 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11912 ? T_MNEM_movs : T_MNEM_mov);
11913 inst.instruction |= inst.operands[0].reg << 8;
11914 encode_thumb32_shifted_operand (1);
11915 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11916 inst.reloc.type = BFD_RELOC_UNUSED;
11921 if (inst.operands[2].isreg)
11923 switch (shift_kind)
11925 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11926 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11927 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11928 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11932 inst.instruction |= inst.operands[0].reg;
11933 inst.instruction |= inst.operands[2].reg << 3;
11935 /* PR 12854: Error on extraneous shifts. */
11936 constraint (inst.operands[2].shifted,
11937 _("extraneous shift as part of operand to shift insn"));
11941 switch (shift_kind)
11943 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11944 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11945 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11948 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11949 inst.instruction |= inst.operands[0].reg;
11950 inst.instruction |= inst.operands[1].reg << 3;
11956 constraint (inst.operands[0].reg > 7
11957 || inst.operands[1].reg > 7, BAD_HIREG);
11958 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11960 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11962 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11963 constraint (inst.operands[0].reg != inst.operands[1].reg,
11964 _("source1 and dest must be same register"));
11966 switch (inst.instruction)
11968 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11969 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11970 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11971 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11975 inst.instruction |= inst.operands[0].reg;
11976 inst.instruction |= inst.operands[2].reg << 3;
11978 /* PR 12854: Error on extraneous shifts. */
11979 constraint (inst.operands[2].shifted,
11980 _("extraneous shift as part of operand to shift insn"));
11984 switch (inst.instruction)
11986 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11987 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11988 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11989 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11992 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11993 inst.instruction |= inst.operands[0].reg;
11994 inst.instruction |= inst.operands[1].reg << 3;
12002 unsigned Rd, Rn, Rm;
12004 Rd = inst.operands[0].reg;
12005 Rn = inst.operands[1].reg;
12006 Rm = inst.operands[2].reg;
12008 reject_bad_reg (Rd);
12009 reject_bad_reg (Rn);
12010 reject_bad_reg (Rm);
12012 inst.instruction |= Rd << 8;
12013 inst.instruction |= Rn << 16;
12014 inst.instruction |= Rm;
12020 unsigned Rd, Rn, Rm;
12022 Rd = inst.operands[0].reg;
12023 Rm = inst.operands[1].reg;
12024 Rn = inst.operands[2].reg;
12026 reject_bad_reg (Rd);
12027 reject_bad_reg (Rn);
12028 reject_bad_reg (Rm);
12030 inst.instruction |= Rd << 8;
12031 inst.instruction |= Rn << 16;
12032 inst.instruction |= Rm;
12038 unsigned int value = inst.reloc.exp.X_add_number;
12039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12040 _("SMC is not permitted on this architecture"));
12041 constraint (inst.reloc.exp.X_op != O_constant,
12042 _("expression too complex"));
12043 inst.reloc.type = BFD_RELOC_UNUSED;
12044 inst.instruction |= (value & 0xf000) >> 12;
12045 inst.instruction |= (value & 0x0ff0);
12046 inst.instruction |= (value & 0x000f) << 16;
12052 unsigned int value = inst.reloc.exp.X_add_number;
12054 inst.reloc.type = BFD_RELOC_UNUSED;
12055 inst.instruction |= (value & 0x0fff);
12056 inst.instruction |= (value & 0xf000) << 4;
12060 do_t_ssat_usat (int bias)
12064 Rd = inst.operands[0].reg;
12065 Rn = inst.operands[2].reg;
12067 reject_bad_reg (Rd);
12068 reject_bad_reg (Rn);
12070 inst.instruction |= Rd << 8;
12071 inst.instruction |= inst.operands[1].imm - bias;
12072 inst.instruction |= Rn << 16;
12074 if (inst.operands[3].present)
12076 offsetT shift_amount = inst.reloc.exp.X_add_number;
12078 inst.reloc.type = BFD_RELOC_UNUSED;
12080 constraint (inst.reloc.exp.X_op != O_constant,
12081 _("expression too complex"));
12083 if (shift_amount != 0)
12085 constraint (shift_amount > 31,
12086 _("shift expression is too large"));
12088 if (inst.operands[3].shift_kind == SHIFT_ASR)
12089 inst.instruction |= 0x00200000; /* sh bit. */
12091 inst.instruction |= (shift_amount & 0x1c) << 10;
12092 inst.instruction |= (shift_amount & 0x03) << 6;
12100 do_t_ssat_usat (1);
12108 Rd = inst.operands[0].reg;
12109 Rn = inst.operands[2].reg;
12111 reject_bad_reg (Rd);
12112 reject_bad_reg (Rn);
12114 inst.instruction |= Rd << 8;
12115 inst.instruction |= inst.operands[1].imm - 1;
12116 inst.instruction |= Rn << 16;
12122 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12123 || inst.operands[2].postind || inst.operands[2].writeback
12124 || inst.operands[2].immisreg || inst.operands[2].shifted
12125 || inst.operands[2].negative,
12128 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12130 inst.instruction |= inst.operands[0].reg << 8;
12131 inst.instruction |= inst.operands[1].reg << 12;
12132 inst.instruction |= inst.operands[2].reg << 16;
12133 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12139 if (!inst.operands[2].present)
12140 inst.operands[2].reg = inst.operands[1].reg + 1;
12142 constraint (inst.operands[0].reg == inst.operands[1].reg
12143 || inst.operands[0].reg == inst.operands[2].reg
12144 || inst.operands[0].reg == inst.operands[3].reg,
12147 inst.instruction |= inst.operands[0].reg;
12148 inst.instruction |= inst.operands[1].reg << 12;
12149 inst.instruction |= inst.operands[2].reg << 8;
12150 inst.instruction |= inst.operands[3].reg << 16;
12156 unsigned Rd, Rn, Rm;
12158 Rd = inst.operands[0].reg;
12159 Rn = inst.operands[1].reg;
12160 Rm = inst.operands[2].reg;
12162 reject_bad_reg (Rd);
12163 reject_bad_reg (Rn);
12164 reject_bad_reg (Rm);
12166 inst.instruction |= Rd << 8;
12167 inst.instruction |= Rn << 16;
12168 inst.instruction |= Rm;
12169 inst.instruction |= inst.operands[3].imm << 4;
12177 Rd = inst.operands[0].reg;
12178 Rm = inst.operands[1].reg;
12180 reject_bad_reg (Rd);
12181 reject_bad_reg (Rm);
12183 if (inst.instruction <= 0xffff
12184 && inst.size_req != 4
12185 && Rd <= 7 && Rm <= 7
12186 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12188 inst.instruction = THUMB_OP16 (inst.instruction);
12189 inst.instruction |= Rd;
12190 inst.instruction |= Rm << 3;
12192 else if (unified_syntax)
12194 if (inst.instruction <= 0xffff)
12195 inst.instruction = THUMB_OP32 (inst.instruction);
12196 inst.instruction |= Rd << 8;
12197 inst.instruction |= Rm;
12198 inst.instruction |= inst.operands[2].imm << 4;
12202 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12203 _("Thumb encoding does not support rotation"));
12204 constraint (1, BAD_HIREG);
12211 /* We have to do the following check manually as ARM_EXT_OS only applies
12213 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12215 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12216 /* This only applies to the v6m howver, not later architectures. */
12217 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12218 as_bad (_("SVC is not permitted on this architecture"));
12219 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12222 inst.reloc.type = BFD_RELOC_ARM_SWI;
12231 half = (inst.instruction & 0x10) != 0;
12232 set_it_insn_type_last ();
12233 constraint (inst.operands[0].immisreg,
12234 _("instruction requires register index"));
12236 Rn = inst.operands[0].reg;
12237 Rm = inst.operands[0].imm;
12239 constraint (Rn == REG_SP, BAD_SP);
12240 reject_bad_reg (Rm);
12242 constraint (!half && inst.operands[0].shifted,
12243 _("instruction does not allow shifted index"));
12244 inst.instruction |= (Rn << 16) | Rm;
12250 do_t_ssat_usat (0);
12258 Rd = inst.operands[0].reg;
12259 Rn = inst.operands[2].reg;
12261 reject_bad_reg (Rd);
12262 reject_bad_reg (Rn);
12264 inst.instruction |= Rd << 8;
12265 inst.instruction |= inst.operands[1].imm;
12266 inst.instruction |= Rn << 16;
12269 /* Neon instruction encoder helpers. */
12271 /* Encodings for the different types for various Neon opcodes. */
12273 /* An "invalid" code for the following tables. */
12276 struct neon_tab_entry
12279 unsigned float_or_poly;
12280 unsigned scalar_or_imm;
12283 /* Map overloaded Neon opcodes to their respective encodings. */
12284 #define NEON_ENC_TAB \
12285 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12286 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12287 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12288 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12289 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12290 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12291 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12292 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12293 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12294 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12295 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12296 /* Register variants of the following two instructions are encoded as
12297 vcge / vcgt with the operands reversed. */ \
12298 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12299 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12300 X(vfma, N_INV, 0x0000c10, N_INV), \
12301 X(vfms, N_INV, 0x0200c10, N_INV), \
12302 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12303 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12304 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12305 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12306 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12307 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12308 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12309 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12310 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12311 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12312 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12313 X(vshl, 0x0000400, N_INV, 0x0800510), \
12314 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12315 X(vand, 0x0000110, N_INV, 0x0800030), \
12316 X(vbic, 0x0100110, N_INV, 0x0800030), \
12317 X(veor, 0x1000110, N_INV, N_INV), \
12318 X(vorn, 0x0300110, N_INV, 0x0800010), \
12319 X(vorr, 0x0200110, N_INV, 0x0800010), \
12320 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12321 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12322 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12323 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12324 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12325 X(vst1, 0x0000000, 0x0800000, N_INV), \
12326 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12327 X(vst2, 0x0000100, 0x0800100, N_INV), \
12328 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12329 X(vst3, 0x0000200, 0x0800200, N_INV), \
12330 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12331 X(vst4, 0x0000300, 0x0800300, N_INV), \
12332 X(vmovn, 0x1b20200, N_INV, N_INV), \
12333 X(vtrn, 0x1b20080, N_INV, N_INV), \
12334 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12335 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12336 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12337 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12338 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12339 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12340 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12341 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12342 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12343 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12344 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12345 X(vseleq, 0xe000a00, N_INV, N_INV), \
12346 X(vselvs, 0xe100a00, N_INV, N_INV), \
12347 X(vselge, 0xe200a00, N_INV, N_INV), \
12348 X(vselgt, 0xe300a00, N_INV, N_INV), \
12349 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12350 X(vminnm, 0xe800a40, 0x3200f10, N_INV)
12354 #define X(OPC,I,F,S) N_MNEM_##OPC
12359 static const struct neon_tab_entry neon_enc_tab[] =
12361 #define X(OPC,I,F,S) { (I), (F), (S) }
12366 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12367 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12368 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12369 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12370 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12371 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12372 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12373 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12374 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12375 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12376 #define NEON_ENC_SINGLE_(X) \
12377 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12378 #define NEON_ENC_DOUBLE_(X) \
12379 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12380 #define NEON_ENC_FPV8_(X) \
12381 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12383 #define NEON_ENCODE(type, inst) \
12386 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12387 inst.is_neon = 1; \
12391 #define check_neon_suffixes \
12394 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12396 as_bad (_("invalid neon suffix for non neon instruction")); \
12402 /* Define shapes for instruction operands. The following mnemonic characters
12403 are used in this table:
12405 F - VFP S<n> register
12406 D - Neon D<n> register
12407 Q - Neon Q<n> register
12411 L - D<n> register list
12413 This table is used to generate various data:
12414 - enumerations of the form NS_DDR to be used as arguments to
12416 - a table classifying shapes into single, double, quad, mixed.
12417 - a table used to drive neon_select_shape. */
12419 #define NEON_SHAPE_DEF \
12420 X(3, (D, D, D), DOUBLE), \
12421 X(3, (Q, Q, Q), QUAD), \
12422 X(3, (D, D, I), DOUBLE), \
12423 X(3, (Q, Q, I), QUAD), \
12424 X(3, (D, D, S), DOUBLE), \
12425 X(3, (Q, Q, S), QUAD), \
12426 X(2, (D, D), DOUBLE), \
12427 X(2, (Q, Q), QUAD), \
12428 X(2, (D, S), DOUBLE), \
12429 X(2, (Q, S), QUAD), \
12430 X(2, (D, R), DOUBLE), \
12431 X(2, (Q, R), QUAD), \
12432 X(2, (D, I), DOUBLE), \
12433 X(2, (Q, I), QUAD), \
12434 X(3, (D, L, D), DOUBLE), \
12435 X(2, (D, Q), MIXED), \
12436 X(2, (Q, D), MIXED), \
12437 X(3, (D, Q, I), MIXED), \
12438 X(3, (Q, D, I), MIXED), \
12439 X(3, (Q, D, D), MIXED), \
12440 X(3, (D, Q, Q), MIXED), \
12441 X(3, (Q, Q, D), MIXED), \
12442 X(3, (Q, D, S), MIXED), \
12443 X(3, (D, Q, S), MIXED), \
12444 X(4, (D, D, D, I), DOUBLE), \
12445 X(4, (Q, Q, Q, I), QUAD), \
12446 X(2, (F, F), SINGLE), \
12447 X(3, (F, F, F), SINGLE), \
12448 X(2, (F, I), SINGLE), \
12449 X(2, (F, D), MIXED), \
12450 X(2, (D, F), MIXED), \
12451 X(3, (F, F, I), MIXED), \
12452 X(4, (R, R, F, F), SINGLE), \
12453 X(4, (F, F, R, R), SINGLE), \
12454 X(3, (D, R, R), DOUBLE), \
12455 X(3, (R, R, D), DOUBLE), \
12456 X(2, (S, R), SINGLE), \
12457 X(2, (R, S), SINGLE), \
12458 X(2, (F, R), SINGLE), \
12459 X(2, (R, F), SINGLE)
12461 #define S2(A,B) NS_##A##B
12462 #define S3(A,B,C) NS_##A##B##C
12463 #define S4(A,B,C,D) NS_##A##B##C##D
12465 #define X(N, L, C) S##N L
12478 enum neon_shape_class
12486 #define X(N, L, C) SC_##C
12488 static enum neon_shape_class neon_shape_class[] =
12506 /* Register widths of above. */
12507 static unsigned neon_shape_el_size[] =
12518 struct neon_shape_info
12521 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12524 #define S2(A,B) { SE_##A, SE_##B }
12525 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12526 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12528 #define X(N, L, C) { N, S##N L }
12530 static struct neon_shape_info neon_shape_tab[] =
12540 /* Bit masks used in type checking given instructions.
12541 'N_EQK' means the type must be the same as (or based on in some way) the key
12542 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12543 set, various other bits can be set as well in order to modify the meaning of
12544 the type constraint. */
12546 enum neon_type_mask
12569 N_KEY = 0x1000000, /* Key element (main type specifier). */
12570 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12571 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12572 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12573 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12574 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12575 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12576 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12577 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12578 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12580 N_MAX_NONSPECIAL = N_F64
12583 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12585 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12586 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12587 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12588 #define N_SUF_32 (N_SU_32 | N_F32)
12589 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12590 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12592 /* Pass this as the first type argument to neon_check_type to ignore types
12594 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12596 /* Select a "shape" for the current instruction (describing register types or
12597 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12598 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12599 function of operand parsing, so this function doesn't need to be called.
12600 Shapes should be listed in order of decreasing length. */
12602 static enum neon_shape
12603 neon_select_shape (enum neon_shape shape, ...)
12606 enum neon_shape first_shape = shape;
12608 /* Fix missing optional operands. FIXME: we don't know at this point how
12609 many arguments we should have, so this makes the assumption that we have
12610 > 1. This is true of all current Neon opcodes, I think, but may not be
12611 true in the future. */
12612 if (!inst.operands[1].present)
12613 inst.operands[1] = inst.operands[0];
12615 va_start (ap, shape);
12617 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12622 for (j = 0; j < neon_shape_tab[shape].els; j++)
12624 if (!inst.operands[j].present)
12630 switch (neon_shape_tab[shape].el[j])
12633 if (!(inst.operands[j].isreg
12634 && inst.operands[j].isvec
12635 && inst.operands[j].issingle
12636 && !inst.operands[j].isquad))
12641 if (!(inst.operands[j].isreg
12642 && inst.operands[j].isvec
12643 && !inst.operands[j].isquad
12644 && !inst.operands[j].issingle))
12649 if (!(inst.operands[j].isreg
12650 && !inst.operands[j].isvec))
12655 if (!(inst.operands[j].isreg
12656 && inst.operands[j].isvec
12657 && inst.operands[j].isquad
12658 && !inst.operands[j].issingle))
12663 if (!(!inst.operands[j].isreg
12664 && !inst.operands[j].isscalar))
12669 if (!(!inst.operands[j].isreg
12670 && inst.operands[j].isscalar))
12680 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12681 /* We've matched all the entries in the shape table, and we don't
12682 have any left over operands which have not been matched. */
12688 if (shape == NS_NULL && first_shape != NS_NULL)
12689 first_error (_("invalid instruction shape"));
12694 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12695 means the Q bit should be set). */
12698 neon_quad (enum neon_shape shape)
12700 return neon_shape_class[shape] == SC_QUAD;
12704 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12707 /* Allow modification to be made to types which are constrained to be
12708 based on the key element, based on bits set alongside N_EQK. */
12709 if ((typebits & N_EQK) != 0)
12711 if ((typebits & N_HLF) != 0)
12713 else if ((typebits & N_DBL) != 0)
12715 if ((typebits & N_SGN) != 0)
12716 *g_type = NT_signed;
12717 else if ((typebits & N_UNS) != 0)
12718 *g_type = NT_unsigned;
12719 else if ((typebits & N_INT) != 0)
12720 *g_type = NT_integer;
12721 else if ((typebits & N_FLT) != 0)
12722 *g_type = NT_float;
12723 else if ((typebits & N_SIZ) != 0)
12724 *g_type = NT_untyped;
12728 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12729 operand type, i.e. the single type specified in a Neon instruction when it
12730 is the only one given. */
12732 static struct neon_type_el
12733 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12735 struct neon_type_el dest = *key;
12737 gas_assert ((thisarg & N_EQK) != 0);
12739 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12744 /* Convert Neon type and size into compact bitmask representation. */
12746 static enum neon_type_mask
12747 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12754 case 8: return N_8;
12755 case 16: return N_16;
12756 case 32: return N_32;
12757 case 64: return N_64;
12765 case 8: return N_I8;
12766 case 16: return N_I16;
12767 case 32: return N_I32;
12768 case 64: return N_I64;
12776 case 16: return N_F16;
12777 case 32: return N_F32;
12778 case 64: return N_F64;
12786 case 8: return N_P8;
12787 case 16: return N_P16;
12795 case 8: return N_S8;
12796 case 16: return N_S16;
12797 case 32: return N_S32;
12798 case 64: return N_S64;
12806 case 8: return N_U8;
12807 case 16: return N_U16;
12808 case 32: return N_U32;
12809 case 64: return N_U64;
12820 /* Convert compact Neon bitmask type representation to a type and size. Only
12821 handles the case where a single bit is set in the mask. */
12824 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12825 enum neon_type_mask mask)
12827 if ((mask & N_EQK) != 0)
12830 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12832 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12834 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12836 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12841 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12843 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12844 *type = NT_unsigned;
12845 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12846 *type = NT_integer;
12847 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12848 *type = NT_untyped;
12849 else if ((mask & (N_P8 | N_P16)) != 0)
12851 else if ((mask & (N_F32 | N_F64)) != 0)
12859 /* Modify a bitmask of allowed types. This is only needed for type
12863 modify_types_allowed (unsigned allowed, unsigned mods)
12866 enum neon_el_type type;
12872 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12874 if (el_type_of_type_chk (&type, &size,
12875 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12877 neon_modify_type_size (mods, &type, &size);
12878 destmask |= type_chk_of_el_type (type, size);
12885 /* Check type and return type classification.
12886 The manual states (paraphrase): If one datatype is given, it indicates the
12888 - the second operand, if there is one
12889 - the operand, if there is no second operand
12890 - the result, if there are no operands.
12891 This isn't quite good enough though, so we use a concept of a "key" datatype
12892 which is set on a per-instruction basis, which is the one which matters when
12893 only one data type is written.
12894 Note: this function has side-effects (e.g. filling in missing operands). All
12895 Neon instructions should call it before performing bit encoding. */
12897 static struct neon_type_el
12898 neon_check_type (unsigned els, enum neon_shape ns, ...)
12901 unsigned i, pass, key_el = 0;
12902 unsigned types[NEON_MAX_TYPE_ELS];
12903 enum neon_el_type k_type = NT_invtype;
12904 unsigned k_size = -1u;
12905 struct neon_type_el badtype = {NT_invtype, -1};
12906 unsigned key_allowed = 0;
12908 /* Optional registers in Neon instructions are always (not) in operand 1.
12909 Fill in the missing operand here, if it was omitted. */
12910 if (els > 1 && !inst.operands[1].present)
12911 inst.operands[1] = inst.operands[0];
12913 /* Suck up all the varargs. */
12915 for (i = 0; i < els; i++)
12917 unsigned thisarg = va_arg (ap, unsigned);
12918 if (thisarg == N_IGNORE_TYPE)
12923 types[i] = thisarg;
12924 if ((thisarg & N_KEY) != 0)
12929 if (inst.vectype.elems > 0)
12930 for (i = 0; i < els; i++)
12931 if (inst.operands[i].vectype.type != NT_invtype)
12933 first_error (_("types specified in both the mnemonic and operands"));
12937 /* Duplicate inst.vectype elements here as necessary.
12938 FIXME: No idea if this is exactly the same as the ARM assembler,
12939 particularly when an insn takes one register and one non-register
12941 if (inst.vectype.elems == 1 && els > 1)
12944 inst.vectype.elems = els;
12945 inst.vectype.el[key_el] = inst.vectype.el[0];
12946 for (j = 0; j < els; j++)
12948 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12951 else if (inst.vectype.elems == 0 && els > 0)
12954 /* No types were given after the mnemonic, so look for types specified
12955 after each operand. We allow some flexibility here; as long as the
12956 "key" operand has a type, we can infer the others. */
12957 for (j = 0; j < els; j++)
12958 if (inst.operands[j].vectype.type != NT_invtype)
12959 inst.vectype.el[j] = inst.operands[j].vectype;
12961 if (inst.operands[key_el].vectype.type != NT_invtype)
12963 for (j = 0; j < els; j++)
12964 if (inst.operands[j].vectype.type == NT_invtype)
12965 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12970 first_error (_("operand types can't be inferred"));
12974 else if (inst.vectype.elems != els)
12976 first_error (_("type specifier has the wrong number of parts"));
12980 for (pass = 0; pass < 2; pass++)
12982 for (i = 0; i < els; i++)
12984 unsigned thisarg = types[i];
12985 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12986 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12987 enum neon_el_type g_type = inst.vectype.el[i].type;
12988 unsigned g_size = inst.vectype.el[i].size;
12990 /* Decay more-specific signed & unsigned types to sign-insensitive
12991 integer types if sign-specific variants are unavailable. */
12992 if ((g_type == NT_signed || g_type == NT_unsigned)
12993 && (types_allowed & N_SU_ALL) == 0)
12994 g_type = NT_integer;
12996 /* If only untyped args are allowed, decay any more specific types to
12997 them. Some instructions only care about signs for some element
12998 sizes, so handle that properly. */
12999 if ((g_size == 8 && (types_allowed & N_8) != 0)
13000 || (g_size == 16 && (types_allowed & N_16) != 0)
13001 || (g_size == 32 && (types_allowed & N_32) != 0)
13002 || (g_size == 64 && (types_allowed & N_64) != 0))
13003 g_type = NT_untyped;
13007 if ((thisarg & N_KEY) != 0)
13011 key_allowed = thisarg & ~N_KEY;
13016 if ((thisarg & N_VFP) != 0)
13018 enum neon_shape_el regshape;
13019 unsigned regwidth, match;
13021 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13024 first_error (_("invalid instruction shape"));
13027 regshape = neon_shape_tab[ns].el[i];
13028 regwidth = neon_shape_el_size[regshape];
13030 /* In VFP mode, operands must match register widths. If we
13031 have a key operand, use its width, else use the width of
13032 the current operand. */
13038 if (regwidth != match)
13040 first_error (_("operand size must match register width"));
13045 if ((thisarg & N_EQK) == 0)
13047 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13049 if ((given_type & types_allowed) == 0)
13051 first_error (_("bad type in Neon instruction"));
13057 enum neon_el_type mod_k_type = k_type;
13058 unsigned mod_k_size = k_size;
13059 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13060 if (g_type != mod_k_type || g_size != mod_k_size)
13062 first_error (_("inconsistent types in Neon instruction"));
13070 return inst.vectype.el[key_el];
13073 /* Neon-style VFP instruction forwarding. */
13075 /* Thumb VFP instructions have 0xE in the condition field. */
13078 do_vfp_cond_or_thumb (void)
13083 inst.instruction |= 0xe0000000;
13085 inst.instruction |= inst.cond << 28;
13088 /* Look up and encode a simple mnemonic, for use as a helper function for the
13089 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13090 etc. It is assumed that operand parsing has already been done, and that the
13091 operands are in the form expected by the given opcode (this isn't necessarily
13092 the same as the form in which they were parsed, hence some massaging must
13093 take place before this function is called).
13094 Checks current arch version against that in the looked-up opcode. */
13097 do_vfp_nsyn_opcode (const char *opname)
13099 const struct asm_opcode *opcode;
13101 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13106 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13107 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13114 inst.instruction = opcode->tvalue;
13115 opcode->tencode ();
13119 inst.instruction = (inst.cond << 28) | opcode->avalue;
13120 opcode->aencode ();
13125 do_vfp_nsyn_add_sub (enum neon_shape rs)
13127 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13132 do_vfp_nsyn_opcode ("fadds");
13134 do_vfp_nsyn_opcode ("fsubs");
13139 do_vfp_nsyn_opcode ("faddd");
13141 do_vfp_nsyn_opcode ("fsubd");
13145 /* Check operand types to see if this is a VFP instruction, and if so call
13149 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13151 enum neon_shape rs;
13152 struct neon_type_el et;
13157 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13158 et = neon_check_type (2, rs,
13159 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13163 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13164 et = neon_check_type (3, rs,
13165 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13172 if (et.type != NT_invtype)
13183 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13185 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13190 do_vfp_nsyn_opcode ("fmacs");
13192 do_vfp_nsyn_opcode ("fnmacs");
13197 do_vfp_nsyn_opcode ("fmacd");
13199 do_vfp_nsyn_opcode ("fnmacd");
13204 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13206 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13211 do_vfp_nsyn_opcode ("ffmas");
13213 do_vfp_nsyn_opcode ("ffnmas");
13218 do_vfp_nsyn_opcode ("ffmad");
13220 do_vfp_nsyn_opcode ("ffnmad");
13225 do_vfp_nsyn_mul (enum neon_shape rs)
13228 do_vfp_nsyn_opcode ("fmuls");
13230 do_vfp_nsyn_opcode ("fmuld");
13234 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13236 int is_neg = (inst.instruction & 0x80) != 0;
13237 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13242 do_vfp_nsyn_opcode ("fnegs");
13244 do_vfp_nsyn_opcode ("fabss");
13249 do_vfp_nsyn_opcode ("fnegd");
13251 do_vfp_nsyn_opcode ("fabsd");
13255 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13256 insns belong to Neon, and are handled elsewhere. */
13259 do_vfp_nsyn_ldm_stm (int is_dbmode)
13261 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13265 do_vfp_nsyn_opcode ("fldmdbs");
13267 do_vfp_nsyn_opcode ("fldmias");
13272 do_vfp_nsyn_opcode ("fstmdbs");
13274 do_vfp_nsyn_opcode ("fstmias");
13279 do_vfp_nsyn_sqrt (void)
13281 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13282 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13285 do_vfp_nsyn_opcode ("fsqrts");
13287 do_vfp_nsyn_opcode ("fsqrtd");
13291 do_vfp_nsyn_div (void)
13293 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13294 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13295 N_F32 | N_F64 | N_KEY | N_VFP);
13298 do_vfp_nsyn_opcode ("fdivs");
13300 do_vfp_nsyn_opcode ("fdivd");
13304 do_vfp_nsyn_nmul (void)
13306 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13307 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13308 N_F32 | N_F64 | N_KEY | N_VFP);
13312 NEON_ENCODE (SINGLE, inst);
13313 do_vfp_sp_dyadic ();
13317 NEON_ENCODE (DOUBLE, inst);
13318 do_vfp_dp_rd_rn_rm ();
13320 do_vfp_cond_or_thumb ();
13324 do_vfp_nsyn_cmp (void)
13326 if (inst.operands[1].isreg)
13328 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13329 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13333 NEON_ENCODE (SINGLE, inst);
13334 do_vfp_sp_monadic ();
13338 NEON_ENCODE (DOUBLE, inst);
13339 do_vfp_dp_rd_rm ();
13344 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13345 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13347 switch (inst.instruction & 0x0fffffff)
13350 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13353 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13361 NEON_ENCODE (SINGLE, inst);
13362 do_vfp_sp_compare_z ();
13366 NEON_ENCODE (DOUBLE, inst);
13370 do_vfp_cond_or_thumb ();
13374 nsyn_insert_sp (void)
13376 inst.operands[1] = inst.operands[0];
13377 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13378 inst.operands[0].reg = REG_SP;
13379 inst.operands[0].isreg = 1;
13380 inst.operands[0].writeback = 1;
13381 inst.operands[0].present = 1;
13385 do_vfp_nsyn_push (void)
13388 if (inst.operands[1].issingle)
13389 do_vfp_nsyn_opcode ("fstmdbs");
13391 do_vfp_nsyn_opcode ("fstmdbd");
13395 do_vfp_nsyn_pop (void)
13398 if (inst.operands[1].issingle)
13399 do_vfp_nsyn_opcode ("fldmias");
13401 do_vfp_nsyn_opcode ("fldmiad");
13404 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13405 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13408 neon_dp_fixup (struct arm_it* insn)
13410 unsigned int i = insn->instruction;
13415 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13426 insn->instruction = i;
13429 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13433 neon_logbits (unsigned x)
13435 return ffs (x) - 4;
13438 #define LOW4(R) ((R) & 0xf)
13439 #define HI1(R) (((R) >> 4) & 1)
13441 /* Encode insns with bit pattern:
13443 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13444 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13446 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13447 different meaning for some instruction. */
13450 neon_three_same (int isquad, int ubit, int size)
13452 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13453 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13454 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13455 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13456 inst.instruction |= LOW4 (inst.operands[2].reg);
13457 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13458 inst.instruction |= (isquad != 0) << 6;
13459 inst.instruction |= (ubit != 0) << 24;
13461 inst.instruction |= neon_logbits (size) << 20;
13463 neon_dp_fixup (&inst);
13466 /* Encode instructions of the form:
13468 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13469 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13471 Don't write size if SIZE == -1. */
13474 neon_two_same (int qbit, int ubit, int size)
13476 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13477 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13478 inst.instruction |= LOW4 (inst.operands[1].reg);
13479 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13480 inst.instruction |= (qbit != 0) << 6;
13481 inst.instruction |= (ubit != 0) << 24;
13484 inst.instruction |= neon_logbits (size) << 18;
13486 neon_dp_fixup (&inst);
13489 /* Neon instruction encoders, in approximate order of appearance. */
13492 do_neon_dyadic_i_su (void)
13494 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13495 struct neon_type_el et = neon_check_type (3, rs,
13496 N_EQK, N_EQK, N_SU_32 | N_KEY);
13497 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13501 do_neon_dyadic_i64_su (void)
13503 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13504 struct neon_type_el et = neon_check_type (3, rs,
13505 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13506 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13510 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13513 unsigned size = et.size >> 3;
13514 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13515 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13516 inst.instruction |= LOW4 (inst.operands[1].reg);
13517 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13518 inst.instruction |= (isquad != 0) << 6;
13519 inst.instruction |= immbits << 16;
13520 inst.instruction |= (size >> 3) << 7;
13521 inst.instruction |= (size & 0x7) << 19;
13523 inst.instruction |= (uval != 0) << 24;
13525 neon_dp_fixup (&inst);
13529 do_neon_shl_imm (void)
13531 if (!inst.operands[2].isreg)
13533 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13534 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13535 NEON_ENCODE (IMMED, inst);
13536 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13540 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13541 struct neon_type_el et = neon_check_type (3, rs,
13542 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13545 /* VSHL/VQSHL 3-register variants have syntax such as:
13547 whereas other 3-register operations encoded by neon_three_same have
13550 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13552 tmp = inst.operands[2].reg;
13553 inst.operands[2].reg = inst.operands[1].reg;
13554 inst.operands[1].reg = tmp;
13555 NEON_ENCODE (INTEGER, inst);
13556 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13561 do_neon_qshl_imm (void)
13563 if (!inst.operands[2].isreg)
13565 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13566 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13568 NEON_ENCODE (IMMED, inst);
13569 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13570 inst.operands[2].imm);
13574 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13575 struct neon_type_el et = neon_check_type (3, rs,
13576 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13579 /* See note in do_neon_shl_imm. */
13580 tmp = inst.operands[2].reg;
13581 inst.operands[2].reg = inst.operands[1].reg;
13582 inst.operands[1].reg = tmp;
13583 NEON_ENCODE (INTEGER, inst);
13584 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13589 do_neon_rshl (void)
13591 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13592 struct neon_type_el et = neon_check_type (3, rs,
13593 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13596 tmp = inst.operands[2].reg;
13597 inst.operands[2].reg = inst.operands[1].reg;
13598 inst.operands[1].reg = tmp;
13599 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13603 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13605 /* Handle .I8 pseudo-instructions. */
13608 /* Unfortunately, this will make everything apart from zero out-of-range.
13609 FIXME is this the intended semantics? There doesn't seem much point in
13610 accepting .I8 if so. */
13611 immediate |= immediate << 8;
13617 if (immediate == (immediate & 0x000000ff))
13619 *immbits = immediate;
13622 else if (immediate == (immediate & 0x0000ff00))
13624 *immbits = immediate >> 8;
13627 else if (immediate == (immediate & 0x00ff0000))
13629 *immbits = immediate >> 16;
13632 else if (immediate == (immediate & 0xff000000))
13634 *immbits = immediate >> 24;
13637 if ((immediate & 0xffff) != (immediate >> 16))
13638 goto bad_immediate;
13639 immediate &= 0xffff;
13642 if (immediate == (immediate & 0x000000ff))
13644 *immbits = immediate;
13647 else if (immediate == (immediate & 0x0000ff00))
13649 *immbits = immediate >> 8;
13654 first_error (_("immediate value out of range"));
13658 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13662 neon_bits_same_in_bytes (unsigned imm)
13664 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13665 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13666 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13667 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13670 /* For immediate of above form, return 0bABCD. */
13673 neon_squash_bits (unsigned imm)
13675 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13676 | ((imm & 0x01000000) >> 21);
13679 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13682 neon_qfloat_bits (unsigned imm)
13684 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13687 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13688 the instruction. *OP is passed as the initial value of the op field, and
13689 may be set to a different value depending on the constant (i.e.
13690 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13691 MVN). If the immediate looks like a repeated pattern then also
13692 try smaller element sizes. */
13695 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13696 unsigned *immbits, int *op, int size,
13697 enum neon_el_type type)
13699 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13701 if (type == NT_float && !float_p)
13704 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13706 if (size != 32 || *op == 1)
13708 *immbits = neon_qfloat_bits (immlo);
13714 if (neon_bits_same_in_bytes (immhi)
13715 && neon_bits_same_in_bytes (immlo))
13719 *immbits = (neon_squash_bits (immhi) << 4)
13720 | neon_squash_bits (immlo);
13725 if (immhi != immlo)
13731 if (immlo == (immlo & 0x000000ff))
13736 else if (immlo == (immlo & 0x0000ff00))
13738 *immbits = immlo >> 8;
13741 else if (immlo == (immlo & 0x00ff0000))
13743 *immbits = immlo >> 16;
13746 else if (immlo == (immlo & 0xff000000))
13748 *immbits = immlo >> 24;
13751 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13753 *immbits = (immlo >> 8) & 0xff;
13756 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13758 *immbits = (immlo >> 16) & 0xff;
13762 if ((immlo & 0xffff) != (immlo >> 16))
13769 if (immlo == (immlo & 0x000000ff))
13774 else if (immlo == (immlo & 0x0000ff00))
13776 *immbits = immlo >> 8;
13780 if ((immlo & 0xff) != (immlo >> 8))
13785 if (immlo == (immlo & 0x000000ff))
13787 /* Don't allow MVN with 8-bit immediate. */
13797 /* Write immediate bits [7:0] to the following locations:
13799 |28/24|23 19|18 16|15 4|3 0|
13800 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13802 This function is used by VMOV/VMVN/VORR/VBIC. */
13805 neon_write_immbits (unsigned immbits)
13807 inst.instruction |= immbits & 0xf;
13808 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13809 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13812 /* Invert low-order SIZE bits of XHI:XLO. */
13815 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13817 unsigned immlo = xlo ? *xlo : 0;
13818 unsigned immhi = xhi ? *xhi : 0;
13823 immlo = (~immlo) & 0xff;
13827 immlo = (~immlo) & 0xffff;
13831 immhi = (~immhi) & 0xffffffff;
13832 /* fall through. */
13835 immlo = (~immlo) & 0xffffffff;
13850 do_neon_logic (void)
13852 if (inst.operands[2].present && inst.operands[2].isreg)
13854 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13855 neon_check_type (3, rs, N_IGNORE_TYPE);
13856 /* U bit and size field were set as part of the bitmask. */
13857 NEON_ENCODE (INTEGER, inst);
13858 neon_three_same (neon_quad (rs), 0, -1);
13862 const int three_ops_form = (inst.operands[2].present
13863 && !inst.operands[2].isreg);
13864 const int immoperand = (three_ops_form ? 2 : 1);
13865 enum neon_shape rs = (three_ops_form
13866 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13867 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13868 struct neon_type_el et = neon_check_type (2, rs,
13869 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13870 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13874 if (et.type == NT_invtype)
13877 if (three_ops_form)
13878 constraint (inst.operands[0].reg != inst.operands[1].reg,
13879 _("first and second operands shall be the same register"));
13881 NEON_ENCODE (IMMED, inst);
13883 immbits = inst.operands[immoperand].imm;
13886 /* .i64 is a pseudo-op, so the immediate must be a repeating
13888 if (immbits != (inst.operands[immoperand].regisimm ?
13889 inst.operands[immoperand].reg : 0))
13891 /* Set immbits to an invalid constant. */
13892 immbits = 0xdeadbeef;
13899 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13903 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13907 /* Pseudo-instruction for VBIC. */
13908 neon_invert_size (&immbits, 0, et.size);
13909 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13913 /* Pseudo-instruction for VORR. */
13914 neon_invert_size (&immbits, 0, et.size);
13915 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13925 inst.instruction |= neon_quad (rs) << 6;
13926 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13927 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13928 inst.instruction |= cmode << 8;
13929 neon_write_immbits (immbits);
13931 neon_dp_fixup (&inst);
13936 do_neon_bitfield (void)
13938 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13939 neon_check_type (3, rs, N_IGNORE_TYPE);
13940 neon_three_same (neon_quad (rs), 0, -1);
13944 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13947 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13948 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13950 if (et.type == NT_float)
13952 NEON_ENCODE (FLOAT, inst);
13953 neon_three_same (neon_quad (rs), 0, -1);
13957 NEON_ENCODE (INTEGER, inst);
13958 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13963 do_neon_dyadic_if_su (void)
13965 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13969 do_neon_dyadic_if_su_d (void)
13971 /* This version only allow D registers, but that constraint is enforced during
13972 operand parsing so we don't need to do anything extra here. */
13973 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13977 do_neon_dyadic_if_i_d (void)
13979 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13980 affected if we specify unsigned args. */
13981 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13984 enum vfp_or_neon_is_neon_bits
13987 NEON_CHECK_ARCH = 2,
13988 NEON_CHECK_ARCH8 = 4
13991 /* Call this function if an instruction which may have belonged to the VFP or
13992 Neon instruction sets, but turned out to be a Neon instruction (due to the
13993 operand types involved, etc.). We have to check and/or fix-up a couple of
13996 - Make sure the user hasn't attempted to make a Neon instruction
13998 - Alter the value in the condition code field if necessary.
13999 - Make sure that the arch supports Neon instructions.
14001 Which of these operations take place depends on bits from enum
14002 vfp_or_neon_is_neon_bits.
14004 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14005 current instruction's condition is COND_ALWAYS, the condition field is
14006 changed to inst.uncond_value. This is necessary because instructions shared
14007 between VFP and Neon may be conditional for the VFP variants only, and the
14008 unconditional Neon version must have, e.g., 0xF in the condition field. */
14011 vfp_or_neon_is_neon (unsigned check)
14013 /* Conditions are always legal in Thumb mode (IT blocks). */
14014 if (!thumb_mode && (check & NEON_CHECK_CC))
14016 if (inst.cond != COND_ALWAYS)
14018 first_error (_(BAD_COND));
14021 if (inst.uncond_value != -1)
14022 inst.instruction |= inst.uncond_value << 28;
14025 if ((check & NEON_CHECK_ARCH)
14026 && !mark_feature_used (&fpu_neon_ext_v1))
14028 first_error (_(BAD_FPU));
14032 if ((check & NEON_CHECK_ARCH8)
14033 && !mark_feature_used (&fpu_neon_ext_armv8))
14035 first_error (_(BAD_FPU));
14043 do_neon_addsub_if_i (void)
14045 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14048 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14051 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14052 affected if we specify unsigned args. */
14053 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14056 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14058 V<op> A,B (A is operand 0, B is operand 2)
14063 so handle that case specially. */
14066 neon_exchange_operands (void)
14068 void *scratch = alloca (sizeof (inst.operands[0]));
14069 if (inst.operands[1].present)
14071 /* Swap operands[1] and operands[2]. */
14072 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14073 inst.operands[1] = inst.operands[2];
14074 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14078 inst.operands[1] = inst.operands[2];
14079 inst.operands[2] = inst.operands[0];
14084 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14086 if (inst.operands[2].isreg)
14089 neon_exchange_operands ();
14090 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14094 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14095 struct neon_type_el et = neon_check_type (2, rs,
14096 N_EQK | N_SIZ, immtypes | N_KEY);
14098 NEON_ENCODE (IMMED, inst);
14099 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14100 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14101 inst.instruction |= LOW4 (inst.operands[1].reg);
14102 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14103 inst.instruction |= neon_quad (rs) << 6;
14104 inst.instruction |= (et.type == NT_float) << 10;
14105 inst.instruction |= neon_logbits (et.size) << 18;
14107 neon_dp_fixup (&inst);
14114 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14118 do_neon_cmp_inv (void)
14120 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14126 neon_compare (N_IF_32, N_IF_32, FALSE);
14129 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14130 scalars, which are encoded in 5 bits, M : Rm.
14131 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14132 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14136 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14138 unsigned regno = NEON_SCALAR_REG (scalar);
14139 unsigned elno = NEON_SCALAR_INDEX (scalar);
14144 if (regno > 7 || elno > 3)
14146 return regno | (elno << 3);
14149 if (regno > 15 || elno > 1)
14151 return regno | (elno << 4);
14155 first_error (_("scalar out of range for multiply instruction"));
14161 /* Encode multiply / multiply-accumulate scalar instructions. */
14164 neon_mul_mac (struct neon_type_el et, int ubit)
14168 /* Give a more helpful error message if we have an invalid type. */
14169 if (et.type == NT_invtype)
14172 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14173 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14174 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14175 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14176 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14177 inst.instruction |= LOW4 (scalar);
14178 inst.instruction |= HI1 (scalar) << 5;
14179 inst.instruction |= (et.type == NT_float) << 8;
14180 inst.instruction |= neon_logbits (et.size) << 20;
14181 inst.instruction |= (ubit != 0) << 24;
14183 neon_dp_fixup (&inst);
14187 do_neon_mac_maybe_scalar (void)
14189 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14192 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14195 if (inst.operands[2].isscalar)
14197 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14198 struct neon_type_el et = neon_check_type (3, rs,
14199 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14200 NEON_ENCODE (SCALAR, inst);
14201 neon_mul_mac (et, neon_quad (rs));
14205 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14206 affected if we specify unsigned args. */
14207 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14212 do_neon_fmac (void)
14214 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14217 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14220 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14226 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14227 struct neon_type_el et = neon_check_type (3, rs,
14228 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14229 neon_three_same (neon_quad (rs), 0, et.size);
14232 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14233 same types as the MAC equivalents. The polynomial type for this instruction
14234 is encoded the same as the integer type. */
14239 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14242 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14245 if (inst.operands[2].isscalar)
14246 do_neon_mac_maybe_scalar ();
14248 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14252 do_neon_qdmulh (void)
14254 if (inst.operands[2].isscalar)
14256 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14257 struct neon_type_el et = neon_check_type (3, rs,
14258 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14259 NEON_ENCODE (SCALAR, inst);
14260 neon_mul_mac (et, neon_quad (rs));
14264 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14265 struct neon_type_el et = neon_check_type (3, rs,
14266 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14267 NEON_ENCODE (INTEGER, inst);
14268 /* The U bit (rounding) comes from bit mask. */
14269 neon_three_same (neon_quad (rs), 0, et.size);
14274 do_neon_fcmp_absolute (void)
14276 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14277 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14278 /* Size field comes from bit mask. */
14279 neon_three_same (neon_quad (rs), 1, -1);
14283 do_neon_fcmp_absolute_inv (void)
14285 neon_exchange_operands ();
14286 do_neon_fcmp_absolute ();
14290 do_neon_step (void)
14292 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14293 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14294 neon_three_same (neon_quad (rs), 0, -1);
14298 do_neon_abs_neg (void)
14300 enum neon_shape rs;
14301 struct neon_type_el et;
14303 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14306 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14309 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14310 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14312 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14313 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14314 inst.instruction |= LOW4 (inst.operands[1].reg);
14315 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14316 inst.instruction |= neon_quad (rs) << 6;
14317 inst.instruction |= (et.type == NT_float) << 10;
14318 inst.instruction |= neon_logbits (et.size) << 18;
14320 neon_dp_fixup (&inst);
14326 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14327 struct neon_type_el et = neon_check_type (2, rs,
14328 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14329 int imm = inst.operands[2].imm;
14330 constraint (imm < 0 || (unsigned)imm >= et.size,
14331 _("immediate out of range for insert"));
14332 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14338 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14339 struct neon_type_el et = neon_check_type (2, rs,
14340 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14341 int imm = inst.operands[2].imm;
14342 constraint (imm < 1 || (unsigned)imm > et.size,
14343 _("immediate out of range for insert"));
14344 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14348 do_neon_qshlu_imm (void)
14350 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14351 struct neon_type_el et = neon_check_type (2, rs,
14352 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14353 int imm = inst.operands[2].imm;
14354 constraint (imm < 0 || (unsigned)imm >= et.size,
14355 _("immediate out of range for shift"));
14356 /* Only encodes the 'U present' variant of the instruction.
14357 In this case, signed types have OP (bit 8) set to 0.
14358 Unsigned types have OP set to 1. */
14359 inst.instruction |= (et.type == NT_unsigned) << 8;
14360 /* The rest of the bits are the same as other immediate shifts. */
14361 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14365 do_neon_qmovn (void)
14367 struct neon_type_el et = neon_check_type (2, NS_DQ,
14368 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14369 /* Saturating move where operands can be signed or unsigned, and the
14370 destination has the same signedness. */
14371 NEON_ENCODE (INTEGER, inst);
14372 if (et.type == NT_unsigned)
14373 inst.instruction |= 0xc0;
14375 inst.instruction |= 0x80;
14376 neon_two_same (0, 1, et.size / 2);
14380 do_neon_qmovun (void)
14382 struct neon_type_el et = neon_check_type (2, NS_DQ,
14383 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14384 /* Saturating move with unsigned results. Operands must be signed. */
14385 NEON_ENCODE (INTEGER, inst);
14386 neon_two_same (0, 1, et.size / 2);
14390 do_neon_rshift_sat_narrow (void)
14392 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14393 or unsigned. If operands are unsigned, results must also be unsigned. */
14394 struct neon_type_el et = neon_check_type (2, NS_DQI,
14395 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14396 int imm = inst.operands[2].imm;
14397 /* This gets the bounds check, size encoding and immediate bits calculation
14401 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14402 VQMOVN.I<size> <Dd>, <Qm>. */
14405 inst.operands[2].present = 0;
14406 inst.instruction = N_MNEM_vqmovn;
14411 constraint (imm < 1 || (unsigned)imm > et.size,
14412 _("immediate out of range"));
14413 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14417 do_neon_rshift_sat_narrow_u (void)
14419 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14420 or unsigned. If operands are unsigned, results must also be unsigned. */
14421 struct neon_type_el et = neon_check_type (2, NS_DQI,
14422 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14423 int imm = inst.operands[2].imm;
14424 /* This gets the bounds check, size encoding and immediate bits calculation
14428 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14429 VQMOVUN.I<size> <Dd>, <Qm>. */
14432 inst.operands[2].present = 0;
14433 inst.instruction = N_MNEM_vqmovun;
14438 constraint (imm < 1 || (unsigned)imm > et.size,
14439 _("immediate out of range"));
14440 /* FIXME: The manual is kind of unclear about what value U should have in
14441 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14443 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14447 do_neon_movn (void)
14449 struct neon_type_el et = neon_check_type (2, NS_DQ,
14450 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14451 NEON_ENCODE (INTEGER, inst);
14452 neon_two_same (0, 1, et.size / 2);
14456 do_neon_rshift_narrow (void)
14458 struct neon_type_el et = neon_check_type (2, NS_DQI,
14459 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14460 int imm = inst.operands[2].imm;
14461 /* This gets the bounds check, size encoding and immediate bits calculation
14465 /* If immediate is zero then we are a pseudo-instruction for
14466 VMOVN.I<size> <Dd>, <Qm> */
14469 inst.operands[2].present = 0;
14470 inst.instruction = N_MNEM_vmovn;
14475 constraint (imm < 1 || (unsigned)imm > et.size,
14476 _("immediate out of range for narrowing operation"));
14477 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14481 do_neon_shll (void)
14483 /* FIXME: Type checking when lengthening. */
14484 struct neon_type_el et = neon_check_type (2, NS_QDI,
14485 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14486 unsigned imm = inst.operands[2].imm;
14488 if (imm == et.size)
14490 /* Maximum shift variant. */
14491 NEON_ENCODE (INTEGER, inst);
14492 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14493 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14494 inst.instruction |= LOW4 (inst.operands[1].reg);
14495 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14496 inst.instruction |= neon_logbits (et.size) << 18;
14498 neon_dp_fixup (&inst);
14502 /* A more-specific type check for non-max versions. */
14503 et = neon_check_type (2, NS_QDI,
14504 N_EQK | N_DBL, N_SU_32 | N_KEY);
14505 NEON_ENCODE (IMMED, inst);
14506 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14510 /* Check the various types for the VCVT instruction, and return which version
14511 the current instruction is. */
14513 #define CVT_FLAVOUR_VAR \
14514 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14515 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14516 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14517 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14518 /* Half-precision conversions. */ \
14519 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14520 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14521 /* VFP instructions. */ \
14522 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14523 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14524 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14525 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14526 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14527 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14528 /* VFP instructions with bitshift. */ \
14529 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14530 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14531 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14532 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14533 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14534 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14535 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14536 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14538 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14539 neon_cvt_flavour_##C,
14541 /* The different types of conversions we can do. */
14542 enum neon_cvt_flavour
14545 neon_cvt_flavour_invalid,
14546 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14551 static enum neon_cvt_flavour
14552 get_neon_cvt_flavour (enum neon_shape rs)
14554 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14555 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14556 if (et.type != NT_invtype) \
14558 inst.error = NULL; \
14559 return (neon_cvt_flavour_##C); \
14562 struct neon_type_el et;
14563 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14564 || rs == NS_FF) ? N_VFP : 0;
14565 /* The instruction versions which take an immediate take one register
14566 argument, which is extended to the width of the full register. Thus the
14567 "source" and "destination" registers must have the same width. Hack that
14568 here by making the size equal to the key (wider, in this case) operand. */
14569 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14573 return neon_cvt_flavour_invalid;
14577 /* Neon-syntax VFP conversions. */
14580 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14582 const char *opname = 0;
14584 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14586 /* Conversions with immediate bitshift. */
14587 const char *enc[] =
14589 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14595 if (flavour < (int) ARRAY_SIZE (enc))
14597 opname = enc[flavour];
14598 constraint (inst.operands[0].reg != inst.operands[1].reg,
14599 _("operands 0 and 1 must be the same register"));
14600 inst.operands[1] = inst.operands[2];
14601 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14606 /* Conversions without bitshift. */
14607 const char *enc[] =
14609 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14615 if (flavour < (int) ARRAY_SIZE (enc))
14616 opname = enc[flavour];
14620 do_vfp_nsyn_opcode (opname);
14624 do_vfp_nsyn_cvtz (void)
14626 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14627 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14628 const char *enc[] =
14630 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14636 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14637 do_vfp_nsyn_opcode (enc[flavour]);
14641 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14643 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14644 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14645 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14647 /* PR11109: Handle round-to-zero for VCVT conversions. */
14649 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14650 && (flavour == neon_cvt_flavour_s32_f32
14651 || flavour == neon_cvt_flavour_u32_f32
14652 || flavour == neon_cvt_flavour_s32_f64
14653 || flavour == neon_cvt_flavour_u32_f64)
14654 && (rs == NS_FD || rs == NS_FF))
14656 do_vfp_nsyn_cvtz ();
14660 /* VFP rather than Neon conversions. */
14661 if (flavour >= neon_cvt_flavour_first_fp)
14663 do_vfp_nsyn_cvt (rs, flavour);
14673 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14675 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14678 /* Fixed-point conversion with #0 immediate is encoded as an
14679 integer conversion. */
14680 if (inst.operands[2].present && inst.operands[2].imm == 0)
14682 immbits = 32 - inst.operands[2].imm;
14683 NEON_ENCODE (IMMED, inst);
14684 if (flavour != neon_cvt_flavour_invalid)
14685 inst.instruction |= enctab[flavour];
14686 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14687 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14688 inst.instruction |= LOW4 (inst.operands[1].reg);
14689 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14690 inst.instruction |= neon_quad (rs) << 6;
14691 inst.instruction |= 1 << 21;
14692 inst.instruction |= immbits << 16;
14694 neon_dp_fixup (&inst);
14702 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14704 NEON_ENCODE (INTEGER, inst);
14706 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14709 if (flavour != neon_cvt_flavour_invalid)
14710 inst.instruction |= enctab[flavour];
14712 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14713 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14714 inst.instruction |= LOW4 (inst.operands[1].reg);
14715 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14716 inst.instruction |= neon_quad (rs) << 6;
14717 inst.instruction |= 2 << 18;
14719 neon_dp_fixup (&inst);
14723 /* Half-precision conversions for Advanced SIMD -- neon. */
14728 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14730 as_bad (_("operand size must match register width"));
14735 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14737 as_bad (_("operand size must match register width"));
14742 inst.instruction = 0x3b60600;
14744 inst.instruction = 0x3b60700;
14746 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14747 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14748 inst.instruction |= LOW4 (inst.operands[1].reg);
14749 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14750 neon_dp_fixup (&inst);
14754 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14755 do_vfp_nsyn_cvt (rs, flavour);
14760 do_neon_cvtr (void)
14762 do_neon_cvt_1 (FALSE);
14768 do_neon_cvt_1 (TRUE);
14772 do_neon_cvtb (void)
14774 inst.instruction = 0xeb20a40;
14776 /* The sizes are attached to the mnemonic. */
14777 if (inst.vectype.el[0].type != NT_invtype
14778 && inst.vectype.el[0].size == 16)
14779 inst.instruction |= 0x00010000;
14781 /* Programmer's syntax: the sizes are attached to the operands. */
14782 else if (inst.operands[0].vectype.type != NT_invtype
14783 && inst.operands[0].vectype.size == 16)
14784 inst.instruction |= 0x00010000;
14786 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14787 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14788 do_vfp_cond_or_thumb ();
14793 do_neon_cvtt (void)
14796 inst.instruction |= 0x80;
14800 neon_move_immediate (void)
14802 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14803 struct neon_type_el et = neon_check_type (2, rs,
14804 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14805 unsigned immlo, immhi = 0, immbits;
14806 int op, cmode, float_p;
14808 constraint (et.type == NT_invtype,
14809 _("operand size must be specified for immediate VMOV"));
14811 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14812 op = (inst.instruction & (1 << 5)) != 0;
14814 immlo = inst.operands[1].imm;
14815 if (inst.operands[1].regisimm)
14816 immhi = inst.operands[1].reg;
14818 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14819 _("immediate has bits set outside the operand size"));
14821 float_p = inst.operands[1].immisfloat;
14823 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14824 et.size, et.type)) == FAIL)
14826 /* Invert relevant bits only. */
14827 neon_invert_size (&immlo, &immhi, et.size);
14828 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14829 with one or the other; those cases are caught by
14830 neon_cmode_for_move_imm. */
14832 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14833 &op, et.size, et.type)) == FAIL)
14835 first_error (_("immediate out of range"));
14840 inst.instruction &= ~(1 << 5);
14841 inst.instruction |= op << 5;
14843 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14844 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14845 inst.instruction |= neon_quad (rs) << 6;
14846 inst.instruction |= cmode << 8;
14848 neon_write_immbits (immbits);
14854 if (inst.operands[1].isreg)
14856 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14858 NEON_ENCODE (INTEGER, inst);
14859 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14860 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14861 inst.instruction |= LOW4 (inst.operands[1].reg);
14862 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14863 inst.instruction |= neon_quad (rs) << 6;
14867 NEON_ENCODE (IMMED, inst);
14868 neon_move_immediate ();
14871 neon_dp_fixup (&inst);
14874 /* Encode instructions of form:
14876 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14877 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14880 neon_mixed_length (struct neon_type_el et, unsigned size)
14882 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14883 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14884 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14885 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14886 inst.instruction |= LOW4 (inst.operands[2].reg);
14887 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14888 inst.instruction |= (et.type == NT_unsigned) << 24;
14889 inst.instruction |= neon_logbits (size) << 20;
14891 neon_dp_fixup (&inst);
14895 do_neon_dyadic_long (void)
14897 /* FIXME: Type checking for lengthening op. */
14898 struct neon_type_el et = neon_check_type (3, NS_QDD,
14899 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14900 neon_mixed_length (et, et.size);
14904 do_neon_abal (void)
14906 struct neon_type_el et = neon_check_type (3, NS_QDD,
14907 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14908 neon_mixed_length (et, et.size);
14912 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14914 if (inst.operands[2].isscalar)
14916 struct neon_type_el et = neon_check_type (3, NS_QDS,
14917 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14918 NEON_ENCODE (SCALAR, inst);
14919 neon_mul_mac (et, et.type == NT_unsigned);
14923 struct neon_type_el et = neon_check_type (3, NS_QDD,
14924 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14925 NEON_ENCODE (INTEGER, inst);
14926 neon_mixed_length (et, et.size);
14931 do_neon_mac_maybe_scalar_long (void)
14933 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14937 do_neon_dyadic_wide (void)
14939 struct neon_type_el et = neon_check_type (3, NS_QQD,
14940 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14941 neon_mixed_length (et, et.size);
14945 do_neon_dyadic_narrow (void)
14947 struct neon_type_el et = neon_check_type (3, NS_QDD,
14948 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14949 /* Operand sign is unimportant, and the U bit is part of the opcode,
14950 so force the operand type to integer. */
14951 et.type = NT_integer;
14952 neon_mixed_length (et, et.size / 2);
14956 do_neon_mul_sat_scalar_long (void)
14958 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14962 do_neon_vmull (void)
14964 if (inst.operands[2].isscalar)
14965 do_neon_mac_maybe_scalar_long ();
14968 struct neon_type_el et = neon_check_type (3, NS_QDD,
14969 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14970 if (et.type == NT_poly)
14971 NEON_ENCODE (POLY, inst);
14973 NEON_ENCODE (INTEGER, inst);
14974 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14975 zero. Should be OK as-is. */
14976 neon_mixed_length (et, et.size);
14983 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14984 struct neon_type_el et = neon_check_type (3, rs,
14985 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14986 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14988 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14989 _("shift out of range"));
14990 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14991 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14992 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14993 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14994 inst.instruction |= LOW4 (inst.operands[2].reg);
14995 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14996 inst.instruction |= neon_quad (rs) << 6;
14997 inst.instruction |= imm << 8;
14999 neon_dp_fixup (&inst);
15005 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15006 struct neon_type_el et = neon_check_type (2, rs,
15007 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15008 unsigned op = (inst.instruction >> 7) & 3;
15009 /* N (width of reversed regions) is encoded as part of the bitmask. We
15010 extract it here to check the elements to be reversed are smaller.
15011 Otherwise we'd get a reserved instruction. */
15012 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15013 gas_assert (elsize != 0);
15014 constraint (et.size >= elsize,
15015 _("elements must be smaller than reversal region"));
15016 neon_two_same (neon_quad (rs), 1, et.size);
15022 if (inst.operands[1].isscalar)
15024 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15025 struct neon_type_el et = neon_check_type (2, rs,
15026 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15027 unsigned sizebits = et.size >> 3;
15028 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15029 int logsize = neon_logbits (et.size);
15030 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15032 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15035 NEON_ENCODE (SCALAR, inst);
15036 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15037 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15038 inst.instruction |= LOW4 (dm);
15039 inst.instruction |= HI1 (dm) << 5;
15040 inst.instruction |= neon_quad (rs) << 6;
15041 inst.instruction |= x << 17;
15042 inst.instruction |= sizebits << 16;
15044 neon_dp_fixup (&inst);
15048 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15049 struct neon_type_el et = neon_check_type (2, rs,
15050 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15051 /* Duplicate ARM register to lanes of vector. */
15052 NEON_ENCODE (ARMREG, inst);
15055 case 8: inst.instruction |= 0x400000; break;
15056 case 16: inst.instruction |= 0x000020; break;
15057 case 32: inst.instruction |= 0x000000; break;
15060 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15061 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15062 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15063 inst.instruction |= neon_quad (rs) << 21;
15064 /* The encoding for this instruction is identical for the ARM and Thumb
15065 variants, except for the condition field. */
15066 do_vfp_cond_or_thumb ();
15070 /* VMOV has particularly many variations. It can be one of:
15071 0. VMOV<c><q> <Qd>, <Qm>
15072 1. VMOV<c><q> <Dd>, <Dm>
15073 (Register operations, which are VORR with Rm = Rn.)
15074 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15075 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15077 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15078 (ARM register to scalar.)
15079 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15080 (Two ARM registers to vector.)
15081 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15082 (Scalar to ARM register.)
15083 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15084 (Vector to two ARM registers.)
15085 8. VMOV.F32 <Sd>, <Sm>
15086 9. VMOV.F64 <Dd>, <Dm>
15087 (VFP register moves.)
15088 10. VMOV.F32 <Sd>, #imm
15089 11. VMOV.F64 <Dd>, #imm
15090 (VFP float immediate load.)
15091 12. VMOV <Rd>, <Sm>
15092 (VFP single to ARM reg.)
15093 13. VMOV <Sd>, <Rm>
15094 (ARM reg to VFP single.)
15095 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15096 (Two ARM regs to two VFP singles.)
15097 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15098 (Two VFP singles to two ARM regs.)
15100 These cases can be disambiguated using neon_select_shape, except cases 1/9
15101 and 3/11 which depend on the operand type too.
15103 All the encoded bits are hardcoded by this function.
15105 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15106 Cases 5, 7 may be used with VFPv2 and above.
15108 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15109 can specify a type where it doesn't make sense to, and is ignored). */
15114 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15115 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15117 struct neon_type_el et;
15118 const char *ldconst = 0;
15122 case NS_DD: /* case 1/9. */
15123 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15124 /* It is not an error here if no type is given. */
15126 if (et.type == NT_float && et.size == 64)
15128 do_vfp_nsyn_opcode ("fcpyd");
15131 /* fall through. */
15133 case NS_QQ: /* case 0/1. */
15135 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15137 /* The architecture manual I have doesn't explicitly state which
15138 value the U bit should have for register->register moves, but
15139 the equivalent VORR instruction has U = 0, so do that. */
15140 inst.instruction = 0x0200110;
15141 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15142 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15143 inst.instruction |= LOW4 (inst.operands[1].reg);
15144 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15145 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15146 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15147 inst.instruction |= neon_quad (rs) << 6;
15149 neon_dp_fixup (&inst);
15153 case NS_DI: /* case 3/11. */
15154 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15156 if (et.type == NT_float && et.size == 64)
15158 /* case 11 (fconstd). */
15159 ldconst = "fconstd";
15160 goto encode_fconstd;
15162 /* fall through. */
15164 case NS_QI: /* case 2/3. */
15165 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15167 inst.instruction = 0x0800010;
15168 neon_move_immediate ();
15169 neon_dp_fixup (&inst);
15172 case NS_SR: /* case 4. */
15174 unsigned bcdebits = 0;
15176 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15177 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15179 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15180 logsize = neon_logbits (et.size);
15182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15185 && et.size != 32, _(BAD_FPU));
15186 constraint (et.type == NT_invtype, _("bad type for scalar"));
15187 constraint (x >= 64 / et.size, _("scalar index out of range"));
15191 case 8: bcdebits = 0x8; break;
15192 case 16: bcdebits = 0x1; break;
15193 case 32: bcdebits = 0x0; break;
15197 bcdebits |= x << logsize;
15199 inst.instruction = 0xe000b10;
15200 do_vfp_cond_or_thumb ();
15201 inst.instruction |= LOW4 (dn) << 16;
15202 inst.instruction |= HI1 (dn) << 7;
15203 inst.instruction |= inst.operands[1].reg << 12;
15204 inst.instruction |= (bcdebits & 3) << 5;
15205 inst.instruction |= (bcdebits >> 2) << 21;
15209 case NS_DRR: /* case 5 (fmdrr). */
15210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15213 inst.instruction = 0xc400b10;
15214 do_vfp_cond_or_thumb ();
15215 inst.instruction |= LOW4 (inst.operands[0].reg);
15216 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15217 inst.instruction |= inst.operands[1].reg << 12;
15218 inst.instruction |= inst.operands[2].reg << 16;
15221 case NS_RS: /* case 6. */
15224 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15225 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15226 unsigned abcdebits = 0;
15228 et = neon_check_type (2, NS_NULL,
15229 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15230 logsize = neon_logbits (et.size);
15232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15234 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15235 && et.size != 32, _(BAD_FPU));
15236 constraint (et.type == NT_invtype, _("bad type for scalar"));
15237 constraint (x >= 64 / et.size, _("scalar index out of range"));
15241 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15242 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15243 case 32: abcdebits = 0x00; break;
15247 abcdebits |= x << logsize;
15248 inst.instruction = 0xe100b10;
15249 do_vfp_cond_or_thumb ();
15250 inst.instruction |= LOW4 (dn) << 16;
15251 inst.instruction |= HI1 (dn) << 7;
15252 inst.instruction |= inst.operands[0].reg << 12;
15253 inst.instruction |= (abcdebits & 3) << 5;
15254 inst.instruction |= (abcdebits >> 2) << 21;
15258 case NS_RRD: /* case 7 (fmrrd). */
15259 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15262 inst.instruction = 0xc500b10;
15263 do_vfp_cond_or_thumb ();
15264 inst.instruction |= inst.operands[0].reg << 12;
15265 inst.instruction |= inst.operands[1].reg << 16;
15266 inst.instruction |= LOW4 (inst.operands[2].reg);
15267 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15270 case NS_FF: /* case 8 (fcpys). */
15271 do_vfp_nsyn_opcode ("fcpys");
15274 case NS_FI: /* case 10 (fconsts). */
15275 ldconst = "fconsts";
15277 if (is_quarter_float (inst.operands[1].imm))
15279 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15280 do_vfp_nsyn_opcode (ldconst);
15283 first_error (_("immediate out of range"));
15286 case NS_RF: /* case 12 (fmrs). */
15287 do_vfp_nsyn_opcode ("fmrs");
15290 case NS_FR: /* case 13 (fmsr). */
15291 do_vfp_nsyn_opcode ("fmsr");
15294 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15295 (one of which is a list), but we have parsed four. Do some fiddling to
15296 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15298 case NS_RRFF: /* case 14 (fmrrs). */
15299 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15300 _("VFP registers must be adjacent"));
15301 inst.operands[2].imm = 2;
15302 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15303 do_vfp_nsyn_opcode ("fmrrs");
15306 case NS_FFRR: /* case 15 (fmsrr). */
15307 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15308 _("VFP registers must be adjacent"));
15309 inst.operands[1] = inst.operands[2];
15310 inst.operands[2] = inst.operands[3];
15311 inst.operands[0].imm = 2;
15312 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15313 do_vfp_nsyn_opcode ("fmsrr");
15322 do_neon_rshift_round_imm (void)
15324 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15325 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15326 int imm = inst.operands[2].imm;
15328 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15331 inst.operands[2].present = 0;
15336 constraint (imm < 1 || (unsigned)imm > et.size,
15337 _("immediate out of range for shift"));
15338 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15343 do_neon_movl (void)
15345 struct neon_type_el et = neon_check_type (2, NS_QD,
15346 N_EQK | N_DBL, N_SU_32 | N_KEY);
15347 unsigned sizebits = et.size >> 3;
15348 inst.instruction |= sizebits << 19;
15349 neon_two_same (0, et.type == NT_unsigned, -1);
15355 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15356 struct neon_type_el et = neon_check_type (2, rs,
15357 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15358 NEON_ENCODE (INTEGER, inst);
15359 neon_two_same (neon_quad (rs), 1, et.size);
15363 do_neon_zip_uzp (void)
15365 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15366 struct neon_type_el et = neon_check_type (2, rs,
15367 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15368 if (rs == NS_DD && et.size == 32)
15370 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15371 inst.instruction = N_MNEM_vtrn;
15375 neon_two_same (neon_quad (rs), 1, et.size);
15379 do_neon_sat_abs_neg (void)
15381 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15382 struct neon_type_el et = neon_check_type (2, rs,
15383 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15384 neon_two_same (neon_quad (rs), 1, et.size);
15388 do_neon_pair_long (void)
15390 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15391 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15392 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15393 inst.instruction |= (et.type == NT_unsigned) << 7;
15394 neon_two_same (neon_quad (rs), 1, et.size);
15398 do_neon_recip_est (void)
15400 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15401 struct neon_type_el et = neon_check_type (2, rs,
15402 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15403 inst.instruction |= (et.type == NT_float) << 8;
15404 neon_two_same (neon_quad (rs), 1, et.size);
15410 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15411 struct neon_type_el et = neon_check_type (2, rs,
15412 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15413 neon_two_same (neon_quad (rs), 1, et.size);
15419 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15420 struct neon_type_el et = neon_check_type (2, rs,
15421 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15422 neon_two_same (neon_quad (rs), 1, et.size);
15428 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15429 struct neon_type_el et = neon_check_type (2, rs,
15430 N_EQK | N_INT, N_8 | N_KEY);
15431 neon_two_same (neon_quad (rs), 1, et.size);
15437 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15438 neon_two_same (neon_quad (rs), 1, -1);
15442 do_neon_tbl_tbx (void)
15444 unsigned listlenbits;
15445 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15447 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15449 first_error (_("bad list length for table lookup"));
15453 listlenbits = inst.operands[1].imm - 1;
15454 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15455 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15456 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15457 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15458 inst.instruction |= LOW4 (inst.operands[2].reg);
15459 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15460 inst.instruction |= listlenbits << 8;
15462 neon_dp_fixup (&inst);
15466 do_neon_ldm_stm (void)
15468 /* P, U and L bits are part of bitmask. */
15469 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15470 unsigned offsetbits = inst.operands[1].imm * 2;
15472 if (inst.operands[1].issingle)
15474 do_vfp_nsyn_ldm_stm (is_dbmode);
15478 constraint (is_dbmode && !inst.operands[0].writeback,
15479 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15481 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15482 _("register list must contain at least 1 and at most 16 "
15485 inst.instruction |= inst.operands[0].reg << 16;
15486 inst.instruction |= inst.operands[0].writeback << 21;
15487 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15488 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15490 inst.instruction |= offsetbits;
15492 do_vfp_cond_or_thumb ();
15496 do_neon_ldr_str (void)
15498 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15500 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15501 And is UNPREDICTABLE in thumb mode. */
15503 && inst.operands[1].reg == REG_PC
15504 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15506 if (!thumb_mode && warn_on_deprecated)
15507 as_warn (_("Use of PC here is deprecated"));
15509 inst.error = _("Use of PC here is UNPREDICTABLE");
15512 if (inst.operands[0].issingle)
15515 do_vfp_nsyn_opcode ("flds");
15517 do_vfp_nsyn_opcode ("fsts");
15522 do_vfp_nsyn_opcode ("fldd");
15524 do_vfp_nsyn_opcode ("fstd");
15528 /* "interleave" version also handles non-interleaving register VLD1/VST1
15532 do_neon_ld_st_interleave (void)
15534 struct neon_type_el et = neon_check_type (1, NS_NULL,
15535 N_8 | N_16 | N_32 | N_64);
15536 unsigned alignbits = 0;
15538 /* The bits in this table go:
15539 0: register stride of one (0) or two (1)
15540 1,2: register list length, minus one (1, 2, 3, 4).
15541 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15542 We use -1 for invalid entries. */
15543 const int typetable[] =
15545 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15546 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15547 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15548 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15552 if (et.type == NT_invtype)
15555 if (inst.operands[1].immisalign)
15556 switch (inst.operands[1].imm >> 8)
15558 case 64: alignbits = 1; break;
15560 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15561 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15562 goto bad_alignment;
15566 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15567 goto bad_alignment;
15572 first_error (_("bad alignment"));
15576 inst.instruction |= alignbits << 4;
15577 inst.instruction |= neon_logbits (et.size) << 6;
15579 /* Bits [4:6] of the immediate in a list specifier encode register stride
15580 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15581 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15582 up the right value for "type" in a table based on this value and the given
15583 list style, then stick it back. */
15584 idx = ((inst.operands[0].imm >> 4) & 7)
15585 | (((inst.instruction >> 8) & 3) << 3);
15587 typebits = typetable[idx];
15589 constraint (typebits == -1, _("bad list type for instruction"));
15591 inst.instruction &= ~0xf00;
15592 inst.instruction |= typebits << 8;
15595 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15596 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15597 otherwise. The variable arguments are a list of pairs of legal (size, align)
15598 values, terminated with -1. */
15601 neon_alignment_bit (int size, int align, int *do_align, ...)
15604 int result = FAIL, thissize, thisalign;
15606 if (!inst.operands[1].immisalign)
15612 va_start (ap, do_align);
15616 thissize = va_arg (ap, int);
15617 if (thissize == -1)
15619 thisalign = va_arg (ap, int);
15621 if (size == thissize && align == thisalign)
15624 while (result != SUCCESS);
15628 if (result == SUCCESS)
15631 first_error (_("unsupported alignment for instruction"));
15637 do_neon_ld_st_lane (void)
15639 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15640 int align_good, do_align = 0;
15641 int logsize = neon_logbits (et.size);
15642 int align = inst.operands[1].imm >> 8;
15643 int n = (inst.instruction >> 8) & 3;
15644 int max_el = 64 / et.size;
15646 if (et.type == NT_invtype)
15649 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15650 _("bad list length"));
15651 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15652 _("scalar index out of range"));
15653 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15655 _("stride of 2 unavailable when element size is 8"));
15659 case 0: /* VLD1 / VST1. */
15660 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15662 if (align_good == FAIL)
15666 unsigned alignbits = 0;
15669 case 16: alignbits = 0x1; break;
15670 case 32: alignbits = 0x3; break;
15673 inst.instruction |= alignbits << 4;
15677 case 1: /* VLD2 / VST2. */
15678 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15680 if (align_good == FAIL)
15683 inst.instruction |= 1 << 4;
15686 case 2: /* VLD3 / VST3. */
15687 constraint (inst.operands[1].immisalign,
15688 _("can't use alignment with this instruction"));
15691 case 3: /* VLD4 / VST4. */
15692 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15693 16, 64, 32, 64, 32, 128, -1);
15694 if (align_good == FAIL)
15698 unsigned alignbits = 0;
15701 case 8: alignbits = 0x1; break;
15702 case 16: alignbits = 0x1; break;
15703 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15706 inst.instruction |= alignbits << 4;
15713 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15714 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15715 inst.instruction |= 1 << (4 + logsize);
15717 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15718 inst.instruction |= logsize << 10;
15721 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15724 do_neon_ld_dup (void)
15726 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15727 int align_good, do_align = 0;
15729 if (et.type == NT_invtype)
15732 switch ((inst.instruction >> 8) & 3)
15734 case 0: /* VLD1. */
15735 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15736 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15737 &do_align, 16, 16, 32, 32, -1);
15738 if (align_good == FAIL)
15740 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15743 case 2: inst.instruction |= 1 << 5; break;
15744 default: first_error (_("bad list length")); return;
15746 inst.instruction |= neon_logbits (et.size) << 6;
15749 case 1: /* VLD2. */
15750 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15751 &do_align, 8, 16, 16, 32, 32, 64, -1);
15752 if (align_good == FAIL)
15754 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15755 _("bad list length"));
15756 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15757 inst.instruction |= 1 << 5;
15758 inst.instruction |= neon_logbits (et.size) << 6;
15761 case 2: /* VLD3. */
15762 constraint (inst.operands[1].immisalign,
15763 _("can't use alignment with this instruction"));
15764 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15765 _("bad list length"));
15766 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15767 inst.instruction |= 1 << 5;
15768 inst.instruction |= neon_logbits (et.size) << 6;
15771 case 3: /* VLD4. */
15773 int align = inst.operands[1].imm >> 8;
15774 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15775 16, 64, 32, 64, 32, 128, -1);
15776 if (align_good == FAIL)
15778 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15779 _("bad list length"));
15780 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15781 inst.instruction |= 1 << 5;
15782 if (et.size == 32 && align == 128)
15783 inst.instruction |= 0x3 << 6;
15785 inst.instruction |= neon_logbits (et.size) << 6;
15792 inst.instruction |= do_align << 4;
15795 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15796 apart from bits [11:4]. */
15799 do_neon_ldx_stx (void)
15801 if (inst.operands[1].isreg)
15802 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15804 switch (NEON_LANE (inst.operands[0].imm))
15806 case NEON_INTERLEAVE_LANES:
15807 NEON_ENCODE (INTERLV, inst);
15808 do_neon_ld_st_interleave ();
15811 case NEON_ALL_LANES:
15812 NEON_ENCODE (DUP, inst);
15817 NEON_ENCODE (LANE, inst);
15818 do_neon_ld_st_lane ();
15821 /* L bit comes from bit mask. */
15822 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15823 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15824 inst.instruction |= inst.operands[1].reg << 16;
15826 if (inst.operands[1].postind)
15828 int postreg = inst.operands[1].imm & 0xf;
15829 constraint (!inst.operands[1].immisreg,
15830 _("post-index must be a register"));
15831 constraint (postreg == 0xd || postreg == 0xf,
15832 _("bad register for post-index"));
15833 inst.instruction |= postreg;
15835 else if (inst.operands[1].writeback)
15837 inst.instruction |= 0xd;
15840 inst.instruction |= 0xf;
15843 inst.instruction |= 0xf9000000;
15845 inst.instruction |= 0xf4000000;
15850 do_vfp_nsyn_fpv8 (enum neon_shape rs)
15852 NEON_ENCODE (FPV8, inst);
15855 do_vfp_sp_dyadic ();
15857 do_vfp_dp_rd_rn_rm ();
15860 inst.instruction |= 0x100;
15862 inst.instruction |= 0xf0000000;
15868 set_it_insn_type (OUTSIDE_IT_INSN);
15870 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
15871 first_error (_("invalid instruction shape"));
15877 set_it_insn_type (OUTSIDE_IT_INSN);
15879 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
15882 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15885 neon_dyadic_misc (NT_untyped, N_F32, 0);
15889 /* Overall per-instruction processing. */
15891 /* We need to be able to fix up arbitrary expressions in some statements.
15892 This is so that we can handle symbols that are an arbitrary distance from
15893 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15894 which returns part of an address in a form which will be valid for
15895 a data instruction. We do this by pushing the expression into a symbol
15896 in the expr_section, and creating a fix for that. */
15899 fix_new_arm (fragS * frag,
15913 /* Create an absolute valued symbol, so we have something to
15914 refer to in the object file. Unfortunately for us, gas's
15915 generic expression parsing will already have folded out
15916 any use of .set foo/.type foo %function that may have
15917 been used to set type information of the target location,
15918 that's being specified symbolically. We have to presume
15919 the user knows what they are doing. */
15923 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15925 symbol = symbol_find_or_make (name);
15926 S_SET_SEGMENT (symbol, absolute_section);
15927 symbol_set_frag (symbol, &zero_address_frag);
15928 S_SET_VALUE (symbol, exp->X_add_number);
15929 exp->X_op = O_symbol;
15930 exp->X_add_symbol = symbol;
15931 exp->X_add_number = 0;
15937 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15938 (enum bfd_reloc_code_real) reloc);
15942 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15943 pc_rel, (enum bfd_reloc_code_real) reloc);
15947 /* Mark whether the fix is to a THUMB instruction, or an ARM
15949 new_fix->tc_fix_data = thumb_mode;
15952 /* Create a frg for an instruction requiring relaxation. */
15954 output_relax_insn (void)
15960 /* The size of the instruction is unknown, so tie the debug info to the
15961 start of the instruction. */
15962 dwarf2_emit_insn (0);
15964 switch (inst.reloc.exp.X_op)
15967 sym = inst.reloc.exp.X_add_symbol;
15968 offset = inst.reloc.exp.X_add_number;
15972 offset = inst.reloc.exp.X_add_number;
15975 sym = make_expr_symbol (&inst.reloc.exp);
15979 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15980 inst.relax, sym, offset, NULL/*offset, opcode*/);
15981 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15984 /* Write a 32-bit thumb instruction to buf. */
15986 put_thumb32_insn (char * buf, unsigned long insn)
15988 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15989 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15993 output_inst (const char * str)
15999 as_bad ("%s -- `%s'", inst.error, str);
16004 output_relax_insn ();
16007 if (inst.size == 0)
16010 to = frag_more (inst.size);
16011 /* PR 9814: Record the thumb mode into the current frag so that we know
16012 what type of NOP padding to use, if necessary. We override any previous
16013 setting so that if the mode has changed then the NOPS that we use will
16014 match the encoding of the last instruction in the frag. */
16015 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16017 if (thumb_mode && (inst.size > THUMB_SIZE))
16019 gas_assert (inst.size == (2 * THUMB_SIZE));
16020 put_thumb32_insn (to, inst.instruction);
16022 else if (inst.size > INSN_SIZE)
16024 gas_assert (inst.size == (2 * INSN_SIZE));
16025 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16026 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16029 md_number_to_chars (to, inst.instruction, inst.size);
16031 if (inst.reloc.type != BFD_RELOC_UNUSED)
16032 fix_new_arm (frag_now, to - frag_now->fr_literal,
16033 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16036 dwarf2_emit_insn (inst.size);
16040 output_it_inst (int cond, int mask, char * to)
16042 unsigned long instruction = 0xbf00;
16045 instruction |= mask;
16046 instruction |= cond << 4;
16050 to = frag_more (2);
16052 dwarf2_emit_insn (2);
16056 md_number_to_chars (to, instruction, 2);
16061 /* Tag values used in struct asm_opcode's tag field. */
16064 OT_unconditional, /* Instruction cannot be conditionalized.
16065 The ARM condition field is still 0xE. */
16066 OT_unconditionalF, /* Instruction cannot be conditionalized
16067 and carries 0xF in its ARM condition field. */
16068 OT_csuffix, /* Instruction takes a conditional suffix. */
16069 OT_csuffixF, /* Some forms of the instruction take a conditional
16070 suffix, others place 0xF where the condition field
16072 OT_cinfix3, /* Instruction takes a conditional infix,
16073 beginning at character index 3. (In
16074 unified mode, it becomes a suffix.) */
16075 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16076 tsts, cmps, cmns, and teqs. */
16077 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16078 character index 3, even in unified mode. Used for
16079 legacy instructions where suffix and infix forms
16080 may be ambiguous. */
16081 OT_csuf_or_in3, /* Instruction takes either a conditional
16082 suffix or an infix at character index 3. */
16083 OT_odd_infix_unc, /* This is the unconditional variant of an
16084 instruction that takes a conditional infix
16085 at an unusual position. In unified mode,
16086 this variant will accept a suffix. */
16087 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16088 are the conditional variants of instructions that
16089 take conditional infixes in unusual positions.
16090 The infix appears at character index
16091 (tag - OT_odd_infix_0). These are not accepted
16092 in unified mode. */
16095 /* Subroutine of md_assemble, responsible for looking up the primary
16096 opcode from the mnemonic the user wrote. STR points to the
16097 beginning of the mnemonic.
16099 This is not simply a hash table lookup, because of conditional
16100 variants. Most instructions have conditional variants, which are
16101 expressed with a _conditional affix_ to the mnemonic. If we were
16102 to encode each conditional variant as a literal string in the opcode
16103 table, it would have approximately 20,000 entries.
16105 Most mnemonics take this affix as a suffix, and in unified syntax,
16106 'most' is upgraded to 'all'. However, in the divided syntax, some
16107 instructions take the affix as an infix, notably the s-variants of
16108 the arithmetic instructions. Of those instructions, all but six
16109 have the infix appear after the third character of the mnemonic.
16111 Accordingly, the algorithm for looking up primary opcodes given
16114 1. Look up the identifier in the opcode table.
16115 If we find a match, go to step U.
16117 2. Look up the last two characters of the identifier in the
16118 conditions table. If we find a match, look up the first N-2
16119 characters of the identifier in the opcode table. If we
16120 find a match, go to step CE.
16122 3. Look up the fourth and fifth characters of the identifier in
16123 the conditions table. If we find a match, extract those
16124 characters from the identifier, and look up the remaining
16125 characters in the opcode table. If we find a match, go
16130 U. Examine the tag field of the opcode structure, in case this is
16131 one of the six instructions with its conditional infix in an
16132 unusual place. If it is, the tag tells us where to find the
16133 infix; look it up in the conditions table and set inst.cond
16134 accordingly. Otherwise, this is an unconditional instruction.
16135 Again set inst.cond accordingly. Return the opcode structure.
16137 CE. Examine the tag field to make sure this is an instruction that
16138 should receive a conditional suffix. If it is not, fail.
16139 Otherwise, set inst.cond from the suffix we already looked up,
16140 and return the opcode structure.
16142 CM. Examine the tag field to make sure this is an instruction that
16143 should receive a conditional infix after the third character.
16144 If it is not, fail. Otherwise, undo the edits to the current
16145 line of input and proceed as for case CE. */
16147 static const struct asm_opcode *
16148 opcode_lookup (char **str)
16152 const struct asm_opcode *opcode;
16153 const struct asm_cond *cond;
16156 /* Scan up to the end of the mnemonic, which must end in white space,
16157 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16158 for (base = end = *str; *end != '\0'; end++)
16159 if (*end == ' ' || *end == '.')
16165 /* Handle a possible width suffix and/or Neon type suffix. */
16170 /* The .w and .n suffixes are only valid if the unified syntax is in
16172 if (unified_syntax && end[1] == 'w')
16174 else if (unified_syntax && end[1] == 'n')
16179 inst.vectype.elems = 0;
16181 *str = end + offset;
16183 if (end[offset] == '.')
16185 /* See if we have a Neon type suffix (possible in either unified or
16186 non-unified ARM syntax mode). */
16187 if (parse_neon_type (&inst.vectype, str) == FAIL)
16190 else if (end[offset] != '\0' && end[offset] != ' ')
16196 /* Look for unaffixed or special-case affixed mnemonic. */
16197 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16202 if (opcode->tag < OT_odd_infix_0)
16204 inst.cond = COND_ALWAYS;
16208 if (warn_on_deprecated && unified_syntax)
16209 as_warn (_("conditional infixes are deprecated in unified syntax"));
16210 affix = base + (opcode->tag - OT_odd_infix_0);
16211 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16214 inst.cond = cond->value;
16218 /* Cannot have a conditional suffix on a mnemonic of less than two
16220 if (end - base < 3)
16223 /* Look for suffixed mnemonic. */
16225 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16226 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16228 if (opcode && cond)
16231 switch (opcode->tag)
16233 case OT_cinfix3_legacy:
16234 /* Ignore conditional suffixes matched on infix only mnemonics. */
16238 case OT_cinfix3_deprecated:
16239 case OT_odd_infix_unc:
16240 if (!unified_syntax)
16242 /* else fall through */
16246 case OT_csuf_or_in3:
16247 inst.cond = cond->value;
16250 case OT_unconditional:
16251 case OT_unconditionalF:
16253 inst.cond = cond->value;
16256 /* Delayed diagnostic. */
16257 inst.error = BAD_COND;
16258 inst.cond = COND_ALWAYS;
16267 /* Cannot have a usual-position infix on a mnemonic of less than
16268 six characters (five would be a suffix). */
16269 if (end - base < 6)
16272 /* Look for infixed mnemonic in the usual position. */
16274 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16278 memcpy (save, affix, 2);
16279 memmove (affix, affix + 2, (end - affix) - 2);
16280 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16282 memmove (affix + 2, affix, (end - affix) - 2);
16283 memcpy (affix, save, 2);
16286 && (opcode->tag == OT_cinfix3
16287 || opcode->tag == OT_cinfix3_deprecated
16288 || opcode->tag == OT_csuf_or_in3
16289 || opcode->tag == OT_cinfix3_legacy))
16292 if (warn_on_deprecated && unified_syntax
16293 && (opcode->tag == OT_cinfix3
16294 || opcode->tag == OT_cinfix3_deprecated))
16295 as_warn (_("conditional infixes are deprecated in unified syntax"));
16297 inst.cond = cond->value;
16304 /* This function generates an initial IT instruction, leaving its block
16305 virtually open for the new instructions. Eventually,
16306 the mask will be updated by now_it_add_mask () each time
16307 a new instruction needs to be included in the IT block.
16308 Finally, the block is closed with close_automatic_it_block ().
16309 The block closure can be requested either from md_assemble (),
16310 a tencode (), or due to a label hook. */
16313 new_automatic_it_block (int cond)
16315 now_it.state = AUTOMATIC_IT_BLOCK;
16316 now_it.mask = 0x18;
16318 now_it.block_length = 1;
16319 mapping_state (MAP_THUMB);
16320 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16321 now_it.warn_deprecated = FALSE;
16322 now_it.insn_cond = TRUE;
16325 /* Close an automatic IT block.
16326 See comments in new_automatic_it_block (). */
16329 close_automatic_it_block (void)
16331 now_it.mask = 0x10;
16332 now_it.block_length = 0;
16335 /* Update the mask of the current automatically-generated IT
16336 instruction. See comments in new_automatic_it_block (). */
16339 now_it_add_mask (int cond)
16341 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16342 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16343 | ((bitvalue) << (nbit)))
16344 const int resulting_bit = (cond & 1);
16346 now_it.mask &= 0xf;
16347 now_it.mask = SET_BIT_VALUE (now_it.mask,
16349 (5 - now_it.block_length));
16350 now_it.mask = SET_BIT_VALUE (now_it.mask,
16352 ((5 - now_it.block_length) - 1) );
16353 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16356 #undef SET_BIT_VALUE
16359 /* The IT blocks handling machinery is accessed through the these functions:
16360 it_fsm_pre_encode () from md_assemble ()
16361 set_it_insn_type () optional, from the tencode functions
16362 set_it_insn_type_last () ditto
16363 in_it_block () ditto
16364 it_fsm_post_encode () from md_assemble ()
16365 force_automatic_it_block_close () from label habdling functions
16368 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16369 initializing the IT insn type with a generic initial value depending
16370 on the inst.condition.
16371 2) During the tencode function, two things may happen:
16372 a) The tencode function overrides the IT insn type by
16373 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16374 b) The tencode function queries the IT block state by
16375 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16377 Both set_it_insn_type and in_it_block run the internal FSM state
16378 handling function (handle_it_state), because: a) setting the IT insn
16379 type may incur in an invalid state (exiting the function),
16380 and b) querying the state requires the FSM to be updated.
16381 Specifically we want to avoid creating an IT block for conditional
16382 branches, so it_fsm_pre_encode is actually a guess and we can't
16383 determine whether an IT block is required until the tencode () routine
16384 has decided what type of instruction this actually it.
16385 Because of this, if set_it_insn_type and in_it_block have to be used,
16386 set_it_insn_type has to be called first.
16388 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16389 determines the insn IT type depending on the inst.cond code.
16390 When a tencode () routine encodes an instruction that can be
16391 either outside an IT block, or, in the case of being inside, has to be
16392 the last one, set_it_insn_type_last () will determine the proper
16393 IT instruction type based on the inst.cond code. Otherwise,
16394 set_it_insn_type can be called for overriding that logic or
16395 for covering other cases.
16397 Calling handle_it_state () may not transition the IT block state to
16398 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16399 still queried. Instead, if the FSM determines that the state should
16400 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16401 after the tencode () function: that's what it_fsm_post_encode () does.
16403 Since in_it_block () calls the state handling function to get an
16404 updated state, an error may occur (due to invalid insns combination).
16405 In that case, inst.error is set.
16406 Therefore, inst.error has to be checked after the execution of
16407 the tencode () routine.
16409 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16410 any pending state change (if any) that didn't take place in
16411 handle_it_state () as explained above. */
16414 it_fsm_pre_encode (void)
16416 if (inst.cond != COND_ALWAYS)
16417 inst.it_insn_type = INSIDE_IT_INSN;
16419 inst.it_insn_type = OUTSIDE_IT_INSN;
16421 now_it.state_handled = 0;
16424 /* IT state FSM handling function. */
16427 handle_it_state (void)
16429 now_it.state_handled = 1;
16430 now_it.insn_cond = FALSE;
16432 switch (now_it.state)
16434 case OUTSIDE_IT_BLOCK:
16435 switch (inst.it_insn_type)
16437 case OUTSIDE_IT_INSN:
16440 case INSIDE_IT_INSN:
16441 case INSIDE_IT_LAST_INSN:
16442 if (thumb_mode == 0)
16445 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16446 as_tsktsk (_("Warning: conditional outside an IT block"\
16451 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16452 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16454 /* Automatically generate the IT instruction. */
16455 new_automatic_it_block (inst.cond);
16456 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16457 close_automatic_it_block ();
16461 inst.error = BAD_OUT_IT;
16467 case IF_INSIDE_IT_LAST_INSN:
16468 case NEUTRAL_IT_INSN:
16472 now_it.state = MANUAL_IT_BLOCK;
16473 now_it.block_length = 0;
16478 case AUTOMATIC_IT_BLOCK:
16479 /* Three things may happen now:
16480 a) We should increment current it block size;
16481 b) We should close current it block (closing insn or 4 insns);
16482 c) We should close current it block and start a new one (due
16483 to incompatible conditions or
16484 4 insns-length block reached). */
16486 switch (inst.it_insn_type)
16488 case OUTSIDE_IT_INSN:
16489 /* The closure of the block shall happen immediatelly,
16490 so any in_it_block () call reports the block as closed. */
16491 force_automatic_it_block_close ();
16494 case INSIDE_IT_INSN:
16495 case INSIDE_IT_LAST_INSN:
16496 case IF_INSIDE_IT_LAST_INSN:
16497 now_it.block_length++;
16499 if (now_it.block_length > 4
16500 || !now_it_compatible (inst.cond))
16502 force_automatic_it_block_close ();
16503 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16504 new_automatic_it_block (inst.cond);
16508 now_it.insn_cond = TRUE;
16509 now_it_add_mask (inst.cond);
16512 if (now_it.state == AUTOMATIC_IT_BLOCK
16513 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16514 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16515 close_automatic_it_block ();
16518 case NEUTRAL_IT_INSN:
16519 now_it.block_length++;
16520 now_it.insn_cond = TRUE;
16522 if (now_it.block_length > 4)
16523 force_automatic_it_block_close ();
16525 now_it_add_mask (now_it.cc & 1);
16529 close_automatic_it_block ();
16530 now_it.state = MANUAL_IT_BLOCK;
16535 case MANUAL_IT_BLOCK:
16537 /* Check conditional suffixes. */
16538 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16541 now_it.mask &= 0x1f;
16542 is_last = (now_it.mask == 0x10);
16543 now_it.insn_cond = TRUE;
16545 switch (inst.it_insn_type)
16547 case OUTSIDE_IT_INSN:
16548 inst.error = BAD_NOT_IT;
16551 case INSIDE_IT_INSN:
16552 if (cond != inst.cond)
16554 inst.error = BAD_IT_COND;
16559 case INSIDE_IT_LAST_INSN:
16560 case IF_INSIDE_IT_LAST_INSN:
16561 if (cond != inst.cond)
16563 inst.error = BAD_IT_COND;
16568 inst.error = BAD_BRANCH;
16573 case NEUTRAL_IT_INSN:
16574 /* The BKPT instruction is unconditional even in an IT block. */
16578 inst.error = BAD_IT_IT;
16588 struct depr_insn_mask
16590 unsigned long pattern;
16591 unsigned long mask;
16592 const char* description;
16595 /* List of 16-bit instruction patterns deprecated in an IT block in
16597 static const struct depr_insn_mask depr_it_insns[] = {
16598 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
16599 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
16600 { 0xa000, 0xb800, N_("ADR") },
16601 { 0x4800, 0xf800, N_("Literal loads") },
16602 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
16603 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
16608 it_fsm_post_encode (void)
16612 if (!now_it.state_handled)
16613 handle_it_state ();
16615 if (now_it.insn_cond
16616 && !now_it.warn_deprecated
16617 && warn_on_deprecated
16618 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
16620 if (inst.instruction >= 0x10000)
16622 as_warn (_("it blocks containing wide Thumb instructions are "
16623 "deprecated in ARMv8"));
16624 now_it.warn_deprecated = TRUE;
16628 const struct depr_insn_mask *p = depr_it_insns;
16630 while (p->mask != 0)
16632 if ((inst.instruction & p->mask) == p->pattern)
16634 as_warn (_("it blocks containing 16-bit Thumb intsructions "
16635 "of the following class are deprecated in ARMv8: "
16636 "%s"), p->description);
16637 now_it.warn_deprecated = TRUE;
16645 if (now_it.block_length > 1)
16647 as_warn (_("it blocks of more than one conditional instruction are "
16648 "deprecated in ARMv8"));
16649 now_it.warn_deprecated = TRUE;
16653 is_last = (now_it.mask == 0x10);
16656 now_it.state = OUTSIDE_IT_BLOCK;
16662 force_automatic_it_block_close (void)
16664 if (now_it.state == AUTOMATIC_IT_BLOCK)
16666 close_automatic_it_block ();
16667 now_it.state = OUTSIDE_IT_BLOCK;
16675 if (!now_it.state_handled)
16676 handle_it_state ();
16678 return now_it.state != OUTSIDE_IT_BLOCK;
16682 md_assemble (char *str)
16685 const struct asm_opcode * opcode;
16687 /* Align the previous label if needed. */
16688 if (last_label_seen != NULL)
16690 symbol_set_frag (last_label_seen, frag_now);
16691 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16692 S_SET_SEGMENT (last_label_seen, now_seg);
16695 memset (&inst, '\0', sizeof (inst));
16696 inst.reloc.type = BFD_RELOC_UNUSED;
16698 opcode = opcode_lookup (&p);
16701 /* It wasn't an instruction, but it might be a register alias of
16702 the form alias .req reg, or a Neon .dn/.qn directive. */
16703 if (! create_register_alias (str, p)
16704 && ! create_neon_reg_alias (str, p))
16705 as_bad (_("bad instruction `%s'"), str);
16710 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16711 as_warn (_("s suffix on comparison instruction is deprecated"));
16713 /* The value which unconditional instructions should have in place of the
16714 condition field. */
16715 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16719 arm_feature_set variant;
16721 variant = cpu_variant;
16722 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16723 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16724 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16725 /* Check that this instruction is supported for this CPU. */
16726 if (!opcode->tvariant
16727 || (thumb_mode == 1
16728 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16730 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16733 if (inst.cond != COND_ALWAYS && !unified_syntax
16734 && opcode->tencode != do_t_branch)
16736 as_bad (_("Thumb does not support conditional execution"));
16740 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16742 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16743 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16744 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16746 /* Two things are addressed here.
16747 1) Implicit require narrow instructions on Thumb-1.
16748 This avoids relaxation accidentally introducing Thumb-2
16750 2) Reject wide instructions in non Thumb-2 cores. */
16751 if (inst.size_req == 0)
16753 else if (inst.size_req == 4)
16755 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16761 inst.instruction = opcode->tvalue;
16763 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16765 /* Prepare the it_insn_type for those encodings that don't set
16767 it_fsm_pre_encode ();
16769 opcode->tencode ();
16771 it_fsm_post_encode ();
16774 if (!(inst.error || inst.relax))
16776 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16777 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16778 if (inst.size_req && inst.size_req != inst.size)
16780 as_bad (_("cannot honor width suffix -- `%s'"), str);
16785 /* Something has gone badly wrong if we try to relax a fixed size
16787 gas_assert (inst.size_req == 0 || !inst.relax);
16789 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16790 *opcode->tvariant);
16791 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16792 set those bits when Thumb-2 32-bit instructions are seen. ie.
16793 anything other than bl/blx and v6-M instructions.
16794 This is overly pessimistic for relaxable instructions. */
16795 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16797 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16798 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16799 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16802 check_neon_suffixes;
16806 mapping_state (MAP_THUMB);
16809 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16813 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16814 is_bx = (opcode->aencode == do_bx);
16816 /* Check that this instruction is supported for this CPU. */
16817 if (!(is_bx && fix_v4bx)
16818 && !(opcode->avariant &&
16819 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16821 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16826 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16830 inst.instruction = opcode->avalue;
16831 if (opcode->tag == OT_unconditionalF)
16832 inst.instruction |= 0xF << 28;
16834 inst.instruction |= inst.cond << 28;
16835 inst.size = INSN_SIZE;
16836 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16838 it_fsm_pre_encode ();
16839 opcode->aencode ();
16840 it_fsm_post_encode ();
16842 /* Arm mode bx is marked as both v4T and v5 because it's still required
16843 on a hypothetical non-thumb v5 core. */
16845 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16847 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16848 *opcode->avariant);
16850 check_neon_suffixes;
16854 mapping_state (MAP_ARM);
16859 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16867 check_it_blocks_finished (void)
16872 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16873 if (seg_info (sect)->tc_segment_info_data.current_it.state
16874 == MANUAL_IT_BLOCK)
16876 as_warn (_("section '%s' finished with an open IT block."),
16880 if (now_it.state == MANUAL_IT_BLOCK)
16881 as_warn (_("file finished with an open IT block."));
16885 /* Various frobbings of labels and their addresses. */
16888 arm_start_line_hook (void)
16890 last_label_seen = NULL;
16894 arm_frob_label (symbolS * sym)
16896 last_label_seen = sym;
16898 ARM_SET_THUMB (sym, thumb_mode);
16900 #if defined OBJ_COFF || defined OBJ_ELF
16901 ARM_SET_INTERWORK (sym, support_interwork);
16904 force_automatic_it_block_close ();
16906 /* Note - do not allow local symbols (.Lxxx) to be labelled
16907 as Thumb functions. This is because these labels, whilst
16908 they exist inside Thumb code, are not the entry points for
16909 possible ARM->Thumb calls. Also, these labels can be used
16910 as part of a computed goto or switch statement. eg gcc
16911 can generate code that looks like this:
16913 ldr r2, [pc, .Laaa]
16923 The first instruction loads the address of the jump table.
16924 The second instruction converts a table index into a byte offset.
16925 The third instruction gets the jump address out of the table.
16926 The fourth instruction performs the jump.
16928 If the address stored at .Laaa is that of a symbol which has the
16929 Thumb_Func bit set, then the linker will arrange for this address
16930 to have the bottom bit set, which in turn would mean that the
16931 address computation performed by the third instruction would end
16932 up with the bottom bit set. Since the ARM is capable of unaligned
16933 word loads, the instruction would then load the incorrect address
16934 out of the jump table, and chaos would ensue. */
16935 if (label_is_thumb_function_name
16936 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16937 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16939 /* When the address of a Thumb function is taken the bottom
16940 bit of that address should be set. This will allow
16941 interworking between Arm and Thumb functions to work
16944 THUMB_SET_FUNC (sym, 1);
16946 label_is_thumb_function_name = FALSE;
16949 dwarf2_emit_label (sym);
16953 arm_data_in_code (void)
16955 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16957 *input_line_pointer = '/';
16958 input_line_pointer += 5;
16959 *input_line_pointer = 0;
16967 arm_canonicalize_symbol_name (char * name)
16971 if (thumb_mode && (len = strlen (name)) > 5
16972 && streq (name + len - 5, "/data"))
16973 *(name + len - 5) = 0;
16978 /* Table of all register names defined by default. The user can
16979 define additional names with .req. Note that all register names
16980 should appear in both upper and lowercase variants. Some registers
16981 also have mixed-case names. */
16983 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16984 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16985 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16986 #define REGSET(p,t) \
16987 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16988 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16989 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16990 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16991 #define REGSETH(p,t) \
16992 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16993 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16994 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16995 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16996 #define REGSET2(p,t) \
16997 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16998 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16999 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17000 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17001 #define SPLRBANK(base,bank,t) \
17002 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17003 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17004 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17005 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17006 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17007 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17009 static const struct reg_entry reg_names[] =
17011 /* ARM integer registers. */
17012 REGSET(r, RN), REGSET(R, RN),
17014 /* ATPCS synonyms. */
17015 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17016 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17017 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17019 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17020 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17021 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17023 /* Well-known aliases. */
17024 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17025 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17027 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17028 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17030 /* Coprocessor numbers. */
17031 REGSET(p, CP), REGSET(P, CP),
17033 /* Coprocessor register numbers. The "cr" variants are for backward
17035 REGSET(c, CN), REGSET(C, CN),
17036 REGSET(cr, CN), REGSET(CR, CN),
17038 /* ARM banked registers. */
17039 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17040 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17041 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17042 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17043 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17044 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17045 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17047 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17048 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17049 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17050 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17051 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17052 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
17053 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17054 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17056 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17057 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17058 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17059 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17060 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17061 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17062 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17063 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17064 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17066 /* FPA registers. */
17067 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17068 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17070 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17071 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17073 /* VFP SP registers. */
17074 REGSET(s,VFS), REGSET(S,VFS),
17075 REGSETH(s,VFS), REGSETH(S,VFS),
17077 /* VFP DP Registers. */
17078 REGSET(d,VFD), REGSET(D,VFD),
17079 /* Extra Neon DP registers. */
17080 REGSETH(d,VFD), REGSETH(D,VFD),
17082 /* Neon QP registers. */
17083 REGSET2(q,NQ), REGSET2(Q,NQ),
17085 /* VFP control registers. */
17086 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17087 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17088 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17089 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17090 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17091 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17093 /* Maverick DSP coprocessor registers. */
17094 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17095 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17097 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17098 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17099 REGDEF(dspsc,0,DSPSC),
17101 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17102 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17103 REGDEF(DSPSC,0,DSPSC),
17105 /* iWMMXt data registers - p0, c0-15. */
17106 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17108 /* iWMMXt control registers - p1, c0-3. */
17109 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17110 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17111 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17112 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17114 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17115 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17116 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17117 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17118 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17120 /* XScale accumulator registers. */
17121 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17127 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17128 within psr_required_here. */
17129 static const struct asm_psr psrs[] =
17131 /* Backward compatibility notation. Note that "all" is no longer
17132 truly all possible PSR bits. */
17133 {"all", PSR_c | PSR_f},
17137 /* Individual flags. */
17143 /* Combinations of flags. */
17144 {"fs", PSR_f | PSR_s},
17145 {"fx", PSR_f | PSR_x},
17146 {"fc", PSR_f | PSR_c},
17147 {"sf", PSR_s | PSR_f},
17148 {"sx", PSR_s | PSR_x},
17149 {"sc", PSR_s | PSR_c},
17150 {"xf", PSR_x | PSR_f},
17151 {"xs", PSR_x | PSR_s},
17152 {"xc", PSR_x | PSR_c},
17153 {"cf", PSR_c | PSR_f},
17154 {"cs", PSR_c | PSR_s},
17155 {"cx", PSR_c | PSR_x},
17156 {"fsx", PSR_f | PSR_s | PSR_x},
17157 {"fsc", PSR_f | PSR_s | PSR_c},
17158 {"fxs", PSR_f | PSR_x | PSR_s},
17159 {"fxc", PSR_f | PSR_x | PSR_c},
17160 {"fcs", PSR_f | PSR_c | PSR_s},
17161 {"fcx", PSR_f | PSR_c | PSR_x},
17162 {"sfx", PSR_s | PSR_f | PSR_x},
17163 {"sfc", PSR_s | PSR_f | PSR_c},
17164 {"sxf", PSR_s | PSR_x | PSR_f},
17165 {"sxc", PSR_s | PSR_x | PSR_c},
17166 {"scf", PSR_s | PSR_c | PSR_f},
17167 {"scx", PSR_s | PSR_c | PSR_x},
17168 {"xfs", PSR_x | PSR_f | PSR_s},
17169 {"xfc", PSR_x | PSR_f | PSR_c},
17170 {"xsf", PSR_x | PSR_s | PSR_f},
17171 {"xsc", PSR_x | PSR_s | PSR_c},
17172 {"xcf", PSR_x | PSR_c | PSR_f},
17173 {"xcs", PSR_x | PSR_c | PSR_s},
17174 {"cfs", PSR_c | PSR_f | PSR_s},
17175 {"cfx", PSR_c | PSR_f | PSR_x},
17176 {"csf", PSR_c | PSR_s | PSR_f},
17177 {"csx", PSR_c | PSR_s | PSR_x},
17178 {"cxf", PSR_c | PSR_x | PSR_f},
17179 {"cxs", PSR_c | PSR_x | PSR_s},
17180 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17181 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17182 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17183 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17184 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17185 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17186 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17187 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17188 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17189 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17190 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17191 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17192 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17193 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17194 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17195 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17196 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17197 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17198 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17199 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17200 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17201 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17202 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17203 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17206 /* Table of V7M psr names. */
17207 static const struct asm_psr v7m_psrs[] =
17209 {"apsr", 0 }, {"APSR", 0 },
17210 {"iapsr", 1 }, {"IAPSR", 1 },
17211 {"eapsr", 2 }, {"EAPSR", 2 },
17212 {"psr", 3 }, {"PSR", 3 },
17213 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17214 {"ipsr", 5 }, {"IPSR", 5 },
17215 {"epsr", 6 }, {"EPSR", 6 },
17216 {"iepsr", 7 }, {"IEPSR", 7 },
17217 {"msp", 8 }, {"MSP", 8 },
17218 {"psp", 9 }, {"PSP", 9 },
17219 {"primask", 16}, {"PRIMASK", 16},
17220 {"basepri", 17}, {"BASEPRI", 17},
17221 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17222 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17223 {"faultmask", 19}, {"FAULTMASK", 19},
17224 {"control", 20}, {"CONTROL", 20}
17227 /* Table of all shift-in-operand names. */
17228 static const struct asm_shift_name shift_names [] =
17230 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17231 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17232 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17233 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17234 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17235 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17238 /* Table of all explicit relocation names. */
17240 static struct reloc_entry reloc_names[] =
17242 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17243 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17244 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17245 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17246 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17247 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17248 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17249 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17250 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17251 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17252 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17253 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17254 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17255 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17256 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17257 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17258 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17259 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17263 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17264 static const struct asm_cond conds[] =
17268 {"cs", 0x2}, {"hs", 0x2},
17269 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17283 #define UL_BARRIER(L,U,CODE,FEAT) \
17284 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17285 { U, CODE, ARM_FEATURE (FEAT, 0) }
17287 static struct asm_barrier_opt barrier_opt_names[] =
17289 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17290 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17291 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17292 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17293 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17294 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17295 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17296 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17297 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17298 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17299 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17300 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17301 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17302 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17303 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17304 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17309 /* Table of ARM-format instructions. */
17311 /* Macros for gluing together operand strings. N.B. In all cases
17312 other than OPS0, the trailing OP_stop comes from default
17313 zero-initialization of the unspecified elements of the array. */
17314 #define OPS0() { OP_stop, }
17315 #define OPS1(a) { OP_##a, }
17316 #define OPS2(a,b) { OP_##a,OP_##b, }
17317 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17318 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17319 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17320 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17322 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17323 This is useful when mixing operands for ARM and THUMB, i.e. using the
17324 MIX_ARM_THUMB_OPERANDS macro.
17325 In order to use these macros, prefix the number of operands with _
17327 #define OPS_1(a) { a, }
17328 #define OPS_2(a,b) { a,b, }
17329 #define OPS_3(a,b,c) { a,b,c, }
17330 #define OPS_4(a,b,c,d) { a,b,c,d, }
17331 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17332 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17334 /* These macros abstract out the exact format of the mnemonic table and
17335 save some repeated characters. */
17337 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17338 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17339 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17340 THUMB_VARIANT, do_##ae, do_##te }
17342 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17343 a T_MNEM_xyz enumerator. */
17344 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17345 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17346 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17347 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17349 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17350 infix after the third character. */
17351 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17352 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17353 THUMB_VARIANT, do_##ae, do_##te }
17354 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17355 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17356 THUMB_VARIANT, do_##ae, do_##te }
17357 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17358 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17359 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17360 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17361 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17362 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17363 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17364 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17366 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17367 appear in the condition table. */
17368 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17369 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17370 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17372 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17373 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17374 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17375 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17376 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17377 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17378 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17379 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17380 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17381 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17382 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17383 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17384 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17385 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17386 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17387 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17388 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17389 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17390 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17391 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17393 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17394 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17395 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17396 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17398 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17399 field is still 0xE. Many of the Thumb variants can be executed
17400 conditionally, so this is checked separately. */
17401 #define TUE(mnem, op, top, nops, ops, ae, te) \
17402 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17403 THUMB_VARIANT, do_##ae, do_##te }
17405 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17406 condition code field. */
17407 #define TUF(mnem, op, top, nops, ops, ae, te) \
17408 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17409 THUMB_VARIANT, do_##ae, do_##te }
17411 /* ARM-only variants of all the above. */
17412 #define CE(mnem, op, nops, ops, ae) \
17413 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17415 #define C3(mnem, op, nops, ops, ae) \
17416 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17418 /* Legacy mnemonics that always have conditional infix after the third
17420 #define CL(mnem, op, nops, ops, ae) \
17421 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17422 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17424 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17425 #define cCE(mnem, op, nops, ops, ae) \
17426 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17428 /* Legacy coprocessor instructions where conditional infix and conditional
17429 suffix are ambiguous. For consistency this includes all FPA instructions,
17430 not just the potentially ambiguous ones. */
17431 #define cCL(mnem, op, nops, ops, ae) \
17432 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17433 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17435 /* Coprocessor, takes either a suffix or a position-3 infix
17436 (for an FPA corner case). */
17437 #define C3E(mnem, op, nops, ops, ae) \
17438 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17439 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17441 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17442 { m1 #m2 m3, OPS##nops ops, \
17443 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17444 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17446 #define CM(m1, m2, op, nops, ops, ae) \
17447 xCM_ (m1, , m2, op, nops, ops, ae), \
17448 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17449 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17450 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17451 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17452 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17453 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17454 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17455 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17456 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17457 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17458 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17459 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17460 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17461 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17462 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17463 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17464 xCM_ (m1, le, m2, op, nops, ops, ae), \
17465 xCM_ (m1, al, m2, op, nops, ops, ae)
17467 #define UE(mnem, op, nops, ops, ae) \
17468 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17470 #define UF(mnem, op, nops, ops, ae) \
17471 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17473 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17474 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17475 use the same encoding function for each. */
17476 #define NUF(mnem, op, nops, ops, enc) \
17477 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17478 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17480 /* Neon data processing, version which indirects through neon_enc_tab for
17481 the various overloaded versions of opcodes. */
17482 #define nUF(mnem, op, nops, ops, enc) \
17483 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17484 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17486 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17488 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17489 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17490 THUMB_VARIANT, do_##enc, do_##enc }
17492 #define NCE(mnem, op, nops, ops, enc) \
17493 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17495 #define NCEF(mnem, op, nops, ops, enc) \
17496 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17498 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17499 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17500 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17501 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17503 #define nCE(mnem, op, nops, ops, enc) \
17504 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17506 #define nCEF(mnem, op, nops, ops, enc) \
17507 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17511 static const struct asm_opcode insns[] =
17513 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17514 #define THUMB_VARIANT &arm_ext_v4t
17515 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17516 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17517 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17518 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17519 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17520 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17521 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17522 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17523 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17524 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17525 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17526 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17527 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17528 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17529 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17530 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17532 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17533 for setting PSR flag bits. They are obsolete in V6 and do not
17534 have Thumb equivalents. */
17535 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17536 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17537 CL("tstp", 110f000, 2, (RR, SH), cmp),
17538 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17539 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17540 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17541 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17542 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17543 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17545 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17546 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17547 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17548 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17550 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17551 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17552 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17554 OP_ADDRGLDR),ldst, t_ldst),
17555 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17557 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17558 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17559 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17560 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17561 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17562 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17564 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17565 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17566 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17567 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17570 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17571 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17572 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17574 /* Thumb-compatibility pseudo ops. */
17575 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17576 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17577 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17578 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17579 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17580 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17581 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17582 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17583 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17584 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17585 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17586 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17588 /* These may simplify to neg. */
17589 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17590 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17592 #undef THUMB_VARIANT
17593 #define THUMB_VARIANT & arm_ext_v6
17595 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17597 /* V1 instructions with no Thumb analogue prior to V6T2. */
17598 #undef THUMB_VARIANT
17599 #define THUMB_VARIANT & arm_ext_v6t2
17601 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17602 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17603 CL("teqp", 130f000, 2, (RR, SH), cmp),
17605 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17606 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17607 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17608 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17610 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17611 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17613 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17614 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17616 /* V1 instructions with no Thumb analogue at all. */
17617 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17618 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17620 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17621 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17622 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17623 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17624 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17625 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17626 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17627 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17630 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17631 #undef THUMB_VARIANT
17632 #define THUMB_VARIANT & arm_ext_v4t
17634 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17635 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17637 #undef THUMB_VARIANT
17638 #define THUMB_VARIANT & arm_ext_v6t2
17640 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17641 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17643 /* Generic coprocessor instructions. */
17644 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17645 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17646 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17647 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17648 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17649 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17650 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17653 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17655 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17656 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17659 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17660 #undef THUMB_VARIANT
17661 #define THUMB_VARIANT & arm_ext_msr
17663 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17664 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17667 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17668 #undef THUMB_VARIANT
17669 #define THUMB_VARIANT & arm_ext_v6t2
17671 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17672 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17673 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17674 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17675 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17676 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17677 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17678 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17681 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17682 #undef THUMB_VARIANT
17683 #define THUMB_VARIANT & arm_ext_v4t
17685 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17686 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17687 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17688 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17689 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17690 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17693 #define ARM_VARIANT & arm_ext_v4t_5
17695 /* ARM Architecture 4T. */
17696 /* Note: bx (and blx) are required on V5, even if the processor does
17697 not support Thumb. */
17698 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17701 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17702 #undef THUMB_VARIANT
17703 #define THUMB_VARIANT & arm_ext_v5t
17705 /* Note: blx has 2 variants; the .value coded here is for
17706 BLX(2). Only this variant has conditional execution. */
17707 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17708 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17710 #undef THUMB_VARIANT
17711 #define THUMB_VARIANT & arm_ext_v6t2
17713 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17714 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17715 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17716 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17717 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17718 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17719 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17720 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17723 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17724 #undef THUMB_VARIANT
17725 #define THUMB_VARIANT &arm_ext_v5exp
17727 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17728 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17729 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17730 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17732 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17733 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17735 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17736 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17737 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17738 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17740 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17741 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17742 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17743 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17745 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17746 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17748 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17749 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17750 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17751 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17754 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17755 #undef THUMB_VARIANT
17756 #define THUMB_VARIANT &arm_ext_v6t2
17758 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17759 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17761 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17762 ADDRGLDRS), ldrd, t_ldstd),
17764 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17765 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17768 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17770 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17773 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17774 #undef THUMB_VARIANT
17775 #define THUMB_VARIANT & arm_ext_v6
17777 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17778 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17779 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17780 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17781 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17782 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17783 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17784 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17785 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17786 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17788 #undef THUMB_VARIANT
17789 #define THUMB_VARIANT & arm_ext_v6t2
17791 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17792 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17794 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17795 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17797 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17798 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17800 /* ARM V6 not included in V7M. */
17801 #undef THUMB_VARIANT
17802 #define THUMB_VARIANT & arm_ext_v6_notm
17803 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17804 UF(rfeib, 9900a00, 1, (RRw), rfe),
17805 UF(rfeda, 8100a00, 1, (RRw), rfe),
17806 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17807 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17808 UF(rfefa, 9900a00, 1, (RRw), rfe),
17809 UF(rfeea, 8100a00, 1, (RRw), rfe),
17810 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17811 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17812 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17813 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17814 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17816 /* ARM V6 not included in V7M (eg. integer SIMD). */
17817 #undef THUMB_VARIANT
17818 #define THUMB_VARIANT & arm_ext_v6_dsp
17819 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17820 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17821 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17822 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17823 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17824 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17825 /* Old name for QASX. */
17826 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17827 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17828 /* Old name for QSAX. */
17829 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17830 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17831 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17832 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17833 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17834 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17835 /* Old name for SASX. */
17836 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17837 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17838 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17839 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17840 /* Old name for SHASX. */
17841 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17842 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17843 /* Old name for SHSAX. */
17844 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17845 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17846 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17847 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17848 /* Old name for SSAX. */
17849 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17850 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17851 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17852 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17853 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17854 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17855 /* Old name for UASX. */
17856 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17857 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17858 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17859 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17860 /* Old name for UHASX. */
17861 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17862 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17863 /* Old name for UHSAX. */
17864 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17865 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17866 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17867 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17868 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17869 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17870 /* Old name for UQASX. */
17871 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17872 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17873 /* Old name for UQSAX. */
17874 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17875 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17876 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17877 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17878 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17879 /* Old name for USAX. */
17880 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17881 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17882 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17883 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17884 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17885 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17886 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17887 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17888 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17889 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17890 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17891 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17892 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17893 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17894 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17895 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17896 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17897 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17898 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17899 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17900 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17901 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17902 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17903 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17904 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17905 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17906 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17907 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17908 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17909 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17910 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17911 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17912 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17913 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17916 #define ARM_VARIANT & arm_ext_v6k
17917 #undef THUMB_VARIANT
17918 #define THUMB_VARIANT & arm_ext_v6k
17920 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17921 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17922 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17923 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17925 #undef THUMB_VARIANT
17926 #define THUMB_VARIANT & arm_ext_v6_notm
17927 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17929 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17930 RRnpcb), strexd, t_strexd),
17932 #undef THUMB_VARIANT
17933 #define THUMB_VARIANT & arm_ext_v6t2
17934 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17936 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17938 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17940 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17942 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17945 #define ARM_VARIANT & arm_ext_sec
17946 #undef THUMB_VARIANT
17947 #define THUMB_VARIANT & arm_ext_sec
17949 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17952 #define ARM_VARIANT & arm_ext_virt
17953 #undef THUMB_VARIANT
17954 #define THUMB_VARIANT & arm_ext_virt
17956 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17957 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17960 #define ARM_VARIANT & arm_ext_v6t2
17961 #undef THUMB_VARIANT
17962 #define THUMB_VARIANT & arm_ext_v6t2
17964 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17965 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17966 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17967 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17969 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17970 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17971 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17972 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17974 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17975 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17976 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17977 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17979 /* Thumb-only instructions. */
17981 #define ARM_VARIANT NULL
17982 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17983 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17985 /* ARM does not really have an IT instruction, so always allow it.
17986 The opcode is copied from Thumb in order to allow warnings in
17987 -mimplicit-it=[never | arm] modes. */
17989 #define ARM_VARIANT & arm_ext_v1
17991 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17992 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17993 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17994 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17995 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17996 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17997 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17998 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17999 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18000 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18001 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18002 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18003 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18004 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18005 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18006 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18007 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18008 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18010 /* Thumb2 only instructions. */
18012 #define ARM_VARIANT NULL
18014 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18015 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18016 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18017 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18018 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18019 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18021 /* Hardware division instructions. */
18023 #define ARM_VARIANT & arm_ext_adiv
18024 #undef THUMB_VARIANT
18025 #define THUMB_VARIANT & arm_ext_div
18027 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18028 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18030 /* ARM V6M/V7 instructions. */
18032 #define ARM_VARIANT & arm_ext_barrier
18033 #undef THUMB_VARIANT
18034 #define THUMB_VARIANT & arm_ext_barrier
18036 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18037 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18038 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18040 /* ARM V7 instructions. */
18042 #define ARM_VARIANT & arm_ext_v7
18043 #undef THUMB_VARIANT
18044 #define THUMB_VARIANT & arm_ext_v7
18046 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18047 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18050 #define ARM_VARIANT & arm_ext_mp
18051 #undef THUMB_VARIANT
18052 #define THUMB_VARIANT & arm_ext_mp
18054 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18056 /* AArchv8 instructions. */
18058 #define ARM_VARIANT & arm_ext_v8
18059 #undef THUMB_VARIANT
18060 #define THUMB_VARIANT & arm_ext_v8
18062 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18063 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18064 TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18065 TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18067 TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18068 TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18069 TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18071 TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18073 TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18075 TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18077 TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18078 TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18079 TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18080 TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18081 TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18082 TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18084 /* ARMv8 T32 only. */
18086 #define ARM_VARIANT NULL
18087 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18088 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18089 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18091 /* FP for ARMv8. */
18093 #define ARM_VARIANT & fpu_vfp_ext_armv8
18094 #undef THUMB_VARIANT
18095 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18097 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18098 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18099 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18100 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18101 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18102 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18105 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18106 #undef THUMB_VARIANT
18107 #define THUMB_VARIANT NULL
18109 cCE("wfs", e200110, 1, (RR), rd),
18110 cCE("rfs", e300110, 1, (RR), rd),
18111 cCE("wfc", e400110, 1, (RR), rd),
18112 cCE("rfc", e500110, 1, (RR), rd),
18114 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18115 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18116 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18117 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18119 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18120 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18121 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18122 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18124 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18125 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18126 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18127 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18128 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18129 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18130 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18131 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18132 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18133 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18134 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18135 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18137 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18138 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18139 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18140 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18141 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18142 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18143 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18144 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18145 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18146 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18147 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18148 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18150 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18151 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18152 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18153 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18154 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18155 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18156 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18157 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18158 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18159 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18160 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18161 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18163 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18164 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18165 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18166 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18167 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18168 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18169 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18170 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18171 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18172 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18173 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18174 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18176 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18177 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18178 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18179 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18180 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18181 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18182 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18183 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18184 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18185 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18186 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18187 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18189 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18190 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18191 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18192 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18193 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18194 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18195 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18196 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18197 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18198 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18199 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18200 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18202 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18203 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18204 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18205 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18206 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18207 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18208 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18209 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18210 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18211 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18212 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18213 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18215 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18216 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18217 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18218 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18219 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18220 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18221 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18222 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18223 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18224 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18225 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18226 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18228 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18229 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18230 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18231 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18232 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18233 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18234 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18235 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18236 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18237 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18238 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18239 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18241 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18242 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18243 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18244 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18245 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18246 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18247 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18248 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18249 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18250 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18251 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18252 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18254 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18255 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18256 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18257 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18258 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18259 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18260 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18261 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18262 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18263 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18264 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18265 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18267 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18268 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18269 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18270 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18271 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18272 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18273 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18274 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18275 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18276 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18277 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18278 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18280 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18281 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18282 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18283 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18284 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18285 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18286 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18287 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18288 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18289 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18290 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18291 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18293 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18294 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18295 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18296 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18297 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18298 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18299 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18300 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18301 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18302 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18303 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18304 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18306 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18307 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18308 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18309 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18310 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18311 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18312 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18313 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18314 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18315 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18316 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18317 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18319 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18320 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18321 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18322 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18323 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18324 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18325 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18326 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18327 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18328 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18329 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18330 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18332 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18333 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18334 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18335 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18336 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18337 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18338 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18339 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18340 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18341 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18342 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18343 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18345 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18346 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18347 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18348 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18349 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18350 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18351 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18352 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18353 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18354 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18355 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18356 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18358 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18359 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18360 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18361 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18362 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18363 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18364 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18365 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18366 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18367 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18368 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18369 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18371 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18372 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18373 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18374 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18375 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18376 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18377 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18378 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18379 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18380 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18381 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18382 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18384 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18385 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18386 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18387 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18388 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18389 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18390 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18391 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18392 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18393 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18394 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18395 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18397 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18398 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18399 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18400 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18401 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18402 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18403 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18404 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18405 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18406 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18407 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18408 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18410 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18411 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18412 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18413 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18414 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18415 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18416 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18417 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18418 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18419 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18420 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18421 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18423 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18424 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18425 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18426 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18427 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18428 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18429 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18430 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18431 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18432 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18433 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18434 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18436 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18437 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18438 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18439 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18440 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18441 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18442 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18443 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18444 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18445 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18446 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18447 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18449 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18450 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18451 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18452 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18453 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18454 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18455 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18456 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18457 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18458 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18459 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18460 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18462 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18463 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18464 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18465 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18466 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18467 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18468 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18469 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18470 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18471 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18472 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18473 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18475 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18476 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18477 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18478 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18479 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18480 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18481 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18482 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18483 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18484 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18485 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18486 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18488 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18489 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18490 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18491 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18492 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18493 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18494 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18495 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18496 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18497 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18498 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18499 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18501 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18502 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18503 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18504 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18506 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18507 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18508 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18509 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18510 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18511 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18512 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18513 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18514 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18515 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18516 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18517 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18519 /* The implementation of the FIX instruction is broken on some
18520 assemblers, in that it accepts a precision specifier as well as a
18521 rounding specifier, despite the fact that this is meaningless.
18522 To be more compatible, we accept it as well, though of course it
18523 does not set any bits. */
18524 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18525 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18526 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18527 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18528 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18529 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18530 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18531 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18532 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18533 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18534 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18535 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18536 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18538 /* Instructions that were new with the real FPA, call them V2. */
18540 #define ARM_VARIANT & fpu_fpa_ext_v2
18542 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18543 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18544 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18545 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18546 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18547 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18550 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18552 /* Moves and type conversions. */
18553 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18554 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18555 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18556 cCE("fmstat", ef1fa10, 0, (), noargs),
18557 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18558 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18559 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18560 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18561 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18562 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18563 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18564 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18565 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18566 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18568 /* Memory operations. */
18569 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18570 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18571 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18572 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18573 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18574 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18575 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18576 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18577 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18578 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18579 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18580 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18581 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18582 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18583 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18584 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18585 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18586 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18588 /* Monadic operations. */
18589 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18590 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18591 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18593 /* Dyadic operations. */
18594 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18595 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18596 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18597 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18598 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18599 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18600 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18601 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18602 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18605 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18606 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18607 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18608 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18610 /* Double precision load/store are still present on single precision
18611 implementations. */
18612 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18613 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18614 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18615 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18616 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18617 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18618 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18619 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18620 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18621 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18624 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18626 /* Moves and type conversions. */
18627 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18628 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18629 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18630 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18631 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18632 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18633 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18634 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18635 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18636 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18637 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18638 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18639 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18641 /* Monadic operations. */
18642 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18643 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18644 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18646 /* Dyadic operations. */
18647 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18648 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18649 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18650 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18651 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18652 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18653 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18654 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18655 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18658 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18659 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18660 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18661 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18664 #define ARM_VARIANT & fpu_vfp_ext_v2
18666 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18667 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18668 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18669 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18671 /* Instructions which may belong to either the Neon or VFP instruction sets.
18672 Individual encoder functions perform additional architecture checks. */
18674 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18675 #undef THUMB_VARIANT
18676 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18678 /* These mnemonics are unique to VFP. */
18679 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18680 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18681 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18682 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18683 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18684 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18685 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18686 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18687 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18688 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18690 /* Mnemonics shared by Neon and VFP. */
18691 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18692 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18693 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18695 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18696 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18698 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18699 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18701 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18702 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18703 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18704 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18705 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18706 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18707 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18708 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18710 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18711 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18712 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18713 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18716 /* NOTE: All VMOV encoding is special-cased! */
18717 NCE(vmov, 0, 1, (VMOV), neon_mov),
18718 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18720 #undef THUMB_VARIANT
18721 #define THUMB_VARIANT & fpu_neon_ext_v1
18723 #define ARM_VARIANT & fpu_neon_ext_v1
18725 /* Data processing with three registers of the same length. */
18726 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18727 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18728 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18729 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18730 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18731 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18732 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18733 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18734 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18735 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18736 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18737 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18738 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18739 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18740 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18741 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18742 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18743 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18744 /* If not immediate, fall back to neon_dyadic_i64_su.
18745 shl_imm should accept I8 I16 I32 I64,
18746 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18747 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18748 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18749 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18750 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18751 /* Logic ops, types optional & ignored. */
18752 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18753 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18754 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18755 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18756 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18757 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18758 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18759 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18760 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18761 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18762 /* Bitfield ops, untyped. */
18763 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18764 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18765 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18766 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18767 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18768 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18769 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18770 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18771 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18772 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18773 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18774 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18775 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18776 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18777 back to neon_dyadic_if_su. */
18778 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18779 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18780 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18781 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18782 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18783 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18784 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18785 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18786 /* Comparison. Type I8 I16 I32 F32. */
18787 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18788 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18789 /* As above, D registers only. */
18790 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18791 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18792 /* Int and float variants, signedness unimportant. */
18793 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18794 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18795 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18796 /* Add/sub take types I8 I16 I32 I64 F32. */
18797 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18798 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18799 /* vtst takes sizes 8, 16, 32. */
18800 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18801 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18802 /* VMUL takes I8 I16 I32 F32 P8. */
18803 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18804 /* VQD{R}MULH takes S16 S32. */
18805 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18806 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18807 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18808 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18809 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18810 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18811 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18812 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18813 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18814 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18815 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18816 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18817 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18818 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18819 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18820 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18822 /* Two address, int/float. Types S8 S16 S32 F32. */
18823 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18824 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18826 /* Data processing with two registers and a shift amount. */
18827 /* Right shifts, and variants with rounding.
18828 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18829 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18830 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18831 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18832 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18833 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18834 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18835 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18836 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18837 /* Shift and insert. Sizes accepted 8 16 32 64. */
18838 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18839 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18840 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18841 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18842 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18843 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18844 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18845 /* Right shift immediate, saturating & narrowing, with rounding variants.
18846 Types accepted S16 S32 S64 U16 U32 U64. */
18847 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18848 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18849 /* As above, unsigned. Types accepted S16 S32 S64. */
18850 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18851 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18852 /* Right shift narrowing. Types accepted I16 I32 I64. */
18853 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18854 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18855 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18856 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18857 /* CVT with optional immediate for fixed-point variant. */
18858 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18860 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18861 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18863 /* Data processing, three registers of different lengths. */
18864 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18865 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18866 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18867 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18868 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18869 /* If not scalar, fall back to neon_dyadic_long.
18870 Vector types as above, scalar types S16 S32 U16 U32. */
18871 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18872 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18873 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18874 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18875 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18876 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18877 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18878 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18879 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18880 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18881 /* Saturating doubling multiplies. Types S16 S32. */
18882 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18883 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18884 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18885 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18886 S16 S32 U16 U32. */
18887 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18889 /* Extract. Size 8. */
18890 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18891 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18893 /* Two registers, miscellaneous. */
18894 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18895 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18896 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18897 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18898 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18899 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18900 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18901 /* Vector replicate. Sizes 8 16 32. */
18902 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18903 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18904 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18905 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18906 /* VMOVN. Types I16 I32 I64. */
18907 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18908 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18909 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18910 /* VQMOVUN. Types S16 S32 S64. */
18911 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18912 /* VZIP / VUZP. Sizes 8 16 32. */
18913 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18914 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18915 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18916 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18917 /* VQABS / VQNEG. Types S8 S16 S32. */
18918 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18919 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18920 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18921 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18922 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18923 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18924 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18925 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18926 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18927 /* Reciprocal estimates. Types U32 F32. */
18928 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18929 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18930 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18931 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18932 /* VCLS. Types S8 S16 S32. */
18933 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18934 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18935 /* VCLZ. Types I8 I16 I32. */
18936 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18937 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18938 /* VCNT. Size 8. */
18939 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18940 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18941 /* Two address, untyped. */
18942 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18943 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18944 /* VTRN. Sizes 8 16 32. */
18945 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18946 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18948 /* Table lookup. Size 8. */
18949 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18950 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18952 #undef THUMB_VARIANT
18953 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18955 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18957 /* Neon element/structure load/store. */
18958 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18959 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18960 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18961 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18962 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18963 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18964 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18965 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18967 #undef THUMB_VARIANT
18968 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18970 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18971 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18972 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18973 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18974 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18975 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18976 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18977 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18978 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18979 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18981 #undef THUMB_VARIANT
18982 #define THUMB_VARIANT & fpu_vfp_ext_v3
18984 #define ARM_VARIANT & fpu_vfp_ext_v3
18986 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18987 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18988 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18989 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18990 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18991 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18992 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18993 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18994 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18997 #define ARM_VARIANT &fpu_vfp_ext_fma
18998 #undef THUMB_VARIANT
18999 #define THUMB_VARIANT &fpu_vfp_ext_fma
19000 /* Mnemonics shared by Neon and VFP. These are included in the
19001 VFP FMA variant; NEON and VFP FMA always includes the NEON
19002 FMA instructions. */
19003 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19004 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19005 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19006 the v form should always be used. */
19007 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19008 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19009 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19010 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19011 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19012 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19014 #undef THUMB_VARIANT
19016 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19018 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19019 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19020 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19021 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19022 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19023 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19024 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19025 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19028 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19030 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19031 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19032 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19033 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19034 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19035 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19036 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19037 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19038 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19039 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19040 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19041 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19042 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19043 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19044 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19045 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19046 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19047 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19048 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19049 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19050 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19051 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19052 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19053 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19054 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19055 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19056 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19057 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19058 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19059 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19060 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19061 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19062 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19063 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19064 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19065 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19066 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19067 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19068 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19069 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19070 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19071 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19072 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19073 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19074 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19075 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19076 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19077 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19078 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19079 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19080 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19081 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19082 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19083 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19084 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19085 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19086 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19087 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19088 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19089 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19090 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19091 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19092 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19093 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19094 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19095 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19096 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19097 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19098 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19099 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19100 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19101 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19102 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19103 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19104 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19105 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19106 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19107 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19108 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19109 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19110 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19111 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19112 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19113 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19114 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19115 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19116 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19117 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19118 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19119 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19120 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19121 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19122 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19123 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19124 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19125 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19126 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19127 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19128 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19129 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19130 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19131 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19132 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19133 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19134 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19135 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19136 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19137 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19138 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19139 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19140 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19141 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19142 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19143 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19144 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19145 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19146 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19147 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19148 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19149 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19150 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19151 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19152 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19153 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19154 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19155 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19156 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19157 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19158 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19159 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19160 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19161 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19162 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19163 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19164 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19165 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19166 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19167 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19168 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19169 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19170 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19171 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19172 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19173 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19174 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19175 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19176 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19177 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19178 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19179 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19180 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19181 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19182 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19183 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19184 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19185 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19186 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19187 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19188 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19189 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19190 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19191 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19194 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19196 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19197 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19198 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19199 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19200 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19201 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19202 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19203 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19204 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19205 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19206 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19207 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19208 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19209 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19210 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19211 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19212 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19213 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19214 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19215 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19216 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19217 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19218 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19219 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19220 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19221 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19222 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19223 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19224 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19225 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19226 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19227 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19228 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19229 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19230 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19231 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19232 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19233 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19234 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19235 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19236 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19237 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19238 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19239 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19240 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19241 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19242 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19243 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19244 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19245 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19246 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19247 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19248 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19249 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19250 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19251 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19252 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19255 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19257 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19258 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19259 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19260 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19261 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19262 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19263 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19264 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19265 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19266 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19267 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19268 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19269 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19270 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19271 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19272 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19273 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19274 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19275 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19276 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19277 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19278 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19279 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19280 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19281 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19282 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19283 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19284 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19285 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19286 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19287 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19288 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19289 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19290 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19291 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19292 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19293 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19294 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19295 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19296 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19297 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19298 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19299 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19300 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19301 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19302 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19303 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19304 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19305 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19306 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19307 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19308 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19309 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19310 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19311 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19312 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19313 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19314 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19315 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19316 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19317 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19318 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19319 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19320 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19321 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19322 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19323 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19324 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19325 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19326 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19327 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19328 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19329 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19330 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19331 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19332 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19335 #undef THUMB_VARIANT
19362 /* MD interface: bits in the object file. */
19364 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19365 for use in the a.out file, and stores them in the array pointed to by buf.
19366 This knows about the endian-ness of the target machine and does
19367 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19368 2 (short) and 4 (long) Floating numbers are put out as a series of
19369 LITTLENUMS (shorts, here at least). */
19372 md_number_to_chars (char * buf, valueT val, int n)
19374 if (target_big_endian)
19375 number_to_chars_bigendian (buf, val, n);
19377 number_to_chars_littleendian (buf, val, n);
19381 md_chars_to_number (char * buf, int n)
19384 unsigned char * where = (unsigned char *) buf;
19386 if (target_big_endian)
19391 result |= (*where++ & 255);
19399 result |= (where[n] & 255);
19406 /* MD interface: Sections. */
19408 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19409 that an rs_machine_dependent frag may reach. */
19412 arm_frag_max_var (fragS *fragp)
19414 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19415 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19417 Note that we generate relaxable instructions even for cases that don't
19418 really need it, like an immediate that's a trivial constant. So we're
19419 overestimating the instruction size for some of those cases. Rather
19420 than putting more intelligence here, it would probably be better to
19421 avoid generating a relaxation frag in the first place when it can be
19422 determined up front that a short instruction will suffice. */
19424 gas_assert (fragp->fr_type == rs_machine_dependent);
19428 /* Estimate the size of a frag before relaxing. Assume everything fits in
19432 md_estimate_size_before_relax (fragS * fragp,
19433 segT segtype ATTRIBUTE_UNUSED)
19439 /* Convert a machine dependent frag. */
19442 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19444 unsigned long insn;
19445 unsigned long old_op;
19453 buf = fragp->fr_literal + fragp->fr_fix;
19455 old_op = bfd_get_16(abfd, buf);
19456 if (fragp->fr_symbol)
19458 exp.X_op = O_symbol;
19459 exp.X_add_symbol = fragp->fr_symbol;
19463 exp.X_op = O_constant;
19465 exp.X_add_number = fragp->fr_offset;
19466 opcode = fragp->fr_subtype;
19469 case T_MNEM_ldr_pc:
19470 case T_MNEM_ldr_pc2:
19471 case T_MNEM_ldr_sp:
19472 case T_MNEM_str_sp:
19479 if (fragp->fr_var == 4)
19481 insn = THUMB_OP32 (opcode);
19482 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19484 insn |= (old_op & 0x700) << 4;
19488 insn |= (old_op & 7) << 12;
19489 insn |= (old_op & 0x38) << 13;
19491 insn |= 0x00000c00;
19492 put_thumb32_insn (buf, insn);
19493 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19497 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19499 pc_rel = (opcode == T_MNEM_ldr_pc2);
19502 if (fragp->fr_var == 4)
19504 insn = THUMB_OP32 (opcode);
19505 insn |= (old_op & 0xf0) << 4;
19506 put_thumb32_insn (buf, insn);
19507 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19511 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19512 exp.X_add_number -= 4;
19520 if (fragp->fr_var == 4)
19522 int r0off = (opcode == T_MNEM_mov
19523 || opcode == T_MNEM_movs) ? 0 : 8;
19524 insn = THUMB_OP32 (opcode);
19525 insn = (insn & 0xe1ffffff) | 0x10000000;
19526 insn |= (old_op & 0x700) << r0off;
19527 put_thumb32_insn (buf, insn);
19528 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19532 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19537 if (fragp->fr_var == 4)
19539 insn = THUMB_OP32(opcode);
19540 put_thumb32_insn (buf, insn);
19541 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19544 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19548 if (fragp->fr_var == 4)
19550 insn = THUMB_OP32(opcode);
19551 insn |= (old_op & 0xf00) << 14;
19552 put_thumb32_insn (buf, insn);
19553 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19556 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19559 case T_MNEM_add_sp:
19560 case T_MNEM_add_pc:
19561 case T_MNEM_inc_sp:
19562 case T_MNEM_dec_sp:
19563 if (fragp->fr_var == 4)
19565 /* ??? Choose between add and addw. */
19566 insn = THUMB_OP32 (opcode);
19567 insn |= (old_op & 0xf0) << 4;
19568 put_thumb32_insn (buf, insn);
19569 if (opcode == T_MNEM_add_pc)
19570 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19572 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19575 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19583 if (fragp->fr_var == 4)
19585 insn = THUMB_OP32 (opcode);
19586 insn |= (old_op & 0xf0) << 4;
19587 insn |= (old_op & 0xf) << 16;
19588 put_thumb32_insn (buf, insn);
19589 if (insn & (1 << 20))
19590 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19592 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19595 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19601 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19602 (enum bfd_reloc_code_real) reloc_type);
19603 fixp->fx_file = fragp->fr_file;
19604 fixp->fx_line = fragp->fr_line;
19605 fragp->fr_fix += fragp->fr_var;
19608 /* Return the size of a relaxable immediate operand instruction.
19609 SHIFT and SIZE specify the form of the allowable immediate. */
19611 relax_immediate (fragS *fragp, int size, int shift)
19617 /* ??? Should be able to do better than this. */
19618 if (fragp->fr_symbol)
19621 low = (1 << shift) - 1;
19622 mask = (1 << (shift + size)) - (1 << shift);
19623 offset = fragp->fr_offset;
19624 /* Force misaligned offsets to 32-bit variant. */
19627 if (offset & ~mask)
19632 /* Get the address of a symbol during relaxation. */
19634 relaxed_symbol_addr (fragS *fragp, long stretch)
19640 sym = fragp->fr_symbol;
19641 sym_frag = symbol_get_frag (sym);
19642 know (S_GET_SEGMENT (sym) != absolute_section
19643 || sym_frag == &zero_address_frag);
19644 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19646 /* If frag has yet to be reached on this pass, assume it will
19647 move by STRETCH just as we did. If this is not so, it will
19648 be because some frag between grows, and that will force
19652 && sym_frag->relax_marker != fragp->relax_marker)
19656 /* Adjust stretch for any alignment frag. Note that if have
19657 been expanding the earlier code, the symbol may be
19658 defined in what appears to be an earlier frag. FIXME:
19659 This doesn't handle the fr_subtype field, which specifies
19660 a maximum number of bytes to skip when doing an
19662 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19664 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19667 stretch = - ((- stretch)
19668 & ~ ((1 << (int) f->fr_offset) - 1));
19670 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19682 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19685 relax_adr (fragS *fragp, asection *sec, long stretch)
19690 /* Assume worst case for symbols not known to be in the same section. */
19691 if (fragp->fr_symbol == NULL
19692 || !S_IS_DEFINED (fragp->fr_symbol)
19693 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19694 || S_IS_WEAK (fragp->fr_symbol))
19697 val = relaxed_symbol_addr (fragp, stretch);
19698 addr = fragp->fr_address + fragp->fr_fix;
19699 addr = (addr + 4) & ~3;
19700 /* Force misaligned targets to 32-bit variant. */
19704 if (val < 0 || val > 1020)
19709 /* Return the size of a relaxable add/sub immediate instruction. */
19711 relax_addsub (fragS *fragp, asection *sec)
19716 buf = fragp->fr_literal + fragp->fr_fix;
19717 op = bfd_get_16(sec->owner, buf);
19718 if ((op & 0xf) == ((op >> 4) & 0xf))
19719 return relax_immediate (fragp, 8, 0);
19721 return relax_immediate (fragp, 3, 0);
19725 /* Return the size of a relaxable branch instruction. BITS is the
19726 size of the offset field in the narrow instruction. */
19729 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19735 /* Assume worst case for symbols not known to be in the same section. */
19736 if (!S_IS_DEFINED (fragp->fr_symbol)
19737 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19738 || S_IS_WEAK (fragp->fr_symbol))
19742 if (S_IS_DEFINED (fragp->fr_symbol)
19743 && ARM_IS_FUNC (fragp->fr_symbol))
19746 /* PR 12532. Global symbols with default visibility might
19747 be preempted, so do not relax relocations to them. */
19748 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19749 && (! S_IS_LOCAL (fragp->fr_symbol)))
19753 val = relaxed_symbol_addr (fragp, stretch);
19754 addr = fragp->fr_address + fragp->fr_fix + 4;
19757 /* Offset is a signed value *2 */
19759 if (val >= limit || val < -limit)
19765 /* Relax a machine dependent frag. This returns the amount by which
19766 the current size of the frag should change. */
19769 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19774 oldsize = fragp->fr_var;
19775 switch (fragp->fr_subtype)
19777 case T_MNEM_ldr_pc2:
19778 newsize = relax_adr (fragp, sec, stretch);
19780 case T_MNEM_ldr_pc:
19781 case T_MNEM_ldr_sp:
19782 case T_MNEM_str_sp:
19783 newsize = relax_immediate (fragp, 8, 2);
19787 newsize = relax_immediate (fragp, 5, 2);
19791 newsize = relax_immediate (fragp, 5, 1);
19795 newsize = relax_immediate (fragp, 5, 0);
19798 newsize = relax_adr (fragp, sec, stretch);
19804 newsize = relax_immediate (fragp, 8, 0);
19807 newsize = relax_branch (fragp, sec, 11, stretch);
19810 newsize = relax_branch (fragp, sec, 8, stretch);
19812 case T_MNEM_add_sp:
19813 case T_MNEM_add_pc:
19814 newsize = relax_immediate (fragp, 8, 2);
19816 case T_MNEM_inc_sp:
19817 case T_MNEM_dec_sp:
19818 newsize = relax_immediate (fragp, 7, 2);
19824 newsize = relax_addsub (fragp, sec);
19830 fragp->fr_var = newsize;
19831 /* Freeze wide instructions that are at or before the same location as
19832 in the previous pass. This avoids infinite loops.
19833 Don't freeze them unconditionally because targets may be artificially
19834 misaligned by the expansion of preceding frags. */
19835 if (stretch <= 0 && newsize > 2)
19837 md_convert_frag (sec->owner, sec, fragp);
19841 return newsize - oldsize;
19844 /* Round up a section size to the appropriate boundary. */
19847 md_section_align (segT segment ATTRIBUTE_UNUSED,
19850 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19851 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19853 /* For a.out, force the section size to be aligned. If we don't do
19854 this, BFD will align it for us, but it will not write out the
19855 final bytes of the section. This may be a bug in BFD, but it is
19856 easier to fix it here since that is how the other a.out targets
19860 align = bfd_get_section_alignment (stdoutput, segment);
19861 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19868 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19869 of an rs_align_code fragment. */
19872 arm_handle_align (fragS * fragP)
19874 static char const arm_noop[2][2][4] =
19877 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19878 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19881 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19882 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19885 static char const thumb_noop[2][2][2] =
19888 {0xc0, 0x46}, /* LE */
19889 {0x46, 0xc0}, /* BE */
19892 {0x00, 0xbf}, /* LE */
19893 {0xbf, 0x00} /* BE */
19896 static char const wide_thumb_noop[2][4] =
19897 { /* Wide Thumb-2 */
19898 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19899 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19902 unsigned bytes, fix, noop_size;
19905 const char *narrow_noop = NULL;
19910 if (fragP->fr_type != rs_align_code)
19913 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19914 p = fragP->fr_literal + fragP->fr_fix;
19917 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19918 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19920 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19922 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19924 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19926 narrow_noop = thumb_noop[1][target_big_endian];
19927 noop = wide_thumb_noop[target_big_endian];
19930 noop = thumb_noop[0][target_big_endian];
19938 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19939 [target_big_endian];
19946 fragP->fr_var = noop_size;
19948 if (bytes & (noop_size - 1))
19950 fix = bytes & (noop_size - 1);
19952 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19954 memset (p, 0, fix);
19961 if (bytes & noop_size)
19963 /* Insert a narrow noop. */
19964 memcpy (p, narrow_noop, noop_size);
19966 bytes -= noop_size;
19970 /* Use wide noops for the remainder */
19974 while (bytes >= noop_size)
19976 memcpy (p, noop, noop_size);
19978 bytes -= noop_size;
19982 fragP->fr_fix += fix;
19985 /* Called from md_do_align. Used to create an alignment
19986 frag in a code section. */
19989 arm_frag_align_code (int n, int max)
19993 /* We assume that there will never be a requirement
19994 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19995 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20000 _("alignments greater than %d bytes not supported in .text sections."),
20001 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20002 as_fatal ("%s", err_msg);
20005 p = frag_var (rs_align_code,
20006 MAX_MEM_FOR_RS_ALIGN_CODE,
20008 (relax_substateT) max,
20015 /* Perform target specific initialisation of a frag.
20016 Note - despite the name this initialisation is not done when the frag
20017 is created, but only when its type is assigned. A frag can be created
20018 and used a long time before its type is set, so beware of assuming that
20019 this initialisationis performed first. */
20023 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20025 /* Record whether this frag is in an ARM or a THUMB area. */
20026 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20029 #else /* OBJ_ELF is defined. */
20031 arm_init_frag (fragS * fragP, int max_chars)
20033 /* If the current ARM vs THUMB mode has not already
20034 been recorded into this frag then do so now. */
20035 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20037 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20039 /* Record a mapping symbol for alignment frags. We will delete this
20040 later if the alignment ends up empty. */
20041 switch (fragP->fr_type)
20044 case rs_align_test:
20046 mapping_state_2 (MAP_DATA, max_chars);
20048 case rs_align_code:
20049 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20057 /* When we change sections we need to issue a new mapping symbol. */
20060 arm_elf_change_section (void)
20062 /* Link an unlinked unwind index table section to the .text section. */
20063 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20064 && elf_linked_to_section (now_seg) == NULL)
20065 elf_linked_to_section (now_seg) = text_section;
20069 arm_elf_section_type (const char * str, size_t len)
20071 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20072 return SHT_ARM_EXIDX;
20077 /* Code to deal with unwinding tables. */
20079 static void add_unwind_adjustsp (offsetT);
20081 /* Generate any deferred unwind frame offset. */
20084 flush_pending_unwind (void)
20088 offset = unwind.pending_offset;
20089 unwind.pending_offset = 0;
20091 add_unwind_adjustsp (offset);
20094 /* Add an opcode to this list for this function. Two-byte opcodes should
20095 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20099 add_unwind_opcode (valueT op, int length)
20101 /* Add any deferred stack adjustment. */
20102 if (unwind.pending_offset)
20103 flush_pending_unwind ();
20105 unwind.sp_restored = 0;
20107 if (unwind.opcode_count + length > unwind.opcode_alloc)
20109 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20110 if (unwind.opcodes)
20111 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20112 unwind.opcode_alloc);
20114 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20119 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20121 unwind.opcode_count++;
20125 /* Add unwind opcodes to adjust the stack pointer. */
20128 add_unwind_adjustsp (offsetT offset)
20132 if (offset > 0x200)
20134 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20139 /* Long form: 0xb2, uleb128. */
20140 /* This might not fit in a word so add the individual bytes,
20141 remembering the list is built in reverse order. */
20142 o = (valueT) ((offset - 0x204) >> 2);
20144 add_unwind_opcode (0, 1);
20146 /* Calculate the uleb128 encoding of the offset. */
20150 bytes[n] = o & 0x7f;
20156 /* Add the insn. */
20158 add_unwind_opcode (bytes[n - 1], 1);
20159 add_unwind_opcode (0xb2, 1);
20161 else if (offset > 0x100)
20163 /* Two short opcodes. */
20164 add_unwind_opcode (0x3f, 1);
20165 op = (offset - 0x104) >> 2;
20166 add_unwind_opcode (op, 1);
20168 else if (offset > 0)
20170 /* Short opcode. */
20171 op = (offset - 4) >> 2;
20172 add_unwind_opcode (op, 1);
20174 else if (offset < 0)
20177 while (offset > 0x100)
20179 add_unwind_opcode (0x7f, 1);
20182 op = ((offset - 4) >> 2) | 0x40;
20183 add_unwind_opcode (op, 1);
20187 /* Finish the list of unwind opcodes for this function. */
20189 finish_unwind_opcodes (void)
20193 if (unwind.fp_used)
20195 /* Adjust sp as necessary. */
20196 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20197 flush_pending_unwind ();
20199 /* After restoring sp from the frame pointer. */
20200 op = 0x90 | unwind.fp_reg;
20201 add_unwind_opcode (op, 1);
20204 flush_pending_unwind ();
20208 /* Start an exception table entry. If idx is nonzero this is an index table
20212 start_unwind_section (const segT text_seg, int idx)
20214 const char * text_name;
20215 const char * prefix;
20216 const char * prefix_once;
20217 const char * group_name;
20221 size_t sec_name_len;
20228 prefix = ELF_STRING_ARM_unwind;
20229 prefix_once = ELF_STRING_ARM_unwind_once;
20230 type = SHT_ARM_EXIDX;
20234 prefix = ELF_STRING_ARM_unwind_info;
20235 prefix_once = ELF_STRING_ARM_unwind_info_once;
20236 type = SHT_PROGBITS;
20239 text_name = segment_name (text_seg);
20240 if (streq (text_name, ".text"))
20243 if (strncmp (text_name, ".gnu.linkonce.t.",
20244 strlen (".gnu.linkonce.t.")) == 0)
20246 prefix = prefix_once;
20247 text_name += strlen (".gnu.linkonce.t.");
20250 prefix_len = strlen (prefix);
20251 text_len = strlen (text_name);
20252 sec_name_len = prefix_len + text_len;
20253 sec_name = (char *) xmalloc (sec_name_len + 1);
20254 memcpy (sec_name, prefix, prefix_len);
20255 memcpy (sec_name + prefix_len, text_name, text_len);
20256 sec_name[prefix_len + text_len] = '\0';
20262 /* Handle COMDAT group. */
20263 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20265 group_name = elf_group_name (text_seg);
20266 if (group_name == NULL)
20268 as_bad (_("Group section `%s' has no group signature"),
20269 segment_name (text_seg));
20270 ignore_rest_of_line ();
20273 flags |= SHF_GROUP;
20277 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20279 /* Set the section link for index tables. */
20281 elf_linked_to_section (now_seg) = text_seg;
20285 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20286 personality routine data. Returns zero, or the index table value for
20287 and inline entry. */
20290 create_unwind_entry (int have_data)
20295 /* The current word of data. */
20297 /* The number of bytes left in this word. */
20300 finish_unwind_opcodes ();
20302 /* Remember the current text section. */
20303 unwind.saved_seg = now_seg;
20304 unwind.saved_subseg = now_subseg;
20306 start_unwind_section (now_seg, 0);
20308 if (unwind.personality_routine == NULL)
20310 if (unwind.personality_index == -2)
20313 as_bad (_("handlerdata in cantunwind frame"));
20314 return 1; /* EXIDX_CANTUNWIND. */
20317 /* Use a default personality routine if none is specified. */
20318 if (unwind.personality_index == -1)
20320 if (unwind.opcode_count > 3)
20321 unwind.personality_index = 1;
20323 unwind.personality_index = 0;
20326 /* Space for the personality routine entry. */
20327 if (unwind.personality_index == 0)
20329 if (unwind.opcode_count > 3)
20330 as_bad (_("too many unwind opcodes for personality routine 0"));
20334 /* All the data is inline in the index table. */
20337 while (unwind.opcode_count > 0)
20339 unwind.opcode_count--;
20340 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20344 /* Pad with "finish" opcodes. */
20346 data = (data << 8) | 0xb0;
20353 /* We get two opcodes "free" in the first word. */
20354 size = unwind.opcode_count - 2;
20358 gas_assert (unwind.personality_index == -1);
20360 /* An extra byte is required for the opcode count. */
20361 size = unwind.opcode_count + 1;
20364 size = (size + 3) >> 2;
20366 as_bad (_("too many unwind opcodes"));
20368 frag_align (2, 0, 0);
20369 record_alignment (now_seg, 2);
20370 unwind.table_entry = expr_build_dot ();
20372 /* Allocate the table entry. */
20373 ptr = frag_more ((size << 2) + 4);
20374 /* PR 13449: Zero the table entries in case some of them are not used. */
20375 memset (ptr, 0, (size << 2) + 4);
20376 where = frag_now_fix () - ((size << 2) + 4);
20378 switch (unwind.personality_index)
20381 /* ??? Should this be a PLT generating relocation? */
20382 /* Custom personality routine. */
20383 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20384 BFD_RELOC_ARM_PREL31);
20389 /* Set the first byte to the number of additional words. */
20390 data = size > 0 ? size - 1 : 0;
20394 /* ABI defined personality routines. */
20396 /* Three opcodes bytes are packed into the first word. */
20403 /* The size and first two opcode bytes go in the first word. */
20404 data = ((0x80 + unwind.personality_index) << 8) | size;
20409 /* Should never happen. */
20413 /* Pack the opcodes into words (MSB first), reversing the list at the same
20415 while (unwind.opcode_count > 0)
20419 md_number_to_chars (ptr, data, 4);
20424 unwind.opcode_count--;
20426 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20429 /* Finish off the last word. */
20432 /* Pad with "finish" opcodes. */
20434 data = (data << 8) | 0xb0;
20436 md_number_to_chars (ptr, data, 4);
20441 /* Add an empty descriptor if there is no user-specified data. */
20442 ptr = frag_more (4);
20443 md_number_to_chars (ptr, 0, 4);
20450 /* Initialize the DWARF-2 unwind information for this procedure. */
20453 tc_arm_frame_initial_instructions (void)
20455 cfi_add_CFA_def_cfa (REG_SP, 0);
20457 #endif /* OBJ_ELF */
20459 /* Convert REGNAME to a DWARF-2 register number. */
20462 tc_arm_regname_to_dw2regnum (char *regname)
20464 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20474 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20478 exp.X_op = O_secrel;
20479 exp.X_add_symbol = symbol;
20480 exp.X_add_number = 0;
20481 emit_expr (&exp, size);
20485 /* MD interface: Symbol and relocation handling. */
20487 /* Return the address within the segment that a PC-relative fixup is
20488 relative to. For ARM, PC-relative fixups applied to instructions
20489 are generally relative to the location of the fixup plus 8 bytes.
20490 Thumb branches are offset by 4, and Thumb loads relative to PC
20491 require special handling. */
20494 md_pcrel_from_section (fixS * fixP, segT seg)
20496 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20498 /* If this is pc-relative and we are going to emit a relocation
20499 then we just want to put out any pipeline compensation that the linker
20500 will need. Otherwise we want to use the calculated base.
20501 For WinCE we skip the bias for externals as well, since this
20502 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20504 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20505 || (arm_force_relocation (fixP)
20507 && !S_IS_EXTERNAL (fixP->fx_addsy)
20513 switch (fixP->fx_r_type)
20515 /* PC relative addressing on the Thumb is slightly odd as the
20516 bottom two bits of the PC are forced to zero for the
20517 calculation. This happens *after* application of the
20518 pipeline offset. However, Thumb adrl already adjusts for
20519 this, so we need not do it again. */
20520 case BFD_RELOC_ARM_THUMB_ADD:
20523 case BFD_RELOC_ARM_THUMB_OFFSET:
20524 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20525 case BFD_RELOC_ARM_T32_ADD_PC12:
20526 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20527 return (base + 4) & ~3;
20529 /* Thumb branches are simply offset by +4. */
20530 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20531 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20532 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20533 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20534 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20537 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20539 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20540 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20541 && ARM_IS_FUNC (fixP->fx_addsy)
20542 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20543 base = fixP->fx_where + fixP->fx_frag->fr_address;
20546 /* BLX is like branches above, but forces the low two bits of PC to
20548 case BFD_RELOC_THUMB_PCREL_BLX:
20550 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20551 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20552 && THUMB_IS_FUNC (fixP->fx_addsy)
20553 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20554 base = fixP->fx_where + fixP->fx_frag->fr_address;
20555 return (base + 4) & ~3;
20557 /* ARM mode branches are offset by +8. However, the Windows CE
20558 loader expects the relocation not to take this into account. */
20559 case BFD_RELOC_ARM_PCREL_BLX:
20561 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20562 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20563 && ARM_IS_FUNC (fixP->fx_addsy)
20564 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20565 base = fixP->fx_where + fixP->fx_frag->fr_address;
20568 case BFD_RELOC_ARM_PCREL_CALL:
20570 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20571 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20572 && THUMB_IS_FUNC (fixP->fx_addsy)
20573 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20574 base = fixP->fx_where + fixP->fx_frag->fr_address;
20577 case BFD_RELOC_ARM_PCREL_BRANCH:
20578 case BFD_RELOC_ARM_PCREL_JUMP:
20579 case BFD_RELOC_ARM_PLT32:
20581 /* When handling fixups immediately, because we have already
20582 discovered the value of a symbol, or the address of the frag involved
20583 we must account for the offset by +8, as the OS loader will never see the reloc.
20584 see fixup_segment() in write.c
20585 The S_IS_EXTERNAL test handles the case of global symbols.
20586 Those need the calculated base, not just the pipe compensation the linker will need. */
20588 && fixP->fx_addsy != NULL
20589 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20590 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20598 /* ARM mode loads relative to PC are also offset by +8. Unlike
20599 branches, the Windows CE loader *does* expect the relocation
20600 to take this into account. */
20601 case BFD_RELOC_ARM_OFFSET_IMM:
20602 case BFD_RELOC_ARM_OFFSET_IMM8:
20603 case BFD_RELOC_ARM_HWLITERAL:
20604 case BFD_RELOC_ARM_LITERAL:
20605 case BFD_RELOC_ARM_CP_OFF_IMM:
20609 /* Other PC-relative relocations are un-offset. */
20615 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20616 Otherwise we have no need to default values of symbols. */
20619 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20622 if (name[0] == '_' && name[1] == 'G'
20623 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20627 if (symbol_find (name))
20628 as_bad (_("GOT already in the symbol table"));
20630 GOT_symbol = symbol_new (name, undefined_section,
20631 (valueT) 0, & zero_address_frag);
20641 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20642 computed as two separate immediate values, added together. We
20643 already know that this value cannot be computed by just one ARM
20646 static unsigned int
20647 validate_immediate_twopart (unsigned int val,
20648 unsigned int * highpart)
20653 for (i = 0; i < 32; i += 2)
20654 if (((a = rotate_left (val, i)) & 0xff) != 0)
20660 * highpart = (a >> 8) | ((i + 24) << 7);
20662 else if (a & 0xff0000)
20664 if (a & 0xff000000)
20666 * highpart = (a >> 16) | ((i + 16) << 7);
20670 gas_assert (a & 0xff000000);
20671 * highpart = (a >> 24) | ((i + 8) << 7);
20674 return (a & 0xff) | (i << 7);
20681 validate_offset_imm (unsigned int val, int hwse)
20683 if ((hwse && val > 255) || val > 4095)
20688 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20689 negative immediate constant by altering the instruction. A bit of
20694 by inverting the second operand, and
20697 by negating the second operand. */
20700 negate_data_op (unsigned long * instruction,
20701 unsigned long value)
20704 unsigned long negated, inverted;
20706 negated = encode_arm_immediate (-value);
20707 inverted = encode_arm_immediate (~value);
20709 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20712 /* First negates. */
20713 case OPCODE_SUB: /* ADD <-> SUB */
20714 new_inst = OPCODE_ADD;
20719 new_inst = OPCODE_SUB;
20723 case OPCODE_CMP: /* CMP <-> CMN */
20724 new_inst = OPCODE_CMN;
20729 new_inst = OPCODE_CMP;
20733 /* Now Inverted ops. */
20734 case OPCODE_MOV: /* MOV <-> MVN */
20735 new_inst = OPCODE_MVN;
20740 new_inst = OPCODE_MOV;
20744 case OPCODE_AND: /* AND <-> BIC */
20745 new_inst = OPCODE_BIC;
20750 new_inst = OPCODE_AND;
20754 case OPCODE_ADC: /* ADC <-> SBC */
20755 new_inst = OPCODE_SBC;
20760 new_inst = OPCODE_ADC;
20764 /* We cannot do anything. */
20769 if (value == (unsigned) FAIL)
20772 *instruction &= OPCODE_MASK;
20773 *instruction |= new_inst << DATA_OP_SHIFT;
20777 /* Like negate_data_op, but for Thumb-2. */
20779 static unsigned int
20780 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20784 unsigned int negated, inverted;
20786 negated = encode_thumb32_immediate (-value);
20787 inverted = encode_thumb32_immediate (~value);
20789 rd = (*instruction >> 8) & 0xf;
20790 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20793 /* ADD <-> SUB. Includes CMP <-> CMN. */
20794 case T2_OPCODE_SUB:
20795 new_inst = T2_OPCODE_ADD;
20799 case T2_OPCODE_ADD:
20800 new_inst = T2_OPCODE_SUB;
20804 /* ORR <-> ORN. Includes MOV <-> MVN. */
20805 case T2_OPCODE_ORR:
20806 new_inst = T2_OPCODE_ORN;
20810 case T2_OPCODE_ORN:
20811 new_inst = T2_OPCODE_ORR;
20815 /* AND <-> BIC. TST has no inverted equivalent. */
20816 case T2_OPCODE_AND:
20817 new_inst = T2_OPCODE_BIC;
20824 case T2_OPCODE_BIC:
20825 new_inst = T2_OPCODE_AND;
20830 case T2_OPCODE_ADC:
20831 new_inst = T2_OPCODE_SBC;
20835 case T2_OPCODE_SBC:
20836 new_inst = T2_OPCODE_ADC;
20840 /* We cannot do anything. */
20845 if (value == (unsigned int)FAIL)
20848 *instruction &= T2_OPCODE_MASK;
20849 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20853 /* Read a 32-bit thumb instruction from buf. */
20854 static unsigned long
20855 get_thumb32_insn (char * buf)
20857 unsigned long insn;
20858 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20859 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20865 /* We usually want to set the low bit on the address of thumb function
20866 symbols. In particular .word foo - . should have the low bit set.
20867 Generic code tries to fold the difference of two symbols to
20868 a constant. Prevent this and force a relocation when the first symbols
20869 is a thumb function. */
20872 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20874 if (op == O_subtract
20875 && l->X_op == O_symbol
20876 && r->X_op == O_symbol
20877 && THUMB_IS_FUNC (l->X_add_symbol))
20879 l->X_op = O_subtract;
20880 l->X_op_symbol = r->X_add_symbol;
20881 l->X_add_number -= r->X_add_number;
20885 /* Process as normal. */
20889 /* Encode Thumb2 unconditional branches and calls. The encoding
20890 for the 2 are identical for the immediate values. */
20893 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20895 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20898 addressT S, I1, I2, lo, hi;
20900 S = (value >> 24) & 0x01;
20901 I1 = (value >> 23) & 0x01;
20902 I2 = (value >> 22) & 0x01;
20903 hi = (value >> 12) & 0x3ff;
20904 lo = (value >> 1) & 0x7ff;
20905 newval = md_chars_to_number (buf, THUMB_SIZE);
20906 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20907 newval |= (S << 10) | hi;
20908 newval2 &= ~T2I1I2MASK;
20909 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20910 md_number_to_chars (buf, newval, THUMB_SIZE);
20911 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20915 md_apply_fix (fixS * fixP,
20919 offsetT value = * valP;
20921 unsigned int newimm;
20922 unsigned long temp;
20924 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20926 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20928 /* Note whether this will delete the relocation. */
20930 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20933 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20934 consistency with the behaviour on 32-bit hosts. Remember value
20936 value &= 0xffffffff;
20937 value ^= 0x80000000;
20938 value -= 0x80000000;
20941 fixP->fx_addnumber = value;
20943 /* Same treatment for fixP->fx_offset. */
20944 fixP->fx_offset &= 0xffffffff;
20945 fixP->fx_offset ^= 0x80000000;
20946 fixP->fx_offset -= 0x80000000;
20948 switch (fixP->fx_r_type)
20950 case BFD_RELOC_NONE:
20951 /* This will need to go in the object file. */
20955 case BFD_RELOC_ARM_IMMEDIATE:
20956 /* We claim that this fixup has been processed here,
20957 even if in fact we generate an error because we do
20958 not have a reloc for it, so tc_gen_reloc will reject it. */
20961 if (fixP->fx_addsy)
20963 const char *msg = 0;
20965 if (! S_IS_DEFINED (fixP->fx_addsy))
20966 msg = _("undefined symbol %s used as an immediate value");
20967 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20968 msg = _("symbol %s is in a different section");
20969 else if (S_IS_WEAK (fixP->fx_addsy))
20970 msg = _("symbol %s is weak and may be overridden later");
20974 as_bad_where (fixP->fx_file, fixP->fx_line,
20975 msg, S_GET_NAME (fixP->fx_addsy));
20980 temp = md_chars_to_number (buf, INSN_SIZE);
20982 /* If the offset is negative, we should use encoding A2 for ADR. */
20983 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
20984 newimm = negate_data_op (&temp, value);
20987 newimm = encode_arm_immediate (value);
20989 /* If the instruction will fail, see if we can fix things up by
20990 changing the opcode. */
20991 if (newimm == (unsigned int) FAIL)
20992 newimm = negate_data_op (&temp, value);
20995 if (newimm == (unsigned int) FAIL)
20997 as_bad_where (fixP->fx_file, fixP->fx_line,
20998 _("invalid constant (%lx) after fixup"),
20999 (unsigned long) value);
21003 newimm |= (temp & 0xfffff000);
21004 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21007 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21009 unsigned int highpart = 0;
21010 unsigned int newinsn = 0xe1a00000; /* nop. */
21012 if (fixP->fx_addsy)
21014 const char *msg = 0;
21016 if (! S_IS_DEFINED (fixP->fx_addsy))
21017 msg = _("undefined symbol %s used as an immediate value");
21018 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21019 msg = _("symbol %s is in a different section");
21020 else if (S_IS_WEAK (fixP->fx_addsy))
21021 msg = _("symbol %s is weak and may be overridden later");
21025 as_bad_where (fixP->fx_file, fixP->fx_line,
21026 msg, S_GET_NAME (fixP->fx_addsy));
21031 newimm = encode_arm_immediate (value);
21032 temp = md_chars_to_number (buf, INSN_SIZE);
21034 /* If the instruction will fail, see if we can fix things up by
21035 changing the opcode. */
21036 if (newimm == (unsigned int) FAIL
21037 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21039 /* No ? OK - try using two ADD instructions to generate
21041 newimm = validate_immediate_twopart (value, & highpart);
21043 /* Yes - then make sure that the second instruction is
21045 if (newimm != (unsigned int) FAIL)
21047 /* Still No ? Try using a negated value. */
21048 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21049 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21050 /* Otherwise - give up. */
21053 as_bad_where (fixP->fx_file, fixP->fx_line,
21054 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21059 /* Replace the first operand in the 2nd instruction (which
21060 is the PC) with the destination register. We have
21061 already added in the PC in the first instruction and we
21062 do not want to do it again. */
21063 newinsn &= ~ 0xf0000;
21064 newinsn |= ((newinsn & 0x0f000) << 4);
21067 newimm |= (temp & 0xfffff000);
21068 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21070 highpart |= (newinsn & 0xfffff000);
21071 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21075 case BFD_RELOC_ARM_OFFSET_IMM:
21076 if (!fixP->fx_done && seg->use_rela_p)
21079 case BFD_RELOC_ARM_LITERAL:
21085 if (validate_offset_imm (value, 0) == FAIL)
21087 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21088 as_bad_where (fixP->fx_file, fixP->fx_line,
21089 _("invalid literal constant: pool needs to be closer"));
21091 as_bad_where (fixP->fx_file, fixP->fx_line,
21092 _("bad immediate value for offset (%ld)"),
21097 newval = md_chars_to_number (buf, INSN_SIZE);
21099 newval &= 0xfffff000;
21102 newval &= 0xff7ff000;
21103 newval |= value | (sign ? INDEX_UP : 0);
21105 md_number_to_chars (buf, newval, INSN_SIZE);
21108 case BFD_RELOC_ARM_OFFSET_IMM8:
21109 case BFD_RELOC_ARM_HWLITERAL:
21115 if (validate_offset_imm (value, 1) == FAIL)
21117 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21118 as_bad_where (fixP->fx_file, fixP->fx_line,
21119 _("invalid literal constant: pool needs to be closer"));
21121 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
21126 newval = md_chars_to_number (buf, INSN_SIZE);
21128 newval &= 0xfffff0f0;
21131 newval &= 0xff7ff0f0;
21132 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21134 md_number_to_chars (buf, newval, INSN_SIZE);
21137 case BFD_RELOC_ARM_T32_OFFSET_U8:
21138 if (value < 0 || value > 1020 || value % 4 != 0)
21139 as_bad_where (fixP->fx_file, fixP->fx_line,
21140 _("bad immediate value for offset (%ld)"), (long) value);
21143 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21145 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21148 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21149 /* This is a complicated relocation used for all varieties of Thumb32
21150 load/store instruction with immediate offset:
21152 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21153 *4, optional writeback(W)
21154 (doubleword load/store)
21156 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21157 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21158 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21159 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21160 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21162 Uppercase letters indicate bits that are already encoded at
21163 this point. Lowercase letters are our problem. For the
21164 second block of instructions, the secondary opcode nybble
21165 (bits 8..11) is present, and bit 23 is zero, even if this is
21166 a PC-relative operation. */
21167 newval = md_chars_to_number (buf, THUMB_SIZE);
21169 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21171 if ((newval & 0xf0000000) == 0xe0000000)
21173 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21175 newval |= (1 << 23);
21178 if (value % 4 != 0)
21180 as_bad_where (fixP->fx_file, fixP->fx_line,
21181 _("offset not a multiple of 4"));
21187 as_bad_where (fixP->fx_file, fixP->fx_line,
21188 _("offset out of range"));
21193 else if ((newval & 0x000f0000) == 0x000f0000)
21195 /* PC-relative, 12-bit offset. */
21197 newval |= (1 << 23);
21202 as_bad_where (fixP->fx_file, fixP->fx_line,
21203 _("offset out of range"));
21208 else if ((newval & 0x00000100) == 0x00000100)
21210 /* Writeback: 8-bit, +/- offset. */
21212 newval |= (1 << 9);
21217 as_bad_where (fixP->fx_file, fixP->fx_line,
21218 _("offset out of range"));
21223 else if ((newval & 0x00000f00) == 0x00000e00)
21225 /* T-instruction: positive 8-bit offset. */
21226 if (value < 0 || value > 0xff)
21228 as_bad_where (fixP->fx_file, fixP->fx_line,
21229 _("offset out of range"));
21237 /* Positive 12-bit or negative 8-bit offset. */
21241 newval |= (1 << 23);
21251 as_bad_where (fixP->fx_file, fixP->fx_line,
21252 _("offset out of range"));
21259 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21260 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21263 case BFD_RELOC_ARM_SHIFT_IMM:
21264 newval = md_chars_to_number (buf, INSN_SIZE);
21265 if (((unsigned long) value) > 32
21267 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21269 as_bad_where (fixP->fx_file, fixP->fx_line,
21270 _("shift expression is too large"));
21275 /* Shifts of zero must be done as lsl. */
21277 else if (value == 32)
21279 newval &= 0xfffff07f;
21280 newval |= (value & 0x1f) << 7;
21281 md_number_to_chars (buf, newval, INSN_SIZE);
21284 case BFD_RELOC_ARM_T32_IMMEDIATE:
21285 case BFD_RELOC_ARM_T32_ADD_IMM:
21286 case BFD_RELOC_ARM_T32_IMM12:
21287 case BFD_RELOC_ARM_T32_ADD_PC12:
21288 /* We claim that this fixup has been processed here,
21289 even if in fact we generate an error because we do
21290 not have a reloc for it, so tc_gen_reloc will reject it. */
21294 && ! S_IS_DEFINED (fixP->fx_addsy))
21296 as_bad_where (fixP->fx_file, fixP->fx_line,
21297 _("undefined symbol %s used as an immediate value"),
21298 S_GET_NAME (fixP->fx_addsy));
21302 newval = md_chars_to_number (buf, THUMB_SIZE);
21304 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21307 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21308 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21310 newimm = encode_thumb32_immediate (value);
21311 if (newimm == (unsigned int) FAIL)
21312 newimm = thumb32_negate_data_op (&newval, value);
21314 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21315 && newimm == (unsigned int) FAIL)
21317 /* Turn add/sum into addw/subw. */
21318 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21319 newval = (newval & 0xfeffffff) | 0x02000000;
21320 /* No flat 12-bit imm encoding for addsw/subsw. */
21321 if ((newval & 0x00100000) == 0)
21323 /* 12 bit immediate for addw/subw. */
21327 newval ^= 0x00a00000;
21330 newimm = (unsigned int) FAIL;
21336 if (newimm == (unsigned int)FAIL)
21338 as_bad_where (fixP->fx_file, fixP->fx_line,
21339 _("invalid constant (%lx) after fixup"),
21340 (unsigned long) value);
21344 newval |= (newimm & 0x800) << 15;
21345 newval |= (newimm & 0x700) << 4;
21346 newval |= (newimm & 0x0ff);
21348 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21349 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21352 case BFD_RELOC_ARM_SMC:
21353 if (((unsigned long) value) > 0xffff)
21354 as_bad_where (fixP->fx_file, fixP->fx_line,
21355 _("invalid smc expression"));
21356 newval = md_chars_to_number (buf, INSN_SIZE);
21357 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21358 md_number_to_chars (buf, newval, INSN_SIZE);
21361 case BFD_RELOC_ARM_HVC:
21362 if (((unsigned long) value) > 0xffff)
21363 as_bad_where (fixP->fx_file, fixP->fx_line,
21364 _("invalid hvc expression"));
21365 newval = md_chars_to_number (buf, INSN_SIZE);
21366 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21367 md_number_to_chars (buf, newval, INSN_SIZE);
21370 case BFD_RELOC_ARM_SWI:
21371 if (fixP->tc_fix_data != 0)
21373 if (((unsigned long) value) > 0xff)
21374 as_bad_where (fixP->fx_file, fixP->fx_line,
21375 _("invalid swi expression"));
21376 newval = md_chars_to_number (buf, THUMB_SIZE);
21378 md_number_to_chars (buf, newval, THUMB_SIZE);
21382 if (((unsigned long) value) > 0x00ffffff)
21383 as_bad_where (fixP->fx_file, fixP->fx_line,
21384 _("invalid swi expression"));
21385 newval = md_chars_to_number (buf, INSN_SIZE);
21387 md_number_to_chars (buf, newval, INSN_SIZE);
21391 case BFD_RELOC_ARM_MULTI:
21392 if (((unsigned long) value) > 0xffff)
21393 as_bad_where (fixP->fx_file, fixP->fx_line,
21394 _("invalid expression in load/store multiple"));
21395 newval = value | md_chars_to_number (buf, INSN_SIZE);
21396 md_number_to_chars (buf, newval, INSN_SIZE);
21400 case BFD_RELOC_ARM_PCREL_CALL:
21402 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21404 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21405 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21406 && THUMB_IS_FUNC (fixP->fx_addsy))
21407 /* Flip the bl to blx. This is a simple flip
21408 bit here because we generate PCREL_CALL for
21409 unconditional bls. */
21411 newval = md_chars_to_number (buf, INSN_SIZE);
21412 newval = newval | 0x10000000;
21413 md_number_to_chars (buf, newval, INSN_SIZE);
21419 goto arm_branch_common;
21421 case BFD_RELOC_ARM_PCREL_JUMP:
21422 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21424 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21425 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21426 && THUMB_IS_FUNC (fixP->fx_addsy))
21428 /* This would map to a bl<cond>, b<cond>,
21429 b<always> to a Thumb function. We
21430 need to force a relocation for this particular
21432 newval = md_chars_to_number (buf, INSN_SIZE);
21436 case BFD_RELOC_ARM_PLT32:
21438 case BFD_RELOC_ARM_PCREL_BRANCH:
21440 goto arm_branch_common;
21442 case BFD_RELOC_ARM_PCREL_BLX:
21445 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21447 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21448 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21449 && ARM_IS_FUNC (fixP->fx_addsy))
21451 /* Flip the blx to a bl and warn. */
21452 const char *name = S_GET_NAME (fixP->fx_addsy);
21453 newval = 0xeb000000;
21454 as_warn_where (fixP->fx_file, fixP->fx_line,
21455 _("blx to '%s' an ARM ISA state function changed to bl"),
21457 md_number_to_chars (buf, newval, INSN_SIZE);
21463 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21464 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21468 /* We are going to store value (shifted right by two) in the
21469 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21470 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21471 also be be clear. */
21473 as_bad_where (fixP->fx_file, fixP->fx_line,
21474 _("misaligned branch destination"));
21475 if ((value & (offsetT)0xfe000000) != (offsetT)0
21476 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21477 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21479 if (fixP->fx_done || !seg->use_rela_p)
21481 newval = md_chars_to_number (buf, INSN_SIZE);
21482 newval |= (value >> 2) & 0x00ffffff;
21483 /* Set the H bit on BLX instructions. */
21487 newval |= 0x01000000;
21489 newval &= ~0x01000000;
21491 md_number_to_chars (buf, newval, INSN_SIZE);
21495 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21496 /* CBZ can only branch forward. */
21498 /* Attempts to use CBZ to branch to the next instruction
21499 (which, strictly speaking, are prohibited) will be turned into
21502 FIXME: It may be better to remove the instruction completely and
21503 perform relaxation. */
21506 newval = md_chars_to_number (buf, THUMB_SIZE);
21507 newval = 0xbf00; /* NOP encoding T1 */
21508 md_number_to_chars (buf, newval, THUMB_SIZE);
21513 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21515 if (fixP->fx_done || !seg->use_rela_p)
21517 newval = md_chars_to_number (buf, THUMB_SIZE);
21518 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21519 md_number_to_chars (buf, newval, THUMB_SIZE);
21524 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21525 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21526 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21528 if (fixP->fx_done || !seg->use_rela_p)
21530 newval = md_chars_to_number (buf, THUMB_SIZE);
21531 newval |= (value & 0x1ff) >> 1;
21532 md_number_to_chars (buf, newval, THUMB_SIZE);
21536 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21537 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21538 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21540 if (fixP->fx_done || !seg->use_rela_p)
21542 newval = md_chars_to_number (buf, THUMB_SIZE);
21543 newval |= (value & 0xfff) >> 1;
21544 md_number_to_chars (buf, newval, THUMB_SIZE);
21548 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21550 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21551 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21552 && ARM_IS_FUNC (fixP->fx_addsy)
21553 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21555 /* Force a relocation for a branch 20 bits wide. */
21558 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21559 as_bad_where (fixP->fx_file, fixP->fx_line,
21560 _("conditional branch out of range"));
21562 if (fixP->fx_done || !seg->use_rela_p)
21565 addressT S, J1, J2, lo, hi;
21567 S = (value & 0x00100000) >> 20;
21568 J2 = (value & 0x00080000) >> 19;
21569 J1 = (value & 0x00040000) >> 18;
21570 hi = (value & 0x0003f000) >> 12;
21571 lo = (value & 0x00000ffe) >> 1;
21573 newval = md_chars_to_number (buf, THUMB_SIZE);
21574 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21575 newval |= (S << 10) | hi;
21576 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21577 md_number_to_chars (buf, newval, THUMB_SIZE);
21578 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21582 case BFD_RELOC_THUMB_PCREL_BLX:
21583 /* If there is a blx from a thumb state function to
21584 another thumb function flip this to a bl and warn
21588 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21589 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21590 && THUMB_IS_FUNC (fixP->fx_addsy))
21592 const char *name = S_GET_NAME (fixP->fx_addsy);
21593 as_warn_where (fixP->fx_file, fixP->fx_line,
21594 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21596 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21597 newval = newval | 0x1000;
21598 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21599 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21604 goto thumb_bl_common;
21606 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21607 /* A bl from Thumb state ISA to an internal ARM state function
21608 is converted to a blx. */
21610 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21611 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21612 && ARM_IS_FUNC (fixP->fx_addsy)
21613 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21615 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21616 newval = newval & ~0x1000;
21617 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21618 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21625 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
21626 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21627 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21630 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21631 /* For a BLX instruction, make sure that the relocation is rounded up
21632 to a word boundary. This follows the semantics of the instruction
21633 which specifies that bit 1 of the target address will come from bit
21634 1 of the base address. */
21635 value = (value + 1) & ~ 1;
21637 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21639 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21640 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21641 else if ((value & ~0x1ffffff)
21642 && ((value & ~0x1ffffff) != ~0x1ffffff))
21643 as_bad_where (fixP->fx_file, fixP->fx_line,
21644 _("Thumb2 branch out of range"));
21647 if (fixP->fx_done || !seg->use_rela_p)
21648 encode_thumb2_b_bl_offset (buf, value);
21652 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21653 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21654 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21656 if (fixP->fx_done || !seg->use_rela_p)
21657 encode_thumb2_b_bl_offset (buf, value);
21662 if (fixP->fx_done || !seg->use_rela_p)
21663 md_number_to_chars (buf, value, 1);
21667 if (fixP->fx_done || !seg->use_rela_p)
21668 md_number_to_chars (buf, value, 2);
21672 case BFD_RELOC_ARM_TLS_CALL:
21673 case BFD_RELOC_ARM_THM_TLS_CALL:
21674 case BFD_RELOC_ARM_TLS_DESCSEQ:
21675 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21676 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21679 case BFD_RELOC_ARM_TLS_GOTDESC:
21680 case BFD_RELOC_ARM_TLS_GD32:
21681 case BFD_RELOC_ARM_TLS_LE32:
21682 case BFD_RELOC_ARM_TLS_IE32:
21683 case BFD_RELOC_ARM_TLS_LDM32:
21684 case BFD_RELOC_ARM_TLS_LDO32:
21685 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21688 case BFD_RELOC_ARM_GOT32:
21689 case BFD_RELOC_ARM_GOTOFF:
21690 if (fixP->fx_done || !seg->use_rela_p)
21691 md_number_to_chars (buf, 0, 4);
21694 case BFD_RELOC_ARM_GOT_PREL:
21695 if (fixP->fx_done || !seg->use_rela_p)
21696 md_number_to_chars (buf, value, 4);
21699 case BFD_RELOC_ARM_TARGET2:
21700 /* TARGET2 is not partial-inplace, so we need to write the
21701 addend here for REL targets, because it won't be written out
21702 during reloc processing later. */
21703 if (fixP->fx_done || !seg->use_rela_p)
21704 md_number_to_chars (buf, fixP->fx_offset, 4);
21708 case BFD_RELOC_RVA:
21710 case BFD_RELOC_ARM_TARGET1:
21711 case BFD_RELOC_ARM_ROSEGREL32:
21712 case BFD_RELOC_ARM_SBREL32:
21713 case BFD_RELOC_32_PCREL:
21715 case BFD_RELOC_32_SECREL:
21717 if (fixP->fx_done || !seg->use_rela_p)
21719 /* For WinCE we only do this for pcrel fixups. */
21720 if (fixP->fx_done || fixP->fx_pcrel)
21722 md_number_to_chars (buf, value, 4);
21726 case BFD_RELOC_ARM_PREL31:
21727 if (fixP->fx_done || !seg->use_rela_p)
21729 newval = md_chars_to_number (buf, 4) & 0x80000000;
21730 if ((value ^ (value >> 1)) & 0x40000000)
21732 as_bad_where (fixP->fx_file, fixP->fx_line,
21733 _("rel31 relocation overflow"));
21735 newval |= value & 0x7fffffff;
21736 md_number_to_chars (buf, newval, 4);
21741 case BFD_RELOC_ARM_CP_OFF_IMM:
21742 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21743 if (value < -1023 || value > 1023 || (value & 3))
21744 as_bad_where (fixP->fx_file, fixP->fx_line,
21745 _("co-processor offset out of range"));
21750 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21751 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21752 newval = md_chars_to_number (buf, INSN_SIZE);
21754 newval = get_thumb32_insn (buf);
21756 newval &= 0xffffff00;
21759 newval &= 0xff7fff00;
21760 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21762 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21763 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21764 md_number_to_chars (buf, newval, INSN_SIZE);
21766 put_thumb32_insn (buf, newval);
21769 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21770 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21771 if (value < -255 || value > 255)
21772 as_bad_where (fixP->fx_file, fixP->fx_line,
21773 _("co-processor offset out of range"));
21775 goto cp_off_common;
21777 case BFD_RELOC_ARM_THUMB_OFFSET:
21778 newval = md_chars_to_number (buf, THUMB_SIZE);
21779 /* Exactly what ranges, and where the offset is inserted depends
21780 on the type of instruction, we can establish this from the
21782 switch (newval >> 12)
21784 case 4: /* PC load. */
21785 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21786 forced to zero for these loads; md_pcrel_from has already
21787 compensated for this. */
21789 as_bad_where (fixP->fx_file, fixP->fx_line,
21790 _("invalid offset, target not word aligned (0x%08lX)"),
21791 (((unsigned long) fixP->fx_frag->fr_address
21792 + (unsigned long) fixP->fx_where) & ~3)
21793 + (unsigned long) value);
21795 if (value & ~0x3fc)
21796 as_bad_where (fixP->fx_file, fixP->fx_line,
21797 _("invalid offset, value too big (0x%08lX)"),
21800 newval |= value >> 2;
21803 case 9: /* SP load/store. */
21804 if (value & ~0x3fc)
21805 as_bad_where (fixP->fx_file, fixP->fx_line,
21806 _("invalid offset, value too big (0x%08lX)"),
21808 newval |= value >> 2;
21811 case 6: /* Word load/store. */
21813 as_bad_where (fixP->fx_file, fixP->fx_line,
21814 _("invalid offset, value too big (0x%08lX)"),
21816 newval |= value << 4; /* 6 - 2. */
21819 case 7: /* Byte load/store. */
21821 as_bad_where (fixP->fx_file, fixP->fx_line,
21822 _("invalid offset, value too big (0x%08lX)"),
21824 newval |= value << 6;
21827 case 8: /* Halfword load/store. */
21829 as_bad_where (fixP->fx_file, fixP->fx_line,
21830 _("invalid offset, value too big (0x%08lX)"),
21832 newval |= value << 5; /* 6 - 1. */
21836 as_bad_where (fixP->fx_file, fixP->fx_line,
21837 "Unable to process relocation for thumb opcode: %lx",
21838 (unsigned long) newval);
21841 md_number_to_chars (buf, newval, THUMB_SIZE);
21844 case BFD_RELOC_ARM_THUMB_ADD:
21845 /* This is a complicated relocation, since we use it for all of
21846 the following immediate relocations:
21850 9bit ADD/SUB SP word-aligned
21851 10bit ADD PC/SP word-aligned
21853 The type of instruction being processed is encoded in the
21860 newval = md_chars_to_number (buf, THUMB_SIZE);
21862 int rd = (newval >> 4) & 0xf;
21863 int rs = newval & 0xf;
21864 int subtract = !!(newval & 0x8000);
21866 /* Check for HI regs, only very restricted cases allowed:
21867 Adjusting SP, and using PC or SP to get an address. */
21868 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21869 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21870 as_bad_where (fixP->fx_file, fixP->fx_line,
21871 _("invalid Hi register with immediate"));
21873 /* If value is negative, choose the opposite instruction. */
21877 subtract = !subtract;
21879 as_bad_where (fixP->fx_file, fixP->fx_line,
21880 _("immediate value out of range"));
21885 if (value & ~0x1fc)
21886 as_bad_where (fixP->fx_file, fixP->fx_line,
21887 _("invalid immediate for stack address calculation"));
21888 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21889 newval |= value >> 2;
21891 else if (rs == REG_PC || rs == REG_SP)
21893 if (subtract || value & ~0x3fc)
21894 as_bad_where (fixP->fx_file, fixP->fx_line,
21895 _("invalid immediate for address calculation (value = 0x%08lX)"),
21896 (unsigned long) value);
21897 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21899 newval |= value >> 2;
21904 as_bad_where (fixP->fx_file, fixP->fx_line,
21905 _("immediate value out of range"));
21906 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21907 newval |= (rd << 8) | value;
21912 as_bad_where (fixP->fx_file, fixP->fx_line,
21913 _("immediate value out of range"));
21914 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21915 newval |= rd | (rs << 3) | (value << 6);
21918 md_number_to_chars (buf, newval, THUMB_SIZE);
21921 case BFD_RELOC_ARM_THUMB_IMM:
21922 newval = md_chars_to_number (buf, THUMB_SIZE);
21923 if (value < 0 || value > 255)
21924 as_bad_where (fixP->fx_file, fixP->fx_line,
21925 _("invalid immediate: %ld is out of range"),
21928 md_number_to_chars (buf, newval, THUMB_SIZE);
21931 case BFD_RELOC_ARM_THUMB_SHIFT:
21932 /* 5bit shift value (0..32). LSL cannot take 32. */
21933 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21934 temp = newval & 0xf800;
21935 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21936 as_bad_where (fixP->fx_file, fixP->fx_line,
21937 _("invalid shift value: %ld"), (long) value);
21938 /* Shifts of zero must be encoded as LSL. */
21940 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21941 /* Shifts of 32 are encoded as zero. */
21942 else if (value == 32)
21944 newval |= value << 6;
21945 md_number_to_chars (buf, newval, THUMB_SIZE);
21948 case BFD_RELOC_VTABLE_INHERIT:
21949 case BFD_RELOC_VTABLE_ENTRY:
21953 case BFD_RELOC_ARM_MOVW:
21954 case BFD_RELOC_ARM_MOVT:
21955 case BFD_RELOC_ARM_THUMB_MOVW:
21956 case BFD_RELOC_ARM_THUMB_MOVT:
21957 if (fixP->fx_done || !seg->use_rela_p)
21959 /* REL format relocations are limited to a 16-bit addend. */
21960 if (!fixP->fx_done)
21962 if (value < -0x8000 || value > 0x7fff)
21963 as_bad_where (fixP->fx_file, fixP->fx_line,
21964 _("offset out of range"));
21966 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21967 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21972 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21973 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21975 newval = get_thumb32_insn (buf);
21976 newval &= 0xfbf08f00;
21977 newval |= (value & 0xf000) << 4;
21978 newval |= (value & 0x0800) << 15;
21979 newval |= (value & 0x0700) << 4;
21980 newval |= (value & 0x00ff);
21981 put_thumb32_insn (buf, newval);
21985 newval = md_chars_to_number (buf, 4);
21986 newval &= 0xfff0f000;
21987 newval |= value & 0x0fff;
21988 newval |= (value & 0xf000) << 4;
21989 md_number_to_chars (buf, newval, 4);
21994 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21995 case BFD_RELOC_ARM_ALU_PC_G0:
21996 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21997 case BFD_RELOC_ARM_ALU_PC_G1:
21998 case BFD_RELOC_ARM_ALU_PC_G2:
21999 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22000 case BFD_RELOC_ARM_ALU_SB_G0:
22001 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22002 case BFD_RELOC_ARM_ALU_SB_G1:
22003 case BFD_RELOC_ARM_ALU_SB_G2:
22004 gas_assert (!fixP->fx_done);
22005 if (!seg->use_rela_p)
22008 bfd_vma encoded_addend;
22009 bfd_vma addend_abs = abs (value);
22011 /* Check that the absolute value of the addend can be
22012 expressed as an 8-bit constant plus a rotation. */
22013 encoded_addend = encode_arm_immediate (addend_abs);
22014 if (encoded_addend == (unsigned int) FAIL)
22015 as_bad_where (fixP->fx_file, fixP->fx_line,
22016 _("the offset 0x%08lX is not representable"),
22017 (unsigned long) addend_abs);
22019 /* Extract the instruction. */
22020 insn = md_chars_to_number (buf, INSN_SIZE);
22022 /* If the addend is positive, use an ADD instruction.
22023 Otherwise use a SUB. Take care not to destroy the S bit. */
22024 insn &= 0xff1fffff;
22030 /* Place the encoded addend into the first 12 bits of the
22032 insn &= 0xfffff000;
22033 insn |= encoded_addend;
22035 /* Update the instruction. */
22036 md_number_to_chars (buf, insn, INSN_SIZE);
22040 case BFD_RELOC_ARM_LDR_PC_G0:
22041 case BFD_RELOC_ARM_LDR_PC_G1:
22042 case BFD_RELOC_ARM_LDR_PC_G2:
22043 case BFD_RELOC_ARM_LDR_SB_G0:
22044 case BFD_RELOC_ARM_LDR_SB_G1:
22045 case BFD_RELOC_ARM_LDR_SB_G2:
22046 gas_assert (!fixP->fx_done);
22047 if (!seg->use_rela_p)
22050 bfd_vma addend_abs = abs (value);
22052 /* Check that the absolute value of the addend can be
22053 encoded in 12 bits. */
22054 if (addend_abs >= 0x1000)
22055 as_bad_where (fixP->fx_file, fixP->fx_line,
22056 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22057 (unsigned long) addend_abs);
22059 /* Extract the instruction. */
22060 insn = md_chars_to_number (buf, INSN_SIZE);
22062 /* If the addend is negative, clear bit 23 of the instruction.
22063 Otherwise set it. */
22065 insn &= ~(1 << 23);
22069 /* Place the absolute value of the addend into the first 12 bits
22070 of the instruction. */
22071 insn &= 0xfffff000;
22072 insn |= addend_abs;
22074 /* Update the instruction. */
22075 md_number_to_chars (buf, insn, INSN_SIZE);
22079 case BFD_RELOC_ARM_LDRS_PC_G0:
22080 case BFD_RELOC_ARM_LDRS_PC_G1:
22081 case BFD_RELOC_ARM_LDRS_PC_G2:
22082 case BFD_RELOC_ARM_LDRS_SB_G0:
22083 case BFD_RELOC_ARM_LDRS_SB_G1:
22084 case BFD_RELOC_ARM_LDRS_SB_G2:
22085 gas_assert (!fixP->fx_done);
22086 if (!seg->use_rela_p)
22089 bfd_vma addend_abs = abs (value);
22091 /* Check that the absolute value of the addend can be
22092 encoded in 8 bits. */
22093 if (addend_abs >= 0x100)
22094 as_bad_where (fixP->fx_file, fixP->fx_line,
22095 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22096 (unsigned long) addend_abs);
22098 /* Extract the instruction. */
22099 insn = md_chars_to_number (buf, INSN_SIZE);
22101 /* If the addend is negative, clear bit 23 of the instruction.
22102 Otherwise set it. */
22104 insn &= ~(1 << 23);
22108 /* Place the first four bits of the absolute value of the addend
22109 into the first 4 bits of the instruction, and the remaining
22110 four into bits 8 .. 11. */
22111 insn &= 0xfffff0f0;
22112 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22114 /* Update the instruction. */
22115 md_number_to_chars (buf, insn, INSN_SIZE);
22119 case BFD_RELOC_ARM_LDC_PC_G0:
22120 case BFD_RELOC_ARM_LDC_PC_G1:
22121 case BFD_RELOC_ARM_LDC_PC_G2:
22122 case BFD_RELOC_ARM_LDC_SB_G0:
22123 case BFD_RELOC_ARM_LDC_SB_G1:
22124 case BFD_RELOC_ARM_LDC_SB_G2:
22125 gas_assert (!fixP->fx_done);
22126 if (!seg->use_rela_p)
22129 bfd_vma addend_abs = abs (value);
22131 /* Check that the absolute value of the addend is a multiple of
22132 four and, when divided by four, fits in 8 bits. */
22133 if (addend_abs & 0x3)
22134 as_bad_where (fixP->fx_file, fixP->fx_line,
22135 _("bad offset 0x%08lX (must be word-aligned)"),
22136 (unsigned long) addend_abs);
22138 if ((addend_abs >> 2) > 0xff)
22139 as_bad_where (fixP->fx_file, fixP->fx_line,
22140 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22141 (unsigned long) addend_abs);
22143 /* Extract the instruction. */
22144 insn = md_chars_to_number (buf, INSN_SIZE);
22146 /* If the addend is negative, clear bit 23 of the instruction.
22147 Otherwise set it. */
22149 insn &= ~(1 << 23);
22153 /* Place the addend (divided by four) into the first eight
22154 bits of the instruction. */
22155 insn &= 0xfffffff0;
22156 insn |= addend_abs >> 2;
22158 /* Update the instruction. */
22159 md_number_to_chars (buf, insn, INSN_SIZE);
22163 case BFD_RELOC_ARM_V4BX:
22164 /* This will need to go in the object file. */
22168 case BFD_RELOC_UNUSED:
22170 as_bad_where (fixP->fx_file, fixP->fx_line,
22171 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22175 /* Translate internal representation of relocation info to BFD target
22179 tc_gen_reloc (asection *section, fixS *fixp)
22182 bfd_reloc_code_real_type code;
22184 reloc = (arelent *) xmalloc (sizeof (arelent));
22186 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22187 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22188 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22190 if (fixp->fx_pcrel)
22192 if (section->use_rela_p)
22193 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22195 fixp->fx_offset = reloc->address;
22197 reloc->addend = fixp->fx_offset;
22199 switch (fixp->fx_r_type)
22202 if (fixp->fx_pcrel)
22204 code = BFD_RELOC_8_PCREL;
22209 if (fixp->fx_pcrel)
22211 code = BFD_RELOC_16_PCREL;
22216 if (fixp->fx_pcrel)
22218 code = BFD_RELOC_32_PCREL;
22222 case BFD_RELOC_ARM_MOVW:
22223 if (fixp->fx_pcrel)
22225 code = BFD_RELOC_ARM_MOVW_PCREL;
22229 case BFD_RELOC_ARM_MOVT:
22230 if (fixp->fx_pcrel)
22232 code = BFD_RELOC_ARM_MOVT_PCREL;
22236 case BFD_RELOC_ARM_THUMB_MOVW:
22237 if (fixp->fx_pcrel)
22239 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22243 case BFD_RELOC_ARM_THUMB_MOVT:
22244 if (fixp->fx_pcrel)
22246 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22250 case BFD_RELOC_NONE:
22251 case BFD_RELOC_ARM_PCREL_BRANCH:
22252 case BFD_RELOC_ARM_PCREL_BLX:
22253 case BFD_RELOC_RVA:
22254 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22255 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22256 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22257 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22258 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22259 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22260 case BFD_RELOC_VTABLE_ENTRY:
22261 case BFD_RELOC_VTABLE_INHERIT:
22263 case BFD_RELOC_32_SECREL:
22265 code = fixp->fx_r_type;
22268 case BFD_RELOC_THUMB_PCREL_BLX:
22270 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22271 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22274 code = BFD_RELOC_THUMB_PCREL_BLX;
22277 case BFD_RELOC_ARM_LITERAL:
22278 case BFD_RELOC_ARM_HWLITERAL:
22279 /* If this is called then the a literal has
22280 been referenced across a section boundary. */
22281 as_bad_where (fixp->fx_file, fixp->fx_line,
22282 _("literal referenced across section boundary"));
22286 case BFD_RELOC_ARM_TLS_CALL:
22287 case BFD_RELOC_ARM_THM_TLS_CALL:
22288 case BFD_RELOC_ARM_TLS_DESCSEQ:
22289 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22290 case BFD_RELOC_ARM_GOT32:
22291 case BFD_RELOC_ARM_GOTOFF:
22292 case BFD_RELOC_ARM_GOT_PREL:
22293 case BFD_RELOC_ARM_PLT32:
22294 case BFD_RELOC_ARM_TARGET1:
22295 case BFD_RELOC_ARM_ROSEGREL32:
22296 case BFD_RELOC_ARM_SBREL32:
22297 case BFD_RELOC_ARM_PREL31:
22298 case BFD_RELOC_ARM_TARGET2:
22299 case BFD_RELOC_ARM_TLS_LE32:
22300 case BFD_RELOC_ARM_TLS_LDO32:
22301 case BFD_RELOC_ARM_PCREL_CALL:
22302 case BFD_RELOC_ARM_PCREL_JUMP:
22303 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22304 case BFD_RELOC_ARM_ALU_PC_G0:
22305 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22306 case BFD_RELOC_ARM_ALU_PC_G1:
22307 case BFD_RELOC_ARM_ALU_PC_G2:
22308 case BFD_RELOC_ARM_LDR_PC_G0:
22309 case BFD_RELOC_ARM_LDR_PC_G1:
22310 case BFD_RELOC_ARM_LDR_PC_G2:
22311 case BFD_RELOC_ARM_LDRS_PC_G0:
22312 case BFD_RELOC_ARM_LDRS_PC_G1:
22313 case BFD_RELOC_ARM_LDRS_PC_G2:
22314 case BFD_RELOC_ARM_LDC_PC_G0:
22315 case BFD_RELOC_ARM_LDC_PC_G1:
22316 case BFD_RELOC_ARM_LDC_PC_G2:
22317 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22318 case BFD_RELOC_ARM_ALU_SB_G0:
22319 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22320 case BFD_RELOC_ARM_ALU_SB_G1:
22321 case BFD_RELOC_ARM_ALU_SB_G2:
22322 case BFD_RELOC_ARM_LDR_SB_G0:
22323 case BFD_RELOC_ARM_LDR_SB_G1:
22324 case BFD_RELOC_ARM_LDR_SB_G2:
22325 case BFD_RELOC_ARM_LDRS_SB_G0:
22326 case BFD_RELOC_ARM_LDRS_SB_G1:
22327 case BFD_RELOC_ARM_LDRS_SB_G2:
22328 case BFD_RELOC_ARM_LDC_SB_G0:
22329 case BFD_RELOC_ARM_LDC_SB_G1:
22330 case BFD_RELOC_ARM_LDC_SB_G2:
22331 case BFD_RELOC_ARM_V4BX:
22332 code = fixp->fx_r_type;
22335 case BFD_RELOC_ARM_TLS_GOTDESC:
22336 case BFD_RELOC_ARM_TLS_GD32:
22337 case BFD_RELOC_ARM_TLS_IE32:
22338 case BFD_RELOC_ARM_TLS_LDM32:
22339 /* BFD will include the symbol's address in the addend.
22340 But we don't want that, so subtract it out again here. */
22341 if (!S_IS_COMMON (fixp->fx_addsy))
22342 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22343 code = fixp->fx_r_type;
22347 case BFD_RELOC_ARM_IMMEDIATE:
22348 as_bad_where (fixp->fx_file, fixp->fx_line,
22349 _("internal relocation (type: IMMEDIATE) not fixed up"));
22352 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22353 as_bad_where (fixp->fx_file, fixp->fx_line,
22354 _("ADRL used for a symbol not defined in the same file"));
22357 case BFD_RELOC_ARM_OFFSET_IMM:
22358 if (section->use_rela_p)
22360 code = fixp->fx_r_type;
22364 if (fixp->fx_addsy != NULL
22365 && !S_IS_DEFINED (fixp->fx_addsy)
22366 && S_IS_LOCAL (fixp->fx_addsy))
22368 as_bad_where (fixp->fx_file, fixp->fx_line,
22369 _("undefined local label `%s'"),
22370 S_GET_NAME (fixp->fx_addsy));
22374 as_bad_where (fixp->fx_file, fixp->fx_line,
22375 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22382 switch (fixp->fx_r_type)
22384 case BFD_RELOC_NONE: type = "NONE"; break;
22385 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22386 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22387 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22388 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22389 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22390 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22391 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22392 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22393 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22394 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22395 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22396 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22397 default: type = _("<unknown>"); break;
22399 as_bad_where (fixp->fx_file, fixp->fx_line,
22400 _("cannot represent %s relocation in this object file format"),
22407 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22409 && fixp->fx_addsy == GOT_symbol)
22411 code = BFD_RELOC_ARM_GOTPC;
22412 reloc->addend = fixp->fx_offset = reloc->address;
22416 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22418 if (reloc->howto == NULL)
22420 as_bad_where (fixp->fx_file, fixp->fx_line,
22421 _("cannot represent %s relocation in this object file format"),
22422 bfd_get_reloc_code_name (code));
22426 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22427 vtable entry to be used in the relocation's section offset. */
22428 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22429 reloc->address = fixp->fx_offset;
22434 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22437 cons_fix_new_arm (fragS * frag,
22442 bfd_reloc_code_real_type type;
22446 FIXME: @@ Should look at CPU word size. */
22450 type = BFD_RELOC_8;
22453 type = BFD_RELOC_16;
22457 type = BFD_RELOC_32;
22460 type = BFD_RELOC_64;
22465 if (exp->X_op == O_secrel)
22467 exp->X_op = O_symbol;
22468 type = BFD_RELOC_32_SECREL;
22472 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22475 #if defined (OBJ_COFF)
22477 arm_validate_fix (fixS * fixP)
22479 /* If the destination of the branch is a defined symbol which does not have
22480 the THUMB_FUNC attribute, then we must be calling a function which has
22481 the (interfacearm) attribute. We look for the Thumb entry point to that
22482 function and change the branch to refer to that function instead. */
22483 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22484 && fixP->fx_addsy != NULL
22485 && S_IS_DEFINED (fixP->fx_addsy)
22486 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22488 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22495 arm_force_relocation (struct fix * fixp)
22497 #if defined (OBJ_COFF) && defined (TE_PE)
22498 if (fixp->fx_r_type == BFD_RELOC_RVA)
22502 /* In case we have a call or a branch to a function in ARM ISA mode from
22503 a thumb function or vice-versa force the relocation. These relocations
22504 are cleared off for some cores that might have blx and simple transformations
22508 switch (fixp->fx_r_type)
22510 case BFD_RELOC_ARM_PCREL_JUMP:
22511 case BFD_RELOC_ARM_PCREL_CALL:
22512 case BFD_RELOC_THUMB_PCREL_BLX:
22513 if (THUMB_IS_FUNC (fixp->fx_addsy))
22517 case BFD_RELOC_ARM_PCREL_BLX:
22518 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22519 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22520 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22521 if (ARM_IS_FUNC (fixp->fx_addsy))
22530 /* Resolve these relocations even if the symbol is extern or weak.
22531 Technically this is probably wrong due to symbol preemption.
22532 In practice these relocations do not have enough range to be useful
22533 at dynamic link time, and some code (e.g. in the Linux kernel)
22534 expects these references to be resolved. */
22535 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22536 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22537 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22538 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22539 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22540 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22541 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22542 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22543 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22544 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22545 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22546 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22547 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22548 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22551 /* Always leave these relocations for the linker. */
22552 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22553 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22554 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22557 /* Always generate relocations against function symbols. */
22558 if (fixp->fx_r_type == BFD_RELOC_32
22560 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22563 return generic_force_reloc (fixp);
22566 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22567 /* Relocations against function names must be left unadjusted,
22568 so that the linker can use this information to generate interworking
22569 stubs. The MIPS version of this function
22570 also prevents relocations that are mips-16 specific, but I do not
22571 know why it does this.
22574 There is one other problem that ought to be addressed here, but
22575 which currently is not: Taking the address of a label (rather
22576 than a function) and then later jumping to that address. Such
22577 addresses also ought to have their bottom bit set (assuming that
22578 they reside in Thumb code), but at the moment they will not. */
22581 arm_fix_adjustable (fixS * fixP)
22583 if (fixP->fx_addsy == NULL)
22586 /* Preserve relocations against symbols with function type. */
22587 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22590 if (THUMB_IS_FUNC (fixP->fx_addsy)
22591 && fixP->fx_subsy == NULL)
22594 /* We need the symbol name for the VTABLE entries. */
22595 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22596 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22599 /* Don't allow symbols to be discarded on GOT related relocs. */
22600 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22601 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22602 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22603 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22604 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22605 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22606 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22607 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22608 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22609 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22610 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22611 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22612 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22613 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22616 /* Similarly for group relocations. */
22617 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22618 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22619 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22622 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22623 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22624 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22625 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22626 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22627 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22628 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22629 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22630 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22635 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22640 elf32_arm_target_format (void)
22643 return (target_big_endian
22644 ? "elf32-bigarm-symbian"
22645 : "elf32-littlearm-symbian");
22646 #elif defined (TE_VXWORKS)
22647 return (target_big_endian
22648 ? "elf32-bigarm-vxworks"
22649 : "elf32-littlearm-vxworks");
22650 #elif defined (TE_NACL)
22651 return (target_big_endian
22652 ? "elf32-bigarm-nacl"
22653 : "elf32-littlearm-nacl");
22655 if (target_big_endian)
22656 return "elf32-bigarm";
22658 return "elf32-littlearm";
22663 armelf_frob_symbol (symbolS * symp,
22666 elf_frob_symbol (symp, puntp);
22670 /* MD interface: Finalization. */
22675 literal_pool * pool;
22677 /* Ensure that all the IT blocks are properly closed. */
22678 check_it_blocks_finished ();
22680 for (pool = list_of_pools; pool; pool = pool->next)
22682 /* Put it at the end of the relevant section. */
22683 subseg_set (pool->section, pool->sub_section);
22685 arm_elf_change_section ();
22692 /* Remove any excess mapping symbols generated for alignment frags in
22693 SEC. We may have created a mapping symbol before a zero byte
22694 alignment; remove it if there's a mapping symbol after the
22697 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22698 void *dummy ATTRIBUTE_UNUSED)
22700 segment_info_type *seginfo = seg_info (sec);
22703 if (seginfo == NULL || seginfo->frchainP == NULL)
22706 for (fragp = seginfo->frchainP->frch_root;
22708 fragp = fragp->fr_next)
22710 symbolS *sym = fragp->tc_frag_data.last_map;
22711 fragS *next = fragp->fr_next;
22713 /* Variable-sized frags have been converted to fixed size by
22714 this point. But if this was variable-sized to start with,
22715 there will be a fixed-size frag after it. So don't handle
22717 if (sym == NULL || next == NULL)
22720 if (S_GET_VALUE (sym) < next->fr_address)
22721 /* Not at the end of this frag. */
22723 know (S_GET_VALUE (sym) == next->fr_address);
22727 if (next->tc_frag_data.first_map != NULL)
22729 /* Next frag starts with a mapping symbol. Discard this
22731 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22735 if (next->fr_next == NULL)
22737 /* This mapping symbol is at the end of the section. Discard
22739 know (next->fr_fix == 0 && next->fr_var == 0);
22740 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22744 /* As long as we have empty frags without any mapping symbols,
22746 /* If the next frag is non-empty and does not start with a
22747 mapping symbol, then this mapping symbol is required. */
22748 if (next->fr_address != next->fr_next->fr_address)
22751 next = next->fr_next;
22753 while (next != NULL);
22758 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22762 arm_adjust_symtab (void)
22767 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22769 if (ARM_IS_THUMB (sym))
22771 if (THUMB_IS_FUNC (sym))
22773 /* Mark the symbol as a Thumb function. */
22774 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22775 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22776 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22778 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22779 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22781 as_bad (_("%s: unexpected function type: %d"),
22782 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22784 else switch (S_GET_STORAGE_CLASS (sym))
22787 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22790 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22793 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22801 if (ARM_IS_INTERWORK (sym))
22802 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22809 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22811 if (ARM_IS_THUMB (sym))
22813 elf_symbol_type * elf_sym;
22815 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22816 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22818 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22819 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22821 /* If it's a .thumb_func, declare it as so,
22822 otherwise tag label as .code 16. */
22823 if (THUMB_IS_FUNC (sym))
22824 elf_sym->internal_elf_sym.st_target_internal
22825 = ST_BRANCH_TO_THUMB;
22826 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22827 elf_sym->internal_elf_sym.st_info =
22828 ELF_ST_INFO (bind, STT_ARM_16BIT);
22833 /* Remove any overlapping mapping symbols generated by alignment frags. */
22834 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22835 /* Now do generic ELF adjustments. */
22836 elf_adjust_symtab ();
22840 /* MD interface: Initialization. */
22843 set_constant_flonums (void)
22847 for (i = 0; i < NUM_FLOAT_VALS; i++)
22848 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22852 /* Auto-select Thumb mode if it's the only available instruction set for the
22853 given architecture. */
22856 autoselect_thumb_from_cpu_variant (void)
22858 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22859 opcode_select (16);
22868 if ( (arm_ops_hsh = hash_new ()) == NULL
22869 || (arm_cond_hsh = hash_new ()) == NULL
22870 || (arm_shift_hsh = hash_new ()) == NULL
22871 || (arm_psr_hsh = hash_new ()) == NULL
22872 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22873 || (arm_reg_hsh = hash_new ()) == NULL
22874 || (arm_reloc_hsh = hash_new ()) == NULL
22875 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22876 as_fatal (_("virtual memory exhausted"));
22878 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22879 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22880 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22881 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22882 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22883 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22884 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22885 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22886 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22887 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22888 (void *) (v7m_psrs + i));
22889 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22890 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22892 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22894 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22895 (void *) (barrier_opt_names + i));
22897 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22899 struct reloc_entry * entry = reloc_names + i;
22901 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22902 /* This makes encode_branch() use the EABI versions of this relocation. */
22903 entry->reloc = BFD_RELOC_UNUSED;
22905 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22909 set_constant_flonums ();
22911 /* Set the cpu variant based on the command-line options. We prefer
22912 -mcpu= over -march= if both are set (as for GCC); and we prefer
22913 -mfpu= over any other way of setting the floating point unit.
22914 Use of legacy options with new options are faulted. */
22917 if (mcpu_cpu_opt || march_cpu_opt)
22918 as_bad (_("use of old and new-style options to set CPU type"));
22920 mcpu_cpu_opt = legacy_cpu;
22922 else if (!mcpu_cpu_opt)
22923 mcpu_cpu_opt = march_cpu_opt;
22928 as_bad (_("use of old and new-style options to set FPU type"));
22930 mfpu_opt = legacy_fpu;
22932 else if (!mfpu_opt)
22934 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22935 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22936 /* Some environments specify a default FPU. If they don't, infer it
22937 from the processor. */
22939 mfpu_opt = mcpu_fpu_opt;
22941 mfpu_opt = march_fpu_opt;
22943 mfpu_opt = &fpu_default;
22949 if (mcpu_cpu_opt != NULL)
22950 mfpu_opt = &fpu_default;
22951 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22952 mfpu_opt = &fpu_arch_vfp_v2;
22954 mfpu_opt = &fpu_arch_fpa;
22960 mcpu_cpu_opt = &cpu_default;
22961 selected_cpu = cpu_default;
22965 selected_cpu = *mcpu_cpu_opt;
22967 mcpu_cpu_opt = &arm_arch_any;
22970 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22972 autoselect_thumb_from_cpu_variant ();
22974 arm_arch_used = thumb_arch_used = arm_arch_none;
22976 #if defined OBJ_COFF || defined OBJ_ELF
22978 unsigned int flags = 0;
22980 #if defined OBJ_ELF
22981 flags = meabi_flags;
22983 switch (meabi_flags)
22985 case EF_ARM_EABI_UNKNOWN:
22987 /* Set the flags in the private structure. */
22988 if (uses_apcs_26) flags |= F_APCS26;
22989 if (support_interwork) flags |= F_INTERWORK;
22990 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22991 if (pic_code) flags |= F_PIC;
22992 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22993 flags |= F_SOFT_FLOAT;
22995 switch (mfloat_abi_opt)
22997 case ARM_FLOAT_ABI_SOFT:
22998 case ARM_FLOAT_ABI_SOFTFP:
22999 flags |= F_SOFT_FLOAT;
23002 case ARM_FLOAT_ABI_HARD:
23003 if (flags & F_SOFT_FLOAT)
23004 as_bad (_("hard-float conflicts with specified fpu"));
23008 /* Using pure-endian doubles (even if soft-float). */
23009 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23010 flags |= F_VFP_FLOAT;
23012 #if defined OBJ_ELF
23013 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23014 flags |= EF_ARM_MAVERICK_FLOAT;
23017 case EF_ARM_EABI_VER4:
23018 case EF_ARM_EABI_VER5:
23019 /* No additional flags to set. */
23026 bfd_set_private_flags (stdoutput, flags);
23028 /* We have run out flags in the COFF header to encode the
23029 status of ATPCS support, so instead we create a dummy,
23030 empty, debug section called .arm.atpcs. */
23035 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23039 bfd_set_section_flags
23040 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23041 bfd_set_section_size (stdoutput, sec, 0);
23042 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23048 /* Record the CPU type as well. */
23049 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23050 mach = bfd_mach_arm_iWMMXt2;
23051 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23052 mach = bfd_mach_arm_iWMMXt;
23053 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23054 mach = bfd_mach_arm_XScale;
23055 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23056 mach = bfd_mach_arm_ep9312;
23057 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23058 mach = bfd_mach_arm_5TE;
23059 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23061 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23062 mach = bfd_mach_arm_5T;
23064 mach = bfd_mach_arm_5;
23066 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23068 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23069 mach = bfd_mach_arm_4T;
23071 mach = bfd_mach_arm_4;
23073 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23074 mach = bfd_mach_arm_3M;
23075 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23076 mach = bfd_mach_arm_3;
23077 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23078 mach = bfd_mach_arm_2a;
23079 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23080 mach = bfd_mach_arm_2;
23082 mach = bfd_mach_arm_unknown;
23084 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23087 /* Command line processing. */
23090 Invocation line includes a switch not recognized by the base assembler.
23091 See if it's a processor-specific option.
23093 This routine is somewhat complicated by the need for backwards
23094 compatibility (since older releases of gcc can't be changed).
23095 The new options try to make the interface as compatible as
23098 New options (supported) are:
23100 -mcpu=<cpu name> Assemble for selected processor
23101 -march=<architecture name> Assemble for selected architecture
23102 -mfpu=<fpu architecture> Assemble for selected FPU.
23103 -EB/-mbig-endian Big-endian
23104 -EL/-mlittle-endian Little-endian
23105 -k Generate PIC code
23106 -mthumb Start in Thumb mode
23107 -mthumb-interwork Code supports ARM/Thumb interworking
23109 -m[no-]warn-deprecated Warn about deprecated features
23111 For now we will also provide support for:
23113 -mapcs-32 32-bit Program counter
23114 -mapcs-26 26-bit Program counter
23115 -macps-float Floats passed in FP registers
23116 -mapcs-reentrant Reentrant code
23118 (sometime these will probably be replaced with -mapcs=<list of options>
23119 and -matpcs=<list of options>)
23121 The remaining options are only supported for back-wards compatibility.
23122 Cpu variants, the arm part is optional:
23123 -m[arm]1 Currently not supported.
23124 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23125 -m[arm]3 Arm 3 processor
23126 -m[arm]6[xx], Arm 6 processors
23127 -m[arm]7[xx][t][[d]m] Arm 7 processors
23128 -m[arm]8[10] Arm 8 processors
23129 -m[arm]9[20][tdmi] Arm 9 processors
23130 -mstrongarm[110[0]] StrongARM processors
23131 -mxscale XScale processors
23132 -m[arm]v[2345[t[e]]] Arm architectures
23133 -mall All (except the ARM1)
23135 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23136 -mfpe-old (No float load/store multiples)
23137 -mvfpxd VFP Single precision
23139 -mno-fpu Disable all floating point instructions
23141 The following CPU names are recognized:
23142 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23143 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23144 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23145 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23146 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23147 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23148 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23152 const char * md_shortopts = "m:k";
23154 #ifdef ARM_BI_ENDIAN
23155 #define OPTION_EB (OPTION_MD_BASE + 0)
23156 #define OPTION_EL (OPTION_MD_BASE + 1)
23158 #if TARGET_BYTES_BIG_ENDIAN
23159 #define OPTION_EB (OPTION_MD_BASE + 0)
23161 #define OPTION_EL (OPTION_MD_BASE + 1)
23164 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23166 struct option md_longopts[] =
23169 {"EB", no_argument, NULL, OPTION_EB},
23172 {"EL", no_argument, NULL, OPTION_EL},
23174 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23175 {NULL, no_argument, NULL, 0}
23178 size_t md_longopts_size = sizeof (md_longopts);
23180 struct arm_option_table
23182 char *option; /* Option name to match. */
23183 char *help; /* Help information. */
23184 int *var; /* Variable to change. */
23185 int value; /* What to change it to. */
23186 char *deprecated; /* If non-null, print this message. */
23189 struct arm_option_table arm_opts[] =
23191 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23192 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23193 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23194 &support_interwork, 1, NULL},
23195 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23196 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23197 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23199 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23200 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23201 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23202 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23205 /* These are recognized by the assembler, but have no affect on code. */
23206 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23207 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23209 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23210 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23211 &warn_on_deprecated, 0, NULL},
23212 {NULL, NULL, NULL, 0, NULL}
23215 struct arm_legacy_option_table
23217 char *option; /* Option name to match. */
23218 const arm_feature_set **var; /* Variable to change. */
23219 const arm_feature_set value; /* What to change it to. */
23220 char *deprecated; /* If non-null, print this message. */
23223 const struct arm_legacy_option_table arm_legacy_opts[] =
23225 /* DON'T add any new processors to this list -- we want the whole list
23226 to go away... Add them to the processors table instead. */
23227 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23228 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23229 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23230 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23231 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23232 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23233 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23234 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23235 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23236 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23237 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23238 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23239 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23240 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23241 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23242 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23243 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23244 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23245 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23246 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23247 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23248 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23249 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23250 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23251 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23252 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23253 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23254 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23255 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23256 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23257 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23258 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23259 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23260 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23261 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23262 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23263 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23264 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23265 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23266 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23267 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23268 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23269 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23270 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23271 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23272 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23273 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23274 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23275 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23276 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23277 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23278 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23279 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23280 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23281 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23282 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23283 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23284 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23285 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23286 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23287 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23288 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23289 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23290 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23291 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23292 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23293 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23294 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23295 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23296 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23297 N_("use -mcpu=strongarm110")},
23298 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23299 N_("use -mcpu=strongarm1100")},
23300 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23301 N_("use -mcpu=strongarm1110")},
23302 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23303 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23304 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23306 /* Architecture variants -- don't add any more to this list either. */
23307 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23308 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23309 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23310 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23311 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23312 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23313 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23314 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23315 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23316 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23317 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23318 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23319 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23320 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23321 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23322 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23323 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23324 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23326 /* Floating point variants -- don't add any more to this list either. */
23327 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23328 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23329 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23330 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23331 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23333 {NULL, NULL, ARM_ARCH_NONE, NULL}
23336 struct arm_cpu_option_table
23340 const arm_feature_set value;
23341 /* For some CPUs we assume an FPU unless the user explicitly sets
23343 const arm_feature_set default_fpu;
23344 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23346 const char *canonical_name;
23349 /* This list should, at a minimum, contain all the cpu names
23350 recognized by GCC. */
23351 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23352 static const struct arm_cpu_option_table arm_cpus[] =
23354 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23355 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23356 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23357 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23358 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23359 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23360 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23361 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23362 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23363 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23364 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23365 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23366 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23367 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23368 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23369 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23370 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23371 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23372 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23373 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23374 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23375 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23376 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23377 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23378 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23379 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23380 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23381 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23382 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23383 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23384 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23385 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23386 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23387 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23388 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23389 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23390 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23391 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23392 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23393 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23394 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23395 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23396 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23397 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23398 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23399 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23400 /* For V5 or later processors we default to using VFP; but the user
23401 should really set the FPU type explicitly. */
23402 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23403 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23404 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23405 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23406 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23407 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23408 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23409 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23410 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23411 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23412 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23413 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23414 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23415 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23416 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23417 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23418 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23419 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23420 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23421 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23423 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23424 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23425 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23426 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23427 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23428 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23429 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23430 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23431 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23433 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23434 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23435 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23436 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23437 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23438 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23439 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23440 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23441 FPU_NONE, "Cortex-A5"),
23442 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23443 FPU_ARCH_NEON_VFP_V4,
23445 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23446 ARM_FEATURE (0, FPU_VFP_V3
23447 | FPU_NEON_EXT_V1),
23449 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23450 ARM_FEATURE (0, FPU_VFP_V3
23451 | FPU_NEON_EXT_V1),
23453 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23454 FPU_ARCH_NEON_VFP_V4,
23456 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23457 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23459 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23460 FPU_NONE, "Cortex-R5"),
23461 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23462 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23463 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23464 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23465 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23466 /* ??? XSCALE is really an architecture. */
23467 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23468 /* ??? iwmmxt is not a processor. */
23469 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23470 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23471 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23473 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23476 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23480 struct arm_arch_option_table
23484 const arm_feature_set value;
23485 const arm_feature_set default_fpu;
23488 /* This list should, at a minimum, contain all the architecture names
23489 recognized by GCC. */
23490 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23491 static const struct arm_arch_option_table arm_archs[] =
23493 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23494 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23495 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23496 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23497 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23498 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23499 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23500 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23501 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23502 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23503 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23504 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23505 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23506 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23507 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23508 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23509 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23510 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23511 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23512 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23513 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23514 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23515 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23516 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23517 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23518 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23519 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23520 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23521 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23522 /* The official spelling of the ARMv7 profile variants is the dashed form.
23523 Accept the non-dashed form for compatibility with old toolchains. */
23524 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23525 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23526 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23527 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23528 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23529 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23530 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23531 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23532 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23533 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23534 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23535 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23537 #undef ARM_ARCH_OPT
23539 /* ISA extensions in the co-processor and main instruction set space. */
23540 struct arm_option_extension_value_table
23544 const arm_feature_set value;
23545 const arm_feature_set allowed_archs;
23548 /* The following table must be in alphabetical order with a NULL last entry.
23550 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23551 static const struct arm_option_extension_value_table arm_extensions[] =
23553 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23554 ARM_FEATURE (ARM_EXT_V8, 0)),
23555 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23556 ARM_FEATURE (ARM_EXT_V8, 0)),
23557 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23558 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23559 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23560 ARM_EXT_OPT ("iwmmxt2",
23561 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23562 ARM_EXT_OPT ("maverick",
23563 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23564 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23565 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23566 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23567 ARM_FEATURE (ARM_EXT_V8, 0)),
23568 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23569 ARM_FEATURE (ARM_EXT_V6M, 0)),
23570 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23571 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23572 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23574 ARM_FEATURE (ARM_EXT_V7A, 0)),
23575 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23576 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23580 /* ISA floating-point and Advanced SIMD extensions. */
23581 struct arm_option_fpu_value_table
23584 const arm_feature_set value;
23587 /* This list should, at a minimum, contain all the fpu names
23588 recognized by GCC. */
23589 static const struct arm_option_fpu_value_table arm_fpus[] =
23591 {"softfpa", FPU_NONE},
23592 {"fpe", FPU_ARCH_FPE},
23593 {"fpe2", FPU_ARCH_FPE},
23594 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23595 {"fpa", FPU_ARCH_FPA},
23596 {"fpa10", FPU_ARCH_FPA},
23597 {"fpa11", FPU_ARCH_FPA},
23598 {"arm7500fe", FPU_ARCH_FPA},
23599 {"softvfp", FPU_ARCH_VFP},
23600 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23601 {"vfp", FPU_ARCH_VFP_V2},
23602 {"vfp9", FPU_ARCH_VFP_V2},
23603 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23604 {"vfp10", FPU_ARCH_VFP_V2},
23605 {"vfp10-r0", FPU_ARCH_VFP_V1},
23606 {"vfpxd", FPU_ARCH_VFP_V1xD},
23607 {"vfpv2", FPU_ARCH_VFP_V2},
23608 {"vfpv3", FPU_ARCH_VFP_V3},
23609 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23610 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23611 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23612 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23613 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23614 {"arm1020t", FPU_ARCH_VFP_V1},
23615 {"arm1020e", FPU_ARCH_VFP_V2},
23616 {"arm1136jfs", FPU_ARCH_VFP_V2},
23617 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23618 {"maverick", FPU_ARCH_MAVERICK},
23619 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23620 {"neon-fp16", FPU_ARCH_NEON_FP16},
23621 {"vfpv4", FPU_ARCH_VFP_V4},
23622 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23623 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23624 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23625 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
23626 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
23627 {"crypto-neon-fp-armv8",
23628 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
23629 {NULL, ARM_ARCH_NONE}
23632 struct arm_option_value_table
23638 static const struct arm_option_value_table arm_float_abis[] =
23640 {"hard", ARM_FLOAT_ABI_HARD},
23641 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23642 {"soft", ARM_FLOAT_ABI_SOFT},
23647 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23648 static const struct arm_option_value_table arm_eabis[] =
23650 {"gnu", EF_ARM_EABI_UNKNOWN},
23651 {"4", EF_ARM_EABI_VER4},
23652 {"5", EF_ARM_EABI_VER5},
23657 struct arm_long_option_table
23659 char * option; /* Substring to match. */
23660 char * help; /* Help information. */
23661 int (* func) (char * subopt); /* Function to decode sub-option. */
23662 char * deprecated; /* If non-null, print this message. */
23666 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23668 arm_feature_set *ext_set = (arm_feature_set *)
23669 xmalloc (sizeof (arm_feature_set));
23671 /* We insist on extensions being specified in alphabetical order, and with
23672 extensions being added before being removed. We achieve this by having
23673 the global ARM_EXTENSIONS table in alphabetical order, and using the
23674 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23675 or removing it (0) and only allowing it to change in the order
23677 const struct arm_option_extension_value_table * opt = NULL;
23678 int adding_value = -1;
23680 /* Copy the feature set, so that we can modify it. */
23681 *ext_set = **opt_p;
23684 while (str != NULL && *str != 0)
23691 as_bad (_("invalid architectural extension"));
23696 ext = strchr (str, '+');
23701 len = strlen (str);
23703 if (len >= 2 && strncmp (str, "no", 2) == 0)
23705 if (adding_value != 0)
23708 opt = arm_extensions;
23716 if (adding_value == -1)
23719 opt = arm_extensions;
23721 else if (adding_value != 1)
23723 as_bad (_("must specify extensions to add before specifying "
23724 "those to remove"));
23731 as_bad (_("missing architectural extension"));
23735 gas_assert (adding_value != -1);
23736 gas_assert (opt != NULL);
23738 /* Scan over the options table trying to find an exact match. */
23739 for (; opt->name != NULL; opt++)
23740 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23742 /* Check we can apply the extension to this architecture. */
23743 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23745 as_bad (_("extension does not apply to the base architecture"));
23749 /* Add or remove the extension. */
23751 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23753 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23758 if (opt->name == NULL)
23760 /* Did we fail to find an extension because it wasn't specified in
23761 alphabetical order, or because it does not exist? */
23763 for (opt = arm_extensions; opt->name != NULL; opt++)
23764 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23767 if (opt->name == NULL)
23768 as_bad (_("unknown architectural extension `%s'"), str);
23770 as_bad (_("architectural extensions must be specified in "
23771 "alphabetical order"));
23777 /* We should skip the extension we've just matched the next time
23789 arm_parse_cpu (char *str)
23791 const struct arm_cpu_option_table *opt;
23792 char *ext = strchr (str, '+');
23798 len = strlen (str);
23802 as_bad (_("missing cpu name `%s'"), str);
23806 for (opt = arm_cpus; opt->name != NULL; opt++)
23807 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23809 mcpu_cpu_opt = &opt->value;
23810 mcpu_fpu_opt = &opt->default_fpu;
23811 if (opt->canonical_name)
23812 strcpy (selected_cpu_name, opt->canonical_name);
23817 for (i = 0; i < len; i++)
23818 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23819 selected_cpu_name[i] = 0;
23823 return arm_parse_extension (ext, &mcpu_cpu_opt);
23828 as_bad (_("unknown cpu `%s'"), str);
23833 arm_parse_arch (char *str)
23835 const struct arm_arch_option_table *opt;
23836 char *ext = strchr (str, '+');
23842 len = strlen (str);
23846 as_bad (_("missing architecture name `%s'"), str);
23850 for (opt = arm_archs; opt->name != NULL; opt++)
23851 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23853 march_cpu_opt = &opt->value;
23854 march_fpu_opt = &opt->default_fpu;
23855 strcpy (selected_cpu_name, opt->name);
23858 return arm_parse_extension (ext, &march_cpu_opt);
23863 as_bad (_("unknown architecture `%s'\n"), str);
23868 arm_parse_fpu (char * str)
23870 const struct arm_option_fpu_value_table * opt;
23872 for (opt = arm_fpus; opt->name != NULL; opt++)
23873 if (streq (opt->name, str))
23875 mfpu_opt = &opt->value;
23879 as_bad (_("unknown floating point format `%s'\n"), str);
23884 arm_parse_float_abi (char * str)
23886 const struct arm_option_value_table * opt;
23888 for (opt = arm_float_abis; opt->name != NULL; opt++)
23889 if (streq (opt->name, str))
23891 mfloat_abi_opt = opt->value;
23895 as_bad (_("unknown floating point abi `%s'\n"), str);
23901 arm_parse_eabi (char * str)
23903 const struct arm_option_value_table *opt;
23905 for (opt = arm_eabis; opt->name != NULL; opt++)
23906 if (streq (opt->name, str))
23908 meabi_flags = opt->value;
23911 as_bad (_("unknown EABI `%s'\n"), str);
23917 arm_parse_it_mode (char * str)
23919 bfd_boolean ret = TRUE;
23921 if (streq ("arm", str))
23922 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23923 else if (streq ("thumb", str))
23924 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23925 else if (streq ("always", str))
23926 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23927 else if (streq ("never", str))
23928 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23931 as_bad (_("unknown implicit IT mode `%s', should be "\
23932 "arm, thumb, always, or never."), str);
23939 struct arm_long_option_table arm_long_opts[] =
23941 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23942 arm_parse_cpu, NULL},
23943 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23944 arm_parse_arch, NULL},
23945 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23946 arm_parse_fpu, NULL},
23947 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23948 arm_parse_float_abi, NULL},
23950 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23951 arm_parse_eabi, NULL},
23953 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23954 arm_parse_it_mode, NULL},
23955 {NULL, NULL, 0, NULL}
23959 md_parse_option (int c, char * arg)
23961 struct arm_option_table *opt;
23962 const struct arm_legacy_option_table *fopt;
23963 struct arm_long_option_table *lopt;
23969 target_big_endian = 1;
23975 target_big_endian = 0;
23979 case OPTION_FIX_V4BX:
23984 /* Listing option. Just ignore these, we don't support additional
23989 for (opt = arm_opts; opt->option != NULL; opt++)
23991 if (c == opt->option[0]
23992 && ((arg == NULL && opt->option[1] == 0)
23993 || streq (arg, opt->option + 1)))
23995 /* If the option is deprecated, tell the user. */
23996 if (warn_on_deprecated && opt->deprecated != NULL)
23997 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23998 arg ? arg : "", _(opt->deprecated));
24000 if (opt->var != NULL)
24001 *opt->var = opt->value;
24007 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24009 if (c == fopt->option[0]
24010 && ((arg == NULL && fopt->option[1] == 0)
24011 || streq (arg, fopt->option + 1)))
24013 /* If the option is deprecated, tell the user. */
24014 if (warn_on_deprecated && fopt->deprecated != NULL)
24015 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24016 arg ? arg : "", _(fopt->deprecated));
24018 if (fopt->var != NULL)
24019 *fopt->var = &fopt->value;
24025 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24027 /* These options are expected to have an argument. */
24028 if (c == lopt->option[0]
24030 && strncmp (arg, lopt->option + 1,
24031 strlen (lopt->option + 1)) == 0)
24033 /* If the option is deprecated, tell the user. */
24034 if (warn_on_deprecated && lopt->deprecated != NULL)
24035 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24036 _(lopt->deprecated));
24038 /* Call the sup-option parser. */
24039 return lopt->func (arg + strlen (lopt->option) - 1);
24050 md_show_usage (FILE * fp)
24052 struct arm_option_table *opt;
24053 struct arm_long_option_table *lopt;
24055 fprintf (fp, _(" ARM-specific assembler options:\n"));
24057 for (opt = arm_opts; opt->option != NULL; opt++)
24058 if (opt->help != NULL)
24059 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24061 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24062 if (lopt->help != NULL)
24063 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24067 -EB assemble code for a big-endian cpu\n"));
24072 -EL assemble code for a little-endian cpu\n"));
24076 --fix-v4bx Allow BX in ARMv4 code\n"));
24084 arm_feature_set flags;
24085 } cpu_arch_ver_table;
24087 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24088 least features first. */
24089 static const cpu_arch_ver_table cpu_arch_ver[] =
24095 {4, ARM_ARCH_V5TE},
24096 {5, ARM_ARCH_V5TEJ},
24100 {11, ARM_ARCH_V6M},
24101 {12, ARM_ARCH_V6SM},
24102 {8, ARM_ARCH_V6T2},
24103 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24104 {10, ARM_ARCH_V7R},
24105 {10, ARM_ARCH_V7M},
24106 {14, ARM_ARCH_V8A},
24110 /* Set an attribute if it has not already been set by the user. */
24112 aeabi_set_attribute_int (int tag, int value)
24115 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24116 || !attributes_set_explicitly[tag])
24117 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24121 aeabi_set_attribute_string (int tag, const char *value)
24124 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24125 || !attributes_set_explicitly[tag])
24126 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24129 /* Set the public EABI object attributes. */
24131 aeabi_set_public_attributes (void)
24136 int fp16_optional = 0;
24137 arm_feature_set flags;
24138 arm_feature_set tmp;
24139 const cpu_arch_ver_table *p;
24141 /* Choose the architecture based on the capabilities of the requested cpu
24142 (if any) and/or the instructions actually used. */
24143 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24144 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24145 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24147 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24148 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24150 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24151 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24153 /* Allow the user to override the reported architecture. */
24156 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24157 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24160 /* We need to make sure that the attributes do not identify us as v6S-M
24161 when the only v6S-M feature in use is the Operating System Extensions. */
24162 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24163 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24164 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24168 for (p = cpu_arch_ver; p->val; p++)
24170 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24173 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24177 /* The table lookup above finds the last architecture to contribute
24178 a new feature. Unfortunately, Tag13 is a subset of the union of
24179 v6T2 and v7-M, so it is never seen as contributing a new feature.
24180 We can not search for the last entry which is entirely used,
24181 because if no CPU is specified we build up only those flags
24182 actually used. Perhaps we should separate out the specified
24183 and implicit cases. Avoid taking this path for -march=all by
24184 checking for contradictory v7-A / v7-M features. */
24186 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24187 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24188 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24191 /* Tag_CPU_name. */
24192 if (selected_cpu_name[0])
24196 q = selected_cpu_name;
24197 if (strncmp (q, "armv", 4) == 0)
24202 for (i = 0; q[i]; i++)
24203 q[i] = TOUPPER (q[i]);
24205 aeabi_set_attribute_string (Tag_CPU_name, q);
24208 /* Tag_CPU_arch. */
24209 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24211 /* Tag_CPU_arch_profile. */
24212 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24214 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24216 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24221 if (profile != '\0')
24222 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24224 /* Tag_ARM_ISA_use. */
24225 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24227 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24229 /* Tag_THUMB_ISA_use. */
24230 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24232 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24233 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24235 /* Tag_VFP_arch. */
24236 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24237 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24238 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24239 aeabi_set_attribute_int (Tag_VFP_arch,
24240 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24242 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24245 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24247 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24249 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24252 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24253 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24254 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24255 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24256 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24258 /* Tag_ABI_HardFP_use. */
24259 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24260 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24261 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24263 /* Tag_WMMX_arch. */
24264 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24265 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24266 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24267 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24269 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24270 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24271 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24272 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24274 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24276 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24280 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24285 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24286 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24287 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24291 We set Tag_DIV_use to two when integer divide instructions have been used
24292 in ARM state, or when Thumb integer divide instructions have been used,
24293 but we have no architecture profile set, nor have we any ARM instructions.
24295 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24298 For new architectures we will have to check these tests. */
24299 gas_assert (arch <= TAG_CPU_ARCH_V8);
24300 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24301 aeabi_set_attribute_int (Tag_DIV_use, 0);
24302 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24303 || (profile == '\0'
24304 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24305 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24306 aeabi_set_attribute_int (Tag_DIV_use, 2);
24308 /* Tag_MP_extension_use. */
24309 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24310 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24312 /* Tag Virtualization_use. */
24313 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24315 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24318 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24321 /* Add the default contents for the .ARM.attributes section. */
24325 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24328 aeabi_set_public_attributes ();
24330 #endif /* OBJ_ELF */
24333 /* Parse a .cpu directive. */
24336 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24338 const struct arm_cpu_option_table *opt;
24342 name = input_line_pointer;
24343 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24344 input_line_pointer++;
24345 saved_char = *input_line_pointer;
24346 *input_line_pointer = 0;
24348 /* Skip the first "all" entry. */
24349 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24350 if (streq (opt->name, name))
24352 mcpu_cpu_opt = &opt->value;
24353 selected_cpu = opt->value;
24354 if (opt->canonical_name)
24355 strcpy (selected_cpu_name, opt->canonical_name);
24359 for (i = 0; opt->name[i]; i++)
24360 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24362 selected_cpu_name[i] = 0;
24364 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24365 *input_line_pointer = saved_char;
24366 demand_empty_rest_of_line ();
24369 as_bad (_("unknown cpu `%s'"), name);
24370 *input_line_pointer = saved_char;
24371 ignore_rest_of_line ();
24375 /* Parse a .arch directive. */
24378 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24380 const struct arm_arch_option_table *opt;
24384 name = input_line_pointer;
24385 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24386 input_line_pointer++;
24387 saved_char = *input_line_pointer;
24388 *input_line_pointer = 0;
24390 /* Skip the first "all" entry. */
24391 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24392 if (streq (opt->name, name))
24394 mcpu_cpu_opt = &opt->value;
24395 selected_cpu = opt->value;
24396 strcpy (selected_cpu_name, opt->name);
24397 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24398 *input_line_pointer = saved_char;
24399 demand_empty_rest_of_line ();
24403 as_bad (_("unknown architecture `%s'\n"), name);
24404 *input_line_pointer = saved_char;
24405 ignore_rest_of_line ();
24409 /* Parse a .object_arch directive. */
24412 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24414 const struct arm_arch_option_table *opt;
24418 name = input_line_pointer;
24419 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24420 input_line_pointer++;
24421 saved_char = *input_line_pointer;
24422 *input_line_pointer = 0;
24424 /* Skip the first "all" entry. */
24425 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24426 if (streq (opt->name, name))
24428 object_arch = &opt->value;
24429 *input_line_pointer = saved_char;
24430 demand_empty_rest_of_line ();
24434 as_bad (_("unknown architecture `%s'\n"), name);
24435 *input_line_pointer = saved_char;
24436 ignore_rest_of_line ();
24439 /* Parse a .arch_extension directive. */
24442 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24444 const struct arm_option_extension_value_table *opt;
24447 int adding_value = 1;
24449 name = input_line_pointer;
24450 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24451 input_line_pointer++;
24452 saved_char = *input_line_pointer;
24453 *input_line_pointer = 0;
24455 if (strlen (name) >= 2
24456 && strncmp (name, "no", 2) == 0)
24462 for (opt = arm_extensions; opt->name != NULL; opt++)
24463 if (streq (opt->name, name))
24465 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24467 as_bad (_("architectural extension `%s' is not allowed for the "
24468 "current base architecture"), name);
24473 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24475 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24477 mcpu_cpu_opt = &selected_cpu;
24478 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24479 *input_line_pointer = saved_char;
24480 demand_empty_rest_of_line ();
24484 if (opt->name == NULL)
24485 as_bad (_("unknown architecture `%s'\n"), name);
24487 *input_line_pointer = saved_char;
24488 ignore_rest_of_line ();
24491 /* Parse a .fpu directive. */
24494 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24496 const struct arm_option_fpu_value_table *opt;
24500 name = input_line_pointer;
24501 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24502 input_line_pointer++;
24503 saved_char = *input_line_pointer;
24504 *input_line_pointer = 0;
24506 for (opt = arm_fpus; opt->name != NULL; opt++)
24507 if (streq (opt->name, name))
24509 mfpu_opt = &opt->value;
24510 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24511 *input_line_pointer = saved_char;
24512 demand_empty_rest_of_line ();
24516 as_bad (_("unknown floating point format `%s'\n"), name);
24517 *input_line_pointer = saved_char;
24518 ignore_rest_of_line ();
24521 /* Copy symbol information. */
24524 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24526 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24530 /* Given a symbolic attribute NAME, return the proper integer value.
24531 Returns -1 if the attribute is not known. */
24534 arm_convert_symbolic_attribute (const char *name)
24536 static const struct
24541 attribute_table[] =
24543 /* When you modify this table you should
24544 also modify the list in doc/c-arm.texi. */
24545 #define T(tag) {#tag, tag}
24546 T (Tag_CPU_raw_name),
24549 T (Tag_CPU_arch_profile),
24550 T (Tag_ARM_ISA_use),
24551 T (Tag_THUMB_ISA_use),
24555 T (Tag_Advanced_SIMD_arch),
24556 T (Tag_PCS_config),
24557 T (Tag_ABI_PCS_R9_use),
24558 T (Tag_ABI_PCS_RW_data),
24559 T (Tag_ABI_PCS_RO_data),
24560 T (Tag_ABI_PCS_GOT_use),
24561 T (Tag_ABI_PCS_wchar_t),
24562 T (Tag_ABI_FP_rounding),
24563 T (Tag_ABI_FP_denormal),
24564 T (Tag_ABI_FP_exceptions),
24565 T (Tag_ABI_FP_user_exceptions),
24566 T (Tag_ABI_FP_number_model),
24567 T (Tag_ABI_align_needed),
24568 T (Tag_ABI_align8_needed),
24569 T (Tag_ABI_align_preserved),
24570 T (Tag_ABI_align8_preserved),
24571 T (Tag_ABI_enum_size),
24572 T (Tag_ABI_HardFP_use),
24573 T (Tag_ABI_VFP_args),
24574 T (Tag_ABI_WMMX_args),
24575 T (Tag_ABI_optimization_goals),
24576 T (Tag_ABI_FP_optimization_goals),
24577 T (Tag_compatibility),
24578 T (Tag_CPU_unaligned_access),
24579 T (Tag_FP_HP_extension),
24580 T (Tag_VFP_HP_extension),
24581 T (Tag_ABI_FP_16bit_format),
24582 T (Tag_MPextension_use),
24584 T (Tag_nodefaults),
24585 T (Tag_also_compatible_with),
24586 T (Tag_conformance),
24588 T (Tag_Virtualization_use),
24589 /* We deliberately do not include Tag_MPextension_use_legacy. */
24597 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24598 if (streq (name, attribute_table[i].name))
24599 return attribute_table[i].tag;
24605 /* Apply sym value for relocations only in the case that
24606 they are for local symbols and you have the respective
24607 architectural feature for blx and simple switches. */
24609 arm_apply_sym_value (struct fix * fixP)
24612 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24613 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24615 switch (fixP->fx_r_type)
24617 case BFD_RELOC_ARM_PCREL_BLX:
24618 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24619 if (ARM_IS_FUNC (fixP->fx_addsy))
24623 case BFD_RELOC_ARM_PCREL_CALL:
24624 case BFD_RELOC_THUMB_PCREL_BLX:
24625 if (THUMB_IS_FUNC (fixP->fx_addsy))
24636 #endif /* OBJ_ELF */