1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
56 /* Architectures are the sum of the base and extensions. */
57 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
58 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
59 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
60 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62 /* Some useful combinations: */
63 #define ARM_ANY 0x00ffffff
64 #define ARM_2UP (ARM_ANY - ARM_1)
65 #define ARM_ALL ARM_2UP /* Not arm1 only */
66 #define ARM_3UP 0x00fffffc
67 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
69 #define FPU_CORE 0x80000000
70 #define FPU_FPA10 0x40000000
71 #define FPU_FPA11 0x40000000
74 /* Some useful combinations */
75 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
76 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
83 #define CPU_DEFAULT ARM_ALL
88 #define FPU_DEFAULT FPU_ALL
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
118 CONST char line_separator_chars[] = ";";
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
124 /* Chars that mean this number is a floating point constant */
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
130 /* Prefix characters that indicate the start of an immediate
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
135 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
138 CONST int md_reloc_size = 8; /* Size of relocation record */
140 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
141 2: assemble for Thumb even though target cpu
142 does not support thumb instructions. */
143 typedef struct arm_fix
151 unsigned long instruction;
156 bfd_reloc_code_real_type type;
166 CONST char * template;
170 static CONST struct asm_shift shift[] =
186 #define NO_SHIFT_RESTRICT 1
187 #define SHIFT_RESTRICT 0
189 #define NUM_FLOAT_VALS 8
191 CONST char * fp_const[] =
193 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
196 /* Number of littlenums required to hold an extended precision number. */
197 #define MAX_LITTLENUMS 6
199 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
209 #define CP_T_X 0x00008000
210 #define CP_T_Y 0x00400000
211 #define CP_T_Pre 0x01000000
212 #define CP_T_UD 0x00800000
213 #define CP_T_WB 0x00200000
215 #define CONDS_BIT (0x00100000)
216 #define LOAD_BIT (0x00100000)
217 #define TRANS_BIT (0x00200000)
221 CONST char * template;
225 /* This is to save a hash look-up in the common case. */
226 #define COND_ALWAYS 0xe0000000
228 static CONST struct asm_cond conds[] =
232 {"cs", 0x20000000}, {"hs", 0x20000000},
233 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
248 /* Warning: If the top bit of the set_bits is set, then the standard
249 instruction bitmask is ignored, and the new bitmask is taken from
253 CONST char * template; /* Basic flag string */
254 unsigned long set_bits; /* Bits to set */
257 static CONST struct asm_flg s_flag[] =
263 static CONST struct asm_flg ldr_flags[] =
267 {"bt", 0x00400000 | TRANS_BIT},
274 static CONST struct asm_flg str_flags[] =
278 {"bt", 0x00400000 | TRANS_BIT},
283 static CONST struct asm_flg byte_flag[] =
289 static CONST struct asm_flg cmp_flags[] =
296 static CONST struct asm_flg ldm_flags[] =
309 static CONST struct asm_flg stm_flags[] =
322 static CONST struct asm_flg lfm_flags[] =
329 static CONST struct asm_flg sfm_flags[] =
336 static CONST struct asm_flg round_flags[] =
344 /* The implementation of the FIX instruction is broken on some assemblers,
345 in that it accepts a precision specifier as well as a rounding specifier,
346 despite the fact that this is meaningless. To be more compatible, we
347 accept it as well, though of course it does not set any bits. */
348 static CONST struct asm_flg fix_flags[] =
365 static CONST struct asm_flg except_flag[] =
371 static CONST struct asm_flg cplong_flag[] =
379 CONST char * template;
384 #define SPSR_BIT (1 << 22) /* The bit that distnguishes CPSR and SPSR. */
385 #define PSR_SHIFT 16 /* How many bits to shift the PSR_xxx bits up by. */
387 #define PSR_c (1 << 0)
388 #define PSR_x (1 << 1)
389 #define PSR_s (1 << 2)
390 #define PSR_f (1 << 3)
392 static CONST struct asm_psr psrs[] =
394 {"CPSR", true, PSR_c | PSR_f},
395 {"CPSR_all", true, PSR_c | PSR_f},
396 {"SPSR", false, PSR_c | PSR_f},
397 {"SPSR_all", false, PSR_c | PSR_f},
398 {"CPSR_flg", true, PSR_f},
399 {"CPSR_f", true, PSR_f},
400 {"SPSR_flg", false, PSR_f},
401 {"SPSR_f", false, PSR_f},
402 {"CPSR_c", true, PSR_c},
403 {"CPSR_ctl", true, PSR_c},
404 {"SPSR_c", false, PSR_c},
405 {"SPSR_ctl", false, PSR_c},
406 {"CPSR_x", true, PSR_x},
407 {"CPSR_s", true, PSR_s},
408 {"SPSR_x", false, PSR_x},
409 {"SPSR_s", false, PSR_s},
410 /* For backwards compatability with older toolchain we also
411 support lower case versions of some of these flags. */
412 {"cpsr", true, PSR_c | PSR_f},
413 {"cpsr_all", true, PSR_c | PSR_f},
414 {"spsr", false, PSR_c | PSR_f},
415 {"spsr_all", false, PSR_c | PSR_f},
416 {"cpsr_flg", true, PSR_f},
417 {"cpsr_f", true, PSR_f},
418 {"spsr_flg", false, PSR_f},
419 {"spsr_f", false, PSR_f},
420 {"cpsr_c", true, PSR_c},
421 {"cpsr_ctl", true, PSR_c},
422 {"spsr_c", false, PSR_c},
423 {"spsr_ctl", false, PSR_c}
426 /* Functions called by parser. */
427 /* ARM instructions */
428 static void do_arit PARAMS ((char *, unsigned long));
429 static void do_cmp PARAMS ((char *, unsigned long));
430 static void do_mov PARAMS ((char *, unsigned long));
431 static void do_ldst PARAMS ((char *, unsigned long));
432 static void do_ldmstm PARAMS ((char *, unsigned long));
433 static void do_branch PARAMS ((char *, unsigned long));
434 static void do_swi PARAMS ((char *, unsigned long));
435 /* Pseudo Op codes */
436 static void do_adr PARAMS ((char *, unsigned long));
437 static void do_adrl PARAMS ((char *, unsigned long));
438 static void do_nop PARAMS ((char *, unsigned long));
440 static void do_mul PARAMS ((char *, unsigned long));
441 static void do_mla PARAMS ((char *, unsigned long));
443 static void do_swap PARAMS ((char *, unsigned long));
445 static void do_msr PARAMS ((char *, unsigned long));
446 static void do_mrs PARAMS ((char *, unsigned long));
448 static void do_mull PARAMS ((char *, unsigned long));
450 static void do_bx PARAMS ((char *, unsigned long));
453 /* Coprocessor Instructions */
454 static void do_cdp PARAMS ((char *, unsigned long));
455 static void do_lstc PARAMS ((char *, unsigned long));
456 static void do_co_reg PARAMS ((char *, unsigned long));
457 static void do_fp_ctrl PARAMS ((char *, unsigned long));
458 static void do_fp_ldst PARAMS ((char *, unsigned long));
459 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
460 static void do_fp_dyadic PARAMS ((char *, unsigned long));
461 static void do_fp_monadic PARAMS ((char *, unsigned long));
462 static void do_fp_cmp PARAMS ((char *, unsigned long));
463 static void do_fp_from_reg PARAMS ((char *, unsigned long));
464 static void do_fp_to_reg PARAMS ((char *, unsigned long));
466 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
467 static int arm_reg_parse PARAMS ((char **));
468 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
469 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
470 static int add_to_lit_pool PARAMS ((void));
471 static unsigned validate_immediate PARAMS ((unsigned));
472 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
473 static int validate_offset_imm PARAMS ((unsigned int, int));
474 static void opcode_select PARAMS ((int));
475 static void end_of_line PARAMS ((char *));
476 static int reg_required_here PARAMS ((char **, int));
477 static int psr_required_here PARAMS ((char **));
478 static int co_proc_number PARAMS ((char **));
479 static int cp_opc_expr PARAMS ((char **, int, int));
480 static int cp_reg_required_here PARAMS ((char **, int));
481 static int fp_reg_required_here PARAMS ((char **, int));
482 static int cp_address_offset PARAMS ((char **));
483 static int cp_address_required_here PARAMS ((char **));
484 static int my_get_float_expression PARAMS ((char **));
485 static int skip_past_comma PARAMS ((char **));
486 static int walk_no_bignums PARAMS ((symbolS *));
487 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
488 static int data_op2 PARAMS ((char **));
489 static int fp_op2 PARAMS ((char **));
490 static long reg_list PARAMS ((char **));
491 static void thumb_load_store PARAMS ((char *, int, int));
492 static int decode_shift PARAMS ((char **, int));
493 static int ldst_extend PARAMS ((char **, int));
494 static void thumb_add_sub PARAMS ((char *, int));
495 static void insert_reg PARAMS ((int));
496 static void thumb_shift PARAMS ((char *, int));
497 static void thumb_mov_compare PARAMS ((char *, int));
498 static void set_constant_flonums PARAMS ((void));
499 static valueT md_chars_to_number PARAMS ((char *, int));
500 static void insert_reg_alias PARAMS ((char *, int));
501 static void output_inst PARAMS ((void));
503 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
506 /* ARM instructions take 4bytes in the object file, Thumb instructions
510 /* LONGEST_INST is the longest basic instruction name without conditions or
511 flags. ARM7M has 4 of length 5. */
513 #define LONGEST_INST 5
518 CONST char * template; /* Basic string to match */
519 unsigned long value; /* Basic instruction code */
521 /* Compulsory suffix that must follow conds. If "", then the
522 instruction is not conditional and must have no suffix. */
523 CONST char * comp_suffix;
525 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
526 unsigned long variants; /* Which CPU variants this exists for */
527 /* Function to call to parse args */
528 void (* parms) PARAMS ((char *, unsigned long));
531 static CONST struct asm_opcode insns[] =
533 /* ARM Instructions */
534 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
535 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
536 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
537 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
538 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
539 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
540 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
541 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
542 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
543 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
544 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
545 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
546 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
547 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
548 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
549 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
550 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
551 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
552 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
553 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
554 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
556 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
557 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
559 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
560 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
564 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
565 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
566 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
568 /* ARM 2 multiplies */
569 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
570 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
572 /* ARM 3 - swp instructions */
573 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
575 /* ARM 6 Coprocessor instructions */
576 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
577 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
578 /* ScottB: our code uses 0x0128f000 for msr.
579 NickC: but this is wrong because the bits 16 through 19 are
580 handled by the PSR_xxx defines above. */
582 /* ARM 7M long multiplies - need signed/unsigned flags! */
583 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
584 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
585 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
586 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
588 /* ARM THUMB interworking */
589 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
591 /* Floating point instructions */
592 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
593 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
594 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
595 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
596 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
597 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
598 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
599 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
600 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
607 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
608 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
609 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
610 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
611 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
612 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
613 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
614 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
615 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
616 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
620 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
621 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
622 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
623 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
624 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
625 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
626 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
627 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
628 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
629 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
630 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
631 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
632 be an optional suffix, but part of the instruction. To be compatible,
634 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
635 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
636 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
637 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
639 /* Generic copressor instructions. */
640 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
641 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
642 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
643 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
644 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
647 /* Defines for various bits that we will want to toggle. */
648 #define INST_IMMEDIATE 0x02000000
649 #define OFFSET_REG 0x02000000
650 #define HWOFFSET_IMM 0x00400000
651 #define SHIFT_BY_REG 0x00000010
652 #define PRE_INDEX 0x01000000
653 #define INDEX_UP 0x00800000
654 #define WRITE_BACK 0x00200000
655 #define LDM_TYPE_2_OR_3 0x00400000
657 #define LITERAL_MASK 0xf000f000
658 #define COND_MASK 0xf0000000
659 #define OPCODE_MASK 0xfe1fffff
660 #define DATA_OP_SHIFT 21
662 /* Codes to distinguish the arithmetic instructions. */
673 #define OPCODE_CMP 10
674 #define OPCODE_CMN 11
675 #define OPCODE_ORR 12
676 #define OPCODE_MOV 13
677 #define OPCODE_BIC 14
678 #define OPCODE_MVN 15
680 static void do_t_nop PARAMS ((char *));
681 static void do_t_arit PARAMS ((char *));
682 static void do_t_add PARAMS ((char *));
683 static void do_t_asr PARAMS ((char *));
684 static void do_t_branch9 PARAMS ((char *));
685 static void do_t_branch12 PARAMS ((char *));
686 static void do_t_branch23 PARAMS ((char *));
687 static void do_t_bx PARAMS ((char *));
688 static void do_t_compare PARAMS ((char *));
689 static void do_t_ldmstm PARAMS ((char *));
690 static void do_t_ldr PARAMS ((char *));
691 static void do_t_ldrb PARAMS ((char *));
692 static void do_t_ldrh PARAMS ((char *));
693 static void do_t_lds PARAMS ((char *));
694 static void do_t_lsl PARAMS ((char *));
695 static void do_t_lsr PARAMS ((char *));
696 static void do_t_mov PARAMS ((char *));
697 static void do_t_push_pop PARAMS ((char *));
698 static void do_t_str PARAMS ((char *));
699 static void do_t_strb PARAMS ((char *));
700 static void do_t_strh PARAMS ((char *));
701 static void do_t_sub PARAMS ((char *));
702 static void do_t_swi PARAMS ((char *));
703 static void do_t_adr PARAMS ((char *));
705 #define T_OPCODE_MUL 0x4340
706 #define T_OPCODE_TST 0x4200
707 #define T_OPCODE_CMN 0x42c0
708 #define T_OPCODE_NEG 0x4240
709 #define T_OPCODE_MVN 0x43c0
711 #define T_OPCODE_ADD_R3 0x1800
712 #define T_OPCODE_SUB_R3 0x1a00
713 #define T_OPCODE_ADD_HI 0x4400
714 #define T_OPCODE_ADD_ST 0xb000
715 #define T_OPCODE_SUB_ST 0xb080
716 #define T_OPCODE_ADD_SP 0xa800
717 #define T_OPCODE_ADD_PC 0xa000
718 #define T_OPCODE_ADD_I8 0x3000
719 #define T_OPCODE_SUB_I8 0x3800
720 #define T_OPCODE_ADD_I3 0x1c00
721 #define T_OPCODE_SUB_I3 0x1e00
723 #define T_OPCODE_ASR_R 0x4100
724 #define T_OPCODE_LSL_R 0x4080
725 #define T_OPCODE_LSR_R 0x40c0
726 #define T_OPCODE_ASR_I 0x1000
727 #define T_OPCODE_LSL_I 0x0000
728 #define T_OPCODE_LSR_I 0x0800
730 #define T_OPCODE_MOV_I8 0x2000
731 #define T_OPCODE_CMP_I8 0x2800
732 #define T_OPCODE_CMP_LR 0x4280
733 #define T_OPCODE_MOV_HR 0x4600
734 #define T_OPCODE_CMP_HR 0x4500
736 #define T_OPCODE_LDR_PC 0x4800
737 #define T_OPCODE_LDR_SP 0x9800
738 #define T_OPCODE_STR_SP 0x9000
739 #define T_OPCODE_LDR_IW 0x6800
740 #define T_OPCODE_STR_IW 0x6000
741 #define T_OPCODE_LDR_IH 0x8800
742 #define T_OPCODE_STR_IH 0x8000
743 #define T_OPCODE_LDR_IB 0x7800
744 #define T_OPCODE_STR_IB 0x7000
745 #define T_OPCODE_LDR_RW 0x5800
746 #define T_OPCODE_STR_RW 0x5000
747 #define T_OPCODE_LDR_RH 0x5a00
748 #define T_OPCODE_STR_RH 0x5200
749 #define T_OPCODE_LDR_RB 0x5c00
750 #define T_OPCODE_STR_RB 0x5400
752 #define T_OPCODE_PUSH 0xb400
753 #define T_OPCODE_POP 0xbc00
755 #define T_OPCODE_BRANCH 0xe7fe
757 static int thumb_reg PARAMS ((char ** str, int hi_lo));
759 #define THUMB_SIZE 2 /* Size of thumb instruction. */
760 #define THUMB_REG_LO 0x1
761 #define THUMB_REG_HI 0x2
762 #define THUMB_REG_ANY 0x3
764 #define THUMB_H1 0x0080
765 #define THUMB_H2 0x0040
772 #define THUMB_COMPARE 1
775 #define THUMB_STORE 1
777 #define THUMB_PP_PC_LR 0x0100
779 /* These three are used for immediate shifts, do not alter. */
781 #define THUMB_HALFWORD 1
786 CONST char * template; /* Basic string to match */
787 unsigned long value; /* Basic instruction code */
789 unsigned long variants; /* Which CPU variants this exists for */
790 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
793 static CONST struct thumb_opcode tinsns[] =
795 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
796 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
797 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
798 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
799 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
800 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
801 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
802 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
803 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
804 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
805 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
806 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
807 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
808 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
809 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
810 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
811 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
812 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
813 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
814 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
815 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
816 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
817 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
818 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
819 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
820 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
821 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
822 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
823 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
824 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
825 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
826 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
827 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
828 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
829 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
830 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
831 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
832 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
833 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
834 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
835 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
836 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
837 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
838 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
839 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
840 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
841 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
842 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
843 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
844 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
845 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
846 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
847 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
848 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
849 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
851 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
852 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
861 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
862 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
863 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
869 /* These are the standard names. Users can add aliases with .req */
870 static CONST struct reg_entry reg_table[] =
872 /* Processor Register Numbers. */
873 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
874 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
875 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
876 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
877 /* APCS conventions. */
878 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
879 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
880 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
881 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
882 /* ATPCS additions to APCS conventions. */
883 {"wr", 7}, {"v8", 11},
885 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
886 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
887 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
888 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
889 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
890 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
891 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
892 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
893 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
894 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
895 /* ATPCS additions to float register names. */
896 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
897 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
898 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
899 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
900 /* FIXME: At some point we need to add VFP register names. */
901 /* Array terminator. */
905 #define BAD_ARGS _("Bad arguments to instruction")
906 #define BAD_PC _("r15 not allowed here")
907 #define BAD_FLAGS _("Instruction should not have flags")
908 #define BAD_COND _("Instruction is not conditional")
910 static struct hash_control * arm_ops_hsh = NULL;
911 static struct hash_control * arm_tops_hsh = NULL;
912 static struct hash_control * arm_cond_hsh = NULL;
913 static struct hash_control * arm_shift_hsh = NULL;
914 static struct hash_control * arm_reg_hsh = NULL;
915 static struct hash_control * arm_psr_hsh = NULL;
917 /* This table describes all the machine specific pseudo-ops the assembler
918 has to support. The fields are:
919 pseudo-op name without dot
920 function to call to execute this pseudo-op
921 Integer arg to pass to the function. */
923 static void s_req PARAMS ((int));
924 static void s_align PARAMS ((int));
925 static void s_bss PARAMS ((int));
926 static void s_even PARAMS ((int));
927 static void s_ltorg PARAMS ((int));
928 static void s_arm PARAMS ((int));
929 static void s_thumb PARAMS ((int));
930 static void s_code PARAMS ((int));
931 static void s_force_thumb PARAMS ((int));
932 static void s_thumb_func PARAMS ((int));
933 static void s_thumb_set PARAMS ((int));
934 static void arm_s_text PARAMS ((int));
935 static void arm_s_data PARAMS ((int));
937 static void arm_s_section PARAMS ((int));
938 static void s_arm_elf_cons PARAMS ((int));
941 static int my_get_expression PARAMS ((expressionS *, char **));
943 CONST pseudo_typeS md_pseudo_table[] =
945 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
947 { "align", s_align, 0 },
949 { "thumb", s_thumb, 0 },
950 { "code", s_code, 0 },
951 { "force_thumb", s_force_thumb, 0 },
952 { "thumb_func", s_thumb_func, 0 },
953 { "thumb_set", s_thumb_set, 0 },
954 { "even", s_even, 0 },
955 { "ltorg", s_ltorg, 0 },
956 { "pool", s_ltorg, 0 },
957 /* Allow for the effect of section changes. */
958 { "text", arm_s_text, 0 },
959 { "data", arm_s_data, 0 },
961 { "section", arm_s_section, 0 },
962 { "section.s", arm_s_section, 0 },
963 { "sect", arm_s_section, 0 },
964 { "sect.s", arm_s_section, 0 },
965 { "word", s_arm_elf_cons, 4 },
966 { "long", s_arm_elf_cons, 4 },
970 { "extend", float_cons, 'x' },
971 { "ldouble", float_cons, 'x' },
972 { "packed", float_cons, 'p' },
976 /* Stuff needed to resolve the label ambiguity
986 symbolS * last_label_seen;
987 static int label_is_thumb_function_name = false;
991 #define MAX_LITERAL_POOL_SIZE 1024
993 typedef struct literalS
995 struct expressionS exp;
996 struct arm_it * inst;
999 literalT literals[MAX_LITERAL_POOL_SIZE];
1000 int next_literal_pool_place = 0; /* Next free entry in the pool */
1001 int lit_pool_num = 1; /* Next literal pool number */
1002 symbolS * current_poolP = NULL;
1009 if (current_poolP == NULL)
1010 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1011 (valueT) 0, &zero_address_frag);
1013 /* Check if this literal value is already in the pool: */
1014 while (lit_count < next_literal_pool_place)
1016 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1017 && inst.reloc.exp.X_op == O_constant
1018 && literals[lit_count].exp.X_add_number
1019 == inst.reloc.exp.X_add_number
1020 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1025 if (lit_count == next_literal_pool_place) /* new entry */
1027 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1029 inst.error = _("Literal Pool Overflow");
1033 literals[next_literal_pool_place].exp = inst.reloc.exp;
1034 lit_count = next_literal_pool_place++;
1037 inst.reloc.exp.X_op = O_symbol;
1038 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1039 inst.reloc.exp.X_add_symbol = current_poolP;
1044 /* Can't use symbol_new here, so have to create a symbol and then at
1045 a later date assign it a value. Thats what these functions do. */
1047 symbol_locate (symbolP, name, segment, valu, frag)
1049 CONST char * name; /* It is copied, the caller can modify */
1050 segT segment; /* Segment identifier (SEG_<something>) */
1051 valueT valu; /* Symbol value */
1052 fragS * frag; /* Associated fragment */
1054 unsigned int name_length;
1055 char * preserved_copy_of_name;
1057 name_length = strlen (name) + 1; /* +1 for \0 */
1058 obstack_grow (¬es, name, name_length);
1059 preserved_copy_of_name = obstack_finish (¬es);
1060 #ifdef STRIP_UNDERSCORE
1061 if (preserved_copy_of_name[0] == '_')
1062 preserved_copy_of_name++;
1065 #ifdef tc_canonicalize_symbol_name
1066 preserved_copy_of_name =
1067 tc_canonicalize_symbol_name (preserved_copy_of_name);
1070 S_SET_NAME (symbolP, preserved_copy_of_name);
1072 S_SET_SEGMENT (symbolP, segment);
1073 S_SET_VALUE (symbolP, valu);
1074 symbol_clear_list_pointers(symbolP);
1076 symbol_set_frag (symbolP, frag);
1078 /* Link to end of symbol chain. */
1080 extern int symbol_table_frozen;
1081 if (symbol_table_frozen)
1085 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1087 obj_symbol_new_hook (symbolP);
1089 #ifdef tc_symbol_new_hook
1090 tc_symbol_new_hook (symbolP);
1094 verify_symbol_chain (symbol_rootP, symbol_lastP);
1095 #endif /* DEBUG_SYMS */
1098 /* Check that an immediate is valid, and if so,
1099 convert it to the right format. */
1101 validate_immediate (val)
1107 #define rotate_left(v, n) (v << n | v >> (32 - n))
1109 for (i = 0; i < 32; i += 2)
1110 if ((a = rotate_left (val, i)) <= 0xff)
1111 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1116 /* Check to see if an immediate can be computed as two seperate immediate
1117 values, added together. We already know that this value cannot be
1118 computed by just one ARM instruction. */
1120 validate_immediate_twopart (val, highpart)
1122 unsigned int * highpart;
1127 for (i = 0; i < 32; i += 2)
1128 if (((a = rotate_left (val, i)) & 0xff) != 0)
1134 * highpart = (a >> 8) | ((i + 24) << 7);
1136 else if (a & 0xff0000)
1141 * highpart = (a >> 16) | ((i + 16) << 7);
1145 assert (a & 0xff000000);
1147 * highpart = (a >> 24) | ((i + 8) << 7);
1150 return (a & 0xff) | (i << 7);
1157 validate_offset_imm (val, hwse)
1161 if ((hwse && val > 255) || val > 4095)
1169 int a ATTRIBUTE_UNUSED;
1171 as_bad (_("Invalid syntax for .req directive."));
1176 int ignore ATTRIBUTE_UNUSED;
1178 /* We don't support putting frags in the BSS segment, we fake it by
1179 marking in_bss, then looking at s_skip for clues?.. */
1180 subseg_set (bss_section, 0);
1181 demand_empty_rest_of_line ();
1186 int ignore ATTRIBUTE_UNUSED;
1188 if (!need_pass_2) /* Never make frag if expect extra pass. */
1189 frag_align (1, 0, 0);
1191 record_alignment (now_seg, 1);
1193 demand_empty_rest_of_line ();
1198 int ignored ATTRIBUTE_UNUSED;
1203 if (current_poolP == NULL)
1206 /* Align pool as you have word accesses */
1207 /* Only make a frag if we have to ... */
1209 frag_align (2, 0, 0);
1211 record_alignment (now_seg, 2);
1213 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1215 symbol_locate (current_poolP, sym_name, now_seg,
1216 (valueT) frag_now_fix (), frag_now);
1217 symbol_table_insert (current_poolP);
1219 ARM_SET_THUMB (current_poolP, thumb_mode);
1221 #if defined OBJ_COFF || defined OBJ_ELF
1222 ARM_SET_INTERWORK (current_poolP, support_interwork);
1225 while (lit_count < next_literal_pool_place)
1226 /* First output the expression in the instruction to the pool. */
1227 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1229 next_literal_pool_place = 0;
1230 current_poolP = NULL;
1234 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1235 int unused ATTRIBUTE_UNUSED;
1238 register long temp_fill;
1239 long max_alignment = 15;
1241 temp = get_absolute_expression ();
1242 if (temp > max_alignment)
1243 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1246 as_bad (_("Alignment negative. 0 assumed."));
1250 if (*input_line_pointer == ',')
1252 input_line_pointer++;
1253 temp_fill = get_absolute_expression ();
1261 /* Only make a frag if we HAVE to. . . */
1262 if (temp && !need_pass_2)
1263 frag_align (temp, (int) temp_fill, 0);
1264 demand_empty_rest_of_line ();
1266 record_alignment (now_seg, temp);
1270 s_force_thumb (ignore)
1271 int ignore ATTRIBUTE_UNUSED;
1273 /* If we are not already in thumb mode go into it, EVEN if
1274 the target processor does not support thumb instructions.
1275 This is used by gcc/config/arm/lib1funcs.asm for example
1276 to compile interworking support functions even if the
1277 target processor should not support interworking. */
1283 record_alignment (now_seg, 1);
1286 demand_empty_rest_of_line ();
1290 s_thumb_func (ignore)
1291 int ignore ATTRIBUTE_UNUSED;
1293 /* The following label is the name/address of the start of a Thumb function.
1294 We need to know this for the interworking support. */
1296 label_is_thumb_function_name = true;
1298 demand_empty_rest_of_line ();
1301 /* Perform a .set directive, but also mark the alias as
1302 being a thumb function. */
1308 /* XXX the following is a duplicate of the code for s_set() in read.c
1309 We cannot just call that code as we need to get at the symbol that
1311 register char * name;
1312 register char delim;
1313 register char * end_name;
1314 register symbolS * symbolP;
1317 * Especial apologies for the random logic:
1318 * this just grew, and could be parsed much more simply!
1321 name = input_line_pointer;
1322 delim = get_symbol_end ();
1323 end_name = input_line_pointer;
1328 if (*input_line_pointer != ',')
1331 as_bad (_("Expected comma after name \"%s\""), name);
1333 ignore_rest_of_line ();
1337 input_line_pointer++;
1340 if (name[0] == '.' && name[1] == '\0')
1342 /* XXX - this should not happen to .thumb_set */
1346 if ((symbolP = symbol_find (name)) == NULL
1347 && (symbolP = md_undefined_symbol (name)) == NULL)
1350 /* When doing symbol listings, play games with dummy fragments living
1351 outside the normal fragment chain to record the file and line info
1353 if (listing & LISTING_SYMBOLS)
1355 extern struct list_info_struct * listing_tail;
1356 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1357 memset (dummy_frag, 0, sizeof(fragS));
1358 dummy_frag->fr_type = rs_fill;
1359 dummy_frag->line = listing_tail;
1360 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1361 dummy_frag->fr_symbol = symbolP;
1365 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1368 /* "set" symbols are local unless otherwise specified. */
1369 SF_SET_LOCAL (symbolP);
1370 #endif /* OBJ_COFF */
1371 } /* make a new symbol */
1373 symbol_table_insert (symbolP);
1378 && S_IS_DEFINED (symbolP)
1379 && S_GET_SEGMENT (symbolP) != reg_section)
1380 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1382 pseudo_set (symbolP);
1384 demand_empty_rest_of_line ();
1386 /* XXX Now we come to the Thumb specific bit of code. */
1388 THUMB_SET_FUNC (symbolP, 1);
1389 ARM_SET_THUMB (symbolP, 1);
1390 #if defined OBJ_ELF || defined OBJ_COFF
1391 ARM_SET_INTERWORK (symbolP, support_interwork);
1395 /* If we change section we must dump the literal pool first. */
1400 if (now_seg != text_section)
1404 obj_elf_text (ignore);
1414 if (flag_readonly_data_in_text)
1416 if (now_seg != text_section)
1419 else if (now_seg != data_section)
1423 obj_elf_data (ignore);
1431 arm_s_section (ignore)
1436 obj_elf_section (ignore);
1441 opcode_select (width)
1449 if (! (cpu_variant & ARM_THUMB))
1450 as_bad (_("selected processor does not support THUMB opcodes"));
1452 /* No need to force the alignment, since we will have been
1453 coming from ARM mode, which is word-aligned. */
1454 record_alignment (now_seg, 1);
1461 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1462 as_bad (_("selected processor does not support ARM opcodes"));
1465 frag_align (2, 0, 0);
1466 record_alignment (now_seg, 1);
1471 as_bad (_("invalid instruction size selected (%d)"), width);
1477 int ignore ATTRIBUTE_UNUSED;
1480 demand_empty_rest_of_line ();
1485 int ignore ATTRIBUTE_UNUSED;
1488 demand_empty_rest_of_line ();
1493 int unused ATTRIBUTE_UNUSED;
1497 temp = get_absolute_expression ();
1502 opcode_select (temp);
1506 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1514 skip_whitespace (str);
1517 inst.error = _("Garbage following instruction");
1521 skip_past_comma (str)
1527 while ((c = *p) == ' ' || c == ',')
1530 if (c == ',' && comma++)
1538 return comma ? SUCCESS : FAIL;
1541 /* A standard register must be given at this point.
1542 Shift is the place to put it in inst.instruction.
1543 Restores input start point on err.
1544 Returns the reg#, or FAIL. */
1546 reg_required_here (str, shift)
1550 static char buff [128]; /* XXX */
1552 char * start = *str;
1554 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1557 inst.instruction |= reg << shift;
1561 /* Restore the start point, we may have got a reg of the wrong class. */
1564 /* In the few cases where we might be able to accept something else
1565 this error can be overridden. */
1566 sprintf (buff, _("Register expected, not '%.100s'"), start);
1572 static CONST struct asm_psr *
1574 register char ** ccp;
1576 char * start = * ccp;
1579 CONST struct asm_psr * psr;
1583 /* Skip to the end of the next word in the input stream. */
1588 while (isalpha (c) || c == '_');
1590 /* Terminate the word. */
1593 /* Now locate the word in the psr hash table. */
1594 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1596 /* Restore the input stream. */
1599 /* If we found a valid match, advance the
1600 stream pointer past the end of the word. */
1606 /* Parse the input looking for a PSR flag. */
1608 psr_required_here (str)
1611 char * start = *str;
1612 CONST struct asm_psr * psr;
1614 psr = arm_psr_parse (str);
1618 /* If this is the SPSR that is being modified, set the R bit. */
1620 inst.instruction |= SPSR_BIT;
1622 /* Set the psr flags in the MSR instruction. */
1623 inst.instruction |= psr->field << PSR_SHIFT;
1628 /* In the few cases where we might be able to accept
1629 something else this error can be overridden. */
1630 inst.error = _("flag for {c}psr instruction expected");
1632 /* Restore the start point. */
1638 co_proc_number (str)
1641 int processor, pchar;
1643 skip_whitespace (* str);
1645 /* The data sheet seems to imply that just a number on its own is valid
1646 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1648 if (**str == 'p' || **str == 'P')
1652 if (pchar >= '0' && pchar <= '9')
1654 processor = pchar - '0';
1655 if (**str >= '0' && **str <= '9')
1657 processor = processor * 10 + *(*str)++ - '0';
1660 inst.error = _("Illegal co-processor number");
1667 inst.error = _("Bad or missing co-processor number");
1671 inst.instruction |= processor << 8;
1676 cp_opc_expr (str, where, length)
1683 skip_whitespace (* str);
1685 memset (&expr, '\0', sizeof (expr));
1687 if (my_get_expression (&expr, str))
1689 if (expr.X_op != O_constant)
1691 inst.error = _("bad or missing expression");
1695 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1697 inst.error = _("immediate co-processor expression too large");
1701 inst.instruction |= expr.X_add_number << where;
1706 cp_reg_required_here (str, where)
1711 char * start = *str;
1713 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1716 inst.instruction |= reg << where;
1720 /* In the few cases where we might be able to accept something else
1721 this error can be overridden. */
1722 inst.error = _("Co-processor register expected");
1724 /* Restore the start point. */
1730 fp_reg_required_here (str, where)
1735 char * start = *str;
1737 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1740 inst.instruction |= reg << where;
1744 /* In the few cases where we might be able to accept something else
1745 this error can be overridden. */
1746 inst.error = _("Floating point register expected");
1748 /* Restore the start point. */
1754 cp_address_offset (str)
1759 skip_whitespace (* str);
1761 if (! is_immediate_prefix (**str))
1763 inst.error = _("immediate expression expected");
1769 if (my_get_expression (& inst.reloc.exp, str))
1772 if (inst.reloc.exp.X_op == O_constant)
1774 offset = inst.reloc.exp.X_add_number;
1778 inst.error = _("co-processor address must be word aligned");
1782 if (offset > 1023 || offset < -1023)
1784 inst.error = _("offset too large");
1789 inst.instruction |= INDEX_UP;
1793 inst.instruction |= offset >> 2;
1796 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1802 cp_address_required_here (str)
1814 skip_whitespace (p);
1816 if ((reg = reg_required_here (& p, 16)) == FAIL)
1819 skip_whitespace (p);
1825 if (skip_past_comma (& p) == SUCCESS)
1828 write_back = WRITE_BACK;
1832 inst.error = _("pc may not be used in post-increment");
1836 if (cp_address_offset (& p) == FAIL)
1840 pre_inc = PRE_INDEX | INDEX_UP;
1844 /* '['Rn, #expr']'[!] */
1846 if (skip_past_comma (& p) == FAIL)
1848 inst.error = _("pre-indexed expression expected");
1852 pre_inc = PRE_INDEX;
1854 if (cp_address_offset (& p) == FAIL)
1857 skip_whitespace (p);
1861 inst.error = _("missing ]");
1865 skip_whitespace (p);
1871 inst.error = _("pc may not be used with write-back");
1876 write_back = WRITE_BACK;
1882 if (my_get_expression (&inst.reloc.exp, &p))
1885 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1886 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1887 inst.reloc.pc_rel = 1;
1888 inst.instruction |= (REG_PC << 16);
1889 pre_inc = PRE_INDEX;
1892 inst.instruction |= write_back | pre_inc;
1900 unsigned long flags;
1902 /* Do nothing really. */
1903 inst.instruction |= flags; /* This is pointless. */
1911 unsigned long flags;
1915 /* Only one syntax. */
1916 skip_whitespace (str);
1918 if (reg_required_here (&str, 12) == FAIL)
1920 inst.error = BAD_ARGS;
1924 if (skip_past_comma (&str) == FAIL)
1926 inst.error = _("comma expected after register name");
1930 skip_whitespace (str);
1932 if ( strcmp (str, "CPSR") == 0
1933 || strcmp (str, "SPSR") == 0
1934 /* Lower case versions for backwards compatability. */
1935 || strcmp (str, "cpsr") == 0
1936 || strcmp (str, "spsr") == 0)
1938 /* This is for backwards compatability with older toolchains. */
1939 else if (strcmp (str, "cpsr_all") == 0
1940 || strcmp (str, "spsr_all") == 0)
1944 inst.error = _("{C|S}PSR expected");
1948 if (* str == 's' || * str == 'S')
1949 inst.instruction |= SPSR_BIT;
1952 inst.instruction |= flags;
1956 /* Two possible forms:
1957 "{C|S}PSR_<field>, Rm",
1958 "{C|S}PSR_f, #expression". */
1962 unsigned long flags;
1964 skip_whitespace (str);
1966 if (psr_required_here (& str) == FAIL)
1969 if (skip_past_comma (& str) == FAIL)
1971 inst.error = _("comma missing after psr flags");
1975 skip_whitespace (str);
1977 if (reg_required_here (& str, 0) != FAIL)
1980 inst.instruction |= flags;
1985 if (! is_immediate_prefix (* str))
1987 inst.error = _("only a register or immediate value can follow a psr flag");
1994 if (my_get_expression (& inst.reloc.exp, & str))
1996 inst.error = _("only a register or immediate value can follow a psr flag");
2000 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2002 inst.error = _("can only set flag field with immediate value");
2006 flags |= INST_IMMEDIATE;
2008 if (inst.reloc.exp.X_add_symbol)
2010 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2011 inst.reloc.pc_rel = 0;
2015 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2017 if (value == (unsigned) FAIL)
2019 inst.error = _("Invalid constant");
2023 inst.instruction |= value;
2027 inst.instruction |= flags;
2031 /* Long Multiply Parser
2032 UMULL RdLo, RdHi, Rm, Rs
2033 SMULL RdLo, RdHi, Rm, Rs
2034 UMLAL RdLo, RdHi, Rm, Rs
2035 SMLAL RdLo, RdHi, Rm, Rs
2038 do_mull (str, flags)
2040 unsigned long flags;
2042 int rdlo, rdhi, rm, rs;
2044 /* Only one format "rdlo, rdhi, rm, rs" */
2045 skip_whitespace (str);
2047 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2049 inst.error = BAD_ARGS;
2053 if (skip_past_comma (&str) == FAIL
2054 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2056 inst.error = BAD_ARGS;
2060 if (skip_past_comma (&str) == FAIL
2061 || (rm = reg_required_here (&str, 0)) == FAIL)
2063 inst.error = BAD_ARGS;
2067 /* rdhi, rdlo and rm must all be different */
2068 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2069 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2071 if (skip_past_comma (&str) == FAIL
2072 || (rs = reg_required_here (&str, 8)) == FAIL)
2074 inst.error = BAD_ARGS;
2078 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2080 inst.error = BAD_PC;
2084 inst.instruction |= flags;
2092 unsigned long flags;
2096 /* Only one format "rd, rm, rs" */
2097 skip_whitespace (str);
2099 if ((rd = reg_required_here (&str, 16)) == FAIL)
2101 inst.error = BAD_ARGS;
2107 inst.error = BAD_PC;
2111 if (skip_past_comma (&str) == FAIL
2112 || (rm = reg_required_here (&str, 0)) == FAIL)
2114 inst.error = BAD_ARGS;
2120 inst.error = BAD_PC;
2125 as_tsktsk (_("rd and rm should be different in mul"));
2127 if (skip_past_comma (&str) == FAIL
2128 || (rm = reg_required_here (&str, 8)) == FAIL)
2130 inst.error = BAD_ARGS;
2136 inst.error = BAD_PC;
2140 inst.instruction |= flags;
2148 unsigned long flags;
2152 /* Only one format "rd, rm, rs, rn" */
2153 skip_whitespace (str);
2155 if ((rd = reg_required_here (&str, 16)) == FAIL)
2157 inst.error = BAD_ARGS;
2163 inst.error = BAD_PC;
2167 if (skip_past_comma (&str) == FAIL
2168 || (rm = reg_required_here (&str, 0)) == FAIL)
2170 inst.error = BAD_ARGS;
2176 inst.error = BAD_PC;
2181 as_tsktsk (_("rd and rm should be different in mla"));
2183 if (skip_past_comma (&str) == FAIL
2184 || (rd = reg_required_here (&str, 8)) == FAIL
2185 || skip_past_comma (&str) == FAIL
2186 || (rm = reg_required_here (&str, 12)) == FAIL)
2188 inst.error = BAD_ARGS;
2192 if (rd == REG_PC || rm == REG_PC)
2194 inst.error = BAD_PC;
2198 inst.instruction |= flags;
2203 /* Returns the index into fp_values of a floating point number, or -1 if
2204 not in the table. */
2206 my_get_float_expression (str)
2209 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2215 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2216 /* Look for a raw floating point number */
2217 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2218 && is_end_of_line [(unsigned char) *save_in])
2220 for (i = 0; i < NUM_FLOAT_VALS; i++)
2222 for (j = 0; j < MAX_LITTLENUMS; j++)
2224 if (words[j] != fp_values[i][j])
2228 if (j == MAX_LITTLENUMS)
2236 /* Try and parse a more complex expression, this will probably fail
2237 unless the code uses a floating point prefix (eg "0f") */
2238 save_in = input_line_pointer;
2239 input_line_pointer = *str;
2240 if (expression (&exp) == absolute_section
2241 && exp.X_op == O_big
2242 && exp.X_add_number < 0)
2244 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2246 if (gen_to_words (words, 5, (long)15) == 0)
2248 for (i = 0; i < NUM_FLOAT_VALS; i++)
2250 for (j = 0; j < MAX_LITTLENUMS; j++)
2252 if (words[j] != fp_values[i][j])
2256 if (j == MAX_LITTLENUMS)
2258 *str = input_line_pointer;
2259 input_line_pointer = save_in;
2266 *str = input_line_pointer;
2267 input_line_pointer = save_in;
2271 /* Return true if anything in the expression is a bignum */
2273 walk_no_bignums (sp)
2276 if (symbol_get_value_expression (sp)->X_op == O_big)
2279 if (symbol_get_value_expression (sp)->X_add_symbol)
2281 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2282 || (symbol_get_value_expression (sp)->X_op_symbol
2283 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2290 my_get_expression (ep, str)
2297 save_in = input_line_pointer;
2298 input_line_pointer = *str;
2299 seg = expression (ep);
2302 if (seg != absolute_section
2303 && seg != text_section
2304 && seg != data_section
2305 && seg != bss_section
2306 && seg != undefined_section)
2308 inst.error = _("bad_segment");
2309 *str = input_line_pointer;
2310 input_line_pointer = save_in;
2315 /* Get rid of any bignums now, so that we don't generate an error for which
2316 we can't establish a line number later on. Big numbers are never valid
2317 in instructions, which is where this routine is always called. */
2318 if (ep->X_op == O_big
2319 || (ep->X_add_symbol
2320 && (walk_no_bignums (ep->X_add_symbol)
2322 && walk_no_bignums (ep->X_op_symbol)))))
2324 inst.error = _("Invalid constant");
2325 *str = input_line_pointer;
2326 input_line_pointer = save_in;
2330 *str = input_line_pointer;
2331 input_line_pointer = save_in;
2335 /* unrestrict should be one if <shift> <register> is permitted for this
2339 decode_shift (str, unrestrict)
2343 struct asm_shift * shft;
2347 skip_whitespace (* str);
2349 for (p = *str; isalpha (*p); p++)
2354 inst.error = _("Shift expression expected");
2360 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2364 if (!strncmp (*str, "rrx", 3)
2365 || !strncmp (*str, "RRX", 3))
2368 inst.instruction |= shft->value;
2372 skip_whitespace (p);
2374 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2376 inst.instruction |= shft->value | SHIFT_BY_REG;
2380 else if (is_immediate_prefix (* p))
2384 if (my_get_expression (&inst.reloc.exp, &p))
2387 /* Validate some simple #expressions */
2388 if (inst.reloc.exp.X_op == O_constant)
2390 unsigned num = inst.reloc.exp.X_add_number;
2392 /* Reject operations greater than 32, or lsl #32 */
2393 if (num > 32 || (num == 32 && shft->value == 0))
2395 inst.error = _("Invalid immediate shift");
2399 /* Shifts of zero should be converted to lsl (which is zero)*/
2406 /* Shifts of 32 are encoded as 0, for those shifts that
2411 inst.instruction |= (num << 7) | shft->value;
2416 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2417 inst.reloc.pc_rel = 0;
2418 inst.instruction |= shft->value;
2424 inst.error = unrestrict ? _("shift requires register or #expression")
2425 : _("shift requires #expression");
2431 inst.error = _("Shift expression expected");
2435 /* Do those data_ops which can take a negative immediate constant */
2436 /* by altering the instuction. A bit of a hack really */
2440 by inverting the second operand, and
2443 by negating the second operand.
2446 negate_data_op (instruction, value)
2447 unsigned long * instruction;
2448 unsigned long value;
2451 unsigned long negated, inverted;
2453 negated = validate_immediate (-value);
2454 inverted = validate_immediate (~value);
2456 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2460 case OPCODE_SUB: /* ADD <-> SUB */
2461 new_inst = OPCODE_ADD;
2466 new_inst = OPCODE_SUB;
2470 case OPCODE_CMP: /* CMP <-> CMN */
2471 new_inst = OPCODE_CMN;
2476 new_inst = OPCODE_CMP;
2480 /* Now Inverted ops */
2481 case OPCODE_MOV: /* MOV <-> MVN */
2482 new_inst = OPCODE_MVN;
2487 new_inst = OPCODE_MOV;
2491 case OPCODE_AND: /* AND <-> BIC */
2492 new_inst = OPCODE_BIC;
2497 new_inst = OPCODE_AND;
2501 case OPCODE_ADC: /* ADC <-> SBC */
2502 new_inst = OPCODE_SBC;
2507 new_inst = OPCODE_ADC;
2511 /* We cannot do anything */
2516 if (value == (unsigned) FAIL)
2519 *instruction &= OPCODE_MASK;
2520 *instruction |= new_inst << DATA_OP_SHIFT;
2531 skip_whitespace (* str);
2533 if (reg_required_here (str, 0) != FAIL)
2535 if (skip_past_comma (str) == SUCCESS)
2536 /* Shift operation on register. */
2537 return decode_shift (str, NO_SHIFT_RESTRICT);
2543 /* Immediate expression */
2544 if (is_immediate_prefix (**str))
2549 if (my_get_expression (&inst.reloc.exp, str))
2552 if (inst.reloc.exp.X_add_symbol)
2554 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2555 inst.reloc.pc_rel = 0;
2559 if (skip_past_comma (str) == SUCCESS)
2561 /* #x, y -- ie explicit rotation by Y */
2562 if (my_get_expression (&expr, str))
2565 if (expr.X_op != O_constant)
2567 inst.error = _("Constant expression expected");
2571 /* Rotate must be a multiple of 2 */
2572 if (((unsigned) expr.X_add_number) > 30
2573 || (expr.X_add_number & 1) != 0
2574 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2576 inst.error = _("Invalid constant");
2579 inst.instruction |= INST_IMMEDIATE;
2580 inst.instruction |= inst.reloc.exp.X_add_number;
2581 inst.instruction |= expr.X_add_number << 7;
2585 /* Implicit rotation, select a suitable one */
2586 value = validate_immediate (inst.reloc.exp.X_add_number);
2590 /* Can't be done, perhaps the code reads something like
2591 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2592 if ((value = negate_data_op (&inst.instruction,
2593 inst.reloc.exp.X_add_number))
2596 inst.error = _("Invalid constant");
2601 inst.instruction |= value;
2604 inst.instruction |= INST_IMMEDIATE;
2609 inst.error = _("Register or shift expression expected");
2618 skip_whitespace (* str);
2620 if (fp_reg_required_here (str, 0) != FAIL)
2624 /* Immediate expression */
2625 if (*((*str)++) == '#')
2631 skip_whitespace (* str);
2633 /* First try and match exact strings, this is to guarantee that
2634 some formats will work even for cross assembly */
2636 for (i = 0; fp_const[i]; i++)
2638 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2642 *str += strlen (fp_const[i]);
2643 if (is_end_of_line[(unsigned char) **str])
2645 inst.instruction |= i + 8;
2652 /* Just because we didn't get a match doesn't mean that the
2653 constant isn't valid, just that it is in a format that we
2654 don't automatically recognize. Try parsing it with
2655 the standard expression routines. */
2656 if ((i = my_get_float_expression (str)) >= 0)
2658 inst.instruction |= i + 8;
2662 inst.error = _("Invalid floating point immediate expression");
2665 inst.error = _("Floating point register or immediate expression expected");
2671 do_arit (str, flags)
2673 unsigned long flags;
2675 skip_whitespace (str);
2677 if (reg_required_here (&str, 12) == FAIL
2678 || skip_past_comma (&str) == FAIL
2679 || reg_required_here (&str, 16) == FAIL
2680 || skip_past_comma (&str) == FAIL
2681 || data_op2 (&str) == FAIL)
2684 inst.error = BAD_ARGS;
2688 inst.instruction |= flags;
2696 unsigned long flags;
2698 /* This is a pseudo-op of the form "adr rd, label" to be converted
2699 into a relative address of the form "add rd, pc, #label-.-8". */
2700 skip_whitespace (str);
2702 if (reg_required_here (&str, 12) == FAIL
2703 || skip_past_comma (&str) == FAIL
2704 || my_get_expression (&inst.reloc.exp, &str))
2707 inst.error = BAD_ARGS;
2711 /* Frag hacking will turn this into a sub instruction if the offset turns
2712 out to be negative. */
2713 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2714 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2715 inst.reloc.pc_rel = 1;
2716 inst.instruction |= flags;
2722 do_adrl (str, flags)
2724 unsigned long flags;
2726 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2727 into a relative address of the form:
2728 add rd, pc, #low(label-.-8)"
2729 add rd, rd, #high(label-.-8)" */
2731 skip_whitespace (str);
2733 if (reg_required_here (& str, 12) == FAIL
2734 || skip_past_comma (& str) == FAIL
2735 || my_get_expression (& inst.reloc.exp, & str))
2738 inst.error = BAD_ARGS;
2744 /* Frag hacking will turn this into a sub instruction if the offset turns
2745 out to be negative. */
2746 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2747 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2748 inst.reloc.pc_rel = 1;
2749 inst.instruction |= flags;
2750 inst.size = INSN_SIZE * 2;
2758 unsigned long flags;
2760 skip_whitespace (str);
2762 if (reg_required_here (&str, 16) == FAIL)
2765 inst.error = BAD_ARGS;
2769 if (skip_past_comma (&str) == FAIL
2770 || data_op2 (&str) == FAIL)
2773 inst.error = BAD_ARGS;
2777 inst.instruction |= flags;
2778 if ((flags & 0x0000f000) == 0)
2779 inst.instruction |= CONDS_BIT;
2788 unsigned long flags;
2790 skip_whitespace (str);
2792 if (reg_required_here (&str, 12) == FAIL)
2795 inst.error = BAD_ARGS;
2799 if (skip_past_comma (&str) == FAIL
2800 || data_op2 (&str) == FAIL)
2803 inst.error = BAD_ARGS;
2807 inst.instruction |= flags;
2813 ldst_extend (str, hwse)
2824 if (my_get_expression (& inst.reloc.exp, str))
2827 if (inst.reloc.exp.X_op == O_constant)
2829 int value = inst.reloc.exp.X_add_number;
2831 if ((hwse && (value < -255 || value > 255))
2832 || (value < -4095 || value > 4095))
2834 inst.error = _("address offset too large");
2844 /* Halfword and signextension instructions have the
2845 immediate value split across bits 11..8 and bits 3..0 */
2847 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2849 inst.instruction |= add | value;
2855 inst.instruction |= HWOFFSET_IMM;
2856 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2859 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2860 inst.reloc.pc_rel = 0;
2865 add = 0; /* and fall through */
2867 (*str)++; /* and fall through */
2869 if (reg_required_here (str, 0) == FAIL)
2873 inst.instruction |= add;
2876 inst.instruction |= add | OFFSET_REG;
2877 if (skip_past_comma (str) == SUCCESS)
2878 return decode_shift (str, SHIFT_RESTRICT);
2886 do_ldst (str, flags)
2888 unsigned long flags;
2895 /* This is not ideal, but it is the simplest way of dealing with the
2896 ARM7T halfword instructions (since they use a different
2897 encoding, but the same mnemonic): */
2898 halfword = (flags & 0x80000000) != 0;
2901 /* This is actually a load/store of a halfword, or a
2902 signed-extension load */
2903 if ((cpu_variant & ARM_HALFWORD) == 0)
2906 = _("Processor does not support halfwords or signed bytes");
2910 inst.instruction = (inst.instruction & COND_MASK)
2911 | (flags & ~COND_MASK);
2916 skip_whitespace (str);
2918 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2921 inst.error = BAD_ARGS;
2925 if (skip_past_comma (& str) == FAIL)
2927 inst.error = _("Address expected");
2937 skip_whitespace (str);
2939 if ((reg = reg_required_here (&str, 16)) == FAIL)
2942 /* Conflicts can occur on stores as well as loads. */
2943 conflict_reg = (conflict_reg == reg);
2945 skip_whitespace (str);
2951 if (skip_past_comma (&str) == SUCCESS)
2953 /* [Rn],... (post inc) */
2954 if (ldst_extend (&str, halfword) == FAIL)
2957 as_warn (_("%s register same as write-back base"),
2958 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2964 inst.instruction |= HWOFFSET_IMM;
2966 skip_whitespace (str);
2971 as_warn (_("%s register same as write-back base"),
2972 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2974 inst.instruction |= WRITE_BACK;
2978 if (! (flags & TRANS_BIT))
2985 if (skip_past_comma (&str) == FAIL)
2987 inst.error = _("pre-indexed expression expected");
2992 if (ldst_extend (&str, halfword) == FAIL)
2995 skip_whitespace (str);
2999 inst.error = _("missing ]");
3003 skip_whitespace (str);
3008 as_warn (_("%s register same as write-back base"),
3009 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
3011 inst.instruction |= WRITE_BACK;
3015 else if (*str == '=')
3017 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
3020 skip_whitespace (str);
3022 if (my_get_expression (&inst.reloc.exp, &str))
3025 if (inst.reloc.exp.X_op != O_constant
3026 && inst.reloc.exp.X_op != O_symbol)
3028 inst.error = _("Constant expression expected");
3032 if (inst.reloc.exp.X_op == O_constant
3033 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
3035 /* This can be done with a mov instruction */
3036 inst.instruction &= LITERAL_MASK;
3037 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3038 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3044 /* Insert into literal pool */
3045 if (add_to_lit_pool () == FAIL)
3048 inst.error = _("literal pool insertion failed");
3052 /* Change the instruction exp to point to the pool */
3055 inst.instruction |= HWOFFSET_IMM;
3056 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3059 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3060 inst.reloc.pc_rel = 1;
3061 inst.instruction |= (REG_PC << 16);
3067 if (my_get_expression (&inst.reloc.exp, &str))
3072 inst.instruction |= HWOFFSET_IMM;
3073 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3076 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3078 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3080 inst.reloc.pc_rel = 1;
3081 inst.instruction |= (REG_PC << 16);
3085 if (pre_inc && (flags & TRANS_BIT))
3086 inst.error = _("Pre-increment instruction with translate");
3088 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3101 /* We come back here if we get ranges concatenated by '+' or '|' */
3116 skip_whitespace (str);
3118 if ((reg = reg_required_here (& str, -1)) == FAIL)
3127 inst.error = _("Bad range in register list");
3131 for (i = cur_reg + 1; i < reg; i++)
3133 if (range & (1 << i))
3135 (_("Warning: Duplicated register (r%d) in register list"),
3143 if (range & (1 << reg))
3144 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3146 else if (reg <= cur_reg)
3147 as_tsktsk (_("Warning: Register range not in ascending order"));
3151 } while (skip_past_comma (&str) != FAIL
3152 || (in_range = 1, *str++ == '-'));
3154 skip_whitespace (str);
3158 inst.error = _("Missing `}'");
3166 if (my_get_expression (&expr, &str))
3169 if (expr.X_op == O_constant)
3171 if (expr.X_add_number
3172 != (expr.X_add_number & 0x0000ffff))
3174 inst.error = _("invalid register mask");
3178 if ((range & expr.X_add_number) != 0)
3180 int regno = range & expr.X_add_number;
3183 regno = (1 << regno) - 1;
3185 (_("Warning: Duplicated register (r%d) in register list"),
3189 range |= expr.X_add_number;
3193 if (inst.reloc.type != 0)
3195 inst.error = _("expression too complex");
3199 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3200 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3201 inst.reloc.pc_rel = 0;
3205 skip_whitespace (str);
3207 if (*str == '|' || *str == '+')
3212 } while (another_range);
3219 do_ldmstm (str, flags)
3221 unsigned long flags;
3226 skip_whitespace (str);
3228 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3231 if (base_reg == REG_PC)
3233 inst.error = _("r15 not allowed as base register");
3237 skip_whitespace (str);
3241 flags |= WRITE_BACK;
3245 if (skip_past_comma (&str) == FAIL
3246 || (range = reg_list (&str)) == FAIL)
3249 inst.error = BAD_ARGS;
3256 flags |= LDM_TYPE_2_OR_3;
3259 inst.instruction |= flags | range;
3267 unsigned long flags;
3269 skip_whitespace (str);
3271 /* Allow optional leading '#'. */
3272 if (is_immediate_prefix (*str))
3275 if (my_get_expression (& inst.reloc.exp, & str))
3278 inst.reloc.type = BFD_RELOC_ARM_SWI;
3279 inst.reloc.pc_rel = 0;
3280 inst.instruction |= flags;
3288 do_swap (str, flags)
3290 unsigned long flags;
3294 skip_whitespace (str);
3296 if ((reg = reg_required_here (&str, 12)) == FAIL)
3301 inst.error = _("r15 not allowed in swap");
3305 if (skip_past_comma (&str) == FAIL
3306 || (reg = reg_required_here (&str, 0)) == FAIL)
3309 inst.error = BAD_ARGS;
3315 inst.error = _("r15 not allowed in swap");
3319 if (skip_past_comma (&str) == FAIL
3322 inst.error = BAD_ARGS;
3326 skip_whitespace (str);
3328 if ((reg = reg_required_here (&str, 16)) == FAIL)
3333 inst.error = BAD_PC;
3337 skip_whitespace (str);
3341 inst.error = _("missing ]");
3345 inst.instruction |= flags;
3351 do_branch (str, flags)
3353 unsigned long flags ATTRIBUTE_UNUSED;
3355 if (my_get_expression (&inst.reloc.exp, &str))
3362 /* ScottB: February 5, 1998 */
3363 /* Check to see of PLT32 reloc required for the instruction. */
3365 /* arm_parse_reloc() works on input_line_pointer.
3366 We actually want to parse the operands to the branch instruction
3367 passed in 'str'. Save the input pointer and restore it later. */
3368 save_in = input_line_pointer;
3369 input_line_pointer = str;
3370 if (inst.reloc.exp.X_op == O_symbol
3372 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3374 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3375 inst.reloc.pc_rel = 0;
3376 /* Modify str to point to after parsed operands, otherwise
3377 end_of_line() will complain about the (PLT) left in str. */
3378 str = input_line_pointer;
3382 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3383 inst.reloc.pc_rel = 1;
3385 input_line_pointer = save_in;
3388 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3389 inst.reloc.pc_rel = 1;
3390 #endif /* OBJ_ELF */
3399 unsigned long flags ATTRIBUTE_UNUSED;
3403 skip_whitespace (str);
3405 if ((reg = reg_required_here (&str, 0)) == FAIL)
3407 inst.error = BAD_ARGS;
3412 inst.error = BAD_PC;
3420 unsigned long flags ATTRIBUTE_UNUSED;
3422 /* Co-processor data operation.
3423 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3424 skip_whitespace (str);
3426 if (co_proc_number (&str) == FAIL)
3429 inst.error = BAD_ARGS;
3433 if (skip_past_comma (&str) == FAIL
3434 || cp_opc_expr (&str, 20,4) == FAIL)
3437 inst.error = BAD_ARGS;
3441 if (skip_past_comma (&str) == FAIL
3442 || cp_reg_required_here (&str, 12) == FAIL)
3445 inst.error = BAD_ARGS;
3449 if (skip_past_comma (&str) == FAIL
3450 || cp_reg_required_here (&str, 16) == FAIL)
3453 inst.error = BAD_ARGS;
3457 if (skip_past_comma (&str) == FAIL
3458 || cp_reg_required_here (&str, 0) == FAIL)
3461 inst.error = BAD_ARGS;
3465 if (skip_past_comma (&str) == SUCCESS)
3467 if (cp_opc_expr (&str, 5, 3) == FAIL)
3470 inst.error = BAD_ARGS;
3480 do_lstc (str, flags)
3482 unsigned long flags;
3484 /* Co-processor register load/store.
3485 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3487 skip_whitespace (str);
3489 if (co_proc_number (&str) == FAIL)
3492 inst.error = BAD_ARGS;
3496 if (skip_past_comma (&str) == FAIL
3497 || cp_reg_required_here (&str, 12) == FAIL)
3500 inst.error = BAD_ARGS;
3504 if (skip_past_comma (&str) == FAIL
3505 || cp_address_required_here (&str) == FAIL)
3508 inst.error = BAD_ARGS;
3512 inst.instruction |= flags;
3518 do_co_reg (str, flags)
3520 unsigned long flags;
3522 /* Co-processor register transfer.
3523 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3525 skip_whitespace (str);
3527 if (co_proc_number (&str) == FAIL)
3530 inst.error = BAD_ARGS;
3534 if (skip_past_comma (&str) == FAIL
3535 || cp_opc_expr (&str, 21, 3) == FAIL)
3538 inst.error = BAD_ARGS;
3542 if (skip_past_comma (&str) == FAIL
3543 || reg_required_here (&str, 12) == FAIL)
3546 inst.error = BAD_ARGS;
3550 if (skip_past_comma (&str) == FAIL
3551 || cp_reg_required_here (&str, 16) == FAIL)
3554 inst.error = BAD_ARGS;
3558 if (skip_past_comma (&str) == FAIL
3559 || cp_reg_required_here (&str, 0) == FAIL)
3562 inst.error = BAD_ARGS;
3566 if (skip_past_comma (&str) == SUCCESS)
3568 if (cp_opc_expr (&str, 5, 3) == FAIL)
3571 inst.error = BAD_ARGS;
3577 inst.error = BAD_COND;
3585 do_fp_ctrl (str, flags)
3587 unsigned long flags ATTRIBUTE_UNUSED;
3589 /* FP control registers.
3590 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3592 skip_whitespace (str);
3594 if (reg_required_here (&str, 12) == FAIL)
3597 inst.error = BAD_ARGS;
3606 do_fp_ldst (str, flags)
3608 unsigned long flags ATTRIBUTE_UNUSED;
3610 skip_whitespace (str);
3612 switch (inst.suffix)
3617 inst.instruction |= CP_T_X;
3620 inst.instruction |= CP_T_Y;
3623 inst.instruction |= CP_T_X | CP_T_Y;
3629 if (fp_reg_required_here (&str, 12) == FAIL)
3632 inst.error = BAD_ARGS;
3636 if (skip_past_comma (&str) == FAIL
3637 || cp_address_required_here (&str) == FAIL)
3640 inst.error = BAD_ARGS;
3648 do_fp_ldmstm (str, flags)
3650 unsigned long flags;
3654 skip_whitespace (str);
3656 if (fp_reg_required_here (&str, 12) == FAIL)
3659 inst.error = BAD_ARGS;
3663 /* Get Number of registers to transfer */
3664 if (skip_past_comma (&str) == FAIL
3665 || my_get_expression (&inst.reloc.exp, &str))
3668 inst.error = _("constant expression expected");
3672 if (inst.reloc.exp.X_op != O_constant)
3674 inst.error = _("Constant value required for number of registers");
3678 num_regs = inst.reloc.exp.X_add_number;
3680 if (num_regs < 1 || num_regs > 4)
3682 inst.error = _("number of registers must be in the range [1:4]");
3689 inst.instruction |= CP_T_X;
3692 inst.instruction |= CP_T_Y;
3695 inst.instruction |= CP_T_Y | CP_T_X;
3709 /* The instruction specified "ea" or "fd", so we can only accept
3710 [Rn]{!}. The instruction does not really support stacking or
3711 unstacking, so we have to emulate these by setting appropriate
3712 bits and offsets. */
3713 if (skip_past_comma (&str) == FAIL
3717 inst.error = BAD_ARGS;
3722 skip_whitespace (str);
3724 if ((reg = reg_required_here (&str, 16)) == FAIL)
3727 skip_whitespace (str);
3731 inst.error = BAD_ARGS;
3742 inst.error = _("R15 not allowed as base register with write-back");
3749 if (flags & CP_T_Pre)
3752 offset = 3 * num_regs;
3758 /* Post-increment */
3762 offset = 3 * num_regs;
3766 /* No write-back, so convert this into a standard pre-increment
3767 instruction -- aesthetically more pleasing. */
3768 flags = CP_T_Pre | CP_T_UD;
3773 inst.instruction |= flags | offset;
3775 else if (skip_past_comma (&str) == FAIL
3776 || cp_address_required_here (&str) == FAIL)
3779 inst.error = BAD_ARGS;
3787 do_fp_dyadic (str, flags)
3789 unsigned long flags;
3791 skip_whitespace (str);
3793 switch (inst.suffix)
3798 inst.instruction |= 0x00000080;
3801 inst.instruction |= 0x00080000;
3807 if (fp_reg_required_here (&str, 12) == FAIL)
3810 inst.error = BAD_ARGS;
3814 if (skip_past_comma (&str) == FAIL
3815 || fp_reg_required_here (&str, 16) == FAIL)
3818 inst.error = BAD_ARGS;
3822 if (skip_past_comma (&str) == FAIL
3823 || fp_op2 (&str) == FAIL)
3826 inst.error = BAD_ARGS;
3830 inst.instruction |= flags;
3836 do_fp_monadic (str, flags)
3838 unsigned long flags;
3840 skip_whitespace (str);
3842 switch (inst.suffix)
3847 inst.instruction |= 0x00000080;
3850 inst.instruction |= 0x00080000;
3856 if (fp_reg_required_here (&str, 12) == FAIL)
3859 inst.error = BAD_ARGS;
3863 if (skip_past_comma (&str) == FAIL
3864 || fp_op2 (&str) == FAIL)
3867 inst.error = BAD_ARGS;
3871 inst.instruction |= flags;
3877 do_fp_cmp (str, flags)
3879 unsigned long flags;
3881 skip_whitespace (str);
3883 if (fp_reg_required_here (&str, 16) == FAIL)
3886 inst.error = BAD_ARGS;
3890 if (skip_past_comma (&str) == FAIL
3891 || fp_op2 (&str) == FAIL)
3894 inst.error = BAD_ARGS;
3898 inst.instruction |= flags;
3904 do_fp_from_reg (str, flags)
3906 unsigned long flags;
3908 skip_whitespace (str);
3910 switch (inst.suffix)
3915 inst.instruction |= 0x00000080;
3918 inst.instruction |= 0x00080000;
3924 if (fp_reg_required_here (&str, 16) == FAIL)
3927 inst.error = BAD_ARGS;
3931 if (skip_past_comma (&str) == FAIL
3932 || reg_required_here (&str, 12) == FAIL)
3935 inst.error = BAD_ARGS;
3939 inst.instruction |= flags;
3945 do_fp_to_reg (str, flags)
3947 unsigned long flags;
3949 skip_whitespace (str);
3951 if (reg_required_here (&str, 12) == FAIL)
3954 if (skip_past_comma (&str) == FAIL
3955 || fp_reg_required_here (&str, 0) == FAIL)
3958 inst.error = BAD_ARGS;
3962 inst.instruction |= flags;
3967 /* Thumb specific routines */
3969 /* Parse and validate that a register is of the right form, this saves
3970 repeated checking of this information in many similar cases.
3971 Unlike the 32-bit case we do not insert the register into the opcode
3972 here, since the position is often unknown until the full instruction
3975 thumb_reg (strp, hi_lo)
3981 if ((reg = reg_required_here (strp, -1)) == FAIL)
3989 inst.error = _("lo register required");
3997 inst.error = _("hi register required");
4009 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4012 thumb_add_sub (str, subtract)
4016 int Rd, Rs, Rn = FAIL;
4018 skip_whitespace (str);
4020 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4021 || skip_past_comma (&str) == FAIL)
4024 inst.error = BAD_ARGS;
4028 if (is_immediate_prefix (*str))
4032 if (my_get_expression (&inst.reloc.exp, &str))
4037 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4040 if (skip_past_comma (&str) == FAIL)
4042 /* Two operand format, shuffle the registers and pretend there
4047 else if (is_immediate_prefix (*str))
4050 if (my_get_expression (&inst.reloc.exp, &str))
4053 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4057 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4058 for the latter case, EXPR contains the immediate that was found. */
4061 /* All register format. */
4062 if (Rd > 7 || Rs > 7 || Rn > 7)
4066 inst.error = _("dest and source1 must be the same register");
4070 /* Can't do this for SUB */
4073 inst.error = _("subtract valid only on lo regs");
4077 inst.instruction = (T_OPCODE_ADD_HI
4078 | (Rd > 7 ? THUMB_H1 : 0)
4079 | (Rn > 7 ? THUMB_H2 : 0));
4080 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4084 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4085 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4090 /* Immediate expression, now things start to get nasty. */
4092 /* First deal with HI regs, only very restricted cases allowed:
4093 Adjusting SP, and using PC or SP to get an address. */
4094 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4095 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4097 inst.error = _("invalid Hi register with immediate");
4101 if (inst.reloc.exp.X_op != O_constant)
4103 /* Value isn't known yet, all we can do is store all the fragments
4104 we know about in the instruction and let the reloc hacking
4106 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4107 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4111 int offset = inst.reloc.exp.X_add_number;
4121 /* Quick check, in case offset is MIN_INT */
4124 inst.error = _("immediate value out of range");
4133 if (offset & ~0x1fc)
4135 inst.error = _("invalid immediate value for stack adjust");
4138 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4139 inst.instruction |= offset >> 2;
4141 else if (Rs == REG_PC || Rs == REG_SP)
4144 || (offset & ~0x3fc))
4146 inst.error = _("invalid immediate for address calculation");
4149 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4151 inst.instruction |= (Rd << 8) | (offset >> 2);
4157 inst.error = _("immediate value out of range");
4160 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4161 inst.instruction |= (Rd << 8) | offset;
4167 inst.error = _("immediate value out of range");
4170 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4171 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4180 thumb_shift (str, shift)
4184 int Rd, Rs, Rn = FAIL;
4186 skip_whitespace (str);
4188 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4189 || skip_past_comma (&str) == FAIL)
4192 inst.error = BAD_ARGS;
4196 if (is_immediate_prefix (*str))
4198 /* Two operand immediate format, set Rs to Rd. */
4201 if (my_get_expression (&inst.reloc.exp, &str))
4206 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4209 if (skip_past_comma (&str) == FAIL)
4211 /* Two operand format, shuffle the registers and pretend there
4216 else if (is_immediate_prefix (*str))
4219 if (my_get_expression (&inst.reloc.exp, &str))
4222 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4226 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4227 for the latter case, EXPR contains the immediate that was found. */
4233 inst.error = _("source1 and dest must be same register");
4239 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4240 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4241 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4244 inst.instruction |= Rd | (Rn << 3);
4250 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4251 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4252 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4255 if (inst.reloc.exp.X_op != O_constant)
4257 /* Value isn't known yet, create a dummy reloc and let reloc
4258 hacking fix it up */
4260 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4264 unsigned shift_value = inst.reloc.exp.X_add_number;
4266 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4268 inst.error = _("Invalid immediate for shift");
4272 /* Shifts of zero are handled by converting to LSL */
4273 if (shift_value == 0)
4274 inst.instruction = T_OPCODE_LSL_I;
4276 /* Shifts of 32 are encoded as a shift of zero */
4277 if (shift_value == 32)
4280 inst.instruction |= shift_value << 6;
4283 inst.instruction |= Rd | (Rs << 3);
4290 thumb_mov_compare (str, move)
4296 skip_whitespace (str);
4298 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4299 || skip_past_comma (&str) == FAIL)
4302 inst.error = BAD_ARGS;
4306 if (is_immediate_prefix (*str))
4309 if (my_get_expression (&inst.reloc.exp, &str))
4312 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4317 if (Rs < 8 && Rd < 8)
4319 if (move == THUMB_MOVE)
4320 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4321 since a MOV instruction produces unpredictable results */
4322 inst.instruction = T_OPCODE_ADD_I3;
4324 inst.instruction = T_OPCODE_CMP_LR;
4325 inst.instruction |= Rd | (Rs << 3);
4329 if (move == THUMB_MOVE)
4330 inst.instruction = T_OPCODE_MOV_HR;
4332 inst.instruction = T_OPCODE_CMP_HR;
4335 inst.instruction |= THUMB_H1;
4338 inst.instruction |= THUMB_H2;
4340 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4347 inst.error = _("only lo regs allowed with immediate");
4351 if (move == THUMB_MOVE)
4352 inst.instruction = T_OPCODE_MOV_I8;
4354 inst.instruction = T_OPCODE_CMP_I8;
4356 inst.instruction |= Rd << 8;
4358 if (inst.reloc.exp.X_op != O_constant)
4359 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4362 unsigned value = inst.reloc.exp.X_add_number;
4366 inst.error = _("invalid immediate");
4370 inst.instruction |= value;
4378 thumb_load_store (str, load_store, size)
4383 int Rd, Rb, Ro = FAIL;
4385 skip_whitespace (str);
4387 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4388 || skip_past_comma (&str) == FAIL)
4391 inst.error = BAD_ARGS;
4398 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4401 if (skip_past_comma (&str) != FAIL)
4403 if (is_immediate_prefix (*str))
4406 if (my_get_expression (&inst.reloc.exp, &str))
4409 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4414 inst.reloc.exp.X_op = O_constant;
4415 inst.reloc.exp.X_add_number = 0;
4420 inst.error = _("expected ']'");
4425 else if (*str == '=')
4427 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4430 skip_whitespace (str);
4432 if (my_get_expression (& inst.reloc.exp, & str))
4437 if ( inst.reloc.exp.X_op != O_constant
4438 && inst.reloc.exp.X_op != O_symbol)
4440 inst.error = "Constant expression expected";
4444 if (inst.reloc.exp.X_op == O_constant
4445 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4447 /* This can be done with a mov instruction */
4449 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4450 inst.instruction |= inst.reloc.exp.X_add_number;
4454 /* Insert into literal pool */
4455 if (add_to_lit_pool () == FAIL)
4458 inst.error = "literal pool insertion failed";
4462 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4463 inst.reloc.pc_rel = 1;
4464 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4465 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4471 if (my_get_expression (&inst.reloc.exp, &str))
4474 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4475 inst.reloc.pc_rel = 1;
4476 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4477 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4482 if (Rb == REG_PC || Rb == REG_SP)
4484 if (size != THUMB_WORD)
4486 inst.error = _("byte or halfword not valid for base register");
4489 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4491 inst.error = _("R15 based store not allowed");
4494 else if (Ro != FAIL)
4496 inst.error = _("Invalid base register for register offset");
4501 inst.instruction = T_OPCODE_LDR_PC;
4502 else if (load_store == THUMB_LOAD)
4503 inst.instruction = T_OPCODE_LDR_SP;
4505 inst.instruction = T_OPCODE_STR_SP;
4507 inst.instruction |= Rd << 8;
4508 if (inst.reloc.exp.X_op == O_constant)
4510 unsigned offset = inst.reloc.exp.X_add_number;
4512 if (offset & ~0x3fc)
4514 inst.error = _("invalid offset");
4518 inst.instruction |= offset >> 2;
4521 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4525 inst.error = _("invalid base register in load/store");
4528 else if (Ro == FAIL)
4530 /* Immediate offset */
4531 if (size == THUMB_WORD)
4532 inst.instruction = (load_store == THUMB_LOAD
4533 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4534 else if (size == THUMB_HALFWORD)
4535 inst.instruction = (load_store == THUMB_LOAD
4536 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4538 inst.instruction = (load_store == THUMB_LOAD
4539 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4541 inst.instruction |= Rd | (Rb << 3);
4543 if (inst.reloc.exp.X_op == O_constant)
4545 unsigned offset = inst.reloc.exp.X_add_number;
4547 if (offset & ~(0x1f << size))
4549 inst.error = _("Invalid offset");
4552 inst.instruction |= (offset >> size) << 6;
4555 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4559 /* Register offset */
4560 if (size == THUMB_WORD)
4561 inst.instruction = (load_store == THUMB_LOAD
4562 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4563 else if (size == THUMB_HALFWORD)
4564 inst.instruction = (load_store == THUMB_LOAD
4565 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4567 inst.instruction = (load_store == THUMB_LOAD
4568 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4570 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4585 /* Handle the Format 4 instructions that do not have equivalents in other
4586 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4594 skip_whitespace (str);
4596 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4597 || skip_past_comma (&str) == FAIL
4598 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4600 inst.error = BAD_ARGS;
4604 if (skip_past_comma (&str) != FAIL)
4606 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4607 (It isn't allowed for CMP either, but that isn't handled by this
4609 if (inst.instruction == T_OPCODE_TST
4610 || inst.instruction == T_OPCODE_CMN
4611 || inst.instruction == T_OPCODE_NEG
4612 || inst.instruction == T_OPCODE_MVN)
4614 inst.error = BAD_ARGS;
4618 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4623 inst.error = _("dest and source1 one must be the same register");
4629 if (inst.instruction == T_OPCODE_MUL
4631 as_tsktsk (_("Rs and Rd must be different in MUL"));
4633 inst.instruction |= Rd | (Rs << 3);
4641 thumb_add_sub (str, 0);
4648 thumb_shift (str, THUMB_ASR);
4655 if (my_get_expression (&inst.reloc.exp, &str))
4657 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4658 inst.reloc.pc_rel = 1;
4666 if (my_get_expression (&inst.reloc.exp, &str))
4668 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4669 inst.reloc.pc_rel = 1;
4673 /* Find the real, Thumb encoded start of a Thumb function. */
4676 find_real_start (symbolP)
4680 const char * name = S_GET_NAME (symbolP);
4681 symbolS * new_target;
4683 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4684 #define STUB_NAME ".real_start_of"
4689 /* Names that start with '.' are local labels, not function entry points.
4690 The compiler may generate BL instructions to these labels because it
4691 needs to perform a branch to a far away location. */
4695 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4696 sprintf (real_start, "%s%s", STUB_NAME, name);
4698 new_target = symbol_find (real_start);
4700 if (new_target == NULL)
4702 as_warn ("Failed to find real start of function: %s\n", name);
4703 new_target = symbolP;
4716 if (my_get_expression (& inst.reloc.exp, & str))
4719 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4720 inst.reloc.pc_rel = 1;
4723 /* If the destination of the branch is a defined symbol which does not have
4724 the THUMB_FUNC attribute, then we must be calling a function which has
4725 the (interfacearm) attribute. We look for the Thumb entry point to that
4726 function and change the branch to refer to that function instead. */
4727 if ( inst.reloc.exp.X_op == O_symbol
4728 && inst.reloc.exp.X_add_symbol != NULL
4729 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4730 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4731 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4740 skip_whitespace (str);
4742 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4745 /* This sets THUMB_H2 from the top bit of reg. */
4746 inst.instruction |= reg << 3;
4748 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4749 should cause the alignment to be checked once it is known. This is
4750 because BX PC only works if the instruction is word aligned. */
4759 thumb_mov_compare (str, THUMB_COMPARE);
4769 skip_whitespace (str);
4771 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4775 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4779 if (skip_past_comma (&str) == FAIL
4780 || (range = reg_list (&str)) == FAIL)
4783 inst.error = BAD_ARGS;
4787 if (inst.reloc.type != BFD_RELOC_NONE)
4789 /* This really doesn't seem worth it. */
4790 inst.reloc.type = BFD_RELOC_NONE;
4791 inst.error = _("Expression too complex");
4797 inst.error = _("only lo-regs valid in load/store multiple");
4801 inst.instruction |= (Rb << 8) | range;
4809 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4816 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4823 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4832 skip_whitespace (str);
4834 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4835 || skip_past_comma (&str) == FAIL
4837 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4838 || skip_past_comma (&str) == FAIL
4839 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4843 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4847 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4855 thumb_shift (str, THUMB_LSL);
4862 thumb_shift (str, THUMB_LSR);
4869 thumb_mov_compare (str, THUMB_MOVE);
4878 skip_whitespace (str);
4880 if ((range = reg_list (&str)) == FAIL)
4883 inst.error = BAD_ARGS;
4887 if (inst.reloc.type != BFD_RELOC_NONE)
4889 /* This really doesn't seem worth it. */
4890 inst.reloc.type = BFD_RELOC_NONE;
4891 inst.error = _("Expression too complex");
4897 if ((inst.instruction == T_OPCODE_PUSH
4898 && (range & ~0xff) == 1 << REG_LR)
4899 || (inst.instruction == T_OPCODE_POP
4900 && (range & ~0xff) == 1 << REG_PC))
4902 inst.instruction |= THUMB_PP_PC_LR;
4907 inst.error = _("invalid register list to push/pop instruction");
4912 inst.instruction |= range;
4920 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4927 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4934 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4941 thumb_add_sub (str, 1);
4948 skip_whitespace (str);
4950 if (my_get_expression (&inst.reloc.exp, &str))
4953 inst.reloc.type = BFD_RELOC_ARM_SWI;
4964 /* This is a pseudo-op of the form "adr rd, label" to be converted
4965 into a relative address of the form "add rd, pc, #label-.-4". */
4966 skip_whitespace (str);
4968 /* Store Rd in temporary location inside instruction. */
4969 if ((reg = reg_required_here (&str, 4)) == FAIL
4970 || (reg > 7) /* For Thumb reg must be r0..r7. */
4971 || skip_past_comma (&str) == FAIL
4972 || my_get_expression (&inst.reloc.exp, &str))
4975 inst.error = BAD_ARGS;
4979 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4980 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
4981 inst.reloc.pc_rel = 1;
4982 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
4991 int len = strlen (reg_table[entry].name) + 2;
4992 char * buf = (char *) xmalloc (len);
4993 char * buf2 = (char *) xmalloc (len);
4996 #ifdef REGISTER_PREFIX
4997 buf[i++] = REGISTER_PREFIX;
5000 strcpy (buf + i, reg_table[entry].name);
5002 for (i = 0; buf[i]; i++)
5003 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5007 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
5008 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
5012 insert_reg_alias (str, regnum)
5016 struct reg_entry *new =
5017 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
5018 char *name = xmalloc (strlen (str) + 1);
5022 new->number = regnum;
5024 hash_insert (arm_reg_hsh, name, (PTR) new);
5028 set_constant_flonums ()
5032 for (i = 0; i < NUM_FLOAT_VALS; i++)
5033 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
5043 if ( (arm_ops_hsh = hash_new ()) == NULL
5044 || (arm_tops_hsh = hash_new ()) == NULL
5045 || (arm_cond_hsh = hash_new ()) == NULL
5046 || (arm_shift_hsh = hash_new ()) == NULL
5047 || (arm_reg_hsh = hash_new ()) == NULL
5048 || (arm_psr_hsh = hash_new ()) == NULL)
5049 as_fatal (_("Virtual memory exhausted"));
5051 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5052 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5053 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5054 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5055 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5056 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5057 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5058 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5059 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5060 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5062 for (i = 0; reg_table[i].name; i++)
5065 set_constant_flonums ();
5067 #if defined OBJ_COFF || defined OBJ_ELF
5069 unsigned int flags = 0;
5071 /* Set the flags in the private structure. */
5072 if (uses_apcs_26) flags |= F_APCS26;
5073 if (support_interwork) flags |= F_INTERWORK;
5074 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5075 if (pic_code) flags |= F_PIC;
5076 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5078 bfd_set_private_flags (stdoutput, flags);
5082 /* Record the CPU type as well. */
5083 switch (cpu_variant & ARM_CPU_MASK)
5086 mach = bfd_mach_arm_2;
5089 case ARM_3: /* Also ARM_250. */
5090 mach = bfd_mach_arm_2a;
5094 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5095 mach = bfd_mach_arm_4;
5098 case ARM_7: /* Also ARM_6. */
5099 mach = bfd_mach_arm_3;
5103 /* Catch special cases. */
5104 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5106 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5107 mach = bfd_mach_arm_5T;
5108 else if (cpu_variant & ARM_EXT_V5)
5109 mach = bfd_mach_arm_5;
5110 else if (cpu_variant & ARM_THUMB)
5111 mach = bfd_mach_arm_4T;
5112 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5113 mach = bfd_mach_arm_4;
5114 else if (cpu_variant & ARM_LONGMUL)
5115 mach = bfd_mach_arm_3M;
5118 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5121 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5122 for use in the a.out file, and stores them in the array pointed to by buf.
5123 This knows about the endian-ness of the target machine and does
5124 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5125 2 (short) and 4 (long) Floating numbers are put out as a series of
5126 LITTLENUMS (shorts, here at least). */
5128 md_number_to_chars (buf, val, n)
5133 if (target_big_endian)
5134 number_to_chars_bigendian (buf, val, n);
5136 number_to_chars_littleendian (buf, val, n);
5140 md_chars_to_number (buf, n)
5145 unsigned char * where = (unsigned char *) buf;
5147 if (target_big_endian)
5152 result |= (*where++ & 255);
5160 result |= (where[n] & 255);
5167 /* Turn a string in input_line_pointer into a floating point constant
5168 of type TYPE, and store the appropriate bytes in *litP. The number
5169 of LITTLENUMS emitted is stored in *sizeP . An error message is
5170 returned, or NULL on OK.
5172 Note that fp constants aren't represent in the normal way on the ARM.
5173 In big endian mode, things are as expected. However, in little endian
5174 mode fp constants are big-endian word-wise, and little-endian byte-wise
5175 within the words. For example, (double) 1.1 in big endian mode is
5176 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5177 the byte sequence 99 99 f1 3f 9a 99 99 99.
5179 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5182 md_atof (type, litP, sizeP)
5188 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5220 return _("Bad call to MD_ATOF()");
5223 t = atof_ieee (input_line_pointer, type, words);
5225 input_line_pointer = t;
5228 if (target_big_endian)
5230 for (i = 0; i < prec; i++)
5232 md_number_to_chars (litP, (valueT) words[i], 2);
5238 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5239 8 byte float the order is 1 0 3 2. */
5240 for (i = 0; i < prec; i += 2)
5242 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5243 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5251 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5253 md_pcrel_from (fixP)
5257 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5258 && fixP->fx_subsy == NULL)
5261 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5263 /* PC relative addressing on the Thumb is slightly odd
5264 as the bottom two bits of the PC are forced to zero
5265 for the calculation. */
5266 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5270 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5271 so we un-adjust here to compensate for the accomodation. */
5272 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5274 return fixP->fx_where + fixP->fx_frag->fr_address;
5278 /* Round up a section size to the appropriate boundary. */
5280 md_section_align (segment, size)
5281 segT segment ATTRIBUTE_UNUSED;
5287 /* Round all sects to multiple of 4 */
5288 return (size + 3) & ~3;
5292 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5293 we have no need to default values of symbols. */
5297 md_undefined_symbol (name)
5298 char * name ATTRIBUTE_UNUSED;
5301 if (name[0] == '_' && name[1] == 'G'
5302 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5306 if (symbol_find (name))
5307 as_bad ("GOT already in the symbol table");
5309 GOT_symbol = symbol_new (name, undefined_section,
5310 (valueT)0, & zero_address_frag);
5320 /* arm_reg_parse () := if it looks like a register, return its token and
5321 advance the pointer. */
5325 register char ** ccp;
5327 char * start = * ccp;
5330 struct reg_entry * reg;
5332 #ifdef REGISTER_PREFIX
5333 if (*start != REGISTER_PREFIX)
5338 #ifdef OPTIONAL_REGISTER_PREFIX
5339 if (*p == OPTIONAL_REGISTER_PREFIX)
5343 if (!isalpha (*p) || !is_name_beginner (*p))
5347 while (isalpha (c) || isdigit (c) || c == '_')
5351 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5364 md_apply_fix3 (fixP, val, seg)
5369 offsetT value = * val;
5371 unsigned int newimm;
5374 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5375 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5377 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5379 /* Note whether this will delete the relocation. */
5380 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5381 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5384 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5388 /* If this symbol is in a different section then we need to leave it for
5389 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5390 so we have to undo it's effects here. */
5393 if (fixP->fx_addsy != NULL
5394 && S_IS_DEFINED (fixP->fx_addsy)
5395 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5398 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5399 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5403 value += md_pcrel_from (fixP);
5407 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5409 switch (fixP->fx_r_type)
5411 case BFD_RELOC_ARM_IMMEDIATE:
5412 newimm = validate_immediate (value);
5413 temp = md_chars_to_number (buf, INSN_SIZE);
5415 /* If the instruction will fail, see if we can fix things up by
5416 changing the opcode. */
5417 if (newimm == (unsigned int) FAIL
5418 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5420 as_bad_where (fixP->fx_file, fixP->fx_line,
5421 _("invalid constant (%lx) after fixup"),
5422 (unsigned long) value);
5426 newimm |= (temp & 0xfffff000);
5427 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5430 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5432 unsigned int highpart = 0;
5433 unsigned int newinsn = 0xe1a00000; /* nop */
5434 newimm = validate_immediate (value);
5435 temp = md_chars_to_number (buf, INSN_SIZE);
5437 /* If the instruction will fail, see if we can fix things up by
5438 changing the opcode. */
5439 if (newimm == (unsigned int) FAIL
5440 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5442 /* No ? OK - try using two ADD instructions to generate the value. */
5443 newimm = validate_immediate_twopart (value, & highpart);
5445 /* Yes - then make sure that the second instruction is also an add. */
5446 if (newimm != (unsigned int) FAIL)
5448 /* Still No ? Try using a negated value. */
5449 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5450 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5451 /* Otherwise - give up. */
5454 as_bad_where (fixP->fx_file, fixP->fx_line,
5455 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5459 /* Replace the first operand in the 2nd instruction (which is the PC)
5460 with the destination register. We have already added in the PC in the
5461 first instruction and we do not want to do it again. */
5462 newinsn &= ~ 0xf0000;
5463 newinsn |= ((newinsn & 0x0f000) << 4);
5466 newimm |= (temp & 0xfffff000);
5467 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5469 highpart |= (newinsn & 0xfffff000);
5470 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5474 case BFD_RELOC_ARM_OFFSET_IMM:
5480 if (validate_offset_imm (value, 0) == FAIL)
5482 as_bad_where (fixP->fx_file, fixP->fx_line,
5483 _("bad immediate value for offset (%ld)"), (long) value);
5487 newval = md_chars_to_number (buf, INSN_SIZE);
5488 newval &= 0xff7ff000;
5489 newval |= value | (sign ? INDEX_UP : 0);
5490 md_number_to_chars (buf, newval, INSN_SIZE);
5493 case BFD_RELOC_ARM_OFFSET_IMM8:
5494 case BFD_RELOC_ARM_HWLITERAL:
5500 if (validate_offset_imm (value, 1) == FAIL)
5502 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5503 as_bad_where (fixP->fx_file, fixP->fx_line,
5504 _("invalid literal constant: pool needs to be closer"));
5506 as_bad (_("bad immediate value for half-word offset (%ld)"),
5511 newval = md_chars_to_number (buf, INSN_SIZE);
5512 newval &= 0xff7ff0f0;
5513 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5514 md_number_to_chars (buf, newval, INSN_SIZE);
5517 case BFD_RELOC_ARM_LITERAL:
5523 if (validate_offset_imm (value, 0) == FAIL)
5525 as_bad_where (fixP->fx_file, fixP->fx_line,
5526 _("invalid literal constant: pool needs to be closer"));
5530 newval = md_chars_to_number (buf, INSN_SIZE);
5531 newval &= 0xff7ff000;
5532 newval |= value | (sign ? INDEX_UP : 0);
5533 md_number_to_chars (buf, newval, INSN_SIZE);
5536 case BFD_RELOC_ARM_SHIFT_IMM:
5537 newval = md_chars_to_number (buf, INSN_SIZE);
5538 if (((unsigned long) value) > 32
5540 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5542 as_bad_where (fixP->fx_file, fixP->fx_line,
5543 _("shift expression is too large"));
5548 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5549 else if (value == 32)
5551 newval &= 0xfffff07f;
5552 newval |= (value & 0x1f) << 7;
5553 md_number_to_chars (buf, newval , INSN_SIZE);
5556 case BFD_RELOC_ARM_SWI:
5557 if (arm_data->thumb_mode)
5559 if (((unsigned long) value) > 0xff)
5560 as_bad_where (fixP->fx_file, fixP->fx_line,
5561 _("Invalid swi expression"));
5562 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5564 md_number_to_chars (buf, newval, THUMB_SIZE);
5568 if (((unsigned long) value) > 0x00ffffff)
5569 as_bad_where (fixP->fx_file, fixP->fx_line,
5570 _("Invalid swi expression"));
5571 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5573 md_number_to_chars (buf, newval , INSN_SIZE);
5577 case BFD_RELOC_ARM_MULTI:
5578 if (((unsigned long) value) > 0xffff)
5579 as_bad_where (fixP->fx_file, fixP->fx_line,
5580 _("Invalid expression in load/store multiple"));
5581 newval = value | md_chars_to_number (buf, INSN_SIZE);
5582 md_number_to_chars (buf, newval, INSN_SIZE);
5585 case BFD_RELOC_ARM_PCREL_BRANCH:
5586 newval = md_chars_to_number (buf, INSN_SIZE);
5588 /* Sign-extend a 24-bit number. */
5589 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5593 value = fixP->fx_offset;
5596 /* We are going to store value (shifted right by two) in the
5597 instruction, in a 24 bit, signed field. Thus we need to check
5598 that none of the top 8 bits of the shifted value (top 7 bits of
5599 the unshifted, unsigned value) are set, or that they are all set. */
5600 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5601 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5604 /* Normally we would be stuck at this point, since we cannot store
5605 the absolute address that is the destination of the branch in the
5606 24 bits of the branch instruction. If however, we happen to know
5607 that the destination of the branch is in the same section as the
5608 branch instruciton itself, then we can compute the relocation for
5609 ourselves and not have to bother the linker with it.
5611 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5612 because I have not worked out how to do this for OBJ_COFF or
5615 && fixP->fx_addsy != NULL
5616 && S_IS_DEFINED (fixP->fx_addsy)
5617 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5619 /* Get pc relative value to go into the branch. */
5622 /* Permit a backward branch provided that enough bits are set.
5623 Allow a forwards branch, provided that enough bits are clear. */
5624 if ((value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5625 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5629 if (! fixP->fx_done)
5631 as_bad_where (fixP->fx_file, fixP->fx_line,
5632 _("gas can't handle same-section branch dest >= 0x04000000"));
5636 value += SEXT24 (newval);
5638 if ((value & ~ ((offsetT) 0xffffff)) != 0
5639 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5640 as_bad_where (fixP->fx_file, fixP->fx_line,
5641 _("out of range branch"));
5643 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5644 md_number_to_chars (buf, newval, INSN_SIZE);
5647 case BFD_RELOC_ARM_PCREL_BLX:
5650 newval = md_chars_to_number (buf, INSN_SIZE);
5654 value = fixP->fx_offset;
5656 hbit = (value >> 1) & 1;
5657 value = (value >> 2) & 0x00ffffff;
5658 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5659 newval = value | (newval & 0xfe000000) | (hbit << 24);
5660 md_number_to_chars (buf, newval, INSN_SIZE);
5664 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5665 newval = md_chars_to_number (buf, THUMB_SIZE);
5667 addressT diff = (newval & 0xff) << 1;
5672 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5673 as_bad_where (fixP->fx_file, fixP->fx_line,
5674 _("Branch out of range"));
5675 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5677 md_number_to_chars (buf, newval, THUMB_SIZE);
5680 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5681 newval = md_chars_to_number (buf, THUMB_SIZE);
5683 addressT diff = (newval & 0x7ff) << 1;
5688 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5689 as_bad_where (fixP->fx_file, fixP->fx_line,
5690 _("Branch out of range"));
5691 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5693 md_number_to_chars (buf, newval, THUMB_SIZE);
5696 case BFD_RELOC_THUMB_PCREL_BLX:
5697 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5702 newval = md_chars_to_number (buf, THUMB_SIZE);
5703 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5704 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5705 if (diff & 0x400000)
5708 value = fixP->fx_offset;
5711 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5712 as_bad_where (fixP->fx_file, fixP->fx_line,
5713 _("Branch with link out of range"));
5715 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5716 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5717 md_number_to_chars (buf, newval, THUMB_SIZE);
5718 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5723 if (fixP->fx_done || fixP->fx_pcrel)
5724 md_number_to_chars (buf, value, 1);
5726 else if (!target_oabi)
5728 value = fixP->fx_offset;
5729 md_number_to_chars (buf, value, 1);
5735 if (fixP->fx_done || fixP->fx_pcrel)
5736 md_number_to_chars (buf, value, 2);
5738 else if (!target_oabi)
5740 value = fixP->fx_offset;
5741 md_number_to_chars (buf, value, 2);
5747 case BFD_RELOC_ARM_GOT32:
5748 case BFD_RELOC_ARM_GOTOFF:
5749 md_number_to_chars (buf, 0, 4);
5755 if (fixP->fx_done || fixP->fx_pcrel)
5756 md_number_to_chars (buf, value, 4);
5758 else if (!target_oabi)
5760 value = fixP->fx_offset;
5761 md_number_to_chars (buf, value, 4);
5767 case BFD_RELOC_ARM_PLT32:
5768 /* It appears the instruction is fully prepared at this point. */
5772 case BFD_RELOC_ARM_GOTPC:
5773 md_number_to_chars (buf, value, 4);
5776 case BFD_RELOC_ARM_CP_OFF_IMM:
5778 if (value < -1023 || value > 1023 || (value & 3))
5779 as_bad_where (fixP->fx_file, fixP->fx_line,
5780 _("Illegal value for co-processor offset"));
5783 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5784 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5785 md_number_to_chars (buf, newval , INSN_SIZE);
5788 case BFD_RELOC_ARM_THUMB_OFFSET:
5789 newval = md_chars_to_number (buf, THUMB_SIZE);
5790 /* Exactly what ranges, and where the offset is inserted depends on
5791 the type of instruction, we can establish this from the top 4 bits */
5792 switch (newval >> 12)
5794 case 4: /* PC load */
5795 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5796 forced to zero for these loads, so we will need to round
5797 up the offset if the instruction address is not word
5798 aligned (since the final address produced must be, and
5799 we can only describe word-aligned immediate offsets). */
5801 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5802 as_bad_where (fixP->fx_file, fixP->fx_line,
5803 _("Invalid offset, target not word aligned (0x%08X)"),
5804 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5806 if ((value + 2) & ~0x3fe)
5807 as_bad_where (fixP->fx_file, fixP->fx_line,
5808 _("Invalid offset, value too big (0x%08X)"), value);
5810 /* Round up, since pc will be rounded down. */
5811 newval |= (value + 2) >> 2;
5814 case 9: /* SP load/store */
5816 as_bad_where (fixP->fx_file, fixP->fx_line,
5817 _("Invalid offset, value too big (0x%08X)"), value);
5818 newval |= value >> 2;
5821 case 6: /* Word load/store */
5823 as_bad_where (fixP->fx_file, fixP->fx_line,
5824 _("Invalid offset, value too big (0x%08X)"), value);
5825 newval |= value << 4; /* 6 - 2 */
5828 case 7: /* Byte load/store */
5830 as_bad_where (fixP->fx_file, fixP->fx_line,
5831 _("Invalid offset, value too big (0x%08X)"), value);
5832 newval |= value << 6;
5835 case 8: /* Halfword load/store */
5837 as_bad_where (fixP->fx_file, fixP->fx_line,
5838 _("Invalid offset, value too big (0x%08X)"), value);
5839 newval |= value << 5; /* 6 - 1 */
5843 as_bad_where (fixP->fx_file, fixP->fx_line,
5844 "Unable to process relocation for thumb opcode: %lx",
5845 (unsigned long) newval);
5848 md_number_to_chars (buf, newval, THUMB_SIZE);
5851 case BFD_RELOC_ARM_THUMB_ADD:
5852 /* This is a complicated relocation, since we use it for all of
5853 the following immediate relocations:
5856 9bit ADD/SUB SP word-aligned
5857 10bit ADD PC/SP word-aligned
5859 The type of instruction being processed is encoded in the
5865 newval = md_chars_to_number (buf, THUMB_SIZE);
5867 int rd = (newval >> 4) & 0xf;
5868 int rs = newval & 0xf;
5869 int subtract = newval & 0x8000;
5874 as_bad_where (fixP->fx_file, fixP->fx_line,
5875 _("Invalid immediate for stack address calculation"));
5876 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5877 newval |= value >> 2;
5879 else if (rs == REG_PC || rs == REG_SP)
5883 as_bad_where (fixP->fx_file, fixP->fx_line,
5884 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5885 (unsigned long) value);
5886 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5888 newval |= value >> 2;
5893 as_bad_where (fixP->fx_file, fixP->fx_line,
5894 _("Invalid 8bit immediate"));
5895 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5896 newval |= (rd << 8) | value;
5901 as_bad_where (fixP->fx_file, fixP->fx_line,
5902 _("Invalid 3bit immediate"));
5903 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5904 newval |= rd | (rs << 3) | (value << 6);
5907 md_number_to_chars (buf, newval , THUMB_SIZE);
5910 case BFD_RELOC_ARM_THUMB_IMM:
5911 newval = md_chars_to_number (buf, THUMB_SIZE);
5912 switch (newval >> 11)
5914 case 0x04: /* 8bit immediate MOV */
5915 case 0x05: /* 8bit immediate CMP */
5916 if (value < 0 || value > 255)
5917 as_bad_where (fixP->fx_file, fixP->fx_line,
5918 _("Invalid immediate: %ld is too large"),
5926 md_number_to_chars (buf, newval , THUMB_SIZE);
5929 case BFD_RELOC_ARM_THUMB_SHIFT:
5930 /* 5bit shift value (0..31) */
5931 if (value < 0 || value > 31)
5932 as_bad_where (fixP->fx_file, fixP->fx_line,
5933 _("Illegal Thumb shift value: %ld"), (long) value);
5934 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5935 newval |= value << 6;
5936 md_number_to_chars (buf, newval , THUMB_SIZE);
5939 case BFD_RELOC_VTABLE_INHERIT:
5940 case BFD_RELOC_VTABLE_ENTRY:
5944 case BFD_RELOC_NONE:
5946 as_bad_where (fixP->fx_file, fixP->fx_line,
5947 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5953 /* Translate internal representation of relocation info to BFD target
5956 tc_gen_reloc (section, fixp)
5957 asection * section ATTRIBUTE_UNUSED;
5961 bfd_reloc_code_real_type code;
5963 reloc = (arelent *) xmalloc (sizeof (arelent));
5965 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5966 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5967 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5969 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5971 if (fixp->fx_pcrel == 0)
5972 reloc->addend = fixp->fx_offset;
5974 reloc->addend = fixp->fx_offset = reloc->address;
5976 reloc->addend = fixp->fx_offset;
5979 switch (fixp->fx_r_type)
5984 code = BFD_RELOC_8_PCREL;
5991 code = BFD_RELOC_16_PCREL;
5998 code = BFD_RELOC_32_PCREL;
6002 case BFD_RELOC_ARM_PCREL_BRANCH:
6003 case BFD_RELOC_ARM_PCREL_BLX:
6005 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6006 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6007 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6008 case BFD_RELOC_THUMB_PCREL_BLX:
6009 case BFD_RELOC_VTABLE_ENTRY:
6010 case BFD_RELOC_VTABLE_INHERIT:
6011 code = fixp->fx_r_type;
6014 case BFD_RELOC_ARM_LITERAL:
6015 case BFD_RELOC_ARM_HWLITERAL:
6016 /* If this is called then the a literal has been referenced across
6017 a section boundary - possibly due to an implicit dump */
6018 as_bad_where (fixp->fx_file, fixp->fx_line,
6019 _("Literal referenced across section boundary (Implicit dump?)"));
6023 case BFD_RELOC_ARM_GOT32:
6024 case BFD_RELOC_ARM_GOTOFF:
6025 case BFD_RELOC_ARM_PLT32:
6026 code = fixp->fx_r_type;
6030 case BFD_RELOC_ARM_IMMEDIATE:
6031 as_bad_where (fixp->fx_file, fixp->fx_line,
6032 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6036 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6037 as_bad_where (fixp->fx_file, fixp->fx_line,
6038 _("ADRL used for a symbol not defined in the same file"),
6042 case BFD_RELOC_ARM_OFFSET_IMM:
6043 as_bad_where (fixp->fx_file, fixp->fx_line,
6044 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6051 switch (fixp->fx_r_type)
6053 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6054 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6055 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6056 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6057 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6058 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6059 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6060 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6061 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6062 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6063 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6064 default: type = _("<unknown>"); break;
6066 as_bad_where (fixp->fx_file, fixp->fx_line,
6067 _("Can not represent %s relocation in this object file format (%d)"),
6068 type, fixp->fx_pcrel);
6074 if (code == BFD_RELOC_32_PCREL
6076 && fixp->fx_addsy == GOT_symbol)
6078 code = BFD_RELOC_ARM_GOTPC;
6079 reloc->addend = fixp->fx_offset = reloc->address;
6083 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6085 if (reloc->howto == NULL)
6087 as_bad_where (fixp->fx_file, fixp->fx_line,
6088 _("Can not represent %s relocation in this object file format"),
6089 bfd_get_reloc_code_name (code));
6093 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6094 vtable entry to be used in the relocation's section offset. */
6095 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6096 reloc->address = fixp->fx_offset;
6102 md_estimate_size_before_relax (fragP, segtype)
6103 fragS * fragP ATTRIBUTE_UNUSED;
6104 segT segtype ATTRIBUTE_UNUSED;
6106 as_fatal (_("md_estimate_size_before_relax\n"));
6111 output_inst PARAMS ((void))
6117 as_bad (inst.error);
6121 to = frag_more (inst.size);
6123 if (thumb_mode && (inst.size > THUMB_SIZE))
6125 assert (inst.size == (2 * THUMB_SIZE));
6126 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6127 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6129 else if (inst.size > INSN_SIZE)
6131 assert (inst.size == (2 * INSN_SIZE));
6132 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6133 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6136 md_number_to_chars (to, inst.instruction, inst.size);
6138 if (inst.reloc.type != BFD_RELOC_NONE)
6139 fix_new_arm (frag_now, to - frag_now->fr_literal,
6140 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6155 /* Align the instruction.
6156 This may not be the right thing to do but ... */
6157 /* arm_align (2, 0); */
6158 listing_prev_line (); /* Defined in listing.h */
6160 /* Align the previous label if needed. */
6161 if (last_label_seen != NULL)
6163 symbol_set_frag (last_label_seen, frag_now);
6164 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6165 S_SET_SEGMENT (last_label_seen, now_seg);
6168 memset (&inst, '\0', sizeof (inst));
6169 inst.reloc.type = BFD_RELOC_NONE;
6171 skip_whitespace (str);
6173 /* Scan up to the end of the op-code, which must end in white space or
6175 for (start = p = str; *p != '\0'; p++)
6181 as_bad (_("No operator -- statement `%s'\n"), str);
6187 CONST struct thumb_opcode * opcode;
6191 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6196 /* Check that this instruction is supported for this CPU. */
6197 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6199 as_bad (_("selected processor does not support this opcode"));
6203 inst.instruction = opcode->value;
6204 inst.size = opcode->size;
6205 (*opcode->parms)(p);
6212 CONST struct asm_opcode * opcode;
6213 unsigned long cond_code;
6215 inst.size = INSN_SIZE;
6216 /* p now points to the end of the opcode, probably white space, but we
6217 have to break the opcode up in case it contains condionals and flags;
6218 keep trying with progressively smaller basic instructions until one
6219 matches, or we run out of opcode. */
6220 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6222 for (; q != str; q--)
6227 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6230 if (opcode && opcode->template)
6232 unsigned long flag_bits = 0;
6235 /* Check that this instruction is supported for this CPU. */
6236 if ((opcode->variants & cpu_variant) == 0)
6239 inst.instruction = opcode->value;
6240 if (q == p) /* Just a simple opcode. */
6242 if (opcode->comp_suffix)
6244 if (*opcode->comp_suffix != '\0')
6245 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6246 str, opcode->comp_suffix);
6248 /* Not a conditional instruction. */
6249 (*opcode->parms)(q, 0);
6253 /* A conditional instruction with default condition. */
6254 inst.instruction |= COND_ALWAYS;
6255 (*opcode->parms)(q, 0);
6261 /* Not just a simple opcode. Check if extra is a conditional. */
6265 CONST struct asm_cond *cond;
6269 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6273 if (cond->value == 0xf0000000)
6275 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6277 cond_code = cond->value;
6281 cond_code = COND_ALWAYS;
6284 cond_code = COND_ALWAYS;
6286 /* Apply the conditional, or complain it's not allowed. */
6287 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6289 /* Instruction isn't conditional */
6290 if (cond_code != COND_ALWAYS)
6292 as_bad (_("Opcode `%s' is unconditional\n"), str);
6297 /* Instruction is conditional: set the condition into it. */
6298 inst.instruction |= cond_code;
6301 /* If there is a compulsory suffix, it should come here, before
6302 any optional flags. */
6303 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6305 CONST char *s = opcode->comp_suffix;
6317 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6318 opcode->comp_suffix);
6325 /* The remainder, if any should now be flags for the instruction;
6326 Scan these checking each one found with the opcode. */
6330 CONST struct asm_flg *flag = opcode->flags;
6339 for (flagno = 0; flag[flagno].template; flagno++)
6341 if (streq (r, flag[flagno].template))
6343 flag_bits |= flag[flagno].set_bits;
6349 if (! flag[flagno].template)
6356 (*opcode->parms) (p, flag_bits);
6366 /* It wasn't an instruction, but it might be a register alias of the form
6369 skip_whitespace (q);
6374 if (*q && !strncmp (q, ".req ", 4))
6377 char * copy_of_str = str;
6381 skip_whitespace (q);
6383 for (r = q; *r != '\0'; r++)
6393 regnum = arm_reg_parse (& q);
6396 reg = arm_reg_parse (& str);
6401 insert_reg_alias (str, regnum);
6403 as_warn (_("register '%s' does not exist\n"), q);
6405 else if (regnum != FAIL)
6408 as_warn (_("ignoring redefinition of register alias '%s'"),
6411 /* Do not warn about redefinitions to the same alias. */
6414 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6418 as_warn (_("ignoring incomplete .req pseuso op"));
6425 as_bad (_("bad instruction `%s'"), start);
6430 * Invocation line includes a switch not recognized by the base assembler.
6431 * See if it's a processor-specific option. These are:
6432 * Cpu variants, the arm part is optional:
6433 * -m[arm]1 Currently not supported.
6434 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6435 * -m[arm]3 Arm 3 processor
6436 * -m[arm]6[xx], Arm 6 processors
6437 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6438 * -m[arm]8[10] Arm 8 processors
6439 * -m[arm]9[20][tdmi] Arm 9 processors
6440 * -mstrongarm[110[0]] StrongARM processors
6441 * -m[arm]v[2345[t]] Arm architectures
6442 * -mall All (except the ARM1)
6444 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6445 * -mfpe-old (No float load/store multiples)
6446 * -mno-fpu Disable all floating point instructions
6447 * Run-time endian selection:
6448 * -EB big endian cpu
6449 * -EL little endian cpu
6450 * ARM Procedure Calling Standard:
6451 * -mapcs-32 32 bit APCS
6452 * -mapcs-26 26 bit APCS
6453 * -mapcs-float Pass floats in float regs
6454 * -mapcs-reentrant Position independent code
6455 * -mthumb-interwork Code supports Arm/Thumb interworking
6456 * -moabi Old ELF ABI
6459 CONST char * md_shortopts = "m:k";
6460 struct option md_longopts[] =
6462 #ifdef ARM_BI_ENDIAN
6463 #define OPTION_EB (OPTION_MD_BASE + 0)
6464 {"EB", no_argument, NULL, OPTION_EB},
6465 #define OPTION_EL (OPTION_MD_BASE + 1)
6466 {"EL", no_argument, NULL, OPTION_EL},
6468 #define OPTION_OABI (OPTION_MD_BASE +2)
6469 {"oabi", no_argument, NULL, OPTION_OABI},
6472 {NULL, no_argument, NULL, 0}
6474 size_t md_longopts_size = sizeof (md_longopts);
6477 md_parse_option (c, arg)
6485 #ifdef ARM_BI_ENDIAN
6487 target_big_endian = 1;
6490 target_big_endian = 0;
6498 if (streq (str, "fpa10"))
6499 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6500 else if (streq (str, "fpa11"))
6501 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6502 else if (streq (str, "fpe-old"))
6503 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6509 if (streq (str, "no-fpu"))
6510 cpu_variant &= ~FPU_ALL;
6515 if (streq (str, "oabi"))
6521 /* Limit assembler to generating only Thumb instructions: */
6522 if (streq (str, "thumb"))
6524 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6525 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6528 else if (streq (str, "thumb-interwork"))
6530 if ((cpu_variant & ARM_THUMB) == 0)
6531 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6532 #if defined OBJ_COFF || defined OBJ_ELF
6533 support_interwork = true;
6541 if (streq (str, "all"))
6543 cpu_variant = ARM_ALL | FPU_ALL;
6546 #if defined OBJ_COFF || defined OBJ_ELF
6547 if (! strncmp (str, "apcs-", 5))
6549 /* GCC passes on all command line options starting "-mapcs-..."
6550 to us, so we must parse them here. */
6554 if (streq (str, "32"))
6556 uses_apcs_26 = false;
6559 else if (streq (str, "26"))
6561 uses_apcs_26 = true;
6564 else if (streq (str, "frame"))
6566 /* Stack frames are being generated - does not affect
6570 else if (streq (str, "stack-check"))
6572 /* Stack checking is being performed - does not affect
6573 linkage, but does require that the functions
6574 __rt_stkovf_split_small and __rt_stkovf_split_big be
6575 present in the final link. */
6579 else if (streq (str, "float"))
6581 /* Floating point arguments are being passed in the floating
6582 point registers. This does affect linking, since this
6583 version of the APCS is incompatible with the version that
6584 passes floating points in the integer registers. */
6586 uses_apcs_float = true;
6589 else if (streq (str, "reentrant"))
6591 /* Reentrant code has been generated. This does affect
6592 linking, since there is no point in linking reentrant/
6593 position independent code with absolute position code. */
6598 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6602 /* Strip off optional "arm" */
6603 if (! strncmp (str, "arm", 3))
6609 if (streq (str, "1"))
6610 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6616 if (streq (str, "2"))
6617 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6618 else if (streq (str, "250"))
6619 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6625 if (streq (str, "3"))
6626 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6632 switch (strtol (str, NULL, 10))
6639 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6647 switch (strtol (str, & str, 10)) /* Eat the processor name */
6660 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6666 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6670 cpu_variant |= ARM_LONGMUL;
6673 case 'f': /* fe => fp enabled cpu. */
6679 case 'c': /* Left over from 710c processor name. */
6680 case 'd': /* Debug */
6681 case 'i': /* Embedded ICE */
6682 /* Included for completeness in ARM processor naming. */
6692 if (streq (str, "8") || streq (str, "810"))
6693 cpu_variant = (cpu_variant & ~ARM_ANY)
6694 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6700 if (streq (str, "9"))
6701 cpu_variant = (cpu_variant & ~ARM_ANY)
6702 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6703 else if (streq (str, "920"))
6704 cpu_variant = (cpu_variant & ~ARM_ANY)
6705 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6706 else if (streq (str, "920t"))
6707 cpu_variant = (cpu_variant & ~ARM_ANY)
6708 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6709 else if (streq (str, "9tdmi"))
6710 cpu_variant = (cpu_variant & ~ARM_ANY)
6711 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6718 if (streq (str, "strongarm")
6719 || streq (str, "strongarm110")
6720 || streq (str, "strongarm1100"))
6721 cpu_variant = (cpu_variant & ~ARM_ANY)
6722 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6728 /* Select variant based on architecture rather than processor. */
6735 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6738 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6741 as_bad (_("Invalid architecture variant -m%s"), arg);
6747 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6751 case 'm': cpu_variant |= ARM_LONGMUL; break;
6754 as_bad (_("Invalid architecture variant -m%s"), arg);
6760 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6764 case 't': cpu_variant |= ARM_THUMB; break;
6767 as_bad (_("Invalid architecture variant -m%s"), arg);
6773 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6776 case 't': cpu_variant |= ARM_THUMB; break;
6779 as_bad (_("Invalid architecture variant -m%s"), arg);
6785 as_bad (_("Invalid architecture variant -m%s"), arg);
6792 as_bad (_("Invalid processor variant -m%s"), arg);
6798 #if defined OBJ_ELF || defined OBJ_COFF
6816 ARM Specific Assembler Options:\n\
6817 -m[arm][<processor name>] select processor variant\n\
6818 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6819 -mthumb only allow Thumb instructions\n\
6820 -mthumb-interwork mark the assembled code as supporting interworking\n\
6821 -mall allow any instruction\n\
6822 -mfpa10, -mfpa11 select floating point architecture\n\
6823 -mfpe-old don't allow floating-point multiple instructions\n\
6824 -mno-fpu don't allow any floating-point instructions.\n\
6825 -k generate PIC code.\n"));
6826 #if defined OBJ_COFF || defined OBJ_ELF
6828 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
6829 -mapcs-float floating point args are passed in FP regs\n\
6830 -mapcs-reentrant the code is position independent/reentrant\n"));
6834 -moabi support the old ELF ABI\n"));
6836 #ifdef ARM_BI_ENDIAN
6838 -EB assemble code for a big endian cpu\n\
6839 -EL assemble code for a little endian cpu\n"));
6843 /* We need to be able to fix up arbitrary expressions in some statements.
6844 This is so that we can handle symbols that are an arbitrary distance from
6845 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6846 which returns part of an address in a form which will be valid for
6847 a data instruction. We do this by pushing the expression into a symbol
6848 in the expr_section, and creating a fix for that. */
6851 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6860 arm_fix_data * arm_data;
6868 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6872 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6877 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6878 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6879 new_fix->tc_fix_data = (PTR) arm_data;
6880 arm_data->thumb_mode = thumb_mode;
6886 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6888 cons_fix_new_arm (frag, where, size, exp)
6894 bfd_reloc_code_real_type type;
6898 FIXME: @@ Should look at CPU word size. */
6905 type = BFD_RELOC_16;
6909 type = BFD_RELOC_32;
6912 type = BFD_RELOC_64;
6916 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6919 /* A good place to do this, although this was probably not intended
6920 for this kind of use. We need to dump the literal pool before
6921 references are made to a null symbol pointer. */
6925 if (current_poolP == NULL)
6928 subseg_set (text_section, 0); /* Put it at the end of text section. */
6930 listing_prev_line ();
6934 arm_start_line_hook ()
6936 last_label_seen = NULL;
6940 arm_frob_label (sym)
6943 last_label_seen = sym;
6945 ARM_SET_THUMB (sym, thumb_mode);
6947 #if defined OBJ_COFF || defined OBJ_ELF
6948 ARM_SET_INTERWORK (sym, support_interwork);
6951 if (label_is_thumb_function_name)
6953 /* When the address of a Thumb function is taken the bottom
6954 bit of that address should be set. This will allow
6955 interworking between Arm and Thumb functions to work
6958 THUMB_SET_FUNC (sym, 1);
6960 label_is_thumb_function_name = false;
6964 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6968 arm_adjust_symtab ()
6973 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6975 if (ARM_IS_THUMB (sym))
6977 if (THUMB_IS_FUNC (sym))
6979 /* Mark the symbol as a Thumb function. */
6980 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6981 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6982 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6984 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6985 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6987 as_bad (_("%s: unexpected function type: %d"),
6988 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6990 else switch (S_GET_STORAGE_CLASS (sym))
6993 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6996 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6999 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7001 default: /* do nothing */
7006 if (ARM_IS_INTERWORK (sym))
7007 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7014 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7016 if (ARM_IS_THUMB (sym))
7018 elf_symbol_type * elf_sym;
7020 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7021 bind = ELF_ST_BIND (elf_sym);
7023 /* If it's a .thumb_func, declare it as so,
7024 otherwise tag label as .code 16. */
7025 if (THUMB_IS_FUNC (sym))
7026 elf_sym->internal_elf_sym.st_info =
7027 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7029 elf_sym->internal_elf_sym.st_info =
7030 ELF_ST_INFO (bind, STT_ARM_16BIT);
7039 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7041 *input_line_pointer = '/';
7042 input_line_pointer += 5;
7043 *input_line_pointer = 0;
7051 arm_canonicalize_symbol_name (name)
7056 if (thumb_mode && (len = strlen (name)) > 5
7057 && streq (name + len - 5, "/data"))
7058 *(name + len - 5) = 0;
7064 arm_validate_fix (fixP)
7067 /* If the destination of the branch is a defined symbol which does not have
7068 the THUMB_FUNC attribute, then we must be calling a function which has
7069 the (interfacearm) attribute. We look for the Thumb entry point to that
7070 function and change the branch to refer to that function instead. */
7071 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7072 && fixP->fx_addsy != NULL
7073 && S_IS_DEFINED (fixP->fx_addsy)
7074 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7076 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7084 /* Relocations against Thumb function names must be left unadjusted,
7085 so that the linker can use this information to correctly set the
7086 bottom bit of their addresses. The MIPS version of this function
7087 also prevents relocations that are mips-16 specific, but I do not
7088 know why it does this.
7091 There is one other problem that ought to be addressed here, but
7092 which currently is not: Taking the address of a label (rather
7093 than a function) and then later jumping to that address. Such
7094 addresses also ought to have their bottom bit set (assuming that
7095 they reside in Thumb code), but at the moment they will not. */
7098 arm_fix_adjustable (fixP)
7101 if (fixP->fx_addsy == NULL)
7104 /* Prevent all adjustments to global symbols. */
7105 if (S_IS_EXTERN (fixP->fx_addsy))
7108 if (S_IS_WEAK (fixP->fx_addsy))
7111 if (THUMB_IS_FUNC (fixP->fx_addsy)
7112 && fixP->fx_subsy == NULL)
7115 /* We need the symbol name for the VTABLE entries */
7116 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7117 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7124 elf32_arm_target_format ()
7126 if (target_big_endian)
7128 return "elf32-bigarm-oabi";
7130 return "elf32-bigarm";
7133 return "elf32-littlearm-oabi";
7135 return "elf32-littlearm";
7139 armelf_frob_symbol (symp, puntp)
7143 elf_frob_symbol (symp, puntp);
7147 arm_force_relocation (fixp)
7150 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7151 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7152 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7153 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7154 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7155 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7161 static bfd_reloc_code_real_type
7171 bfd_reloc_code_real_type reloc;
7175 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7176 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7177 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7178 /* ScottB: Jan 30, 1998 */
7179 /* Added support for parsing "var(PLT)" branch instructions */
7180 /* generated by GCC for PLT relocs */
7181 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7182 { NULL, 0, BFD_RELOC_UNUSED }
7186 for (i = 0, ip = input_line_pointer;
7187 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7189 id[i] = tolower (*ip);
7191 for (i = 0; reloc_map[i].str; i++)
7192 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7195 input_line_pointer += reloc_map[i].len;
7197 return reloc_map[i].reloc;
7201 s_arm_elf_cons (nbytes)
7206 #ifdef md_flush_pending_output
7207 md_flush_pending_output ();
7210 if (is_it_end_of_statement ())
7212 demand_empty_rest_of_line ();
7216 #ifdef md_cons_align
7217 md_cons_align (nbytes);
7222 bfd_reloc_code_real_type reloc;
7226 if (exp.X_op == O_symbol
7227 && * input_line_pointer == '('
7228 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7230 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7231 int size = bfd_get_reloc_size (howto);
7234 as_bad ("%s relocations do not fit in %d bytes",
7235 howto->name, nbytes);
7238 register char * p = frag_more ((int) nbytes);
7239 int offset = nbytes - size;
7241 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7246 emit_expr (& exp, (unsigned int) nbytes);
7248 while (*input_line_pointer++ == ',');
7250 input_line_pointer--; /* Put terminator back into stream. */
7251 demand_empty_rest_of_line ();
7254 #endif /* OBJ_ELF */