1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
337 enum neon_el_type type;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el[NEON_MAX_TYPE_ELS];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN /* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type;
389 enum it_instruction_type it_insn_type;
395 struct neon_type_el vectype;
396 unsigned present : 1; /* Operand present. */
397 unsigned isreg : 1; /* Operand was a register. */
398 unsigned immisreg : 1; /* .imm field is a second register. */
399 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle : 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc : 1; /* Operand has relocation suffix. */
409 unsigned writeback : 1; /* Operand has trailing ! */
410 unsigned preind : 1; /* Preindexed address. */
411 unsigned postind : 1; /* Postindexed address. */
412 unsigned negative : 1; /* Index register was negated. */
413 unsigned shifted : 1; /* Shift applied to operation. */
414 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
415 } operands[ARM_IT_MAX_OPERANDS];
418 static struct arm_it inst;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name;
454 #define COND_ALWAYS 0xE
458 const char * template_name;
462 struct asm_barrier_opt
464 const char * template_name;
468 /* The bit that distinguishes CPSR and SPSR. */
469 #define SPSR_BIT (1 << 22)
471 /* The individual PSR flag bits. */
472 #define PSR_c (1 << 16)
473 #define PSR_x (1 << 17)
474 #define PSR_s (1 << 18)
475 #define PSR_f (1 << 19)
480 bfd_reloc_code_real_type reloc;
485 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
486 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
491 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
494 /* Bits for DEFINED field in neon_typed_alias. */
495 #define NTA_HASTYPE 1
496 #define NTA_HASINDEX 2
498 struct neon_typed_alias
500 unsigned char defined;
502 struct neon_type_el eltype;
505 /* ARM register categories. This includes coprocessor numbers and various
506 architecture extensions' registers. */
533 /* Structure for a hash table entry for a register.
534 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
535 information which states whether a vector type or index is specified (for a
536 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
542 unsigned char builtin;
543 struct neon_typed_alias * neon;
546 /* Diagnostics used when we don't get a register of the expected type. */
547 const char * const reg_expected_msgs[] =
549 N_("ARM register expected"),
550 N_("bad or missing co-processor number"),
551 N_("co-processor register expected"),
552 N_("FPA register expected"),
553 N_("VFP single precision register expected"),
554 N_("VFP/Neon double precision register expected"),
555 N_("Neon quad precision register expected"),
556 N_("VFP single or double precision register expected"),
557 N_("Neon double or quad precision register expected"),
558 N_("VFP single, double or Neon quad precision register expected"),
559 N_("VFP system register expected"),
560 N_("Maverick MVF register expected"),
561 N_("Maverick MVD register expected"),
562 N_("Maverick MVFX register expected"),
563 N_("Maverick MVDX register expected"),
564 N_("Maverick MVAX register expected"),
565 N_("Maverick DSPSC register expected"),
566 N_("iWMMXt data register expected"),
567 N_("iWMMXt control register expected"),
568 N_("iWMMXt scalar register expected"),
569 N_("XScale accumulator register expected"),
572 /* Some well known registers that we refer to directly elsewhere. */
578 /* ARM instructions take 4bytes in the object file, Thumb instructions
584 /* Basic string to match. */
585 const char * template_name;
587 /* Parameters to instruction. */
588 unsigned int operands[8];
590 /* Conditional tag - see opcode_lookup. */
591 unsigned int tag : 4;
593 /* Basic instruction code. */
594 unsigned int avalue : 28;
596 /* Thumb-format instruction code. */
599 /* Which architecture variant provides this instruction. */
600 const arm_feature_set * avariant;
601 const arm_feature_set * tvariant;
603 /* Function to call to encode instruction in ARM format. */
604 void (* aencode) (void);
606 /* Function to call to encode instruction in Thumb format. */
607 void (* tencode) (void);
610 /* Defines for various bits that we will want to toggle. */
611 #define INST_IMMEDIATE 0x02000000
612 #define OFFSET_REG 0x02000000
613 #define HWOFFSET_IMM 0x00400000
614 #define SHIFT_BY_REG 0x00000010
615 #define PRE_INDEX 0x01000000
616 #define INDEX_UP 0x00800000
617 #define WRITE_BACK 0x00200000
618 #define LDM_TYPE_2_OR_3 0x00400000
619 #define CPSI_MMOD 0x00020000
621 #define LITERAL_MASK 0xf000f000
622 #define OPCODE_MASK 0xfe1fffff
623 #define V4_STR_BIT 0x00000020
625 #define T2_SUBS_PC_LR 0xf3de8f00
627 #define DATA_OP_SHIFT 21
629 #define T2_OPCODE_MASK 0xfe1fffff
630 #define T2_DATA_OP_SHIFT 21
632 #define A_COND_MASK 0xf0000000
633 #define A_PUSH_POP_OP_MASK 0x0fff0000
635 /* Opcodes for pushing/poping registers to/from the stack. */
636 #define A1_OPCODE_PUSH 0x092d0000
637 #define A2_OPCODE_PUSH 0x052d0004
638 #define A2_OPCODE_POP 0x049d0004
640 /* Codes to distinguish the arithmetic instructions. */
651 #define OPCODE_CMP 10
652 #define OPCODE_CMN 11
653 #define OPCODE_ORR 12
654 #define OPCODE_MOV 13
655 #define OPCODE_BIC 14
656 #define OPCODE_MVN 15
658 #define T2_OPCODE_AND 0
659 #define T2_OPCODE_BIC 1
660 #define T2_OPCODE_ORR 2
661 #define T2_OPCODE_ORN 3
662 #define T2_OPCODE_EOR 4
663 #define T2_OPCODE_ADD 8
664 #define T2_OPCODE_ADC 10
665 #define T2_OPCODE_SBC 11
666 #define T2_OPCODE_SUB 13
667 #define T2_OPCODE_RSB 14
669 #define T_OPCODE_MUL 0x4340
670 #define T_OPCODE_TST 0x4200
671 #define T_OPCODE_CMN 0x42c0
672 #define T_OPCODE_NEG 0x4240
673 #define T_OPCODE_MVN 0x43c0
675 #define T_OPCODE_ADD_R3 0x1800
676 #define T_OPCODE_SUB_R3 0x1a00
677 #define T_OPCODE_ADD_HI 0x4400
678 #define T_OPCODE_ADD_ST 0xb000
679 #define T_OPCODE_SUB_ST 0xb080
680 #define T_OPCODE_ADD_SP 0xa800
681 #define T_OPCODE_ADD_PC 0xa000
682 #define T_OPCODE_ADD_I8 0x3000
683 #define T_OPCODE_SUB_I8 0x3800
684 #define T_OPCODE_ADD_I3 0x1c00
685 #define T_OPCODE_SUB_I3 0x1e00
687 #define T_OPCODE_ASR_R 0x4100
688 #define T_OPCODE_LSL_R 0x4080
689 #define T_OPCODE_LSR_R 0x40c0
690 #define T_OPCODE_ROR_R 0x41c0
691 #define T_OPCODE_ASR_I 0x1000
692 #define T_OPCODE_LSL_I 0x0000
693 #define T_OPCODE_LSR_I 0x0800
695 #define T_OPCODE_MOV_I8 0x2000
696 #define T_OPCODE_CMP_I8 0x2800
697 #define T_OPCODE_CMP_LR 0x4280
698 #define T_OPCODE_MOV_HR 0x4600
699 #define T_OPCODE_CMP_HR 0x4500
701 #define T_OPCODE_LDR_PC 0x4800
702 #define T_OPCODE_LDR_SP 0x9800
703 #define T_OPCODE_STR_SP 0x9000
704 #define T_OPCODE_LDR_IW 0x6800
705 #define T_OPCODE_STR_IW 0x6000
706 #define T_OPCODE_LDR_IH 0x8800
707 #define T_OPCODE_STR_IH 0x8000
708 #define T_OPCODE_LDR_IB 0x7800
709 #define T_OPCODE_STR_IB 0x7000
710 #define T_OPCODE_LDR_RW 0x5800
711 #define T_OPCODE_STR_RW 0x5000
712 #define T_OPCODE_LDR_RH 0x5a00
713 #define T_OPCODE_STR_RH 0x5200
714 #define T_OPCODE_LDR_RB 0x5c00
715 #define T_OPCODE_STR_RB 0x5400
717 #define T_OPCODE_PUSH 0xb400
718 #define T_OPCODE_POP 0xbc00
720 #define T_OPCODE_BRANCH 0xe000
722 #define THUMB_SIZE 2 /* Size of thumb instruction. */
723 #define THUMB_PP_PC_LR 0x0100
724 #define THUMB_LOAD_BIT 0x0800
725 #define THUMB2_LOAD_BIT 0x00100000
727 #define BAD_ARGS _("bad arguments to instruction")
728 #define BAD_SP _("r13 not allowed here")
729 #define BAD_PC _("r15 not allowed here")
730 #define BAD_COND _("instruction cannot be conditional")
731 #define BAD_OVERLAP _("registers may not be the same")
732 #define BAD_HIREG _("lo register required")
733 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
734 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
735 #define BAD_BRANCH _("branch must be last instruction in IT block")
736 #define BAD_NOT_IT _("instruction not allowed in IT block")
737 #define BAD_FPU _("selected FPU does not support instruction")
738 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
739 #define BAD_IT_COND _("incorrect condition in IT block")
740 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
741 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
742 #define BAD_PC_ADDRESSING \
743 _("cannot use register index with PC-relative addressing")
744 #define BAD_PC_WRITEBACK \
745 _("cannot use writeback with PC-relative addressing")
746 #define BAD_RANGE _("branch out of range")
748 static struct hash_control * arm_ops_hsh;
749 static struct hash_control * arm_cond_hsh;
750 static struct hash_control * arm_shift_hsh;
751 static struct hash_control * arm_psr_hsh;
752 static struct hash_control * arm_v7m_psr_hsh;
753 static struct hash_control * arm_reg_hsh;
754 static struct hash_control * arm_reloc_hsh;
755 static struct hash_control * arm_barrier_opt_hsh;
757 /* Stuff needed to resolve the label ambiguity
766 symbolS * last_label_seen;
767 static int label_is_thumb_function_name = FALSE;
769 /* Literal pool structure. Held on a per-section
770 and per-sub-section basis. */
772 #define MAX_LITERAL_POOL_SIZE 1024
773 typedef struct literal_pool
775 expressionS literals [MAX_LITERAL_POOL_SIZE];
776 unsigned int next_free_entry;
782 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
784 struct literal_pool * next;
787 /* Pointer to a linked list of literal pools. */
788 literal_pool * list_of_pools = NULL;
791 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
793 static struct current_it now_it;
797 now_it_compatible (int cond)
799 return (cond & ~1) == (now_it.cc & ~1);
803 conditional_insn (void)
805 return inst.cond != COND_ALWAYS;
808 static int in_it_block (void);
810 static int handle_it_state (void);
812 static void force_automatic_it_block_close (void);
814 static void it_fsm_post_encode (void);
816 #define set_it_insn_type(type) \
819 inst.it_insn_type = type; \
820 if (handle_it_state () == FAIL) \
825 #define set_it_insn_type_nonvoid(type, failret) \
828 inst.it_insn_type = type; \
829 if (handle_it_state () == FAIL) \
834 #define set_it_insn_type_last() \
837 if (inst.cond == COND_ALWAYS) \
838 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
840 set_it_insn_type (INSIDE_IT_LAST_INSN); \
846 /* This array holds the chars that always start a comment. If the
847 pre-processor is disabled, these aren't very useful. */
848 const char comment_chars[] = "@";
850 /* This array holds the chars that only start a comment at the beginning of
851 a line. If the line seems to have the form '# 123 filename'
852 .line and .file directives will appear in the pre-processed output. */
853 /* Note that input_file.c hand checks for '#' at the beginning of the
854 first line of the input file. This is because the compiler outputs
855 #NO_APP at the beginning of its output. */
856 /* Also note that comments like this one will always work. */
857 const char line_comment_chars[] = "#";
859 const char line_separator_chars[] = ";";
861 /* Chars that can be used to separate mant
862 from exp in floating point numbers. */
863 const char EXP_CHARS[] = "eE";
865 /* Chars that mean this number is a floating point constant. */
869 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
871 /* Prefix characters that indicate the start of an immediate
873 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
875 /* Separator character handling. */
877 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
880 skip_past_char (char ** str, char c)
891 #define skip_past_comma(str) skip_past_char (str, ',')
893 /* Arithmetic expressions (possibly involving symbols). */
895 /* Return TRUE if anything in the expression is a bignum. */
898 walk_no_bignums (symbolS * sp)
900 if (symbol_get_value_expression (sp)->X_op == O_big)
903 if (symbol_get_value_expression (sp)->X_add_symbol)
905 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
906 || (symbol_get_value_expression (sp)->X_op_symbol
907 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
913 static int in_my_get_expression = 0;
915 /* Third argument to my_get_expression. */
916 #define GE_NO_PREFIX 0
917 #define GE_IMM_PREFIX 1
918 #define GE_OPT_PREFIX 2
919 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
920 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
921 #define GE_OPT_PREFIX_BIG 3
924 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
929 /* In unified syntax, all prefixes are optional. */
931 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
936 case GE_NO_PREFIX: break;
938 if (!is_immediate_prefix (**str))
940 inst.error = _("immediate expression requires a # prefix");
946 case GE_OPT_PREFIX_BIG:
947 if (is_immediate_prefix (**str))
953 memset (ep, 0, sizeof (expressionS));
955 save_in = input_line_pointer;
956 input_line_pointer = *str;
957 in_my_get_expression = 1;
958 seg = expression (ep);
959 in_my_get_expression = 0;
961 if (ep->X_op == O_illegal || ep->X_op == O_absent)
963 /* We found a bad or missing expression in md_operand(). */
964 *str = input_line_pointer;
965 input_line_pointer = save_in;
966 if (inst.error == NULL)
967 inst.error = (ep->X_op == O_absent
968 ? _("missing expression") :_("bad expression"));
973 if (seg != absolute_section
974 && seg != text_section
975 && seg != data_section
976 && seg != bss_section
977 && seg != undefined_section)
979 inst.error = _("bad segment");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
988 /* Get rid of any bignums now, so that we don't generate an error for which
989 we can't establish a line number later on. Big numbers are never valid
990 in instructions, which is where this routine is always called. */
991 if (prefix_mode != GE_OPT_PREFIX_BIG
992 && (ep->X_op == O_big
994 && (walk_no_bignums (ep->X_add_symbol)
996 && walk_no_bignums (ep->X_op_symbol))))))
998 inst.error = _("invalid constant");
999 *str = input_line_pointer;
1000 input_line_pointer = save_in;
1004 *str = input_line_pointer;
1005 input_line_pointer = save_in;
1009 /* Turn a string in input_line_pointer into a floating point constant
1010 of type TYPE, and store the appropriate bytes in *LITP. The number
1011 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1012 returned, or NULL on OK.
1014 Note that fp constants aren't represent in the normal way on the ARM.
1015 In big endian mode, things are as expected. However, in little endian
1016 mode fp constants are big-endian word-wise, and little-endian byte-wise
1017 within the words. For example, (double) 1.1 in big endian mode is
1018 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1019 the byte sequence 99 99 f1 3f 9a 99 99 99.
1021 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1024 md_atof (int type, char * litP, int * sizeP)
1027 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1059 return _("Unrecognized or unsupported floating point constant");
1062 t = atof_ieee (input_line_pointer, type, words);
1064 input_line_pointer = t;
1065 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1067 if (target_big_endian)
1069 for (i = 0; i < prec; i++)
1071 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1072 litP += sizeof (LITTLENUM_TYPE);
1077 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1078 for (i = prec - 1; i >= 0; i--)
1080 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1081 litP += sizeof (LITTLENUM_TYPE);
1084 /* For a 4 byte float the order of elements in `words' is 1 0.
1085 For an 8 byte float the order is 1 0 3 2. */
1086 for (i = 0; i < prec; i += 2)
1088 md_number_to_chars (litP, (valueT) words[i + 1],
1089 sizeof (LITTLENUM_TYPE));
1090 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1091 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += 2 * sizeof (LITTLENUM_TYPE);
1099 /* We handle all bad expressions here, so that we can report the faulty
1100 instruction in the error message. */
1102 md_operand (expressionS * exp)
1104 if (in_my_get_expression)
1105 exp->X_op = O_illegal;
1108 /* Immediate values. */
1110 /* Generic immediate-value read function for use in directives.
1111 Accepts anything that 'expression' can fold to a constant.
1112 *val receives the number. */
1115 immediate_for_directive (int *val)
1118 exp.X_op = O_illegal;
1120 if (is_immediate_prefix (*input_line_pointer))
1122 input_line_pointer++;
1126 if (exp.X_op != O_constant)
1128 as_bad (_("expected #constant"));
1129 ignore_rest_of_line ();
1132 *val = exp.X_add_number;
1137 /* Register parsing. */
1139 /* Generic register parser. CCP points to what should be the
1140 beginning of a register name. If it is indeed a valid register
1141 name, advance CCP over it and return the reg_entry structure;
1142 otherwise return NULL. Does not issue diagnostics. */
1144 static struct reg_entry *
1145 arm_reg_parse_multi (char **ccp)
1149 struct reg_entry *reg;
1151 #ifdef REGISTER_PREFIX
1152 if (*start != REGISTER_PREFIX)
1156 #ifdef OPTIONAL_REGISTER_PREFIX
1157 if (*start == OPTIONAL_REGISTER_PREFIX)
1162 if (!ISALPHA (*p) || !is_name_beginner (*p))
1167 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1169 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1179 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1180 enum arm_reg_type type)
1182 /* Alternative syntaxes are accepted for a few register classes. */
1189 /* Generic coprocessor register names are allowed for these. */
1190 if (reg && reg->type == REG_TYPE_CN)
1195 /* For backward compatibility, a bare number is valid here. */
1197 unsigned long processor = strtoul (start, ccp, 10);
1198 if (*ccp != start && processor <= 15)
1202 case REG_TYPE_MMXWC:
1203 /* WC includes WCG. ??? I'm not sure this is true for all
1204 instructions that take WC registers. */
1205 if (reg && reg->type == REG_TYPE_MMXWCG)
1216 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1217 return value is the register number or FAIL. */
1220 arm_reg_parse (char **ccp, enum arm_reg_type type)
1223 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1226 /* Do not allow a scalar (reg+index) to parse as a register. */
1227 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1230 if (reg && reg->type == type)
1233 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1240 /* Parse a Neon type specifier. *STR should point at the leading '.'
1241 character. Does no verification at this stage that the type fits the opcode
1248 Can all be legally parsed by this function.
1250 Fills in neon_type struct pointer with parsed information, and updates STR
1251 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1252 type, FAIL if not. */
1255 parse_neon_type (struct neon_type *type, char **str)
1262 while (type->elems < NEON_MAX_TYPE_ELS)
1264 enum neon_el_type thistype = NT_untyped;
1265 unsigned thissize = -1u;
1272 /* Just a size without an explicit type. */
1276 switch (TOLOWER (*ptr))
1278 case 'i': thistype = NT_integer; break;
1279 case 'f': thistype = NT_float; break;
1280 case 'p': thistype = NT_poly; break;
1281 case 's': thistype = NT_signed; break;
1282 case 'u': thistype = NT_unsigned; break;
1284 thistype = NT_float;
1289 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1295 /* .f is an abbreviation for .f32. */
1296 if (thistype == NT_float && !ISDIGIT (*ptr))
1301 thissize = strtoul (ptr, &ptr, 10);
1303 if (thissize != 8 && thissize != 16 && thissize != 32
1306 as_bad (_("bad size %d in type specifier"), thissize);
1314 type->el[type->elems].type = thistype;
1315 type->el[type->elems].size = thissize;
1320 /* Empty/missing type is not a successful parse. */
1321 if (type->elems == 0)
1329 /* Errors may be set multiple times during parsing or bit encoding
1330 (particularly in the Neon bits), but usually the earliest error which is set
1331 will be the most meaningful. Avoid overwriting it with later (cascading)
1332 errors by calling this function. */
1335 first_error (const char *err)
1341 /* Parse a single type, e.g. ".s32", leading period included. */
1343 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1346 struct neon_type optype;
1350 if (parse_neon_type (&optype, &str) == SUCCESS)
1352 if (optype.elems == 1)
1353 *vectype = optype.el[0];
1356 first_error (_("only one type should be specified for operand"));
1362 first_error (_("vector type expected"));
1374 /* Special meanings for indices (which have a range of 0-7), which will fit into
1377 #define NEON_ALL_LANES 15
1378 #define NEON_INTERLEAVE_LANES 14
1380 /* Parse either a register or a scalar, with an optional type. Return the
1381 register number, and optionally fill in the actual type of the register
1382 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1383 type/index information in *TYPEINFO. */
1386 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1387 enum arm_reg_type *rtype,
1388 struct neon_typed_alias *typeinfo)
1391 struct reg_entry *reg = arm_reg_parse_multi (&str);
1392 struct neon_typed_alias atype;
1393 struct neon_type_el parsetype;
1397 atype.eltype.type = NT_invtype;
1398 atype.eltype.size = -1;
1400 /* Try alternate syntax for some types of register. Note these are mutually
1401 exclusive with the Neon syntax extensions. */
1404 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1412 /* Undo polymorphism when a set of register types may be accepted. */
1413 if ((type == REG_TYPE_NDQ
1414 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1415 || (type == REG_TYPE_VFSD
1416 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1417 || (type == REG_TYPE_NSDQ
1418 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1419 || reg->type == REG_TYPE_NQ))
1420 || (type == REG_TYPE_MMXWC
1421 && (reg->type == REG_TYPE_MMXWCG)))
1422 type = (enum arm_reg_type) reg->type;
1424 if (type != reg->type)
1430 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1432 if ((atype.defined & NTA_HASTYPE) != 0)
1434 first_error (_("can't redefine type for operand"));
1437 atype.defined |= NTA_HASTYPE;
1438 atype.eltype = parsetype;
1441 if (skip_past_char (&str, '[') == SUCCESS)
1443 if (type != REG_TYPE_VFD)
1445 first_error (_("only D registers may be indexed"));
1449 if ((atype.defined & NTA_HASINDEX) != 0)
1451 first_error (_("can't change index for operand"));
1455 atype.defined |= NTA_HASINDEX;
1457 if (skip_past_char (&str, ']') == SUCCESS)
1458 atype.index = NEON_ALL_LANES;
1463 my_get_expression (&exp, &str, GE_NO_PREFIX);
1465 if (exp.X_op != O_constant)
1467 first_error (_("constant expression required"));
1471 if (skip_past_char (&str, ']') == FAIL)
1474 atype.index = exp.X_add_number;
1489 /* Like arm_reg_parse, but allow allow the following extra features:
1490 - If RTYPE is non-zero, return the (possibly restricted) type of the
1491 register (e.g. Neon double or quad reg when either has been requested).
1492 - If this is a Neon vector type with additional type information, fill
1493 in the struct pointed to by VECTYPE (if non-NULL).
1494 This function will fault on encountering a scalar. */
1497 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1498 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1500 struct neon_typed_alias atype;
1502 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1507 /* Do not allow regname(... to parse as a register. */
1511 /* Do not allow a scalar (reg+index) to parse as a register. */
1512 if ((atype.defined & NTA_HASINDEX) != 0)
1514 first_error (_("register operand expected, but got scalar"));
1519 *vectype = atype.eltype;
1526 #define NEON_SCALAR_REG(X) ((X) >> 4)
1527 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1529 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1530 have enough information to be able to do a good job bounds-checking. So, we
1531 just do easy checks here, and do further checks later. */
1534 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1538 struct neon_typed_alias atype;
1540 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1542 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1545 if (atype.index == NEON_ALL_LANES)
1547 first_error (_("scalar must have an index"));
1550 else if (atype.index >= 64 / elsize)
1552 first_error (_("scalar index out of range"));
1557 *type = atype.eltype;
1561 return reg * 16 + atype.index;
1564 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1567 parse_reg_list (char ** strp)
1569 char * str = * strp;
1573 /* We come back here if we get ranges concatenated by '+' or '|'. */
1588 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1590 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1600 first_error (_("bad range in register list"));
1604 for (i = cur_reg + 1; i < reg; i++)
1606 if (range & (1 << i))
1608 (_("Warning: duplicated register (r%d) in register list"),
1616 if (range & (1 << reg))
1617 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1619 else if (reg <= cur_reg)
1620 as_tsktsk (_("Warning: register range not in ascending order"));
1625 while (skip_past_comma (&str) != FAIL
1626 || (in_range = 1, *str++ == '-'));
1631 first_error (_("missing `}'"));
1639 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1642 if (exp.X_op == O_constant)
1644 if (exp.X_add_number
1645 != (exp.X_add_number & 0x0000ffff))
1647 inst.error = _("invalid register mask");
1651 if ((range & exp.X_add_number) != 0)
1653 int regno = range & exp.X_add_number;
1656 regno = (1 << regno) - 1;
1658 (_("Warning: duplicated register (r%d) in register list"),
1662 range |= exp.X_add_number;
1666 if (inst.reloc.type != 0)
1668 inst.error = _("expression too complex");
1672 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1673 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1674 inst.reloc.pc_rel = 0;
1678 if (*str == '|' || *str == '+')
1684 while (another_range);
1690 /* Types of registers in a list. */
1699 /* Parse a VFP register list. If the string is invalid return FAIL.
1700 Otherwise return the number of registers, and set PBASE to the first
1701 register. Parses registers of type ETYPE.
1702 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1703 - Q registers can be used to specify pairs of D registers
1704 - { } can be omitted from around a singleton register list
1705 FIXME: This is not implemented, as it would require backtracking in
1708 This could be done (the meaning isn't really ambiguous), but doesn't
1709 fit in well with the current parsing framework.
1710 - 32 D registers may be used (also true for VFPv3).
1711 FIXME: Types are ignored in these register lists, which is probably a
1715 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1720 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1724 unsigned long mask = 0;
1729 inst.error = _("expecting {");
1738 regtype = REG_TYPE_VFS;
1743 regtype = REG_TYPE_VFD;
1746 case REGLIST_NEON_D:
1747 regtype = REG_TYPE_NDQ;
1751 if (etype != REGLIST_VFP_S)
1753 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1754 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1758 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1761 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1768 base_reg = max_regs;
1772 int setmask = 1, addregs = 1;
1774 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1776 if (new_base == FAIL)
1778 first_error (_(reg_expected_msgs[regtype]));
1782 if (new_base >= max_regs)
1784 first_error (_("register out of range in list"));
1788 /* Note: a value of 2 * n is returned for the register Q<n>. */
1789 if (regtype == REG_TYPE_NQ)
1795 if (new_base < base_reg)
1796 base_reg = new_base;
1798 if (mask & (setmask << new_base))
1800 first_error (_("invalid register list"));
1804 if ((mask >> new_base) != 0 && ! warned)
1806 as_tsktsk (_("register list not in ascending order"));
1810 mask |= setmask << new_base;
1813 if (*str == '-') /* We have the start of a range expression */
1819 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1822 inst.error = gettext (reg_expected_msgs[regtype]);
1826 if (high_range >= max_regs)
1828 first_error (_("register out of range in list"));
1832 if (regtype == REG_TYPE_NQ)
1833 high_range = high_range + 1;
1835 if (high_range <= new_base)
1837 inst.error = _("register range not in ascending order");
1841 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1843 if (mask & (setmask << new_base))
1845 inst.error = _("invalid register list");
1849 mask |= setmask << new_base;
1854 while (skip_past_comma (&str) != FAIL);
1858 /* Sanity check -- should have raised a parse error above. */
1859 if (count == 0 || count > max_regs)
1864 /* Final test -- the registers must be consecutive. */
1866 for (i = 0; i < count; i++)
1868 if ((mask & (1u << i)) == 0)
1870 inst.error = _("non-contiguous register range");
1880 /* True if two alias types are the same. */
1883 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1891 if (a->defined != b->defined)
1894 if ((a->defined & NTA_HASTYPE) != 0
1895 && (a->eltype.type != b->eltype.type
1896 || a->eltype.size != b->eltype.size))
1899 if ((a->defined & NTA_HASINDEX) != 0
1900 && (a->index != b->index))
1906 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1907 The base register is put in *PBASE.
1908 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1910 The register stride (minus one) is put in bit 4 of the return value.
1911 Bits [6:5] encode the list length (minus one).
1912 The type of the list elements is put in *ELTYPE, if non-NULL. */
1914 #define NEON_LANE(X) ((X) & 0xf)
1915 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1916 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1919 parse_neon_el_struct_list (char **str, unsigned *pbase,
1920 struct neon_type_el *eltype)
1927 int leading_brace = 0;
1928 enum arm_reg_type rtype = REG_TYPE_NDQ;
1929 const char *const incr_error = _("register stride must be 1 or 2");
1930 const char *const type_error = _("mismatched element/structure types in list");
1931 struct neon_typed_alias firsttype;
1933 if (skip_past_char (&ptr, '{') == SUCCESS)
1938 struct neon_typed_alias atype;
1939 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1943 first_error (_(reg_expected_msgs[rtype]));
1950 if (rtype == REG_TYPE_NQ)
1956 else if (reg_incr == -1)
1958 reg_incr = getreg - base_reg;
1959 if (reg_incr < 1 || reg_incr > 2)
1961 first_error (_(incr_error));
1965 else if (getreg != base_reg + reg_incr * count)
1967 first_error (_(incr_error));
1971 if (! neon_alias_types_same (&atype, &firsttype))
1973 first_error (_(type_error));
1977 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1981 struct neon_typed_alias htype;
1982 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1984 lane = NEON_INTERLEAVE_LANES;
1985 else if (lane != NEON_INTERLEAVE_LANES)
1987 first_error (_(type_error));
1992 else if (reg_incr != 1)
1994 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1998 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2001 first_error (_(reg_expected_msgs[rtype]));
2004 if (! neon_alias_types_same (&htype, &firsttype))
2006 first_error (_(type_error));
2009 count += hireg + dregs - getreg;
2013 /* If we're using Q registers, we can't use [] or [n] syntax. */
2014 if (rtype == REG_TYPE_NQ)
2020 if ((atype.defined & NTA_HASINDEX) != 0)
2024 else if (lane != atype.index)
2026 first_error (_(type_error));
2030 else if (lane == -1)
2031 lane = NEON_INTERLEAVE_LANES;
2032 else if (lane != NEON_INTERLEAVE_LANES)
2034 first_error (_(type_error));
2039 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2041 /* No lane set by [x]. We must be interleaving structures. */
2043 lane = NEON_INTERLEAVE_LANES;
2046 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2047 || (count > 1 && reg_incr == -1))
2049 first_error (_("error parsing element/structure list"));
2053 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2055 first_error (_("expected }"));
2063 *eltype = firsttype.eltype;
2068 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2071 /* Parse an explicit relocation suffix on an expression. This is
2072 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2073 arm_reloc_hsh contains no entries, so this function can only
2074 succeed if there is no () after the word. Returns -1 on error,
2075 BFD_RELOC_UNUSED if there wasn't any suffix. */
2078 parse_reloc (char **str)
2080 struct reloc_entry *r;
2084 return BFD_RELOC_UNUSED;
2089 while (*q && *q != ')' && *q != ',')
2094 if ((r = (struct reloc_entry *)
2095 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2102 /* Directives: register aliases. */
2104 static struct reg_entry *
2105 insert_reg_alias (char *str, unsigned number, int type)
2107 struct reg_entry *new_reg;
2110 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2112 if (new_reg->builtin)
2113 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2115 /* Only warn about a redefinition if it's not defined as the
2117 else if (new_reg->number != number || new_reg->type != type)
2118 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2123 name = xstrdup (str);
2124 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2126 new_reg->name = name;
2127 new_reg->number = number;
2128 new_reg->type = type;
2129 new_reg->builtin = FALSE;
2130 new_reg->neon = NULL;
2132 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2139 insert_neon_reg_alias (char *str, int number, int type,
2140 struct neon_typed_alias *atype)
2142 struct reg_entry *reg = insert_reg_alias (str, number, type);
2146 first_error (_("attempt to redefine typed alias"));
2152 reg->neon = (struct neon_typed_alias *)
2153 xmalloc (sizeof (struct neon_typed_alias));
2154 *reg->neon = *atype;
2158 /* Look for the .req directive. This is of the form:
2160 new_register_name .req existing_register_name
2162 If we find one, or if it looks sufficiently like one that we want to
2163 handle any error here, return TRUE. Otherwise return FALSE. */
2166 create_register_alias (char * newname, char *p)
2168 struct reg_entry *old;
2169 char *oldname, *nbuf;
2172 /* The input scrubber ensures that whitespace after the mnemonic is
2173 collapsed to single spaces. */
2175 if (strncmp (oldname, " .req ", 6) != 0)
2179 if (*oldname == '\0')
2182 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2185 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2189 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2190 the desired alias name, and p points to its end. If not, then
2191 the desired alias name is in the global original_case_string. */
2192 #ifdef TC_CASE_SENSITIVE
2195 newname = original_case_string;
2196 nlen = strlen (newname);
2199 nbuf = (char *) alloca (nlen + 1);
2200 memcpy (nbuf, newname, nlen);
2203 /* Create aliases under the new name as stated; an all-lowercase
2204 version of the new name; and an all-uppercase version of the new
2206 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2208 for (p = nbuf; *p; p++)
2211 if (strncmp (nbuf, newname, nlen))
2213 /* If this attempt to create an additional alias fails, do not bother
2214 trying to create the all-lower case alias. We will fail and issue
2215 a second, duplicate error message. This situation arises when the
2216 programmer does something like:
2219 The second .req creates the "Foo" alias but then fails to create
2220 the artificial FOO alias because it has already been created by the
2222 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2226 for (p = nbuf; *p; p++)
2229 if (strncmp (nbuf, newname, nlen))
2230 insert_reg_alias (nbuf, old->number, old->type);
2236 /* Create a Neon typed/indexed register alias using directives, e.g.:
2241 These typed registers can be used instead of the types specified after the
2242 Neon mnemonic, so long as all operands given have types. Types can also be
2243 specified directly, e.g.:
2244 vadd d0.s32, d1.s32, d2.s32 */
2247 create_neon_reg_alias (char *newname, char *p)
2249 enum arm_reg_type basetype;
2250 struct reg_entry *basereg;
2251 struct reg_entry mybasereg;
2252 struct neon_type ntype;
2253 struct neon_typed_alias typeinfo;
2254 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2257 typeinfo.defined = 0;
2258 typeinfo.eltype.type = NT_invtype;
2259 typeinfo.eltype.size = -1;
2260 typeinfo.index = -1;
2264 if (strncmp (p, " .dn ", 5) == 0)
2265 basetype = REG_TYPE_VFD;
2266 else if (strncmp (p, " .qn ", 5) == 0)
2267 basetype = REG_TYPE_NQ;
2276 basereg = arm_reg_parse_multi (&p);
2278 if (basereg && basereg->type != basetype)
2280 as_bad (_("bad type for register"));
2284 if (basereg == NULL)
2287 /* Try parsing as an integer. */
2288 my_get_expression (&exp, &p, GE_NO_PREFIX);
2289 if (exp.X_op != O_constant)
2291 as_bad (_("expression must be constant"));
2294 basereg = &mybasereg;
2295 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2301 typeinfo = *basereg->neon;
2303 if (parse_neon_type (&ntype, &p) == SUCCESS)
2305 /* We got a type. */
2306 if (typeinfo.defined & NTA_HASTYPE)
2308 as_bad (_("can't redefine the type of a register alias"));
2312 typeinfo.defined |= NTA_HASTYPE;
2313 if (ntype.elems != 1)
2315 as_bad (_("you must specify a single type only"));
2318 typeinfo.eltype = ntype.el[0];
2321 if (skip_past_char (&p, '[') == SUCCESS)
2324 /* We got a scalar index. */
2326 if (typeinfo.defined & NTA_HASINDEX)
2328 as_bad (_("can't redefine the index of a scalar alias"));
2332 my_get_expression (&exp, &p, GE_NO_PREFIX);
2334 if (exp.X_op != O_constant)
2336 as_bad (_("scalar index must be constant"));
2340 typeinfo.defined |= NTA_HASINDEX;
2341 typeinfo.index = exp.X_add_number;
2343 if (skip_past_char (&p, ']') == FAIL)
2345 as_bad (_("expecting ]"));
2350 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2351 the desired alias name, and p points to its end. If not, then
2352 the desired alias name is in the global original_case_string. */
2353 #ifdef TC_CASE_SENSITIVE
2354 namelen = nameend - newname;
2356 newname = original_case_string;
2357 namelen = strlen (newname);
2360 namebuf = (char *) alloca (namelen + 1);
2361 strncpy (namebuf, newname, namelen);
2362 namebuf[namelen] = '\0';
2364 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2365 typeinfo.defined != 0 ? &typeinfo : NULL);
2367 /* Insert name in all uppercase. */
2368 for (p = namebuf; *p; p++)
2371 if (strncmp (namebuf, newname, namelen))
2372 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2373 typeinfo.defined != 0 ? &typeinfo : NULL);
2375 /* Insert name in all lowercase. */
2376 for (p = namebuf; *p; p++)
2379 if (strncmp (namebuf, newname, namelen))
2380 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2381 typeinfo.defined != 0 ? &typeinfo : NULL);
2386 /* Should never be called, as .req goes between the alias and the
2387 register name, not at the beginning of the line. */
2390 s_req (int a ATTRIBUTE_UNUSED)
2392 as_bad (_("invalid syntax for .req directive"));
2396 s_dn (int a ATTRIBUTE_UNUSED)
2398 as_bad (_("invalid syntax for .dn directive"));
2402 s_qn (int a ATTRIBUTE_UNUSED)
2404 as_bad (_("invalid syntax for .qn directive"));
2407 /* The .unreq directive deletes an alias which was previously defined
2408 by .req. For example:
2414 s_unreq (int a ATTRIBUTE_UNUSED)
2419 name = input_line_pointer;
2421 while (*input_line_pointer != 0
2422 && *input_line_pointer != ' '
2423 && *input_line_pointer != '\n')
2424 ++input_line_pointer;
2426 saved_char = *input_line_pointer;
2427 *input_line_pointer = 0;
2430 as_bad (_("invalid syntax for .unreq directive"));
2433 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2437 as_bad (_("unknown register alias '%s'"), name);
2438 else if (reg->builtin)
2439 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2446 hash_delete (arm_reg_hsh, name, FALSE);
2447 free ((char *) reg->name);
2452 /* Also locate the all upper case and all lower case versions.
2453 Do not complain if we cannot find one or the other as it
2454 was probably deleted above. */
2456 nbuf = strdup (name);
2457 for (p = nbuf; *p; p++)
2459 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2462 hash_delete (arm_reg_hsh, nbuf, FALSE);
2463 free ((char *) reg->name);
2469 for (p = nbuf; *p; p++)
2471 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2474 hash_delete (arm_reg_hsh, nbuf, FALSE);
2475 free ((char *) reg->name);
2485 *input_line_pointer = saved_char;
2486 demand_empty_rest_of_line ();
2489 /* Directives: Instruction set selection. */
2492 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2493 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2494 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2495 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2497 /* Create a new mapping symbol for the transition to STATE. */
2500 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2503 const char * symname;
2510 type = BSF_NO_FLAGS;
2514 type = BSF_NO_FLAGS;
2518 type = BSF_NO_FLAGS;
2524 symbolP = symbol_new (symname, now_seg, value, frag);
2525 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2530 THUMB_SET_FUNC (symbolP, 0);
2531 ARM_SET_THUMB (symbolP, 0);
2532 ARM_SET_INTERWORK (symbolP, support_interwork);
2536 THUMB_SET_FUNC (symbolP, 1);
2537 ARM_SET_THUMB (symbolP, 1);
2538 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 /* Save the mapping symbols for future reference. Also check that
2547 we do not place two mapping symbols at the same offset within a
2548 frag. We'll handle overlap between frags in
2549 check_mapping_symbols.
2551 If .fill or other data filling directive generates zero sized data,
2552 the mapping symbol for the following code will have the same value
2553 as the one generated for the data filling directive. In this case,
2554 we replace the old symbol with the new one at the same address. */
2557 if (frag->tc_frag_data.first_map != NULL)
2559 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2560 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2562 frag->tc_frag_data.first_map = symbolP;
2564 if (frag->tc_frag_data.last_map != NULL)
2566 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2567 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2568 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2570 frag->tc_frag_data.last_map = symbolP;
2573 /* We must sometimes convert a region marked as code to data during
2574 code alignment, if an odd number of bytes have to be padded. The
2575 code mapping symbol is pushed to an aligned address. */
2578 insert_data_mapping_symbol (enum mstate state,
2579 valueT value, fragS *frag, offsetT bytes)
2581 /* If there was already a mapping symbol, remove it. */
2582 if (frag->tc_frag_data.last_map != NULL
2583 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2585 symbolS *symp = frag->tc_frag_data.last_map;
2589 know (frag->tc_frag_data.first_map == symp);
2590 frag->tc_frag_data.first_map = NULL;
2592 frag->tc_frag_data.last_map = NULL;
2593 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2596 make_mapping_symbol (MAP_DATA, value, frag);
2597 make_mapping_symbol (state, value + bytes, frag);
2600 static void mapping_state_2 (enum mstate state, int max_chars);
2602 /* Set the mapping state to STATE. Only call this when about to
2603 emit some STATE bytes to the file. */
2606 mapping_state (enum mstate state)
2608 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2610 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2612 if (mapstate == state)
2613 /* The mapping symbol has already been emitted.
2614 There is nothing else to do. */
2617 if (state == MAP_ARM || state == MAP_THUMB)
2619 All ARM instructions require 4-byte alignment.
2620 (Almost) all Thumb instructions require 2-byte alignment.
2622 When emitting instructions into any section, mark the section
2625 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2626 but themselves require 2-byte alignment; this applies to some
2627 PC- relative forms. However, these cases will invovle implicit
2628 literal pool generation or an explicit .align >=2, both of
2629 which will cause the section to me marked with sufficient
2630 alignment. Thus, we don't handle those cases here. */
2631 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2633 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2634 /* This case will be evaluated later in the next else. */
2636 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2637 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2639 /* Only add the symbol if the offset is > 0:
2640 if we're at the first frag, check it's size > 0;
2641 if we're not at the first frag, then for sure
2642 the offset is > 0. */
2643 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2644 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2647 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2650 mapping_state_2 (state, 0);
2654 /* Same as mapping_state, but MAX_CHARS bytes have already been
2655 allocated. Put the mapping symbol that far back. */
2658 mapping_state_2 (enum mstate state, int max_chars)
2660 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2662 if (!SEG_NORMAL (now_seg))
2665 if (mapstate == state)
2666 /* The mapping symbol has already been emitted.
2667 There is nothing else to do. */
2670 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2671 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2674 #define mapping_state(x) ((void)0)
2675 #define mapping_state_2(x, y) ((void)0)
2678 /* Find the real, Thumb encoded start of a Thumb function. */
2682 find_real_start (symbolS * symbolP)
2685 const char * name = S_GET_NAME (symbolP);
2686 symbolS * new_target;
2688 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2689 #define STUB_NAME ".real_start_of"
2694 /* The compiler may generate BL instructions to local labels because
2695 it needs to perform a branch to a far away location. These labels
2696 do not have a corresponding ".real_start_of" label. We check
2697 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2698 the ".real_start_of" convention for nonlocal branches. */
2699 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2702 real_start = ACONCAT ((STUB_NAME, name, NULL));
2703 new_target = symbol_find (real_start);
2705 if (new_target == NULL)
2707 as_warn (_("Failed to find real start of function: %s\n"), name);
2708 new_target = symbolP;
2716 opcode_select (int width)
2723 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2724 as_bad (_("selected processor does not support THUMB opcodes"));
2727 /* No need to force the alignment, since we will have been
2728 coming from ARM mode, which is word-aligned. */
2729 record_alignment (now_seg, 1);
2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2737 as_bad (_("selected processor does not support ARM opcodes"));
2742 frag_align (2, 0, 0);
2744 record_alignment (now_seg, 1);
2749 as_bad (_("invalid instruction size selected (%d)"), width);
2754 s_arm (int ignore ATTRIBUTE_UNUSED)
2757 demand_empty_rest_of_line ();
2761 s_thumb (int ignore ATTRIBUTE_UNUSED)
2764 demand_empty_rest_of_line ();
2768 s_code (int unused ATTRIBUTE_UNUSED)
2772 temp = get_absolute_expression ();
2777 opcode_select (temp);
2781 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2786 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2788 /* If we are not already in thumb mode go into it, EVEN if
2789 the target processor does not support thumb instructions.
2790 This is used by gcc/config/arm/lib1funcs.asm for example
2791 to compile interworking support functions even if the
2792 target processor should not support interworking. */
2796 record_alignment (now_seg, 1);
2799 demand_empty_rest_of_line ();
2803 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2807 /* The following label is the name/address of the start of a Thumb function.
2808 We need to know this for the interworking support. */
2809 label_is_thumb_function_name = TRUE;
2812 /* Perform a .set directive, but also mark the alias as
2813 being a thumb function. */
2816 s_thumb_set (int equiv)
2818 /* XXX the following is a duplicate of the code for s_set() in read.c
2819 We cannot just call that code as we need to get at the symbol that
2826 /* Especial apologies for the random logic:
2827 This just grew, and could be parsed much more simply!
2829 name = input_line_pointer;
2830 delim = get_symbol_end ();
2831 end_name = input_line_pointer;
2834 if (*input_line_pointer != ',')
2837 as_bad (_("expected comma after name \"%s\""), name);
2839 ignore_rest_of_line ();
2843 input_line_pointer++;
2846 if (name[0] == '.' && name[1] == '\0')
2848 /* XXX - this should not happen to .thumb_set. */
2852 if ((symbolP = symbol_find (name)) == NULL
2853 && (symbolP = md_undefined_symbol (name)) == NULL)
2856 /* When doing symbol listings, play games with dummy fragments living
2857 outside the normal fragment chain to record the file and line info
2859 if (listing & LISTING_SYMBOLS)
2861 extern struct list_info_struct * listing_tail;
2862 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2864 memset (dummy_frag, 0, sizeof (fragS));
2865 dummy_frag->fr_type = rs_fill;
2866 dummy_frag->line = listing_tail;
2867 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2868 dummy_frag->fr_symbol = symbolP;
2872 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2875 /* "set" symbols are local unless otherwise specified. */
2876 SF_SET_LOCAL (symbolP);
2877 #endif /* OBJ_COFF */
2878 } /* Make a new symbol. */
2880 symbol_table_insert (symbolP);
2885 && S_IS_DEFINED (symbolP)
2886 && S_GET_SEGMENT (symbolP) != reg_section)
2887 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2889 pseudo_set (symbolP);
2891 demand_empty_rest_of_line ();
2893 /* XXX Now we come to the Thumb specific bit of code. */
2895 THUMB_SET_FUNC (symbolP, 1);
2896 ARM_SET_THUMB (symbolP, 1);
2897 #if defined OBJ_ELF || defined OBJ_COFF
2898 ARM_SET_INTERWORK (symbolP, support_interwork);
2902 /* Directives: Mode selection. */
2904 /* .syntax [unified|divided] - choose the new unified syntax
2905 (same for Arm and Thumb encoding, modulo slight differences in what
2906 can be represented) or the old divergent syntax for each mode. */
2908 s_syntax (int unused ATTRIBUTE_UNUSED)
2912 name = input_line_pointer;
2913 delim = get_symbol_end ();
2915 if (!strcasecmp (name, "unified"))
2916 unified_syntax = TRUE;
2917 else if (!strcasecmp (name, "divided"))
2918 unified_syntax = FALSE;
2921 as_bad (_("unrecognized syntax mode \"%s\""), name);
2924 *input_line_pointer = delim;
2925 demand_empty_rest_of_line ();
2928 /* Directives: sectioning and alignment. */
2930 /* Same as s_align_ptwo but align 0 => align 2. */
2933 s_align (int unused ATTRIBUTE_UNUSED)
2938 long max_alignment = 15;
2940 temp = get_absolute_expression ();
2941 if (temp > max_alignment)
2942 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2945 as_bad (_("alignment negative. 0 assumed."));
2949 if (*input_line_pointer == ',')
2951 input_line_pointer++;
2952 temp_fill = get_absolute_expression ();
2964 /* Only make a frag if we HAVE to. */
2965 if (temp && !need_pass_2)
2967 if (!fill_p && subseg_text_p (now_seg))
2968 frag_align_code (temp, 0);
2970 frag_align (temp, (int) temp_fill, 0);
2972 demand_empty_rest_of_line ();
2974 record_alignment (now_seg, temp);
2978 s_bss (int ignore ATTRIBUTE_UNUSED)
2980 /* We don't support putting frags in the BSS segment, we fake it by
2981 marking in_bss, then looking at s_skip for clues. */
2982 subseg_set (bss_section, 0);
2983 demand_empty_rest_of_line ();
2985 #ifdef md_elf_section_change_hook
2986 md_elf_section_change_hook ();
2991 s_even (int ignore ATTRIBUTE_UNUSED)
2993 /* Never make frag if expect extra pass. */
2995 frag_align (1, 0, 0);
2997 record_alignment (now_seg, 1);
2999 demand_empty_rest_of_line ();
3002 /* Directives: Literal pools. */
3004 static literal_pool *
3005 find_literal_pool (void)
3007 literal_pool * pool;
3009 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3011 if (pool->section == now_seg
3012 && pool->sub_section == now_subseg)
3019 static literal_pool *
3020 find_or_make_literal_pool (void)
3022 /* Next literal pool ID number. */
3023 static unsigned int latest_pool_num = 1;
3024 literal_pool * pool;
3026 pool = find_literal_pool ();
3030 /* Create a new pool. */
3031 pool = (literal_pool *) xmalloc (sizeof (* pool));
3035 pool->next_free_entry = 0;
3036 pool->section = now_seg;
3037 pool->sub_section = now_subseg;
3038 pool->next = list_of_pools;
3039 pool->symbol = NULL;
3041 /* Add it to the list. */
3042 list_of_pools = pool;
3045 /* New pools, and emptied pools, will have a NULL symbol. */
3046 if (pool->symbol == NULL)
3048 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3049 (valueT) 0, &zero_address_frag);
3050 pool->id = latest_pool_num ++;
3057 /* Add the literal in the global 'inst'
3058 structure to the relevant literal pool. */
3061 add_to_lit_pool (void)
3063 literal_pool * pool;
3066 pool = find_or_make_literal_pool ();
3068 /* Check if this literal value is already in the pool. */
3069 for (entry = 0; entry < pool->next_free_entry; entry ++)
3071 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3072 && (inst.reloc.exp.X_op == O_constant)
3073 && (pool->literals[entry].X_add_number
3074 == inst.reloc.exp.X_add_number)
3075 && (pool->literals[entry].X_unsigned
3076 == inst.reloc.exp.X_unsigned))
3079 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3080 && (inst.reloc.exp.X_op == O_symbol)
3081 && (pool->literals[entry].X_add_number
3082 == inst.reloc.exp.X_add_number)
3083 && (pool->literals[entry].X_add_symbol
3084 == inst.reloc.exp.X_add_symbol)
3085 && (pool->literals[entry].X_op_symbol
3086 == inst.reloc.exp.X_op_symbol))
3090 /* Do we need to create a new entry? */
3091 if (entry == pool->next_free_entry)
3093 if (entry >= MAX_LITERAL_POOL_SIZE)
3095 inst.error = _("literal pool overflow");
3099 pool->literals[entry] = inst.reloc.exp;
3101 /* PR ld/12974: Record the location of the first source line to reference
3102 this entry in the literal pool. If it turns out during linking that the
3103 symbol does not exist we will be able to give an accurate line number for
3104 the (first use of the) missing reference. */
3105 if (debug_type == DEBUG_DWARF2)
3106 dwarf2_where (pool->locs + entry);
3108 pool->next_free_entry += 1;
3111 inst.reloc.exp.X_op = O_symbol;
3112 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3113 inst.reloc.exp.X_add_symbol = pool->symbol;
3118 /* Can't use symbol_new here, so have to create a symbol and then at
3119 a later date assign it a value. Thats what these functions do. */
3122 symbol_locate (symbolS * symbolP,
3123 const char * name, /* It is copied, the caller can modify. */
3124 segT segment, /* Segment identifier (SEG_<something>). */
3125 valueT valu, /* Symbol value. */
3126 fragS * frag) /* Associated fragment. */
3128 unsigned int name_length;
3129 char * preserved_copy_of_name;
3131 name_length = strlen (name) + 1; /* +1 for \0. */
3132 obstack_grow (¬es, name, name_length);
3133 preserved_copy_of_name = (char *) obstack_finish (¬es);
3135 #ifdef tc_canonicalize_symbol_name
3136 preserved_copy_of_name =
3137 tc_canonicalize_symbol_name (preserved_copy_of_name);
3140 S_SET_NAME (symbolP, preserved_copy_of_name);
3142 S_SET_SEGMENT (symbolP, segment);
3143 S_SET_VALUE (symbolP, valu);
3144 symbol_clear_list_pointers (symbolP);
3146 symbol_set_frag (symbolP, frag);
3148 /* Link to end of symbol chain. */
3150 extern int symbol_table_frozen;
3152 if (symbol_table_frozen)
3156 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3158 obj_symbol_new_hook (symbolP);
3160 #ifdef tc_symbol_new_hook
3161 tc_symbol_new_hook (symbolP);
3165 verify_symbol_chain (symbol_rootP, symbol_lastP);
3166 #endif /* DEBUG_SYMS */
3171 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3174 literal_pool * pool;
3177 pool = find_literal_pool ();
3179 || pool->symbol == NULL
3180 || pool->next_free_entry == 0)
3183 mapping_state (MAP_DATA);
3185 /* Align pool as you have word accesses.
3186 Only make a frag if we have to. */
3188 frag_align (2, 0, 0);
3190 record_alignment (now_seg, 2);
3192 sprintf (sym_name, "$$lit_\002%x", pool->id);
3194 symbol_locate (pool->symbol, sym_name, now_seg,
3195 (valueT) frag_now_fix (), frag_now);
3196 symbol_table_insert (pool->symbol);
3198 ARM_SET_THUMB (pool->symbol, thumb_mode);
3200 #if defined OBJ_COFF || defined OBJ_ELF
3201 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3204 for (entry = 0; entry < pool->next_free_entry; entry ++)
3207 if (debug_type == DEBUG_DWARF2)
3208 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3210 /* First output the expression in the instruction to the pool. */
3211 emit_expr (&(pool->literals[entry]), 4); /* .word */
3214 /* Mark the pool as empty. */
3215 pool->next_free_entry = 0;
3216 pool->symbol = NULL;
3220 /* Forward declarations for functions below, in the MD interface
3222 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3223 static valueT create_unwind_entry (int);
3224 static void start_unwind_section (const segT, int);
3225 static void add_unwind_opcode (valueT, int);
3226 static void flush_pending_unwind (void);
3228 /* Directives: Data. */
3231 s_arm_elf_cons (int nbytes)
3235 #ifdef md_flush_pending_output
3236 md_flush_pending_output ();
3239 if (is_it_end_of_statement ())
3241 demand_empty_rest_of_line ();
3245 #ifdef md_cons_align
3246 md_cons_align (nbytes);
3249 mapping_state (MAP_DATA);
3253 char *base = input_line_pointer;
3257 if (exp.X_op != O_symbol)
3258 emit_expr (&exp, (unsigned int) nbytes);
3261 char *before_reloc = input_line_pointer;
3262 reloc = parse_reloc (&input_line_pointer);
3265 as_bad (_("unrecognized relocation suffix"));
3266 ignore_rest_of_line ();
3269 else if (reloc == BFD_RELOC_UNUSED)
3270 emit_expr (&exp, (unsigned int) nbytes);
3273 reloc_howto_type *howto = (reloc_howto_type *)
3274 bfd_reloc_type_lookup (stdoutput,
3275 (bfd_reloc_code_real_type) reloc);
3276 int size = bfd_get_reloc_size (howto);
3278 if (reloc == BFD_RELOC_ARM_PLT32)
3280 as_bad (_("(plt) is only valid on branch targets"));
3281 reloc = BFD_RELOC_UNUSED;
3286 as_bad (_("%s relocations do not fit in %d bytes"),
3287 howto->name, nbytes);
3290 /* We've parsed an expression stopping at O_symbol.
3291 But there may be more expression left now that we
3292 have parsed the relocation marker. Parse it again.
3293 XXX Surely there is a cleaner way to do this. */
3294 char *p = input_line_pointer;
3296 char *save_buf = (char *) alloca (input_line_pointer - base);
3297 memcpy (save_buf, base, input_line_pointer - base);
3298 memmove (base + (input_line_pointer - before_reloc),
3299 base, before_reloc - base);
3301 input_line_pointer = base + (input_line_pointer-before_reloc);
3303 memcpy (base, save_buf, p - base);
3305 offset = nbytes - size;
3306 p = frag_more ((int) nbytes);
3307 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3308 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3313 while (*input_line_pointer++ == ',');
3315 /* Put terminator back into stream. */
3316 input_line_pointer --;
3317 demand_empty_rest_of_line ();
3320 /* Emit an expression containing a 32-bit thumb instruction.
3321 Implementation based on put_thumb32_insn. */
3324 emit_thumb32_expr (expressionS * exp)
3326 expressionS exp_high = *exp;
3328 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3329 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3330 exp->X_add_number &= 0xffff;
3331 emit_expr (exp, (unsigned int) THUMB_SIZE);
3334 /* Guess the instruction size based on the opcode. */
3337 thumb_insn_size (int opcode)
3339 if ((unsigned int) opcode < 0xe800u)
3341 else if ((unsigned int) opcode >= 0xe8000000u)
3348 emit_insn (expressionS *exp, int nbytes)
3352 if (exp->X_op == O_constant)
3357 size = thumb_insn_size (exp->X_add_number);
3361 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3363 as_bad (_(".inst.n operand too big. "\
3364 "Use .inst.w instead"));
3369 if (now_it.state == AUTOMATIC_IT_BLOCK)
3370 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3372 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3374 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3375 emit_thumb32_expr (exp);
3377 emit_expr (exp, (unsigned int) size);
3379 it_fsm_post_encode ();
3383 as_bad (_("cannot determine Thumb instruction size. " \
3384 "Use .inst.n/.inst.w instead"));
3387 as_bad (_("constant expression required"));
3392 /* Like s_arm_elf_cons but do not use md_cons_align and
3393 set the mapping state to MAP_ARM/MAP_THUMB. */
3396 s_arm_elf_inst (int nbytes)
3398 if (is_it_end_of_statement ())
3400 demand_empty_rest_of_line ();
3404 /* Calling mapping_state () here will not change ARM/THUMB,
3405 but will ensure not to be in DATA state. */
3408 mapping_state (MAP_THUMB);
3413 as_bad (_("width suffixes are invalid in ARM mode"));
3414 ignore_rest_of_line ();
3420 mapping_state (MAP_ARM);
3429 if (! emit_insn (& exp, nbytes))
3431 ignore_rest_of_line ();
3435 while (*input_line_pointer++ == ',');
3437 /* Put terminator back into stream. */
3438 input_line_pointer --;
3439 demand_empty_rest_of_line ();
3442 /* Parse a .rel31 directive. */
3445 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3452 if (*input_line_pointer == '1')
3453 highbit = 0x80000000;
3454 else if (*input_line_pointer != '0')
3455 as_bad (_("expected 0 or 1"));
3457 input_line_pointer++;
3458 if (*input_line_pointer != ',')
3459 as_bad (_("missing comma"));
3460 input_line_pointer++;
3462 #ifdef md_flush_pending_output
3463 md_flush_pending_output ();
3466 #ifdef md_cons_align
3470 mapping_state (MAP_DATA);
3475 md_number_to_chars (p, highbit, 4);
3476 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3477 BFD_RELOC_ARM_PREL31);
3479 demand_empty_rest_of_line ();
3482 /* Directives: AEABI stack-unwind tables. */
3484 /* Parse an unwind_fnstart directive. Simply records the current location. */
3487 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3489 demand_empty_rest_of_line ();
3490 if (unwind.proc_start)
3492 as_bad (_("duplicate .fnstart directive"));
3496 /* Mark the start of the function. */
3497 unwind.proc_start = expr_build_dot ();
3499 /* Reset the rest of the unwind info. */
3500 unwind.opcode_count = 0;
3501 unwind.table_entry = NULL;
3502 unwind.personality_routine = NULL;
3503 unwind.personality_index = -1;
3504 unwind.frame_size = 0;
3505 unwind.fp_offset = 0;
3506 unwind.fp_reg = REG_SP;
3508 unwind.sp_restored = 0;
3512 /* Parse a handlerdata directive. Creates the exception handling table entry
3513 for the function. */
3516 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3518 demand_empty_rest_of_line ();
3519 if (!unwind.proc_start)
3520 as_bad (MISSING_FNSTART);
3522 if (unwind.table_entry)
3523 as_bad (_("duplicate .handlerdata directive"));
3525 create_unwind_entry (1);
3528 /* Parse an unwind_fnend directive. Generates the index table entry. */
3531 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3536 unsigned int marked_pr_dependency;
3538 demand_empty_rest_of_line ();
3540 if (!unwind.proc_start)
3542 as_bad (_(".fnend directive without .fnstart"));
3546 /* Add eh table entry. */
3547 if (unwind.table_entry == NULL)
3548 val = create_unwind_entry (0);
3552 /* Add index table entry. This is two words. */
3553 start_unwind_section (unwind.saved_seg, 1);
3554 frag_align (2, 0, 0);
3555 record_alignment (now_seg, 2);
3557 ptr = frag_more (8);
3559 where = frag_now_fix () - 8;
3561 /* Self relative offset of the function start. */
3562 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3563 BFD_RELOC_ARM_PREL31);
3565 /* Indicate dependency on EHABI-defined personality routines to the
3566 linker, if it hasn't been done already. */
3567 marked_pr_dependency
3568 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3569 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3570 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3572 static const char *const name[] =
3574 "__aeabi_unwind_cpp_pr0",
3575 "__aeabi_unwind_cpp_pr1",
3576 "__aeabi_unwind_cpp_pr2"
3578 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3579 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3580 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3581 |= 1 << unwind.personality_index;
3585 /* Inline exception table entry. */
3586 md_number_to_chars (ptr + 4, val, 4);
3588 /* Self relative offset of the table entry. */
3589 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3590 BFD_RELOC_ARM_PREL31);
3592 /* Restore the original section. */
3593 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3595 unwind.proc_start = NULL;
3599 /* Parse an unwind_cantunwind directive. */
3602 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3604 demand_empty_rest_of_line ();
3605 if (!unwind.proc_start)
3606 as_bad (MISSING_FNSTART);
3608 if (unwind.personality_routine || unwind.personality_index != -1)
3609 as_bad (_("personality routine specified for cantunwind frame"));
3611 unwind.personality_index = -2;
3615 /* Parse a personalityindex directive. */
3618 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3622 if (!unwind.proc_start)
3623 as_bad (MISSING_FNSTART);
3625 if (unwind.personality_routine || unwind.personality_index != -1)
3626 as_bad (_("duplicate .personalityindex directive"));
3630 if (exp.X_op != O_constant
3631 || exp.X_add_number < 0 || exp.X_add_number > 15)
3633 as_bad (_("bad personality routine number"));
3634 ignore_rest_of_line ();
3638 unwind.personality_index = exp.X_add_number;
3640 demand_empty_rest_of_line ();
3644 /* Parse a personality directive. */
3647 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3651 if (!unwind.proc_start)
3652 as_bad (MISSING_FNSTART);
3654 if (unwind.personality_routine || unwind.personality_index != -1)
3655 as_bad (_("duplicate .personality directive"));
3657 name = input_line_pointer;
3658 c = get_symbol_end ();
3659 p = input_line_pointer;
3660 unwind.personality_routine = symbol_find_or_make (name);
3662 demand_empty_rest_of_line ();
3666 /* Parse a directive saving core registers. */
3669 s_arm_unwind_save_core (void)
3675 range = parse_reg_list (&input_line_pointer);
3678 as_bad (_("expected register list"));
3679 ignore_rest_of_line ();
3683 demand_empty_rest_of_line ();
3685 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3686 into .unwind_save {..., sp...}. We aren't bothered about the value of
3687 ip because it is clobbered by calls. */
3688 if (unwind.sp_restored && unwind.fp_reg == 12
3689 && (range & 0x3000) == 0x1000)
3691 unwind.opcode_count--;
3692 unwind.sp_restored = 0;
3693 range = (range | 0x2000) & ~0x1000;
3694 unwind.pending_offset = 0;
3700 /* See if we can use the short opcodes. These pop a block of up to 8
3701 registers starting with r4, plus maybe r14. */
3702 for (n = 0; n < 8; n++)
3704 /* Break at the first non-saved register. */
3705 if ((range & (1 << (n + 4))) == 0)
3708 /* See if there are any other bits set. */
3709 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3711 /* Use the long form. */
3712 op = 0x8000 | ((range >> 4) & 0xfff);
3713 add_unwind_opcode (op, 2);
3717 /* Use the short form. */
3719 op = 0xa8; /* Pop r14. */
3721 op = 0xa0; /* Do not pop r14. */
3723 add_unwind_opcode (op, 1);
3730 op = 0xb100 | (range & 0xf);
3731 add_unwind_opcode (op, 2);
3734 /* Record the number of bytes pushed. */
3735 for (n = 0; n < 16; n++)
3737 if (range & (1 << n))
3738 unwind.frame_size += 4;
3743 /* Parse a directive saving FPA registers. */
3746 s_arm_unwind_save_fpa (int reg)
3752 /* Get Number of registers to transfer. */
3753 if (skip_past_comma (&input_line_pointer) != FAIL)
3756 exp.X_op = O_illegal;
3758 if (exp.X_op != O_constant)
3760 as_bad (_("expected , <constant>"));
3761 ignore_rest_of_line ();
3765 num_regs = exp.X_add_number;
3767 if (num_regs < 1 || num_regs > 4)
3769 as_bad (_("number of registers must be in the range [1:4]"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op = 0xb4 | (num_regs - 1);
3780 add_unwind_opcode (op, 1);
3785 op = 0xc800 | (reg << 4) | (num_regs - 1);
3786 add_unwind_opcode (op, 2);
3788 unwind.frame_size += num_regs * 12;
3792 /* Parse a directive saving VFP registers for ARMv6 and above. */
3795 s_arm_unwind_save_vfp_armv6 (void)
3800 int num_vfpv3_regs = 0;
3801 int num_regs_below_16;
3803 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3806 as_bad (_("expected register list"));
3807 ignore_rest_of_line ();
3811 demand_empty_rest_of_line ();
3813 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3814 than FSTMX/FLDMX-style ones). */
3816 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3818 num_vfpv3_regs = count;
3819 else if (start + count > 16)
3820 num_vfpv3_regs = start + count - 16;
3822 if (num_vfpv3_regs > 0)
3824 int start_offset = start > 16 ? start - 16 : 0;
3825 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3826 add_unwind_opcode (op, 2);
3829 /* Generate opcode for registers numbered in the range 0 .. 15. */
3830 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3831 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3832 if (num_regs_below_16 > 0)
3834 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3835 add_unwind_opcode (op, 2);
3838 unwind.frame_size += count * 8;
3842 /* Parse a directive saving VFP registers for pre-ARMv6. */
3845 s_arm_unwind_save_vfp (void)
3851 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3854 as_bad (_("expected register list"));
3855 ignore_rest_of_line ();
3859 demand_empty_rest_of_line ();
3864 op = 0xb8 | (count - 1);
3865 add_unwind_opcode (op, 1);
3870 op = 0xb300 | (reg << 4) | (count - 1);
3871 add_unwind_opcode (op, 2);
3873 unwind.frame_size += count * 8 + 4;
3877 /* Parse a directive saving iWMMXt data registers. */
3880 s_arm_unwind_save_mmxwr (void)
3888 if (*input_line_pointer == '{')
3889 input_line_pointer++;
3893 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3897 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3902 as_tsktsk (_("register list not in ascending order"));
3905 if (*input_line_pointer == '-')
3907 input_line_pointer++;
3908 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3911 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3914 else if (reg >= hi_reg)
3916 as_bad (_("bad register range"));
3919 for (; reg < hi_reg; reg++)
3923 while (skip_past_comma (&input_line_pointer) != FAIL);
3925 if (*input_line_pointer == '}')
3926 input_line_pointer++;
3928 demand_empty_rest_of_line ();
3930 /* Generate any deferred opcodes because we're going to be looking at
3932 flush_pending_unwind ();
3934 for (i = 0; i < 16; i++)
3936 if (mask & (1 << i))
3937 unwind.frame_size += 8;
3940 /* Attempt to combine with a previous opcode. We do this because gcc
3941 likes to output separate unwind directives for a single block of
3943 if (unwind.opcode_count > 0)
3945 i = unwind.opcodes[unwind.opcode_count - 1];
3946 if ((i & 0xf8) == 0xc0)
3949 /* Only merge if the blocks are contiguous. */
3952 if ((mask & 0xfe00) == (1 << 9))
3954 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3955 unwind.opcode_count--;
3958 else if (i == 6 && unwind.opcode_count >= 2)
3960 i = unwind.opcodes[unwind.opcode_count - 2];
3964 op = 0xffff << (reg - 1);
3966 && ((mask & op) == (1u << (reg - 1))))
3968 op = (1 << (reg + i + 1)) - 1;
3969 op &= ~((1 << reg) - 1);
3971 unwind.opcode_count -= 2;
3978 /* We want to generate opcodes in the order the registers have been
3979 saved, ie. descending order. */
3980 for (reg = 15; reg >= -1; reg--)
3982 /* Save registers in blocks. */
3984 || !(mask & (1 << reg)))
3986 /* We found an unsaved reg. Generate opcodes to save the
3993 op = 0xc0 | (hi_reg - 10);
3994 add_unwind_opcode (op, 1);
3999 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4000 add_unwind_opcode (op, 2);
4009 ignore_rest_of_line ();
4013 s_arm_unwind_save_mmxwcg (void)
4020 if (*input_line_pointer == '{')
4021 input_line_pointer++;
4025 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4029 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4035 as_tsktsk (_("register list not in ascending order"));
4038 if (*input_line_pointer == '-')
4040 input_line_pointer++;
4041 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4044 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4047 else if (reg >= hi_reg)
4049 as_bad (_("bad register range"));
4052 for (; reg < hi_reg; reg++)
4056 while (skip_past_comma (&input_line_pointer) != FAIL);
4058 if (*input_line_pointer == '}')
4059 input_line_pointer++;
4061 demand_empty_rest_of_line ();
4063 /* Generate any deferred opcodes because we're going to be looking at
4065 flush_pending_unwind ();
4067 for (reg = 0; reg < 16; reg++)
4069 if (mask & (1 << reg))
4070 unwind.frame_size += 4;
4073 add_unwind_opcode (op, 2);
4076 ignore_rest_of_line ();
4080 /* Parse an unwind_save directive.
4081 If the argument is non-zero, this is a .vsave directive. */
4084 s_arm_unwind_save (int arch_v6)
4087 struct reg_entry *reg;
4088 bfd_boolean had_brace = FALSE;
4090 if (!unwind.proc_start)
4091 as_bad (MISSING_FNSTART);
4093 /* Figure out what sort of save we have. */
4094 peek = input_line_pointer;
4102 reg = arm_reg_parse_multi (&peek);
4106 as_bad (_("register expected"));
4107 ignore_rest_of_line ();
4116 as_bad (_("FPA .unwind_save does not take a register list"));
4117 ignore_rest_of_line ();
4120 input_line_pointer = peek;
4121 s_arm_unwind_save_fpa (reg->number);
4124 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4127 s_arm_unwind_save_vfp_armv6 ();
4129 s_arm_unwind_save_vfp ();
4131 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4132 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4135 as_bad (_(".unwind_save does not support this kind of register"));
4136 ignore_rest_of_line ();
4141 /* Parse an unwind_movsp directive. */
4144 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4150 if (!unwind.proc_start)
4151 as_bad (MISSING_FNSTART);
4153 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4156 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4157 ignore_rest_of_line ();
4161 /* Optional constant. */
4162 if (skip_past_comma (&input_line_pointer) != FAIL)
4164 if (immediate_for_directive (&offset) == FAIL)
4170 demand_empty_rest_of_line ();
4172 if (reg == REG_SP || reg == REG_PC)
4174 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4178 if (unwind.fp_reg != REG_SP)
4179 as_bad (_("unexpected .unwind_movsp directive"));
4181 /* Generate opcode to restore the value. */
4183 add_unwind_opcode (op, 1);
4185 /* Record the information for later. */
4186 unwind.fp_reg = reg;
4187 unwind.fp_offset = unwind.frame_size - offset;
4188 unwind.sp_restored = 1;
4191 /* Parse an unwind_pad directive. */
4194 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4198 if (!unwind.proc_start)
4199 as_bad (MISSING_FNSTART);
4201 if (immediate_for_directive (&offset) == FAIL)
4206 as_bad (_("stack increment must be multiple of 4"));
4207 ignore_rest_of_line ();
4211 /* Don't generate any opcodes, just record the details for later. */
4212 unwind.frame_size += offset;
4213 unwind.pending_offset += offset;
4215 demand_empty_rest_of_line ();
4218 /* Parse an unwind_setfp directive. */
4221 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4227 if (!unwind.proc_start)
4228 as_bad (MISSING_FNSTART);
4230 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4231 if (skip_past_comma (&input_line_pointer) == FAIL)
4234 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4236 if (fp_reg == FAIL || sp_reg == FAIL)
4238 as_bad (_("expected <reg>, <reg>"));
4239 ignore_rest_of_line ();
4243 /* Optional constant. */
4244 if (skip_past_comma (&input_line_pointer) != FAIL)
4246 if (immediate_for_directive (&offset) == FAIL)
4252 demand_empty_rest_of_line ();
4254 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4256 as_bad (_("register must be either sp or set by a previous"
4257 "unwind_movsp directive"));
4261 /* Don't generate any opcodes, just record the information for later. */
4262 unwind.fp_reg = fp_reg;
4264 if (sp_reg == REG_SP)
4265 unwind.fp_offset = unwind.frame_size - offset;
4267 unwind.fp_offset -= offset;
4270 /* Parse an unwind_raw directive. */
4273 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4276 /* This is an arbitrary limit. */
4277 unsigned char op[16];
4280 if (!unwind.proc_start)
4281 as_bad (MISSING_FNSTART);
4284 if (exp.X_op == O_constant
4285 && skip_past_comma (&input_line_pointer) != FAIL)
4287 unwind.frame_size += exp.X_add_number;
4291 exp.X_op = O_illegal;
4293 if (exp.X_op != O_constant)
4295 as_bad (_("expected <offset>, <opcode>"));
4296 ignore_rest_of_line ();
4302 /* Parse the opcode. */
4307 as_bad (_("unwind opcode too long"));
4308 ignore_rest_of_line ();
4310 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4312 as_bad (_("invalid unwind opcode"));
4313 ignore_rest_of_line ();
4316 op[count++] = exp.X_add_number;
4318 /* Parse the next byte. */
4319 if (skip_past_comma (&input_line_pointer) == FAIL)
4325 /* Add the opcode bytes in reverse order. */
4327 add_unwind_opcode (op[count], 1);
4329 demand_empty_rest_of_line ();
4333 /* Parse a .eabi_attribute directive. */
4336 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4338 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4340 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4341 attributes_set_explicitly[tag] = 1;
4344 /* Emit a tls fix for the symbol. */
4347 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4351 #ifdef md_flush_pending_output
4352 md_flush_pending_output ();
4355 #ifdef md_cons_align
4359 /* Since we're just labelling the code, there's no need to define a
4362 p = obstack_next_free (&frchain_now->frch_obstack);
4363 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4364 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4365 : BFD_RELOC_ARM_TLS_DESCSEQ);
4367 #endif /* OBJ_ELF */
4369 static void s_arm_arch (int);
4370 static void s_arm_object_arch (int);
4371 static void s_arm_cpu (int);
4372 static void s_arm_fpu (int);
4373 static void s_arm_arch_extension (int);
4378 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4385 if (exp.X_op == O_symbol)
4386 exp.X_op = O_secrel;
4388 emit_expr (&exp, 4);
4390 while (*input_line_pointer++ == ',');
4392 input_line_pointer--;
4393 demand_empty_rest_of_line ();
4397 /* This table describes all the machine specific pseudo-ops the assembler
4398 has to support. The fields are:
4399 pseudo-op name without dot
4400 function to call to execute this pseudo-op
4401 Integer arg to pass to the function. */
4403 const pseudo_typeS md_pseudo_table[] =
4405 /* Never called because '.req' does not start a line. */
4406 { "req", s_req, 0 },
4407 /* Following two are likewise never called. */
4410 { "unreq", s_unreq, 0 },
4411 { "bss", s_bss, 0 },
4412 { "align", s_align, 0 },
4413 { "arm", s_arm, 0 },
4414 { "thumb", s_thumb, 0 },
4415 { "code", s_code, 0 },
4416 { "force_thumb", s_force_thumb, 0 },
4417 { "thumb_func", s_thumb_func, 0 },
4418 { "thumb_set", s_thumb_set, 0 },
4419 { "even", s_even, 0 },
4420 { "ltorg", s_ltorg, 0 },
4421 { "pool", s_ltorg, 0 },
4422 { "syntax", s_syntax, 0 },
4423 { "cpu", s_arm_cpu, 0 },
4424 { "arch", s_arm_arch, 0 },
4425 { "object_arch", s_arm_object_arch, 0 },
4426 { "fpu", s_arm_fpu, 0 },
4427 { "arch_extension", s_arm_arch_extension, 0 },
4429 { "word", s_arm_elf_cons, 4 },
4430 { "long", s_arm_elf_cons, 4 },
4431 { "inst.n", s_arm_elf_inst, 2 },
4432 { "inst.w", s_arm_elf_inst, 4 },
4433 { "inst", s_arm_elf_inst, 0 },
4434 { "rel31", s_arm_rel31, 0 },
4435 { "fnstart", s_arm_unwind_fnstart, 0 },
4436 { "fnend", s_arm_unwind_fnend, 0 },
4437 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4438 { "personality", s_arm_unwind_personality, 0 },
4439 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4440 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4441 { "save", s_arm_unwind_save, 0 },
4442 { "vsave", s_arm_unwind_save, 1 },
4443 { "movsp", s_arm_unwind_movsp, 0 },
4444 { "pad", s_arm_unwind_pad, 0 },
4445 { "setfp", s_arm_unwind_setfp, 0 },
4446 { "unwind_raw", s_arm_unwind_raw, 0 },
4447 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4448 { "tlsdescseq", s_arm_tls_descseq, 0 },
4452 /* These are used for dwarf. */
4456 /* These are used for dwarf2. */
4457 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4458 { "loc", dwarf2_directive_loc, 0 },
4459 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4461 { "extend", float_cons, 'x' },
4462 { "ldouble", float_cons, 'x' },
4463 { "packed", float_cons, 'p' },
4465 {"secrel32", pe_directive_secrel, 0},
4470 /* Parser functions used exclusively in instruction operands. */
4472 /* Generic immediate-value read function for use in insn parsing.
4473 STR points to the beginning of the immediate (the leading #);
4474 VAL receives the value; if the value is outside [MIN, MAX]
4475 issue an error. PREFIX_OPT is true if the immediate prefix is
4479 parse_immediate (char **str, int *val, int min, int max,
4480 bfd_boolean prefix_opt)
4483 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4484 if (exp.X_op != O_constant)
4486 inst.error = _("constant expression required");
4490 if (exp.X_add_number < min || exp.X_add_number > max)
4492 inst.error = _("immediate value out of range");
4496 *val = exp.X_add_number;
4500 /* Less-generic immediate-value read function with the possibility of loading a
4501 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4502 instructions. Puts the result directly in inst.operands[i]. */
4505 parse_big_immediate (char **str, int i)
4510 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4512 if (exp.X_op == O_constant)
4514 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4515 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4516 O_constant. We have to be careful not to break compilation for
4517 32-bit X_add_number, though. */
4518 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4520 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4521 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4522 inst.operands[i].regisimm = 1;
4525 else if (exp.X_op == O_big
4526 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4528 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4530 /* Bignums have their least significant bits in
4531 generic_bignum[0]. Make sure we put 32 bits in imm and
4532 32 bits in reg, in a (hopefully) portable way. */
4533 gas_assert (parts != 0);
4535 /* Make sure that the number is not too big.
4536 PR 11972: Bignums can now be sign-extended to the
4537 size of a .octa so check that the out of range bits
4538 are all zero or all one. */
4539 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4541 LITTLENUM_TYPE m = -1;
4543 if (generic_bignum[parts * 2] != 0
4544 && generic_bignum[parts * 2] != m)
4547 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4548 if (generic_bignum[j] != generic_bignum[j-1])
4552 inst.operands[i].imm = 0;
4553 for (j = 0; j < parts; j++, idx++)
4554 inst.operands[i].imm |= generic_bignum[idx]
4555 << (LITTLENUM_NUMBER_OF_BITS * j);
4556 inst.operands[i].reg = 0;
4557 for (j = 0; j < parts; j++, idx++)
4558 inst.operands[i].reg |= generic_bignum[idx]
4559 << (LITTLENUM_NUMBER_OF_BITS * j);
4560 inst.operands[i].regisimm = 1;
4570 /* Returns the pseudo-register number of an FPA immediate constant,
4571 or FAIL if there isn't a valid constant here. */
4574 parse_fpa_immediate (char ** str)
4576 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4582 /* First try and match exact strings, this is to guarantee
4583 that some formats will work even for cross assembly. */
4585 for (i = 0; fp_const[i]; i++)
4587 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4591 *str += strlen (fp_const[i]);
4592 if (is_end_of_line[(unsigned char) **str])
4598 /* Just because we didn't get a match doesn't mean that the constant
4599 isn't valid, just that it is in a format that we don't
4600 automatically recognize. Try parsing it with the standard
4601 expression routines. */
4603 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4605 /* Look for a raw floating point number. */
4606 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4607 && is_end_of_line[(unsigned char) *save_in])
4609 for (i = 0; i < NUM_FLOAT_VALS; i++)
4611 for (j = 0; j < MAX_LITTLENUMS; j++)
4613 if (words[j] != fp_values[i][j])
4617 if (j == MAX_LITTLENUMS)
4625 /* Try and parse a more complex expression, this will probably fail
4626 unless the code uses a floating point prefix (eg "0f"). */
4627 save_in = input_line_pointer;
4628 input_line_pointer = *str;
4629 if (expression (&exp) == absolute_section
4630 && exp.X_op == O_big
4631 && exp.X_add_number < 0)
4633 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4635 if (gen_to_words (words, 5, (long) 15) == 0)
4637 for (i = 0; i < NUM_FLOAT_VALS; i++)
4639 for (j = 0; j < MAX_LITTLENUMS; j++)
4641 if (words[j] != fp_values[i][j])
4645 if (j == MAX_LITTLENUMS)
4647 *str = input_line_pointer;
4648 input_line_pointer = save_in;
4655 *str = input_line_pointer;
4656 input_line_pointer = save_in;
4657 inst.error = _("invalid FPA immediate expression");
4661 /* Returns 1 if a number has "quarter-precision" float format
4662 0baBbbbbbc defgh000 00000000 00000000. */
4665 is_quarter_float (unsigned imm)
4667 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4668 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4671 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4672 0baBbbbbbc defgh000 00000000 00000000.
4673 The zero and minus-zero cases need special handling, since they can't be
4674 encoded in the "quarter-precision" float format, but can nonetheless be
4675 loaded as integer constants. */
4678 parse_qfloat_immediate (char **ccp, int *immed)
4682 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4683 int found_fpchar = 0;
4685 skip_past_char (&str, '#');
4687 /* We must not accidentally parse an integer as a floating-point number. Make
4688 sure that the value we parse is not an integer by checking for special
4689 characters '.' or 'e'.
4690 FIXME: This is a horrible hack, but doing better is tricky because type
4691 information isn't in a very usable state at parse time. */
4693 skip_whitespace (fpnum);
4695 if (strncmp (fpnum, "0x", 2) == 0)
4699 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4700 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4710 if ((str = atof_ieee (str, 's', words)) != NULL)
4712 unsigned fpword = 0;
4715 /* Our FP word must be 32 bits (single-precision FP). */
4716 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4718 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4722 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4735 /* Shift operands. */
4738 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4741 struct asm_shift_name
4744 enum shift_kind kind;
4747 /* Third argument to parse_shift. */
4748 enum parse_shift_mode
4750 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4751 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4752 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4753 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4754 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4757 /* Parse a <shift> specifier on an ARM data processing instruction.
4758 This has three forms:
4760 (LSL|LSR|ASL|ASR|ROR) Rs
4761 (LSL|LSR|ASL|ASR|ROR) #imm
4764 Note that ASL is assimilated to LSL in the instruction encoding, and
4765 RRX to ROR #0 (which cannot be written as such). */
4768 parse_shift (char **str, int i, enum parse_shift_mode mode)
4770 const struct asm_shift_name *shift_name;
4771 enum shift_kind shift;
4776 for (p = *str; ISALPHA (*p); p++)
4781 inst.error = _("shift expression expected");
4785 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4788 if (shift_name == NULL)
4790 inst.error = _("shift expression expected");
4794 shift = shift_name->kind;
4798 case NO_SHIFT_RESTRICT:
4799 case SHIFT_IMMEDIATE: break;
4801 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4802 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4804 inst.error = _("'LSL' or 'ASR' required");
4809 case SHIFT_LSL_IMMEDIATE:
4810 if (shift != SHIFT_LSL)
4812 inst.error = _("'LSL' required");
4817 case SHIFT_ASR_IMMEDIATE:
4818 if (shift != SHIFT_ASR)
4820 inst.error = _("'ASR' required");
4828 if (shift != SHIFT_RRX)
4830 /* Whitespace can appear here if the next thing is a bare digit. */
4831 skip_whitespace (p);
4833 if (mode == NO_SHIFT_RESTRICT
4834 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4836 inst.operands[i].imm = reg;
4837 inst.operands[i].immisreg = 1;
4839 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4842 inst.operands[i].shift_kind = shift;
4843 inst.operands[i].shifted = 1;
4848 /* Parse a <shifter_operand> for an ARM data processing instruction:
4851 #<immediate>, <rotate>
4855 where <shift> is defined by parse_shift above, and <rotate> is a
4856 multiple of 2 between 0 and 30. Validation of immediate operands
4857 is deferred to md_apply_fix. */
4860 parse_shifter_operand (char **str, int i)
4865 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4867 inst.operands[i].reg = value;
4868 inst.operands[i].isreg = 1;
4870 /* parse_shift will override this if appropriate */
4871 inst.reloc.exp.X_op = O_constant;
4872 inst.reloc.exp.X_add_number = 0;
4874 if (skip_past_comma (str) == FAIL)
4877 /* Shift operation on register. */
4878 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4881 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4884 if (skip_past_comma (str) == SUCCESS)
4886 /* #x, y -- ie explicit rotation by Y. */
4887 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4890 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4892 inst.error = _("constant expression expected");
4896 value = exp.X_add_number;
4897 if (value < 0 || value > 30 || value % 2 != 0)
4899 inst.error = _("invalid rotation");
4902 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4904 inst.error = _("invalid constant");
4908 /* Encode as specified. */
4909 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4913 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4914 inst.reloc.pc_rel = 0;
4918 /* Group relocation information. Each entry in the table contains the
4919 textual name of the relocation as may appear in assembler source
4920 and must end with a colon.
4921 Along with this textual name are the relocation codes to be used if
4922 the corresponding instruction is an ALU instruction (ADD or SUB only),
4923 an LDR, an LDRS, or an LDC. */
4925 struct group_reloc_table_entry
4936 /* Varieties of non-ALU group relocation. */
4943 static struct group_reloc_table_entry group_reloc_table[] =
4944 { /* Program counter relative: */
4946 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4951 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4952 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4953 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4954 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4956 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4962 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4963 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4964 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4967 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4968 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4969 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4970 /* Section base relative */
4972 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4977 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4978 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4979 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4980 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4982 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4987 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4988 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4989 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4990 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4992 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4993 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4994 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4995 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4997 /* Given the address of a pointer pointing to the textual name of a group
4998 relocation as may appear in assembler source, attempt to find its details
4999 in group_reloc_table. The pointer will be updated to the character after
5000 the trailing colon. On failure, FAIL will be returned; SUCCESS
5001 otherwise. On success, *entry will be updated to point at the relevant
5002 group_reloc_table entry. */
5005 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5008 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5010 int length = strlen (group_reloc_table[i].name);
5012 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5013 && (*str)[length] == ':')
5015 *out = &group_reloc_table[i];
5016 *str += (length + 1);
5024 /* Parse a <shifter_operand> for an ARM data processing instruction
5025 (as for parse_shifter_operand) where group relocations are allowed:
5028 #<immediate>, <rotate>
5029 #:<group_reloc>:<expression>
5033 where <group_reloc> is one of the strings defined in group_reloc_table.
5034 The hashes are optional.
5036 Everything else is as for parse_shifter_operand. */
5038 static parse_operand_result
5039 parse_shifter_operand_group_reloc (char **str, int i)
5041 /* Determine if we have the sequence of characters #: or just :
5042 coming next. If we do, then we check for a group relocation.
5043 If we don't, punt the whole lot to parse_shifter_operand. */
5045 if (((*str)[0] == '#' && (*str)[1] == ':')
5046 || (*str)[0] == ':')
5048 struct group_reloc_table_entry *entry;
5050 if ((*str)[0] == '#')
5055 /* Try to parse a group relocation. Anything else is an error. */
5056 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5058 inst.error = _("unknown group relocation");
5059 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5062 /* We now have the group relocation table entry corresponding to
5063 the name in the assembler source. Next, we parse the expression. */
5064 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5065 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5067 /* Record the relocation type (always the ALU variant here). */
5068 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5069 gas_assert (inst.reloc.type != 0);
5071 return PARSE_OPERAND_SUCCESS;
5074 return parse_shifter_operand (str, i) == SUCCESS
5075 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5077 /* Never reached. */
5080 /* Parse a Neon alignment expression. Information is written to
5081 inst.operands[i]. We assume the initial ':' has been skipped.
5083 align .imm = align << 8, .immisalign=1, .preind=0 */
5084 static parse_operand_result
5085 parse_neon_alignment (char **str, int i)
5090 my_get_expression (&exp, &p, GE_NO_PREFIX);
5092 if (exp.X_op != O_constant)
5094 inst.error = _("alignment must be constant");
5095 return PARSE_OPERAND_FAIL;
5098 inst.operands[i].imm = exp.X_add_number << 8;
5099 inst.operands[i].immisalign = 1;
5100 /* Alignments are not pre-indexes. */
5101 inst.operands[i].preind = 0;
5104 return PARSE_OPERAND_SUCCESS;
5107 /* Parse all forms of an ARM address expression. Information is written
5108 to inst.operands[i] and/or inst.reloc.
5110 Preindexed addressing (.preind=1):
5112 [Rn, #offset] .reg=Rn .reloc.exp=offset
5113 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5114 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 .shift_kind=shift .reloc.exp=shift_imm
5117 These three may have a trailing ! which causes .writeback to be set also.
5119 Postindexed addressing (.postind=1, .writeback=1):
5121 [Rn], #offset .reg=Rn .reloc.exp=offset
5122 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5123 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 .shift_kind=shift .reloc.exp=shift_imm
5126 Unindexed addressing (.preind=0, .postind=0):
5128 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5132 [Rn]{!} shorthand for [Rn,#0]{!}
5133 =immediate .isreg=0 .reloc.exp=immediate
5134 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5136 It is the caller's responsibility to check for addressing modes not
5137 supported by the instruction, and to set inst.reloc.type. */
5139 static parse_operand_result
5140 parse_address_main (char **str, int i, int group_relocations,
5141 group_reloc_type group_type)
5146 if (skip_past_char (&p, '[') == FAIL)
5148 if (skip_past_char (&p, '=') == FAIL)
5150 /* Bare address - translate to PC-relative offset. */
5151 inst.reloc.pc_rel = 1;
5152 inst.operands[i].reg = REG_PC;
5153 inst.operands[i].isreg = 1;
5154 inst.operands[i].preind = 1;
5156 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5158 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5159 return PARSE_OPERAND_FAIL;
5162 return PARSE_OPERAND_SUCCESS;
5165 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5167 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5168 return PARSE_OPERAND_FAIL;
5170 inst.operands[i].reg = reg;
5171 inst.operands[i].isreg = 1;
5173 if (skip_past_comma (&p) == SUCCESS)
5175 inst.operands[i].preind = 1;
5178 else if (*p == '-') p++, inst.operands[i].negative = 1;
5180 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5182 inst.operands[i].imm = reg;
5183 inst.operands[i].immisreg = 1;
5185 if (skip_past_comma (&p) == SUCCESS)
5186 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5187 return PARSE_OPERAND_FAIL;
5189 else if (skip_past_char (&p, ':') == SUCCESS)
5191 /* FIXME: '@' should be used here, but it's filtered out by generic
5192 code before we get to see it here. This may be subject to
5194 parse_operand_result result = parse_neon_alignment (&p, i);
5196 if (result != PARSE_OPERAND_SUCCESS)
5201 if (inst.operands[i].negative)
5203 inst.operands[i].negative = 0;
5207 if (group_relocations
5208 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5210 struct group_reloc_table_entry *entry;
5212 /* Skip over the #: or : sequence. */
5218 /* Try to parse a group relocation. Anything else is an
5220 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5222 inst.error = _("unknown group relocation");
5223 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5226 /* We now have the group relocation table entry corresponding to
5227 the name in the assembler source. Next, we parse the
5229 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5230 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5232 /* Record the relocation type. */
5236 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5240 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5244 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5251 if (inst.reloc.type == 0)
5253 inst.error = _("this group relocation is not allowed on this instruction");
5254 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5260 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5261 return PARSE_OPERAND_FAIL;
5262 /* If the offset is 0, find out if it's a +0 or -0. */
5263 if (inst.reloc.exp.X_op == O_constant
5264 && inst.reloc.exp.X_add_number == 0)
5266 skip_whitespace (q);
5270 skip_whitespace (q);
5273 inst.operands[i].negative = 1;
5278 else if (skip_past_char (&p, ':') == SUCCESS)
5280 /* FIXME: '@' should be used here, but it's filtered out by generic code
5281 before we get to see it here. This may be subject to change. */
5282 parse_operand_result result = parse_neon_alignment (&p, i);
5284 if (result != PARSE_OPERAND_SUCCESS)
5288 if (skip_past_char (&p, ']') == FAIL)
5290 inst.error = _("']' expected");
5291 return PARSE_OPERAND_FAIL;
5294 if (skip_past_char (&p, '!') == SUCCESS)
5295 inst.operands[i].writeback = 1;
5297 else if (skip_past_comma (&p) == SUCCESS)
5299 if (skip_past_char (&p, '{') == SUCCESS)
5301 /* [Rn], {expr} - unindexed, with option */
5302 if (parse_immediate (&p, &inst.operands[i].imm,
5303 0, 255, TRUE) == FAIL)
5304 return PARSE_OPERAND_FAIL;
5306 if (skip_past_char (&p, '}') == FAIL)
5308 inst.error = _("'}' expected at end of 'option' field");
5309 return PARSE_OPERAND_FAIL;
5311 if (inst.operands[i].preind)
5313 inst.error = _("cannot combine index with option");
5314 return PARSE_OPERAND_FAIL;
5317 return PARSE_OPERAND_SUCCESS;
5321 inst.operands[i].postind = 1;
5322 inst.operands[i].writeback = 1;
5324 if (inst.operands[i].preind)
5326 inst.error = _("cannot combine pre- and post-indexing");
5327 return PARSE_OPERAND_FAIL;
5331 else if (*p == '-') p++, inst.operands[i].negative = 1;
5333 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5335 /* We might be using the immediate for alignment already. If we
5336 are, OR the register number into the low-order bits. */
5337 if (inst.operands[i].immisalign)
5338 inst.operands[i].imm |= reg;
5340 inst.operands[i].imm = reg;
5341 inst.operands[i].immisreg = 1;
5343 if (skip_past_comma (&p) == SUCCESS)
5344 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5345 return PARSE_OPERAND_FAIL;
5350 if (inst.operands[i].negative)
5352 inst.operands[i].negative = 0;
5355 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5356 return PARSE_OPERAND_FAIL;
5357 /* If the offset is 0, find out if it's a +0 or -0. */
5358 if (inst.reloc.exp.X_op == O_constant
5359 && inst.reloc.exp.X_add_number == 0)
5361 skip_whitespace (q);
5365 skip_whitespace (q);
5368 inst.operands[i].negative = 1;
5374 /* If at this point neither .preind nor .postind is set, we have a
5375 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5376 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5378 inst.operands[i].preind = 1;
5379 inst.reloc.exp.X_op = O_constant;
5380 inst.reloc.exp.X_add_number = 0;
5383 return PARSE_OPERAND_SUCCESS;
5387 parse_address (char **str, int i)
5389 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5393 static parse_operand_result
5394 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5396 return parse_address_main (str, i, 1, type);
5399 /* Parse an operand for a MOVW or MOVT instruction. */
5401 parse_half (char **str)
5406 skip_past_char (&p, '#');
5407 if (strncasecmp (p, ":lower16:", 9) == 0)
5408 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5409 else if (strncasecmp (p, ":upper16:", 9) == 0)
5410 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5412 if (inst.reloc.type != BFD_RELOC_UNUSED)
5415 skip_whitespace (p);
5418 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5421 if (inst.reloc.type == BFD_RELOC_UNUSED)
5423 if (inst.reloc.exp.X_op != O_constant)
5425 inst.error = _("constant expression expected");
5428 if (inst.reloc.exp.X_add_number < 0
5429 || inst.reloc.exp.X_add_number > 0xffff)
5431 inst.error = _("immediate value out of range");
5439 /* Miscellaneous. */
5441 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5442 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5444 parse_psr (char **str, bfd_boolean lhs)
5447 unsigned long psr_field;
5448 const struct asm_psr *psr;
5450 bfd_boolean is_apsr = FALSE;
5451 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5453 /* PR gas/12698: If the user has specified -march=all then m_profile will
5454 be TRUE, but we want to ignore it in this case as we are building for any
5455 CPU type, including non-m variants. */
5456 if (selected_cpu.core == arm_arch_any.core)
5459 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5460 feature for ease of use and backwards compatibility. */
5462 if (strncasecmp (p, "SPSR", 4) == 0)
5465 goto unsupported_psr;
5467 psr_field = SPSR_BIT;
5469 else if (strncasecmp (p, "CPSR", 4) == 0)
5472 goto unsupported_psr;
5476 else if (strncasecmp (p, "APSR", 4) == 0)
5478 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5479 and ARMv7-R architecture CPUs. */
5488 while (ISALNUM (*p) || *p == '_');
5490 if (strncasecmp (start, "iapsr", 5) == 0
5491 || strncasecmp (start, "eapsr", 5) == 0
5492 || strncasecmp (start, "xpsr", 4) == 0
5493 || strncasecmp (start, "psr", 3) == 0)
5494 p = start + strcspn (start, "rR") + 1;
5496 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5502 /* If APSR is being written, a bitfield may be specified. Note that
5503 APSR itself is handled above. */
5504 if (psr->field <= 3)
5506 psr_field = psr->field;
5512 /* M-profile MSR instructions have the mask field set to "10", except
5513 *PSR variants which modify APSR, which may use a different mask (and
5514 have been handled already). Do that by setting the PSR_f field
5516 return psr->field | (lhs ? PSR_f : 0);
5519 goto unsupported_psr;
5525 /* A suffix follows. */
5531 while (ISALNUM (*p) || *p == '_');
5535 /* APSR uses a notation for bits, rather than fields. */
5536 unsigned int nzcvq_bits = 0;
5537 unsigned int g_bit = 0;
5540 for (bit = start; bit != p; bit++)
5542 switch (TOLOWER (*bit))
5545 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5549 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5553 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5557 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5561 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5565 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5569 inst.error = _("unexpected bit specified after APSR");
5574 if (nzcvq_bits == 0x1f)
5579 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5581 inst.error = _("selected processor does not "
5582 "support DSP extension");
5589 if ((nzcvq_bits & 0x20) != 0
5590 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5591 || (g_bit & 0x2) != 0)
5593 inst.error = _("bad bitmask specified after APSR");
5599 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5604 psr_field |= psr->field;
5610 goto error; /* Garbage after "[CS]PSR". */
5612 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5613 is deprecated, but allow it anyway. */
5617 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5620 else if (!m_profile)
5621 /* These bits are never right for M-profile devices: don't set them
5622 (only code paths which read/write APSR reach here). */
5623 psr_field |= (PSR_c | PSR_f);
5629 inst.error = _("selected processor does not support requested special "
5630 "purpose register");
5634 inst.error = _("flag for {c}psr instruction expected");
5638 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5639 value suitable for splatting into the AIF field of the instruction. */
5642 parse_cps_flags (char **str)
5651 case '\0': case ',':
5654 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5655 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5656 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5659 inst.error = _("unrecognized CPS flag");
5664 if (saw_a_flag == 0)
5666 inst.error = _("missing CPS flags");
5674 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5675 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5678 parse_endian_specifier (char **str)
5683 if (strncasecmp (s, "BE", 2))
5685 else if (strncasecmp (s, "LE", 2))
5689 inst.error = _("valid endian specifiers are be or le");
5693 if (ISALNUM (s[2]) || s[2] == '_')
5695 inst.error = _("valid endian specifiers are be or le");
5700 return little_endian;
5703 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5704 value suitable for poking into the rotate field of an sxt or sxta
5705 instruction, or FAIL on error. */
5708 parse_ror (char **str)
5713 if (strncasecmp (s, "ROR", 3) == 0)
5717 inst.error = _("missing rotation field after comma");
5721 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5726 case 0: *str = s; return 0x0;
5727 case 8: *str = s; return 0x1;
5728 case 16: *str = s; return 0x2;
5729 case 24: *str = s; return 0x3;
5732 inst.error = _("rotation can only be 0, 8, 16, or 24");
5737 /* Parse a conditional code (from conds[] below). The value returned is in the
5738 range 0 .. 14, or FAIL. */
5740 parse_cond (char **str)
5743 const struct asm_cond *c;
5745 /* Condition codes are always 2 characters, so matching up to
5746 3 characters is sufficient. */
5751 while (ISALPHA (*q) && n < 3)
5753 cond[n] = TOLOWER (*q);
5758 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5761 inst.error = _("condition required");
5769 /* Parse an option for a barrier instruction. Returns the encoding for the
5772 parse_barrier (char **str)
5775 const struct asm_barrier_opt *o;
5778 while (ISALPHA (*q))
5781 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5790 /* Parse the operands of a table branch instruction. Similar to a memory
5793 parse_tb (char **str)
5798 if (skip_past_char (&p, '[') == FAIL)
5800 inst.error = _("'[' expected");
5804 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5806 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5809 inst.operands[0].reg = reg;
5811 if (skip_past_comma (&p) == FAIL)
5813 inst.error = _("',' expected");
5817 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5819 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5822 inst.operands[0].imm = reg;
5824 if (skip_past_comma (&p) == SUCCESS)
5826 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5828 if (inst.reloc.exp.X_add_number != 1)
5830 inst.error = _("invalid shift");
5833 inst.operands[0].shifted = 1;
5836 if (skip_past_char (&p, ']') == FAIL)
5838 inst.error = _("']' expected");
5845 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5846 information on the types the operands can take and how they are encoded.
5847 Up to four operands may be read; this function handles setting the
5848 ".present" field for each read operand itself.
5849 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5850 else returns FAIL. */
5853 parse_neon_mov (char **str, int *which_operand)
5855 int i = *which_operand, val;
5856 enum arm_reg_type rtype;
5858 struct neon_type_el optype;
5860 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5862 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5863 inst.operands[i].reg = val;
5864 inst.operands[i].isscalar = 1;
5865 inst.operands[i].vectype = optype;
5866 inst.operands[i++].present = 1;
5868 if (skip_past_comma (&ptr) == FAIL)
5871 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5874 inst.operands[i].reg = val;
5875 inst.operands[i].isreg = 1;
5876 inst.operands[i].present = 1;
5878 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5881 /* Cases 0, 1, 2, 3, 5 (D only). */
5882 if (skip_past_comma (&ptr) == FAIL)
5885 inst.operands[i].reg = val;
5886 inst.operands[i].isreg = 1;
5887 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5888 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5889 inst.operands[i].isvec = 1;
5890 inst.operands[i].vectype = optype;
5891 inst.operands[i++].present = 1;
5893 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5895 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5896 Case 13: VMOV <Sd>, <Rm> */
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5901 if (rtype == REG_TYPE_NQ)
5903 first_error (_("can't use Neon quad register here"));
5906 else if (rtype != REG_TYPE_VFS)
5909 if (skip_past_comma (&ptr) == FAIL)
5911 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5913 inst.operands[i].reg = val;
5914 inst.operands[i].isreg = 1;
5915 inst.operands[i].present = 1;
5918 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5921 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5922 Case 1: VMOV<c><q> <Dd>, <Dm>
5923 Case 8: VMOV.F32 <Sd>, <Sm>
5924 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5926 inst.operands[i].reg = val;
5927 inst.operands[i].isreg = 1;
5928 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5929 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5930 inst.operands[i].isvec = 1;
5931 inst.operands[i].vectype = optype;
5932 inst.operands[i].present = 1;
5934 if (skip_past_comma (&ptr) == SUCCESS)
5939 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5942 inst.operands[i].reg = val;
5943 inst.operands[i].isreg = 1;
5944 inst.operands[i++].present = 1;
5946 if (skip_past_comma (&ptr) == FAIL)
5949 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5952 inst.operands[i].reg = val;
5953 inst.operands[i].isreg = 1;
5954 inst.operands[i].present = 1;
5957 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5958 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5959 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5960 Case 10: VMOV.F32 <Sd>, #<imm>
5961 Case 11: VMOV.F64 <Dd>, #<imm> */
5962 inst.operands[i].immisfloat = 1;
5963 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5964 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5965 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5969 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5973 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5976 inst.operands[i].reg = val;
5977 inst.operands[i].isreg = 1;
5978 inst.operands[i++].present = 1;
5980 if (skip_past_comma (&ptr) == FAIL)
5983 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5985 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5986 inst.operands[i].reg = val;
5987 inst.operands[i].isscalar = 1;
5988 inst.operands[i].present = 1;
5989 inst.operands[i].vectype = optype;
5991 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5993 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5994 inst.operands[i].reg = val;
5995 inst.operands[i].isreg = 1;
5996 inst.operands[i++].present = 1;
5998 if (skip_past_comma (&ptr) == FAIL)
6001 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6004 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6008 inst.operands[i].reg = val;
6009 inst.operands[i].isreg = 1;
6010 inst.operands[i].isvec = 1;
6011 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6012 inst.operands[i].vectype = optype;
6013 inst.operands[i].present = 1;
6015 if (rtype == REG_TYPE_VFS)
6019 if (skip_past_comma (&ptr) == FAIL)
6021 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6024 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6027 inst.operands[i].reg = val;
6028 inst.operands[i].isreg = 1;
6029 inst.operands[i].isvec = 1;
6030 inst.operands[i].issingle = 1;
6031 inst.operands[i].vectype = optype;
6032 inst.operands[i].present = 1;
6035 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6039 inst.operands[i].reg = val;
6040 inst.operands[i].isreg = 1;
6041 inst.operands[i].isvec = 1;
6042 inst.operands[i].issingle = 1;
6043 inst.operands[i].vectype = optype;
6044 inst.operands[i].present = 1;
6049 first_error (_("parse error"));
6053 /* Successfully parsed the operands. Update args. */
6059 first_error (_("expected comma"));
6063 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6067 /* Use this macro when the operand constraints are different
6068 for ARM and THUMB (e.g. ldrd). */
6069 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6070 ((arm_operand) | ((thumb_operand) << 16))
6072 /* Matcher codes for parse_operands. */
6073 enum operand_parse_code
6075 OP_stop, /* end of line */
6077 OP_RR, /* ARM register */
6078 OP_RRnpc, /* ARM register, not r15 */
6079 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6080 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6081 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6082 optional trailing ! */
6083 OP_RRw, /* ARM register, not r15, optional trailing ! */
6084 OP_RCP, /* Coprocessor number */
6085 OP_RCN, /* Coprocessor register */
6086 OP_RF, /* FPA register */
6087 OP_RVS, /* VFP single precision register */
6088 OP_RVD, /* VFP double precision register (0..15) */
6089 OP_RND, /* Neon double precision register (0..31) */
6090 OP_RNQ, /* Neon quad precision register */
6091 OP_RVSD, /* VFP single or double precision register */
6092 OP_RNDQ, /* Neon double or quad precision register */
6093 OP_RNSDQ, /* Neon single, double or quad precision register */
6094 OP_RNSC, /* Neon scalar D[X] */
6095 OP_RVC, /* VFP control register */
6096 OP_RMF, /* Maverick F register */
6097 OP_RMD, /* Maverick D register */
6098 OP_RMFX, /* Maverick FX register */
6099 OP_RMDX, /* Maverick DX register */
6100 OP_RMAX, /* Maverick AX register */
6101 OP_RMDS, /* Maverick DSPSC register */
6102 OP_RIWR, /* iWMMXt wR register */
6103 OP_RIWC, /* iWMMXt wC register */
6104 OP_RIWG, /* iWMMXt wCG register */
6105 OP_RXA, /* XScale accumulator register */
6107 OP_REGLST, /* ARM register list */
6108 OP_VRSLST, /* VFP single-precision register list */
6109 OP_VRDLST, /* VFP double-precision register list */
6110 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6111 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6112 OP_NSTRLST, /* Neon element/structure list */
6114 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6115 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6116 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6117 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6118 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6119 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6120 OP_VMOV, /* Neon VMOV operands. */
6121 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6122 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6123 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6125 OP_I0, /* immediate zero */
6126 OP_I7, /* immediate value 0 .. 7 */
6127 OP_I15, /* 0 .. 15 */
6128 OP_I16, /* 1 .. 16 */
6129 OP_I16z, /* 0 .. 16 */
6130 OP_I31, /* 0 .. 31 */
6131 OP_I31w, /* 0 .. 31, optional trailing ! */
6132 OP_I32, /* 1 .. 32 */
6133 OP_I32z, /* 0 .. 32 */
6134 OP_I63, /* 0 .. 63 */
6135 OP_I63s, /* -64 .. 63 */
6136 OP_I64, /* 1 .. 64 */
6137 OP_I64z, /* 0 .. 64 */
6138 OP_I255, /* 0 .. 255 */
6140 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6141 OP_I7b, /* 0 .. 7 */
6142 OP_I15b, /* 0 .. 15 */
6143 OP_I31b, /* 0 .. 31 */
6145 OP_SH, /* shifter operand */
6146 OP_SHG, /* shifter operand with possible group relocation */
6147 OP_ADDR, /* Memory address expression (any mode) */
6148 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6149 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6150 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6151 OP_EXP, /* arbitrary expression */
6152 OP_EXPi, /* same, with optional immediate prefix */
6153 OP_EXPr, /* same, with optional relocation suffix */
6154 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6156 OP_CPSF, /* CPS flags */
6157 OP_ENDI, /* Endianness specifier */
6158 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6159 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6160 OP_COND, /* conditional code */
6161 OP_TB, /* Table branch. */
6163 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6165 OP_RRnpc_I0, /* ARM register or literal 0 */
6166 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6167 OP_RR_EXi, /* ARM register or expression with imm prefix */
6168 OP_RF_IF, /* FPA register or immediate */
6169 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6170 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6172 /* Optional operands. */
6173 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6174 OP_oI31b, /* 0 .. 31 */
6175 OP_oI32b, /* 1 .. 32 */
6176 OP_oI32z, /* 0 .. 32 */
6177 OP_oIffffb, /* 0 .. 65535 */
6178 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6180 OP_oRR, /* ARM register */
6181 OP_oRRnpc, /* ARM register, not the PC */
6182 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6183 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6184 OP_oRND, /* Optional Neon double precision register */
6185 OP_oRNQ, /* Optional Neon quad precision register */
6186 OP_oRNDQ, /* Optional Neon double or quad precision register */
6187 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6188 OP_oSHll, /* LSL immediate */
6189 OP_oSHar, /* ASR immediate */
6190 OP_oSHllar, /* LSL or ASR immediate */
6191 OP_oROR, /* ROR 0/8/16/24 */
6192 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6194 /* Some pre-defined mixed (ARM/THUMB) operands. */
6195 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6196 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6197 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6199 OP_FIRST_OPTIONAL = OP_oI7b
6202 /* Generic instruction operand parser. This does no encoding and no
6203 semantic validation; it merely squirrels values away in the inst
6204 structure. Returns SUCCESS or FAIL depending on whether the
6205 specified grammar matched. */
6207 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6209 unsigned const int *upat = pattern;
6210 char *backtrack_pos = 0;
6211 const char *backtrack_error = 0;
6212 int i, val = 0, backtrack_index = 0;
6213 enum arm_reg_type rtype;
6214 parse_operand_result result;
6215 unsigned int op_parse_code;
6217 #define po_char_or_fail(chr) \
6220 if (skip_past_char (&str, chr) == FAIL) \
6225 #define po_reg_or_fail(regtype) \
6228 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6229 & inst.operands[i].vectype); \
6232 first_error (_(reg_expected_msgs[regtype])); \
6235 inst.operands[i].reg = val; \
6236 inst.operands[i].isreg = 1; \
6237 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6238 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6239 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6240 || rtype == REG_TYPE_VFD \
6241 || rtype == REG_TYPE_NQ); \
6245 #define po_reg_or_goto(regtype, label) \
6248 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6249 & inst.operands[i].vectype); \
6253 inst.operands[i].reg = val; \
6254 inst.operands[i].isreg = 1; \
6255 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6256 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6257 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6258 || rtype == REG_TYPE_VFD \
6259 || rtype == REG_TYPE_NQ); \
6263 #define po_imm_or_fail(min, max, popt) \
6266 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6268 inst.operands[i].imm = val; \
6272 #define po_scalar_or_goto(elsz, label) \
6275 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6278 inst.operands[i].reg = val; \
6279 inst.operands[i].isscalar = 1; \
6283 #define po_misc_or_fail(expr) \
6291 #define po_misc_or_fail_no_backtrack(expr) \
6295 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6296 backtrack_pos = 0; \
6297 if (result != PARSE_OPERAND_SUCCESS) \
6302 #define po_barrier_or_imm(str) \
6305 val = parse_barrier (&str); \
6308 if (ISALPHA (*str)) \
6315 if ((inst.instruction & 0xf0) == 0x60 \
6318 /* ISB can only take SY as an option. */ \
6319 inst.error = _("invalid barrier type"); \
6326 skip_whitespace (str);
6328 for (i = 0; upat[i] != OP_stop; i++)
6330 op_parse_code = upat[i];
6331 if (op_parse_code >= 1<<16)
6332 op_parse_code = thumb ? (op_parse_code >> 16)
6333 : (op_parse_code & ((1<<16)-1));
6335 if (op_parse_code >= OP_FIRST_OPTIONAL)
6337 /* Remember where we are in case we need to backtrack. */
6338 gas_assert (!backtrack_pos);
6339 backtrack_pos = str;
6340 backtrack_error = inst.error;
6341 backtrack_index = i;
6344 if (i > 0 && (i > 1 || inst.operands[0].present))
6345 po_char_or_fail (',');
6347 switch (op_parse_code)
6355 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6356 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6357 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6358 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6359 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6360 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6362 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6364 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6366 /* Also accept generic coprocessor regs for unknown registers. */
6368 po_reg_or_fail (REG_TYPE_CN);
6370 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6371 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6372 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6373 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6374 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6375 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6376 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6377 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6378 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6379 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6381 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6383 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6384 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6386 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6388 /* Neon scalar. Using an element size of 8 means that some invalid
6389 scalars are accepted here, so deal with those in later code. */
6390 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6394 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6397 po_imm_or_fail (0, 0, TRUE);
6402 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6407 po_scalar_or_goto (8, try_rr);
6410 po_reg_or_fail (REG_TYPE_RN);
6416 po_scalar_or_goto (8, try_nsdq);
6419 po_reg_or_fail (REG_TYPE_NSDQ);
6425 po_scalar_or_goto (8, try_ndq);
6428 po_reg_or_fail (REG_TYPE_NDQ);
6434 po_scalar_or_goto (8, try_vfd);
6437 po_reg_or_fail (REG_TYPE_VFD);
6442 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6443 not careful then bad things might happen. */
6444 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6449 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6452 /* There's a possibility of getting a 64-bit immediate here, so
6453 we need special handling. */
6454 if (parse_big_immediate (&str, i) == FAIL)
6456 inst.error = _("immediate value is out of range");
6464 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6467 po_imm_or_fail (0, 63, TRUE);
6472 po_char_or_fail ('[');
6473 po_reg_or_fail (REG_TYPE_RN);
6474 po_char_or_fail (']');
6480 po_reg_or_fail (REG_TYPE_RN);
6481 if (skip_past_char (&str, '!') == SUCCESS)
6482 inst.operands[i].writeback = 1;
6486 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6487 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6488 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6489 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6490 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6491 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6492 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6493 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6494 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6495 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6496 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6497 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6499 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6501 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6502 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6504 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6505 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6506 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6507 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6509 /* Immediate variants */
6511 po_char_or_fail ('{');
6512 po_imm_or_fail (0, 255, TRUE);
6513 po_char_or_fail ('}');
6517 /* The expression parser chokes on a trailing !, so we have
6518 to find it first and zap it. */
6521 while (*s && *s != ',')
6526 inst.operands[i].writeback = 1;
6528 po_imm_or_fail (0, 31, TRUE);
6536 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6541 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6546 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6548 if (inst.reloc.exp.X_op == O_symbol)
6550 val = parse_reloc (&str);
6553 inst.error = _("unrecognized relocation suffix");
6556 else if (val != BFD_RELOC_UNUSED)
6558 inst.operands[i].imm = val;
6559 inst.operands[i].hasreloc = 1;
6564 /* Operand for MOVW or MOVT. */
6566 po_misc_or_fail (parse_half (&str));
6569 /* Register or expression. */
6570 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6571 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6573 /* Register or immediate. */
6574 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6575 I0: po_imm_or_fail (0, 0, FALSE); break;
6577 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6579 if (!is_immediate_prefix (*str))
6582 val = parse_fpa_immediate (&str);
6585 /* FPA immediates are encoded as registers 8-15.
6586 parse_fpa_immediate has already applied the offset. */
6587 inst.operands[i].reg = val;
6588 inst.operands[i].isreg = 1;
6591 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6592 I32z: po_imm_or_fail (0, 32, FALSE); break;
6594 /* Two kinds of register. */
6597 struct reg_entry *rege = arm_reg_parse_multi (&str);
6599 || (rege->type != REG_TYPE_MMXWR
6600 && rege->type != REG_TYPE_MMXWC
6601 && rege->type != REG_TYPE_MMXWCG))
6603 inst.error = _("iWMMXt data or control register expected");
6606 inst.operands[i].reg = rege->number;
6607 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6613 struct reg_entry *rege = arm_reg_parse_multi (&str);
6615 || (rege->type != REG_TYPE_MMXWC
6616 && rege->type != REG_TYPE_MMXWCG))
6618 inst.error = _("iWMMXt control register expected");
6621 inst.operands[i].reg = rege->number;
6622 inst.operands[i].isreg = 1;
6627 case OP_CPSF: val = parse_cps_flags (&str); break;
6628 case OP_ENDI: val = parse_endian_specifier (&str); break;
6629 case OP_oROR: val = parse_ror (&str); break;
6630 case OP_COND: val = parse_cond (&str); break;
6631 case OP_oBARRIER_I15:
6632 po_barrier_or_imm (str); break;
6634 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6640 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6641 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6643 inst.error = _("Banked registers are not available with this "
6649 val = parse_psr (&str, op_parse_code == OP_wPSR);
6653 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6656 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6658 if (strncasecmp (str, "APSR_", 5) == 0)
6665 case 'c': found = (found & 1) ? 16 : found | 1; break;
6666 case 'n': found = (found & 2) ? 16 : found | 2; break;
6667 case 'z': found = (found & 4) ? 16 : found | 4; break;
6668 case 'v': found = (found & 8) ? 16 : found | 8; break;
6669 default: found = 16;
6673 inst.operands[i].isvec = 1;
6674 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6675 inst.operands[i].reg = REG_PC;
6682 po_misc_or_fail (parse_tb (&str));
6685 /* Register lists. */
6687 val = parse_reg_list (&str);
6690 inst.operands[1].writeback = 1;
6696 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6700 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6704 /* Allow Q registers too. */
6705 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6710 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6712 inst.operands[i].issingle = 1;
6717 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6722 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6723 &inst.operands[i].vectype);
6726 /* Addressing modes */
6728 po_misc_or_fail (parse_address (&str, i));
6732 po_misc_or_fail_no_backtrack (
6733 parse_address_group_reloc (&str, i, GROUP_LDR));
6737 po_misc_or_fail_no_backtrack (
6738 parse_address_group_reloc (&str, i, GROUP_LDRS));
6742 po_misc_or_fail_no_backtrack (
6743 parse_address_group_reloc (&str, i, GROUP_LDC));
6747 po_misc_or_fail (parse_shifter_operand (&str, i));
6751 po_misc_or_fail_no_backtrack (
6752 parse_shifter_operand_group_reloc (&str, i));
6756 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6760 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6764 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6768 as_fatal (_("unhandled operand code %d"), op_parse_code);
6771 /* Various value-based sanity checks and shared operations. We
6772 do not signal immediate failures for the register constraints;
6773 this allows a syntax error to take precedence. */
6774 switch (op_parse_code)
6782 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6783 inst.error = BAD_PC;
6788 if (inst.operands[i].isreg)
6790 if (inst.operands[i].reg == REG_PC)
6791 inst.error = BAD_PC;
6792 else if (inst.operands[i].reg == REG_SP)
6793 inst.error = BAD_SP;
6798 if (inst.operands[i].isreg
6799 && inst.operands[i].reg == REG_PC
6800 && (inst.operands[i].writeback || thumb))
6801 inst.error = BAD_PC;
6810 case OP_oBARRIER_I15:
6819 inst.operands[i].imm = val;
6826 /* If we get here, this operand was successfully parsed. */
6827 inst.operands[i].present = 1;
6831 inst.error = BAD_ARGS;
6836 /* The parse routine should already have set inst.error, but set a
6837 default here just in case. */
6839 inst.error = _("syntax error");
6843 /* Do not backtrack over a trailing optional argument that
6844 absorbed some text. We will only fail again, with the
6845 'garbage following instruction' error message, which is
6846 probably less helpful than the current one. */
6847 if (backtrack_index == i && backtrack_pos != str
6848 && upat[i+1] == OP_stop)
6851 inst.error = _("syntax error");
6855 /* Try again, skipping the optional argument at backtrack_pos. */
6856 str = backtrack_pos;
6857 inst.error = backtrack_error;
6858 inst.operands[backtrack_index].present = 0;
6859 i = backtrack_index;
6863 /* Check that we have parsed all the arguments. */
6864 if (*str != '\0' && !inst.error)
6865 inst.error = _("garbage following instruction");
6867 return inst.error ? FAIL : SUCCESS;
6870 #undef po_char_or_fail
6871 #undef po_reg_or_fail
6872 #undef po_reg_or_goto
6873 #undef po_imm_or_fail
6874 #undef po_scalar_or_fail
6875 #undef po_barrier_or_imm
6877 /* Shorthand macro for instruction encoding functions issuing errors. */
6878 #define constraint(expr, err) \
6889 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6890 instructions are unpredictable if these registers are used. This
6891 is the BadReg predicate in ARM's Thumb-2 documentation. */
6892 #define reject_bad_reg(reg) \
6894 if (reg == REG_SP || reg == REG_PC) \
6896 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6901 /* If REG is R13 (the stack pointer), warn that its use is
6903 #define warn_deprecated_sp(reg) \
6905 if (warn_on_deprecated && reg == REG_SP) \
6906 as_warn (_("use of r13 is deprecated")); \
6909 /* Functions for operand encoding. ARM, then Thumb. */
6911 #define rotate_left(v, n) (v << n | v >> (32 - n))
6913 /* If VAL can be encoded in the immediate field of an ARM instruction,
6914 return the encoded form. Otherwise, return FAIL. */
6917 encode_arm_immediate (unsigned int val)
6921 for (i = 0; i < 32; i += 2)
6922 if ((a = rotate_left (val, i)) <= 0xff)
6923 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6928 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6929 return the encoded form. Otherwise, return FAIL. */
6931 encode_thumb32_immediate (unsigned int val)
6938 for (i = 1; i <= 24; i++)
6941 if ((val & ~(0xff << i)) == 0)
6942 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6946 if (val == ((a << 16) | a))
6948 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6952 if (val == ((a << 16) | a))
6953 return 0x200 | (a >> 8);
6957 /* Encode a VFP SP or DP register number into inst.instruction. */
6960 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6962 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6965 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6968 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6971 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6976 first_error (_("D register out of range for selected VFP version"));
6984 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6988 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6992 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6996 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7000 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7004 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7012 /* Encode a <shift> in an ARM-format instruction. The immediate,
7013 if any, is handled by md_apply_fix. */
7015 encode_arm_shift (int i)
7017 if (inst.operands[i].shift_kind == SHIFT_RRX)
7018 inst.instruction |= SHIFT_ROR << 5;
7021 inst.instruction |= inst.operands[i].shift_kind << 5;
7022 if (inst.operands[i].immisreg)
7024 inst.instruction |= SHIFT_BY_REG;
7025 inst.instruction |= inst.operands[i].imm << 8;
7028 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7033 encode_arm_shifter_operand (int i)
7035 if (inst.operands[i].isreg)
7037 inst.instruction |= inst.operands[i].reg;
7038 encode_arm_shift (i);
7042 inst.instruction |= INST_IMMEDIATE;
7043 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7044 inst.instruction |= inst.operands[i].imm;
7048 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7050 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7053 Generate an error if the operand is not a register. */
7054 constraint (!inst.operands[i].isreg,
7055 _("Instruction does not support =N addresses"));
7057 inst.instruction |= inst.operands[i].reg << 16;
7059 if (inst.operands[i].preind)
7063 inst.error = _("instruction does not accept preindexed addressing");
7066 inst.instruction |= PRE_INDEX;
7067 if (inst.operands[i].writeback)
7068 inst.instruction |= WRITE_BACK;
7071 else if (inst.operands[i].postind)
7073 gas_assert (inst.operands[i].writeback);
7075 inst.instruction |= WRITE_BACK;
7077 else /* unindexed - only for coprocessor */
7079 inst.error = _("instruction does not accept unindexed addressing");
7083 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7084 && (((inst.instruction & 0x000f0000) >> 16)
7085 == ((inst.instruction & 0x0000f000) >> 12)))
7086 as_warn ((inst.instruction & LOAD_BIT)
7087 ? _("destination register same as write-back base")
7088 : _("source register same as write-back base"));
7091 /* inst.operands[i] was set up by parse_address. Encode it into an
7092 ARM-format mode 2 load or store instruction. If is_t is true,
7093 reject forms that cannot be used with a T instruction (i.e. not
7096 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7098 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7100 encode_arm_addr_mode_common (i, is_t);
7102 if (inst.operands[i].immisreg)
7104 constraint ((inst.operands[i].imm == REG_PC
7105 || (is_pc && inst.operands[i].writeback)),
7107 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7108 inst.instruction |= inst.operands[i].imm;
7109 if (!inst.operands[i].negative)
7110 inst.instruction |= INDEX_UP;
7111 if (inst.operands[i].shifted)
7113 if (inst.operands[i].shift_kind == SHIFT_RRX)
7114 inst.instruction |= SHIFT_ROR << 5;
7117 inst.instruction |= inst.operands[i].shift_kind << 5;
7118 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7122 else /* immediate offset in inst.reloc */
7124 if (is_pc && !inst.reloc.pc_rel)
7126 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7128 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7129 cannot use PC in addressing.
7130 PC cannot be used in writeback addressing, either. */
7131 constraint ((is_t || inst.operands[i].writeback),
7134 /* Use of PC in str is deprecated for ARMv7. */
7135 if (warn_on_deprecated
7137 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7138 as_warn (_("use of PC in this instruction is deprecated"));
7141 if (inst.reloc.type == BFD_RELOC_UNUSED)
7143 /* Prefer + for zero encoded value. */
7144 if (!inst.operands[i].negative)
7145 inst.instruction |= INDEX_UP;
7146 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7151 /* inst.operands[i] was set up by parse_address. Encode it into an
7152 ARM-format mode 3 load or store instruction. Reject forms that
7153 cannot be used with such instructions. If is_t is true, reject
7154 forms that cannot be used with a T instruction (i.e. not
7157 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7159 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7161 inst.error = _("instruction does not accept scaled register index");
7165 encode_arm_addr_mode_common (i, is_t);
7167 if (inst.operands[i].immisreg)
7169 constraint ((inst.operands[i].imm == REG_PC
7170 || inst.operands[i].reg == REG_PC),
7172 inst.instruction |= inst.operands[i].imm;
7173 if (!inst.operands[i].negative)
7174 inst.instruction |= INDEX_UP;
7176 else /* immediate offset in inst.reloc */
7178 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7179 && inst.operands[i].writeback),
7181 inst.instruction |= HWOFFSET_IMM;
7182 if (inst.reloc.type == BFD_RELOC_UNUSED)
7184 /* Prefer + for zero encoded value. */
7185 if (!inst.operands[i].negative)
7186 inst.instruction |= INDEX_UP;
7188 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7193 /* inst.operands[i] was set up by parse_address. Encode it into an
7194 ARM-format instruction. Reject all forms which cannot be encoded
7195 into a coprocessor load/store instruction. If wb_ok is false,
7196 reject use of writeback; if unind_ok is false, reject use of
7197 unindexed addressing. If reloc_override is not 0, use it instead
7198 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7199 (in which case it is preserved). */
7202 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7204 inst.instruction |= inst.operands[i].reg << 16;
7206 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7208 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7210 gas_assert (!inst.operands[i].writeback);
7213 inst.error = _("instruction does not support unindexed addressing");
7216 inst.instruction |= inst.operands[i].imm;
7217 inst.instruction |= INDEX_UP;
7221 if (inst.operands[i].preind)
7222 inst.instruction |= PRE_INDEX;
7224 if (inst.operands[i].writeback)
7226 if (inst.operands[i].reg == REG_PC)
7228 inst.error = _("pc may not be used with write-back");
7233 inst.error = _("instruction does not support writeback");
7236 inst.instruction |= WRITE_BACK;
7240 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7241 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7242 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7243 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7246 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7248 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7251 /* Prefer + for zero encoded value. */
7252 if (!inst.operands[i].negative)
7253 inst.instruction |= INDEX_UP;
7258 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7259 Determine whether it can be performed with a move instruction; if
7260 it can, convert inst.instruction to that move instruction and
7261 return TRUE; if it can't, convert inst.instruction to a literal-pool
7262 load and return FALSE. If this is not a valid thing to do in the
7263 current context, set inst.error and return TRUE.
7265 inst.operands[i] describes the destination register. */
7268 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7273 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7277 if ((inst.instruction & tbit) == 0)
7279 inst.error = _("invalid pseudo operation");
7282 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7284 inst.error = _("constant expression expected");
7287 if (inst.reloc.exp.X_op == O_constant)
7291 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7293 /* This can be done with a mov(1) instruction. */
7294 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7295 inst.instruction |= inst.reloc.exp.X_add_number;
7301 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7304 /* This can be done with a mov instruction. */
7305 inst.instruction &= LITERAL_MASK;
7306 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7307 inst.instruction |= value & 0xfff;
7311 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7314 /* This can be done with a mvn instruction. */
7315 inst.instruction &= LITERAL_MASK;
7316 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7317 inst.instruction |= value & 0xfff;
7323 if (add_to_lit_pool () == FAIL)
7325 inst.error = _("literal pool insertion failed");
7328 inst.operands[1].reg = REG_PC;
7329 inst.operands[1].isreg = 1;
7330 inst.operands[1].preind = 1;
7331 inst.reloc.pc_rel = 1;
7332 inst.reloc.type = (thumb_p
7333 ? BFD_RELOC_ARM_THUMB_OFFSET
7335 ? BFD_RELOC_ARM_HWLITERAL
7336 : BFD_RELOC_ARM_LITERAL));
7340 /* Functions for instruction encoding, sorted by sub-architecture.
7341 First some generics; their names are taken from the conventional
7342 bit positions for register arguments in ARM format instructions. */
7352 inst.instruction |= inst.operands[0].reg << 12;
7358 inst.instruction |= inst.operands[0].reg << 12;
7359 inst.instruction |= inst.operands[1].reg;
7365 inst.instruction |= inst.operands[0].reg << 12;
7366 inst.instruction |= inst.operands[1].reg << 16;
7372 inst.instruction |= inst.operands[0].reg << 16;
7373 inst.instruction |= inst.operands[1].reg << 12;
7377 check_obsolete (const arm_feature_set *feature, const char *msg)
7379 if (ARM_CPU_IS_ANY (cpu_variant))
7381 as_warn ("%s", msg);
7384 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7396 unsigned Rn = inst.operands[2].reg;
7397 /* Enforce restrictions on SWP instruction. */
7398 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7400 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7401 _("Rn must not overlap other operands"));
7403 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7405 if (!check_obsolete (&arm_ext_v8,
7406 _("swp{b} use is obsoleted for ARMv8 and later"))
7407 && warn_on_deprecated
7408 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7409 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7412 inst.instruction |= inst.operands[0].reg << 12;
7413 inst.instruction |= inst.operands[1].reg;
7414 inst.instruction |= Rn << 16;
7420 inst.instruction |= inst.operands[0].reg << 12;
7421 inst.instruction |= inst.operands[1].reg << 16;
7422 inst.instruction |= inst.operands[2].reg;
7428 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7429 constraint (((inst.reloc.exp.X_op != O_constant
7430 && inst.reloc.exp.X_op != O_illegal)
7431 || inst.reloc.exp.X_add_number != 0),
7433 inst.instruction |= inst.operands[0].reg;
7434 inst.instruction |= inst.operands[1].reg << 12;
7435 inst.instruction |= inst.operands[2].reg << 16;
7441 inst.instruction |= inst.operands[0].imm;
7447 inst.instruction |= inst.operands[0].reg << 12;
7448 encode_arm_cp_address (1, TRUE, TRUE, 0);
7451 /* ARM instructions, in alphabetical order by function name (except
7452 that wrapper functions appear immediately after the function they
7455 /* This is a pseudo-op of the form "adr rd, label" to be converted
7456 into a relative address of the form "add rd, pc, #label-.-8". */
7461 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7463 /* Frag hacking will turn this into a sub instruction if the offset turns
7464 out to be negative. */
7465 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7466 inst.reloc.pc_rel = 1;
7467 inst.reloc.exp.X_add_number -= 8;
7470 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7471 into a relative address of the form:
7472 add rd, pc, #low(label-.-8)"
7473 add rd, rd, #high(label-.-8)" */
7478 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7480 /* Frag hacking will turn this into a sub instruction if the offset turns
7481 out to be negative. */
7482 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7483 inst.reloc.pc_rel = 1;
7484 inst.size = INSN_SIZE * 2;
7485 inst.reloc.exp.X_add_number -= 8;
7491 if (!inst.operands[1].present)
7492 inst.operands[1].reg = inst.operands[0].reg;
7493 inst.instruction |= inst.operands[0].reg << 12;
7494 inst.instruction |= inst.operands[1].reg << 16;
7495 encode_arm_shifter_operand (2);
7501 if (inst.operands[0].present)
7503 constraint ((inst.instruction & 0xf0) != 0x40
7504 && inst.operands[0].imm > 0xf
7505 && inst.operands[0].imm < 0x0,
7506 _("bad barrier type"));
7507 inst.instruction |= inst.operands[0].imm;
7510 inst.instruction |= 0xf;
7516 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7517 constraint (msb > 32, _("bit-field extends past end of register"));
7518 /* The instruction encoding stores the LSB and MSB,
7519 not the LSB and width. */
7520 inst.instruction |= inst.operands[0].reg << 12;
7521 inst.instruction |= inst.operands[1].imm << 7;
7522 inst.instruction |= (msb - 1) << 16;
7530 /* #0 in second position is alternative syntax for bfc, which is
7531 the same instruction but with REG_PC in the Rm field. */
7532 if (!inst.operands[1].isreg)
7533 inst.operands[1].reg = REG_PC;
7535 msb = inst.operands[2].imm + inst.operands[3].imm;
7536 constraint (msb > 32, _("bit-field extends past end of register"));
7537 /* The instruction encoding stores the LSB and MSB,
7538 not the LSB and width. */
7539 inst.instruction |= inst.operands[0].reg << 12;
7540 inst.instruction |= inst.operands[1].reg;
7541 inst.instruction |= inst.operands[2].imm << 7;
7542 inst.instruction |= (msb - 1) << 16;
7548 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7549 _("bit-field extends past end of register"));
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].reg;
7552 inst.instruction |= inst.operands[2].imm << 7;
7553 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7556 /* ARM V5 breakpoint instruction (argument parse)
7557 BKPT <16 bit unsigned immediate>
7558 Instruction is not conditional.
7559 The bit pattern given in insns[] has the COND_ALWAYS condition,
7560 and it is an error if the caller tried to override that. */
7565 /* Top 12 of 16 bits to bits 19:8. */
7566 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7568 /* Bottom 4 of 16 bits to bits 3:0. */
7569 inst.instruction |= inst.operands[0].imm & 0xf;
7573 encode_branch (int default_reloc)
7575 if (inst.operands[0].hasreloc)
7577 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7578 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7579 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7580 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7581 ? BFD_RELOC_ARM_PLT32
7582 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7585 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7586 inst.reloc.pc_rel = 1;
7593 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7594 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7597 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7604 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7606 if (inst.cond == COND_ALWAYS)
7607 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7609 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7613 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7616 /* ARM V5 branch-link-exchange instruction (argument parse)
7617 BLX <target_addr> ie BLX(1)
7618 BLX{<condition>} <Rm> ie BLX(2)
7619 Unfortunately, there are two different opcodes for this mnemonic.
7620 So, the insns[].value is not used, and the code here zaps values
7621 into inst.instruction.
7622 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7627 if (inst.operands[0].isreg)
7629 /* Arg is a register; the opcode provided by insns[] is correct.
7630 It is not illegal to do "blx pc", just useless. */
7631 if (inst.operands[0].reg == REG_PC)
7632 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7634 inst.instruction |= inst.operands[0].reg;
7638 /* Arg is an address; this instruction cannot be executed
7639 conditionally, and the opcode must be adjusted.
7640 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7641 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7642 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7643 inst.instruction = 0xfa000000;
7644 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7651 bfd_boolean want_reloc;
7653 if (inst.operands[0].reg == REG_PC)
7654 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7656 inst.instruction |= inst.operands[0].reg;
7657 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7658 it is for ARMv4t or earlier. */
7659 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7660 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7664 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7669 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7673 /* ARM v5TEJ. Jump to Jazelle code. */
7678 if (inst.operands[0].reg == REG_PC)
7679 as_tsktsk (_("use of r15 in bxj is not really useful"));
7681 inst.instruction |= inst.operands[0].reg;
7684 /* Co-processor data operation:
7685 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7686 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7690 inst.instruction |= inst.operands[0].reg << 8;
7691 inst.instruction |= inst.operands[1].imm << 20;
7692 inst.instruction |= inst.operands[2].reg << 12;
7693 inst.instruction |= inst.operands[3].reg << 16;
7694 inst.instruction |= inst.operands[4].reg;
7695 inst.instruction |= inst.operands[5].imm << 5;
7701 inst.instruction |= inst.operands[0].reg << 16;
7702 encode_arm_shifter_operand (1);
7705 /* Transfer between coprocessor and ARM registers.
7706 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7711 No special properties. */
7718 Rd = inst.operands[2].reg;
7721 if (inst.instruction == 0xee000010
7722 || inst.instruction == 0xfe000010)
7724 reject_bad_reg (Rd);
7727 constraint (Rd == REG_SP, BAD_SP);
7732 if (inst.instruction == 0xe000010)
7733 constraint (Rd == REG_PC, BAD_PC);
7737 inst.instruction |= inst.operands[0].reg << 8;
7738 inst.instruction |= inst.operands[1].imm << 21;
7739 inst.instruction |= Rd << 12;
7740 inst.instruction |= inst.operands[3].reg << 16;
7741 inst.instruction |= inst.operands[4].reg;
7742 inst.instruction |= inst.operands[5].imm << 5;
7745 /* Transfer between coprocessor register and pair of ARM registers.
7746 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7751 Two XScale instructions are special cases of these:
7753 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7754 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7756 Result unpredictable if Rd or Rn is R15. */
7763 Rd = inst.operands[2].reg;
7764 Rn = inst.operands[3].reg;
7768 reject_bad_reg (Rd);
7769 reject_bad_reg (Rn);
7773 constraint (Rd == REG_PC, BAD_PC);
7774 constraint (Rn == REG_PC, BAD_PC);
7777 inst.instruction |= inst.operands[0].reg << 8;
7778 inst.instruction |= inst.operands[1].imm << 4;
7779 inst.instruction |= Rd << 12;
7780 inst.instruction |= Rn << 16;
7781 inst.instruction |= inst.operands[4].reg;
7787 inst.instruction |= inst.operands[0].imm << 6;
7788 if (inst.operands[1].present)
7790 inst.instruction |= CPSI_MMOD;
7791 inst.instruction |= inst.operands[1].imm;
7798 inst.instruction |= inst.operands[0].imm;
7804 unsigned Rd, Rn, Rm;
7806 Rd = inst.operands[0].reg;
7807 Rn = (inst.operands[1].present
7808 ? inst.operands[1].reg : Rd);
7809 Rm = inst.operands[2].reg;
7811 constraint ((Rd == REG_PC), BAD_PC);
7812 constraint ((Rn == REG_PC), BAD_PC);
7813 constraint ((Rm == REG_PC), BAD_PC);
7815 inst.instruction |= Rd << 16;
7816 inst.instruction |= Rn << 0;
7817 inst.instruction |= Rm << 8;
7823 /* There is no IT instruction in ARM mode. We
7824 process it to do the validation as if in
7825 thumb mode, just in case the code gets
7826 assembled for thumb using the unified syntax. */
7831 set_it_insn_type (IT_INSN);
7832 now_it.mask = (inst.instruction & 0xf) | 0x10;
7833 now_it.cc = inst.operands[0].imm;
7837 /* If there is only one register in the register list,
7838 then return its register number. Otherwise return -1. */
7840 only_one_reg_in_list (int range)
7842 int i = ffs (range) - 1;
7843 return (i > 15 || range != (1 << i)) ? -1 : i;
7847 encode_ldmstm(int from_push_pop_mnem)
7849 int base_reg = inst.operands[0].reg;
7850 int range = inst.operands[1].imm;
7853 inst.instruction |= base_reg << 16;
7854 inst.instruction |= range;
7856 if (inst.operands[1].writeback)
7857 inst.instruction |= LDM_TYPE_2_OR_3;
7859 if (inst.operands[0].writeback)
7861 inst.instruction |= WRITE_BACK;
7862 /* Check for unpredictable uses of writeback. */
7863 if (inst.instruction & LOAD_BIT)
7865 /* Not allowed in LDM type 2. */
7866 if ((inst.instruction & LDM_TYPE_2_OR_3)
7867 && ((range & (1 << REG_PC)) == 0))
7868 as_warn (_("writeback of base register is UNPREDICTABLE"));
7869 /* Only allowed if base reg not in list for other types. */
7870 else if (range & (1 << base_reg))
7871 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7875 /* Not allowed for type 2. */
7876 if (inst.instruction & LDM_TYPE_2_OR_3)
7877 as_warn (_("writeback of base register is UNPREDICTABLE"));
7878 /* Only allowed if base reg not in list, or first in list. */
7879 else if ((range & (1 << base_reg))
7880 && (range & ((1 << base_reg) - 1)))
7881 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7885 /* If PUSH/POP has only one register, then use the A2 encoding. */
7886 one_reg = only_one_reg_in_list (range);
7887 if (from_push_pop_mnem && one_reg >= 0)
7889 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7891 inst.instruction &= A_COND_MASK;
7892 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7893 inst.instruction |= one_reg << 12;
7900 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7903 /* ARMv5TE load-consecutive (argument parse)
7912 constraint (inst.operands[0].reg % 2 != 0,
7913 _("first transfer register must be even"));
7914 constraint (inst.operands[1].present
7915 && inst.operands[1].reg != inst.operands[0].reg + 1,
7916 _("can only transfer two consecutive registers"));
7917 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7918 constraint (!inst.operands[2].isreg, _("'[' expected"));
7920 if (!inst.operands[1].present)
7921 inst.operands[1].reg = inst.operands[0].reg + 1;
7923 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7924 register and the first register written; we have to diagnose
7925 overlap between the base and the second register written here. */
7927 if (inst.operands[2].reg == inst.operands[1].reg
7928 && (inst.operands[2].writeback || inst.operands[2].postind))
7929 as_warn (_("base register written back, and overlaps "
7930 "second transfer register"));
7932 if (!(inst.instruction & V4_STR_BIT))
7934 /* For an index-register load, the index register must not overlap the
7935 destination (even if not write-back). */
7936 if (inst.operands[2].immisreg
7937 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7938 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7939 as_warn (_("index register overlaps transfer register"));
7941 inst.instruction |= inst.operands[0].reg << 12;
7942 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7948 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7949 || inst.operands[1].postind || inst.operands[1].writeback
7950 || inst.operands[1].immisreg || inst.operands[1].shifted
7951 || inst.operands[1].negative
7952 /* This can arise if the programmer has written
7954 or if they have mistakenly used a register name as the last
7957 It is very difficult to distinguish between these two cases
7958 because "rX" might actually be a label. ie the register
7959 name has been occluded by a symbol of the same name. So we
7960 just generate a general 'bad addressing mode' type error
7961 message and leave it up to the programmer to discover the
7962 true cause and fix their mistake. */
7963 || (inst.operands[1].reg == REG_PC),
7966 constraint (inst.reloc.exp.X_op != O_constant
7967 || inst.reloc.exp.X_add_number != 0,
7968 _("offset must be zero in ARM encoding"));
7970 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7972 inst.instruction |= inst.operands[0].reg << 12;
7973 inst.instruction |= inst.operands[1].reg << 16;
7974 inst.reloc.type = BFD_RELOC_UNUSED;
7980 constraint (inst.operands[0].reg % 2 != 0,
7981 _("even register required"));
7982 constraint (inst.operands[1].present
7983 && inst.operands[1].reg != inst.operands[0].reg + 1,
7984 _("can only load two consecutive registers"));
7985 /* If op 1 were present and equal to PC, this function wouldn't
7986 have been called in the first place. */
7987 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7989 inst.instruction |= inst.operands[0].reg << 12;
7990 inst.instruction |= inst.operands[2].reg << 16;
7993 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7994 which is not a multiple of four is UNPREDICTABLE. */
7996 check_ldr_r15_aligned (void)
7998 constraint (!(inst.operands[1].immisreg)
7999 && (inst.operands[0].reg == REG_PC
8000 && inst.operands[1].reg == REG_PC
8001 && (inst.reloc.exp.X_add_number & 0x3)),
8002 _("ldr to register 15 must be 4-byte alligned"));
8008 inst.instruction |= inst.operands[0].reg << 12;
8009 if (!inst.operands[1].isreg)
8010 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8012 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8013 check_ldr_r15_aligned ();
8019 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8021 if (inst.operands[1].preind)
8023 constraint (inst.reloc.exp.X_op != O_constant
8024 || inst.reloc.exp.X_add_number != 0,
8025 _("this instruction requires a post-indexed address"));
8027 inst.operands[1].preind = 0;
8028 inst.operands[1].postind = 1;
8029 inst.operands[1].writeback = 1;
8031 inst.instruction |= inst.operands[0].reg << 12;
8032 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8035 /* Halfword and signed-byte load/store operations. */
8040 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8041 inst.instruction |= inst.operands[0].reg << 12;
8042 if (!inst.operands[1].isreg)
8043 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8045 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8051 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8053 if (inst.operands[1].preind)
8055 constraint (inst.reloc.exp.X_op != O_constant
8056 || inst.reloc.exp.X_add_number != 0,
8057 _("this instruction requires a post-indexed address"));
8059 inst.operands[1].preind = 0;
8060 inst.operands[1].postind = 1;
8061 inst.operands[1].writeback = 1;
8063 inst.instruction |= inst.operands[0].reg << 12;
8064 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8067 /* Co-processor register load/store.
8068 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8072 inst.instruction |= inst.operands[0].reg << 8;
8073 inst.instruction |= inst.operands[1].reg << 12;
8074 encode_arm_cp_address (2, TRUE, TRUE, 0);
8080 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8081 if (inst.operands[0].reg == inst.operands[1].reg
8082 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8083 && !(inst.instruction & 0x00400000))
8084 as_tsktsk (_("Rd and Rm should be different in mla"));
8086 inst.instruction |= inst.operands[0].reg << 16;
8087 inst.instruction |= inst.operands[1].reg;
8088 inst.instruction |= inst.operands[2].reg << 8;
8089 inst.instruction |= inst.operands[3].reg << 12;
8095 inst.instruction |= inst.operands[0].reg << 12;
8096 encode_arm_shifter_operand (1);
8099 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8106 top = (inst.instruction & 0x00400000) != 0;
8107 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8108 _(":lower16: not allowed this instruction"));
8109 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8110 _(":upper16: not allowed instruction"));
8111 inst.instruction |= inst.operands[0].reg << 12;
8112 if (inst.reloc.type == BFD_RELOC_UNUSED)
8114 imm = inst.reloc.exp.X_add_number;
8115 /* The value is in two pieces: 0:11, 16:19. */
8116 inst.instruction |= (imm & 0x00000fff);
8117 inst.instruction |= (imm & 0x0000f000) << 4;
8121 static void do_vfp_nsyn_opcode (const char *);
8124 do_vfp_nsyn_mrs (void)
8126 if (inst.operands[0].isvec)
8128 if (inst.operands[1].reg != 1)
8129 first_error (_("operand 1 must be FPSCR"));
8130 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8131 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8132 do_vfp_nsyn_opcode ("fmstat");
8134 else if (inst.operands[1].isvec)
8135 do_vfp_nsyn_opcode ("fmrx");
8143 do_vfp_nsyn_msr (void)
8145 if (inst.operands[0].isvec)
8146 do_vfp_nsyn_opcode ("fmxr");
8156 unsigned Rt = inst.operands[0].reg;
8158 if (thumb_mode && inst.operands[0].reg == REG_SP)
8160 inst.error = BAD_SP;
8164 /* APSR_ sets isvec. All other refs to PC are illegal. */
8165 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8167 inst.error = BAD_PC;
8171 switch (inst.operands[1].reg)
8178 inst.instruction |= (inst.operands[1].reg << 16);
8181 first_error (_("operand 1 must be a VFP extension System Register"));
8184 inst.instruction |= (Rt << 12);
8190 unsigned Rt = inst.operands[1].reg;
8193 reject_bad_reg (Rt);
8194 else if (Rt == REG_PC)
8196 inst.error = BAD_PC;
8200 switch (inst.operands[0].reg)
8205 inst.instruction |= (inst.operands[0].reg << 16);
8208 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8211 inst.instruction |= (Rt << 12);
8219 if (do_vfp_nsyn_mrs () == SUCCESS)
8222 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8223 inst.instruction |= inst.operands[0].reg << 12;
8225 if (inst.operands[1].isreg)
8227 br = inst.operands[1].reg;
8228 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8229 as_bad (_("bad register for mrs"));
8233 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8234 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8236 _("'APSR', 'CPSR' or 'SPSR' expected"));
8237 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8240 inst.instruction |= br;
8243 /* Two possible forms:
8244 "{C|S}PSR_<field>, Rm",
8245 "{C|S}PSR_f, #expression". */
8250 if (do_vfp_nsyn_msr () == SUCCESS)
8253 inst.instruction |= inst.operands[0].imm;
8254 if (inst.operands[1].isreg)
8255 inst.instruction |= inst.operands[1].reg;
8258 inst.instruction |= INST_IMMEDIATE;
8259 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8260 inst.reloc.pc_rel = 0;
8267 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8269 if (!inst.operands[2].present)
8270 inst.operands[2].reg = inst.operands[0].reg;
8271 inst.instruction |= inst.operands[0].reg << 16;
8272 inst.instruction |= inst.operands[1].reg;
8273 inst.instruction |= inst.operands[2].reg << 8;
8275 if (inst.operands[0].reg == inst.operands[1].reg
8276 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8277 as_tsktsk (_("Rd and Rm should be different in mul"));
8280 /* Long Multiply Parser
8281 UMULL RdLo, RdHi, Rm, Rs
8282 SMULL RdLo, RdHi, Rm, Rs
8283 UMLAL RdLo, RdHi, Rm, Rs
8284 SMLAL RdLo, RdHi, Rm, Rs. */
8289 inst.instruction |= inst.operands[0].reg << 12;
8290 inst.instruction |= inst.operands[1].reg << 16;
8291 inst.instruction |= inst.operands[2].reg;
8292 inst.instruction |= inst.operands[3].reg << 8;
8294 /* rdhi and rdlo must be different. */
8295 if (inst.operands[0].reg == inst.operands[1].reg)
8296 as_tsktsk (_("rdhi and rdlo must be different"));
8298 /* rdhi, rdlo and rm must all be different before armv6. */
8299 if ((inst.operands[0].reg == inst.operands[2].reg
8300 || inst.operands[1].reg == inst.operands[2].reg)
8301 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8302 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8308 if (inst.operands[0].present
8309 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8311 /* Architectural NOP hints are CPSR sets with no bits selected. */
8312 inst.instruction &= 0xf0000000;
8313 inst.instruction |= 0x0320f000;
8314 if (inst.operands[0].present)
8315 inst.instruction |= inst.operands[0].imm;
8319 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8320 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8321 Condition defaults to COND_ALWAYS.
8322 Error if Rd, Rn or Rm are R15. */
8327 inst.instruction |= inst.operands[0].reg << 12;
8328 inst.instruction |= inst.operands[1].reg << 16;
8329 inst.instruction |= inst.operands[2].reg;
8330 if (inst.operands[3].present)
8331 encode_arm_shift (3);
8334 /* ARM V6 PKHTB (Argument Parse). */
8339 if (!inst.operands[3].present)
8341 /* If the shift specifier is omitted, turn the instruction
8342 into pkhbt rd, rm, rn. */
8343 inst.instruction &= 0xfff00010;
8344 inst.instruction |= inst.operands[0].reg << 12;
8345 inst.instruction |= inst.operands[1].reg;
8346 inst.instruction |= inst.operands[2].reg << 16;
8350 inst.instruction |= inst.operands[0].reg << 12;
8351 inst.instruction |= inst.operands[1].reg << 16;
8352 inst.instruction |= inst.operands[2].reg;
8353 encode_arm_shift (3);
8357 /* ARMv5TE: Preload-Cache
8358 MP Extensions: Preload for write
8362 Syntactically, like LDR with B=1, W=0, L=1. */
8367 constraint (!inst.operands[0].isreg,
8368 _("'[' expected after PLD mnemonic"));
8369 constraint (inst.operands[0].postind,
8370 _("post-indexed expression used in preload instruction"));
8371 constraint (inst.operands[0].writeback,
8372 _("writeback used in preload instruction"));
8373 constraint (!inst.operands[0].preind,
8374 _("unindexed addressing used in preload instruction"));
8375 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8378 /* ARMv7: PLI <addr_mode> */
8382 constraint (!inst.operands[0].isreg,
8383 _("'[' expected after PLI mnemonic"));
8384 constraint (inst.operands[0].postind,
8385 _("post-indexed expression used in preload instruction"));
8386 constraint (inst.operands[0].writeback,
8387 _("writeback used in preload instruction"));
8388 constraint (!inst.operands[0].preind,
8389 _("unindexed addressing used in preload instruction"));
8390 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8391 inst.instruction &= ~PRE_INDEX;
8397 inst.operands[1] = inst.operands[0];
8398 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8399 inst.operands[0].isreg = 1;
8400 inst.operands[0].writeback = 1;
8401 inst.operands[0].reg = REG_SP;
8402 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8405 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8406 word at the specified address and the following word
8408 Unconditionally executed.
8409 Error if Rn is R15. */
8414 inst.instruction |= inst.operands[0].reg << 16;
8415 if (inst.operands[0].writeback)
8416 inst.instruction |= WRITE_BACK;
8419 /* ARM V6 ssat (argument parse). */
8424 inst.instruction |= inst.operands[0].reg << 12;
8425 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8426 inst.instruction |= inst.operands[2].reg;
8428 if (inst.operands[3].present)
8429 encode_arm_shift (3);
8432 /* ARM V6 usat (argument parse). */
8437 inst.instruction |= inst.operands[0].reg << 12;
8438 inst.instruction |= inst.operands[1].imm << 16;
8439 inst.instruction |= inst.operands[2].reg;
8441 if (inst.operands[3].present)
8442 encode_arm_shift (3);
8445 /* ARM V6 ssat16 (argument parse). */
8450 inst.instruction |= inst.operands[0].reg << 12;
8451 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8452 inst.instruction |= inst.operands[2].reg;
8458 inst.instruction |= inst.operands[0].reg << 12;
8459 inst.instruction |= inst.operands[1].imm << 16;
8460 inst.instruction |= inst.operands[2].reg;
8463 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8464 preserving the other bits.
8466 setend <endian_specifier>, where <endian_specifier> is either
8472 if (inst.operands[0].imm)
8473 inst.instruction |= 0x200;
8479 unsigned int Rm = (inst.operands[1].present
8480 ? inst.operands[1].reg
8481 : inst.operands[0].reg);
8483 inst.instruction |= inst.operands[0].reg << 12;
8484 inst.instruction |= Rm;
8485 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8487 inst.instruction |= inst.operands[2].reg << 8;
8488 inst.instruction |= SHIFT_BY_REG;
8489 /* PR 12854: Error on extraneous shifts. */
8490 constraint (inst.operands[2].shifted,
8491 _("extraneous shift as part of operand to shift insn"));
8494 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8500 inst.reloc.type = BFD_RELOC_ARM_SMC;
8501 inst.reloc.pc_rel = 0;
8507 inst.reloc.type = BFD_RELOC_ARM_HVC;
8508 inst.reloc.pc_rel = 0;
8514 inst.reloc.type = BFD_RELOC_ARM_SWI;
8515 inst.reloc.pc_rel = 0;
8518 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8519 SMLAxy{cond} Rd,Rm,Rs,Rn
8520 SMLAWy{cond} Rd,Rm,Rs,Rn
8521 Error if any register is R15. */
8526 inst.instruction |= inst.operands[0].reg << 16;
8527 inst.instruction |= inst.operands[1].reg;
8528 inst.instruction |= inst.operands[2].reg << 8;
8529 inst.instruction |= inst.operands[3].reg << 12;
8532 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8533 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8534 Error if any register is R15.
8535 Warning if Rdlo == Rdhi. */
8540 inst.instruction |= inst.operands[0].reg << 12;
8541 inst.instruction |= inst.operands[1].reg << 16;
8542 inst.instruction |= inst.operands[2].reg;
8543 inst.instruction |= inst.operands[3].reg << 8;
8545 if (inst.operands[0].reg == inst.operands[1].reg)
8546 as_tsktsk (_("rdhi and rdlo must be different"));
8549 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8550 SMULxy{cond} Rd,Rm,Rs
8551 Error if any register is R15. */
8556 inst.instruction |= inst.operands[0].reg << 16;
8557 inst.instruction |= inst.operands[1].reg;
8558 inst.instruction |= inst.operands[2].reg << 8;
8561 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8562 the same for both ARM and Thumb-2. */
8569 if (inst.operands[0].present)
8571 reg = inst.operands[0].reg;
8572 constraint (reg != REG_SP, _("SRS base register must be r13"));
8577 inst.instruction |= reg << 16;
8578 inst.instruction |= inst.operands[1].imm;
8579 if (inst.operands[0].writeback || inst.operands[1].writeback)
8580 inst.instruction |= WRITE_BACK;
8583 /* ARM V6 strex (argument parse). */
8588 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8589 || inst.operands[2].postind || inst.operands[2].writeback
8590 || inst.operands[2].immisreg || inst.operands[2].shifted
8591 || inst.operands[2].negative
8592 /* See comment in do_ldrex(). */
8593 || (inst.operands[2].reg == REG_PC),
8596 constraint (inst.operands[0].reg == inst.operands[1].reg
8597 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8599 constraint (inst.reloc.exp.X_op != O_constant
8600 || inst.reloc.exp.X_add_number != 0,
8601 _("offset must be zero in ARM encoding"));
8603 inst.instruction |= inst.operands[0].reg << 12;
8604 inst.instruction |= inst.operands[1].reg;
8605 inst.instruction |= inst.operands[2].reg << 16;
8606 inst.reloc.type = BFD_RELOC_UNUSED;
8612 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8613 || inst.operands[2].postind || inst.operands[2].writeback
8614 || inst.operands[2].immisreg || inst.operands[2].shifted
8615 || inst.operands[2].negative,
8618 constraint (inst.operands[0].reg == inst.operands[1].reg
8619 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8627 constraint (inst.operands[1].reg % 2 != 0,
8628 _("even register required"));
8629 constraint (inst.operands[2].present
8630 && inst.operands[2].reg != inst.operands[1].reg + 1,
8631 _("can only store two consecutive registers"));
8632 /* If op 2 were present and equal to PC, this function wouldn't
8633 have been called in the first place. */
8634 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8636 constraint (inst.operands[0].reg == inst.operands[1].reg
8637 || inst.operands[0].reg == inst.operands[1].reg + 1
8638 || inst.operands[0].reg == inst.operands[3].reg,
8641 inst.instruction |= inst.operands[0].reg << 12;
8642 inst.instruction |= inst.operands[1].reg;
8643 inst.instruction |= inst.operands[3].reg << 16;
8646 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8647 extends it to 32-bits, and adds the result to a value in another
8648 register. You can specify a rotation by 0, 8, 16, or 24 bits
8649 before extracting the 16-bit value.
8650 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8651 Condition defaults to COND_ALWAYS.
8652 Error if any register uses R15. */
8657 inst.instruction |= inst.operands[0].reg << 12;
8658 inst.instruction |= inst.operands[1].reg << 16;
8659 inst.instruction |= inst.operands[2].reg;
8660 inst.instruction |= inst.operands[3].imm << 10;
8665 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8666 Condition defaults to COND_ALWAYS.
8667 Error if any register uses R15. */
8672 inst.instruction |= inst.operands[0].reg << 12;
8673 inst.instruction |= inst.operands[1].reg;
8674 inst.instruction |= inst.operands[2].imm << 10;
8677 /* VFP instructions. In a logical order: SP variant first, monad
8678 before dyad, arithmetic then move then load/store. */
8681 do_vfp_sp_monadic (void)
8683 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8684 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8688 do_vfp_sp_dyadic (void)
8690 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8691 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8692 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8696 do_vfp_sp_compare_z (void)
8698 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8702 do_vfp_dp_sp_cvt (void)
8704 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8705 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8709 do_vfp_sp_dp_cvt (void)
8711 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8712 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8716 do_vfp_reg_from_sp (void)
8718 inst.instruction |= inst.operands[0].reg << 12;
8719 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8723 do_vfp_reg2_from_sp2 (void)
8725 constraint (inst.operands[2].imm != 2,
8726 _("only two consecutive VFP SP registers allowed here"));
8727 inst.instruction |= inst.operands[0].reg << 12;
8728 inst.instruction |= inst.operands[1].reg << 16;
8729 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8733 do_vfp_sp_from_reg (void)
8735 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8736 inst.instruction |= inst.operands[1].reg << 12;
8740 do_vfp_sp2_from_reg2 (void)
8742 constraint (inst.operands[0].imm != 2,
8743 _("only two consecutive VFP SP registers allowed here"));
8744 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8745 inst.instruction |= inst.operands[1].reg << 12;
8746 inst.instruction |= inst.operands[2].reg << 16;
8750 do_vfp_sp_ldst (void)
8752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8753 encode_arm_cp_address (1, FALSE, TRUE, 0);
8757 do_vfp_dp_ldst (void)
8759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8760 encode_arm_cp_address (1, FALSE, TRUE, 0);
8765 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8767 if (inst.operands[0].writeback)
8768 inst.instruction |= WRITE_BACK;
8770 constraint (ldstm_type != VFP_LDSTMIA,
8771 _("this addressing mode requires base-register writeback"));
8772 inst.instruction |= inst.operands[0].reg << 16;
8773 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8774 inst.instruction |= inst.operands[1].imm;
8778 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8782 if (inst.operands[0].writeback)
8783 inst.instruction |= WRITE_BACK;
8785 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8786 _("this addressing mode requires base-register writeback"));
8788 inst.instruction |= inst.operands[0].reg << 16;
8789 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8791 count = inst.operands[1].imm << 1;
8792 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8795 inst.instruction |= count;
8799 do_vfp_sp_ldstmia (void)
8801 vfp_sp_ldstm (VFP_LDSTMIA);
8805 do_vfp_sp_ldstmdb (void)
8807 vfp_sp_ldstm (VFP_LDSTMDB);
8811 do_vfp_dp_ldstmia (void)
8813 vfp_dp_ldstm (VFP_LDSTMIA);
8817 do_vfp_dp_ldstmdb (void)
8819 vfp_dp_ldstm (VFP_LDSTMDB);
8823 do_vfp_xp_ldstmia (void)
8825 vfp_dp_ldstm (VFP_LDSTMIAX);
8829 do_vfp_xp_ldstmdb (void)
8831 vfp_dp_ldstm (VFP_LDSTMDBX);
8835 do_vfp_dp_rd_rm (void)
8837 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8838 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8842 do_vfp_dp_rn_rd (void)
8844 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8845 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8849 do_vfp_dp_rd_rn (void)
8851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8852 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8856 do_vfp_dp_rd_rn_rm (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8859 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8860 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8866 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8870 do_vfp_dp_rm_rd_rn (void)
8872 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8873 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8874 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8877 /* VFPv3 instructions. */
8879 do_vfp_sp_const (void)
8881 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8882 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8883 inst.instruction |= (inst.operands[1].imm & 0x0f);
8887 do_vfp_dp_const (void)
8889 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8890 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8891 inst.instruction |= (inst.operands[1].imm & 0x0f);
8895 vfp_conv (int srcsize)
8897 int immbits = srcsize - inst.operands[1].imm;
8899 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8901 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8902 i.e. immbits must be in range 0 - 16. */
8903 inst.error = _("immediate value out of range, expected range [0, 16]");
8906 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8908 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8909 i.e. immbits must be in range 0 - 31. */
8910 inst.error = _("immediate value out of range, expected range [1, 32]");
8914 inst.instruction |= (immbits & 1) << 5;
8915 inst.instruction |= (immbits >> 1);
8919 do_vfp_sp_conv_16 (void)
8921 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8926 do_vfp_dp_conv_16 (void)
8928 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8933 do_vfp_sp_conv_32 (void)
8935 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8940 do_vfp_dp_conv_32 (void)
8942 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8946 /* FPA instructions. Also in a logical order. */
8951 inst.instruction |= inst.operands[0].reg << 16;
8952 inst.instruction |= inst.operands[1].reg;
8956 do_fpa_ldmstm (void)
8958 inst.instruction |= inst.operands[0].reg << 12;
8959 switch (inst.operands[1].imm)
8961 case 1: inst.instruction |= CP_T_X; break;
8962 case 2: inst.instruction |= CP_T_Y; break;
8963 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8968 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8970 /* The instruction specified "ea" or "fd", so we can only accept
8971 [Rn]{!}. The instruction does not really support stacking or
8972 unstacking, so we have to emulate these by setting appropriate
8973 bits and offsets. */
8974 constraint (inst.reloc.exp.X_op != O_constant
8975 || inst.reloc.exp.X_add_number != 0,
8976 _("this instruction does not support indexing"));
8978 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8979 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8981 if (!(inst.instruction & INDEX_UP))
8982 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8984 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8986 inst.operands[2].preind = 0;
8987 inst.operands[2].postind = 1;
8991 encode_arm_cp_address (2, TRUE, TRUE, 0);
8994 /* iWMMXt instructions: strictly in alphabetical order. */
8997 do_iwmmxt_tandorc (void)
8999 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9003 do_iwmmxt_textrc (void)
9005 inst.instruction |= inst.operands[0].reg << 12;
9006 inst.instruction |= inst.operands[1].imm;
9010 do_iwmmxt_textrm (void)
9012 inst.instruction |= inst.operands[0].reg << 12;
9013 inst.instruction |= inst.operands[1].reg << 16;
9014 inst.instruction |= inst.operands[2].imm;
9018 do_iwmmxt_tinsr (void)
9020 inst.instruction |= inst.operands[0].reg << 16;
9021 inst.instruction |= inst.operands[1].reg << 12;
9022 inst.instruction |= inst.operands[2].imm;
9026 do_iwmmxt_tmia (void)
9028 inst.instruction |= inst.operands[0].reg << 5;
9029 inst.instruction |= inst.operands[1].reg;
9030 inst.instruction |= inst.operands[2].reg << 12;
9034 do_iwmmxt_waligni (void)
9036 inst.instruction |= inst.operands[0].reg << 12;
9037 inst.instruction |= inst.operands[1].reg << 16;
9038 inst.instruction |= inst.operands[2].reg;
9039 inst.instruction |= inst.operands[3].imm << 20;
9043 do_iwmmxt_wmerge (void)
9045 inst.instruction |= inst.operands[0].reg << 12;
9046 inst.instruction |= inst.operands[1].reg << 16;
9047 inst.instruction |= inst.operands[2].reg;
9048 inst.instruction |= inst.operands[3].imm << 21;
9052 do_iwmmxt_wmov (void)
9054 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9055 inst.instruction |= inst.operands[0].reg << 12;
9056 inst.instruction |= inst.operands[1].reg << 16;
9057 inst.instruction |= inst.operands[1].reg;
9061 do_iwmmxt_wldstbh (void)
9064 inst.instruction |= inst.operands[0].reg << 12;
9066 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9068 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9069 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9073 do_iwmmxt_wldstw (void)
9075 /* RIWR_RIWC clears .isreg for a control register. */
9076 if (!inst.operands[0].isreg)
9078 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9079 inst.instruction |= 0xf0000000;
9082 inst.instruction |= inst.operands[0].reg << 12;
9083 encode_arm_cp_address (1, TRUE, TRUE, 0);
9087 do_iwmmxt_wldstd (void)
9089 inst.instruction |= inst.operands[0].reg << 12;
9090 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9091 && inst.operands[1].immisreg)
9093 inst.instruction &= ~0x1a000ff;
9094 inst.instruction |= (0xf << 28);
9095 if (inst.operands[1].preind)
9096 inst.instruction |= PRE_INDEX;
9097 if (!inst.operands[1].negative)
9098 inst.instruction |= INDEX_UP;
9099 if (inst.operands[1].writeback)
9100 inst.instruction |= WRITE_BACK;
9101 inst.instruction |= inst.operands[1].reg << 16;
9102 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9103 inst.instruction |= inst.operands[1].imm;
9106 encode_arm_cp_address (1, TRUE, FALSE, 0);
9110 do_iwmmxt_wshufh (void)
9112 inst.instruction |= inst.operands[0].reg << 12;
9113 inst.instruction |= inst.operands[1].reg << 16;
9114 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9115 inst.instruction |= (inst.operands[2].imm & 0x0f);
9119 do_iwmmxt_wzero (void)
9121 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9122 inst.instruction |= inst.operands[0].reg;
9123 inst.instruction |= inst.operands[0].reg << 12;
9124 inst.instruction |= inst.operands[0].reg << 16;
9128 do_iwmmxt_wrwrwr_or_imm5 (void)
9130 if (inst.operands[2].isreg)
9133 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9134 _("immediate operand requires iWMMXt2"));
9136 if (inst.operands[2].imm == 0)
9138 switch ((inst.instruction >> 20) & 0xf)
9144 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9145 inst.operands[2].imm = 16;
9146 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9152 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9153 inst.operands[2].imm = 32;
9154 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9161 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9163 wrn = (inst.instruction >> 16) & 0xf;
9164 inst.instruction &= 0xff0fff0f;
9165 inst.instruction |= wrn;
9166 /* Bail out here; the instruction is now assembled. */
9171 /* Map 32 -> 0, etc. */
9172 inst.operands[2].imm &= 0x1f;
9173 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9177 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9178 operations first, then control, shift, and load/store. */
9180 /* Insns like "foo X,Y,Z". */
9183 do_mav_triple (void)
9185 inst.instruction |= inst.operands[0].reg << 16;
9186 inst.instruction |= inst.operands[1].reg;
9187 inst.instruction |= inst.operands[2].reg << 12;
9190 /* Insns like "foo W,X,Y,Z".
9191 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9196 inst.instruction |= inst.operands[0].reg << 5;
9197 inst.instruction |= inst.operands[1].reg << 12;
9198 inst.instruction |= inst.operands[2].reg << 16;
9199 inst.instruction |= inst.operands[3].reg;
9202 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9206 inst.instruction |= inst.operands[1].reg << 12;
9209 /* Maverick shift immediate instructions.
9210 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9211 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9216 int imm = inst.operands[2].imm;
9218 inst.instruction |= inst.operands[0].reg << 12;
9219 inst.instruction |= inst.operands[1].reg << 16;
9221 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9222 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9223 Bit 4 should be 0. */
9224 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9226 inst.instruction |= imm;
9229 /* XScale instructions. Also sorted arithmetic before move. */
9231 /* Xscale multiply-accumulate (argument parse)
9234 MIAxycc acc0,Rm,Rs. */
9239 inst.instruction |= inst.operands[1].reg;
9240 inst.instruction |= inst.operands[2].reg << 12;
9243 /* Xscale move-accumulator-register (argument parse)
9245 MARcc acc0,RdLo,RdHi. */
9250 inst.instruction |= inst.operands[1].reg << 12;
9251 inst.instruction |= inst.operands[2].reg << 16;
9254 /* Xscale move-register-accumulator (argument parse)
9256 MRAcc RdLo,RdHi,acc0. */
9261 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9262 inst.instruction |= inst.operands[0].reg << 12;
9263 inst.instruction |= inst.operands[1].reg << 16;
9266 /* Encoding functions relevant only to Thumb. */
9268 /* inst.operands[i] is a shifted-register operand; encode
9269 it into inst.instruction in the format used by Thumb32. */
9272 encode_thumb32_shifted_operand (int i)
9274 unsigned int value = inst.reloc.exp.X_add_number;
9275 unsigned int shift = inst.operands[i].shift_kind;
9277 constraint (inst.operands[i].immisreg,
9278 _("shift by register not allowed in thumb mode"));
9279 inst.instruction |= inst.operands[i].reg;
9280 if (shift == SHIFT_RRX)
9281 inst.instruction |= SHIFT_ROR << 4;
9284 constraint (inst.reloc.exp.X_op != O_constant,
9285 _("expression too complex"));
9287 constraint (value > 32
9288 || (value == 32 && (shift == SHIFT_LSL
9289 || shift == SHIFT_ROR)),
9290 _("shift expression is too large"));
9294 else if (value == 32)
9297 inst.instruction |= shift << 4;
9298 inst.instruction |= (value & 0x1c) << 10;
9299 inst.instruction |= (value & 0x03) << 6;
9304 /* inst.operands[i] was set up by parse_address. Encode it into a
9305 Thumb32 format load or store instruction. Reject forms that cannot
9306 be used with such instructions. If is_t is true, reject forms that
9307 cannot be used with a T instruction; if is_d is true, reject forms
9308 that cannot be used with a D instruction. If it is a store insn,
9312 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9314 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9316 constraint (!inst.operands[i].isreg,
9317 _("Instruction does not support =N addresses"));
9319 inst.instruction |= inst.operands[i].reg << 16;
9320 if (inst.operands[i].immisreg)
9322 constraint (is_pc, BAD_PC_ADDRESSING);
9323 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9324 constraint (inst.operands[i].negative,
9325 _("Thumb does not support negative register indexing"));
9326 constraint (inst.operands[i].postind,
9327 _("Thumb does not support register post-indexing"));
9328 constraint (inst.operands[i].writeback,
9329 _("Thumb does not support register indexing with writeback"));
9330 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9331 _("Thumb supports only LSL in shifted register indexing"));
9333 inst.instruction |= inst.operands[i].imm;
9334 if (inst.operands[i].shifted)
9336 constraint (inst.reloc.exp.X_op != O_constant,
9337 _("expression too complex"));
9338 constraint (inst.reloc.exp.X_add_number < 0
9339 || inst.reloc.exp.X_add_number > 3,
9340 _("shift out of range"));
9341 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9343 inst.reloc.type = BFD_RELOC_UNUSED;
9345 else if (inst.operands[i].preind)
9347 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9348 constraint (is_t && inst.operands[i].writeback,
9349 _("cannot use writeback with this instruction"));
9350 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9351 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9355 inst.instruction |= 0x01000000;
9356 if (inst.operands[i].writeback)
9357 inst.instruction |= 0x00200000;
9361 inst.instruction |= 0x00000c00;
9362 if (inst.operands[i].writeback)
9363 inst.instruction |= 0x00000100;
9365 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9367 else if (inst.operands[i].postind)
9369 gas_assert (inst.operands[i].writeback);
9370 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9371 constraint (is_t, _("cannot use post-indexing with this instruction"));
9374 inst.instruction |= 0x00200000;
9376 inst.instruction |= 0x00000900;
9377 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9379 else /* unindexed - only for coprocessor */
9380 inst.error = _("instruction does not accept unindexed addressing");
9383 /* Table of Thumb instructions which exist in both 16- and 32-bit
9384 encodings (the latter only in post-V6T2 cores). The index is the
9385 value used in the insns table below. When there is more than one
9386 possible 16-bit encoding for the instruction, this table always
9388 Also contains several pseudo-instructions used during relaxation. */
9389 #define T16_32_TAB \
9390 X(_adc, 4140, eb400000), \
9391 X(_adcs, 4140, eb500000), \
9392 X(_add, 1c00, eb000000), \
9393 X(_adds, 1c00, eb100000), \
9394 X(_addi, 0000, f1000000), \
9395 X(_addis, 0000, f1100000), \
9396 X(_add_pc,000f, f20f0000), \
9397 X(_add_sp,000d, f10d0000), \
9398 X(_adr, 000f, f20f0000), \
9399 X(_and, 4000, ea000000), \
9400 X(_ands, 4000, ea100000), \
9401 X(_asr, 1000, fa40f000), \
9402 X(_asrs, 1000, fa50f000), \
9403 X(_b, e000, f000b000), \
9404 X(_bcond, d000, f0008000), \
9405 X(_bic, 4380, ea200000), \
9406 X(_bics, 4380, ea300000), \
9407 X(_cmn, 42c0, eb100f00), \
9408 X(_cmp, 2800, ebb00f00), \
9409 X(_cpsie, b660, f3af8400), \
9410 X(_cpsid, b670, f3af8600), \
9411 X(_cpy, 4600, ea4f0000), \
9412 X(_dec_sp,80dd, f1ad0d00), \
9413 X(_eor, 4040, ea800000), \
9414 X(_eors, 4040, ea900000), \
9415 X(_inc_sp,00dd, f10d0d00), \
9416 X(_ldmia, c800, e8900000), \
9417 X(_ldr, 6800, f8500000), \
9418 X(_ldrb, 7800, f8100000), \
9419 X(_ldrh, 8800, f8300000), \
9420 X(_ldrsb, 5600, f9100000), \
9421 X(_ldrsh, 5e00, f9300000), \
9422 X(_ldr_pc,4800, f85f0000), \
9423 X(_ldr_pc2,4800, f85f0000), \
9424 X(_ldr_sp,9800, f85d0000), \
9425 X(_lsl, 0000, fa00f000), \
9426 X(_lsls, 0000, fa10f000), \
9427 X(_lsr, 0800, fa20f000), \
9428 X(_lsrs, 0800, fa30f000), \
9429 X(_mov, 2000, ea4f0000), \
9430 X(_movs, 2000, ea5f0000), \
9431 X(_mul, 4340, fb00f000), \
9432 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9433 X(_mvn, 43c0, ea6f0000), \
9434 X(_mvns, 43c0, ea7f0000), \
9435 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9436 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9437 X(_orr, 4300, ea400000), \
9438 X(_orrs, 4300, ea500000), \
9439 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9440 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9441 X(_rev, ba00, fa90f080), \
9442 X(_rev16, ba40, fa90f090), \
9443 X(_revsh, bac0, fa90f0b0), \
9444 X(_ror, 41c0, fa60f000), \
9445 X(_rors, 41c0, fa70f000), \
9446 X(_sbc, 4180, eb600000), \
9447 X(_sbcs, 4180, eb700000), \
9448 X(_stmia, c000, e8800000), \
9449 X(_str, 6000, f8400000), \
9450 X(_strb, 7000, f8000000), \
9451 X(_strh, 8000, f8200000), \
9452 X(_str_sp,9000, f84d0000), \
9453 X(_sub, 1e00, eba00000), \
9454 X(_subs, 1e00, ebb00000), \
9455 X(_subi, 8000, f1a00000), \
9456 X(_subis, 8000, f1b00000), \
9457 X(_sxtb, b240, fa4ff080), \
9458 X(_sxth, b200, fa0ff080), \
9459 X(_tst, 4200, ea100f00), \
9460 X(_uxtb, b2c0, fa5ff080), \
9461 X(_uxth, b280, fa1ff080), \
9462 X(_nop, bf00, f3af8000), \
9463 X(_yield, bf10, f3af8001), \
9464 X(_wfe, bf20, f3af8002), \
9465 X(_wfi, bf30, f3af8003), \
9466 X(_sev, bf40, f3af8004),
9468 /* To catch errors in encoding functions, the codes are all offset by
9469 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9470 as 16-bit instructions. */
9471 #define X(a,b,c) T_MNEM##a
9472 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9475 #define X(a,b,c) 0x##b
9476 static const unsigned short thumb_op16[] = { T16_32_TAB };
9477 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9480 #define X(a,b,c) 0x##c
9481 static const unsigned int thumb_op32[] = { T16_32_TAB };
9482 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9483 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9487 /* Thumb instruction encoders, in alphabetical order. */
9492 do_t_add_sub_w (void)
9496 Rd = inst.operands[0].reg;
9497 Rn = inst.operands[1].reg;
9499 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9500 is the SP-{plus,minus}-immediate form of the instruction. */
9502 constraint (Rd == REG_PC, BAD_PC);
9504 reject_bad_reg (Rd);
9506 inst.instruction |= (Rn << 16) | (Rd << 8);
9507 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9510 /* Parse an add or subtract instruction. We get here with inst.instruction
9511 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9518 Rd = inst.operands[0].reg;
9519 Rs = (inst.operands[1].present
9520 ? inst.operands[1].reg /* Rd, Rs, foo */
9521 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9524 set_it_insn_type_last ();
9532 flags = (inst.instruction == T_MNEM_adds
9533 || inst.instruction == T_MNEM_subs);
9535 narrow = !in_it_block ();
9537 narrow = in_it_block ();
9538 if (!inst.operands[2].isreg)
9542 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9544 add = (inst.instruction == T_MNEM_add
9545 || inst.instruction == T_MNEM_adds);
9547 if (inst.size_req != 4)
9549 /* Attempt to use a narrow opcode, with relaxation if
9551 if (Rd == REG_SP && Rs == REG_SP && !flags)
9552 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9553 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9554 opcode = T_MNEM_add_sp;
9555 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9556 opcode = T_MNEM_add_pc;
9557 else if (Rd <= 7 && Rs <= 7 && narrow)
9560 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9562 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9566 inst.instruction = THUMB_OP16(opcode);
9567 inst.instruction |= (Rd << 4) | Rs;
9568 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9569 if (inst.size_req != 2)
9570 inst.relax = opcode;
9573 constraint (inst.size_req == 2, BAD_HIREG);
9575 if (inst.size_req == 4
9576 || (inst.size_req != 2 && !opcode))
9580 constraint (add, BAD_PC);
9581 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9582 _("only SUBS PC, LR, #const allowed"));
9583 constraint (inst.reloc.exp.X_op != O_constant,
9584 _("expression too complex"));
9585 constraint (inst.reloc.exp.X_add_number < 0
9586 || inst.reloc.exp.X_add_number > 0xff,
9587 _("immediate value out of range"));
9588 inst.instruction = T2_SUBS_PC_LR
9589 | inst.reloc.exp.X_add_number;
9590 inst.reloc.type = BFD_RELOC_UNUSED;
9593 else if (Rs == REG_PC)
9595 /* Always use addw/subw. */
9596 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9597 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9601 inst.instruction = THUMB_OP32 (inst.instruction);
9602 inst.instruction = (inst.instruction & 0xe1ffffff)
9605 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9607 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9609 inst.instruction |= Rd << 8;
9610 inst.instruction |= Rs << 16;
9615 unsigned int value = inst.reloc.exp.X_add_number;
9616 unsigned int shift = inst.operands[2].shift_kind;
9618 Rn = inst.operands[2].reg;
9619 /* See if we can do this with a 16-bit instruction. */
9620 if (!inst.operands[2].shifted && inst.size_req != 4)
9622 if (Rd > 7 || Rs > 7 || Rn > 7)
9627 inst.instruction = ((inst.instruction == T_MNEM_adds
9628 || inst.instruction == T_MNEM_add)
9631 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9635 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9637 /* Thumb-1 cores (except v6-M) require at least one high
9638 register in a narrow non flag setting add. */
9639 if (Rd > 7 || Rn > 7
9640 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9641 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9648 inst.instruction = T_OPCODE_ADD_HI;
9649 inst.instruction |= (Rd & 8) << 4;
9650 inst.instruction |= (Rd & 7);
9651 inst.instruction |= Rn << 3;
9657 constraint (Rd == REG_PC, BAD_PC);
9658 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9659 constraint (Rs == REG_PC, BAD_PC);
9660 reject_bad_reg (Rn);
9662 /* If we get here, it can't be done in 16 bits. */
9663 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9664 _("shift must be constant"));
9665 inst.instruction = THUMB_OP32 (inst.instruction);
9666 inst.instruction |= Rd << 8;
9667 inst.instruction |= Rs << 16;
9668 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9669 _("shift value over 3 not allowed in thumb mode"));
9670 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9671 _("only LSL shift allowed in thumb mode"));
9672 encode_thumb32_shifted_operand (2);
9677 constraint (inst.instruction == T_MNEM_adds
9678 || inst.instruction == T_MNEM_subs,
9681 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9683 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9684 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9687 inst.instruction = (inst.instruction == T_MNEM_add
9689 inst.instruction |= (Rd << 4) | Rs;
9690 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9694 Rn = inst.operands[2].reg;
9695 constraint (inst.operands[2].shifted, _("unshifted register required"));
9697 /* We now have Rd, Rs, and Rn set to registers. */
9698 if (Rd > 7 || Rs > 7 || Rn > 7)
9700 /* Can't do this for SUB. */
9701 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9702 inst.instruction = T_OPCODE_ADD_HI;
9703 inst.instruction |= (Rd & 8) << 4;
9704 inst.instruction |= (Rd & 7);
9706 inst.instruction |= Rn << 3;
9708 inst.instruction |= Rs << 3;
9710 constraint (1, _("dest must overlap one source register"));
9714 inst.instruction = (inst.instruction == T_MNEM_add
9715 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9716 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9726 Rd = inst.operands[0].reg;
9727 reject_bad_reg (Rd);
9729 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9731 /* Defer to section relaxation. */
9732 inst.relax = inst.instruction;
9733 inst.instruction = THUMB_OP16 (inst.instruction);
9734 inst.instruction |= Rd << 4;
9736 else if (unified_syntax && inst.size_req != 2)
9738 /* Generate a 32-bit opcode. */
9739 inst.instruction = THUMB_OP32 (inst.instruction);
9740 inst.instruction |= Rd << 8;
9741 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9742 inst.reloc.pc_rel = 1;
9746 /* Generate a 16-bit opcode. */
9747 inst.instruction = THUMB_OP16 (inst.instruction);
9748 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9749 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9750 inst.reloc.pc_rel = 1;
9752 inst.instruction |= Rd << 4;
9756 /* Arithmetic instructions for which there is just one 16-bit
9757 instruction encoding, and it allows only two low registers.
9758 For maximal compatibility with ARM syntax, we allow three register
9759 operands even when Thumb-32 instructions are not available, as long
9760 as the first two are identical. For instance, both "sbc r0,r1" and
9761 "sbc r0,r0,r1" are allowed. */
9767 Rd = inst.operands[0].reg;
9768 Rs = (inst.operands[1].present
9769 ? inst.operands[1].reg /* Rd, Rs, foo */
9770 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9771 Rn = inst.operands[2].reg;
9773 reject_bad_reg (Rd);
9774 reject_bad_reg (Rs);
9775 if (inst.operands[2].isreg)
9776 reject_bad_reg (Rn);
9780 if (!inst.operands[2].isreg)
9782 /* For an immediate, we always generate a 32-bit opcode;
9783 section relaxation will shrink it later if possible. */
9784 inst.instruction = THUMB_OP32 (inst.instruction);
9785 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9786 inst.instruction |= Rd << 8;
9787 inst.instruction |= Rs << 16;
9788 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9794 /* See if we can do this with a 16-bit instruction. */
9795 if (THUMB_SETS_FLAGS (inst.instruction))
9796 narrow = !in_it_block ();
9798 narrow = in_it_block ();
9800 if (Rd > 7 || Rn > 7 || Rs > 7)
9802 if (inst.operands[2].shifted)
9804 if (inst.size_req == 4)
9810 inst.instruction = THUMB_OP16 (inst.instruction);
9811 inst.instruction |= Rd;
9812 inst.instruction |= Rn << 3;
9816 /* If we get here, it can't be done in 16 bits. */
9817 constraint (inst.operands[2].shifted
9818 && inst.operands[2].immisreg,
9819 _("shift must be constant"));
9820 inst.instruction = THUMB_OP32 (inst.instruction);
9821 inst.instruction |= Rd << 8;
9822 inst.instruction |= Rs << 16;
9823 encode_thumb32_shifted_operand (2);
9828 /* On its face this is a lie - the instruction does set the
9829 flags. However, the only supported mnemonic in this mode
9831 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9833 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9834 _("unshifted register required"));
9835 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9836 constraint (Rd != Rs,
9837 _("dest and source1 must be the same register"));
9839 inst.instruction = THUMB_OP16 (inst.instruction);
9840 inst.instruction |= Rd;
9841 inst.instruction |= Rn << 3;
9845 /* Similarly, but for instructions where the arithmetic operation is
9846 commutative, so we can allow either of them to be different from
9847 the destination operand in a 16-bit instruction. For instance, all
9848 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9855 Rd = inst.operands[0].reg;
9856 Rs = (inst.operands[1].present
9857 ? inst.operands[1].reg /* Rd, Rs, foo */
9858 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9859 Rn = inst.operands[2].reg;
9861 reject_bad_reg (Rd);
9862 reject_bad_reg (Rs);
9863 if (inst.operands[2].isreg)
9864 reject_bad_reg (Rn);
9868 if (!inst.operands[2].isreg)
9870 /* For an immediate, we always generate a 32-bit opcode;
9871 section relaxation will shrink it later if possible. */
9872 inst.instruction = THUMB_OP32 (inst.instruction);
9873 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9874 inst.instruction |= Rd << 8;
9875 inst.instruction |= Rs << 16;
9876 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9882 /* See if we can do this with a 16-bit instruction. */
9883 if (THUMB_SETS_FLAGS (inst.instruction))
9884 narrow = !in_it_block ();
9886 narrow = in_it_block ();
9888 if (Rd > 7 || Rn > 7 || Rs > 7)
9890 if (inst.operands[2].shifted)
9892 if (inst.size_req == 4)
9899 inst.instruction = THUMB_OP16 (inst.instruction);
9900 inst.instruction |= Rd;
9901 inst.instruction |= Rn << 3;
9906 inst.instruction = THUMB_OP16 (inst.instruction);
9907 inst.instruction |= Rd;
9908 inst.instruction |= Rs << 3;
9913 /* If we get here, it can't be done in 16 bits. */
9914 constraint (inst.operands[2].shifted
9915 && inst.operands[2].immisreg,
9916 _("shift must be constant"));
9917 inst.instruction = THUMB_OP32 (inst.instruction);
9918 inst.instruction |= Rd << 8;
9919 inst.instruction |= Rs << 16;
9920 encode_thumb32_shifted_operand (2);
9925 /* On its face this is a lie - the instruction does set the
9926 flags. However, the only supported mnemonic in this mode
9928 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9930 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9931 _("unshifted register required"));
9932 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9934 inst.instruction = THUMB_OP16 (inst.instruction);
9935 inst.instruction |= Rd;
9938 inst.instruction |= Rn << 3;
9940 inst.instruction |= Rs << 3;
9942 constraint (1, _("dest must overlap one source register"));
9949 if (inst.operands[0].present)
9951 constraint ((inst.instruction & 0xf0) != 0x40
9952 && inst.operands[0].imm > 0xf
9953 && inst.operands[0].imm < 0x0,
9954 _("bad barrier type"));
9955 inst.instruction |= inst.operands[0].imm;
9958 inst.instruction |= 0xf;
9965 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9966 constraint (msb > 32, _("bit-field extends past end of register"));
9967 /* The instruction encoding stores the LSB and MSB,
9968 not the LSB and width. */
9969 Rd = inst.operands[0].reg;
9970 reject_bad_reg (Rd);
9971 inst.instruction |= Rd << 8;
9972 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9973 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9974 inst.instruction |= msb - 1;
9983 Rd = inst.operands[0].reg;
9984 reject_bad_reg (Rd);
9986 /* #0 in second position is alternative syntax for bfc, which is
9987 the same instruction but with REG_PC in the Rm field. */
9988 if (!inst.operands[1].isreg)
9992 Rn = inst.operands[1].reg;
9993 reject_bad_reg (Rn);
9996 msb = inst.operands[2].imm + inst.operands[3].imm;
9997 constraint (msb > 32, _("bit-field extends past end of register"));
9998 /* The instruction encoding stores the LSB and MSB,
9999 not the LSB and width. */
10000 inst.instruction |= Rd << 8;
10001 inst.instruction |= Rn << 16;
10002 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10003 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10004 inst.instruction |= msb - 1;
10012 Rd = inst.operands[0].reg;
10013 Rn = inst.operands[1].reg;
10015 reject_bad_reg (Rd);
10016 reject_bad_reg (Rn);
10018 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10019 _("bit-field extends past end of register"));
10020 inst.instruction |= Rd << 8;
10021 inst.instruction |= Rn << 16;
10022 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10023 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10024 inst.instruction |= inst.operands[3].imm - 1;
10027 /* ARM V5 Thumb BLX (argument parse)
10028 BLX <target_addr> which is BLX(1)
10029 BLX <Rm> which is BLX(2)
10030 Unfortunately, there are two different opcodes for this mnemonic.
10031 So, the insns[].value is not used, and the code here zaps values
10032 into inst.instruction.
10034 ??? How to take advantage of the additional two bits of displacement
10035 available in Thumb32 mode? Need new relocation? */
10040 set_it_insn_type_last ();
10042 if (inst.operands[0].isreg)
10044 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10045 /* We have a register, so this is BLX(2). */
10046 inst.instruction |= inst.operands[0].reg << 3;
10050 /* No register. This must be BLX(1). */
10051 inst.instruction = 0xf000e800;
10052 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10064 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10066 if (in_it_block ())
10068 /* Conditional branches inside IT blocks are encoded as unconditional
10070 cond = COND_ALWAYS;
10075 if (cond != COND_ALWAYS)
10076 opcode = T_MNEM_bcond;
10078 opcode = inst.instruction;
10081 && (inst.size_req == 4
10082 || (inst.size_req != 2
10083 && (inst.operands[0].hasreloc
10084 || inst.reloc.exp.X_op == O_constant))))
10086 inst.instruction = THUMB_OP32(opcode);
10087 if (cond == COND_ALWAYS)
10088 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10091 gas_assert (cond != 0xF);
10092 inst.instruction |= cond << 22;
10093 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10098 inst.instruction = THUMB_OP16(opcode);
10099 if (cond == COND_ALWAYS)
10100 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10103 inst.instruction |= cond << 8;
10104 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10106 /* Allow section relaxation. */
10107 if (unified_syntax && inst.size_req != 2)
10108 inst.relax = opcode;
10110 inst.reloc.type = reloc;
10111 inst.reloc.pc_rel = 1;
10117 constraint (inst.cond != COND_ALWAYS,
10118 _("instruction is always unconditional"));
10119 if (inst.operands[0].present)
10121 constraint (inst.operands[0].imm > 255,
10122 _("immediate value out of range"));
10123 inst.instruction |= inst.operands[0].imm;
10124 set_it_insn_type (NEUTRAL_IT_INSN);
10129 do_t_branch23 (void)
10131 set_it_insn_type_last ();
10132 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10134 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10135 this file. We used to simply ignore the PLT reloc type here --
10136 the branch encoding is now needed to deal with TLSCALL relocs.
10137 So if we see a PLT reloc now, put it back to how it used to be to
10138 keep the preexisting behaviour. */
10139 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10140 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10142 #if defined(OBJ_COFF)
10143 /* If the destination of the branch is a defined symbol which does not have
10144 the THUMB_FUNC attribute, then we must be calling a function which has
10145 the (interfacearm) attribute. We look for the Thumb entry point to that
10146 function and change the branch to refer to that function instead. */
10147 if ( inst.reloc.exp.X_op == O_symbol
10148 && inst.reloc.exp.X_add_symbol != NULL
10149 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10150 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10151 inst.reloc.exp.X_add_symbol =
10152 find_real_start (inst.reloc.exp.X_add_symbol);
10159 set_it_insn_type_last ();
10160 inst.instruction |= inst.operands[0].reg << 3;
10161 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10162 should cause the alignment to be checked once it is known. This is
10163 because BX PC only works if the instruction is word aligned. */
10171 set_it_insn_type_last ();
10172 Rm = inst.operands[0].reg;
10173 reject_bad_reg (Rm);
10174 inst.instruction |= Rm << 16;
10183 Rd = inst.operands[0].reg;
10184 Rm = inst.operands[1].reg;
10186 reject_bad_reg (Rd);
10187 reject_bad_reg (Rm);
10189 inst.instruction |= Rd << 8;
10190 inst.instruction |= Rm << 16;
10191 inst.instruction |= Rm;
10197 set_it_insn_type (OUTSIDE_IT_INSN);
10198 inst.instruction |= inst.operands[0].imm;
10204 set_it_insn_type (OUTSIDE_IT_INSN);
10206 && (inst.operands[1].present || inst.size_req == 4)
10207 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10209 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10210 inst.instruction = 0xf3af8000;
10211 inst.instruction |= imod << 9;
10212 inst.instruction |= inst.operands[0].imm << 5;
10213 if (inst.operands[1].present)
10214 inst.instruction |= 0x100 | inst.operands[1].imm;
10218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10219 && (inst.operands[0].imm & 4),
10220 _("selected processor does not support 'A' form "
10221 "of this instruction"));
10222 constraint (inst.operands[1].present || inst.size_req == 4,
10223 _("Thumb does not support the 2-argument "
10224 "form of this instruction"));
10225 inst.instruction |= inst.operands[0].imm;
10229 /* THUMB CPY instruction (argument parse). */
10234 if (inst.size_req == 4)
10236 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10237 inst.instruction |= inst.operands[0].reg << 8;
10238 inst.instruction |= inst.operands[1].reg;
10242 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10243 inst.instruction |= (inst.operands[0].reg & 0x7);
10244 inst.instruction |= inst.operands[1].reg << 3;
10251 set_it_insn_type (OUTSIDE_IT_INSN);
10252 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10253 inst.instruction |= inst.operands[0].reg;
10254 inst.reloc.pc_rel = 1;
10255 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10261 inst.instruction |= inst.operands[0].imm;
10267 unsigned Rd, Rn, Rm;
10269 Rd = inst.operands[0].reg;
10270 Rn = (inst.operands[1].present
10271 ? inst.operands[1].reg : Rd);
10272 Rm = inst.operands[2].reg;
10274 reject_bad_reg (Rd);
10275 reject_bad_reg (Rn);
10276 reject_bad_reg (Rm);
10278 inst.instruction |= Rd << 8;
10279 inst.instruction |= Rn << 16;
10280 inst.instruction |= Rm;
10286 if (unified_syntax && inst.size_req == 4)
10287 inst.instruction = THUMB_OP32 (inst.instruction);
10289 inst.instruction = THUMB_OP16 (inst.instruction);
10295 unsigned int cond = inst.operands[0].imm;
10297 set_it_insn_type (IT_INSN);
10298 now_it.mask = (inst.instruction & 0xf) | 0x10;
10301 /* If the condition is a negative condition, invert the mask. */
10302 if ((cond & 0x1) == 0x0)
10304 unsigned int mask = inst.instruction & 0x000f;
10306 if ((mask & 0x7) == 0)
10307 /* no conversion needed */;
10308 else if ((mask & 0x3) == 0)
10310 else if ((mask & 0x1) == 0)
10315 inst.instruction &= 0xfff0;
10316 inst.instruction |= mask;
10319 inst.instruction |= cond << 4;
10322 /* Helper function used for both push/pop and ldm/stm. */
10324 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10328 load = (inst.instruction & (1 << 20)) != 0;
10330 if (mask & (1 << 13))
10331 inst.error = _("SP not allowed in register list");
10333 if ((mask & (1 << base)) != 0
10335 inst.error = _("having the base register in the register list when "
10336 "using write back is UNPREDICTABLE");
10340 if (mask & (1 << 15))
10342 if (mask & (1 << 14))
10343 inst.error = _("LR and PC should not both be in register list");
10345 set_it_insn_type_last ();
10350 if (mask & (1 << 15))
10351 inst.error = _("PC not allowed in register list");
10354 if ((mask & (mask - 1)) == 0)
10356 /* Single register transfers implemented as str/ldr. */
10359 if (inst.instruction & (1 << 23))
10360 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10362 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10366 if (inst.instruction & (1 << 23))
10367 inst.instruction = 0x00800000; /* ia -> [base] */
10369 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10372 inst.instruction |= 0xf8400000;
10374 inst.instruction |= 0x00100000;
10376 mask = ffs (mask) - 1;
10379 else if (writeback)
10380 inst.instruction |= WRITE_BACK;
10382 inst.instruction |= mask;
10383 inst.instruction |= base << 16;
10389 /* This really doesn't seem worth it. */
10390 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10391 _("expression too complex"));
10392 constraint (inst.operands[1].writeback,
10393 _("Thumb load/store multiple does not support {reglist}^"));
10395 if (unified_syntax)
10397 bfd_boolean narrow;
10401 /* See if we can use a 16-bit instruction. */
10402 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10403 && inst.size_req != 4
10404 && !(inst.operands[1].imm & ~0xff))
10406 mask = 1 << inst.operands[0].reg;
10408 if (inst.operands[0].reg <= 7)
10410 if (inst.instruction == T_MNEM_stmia
10411 ? inst.operands[0].writeback
10412 : (inst.operands[0].writeback
10413 == !(inst.operands[1].imm & mask)))
10415 if (inst.instruction == T_MNEM_stmia
10416 && (inst.operands[1].imm & mask)
10417 && (inst.operands[1].imm & (mask - 1)))
10418 as_warn (_("value stored for r%d is UNKNOWN"),
10419 inst.operands[0].reg);
10421 inst.instruction = THUMB_OP16 (inst.instruction);
10422 inst.instruction |= inst.operands[0].reg << 8;
10423 inst.instruction |= inst.operands[1].imm;
10426 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10428 /* This means 1 register in reg list one of 3 situations:
10429 1. Instruction is stmia, but without writeback.
10430 2. lmdia without writeback, but with Rn not in
10432 3. ldmia with writeback, but with Rn in reglist.
10433 Case 3 is UNPREDICTABLE behaviour, so we handle
10434 case 1 and 2 which can be converted into a 16-bit
10435 str or ldr. The SP cases are handled below. */
10436 unsigned long opcode;
10437 /* First, record an error for Case 3. */
10438 if (inst.operands[1].imm & mask
10439 && inst.operands[0].writeback)
10441 _("having the base register in the register list when "
10442 "using write back is UNPREDICTABLE");
10444 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10446 inst.instruction = THUMB_OP16 (opcode);
10447 inst.instruction |= inst.operands[0].reg << 3;
10448 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10452 else if (inst.operands[0] .reg == REG_SP)
10454 if (inst.operands[0].writeback)
10457 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10458 ? T_MNEM_push : T_MNEM_pop);
10459 inst.instruction |= inst.operands[1].imm;
10462 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10465 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10466 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10467 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10475 if (inst.instruction < 0xffff)
10476 inst.instruction = THUMB_OP32 (inst.instruction);
10478 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10479 inst.operands[0].writeback);
10484 constraint (inst.operands[0].reg > 7
10485 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10486 constraint (inst.instruction != T_MNEM_ldmia
10487 && inst.instruction != T_MNEM_stmia,
10488 _("Thumb-2 instruction only valid in unified syntax"));
10489 if (inst.instruction == T_MNEM_stmia)
10491 if (!inst.operands[0].writeback)
10492 as_warn (_("this instruction will write back the base register"));
10493 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10494 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10495 as_warn (_("value stored for r%d is UNKNOWN"),
10496 inst.operands[0].reg);
10500 if (!inst.operands[0].writeback
10501 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10502 as_warn (_("this instruction will write back the base register"));
10503 else if (inst.operands[0].writeback
10504 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10505 as_warn (_("this instruction will not write back the base register"));
10508 inst.instruction = THUMB_OP16 (inst.instruction);
10509 inst.instruction |= inst.operands[0].reg << 8;
10510 inst.instruction |= inst.operands[1].imm;
10517 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10518 || inst.operands[1].postind || inst.operands[1].writeback
10519 || inst.operands[1].immisreg || inst.operands[1].shifted
10520 || inst.operands[1].negative,
10523 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10525 inst.instruction |= inst.operands[0].reg << 12;
10526 inst.instruction |= inst.operands[1].reg << 16;
10527 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10533 if (!inst.operands[1].present)
10535 constraint (inst.operands[0].reg == REG_LR,
10536 _("r14 not allowed as first register "
10537 "when second register is omitted"));
10538 inst.operands[1].reg = inst.operands[0].reg + 1;
10540 constraint (inst.operands[0].reg == inst.operands[1].reg,
10543 inst.instruction |= inst.operands[0].reg << 12;
10544 inst.instruction |= inst.operands[1].reg << 8;
10545 inst.instruction |= inst.operands[2].reg << 16;
10551 unsigned long opcode;
10554 if (inst.operands[0].isreg
10555 && !inst.operands[0].preind
10556 && inst.operands[0].reg == REG_PC)
10557 set_it_insn_type_last ();
10559 opcode = inst.instruction;
10560 if (unified_syntax)
10562 if (!inst.operands[1].isreg)
10564 if (opcode <= 0xffff)
10565 inst.instruction = THUMB_OP32 (opcode);
10566 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10569 if (inst.operands[1].isreg
10570 && !inst.operands[1].writeback
10571 && !inst.operands[1].shifted && !inst.operands[1].postind
10572 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10573 && opcode <= 0xffff
10574 && inst.size_req != 4)
10576 /* Insn may have a 16-bit form. */
10577 Rn = inst.operands[1].reg;
10578 if (inst.operands[1].immisreg)
10580 inst.instruction = THUMB_OP16 (opcode);
10582 if (Rn <= 7 && inst.operands[1].imm <= 7)
10584 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10585 reject_bad_reg (inst.operands[1].imm);
10587 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10588 && opcode != T_MNEM_ldrsb)
10589 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10590 || (Rn == REG_SP && opcode == T_MNEM_str))
10597 if (inst.reloc.pc_rel)
10598 opcode = T_MNEM_ldr_pc2;
10600 opcode = T_MNEM_ldr_pc;
10604 if (opcode == T_MNEM_ldr)
10605 opcode = T_MNEM_ldr_sp;
10607 opcode = T_MNEM_str_sp;
10609 inst.instruction = inst.operands[0].reg << 8;
10613 inst.instruction = inst.operands[0].reg;
10614 inst.instruction |= inst.operands[1].reg << 3;
10616 inst.instruction |= THUMB_OP16 (opcode);
10617 if (inst.size_req == 2)
10618 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10620 inst.relax = opcode;
10624 /* Definitely a 32-bit variant. */
10626 /* Warning for Erratum 752419. */
10627 if (opcode == T_MNEM_ldr
10628 && inst.operands[0].reg == REG_SP
10629 && inst.operands[1].writeback == 1
10630 && !inst.operands[1].immisreg)
10632 if (no_cpu_selected ()
10633 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10634 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10635 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10636 as_warn (_("This instruction may be unpredictable "
10637 "if executed on M-profile cores "
10638 "with interrupts enabled."));
10641 /* Do some validations regarding addressing modes. */
10642 if (inst.operands[1].immisreg)
10643 reject_bad_reg (inst.operands[1].imm);
10645 constraint (inst.operands[1].writeback == 1
10646 && inst.operands[0].reg == inst.operands[1].reg,
10649 inst.instruction = THUMB_OP32 (opcode);
10650 inst.instruction |= inst.operands[0].reg << 12;
10651 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10652 check_ldr_r15_aligned ();
10656 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10658 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10660 /* Only [Rn,Rm] is acceptable. */
10661 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10662 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10663 || inst.operands[1].postind || inst.operands[1].shifted
10664 || inst.operands[1].negative,
10665 _("Thumb does not support this addressing mode"));
10666 inst.instruction = THUMB_OP16 (inst.instruction);
10670 inst.instruction = THUMB_OP16 (inst.instruction);
10671 if (!inst.operands[1].isreg)
10672 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10675 constraint (!inst.operands[1].preind
10676 || inst.operands[1].shifted
10677 || inst.operands[1].writeback,
10678 _("Thumb does not support this addressing mode"));
10679 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10681 constraint (inst.instruction & 0x0600,
10682 _("byte or halfword not valid for base register"));
10683 constraint (inst.operands[1].reg == REG_PC
10684 && !(inst.instruction & THUMB_LOAD_BIT),
10685 _("r15 based store not allowed"));
10686 constraint (inst.operands[1].immisreg,
10687 _("invalid base register for register offset"));
10689 if (inst.operands[1].reg == REG_PC)
10690 inst.instruction = T_OPCODE_LDR_PC;
10691 else if (inst.instruction & THUMB_LOAD_BIT)
10692 inst.instruction = T_OPCODE_LDR_SP;
10694 inst.instruction = T_OPCODE_STR_SP;
10696 inst.instruction |= inst.operands[0].reg << 8;
10697 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10701 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10702 if (!inst.operands[1].immisreg)
10704 /* Immediate offset. */
10705 inst.instruction |= inst.operands[0].reg;
10706 inst.instruction |= inst.operands[1].reg << 3;
10707 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10711 /* Register offset. */
10712 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10713 constraint (inst.operands[1].negative,
10714 _("Thumb does not support this addressing mode"));
10717 switch (inst.instruction)
10719 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10720 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10721 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10722 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10723 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10724 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10725 case 0x5600 /* ldrsb */:
10726 case 0x5e00 /* ldrsh */: break;
10730 inst.instruction |= inst.operands[0].reg;
10731 inst.instruction |= inst.operands[1].reg << 3;
10732 inst.instruction |= inst.operands[1].imm << 6;
10738 if (!inst.operands[1].present)
10740 inst.operands[1].reg = inst.operands[0].reg + 1;
10741 constraint (inst.operands[0].reg == REG_LR,
10742 _("r14 not allowed here"));
10743 constraint (inst.operands[0].reg == REG_R12,
10744 _("r12 not allowed here"));
10747 if (inst.operands[2].writeback
10748 && (inst.operands[0].reg == inst.operands[2].reg
10749 || inst.operands[1].reg == inst.operands[2].reg))
10750 as_warn (_("base register written back, and overlaps "
10751 "one of transfer registers"));
10753 inst.instruction |= inst.operands[0].reg << 12;
10754 inst.instruction |= inst.operands[1].reg << 8;
10755 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10761 inst.instruction |= inst.operands[0].reg << 12;
10762 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10768 unsigned Rd, Rn, Rm, Ra;
10770 Rd = inst.operands[0].reg;
10771 Rn = inst.operands[1].reg;
10772 Rm = inst.operands[2].reg;
10773 Ra = inst.operands[3].reg;
10775 reject_bad_reg (Rd);
10776 reject_bad_reg (Rn);
10777 reject_bad_reg (Rm);
10778 reject_bad_reg (Ra);
10780 inst.instruction |= Rd << 8;
10781 inst.instruction |= Rn << 16;
10782 inst.instruction |= Rm;
10783 inst.instruction |= Ra << 12;
10789 unsigned RdLo, RdHi, Rn, Rm;
10791 RdLo = inst.operands[0].reg;
10792 RdHi = inst.operands[1].reg;
10793 Rn = inst.operands[2].reg;
10794 Rm = inst.operands[3].reg;
10796 reject_bad_reg (RdLo);
10797 reject_bad_reg (RdHi);
10798 reject_bad_reg (Rn);
10799 reject_bad_reg (Rm);
10801 inst.instruction |= RdLo << 12;
10802 inst.instruction |= RdHi << 8;
10803 inst.instruction |= Rn << 16;
10804 inst.instruction |= Rm;
10808 do_t_mov_cmp (void)
10812 Rn = inst.operands[0].reg;
10813 Rm = inst.operands[1].reg;
10816 set_it_insn_type_last ();
10818 if (unified_syntax)
10820 int r0off = (inst.instruction == T_MNEM_mov
10821 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10822 unsigned long opcode;
10823 bfd_boolean narrow;
10824 bfd_boolean low_regs;
10826 low_regs = (Rn <= 7 && Rm <= 7);
10827 opcode = inst.instruction;
10828 if (in_it_block ())
10829 narrow = opcode != T_MNEM_movs;
10831 narrow = opcode != T_MNEM_movs || low_regs;
10832 if (inst.size_req == 4
10833 || inst.operands[1].shifted)
10836 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10837 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10838 && !inst.operands[1].shifted
10842 inst.instruction = T2_SUBS_PC_LR;
10846 if (opcode == T_MNEM_cmp)
10848 constraint (Rn == REG_PC, BAD_PC);
10851 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10853 warn_deprecated_sp (Rm);
10854 /* R15 was documented as a valid choice for Rm in ARMv6,
10855 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10856 tools reject R15, so we do too. */
10857 constraint (Rm == REG_PC, BAD_PC);
10860 reject_bad_reg (Rm);
10862 else if (opcode == T_MNEM_mov
10863 || opcode == T_MNEM_movs)
10865 if (inst.operands[1].isreg)
10867 if (opcode == T_MNEM_movs)
10869 reject_bad_reg (Rn);
10870 reject_bad_reg (Rm);
10874 /* This is mov.n. */
10875 if ((Rn == REG_SP || Rn == REG_PC)
10876 && (Rm == REG_SP || Rm == REG_PC))
10878 as_warn (_("Use of r%u as a source register is "
10879 "deprecated when r%u is the destination "
10880 "register."), Rm, Rn);
10885 /* This is mov.w. */
10886 constraint (Rn == REG_PC, BAD_PC);
10887 constraint (Rm == REG_PC, BAD_PC);
10888 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10892 reject_bad_reg (Rn);
10895 if (!inst.operands[1].isreg)
10897 /* Immediate operand. */
10898 if (!in_it_block () && opcode == T_MNEM_mov)
10900 if (low_regs && narrow)
10902 inst.instruction = THUMB_OP16 (opcode);
10903 inst.instruction |= Rn << 8;
10904 if (inst.size_req == 2)
10905 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10907 inst.relax = opcode;
10911 inst.instruction = THUMB_OP32 (inst.instruction);
10912 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10913 inst.instruction |= Rn << r0off;
10914 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10917 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10918 && (inst.instruction == T_MNEM_mov
10919 || inst.instruction == T_MNEM_movs))
10921 /* Register shifts are encoded as separate shift instructions. */
10922 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10924 if (in_it_block ())
10929 if (inst.size_req == 4)
10932 if (!low_regs || inst.operands[1].imm > 7)
10938 switch (inst.operands[1].shift_kind)
10941 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10944 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10947 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10950 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10956 inst.instruction = opcode;
10959 inst.instruction |= Rn;
10960 inst.instruction |= inst.operands[1].imm << 3;
10965 inst.instruction |= CONDS_BIT;
10967 inst.instruction |= Rn << 8;
10968 inst.instruction |= Rm << 16;
10969 inst.instruction |= inst.operands[1].imm;
10974 /* Some mov with immediate shift have narrow variants.
10975 Register shifts are handled above. */
10976 if (low_regs && inst.operands[1].shifted
10977 && (inst.instruction == T_MNEM_mov
10978 || inst.instruction == T_MNEM_movs))
10980 if (in_it_block ())
10981 narrow = (inst.instruction == T_MNEM_mov);
10983 narrow = (inst.instruction == T_MNEM_movs);
10988 switch (inst.operands[1].shift_kind)
10990 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10991 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10992 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10993 default: narrow = FALSE; break;
10999 inst.instruction |= Rn;
11000 inst.instruction |= Rm << 3;
11001 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11005 inst.instruction = THUMB_OP32 (inst.instruction);
11006 inst.instruction |= Rn << r0off;
11007 encode_thumb32_shifted_operand (1);
11011 switch (inst.instruction)
11014 /* In v4t or v5t a move of two lowregs produces unpredictable
11015 results. Don't allow this. */
11018 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11019 "MOV Rd, Rs with two low registers is not "
11020 "permitted on this architecture");
11021 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11025 inst.instruction = T_OPCODE_MOV_HR;
11026 inst.instruction |= (Rn & 0x8) << 4;
11027 inst.instruction |= (Rn & 0x7);
11028 inst.instruction |= Rm << 3;
11032 /* We know we have low registers at this point.
11033 Generate LSLS Rd, Rs, #0. */
11034 inst.instruction = T_OPCODE_LSL_I;
11035 inst.instruction |= Rn;
11036 inst.instruction |= Rm << 3;
11042 inst.instruction = T_OPCODE_CMP_LR;
11043 inst.instruction |= Rn;
11044 inst.instruction |= Rm << 3;
11048 inst.instruction = T_OPCODE_CMP_HR;
11049 inst.instruction |= (Rn & 0x8) << 4;
11050 inst.instruction |= (Rn & 0x7);
11051 inst.instruction |= Rm << 3;
11058 inst.instruction = THUMB_OP16 (inst.instruction);
11060 /* PR 10443: Do not silently ignore shifted operands. */
11061 constraint (inst.operands[1].shifted,
11062 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11064 if (inst.operands[1].isreg)
11066 if (Rn < 8 && Rm < 8)
11068 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11069 since a MOV instruction produces unpredictable results. */
11070 if (inst.instruction == T_OPCODE_MOV_I8)
11071 inst.instruction = T_OPCODE_ADD_I3;
11073 inst.instruction = T_OPCODE_CMP_LR;
11075 inst.instruction |= Rn;
11076 inst.instruction |= Rm << 3;
11080 if (inst.instruction == T_OPCODE_MOV_I8)
11081 inst.instruction = T_OPCODE_MOV_HR;
11083 inst.instruction = T_OPCODE_CMP_HR;
11089 constraint (Rn > 7,
11090 _("only lo regs allowed with immediate"));
11091 inst.instruction |= Rn << 8;
11092 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11103 top = (inst.instruction & 0x00800000) != 0;
11104 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11106 constraint (top, _(":lower16: not allowed this instruction"));
11107 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11109 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11111 constraint (!top, _(":upper16: not allowed this instruction"));
11112 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11115 Rd = inst.operands[0].reg;
11116 reject_bad_reg (Rd);
11118 inst.instruction |= Rd << 8;
11119 if (inst.reloc.type == BFD_RELOC_UNUSED)
11121 imm = inst.reloc.exp.X_add_number;
11122 inst.instruction |= (imm & 0xf000) << 4;
11123 inst.instruction |= (imm & 0x0800) << 15;
11124 inst.instruction |= (imm & 0x0700) << 4;
11125 inst.instruction |= (imm & 0x00ff);
11130 do_t_mvn_tst (void)
11134 Rn = inst.operands[0].reg;
11135 Rm = inst.operands[1].reg;
11137 if (inst.instruction == T_MNEM_cmp
11138 || inst.instruction == T_MNEM_cmn)
11139 constraint (Rn == REG_PC, BAD_PC);
11141 reject_bad_reg (Rn);
11142 reject_bad_reg (Rm);
11144 if (unified_syntax)
11146 int r0off = (inst.instruction == T_MNEM_mvn
11147 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11148 bfd_boolean narrow;
11150 if (inst.size_req == 4
11151 || inst.instruction > 0xffff
11152 || inst.operands[1].shifted
11153 || Rn > 7 || Rm > 7)
11155 else if (inst.instruction == T_MNEM_cmn)
11157 else if (THUMB_SETS_FLAGS (inst.instruction))
11158 narrow = !in_it_block ();
11160 narrow = in_it_block ();
11162 if (!inst.operands[1].isreg)
11164 /* For an immediate, we always generate a 32-bit opcode;
11165 section relaxation will shrink it later if possible. */
11166 if (inst.instruction < 0xffff)
11167 inst.instruction = THUMB_OP32 (inst.instruction);
11168 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11169 inst.instruction |= Rn << r0off;
11170 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11174 /* See if we can do this with a 16-bit instruction. */
11177 inst.instruction = THUMB_OP16 (inst.instruction);
11178 inst.instruction |= Rn;
11179 inst.instruction |= Rm << 3;
11183 constraint (inst.operands[1].shifted
11184 && inst.operands[1].immisreg,
11185 _("shift must be constant"));
11186 if (inst.instruction < 0xffff)
11187 inst.instruction = THUMB_OP32 (inst.instruction);
11188 inst.instruction |= Rn << r0off;
11189 encode_thumb32_shifted_operand (1);
11195 constraint (inst.instruction > 0xffff
11196 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11197 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11198 _("unshifted register required"));
11199 constraint (Rn > 7 || Rm > 7,
11202 inst.instruction = THUMB_OP16 (inst.instruction);
11203 inst.instruction |= Rn;
11204 inst.instruction |= Rm << 3;
11213 if (do_vfp_nsyn_mrs () == SUCCESS)
11216 Rd = inst.operands[0].reg;
11217 reject_bad_reg (Rd);
11218 inst.instruction |= Rd << 8;
11220 if (inst.operands[1].isreg)
11222 unsigned br = inst.operands[1].reg;
11223 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11224 as_bad (_("bad register for mrs"));
11226 inst.instruction |= br & (0xf << 16);
11227 inst.instruction |= (br & 0x300) >> 4;
11228 inst.instruction |= (br & SPSR_BIT) >> 2;
11232 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11234 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11236 /* PR gas/12698: The constraint is only applied for m_profile.
11237 If the user has specified -march=all, we want to ignore it as
11238 we are building for any CPU type, including non-m variants. */
11239 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11240 constraint ((flags != 0) && m_profile, _("selected processor does "
11241 "not support requested special purpose register"));
11244 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11246 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11247 _("'APSR', 'CPSR' or 'SPSR' expected"));
11249 inst.instruction |= (flags & SPSR_BIT) >> 2;
11250 inst.instruction |= inst.operands[1].imm & 0xff;
11251 inst.instruction |= 0xf0000;
11261 if (do_vfp_nsyn_msr () == SUCCESS)
11264 constraint (!inst.operands[1].isreg,
11265 _("Thumb encoding does not support an immediate here"));
11267 if (inst.operands[0].isreg)
11268 flags = (int)(inst.operands[0].reg);
11270 flags = inst.operands[0].imm;
11272 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11274 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11276 /* PR gas/12698: The constraint is only applied for m_profile.
11277 If the user has specified -march=all, we want to ignore it as
11278 we are building for any CPU type, including non-m variants. */
11279 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11280 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11281 && (bits & ~(PSR_s | PSR_f)) != 0)
11282 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11283 && bits != PSR_f)) && m_profile,
11284 _("selected processor does not support requested special "
11285 "purpose register"));
11288 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11289 "requested special purpose register"));
11291 Rn = inst.operands[1].reg;
11292 reject_bad_reg (Rn);
11294 inst.instruction |= (flags & SPSR_BIT) >> 2;
11295 inst.instruction |= (flags & 0xf0000) >> 8;
11296 inst.instruction |= (flags & 0x300) >> 4;
11297 inst.instruction |= (flags & 0xff);
11298 inst.instruction |= Rn << 16;
11304 bfd_boolean narrow;
11305 unsigned Rd, Rn, Rm;
11307 if (!inst.operands[2].present)
11308 inst.operands[2].reg = inst.operands[0].reg;
11310 Rd = inst.operands[0].reg;
11311 Rn = inst.operands[1].reg;
11312 Rm = inst.operands[2].reg;
11314 if (unified_syntax)
11316 if (inst.size_req == 4
11322 else if (inst.instruction == T_MNEM_muls)
11323 narrow = !in_it_block ();
11325 narrow = in_it_block ();
11329 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11330 constraint (Rn > 7 || Rm > 7,
11337 /* 16-bit MULS/Conditional MUL. */
11338 inst.instruction = THUMB_OP16 (inst.instruction);
11339 inst.instruction |= Rd;
11342 inst.instruction |= Rm << 3;
11344 inst.instruction |= Rn << 3;
11346 constraint (1, _("dest must overlap one source register"));
11350 constraint (inst.instruction != T_MNEM_mul,
11351 _("Thumb-2 MUL must not set flags"));
11353 inst.instruction = THUMB_OP32 (inst.instruction);
11354 inst.instruction |= Rd << 8;
11355 inst.instruction |= Rn << 16;
11356 inst.instruction |= Rm << 0;
11358 reject_bad_reg (Rd);
11359 reject_bad_reg (Rn);
11360 reject_bad_reg (Rm);
11367 unsigned RdLo, RdHi, Rn, Rm;
11369 RdLo = inst.operands[0].reg;
11370 RdHi = inst.operands[1].reg;
11371 Rn = inst.operands[2].reg;
11372 Rm = inst.operands[3].reg;
11374 reject_bad_reg (RdLo);
11375 reject_bad_reg (RdHi);
11376 reject_bad_reg (Rn);
11377 reject_bad_reg (Rm);
11379 inst.instruction |= RdLo << 12;
11380 inst.instruction |= RdHi << 8;
11381 inst.instruction |= Rn << 16;
11382 inst.instruction |= Rm;
11385 as_tsktsk (_("rdhi and rdlo must be different"));
11391 set_it_insn_type (NEUTRAL_IT_INSN);
11393 if (unified_syntax)
11395 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11397 inst.instruction = THUMB_OP32 (inst.instruction);
11398 inst.instruction |= inst.operands[0].imm;
11402 /* PR9722: Check for Thumb2 availability before
11403 generating a thumb2 nop instruction. */
11404 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11406 inst.instruction = THUMB_OP16 (inst.instruction);
11407 inst.instruction |= inst.operands[0].imm << 4;
11410 inst.instruction = 0x46c0;
11415 constraint (inst.operands[0].present,
11416 _("Thumb does not support NOP with hints"));
11417 inst.instruction = 0x46c0;
11424 if (unified_syntax)
11426 bfd_boolean narrow;
11428 if (THUMB_SETS_FLAGS (inst.instruction))
11429 narrow = !in_it_block ();
11431 narrow = in_it_block ();
11432 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11434 if (inst.size_req == 4)
11439 inst.instruction = THUMB_OP32 (inst.instruction);
11440 inst.instruction |= inst.operands[0].reg << 8;
11441 inst.instruction |= inst.operands[1].reg << 16;
11445 inst.instruction = THUMB_OP16 (inst.instruction);
11446 inst.instruction |= inst.operands[0].reg;
11447 inst.instruction |= inst.operands[1].reg << 3;
11452 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11454 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11456 inst.instruction = THUMB_OP16 (inst.instruction);
11457 inst.instruction |= inst.operands[0].reg;
11458 inst.instruction |= inst.operands[1].reg << 3;
11467 Rd = inst.operands[0].reg;
11468 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11470 reject_bad_reg (Rd);
11471 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11472 reject_bad_reg (Rn);
11474 inst.instruction |= Rd << 8;
11475 inst.instruction |= Rn << 16;
11477 if (!inst.operands[2].isreg)
11479 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11480 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11486 Rm = inst.operands[2].reg;
11487 reject_bad_reg (Rm);
11489 constraint (inst.operands[2].shifted
11490 && inst.operands[2].immisreg,
11491 _("shift must be constant"));
11492 encode_thumb32_shifted_operand (2);
11499 unsigned Rd, Rn, Rm;
11501 Rd = inst.operands[0].reg;
11502 Rn = inst.operands[1].reg;
11503 Rm = inst.operands[2].reg;
11505 reject_bad_reg (Rd);
11506 reject_bad_reg (Rn);
11507 reject_bad_reg (Rm);
11509 inst.instruction |= Rd << 8;
11510 inst.instruction |= Rn << 16;
11511 inst.instruction |= Rm;
11512 if (inst.operands[3].present)
11514 unsigned int val = inst.reloc.exp.X_add_number;
11515 constraint (inst.reloc.exp.X_op != O_constant,
11516 _("expression too complex"));
11517 inst.instruction |= (val & 0x1c) << 10;
11518 inst.instruction |= (val & 0x03) << 6;
11525 if (!inst.operands[3].present)
11529 inst.instruction &= ~0x00000020;
11531 /* PR 10168. Swap the Rm and Rn registers. */
11532 Rtmp = inst.operands[1].reg;
11533 inst.operands[1].reg = inst.operands[2].reg;
11534 inst.operands[2].reg = Rtmp;
11542 if (inst.operands[0].immisreg)
11543 reject_bad_reg (inst.operands[0].imm);
11545 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11549 do_t_push_pop (void)
11553 constraint (inst.operands[0].writeback,
11554 _("push/pop do not support {reglist}^"));
11555 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11556 _("expression too complex"));
11558 mask = inst.operands[0].imm;
11559 if ((mask & ~0xff) == 0)
11560 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11561 else if ((inst.instruction == T_MNEM_push
11562 && (mask & ~0xff) == 1 << REG_LR)
11563 || (inst.instruction == T_MNEM_pop
11564 && (mask & ~0xff) == 1 << REG_PC))
11566 inst.instruction = THUMB_OP16 (inst.instruction);
11567 inst.instruction |= THUMB_PP_PC_LR;
11568 inst.instruction |= mask & 0xff;
11570 else if (unified_syntax)
11572 inst.instruction = THUMB_OP32 (inst.instruction);
11573 encode_thumb2_ldmstm (13, mask, TRUE);
11577 inst.error = _("invalid register list to push/pop instruction");
11587 Rd = inst.operands[0].reg;
11588 Rm = inst.operands[1].reg;
11590 reject_bad_reg (Rd);
11591 reject_bad_reg (Rm);
11593 inst.instruction |= Rd << 8;
11594 inst.instruction |= Rm << 16;
11595 inst.instruction |= Rm;
11603 Rd = inst.operands[0].reg;
11604 Rm = inst.operands[1].reg;
11606 reject_bad_reg (Rd);
11607 reject_bad_reg (Rm);
11609 if (Rd <= 7 && Rm <= 7
11610 && inst.size_req != 4)
11612 inst.instruction = THUMB_OP16 (inst.instruction);
11613 inst.instruction |= Rd;
11614 inst.instruction |= Rm << 3;
11616 else if (unified_syntax)
11618 inst.instruction = THUMB_OP32 (inst.instruction);
11619 inst.instruction |= Rd << 8;
11620 inst.instruction |= Rm << 16;
11621 inst.instruction |= Rm;
11624 inst.error = BAD_HIREG;
11632 Rd = inst.operands[0].reg;
11633 Rm = inst.operands[1].reg;
11635 reject_bad_reg (Rd);
11636 reject_bad_reg (Rm);
11638 inst.instruction |= Rd << 8;
11639 inst.instruction |= Rm;
11647 Rd = inst.operands[0].reg;
11648 Rs = (inst.operands[1].present
11649 ? inst.operands[1].reg /* Rd, Rs, foo */
11650 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11652 reject_bad_reg (Rd);
11653 reject_bad_reg (Rs);
11654 if (inst.operands[2].isreg)
11655 reject_bad_reg (inst.operands[2].reg);
11657 inst.instruction |= Rd << 8;
11658 inst.instruction |= Rs << 16;
11659 if (!inst.operands[2].isreg)
11661 bfd_boolean narrow;
11663 if ((inst.instruction & 0x00100000) != 0)
11664 narrow = !in_it_block ();
11666 narrow = in_it_block ();
11668 if (Rd > 7 || Rs > 7)
11671 if (inst.size_req == 4 || !unified_syntax)
11674 if (inst.reloc.exp.X_op != O_constant
11675 || inst.reloc.exp.X_add_number != 0)
11678 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11679 relaxation, but it doesn't seem worth the hassle. */
11682 inst.reloc.type = BFD_RELOC_UNUSED;
11683 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11684 inst.instruction |= Rs << 3;
11685 inst.instruction |= Rd;
11689 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11690 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11694 encode_thumb32_shifted_operand (2);
11700 set_it_insn_type (OUTSIDE_IT_INSN);
11701 if (inst.operands[0].imm)
11702 inst.instruction |= 0x8;
11708 if (!inst.operands[1].present)
11709 inst.operands[1].reg = inst.operands[0].reg;
11711 if (unified_syntax)
11713 bfd_boolean narrow;
11716 switch (inst.instruction)
11719 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11721 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11723 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11725 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11729 if (THUMB_SETS_FLAGS (inst.instruction))
11730 narrow = !in_it_block ();
11732 narrow = in_it_block ();
11733 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11735 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11737 if (inst.operands[2].isreg
11738 && (inst.operands[1].reg != inst.operands[0].reg
11739 || inst.operands[2].reg > 7))
11741 if (inst.size_req == 4)
11744 reject_bad_reg (inst.operands[0].reg);
11745 reject_bad_reg (inst.operands[1].reg);
11749 if (inst.operands[2].isreg)
11751 reject_bad_reg (inst.operands[2].reg);
11752 inst.instruction = THUMB_OP32 (inst.instruction);
11753 inst.instruction |= inst.operands[0].reg << 8;
11754 inst.instruction |= inst.operands[1].reg << 16;
11755 inst.instruction |= inst.operands[2].reg;
11757 /* PR 12854: Error on extraneous shifts. */
11758 constraint (inst.operands[2].shifted,
11759 _("extraneous shift as part of operand to shift insn"));
11763 inst.operands[1].shifted = 1;
11764 inst.operands[1].shift_kind = shift_kind;
11765 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11766 ? T_MNEM_movs : T_MNEM_mov);
11767 inst.instruction |= inst.operands[0].reg << 8;
11768 encode_thumb32_shifted_operand (1);
11769 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11770 inst.reloc.type = BFD_RELOC_UNUSED;
11775 if (inst.operands[2].isreg)
11777 switch (shift_kind)
11779 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11780 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11781 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11782 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11786 inst.instruction |= inst.operands[0].reg;
11787 inst.instruction |= inst.operands[2].reg << 3;
11789 /* PR 12854: Error on extraneous shifts. */
11790 constraint (inst.operands[2].shifted,
11791 _("extraneous shift as part of operand to shift insn"));
11795 switch (shift_kind)
11797 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11798 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11799 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11802 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11803 inst.instruction |= inst.operands[0].reg;
11804 inst.instruction |= inst.operands[1].reg << 3;
11810 constraint (inst.operands[0].reg > 7
11811 || inst.operands[1].reg > 7, BAD_HIREG);
11812 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11814 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11816 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11817 constraint (inst.operands[0].reg != inst.operands[1].reg,
11818 _("source1 and dest must be same register"));
11820 switch (inst.instruction)
11822 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11823 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11824 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11825 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11829 inst.instruction |= inst.operands[0].reg;
11830 inst.instruction |= inst.operands[2].reg << 3;
11832 /* PR 12854: Error on extraneous shifts. */
11833 constraint (inst.operands[2].shifted,
11834 _("extraneous shift as part of operand to shift insn"));
11838 switch (inst.instruction)
11840 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11841 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11842 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11843 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11846 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11847 inst.instruction |= inst.operands[0].reg;
11848 inst.instruction |= inst.operands[1].reg << 3;
11856 unsigned Rd, Rn, Rm;
11858 Rd = inst.operands[0].reg;
11859 Rn = inst.operands[1].reg;
11860 Rm = inst.operands[2].reg;
11862 reject_bad_reg (Rd);
11863 reject_bad_reg (Rn);
11864 reject_bad_reg (Rm);
11866 inst.instruction |= Rd << 8;
11867 inst.instruction |= Rn << 16;
11868 inst.instruction |= Rm;
11874 unsigned Rd, Rn, Rm;
11876 Rd = inst.operands[0].reg;
11877 Rm = inst.operands[1].reg;
11878 Rn = inst.operands[2].reg;
11880 reject_bad_reg (Rd);
11881 reject_bad_reg (Rn);
11882 reject_bad_reg (Rm);
11884 inst.instruction |= Rd << 8;
11885 inst.instruction |= Rn << 16;
11886 inst.instruction |= Rm;
11892 unsigned int value = inst.reloc.exp.X_add_number;
11893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11894 _("SMC is not permitted on this architecture"));
11895 constraint (inst.reloc.exp.X_op != O_constant,
11896 _("expression too complex"));
11897 inst.reloc.type = BFD_RELOC_UNUSED;
11898 inst.instruction |= (value & 0xf000) >> 12;
11899 inst.instruction |= (value & 0x0ff0);
11900 inst.instruction |= (value & 0x000f) << 16;
11906 unsigned int value = inst.reloc.exp.X_add_number;
11908 inst.reloc.type = BFD_RELOC_UNUSED;
11909 inst.instruction |= (value & 0x0fff);
11910 inst.instruction |= (value & 0xf000) << 4;
11914 do_t_ssat_usat (int bias)
11918 Rd = inst.operands[0].reg;
11919 Rn = inst.operands[2].reg;
11921 reject_bad_reg (Rd);
11922 reject_bad_reg (Rn);
11924 inst.instruction |= Rd << 8;
11925 inst.instruction |= inst.operands[1].imm - bias;
11926 inst.instruction |= Rn << 16;
11928 if (inst.operands[3].present)
11930 offsetT shift_amount = inst.reloc.exp.X_add_number;
11932 inst.reloc.type = BFD_RELOC_UNUSED;
11934 constraint (inst.reloc.exp.X_op != O_constant,
11935 _("expression too complex"));
11937 if (shift_amount != 0)
11939 constraint (shift_amount > 31,
11940 _("shift expression is too large"));
11942 if (inst.operands[3].shift_kind == SHIFT_ASR)
11943 inst.instruction |= 0x00200000; /* sh bit. */
11945 inst.instruction |= (shift_amount & 0x1c) << 10;
11946 inst.instruction |= (shift_amount & 0x03) << 6;
11954 do_t_ssat_usat (1);
11962 Rd = inst.operands[0].reg;
11963 Rn = inst.operands[2].reg;
11965 reject_bad_reg (Rd);
11966 reject_bad_reg (Rn);
11968 inst.instruction |= Rd << 8;
11969 inst.instruction |= inst.operands[1].imm - 1;
11970 inst.instruction |= Rn << 16;
11976 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11977 || inst.operands[2].postind || inst.operands[2].writeback
11978 || inst.operands[2].immisreg || inst.operands[2].shifted
11979 || inst.operands[2].negative,
11982 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11984 inst.instruction |= inst.operands[0].reg << 8;
11985 inst.instruction |= inst.operands[1].reg << 12;
11986 inst.instruction |= inst.operands[2].reg << 16;
11987 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11993 if (!inst.operands[2].present)
11994 inst.operands[2].reg = inst.operands[1].reg + 1;
11996 constraint (inst.operands[0].reg == inst.operands[1].reg
11997 || inst.operands[0].reg == inst.operands[2].reg
11998 || inst.operands[0].reg == inst.operands[3].reg,
12001 inst.instruction |= inst.operands[0].reg;
12002 inst.instruction |= inst.operands[1].reg << 12;
12003 inst.instruction |= inst.operands[2].reg << 8;
12004 inst.instruction |= inst.operands[3].reg << 16;
12010 unsigned Rd, Rn, Rm;
12012 Rd = inst.operands[0].reg;
12013 Rn = inst.operands[1].reg;
12014 Rm = inst.operands[2].reg;
12016 reject_bad_reg (Rd);
12017 reject_bad_reg (Rn);
12018 reject_bad_reg (Rm);
12020 inst.instruction |= Rd << 8;
12021 inst.instruction |= Rn << 16;
12022 inst.instruction |= Rm;
12023 inst.instruction |= inst.operands[3].imm << 4;
12031 Rd = inst.operands[0].reg;
12032 Rm = inst.operands[1].reg;
12034 reject_bad_reg (Rd);
12035 reject_bad_reg (Rm);
12037 if (inst.instruction <= 0xffff
12038 && inst.size_req != 4
12039 && Rd <= 7 && Rm <= 7
12040 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12042 inst.instruction = THUMB_OP16 (inst.instruction);
12043 inst.instruction |= Rd;
12044 inst.instruction |= Rm << 3;
12046 else if (unified_syntax)
12048 if (inst.instruction <= 0xffff)
12049 inst.instruction = THUMB_OP32 (inst.instruction);
12050 inst.instruction |= Rd << 8;
12051 inst.instruction |= Rm;
12052 inst.instruction |= inst.operands[2].imm << 4;
12056 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12057 _("Thumb encoding does not support rotation"));
12058 constraint (1, BAD_HIREG);
12065 /* We have to do the following check manually as ARM_EXT_OS only applies
12067 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12069 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12070 /* This only applies to the v6m howver, not later architectures. */
12071 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12072 as_bad (_("SVC is not permitted on this architecture"));
12073 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12076 inst.reloc.type = BFD_RELOC_ARM_SWI;
12085 half = (inst.instruction & 0x10) != 0;
12086 set_it_insn_type_last ();
12087 constraint (inst.operands[0].immisreg,
12088 _("instruction requires register index"));
12090 Rn = inst.operands[0].reg;
12091 Rm = inst.operands[0].imm;
12093 constraint (Rn == REG_SP, BAD_SP);
12094 reject_bad_reg (Rm);
12096 constraint (!half && inst.operands[0].shifted,
12097 _("instruction does not allow shifted index"));
12098 inst.instruction |= (Rn << 16) | Rm;
12104 do_t_ssat_usat (0);
12112 Rd = inst.operands[0].reg;
12113 Rn = inst.operands[2].reg;
12115 reject_bad_reg (Rd);
12116 reject_bad_reg (Rn);
12118 inst.instruction |= Rd << 8;
12119 inst.instruction |= inst.operands[1].imm;
12120 inst.instruction |= Rn << 16;
12123 /* Neon instruction encoder helpers. */
12125 /* Encodings for the different types for various Neon opcodes. */
12127 /* An "invalid" code for the following tables. */
12130 struct neon_tab_entry
12133 unsigned float_or_poly;
12134 unsigned scalar_or_imm;
12137 /* Map overloaded Neon opcodes to their respective encodings. */
12138 #define NEON_ENC_TAB \
12139 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12140 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12141 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12142 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12143 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12144 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12145 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12146 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12147 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12148 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12149 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12150 /* Register variants of the following two instructions are encoded as
12151 vcge / vcgt with the operands reversed. */ \
12152 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12153 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12154 X(vfma, N_INV, 0x0000c10, N_INV), \
12155 X(vfms, N_INV, 0x0200c10, N_INV), \
12156 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12157 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12158 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12159 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12160 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12161 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12162 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12163 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12164 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12165 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12166 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12167 X(vshl, 0x0000400, N_INV, 0x0800510), \
12168 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12169 X(vand, 0x0000110, N_INV, 0x0800030), \
12170 X(vbic, 0x0100110, N_INV, 0x0800030), \
12171 X(veor, 0x1000110, N_INV, N_INV), \
12172 X(vorn, 0x0300110, N_INV, 0x0800010), \
12173 X(vorr, 0x0200110, N_INV, 0x0800010), \
12174 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12175 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12176 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12177 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12178 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12179 X(vst1, 0x0000000, 0x0800000, N_INV), \
12180 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12181 X(vst2, 0x0000100, 0x0800100, N_INV), \
12182 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12183 X(vst3, 0x0000200, 0x0800200, N_INV), \
12184 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12185 X(vst4, 0x0000300, 0x0800300, N_INV), \
12186 X(vmovn, 0x1b20200, N_INV, N_INV), \
12187 X(vtrn, 0x1b20080, N_INV, N_INV), \
12188 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12189 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12190 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12191 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12192 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12193 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12194 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12195 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12196 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12197 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12198 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12202 #define X(OPC,I,F,S) N_MNEM_##OPC
12207 static const struct neon_tab_entry neon_enc_tab[] =
12209 #define X(OPC,I,F,S) { (I), (F), (S) }
12214 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12215 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12216 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12217 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12218 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12219 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12220 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12221 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12222 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12223 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12224 #define NEON_ENC_SINGLE_(X) \
12225 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12226 #define NEON_ENC_DOUBLE_(X) \
12227 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12229 #define NEON_ENCODE(type, inst) \
12232 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12233 inst.is_neon = 1; \
12237 #define check_neon_suffixes \
12240 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12242 as_bad (_("invalid neon suffix for non neon instruction")); \
12248 /* Define shapes for instruction operands. The following mnemonic characters
12249 are used in this table:
12251 F - VFP S<n> register
12252 D - Neon D<n> register
12253 Q - Neon Q<n> register
12257 L - D<n> register list
12259 This table is used to generate various data:
12260 - enumerations of the form NS_DDR to be used as arguments to
12262 - a table classifying shapes into single, double, quad, mixed.
12263 - a table used to drive neon_select_shape. */
12265 #define NEON_SHAPE_DEF \
12266 X(3, (D, D, D), DOUBLE), \
12267 X(3, (Q, Q, Q), QUAD), \
12268 X(3, (D, D, I), DOUBLE), \
12269 X(3, (Q, Q, I), QUAD), \
12270 X(3, (D, D, S), DOUBLE), \
12271 X(3, (Q, Q, S), QUAD), \
12272 X(2, (D, D), DOUBLE), \
12273 X(2, (Q, Q), QUAD), \
12274 X(2, (D, S), DOUBLE), \
12275 X(2, (Q, S), QUAD), \
12276 X(2, (D, R), DOUBLE), \
12277 X(2, (Q, R), QUAD), \
12278 X(2, (D, I), DOUBLE), \
12279 X(2, (Q, I), QUAD), \
12280 X(3, (D, L, D), DOUBLE), \
12281 X(2, (D, Q), MIXED), \
12282 X(2, (Q, D), MIXED), \
12283 X(3, (D, Q, I), MIXED), \
12284 X(3, (Q, D, I), MIXED), \
12285 X(3, (Q, D, D), MIXED), \
12286 X(3, (D, Q, Q), MIXED), \
12287 X(3, (Q, Q, D), MIXED), \
12288 X(3, (Q, D, S), MIXED), \
12289 X(3, (D, Q, S), MIXED), \
12290 X(4, (D, D, D, I), DOUBLE), \
12291 X(4, (Q, Q, Q, I), QUAD), \
12292 X(2, (F, F), SINGLE), \
12293 X(3, (F, F, F), SINGLE), \
12294 X(2, (F, I), SINGLE), \
12295 X(2, (F, D), MIXED), \
12296 X(2, (D, F), MIXED), \
12297 X(3, (F, F, I), MIXED), \
12298 X(4, (R, R, F, F), SINGLE), \
12299 X(4, (F, F, R, R), SINGLE), \
12300 X(3, (D, R, R), DOUBLE), \
12301 X(3, (R, R, D), DOUBLE), \
12302 X(2, (S, R), SINGLE), \
12303 X(2, (R, S), SINGLE), \
12304 X(2, (F, R), SINGLE), \
12305 X(2, (R, F), SINGLE)
12307 #define S2(A,B) NS_##A##B
12308 #define S3(A,B,C) NS_##A##B##C
12309 #define S4(A,B,C,D) NS_##A##B##C##D
12311 #define X(N, L, C) S##N L
12324 enum neon_shape_class
12332 #define X(N, L, C) SC_##C
12334 static enum neon_shape_class neon_shape_class[] =
12352 /* Register widths of above. */
12353 static unsigned neon_shape_el_size[] =
12364 struct neon_shape_info
12367 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12370 #define S2(A,B) { SE_##A, SE_##B }
12371 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12372 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12374 #define X(N, L, C) { N, S##N L }
12376 static struct neon_shape_info neon_shape_tab[] =
12386 /* Bit masks used in type checking given instructions.
12387 'N_EQK' means the type must be the same as (or based on in some way) the key
12388 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12389 set, various other bits can be set as well in order to modify the meaning of
12390 the type constraint. */
12392 enum neon_type_mask
12415 N_KEY = 0x1000000, /* Key element (main type specifier). */
12416 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12417 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12418 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12419 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12420 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12421 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12422 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12423 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12424 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12426 N_MAX_NONSPECIAL = N_F64
12429 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12431 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12432 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12433 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12434 #define N_SUF_32 (N_SU_32 | N_F32)
12435 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12436 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12438 /* Pass this as the first type argument to neon_check_type to ignore types
12440 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12442 /* Select a "shape" for the current instruction (describing register types or
12443 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12444 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12445 function of operand parsing, so this function doesn't need to be called.
12446 Shapes should be listed in order of decreasing length. */
12448 static enum neon_shape
12449 neon_select_shape (enum neon_shape shape, ...)
12452 enum neon_shape first_shape = shape;
12454 /* Fix missing optional operands. FIXME: we don't know at this point how
12455 many arguments we should have, so this makes the assumption that we have
12456 > 1. This is true of all current Neon opcodes, I think, but may not be
12457 true in the future. */
12458 if (!inst.operands[1].present)
12459 inst.operands[1] = inst.operands[0];
12461 va_start (ap, shape);
12463 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12468 for (j = 0; j < neon_shape_tab[shape].els; j++)
12470 if (!inst.operands[j].present)
12476 switch (neon_shape_tab[shape].el[j])
12479 if (!(inst.operands[j].isreg
12480 && inst.operands[j].isvec
12481 && inst.operands[j].issingle
12482 && !inst.operands[j].isquad))
12487 if (!(inst.operands[j].isreg
12488 && inst.operands[j].isvec
12489 && !inst.operands[j].isquad
12490 && !inst.operands[j].issingle))
12495 if (!(inst.operands[j].isreg
12496 && !inst.operands[j].isvec))
12501 if (!(inst.operands[j].isreg
12502 && inst.operands[j].isvec
12503 && inst.operands[j].isquad
12504 && !inst.operands[j].issingle))
12509 if (!(!inst.operands[j].isreg
12510 && !inst.operands[j].isscalar))
12515 if (!(!inst.operands[j].isreg
12516 && inst.operands[j].isscalar))
12526 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12527 /* We've matched all the entries in the shape table, and we don't
12528 have any left over operands which have not been matched. */
12534 if (shape == NS_NULL && first_shape != NS_NULL)
12535 first_error (_("invalid instruction shape"));
12540 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12541 means the Q bit should be set). */
12544 neon_quad (enum neon_shape shape)
12546 return neon_shape_class[shape] == SC_QUAD;
12550 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12553 /* Allow modification to be made to types which are constrained to be
12554 based on the key element, based on bits set alongside N_EQK. */
12555 if ((typebits & N_EQK) != 0)
12557 if ((typebits & N_HLF) != 0)
12559 else if ((typebits & N_DBL) != 0)
12561 if ((typebits & N_SGN) != 0)
12562 *g_type = NT_signed;
12563 else if ((typebits & N_UNS) != 0)
12564 *g_type = NT_unsigned;
12565 else if ((typebits & N_INT) != 0)
12566 *g_type = NT_integer;
12567 else if ((typebits & N_FLT) != 0)
12568 *g_type = NT_float;
12569 else if ((typebits & N_SIZ) != 0)
12570 *g_type = NT_untyped;
12574 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12575 operand type, i.e. the single type specified in a Neon instruction when it
12576 is the only one given. */
12578 static struct neon_type_el
12579 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12581 struct neon_type_el dest = *key;
12583 gas_assert ((thisarg & N_EQK) != 0);
12585 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12590 /* Convert Neon type and size into compact bitmask representation. */
12592 static enum neon_type_mask
12593 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12600 case 8: return N_8;
12601 case 16: return N_16;
12602 case 32: return N_32;
12603 case 64: return N_64;
12611 case 8: return N_I8;
12612 case 16: return N_I16;
12613 case 32: return N_I32;
12614 case 64: return N_I64;
12622 case 16: return N_F16;
12623 case 32: return N_F32;
12624 case 64: return N_F64;
12632 case 8: return N_P8;
12633 case 16: return N_P16;
12641 case 8: return N_S8;
12642 case 16: return N_S16;
12643 case 32: return N_S32;
12644 case 64: return N_S64;
12652 case 8: return N_U8;
12653 case 16: return N_U16;
12654 case 32: return N_U32;
12655 case 64: return N_U64;
12666 /* Convert compact Neon bitmask type representation to a type and size. Only
12667 handles the case where a single bit is set in the mask. */
12670 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12671 enum neon_type_mask mask)
12673 if ((mask & N_EQK) != 0)
12676 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12678 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12680 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12682 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12687 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12689 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12690 *type = NT_unsigned;
12691 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12692 *type = NT_integer;
12693 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12694 *type = NT_untyped;
12695 else if ((mask & (N_P8 | N_P16)) != 0)
12697 else if ((mask & (N_F32 | N_F64)) != 0)
12705 /* Modify a bitmask of allowed types. This is only needed for type
12709 modify_types_allowed (unsigned allowed, unsigned mods)
12712 enum neon_el_type type;
12718 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12720 if (el_type_of_type_chk (&type, &size,
12721 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12723 neon_modify_type_size (mods, &type, &size);
12724 destmask |= type_chk_of_el_type (type, size);
12731 /* Check type and return type classification.
12732 The manual states (paraphrase): If one datatype is given, it indicates the
12734 - the second operand, if there is one
12735 - the operand, if there is no second operand
12736 - the result, if there are no operands.
12737 This isn't quite good enough though, so we use a concept of a "key" datatype
12738 which is set on a per-instruction basis, which is the one which matters when
12739 only one data type is written.
12740 Note: this function has side-effects (e.g. filling in missing operands). All
12741 Neon instructions should call it before performing bit encoding. */
12743 static struct neon_type_el
12744 neon_check_type (unsigned els, enum neon_shape ns, ...)
12747 unsigned i, pass, key_el = 0;
12748 unsigned types[NEON_MAX_TYPE_ELS];
12749 enum neon_el_type k_type = NT_invtype;
12750 unsigned k_size = -1u;
12751 struct neon_type_el badtype = {NT_invtype, -1};
12752 unsigned key_allowed = 0;
12754 /* Optional registers in Neon instructions are always (not) in operand 1.
12755 Fill in the missing operand here, if it was omitted. */
12756 if (els > 1 && !inst.operands[1].present)
12757 inst.operands[1] = inst.operands[0];
12759 /* Suck up all the varargs. */
12761 for (i = 0; i < els; i++)
12763 unsigned thisarg = va_arg (ap, unsigned);
12764 if (thisarg == N_IGNORE_TYPE)
12769 types[i] = thisarg;
12770 if ((thisarg & N_KEY) != 0)
12775 if (inst.vectype.elems > 0)
12776 for (i = 0; i < els; i++)
12777 if (inst.operands[i].vectype.type != NT_invtype)
12779 first_error (_("types specified in both the mnemonic and operands"));
12783 /* Duplicate inst.vectype elements here as necessary.
12784 FIXME: No idea if this is exactly the same as the ARM assembler,
12785 particularly when an insn takes one register and one non-register
12787 if (inst.vectype.elems == 1 && els > 1)
12790 inst.vectype.elems = els;
12791 inst.vectype.el[key_el] = inst.vectype.el[0];
12792 for (j = 0; j < els; j++)
12794 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12797 else if (inst.vectype.elems == 0 && els > 0)
12800 /* No types were given after the mnemonic, so look for types specified
12801 after each operand. We allow some flexibility here; as long as the
12802 "key" operand has a type, we can infer the others. */
12803 for (j = 0; j < els; j++)
12804 if (inst.operands[j].vectype.type != NT_invtype)
12805 inst.vectype.el[j] = inst.operands[j].vectype;
12807 if (inst.operands[key_el].vectype.type != NT_invtype)
12809 for (j = 0; j < els; j++)
12810 if (inst.operands[j].vectype.type == NT_invtype)
12811 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12816 first_error (_("operand types can't be inferred"));
12820 else if (inst.vectype.elems != els)
12822 first_error (_("type specifier has the wrong number of parts"));
12826 for (pass = 0; pass < 2; pass++)
12828 for (i = 0; i < els; i++)
12830 unsigned thisarg = types[i];
12831 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12832 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12833 enum neon_el_type g_type = inst.vectype.el[i].type;
12834 unsigned g_size = inst.vectype.el[i].size;
12836 /* Decay more-specific signed & unsigned types to sign-insensitive
12837 integer types if sign-specific variants are unavailable. */
12838 if ((g_type == NT_signed || g_type == NT_unsigned)
12839 && (types_allowed & N_SU_ALL) == 0)
12840 g_type = NT_integer;
12842 /* If only untyped args are allowed, decay any more specific types to
12843 them. Some instructions only care about signs for some element
12844 sizes, so handle that properly. */
12845 if ((g_size == 8 && (types_allowed & N_8) != 0)
12846 || (g_size == 16 && (types_allowed & N_16) != 0)
12847 || (g_size == 32 && (types_allowed & N_32) != 0)
12848 || (g_size == 64 && (types_allowed & N_64) != 0))
12849 g_type = NT_untyped;
12853 if ((thisarg & N_KEY) != 0)
12857 key_allowed = thisarg & ~N_KEY;
12862 if ((thisarg & N_VFP) != 0)
12864 enum neon_shape_el regshape;
12865 unsigned regwidth, match;
12867 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12870 first_error (_("invalid instruction shape"));
12873 regshape = neon_shape_tab[ns].el[i];
12874 regwidth = neon_shape_el_size[regshape];
12876 /* In VFP mode, operands must match register widths. If we
12877 have a key operand, use its width, else use the width of
12878 the current operand. */
12884 if (regwidth != match)
12886 first_error (_("operand size must match register width"));
12891 if ((thisarg & N_EQK) == 0)
12893 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12895 if ((given_type & types_allowed) == 0)
12897 first_error (_("bad type in Neon instruction"));
12903 enum neon_el_type mod_k_type = k_type;
12904 unsigned mod_k_size = k_size;
12905 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12906 if (g_type != mod_k_type || g_size != mod_k_size)
12908 first_error (_("inconsistent types in Neon instruction"));
12916 return inst.vectype.el[key_el];
12919 /* Neon-style VFP instruction forwarding. */
12921 /* Thumb VFP instructions have 0xE in the condition field. */
12924 do_vfp_cond_or_thumb (void)
12929 inst.instruction |= 0xe0000000;
12931 inst.instruction |= inst.cond << 28;
12934 /* Look up and encode a simple mnemonic, for use as a helper function for the
12935 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12936 etc. It is assumed that operand parsing has already been done, and that the
12937 operands are in the form expected by the given opcode (this isn't necessarily
12938 the same as the form in which they were parsed, hence some massaging must
12939 take place before this function is called).
12940 Checks current arch version against that in the looked-up opcode. */
12943 do_vfp_nsyn_opcode (const char *opname)
12945 const struct asm_opcode *opcode;
12947 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12953 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12960 inst.instruction = opcode->tvalue;
12961 opcode->tencode ();
12965 inst.instruction = (inst.cond << 28) | opcode->avalue;
12966 opcode->aencode ();
12971 do_vfp_nsyn_add_sub (enum neon_shape rs)
12973 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12978 do_vfp_nsyn_opcode ("fadds");
12980 do_vfp_nsyn_opcode ("fsubs");
12985 do_vfp_nsyn_opcode ("faddd");
12987 do_vfp_nsyn_opcode ("fsubd");
12991 /* Check operand types to see if this is a VFP instruction, and if so call
12995 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12997 enum neon_shape rs;
12998 struct neon_type_el et;
13003 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13004 et = neon_check_type (2, rs,
13005 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13009 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13010 et = neon_check_type (3, rs,
13011 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13018 if (et.type != NT_invtype)
13029 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13031 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13036 do_vfp_nsyn_opcode ("fmacs");
13038 do_vfp_nsyn_opcode ("fnmacs");
13043 do_vfp_nsyn_opcode ("fmacd");
13045 do_vfp_nsyn_opcode ("fnmacd");
13050 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13052 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13057 do_vfp_nsyn_opcode ("ffmas");
13059 do_vfp_nsyn_opcode ("ffnmas");
13064 do_vfp_nsyn_opcode ("ffmad");
13066 do_vfp_nsyn_opcode ("ffnmad");
13071 do_vfp_nsyn_mul (enum neon_shape rs)
13074 do_vfp_nsyn_opcode ("fmuls");
13076 do_vfp_nsyn_opcode ("fmuld");
13080 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13082 int is_neg = (inst.instruction & 0x80) != 0;
13083 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13088 do_vfp_nsyn_opcode ("fnegs");
13090 do_vfp_nsyn_opcode ("fabss");
13095 do_vfp_nsyn_opcode ("fnegd");
13097 do_vfp_nsyn_opcode ("fabsd");
13101 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13102 insns belong to Neon, and are handled elsewhere. */
13105 do_vfp_nsyn_ldm_stm (int is_dbmode)
13107 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13111 do_vfp_nsyn_opcode ("fldmdbs");
13113 do_vfp_nsyn_opcode ("fldmias");
13118 do_vfp_nsyn_opcode ("fstmdbs");
13120 do_vfp_nsyn_opcode ("fstmias");
13125 do_vfp_nsyn_sqrt (void)
13127 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13128 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13131 do_vfp_nsyn_opcode ("fsqrts");
13133 do_vfp_nsyn_opcode ("fsqrtd");
13137 do_vfp_nsyn_div (void)
13139 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13140 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13141 N_F32 | N_F64 | N_KEY | N_VFP);
13144 do_vfp_nsyn_opcode ("fdivs");
13146 do_vfp_nsyn_opcode ("fdivd");
13150 do_vfp_nsyn_nmul (void)
13152 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13153 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13154 N_F32 | N_F64 | N_KEY | N_VFP);
13158 NEON_ENCODE (SINGLE, inst);
13159 do_vfp_sp_dyadic ();
13163 NEON_ENCODE (DOUBLE, inst);
13164 do_vfp_dp_rd_rn_rm ();
13166 do_vfp_cond_or_thumb ();
13170 do_vfp_nsyn_cmp (void)
13172 if (inst.operands[1].isreg)
13174 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13175 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13179 NEON_ENCODE (SINGLE, inst);
13180 do_vfp_sp_monadic ();
13184 NEON_ENCODE (DOUBLE, inst);
13185 do_vfp_dp_rd_rm ();
13190 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13191 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13193 switch (inst.instruction & 0x0fffffff)
13196 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13199 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13207 NEON_ENCODE (SINGLE, inst);
13208 do_vfp_sp_compare_z ();
13212 NEON_ENCODE (DOUBLE, inst);
13216 do_vfp_cond_or_thumb ();
13220 nsyn_insert_sp (void)
13222 inst.operands[1] = inst.operands[0];
13223 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13224 inst.operands[0].reg = REG_SP;
13225 inst.operands[0].isreg = 1;
13226 inst.operands[0].writeback = 1;
13227 inst.operands[0].present = 1;
13231 do_vfp_nsyn_push (void)
13234 if (inst.operands[1].issingle)
13235 do_vfp_nsyn_opcode ("fstmdbs");
13237 do_vfp_nsyn_opcode ("fstmdbd");
13241 do_vfp_nsyn_pop (void)
13244 if (inst.operands[1].issingle)
13245 do_vfp_nsyn_opcode ("fldmias");
13247 do_vfp_nsyn_opcode ("fldmiad");
13250 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13251 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13254 neon_dp_fixup (struct arm_it* insn)
13256 unsigned int i = insn->instruction;
13261 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13272 insn->instruction = i;
13275 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13279 neon_logbits (unsigned x)
13281 return ffs (x) - 4;
13284 #define LOW4(R) ((R) & 0xf)
13285 #define HI1(R) (((R) >> 4) & 1)
13287 /* Encode insns with bit pattern:
13289 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13290 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13292 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13293 different meaning for some instruction. */
13296 neon_three_same (int isquad, int ubit, int size)
13298 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13299 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13300 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13301 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13302 inst.instruction |= LOW4 (inst.operands[2].reg);
13303 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13304 inst.instruction |= (isquad != 0) << 6;
13305 inst.instruction |= (ubit != 0) << 24;
13307 inst.instruction |= neon_logbits (size) << 20;
13309 neon_dp_fixup (&inst);
13312 /* Encode instructions of the form:
13314 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13315 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13317 Don't write size if SIZE == -1. */
13320 neon_two_same (int qbit, int ubit, int size)
13322 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13323 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13324 inst.instruction |= LOW4 (inst.operands[1].reg);
13325 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13326 inst.instruction |= (qbit != 0) << 6;
13327 inst.instruction |= (ubit != 0) << 24;
13330 inst.instruction |= neon_logbits (size) << 18;
13332 neon_dp_fixup (&inst);
13335 /* Neon instruction encoders, in approximate order of appearance. */
13338 do_neon_dyadic_i_su (void)
13340 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13341 struct neon_type_el et = neon_check_type (3, rs,
13342 N_EQK, N_EQK, N_SU_32 | N_KEY);
13343 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13347 do_neon_dyadic_i64_su (void)
13349 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13350 struct neon_type_el et = neon_check_type (3, rs,
13351 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13352 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13356 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13359 unsigned size = et.size >> 3;
13360 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13361 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13362 inst.instruction |= LOW4 (inst.operands[1].reg);
13363 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13364 inst.instruction |= (isquad != 0) << 6;
13365 inst.instruction |= immbits << 16;
13366 inst.instruction |= (size >> 3) << 7;
13367 inst.instruction |= (size & 0x7) << 19;
13369 inst.instruction |= (uval != 0) << 24;
13371 neon_dp_fixup (&inst);
13375 do_neon_shl_imm (void)
13377 if (!inst.operands[2].isreg)
13379 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13380 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13381 NEON_ENCODE (IMMED, inst);
13382 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13386 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13387 struct neon_type_el et = neon_check_type (3, rs,
13388 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13391 /* VSHL/VQSHL 3-register variants have syntax such as:
13393 whereas other 3-register operations encoded by neon_three_same have
13396 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13398 tmp = inst.operands[2].reg;
13399 inst.operands[2].reg = inst.operands[1].reg;
13400 inst.operands[1].reg = tmp;
13401 NEON_ENCODE (INTEGER, inst);
13402 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13407 do_neon_qshl_imm (void)
13409 if (!inst.operands[2].isreg)
13411 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13412 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13414 NEON_ENCODE (IMMED, inst);
13415 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13416 inst.operands[2].imm);
13420 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13421 struct neon_type_el et = neon_check_type (3, rs,
13422 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13425 /* See note in do_neon_shl_imm. */
13426 tmp = inst.operands[2].reg;
13427 inst.operands[2].reg = inst.operands[1].reg;
13428 inst.operands[1].reg = tmp;
13429 NEON_ENCODE (INTEGER, inst);
13430 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13435 do_neon_rshl (void)
13437 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13438 struct neon_type_el et = neon_check_type (3, rs,
13439 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13442 tmp = inst.operands[2].reg;
13443 inst.operands[2].reg = inst.operands[1].reg;
13444 inst.operands[1].reg = tmp;
13445 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13449 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13451 /* Handle .I8 pseudo-instructions. */
13454 /* Unfortunately, this will make everything apart from zero out-of-range.
13455 FIXME is this the intended semantics? There doesn't seem much point in
13456 accepting .I8 if so. */
13457 immediate |= immediate << 8;
13463 if (immediate == (immediate & 0x000000ff))
13465 *immbits = immediate;
13468 else if (immediate == (immediate & 0x0000ff00))
13470 *immbits = immediate >> 8;
13473 else if (immediate == (immediate & 0x00ff0000))
13475 *immbits = immediate >> 16;
13478 else if (immediate == (immediate & 0xff000000))
13480 *immbits = immediate >> 24;
13483 if ((immediate & 0xffff) != (immediate >> 16))
13484 goto bad_immediate;
13485 immediate &= 0xffff;
13488 if (immediate == (immediate & 0x000000ff))
13490 *immbits = immediate;
13493 else if (immediate == (immediate & 0x0000ff00))
13495 *immbits = immediate >> 8;
13500 first_error (_("immediate value out of range"));
13504 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13508 neon_bits_same_in_bytes (unsigned imm)
13510 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13511 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13512 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13513 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13516 /* For immediate of above form, return 0bABCD. */
13519 neon_squash_bits (unsigned imm)
13521 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13522 | ((imm & 0x01000000) >> 21);
13525 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13528 neon_qfloat_bits (unsigned imm)
13530 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13533 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13534 the instruction. *OP is passed as the initial value of the op field, and
13535 may be set to a different value depending on the constant (i.e.
13536 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13537 MVN). If the immediate looks like a repeated pattern then also
13538 try smaller element sizes. */
13541 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13542 unsigned *immbits, int *op, int size,
13543 enum neon_el_type type)
13545 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13547 if (type == NT_float && !float_p)
13550 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13552 if (size != 32 || *op == 1)
13554 *immbits = neon_qfloat_bits (immlo);
13560 if (neon_bits_same_in_bytes (immhi)
13561 && neon_bits_same_in_bytes (immlo))
13565 *immbits = (neon_squash_bits (immhi) << 4)
13566 | neon_squash_bits (immlo);
13571 if (immhi != immlo)
13577 if (immlo == (immlo & 0x000000ff))
13582 else if (immlo == (immlo & 0x0000ff00))
13584 *immbits = immlo >> 8;
13587 else if (immlo == (immlo & 0x00ff0000))
13589 *immbits = immlo >> 16;
13592 else if (immlo == (immlo & 0xff000000))
13594 *immbits = immlo >> 24;
13597 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13599 *immbits = (immlo >> 8) & 0xff;
13602 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13604 *immbits = (immlo >> 16) & 0xff;
13608 if ((immlo & 0xffff) != (immlo >> 16))
13615 if (immlo == (immlo & 0x000000ff))
13620 else if (immlo == (immlo & 0x0000ff00))
13622 *immbits = immlo >> 8;
13626 if ((immlo & 0xff) != (immlo >> 8))
13631 if (immlo == (immlo & 0x000000ff))
13633 /* Don't allow MVN with 8-bit immediate. */
13643 /* Write immediate bits [7:0] to the following locations:
13645 |28/24|23 19|18 16|15 4|3 0|
13646 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13648 This function is used by VMOV/VMVN/VORR/VBIC. */
13651 neon_write_immbits (unsigned immbits)
13653 inst.instruction |= immbits & 0xf;
13654 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13655 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13658 /* Invert low-order SIZE bits of XHI:XLO. */
13661 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13663 unsigned immlo = xlo ? *xlo : 0;
13664 unsigned immhi = xhi ? *xhi : 0;
13669 immlo = (~immlo) & 0xff;
13673 immlo = (~immlo) & 0xffff;
13677 immhi = (~immhi) & 0xffffffff;
13678 /* fall through. */
13681 immlo = (~immlo) & 0xffffffff;
13696 do_neon_logic (void)
13698 if (inst.operands[2].present && inst.operands[2].isreg)
13700 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13701 neon_check_type (3, rs, N_IGNORE_TYPE);
13702 /* U bit and size field were set as part of the bitmask. */
13703 NEON_ENCODE (INTEGER, inst);
13704 neon_three_same (neon_quad (rs), 0, -1);
13708 const int three_ops_form = (inst.operands[2].present
13709 && !inst.operands[2].isreg);
13710 const int immoperand = (three_ops_form ? 2 : 1);
13711 enum neon_shape rs = (three_ops_form
13712 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13713 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13714 struct neon_type_el et = neon_check_type (2, rs,
13715 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13716 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13720 if (et.type == NT_invtype)
13723 if (three_ops_form)
13724 constraint (inst.operands[0].reg != inst.operands[1].reg,
13725 _("first and second operands shall be the same register"));
13727 NEON_ENCODE (IMMED, inst);
13729 immbits = inst.operands[immoperand].imm;
13732 /* .i64 is a pseudo-op, so the immediate must be a repeating
13734 if (immbits != (inst.operands[immoperand].regisimm ?
13735 inst.operands[immoperand].reg : 0))
13737 /* Set immbits to an invalid constant. */
13738 immbits = 0xdeadbeef;
13745 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13749 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13753 /* Pseudo-instruction for VBIC. */
13754 neon_invert_size (&immbits, 0, et.size);
13755 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13759 /* Pseudo-instruction for VORR. */
13760 neon_invert_size (&immbits, 0, et.size);
13761 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13771 inst.instruction |= neon_quad (rs) << 6;
13772 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13773 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13774 inst.instruction |= cmode << 8;
13775 neon_write_immbits (immbits);
13777 neon_dp_fixup (&inst);
13782 do_neon_bitfield (void)
13784 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13785 neon_check_type (3, rs, N_IGNORE_TYPE);
13786 neon_three_same (neon_quad (rs), 0, -1);
13790 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13793 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13794 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13796 if (et.type == NT_float)
13798 NEON_ENCODE (FLOAT, inst);
13799 neon_three_same (neon_quad (rs), 0, -1);
13803 NEON_ENCODE (INTEGER, inst);
13804 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13809 do_neon_dyadic_if_su (void)
13811 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13815 do_neon_dyadic_if_su_d (void)
13817 /* This version only allow D registers, but that constraint is enforced during
13818 operand parsing so we don't need to do anything extra here. */
13819 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13823 do_neon_dyadic_if_i_d (void)
13825 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13826 affected if we specify unsigned args. */
13827 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13830 enum vfp_or_neon_is_neon_bits
13833 NEON_CHECK_ARCH = 2
13836 /* Call this function if an instruction which may have belonged to the VFP or
13837 Neon instruction sets, but turned out to be a Neon instruction (due to the
13838 operand types involved, etc.). We have to check and/or fix-up a couple of
13841 - Make sure the user hasn't attempted to make a Neon instruction
13843 - Alter the value in the condition code field if necessary.
13844 - Make sure that the arch supports Neon instructions.
13846 Which of these operations take place depends on bits from enum
13847 vfp_or_neon_is_neon_bits.
13849 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13850 current instruction's condition is COND_ALWAYS, the condition field is
13851 changed to inst.uncond_value. This is necessary because instructions shared
13852 between VFP and Neon may be conditional for the VFP variants only, and the
13853 unconditional Neon version must have, e.g., 0xF in the condition field. */
13856 vfp_or_neon_is_neon (unsigned check)
13858 /* Conditions are always legal in Thumb mode (IT blocks). */
13859 if (!thumb_mode && (check & NEON_CHECK_CC))
13861 if (inst.cond != COND_ALWAYS)
13863 first_error (_(BAD_COND));
13866 if (inst.uncond_value != -1)
13867 inst.instruction |= inst.uncond_value << 28;
13870 if ((check & NEON_CHECK_ARCH)
13871 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13873 first_error (_(BAD_FPU));
13881 do_neon_addsub_if_i (void)
13883 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13886 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13889 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13890 affected if we specify unsigned args. */
13891 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13894 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13896 V<op> A,B (A is operand 0, B is operand 2)
13901 so handle that case specially. */
13904 neon_exchange_operands (void)
13906 void *scratch = alloca (sizeof (inst.operands[0]));
13907 if (inst.operands[1].present)
13909 /* Swap operands[1] and operands[2]. */
13910 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13911 inst.operands[1] = inst.operands[2];
13912 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13916 inst.operands[1] = inst.operands[2];
13917 inst.operands[2] = inst.operands[0];
13922 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13924 if (inst.operands[2].isreg)
13927 neon_exchange_operands ();
13928 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13932 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13933 struct neon_type_el et = neon_check_type (2, rs,
13934 N_EQK | N_SIZ, immtypes | N_KEY);
13936 NEON_ENCODE (IMMED, inst);
13937 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13938 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13939 inst.instruction |= LOW4 (inst.operands[1].reg);
13940 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13941 inst.instruction |= neon_quad (rs) << 6;
13942 inst.instruction |= (et.type == NT_float) << 10;
13943 inst.instruction |= neon_logbits (et.size) << 18;
13945 neon_dp_fixup (&inst);
13952 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13956 do_neon_cmp_inv (void)
13958 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13964 neon_compare (N_IF_32, N_IF_32, FALSE);
13967 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13968 scalars, which are encoded in 5 bits, M : Rm.
13969 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13970 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13974 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13976 unsigned regno = NEON_SCALAR_REG (scalar);
13977 unsigned elno = NEON_SCALAR_INDEX (scalar);
13982 if (regno > 7 || elno > 3)
13984 return regno | (elno << 3);
13987 if (regno > 15 || elno > 1)
13989 return regno | (elno << 4);
13993 first_error (_("scalar out of range for multiply instruction"));
13999 /* Encode multiply / multiply-accumulate scalar instructions. */
14002 neon_mul_mac (struct neon_type_el et, int ubit)
14006 /* Give a more helpful error message if we have an invalid type. */
14007 if (et.type == NT_invtype)
14010 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14011 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14012 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14013 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14014 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14015 inst.instruction |= LOW4 (scalar);
14016 inst.instruction |= HI1 (scalar) << 5;
14017 inst.instruction |= (et.type == NT_float) << 8;
14018 inst.instruction |= neon_logbits (et.size) << 20;
14019 inst.instruction |= (ubit != 0) << 24;
14021 neon_dp_fixup (&inst);
14025 do_neon_mac_maybe_scalar (void)
14027 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14030 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14033 if (inst.operands[2].isscalar)
14035 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14036 struct neon_type_el et = neon_check_type (3, rs,
14037 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14038 NEON_ENCODE (SCALAR, inst);
14039 neon_mul_mac (et, neon_quad (rs));
14043 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14044 affected if we specify unsigned args. */
14045 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14050 do_neon_fmac (void)
14052 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14055 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14058 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14064 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14065 struct neon_type_el et = neon_check_type (3, rs,
14066 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14067 neon_three_same (neon_quad (rs), 0, et.size);
14070 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14071 same types as the MAC equivalents. The polynomial type for this instruction
14072 is encoded the same as the integer type. */
14077 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14080 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14083 if (inst.operands[2].isscalar)
14084 do_neon_mac_maybe_scalar ();
14086 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14090 do_neon_qdmulh (void)
14092 if (inst.operands[2].isscalar)
14094 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14095 struct neon_type_el et = neon_check_type (3, rs,
14096 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14097 NEON_ENCODE (SCALAR, inst);
14098 neon_mul_mac (et, neon_quad (rs));
14102 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14103 struct neon_type_el et = neon_check_type (3, rs,
14104 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14105 NEON_ENCODE (INTEGER, inst);
14106 /* The U bit (rounding) comes from bit mask. */
14107 neon_three_same (neon_quad (rs), 0, et.size);
14112 do_neon_fcmp_absolute (void)
14114 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14115 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14116 /* Size field comes from bit mask. */
14117 neon_three_same (neon_quad (rs), 1, -1);
14121 do_neon_fcmp_absolute_inv (void)
14123 neon_exchange_operands ();
14124 do_neon_fcmp_absolute ();
14128 do_neon_step (void)
14130 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14131 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14132 neon_three_same (neon_quad (rs), 0, -1);
14136 do_neon_abs_neg (void)
14138 enum neon_shape rs;
14139 struct neon_type_el et;
14141 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14144 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14147 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14148 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14150 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14151 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14152 inst.instruction |= LOW4 (inst.operands[1].reg);
14153 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14154 inst.instruction |= neon_quad (rs) << 6;
14155 inst.instruction |= (et.type == NT_float) << 10;
14156 inst.instruction |= neon_logbits (et.size) << 18;
14158 neon_dp_fixup (&inst);
14164 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14165 struct neon_type_el et = neon_check_type (2, rs,
14166 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14167 int imm = inst.operands[2].imm;
14168 constraint (imm < 0 || (unsigned)imm >= et.size,
14169 _("immediate out of range for insert"));
14170 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14176 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14177 struct neon_type_el et = neon_check_type (2, rs,
14178 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14179 int imm = inst.operands[2].imm;
14180 constraint (imm < 1 || (unsigned)imm > et.size,
14181 _("immediate out of range for insert"));
14182 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14186 do_neon_qshlu_imm (void)
14188 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14189 struct neon_type_el et = neon_check_type (2, rs,
14190 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14191 int imm = inst.operands[2].imm;
14192 constraint (imm < 0 || (unsigned)imm >= et.size,
14193 _("immediate out of range for shift"));
14194 /* Only encodes the 'U present' variant of the instruction.
14195 In this case, signed types have OP (bit 8) set to 0.
14196 Unsigned types have OP set to 1. */
14197 inst.instruction |= (et.type == NT_unsigned) << 8;
14198 /* The rest of the bits are the same as other immediate shifts. */
14199 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14203 do_neon_qmovn (void)
14205 struct neon_type_el et = neon_check_type (2, NS_DQ,
14206 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14207 /* Saturating move where operands can be signed or unsigned, and the
14208 destination has the same signedness. */
14209 NEON_ENCODE (INTEGER, inst);
14210 if (et.type == NT_unsigned)
14211 inst.instruction |= 0xc0;
14213 inst.instruction |= 0x80;
14214 neon_two_same (0, 1, et.size / 2);
14218 do_neon_qmovun (void)
14220 struct neon_type_el et = neon_check_type (2, NS_DQ,
14221 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14222 /* Saturating move with unsigned results. Operands must be signed. */
14223 NEON_ENCODE (INTEGER, inst);
14224 neon_two_same (0, 1, et.size / 2);
14228 do_neon_rshift_sat_narrow (void)
14230 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14231 or unsigned. If operands are unsigned, results must also be unsigned. */
14232 struct neon_type_el et = neon_check_type (2, NS_DQI,
14233 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14234 int imm = inst.operands[2].imm;
14235 /* This gets the bounds check, size encoding and immediate bits calculation
14239 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14240 VQMOVN.I<size> <Dd>, <Qm>. */
14243 inst.operands[2].present = 0;
14244 inst.instruction = N_MNEM_vqmovn;
14249 constraint (imm < 1 || (unsigned)imm > et.size,
14250 _("immediate out of range"));
14251 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14255 do_neon_rshift_sat_narrow_u (void)
14257 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14258 or unsigned. If operands are unsigned, results must also be unsigned. */
14259 struct neon_type_el et = neon_check_type (2, NS_DQI,
14260 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14261 int imm = inst.operands[2].imm;
14262 /* This gets the bounds check, size encoding and immediate bits calculation
14266 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14267 VQMOVUN.I<size> <Dd>, <Qm>. */
14270 inst.operands[2].present = 0;
14271 inst.instruction = N_MNEM_vqmovun;
14276 constraint (imm < 1 || (unsigned)imm > et.size,
14277 _("immediate out of range"));
14278 /* FIXME: The manual is kind of unclear about what value U should have in
14279 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14281 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14285 do_neon_movn (void)
14287 struct neon_type_el et = neon_check_type (2, NS_DQ,
14288 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14289 NEON_ENCODE (INTEGER, inst);
14290 neon_two_same (0, 1, et.size / 2);
14294 do_neon_rshift_narrow (void)
14296 struct neon_type_el et = neon_check_type (2, NS_DQI,
14297 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14298 int imm = inst.operands[2].imm;
14299 /* This gets the bounds check, size encoding and immediate bits calculation
14303 /* If immediate is zero then we are a pseudo-instruction for
14304 VMOVN.I<size> <Dd>, <Qm> */
14307 inst.operands[2].present = 0;
14308 inst.instruction = N_MNEM_vmovn;
14313 constraint (imm < 1 || (unsigned)imm > et.size,
14314 _("immediate out of range for narrowing operation"));
14315 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14319 do_neon_shll (void)
14321 /* FIXME: Type checking when lengthening. */
14322 struct neon_type_el et = neon_check_type (2, NS_QDI,
14323 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14324 unsigned imm = inst.operands[2].imm;
14326 if (imm == et.size)
14328 /* Maximum shift variant. */
14329 NEON_ENCODE (INTEGER, inst);
14330 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14331 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14332 inst.instruction |= LOW4 (inst.operands[1].reg);
14333 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14334 inst.instruction |= neon_logbits (et.size) << 18;
14336 neon_dp_fixup (&inst);
14340 /* A more-specific type check for non-max versions. */
14341 et = neon_check_type (2, NS_QDI,
14342 N_EQK | N_DBL, N_SU_32 | N_KEY);
14343 NEON_ENCODE (IMMED, inst);
14344 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14348 /* Check the various types for the VCVT instruction, and return which version
14349 the current instruction is. */
14352 neon_cvt_flavour (enum neon_shape rs)
14354 #define CVT_VAR(C,X,Y) \
14355 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14356 if (et.type != NT_invtype) \
14358 inst.error = NULL; \
14361 struct neon_type_el et;
14362 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14363 || rs == NS_FF) ? N_VFP : 0;
14364 /* The instruction versions which take an immediate take one register
14365 argument, which is extended to the width of the full register. Thus the
14366 "source" and "destination" registers must have the same width. Hack that
14367 here by making the size equal to the key (wider, in this case) operand. */
14368 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14370 CVT_VAR (0, N_S32, N_F32);
14371 CVT_VAR (1, N_U32, N_F32);
14372 CVT_VAR (2, N_F32, N_S32);
14373 CVT_VAR (3, N_F32, N_U32);
14374 /* Half-precision conversions. */
14375 CVT_VAR (4, N_F32, N_F16);
14376 CVT_VAR (5, N_F16, N_F32);
14380 /* VFP instructions. */
14381 CVT_VAR (6, N_F32, N_F64);
14382 CVT_VAR (7, N_F64, N_F32);
14383 CVT_VAR (8, N_S32, N_F64 | key);
14384 CVT_VAR (9, N_U32, N_F64 | key);
14385 CVT_VAR (10, N_F64 | key, N_S32);
14386 CVT_VAR (11, N_F64 | key, N_U32);
14387 /* VFP instructions with bitshift. */
14388 CVT_VAR (12, N_F32 | key, N_S16);
14389 CVT_VAR (13, N_F32 | key, N_U16);
14390 CVT_VAR (14, N_F64 | key, N_S16);
14391 CVT_VAR (15, N_F64 | key, N_U16);
14392 CVT_VAR (16, N_S16, N_F32 | key);
14393 CVT_VAR (17, N_U16, N_F32 | key);
14394 CVT_VAR (18, N_S16, N_F64 | key);
14395 CVT_VAR (19, N_U16, N_F64 | key);
14401 /* Neon-syntax VFP conversions. */
14404 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14406 const char *opname = 0;
14408 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14410 /* Conversions with immediate bitshift. */
14411 const char *enc[] =
14435 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14437 opname = enc[flavour];
14438 constraint (inst.operands[0].reg != inst.operands[1].reg,
14439 _("operands 0 and 1 must be the same register"));
14440 inst.operands[1] = inst.operands[2];
14441 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14446 /* Conversions without bitshift. */
14447 const char *enc[] =
14463 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14464 opname = enc[flavour];
14468 do_vfp_nsyn_opcode (opname);
14472 do_vfp_nsyn_cvtz (void)
14474 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14475 int flavour = neon_cvt_flavour (rs);
14476 const char *enc[] =
14490 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14491 do_vfp_nsyn_opcode (enc[flavour]);
14495 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14497 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14498 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14499 int flavour = neon_cvt_flavour (rs);
14501 /* PR11109: Handle round-to-zero for VCVT conversions. */
14503 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14504 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14505 && (rs == NS_FD || rs == NS_FF))
14507 do_vfp_nsyn_cvtz ();
14511 /* VFP rather than Neon conversions. */
14514 do_vfp_nsyn_cvt (rs, flavour);
14524 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14526 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14529 /* Fixed-point conversion with #0 immediate is encoded as an
14530 integer conversion. */
14531 if (inst.operands[2].present && inst.operands[2].imm == 0)
14533 immbits = 32 - inst.operands[2].imm;
14534 NEON_ENCODE (IMMED, inst);
14536 inst.instruction |= enctab[flavour];
14537 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14538 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14539 inst.instruction |= LOW4 (inst.operands[1].reg);
14540 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14541 inst.instruction |= neon_quad (rs) << 6;
14542 inst.instruction |= 1 << 21;
14543 inst.instruction |= immbits << 16;
14545 neon_dp_fixup (&inst);
14553 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14555 NEON_ENCODE (INTEGER, inst);
14557 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14561 inst.instruction |= enctab[flavour];
14563 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14564 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14565 inst.instruction |= LOW4 (inst.operands[1].reg);
14566 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14567 inst.instruction |= neon_quad (rs) << 6;
14568 inst.instruction |= 2 << 18;
14570 neon_dp_fixup (&inst);
14574 /* Half-precision conversions for Advanced SIMD -- neon. */
14579 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14581 as_bad (_("operand size must match register width"));
14586 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14588 as_bad (_("operand size must match register width"));
14593 inst.instruction = 0x3b60600;
14595 inst.instruction = 0x3b60700;
14597 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14598 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14599 inst.instruction |= LOW4 (inst.operands[1].reg);
14600 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14601 neon_dp_fixup (&inst);
14605 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14606 do_vfp_nsyn_cvt (rs, flavour);
14611 do_neon_cvtr (void)
14613 do_neon_cvt_1 (FALSE);
14619 do_neon_cvt_1 (TRUE);
14623 do_neon_cvtb (void)
14625 inst.instruction = 0xeb20a40;
14627 /* The sizes are attached to the mnemonic. */
14628 if (inst.vectype.el[0].type != NT_invtype
14629 && inst.vectype.el[0].size == 16)
14630 inst.instruction |= 0x00010000;
14632 /* Programmer's syntax: the sizes are attached to the operands. */
14633 else if (inst.operands[0].vectype.type != NT_invtype
14634 && inst.operands[0].vectype.size == 16)
14635 inst.instruction |= 0x00010000;
14637 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14638 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14639 do_vfp_cond_or_thumb ();
14644 do_neon_cvtt (void)
14647 inst.instruction |= 0x80;
14651 neon_move_immediate (void)
14653 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14654 struct neon_type_el et = neon_check_type (2, rs,
14655 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14656 unsigned immlo, immhi = 0, immbits;
14657 int op, cmode, float_p;
14659 constraint (et.type == NT_invtype,
14660 _("operand size must be specified for immediate VMOV"));
14662 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14663 op = (inst.instruction & (1 << 5)) != 0;
14665 immlo = inst.operands[1].imm;
14666 if (inst.operands[1].regisimm)
14667 immhi = inst.operands[1].reg;
14669 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14670 _("immediate has bits set outside the operand size"));
14672 float_p = inst.operands[1].immisfloat;
14674 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14675 et.size, et.type)) == FAIL)
14677 /* Invert relevant bits only. */
14678 neon_invert_size (&immlo, &immhi, et.size);
14679 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14680 with one or the other; those cases are caught by
14681 neon_cmode_for_move_imm. */
14683 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14684 &op, et.size, et.type)) == FAIL)
14686 first_error (_("immediate out of range"));
14691 inst.instruction &= ~(1 << 5);
14692 inst.instruction |= op << 5;
14694 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14695 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14696 inst.instruction |= neon_quad (rs) << 6;
14697 inst.instruction |= cmode << 8;
14699 neon_write_immbits (immbits);
14705 if (inst.operands[1].isreg)
14707 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14709 NEON_ENCODE (INTEGER, inst);
14710 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14711 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14712 inst.instruction |= LOW4 (inst.operands[1].reg);
14713 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14714 inst.instruction |= neon_quad (rs) << 6;
14718 NEON_ENCODE (IMMED, inst);
14719 neon_move_immediate ();
14722 neon_dp_fixup (&inst);
14725 /* Encode instructions of form:
14727 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14728 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14731 neon_mixed_length (struct neon_type_el et, unsigned size)
14733 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14734 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14735 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14736 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14737 inst.instruction |= LOW4 (inst.operands[2].reg);
14738 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14739 inst.instruction |= (et.type == NT_unsigned) << 24;
14740 inst.instruction |= neon_logbits (size) << 20;
14742 neon_dp_fixup (&inst);
14746 do_neon_dyadic_long (void)
14748 /* FIXME: Type checking for lengthening op. */
14749 struct neon_type_el et = neon_check_type (3, NS_QDD,
14750 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14751 neon_mixed_length (et, et.size);
14755 do_neon_abal (void)
14757 struct neon_type_el et = neon_check_type (3, NS_QDD,
14758 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14759 neon_mixed_length (et, et.size);
14763 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14765 if (inst.operands[2].isscalar)
14767 struct neon_type_el et = neon_check_type (3, NS_QDS,
14768 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14769 NEON_ENCODE (SCALAR, inst);
14770 neon_mul_mac (et, et.type == NT_unsigned);
14774 struct neon_type_el et = neon_check_type (3, NS_QDD,
14775 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14776 NEON_ENCODE (INTEGER, inst);
14777 neon_mixed_length (et, et.size);
14782 do_neon_mac_maybe_scalar_long (void)
14784 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14788 do_neon_dyadic_wide (void)
14790 struct neon_type_el et = neon_check_type (3, NS_QQD,
14791 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14792 neon_mixed_length (et, et.size);
14796 do_neon_dyadic_narrow (void)
14798 struct neon_type_el et = neon_check_type (3, NS_QDD,
14799 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14800 /* Operand sign is unimportant, and the U bit is part of the opcode,
14801 so force the operand type to integer. */
14802 et.type = NT_integer;
14803 neon_mixed_length (et, et.size / 2);
14807 do_neon_mul_sat_scalar_long (void)
14809 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14813 do_neon_vmull (void)
14815 if (inst.operands[2].isscalar)
14816 do_neon_mac_maybe_scalar_long ();
14819 struct neon_type_el et = neon_check_type (3, NS_QDD,
14820 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14821 if (et.type == NT_poly)
14822 NEON_ENCODE (POLY, inst);
14824 NEON_ENCODE (INTEGER, inst);
14825 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14826 zero. Should be OK as-is. */
14827 neon_mixed_length (et, et.size);
14834 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14835 struct neon_type_el et = neon_check_type (3, rs,
14836 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14837 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14839 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14840 _("shift out of range"));
14841 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14842 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14843 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14844 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14845 inst.instruction |= LOW4 (inst.operands[2].reg);
14846 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14847 inst.instruction |= neon_quad (rs) << 6;
14848 inst.instruction |= imm << 8;
14850 neon_dp_fixup (&inst);
14856 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14857 struct neon_type_el et = neon_check_type (2, rs,
14858 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14859 unsigned op = (inst.instruction >> 7) & 3;
14860 /* N (width of reversed regions) is encoded as part of the bitmask. We
14861 extract it here to check the elements to be reversed are smaller.
14862 Otherwise we'd get a reserved instruction. */
14863 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14864 gas_assert (elsize != 0);
14865 constraint (et.size >= elsize,
14866 _("elements must be smaller than reversal region"));
14867 neon_two_same (neon_quad (rs), 1, et.size);
14873 if (inst.operands[1].isscalar)
14875 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14876 struct neon_type_el et = neon_check_type (2, rs,
14877 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14878 unsigned sizebits = et.size >> 3;
14879 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14880 int logsize = neon_logbits (et.size);
14881 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14883 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14886 NEON_ENCODE (SCALAR, inst);
14887 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14888 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14889 inst.instruction |= LOW4 (dm);
14890 inst.instruction |= HI1 (dm) << 5;
14891 inst.instruction |= neon_quad (rs) << 6;
14892 inst.instruction |= x << 17;
14893 inst.instruction |= sizebits << 16;
14895 neon_dp_fixup (&inst);
14899 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14900 struct neon_type_el et = neon_check_type (2, rs,
14901 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14902 /* Duplicate ARM register to lanes of vector. */
14903 NEON_ENCODE (ARMREG, inst);
14906 case 8: inst.instruction |= 0x400000; break;
14907 case 16: inst.instruction |= 0x000020; break;
14908 case 32: inst.instruction |= 0x000000; break;
14911 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14912 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14913 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14914 inst.instruction |= neon_quad (rs) << 21;
14915 /* The encoding for this instruction is identical for the ARM and Thumb
14916 variants, except for the condition field. */
14917 do_vfp_cond_or_thumb ();
14921 /* VMOV has particularly many variations. It can be one of:
14922 0. VMOV<c><q> <Qd>, <Qm>
14923 1. VMOV<c><q> <Dd>, <Dm>
14924 (Register operations, which are VORR with Rm = Rn.)
14925 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14926 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14928 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14929 (ARM register to scalar.)
14930 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14931 (Two ARM registers to vector.)
14932 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14933 (Scalar to ARM register.)
14934 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14935 (Vector to two ARM registers.)
14936 8. VMOV.F32 <Sd>, <Sm>
14937 9. VMOV.F64 <Dd>, <Dm>
14938 (VFP register moves.)
14939 10. VMOV.F32 <Sd>, #imm
14940 11. VMOV.F64 <Dd>, #imm
14941 (VFP float immediate load.)
14942 12. VMOV <Rd>, <Sm>
14943 (VFP single to ARM reg.)
14944 13. VMOV <Sd>, <Rm>
14945 (ARM reg to VFP single.)
14946 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14947 (Two ARM regs to two VFP singles.)
14948 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14949 (Two VFP singles to two ARM regs.)
14951 These cases can be disambiguated using neon_select_shape, except cases 1/9
14952 and 3/11 which depend on the operand type too.
14954 All the encoded bits are hardcoded by this function.
14956 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14957 Cases 5, 7 may be used with VFPv2 and above.
14959 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14960 can specify a type where it doesn't make sense to, and is ignored). */
14965 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14966 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14968 struct neon_type_el et;
14969 const char *ldconst = 0;
14973 case NS_DD: /* case 1/9. */
14974 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14975 /* It is not an error here if no type is given. */
14977 if (et.type == NT_float && et.size == 64)
14979 do_vfp_nsyn_opcode ("fcpyd");
14982 /* fall through. */
14984 case NS_QQ: /* case 0/1. */
14986 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14988 /* The architecture manual I have doesn't explicitly state which
14989 value the U bit should have for register->register moves, but
14990 the equivalent VORR instruction has U = 0, so do that. */
14991 inst.instruction = 0x0200110;
14992 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14993 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14994 inst.instruction |= LOW4 (inst.operands[1].reg);
14995 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14996 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14997 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14998 inst.instruction |= neon_quad (rs) << 6;
15000 neon_dp_fixup (&inst);
15004 case NS_DI: /* case 3/11. */
15005 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15007 if (et.type == NT_float && et.size == 64)
15009 /* case 11 (fconstd). */
15010 ldconst = "fconstd";
15011 goto encode_fconstd;
15013 /* fall through. */
15015 case NS_QI: /* case 2/3. */
15016 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15018 inst.instruction = 0x0800010;
15019 neon_move_immediate ();
15020 neon_dp_fixup (&inst);
15023 case NS_SR: /* case 4. */
15025 unsigned bcdebits = 0;
15027 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15028 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15030 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15031 logsize = neon_logbits (et.size);
15033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15036 && et.size != 32, _(BAD_FPU));
15037 constraint (et.type == NT_invtype, _("bad type for scalar"));
15038 constraint (x >= 64 / et.size, _("scalar index out of range"));
15042 case 8: bcdebits = 0x8; break;
15043 case 16: bcdebits = 0x1; break;
15044 case 32: bcdebits = 0x0; break;
15048 bcdebits |= x << logsize;
15050 inst.instruction = 0xe000b10;
15051 do_vfp_cond_or_thumb ();
15052 inst.instruction |= LOW4 (dn) << 16;
15053 inst.instruction |= HI1 (dn) << 7;
15054 inst.instruction |= inst.operands[1].reg << 12;
15055 inst.instruction |= (bcdebits & 3) << 5;
15056 inst.instruction |= (bcdebits >> 2) << 21;
15060 case NS_DRR: /* case 5 (fmdrr). */
15061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15064 inst.instruction = 0xc400b10;
15065 do_vfp_cond_or_thumb ();
15066 inst.instruction |= LOW4 (inst.operands[0].reg);
15067 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15068 inst.instruction |= inst.operands[1].reg << 12;
15069 inst.instruction |= inst.operands[2].reg << 16;
15072 case NS_RS: /* case 6. */
15075 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15076 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15077 unsigned abcdebits = 0;
15079 et = neon_check_type (2, NS_NULL,
15080 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15081 logsize = neon_logbits (et.size);
15083 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15086 && et.size != 32, _(BAD_FPU));
15087 constraint (et.type == NT_invtype, _("bad type for scalar"));
15088 constraint (x >= 64 / et.size, _("scalar index out of range"));
15092 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15093 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15094 case 32: abcdebits = 0x00; break;
15098 abcdebits |= x << logsize;
15099 inst.instruction = 0xe100b10;
15100 do_vfp_cond_or_thumb ();
15101 inst.instruction |= LOW4 (dn) << 16;
15102 inst.instruction |= HI1 (dn) << 7;
15103 inst.instruction |= inst.operands[0].reg << 12;
15104 inst.instruction |= (abcdebits & 3) << 5;
15105 inst.instruction |= (abcdebits >> 2) << 21;
15109 case NS_RRD: /* case 7 (fmrrd). */
15110 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15113 inst.instruction = 0xc500b10;
15114 do_vfp_cond_or_thumb ();
15115 inst.instruction |= inst.operands[0].reg << 12;
15116 inst.instruction |= inst.operands[1].reg << 16;
15117 inst.instruction |= LOW4 (inst.operands[2].reg);
15118 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15121 case NS_FF: /* case 8 (fcpys). */
15122 do_vfp_nsyn_opcode ("fcpys");
15125 case NS_FI: /* case 10 (fconsts). */
15126 ldconst = "fconsts";
15128 if (is_quarter_float (inst.operands[1].imm))
15130 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15131 do_vfp_nsyn_opcode (ldconst);
15134 first_error (_("immediate out of range"));
15137 case NS_RF: /* case 12 (fmrs). */
15138 do_vfp_nsyn_opcode ("fmrs");
15141 case NS_FR: /* case 13 (fmsr). */
15142 do_vfp_nsyn_opcode ("fmsr");
15145 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15146 (one of which is a list), but we have parsed four. Do some fiddling to
15147 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15149 case NS_RRFF: /* case 14 (fmrrs). */
15150 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15151 _("VFP registers must be adjacent"));
15152 inst.operands[2].imm = 2;
15153 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15154 do_vfp_nsyn_opcode ("fmrrs");
15157 case NS_FFRR: /* case 15 (fmsrr). */
15158 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15159 _("VFP registers must be adjacent"));
15160 inst.operands[1] = inst.operands[2];
15161 inst.operands[2] = inst.operands[3];
15162 inst.operands[0].imm = 2;
15163 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15164 do_vfp_nsyn_opcode ("fmsrr");
15173 do_neon_rshift_round_imm (void)
15175 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15176 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15177 int imm = inst.operands[2].imm;
15179 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15182 inst.operands[2].present = 0;
15187 constraint (imm < 1 || (unsigned)imm > et.size,
15188 _("immediate out of range for shift"));
15189 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15194 do_neon_movl (void)
15196 struct neon_type_el et = neon_check_type (2, NS_QD,
15197 N_EQK | N_DBL, N_SU_32 | N_KEY);
15198 unsigned sizebits = et.size >> 3;
15199 inst.instruction |= sizebits << 19;
15200 neon_two_same (0, et.type == NT_unsigned, -1);
15206 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15207 struct neon_type_el et = neon_check_type (2, rs,
15208 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15209 NEON_ENCODE (INTEGER, inst);
15210 neon_two_same (neon_quad (rs), 1, et.size);
15214 do_neon_zip_uzp (void)
15216 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15217 struct neon_type_el et = neon_check_type (2, rs,
15218 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15219 if (rs == NS_DD && et.size == 32)
15221 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15222 inst.instruction = N_MNEM_vtrn;
15226 neon_two_same (neon_quad (rs), 1, et.size);
15230 do_neon_sat_abs_neg (void)
15232 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15233 struct neon_type_el et = neon_check_type (2, rs,
15234 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15235 neon_two_same (neon_quad (rs), 1, et.size);
15239 do_neon_pair_long (void)
15241 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15242 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15243 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15244 inst.instruction |= (et.type == NT_unsigned) << 7;
15245 neon_two_same (neon_quad (rs), 1, et.size);
15249 do_neon_recip_est (void)
15251 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15252 struct neon_type_el et = neon_check_type (2, rs,
15253 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15254 inst.instruction |= (et.type == NT_float) << 8;
15255 neon_two_same (neon_quad (rs), 1, et.size);
15261 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15262 struct neon_type_el et = neon_check_type (2, rs,
15263 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15264 neon_two_same (neon_quad (rs), 1, et.size);
15270 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15271 struct neon_type_el et = neon_check_type (2, rs,
15272 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15273 neon_two_same (neon_quad (rs), 1, et.size);
15279 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15280 struct neon_type_el et = neon_check_type (2, rs,
15281 N_EQK | N_INT, N_8 | N_KEY);
15282 neon_two_same (neon_quad (rs), 1, et.size);
15288 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15289 neon_two_same (neon_quad (rs), 1, -1);
15293 do_neon_tbl_tbx (void)
15295 unsigned listlenbits;
15296 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15298 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15300 first_error (_("bad list length for table lookup"));
15304 listlenbits = inst.operands[1].imm - 1;
15305 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15306 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15307 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15308 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15309 inst.instruction |= LOW4 (inst.operands[2].reg);
15310 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15311 inst.instruction |= listlenbits << 8;
15313 neon_dp_fixup (&inst);
15317 do_neon_ldm_stm (void)
15319 /* P, U and L bits are part of bitmask. */
15320 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15321 unsigned offsetbits = inst.operands[1].imm * 2;
15323 if (inst.operands[1].issingle)
15325 do_vfp_nsyn_ldm_stm (is_dbmode);
15329 constraint (is_dbmode && !inst.operands[0].writeback,
15330 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15332 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15333 _("register list must contain at least 1 and at most 16 "
15336 inst.instruction |= inst.operands[0].reg << 16;
15337 inst.instruction |= inst.operands[0].writeback << 21;
15338 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15339 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15341 inst.instruction |= offsetbits;
15343 do_vfp_cond_or_thumb ();
15347 do_neon_ldr_str (void)
15349 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15351 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15352 And is UNPREDICTABLE in thumb mode. */
15354 && inst.operands[1].reg == REG_PC
15355 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15357 if (!thumb_mode && warn_on_deprecated)
15358 as_warn (_("Use of PC here is deprecated"));
15360 inst.error = _("Use of PC here is UNPREDICTABLE");
15363 if (inst.operands[0].issingle)
15366 do_vfp_nsyn_opcode ("flds");
15368 do_vfp_nsyn_opcode ("fsts");
15373 do_vfp_nsyn_opcode ("fldd");
15375 do_vfp_nsyn_opcode ("fstd");
15379 /* "interleave" version also handles non-interleaving register VLD1/VST1
15383 do_neon_ld_st_interleave (void)
15385 struct neon_type_el et = neon_check_type (1, NS_NULL,
15386 N_8 | N_16 | N_32 | N_64);
15387 unsigned alignbits = 0;
15389 /* The bits in this table go:
15390 0: register stride of one (0) or two (1)
15391 1,2: register list length, minus one (1, 2, 3, 4).
15392 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15393 We use -1 for invalid entries. */
15394 const int typetable[] =
15396 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15397 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15398 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15399 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15403 if (et.type == NT_invtype)
15406 if (inst.operands[1].immisalign)
15407 switch (inst.operands[1].imm >> 8)
15409 case 64: alignbits = 1; break;
15411 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15412 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15413 goto bad_alignment;
15417 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15418 goto bad_alignment;
15423 first_error (_("bad alignment"));
15427 inst.instruction |= alignbits << 4;
15428 inst.instruction |= neon_logbits (et.size) << 6;
15430 /* Bits [4:6] of the immediate in a list specifier encode register stride
15431 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15432 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15433 up the right value for "type" in a table based on this value and the given
15434 list style, then stick it back. */
15435 idx = ((inst.operands[0].imm >> 4) & 7)
15436 | (((inst.instruction >> 8) & 3) << 3);
15438 typebits = typetable[idx];
15440 constraint (typebits == -1, _("bad list type for instruction"));
15442 inst.instruction &= ~0xf00;
15443 inst.instruction |= typebits << 8;
15446 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15447 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15448 otherwise. The variable arguments are a list of pairs of legal (size, align)
15449 values, terminated with -1. */
15452 neon_alignment_bit (int size, int align, int *do_align, ...)
15455 int result = FAIL, thissize, thisalign;
15457 if (!inst.operands[1].immisalign)
15463 va_start (ap, do_align);
15467 thissize = va_arg (ap, int);
15468 if (thissize == -1)
15470 thisalign = va_arg (ap, int);
15472 if (size == thissize && align == thisalign)
15475 while (result != SUCCESS);
15479 if (result == SUCCESS)
15482 first_error (_("unsupported alignment for instruction"));
15488 do_neon_ld_st_lane (void)
15490 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15491 int align_good, do_align = 0;
15492 int logsize = neon_logbits (et.size);
15493 int align = inst.operands[1].imm >> 8;
15494 int n = (inst.instruction >> 8) & 3;
15495 int max_el = 64 / et.size;
15497 if (et.type == NT_invtype)
15500 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15501 _("bad list length"));
15502 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15503 _("scalar index out of range"));
15504 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15506 _("stride of 2 unavailable when element size is 8"));
15510 case 0: /* VLD1 / VST1. */
15511 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15513 if (align_good == FAIL)
15517 unsigned alignbits = 0;
15520 case 16: alignbits = 0x1; break;
15521 case 32: alignbits = 0x3; break;
15524 inst.instruction |= alignbits << 4;
15528 case 1: /* VLD2 / VST2. */
15529 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15531 if (align_good == FAIL)
15534 inst.instruction |= 1 << 4;
15537 case 2: /* VLD3 / VST3. */
15538 constraint (inst.operands[1].immisalign,
15539 _("can't use alignment with this instruction"));
15542 case 3: /* VLD4 / VST4. */
15543 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15544 16, 64, 32, 64, 32, 128, -1);
15545 if (align_good == FAIL)
15549 unsigned alignbits = 0;
15552 case 8: alignbits = 0x1; break;
15553 case 16: alignbits = 0x1; break;
15554 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15557 inst.instruction |= alignbits << 4;
15564 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15565 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15566 inst.instruction |= 1 << (4 + logsize);
15568 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15569 inst.instruction |= logsize << 10;
15572 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15575 do_neon_ld_dup (void)
15577 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15578 int align_good, do_align = 0;
15580 if (et.type == NT_invtype)
15583 switch ((inst.instruction >> 8) & 3)
15585 case 0: /* VLD1. */
15586 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15587 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15588 &do_align, 16, 16, 32, 32, -1);
15589 if (align_good == FAIL)
15591 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15594 case 2: inst.instruction |= 1 << 5; break;
15595 default: first_error (_("bad list length")); return;
15597 inst.instruction |= neon_logbits (et.size) << 6;
15600 case 1: /* VLD2. */
15601 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15602 &do_align, 8, 16, 16, 32, 32, 64, -1);
15603 if (align_good == FAIL)
15605 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15606 _("bad list length"));
15607 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15608 inst.instruction |= 1 << 5;
15609 inst.instruction |= neon_logbits (et.size) << 6;
15612 case 2: /* VLD3. */
15613 constraint (inst.operands[1].immisalign,
15614 _("can't use alignment with this instruction"));
15615 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15616 _("bad list length"));
15617 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15618 inst.instruction |= 1 << 5;
15619 inst.instruction |= neon_logbits (et.size) << 6;
15622 case 3: /* VLD4. */
15624 int align = inst.operands[1].imm >> 8;
15625 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15626 16, 64, 32, 64, 32, 128, -1);
15627 if (align_good == FAIL)
15629 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15630 _("bad list length"));
15631 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15632 inst.instruction |= 1 << 5;
15633 if (et.size == 32 && align == 128)
15634 inst.instruction |= 0x3 << 6;
15636 inst.instruction |= neon_logbits (et.size) << 6;
15643 inst.instruction |= do_align << 4;
15646 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15647 apart from bits [11:4]. */
15650 do_neon_ldx_stx (void)
15652 if (inst.operands[1].isreg)
15653 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15655 switch (NEON_LANE (inst.operands[0].imm))
15657 case NEON_INTERLEAVE_LANES:
15658 NEON_ENCODE (INTERLV, inst);
15659 do_neon_ld_st_interleave ();
15662 case NEON_ALL_LANES:
15663 NEON_ENCODE (DUP, inst);
15668 NEON_ENCODE (LANE, inst);
15669 do_neon_ld_st_lane ();
15672 /* L bit comes from bit mask. */
15673 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15674 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15675 inst.instruction |= inst.operands[1].reg << 16;
15677 if (inst.operands[1].postind)
15679 int postreg = inst.operands[1].imm & 0xf;
15680 constraint (!inst.operands[1].immisreg,
15681 _("post-index must be a register"));
15682 constraint (postreg == 0xd || postreg == 0xf,
15683 _("bad register for post-index"));
15684 inst.instruction |= postreg;
15686 else if (inst.operands[1].writeback)
15688 inst.instruction |= 0xd;
15691 inst.instruction |= 0xf;
15694 inst.instruction |= 0xf9000000;
15696 inst.instruction |= 0xf4000000;
15699 /* Overall per-instruction processing. */
15701 /* We need to be able to fix up arbitrary expressions in some statements.
15702 This is so that we can handle symbols that are an arbitrary distance from
15703 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15704 which returns part of an address in a form which will be valid for
15705 a data instruction. We do this by pushing the expression into a symbol
15706 in the expr_section, and creating a fix for that. */
15709 fix_new_arm (fragS * frag,
15723 /* Create an absolute valued symbol, so we have something to
15724 refer to in the object file. Unfortunately for us, gas's
15725 generic expression parsing will already have folded out
15726 any use of .set foo/.type foo %function that may have
15727 been used to set type information of the target location,
15728 that's being specified symbolically. We have to presume
15729 the user knows what they are doing. */
15733 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15735 symbol = symbol_find_or_make (name);
15736 S_SET_SEGMENT (symbol, absolute_section);
15737 symbol_set_frag (symbol, &zero_address_frag);
15738 S_SET_VALUE (symbol, exp->X_add_number);
15739 exp->X_op = O_symbol;
15740 exp->X_add_symbol = symbol;
15741 exp->X_add_number = 0;
15747 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15748 (enum bfd_reloc_code_real) reloc);
15752 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15753 pc_rel, (enum bfd_reloc_code_real) reloc);
15757 /* Mark whether the fix is to a THUMB instruction, or an ARM
15759 new_fix->tc_fix_data = thumb_mode;
15762 /* Create a frg for an instruction requiring relaxation. */
15764 output_relax_insn (void)
15770 /* The size of the instruction is unknown, so tie the debug info to the
15771 start of the instruction. */
15772 dwarf2_emit_insn (0);
15774 switch (inst.reloc.exp.X_op)
15777 sym = inst.reloc.exp.X_add_symbol;
15778 offset = inst.reloc.exp.X_add_number;
15782 offset = inst.reloc.exp.X_add_number;
15785 sym = make_expr_symbol (&inst.reloc.exp);
15789 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15790 inst.relax, sym, offset, NULL/*offset, opcode*/);
15791 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15794 /* Write a 32-bit thumb instruction to buf. */
15796 put_thumb32_insn (char * buf, unsigned long insn)
15798 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15799 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15803 output_inst (const char * str)
15809 as_bad ("%s -- `%s'", inst.error, str);
15814 output_relax_insn ();
15817 if (inst.size == 0)
15820 to = frag_more (inst.size);
15821 /* PR 9814: Record the thumb mode into the current frag so that we know
15822 what type of NOP padding to use, if necessary. We override any previous
15823 setting so that if the mode has changed then the NOPS that we use will
15824 match the encoding of the last instruction in the frag. */
15825 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15827 if (thumb_mode && (inst.size > THUMB_SIZE))
15829 gas_assert (inst.size == (2 * THUMB_SIZE));
15830 put_thumb32_insn (to, inst.instruction);
15832 else if (inst.size > INSN_SIZE)
15834 gas_assert (inst.size == (2 * INSN_SIZE));
15835 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15836 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15839 md_number_to_chars (to, inst.instruction, inst.size);
15841 if (inst.reloc.type != BFD_RELOC_UNUSED)
15842 fix_new_arm (frag_now, to - frag_now->fr_literal,
15843 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15846 dwarf2_emit_insn (inst.size);
15850 output_it_inst (int cond, int mask, char * to)
15852 unsigned long instruction = 0xbf00;
15855 instruction |= mask;
15856 instruction |= cond << 4;
15860 to = frag_more (2);
15862 dwarf2_emit_insn (2);
15866 md_number_to_chars (to, instruction, 2);
15871 /* Tag values used in struct asm_opcode's tag field. */
15874 OT_unconditional, /* Instruction cannot be conditionalized.
15875 The ARM condition field is still 0xE. */
15876 OT_unconditionalF, /* Instruction cannot be conditionalized
15877 and carries 0xF in its ARM condition field. */
15878 OT_csuffix, /* Instruction takes a conditional suffix. */
15879 OT_csuffixF, /* Some forms of the instruction take a conditional
15880 suffix, others place 0xF where the condition field
15882 OT_cinfix3, /* Instruction takes a conditional infix,
15883 beginning at character index 3. (In
15884 unified mode, it becomes a suffix.) */
15885 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15886 tsts, cmps, cmns, and teqs. */
15887 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15888 character index 3, even in unified mode. Used for
15889 legacy instructions where suffix and infix forms
15890 may be ambiguous. */
15891 OT_csuf_or_in3, /* Instruction takes either a conditional
15892 suffix or an infix at character index 3. */
15893 OT_odd_infix_unc, /* This is the unconditional variant of an
15894 instruction that takes a conditional infix
15895 at an unusual position. In unified mode,
15896 this variant will accept a suffix. */
15897 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15898 are the conditional variants of instructions that
15899 take conditional infixes in unusual positions.
15900 The infix appears at character index
15901 (tag - OT_odd_infix_0). These are not accepted
15902 in unified mode. */
15905 /* Subroutine of md_assemble, responsible for looking up the primary
15906 opcode from the mnemonic the user wrote. STR points to the
15907 beginning of the mnemonic.
15909 This is not simply a hash table lookup, because of conditional
15910 variants. Most instructions have conditional variants, which are
15911 expressed with a _conditional affix_ to the mnemonic. If we were
15912 to encode each conditional variant as a literal string in the opcode
15913 table, it would have approximately 20,000 entries.
15915 Most mnemonics take this affix as a suffix, and in unified syntax,
15916 'most' is upgraded to 'all'. However, in the divided syntax, some
15917 instructions take the affix as an infix, notably the s-variants of
15918 the arithmetic instructions. Of those instructions, all but six
15919 have the infix appear after the third character of the mnemonic.
15921 Accordingly, the algorithm for looking up primary opcodes given
15924 1. Look up the identifier in the opcode table.
15925 If we find a match, go to step U.
15927 2. Look up the last two characters of the identifier in the
15928 conditions table. If we find a match, look up the first N-2
15929 characters of the identifier in the opcode table. If we
15930 find a match, go to step CE.
15932 3. Look up the fourth and fifth characters of the identifier in
15933 the conditions table. If we find a match, extract those
15934 characters from the identifier, and look up the remaining
15935 characters in the opcode table. If we find a match, go
15940 U. Examine the tag field of the opcode structure, in case this is
15941 one of the six instructions with its conditional infix in an
15942 unusual place. If it is, the tag tells us where to find the
15943 infix; look it up in the conditions table and set inst.cond
15944 accordingly. Otherwise, this is an unconditional instruction.
15945 Again set inst.cond accordingly. Return the opcode structure.
15947 CE. Examine the tag field to make sure this is an instruction that
15948 should receive a conditional suffix. If it is not, fail.
15949 Otherwise, set inst.cond from the suffix we already looked up,
15950 and return the opcode structure.
15952 CM. Examine the tag field to make sure this is an instruction that
15953 should receive a conditional infix after the third character.
15954 If it is not, fail. Otherwise, undo the edits to the current
15955 line of input and proceed as for case CE. */
15957 static const struct asm_opcode *
15958 opcode_lookup (char **str)
15962 const struct asm_opcode *opcode;
15963 const struct asm_cond *cond;
15966 /* Scan up to the end of the mnemonic, which must end in white space,
15967 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15968 for (base = end = *str; *end != '\0'; end++)
15969 if (*end == ' ' || *end == '.')
15975 /* Handle a possible width suffix and/or Neon type suffix. */
15980 /* The .w and .n suffixes are only valid if the unified syntax is in
15982 if (unified_syntax && end[1] == 'w')
15984 else if (unified_syntax && end[1] == 'n')
15989 inst.vectype.elems = 0;
15991 *str = end + offset;
15993 if (end[offset] == '.')
15995 /* See if we have a Neon type suffix (possible in either unified or
15996 non-unified ARM syntax mode). */
15997 if (parse_neon_type (&inst.vectype, str) == FAIL)
16000 else if (end[offset] != '\0' && end[offset] != ' ')
16006 /* Look for unaffixed or special-case affixed mnemonic. */
16007 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16012 if (opcode->tag < OT_odd_infix_0)
16014 inst.cond = COND_ALWAYS;
16018 if (warn_on_deprecated && unified_syntax)
16019 as_warn (_("conditional infixes are deprecated in unified syntax"));
16020 affix = base + (opcode->tag - OT_odd_infix_0);
16021 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16024 inst.cond = cond->value;
16028 /* Cannot have a conditional suffix on a mnemonic of less than two
16030 if (end - base < 3)
16033 /* Look for suffixed mnemonic. */
16035 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16036 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16038 if (opcode && cond)
16041 switch (opcode->tag)
16043 case OT_cinfix3_legacy:
16044 /* Ignore conditional suffixes matched on infix only mnemonics. */
16048 case OT_cinfix3_deprecated:
16049 case OT_odd_infix_unc:
16050 if (!unified_syntax)
16052 /* else fall through */
16056 case OT_csuf_or_in3:
16057 inst.cond = cond->value;
16060 case OT_unconditional:
16061 case OT_unconditionalF:
16063 inst.cond = cond->value;
16066 /* Delayed diagnostic. */
16067 inst.error = BAD_COND;
16068 inst.cond = COND_ALWAYS;
16077 /* Cannot have a usual-position infix on a mnemonic of less than
16078 six characters (five would be a suffix). */
16079 if (end - base < 6)
16082 /* Look for infixed mnemonic in the usual position. */
16084 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16088 memcpy (save, affix, 2);
16089 memmove (affix, affix + 2, (end - affix) - 2);
16090 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16092 memmove (affix + 2, affix, (end - affix) - 2);
16093 memcpy (affix, save, 2);
16096 && (opcode->tag == OT_cinfix3
16097 || opcode->tag == OT_cinfix3_deprecated
16098 || opcode->tag == OT_csuf_or_in3
16099 || opcode->tag == OT_cinfix3_legacy))
16102 if (warn_on_deprecated && unified_syntax
16103 && (opcode->tag == OT_cinfix3
16104 || opcode->tag == OT_cinfix3_deprecated))
16105 as_warn (_("conditional infixes are deprecated in unified syntax"));
16107 inst.cond = cond->value;
16114 /* This function generates an initial IT instruction, leaving its block
16115 virtually open for the new instructions. Eventually,
16116 the mask will be updated by now_it_add_mask () each time
16117 a new instruction needs to be included in the IT block.
16118 Finally, the block is closed with close_automatic_it_block ().
16119 The block closure can be requested either from md_assemble (),
16120 a tencode (), or due to a label hook. */
16123 new_automatic_it_block (int cond)
16125 now_it.state = AUTOMATIC_IT_BLOCK;
16126 now_it.mask = 0x18;
16128 now_it.block_length = 1;
16129 mapping_state (MAP_THUMB);
16130 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16133 /* Close an automatic IT block.
16134 See comments in new_automatic_it_block (). */
16137 close_automatic_it_block (void)
16139 now_it.mask = 0x10;
16140 now_it.block_length = 0;
16143 /* Update the mask of the current automatically-generated IT
16144 instruction. See comments in new_automatic_it_block (). */
16147 now_it_add_mask (int cond)
16149 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16150 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16151 | ((bitvalue) << (nbit)))
16152 const int resulting_bit = (cond & 1);
16154 now_it.mask &= 0xf;
16155 now_it.mask = SET_BIT_VALUE (now_it.mask,
16157 (5 - now_it.block_length));
16158 now_it.mask = SET_BIT_VALUE (now_it.mask,
16160 ((5 - now_it.block_length) - 1) );
16161 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16164 #undef SET_BIT_VALUE
16167 /* The IT blocks handling machinery is accessed through the these functions:
16168 it_fsm_pre_encode () from md_assemble ()
16169 set_it_insn_type () optional, from the tencode functions
16170 set_it_insn_type_last () ditto
16171 in_it_block () ditto
16172 it_fsm_post_encode () from md_assemble ()
16173 force_automatic_it_block_close () from label habdling functions
16176 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16177 initializing the IT insn type with a generic initial value depending
16178 on the inst.condition.
16179 2) During the tencode function, two things may happen:
16180 a) The tencode function overrides the IT insn type by
16181 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16182 b) The tencode function queries the IT block state by
16183 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16185 Both set_it_insn_type and in_it_block run the internal FSM state
16186 handling function (handle_it_state), because: a) setting the IT insn
16187 type may incur in an invalid state (exiting the function),
16188 and b) querying the state requires the FSM to be updated.
16189 Specifically we want to avoid creating an IT block for conditional
16190 branches, so it_fsm_pre_encode is actually a guess and we can't
16191 determine whether an IT block is required until the tencode () routine
16192 has decided what type of instruction this actually it.
16193 Because of this, if set_it_insn_type and in_it_block have to be used,
16194 set_it_insn_type has to be called first.
16196 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16197 determines the insn IT type depending on the inst.cond code.
16198 When a tencode () routine encodes an instruction that can be
16199 either outside an IT block, or, in the case of being inside, has to be
16200 the last one, set_it_insn_type_last () will determine the proper
16201 IT instruction type based on the inst.cond code. Otherwise,
16202 set_it_insn_type can be called for overriding that logic or
16203 for covering other cases.
16205 Calling handle_it_state () may not transition the IT block state to
16206 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16207 still queried. Instead, if the FSM determines that the state should
16208 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16209 after the tencode () function: that's what it_fsm_post_encode () does.
16211 Since in_it_block () calls the state handling function to get an
16212 updated state, an error may occur (due to invalid insns combination).
16213 In that case, inst.error is set.
16214 Therefore, inst.error has to be checked after the execution of
16215 the tencode () routine.
16217 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16218 any pending state change (if any) that didn't take place in
16219 handle_it_state () as explained above. */
16222 it_fsm_pre_encode (void)
16224 if (inst.cond != COND_ALWAYS)
16225 inst.it_insn_type = INSIDE_IT_INSN;
16227 inst.it_insn_type = OUTSIDE_IT_INSN;
16229 now_it.state_handled = 0;
16232 /* IT state FSM handling function. */
16235 handle_it_state (void)
16237 now_it.state_handled = 1;
16239 switch (now_it.state)
16241 case OUTSIDE_IT_BLOCK:
16242 switch (inst.it_insn_type)
16244 case OUTSIDE_IT_INSN:
16247 case INSIDE_IT_INSN:
16248 case INSIDE_IT_LAST_INSN:
16249 if (thumb_mode == 0)
16252 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16253 as_tsktsk (_("Warning: conditional outside an IT block"\
16258 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16259 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16261 /* Automatically generate the IT instruction. */
16262 new_automatic_it_block (inst.cond);
16263 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16264 close_automatic_it_block ();
16268 inst.error = BAD_OUT_IT;
16274 case IF_INSIDE_IT_LAST_INSN:
16275 case NEUTRAL_IT_INSN:
16279 now_it.state = MANUAL_IT_BLOCK;
16280 now_it.block_length = 0;
16285 case AUTOMATIC_IT_BLOCK:
16286 /* Three things may happen now:
16287 a) We should increment current it block size;
16288 b) We should close current it block (closing insn or 4 insns);
16289 c) We should close current it block and start a new one (due
16290 to incompatible conditions or
16291 4 insns-length block reached). */
16293 switch (inst.it_insn_type)
16295 case OUTSIDE_IT_INSN:
16296 /* The closure of the block shall happen immediatelly,
16297 so any in_it_block () call reports the block as closed. */
16298 force_automatic_it_block_close ();
16301 case INSIDE_IT_INSN:
16302 case INSIDE_IT_LAST_INSN:
16303 case IF_INSIDE_IT_LAST_INSN:
16304 now_it.block_length++;
16306 if (now_it.block_length > 4
16307 || !now_it_compatible (inst.cond))
16309 force_automatic_it_block_close ();
16310 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16311 new_automatic_it_block (inst.cond);
16315 now_it_add_mask (inst.cond);
16318 if (now_it.state == AUTOMATIC_IT_BLOCK
16319 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16320 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16321 close_automatic_it_block ();
16324 case NEUTRAL_IT_INSN:
16325 now_it.block_length++;
16327 if (now_it.block_length > 4)
16328 force_automatic_it_block_close ();
16330 now_it_add_mask (now_it.cc & 1);
16334 close_automatic_it_block ();
16335 now_it.state = MANUAL_IT_BLOCK;
16340 case MANUAL_IT_BLOCK:
16342 /* Check conditional suffixes. */
16343 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16346 now_it.mask &= 0x1f;
16347 is_last = (now_it.mask == 0x10);
16349 switch (inst.it_insn_type)
16351 case OUTSIDE_IT_INSN:
16352 inst.error = BAD_NOT_IT;
16355 case INSIDE_IT_INSN:
16356 if (cond != inst.cond)
16358 inst.error = BAD_IT_COND;
16363 case INSIDE_IT_LAST_INSN:
16364 case IF_INSIDE_IT_LAST_INSN:
16365 if (cond != inst.cond)
16367 inst.error = BAD_IT_COND;
16372 inst.error = BAD_BRANCH;
16377 case NEUTRAL_IT_INSN:
16378 /* The BKPT instruction is unconditional even in an IT block. */
16382 inst.error = BAD_IT_IT;
16393 it_fsm_post_encode (void)
16397 if (!now_it.state_handled)
16398 handle_it_state ();
16400 is_last = (now_it.mask == 0x10);
16403 now_it.state = OUTSIDE_IT_BLOCK;
16409 force_automatic_it_block_close (void)
16411 if (now_it.state == AUTOMATIC_IT_BLOCK)
16413 close_automatic_it_block ();
16414 now_it.state = OUTSIDE_IT_BLOCK;
16422 if (!now_it.state_handled)
16423 handle_it_state ();
16425 return now_it.state != OUTSIDE_IT_BLOCK;
16429 md_assemble (char *str)
16432 const struct asm_opcode * opcode;
16434 /* Align the previous label if needed. */
16435 if (last_label_seen != NULL)
16437 symbol_set_frag (last_label_seen, frag_now);
16438 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16439 S_SET_SEGMENT (last_label_seen, now_seg);
16442 memset (&inst, '\0', sizeof (inst));
16443 inst.reloc.type = BFD_RELOC_UNUSED;
16445 opcode = opcode_lookup (&p);
16448 /* It wasn't an instruction, but it might be a register alias of
16449 the form alias .req reg, or a Neon .dn/.qn directive. */
16450 if (! create_register_alias (str, p)
16451 && ! create_neon_reg_alias (str, p))
16452 as_bad (_("bad instruction `%s'"), str);
16457 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16458 as_warn (_("s suffix on comparison instruction is deprecated"));
16460 /* The value which unconditional instructions should have in place of the
16461 condition field. */
16462 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16466 arm_feature_set variant;
16468 variant = cpu_variant;
16469 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16470 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16471 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16472 /* Check that this instruction is supported for this CPU. */
16473 if (!opcode->tvariant
16474 || (thumb_mode == 1
16475 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16477 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16480 if (inst.cond != COND_ALWAYS && !unified_syntax
16481 && opcode->tencode != do_t_branch)
16483 as_bad (_("Thumb does not support conditional execution"));
16487 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16489 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16490 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16491 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16493 /* Two things are addressed here.
16494 1) Implicit require narrow instructions on Thumb-1.
16495 This avoids relaxation accidentally introducing Thumb-2
16497 2) Reject wide instructions in non Thumb-2 cores. */
16498 if (inst.size_req == 0)
16500 else if (inst.size_req == 4)
16502 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16508 inst.instruction = opcode->tvalue;
16510 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16512 /* Prepare the it_insn_type for those encodings that don't set
16514 it_fsm_pre_encode ();
16516 opcode->tencode ();
16518 it_fsm_post_encode ();
16521 if (!(inst.error || inst.relax))
16523 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16524 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16525 if (inst.size_req && inst.size_req != inst.size)
16527 as_bad (_("cannot honor width suffix -- `%s'"), str);
16532 /* Something has gone badly wrong if we try to relax a fixed size
16534 gas_assert (inst.size_req == 0 || !inst.relax);
16536 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16537 *opcode->tvariant);
16538 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16539 set those bits when Thumb-2 32-bit instructions are seen. ie.
16540 anything other than bl/blx and v6-M instructions.
16541 This is overly pessimistic for relaxable instructions. */
16542 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16544 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16545 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16546 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16549 check_neon_suffixes;
16553 mapping_state (MAP_THUMB);
16556 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16560 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16561 is_bx = (opcode->aencode == do_bx);
16563 /* Check that this instruction is supported for this CPU. */
16564 if (!(is_bx && fix_v4bx)
16565 && !(opcode->avariant &&
16566 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16568 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16573 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16577 inst.instruction = opcode->avalue;
16578 if (opcode->tag == OT_unconditionalF)
16579 inst.instruction |= 0xF << 28;
16581 inst.instruction |= inst.cond << 28;
16582 inst.size = INSN_SIZE;
16583 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16585 it_fsm_pre_encode ();
16586 opcode->aencode ();
16587 it_fsm_post_encode ();
16589 /* Arm mode bx is marked as both v4T and v5 because it's still required
16590 on a hypothetical non-thumb v5 core. */
16592 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16594 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16595 *opcode->avariant);
16597 check_neon_suffixes;
16601 mapping_state (MAP_ARM);
16606 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16614 check_it_blocks_finished (void)
16619 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16620 if (seg_info (sect)->tc_segment_info_data.current_it.state
16621 == MANUAL_IT_BLOCK)
16623 as_warn (_("section '%s' finished with an open IT block."),
16627 if (now_it.state == MANUAL_IT_BLOCK)
16628 as_warn (_("file finished with an open IT block."));
16632 /* Various frobbings of labels and their addresses. */
16635 arm_start_line_hook (void)
16637 last_label_seen = NULL;
16641 arm_frob_label (symbolS * sym)
16643 last_label_seen = sym;
16645 ARM_SET_THUMB (sym, thumb_mode);
16647 #if defined OBJ_COFF || defined OBJ_ELF
16648 ARM_SET_INTERWORK (sym, support_interwork);
16651 force_automatic_it_block_close ();
16653 /* Note - do not allow local symbols (.Lxxx) to be labelled
16654 as Thumb functions. This is because these labels, whilst
16655 they exist inside Thumb code, are not the entry points for
16656 possible ARM->Thumb calls. Also, these labels can be used
16657 as part of a computed goto or switch statement. eg gcc
16658 can generate code that looks like this:
16660 ldr r2, [pc, .Laaa]
16670 The first instruction loads the address of the jump table.
16671 The second instruction converts a table index into a byte offset.
16672 The third instruction gets the jump address out of the table.
16673 The fourth instruction performs the jump.
16675 If the address stored at .Laaa is that of a symbol which has the
16676 Thumb_Func bit set, then the linker will arrange for this address
16677 to have the bottom bit set, which in turn would mean that the
16678 address computation performed by the third instruction would end
16679 up with the bottom bit set. Since the ARM is capable of unaligned
16680 word loads, the instruction would then load the incorrect address
16681 out of the jump table, and chaos would ensue. */
16682 if (label_is_thumb_function_name
16683 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16684 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16686 /* When the address of a Thumb function is taken the bottom
16687 bit of that address should be set. This will allow
16688 interworking between Arm and Thumb functions to work
16691 THUMB_SET_FUNC (sym, 1);
16693 label_is_thumb_function_name = FALSE;
16696 dwarf2_emit_label (sym);
16700 arm_data_in_code (void)
16702 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16704 *input_line_pointer = '/';
16705 input_line_pointer += 5;
16706 *input_line_pointer = 0;
16714 arm_canonicalize_symbol_name (char * name)
16718 if (thumb_mode && (len = strlen (name)) > 5
16719 && streq (name + len - 5, "/data"))
16720 *(name + len - 5) = 0;
16725 /* Table of all register names defined by default. The user can
16726 define additional names with .req. Note that all register names
16727 should appear in both upper and lowercase variants. Some registers
16728 also have mixed-case names. */
16730 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16731 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16732 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16733 #define REGSET(p,t) \
16734 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16735 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16736 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16737 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16738 #define REGSETH(p,t) \
16739 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16740 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16741 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16742 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16743 #define REGSET2(p,t) \
16744 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16745 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16746 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16747 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16748 #define SPLRBANK(base,bank,t) \
16749 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16750 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16751 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16752 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16753 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16754 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16756 static const struct reg_entry reg_names[] =
16758 /* ARM integer registers. */
16759 REGSET(r, RN), REGSET(R, RN),
16761 /* ATPCS synonyms. */
16762 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16763 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16764 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16766 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16767 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16768 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16770 /* Well-known aliases. */
16771 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16772 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16774 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16775 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16777 /* Coprocessor numbers. */
16778 REGSET(p, CP), REGSET(P, CP),
16780 /* Coprocessor register numbers. The "cr" variants are for backward
16782 REGSET(c, CN), REGSET(C, CN),
16783 REGSET(cr, CN), REGSET(CR, CN),
16785 /* ARM banked registers. */
16786 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16787 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16788 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16789 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16790 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16791 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16792 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16794 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16795 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16796 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16797 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16798 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16799 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16800 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16801 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16803 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16804 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16805 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16806 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16807 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16808 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16809 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16810 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16811 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16813 /* FPA registers. */
16814 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16815 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16817 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16818 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16820 /* VFP SP registers. */
16821 REGSET(s,VFS), REGSET(S,VFS),
16822 REGSETH(s,VFS), REGSETH(S,VFS),
16824 /* VFP DP Registers. */
16825 REGSET(d,VFD), REGSET(D,VFD),
16826 /* Extra Neon DP registers. */
16827 REGSETH(d,VFD), REGSETH(D,VFD),
16829 /* Neon QP registers. */
16830 REGSET2(q,NQ), REGSET2(Q,NQ),
16832 /* VFP control registers. */
16833 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16834 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16835 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16836 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16837 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16838 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16840 /* Maverick DSP coprocessor registers. */
16841 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16842 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16844 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16845 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16846 REGDEF(dspsc,0,DSPSC),
16848 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16849 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16850 REGDEF(DSPSC,0,DSPSC),
16852 /* iWMMXt data registers - p0, c0-15. */
16853 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16855 /* iWMMXt control registers - p1, c0-3. */
16856 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16857 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16858 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16859 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16861 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16862 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16863 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16864 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16865 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16867 /* XScale accumulator registers. */
16868 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16874 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16875 within psr_required_here. */
16876 static const struct asm_psr psrs[] =
16878 /* Backward compatibility notation. Note that "all" is no longer
16879 truly all possible PSR bits. */
16880 {"all", PSR_c | PSR_f},
16884 /* Individual flags. */
16890 /* Combinations of flags. */
16891 {"fs", PSR_f | PSR_s},
16892 {"fx", PSR_f | PSR_x},
16893 {"fc", PSR_f | PSR_c},
16894 {"sf", PSR_s | PSR_f},
16895 {"sx", PSR_s | PSR_x},
16896 {"sc", PSR_s | PSR_c},
16897 {"xf", PSR_x | PSR_f},
16898 {"xs", PSR_x | PSR_s},
16899 {"xc", PSR_x | PSR_c},
16900 {"cf", PSR_c | PSR_f},
16901 {"cs", PSR_c | PSR_s},
16902 {"cx", PSR_c | PSR_x},
16903 {"fsx", PSR_f | PSR_s | PSR_x},
16904 {"fsc", PSR_f | PSR_s | PSR_c},
16905 {"fxs", PSR_f | PSR_x | PSR_s},
16906 {"fxc", PSR_f | PSR_x | PSR_c},
16907 {"fcs", PSR_f | PSR_c | PSR_s},
16908 {"fcx", PSR_f | PSR_c | PSR_x},
16909 {"sfx", PSR_s | PSR_f | PSR_x},
16910 {"sfc", PSR_s | PSR_f | PSR_c},
16911 {"sxf", PSR_s | PSR_x | PSR_f},
16912 {"sxc", PSR_s | PSR_x | PSR_c},
16913 {"scf", PSR_s | PSR_c | PSR_f},
16914 {"scx", PSR_s | PSR_c | PSR_x},
16915 {"xfs", PSR_x | PSR_f | PSR_s},
16916 {"xfc", PSR_x | PSR_f | PSR_c},
16917 {"xsf", PSR_x | PSR_s | PSR_f},
16918 {"xsc", PSR_x | PSR_s | PSR_c},
16919 {"xcf", PSR_x | PSR_c | PSR_f},
16920 {"xcs", PSR_x | PSR_c | PSR_s},
16921 {"cfs", PSR_c | PSR_f | PSR_s},
16922 {"cfx", PSR_c | PSR_f | PSR_x},
16923 {"csf", PSR_c | PSR_s | PSR_f},
16924 {"csx", PSR_c | PSR_s | PSR_x},
16925 {"cxf", PSR_c | PSR_x | PSR_f},
16926 {"cxs", PSR_c | PSR_x | PSR_s},
16927 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16928 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16929 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16930 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16931 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16932 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16933 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16934 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16935 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16936 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16937 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16938 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16939 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16940 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16941 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16942 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16943 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16944 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16945 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16946 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16947 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16948 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16949 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16950 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16953 /* Table of V7M psr names. */
16954 static const struct asm_psr v7m_psrs[] =
16956 {"apsr", 0 }, {"APSR", 0 },
16957 {"iapsr", 1 }, {"IAPSR", 1 },
16958 {"eapsr", 2 }, {"EAPSR", 2 },
16959 {"psr", 3 }, {"PSR", 3 },
16960 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16961 {"ipsr", 5 }, {"IPSR", 5 },
16962 {"epsr", 6 }, {"EPSR", 6 },
16963 {"iepsr", 7 }, {"IEPSR", 7 },
16964 {"msp", 8 }, {"MSP", 8 },
16965 {"psp", 9 }, {"PSP", 9 },
16966 {"primask", 16}, {"PRIMASK", 16},
16967 {"basepri", 17}, {"BASEPRI", 17},
16968 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16969 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16970 {"faultmask", 19}, {"FAULTMASK", 19},
16971 {"control", 20}, {"CONTROL", 20}
16974 /* Table of all shift-in-operand names. */
16975 static const struct asm_shift_name shift_names [] =
16977 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16978 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16979 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16980 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16981 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16982 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16985 /* Table of all explicit relocation names. */
16987 static struct reloc_entry reloc_names[] =
16989 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16990 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16991 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16992 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16993 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16994 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16995 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16996 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16997 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16998 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16999 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17000 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17001 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17002 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17003 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17004 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17005 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17006 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17010 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17011 static const struct asm_cond conds[] =
17015 {"cs", 0x2}, {"hs", 0x2},
17016 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17030 static struct asm_barrier_opt barrier_opt_names[] =
17032 { "sy", 0xf }, { "SY", 0xf },
17033 { "un", 0x7 }, { "UN", 0x7 },
17034 { "st", 0xe }, { "ST", 0xe },
17035 { "unst", 0x6 }, { "UNST", 0x6 },
17036 { "ish", 0xb }, { "ISH", 0xb },
17037 { "sh", 0xb }, { "SH", 0xb },
17038 { "ishst", 0xa }, { "ISHST", 0xa },
17039 { "shst", 0xa }, { "SHST", 0xa },
17040 { "nsh", 0x7 }, { "NSH", 0x7 },
17041 { "nshst", 0x6 }, { "NSHST", 0x6 },
17042 { "osh", 0x3 }, { "OSH", 0x3 },
17043 { "oshst", 0x2 }, { "OSHST", 0x2 }
17046 /* Table of ARM-format instructions. */
17048 /* Macros for gluing together operand strings. N.B. In all cases
17049 other than OPS0, the trailing OP_stop comes from default
17050 zero-initialization of the unspecified elements of the array. */
17051 #define OPS0() { OP_stop, }
17052 #define OPS1(a) { OP_##a, }
17053 #define OPS2(a,b) { OP_##a,OP_##b, }
17054 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17055 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17056 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17057 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17059 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17060 This is useful when mixing operands for ARM and THUMB, i.e. using the
17061 MIX_ARM_THUMB_OPERANDS macro.
17062 In order to use these macros, prefix the number of operands with _
17064 #define OPS_1(a) { a, }
17065 #define OPS_2(a,b) { a,b, }
17066 #define OPS_3(a,b,c) { a,b,c, }
17067 #define OPS_4(a,b,c,d) { a,b,c,d, }
17068 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17069 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17071 /* These macros abstract out the exact format of the mnemonic table and
17072 save some repeated characters. */
17074 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17075 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17076 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17077 THUMB_VARIANT, do_##ae, do_##te }
17079 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17080 a T_MNEM_xyz enumerator. */
17081 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17082 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17083 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17084 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17086 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17087 infix after the third character. */
17088 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17089 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17090 THUMB_VARIANT, do_##ae, do_##te }
17091 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17092 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17093 THUMB_VARIANT, do_##ae, do_##te }
17094 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17095 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17096 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17097 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17098 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17099 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17100 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17101 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17103 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17104 appear in the condition table. */
17105 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17106 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17107 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17109 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17110 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17111 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17112 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17113 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17114 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17115 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17116 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17117 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17118 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17119 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17120 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17121 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17122 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17123 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17124 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17125 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17126 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17127 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17128 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17130 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17131 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17132 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17133 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17135 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17136 field is still 0xE. Many of the Thumb variants can be executed
17137 conditionally, so this is checked separately. */
17138 #define TUE(mnem, op, top, nops, ops, ae, te) \
17139 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17140 THUMB_VARIANT, do_##ae, do_##te }
17142 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17143 condition code field. */
17144 #define TUF(mnem, op, top, nops, ops, ae, te) \
17145 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17146 THUMB_VARIANT, do_##ae, do_##te }
17148 /* ARM-only variants of all the above. */
17149 #define CE(mnem, op, nops, ops, ae) \
17150 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17152 #define C3(mnem, op, nops, ops, ae) \
17153 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17155 /* Legacy mnemonics that always have conditional infix after the third
17157 #define CL(mnem, op, nops, ops, ae) \
17158 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17159 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17161 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17162 #define cCE(mnem, op, nops, ops, ae) \
17163 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17165 /* Legacy coprocessor instructions where conditional infix and conditional
17166 suffix are ambiguous. For consistency this includes all FPA instructions,
17167 not just the potentially ambiguous ones. */
17168 #define cCL(mnem, op, nops, ops, ae) \
17169 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17170 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17172 /* Coprocessor, takes either a suffix or a position-3 infix
17173 (for an FPA corner case). */
17174 #define C3E(mnem, op, nops, ops, ae) \
17175 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17176 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17178 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17179 { m1 #m2 m3, OPS##nops ops, \
17180 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17181 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17183 #define CM(m1, m2, op, nops, ops, ae) \
17184 xCM_ (m1, , m2, op, nops, ops, ae), \
17185 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17186 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17187 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17188 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17189 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17190 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17191 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17192 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17193 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17194 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17195 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17196 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17197 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17198 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17199 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17200 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17201 xCM_ (m1, le, m2, op, nops, ops, ae), \
17202 xCM_ (m1, al, m2, op, nops, ops, ae)
17204 #define UE(mnem, op, nops, ops, ae) \
17205 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17207 #define UF(mnem, op, nops, ops, ae) \
17208 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17210 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17211 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17212 use the same encoding function for each. */
17213 #define NUF(mnem, op, nops, ops, enc) \
17214 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17215 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17217 /* Neon data processing, version which indirects through neon_enc_tab for
17218 the various overloaded versions of opcodes. */
17219 #define nUF(mnem, op, nops, ops, enc) \
17220 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17221 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17223 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17225 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17226 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17227 THUMB_VARIANT, do_##enc, do_##enc }
17229 #define NCE(mnem, op, nops, ops, enc) \
17230 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17232 #define NCEF(mnem, op, nops, ops, enc) \
17233 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17235 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17236 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17237 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17238 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17240 #define nCE(mnem, op, nops, ops, enc) \
17241 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17243 #define nCEF(mnem, op, nops, ops, enc) \
17244 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17248 static const struct asm_opcode insns[] =
17250 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17251 #define THUMB_VARIANT &arm_ext_v4t
17252 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17253 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17254 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17255 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17256 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17257 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17258 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17259 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17260 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17261 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17262 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17263 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17264 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17265 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17266 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17267 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17269 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17270 for setting PSR flag bits. They are obsolete in V6 and do not
17271 have Thumb equivalents. */
17272 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17273 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17274 CL("tstp", 110f000, 2, (RR, SH), cmp),
17275 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17276 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17277 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17278 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17279 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17280 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17282 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17283 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17284 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17285 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17287 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17288 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17289 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17291 OP_ADDRGLDR),ldst, t_ldst),
17292 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17294 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17295 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17296 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17297 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17298 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17299 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17301 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17302 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17303 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17304 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17307 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17308 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17309 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17311 /* Thumb-compatibility pseudo ops. */
17312 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17313 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17314 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17315 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17316 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17317 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17318 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17319 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17320 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17321 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17322 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17323 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17325 /* These may simplify to neg. */
17326 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17327 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17329 #undef THUMB_VARIANT
17330 #define THUMB_VARIANT & arm_ext_v6
17332 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17334 /* V1 instructions with no Thumb analogue prior to V6T2. */
17335 #undef THUMB_VARIANT
17336 #define THUMB_VARIANT & arm_ext_v6t2
17338 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17339 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17340 CL("teqp", 130f000, 2, (RR, SH), cmp),
17342 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17343 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17344 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17345 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17347 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17348 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17350 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17351 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17353 /* V1 instructions with no Thumb analogue at all. */
17354 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17355 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17357 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17358 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17359 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17360 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17361 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17362 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17363 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17364 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17367 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17368 #undef THUMB_VARIANT
17369 #define THUMB_VARIANT & arm_ext_v4t
17371 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17372 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17374 #undef THUMB_VARIANT
17375 #define THUMB_VARIANT & arm_ext_v6t2
17377 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17378 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17380 /* Generic coprocessor instructions. */
17381 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17382 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17383 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17384 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17385 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17386 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17387 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17390 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17392 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17393 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17396 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17397 #undef THUMB_VARIANT
17398 #define THUMB_VARIANT & arm_ext_msr
17400 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17401 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17404 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17405 #undef THUMB_VARIANT
17406 #define THUMB_VARIANT & arm_ext_v6t2
17408 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17409 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17410 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17411 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17412 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17413 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17414 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17415 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17418 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17419 #undef THUMB_VARIANT
17420 #define THUMB_VARIANT & arm_ext_v4t
17422 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17423 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17424 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17425 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17426 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17427 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17430 #define ARM_VARIANT & arm_ext_v4t_5
17432 /* ARM Architecture 4T. */
17433 /* Note: bx (and blx) are required on V5, even if the processor does
17434 not support Thumb. */
17435 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17438 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17439 #undef THUMB_VARIANT
17440 #define THUMB_VARIANT & arm_ext_v5t
17442 /* Note: blx has 2 variants; the .value coded here is for
17443 BLX(2). Only this variant has conditional execution. */
17444 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17445 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17447 #undef THUMB_VARIANT
17448 #define THUMB_VARIANT & arm_ext_v6t2
17450 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17451 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17452 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17453 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17454 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17455 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17456 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17457 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17460 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17461 #undef THUMB_VARIANT
17462 #define THUMB_VARIANT &arm_ext_v5exp
17464 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17465 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17466 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17467 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17469 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17470 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17472 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17473 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17474 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17475 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17477 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17478 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17479 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17480 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17482 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17483 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17485 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17486 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17487 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17488 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17491 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17492 #undef THUMB_VARIANT
17493 #define THUMB_VARIANT &arm_ext_v6t2
17495 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17496 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17498 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17499 ADDRGLDRS), ldrd, t_ldstd),
17501 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17502 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17505 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17507 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17510 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17511 #undef THUMB_VARIANT
17512 #define THUMB_VARIANT & arm_ext_v6
17514 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17515 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17516 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17517 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17518 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17519 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17520 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17521 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17522 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17523 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17525 #undef THUMB_VARIANT
17526 #define THUMB_VARIANT & arm_ext_v6t2
17528 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17529 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17531 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17532 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17534 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17535 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17537 /* ARM V6 not included in V7M. */
17538 #undef THUMB_VARIANT
17539 #define THUMB_VARIANT & arm_ext_v6_notm
17540 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17541 UF(rfeib, 9900a00, 1, (RRw), rfe),
17542 UF(rfeda, 8100a00, 1, (RRw), rfe),
17543 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17544 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17545 UF(rfefa, 9900a00, 1, (RRw), rfe),
17546 UF(rfeea, 8100a00, 1, (RRw), rfe),
17547 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17548 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17549 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17550 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17551 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17553 /* ARM V6 not included in V7M (eg. integer SIMD). */
17554 #undef THUMB_VARIANT
17555 #define THUMB_VARIANT & arm_ext_v6_dsp
17556 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17557 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17558 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17559 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17560 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17561 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17562 /* Old name for QASX. */
17563 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17564 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17565 /* Old name for QSAX. */
17566 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17567 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17568 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17569 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17570 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17571 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17572 /* Old name for SASX. */
17573 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17574 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17575 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17576 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17577 /* Old name for SHASX. */
17578 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17579 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17580 /* Old name for SHSAX. */
17581 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17582 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17583 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17584 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17585 /* Old name for SSAX. */
17586 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17587 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17588 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17589 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17590 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17591 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17592 /* Old name for UASX. */
17593 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17594 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17595 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17596 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17597 /* Old name for UHASX. */
17598 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17599 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17600 /* Old name for UHSAX. */
17601 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17602 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17603 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17604 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17605 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17606 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17607 /* Old name for UQASX. */
17608 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17609 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17610 /* Old name for UQSAX. */
17611 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17612 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17613 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17614 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17615 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17616 /* Old name for USAX. */
17617 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17618 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17619 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17620 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17621 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17622 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17623 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17624 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17625 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17626 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17627 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17628 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17629 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17630 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17631 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17632 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17633 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17634 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17635 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17636 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17637 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17638 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17639 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17640 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17641 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17642 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17643 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17644 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17645 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17646 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17647 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17648 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17649 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17650 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17653 #define ARM_VARIANT & arm_ext_v6k
17654 #undef THUMB_VARIANT
17655 #define THUMB_VARIANT & arm_ext_v6k
17657 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17658 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17659 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17660 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17662 #undef THUMB_VARIANT
17663 #define THUMB_VARIANT & arm_ext_v6_notm
17664 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17666 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17667 RRnpcb), strexd, t_strexd),
17669 #undef THUMB_VARIANT
17670 #define THUMB_VARIANT & arm_ext_v6t2
17671 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17673 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17675 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17677 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17679 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17682 #define ARM_VARIANT & arm_ext_sec
17683 #undef THUMB_VARIANT
17684 #define THUMB_VARIANT & arm_ext_sec
17686 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17689 #define ARM_VARIANT & arm_ext_virt
17690 #undef THUMB_VARIANT
17691 #define THUMB_VARIANT & arm_ext_virt
17693 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17694 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17697 #define ARM_VARIANT & arm_ext_v6t2
17698 #undef THUMB_VARIANT
17699 #define THUMB_VARIANT & arm_ext_v6t2
17701 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17702 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17703 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17704 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17706 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17707 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17708 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17709 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17711 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17712 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17713 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17714 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17716 /* Thumb-only instructions. */
17718 #define ARM_VARIANT NULL
17719 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17720 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17722 /* ARM does not really have an IT instruction, so always allow it.
17723 The opcode is copied from Thumb in order to allow warnings in
17724 -mimplicit-it=[never | arm] modes. */
17726 #define ARM_VARIANT & arm_ext_v1
17728 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17729 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17730 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17731 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17732 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17733 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17734 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17735 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17736 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17737 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17738 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17739 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17740 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17741 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17742 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17743 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17744 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17745 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17747 /* Thumb2 only instructions. */
17749 #define ARM_VARIANT NULL
17751 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17752 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17753 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17754 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17755 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17756 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17758 /* Hardware division instructions. */
17760 #define ARM_VARIANT & arm_ext_adiv
17761 #undef THUMB_VARIANT
17762 #define THUMB_VARIANT & arm_ext_div
17764 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17765 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17767 /* ARM V6M/V7 instructions. */
17769 #define ARM_VARIANT & arm_ext_barrier
17770 #undef THUMB_VARIANT
17771 #define THUMB_VARIANT & arm_ext_barrier
17773 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17774 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17775 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17777 /* ARM V7 instructions. */
17779 #define ARM_VARIANT & arm_ext_v7
17780 #undef THUMB_VARIANT
17781 #define THUMB_VARIANT & arm_ext_v7
17783 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17784 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17787 #define ARM_VARIANT & arm_ext_mp
17788 #undef THUMB_VARIANT
17789 #define THUMB_VARIANT & arm_ext_mp
17791 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17794 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17796 cCE("wfs", e200110, 1, (RR), rd),
17797 cCE("rfs", e300110, 1, (RR), rd),
17798 cCE("wfc", e400110, 1, (RR), rd),
17799 cCE("rfc", e500110, 1, (RR), rd),
17801 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17802 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17803 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17804 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17806 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17807 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17808 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17809 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17811 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17812 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17813 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17814 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17815 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17816 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17817 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17818 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17819 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17820 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17821 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17822 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17824 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17825 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17826 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17827 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17828 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17829 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17830 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17831 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17832 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17833 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17834 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17835 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17837 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17838 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17839 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17840 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17841 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17842 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17843 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17844 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17845 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17846 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17847 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17848 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17850 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17851 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17852 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17853 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17854 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17855 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17856 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17857 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17858 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17859 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17860 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17861 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17863 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17864 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17865 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17866 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17867 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17868 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17869 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17870 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17871 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17872 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17873 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17874 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17876 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17877 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17878 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17879 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17880 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17881 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17882 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17883 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17884 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17885 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17886 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17887 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17889 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17890 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17891 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17892 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17893 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17894 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17895 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17896 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17897 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17898 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17899 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17900 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17902 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17903 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17904 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17905 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17906 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17907 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17908 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17909 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17910 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17911 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17912 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17913 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17915 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17916 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17917 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17918 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17919 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17920 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17921 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17922 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17923 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17924 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17925 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17926 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17928 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17929 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17930 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17931 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17932 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17933 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17934 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17935 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17936 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17937 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17938 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17939 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17941 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17942 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17943 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17944 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17945 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17946 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17947 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17948 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17949 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17950 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17951 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17952 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17954 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17955 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17956 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17957 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17958 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17959 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17960 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17961 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17962 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17963 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17964 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17965 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17967 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17968 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17969 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17970 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17971 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17972 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17973 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17974 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17975 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17976 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17977 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17978 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17980 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17981 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17982 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17983 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17984 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17985 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17986 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17987 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17988 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17989 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17990 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17991 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17993 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17994 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17995 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17996 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17997 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17998 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17999 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18000 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18001 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18002 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18003 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18004 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18006 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18007 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18008 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18009 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18010 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18011 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18012 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18013 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18014 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18015 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18016 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18017 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18019 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18065 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18067 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18069 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18077 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18078 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18079 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18080 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18082 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18090 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18091 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18092 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18093 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18094 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18095 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18097 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18098 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18099 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18100 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18101 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18102 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18103 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18104 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18105 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18106 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18107 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18108 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18110 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18111 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18112 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18113 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18114 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18115 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18116 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18117 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18118 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18119 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18120 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18121 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18123 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18124 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18125 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18126 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18127 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18128 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18129 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18130 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18131 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18132 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18133 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18134 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18136 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18137 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18138 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18139 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18140 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18141 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18142 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18143 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18144 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18145 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18146 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18147 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18149 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18150 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18151 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18152 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18153 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18154 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18155 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18156 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18157 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18158 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18159 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18160 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18162 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18163 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18164 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18165 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18166 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18167 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18168 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18169 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18170 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18171 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18172 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18173 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18175 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18176 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18177 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18178 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18179 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18180 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18181 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18182 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18183 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18184 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18185 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18186 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18188 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18189 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18190 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18191 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18193 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18194 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18195 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18196 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18197 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18198 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18199 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18200 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18201 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18202 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18203 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18204 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18206 /* The implementation of the FIX instruction is broken on some
18207 assemblers, in that it accepts a precision specifier as well as a
18208 rounding specifier, despite the fact that this is meaningless.
18209 To be more compatible, we accept it as well, though of course it
18210 does not set any bits. */
18211 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18212 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18213 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18214 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18215 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18216 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18217 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18218 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18219 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18220 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18221 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18222 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18223 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18225 /* Instructions that were new with the real FPA, call them V2. */
18227 #define ARM_VARIANT & fpu_fpa_ext_v2
18229 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18230 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18231 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18232 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18233 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18234 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18237 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18239 /* Moves and type conversions. */
18240 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18241 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18242 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18243 cCE("fmstat", ef1fa10, 0, (), noargs),
18244 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18245 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18246 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18247 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18248 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18249 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18250 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18251 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18252 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18253 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18255 /* Memory operations. */
18256 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18257 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18258 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18259 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18260 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18261 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18262 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18263 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18264 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18265 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18266 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18267 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18268 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18269 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18270 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18271 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18272 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18273 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18275 /* Monadic operations. */
18276 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18277 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18278 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18280 /* Dyadic operations. */
18281 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18282 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18283 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18284 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18285 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18286 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18287 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18288 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18289 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18292 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18293 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18294 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18295 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18297 /* Double precision load/store are still present on single precision
18298 implementations. */
18299 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18300 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18301 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18302 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18303 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18304 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18305 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18306 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18307 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18308 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18311 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18313 /* Moves and type conversions. */
18314 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18315 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18316 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18317 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18318 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18319 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18320 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18321 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18322 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18323 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18324 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18325 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18326 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18328 /* Monadic operations. */
18329 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18330 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18331 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18333 /* Dyadic operations. */
18334 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18335 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18336 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18337 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18338 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18339 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18340 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18341 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18342 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18345 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18346 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18347 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18348 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18351 #define ARM_VARIANT & fpu_vfp_ext_v2
18353 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18354 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18355 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18356 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18358 /* Instructions which may belong to either the Neon or VFP instruction sets.
18359 Individual encoder functions perform additional architecture checks. */
18361 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18362 #undef THUMB_VARIANT
18363 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18365 /* These mnemonics are unique to VFP. */
18366 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18367 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18368 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18369 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18370 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18371 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18372 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18373 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18374 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18375 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18377 /* Mnemonics shared by Neon and VFP. */
18378 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18379 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18380 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18382 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18383 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18385 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18386 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18388 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18389 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18390 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18391 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18392 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18393 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18394 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18395 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18397 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18398 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18399 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18400 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18403 /* NOTE: All VMOV encoding is special-cased! */
18404 NCE(vmov, 0, 1, (VMOV), neon_mov),
18405 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18407 #undef THUMB_VARIANT
18408 #define THUMB_VARIANT & fpu_neon_ext_v1
18410 #define ARM_VARIANT & fpu_neon_ext_v1
18412 /* Data processing with three registers of the same length. */
18413 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18414 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18415 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18416 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18417 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18418 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18419 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18420 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18421 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18422 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18423 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18424 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18425 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18426 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18427 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18428 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18429 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18430 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18431 /* If not immediate, fall back to neon_dyadic_i64_su.
18432 shl_imm should accept I8 I16 I32 I64,
18433 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18434 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18435 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18436 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18437 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18438 /* Logic ops, types optional & ignored. */
18439 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18440 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18441 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18442 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18443 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18444 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18445 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18446 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18447 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18448 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18449 /* Bitfield ops, untyped. */
18450 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18451 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18452 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18453 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18454 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18455 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18456 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18457 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18458 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18459 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18460 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18461 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18462 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18463 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18464 back to neon_dyadic_if_su. */
18465 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18466 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18467 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18468 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18469 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18470 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18471 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18472 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18473 /* Comparison. Type I8 I16 I32 F32. */
18474 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18475 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18476 /* As above, D registers only. */
18477 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18478 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18479 /* Int and float variants, signedness unimportant. */
18480 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18481 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18482 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18483 /* Add/sub take types I8 I16 I32 I64 F32. */
18484 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18485 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18486 /* vtst takes sizes 8, 16, 32. */
18487 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18488 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18489 /* VMUL takes I8 I16 I32 F32 P8. */
18490 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18491 /* VQD{R}MULH takes S16 S32. */
18492 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18493 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18494 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18495 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18496 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18497 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18498 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18499 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18500 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18501 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18502 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18503 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18504 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18505 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18506 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18507 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18509 /* Two address, int/float. Types S8 S16 S32 F32. */
18510 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18511 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18513 /* Data processing with two registers and a shift amount. */
18514 /* Right shifts, and variants with rounding.
18515 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18516 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18517 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18518 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18519 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18520 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18521 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18522 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18523 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18524 /* Shift and insert. Sizes accepted 8 16 32 64. */
18525 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18526 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18527 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18528 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18529 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18530 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18531 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18532 /* Right shift immediate, saturating & narrowing, with rounding variants.
18533 Types accepted S16 S32 S64 U16 U32 U64. */
18534 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18535 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18536 /* As above, unsigned. Types accepted S16 S32 S64. */
18537 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18538 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18539 /* Right shift narrowing. Types accepted I16 I32 I64. */
18540 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18541 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18542 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18543 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18544 /* CVT with optional immediate for fixed-point variant. */
18545 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18547 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18548 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18550 /* Data processing, three registers of different lengths. */
18551 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18552 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18553 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18554 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18555 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18556 /* If not scalar, fall back to neon_dyadic_long.
18557 Vector types as above, scalar types S16 S32 U16 U32. */
18558 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18559 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18560 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18561 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18562 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18563 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18564 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18565 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18566 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18567 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18568 /* Saturating doubling multiplies. Types S16 S32. */
18569 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18570 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18571 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18572 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18573 S16 S32 U16 U32. */
18574 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18576 /* Extract. Size 8. */
18577 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18578 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18580 /* Two registers, miscellaneous. */
18581 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18582 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18583 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18584 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18585 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18586 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18587 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18588 /* Vector replicate. Sizes 8 16 32. */
18589 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18590 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18591 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18592 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18593 /* VMOVN. Types I16 I32 I64. */
18594 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18595 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18596 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18597 /* VQMOVUN. Types S16 S32 S64. */
18598 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18599 /* VZIP / VUZP. Sizes 8 16 32. */
18600 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18601 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18602 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18603 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18604 /* VQABS / VQNEG. Types S8 S16 S32. */
18605 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18606 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18607 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18608 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18609 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18610 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18611 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18612 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18613 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18614 /* Reciprocal estimates. Types U32 F32. */
18615 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18616 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18617 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18618 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18619 /* VCLS. Types S8 S16 S32. */
18620 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18621 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18622 /* VCLZ. Types I8 I16 I32. */
18623 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18624 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18625 /* VCNT. Size 8. */
18626 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18627 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18628 /* Two address, untyped. */
18629 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18630 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18631 /* VTRN. Sizes 8 16 32. */
18632 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18633 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18635 /* Table lookup. Size 8. */
18636 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18637 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18639 #undef THUMB_VARIANT
18640 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18642 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18644 /* Neon element/structure load/store. */
18645 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18646 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18647 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18648 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18649 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18650 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18651 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18652 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18654 #undef THUMB_VARIANT
18655 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18657 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18658 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18659 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18660 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18661 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18662 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18663 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18664 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18665 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18666 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18668 #undef THUMB_VARIANT
18669 #define THUMB_VARIANT & fpu_vfp_ext_v3
18671 #define ARM_VARIANT & fpu_vfp_ext_v3
18673 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18674 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18675 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18676 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18677 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18678 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18679 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18680 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18681 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18684 #define ARM_VARIANT &fpu_vfp_ext_fma
18685 #undef THUMB_VARIANT
18686 #define THUMB_VARIANT &fpu_vfp_ext_fma
18687 /* Mnemonics shared by Neon and VFP. These are included in the
18688 VFP FMA variant; NEON and VFP FMA always includes the NEON
18689 FMA instructions. */
18690 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18691 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18692 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18693 the v form should always be used. */
18694 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18695 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18696 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18697 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18698 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18699 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18701 #undef THUMB_VARIANT
18703 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18705 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18706 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18707 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18708 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18709 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18710 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18711 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18712 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18715 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18717 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18718 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18719 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18720 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18721 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18722 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18723 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18724 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18725 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18726 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18727 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18728 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18729 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18730 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18731 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18732 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18733 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18734 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18735 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18736 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18737 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18738 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18739 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18740 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18741 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18742 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18743 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18744 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18745 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18746 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18747 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18748 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18749 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18750 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18751 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18752 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18753 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18754 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18755 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18759 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18760 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18764 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18775 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18779 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18784 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18785 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18786 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18787 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18788 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18789 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18790 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18791 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18792 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18793 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18794 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18806 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18809 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18810 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18818 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18819 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18820 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18821 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18822 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18823 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18828 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18829 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18830 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18831 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18832 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18833 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18834 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18835 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18836 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18837 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18838 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18839 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18840 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18841 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18842 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18843 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18844 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18845 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18846 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18847 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18848 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18849 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18850 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18851 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18852 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18853 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18854 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18855 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18856 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18857 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18858 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18859 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18860 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18861 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18862 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18863 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18864 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18865 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18866 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18867 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18868 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18869 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18870 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18871 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18872 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18873 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18874 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18875 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18876 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18877 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18878 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18881 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18883 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18884 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18885 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18886 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18887 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18888 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18889 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18890 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18891 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18892 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18893 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18894 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18895 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18896 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18897 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18898 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18899 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18900 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18901 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18902 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18903 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18904 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18905 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18906 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18907 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18908 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18909 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18910 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18911 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18912 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18913 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18914 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18915 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18916 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18917 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18918 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18919 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18920 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18921 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18922 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18923 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18924 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18925 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18926 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18927 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18928 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18929 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18930 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18931 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18932 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18933 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18934 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18935 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18936 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18937 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18938 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18939 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18942 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18944 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18945 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18946 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18947 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18948 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18949 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18950 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18951 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18952 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18953 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18954 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18955 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18956 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18957 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18958 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18959 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18960 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18961 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18962 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18963 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18964 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18965 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18966 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18967 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18968 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18969 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18970 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18971 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18972 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18973 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18974 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18975 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18976 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18977 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18978 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18979 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18980 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18981 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18982 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18983 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18984 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18985 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18986 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18987 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18988 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18989 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18990 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18991 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18992 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18993 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18994 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18995 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18996 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18997 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18998 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18999 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19000 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19001 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19002 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19003 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19004 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19005 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19006 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19007 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19008 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19009 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19010 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19011 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19012 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19013 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19014 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19015 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19016 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19017 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19018 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19019 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19022 #undef THUMB_VARIANT
19049 /* MD interface: bits in the object file. */
19051 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19052 for use in the a.out file, and stores them in the array pointed to by buf.
19053 This knows about the endian-ness of the target machine and does
19054 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19055 2 (short) and 4 (long) Floating numbers are put out as a series of
19056 LITTLENUMS (shorts, here at least). */
19059 md_number_to_chars (char * buf, valueT val, int n)
19061 if (target_big_endian)
19062 number_to_chars_bigendian (buf, val, n);
19064 number_to_chars_littleendian (buf, val, n);
19068 md_chars_to_number (char * buf, int n)
19071 unsigned char * where = (unsigned char *) buf;
19073 if (target_big_endian)
19078 result |= (*where++ & 255);
19086 result |= (where[n] & 255);
19093 /* MD interface: Sections. */
19095 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19096 that an rs_machine_dependent frag may reach. */
19099 arm_frag_max_var (fragS *fragp)
19101 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19102 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19104 Note that we generate relaxable instructions even for cases that don't
19105 really need it, like an immediate that's a trivial constant. So we're
19106 overestimating the instruction size for some of those cases. Rather
19107 than putting more intelligence here, it would probably be better to
19108 avoid generating a relaxation frag in the first place when it can be
19109 determined up front that a short instruction will suffice. */
19111 gas_assert (fragp->fr_type == rs_machine_dependent);
19115 /* Estimate the size of a frag before relaxing. Assume everything fits in
19119 md_estimate_size_before_relax (fragS * fragp,
19120 segT segtype ATTRIBUTE_UNUSED)
19126 /* Convert a machine dependent frag. */
19129 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19131 unsigned long insn;
19132 unsigned long old_op;
19140 buf = fragp->fr_literal + fragp->fr_fix;
19142 old_op = bfd_get_16(abfd, buf);
19143 if (fragp->fr_symbol)
19145 exp.X_op = O_symbol;
19146 exp.X_add_symbol = fragp->fr_symbol;
19150 exp.X_op = O_constant;
19152 exp.X_add_number = fragp->fr_offset;
19153 opcode = fragp->fr_subtype;
19156 case T_MNEM_ldr_pc:
19157 case T_MNEM_ldr_pc2:
19158 case T_MNEM_ldr_sp:
19159 case T_MNEM_str_sp:
19166 if (fragp->fr_var == 4)
19168 insn = THUMB_OP32 (opcode);
19169 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19171 insn |= (old_op & 0x700) << 4;
19175 insn |= (old_op & 7) << 12;
19176 insn |= (old_op & 0x38) << 13;
19178 insn |= 0x00000c00;
19179 put_thumb32_insn (buf, insn);
19180 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19184 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19186 pc_rel = (opcode == T_MNEM_ldr_pc2);
19189 if (fragp->fr_var == 4)
19191 insn = THUMB_OP32 (opcode);
19192 insn |= (old_op & 0xf0) << 4;
19193 put_thumb32_insn (buf, insn);
19194 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19198 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19199 exp.X_add_number -= 4;
19207 if (fragp->fr_var == 4)
19209 int r0off = (opcode == T_MNEM_mov
19210 || opcode == T_MNEM_movs) ? 0 : 8;
19211 insn = THUMB_OP32 (opcode);
19212 insn = (insn & 0xe1ffffff) | 0x10000000;
19213 insn |= (old_op & 0x700) << r0off;
19214 put_thumb32_insn (buf, insn);
19215 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19219 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19224 if (fragp->fr_var == 4)
19226 insn = THUMB_OP32(opcode);
19227 put_thumb32_insn (buf, insn);
19228 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19231 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19235 if (fragp->fr_var == 4)
19237 insn = THUMB_OP32(opcode);
19238 insn |= (old_op & 0xf00) << 14;
19239 put_thumb32_insn (buf, insn);
19240 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19243 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19246 case T_MNEM_add_sp:
19247 case T_MNEM_add_pc:
19248 case T_MNEM_inc_sp:
19249 case T_MNEM_dec_sp:
19250 if (fragp->fr_var == 4)
19252 /* ??? Choose between add and addw. */
19253 insn = THUMB_OP32 (opcode);
19254 insn |= (old_op & 0xf0) << 4;
19255 put_thumb32_insn (buf, insn);
19256 if (opcode == T_MNEM_add_pc)
19257 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19259 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19262 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19270 if (fragp->fr_var == 4)
19272 insn = THUMB_OP32 (opcode);
19273 insn |= (old_op & 0xf0) << 4;
19274 insn |= (old_op & 0xf) << 16;
19275 put_thumb32_insn (buf, insn);
19276 if (insn & (1 << 20))
19277 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19279 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19282 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19288 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19289 (enum bfd_reloc_code_real) reloc_type);
19290 fixp->fx_file = fragp->fr_file;
19291 fixp->fx_line = fragp->fr_line;
19292 fragp->fr_fix += fragp->fr_var;
19295 /* Return the size of a relaxable immediate operand instruction.
19296 SHIFT and SIZE specify the form of the allowable immediate. */
19298 relax_immediate (fragS *fragp, int size, int shift)
19304 /* ??? Should be able to do better than this. */
19305 if (fragp->fr_symbol)
19308 low = (1 << shift) - 1;
19309 mask = (1 << (shift + size)) - (1 << shift);
19310 offset = fragp->fr_offset;
19311 /* Force misaligned offsets to 32-bit variant. */
19314 if (offset & ~mask)
19319 /* Get the address of a symbol during relaxation. */
19321 relaxed_symbol_addr (fragS *fragp, long stretch)
19327 sym = fragp->fr_symbol;
19328 sym_frag = symbol_get_frag (sym);
19329 know (S_GET_SEGMENT (sym) != absolute_section
19330 || sym_frag == &zero_address_frag);
19331 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19333 /* If frag has yet to be reached on this pass, assume it will
19334 move by STRETCH just as we did. If this is not so, it will
19335 be because some frag between grows, and that will force
19339 && sym_frag->relax_marker != fragp->relax_marker)
19343 /* Adjust stretch for any alignment frag. Note that if have
19344 been expanding the earlier code, the symbol may be
19345 defined in what appears to be an earlier frag. FIXME:
19346 This doesn't handle the fr_subtype field, which specifies
19347 a maximum number of bytes to skip when doing an
19349 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19351 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19354 stretch = - ((- stretch)
19355 & ~ ((1 << (int) f->fr_offset) - 1));
19357 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19369 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19372 relax_adr (fragS *fragp, asection *sec, long stretch)
19377 /* Assume worst case for symbols not known to be in the same section. */
19378 if (fragp->fr_symbol == NULL
19379 || !S_IS_DEFINED (fragp->fr_symbol)
19380 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19381 || S_IS_WEAK (fragp->fr_symbol))
19384 val = relaxed_symbol_addr (fragp, stretch);
19385 addr = fragp->fr_address + fragp->fr_fix;
19386 addr = (addr + 4) & ~3;
19387 /* Force misaligned targets to 32-bit variant. */
19391 if (val < 0 || val > 1020)
19396 /* Return the size of a relaxable add/sub immediate instruction. */
19398 relax_addsub (fragS *fragp, asection *sec)
19403 buf = fragp->fr_literal + fragp->fr_fix;
19404 op = bfd_get_16(sec->owner, buf);
19405 if ((op & 0xf) == ((op >> 4) & 0xf))
19406 return relax_immediate (fragp, 8, 0);
19408 return relax_immediate (fragp, 3, 0);
19412 /* Return the size of a relaxable branch instruction. BITS is the
19413 size of the offset field in the narrow instruction. */
19416 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19422 /* Assume worst case for symbols not known to be in the same section. */
19423 if (!S_IS_DEFINED (fragp->fr_symbol)
19424 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19425 || S_IS_WEAK (fragp->fr_symbol))
19429 if (S_IS_DEFINED (fragp->fr_symbol)
19430 && ARM_IS_FUNC (fragp->fr_symbol))
19433 /* PR 12532. Global symbols with default visibility might
19434 be preempted, so do not relax relocations to them. */
19435 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19436 && (! S_IS_LOCAL (fragp->fr_symbol)))
19440 val = relaxed_symbol_addr (fragp, stretch);
19441 addr = fragp->fr_address + fragp->fr_fix + 4;
19444 /* Offset is a signed value *2 */
19446 if (val >= limit || val < -limit)
19452 /* Relax a machine dependent frag. This returns the amount by which
19453 the current size of the frag should change. */
19456 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19461 oldsize = fragp->fr_var;
19462 switch (fragp->fr_subtype)
19464 case T_MNEM_ldr_pc2:
19465 newsize = relax_adr (fragp, sec, stretch);
19467 case T_MNEM_ldr_pc:
19468 case T_MNEM_ldr_sp:
19469 case T_MNEM_str_sp:
19470 newsize = relax_immediate (fragp, 8, 2);
19474 newsize = relax_immediate (fragp, 5, 2);
19478 newsize = relax_immediate (fragp, 5, 1);
19482 newsize = relax_immediate (fragp, 5, 0);
19485 newsize = relax_adr (fragp, sec, stretch);
19491 newsize = relax_immediate (fragp, 8, 0);
19494 newsize = relax_branch (fragp, sec, 11, stretch);
19497 newsize = relax_branch (fragp, sec, 8, stretch);
19499 case T_MNEM_add_sp:
19500 case T_MNEM_add_pc:
19501 newsize = relax_immediate (fragp, 8, 2);
19503 case T_MNEM_inc_sp:
19504 case T_MNEM_dec_sp:
19505 newsize = relax_immediate (fragp, 7, 2);
19511 newsize = relax_addsub (fragp, sec);
19517 fragp->fr_var = newsize;
19518 /* Freeze wide instructions that are at or before the same location as
19519 in the previous pass. This avoids infinite loops.
19520 Don't freeze them unconditionally because targets may be artificially
19521 misaligned by the expansion of preceding frags. */
19522 if (stretch <= 0 && newsize > 2)
19524 md_convert_frag (sec->owner, sec, fragp);
19528 return newsize - oldsize;
19531 /* Round up a section size to the appropriate boundary. */
19534 md_section_align (segT segment ATTRIBUTE_UNUSED,
19537 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19538 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19540 /* For a.out, force the section size to be aligned. If we don't do
19541 this, BFD will align it for us, but it will not write out the
19542 final bytes of the section. This may be a bug in BFD, but it is
19543 easier to fix it here since that is how the other a.out targets
19547 align = bfd_get_section_alignment (stdoutput, segment);
19548 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19555 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19556 of an rs_align_code fragment. */
19559 arm_handle_align (fragS * fragP)
19561 static char const arm_noop[2][2][4] =
19564 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19565 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19568 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19569 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19572 static char const thumb_noop[2][2][2] =
19575 {0xc0, 0x46}, /* LE */
19576 {0x46, 0xc0}, /* BE */
19579 {0x00, 0xbf}, /* LE */
19580 {0xbf, 0x00} /* BE */
19583 static char const wide_thumb_noop[2][4] =
19584 { /* Wide Thumb-2 */
19585 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19586 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19589 unsigned bytes, fix, noop_size;
19592 const char *narrow_noop = NULL;
19597 if (fragP->fr_type != rs_align_code)
19600 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19601 p = fragP->fr_literal + fragP->fr_fix;
19604 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19605 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19607 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19609 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19611 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19613 narrow_noop = thumb_noop[1][target_big_endian];
19614 noop = wide_thumb_noop[target_big_endian];
19617 noop = thumb_noop[0][target_big_endian];
19625 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19626 [target_big_endian];
19633 fragP->fr_var = noop_size;
19635 if (bytes & (noop_size - 1))
19637 fix = bytes & (noop_size - 1);
19639 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19641 memset (p, 0, fix);
19648 if (bytes & noop_size)
19650 /* Insert a narrow noop. */
19651 memcpy (p, narrow_noop, noop_size);
19653 bytes -= noop_size;
19657 /* Use wide noops for the remainder */
19661 while (bytes >= noop_size)
19663 memcpy (p, noop, noop_size);
19665 bytes -= noop_size;
19669 fragP->fr_fix += fix;
19672 /* Called from md_do_align. Used to create an alignment
19673 frag in a code section. */
19676 arm_frag_align_code (int n, int max)
19680 /* We assume that there will never be a requirement
19681 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19682 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19687 _("alignments greater than %d bytes not supported in .text sections."),
19688 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19689 as_fatal ("%s", err_msg);
19692 p = frag_var (rs_align_code,
19693 MAX_MEM_FOR_RS_ALIGN_CODE,
19695 (relax_substateT) max,
19702 /* Perform target specific initialisation of a frag.
19703 Note - despite the name this initialisation is not done when the frag
19704 is created, but only when its type is assigned. A frag can be created
19705 and used a long time before its type is set, so beware of assuming that
19706 this initialisationis performed first. */
19710 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19712 /* Record whether this frag is in an ARM or a THUMB area. */
19713 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19716 #else /* OBJ_ELF is defined. */
19718 arm_init_frag (fragS * fragP, int max_chars)
19720 /* If the current ARM vs THUMB mode has not already
19721 been recorded into this frag then do so now. */
19722 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19724 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19726 /* Record a mapping symbol for alignment frags. We will delete this
19727 later if the alignment ends up empty. */
19728 switch (fragP->fr_type)
19731 case rs_align_test:
19733 mapping_state_2 (MAP_DATA, max_chars);
19735 case rs_align_code:
19736 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19744 /* When we change sections we need to issue a new mapping symbol. */
19747 arm_elf_change_section (void)
19749 /* Link an unlinked unwind index table section to the .text section. */
19750 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19751 && elf_linked_to_section (now_seg) == NULL)
19752 elf_linked_to_section (now_seg) = text_section;
19756 arm_elf_section_type (const char * str, size_t len)
19758 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19759 return SHT_ARM_EXIDX;
19764 /* Code to deal with unwinding tables. */
19766 static void add_unwind_adjustsp (offsetT);
19768 /* Generate any deferred unwind frame offset. */
19771 flush_pending_unwind (void)
19775 offset = unwind.pending_offset;
19776 unwind.pending_offset = 0;
19778 add_unwind_adjustsp (offset);
19781 /* Add an opcode to this list for this function. Two-byte opcodes should
19782 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19786 add_unwind_opcode (valueT op, int length)
19788 /* Add any deferred stack adjustment. */
19789 if (unwind.pending_offset)
19790 flush_pending_unwind ();
19792 unwind.sp_restored = 0;
19794 if (unwind.opcode_count + length > unwind.opcode_alloc)
19796 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19797 if (unwind.opcodes)
19798 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19799 unwind.opcode_alloc);
19801 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19806 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19808 unwind.opcode_count++;
19812 /* Add unwind opcodes to adjust the stack pointer. */
19815 add_unwind_adjustsp (offsetT offset)
19819 if (offset > 0x200)
19821 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19826 /* Long form: 0xb2, uleb128. */
19827 /* This might not fit in a word so add the individual bytes,
19828 remembering the list is built in reverse order. */
19829 o = (valueT) ((offset - 0x204) >> 2);
19831 add_unwind_opcode (0, 1);
19833 /* Calculate the uleb128 encoding of the offset. */
19837 bytes[n] = o & 0x7f;
19843 /* Add the insn. */
19845 add_unwind_opcode (bytes[n - 1], 1);
19846 add_unwind_opcode (0xb2, 1);
19848 else if (offset > 0x100)
19850 /* Two short opcodes. */
19851 add_unwind_opcode (0x3f, 1);
19852 op = (offset - 0x104) >> 2;
19853 add_unwind_opcode (op, 1);
19855 else if (offset > 0)
19857 /* Short opcode. */
19858 op = (offset - 4) >> 2;
19859 add_unwind_opcode (op, 1);
19861 else if (offset < 0)
19864 while (offset > 0x100)
19866 add_unwind_opcode (0x7f, 1);
19869 op = ((offset - 4) >> 2) | 0x40;
19870 add_unwind_opcode (op, 1);
19874 /* Finish the list of unwind opcodes for this function. */
19876 finish_unwind_opcodes (void)
19880 if (unwind.fp_used)
19882 /* Adjust sp as necessary. */
19883 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19884 flush_pending_unwind ();
19886 /* After restoring sp from the frame pointer. */
19887 op = 0x90 | unwind.fp_reg;
19888 add_unwind_opcode (op, 1);
19891 flush_pending_unwind ();
19895 /* Start an exception table entry. If idx is nonzero this is an index table
19899 start_unwind_section (const segT text_seg, int idx)
19901 const char * text_name;
19902 const char * prefix;
19903 const char * prefix_once;
19904 const char * group_name;
19908 size_t sec_name_len;
19915 prefix = ELF_STRING_ARM_unwind;
19916 prefix_once = ELF_STRING_ARM_unwind_once;
19917 type = SHT_ARM_EXIDX;
19921 prefix = ELF_STRING_ARM_unwind_info;
19922 prefix_once = ELF_STRING_ARM_unwind_info_once;
19923 type = SHT_PROGBITS;
19926 text_name = segment_name (text_seg);
19927 if (streq (text_name, ".text"))
19930 if (strncmp (text_name, ".gnu.linkonce.t.",
19931 strlen (".gnu.linkonce.t.")) == 0)
19933 prefix = prefix_once;
19934 text_name += strlen (".gnu.linkonce.t.");
19937 prefix_len = strlen (prefix);
19938 text_len = strlen (text_name);
19939 sec_name_len = prefix_len + text_len;
19940 sec_name = (char *) xmalloc (sec_name_len + 1);
19941 memcpy (sec_name, prefix, prefix_len);
19942 memcpy (sec_name + prefix_len, text_name, text_len);
19943 sec_name[prefix_len + text_len] = '\0';
19949 /* Handle COMDAT group. */
19950 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19952 group_name = elf_group_name (text_seg);
19953 if (group_name == NULL)
19955 as_bad (_("Group section `%s' has no group signature"),
19956 segment_name (text_seg));
19957 ignore_rest_of_line ();
19960 flags |= SHF_GROUP;
19964 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19966 /* Set the section link for index tables. */
19968 elf_linked_to_section (now_seg) = text_seg;
19972 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19973 personality routine data. Returns zero, or the index table value for
19974 and inline entry. */
19977 create_unwind_entry (int have_data)
19982 /* The current word of data. */
19984 /* The number of bytes left in this word. */
19987 finish_unwind_opcodes ();
19989 /* Remember the current text section. */
19990 unwind.saved_seg = now_seg;
19991 unwind.saved_subseg = now_subseg;
19993 start_unwind_section (now_seg, 0);
19995 if (unwind.personality_routine == NULL)
19997 if (unwind.personality_index == -2)
20000 as_bad (_("handlerdata in cantunwind frame"));
20001 return 1; /* EXIDX_CANTUNWIND. */
20004 /* Use a default personality routine if none is specified. */
20005 if (unwind.personality_index == -1)
20007 if (unwind.opcode_count > 3)
20008 unwind.personality_index = 1;
20010 unwind.personality_index = 0;
20013 /* Space for the personality routine entry. */
20014 if (unwind.personality_index == 0)
20016 if (unwind.opcode_count > 3)
20017 as_bad (_("too many unwind opcodes for personality routine 0"));
20021 /* All the data is inline in the index table. */
20024 while (unwind.opcode_count > 0)
20026 unwind.opcode_count--;
20027 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20031 /* Pad with "finish" opcodes. */
20033 data = (data << 8) | 0xb0;
20040 /* We get two opcodes "free" in the first word. */
20041 size = unwind.opcode_count - 2;
20045 gas_assert (unwind.personality_index == -1);
20047 /* An extra byte is required for the opcode count. */
20048 size = unwind.opcode_count + 1;
20051 size = (size + 3) >> 2;
20053 as_bad (_("too many unwind opcodes"));
20055 frag_align (2, 0, 0);
20056 record_alignment (now_seg, 2);
20057 unwind.table_entry = expr_build_dot ();
20059 /* Allocate the table entry. */
20060 ptr = frag_more ((size << 2) + 4);
20061 /* PR 13449: Zero the table entries in case some of them are not used. */
20062 memset (ptr, 0, (size << 2) + 4);
20063 where = frag_now_fix () - ((size << 2) + 4);
20065 switch (unwind.personality_index)
20068 /* ??? Should this be a PLT generating relocation? */
20069 /* Custom personality routine. */
20070 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20071 BFD_RELOC_ARM_PREL31);
20076 /* Set the first byte to the number of additional words. */
20077 data = size > 0 ? size - 1 : 0;
20081 /* ABI defined personality routines. */
20083 /* Three opcodes bytes are packed into the first word. */
20090 /* The size and first two opcode bytes go in the first word. */
20091 data = ((0x80 + unwind.personality_index) << 8) | size;
20096 /* Should never happen. */
20100 /* Pack the opcodes into words (MSB first), reversing the list at the same
20102 while (unwind.opcode_count > 0)
20106 md_number_to_chars (ptr, data, 4);
20111 unwind.opcode_count--;
20113 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20116 /* Finish off the last word. */
20119 /* Pad with "finish" opcodes. */
20121 data = (data << 8) | 0xb0;
20123 md_number_to_chars (ptr, data, 4);
20128 /* Add an empty descriptor if there is no user-specified data. */
20129 ptr = frag_more (4);
20130 md_number_to_chars (ptr, 0, 4);
20137 /* Initialize the DWARF-2 unwind information for this procedure. */
20140 tc_arm_frame_initial_instructions (void)
20142 cfi_add_CFA_def_cfa (REG_SP, 0);
20144 #endif /* OBJ_ELF */
20146 /* Convert REGNAME to a DWARF-2 register number. */
20149 tc_arm_regname_to_dw2regnum (char *regname)
20151 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20161 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20165 exp.X_op = O_secrel;
20166 exp.X_add_symbol = symbol;
20167 exp.X_add_number = 0;
20168 emit_expr (&exp, size);
20172 /* MD interface: Symbol and relocation handling. */
20174 /* Return the address within the segment that a PC-relative fixup is
20175 relative to. For ARM, PC-relative fixups applied to instructions
20176 are generally relative to the location of the fixup plus 8 bytes.
20177 Thumb branches are offset by 4, and Thumb loads relative to PC
20178 require special handling. */
20181 md_pcrel_from_section (fixS * fixP, segT seg)
20183 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20185 /* If this is pc-relative and we are going to emit a relocation
20186 then we just want to put out any pipeline compensation that the linker
20187 will need. Otherwise we want to use the calculated base.
20188 For WinCE we skip the bias for externals as well, since this
20189 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20191 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20192 || (arm_force_relocation (fixP)
20194 && !S_IS_EXTERNAL (fixP->fx_addsy)
20200 switch (fixP->fx_r_type)
20202 /* PC relative addressing on the Thumb is slightly odd as the
20203 bottom two bits of the PC are forced to zero for the
20204 calculation. This happens *after* application of the
20205 pipeline offset. However, Thumb adrl already adjusts for
20206 this, so we need not do it again. */
20207 case BFD_RELOC_ARM_THUMB_ADD:
20210 case BFD_RELOC_ARM_THUMB_OFFSET:
20211 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20212 case BFD_RELOC_ARM_T32_ADD_PC12:
20213 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20214 return (base + 4) & ~3;
20216 /* Thumb branches are simply offset by +4. */
20217 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20218 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20219 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20220 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20221 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20224 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20226 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20227 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20228 && ARM_IS_FUNC (fixP->fx_addsy)
20229 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20230 base = fixP->fx_where + fixP->fx_frag->fr_address;
20233 /* BLX is like branches above, but forces the low two bits of PC to
20235 case BFD_RELOC_THUMB_PCREL_BLX:
20237 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20238 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20239 && THUMB_IS_FUNC (fixP->fx_addsy)
20240 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20241 base = fixP->fx_where + fixP->fx_frag->fr_address;
20242 return (base + 4) & ~3;
20244 /* ARM mode branches are offset by +8. However, the Windows CE
20245 loader expects the relocation not to take this into account. */
20246 case BFD_RELOC_ARM_PCREL_BLX:
20248 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20249 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20250 && ARM_IS_FUNC (fixP->fx_addsy)
20251 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20252 base = fixP->fx_where + fixP->fx_frag->fr_address;
20255 case BFD_RELOC_ARM_PCREL_CALL:
20257 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20258 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20259 && THUMB_IS_FUNC (fixP->fx_addsy)
20260 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20261 base = fixP->fx_where + fixP->fx_frag->fr_address;
20264 case BFD_RELOC_ARM_PCREL_BRANCH:
20265 case BFD_RELOC_ARM_PCREL_JUMP:
20266 case BFD_RELOC_ARM_PLT32:
20268 /* When handling fixups immediately, because we have already
20269 discovered the value of a symbol, or the address of the frag involved
20270 we must account for the offset by +8, as the OS loader will never see the reloc.
20271 see fixup_segment() in write.c
20272 The S_IS_EXTERNAL test handles the case of global symbols.
20273 Those need the calculated base, not just the pipe compensation the linker will need. */
20275 && fixP->fx_addsy != NULL
20276 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20277 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20285 /* ARM mode loads relative to PC are also offset by +8. Unlike
20286 branches, the Windows CE loader *does* expect the relocation
20287 to take this into account. */
20288 case BFD_RELOC_ARM_OFFSET_IMM:
20289 case BFD_RELOC_ARM_OFFSET_IMM8:
20290 case BFD_RELOC_ARM_HWLITERAL:
20291 case BFD_RELOC_ARM_LITERAL:
20292 case BFD_RELOC_ARM_CP_OFF_IMM:
20296 /* Other PC-relative relocations are un-offset. */
20302 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20303 Otherwise we have no need to default values of symbols. */
20306 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20309 if (name[0] == '_' && name[1] == 'G'
20310 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20314 if (symbol_find (name))
20315 as_bad (_("GOT already in the symbol table"));
20317 GOT_symbol = symbol_new (name, undefined_section,
20318 (valueT) 0, & zero_address_frag);
20328 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20329 computed as two separate immediate values, added together. We
20330 already know that this value cannot be computed by just one ARM
20333 static unsigned int
20334 validate_immediate_twopart (unsigned int val,
20335 unsigned int * highpart)
20340 for (i = 0; i < 32; i += 2)
20341 if (((a = rotate_left (val, i)) & 0xff) != 0)
20347 * highpart = (a >> 8) | ((i + 24) << 7);
20349 else if (a & 0xff0000)
20351 if (a & 0xff000000)
20353 * highpart = (a >> 16) | ((i + 16) << 7);
20357 gas_assert (a & 0xff000000);
20358 * highpart = (a >> 24) | ((i + 8) << 7);
20361 return (a & 0xff) | (i << 7);
20368 validate_offset_imm (unsigned int val, int hwse)
20370 if ((hwse && val > 255) || val > 4095)
20375 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20376 negative immediate constant by altering the instruction. A bit of
20381 by inverting the second operand, and
20384 by negating the second operand. */
20387 negate_data_op (unsigned long * instruction,
20388 unsigned long value)
20391 unsigned long negated, inverted;
20393 negated = encode_arm_immediate (-value);
20394 inverted = encode_arm_immediate (~value);
20396 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20399 /* First negates. */
20400 case OPCODE_SUB: /* ADD <-> SUB */
20401 new_inst = OPCODE_ADD;
20406 new_inst = OPCODE_SUB;
20410 case OPCODE_CMP: /* CMP <-> CMN */
20411 new_inst = OPCODE_CMN;
20416 new_inst = OPCODE_CMP;
20420 /* Now Inverted ops. */
20421 case OPCODE_MOV: /* MOV <-> MVN */
20422 new_inst = OPCODE_MVN;
20427 new_inst = OPCODE_MOV;
20431 case OPCODE_AND: /* AND <-> BIC */
20432 new_inst = OPCODE_BIC;
20437 new_inst = OPCODE_AND;
20441 case OPCODE_ADC: /* ADC <-> SBC */
20442 new_inst = OPCODE_SBC;
20447 new_inst = OPCODE_ADC;
20451 /* We cannot do anything. */
20456 if (value == (unsigned) FAIL)
20459 *instruction &= OPCODE_MASK;
20460 *instruction |= new_inst << DATA_OP_SHIFT;
20464 /* Like negate_data_op, but for Thumb-2. */
20466 static unsigned int
20467 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20471 unsigned int negated, inverted;
20473 negated = encode_thumb32_immediate (-value);
20474 inverted = encode_thumb32_immediate (~value);
20476 rd = (*instruction >> 8) & 0xf;
20477 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20480 /* ADD <-> SUB. Includes CMP <-> CMN. */
20481 case T2_OPCODE_SUB:
20482 new_inst = T2_OPCODE_ADD;
20486 case T2_OPCODE_ADD:
20487 new_inst = T2_OPCODE_SUB;
20491 /* ORR <-> ORN. Includes MOV <-> MVN. */
20492 case T2_OPCODE_ORR:
20493 new_inst = T2_OPCODE_ORN;
20497 case T2_OPCODE_ORN:
20498 new_inst = T2_OPCODE_ORR;
20502 /* AND <-> BIC. TST has no inverted equivalent. */
20503 case T2_OPCODE_AND:
20504 new_inst = T2_OPCODE_BIC;
20511 case T2_OPCODE_BIC:
20512 new_inst = T2_OPCODE_AND;
20517 case T2_OPCODE_ADC:
20518 new_inst = T2_OPCODE_SBC;
20522 case T2_OPCODE_SBC:
20523 new_inst = T2_OPCODE_ADC;
20527 /* We cannot do anything. */
20532 if (value == (unsigned int)FAIL)
20535 *instruction &= T2_OPCODE_MASK;
20536 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20540 /* Read a 32-bit thumb instruction from buf. */
20541 static unsigned long
20542 get_thumb32_insn (char * buf)
20544 unsigned long insn;
20545 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20546 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20552 /* We usually want to set the low bit on the address of thumb function
20553 symbols. In particular .word foo - . should have the low bit set.
20554 Generic code tries to fold the difference of two symbols to
20555 a constant. Prevent this and force a relocation when the first symbols
20556 is a thumb function. */
20559 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20561 if (op == O_subtract
20562 && l->X_op == O_symbol
20563 && r->X_op == O_symbol
20564 && THUMB_IS_FUNC (l->X_add_symbol))
20566 l->X_op = O_subtract;
20567 l->X_op_symbol = r->X_add_symbol;
20568 l->X_add_number -= r->X_add_number;
20572 /* Process as normal. */
20576 /* Encode Thumb2 unconditional branches and calls. The encoding
20577 for the 2 are identical for the immediate values. */
20580 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20582 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20585 addressT S, I1, I2, lo, hi;
20587 S = (value >> 24) & 0x01;
20588 I1 = (value >> 23) & 0x01;
20589 I2 = (value >> 22) & 0x01;
20590 hi = (value >> 12) & 0x3ff;
20591 lo = (value >> 1) & 0x7ff;
20592 newval = md_chars_to_number (buf, THUMB_SIZE);
20593 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20594 newval |= (S << 10) | hi;
20595 newval2 &= ~T2I1I2MASK;
20596 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20597 md_number_to_chars (buf, newval, THUMB_SIZE);
20598 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20602 md_apply_fix (fixS * fixP,
20606 offsetT value = * valP;
20608 unsigned int newimm;
20609 unsigned long temp;
20611 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20613 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20615 /* Note whether this will delete the relocation. */
20617 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20620 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20621 consistency with the behaviour on 32-bit hosts. Remember value
20623 value &= 0xffffffff;
20624 value ^= 0x80000000;
20625 value -= 0x80000000;
20628 fixP->fx_addnumber = value;
20630 /* Same treatment for fixP->fx_offset. */
20631 fixP->fx_offset &= 0xffffffff;
20632 fixP->fx_offset ^= 0x80000000;
20633 fixP->fx_offset -= 0x80000000;
20635 switch (fixP->fx_r_type)
20637 case BFD_RELOC_NONE:
20638 /* This will need to go in the object file. */
20642 case BFD_RELOC_ARM_IMMEDIATE:
20643 /* We claim that this fixup has been processed here,
20644 even if in fact we generate an error because we do
20645 not have a reloc for it, so tc_gen_reloc will reject it. */
20648 if (fixP->fx_addsy)
20650 const char *msg = 0;
20652 if (! S_IS_DEFINED (fixP->fx_addsy))
20653 msg = _("undefined symbol %s used as an immediate value");
20654 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20655 msg = _("symbol %s is in a different section");
20656 else if (S_IS_WEAK (fixP->fx_addsy))
20657 msg = _("symbol %s is weak and may be overridden later");
20661 as_bad_where (fixP->fx_file, fixP->fx_line,
20662 msg, S_GET_NAME (fixP->fx_addsy));
20667 temp = md_chars_to_number (buf, INSN_SIZE);
20669 /* If the offset is negative, we should use encoding A2 for ADR. */
20670 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
20671 newimm = negate_data_op (&temp, value);
20674 newimm = encode_arm_immediate (value);
20676 /* If the instruction will fail, see if we can fix things up by
20677 changing the opcode. */
20678 if (newimm == (unsigned int) FAIL)
20679 newimm = negate_data_op (&temp, value);
20682 if (newimm == (unsigned int) FAIL)
20684 as_bad_where (fixP->fx_file, fixP->fx_line,
20685 _("invalid constant (%lx) after fixup"),
20686 (unsigned long) value);
20690 newimm |= (temp & 0xfffff000);
20691 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20694 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20696 unsigned int highpart = 0;
20697 unsigned int newinsn = 0xe1a00000; /* nop. */
20699 if (fixP->fx_addsy)
20701 const char *msg = 0;
20703 if (! S_IS_DEFINED (fixP->fx_addsy))
20704 msg = _("undefined symbol %s used as an immediate value");
20705 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20706 msg = _("symbol %s is in a different section");
20707 else if (S_IS_WEAK (fixP->fx_addsy))
20708 msg = _("symbol %s is weak and may be overridden later");
20712 as_bad_where (fixP->fx_file, fixP->fx_line,
20713 msg, S_GET_NAME (fixP->fx_addsy));
20718 newimm = encode_arm_immediate (value);
20719 temp = md_chars_to_number (buf, INSN_SIZE);
20721 /* If the instruction will fail, see if we can fix things up by
20722 changing the opcode. */
20723 if (newimm == (unsigned int) FAIL
20724 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20726 /* No ? OK - try using two ADD instructions to generate
20728 newimm = validate_immediate_twopart (value, & highpart);
20730 /* Yes - then make sure that the second instruction is
20732 if (newimm != (unsigned int) FAIL)
20734 /* Still No ? Try using a negated value. */
20735 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20736 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20737 /* Otherwise - give up. */
20740 as_bad_where (fixP->fx_file, fixP->fx_line,
20741 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20746 /* Replace the first operand in the 2nd instruction (which
20747 is the PC) with the destination register. We have
20748 already added in the PC in the first instruction and we
20749 do not want to do it again. */
20750 newinsn &= ~ 0xf0000;
20751 newinsn |= ((newinsn & 0x0f000) << 4);
20754 newimm |= (temp & 0xfffff000);
20755 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20757 highpart |= (newinsn & 0xfffff000);
20758 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20762 case BFD_RELOC_ARM_OFFSET_IMM:
20763 if (!fixP->fx_done && seg->use_rela_p)
20766 case BFD_RELOC_ARM_LITERAL:
20772 if (validate_offset_imm (value, 0) == FAIL)
20774 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20775 as_bad_where (fixP->fx_file, fixP->fx_line,
20776 _("invalid literal constant: pool needs to be closer"));
20778 as_bad_where (fixP->fx_file, fixP->fx_line,
20779 _("bad immediate value for offset (%ld)"),
20784 newval = md_chars_to_number (buf, INSN_SIZE);
20786 newval &= 0xfffff000;
20789 newval &= 0xff7ff000;
20790 newval |= value | (sign ? INDEX_UP : 0);
20792 md_number_to_chars (buf, newval, INSN_SIZE);
20795 case BFD_RELOC_ARM_OFFSET_IMM8:
20796 case BFD_RELOC_ARM_HWLITERAL:
20802 if (validate_offset_imm (value, 1) == FAIL)
20804 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20805 as_bad_where (fixP->fx_file, fixP->fx_line,
20806 _("invalid literal constant: pool needs to be closer"));
20808 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20813 newval = md_chars_to_number (buf, INSN_SIZE);
20815 newval &= 0xfffff0f0;
20818 newval &= 0xff7ff0f0;
20819 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20821 md_number_to_chars (buf, newval, INSN_SIZE);
20824 case BFD_RELOC_ARM_T32_OFFSET_U8:
20825 if (value < 0 || value > 1020 || value % 4 != 0)
20826 as_bad_where (fixP->fx_file, fixP->fx_line,
20827 _("bad immediate value for offset (%ld)"), (long) value);
20830 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20832 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20835 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20836 /* This is a complicated relocation used for all varieties of Thumb32
20837 load/store instruction with immediate offset:
20839 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20840 *4, optional writeback(W)
20841 (doubleword load/store)
20843 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20844 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20845 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20846 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20847 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20849 Uppercase letters indicate bits that are already encoded at
20850 this point. Lowercase letters are our problem. For the
20851 second block of instructions, the secondary opcode nybble
20852 (bits 8..11) is present, and bit 23 is zero, even if this is
20853 a PC-relative operation. */
20854 newval = md_chars_to_number (buf, THUMB_SIZE);
20856 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20858 if ((newval & 0xf0000000) == 0xe0000000)
20860 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20862 newval |= (1 << 23);
20865 if (value % 4 != 0)
20867 as_bad_where (fixP->fx_file, fixP->fx_line,
20868 _("offset not a multiple of 4"));
20874 as_bad_where (fixP->fx_file, fixP->fx_line,
20875 _("offset out of range"));
20880 else if ((newval & 0x000f0000) == 0x000f0000)
20882 /* PC-relative, 12-bit offset. */
20884 newval |= (1 << 23);
20889 as_bad_where (fixP->fx_file, fixP->fx_line,
20890 _("offset out of range"));
20895 else if ((newval & 0x00000100) == 0x00000100)
20897 /* Writeback: 8-bit, +/- offset. */
20899 newval |= (1 << 9);
20904 as_bad_where (fixP->fx_file, fixP->fx_line,
20905 _("offset out of range"));
20910 else if ((newval & 0x00000f00) == 0x00000e00)
20912 /* T-instruction: positive 8-bit offset. */
20913 if (value < 0 || value > 0xff)
20915 as_bad_where (fixP->fx_file, fixP->fx_line,
20916 _("offset out of range"));
20924 /* Positive 12-bit or negative 8-bit offset. */
20928 newval |= (1 << 23);
20938 as_bad_where (fixP->fx_file, fixP->fx_line,
20939 _("offset out of range"));
20946 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20947 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20950 case BFD_RELOC_ARM_SHIFT_IMM:
20951 newval = md_chars_to_number (buf, INSN_SIZE);
20952 if (((unsigned long) value) > 32
20954 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20956 as_bad_where (fixP->fx_file, fixP->fx_line,
20957 _("shift expression is too large"));
20962 /* Shifts of zero must be done as lsl. */
20964 else if (value == 32)
20966 newval &= 0xfffff07f;
20967 newval |= (value & 0x1f) << 7;
20968 md_number_to_chars (buf, newval, INSN_SIZE);
20971 case BFD_RELOC_ARM_T32_IMMEDIATE:
20972 case BFD_RELOC_ARM_T32_ADD_IMM:
20973 case BFD_RELOC_ARM_T32_IMM12:
20974 case BFD_RELOC_ARM_T32_ADD_PC12:
20975 /* We claim that this fixup has been processed here,
20976 even if in fact we generate an error because we do
20977 not have a reloc for it, so tc_gen_reloc will reject it. */
20981 && ! S_IS_DEFINED (fixP->fx_addsy))
20983 as_bad_where (fixP->fx_file, fixP->fx_line,
20984 _("undefined symbol %s used as an immediate value"),
20985 S_GET_NAME (fixP->fx_addsy));
20989 newval = md_chars_to_number (buf, THUMB_SIZE);
20991 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20994 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20995 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20997 newimm = encode_thumb32_immediate (value);
20998 if (newimm == (unsigned int) FAIL)
20999 newimm = thumb32_negate_data_op (&newval, value);
21001 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21002 && newimm == (unsigned int) FAIL)
21004 /* Turn add/sum into addw/subw. */
21005 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21006 newval = (newval & 0xfeffffff) | 0x02000000;
21007 /* No flat 12-bit imm encoding for addsw/subsw. */
21008 if ((newval & 0x00100000) == 0)
21010 /* 12 bit immediate for addw/subw. */
21014 newval ^= 0x00a00000;
21017 newimm = (unsigned int) FAIL;
21023 if (newimm == (unsigned int)FAIL)
21025 as_bad_where (fixP->fx_file, fixP->fx_line,
21026 _("invalid constant (%lx) after fixup"),
21027 (unsigned long) value);
21031 newval |= (newimm & 0x800) << 15;
21032 newval |= (newimm & 0x700) << 4;
21033 newval |= (newimm & 0x0ff);
21035 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21036 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21039 case BFD_RELOC_ARM_SMC:
21040 if (((unsigned long) value) > 0xffff)
21041 as_bad_where (fixP->fx_file, fixP->fx_line,
21042 _("invalid smc expression"));
21043 newval = md_chars_to_number (buf, INSN_SIZE);
21044 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21045 md_number_to_chars (buf, newval, INSN_SIZE);
21048 case BFD_RELOC_ARM_HVC:
21049 if (((unsigned long) value) > 0xffff)
21050 as_bad_where (fixP->fx_file, fixP->fx_line,
21051 _("invalid hvc expression"));
21052 newval = md_chars_to_number (buf, INSN_SIZE);
21053 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21054 md_number_to_chars (buf, newval, INSN_SIZE);
21057 case BFD_RELOC_ARM_SWI:
21058 if (fixP->tc_fix_data != 0)
21060 if (((unsigned long) value) > 0xff)
21061 as_bad_where (fixP->fx_file, fixP->fx_line,
21062 _("invalid swi expression"));
21063 newval = md_chars_to_number (buf, THUMB_SIZE);
21065 md_number_to_chars (buf, newval, THUMB_SIZE);
21069 if (((unsigned long) value) > 0x00ffffff)
21070 as_bad_where (fixP->fx_file, fixP->fx_line,
21071 _("invalid swi expression"));
21072 newval = md_chars_to_number (buf, INSN_SIZE);
21074 md_number_to_chars (buf, newval, INSN_SIZE);
21078 case BFD_RELOC_ARM_MULTI:
21079 if (((unsigned long) value) > 0xffff)
21080 as_bad_where (fixP->fx_file, fixP->fx_line,
21081 _("invalid expression in load/store multiple"));
21082 newval = value | md_chars_to_number (buf, INSN_SIZE);
21083 md_number_to_chars (buf, newval, INSN_SIZE);
21087 case BFD_RELOC_ARM_PCREL_CALL:
21089 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21091 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21092 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21093 && THUMB_IS_FUNC (fixP->fx_addsy))
21094 /* Flip the bl to blx. This is a simple flip
21095 bit here because we generate PCREL_CALL for
21096 unconditional bls. */
21098 newval = md_chars_to_number (buf, INSN_SIZE);
21099 newval = newval | 0x10000000;
21100 md_number_to_chars (buf, newval, INSN_SIZE);
21106 goto arm_branch_common;
21108 case BFD_RELOC_ARM_PCREL_JUMP:
21109 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21111 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21112 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21113 && THUMB_IS_FUNC (fixP->fx_addsy))
21115 /* This would map to a bl<cond>, b<cond>,
21116 b<always> to a Thumb function. We
21117 need to force a relocation for this particular
21119 newval = md_chars_to_number (buf, INSN_SIZE);
21123 case BFD_RELOC_ARM_PLT32:
21125 case BFD_RELOC_ARM_PCREL_BRANCH:
21127 goto arm_branch_common;
21129 case BFD_RELOC_ARM_PCREL_BLX:
21132 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21134 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21135 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21136 && ARM_IS_FUNC (fixP->fx_addsy))
21138 /* Flip the blx to a bl and warn. */
21139 const char *name = S_GET_NAME (fixP->fx_addsy);
21140 newval = 0xeb000000;
21141 as_warn_where (fixP->fx_file, fixP->fx_line,
21142 _("blx to '%s' an ARM ISA state function changed to bl"),
21144 md_number_to_chars (buf, newval, INSN_SIZE);
21150 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21151 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21155 /* We are going to store value (shifted right by two) in the
21156 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21157 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21158 also be be clear. */
21160 as_bad_where (fixP->fx_file, fixP->fx_line,
21161 _("misaligned branch destination"));
21162 if ((value & (offsetT)0xfe000000) != (offsetT)0
21163 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21164 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21166 if (fixP->fx_done || !seg->use_rela_p)
21168 newval = md_chars_to_number (buf, INSN_SIZE);
21169 newval |= (value >> 2) & 0x00ffffff;
21170 /* Set the H bit on BLX instructions. */
21174 newval |= 0x01000000;
21176 newval &= ~0x01000000;
21178 md_number_to_chars (buf, newval, INSN_SIZE);
21182 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21183 /* CBZ can only branch forward. */
21185 /* Attempts to use CBZ to branch to the next instruction
21186 (which, strictly speaking, are prohibited) will be turned into
21189 FIXME: It may be better to remove the instruction completely and
21190 perform relaxation. */
21193 newval = md_chars_to_number (buf, THUMB_SIZE);
21194 newval = 0xbf00; /* NOP encoding T1 */
21195 md_number_to_chars (buf, newval, THUMB_SIZE);
21200 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21202 if (fixP->fx_done || !seg->use_rela_p)
21204 newval = md_chars_to_number (buf, THUMB_SIZE);
21205 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21206 md_number_to_chars (buf, newval, THUMB_SIZE);
21211 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21212 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21213 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21215 if (fixP->fx_done || !seg->use_rela_p)
21217 newval = md_chars_to_number (buf, THUMB_SIZE);
21218 newval |= (value & 0x1ff) >> 1;
21219 md_number_to_chars (buf, newval, THUMB_SIZE);
21223 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21224 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21225 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21227 if (fixP->fx_done || !seg->use_rela_p)
21229 newval = md_chars_to_number (buf, THUMB_SIZE);
21230 newval |= (value & 0xfff) >> 1;
21231 md_number_to_chars (buf, newval, THUMB_SIZE);
21235 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21237 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21238 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21239 && ARM_IS_FUNC (fixP->fx_addsy)
21240 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21242 /* Force a relocation for a branch 20 bits wide. */
21245 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21246 as_bad_where (fixP->fx_file, fixP->fx_line,
21247 _("conditional branch out of range"));
21249 if (fixP->fx_done || !seg->use_rela_p)
21252 addressT S, J1, J2, lo, hi;
21254 S = (value & 0x00100000) >> 20;
21255 J2 = (value & 0x00080000) >> 19;
21256 J1 = (value & 0x00040000) >> 18;
21257 hi = (value & 0x0003f000) >> 12;
21258 lo = (value & 0x00000ffe) >> 1;
21260 newval = md_chars_to_number (buf, THUMB_SIZE);
21261 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21262 newval |= (S << 10) | hi;
21263 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21264 md_number_to_chars (buf, newval, THUMB_SIZE);
21265 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21269 case BFD_RELOC_THUMB_PCREL_BLX:
21270 /* If there is a blx from a thumb state function to
21271 another thumb function flip this to a bl and warn
21275 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21276 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21277 && THUMB_IS_FUNC (fixP->fx_addsy))
21279 const char *name = S_GET_NAME (fixP->fx_addsy);
21280 as_warn_where (fixP->fx_file, fixP->fx_line,
21281 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21283 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21284 newval = newval | 0x1000;
21285 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21286 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21291 goto thumb_bl_common;
21293 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21294 /* A bl from Thumb state ISA to an internal ARM state function
21295 is converted to a blx. */
21297 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21298 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21299 && ARM_IS_FUNC (fixP->fx_addsy)
21300 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21302 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21303 newval = newval & ~0x1000;
21304 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21305 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21312 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
21313 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21314 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21317 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21318 /* For a BLX instruction, make sure that the relocation is rounded up
21319 to a word boundary. This follows the semantics of the instruction
21320 which specifies that bit 1 of the target address will come from bit
21321 1 of the base address. */
21322 value = (value + 1) & ~ 1;
21324 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21326 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21327 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21328 else if ((value & ~0x1ffffff)
21329 && ((value & ~0x1ffffff) != ~0x1ffffff))
21330 as_bad_where (fixP->fx_file, fixP->fx_line,
21331 _("Thumb2 branch out of range"));
21334 if (fixP->fx_done || !seg->use_rela_p)
21335 encode_thumb2_b_bl_offset (buf, value);
21339 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21340 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21341 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21343 if (fixP->fx_done || !seg->use_rela_p)
21344 encode_thumb2_b_bl_offset (buf, value);
21349 if (fixP->fx_done || !seg->use_rela_p)
21350 md_number_to_chars (buf, value, 1);
21354 if (fixP->fx_done || !seg->use_rela_p)
21355 md_number_to_chars (buf, value, 2);
21359 case BFD_RELOC_ARM_TLS_CALL:
21360 case BFD_RELOC_ARM_THM_TLS_CALL:
21361 case BFD_RELOC_ARM_TLS_DESCSEQ:
21362 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21363 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21366 case BFD_RELOC_ARM_TLS_GOTDESC:
21367 case BFD_RELOC_ARM_TLS_GD32:
21368 case BFD_RELOC_ARM_TLS_LE32:
21369 case BFD_RELOC_ARM_TLS_IE32:
21370 case BFD_RELOC_ARM_TLS_LDM32:
21371 case BFD_RELOC_ARM_TLS_LDO32:
21372 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21375 case BFD_RELOC_ARM_GOT32:
21376 case BFD_RELOC_ARM_GOTOFF:
21377 if (fixP->fx_done || !seg->use_rela_p)
21378 md_number_to_chars (buf, 0, 4);
21381 case BFD_RELOC_ARM_GOT_PREL:
21382 if (fixP->fx_done || !seg->use_rela_p)
21383 md_number_to_chars (buf, value, 4);
21386 case BFD_RELOC_ARM_TARGET2:
21387 /* TARGET2 is not partial-inplace, so we need to write the
21388 addend here for REL targets, because it won't be written out
21389 during reloc processing later. */
21390 if (fixP->fx_done || !seg->use_rela_p)
21391 md_number_to_chars (buf, fixP->fx_offset, 4);
21395 case BFD_RELOC_RVA:
21397 case BFD_RELOC_ARM_TARGET1:
21398 case BFD_RELOC_ARM_ROSEGREL32:
21399 case BFD_RELOC_ARM_SBREL32:
21400 case BFD_RELOC_32_PCREL:
21402 case BFD_RELOC_32_SECREL:
21404 if (fixP->fx_done || !seg->use_rela_p)
21406 /* For WinCE we only do this for pcrel fixups. */
21407 if (fixP->fx_done || fixP->fx_pcrel)
21409 md_number_to_chars (buf, value, 4);
21413 case BFD_RELOC_ARM_PREL31:
21414 if (fixP->fx_done || !seg->use_rela_p)
21416 newval = md_chars_to_number (buf, 4) & 0x80000000;
21417 if ((value ^ (value >> 1)) & 0x40000000)
21419 as_bad_where (fixP->fx_file, fixP->fx_line,
21420 _("rel31 relocation overflow"));
21422 newval |= value & 0x7fffffff;
21423 md_number_to_chars (buf, newval, 4);
21428 case BFD_RELOC_ARM_CP_OFF_IMM:
21429 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21430 if (value < -1023 || value > 1023 || (value & 3))
21431 as_bad_where (fixP->fx_file, fixP->fx_line,
21432 _("co-processor offset out of range"));
21437 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21438 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21439 newval = md_chars_to_number (buf, INSN_SIZE);
21441 newval = get_thumb32_insn (buf);
21443 newval &= 0xffffff00;
21446 newval &= 0xff7fff00;
21447 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21449 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21450 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21451 md_number_to_chars (buf, newval, INSN_SIZE);
21453 put_thumb32_insn (buf, newval);
21456 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21457 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21458 if (value < -255 || value > 255)
21459 as_bad_where (fixP->fx_file, fixP->fx_line,
21460 _("co-processor offset out of range"));
21462 goto cp_off_common;
21464 case BFD_RELOC_ARM_THUMB_OFFSET:
21465 newval = md_chars_to_number (buf, THUMB_SIZE);
21466 /* Exactly what ranges, and where the offset is inserted depends
21467 on the type of instruction, we can establish this from the
21469 switch (newval >> 12)
21471 case 4: /* PC load. */
21472 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21473 forced to zero for these loads; md_pcrel_from has already
21474 compensated for this. */
21476 as_bad_where (fixP->fx_file, fixP->fx_line,
21477 _("invalid offset, target not word aligned (0x%08lX)"),
21478 (((unsigned long) fixP->fx_frag->fr_address
21479 + (unsigned long) fixP->fx_where) & ~3)
21480 + (unsigned long) value);
21482 if (value & ~0x3fc)
21483 as_bad_where (fixP->fx_file, fixP->fx_line,
21484 _("invalid offset, value too big (0x%08lX)"),
21487 newval |= value >> 2;
21490 case 9: /* SP load/store. */
21491 if (value & ~0x3fc)
21492 as_bad_where (fixP->fx_file, fixP->fx_line,
21493 _("invalid offset, value too big (0x%08lX)"),
21495 newval |= value >> 2;
21498 case 6: /* Word load/store. */
21500 as_bad_where (fixP->fx_file, fixP->fx_line,
21501 _("invalid offset, value too big (0x%08lX)"),
21503 newval |= value << 4; /* 6 - 2. */
21506 case 7: /* Byte load/store. */
21508 as_bad_where (fixP->fx_file, fixP->fx_line,
21509 _("invalid offset, value too big (0x%08lX)"),
21511 newval |= value << 6;
21514 case 8: /* Halfword load/store. */
21516 as_bad_where (fixP->fx_file, fixP->fx_line,
21517 _("invalid offset, value too big (0x%08lX)"),
21519 newval |= value << 5; /* 6 - 1. */
21523 as_bad_where (fixP->fx_file, fixP->fx_line,
21524 "Unable to process relocation for thumb opcode: %lx",
21525 (unsigned long) newval);
21528 md_number_to_chars (buf, newval, THUMB_SIZE);
21531 case BFD_RELOC_ARM_THUMB_ADD:
21532 /* This is a complicated relocation, since we use it for all of
21533 the following immediate relocations:
21537 9bit ADD/SUB SP word-aligned
21538 10bit ADD PC/SP word-aligned
21540 The type of instruction being processed is encoded in the
21547 newval = md_chars_to_number (buf, THUMB_SIZE);
21549 int rd = (newval >> 4) & 0xf;
21550 int rs = newval & 0xf;
21551 int subtract = !!(newval & 0x8000);
21553 /* Check for HI regs, only very restricted cases allowed:
21554 Adjusting SP, and using PC or SP to get an address. */
21555 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21556 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21557 as_bad_where (fixP->fx_file, fixP->fx_line,
21558 _("invalid Hi register with immediate"));
21560 /* If value is negative, choose the opposite instruction. */
21564 subtract = !subtract;
21566 as_bad_where (fixP->fx_file, fixP->fx_line,
21567 _("immediate value out of range"));
21572 if (value & ~0x1fc)
21573 as_bad_where (fixP->fx_file, fixP->fx_line,
21574 _("invalid immediate for stack address calculation"));
21575 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21576 newval |= value >> 2;
21578 else if (rs == REG_PC || rs == REG_SP)
21580 if (subtract || value & ~0x3fc)
21581 as_bad_where (fixP->fx_file, fixP->fx_line,
21582 _("invalid immediate for address calculation (value = 0x%08lX)"),
21583 (unsigned long) value);
21584 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21586 newval |= value >> 2;
21591 as_bad_where (fixP->fx_file, fixP->fx_line,
21592 _("immediate value out of range"));
21593 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21594 newval |= (rd << 8) | value;
21599 as_bad_where (fixP->fx_file, fixP->fx_line,
21600 _("immediate value out of range"));
21601 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21602 newval |= rd | (rs << 3) | (value << 6);
21605 md_number_to_chars (buf, newval, THUMB_SIZE);
21608 case BFD_RELOC_ARM_THUMB_IMM:
21609 newval = md_chars_to_number (buf, THUMB_SIZE);
21610 if (value < 0 || value > 255)
21611 as_bad_where (fixP->fx_file, fixP->fx_line,
21612 _("invalid immediate: %ld is out of range"),
21615 md_number_to_chars (buf, newval, THUMB_SIZE);
21618 case BFD_RELOC_ARM_THUMB_SHIFT:
21619 /* 5bit shift value (0..32). LSL cannot take 32. */
21620 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21621 temp = newval & 0xf800;
21622 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21623 as_bad_where (fixP->fx_file, fixP->fx_line,
21624 _("invalid shift value: %ld"), (long) value);
21625 /* Shifts of zero must be encoded as LSL. */
21627 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21628 /* Shifts of 32 are encoded as zero. */
21629 else if (value == 32)
21631 newval |= value << 6;
21632 md_number_to_chars (buf, newval, THUMB_SIZE);
21635 case BFD_RELOC_VTABLE_INHERIT:
21636 case BFD_RELOC_VTABLE_ENTRY:
21640 case BFD_RELOC_ARM_MOVW:
21641 case BFD_RELOC_ARM_MOVT:
21642 case BFD_RELOC_ARM_THUMB_MOVW:
21643 case BFD_RELOC_ARM_THUMB_MOVT:
21644 if (fixP->fx_done || !seg->use_rela_p)
21646 /* REL format relocations are limited to a 16-bit addend. */
21647 if (!fixP->fx_done)
21649 if (value < -0x8000 || value > 0x7fff)
21650 as_bad_where (fixP->fx_file, fixP->fx_line,
21651 _("offset out of range"));
21653 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21654 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21659 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21660 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21662 newval = get_thumb32_insn (buf);
21663 newval &= 0xfbf08f00;
21664 newval |= (value & 0xf000) << 4;
21665 newval |= (value & 0x0800) << 15;
21666 newval |= (value & 0x0700) << 4;
21667 newval |= (value & 0x00ff);
21668 put_thumb32_insn (buf, newval);
21672 newval = md_chars_to_number (buf, 4);
21673 newval &= 0xfff0f000;
21674 newval |= value & 0x0fff;
21675 newval |= (value & 0xf000) << 4;
21676 md_number_to_chars (buf, newval, 4);
21681 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21682 case BFD_RELOC_ARM_ALU_PC_G0:
21683 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21684 case BFD_RELOC_ARM_ALU_PC_G1:
21685 case BFD_RELOC_ARM_ALU_PC_G2:
21686 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21687 case BFD_RELOC_ARM_ALU_SB_G0:
21688 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21689 case BFD_RELOC_ARM_ALU_SB_G1:
21690 case BFD_RELOC_ARM_ALU_SB_G2:
21691 gas_assert (!fixP->fx_done);
21692 if (!seg->use_rela_p)
21695 bfd_vma encoded_addend;
21696 bfd_vma addend_abs = abs (value);
21698 /* Check that the absolute value of the addend can be
21699 expressed as an 8-bit constant plus a rotation. */
21700 encoded_addend = encode_arm_immediate (addend_abs);
21701 if (encoded_addend == (unsigned int) FAIL)
21702 as_bad_where (fixP->fx_file, fixP->fx_line,
21703 _("the offset 0x%08lX is not representable"),
21704 (unsigned long) addend_abs);
21706 /* Extract the instruction. */
21707 insn = md_chars_to_number (buf, INSN_SIZE);
21709 /* If the addend is positive, use an ADD instruction.
21710 Otherwise use a SUB. Take care not to destroy the S bit. */
21711 insn &= 0xff1fffff;
21717 /* Place the encoded addend into the first 12 bits of the
21719 insn &= 0xfffff000;
21720 insn |= encoded_addend;
21722 /* Update the instruction. */
21723 md_number_to_chars (buf, insn, INSN_SIZE);
21727 case BFD_RELOC_ARM_LDR_PC_G0:
21728 case BFD_RELOC_ARM_LDR_PC_G1:
21729 case BFD_RELOC_ARM_LDR_PC_G2:
21730 case BFD_RELOC_ARM_LDR_SB_G0:
21731 case BFD_RELOC_ARM_LDR_SB_G1:
21732 case BFD_RELOC_ARM_LDR_SB_G2:
21733 gas_assert (!fixP->fx_done);
21734 if (!seg->use_rela_p)
21737 bfd_vma addend_abs = abs (value);
21739 /* Check that the absolute value of the addend can be
21740 encoded in 12 bits. */
21741 if (addend_abs >= 0x1000)
21742 as_bad_where (fixP->fx_file, fixP->fx_line,
21743 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21744 (unsigned long) addend_abs);
21746 /* Extract the instruction. */
21747 insn = md_chars_to_number (buf, INSN_SIZE);
21749 /* If the addend is negative, clear bit 23 of the instruction.
21750 Otherwise set it. */
21752 insn &= ~(1 << 23);
21756 /* Place the absolute value of the addend into the first 12 bits
21757 of the instruction. */
21758 insn &= 0xfffff000;
21759 insn |= addend_abs;
21761 /* Update the instruction. */
21762 md_number_to_chars (buf, insn, INSN_SIZE);
21766 case BFD_RELOC_ARM_LDRS_PC_G0:
21767 case BFD_RELOC_ARM_LDRS_PC_G1:
21768 case BFD_RELOC_ARM_LDRS_PC_G2:
21769 case BFD_RELOC_ARM_LDRS_SB_G0:
21770 case BFD_RELOC_ARM_LDRS_SB_G1:
21771 case BFD_RELOC_ARM_LDRS_SB_G2:
21772 gas_assert (!fixP->fx_done);
21773 if (!seg->use_rela_p)
21776 bfd_vma addend_abs = abs (value);
21778 /* Check that the absolute value of the addend can be
21779 encoded in 8 bits. */
21780 if (addend_abs >= 0x100)
21781 as_bad_where (fixP->fx_file, fixP->fx_line,
21782 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21783 (unsigned long) addend_abs);
21785 /* Extract the instruction. */
21786 insn = md_chars_to_number (buf, INSN_SIZE);
21788 /* If the addend is negative, clear bit 23 of the instruction.
21789 Otherwise set it. */
21791 insn &= ~(1 << 23);
21795 /* Place the first four bits of the absolute value of the addend
21796 into the first 4 bits of the instruction, and the remaining
21797 four into bits 8 .. 11. */
21798 insn &= 0xfffff0f0;
21799 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21801 /* Update the instruction. */
21802 md_number_to_chars (buf, insn, INSN_SIZE);
21806 case BFD_RELOC_ARM_LDC_PC_G0:
21807 case BFD_RELOC_ARM_LDC_PC_G1:
21808 case BFD_RELOC_ARM_LDC_PC_G2:
21809 case BFD_RELOC_ARM_LDC_SB_G0:
21810 case BFD_RELOC_ARM_LDC_SB_G1:
21811 case BFD_RELOC_ARM_LDC_SB_G2:
21812 gas_assert (!fixP->fx_done);
21813 if (!seg->use_rela_p)
21816 bfd_vma addend_abs = abs (value);
21818 /* Check that the absolute value of the addend is a multiple of
21819 four and, when divided by four, fits in 8 bits. */
21820 if (addend_abs & 0x3)
21821 as_bad_where (fixP->fx_file, fixP->fx_line,
21822 _("bad offset 0x%08lX (must be word-aligned)"),
21823 (unsigned long) addend_abs);
21825 if ((addend_abs >> 2) > 0xff)
21826 as_bad_where (fixP->fx_file, fixP->fx_line,
21827 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21828 (unsigned long) addend_abs);
21830 /* Extract the instruction. */
21831 insn = md_chars_to_number (buf, INSN_SIZE);
21833 /* If the addend is negative, clear bit 23 of the instruction.
21834 Otherwise set it. */
21836 insn &= ~(1 << 23);
21840 /* Place the addend (divided by four) into the first eight
21841 bits of the instruction. */
21842 insn &= 0xfffffff0;
21843 insn |= addend_abs >> 2;
21845 /* Update the instruction. */
21846 md_number_to_chars (buf, insn, INSN_SIZE);
21850 case BFD_RELOC_ARM_V4BX:
21851 /* This will need to go in the object file. */
21855 case BFD_RELOC_UNUSED:
21857 as_bad_where (fixP->fx_file, fixP->fx_line,
21858 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21862 /* Translate internal representation of relocation info to BFD target
21866 tc_gen_reloc (asection *section, fixS *fixp)
21869 bfd_reloc_code_real_type code;
21871 reloc = (arelent *) xmalloc (sizeof (arelent));
21873 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21874 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21875 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21877 if (fixp->fx_pcrel)
21879 if (section->use_rela_p)
21880 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21882 fixp->fx_offset = reloc->address;
21884 reloc->addend = fixp->fx_offset;
21886 switch (fixp->fx_r_type)
21889 if (fixp->fx_pcrel)
21891 code = BFD_RELOC_8_PCREL;
21896 if (fixp->fx_pcrel)
21898 code = BFD_RELOC_16_PCREL;
21903 if (fixp->fx_pcrel)
21905 code = BFD_RELOC_32_PCREL;
21909 case BFD_RELOC_ARM_MOVW:
21910 if (fixp->fx_pcrel)
21912 code = BFD_RELOC_ARM_MOVW_PCREL;
21916 case BFD_RELOC_ARM_MOVT:
21917 if (fixp->fx_pcrel)
21919 code = BFD_RELOC_ARM_MOVT_PCREL;
21923 case BFD_RELOC_ARM_THUMB_MOVW:
21924 if (fixp->fx_pcrel)
21926 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21930 case BFD_RELOC_ARM_THUMB_MOVT:
21931 if (fixp->fx_pcrel)
21933 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21937 case BFD_RELOC_NONE:
21938 case BFD_RELOC_ARM_PCREL_BRANCH:
21939 case BFD_RELOC_ARM_PCREL_BLX:
21940 case BFD_RELOC_RVA:
21941 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21942 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21943 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21944 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21945 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21946 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21947 case BFD_RELOC_VTABLE_ENTRY:
21948 case BFD_RELOC_VTABLE_INHERIT:
21950 case BFD_RELOC_32_SECREL:
21952 code = fixp->fx_r_type;
21955 case BFD_RELOC_THUMB_PCREL_BLX:
21957 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21958 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21961 code = BFD_RELOC_THUMB_PCREL_BLX;
21964 case BFD_RELOC_ARM_LITERAL:
21965 case BFD_RELOC_ARM_HWLITERAL:
21966 /* If this is called then the a literal has
21967 been referenced across a section boundary. */
21968 as_bad_where (fixp->fx_file, fixp->fx_line,
21969 _("literal referenced across section boundary"));
21973 case BFD_RELOC_ARM_TLS_CALL:
21974 case BFD_RELOC_ARM_THM_TLS_CALL:
21975 case BFD_RELOC_ARM_TLS_DESCSEQ:
21976 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21977 case BFD_RELOC_ARM_GOT32:
21978 case BFD_RELOC_ARM_GOTOFF:
21979 case BFD_RELOC_ARM_GOT_PREL:
21980 case BFD_RELOC_ARM_PLT32:
21981 case BFD_RELOC_ARM_TARGET1:
21982 case BFD_RELOC_ARM_ROSEGREL32:
21983 case BFD_RELOC_ARM_SBREL32:
21984 case BFD_RELOC_ARM_PREL31:
21985 case BFD_RELOC_ARM_TARGET2:
21986 case BFD_RELOC_ARM_TLS_LE32:
21987 case BFD_RELOC_ARM_TLS_LDO32:
21988 case BFD_RELOC_ARM_PCREL_CALL:
21989 case BFD_RELOC_ARM_PCREL_JUMP:
21990 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21991 case BFD_RELOC_ARM_ALU_PC_G0:
21992 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21993 case BFD_RELOC_ARM_ALU_PC_G1:
21994 case BFD_RELOC_ARM_ALU_PC_G2:
21995 case BFD_RELOC_ARM_LDR_PC_G0:
21996 case BFD_RELOC_ARM_LDR_PC_G1:
21997 case BFD_RELOC_ARM_LDR_PC_G2:
21998 case BFD_RELOC_ARM_LDRS_PC_G0:
21999 case BFD_RELOC_ARM_LDRS_PC_G1:
22000 case BFD_RELOC_ARM_LDRS_PC_G2:
22001 case BFD_RELOC_ARM_LDC_PC_G0:
22002 case BFD_RELOC_ARM_LDC_PC_G1:
22003 case BFD_RELOC_ARM_LDC_PC_G2:
22004 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22005 case BFD_RELOC_ARM_ALU_SB_G0:
22006 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22007 case BFD_RELOC_ARM_ALU_SB_G1:
22008 case BFD_RELOC_ARM_ALU_SB_G2:
22009 case BFD_RELOC_ARM_LDR_SB_G0:
22010 case BFD_RELOC_ARM_LDR_SB_G1:
22011 case BFD_RELOC_ARM_LDR_SB_G2:
22012 case BFD_RELOC_ARM_LDRS_SB_G0:
22013 case BFD_RELOC_ARM_LDRS_SB_G1:
22014 case BFD_RELOC_ARM_LDRS_SB_G2:
22015 case BFD_RELOC_ARM_LDC_SB_G0:
22016 case BFD_RELOC_ARM_LDC_SB_G1:
22017 case BFD_RELOC_ARM_LDC_SB_G2:
22018 case BFD_RELOC_ARM_V4BX:
22019 code = fixp->fx_r_type;
22022 case BFD_RELOC_ARM_TLS_GOTDESC:
22023 case BFD_RELOC_ARM_TLS_GD32:
22024 case BFD_RELOC_ARM_TLS_IE32:
22025 case BFD_RELOC_ARM_TLS_LDM32:
22026 /* BFD will include the symbol's address in the addend.
22027 But we don't want that, so subtract it out again here. */
22028 if (!S_IS_COMMON (fixp->fx_addsy))
22029 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22030 code = fixp->fx_r_type;
22034 case BFD_RELOC_ARM_IMMEDIATE:
22035 as_bad_where (fixp->fx_file, fixp->fx_line,
22036 _("internal relocation (type: IMMEDIATE) not fixed up"));
22039 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22040 as_bad_where (fixp->fx_file, fixp->fx_line,
22041 _("ADRL used for a symbol not defined in the same file"));
22044 case BFD_RELOC_ARM_OFFSET_IMM:
22045 if (section->use_rela_p)
22047 code = fixp->fx_r_type;
22051 if (fixp->fx_addsy != NULL
22052 && !S_IS_DEFINED (fixp->fx_addsy)
22053 && S_IS_LOCAL (fixp->fx_addsy))
22055 as_bad_where (fixp->fx_file, fixp->fx_line,
22056 _("undefined local label `%s'"),
22057 S_GET_NAME (fixp->fx_addsy));
22061 as_bad_where (fixp->fx_file, fixp->fx_line,
22062 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22069 switch (fixp->fx_r_type)
22071 case BFD_RELOC_NONE: type = "NONE"; break;
22072 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22073 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22074 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22075 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22076 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22077 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22078 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22079 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22080 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22081 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22082 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22083 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22084 default: type = _("<unknown>"); break;
22086 as_bad_where (fixp->fx_file, fixp->fx_line,
22087 _("cannot represent %s relocation in this object file format"),
22094 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22096 && fixp->fx_addsy == GOT_symbol)
22098 code = BFD_RELOC_ARM_GOTPC;
22099 reloc->addend = fixp->fx_offset = reloc->address;
22103 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22105 if (reloc->howto == NULL)
22107 as_bad_where (fixp->fx_file, fixp->fx_line,
22108 _("cannot represent %s relocation in this object file format"),
22109 bfd_get_reloc_code_name (code));
22113 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22114 vtable entry to be used in the relocation's section offset. */
22115 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22116 reloc->address = fixp->fx_offset;
22121 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22124 cons_fix_new_arm (fragS * frag,
22129 bfd_reloc_code_real_type type;
22133 FIXME: @@ Should look at CPU word size. */
22137 type = BFD_RELOC_8;
22140 type = BFD_RELOC_16;
22144 type = BFD_RELOC_32;
22147 type = BFD_RELOC_64;
22152 if (exp->X_op == O_secrel)
22154 exp->X_op = O_symbol;
22155 type = BFD_RELOC_32_SECREL;
22159 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22162 #if defined (OBJ_COFF)
22164 arm_validate_fix (fixS * fixP)
22166 /* If the destination of the branch is a defined symbol which does not have
22167 the THUMB_FUNC attribute, then we must be calling a function which has
22168 the (interfacearm) attribute. We look for the Thumb entry point to that
22169 function and change the branch to refer to that function instead. */
22170 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22171 && fixP->fx_addsy != NULL
22172 && S_IS_DEFINED (fixP->fx_addsy)
22173 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22175 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22182 arm_force_relocation (struct fix * fixp)
22184 #if defined (OBJ_COFF) && defined (TE_PE)
22185 if (fixp->fx_r_type == BFD_RELOC_RVA)
22189 /* In case we have a call or a branch to a function in ARM ISA mode from
22190 a thumb function or vice-versa force the relocation. These relocations
22191 are cleared off for some cores that might have blx and simple transformations
22195 switch (fixp->fx_r_type)
22197 case BFD_RELOC_ARM_PCREL_JUMP:
22198 case BFD_RELOC_ARM_PCREL_CALL:
22199 case BFD_RELOC_THUMB_PCREL_BLX:
22200 if (THUMB_IS_FUNC (fixp->fx_addsy))
22204 case BFD_RELOC_ARM_PCREL_BLX:
22205 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22206 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22207 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22208 if (ARM_IS_FUNC (fixp->fx_addsy))
22217 /* Resolve these relocations even if the symbol is extern or weak.
22218 Technically this is probably wrong due to symbol preemption.
22219 In practice these relocations do not have enough range to be useful
22220 at dynamic link time, and some code (e.g. in the Linux kernel)
22221 expects these references to be resolved. */
22222 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22223 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22224 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22225 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22226 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22227 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22228 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22229 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22230 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22231 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22232 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22233 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22234 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22235 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22238 /* Always leave these relocations for the linker. */
22239 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22240 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22241 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22244 /* Always generate relocations against function symbols. */
22245 if (fixp->fx_r_type == BFD_RELOC_32
22247 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22250 return generic_force_reloc (fixp);
22253 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22254 /* Relocations against function names must be left unadjusted,
22255 so that the linker can use this information to generate interworking
22256 stubs. The MIPS version of this function
22257 also prevents relocations that are mips-16 specific, but I do not
22258 know why it does this.
22261 There is one other problem that ought to be addressed here, but
22262 which currently is not: Taking the address of a label (rather
22263 than a function) and then later jumping to that address. Such
22264 addresses also ought to have their bottom bit set (assuming that
22265 they reside in Thumb code), but at the moment they will not. */
22268 arm_fix_adjustable (fixS * fixP)
22270 if (fixP->fx_addsy == NULL)
22273 /* Preserve relocations against symbols with function type. */
22274 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22277 if (THUMB_IS_FUNC (fixP->fx_addsy)
22278 && fixP->fx_subsy == NULL)
22281 /* We need the symbol name for the VTABLE entries. */
22282 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22283 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22286 /* Don't allow symbols to be discarded on GOT related relocs. */
22287 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22288 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22289 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22290 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22291 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22292 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22293 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22294 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22295 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22296 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22297 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22298 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22299 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22300 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22303 /* Similarly for group relocations. */
22304 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22305 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22306 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22309 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22310 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22311 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22312 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22313 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22314 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22315 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22316 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22317 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22322 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22327 elf32_arm_target_format (void)
22330 return (target_big_endian
22331 ? "elf32-bigarm-symbian"
22332 : "elf32-littlearm-symbian");
22333 #elif defined (TE_VXWORKS)
22334 return (target_big_endian
22335 ? "elf32-bigarm-vxworks"
22336 : "elf32-littlearm-vxworks");
22337 #elif defined (TE_NACL)
22338 return (target_big_endian
22339 ? "elf32-bigarm-nacl"
22340 : "elf32-littlearm-nacl");
22342 if (target_big_endian)
22343 return "elf32-bigarm";
22345 return "elf32-littlearm";
22350 armelf_frob_symbol (symbolS * symp,
22353 elf_frob_symbol (symp, puntp);
22357 /* MD interface: Finalization. */
22362 literal_pool * pool;
22364 /* Ensure that all the IT blocks are properly closed. */
22365 check_it_blocks_finished ();
22367 for (pool = list_of_pools; pool; pool = pool->next)
22369 /* Put it at the end of the relevant section. */
22370 subseg_set (pool->section, pool->sub_section);
22372 arm_elf_change_section ();
22379 /* Remove any excess mapping symbols generated for alignment frags in
22380 SEC. We may have created a mapping symbol before a zero byte
22381 alignment; remove it if there's a mapping symbol after the
22384 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22385 void *dummy ATTRIBUTE_UNUSED)
22387 segment_info_type *seginfo = seg_info (sec);
22390 if (seginfo == NULL || seginfo->frchainP == NULL)
22393 for (fragp = seginfo->frchainP->frch_root;
22395 fragp = fragp->fr_next)
22397 symbolS *sym = fragp->tc_frag_data.last_map;
22398 fragS *next = fragp->fr_next;
22400 /* Variable-sized frags have been converted to fixed size by
22401 this point. But if this was variable-sized to start with,
22402 there will be a fixed-size frag after it. So don't handle
22404 if (sym == NULL || next == NULL)
22407 if (S_GET_VALUE (sym) < next->fr_address)
22408 /* Not at the end of this frag. */
22410 know (S_GET_VALUE (sym) == next->fr_address);
22414 if (next->tc_frag_data.first_map != NULL)
22416 /* Next frag starts with a mapping symbol. Discard this
22418 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22422 if (next->fr_next == NULL)
22424 /* This mapping symbol is at the end of the section. Discard
22426 know (next->fr_fix == 0 && next->fr_var == 0);
22427 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22431 /* As long as we have empty frags without any mapping symbols,
22433 /* If the next frag is non-empty and does not start with a
22434 mapping symbol, then this mapping symbol is required. */
22435 if (next->fr_address != next->fr_next->fr_address)
22438 next = next->fr_next;
22440 while (next != NULL);
22445 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22449 arm_adjust_symtab (void)
22454 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22456 if (ARM_IS_THUMB (sym))
22458 if (THUMB_IS_FUNC (sym))
22460 /* Mark the symbol as a Thumb function. */
22461 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22462 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22463 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22465 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22466 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22468 as_bad (_("%s: unexpected function type: %d"),
22469 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22471 else switch (S_GET_STORAGE_CLASS (sym))
22474 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22477 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22480 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22488 if (ARM_IS_INTERWORK (sym))
22489 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22496 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22498 if (ARM_IS_THUMB (sym))
22500 elf_symbol_type * elf_sym;
22502 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22503 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22505 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22506 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22508 /* If it's a .thumb_func, declare it as so,
22509 otherwise tag label as .code 16. */
22510 if (THUMB_IS_FUNC (sym))
22511 elf_sym->internal_elf_sym.st_target_internal
22512 = ST_BRANCH_TO_THUMB;
22513 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22514 elf_sym->internal_elf_sym.st_info =
22515 ELF_ST_INFO (bind, STT_ARM_16BIT);
22520 /* Remove any overlapping mapping symbols generated by alignment frags. */
22521 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22522 /* Now do generic ELF adjustments. */
22523 elf_adjust_symtab ();
22527 /* MD interface: Initialization. */
22530 set_constant_flonums (void)
22534 for (i = 0; i < NUM_FLOAT_VALS; i++)
22535 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22539 /* Auto-select Thumb mode if it's the only available instruction set for the
22540 given architecture. */
22543 autoselect_thumb_from_cpu_variant (void)
22545 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22546 opcode_select (16);
22555 if ( (arm_ops_hsh = hash_new ()) == NULL
22556 || (arm_cond_hsh = hash_new ()) == NULL
22557 || (arm_shift_hsh = hash_new ()) == NULL
22558 || (arm_psr_hsh = hash_new ()) == NULL
22559 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22560 || (arm_reg_hsh = hash_new ()) == NULL
22561 || (arm_reloc_hsh = hash_new ()) == NULL
22562 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22563 as_fatal (_("virtual memory exhausted"));
22565 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22566 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22567 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22568 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22569 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22570 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22571 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22572 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22573 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22574 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22575 (void *) (v7m_psrs + i));
22576 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22577 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22579 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22581 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22582 (void *) (barrier_opt_names + i));
22584 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22586 struct reloc_entry * entry = reloc_names + i;
22588 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22589 /* This makes encode_branch() use the EABI versions of this relocation. */
22590 entry->reloc = BFD_RELOC_UNUSED;
22592 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22596 set_constant_flonums ();
22598 /* Set the cpu variant based on the command-line options. We prefer
22599 -mcpu= over -march= if both are set (as for GCC); and we prefer
22600 -mfpu= over any other way of setting the floating point unit.
22601 Use of legacy options with new options are faulted. */
22604 if (mcpu_cpu_opt || march_cpu_opt)
22605 as_bad (_("use of old and new-style options to set CPU type"));
22607 mcpu_cpu_opt = legacy_cpu;
22609 else if (!mcpu_cpu_opt)
22610 mcpu_cpu_opt = march_cpu_opt;
22615 as_bad (_("use of old and new-style options to set FPU type"));
22617 mfpu_opt = legacy_fpu;
22619 else if (!mfpu_opt)
22621 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22622 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22623 /* Some environments specify a default FPU. If they don't, infer it
22624 from the processor. */
22626 mfpu_opt = mcpu_fpu_opt;
22628 mfpu_opt = march_fpu_opt;
22630 mfpu_opt = &fpu_default;
22636 if (mcpu_cpu_opt != NULL)
22637 mfpu_opt = &fpu_default;
22638 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22639 mfpu_opt = &fpu_arch_vfp_v2;
22641 mfpu_opt = &fpu_arch_fpa;
22647 mcpu_cpu_opt = &cpu_default;
22648 selected_cpu = cpu_default;
22652 selected_cpu = *mcpu_cpu_opt;
22654 mcpu_cpu_opt = &arm_arch_any;
22657 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22659 autoselect_thumb_from_cpu_variant ();
22661 arm_arch_used = thumb_arch_used = arm_arch_none;
22663 #if defined OBJ_COFF || defined OBJ_ELF
22665 unsigned int flags = 0;
22667 #if defined OBJ_ELF
22668 flags = meabi_flags;
22670 switch (meabi_flags)
22672 case EF_ARM_EABI_UNKNOWN:
22674 /* Set the flags in the private structure. */
22675 if (uses_apcs_26) flags |= F_APCS26;
22676 if (support_interwork) flags |= F_INTERWORK;
22677 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22678 if (pic_code) flags |= F_PIC;
22679 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22680 flags |= F_SOFT_FLOAT;
22682 switch (mfloat_abi_opt)
22684 case ARM_FLOAT_ABI_SOFT:
22685 case ARM_FLOAT_ABI_SOFTFP:
22686 flags |= F_SOFT_FLOAT;
22689 case ARM_FLOAT_ABI_HARD:
22690 if (flags & F_SOFT_FLOAT)
22691 as_bad (_("hard-float conflicts with specified fpu"));
22695 /* Using pure-endian doubles (even if soft-float). */
22696 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22697 flags |= F_VFP_FLOAT;
22699 #if defined OBJ_ELF
22700 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22701 flags |= EF_ARM_MAVERICK_FLOAT;
22704 case EF_ARM_EABI_VER4:
22705 case EF_ARM_EABI_VER5:
22706 /* No additional flags to set. */
22713 bfd_set_private_flags (stdoutput, flags);
22715 /* We have run out flags in the COFF header to encode the
22716 status of ATPCS support, so instead we create a dummy,
22717 empty, debug section called .arm.atpcs. */
22722 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22726 bfd_set_section_flags
22727 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22728 bfd_set_section_size (stdoutput, sec, 0);
22729 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22735 /* Record the CPU type as well. */
22736 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22737 mach = bfd_mach_arm_iWMMXt2;
22738 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22739 mach = bfd_mach_arm_iWMMXt;
22740 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22741 mach = bfd_mach_arm_XScale;
22742 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22743 mach = bfd_mach_arm_ep9312;
22744 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22745 mach = bfd_mach_arm_5TE;
22746 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22748 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22749 mach = bfd_mach_arm_5T;
22751 mach = bfd_mach_arm_5;
22753 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22755 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22756 mach = bfd_mach_arm_4T;
22758 mach = bfd_mach_arm_4;
22760 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22761 mach = bfd_mach_arm_3M;
22762 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22763 mach = bfd_mach_arm_3;
22764 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22765 mach = bfd_mach_arm_2a;
22766 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22767 mach = bfd_mach_arm_2;
22769 mach = bfd_mach_arm_unknown;
22771 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22774 /* Command line processing. */
22777 Invocation line includes a switch not recognized by the base assembler.
22778 See if it's a processor-specific option.
22780 This routine is somewhat complicated by the need for backwards
22781 compatibility (since older releases of gcc can't be changed).
22782 The new options try to make the interface as compatible as
22785 New options (supported) are:
22787 -mcpu=<cpu name> Assemble for selected processor
22788 -march=<architecture name> Assemble for selected architecture
22789 -mfpu=<fpu architecture> Assemble for selected FPU.
22790 -EB/-mbig-endian Big-endian
22791 -EL/-mlittle-endian Little-endian
22792 -k Generate PIC code
22793 -mthumb Start in Thumb mode
22794 -mthumb-interwork Code supports ARM/Thumb interworking
22796 -m[no-]warn-deprecated Warn about deprecated features
22798 For now we will also provide support for:
22800 -mapcs-32 32-bit Program counter
22801 -mapcs-26 26-bit Program counter
22802 -macps-float Floats passed in FP registers
22803 -mapcs-reentrant Reentrant code
22805 (sometime these will probably be replaced with -mapcs=<list of options>
22806 and -matpcs=<list of options>)
22808 The remaining options are only supported for back-wards compatibility.
22809 Cpu variants, the arm part is optional:
22810 -m[arm]1 Currently not supported.
22811 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22812 -m[arm]3 Arm 3 processor
22813 -m[arm]6[xx], Arm 6 processors
22814 -m[arm]7[xx][t][[d]m] Arm 7 processors
22815 -m[arm]8[10] Arm 8 processors
22816 -m[arm]9[20][tdmi] Arm 9 processors
22817 -mstrongarm[110[0]] StrongARM processors
22818 -mxscale XScale processors
22819 -m[arm]v[2345[t[e]]] Arm architectures
22820 -mall All (except the ARM1)
22822 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22823 -mfpe-old (No float load/store multiples)
22824 -mvfpxd VFP Single precision
22826 -mno-fpu Disable all floating point instructions
22828 The following CPU names are recognized:
22829 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22830 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22831 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22832 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22833 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22834 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22835 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22839 const char * md_shortopts = "m:k";
22841 #ifdef ARM_BI_ENDIAN
22842 #define OPTION_EB (OPTION_MD_BASE + 0)
22843 #define OPTION_EL (OPTION_MD_BASE + 1)
22845 #if TARGET_BYTES_BIG_ENDIAN
22846 #define OPTION_EB (OPTION_MD_BASE + 0)
22848 #define OPTION_EL (OPTION_MD_BASE + 1)
22851 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22853 struct option md_longopts[] =
22856 {"EB", no_argument, NULL, OPTION_EB},
22859 {"EL", no_argument, NULL, OPTION_EL},
22861 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22862 {NULL, no_argument, NULL, 0}
22865 size_t md_longopts_size = sizeof (md_longopts);
22867 struct arm_option_table
22869 char *option; /* Option name to match. */
22870 char *help; /* Help information. */
22871 int *var; /* Variable to change. */
22872 int value; /* What to change it to. */
22873 char *deprecated; /* If non-null, print this message. */
22876 struct arm_option_table arm_opts[] =
22878 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22879 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22880 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22881 &support_interwork, 1, NULL},
22882 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22883 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22884 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22886 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22887 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22888 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22889 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22892 /* These are recognized by the assembler, but have no affect on code. */
22893 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22894 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22896 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22897 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22898 &warn_on_deprecated, 0, NULL},
22899 {NULL, NULL, NULL, 0, NULL}
22902 struct arm_legacy_option_table
22904 char *option; /* Option name to match. */
22905 const arm_feature_set **var; /* Variable to change. */
22906 const arm_feature_set value; /* What to change it to. */
22907 char *deprecated; /* If non-null, print this message. */
22910 const struct arm_legacy_option_table arm_legacy_opts[] =
22912 /* DON'T add any new processors to this list -- we want the whole list
22913 to go away... Add them to the processors table instead. */
22914 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22915 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22916 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22917 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22918 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22919 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22920 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22921 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22922 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22923 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22924 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22925 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22926 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22927 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22928 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22929 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22930 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22931 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22932 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22933 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22934 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22935 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22936 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22937 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22938 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22939 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22940 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22941 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22942 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22943 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22944 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22945 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22946 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22947 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22948 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22949 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22950 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22951 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22952 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22953 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22954 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22955 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22956 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22957 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22958 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22959 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22960 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22961 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22962 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22963 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22964 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22965 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22966 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22967 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22968 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22969 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22970 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22971 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22972 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22973 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22974 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22975 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22976 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22977 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22978 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22979 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22980 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22981 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22982 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22983 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22984 N_("use -mcpu=strongarm110")},
22985 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22986 N_("use -mcpu=strongarm1100")},
22987 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22988 N_("use -mcpu=strongarm1110")},
22989 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22990 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22991 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22993 /* Architecture variants -- don't add any more to this list either. */
22994 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22995 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22996 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22997 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22998 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22999 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23000 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23001 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23002 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23003 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23004 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23005 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23006 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23007 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23008 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23009 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23010 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23011 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23013 /* Floating point variants -- don't add any more to this list either. */
23014 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23015 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23016 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23017 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23018 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23020 {NULL, NULL, ARM_ARCH_NONE, NULL}
23023 struct arm_cpu_option_table
23027 const arm_feature_set value;
23028 /* For some CPUs we assume an FPU unless the user explicitly sets
23030 const arm_feature_set default_fpu;
23031 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23033 const char *canonical_name;
23036 /* This list should, at a minimum, contain all the cpu names
23037 recognized by GCC. */
23038 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23039 static const struct arm_cpu_option_table arm_cpus[] =
23041 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23042 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23043 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23044 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23045 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23046 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23047 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23048 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23049 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23050 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23051 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23052 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23053 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23054 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23055 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23056 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23057 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23058 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23059 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23060 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23061 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23062 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23063 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23064 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23065 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23066 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23067 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23068 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23069 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23070 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23071 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23072 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23073 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23074 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23075 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23076 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23077 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23078 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23079 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23080 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23081 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23082 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23083 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23084 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23085 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23086 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23087 /* For V5 or later processors we default to using VFP; but the user
23088 should really set the FPU type explicitly. */
23089 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23090 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23091 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23092 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23093 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23094 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23095 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23096 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23097 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23098 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23099 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23100 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23101 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23102 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23103 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23104 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23105 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23106 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23107 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23108 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23110 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23111 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23112 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23113 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23114 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23115 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23116 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23117 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23118 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23120 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23121 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23122 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23123 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23124 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23125 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23126 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23127 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23128 FPU_NONE, "Cortex-A5"),
23129 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23130 FPU_ARCH_NEON_VFP_V4,
23132 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23133 ARM_FEATURE (0, FPU_VFP_V3
23134 | FPU_NEON_EXT_V1),
23136 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23137 ARM_FEATURE (0, FPU_VFP_V3
23138 | FPU_NEON_EXT_V1),
23140 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23141 FPU_ARCH_NEON_VFP_V4,
23143 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23144 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23146 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23147 FPU_NONE, "Cortex-R5"),
23148 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23149 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23150 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23151 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23152 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23153 /* ??? XSCALE is really an architecture. */
23154 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23155 /* ??? iwmmxt is not a processor. */
23156 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23157 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23158 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23160 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23163 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23167 struct arm_arch_option_table
23171 const arm_feature_set value;
23172 const arm_feature_set default_fpu;
23175 /* This list should, at a minimum, contain all the architecture names
23176 recognized by GCC. */
23177 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23178 static const struct arm_arch_option_table arm_archs[] =
23180 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23181 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23182 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23183 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23184 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23185 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23186 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23187 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23188 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23189 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23190 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23191 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23192 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23193 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23194 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23195 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23196 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23197 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23198 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23199 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23200 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23201 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23202 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23203 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23204 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23205 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23206 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23207 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23208 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23209 /* The official spelling of the ARMv7 profile variants is the dashed form.
23210 Accept the non-dashed form for compatibility with old toolchains. */
23211 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23212 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23213 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23214 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23215 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23216 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23217 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23218 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23219 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23220 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23221 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23222 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23224 #undef ARM_ARCH_OPT
23226 /* ISA extensions in the co-processor and main instruction set space. */
23227 struct arm_option_extension_value_table
23231 const arm_feature_set value;
23232 const arm_feature_set allowed_archs;
23235 /* The following table must be in alphabetical order with a NULL last entry.
23237 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23238 static const struct arm_option_extension_value_table arm_extensions[] =
23240 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23241 ARM_FEATURE (ARM_EXT_V8, 0)),
23242 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23243 ARM_FEATURE (ARM_EXT_V8, 0)),
23244 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23245 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23246 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23247 ARM_EXT_OPT ("iwmmxt2",
23248 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23249 ARM_EXT_OPT ("maverick",
23250 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23251 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23252 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23253 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23254 ARM_FEATURE (ARM_EXT_V8, 0)),
23255 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23256 ARM_FEATURE (ARM_EXT_V6M, 0)),
23257 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23258 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23259 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23261 ARM_FEATURE (ARM_EXT_V7A, 0)),
23262 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23263 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23267 /* ISA floating-point and Advanced SIMD extensions. */
23268 struct arm_option_fpu_value_table
23271 const arm_feature_set value;
23274 /* This list should, at a minimum, contain all the fpu names
23275 recognized by GCC. */
23276 static const struct arm_option_fpu_value_table arm_fpus[] =
23278 {"softfpa", FPU_NONE},
23279 {"fpe", FPU_ARCH_FPE},
23280 {"fpe2", FPU_ARCH_FPE},
23281 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23282 {"fpa", FPU_ARCH_FPA},
23283 {"fpa10", FPU_ARCH_FPA},
23284 {"fpa11", FPU_ARCH_FPA},
23285 {"arm7500fe", FPU_ARCH_FPA},
23286 {"softvfp", FPU_ARCH_VFP},
23287 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23288 {"vfp", FPU_ARCH_VFP_V2},
23289 {"vfp9", FPU_ARCH_VFP_V2},
23290 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23291 {"vfp10", FPU_ARCH_VFP_V2},
23292 {"vfp10-r0", FPU_ARCH_VFP_V1},
23293 {"vfpxd", FPU_ARCH_VFP_V1xD},
23294 {"vfpv2", FPU_ARCH_VFP_V2},
23295 {"vfpv3", FPU_ARCH_VFP_V3},
23296 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23297 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23298 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23299 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23300 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23301 {"arm1020t", FPU_ARCH_VFP_V1},
23302 {"arm1020e", FPU_ARCH_VFP_V2},
23303 {"arm1136jfs", FPU_ARCH_VFP_V2},
23304 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23305 {"maverick", FPU_ARCH_MAVERICK},
23306 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23307 {"neon-fp16", FPU_ARCH_NEON_FP16},
23308 {"vfpv4", FPU_ARCH_VFP_V4},
23309 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23310 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23311 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23312 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
23313 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
23314 {"crypto-neon-fp-armv8",
23315 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
23316 {NULL, ARM_ARCH_NONE}
23319 struct arm_option_value_table
23325 static const struct arm_option_value_table arm_float_abis[] =
23327 {"hard", ARM_FLOAT_ABI_HARD},
23328 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23329 {"soft", ARM_FLOAT_ABI_SOFT},
23334 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23335 static const struct arm_option_value_table arm_eabis[] =
23337 {"gnu", EF_ARM_EABI_UNKNOWN},
23338 {"4", EF_ARM_EABI_VER4},
23339 {"5", EF_ARM_EABI_VER5},
23344 struct arm_long_option_table
23346 char * option; /* Substring to match. */
23347 char * help; /* Help information. */
23348 int (* func) (char * subopt); /* Function to decode sub-option. */
23349 char * deprecated; /* If non-null, print this message. */
23353 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23355 arm_feature_set *ext_set = (arm_feature_set *)
23356 xmalloc (sizeof (arm_feature_set));
23358 /* We insist on extensions being specified in alphabetical order, and with
23359 extensions being added before being removed. We achieve this by having
23360 the global ARM_EXTENSIONS table in alphabetical order, and using the
23361 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23362 or removing it (0) and only allowing it to change in the order
23364 const struct arm_option_extension_value_table * opt = NULL;
23365 int adding_value = -1;
23367 /* Copy the feature set, so that we can modify it. */
23368 *ext_set = **opt_p;
23371 while (str != NULL && *str != 0)
23378 as_bad (_("invalid architectural extension"));
23383 ext = strchr (str, '+');
23388 len = strlen (str);
23390 if (len >= 2 && strncmp (str, "no", 2) == 0)
23392 if (adding_value != 0)
23395 opt = arm_extensions;
23403 if (adding_value == -1)
23406 opt = arm_extensions;
23408 else if (adding_value != 1)
23410 as_bad (_("must specify extensions to add before specifying "
23411 "those to remove"));
23418 as_bad (_("missing architectural extension"));
23422 gas_assert (adding_value != -1);
23423 gas_assert (opt != NULL);
23425 /* Scan over the options table trying to find an exact match. */
23426 for (; opt->name != NULL; opt++)
23427 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23429 /* Check we can apply the extension to this architecture. */
23430 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23432 as_bad (_("extension does not apply to the base architecture"));
23436 /* Add or remove the extension. */
23438 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23440 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23445 if (opt->name == NULL)
23447 /* Did we fail to find an extension because it wasn't specified in
23448 alphabetical order, or because it does not exist? */
23450 for (opt = arm_extensions; opt->name != NULL; opt++)
23451 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23454 if (opt->name == NULL)
23455 as_bad (_("unknown architectural extension `%s'"), str);
23457 as_bad (_("architectural extensions must be specified in "
23458 "alphabetical order"));
23464 /* We should skip the extension we've just matched the next time
23476 arm_parse_cpu (char *str)
23478 const struct arm_cpu_option_table *opt;
23479 char *ext = strchr (str, '+');
23485 len = strlen (str);
23489 as_bad (_("missing cpu name `%s'"), str);
23493 for (opt = arm_cpus; opt->name != NULL; opt++)
23494 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23496 mcpu_cpu_opt = &opt->value;
23497 mcpu_fpu_opt = &opt->default_fpu;
23498 if (opt->canonical_name)
23499 strcpy (selected_cpu_name, opt->canonical_name);
23504 for (i = 0; i < len; i++)
23505 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23506 selected_cpu_name[i] = 0;
23510 return arm_parse_extension (ext, &mcpu_cpu_opt);
23515 as_bad (_("unknown cpu `%s'"), str);
23520 arm_parse_arch (char *str)
23522 const struct arm_arch_option_table *opt;
23523 char *ext = strchr (str, '+');
23529 len = strlen (str);
23533 as_bad (_("missing architecture name `%s'"), str);
23537 for (opt = arm_archs; opt->name != NULL; opt++)
23538 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23540 march_cpu_opt = &opt->value;
23541 march_fpu_opt = &opt->default_fpu;
23542 strcpy (selected_cpu_name, opt->name);
23545 return arm_parse_extension (ext, &march_cpu_opt);
23550 as_bad (_("unknown architecture `%s'\n"), str);
23555 arm_parse_fpu (char * str)
23557 const struct arm_option_fpu_value_table * opt;
23559 for (opt = arm_fpus; opt->name != NULL; opt++)
23560 if (streq (opt->name, str))
23562 mfpu_opt = &opt->value;
23566 as_bad (_("unknown floating point format `%s'\n"), str);
23571 arm_parse_float_abi (char * str)
23573 const struct arm_option_value_table * opt;
23575 for (opt = arm_float_abis; opt->name != NULL; opt++)
23576 if (streq (opt->name, str))
23578 mfloat_abi_opt = opt->value;
23582 as_bad (_("unknown floating point abi `%s'\n"), str);
23588 arm_parse_eabi (char * str)
23590 const struct arm_option_value_table *opt;
23592 for (opt = arm_eabis; opt->name != NULL; opt++)
23593 if (streq (opt->name, str))
23595 meabi_flags = opt->value;
23598 as_bad (_("unknown EABI `%s'\n"), str);
23604 arm_parse_it_mode (char * str)
23606 bfd_boolean ret = TRUE;
23608 if (streq ("arm", str))
23609 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23610 else if (streq ("thumb", str))
23611 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23612 else if (streq ("always", str))
23613 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23614 else if (streq ("never", str))
23615 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23618 as_bad (_("unknown implicit IT mode `%s', should be "\
23619 "arm, thumb, always, or never."), str);
23626 struct arm_long_option_table arm_long_opts[] =
23628 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23629 arm_parse_cpu, NULL},
23630 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23631 arm_parse_arch, NULL},
23632 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23633 arm_parse_fpu, NULL},
23634 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23635 arm_parse_float_abi, NULL},
23637 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23638 arm_parse_eabi, NULL},
23640 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23641 arm_parse_it_mode, NULL},
23642 {NULL, NULL, 0, NULL}
23646 md_parse_option (int c, char * arg)
23648 struct arm_option_table *opt;
23649 const struct arm_legacy_option_table *fopt;
23650 struct arm_long_option_table *lopt;
23656 target_big_endian = 1;
23662 target_big_endian = 0;
23666 case OPTION_FIX_V4BX:
23671 /* Listing option. Just ignore these, we don't support additional
23676 for (opt = arm_opts; opt->option != NULL; opt++)
23678 if (c == opt->option[0]
23679 && ((arg == NULL && opt->option[1] == 0)
23680 || streq (arg, opt->option + 1)))
23682 /* If the option is deprecated, tell the user. */
23683 if (warn_on_deprecated && opt->deprecated != NULL)
23684 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23685 arg ? arg : "", _(opt->deprecated));
23687 if (opt->var != NULL)
23688 *opt->var = opt->value;
23694 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23696 if (c == fopt->option[0]
23697 && ((arg == NULL && fopt->option[1] == 0)
23698 || streq (arg, fopt->option + 1)))
23700 /* If the option is deprecated, tell the user. */
23701 if (warn_on_deprecated && fopt->deprecated != NULL)
23702 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23703 arg ? arg : "", _(fopt->deprecated));
23705 if (fopt->var != NULL)
23706 *fopt->var = &fopt->value;
23712 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23714 /* These options are expected to have an argument. */
23715 if (c == lopt->option[0]
23717 && strncmp (arg, lopt->option + 1,
23718 strlen (lopt->option + 1)) == 0)
23720 /* If the option is deprecated, tell the user. */
23721 if (warn_on_deprecated && lopt->deprecated != NULL)
23722 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23723 _(lopt->deprecated));
23725 /* Call the sup-option parser. */
23726 return lopt->func (arg + strlen (lopt->option) - 1);
23737 md_show_usage (FILE * fp)
23739 struct arm_option_table *opt;
23740 struct arm_long_option_table *lopt;
23742 fprintf (fp, _(" ARM-specific assembler options:\n"));
23744 for (opt = arm_opts; opt->option != NULL; opt++)
23745 if (opt->help != NULL)
23746 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23748 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23749 if (lopt->help != NULL)
23750 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23754 -EB assemble code for a big-endian cpu\n"));
23759 -EL assemble code for a little-endian cpu\n"));
23763 --fix-v4bx Allow BX in ARMv4 code\n"));
23771 arm_feature_set flags;
23772 } cpu_arch_ver_table;
23774 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23775 least features first. */
23776 static const cpu_arch_ver_table cpu_arch_ver[] =
23782 {4, ARM_ARCH_V5TE},
23783 {5, ARM_ARCH_V5TEJ},
23787 {11, ARM_ARCH_V6M},
23788 {12, ARM_ARCH_V6SM},
23789 {8, ARM_ARCH_V6T2},
23790 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
23791 {10, ARM_ARCH_V7R},
23792 {10, ARM_ARCH_V7M},
23793 {14, ARM_ARCH_V8A},
23797 /* Set an attribute if it has not already been set by the user. */
23799 aeabi_set_attribute_int (int tag, int value)
23802 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23803 || !attributes_set_explicitly[tag])
23804 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23808 aeabi_set_attribute_string (int tag, const char *value)
23811 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23812 || !attributes_set_explicitly[tag])
23813 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23816 /* Set the public EABI object attributes. */
23818 aeabi_set_public_attributes (void)
23823 int fp16_optional = 0;
23824 arm_feature_set flags;
23825 arm_feature_set tmp;
23826 const cpu_arch_ver_table *p;
23828 /* Choose the architecture based on the capabilities of the requested cpu
23829 (if any) and/or the instructions actually used. */
23830 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23831 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23832 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23834 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23835 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23837 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23838 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23840 /* Allow the user to override the reported architecture. */
23843 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23844 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23847 /* We need to make sure that the attributes do not identify us as v6S-M
23848 when the only v6S-M feature in use is the Operating System Extensions. */
23849 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23850 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23851 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23855 for (p = cpu_arch_ver; p->val; p++)
23857 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23860 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23864 /* The table lookup above finds the last architecture to contribute
23865 a new feature. Unfortunately, Tag13 is a subset of the union of
23866 v6T2 and v7-M, so it is never seen as contributing a new feature.
23867 We can not search for the last entry which is entirely used,
23868 because if no CPU is specified we build up only those flags
23869 actually used. Perhaps we should separate out the specified
23870 and implicit cases. Avoid taking this path for -march=all by
23871 checking for contradictory v7-A / v7-M features. */
23873 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23874 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23875 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23878 /* Tag_CPU_name. */
23879 if (selected_cpu_name[0])
23883 q = selected_cpu_name;
23884 if (strncmp (q, "armv", 4) == 0)
23889 for (i = 0; q[i]; i++)
23890 q[i] = TOUPPER (q[i]);
23892 aeabi_set_attribute_string (Tag_CPU_name, q);
23895 /* Tag_CPU_arch. */
23896 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23898 /* Tag_CPU_arch_profile. */
23899 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23901 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23903 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23908 if (profile != '\0')
23909 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
23911 /* Tag_ARM_ISA_use. */
23912 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23914 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23916 /* Tag_THUMB_ISA_use. */
23917 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23919 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23920 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23922 /* Tag_VFP_arch. */
23923 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
23924 aeabi_set_attribute_int (Tag_VFP_arch, 7);
23925 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23926 aeabi_set_attribute_int (Tag_VFP_arch,
23927 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23929 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23932 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23934 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23936 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23939 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23940 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23941 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23942 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23943 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23945 /* Tag_ABI_HardFP_use. */
23946 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23947 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23948 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23950 /* Tag_WMMX_arch. */
23951 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23952 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23953 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23954 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23956 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23957 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
23958 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
23959 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23961 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
23963 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
23967 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
23972 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23973 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
23974 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23978 We set Tag_DIV_use to two when integer divide instructions have been used
23979 in ARM state, or when Thumb integer divide instructions have been used,
23980 but we have no architecture profile set, nor have we any ARM instructions.
23982 For ARMv8 we set the tag to 0 as integer divide is implied by the base
23985 For new architectures we will have to check these tests. */
23986 gas_assert (arch <= TAG_CPU_ARCH_V8);
23987 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
23988 aeabi_set_attribute_int (Tag_DIV_use, 0);
23989 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
23990 || (profile == '\0'
23991 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
23992 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
23993 aeabi_set_attribute_int (Tag_DIV_use, 2);
23995 /* Tag_MP_extension_use. */
23996 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23997 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23999 /* Tag Virtualization_use. */
24000 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24002 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24005 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24008 /* Add the default contents for the .ARM.attributes section. */
24012 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24015 aeabi_set_public_attributes ();
24017 #endif /* OBJ_ELF */
24020 /* Parse a .cpu directive. */
24023 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24025 const struct arm_cpu_option_table *opt;
24029 name = input_line_pointer;
24030 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24031 input_line_pointer++;
24032 saved_char = *input_line_pointer;
24033 *input_line_pointer = 0;
24035 /* Skip the first "all" entry. */
24036 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24037 if (streq (opt->name, name))
24039 mcpu_cpu_opt = &opt->value;
24040 selected_cpu = opt->value;
24041 if (opt->canonical_name)
24042 strcpy (selected_cpu_name, opt->canonical_name);
24046 for (i = 0; opt->name[i]; i++)
24047 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24049 selected_cpu_name[i] = 0;
24051 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24052 *input_line_pointer = saved_char;
24053 demand_empty_rest_of_line ();
24056 as_bad (_("unknown cpu `%s'"), name);
24057 *input_line_pointer = saved_char;
24058 ignore_rest_of_line ();
24062 /* Parse a .arch directive. */
24065 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24067 const struct arm_arch_option_table *opt;
24071 name = input_line_pointer;
24072 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24073 input_line_pointer++;
24074 saved_char = *input_line_pointer;
24075 *input_line_pointer = 0;
24077 /* Skip the first "all" entry. */
24078 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24079 if (streq (opt->name, name))
24081 mcpu_cpu_opt = &opt->value;
24082 selected_cpu = opt->value;
24083 strcpy (selected_cpu_name, opt->name);
24084 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24085 *input_line_pointer = saved_char;
24086 demand_empty_rest_of_line ();
24090 as_bad (_("unknown architecture `%s'\n"), name);
24091 *input_line_pointer = saved_char;
24092 ignore_rest_of_line ();
24096 /* Parse a .object_arch directive. */
24099 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24101 const struct arm_arch_option_table *opt;
24105 name = input_line_pointer;
24106 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24107 input_line_pointer++;
24108 saved_char = *input_line_pointer;
24109 *input_line_pointer = 0;
24111 /* Skip the first "all" entry. */
24112 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24113 if (streq (opt->name, name))
24115 object_arch = &opt->value;
24116 *input_line_pointer = saved_char;
24117 demand_empty_rest_of_line ();
24121 as_bad (_("unknown architecture `%s'\n"), name);
24122 *input_line_pointer = saved_char;
24123 ignore_rest_of_line ();
24126 /* Parse a .arch_extension directive. */
24129 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24131 const struct arm_option_extension_value_table *opt;
24134 int adding_value = 1;
24136 name = input_line_pointer;
24137 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24138 input_line_pointer++;
24139 saved_char = *input_line_pointer;
24140 *input_line_pointer = 0;
24142 if (strlen (name) >= 2
24143 && strncmp (name, "no", 2) == 0)
24149 for (opt = arm_extensions; opt->name != NULL; opt++)
24150 if (streq (opt->name, name))
24152 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24154 as_bad (_("architectural extension `%s' is not allowed for the "
24155 "current base architecture"), name);
24160 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24162 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24164 mcpu_cpu_opt = &selected_cpu;
24165 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24166 *input_line_pointer = saved_char;
24167 demand_empty_rest_of_line ();
24171 if (opt->name == NULL)
24172 as_bad (_("unknown architecture `%s'\n"), name);
24174 *input_line_pointer = saved_char;
24175 ignore_rest_of_line ();
24178 /* Parse a .fpu directive. */
24181 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24183 const struct arm_option_fpu_value_table *opt;
24187 name = input_line_pointer;
24188 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24189 input_line_pointer++;
24190 saved_char = *input_line_pointer;
24191 *input_line_pointer = 0;
24193 for (opt = arm_fpus; opt->name != NULL; opt++)
24194 if (streq (opt->name, name))
24196 mfpu_opt = &opt->value;
24197 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24198 *input_line_pointer = saved_char;
24199 demand_empty_rest_of_line ();
24203 as_bad (_("unknown floating point format `%s'\n"), name);
24204 *input_line_pointer = saved_char;
24205 ignore_rest_of_line ();
24208 /* Copy symbol information. */
24211 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24213 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24217 /* Given a symbolic attribute NAME, return the proper integer value.
24218 Returns -1 if the attribute is not known. */
24221 arm_convert_symbolic_attribute (const char *name)
24223 static const struct
24228 attribute_table[] =
24230 /* When you modify this table you should
24231 also modify the list in doc/c-arm.texi. */
24232 #define T(tag) {#tag, tag}
24233 T (Tag_CPU_raw_name),
24236 T (Tag_CPU_arch_profile),
24237 T (Tag_ARM_ISA_use),
24238 T (Tag_THUMB_ISA_use),
24242 T (Tag_Advanced_SIMD_arch),
24243 T (Tag_PCS_config),
24244 T (Tag_ABI_PCS_R9_use),
24245 T (Tag_ABI_PCS_RW_data),
24246 T (Tag_ABI_PCS_RO_data),
24247 T (Tag_ABI_PCS_GOT_use),
24248 T (Tag_ABI_PCS_wchar_t),
24249 T (Tag_ABI_FP_rounding),
24250 T (Tag_ABI_FP_denormal),
24251 T (Tag_ABI_FP_exceptions),
24252 T (Tag_ABI_FP_user_exceptions),
24253 T (Tag_ABI_FP_number_model),
24254 T (Tag_ABI_align_needed),
24255 T (Tag_ABI_align8_needed),
24256 T (Tag_ABI_align_preserved),
24257 T (Tag_ABI_align8_preserved),
24258 T (Tag_ABI_enum_size),
24259 T (Tag_ABI_HardFP_use),
24260 T (Tag_ABI_VFP_args),
24261 T (Tag_ABI_WMMX_args),
24262 T (Tag_ABI_optimization_goals),
24263 T (Tag_ABI_FP_optimization_goals),
24264 T (Tag_compatibility),
24265 T (Tag_CPU_unaligned_access),
24266 T (Tag_FP_HP_extension),
24267 T (Tag_VFP_HP_extension),
24268 T (Tag_ABI_FP_16bit_format),
24269 T (Tag_MPextension_use),
24271 T (Tag_nodefaults),
24272 T (Tag_also_compatible_with),
24273 T (Tag_conformance),
24275 T (Tag_Virtualization_use),
24276 /* We deliberately do not include Tag_MPextension_use_legacy. */
24284 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24285 if (streq (name, attribute_table[i].name))
24286 return attribute_table[i].tag;
24292 /* Apply sym value for relocations only in the case that
24293 they are for local symbols and you have the respective
24294 architectural feature for blx and simple switches. */
24296 arm_apply_sym_value (struct fix * fixP)
24299 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24300 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24302 switch (fixP->fx_r_type)
24304 case BFD_RELOC_ARM_PCREL_BLX:
24305 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24306 if (ARM_IS_FUNC (fixP->fx_addsy))
24310 case BFD_RELOC_ARM_PCREL_CALL:
24311 case BFD_RELOC_THUMB_PCREL_BLX:
24312 if (THUMB_IS_FUNC (fixP->fx_addsy))
24323 #endif /* OBJ_ELF */