1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld. */
327 const char arm_symbol_chars[] = "#[]";
342 enum neon_el_type type;
346 #define NEON_MAX_TYPE_ELS 4
350 struct neon_type_el el[NEON_MAX_TYPE_ELS];
354 enum it_instruction_type
359 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
360 if inside, should be the last one. */
361 NEUTRAL_IT_INSN, /* This could be either inside or outside,
362 i.e. BKPT and NOP. */
363 IT_INSN /* The IT insn has been parsed. */
366 /* The maximum number of operands we need. */
367 #define ARM_IT_MAX_OPERANDS 6
372 unsigned long instruction;
376 /* "uncond_value" is set to the value in place of the conditional field in
377 unconditional versions of the instruction, or -1 if nothing is
380 struct neon_type vectype;
381 /* This does not indicate an actual NEON instruction, only that
382 the mnemonic accepts neon-style type suffixes. */
384 /* Set to the opcode if the instruction needs relaxation.
385 Zero if the instruction is not relaxed. */
389 bfd_reloc_code_real_type type;
394 enum it_instruction_type it_insn_type;
400 struct neon_type_el vectype;
401 unsigned present : 1; /* Operand present. */
402 unsigned isreg : 1; /* Operand was a register. */
403 unsigned immisreg : 1; /* .imm field is a second register. */
404 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
405 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
406 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
407 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
408 instructions. This allows us to disambiguate ARM <-> vector insns. */
409 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
410 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
411 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
412 unsigned issingle : 1; /* Operand is VFP single-precision register. */
413 unsigned hasreloc : 1; /* Operand has relocation suffix. */
414 unsigned writeback : 1; /* Operand has trailing ! */
415 unsigned preind : 1; /* Preindexed address. */
416 unsigned postind : 1; /* Postindexed address. */
417 unsigned negative : 1; /* Index register was negated. */
418 unsigned shifted : 1; /* Shift applied to operation. */
419 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
420 } operands[ARM_IT_MAX_OPERANDS];
423 static struct arm_it inst;
425 #define NUM_FLOAT_VALS 8
427 const char * fp_const[] =
429 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
432 /* Number of littlenums required to hold an extended precision number. */
433 #define MAX_LITTLENUMS 6
435 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
445 #define CP_T_X 0x00008000
446 #define CP_T_Y 0x00400000
448 #define CONDS_BIT 0x00100000
449 #define LOAD_BIT 0x00100000
451 #define DOUBLE_LOAD_FLAG 0x00000001
455 const char * template_name;
459 #define COND_ALWAYS 0xE
463 const char * template_name;
467 struct asm_barrier_opt
469 const char * template_name;
471 const arm_feature_set arch;
474 /* The bit that distinguishes CPSR and SPSR. */
475 #define SPSR_BIT (1 << 22)
477 /* The individual PSR flag bits. */
478 #define PSR_c (1 << 16)
479 #define PSR_x (1 << 17)
480 #define PSR_s (1 << 18)
481 #define PSR_f (1 << 19)
486 bfd_reloc_code_real_type reloc;
491 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
492 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
497 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
500 /* Bits for DEFINED field in neon_typed_alias. */
501 #define NTA_HASTYPE 1
502 #define NTA_HASINDEX 2
504 struct neon_typed_alias
506 unsigned char defined;
508 struct neon_type_el eltype;
511 /* ARM register categories. This includes coprocessor numbers and various
512 architecture extensions' registers. */
539 /* Structure for a hash table entry for a register.
540 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
541 information which states whether a vector type or index is specified (for a
542 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
548 unsigned char builtin;
549 struct neon_typed_alias * neon;
552 /* Diagnostics used when we don't get a register of the expected type. */
553 const char * const reg_expected_msgs[] =
555 N_("ARM register expected"),
556 N_("bad or missing co-processor number"),
557 N_("co-processor register expected"),
558 N_("FPA register expected"),
559 N_("VFP single precision register expected"),
560 N_("VFP/Neon double precision register expected"),
561 N_("Neon quad precision register expected"),
562 N_("VFP single or double precision register expected"),
563 N_("Neon double or quad precision register expected"),
564 N_("VFP single, double or Neon quad precision register expected"),
565 N_("VFP system register expected"),
566 N_("Maverick MVF register expected"),
567 N_("Maverick MVD register expected"),
568 N_("Maverick MVFX register expected"),
569 N_("Maverick MVDX register expected"),
570 N_("Maverick MVAX register expected"),
571 N_("Maverick DSPSC register expected"),
572 N_("iWMMXt data register expected"),
573 N_("iWMMXt control register expected"),
574 N_("iWMMXt scalar register expected"),
575 N_("XScale accumulator register expected"),
578 /* Some well known registers that we refer to directly elsewhere. */
584 /* ARM instructions take 4bytes in the object file, Thumb instructions
590 /* Basic string to match. */
591 const char * template_name;
593 /* Parameters to instruction. */
594 unsigned int operands[8];
596 /* Conditional tag - see opcode_lookup. */
597 unsigned int tag : 4;
599 /* Basic instruction code. */
600 unsigned int avalue : 28;
602 /* Thumb-format instruction code. */
605 /* Which architecture variant provides this instruction. */
606 const arm_feature_set * avariant;
607 const arm_feature_set * tvariant;
609 /* Function to call to encode instruction in ARM format. */
610 void (* aencode) (void);
612 /* Function to call to encode instruction in Thumb format. */
613 void (* tencode) (void);
616 /* Defines for various bits that we will want to toggle. */
617 #define INST_IMMEDIATE 0x02000000
618 #define OFFSET_REG 0x02000000
619 #define HWOFFSET_IMM 0x00400000
620 #define SHIFT_BY_REG 0x00000010
621 #define PRE_INDEX 0x01000000
622 #define INDEX_UP 0x00800000
623 #define WRITE_BACK 0x00200000
624 #define LDM_TYPE_2_OR_3 0x00400000
625 #define CPSI_MMOD 0x00020000
627 #define LITERAL_MASK 0xf000f000
628 #define OPCODE_MASK 0xfe1fffff
629 #define V4_STR_BIT 0x00000020
631 #define T2_SUBS_PC_LR 0xf3de8f00
633 #define DATA_OP_SHIFT 21
635 #define T2_OPCODE_MASK 0xfe1fffff
636 #define T2_DATA_OP_SHIFT 21
638 #define A_COND_MASK 0xf0000000
639 #define A_PUSH_POP_OP_MASK 0x0fff0000
641 /* Opcodes for pushing/poping registers to/from the stack. */
642 #define A1_OPCODE_PUSH 0x092d0000
643 #define A2_OPCODE_PUSH 0x052d0004
644 #define A2_OPCODE_POP 0x049d0004
646 /* Codes to distinguish the arithmetic instructions. */
657 #define OPCODE_CMP 10
658 #define OPCODE_CMN 11
659 #define OPCODE_ORR 12
660 #define OPCODE_MOV 13
661 #define OPCODE_BIC 14
662 #define OPCODE_MVN 15
664 #define T2_OPCODE_AND 0
665 #define T2_OPCODE_BIC 1
666 #define T2_OPCODE_ORR 2
667 #define T2_OPCODE_ORN 3
668 #define T2_OPCODE_EOR 4
669 #define T2_OPCODE_ADD 8
670 #define T2_OPCODE_ADC 10
671 #define T2_OPCODE_SBC 11
672 #define T2_OPCODE_SUB 13
673 #define T2_OPCODE_RSB 14
675 #define T_OPCODE_MUL 0x4340
676 #define T_OPCODE_TST 0x4200
677 #define T_OPCODE_CMN 0x42c0
678 #define T_OPCODE_NEG 0x4240
679 #define T_OPCODE_MVN 0x43c0
681 #define T_OPCODE_ADD_R3 0x1800
682 #define T_OPCODE_SUB_R3 0x1a00
683 #define T_OPCODE_ADD_HI 0x4400
684 #define T_OPCODE_ADD_ST 0xb000
685 #define T_OPCODE_SUB_ST 0xb080
686 #define T_OPCODE_ADD_SP 0xa800
687 #define T_OPCODE_ADD_PC 0xa000
688 #define T_OPCODE_ADD_I8 0x3000
689 #define T_OPCODE_SUB_I8 0x3800
690 #define T_OPCODE_ADD_I3 0x1c00
691 #define T_OPCODE_SUB_I3 0x1e00
693 #define T_OPCODE_ASR_R 0x4100
694 #define T_OPCODE_LSL_R 0x4080
695 #define T_OPCODE_LSR_R 0x40c0
696 #define T_OPCODE_ROR_R 0x41c0
697 #define T_OPCODE_ASR_I 0x1000
698 #define T_OPCODE_LSL_I 0x0000
699 #define T_OPCODE_LSR_I 0x0800
701 #define T_OPCODE_MOV_I8 0x2000
702 #define T_OPCODE_CMP_I8 0x2800
703 #define T_OPCODE_CMP_LR 0x4280
704 #define T_OPCODE_MOV_HR 0x4600
705 #define T_OPCODE_CMP_HR 0x4500
707 #define T_OPCODE_LDR_PC 0x4800
708 #define T_OPCODE_LDR_SP 0x9800
709 #define T_OPCODE_STR_SP 0x9000
710 #define T_OPCODE_LDR_IW 0x6800
711 #define T_OPCODE_STR_IW 0x6000
712 #define T_OPCODE_LDR_IH 0x8800
713 #define T_OPCODE_STR_IH 0x8000
714 #define T_OPCODE_LDR_IB 0x7800
715 #define T_OPCODE_STR_IB 0x7000
716 #define T_OPCODE_LDR_RW 0x5800
717 #define T_OPCODE_STR_RW 0x5000
718 #define T_OPCODE_LDR_RH 0x5a00
719 #define T_OPCODE_STR_RH 0x5200
720 #define T_OPCODE_LDR_RB 0x5c00
721 #define T_OPCODE_STR_RB 0x5400
723 #define T_OPCODE_PUSH 0xb400
724 #define T_OPCODE_POP 0xbc00
726 #define T_OPCODE_BRANCH 0xe000
728 #define THUMB_SIZE 2 /* Size of thumb instruction. */
729 #define THUMB_PP_PC_LR 0x0100
730 #define THUMB_LOAD_BIT 0x0800
731 #define THUMB2_LOAD_BIT 0x00100000
733 #define BAD_ARGS _("bad arguments to instruction")
734 #define BAD_SP _("r13 not allowed here")
735 #define BAD_PC _("r15 not allowed here")
736 #define BAD_COND _("instruction cannot be conditional")
737 #define BAD_OVERLAP _("registers may not be the same")
738 #define BAD_HIREG _("lo register required")
739 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
740 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
741 #define BAD_BRANCH _("branch must be last instruction in IT block")
742 #define BAD_NOT_IT _("instruction not allowed in IT block")
743 #define BAD_FPU _("selected FPU does not support instruction")
744 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
745 #define BAD_IT_COND _("incorrect condition in IT block")
746 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
747 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
748 #define BAD_PC_ADDRESSING \
749 _("cannot use register index with PC-relative addressing")
750 #define BAD_PC_WRITEBACK \
751 _("cannot use writeback with PC-relative addressing")
752 #define BAD_RANGE _("branch out of range")
754 static struct hash_control * arm_ops_hsh;
755 static struct hash_control * arm_cond_hsh;
756 static struct hash_control * arm_shift_hsh;
757 static struct hash_control * arm_psr_hsh;
758 static struct hash_control * arm_v7m_psr_hsh;
759 static struct hash_control * arm_reg_hsh;
760 static struct hash_control * arm_reloc_hsh;
761 static struct hash_control * arm_barrier_opt_hsh;
763 /* Stuff needed to resolve the label ambiguity
772 symbolS * last_label_seen;
773 static int label_is_thumb_function_name = FALSE;
775 /* Literal pool structure. Held on a per-section
776 and per-sub-section basis. */
778 #define MAX_LITERAL_POOL_SIZE 1024
779 typedef struct literal_pool
781 expressionS literals [MAX_LITERAL_POOL_SIZE];
782 unsigned int next_free_entry;
788 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
790 struct literal_pool * next;
793 /* Pointer to a linked list of literal pools. */
794 literal_pool * list_of_pools = NULL;
797 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
799 static struct current_it now_it;
803 now_it_compatible (int cond)
805 return (cond & ~1) == (now_it.cc & ~1);
809 conditional_insn (void)
811 return inst.cond != COND_ALWAYS;
814 static int in_it_block (void);
816 static int handle_it_state (void);
818 static void force_automatic_it_block_close (void);
820 static void it_fsm_post_encode (void);
822 #define set_it_insn_type(type) \
825 inst.it_insn_type = type; \
826 if (handle_it_state () == FAIL) \
831 #define set_it_insn_type_nonvoid(type, failret) \
834 inst.it_insn_type = type; \
835 if (handle_it_state () == FAIL) \
840 #define set_it_insn_type_last() \
843 if (inst.cond == COND_ALWAYS) \
844 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
846 set_it_insn_type (INSIDE_IT_LAST_INSN); \
852 /* This array holds the chars that always start a comment. If the
853 pre-processor is disabled, these aren't very useful. */
854 const char comment_chars[] = "@";
856 /* This array holds the chars that only start a comment at the beginning of
857 a line. If the line seems to have the form '# 123 filename'
858 .line and .file directives will appear in the pre-processed output. */
859 /* Note that input_file.c hand checks for '#' at the beginning of the
860 first line of the input file. This is because the compiler outputs
861 #NO_APP at the beginning of its output. */
862 /* Also note that comments like this one will always work. */
863 const char line_comment_chars[] = "#";
865 const char line_separator_chars[] = ";";
867 /* Chars that can be used to separate mant
868 from exp in floating point numbers. */
869 const char EXP_CHARS[] = "eE";
871 /* Chars that mean this number is a floating point constant. */
875 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
877 /* Prefix characters that indicate the start of an immediate
879 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
881 /* Separator character handling. */
883 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
886 skip_past_char (char ** str, char c)
897 #define skip_past_comma(str) skip_past_char (str, ',')
899 /* Arithmetic expressions (possibly involving symbols). */
901 /* Return TRUE if anything in the expression is a bignum. */
904 walk_no_bignums (symbolS * sp)
906 if (symbol_get_value_expression (sp)->X_op == O_big)
909 if (symbol_get_value_expression (sp)->X_add_symbol)
911 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
912 || (symbol_get_value_expression (sp)->X_op_symbol
913 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
919 static int in_my_get_expression = 0;
921 /* Third argument to my_get_expression. */
922 #define GE_NO_PREFIX 0
923 #define GE_IMM_PREFIX 1
924 #define GE_OPT_PREFIX 2
925 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
926 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
927 #define GE_OPT_PREFIX_BIG 3
930 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
935 /* In unified syntax, all prefixes are optional. */
937 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
942 case GE_NO_PREFIX: break;
944 if (!is_immediate_prefix (**str))
946 inst.error = _("immediate expression requires a # prefix");
952 case GE_OPT_PREFIX_BIG:
953 if (is_immediate_prefix (**str))
959 memset (ep, 0, sizeof (expressionS));
961 save_in = input_line_pointer;
962 input_line_pointer = *str;
963 in_my_get_expression = 1;
964 seg = expression (ep);
965 in_my_get_expression = 0;
967 if (ep->X_op == O_illegal || ep->X_op == O_absent)
969 /* We found a bad or missing expression in md_operand(). */
970 *str = input_line_pointer;
971 input_line_pointer = save_in;
972 if (inst.error == NULL)
973 inst.error = (ep->X_op == O_absent
974 ? _("missing expression") :_("bad expression"));
979 if (seg != absolute_section
980 && seg != text_section
981 && seg != data_section
982 && seg != bss_section
983 && seg != undefined_section)
985 inst.error = _("bad segment");
986 *str = input_line_pointer;
987 input_line_pointer = save_in;
994 /* Get rid of any bignums now, so that we don't generate an error for which
995 we can't establish a line number later on. Big numbers are never valid
996 in instructions, which is where this routine is always called. */
997 if (prefix_mode != GE_OPT_PREFIX_BIG
998 && (ep->X_op == O_big
1000 && (walk_no_bignums (ep->X_add_symbol)
1002 && walk_no_bignums (ep->X_op_symbol))))))
1004 inst.error = _("invalid constant");
1005 *str = input_line_pointer;
1006 input_line_pointer = save_in;
1010 *str = input_line_pointer;
1011 input_line_pointer = save_in;
1015 /* Turn a string in input_line_pointer into a floating point constant
1016 of type TYPE, and store the appropriate bytes in *LITP. The number
1017 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1018 returned, or NULL on OK.
1020 Note that fp constants aren't represent in the normal way on the ARM.
1021 In big endian mode, things are as expected. However, in little endian
1022 mode fp constants are big-endian word-wise, and little-endian byte-wise
1023 within the words. For example, (double) 1.1 in big endian mode is
1024 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1025 the byte sequence 99 99 f1 3f 9a 99 99 99.
1027 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1030 md_atof (int type, char * litP, int * sizeP)
1033 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1065 return _("Unrecognized or unsupported floating point constant");
1068 t = atof_ieee (input_line_pointer, type, words);
1070 input_line_pointer = t;
1071 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1073 if (target_big_endian)
1075 for (i = 0; i < prec; i++)
1077 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1078 litP += sizeof (LITTLENUM_TYPE);
1083 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1084 for (i = prec - 1; i >= 0; i--)
1086 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1087 litP += sizeof (LITTLENUM_TYPE);
1090 /* For a 4 byte float the order of elements in `words' is 1 0.
1091 For an 8 byte float the order is 1 0 3 2. */
1092 for (i = 0; i < prec; i += 2)
1094 md_number_to_chars (litP, (valueT) words[i + 1],
1095 sizeof (LITTLENUM_TYPE));
1096 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1097 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1098 litP += 2 * sizeof (LITTLENUM_TYPE);
1105 /* We handle all bad expressions here, so that we can report the faulty
1106 instruction in the error message. */
1108 md_operand (expressionS * exp)
1110 if (in_my_get_expression)
1111 exp->X_op = O_illegal;
1114 /* Immediate values. */
1116 /* Generic immediate-value read function for use in directives.
1117 Accepts anything that 'expression' can fold to a constant.
1118 *val receives the number. */
1121 immediate_for_directive (int *val)
1124 exp.X_op = O_illegal;
1126 if (is_immediate_prefix (*input_line_pointer))
1128 input_line_pointer++;
1132 if (exp.X_op != O_constant)
1134 as_bad (_("expected #constant"));
1135 ignore_rest_of_line ();
1138 *val = exp.X_add_number;
1143 /* Register parsing. */
1145 /* Generic register parser. CCP points to what should be the
1146 beginning of a register name. If it is indeed a valid register
1147 name, advance CCP over it and return the reg_entry structure;
1148 otherwise return NULL. Does not issue diagnostics. */
1150 static struct reg_entry *
1151 arm_reg_parse_multi (char **ccp)
1155 struct reg_entry *reg;
1157 #ifdef REGISTER_PREFIX
1158 if (*start != REGISTER_PREFIX)
1162 #ifdef OPTIONAL_REGISTER_PREFIX
1163 if (*start == OPTIONAL_REGISTER_PREFIX)
1168 if (!ISALPHA (*p) || !is_name_beginner (*p))
1173 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1175 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1185 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1186 enum arm_reg_type type)
1188 /* Alternative syntaxes are accepted for a few register classes. */
1195 /* Generic coprocessor register names are allowed for these. */
1196 if (reg && reg->type == REG_TYPE_CN)
1201 /* For backward compatibility, a bare number is valid here. */
1203 unsigned long processor = strtoul (start, ccp, 10);
1204 if (*ccp != start && processor <= 15)
1208 case REG_TYPE_MMXWC:
1209 /* WC includes WCG. ??? I'm not sure this is true for all
1210 instructions that take WC registers. */
1211 if (reg && reg->type == REG_TYPE_MMXWCG)
1222 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1223 return value is the register number or FAIL. */
1226 arm_reg_parse (char **ccp, enum arm_reg_type type)
1229 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1232 /* Do not allow a scalar (reg+index) to parse as a register. */
1233 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1236 if (reg && reg->type == type)
1239 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1246 /* Parse a Neon type specifier. *STR should point at the leading '.'
1247 character. Does no verification at this stage that the type fits the opcode
1254 Can all be legally parsed by this function.
1256 Fills in neon_type struct pointer with parsed information, and updates STR
1257 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1258 type, FAIL if not. */
1261 parse_neon_type (struct neon_type *type, char **str)
1268 while (type->elems < NEON_MAX_TYPE_ELS)
1270 enum neon_el_type thistype = NT_untyped;
1271 unsigned thissize = -1u;
1278 /* Just a size without an explicit type. */
1282 switch (TOLOWER (*ptr))
1284 case 'i': thistype = NT_integer; break;
1285 case 'f': thistype = NT_float; break;
1286 case 'p': thistype = NT_poly; break;
1287 case 's': thistype = NT_signed; break;
1288 case 'u': thistype = NT_unsigned; break;
1290 thistype = NT_float;
1295 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1301 /* .f is an abbreviation for .f32. */
1302 if (thistype == NT_float && !ISDIGIT (*ptr))
1307 thissize = strtoul (ptr, &ptr, 10);
1309 if (thissize != 8 && thissize != 16 && thissize != 32
1312 as_bad (_("bad size %d in type specifier"), thissize);
1320 type->el[type->elems].type = thistype;
1321 type->el[type->elems].size = thissize;
1326 /* Empty/missing type is not a successful parse. */
1327 if (type->elems == 0)
1335 /* Errors may be set multiple times during parsing or bit encoding
1336 (particularly in the Neon bits), but usually the earliest error which is set
1337 will be the most meaningful. Avoid overwriting it with later (cascading)
1338 errors by calling this function. */
1341 first_error (const char *err)
1347 /* Parse a single type, e.g. ".s32", leading period included. */
1349 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1352 struct neon_type optype;
1356 if (parse_neon_type (&optype, &str) == SUCCESS)
1358 if (optype.elems == 1)
1359 *vectype = optype.el[0];
1362 first_error (_("only one type should be specified for operand"));
1368 first_error (_("vector type expected"));
1380 /* Special meanings for indices (which have a range of 0-7), which will fit into
1383 #define NEON_ALL_LANES 15
1384 #define NEON_INTERLEAVE_LANES 14
1386 /* Parse either a register or a scalar, with an optional type. Return the
1387 register number, and optionally fill in the actual type of the register
1388 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1389 type/index information in *TYPEINFO. */
1392 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1393 enum arm_reg_type *rtype,
1394 struct neon_typed_alias *typeinfo)
1397 struct reg_entry *reg = arm_reg_parse_multi (&str);
1398 struct neon_typed_alias atype;
1399 struct neon_type_el parsetype;
1403 atype.eltype.type = NT_invtype;
1404 atype.eltype.size = -1;
1406 /* Try alternate syntax for some types of register. Note these are mutually
1407 exclusive with the Neon syntax extensions. */
1410 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1418 /* Undo polymorphism when a set of register types may be accepted. */
1419 if ((type == REG_TYPE_NDQ
1420 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1421 || (type == REG_TYPE_VFSD
1422 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1423 || (type == REG_TYPE_NSDQ
1424 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1425 || reg->type == REG_TYPE_NQ))
1426 || (type == REG_TYPE_MMXWC
1427 && (reg->type == REG_TYPE_MMXWCG)))
1428 type = (enum arm_reg_type) reg->type;
1430 if (type != reg->type)
1436 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1438 if ((atype.defined & NTA_HASTYPE) != 0)
1440 first_error (_("can't redefine type for operand"));
1443 atype.defined |= NTA_HASTYPE;
1444 atype.eltype = parsetype;
1447 if (skip_past_char (&str, '[') == SUCCESS)
1449 if (type != REG_TYPE_VFD)
1451 first_error (_("only D registers may be indexed"));
1455 if ((atype.defined & NTA_HASINDEX) != 0)
1457 first_error (_("can't change index for operand"));
1461 atype.defined |= NTA_HASINDEX;
1463 if (skip_past_char (&str, ']') == SUCCESS)
1464 atype.index = NEON_ALL_LANES;
1469 my_get_expression (&exp, &str, GE_NO_PREFIX);
1471 if (exp.X_op != O_constant)
1473 first_error (_("constant expression required"));
1477 if (skip_past_char (&str, ']') == FAIL)
1480 atype.index = exp.X_add_number;
1495 /* Like arm_reg_parse, but allow allow the following extra features:
1496 - If RTYPE is non-zero, return the (possibly restricted) type of the
1497 register (e.g. Neon double or quad reg when either has been requested).
1498 - If this is a Neon vector type with additional type information, fill
1499 in the struct pointed to by VECTYPE (if non-NULL).
1500 This function will fault on encountering a scalar. */
1503 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1504 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1506 struct neon_typed_alias atype;
1508 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1513 /* Do not allow regname(... to parse as a register. */
1517 /* Do not allow a scalar (reg+index) to parse as a register. */
1518 if ((atype.defined & NTA_HASINDEX) != 0)
1520 first_error (_("register operand expected, but got scalar"));
1525 *vectype = atype.eltype;
1532 #define NEON_SCALAR_REG(X) ((X) >> 4)
1533 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1535 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1536 have enough information to be able to do a good job bounds-checking. So, we
1537 just do easy checks here, and do further checks later. */
1540 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1544 struct neon_typed_alias atype;
1546 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1548 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1551 if (atype.index == NEON_ALL_LANES)
1553 first_error (_("scalar must have an index"));
1556 else if (atype.index >= 64 / elsize)
1558 first_error (_("scalar index out of range"));
1563 *type = atype.eltype;
1567 return reg * 16 + atype.index;
1570 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1573 parse_reg_list (char ** strp)
1575 char * str = * strp;
1579 /* We come back here if we get ranges concatenated by '+' or '|'. */
1594 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1596 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1606 first_error (_("bad range in register list"));
1610 for (i = cur_reg + 1; i < reg; i++)
1612 if (range & (1 << i))
1614 (_("Warning: duplicated register (r%d) in register list"),
1622 if (range & (1 << reg))
1623 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1625 else if (reg <= cur_reg)
1626 as_tsktsk (_("Warning: register range not in ascending order"));
1631 while (skip_past_comma (&str) != FAIL
1632 || (in_range = 1, *str++ == '-'));
1637 first_error (_("missing `}'"));
1645 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1648 if (exp.X_op == O_constant)
1650 if (exp.X_add_number
1651 != (exp.X_add_number & 0x0000ffff))
1653 inst.error = _("invalid register mask");
1657 if ((range & exp.X_add_number) != 0)
1659 int regno = range & exp.X_add_number;
1662 regno = (1 << regno) - 1;
1664 (_("Warning: duplicated register (r%d) in register list"),
1668 range |= exp.X_add_number;
1672 if (inst.reloc.type != 0)
1674 inst.error = _("expression too complex");
1678 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1679 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1680 inst.reloc.pc_rel = 0;
1684 if (*str == '|' || *str == '+')
1690 while (another_range);
1696 /* Types of registers in a list. */
1705 /* Parse a VFP register list. If the string is invalid return FAIL.
1706 Otherwise return the number of registers, and set PBASE to the first
1707 register. Parses registers of type ETYPE.
1708 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1709 - Q registers can be used to specify pairs of D registers
1710 - { } can be omitted from around a singleton register list
1711 FIXME: This is not implemented, as it would require backtracking in
1714 This could be done (the meaning isn't really ambiguous), but doesn't
1715 fit in well with the current parsing framework.
1716 - 32 D registers may be used (also true for VFPv3).
1717 FIXME: Types are ignored in these register lists, which is probably a
1721 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1726 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1730 unsigned long mask = 0;
1735 inst.error = _("expecting {");
1744 regtype = REG_TYPE_VFS;
1749 regtype = REG_TYPE_VFD;
1752 case REGLIST_NEON_D:
1753 regtype = REG_TYPE_NDQ;
1757 if (etype != REGLIST_VFP_S)
1759 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1760 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1764 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1767 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1774 base_reg = max_regs;
1778 int setmask = 1, addregs = 1;
1780 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1782 if (new_base == FAIL)
1784 first_error (_(reg_expected_msgs[regtype]));
1788 if (new_base >= max_regs)
1790 first_error (_("register out of range in list"));
1794 /* Note: a value of 2 * n is returned for the register Q<n>. */
1795 if (regtype == REG_TYPE_NQ)
1801 if (new_base < base_reg)
1802 base_reg = new_base;
1804 if (mask & (setmask << new_base))
1806 first_error (_("invalid register list"));
1810 if ((mask >> new_base) != 0 && ! warned)
1812 as_tsktsk (_("register list not in ascending order"));
1816 mask |= setmask << new_base;
1819 if (*str == '-') /* We have the start of a range expression */
1825 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1828 inst.error = gettext (reg_expected_msgs[regtype]);
1832 if (high_range >= max_regs)
1834 first_error (_("register out of range in list"));
1838 if (regtype == REG_TYPE_NQ)
1839 high_range = high_range + 1;
1841 if (high_range <= new_base)
1843 inst.error = _("register range not in ascending order");
1847 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1849 if (mask & (setmask << new_base))
1851 inst.error = _("invalid register list");
1855 mask |= setmask << new_base;
1860 while (skip_past_comma (&str) != FAIL);
1864 /* Sanity check -- should have raised a parse error above. */
1865 if (count == 0 || count > max_regs)
1870 /* Final test -- the registers must be consecutive. */
1872 for (i = 0; i < count; i++)
1874 if ((mask & (1u << i)) == 0)
1876 inst.error = _("non-contiguous register range");
1886 /* True if two alias types are the same. */
1889 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1897 if (a->defined != b->defined)
1900 if ((a->defined & NTA_HASTYPE) != 0
1901 && (a->eltype.type != b->eltype.type
1902 || a->eltype.size != b->eltype.size))
1905 if ((a->defined & NTA_HASINDEX) != 0
1906 && (a->index != b->index))
1912 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1913 The base register is put in *PBASE.
1914 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1916 The register stride (minus one) is put in bit 4 of the return value.
1917 Bits [6:5] encode the list length (minus one).
1918 The type of the list elements is put in *ELTYPE, if non-NULL. */
1920 #define NEON_LANE(X) ((X) & 0xf)
1921 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1922 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1925 parse_neon_el_struct_list (char **str, unsigned *pbase,
1926 struct neon_type_el *eltype)
1933 int leading_brace = 0;
1934 enum arm_reg_type rtype = REG_TYPE_NDQ;
1935 const char *const incr_error = _("register stride must be 1 or 2");
1936 const char *const type_error = _("mismatched element/structure types in list");
1937 struct neon_typed_alias firsttype;
1939 if (skip_past_char (&ptr, '{') == SUCCESS)
1944 struct neon_typed_alias atype;
1945 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1949 first_error (_(reg_expected_msgs[rtype]));
1956 if (rtype == REG_TYPE_NQ)
1962 else if (reg_incr == -1)
1964 reg_incr = getreg - base_reg;
1965 if (reg_incr < 1 || reg_incr > 2)
1967 first_error (_(incr_error));
1971 else if (getreg != base_reg + reg_incr * count)
1973 first_error (_(incr_error));
1977 if (! neon_alias_types_same (&atype, &firsttype))
1979 first_error (_(type_error));
1983 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1987 struct neon_typed_alias htype;
1988 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1990 lane = NEON_INTERLEAVE_LANES;
1991 else if (lane != NEON_INTERLEAVE_LANES)
1993 first_error (_(type_error));
1998 else if (reg_incr != 1)
2000 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2004 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2007 first_error (_(reg_expected_msgs[rtype]));
2010 if (! neon_alias_types_same (&htype, &firsttype))
2012 first_error (_(type_error));
2015 count += hireg + dregs - getreg;
2019 /* If we're using Q registers, we can't use [] or [n] syntax. */
2020 if (rtype == REG_TYPE_NQ)
2026 if ((atype.defined & NTA_HASINDEX) != 0)
2030 else if (lane != atype.index)
2032 first_error (_(type_error));
2036 else if (lane == -1)
2037 lane = NEON_INTERLEAVE_LANES;
2038 else if (lane != NEON_INTERLEAVE_LANES)
2040 first_error (_(type_error));
2045 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2047 /* No lane set by [x]. We must be interleaving structures. */
2049 lane = NEON_INTERLEAVE_LANES;
2052 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2053 || (count > 1 && reg_incr == -1))
2055 first_error (_("error parsing element/structure list"));
2059 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2061 first_error (_("expected }"));
2069 *eltype = firsttype.eltype;
2074 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2077 /* Parse an explicit relocation suffix on an expression. This is
2078 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2079 arm_reloc_hsh contains no entries, so this function can only
2080 succeed if there is no () after the word. Returns -1 on error,
2081 BFD_RELOC_UNUSED if there wasn't any suffix. */
2084 parse_reloc (char **str)
2086 struct reloc_entry *r;
2090 return BFD_RELOC_UNUSED;
2095 while (*q && *q != ')' && *q != ',')
2100 if ((r = (struct reloc_entry *)
2101 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2108 /* Directives: register aliases. */
2110 static struct reg_entry *
2111 insert_reg_alias (char *str, unsigned number, int type)
2113 struct reg_entry *new_reg;
2116 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2118 if (new_reg->builtin)
2119 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2121 /* Only warn about a redefinition if it's not defined as the
2123 else if (new_reg->number != number || new_reg->type != type)
2124 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2129 name = xstrdup (str);
2130 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2132 new_reg->name = name;
2133 new_reg->number = number;
2134 new_reg->type = type;
2135 new_reg->builtin = FALSE;
2136 new_reg->neon = NULL;
2138 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2145 insert_neon_reg_alias (char *str, int number, int type,
2146 struct neon_typed_alias *atype)
2148 struct reg_entry *reg = insert_reg_alias (str, number, type);
2152 first_error (_("attempt to redefine typed alias"));
2158 reg->neon = (struct neon_typed_alias *)
2159 xmalloc (sizeof (struct neon_typed_alias));
2160 *reg->neon = *atype;
2164 /* Look for the .req directive. This is of the form:
2166 new_register_name .req existing_register_name
2168 If we find one, or if it looks sufficiently like one that we want to
2169 handle any error here, return TRUE. Otherwise return FALSE. */
2172 create_register_alias (char * newname, char *p)
2174 struct reg_entry *old;
2175 char *oldname, *nbuf;
2178 /* The input scrubber ensures that whitespace after the mnemonic is
2179 collapsed to single spaces. */
2181 if (strncmp (oldname, " .req ", 6) != 0)
2185 if (*oldname == '\0')
2188 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2191 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2195 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2196 the desired alias name, and p points to its end. If not, then
2197 the desired alias name is in the global original_case_string. */
2198 #ifdef TC_CASE_SENSITIVE
2201 newname = original_case_string;
2202 nlen = strlen (newname);
2205 nbuf = (char *) alloca (nlen + 1);
2206 memcpy (nbuf, newname, nlen);
2209 /* Create aliases under the new name as stated; an all-lowercase
2210 version of the new name; and an all-uppercase version of the new
2212 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2214 for (p = nbuf; *p; p++)
2217 if (strncmp (nbuf, newname, nlen))
2219 /* If this attempt to create an additional alias fails, do not bother
2220 trying to create the all-lower case alias. We will fail and issue
2221 a second, duplicate error message. This situation arises when the
2222 programmer does something like:
2225 The second .req creates the "Foo" alias but then fails to create
2226 the artificial FOO alias because it has already been created by the
2228 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2232 for (p = nbuf; *p; p++)
2235 if (strncmp (nbuf, newname, nlen))
2236 insert_reg_alias (nbuf, old->number, old->type);
2242 /* Create a Neon typed/indexed register alias using directives, e.g.:
2247 These typed registers can be used instead of the types specified after the
2248 Neon mnemonic, so long as all operands given have types. Types can also be
2249 specified directly, e.g.:
2250 vadd d0.s32, d1.s32, d2.s32 */
2253 create_neon_reg_alias (char *newname, char *p)
2255 enum arm_reg_type basetype;
2256 struct reg_entry *basereg;
2257 struct reg_entry mybasereg;
2258 struct neon_type ntype;
2259 struct neon_typed_alias typeinfo;
2260 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2263 typeinfo.defined = 0;
2264 typeinfo.eltype.type = NT_invtype;
2265 typeinfo.eltype.size = -1;
2266 typeinfo.index = -1;
2270 if (strncmp (p, " .dn ", 5) == 0)
2271 basetype = REG_TYPE_VFD;
2272 else if (strncmp (p, " .qn ", 5) == 0)
2273 basetype = REG_TYPE_NQ;
2282 basereg = arm_reg_parse_multi (&p);
2284 if (basereg && basereg->type != basetype)
2286 as_bad (_("bad type for register"));
2290 if (basereg == NULL)
2293 /* Try parsing as an integer. */
2294 my_get_expression (&exp, &p, GE_NO_PREFIX);
2295 if (exp.X_op != O_constant)
2297 as_bad (_("expression must be constant"));
2300 basereg = &mybasereg;
2301 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2307 typeinfo = *basereg->neon;
2309 if (parse_neon_type (&ntype, &p) == SUCCESS)
2311 /* We got a type. */
2312 if (typeinfo.defined & NTA_HASTYPE)
2314 as_bad (_("can't redefine the type of a register alias"));
2318 typeinfo.defined |= NTA_HASTYPE;
2319 if (ntype.elems != 1)
2321 as_bad (_("you must specify a single type only"));
2324 typeinfo.eltype = ntype.el[0];
2327 if (skip_past_char (&p, '[') == SUCCESS)
2330 /* We got a scalar index. */
2332 if (typeinfo.defined & NTA_HASINDEX)
2334 as_bad (_("can't redefine the index of a scalar alias"));
2338 my_get_expression (&exp, &p, GE_NO_PREFIX);
2340 if (exp.X_op != O_constant)
2342 as_bad (_("scalar index must be constant"));
2346 typeinfo.defined |= NTA_HASINDEX;
2347 typeinfo.index = exp.X_add_number;
2349 if (skip_past_char (&p, ']') == FAIL)
2351 as_bad (_("expecting ]"));
2356 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2357 the desired alias name, and p points to its end. If not, then
2358 the desired alias name is in the global original_case_string. */
2359 #ifdef TC_CASE_SENSITIVE
2360 namelen = nameend - newname;
2362 newname = original_case_string;
2363 namelen = strlen (newname);
2366 namebuf = (char *) alloca (namelen + 1);
2367 strncpy (namebuf, newname, namelen);
2368 namebuf[namelen] = '\0';
2370 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2371 typeinfo.defined != 0 ? &typeinfo : NULL);
2373 /* Insert name in all uppercase. */
2374 for (p = namebuf; *p; p++)
2377 if (strncmp (namebuf, newname, namelen))
2378 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2379 typeinfo.defined != 0 ? &typeinfo : NULL);
2381 /* Insert name in all lowercase. */
2382 for (p = namebuf; *p; p++)
2385 if (strncmp (namebuf, newname, namelen))
2386 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2387 typeinfo.defined != 0 ? &typeinfo : NULL);
2392 /* Should never be called, as .req goes between the alias and the
2393 register name, not at the beginning of the line. */
2396 s_req (int a ATTRIBUTE_UNUSED)
2398 as_bad (_("invalid syntax for .req directive"));
2402 s_dn (int a ATTRIBUTE_UNUSED)
2404 as_bad (_("invalid syntax for .dn directive"));
2408 s_qn (int a ATTRIBUTE_UNUSED)
2410 as_bad (_("invalid syntax for .qn directive"));
2413 /* The .unreq directive deletes an alias which was previously defined
2414 by .req. For example:
2420 s_unreq (int a ATTRIBUTE_UNUSED)
2425 name = input_line_pointer;
2427 while (*input_line_pointer != 0
2428 && *input_line_pointer != ' '
2429 && *input_line_pointer != '\n')
2430 ++input_line_pointer;
2432 saved_char = *input_line_pointer;
2433 *input_line_pointer = 0;
2436 as_bad (_("invalid syntax for .unreq directive"));
2439 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2443 as_bad (_("unknown register alias '%s'"), name);
2444 else if (reg->builtin)
2445 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2452 hash_delete (arm_reg_hsh, name, FALSE);
2453 free ((char *) reg->name);
2458 /* Also locate the all upper case and all lower case versions.
2459 Do not complain if we cannot find one or the other as it
2460 was probably deleted above. */
2462 nbuf = strdup (name);
2463 for (p = nbuf; *p; p++)
2465 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2468 hash_delete (arm_reg_hsh, nbuf, FALSE);
2469 free ((char *) reg->name);
2475 for (p = nbuf; *p; p++)
2477 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2480 hash_delete (arm_reg_hsh, nbuf, FALSE);
2481 free ((char *) reg->name);
2491 *input_line_pointer = saved_char;
2492 demand_empty_rest_of_line ();
2495 /* Directives: Instruction set selection. */
2498 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2499 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2500 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2501 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2503 /* Create a new mapping symbol for the transition to STATE. */
2506 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2509 const char * symname;
2516 type = BSF_NO_FLAGS;
2520 type = BSF_NO_FLAGS;
2524 type = BSF_NO_FLAGS;
2530 symbolP = symbol_new (symname, now_seg, value, frag);
2531 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2536 THUMB_SET_FUNC (symbolP, 0);
2537 ARM_SET_THUMB (symbolP, 0);
2538 ARM_SET_INTERWORK (symbolP, support_interwork);
2542 THUMB_SET_FUNC (symbolP, 1);
2543 ARM_SET_THUMB (symbolP, 1);
2544 ARM_SET_INTERWORK (symbolP, support_interwork);
2552 /* Save the mapping symbols for future reference. Also check that
2553 we do not place two mapping symbols at the same offset within a
2554 frag. We'll handle overlap between frags in
2555 check_mapping_symbols.
2557 If .fill or other data filling directive generates zero sized data,
2558 the mapping symbol for the following code will have the same value
2559 as the one generated for the data filling directive. In this case,
2560 we replace the old symbol with the new one at the same address. */
2563 if (frag->tc_frag_data.first_map != NULL)
2565 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2566 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2568 frag->tc_frag_data.first_map = symbolP;
2570 if (frag->tc_frag_data.last_map != NULL)
2572 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2573 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2574 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2576 frag->tc_frag_data.last_map = symbolP;
2579 /* We must sometimes convert a region marked as code to data during
2580 code alignment, if an odd number of bytes have to be padded. The
2581 code mapping symbol is pushed to an aligned address. */
2584 insert_data_mapping_symbol (enum mstate state,
2585 valueT value, fragS *frag, offsetT bytes)
2587 /* If there was already a mapping symbol, remove it. */
2588 if (frag->tc_frag_data.last_map != NULL
2589 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2591 symbolS *symp = frag->tc_frag_data.last_map;
2595 know (frag->tc_frag_data.first_map == symp);
2596 frag->tc_frag_data.first_map = NULL;
2598 frag->tc_frag_data.last_map = NULL;
2599 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2602 make_mapping_symbol (MAP_DATA, value, frag);
2603 make_mapping_symbol (state, value + bytes, frag);
2606 static void mapping_state_2 (enum mstate state, int max_chars);
2608 /* Set the mapping state to STATE. Only call this when about to
2609 emit some STATE bytes to the file. */
2612 mapping_state (enum mstate state)
2614 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2616 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2618 if (mapstate == state)
2619 /* The mapping symbol has already been emitted.
2620 There is nothing else to do. */
2623 if (state == MAP_ARM || state == MAP_THUMB)
2625 All ARM instructions require 4-byte alignment.
2626 (Almost) all Thumb instructions require 2-byte alignment.
2628 When emitting instructions into any section, mark the section
2631 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2632 but themselves require 2-byte alignment; this applies to some
2633 PC- relative forms. However, these cases will invovle implicit
2634 literal pool generation or an explicit .align >=2, both of
2635 which will cause the section to me marked with sufficient
2636 alignment. Thus, we don't handle those cases here. */
2637 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2639 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2640 /* This case will be evaluated later in the next else. */
2642 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2643 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2645 /* Only add the symbol if the offset is > 0:
2646 if we're at the first frag, check it's size > 0;
2647 if we're not at the first frag, then for sure
2648 the offset is > 0. */
2649 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2650 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2653 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2656 mapping_state_2 (state, 0);
2660 /* Same as mapping_state, but MAX_CHARS bytes have already been
2661 allocated. Put the mapping symbol that far back. */
2664 mapping_state_2 (enum mstate state, int max_chars)
2666 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2668 if (!SEG_NORMAL (now_seg))
2671 if (mapstate == state)
2672 /* The mapping symbol has already been emitted.
2673 There is nothing else to do. */
2676 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2677 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2680 #define mapping_state(x) ((void)0)
2681 #define mapping_state_2(x, y) ((void)0)
2684 /* Find the real, Thumb encoded start of a Thumb function. */
2688 find_real_start (symbolS * symbolP)
2691 const char * name = S_GET_NAME (symbolP);
2692 symbolS * new_target;
2694 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2695 #define STUB_NAME ".real_start_of"
2700 /* The compiler may generate BL instructions to local labels because
2701 it needs to perform a branch to a far away location. These labels
2702 do not have a corresponding ".real_start_of" label. We check
2703 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2704 the ".real_start_of" convention for nonlocal branches. */
2705 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2708 real_start = ACONCAT ((STUB_NAME, name, NULL));
2709 new_target = symbol_find (real_start);
2711 if (new_target == NULL)
2713 as_warn (_("Failed to find real start of function: %s\n"), name);
2714 new_target = symbolP;
2722 opcode_select (int width)
2729 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2730 as_bad (_("selected processor does not support THUMB opcodes"));
2733 /* No need to force the alignment, since we will have been
2734 coming from ARM mode, which is word-aligned. */
2735 record_alignment (now_seg, 1);
2742 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2743 as_bad (_("selected processor does not support ARM opcodes"));
2748 frag_align (2, 0, 0);
2750 record_alignment (now_seg, 1);
2755 as_bad (_("invalid instruction size selected (%d)"), width);
2760 s_arm (int ignore ATTRIBUTE_UNUSED)
2763 demand_empty_rest_of_line ();
2767 s_thumb (int ignore ATTRIBUTE_UNUSED)
2770 demand_empty_rest_of_line ();
2774 s_code (int unused ATTRIBUTE_UNUSED)
2778 temp = get_absolute_expression ();
2783 opcode_select (temp);
2787 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2792 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2794 /* If we are not already in thumb mode go into it, EVEN if
2795 the target processor does not support thumb instructions.
2796 This is used by gcc/config/arm/lib1funcs.asm for example
2797 to compile interworking support functions even if the
2798 target processor should not support interworking. */
2802 record_alignment (now_seg, 1);
2805 demand_empty_rest_of_line ();
2809 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2813 /* The following label is the name/address of the start of a Thumb function.
2814 We need to know this for the interworking support. */
2815 label_is_thumb_function_name = TRUE;
2818 /* Perform a .set directive, but also mark the alias as
2819 being a thumb function. */
2822 s_thumb_set (int equiv)
2824 /* XXX the following is a duplicate of the code for s_set() in read.c
2825 We cannot just call that code as we need to get at the symbol that
2832 /* Especial apologies for the random logic:
2833 This just grew, and could be parsed much more simply!
2835 name = input_line_pointer;
2836 delim = get_symbol_end ();
2837 end_name = input_line_pointer;
2840 if (*input_line_pointer != ',')
2843 as_bad (_("expected comma after name \"%s\""), name);
2845 ignore_rest_of_line ();
2849 input_line_pointer++;
2852 if (name[0] == '.' && name[1] == '\0')
2854 /* XXX - this should not happen to .thumb_set. */
2858 if ((symbolP = symbol_find (name)) == NULL
2859 && (symbolP = md_undefined_symbol (name)) == NULL)
2862 /* When doing symbol listings, play games with dummy fragments living
2863 outside the normal fragment chain to record the file and line info
2865 if (listing & LISTING_SYMBOLS)
2867 extern struct list_info_struct * listing_tail;
2868 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2870 memset (dummy_frag, 0, sizeof (fragS));
2871 dummy_frag->fr_type = rs_fill;
2872 dummy_frag->line = listing_tail;
2873 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2874 dummy_frag->fr_symbol = symbolP;
2878 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2881 /* "set" symbols are local unless otherwise specified. */
2882 SF_SET_LOCAL (symbolP);
2883 #endif /* OBJ_COFF */
2884 } /* Make a new symbol. */
2886 symbol_table_insert (symbolP);
2891 && S_IS_DEFINED (symbolP)
2892 && S_GET_SEGMENT (symbolP) != reg_section)
2893 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2895 pseudo_set (symbolP);
2897 demand_empty_rest_of_line ();
2899 /* XXX Now we come to the Thumb specific bit of code. */
2901 THUMB_SET_FUNC (symbolP, 1);
2902 ARM_SET_THUMB (symbolP, 1);
2903 #if defined OBJ_ELF || defined OBJ_COFF
2904 ARM_SET_INTERWORK (symbolP, support_interwork);
2908 /* Directives: Mode selection. */
2910 /* .syntax [unified|divided] - choose the new unified syntax
2911 (same for Arm and Thumb encoding, modulo slight differences in what
2912 can be represented) or the old divergent syntax for each mode. */
2914 s_syntax (int unused ATTRIBUTE_UNUSED)
2918 name = input_line_pointer;
2919 delim = get_symbol_end ();
2921 if (!strcasecmp (name, "unified"))
2922 unified_syntax = TRUE;
2923 else if (!strcasecmp (name, "divided"))
2924 unified_syntax = FALSE;
2927 as_bad (_("unrecognized syntax mode \"%s\""), name);
2930 *input_line_pointer = delim;
2931 demand_empty_rest_of_line ();
2934 /* Directives: sectioning and alignment. */
2936 /* Same as s_align_ptwo but align 0 => align 2. */
2939 s_align (int unused ATTRIBUTE_UNUSED)
2944 long max_alignment = 15;
2946 temp = get_absolute_expression ();
2947 if (temp > max_alignment)
2948 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2951 as_bad (_("alignment negative. 0 assumed."));
2955 if (*input_line_pointer == ',')
2957 input_line_pointer++;
2958 temp_fill = get_absolute_expression ();
2970 /* Only make a frag if we HAVE to. */
2971 if (temp && !need_pass_2)
2973 if (!fill_p && subseg_text_p (now_seg))
2974 frag_align_code (temp, 0);
2976 frag_align (temp, (int) temp_fill, 0);
2978 demand_empty_rest_of_line ();
2980 record_alignment (now_seg, temp);
2984 s_bss (int ignore ATTRIBUTE_UNUSED)
2986 /* We don't support putting frags in the BSS segment, we fake it by
2987 marking in_bss, then looking at s_skip for clues. */
2988 subseg_set (bss_section, 0);
2989 demand_empty_rest_of_line ();
2991 #ifdef md_elf_section_change_hook
2992 md_elf_section_change_hook ();
2997 s_even (int ignore ATTRIBUTE_UNUSED)
2999 /* Never make frag if expect extra pass. */
3001 frag_align (1, 0, 0);
3003 record_alignment (now_seg, 1);
3005 demand_empty_rest_of_line ();
3008 /* Directives: Literal pools. */
3010 static literal_pool *
3011 find_literal_pool (void)
3013 literal_pool * pool;
3015 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3017 if (pool->section == now_seg
3018 && pool->sub_section == now_subseg)
3025 static literal_pool *
3026 find_or_make_literal_pool (void)
3028 /* Next literal pool ID number. */
3029 static unsigned int latest_pool_num = 1;
3030 literal_pool * pool;
3032 pool = find_literal_pool ();
3036 /* Create a new pool. */
3037 pool = (literal_pool *) xmalloc (sizeof (* pool));
3041 pool->next_free_entry = 0;
3042 pool->section = now_seg;
3043 pool->sub_section = now_subseg;
3044 pool->next = list_of_pools;
3045 pool->symbol = NULL;
3047 /* Add it to the list. */
3048 list_of_pools = pool;
3051 /* New pools, and emptied pools, will have a NULL symbol. */
3052 if (pool->symbol == NULL)
3054 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3055 (valueT) 0, &zero_address_frag);
3056 pool->id = latest_pool_num ++;
3063 /* Add the literal in the global 'inst'
3064 structure to the relevant literal pool. */
3067 add_to_lit_pool (void)
3069 literal_pool * pool;
3072 pool = find_or_make_literal_pool ();
3074 /* Check if this literal value is already in the pool. */
3075 for (entry = 0; entry < pool->next_free_entry; entry ++)
3077 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3078 && (inst.reloc.exp.X_op == O_constant)
3079 && (pool->literals[entry].X_add_number
3080 == inst.reloc.exp.X_add_number)
3081 && (pool->literals[entry].X_unsigned
3082 == inst.reloc.exp.X_unsigned))
3085 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3086 && (inst.reloc.exp.X_op == O_symbol)
3087 && (pool->literals[entry].X_add_number
3088 == inst.reloc.exp.X_add_number)
3089 && (pool->literals[entry].X_add_symbol
3090 == inst.reloc.exp.X_add_symbol)
3091 && (pool->literals[entry].X_op_symbol
3092 == inst.reloc.exp.X_op_symbol))
3096 /* Do we need to create a new entry? */
3097 if (entry == pool->next_free_entry)
3099 if (entry >= MAX_LITERAL_POOL_SIZE)
3101 inst.error = _("literal pool overflow");
3105 pool->literals[entry] = inst.reloc.exp;
3107 /* PR ld/12974: Record the location of the first source line to reference
3108 this entry in the literal pool. If it turns out during linking that the
3109 symbol does not exist we will be able to give an accurate line number for
3110 the (first use of the) missing reference. */
3111 if (debug_type == DEBUG_DWARF2)
3112 dwarf2_where (pool->locs + entry);
3114 pool->next_free_entry += 1;
3117 inst.reloc.exp.X_op = O_symbol;
3118 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3119 inst.reloc.exp.X_add_symbol = pool->symbol;
3124 /* Can't use symbol_new here, so have to create a symbol and then at
3125 a later date assign it a value. Thats what these functions do. */
3128 symbol_locate (symbolS * symbolP,
3129 const char * name, /* It is copied, the caller can modify. */
3130 segT segment, /* Segment identifier (SEG_<something>). */
3131 valueT valu, /* Symbol value. */
3132 fragS * frag) /* Associated fragment. */
3134 unsigned int name_length;
3135 char * preserved_copy_of_name;
3137 name_length = strlen (name) + 1; /* +1 for \0. */
3138 obstack_grow (¬es, name, name_length);
3139 preserved_copy_of_name = (char *) obstack_finish (¬es);
3141 #ifdef tc_canonicalize_symbol_name
3142 preserved_copy_of_name =
3143 tc_canonicalize_symbol_name (preserved_copy_of_name);
3146 S_SET_NAME (symbolP, preserved_copy_of_name);
3148 S_SET_SEGMENT (symbolP, segment);
3149 S_SET_VALUE (symbolP, valu);
3150 symbol_clear_list_pointers (symbolP);
3152 symbol_set_frag (symbolP, frag);
3154 /* Link to end of symbol chain. */
3156 extern int symbol_table_frozen;
3158 if (symbol_table_frozen)
3162 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3164 obj_symbol_new_hook (symbolP);
3166 #ifdef tc_symbol_new_hook
3167 tc_symbol_new_hook (symbolP);
3171 verify_symbol_chain (symbol_rootP, symbol_lastP);
3172 #endif /* DEBUG_SYMS */
3177 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3180 literal_pool * pool;
3183 pool = find_literal_pool ();
3185 || pool->symbol == NULL
3186 || pool->next_free_entry == 0)
3189 mapping_state (MAP_DATA);
3191 /* Align pool as you have word accesses.
3192 Only make a frag if we have to. */
3194 frag_align (2, 0, 0);
3196 record_alignment (now_seg, 2);
3198 sprintf (sym_name, "$$lit_\002%x", pool->id);
3200 symbol_locate (pool->symbol, sym_name, now_seg,
3201 (valueT) frag_now_fix (), frag_now);
3202 symbol_table_insert (pool->symbol);
3204 ARM_SET_THUMB (pool->symbol, thumb_mode);
3206 #if defined OBJ_COFF || defined OBJ_ELF
3207 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3210 for (entry = 0; entry < pool->next_free_entry; entry ++)
3213 if (debug_type == DEBUG_DWARF2)
3214 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3216 /* First output the expression in the instruction to the pool. */
3217 emit_expr (&(pool->literals[entry]), 4); /* .word */
3220 /* Mark the pool as empty. */
3221 pool->next_free_entry = 0;
3222 pool->symbol = NULL;
3226 /* Forward declarations for functions below, in the MD interface
3228 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3229 static valueT create_unwind_entry (int);
3230 static void start_unwind_section (const segT, int);
3231 static void add_unwind_opcode (valueT, int);
3232 static void flush_pending_unwind (void);
3234 /* Directives: Data. */
3237 s_arm_elf_cons (int nbytes)
3241 #ifdef md_flush_pending_output
3242 md_flush_pending_output ();
3245 if (is_it_end_of_statement ())
3247 demand_empty_rest_of_line ();
3251 #ifdef md_cons_align
3252 md_cons_align (nbytes);
3255 mapping_state (MAP_DATA);
3259 char *base = input_line_pointer;
3263 if (exp.X_op != O_symbol)
3264 emit_expr (&exp, (unsigned int) nbytes);
3267 char *before_reloc = input_line_pointer;
3268 reloc = parse_reloc (&input_line_pointer);
3271 as_bad (_("unrecognized relocation suffix"));
3272 ignore_rest_of_line ();
3275 else if (reloc == BFD_RELOC_UNUSED)
3276 emit_expr (&exp, (unsigned int) nbytes);
3279 reloc_howto_type *howto = (reloc_howto_type *)
3280 bfd_reloc_type_lookup (stdoutput,
3281 (bfd_reloc_code_real_type) reloc);
3282 int size = bfd_get_reloc_size (howto);
3284 if (reloc == BFD_RELOC_ARM_PLT32)
3286 as_bad (_("(plt) is only valid on branch targets"));
3287 reloc = BFD_RELOC_UNUSED;
3292 as_bad (_("%s relocations do not fit in %d bytes"),
3293 howto->name, nbytes);
3296 /* We've parsed an expression stopping at O_symbol.
3297 But there may be more expression left now that we
3298 have parsed the relocation marker. Parse it again.
3299 XXX Surely there is a cleaner way to do this. */
3300 char *p = input_line_pointer;
3302 char *save_buf = (char *) alloca (input_line_pointer - base);
3303 memcpy (save_buf, base, input_line_pointer - base);
3304 memmove (base + (input_line_pointer - before_reloc),
3305 base, before_reloc - base);
3307 input_line_pointer = base + (input_line_pointer-before_reloc);
3309 memcpy (base, save_buf, p - base);
3311 offset = nbytes - size;
3312 p = frag_more ((int) nbytes);
3313 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3314 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3319 while (*input_line_pointer++ == ',');
3321 /* Put terminator back into stream. */
3322 input_line_pointer --;
3323 demand_empty_rest_of_line ();
3326 /* Emit an expression containing a 32-bit thumb instruction.
3327 Implementation based on put_thumb32_insn. */
3330 emit_thumb32_expr (expressionS * exp)
3332 expressionS exp_high = *exp;
3334 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3335 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3336 exp->X_add_number &= 0xffff;
3337 emit_expr (exp, (unsigned int) THUMB_SIZE);
3340 /* Guess the instruction size based on the opcode. */
3343 thumb_insn_size (int opcode)
3345 if ((unsigned int) opcode < 0xe800u)
3347 else if ((unsigned int) opcode >= 0xe8000000u)
3354 emit_insn (expressionS *exp, int nbytes)
3358 if (exp->X_op == O_constant)
3363 size = thumb_insn_size (exp->X_add_number);
3367 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3369 as_bad (_(".inst.n operand too big. "\
3370 "Use .inst.w instead"));
3375 if (now_it.state == AUTOMATIC_IT_BLOCK)
3376 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3378 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3380 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3381 emit_thumb32_expr (exp);
3383 emit_expr (exp, (unsigned int) size);
3385 it_fsm_post_encode ();
3389 as_bad (_("cannot determine Thumb instruction size. " \
3390 "Use .inst.n/.inst.w instead"));
3393 as_bad (_("constant expression required"));
3398 /* Like s_arm_elf_cons but do not use md_cons_align and
3399 set the mapping state to MAP_ARM/MAP_THUMB. */
3402 s_arm_elf_inst (int nbytes)
3404 if (is_it_end_of_statement ())
3406 demand_empty_rest_of_line ();
3410 /* Calling mapping_state () here will not change ARM/THUMB,
3411 but will ensure not to be in DATA state. */
3414 mapping_state (MAP_THUMB);
3419 as_bad (_("width suffixes are invalid in ARM mode"));
3420 ignore_rest_of_line ();
3426 mapping_state (MAP_ARM);
3435 if (! emit_insn (& exp, nbytes))
3437 ignore_rest_of_line ();
3441 while (*input_line_pointer++ == ',');
3443 /* Put terminator back into stream. */
3444 input_line_pointer --;
3445 demand_empty_rest_of_line ();
3448 /* Parse a .rel31 directive. */
3451 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3458 if (*input_line_pointer == '1')
3459 highbit = 0x80000000;
3460 else if (*input_line_pointer != '0')
3461 as_bad (_("expected 0 or 1"));
3463 input_line_pointer++;
3464 if (*input_line_pointer != ',')
3465 as_bad (_("missing comma"));
3466 input_line_pointer++;
3468 #ifdef md_flush_pending_output
3469 md_flush_pending_output ();
3472 #ifdef md_cons_align
3476 mapping_state (MAP_DATA);
3481 md_number_to_chars (p, highbit, 4);
3482 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3483 BFD_RELOC_ARM_PREL31);
3485 demand_empty_rest_of_line ();
3488 /* Directives: AEABI stack-unwind tables. */
3490 /* Parse an unwind_fnstart directive. Simply records the current location. */
3493 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3495 demand_empty_rest_of_line ();
3496 if (unwind.proc_start)
3498 as_bad (_("duplicate .fnstart directive"));
3502 /* Mark the start of the function. */
3503 unwind.proc_start = expr_build_dot ();
3505 /* Reset the rest of the unwind info. */
3506 unwind.opcode_count = 0;
3507 unwind.table_entry = NULL;
3508 unwind.personality_routine = NULL;
3509 unwind.personality_index = -1;
3510 unwind.frame_size = 0;
3511 unwind.fp_offset = 0;
3512 unwind.fp_reg = REG_SP;
3514 unwind.sp_restored = 0;
3518 /* Parse a handlerdata directive. Creates the exception handling table entry
3519 for the function. */
3522 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3524 demand_empty_rest_of_line ();
3525 if (!unwind.proc_start)
3526 as_bad (MISSING_FNSTART);
3528 if (unwind.table_entry)
3529 as_bad (_("duplicate .handlerdata directive"));
3531 create_unwind_entry (1);
3534 /* Parse an unwind_fnend directive. Generates the index table entry. */
3537 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3542 unsigned int marked_pr_dependency;
3544 demand_empty_rest_of_line ();
3546 if (!unwind.proc_start)
3548 as_bad (_(".fnend directive without .fnstart"));
3552 /* Add eh table entry. */
3553 if (unwind.table_entry == NULL)
3554 val = create_unwind_entry (0);
3558 /* Add index table entry. This is two words. */
3559 start_unwind_section (unwind.saved_seg, 1);
3560 frag_align (2, 0, 0);
3561 record_alignment (now_seg, 2);
3563 ptr = frag_more (8);
3565 where = frag_now_fix () - 8;
3567 /* Self relative offset of the function start. */
3568 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3569 BFD_RELOC_ARM_PREL31);
3571 /* Indicate dependency on EHABI-defined personality routines to the
3572 linker, if it hasn't been done already. */
3573 marked_pr_dependency
3574 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3575 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3576 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3578 static const char *const name[] =
3580 "__aeabi_unwind_cpp_pr0",
3581 "__aeabi_unwind_cpp_pr1",
3582 "__aeabi_unwind_cpp_pr2"
3584 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3585 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3586 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3587 |= 1 << unwind.personality_index;
3591 /* Inline exception table entry. */
3592 md_number_to_chars (ptr + 4, val, 4);
3594 /* Self relative offset of the table entry. */
3595 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3596 BFD_RELOC_ARM_PREL31);
3598 /* Restore the original section. */
3599 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3601 unwind.proc_start = NULL;
3605 /* Parse an unwind_cantunwind directive. */
3608 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3610 demand_empty_rest_of_line ();
3611 if (!unwind.proc_start)
3612 as_bad (MISSING_FNSTART);
3614 if (unwind.personality_routine || unwind.personality_index != -1)
3615 as_bad (_("personality routine specified for cantunwind frame"));
3617 unwind.personality_index = -2;
3621 /* Parse a personalityindex directive. */
3624 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3628 if (!unwind.proc_start)
3629 as_bad (MISSING_FNSTART);
3631 if (unwind.personality_routine || unwind.personality_index != -1)
3632 as_bad (_("duplicate .personalityindex directive"));
3636 if (exp.X_op != O_constant
3637 || exp.X_add_number < 0 || exp.X_add_number > 15)
3639 as_bad (_("bad personality routine number"));
3640 ignore_rest_of_line ();
3644 unwind.personality_index = exp.X_add_number;
3646 demand_empty_rest_of_line ();
3650 /* Parse a personality directive. */
3653 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3657 if (!unwind.proc_start)
3658 as_bad (MISSING_FNSTART);
3660 if (unwind.personality_routine || unwind.personality_index != -1)
3661 as_bad (_("duplicate .personality directive"));
3663 name = input_line_pointer;
3664 c = get_symbol_end ();
3665 p = input_line_pointer;
3666 unwind.personality_routine = symbol_find_or_make (name);
3668 demand_empty_rest_of_line ();
3672 /* Parse a directive saving core registers. */
3675 s_arm_unwind_save_core (void)
3681 range = parse_reg_list (&input_line_pointer);
3684 as_bad (_("expected register list"));
3685 ignore_rest_of_line ();
3689 demand_empty_rest_of_line ();
3691 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3692 into .unwind_save {..., sp...}. We aren't bothered about the value of
3693 ip because it is clobbered by calls. */
3694 if (unwind.sp_restored && unwind.fp_reg == 12
3695 && (range & 0x3000) == 0x1000)
3697 unwind.opcode_count--;
3698 unwind.sp_restored = 0;
3699 range = (range | 0x2000) & ~0x1000;
3700 unwind.pending_offset = 0;
3706 /* See if we can use the short opcodes. These pop a block of up to 8
3707 registers starting with r4, plus maybe r14. */
3708 for (n = 0; n < 8; n++)
3710 /* Break at the first non-saved register. */
3711 if ((range & (1 << (n + 4))) == 0)
3714 /* See if there are any other bits set. */
3715 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3717 /* Use the long form. */
3718 op = 0x8000 | ((range >> 4) & 0xfff);
3719 add_unwind_opcode (op, 2);
3723 /* Use the short form. */
3725 op = 0xa8; /* Pop r14. */
3727 op = 0xa0; /* Do not pop r14. */
3729 add_unwind_opcode (op, 1);
3736 op = 0xb100 | (range & 0xf);
3737 add_unwind_opcode (op, 2);
3740 /* Record the number of bytes pushed. */
3741 for (n = 0; n < 16; n++)
3743 if (range & (1 << n))
3744 unwind.frame_size += 4;
3749 /* Parse a directive saving FPA registers. */
3752 s_arm_unwind_save_fpa (int reg)
3758 /* Get Number of registers to transfer. */
3759 if (skip_past_comma (&input_line_pointer) != FAIL)
3762 exp.X_op = O_illegal;
3764 if (exp.X_op != O_constant)
3766 as_bad (_("expected , <constant>"));
3767 ignore_rest_of_line ();
3771 num_regs = exp.X_add_number;
3773 if (num_regs < 1 || num_regs > 4)
3775 as_bad (_("number of registers must be in the range [1:4]"));
3776 ignore_rest_of_line ();
3780 demand_empty_rest_of_line ();
3785 op = 0xb4 | (num_regs - 1);
3786 add_unwind_opcode (op, 1);
3791 op = 0xc800 | (reg << 4) | (num_regs - 1);
3792 add_unwind_opcode (op, 2);
3794 unwind.frame_size += num_regs * 12;
3798 /* Parse a directive saving VFP registers for ARMv6 and above. */
3801 s_arm_unwind_save_vfp_armv6 (void)
3806 int num_vfpv3_regs = 0;
3807 int num_regs_below_16;
3809 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3812 as_bad (_("expected register list"));
3813 ignore_rest_of_line ();
3817 demand_empty_rest_of_line ();
3819 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3820 than FSTMX/FLDMX-style ones). */
3822 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3824 num_vfpv3_regs = count;
3825 else if (start + count > 16)
3826 num_vfpv3_regs = start + count - 16;
3828 if (num_vfpv3_regs > 0)
3830 int start_offset = start > 16 ? start - 16 : 0;
3831 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3832 add_unwind_opcode (op, 2);
3835 /* Generate opcode for registers numbered in the range 0 .. 15. */
3836 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3837 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3838 if (num_regs_below_16 > 0)
3840 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3841 add_unwind_opcode (op, 2);
3844 unwind.frame_size += count * 8;
3848 /* Parse a directive saving VFP registers for pre-ARMv6. */
3851 s_arm_unwind_save_vfp (void)
3857 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3860 as_bad (_("expected register list"));
3861 ignore_rest_of_line ();
3865 demand_empty_rest_of_line ();
3870 op = 0xb8 | (count - 1);
3871 add_unwind_opcode (op, 1);
3876 op = 0xb300 | (reg << 4) | (count - 1);
3877 add_unwind_opcode (op, 2);
3879 unwind.frame_size += count * 8 + 4;
3883 /* Parse a directive saving iWMMXt data registers. */
3886 s_arm_unwind_save_mmxwr (void)
3894 if (*input_line_pointer == '{')
3895 input_line_pointer++;
3899 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3903 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3908 as_tsktsk (_("register list not in ascending order"));
3911 if (*input_line_pointer == '-')
3913 input_line_pointer++;
3914 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3917 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3920 else if (reg >= hi_reg)
3922 as_bad (_("bad register range"));
3925 for (; reg < hi_reg; reg++)
3929 while (skip_past_comma (&input_line_pointer) != FAIL);
3931 if (*input_line_pointer == '}')
3932 input_line_pointer++;
3934 demand_empty_rest_of_line ();
3936 /* Generate any deferred opcodes because we're going to be looking at
3938 flush_pending_unwind ();
3940 for (i = 0; i < 16; i++)
3942 if (mask & (1 << i))
3943 unwind.frame_size += 8;
3946 /* Attempt to combine with a previous opcode. We do this because gcc
3947 likes to output separate unwind directives for a single block of
3949 if (unwind.opcode_count > 0)
3951 i = unwind.opcodes[unwind.opcode_count - 1];
3952 if ((i & 0xf8) == 0xc0)
3955 /* Only merge if the blocks are contiguous. */
3958 if ((mask & 0xfe00) == (1 << 9))
3960 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3961 unwind.opcode_count--;
3964 else if (i == 6 && unwind.opcode_count >= 2)
3966 i = unwind.opcodes[unwind.opcode_count - 2];
3970 op = 0xffff << (reg - 1);
3972 && ((mask & op) == (1u << (reg - 1))))
3974 op = (1 << (reg + i + 1)) - 1;
3975 op &= ~((1 << reg) - 1);
3977 unwind.opcode_count -= 2;
3984 /* We want to generate opcodes in the order the registers have been
3985 saved, ie. descending order. */
3986 for (reg = 15; reg >= -1; reg--)
3988 /* Save registers in blocks. */
3990 || !(mask & (1 << reg)))
3992 /* We found an unsaved reg. Generate opcodes to save the
3999 op = 0xc0 | (hi_reg - 10);
4000 add_unwind_opcode (op, 1);
4005 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4006 add_unwind_opcode (op, 2);
4015 ignore_rest_of_line ();
4019 s_arm_unwind_save_mmxwcg (void)
4026 if (*input_line_pointer == '{')
4027 input_line_pointer++;
4031 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4035 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4041 as_tsktsk (_("register list not in ascending order"));
4044 if (*input_line_pointer == '-')
4046 input_line_pointer++;
4047 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4050 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4053 else if (reg >= hi_reg)
4055 as_bad (_("bad register range"));
4058 for (; reg < hi_reg; reg++)
4062 while (skip_past_comma (&input_line_pointer) != FAIL);
4064 if (*input_line_pointer == '}')
4065 input_line_pointer++;
4067 demand_empty_rest_of_line ();
4069 /* Generate any deferred opcodes because we're going to be looking at
4071 flush_pending_unwind ();
4073 for (reg = 0; reg < 16; reg++)
4075 if (mask & (1 << reg))
4076 unwind.frame_size += 4;
4079 add_unwind_opcode (op, 2);
4082 ignore_rest_of_line ();
4086 /* Parse an unwind_save directive.
4087 If the argument is non-zero, this is a .vsave directive. */
4090 s_arm_unwind_save (int arch_v6)
4093 struct reg_entry *reg;
4094 bfd_boolean had_brace = FALSE;
4096 if (!unwind.proc_start)
4097 as_bad (MISSING_FNSTART);
4099 /* Figure out what sort of save we have. */
4100 peek = input_line_pointer;
4108 reg = arm_reg_parse_multi (&peek);
4112 as_bad (_("register expected"));
4113 ignore_rest_of_line ();
4122 as_bad (_("FPA .unwind_save does not take a register list"));
4123 ignore_rest_of_line ();
4126 input_line_pointer = peek;
4127 s_arm_unwind_save_fpa (reg->number);
4130 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4133 s_arm_unwind_save_vfp_armv6 ();
4135 s_arm_unwind_save_vfp ();
4137 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4138 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4141 as_bad (_(".unwind_save does not support this kind of register"));
4142 ignore_rest_of_line ();
4147 /* Parse an unwind_movsp directive. */
4150 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4156 if (!unwind.proc_start)
4157 as_bad (MISSING_FNSTART);
4159 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4162 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4163 ignore_rest_of_line ();
4167 /* Optional constant. */
4168 if (skip_past_comma (&input_line_pointer) != FAIL)
4170 if (immediate_for_directive (&offset) == FAIL)
4176 demand_empty_rest_of_line ();
4178 if (reg == REG_SP || reg == REG_PC)
4180 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4184 if (unwind.fp_reg != REG_SP)
4185 as_bad (_("unexpected .unwind_movsp directive"));
4187 /* Generate opcode to restore the value. */
4189 add_unwind_opcode (op, 1);
4191 /* Record the information for later. */
4192 unwind.fp_reg = reg;
4193 unwind.fp_offset = unwind.frame_size - offset;
4194 unwind.sp_restored = 1;
4197 /* Parse an unwind_pad directive. */
4200 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4204 if (!unwind.proc_start)
4205 as_bad (MISSING_FNSTART);
4207 if (immediate_for_directive (&offset) == FAIL)
4212 as_bad (_("stack increment must be multiple of 4"));
4213 ignore_rest_of_line ();
4217 /* Don't generate any opcodes, just record the details for later. */
4218 unwind.frame_size += offset;
4219 unwind.pending_offset += offset;
4221 demand_empty_rest_of_line ();
4224 /* Parse an unwind_setfp directive. */
4227 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4233 if (!unwind.proc_start)
4234 as_bad (MISSING_FNSTART);
4236 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4237 if (skip_past_comma (&input_line_pointer) == FAIL)
4240 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4242 if (fp_reg == FAIL || sp_reg == FAIL)
4244 as_bad (_("expected <reg>, <reg>"));
4245 ignore_rest_of_line ();
4249 /* Optional constant. */
4250 if (skip_past_comma (&input_line_pointer) != FAIL)
4252 if (immediate_for_directive (&offset) == FAIL)
4258 demand_empty_rest_of_line ();
4260 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4262 as_bad (_("register must be either sp or set by a previous"
4263 "unwind_movsp directive"));
4267 /* Don't generate any opcodes, just record the information for later. */
4268 unwind.fp_reg = fp_reg;
4270 if (sp_reg == REG_SP)
4271 unwind.fp_offset = unwind.frame_size - offset;
4273 unwind.fp_offset -= offset;
4276 /* Parse an unwind_raw directive. */
4279 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4282 /* This is an arbitrary limit. */
4283 unsigned char op[16];
4286 if (!unwind.proc_start)
4287 as_bad (MISSING_FNSTART);
4290 if (exp.X_op == O_constant
4291 && skip_past_comma (&input_line_pointer) != FAIL)
4293 unwind.frame_size += exp.X_add_number;
4297 exp.X_op = O_illegal;
4299 if (exp.X_op != O_constant)
4301 as_bad (_("expected <offset>, <opcode>"));
4302 ignore_rest_of_line ();
4308 /* Parse the opcode. */
4313 as_bad (_("unwind opcode too long"));
4314 ignore_rest_of_line ();
4316 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4318 as_bad (_("invalid unwind opcode"));
4319 ignore_rest_of_line ();
4322 op[count++] = exp.X_add_number;
4324 /* Parse the next byte. */
4325 if (skip_past_comma (&input_line_pointer) == FAIL)
4331 /* Add the opcode bytes in reverse order. */
4333 add_unwind_opcode (op[count], 1);
4335 demand_empty_rest_of_line ();
4339 /* Parse a .eabi_attribute directive. */
4342 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4344 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4346 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4347 attributes_set_explicitly[tag] = 1;
4350 /* Emit a tls fix for the symbol. */
4353 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4357 #ifdef md_flush_pending_output
4358 md_flush_pending_output ();
4361 #ifdef md_cons_align
4365 /* Since we're just labelling the code, there's no need to define a
4368 p = obstack_next_free (&frchain_now->frch_obstack);
4369 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4370 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4371 : BFD_RELOC_ARM_TLS_DESCSEQ);
4373 #endif /* OBJ_ELF */
4375 static void s_arm_arch (int);
4376 static void s_arm_object_arch (int);
4377 static void s_arm_cpu (int);
4378 static void s_arm_fpu (int);
4379 static void s_arm_arch_extension (int);
4384 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4391 if (exp.X_op == O_symbol)
4392 exp.X_op = O_secrel;
4394 emit_expr (&exp, 4);
4396 while (*input_line_pointer++ == ',');
4398 input_line_pointer--;
4399 demand_empty_rest_of_line ();
4403 /* This table describes all the machine specific pseudo-ops the assembler
4404 has to support. The fields are:
4405 pseudo-op name without dot
4406 function to call to execute this pseudo-op
4407 Integer arg to pass to the function. */
4409 const pseudo_typeS md_pseudo_table[] =
4411 /* Never called because '.req' does not start a line. */
4412 { "req", s_req, 0 },
4413 /* Following two are likewise never called. */
4416 { "unreq", s_unreq, 0 },
4417 { "bss", s_bss, 0 },
4418 { "align", s_align, 0 },
4419 { "arm", s_arm, 0 },
4420 { "thumb", s_thumb, 0 },
4421 { "code", s_code, 0 },
4422 { "force_thumb", s_force_thumb, 0 },
4423 { "thumb_func", s_thumb_func, 0 },
4424 { "thumb_set", s_thumb_set, 0 },
4425 { "even", s_even, 0 },
4426 { "ltorg", s_ltorg, 0 },
4427 { "pool", s_ltorg, 0 },
4428 { "syntax", s_syntax, 0 },
4429 { "cpu", s_arm_cpu, 0 },
4430 { "arch", s_arm_arch, 0 },
4431 { "object_arch", s_arm_object_arch, 0 },
4432 { "fpu", s_arm_fpu, 0 },
4433 { "arch_extension", s_arm_arch_extension, 0 },
4435 { "word", s_arm_elf_cons, 4 },
4436 { "long", s_arm_elf_cons, 4 },
4437 { "inst.n", s_arm_elf_inst, 2 },
4438 { "inst.w", s_arm_elf_inst, 4 },
4439 { "inst", s_arm_elf_inst, 0 },
4440 { "rel31", s_arm_rel31, 0 },
4441 { "fnstart", s_arm_unwind_fnstart, 0 },
4442 { "fnend", s_arm_unwind_fnend, 0 },
4443 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4444 { "personality", s_arm_unwind_personality, 0 },
4445 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4446 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4447 { "save", s_arm_unwind_save, 0 },
4448 { "vsave", s_arm_unwind_save, 1 },
4449 { "movsp", s_arm_unwind_movsp, 0 },
4450 { "pad", s_arm_unwind_pad, 0 },
4451 { "setfp", s_arm_unwind_setfp, 0 },
4452 { "unwind_raw", s_arm_unwind_raw, 0 },
4453 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4454 { "tlsdescseq", s_arm_tls_descseq, 0 },
4458 /* These are used for dwarf. */
4462 /* These are used for dwarf2. */
4463 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4464 { "loc", dwarf2_directive_loc, 0 },
4465 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4467 { "extend", float_cons, 'x' },
4468 { "ldouble", float_cons, 'x' },
4469 { "packed", float_cons, 'p' },
4471 {"secrel32", pe_directive_secrel, 0},
4476 /* Parser functions used exclusively in instruction operands. */
4478 /* Generic immediate-value read function for use in insn parsing.
4479 STR points to the beginning of the immediate (the leading #);
4480 VAL receives the value; if the value is outside [MIN, MAX]
4481 issue an error. PREFIX_OPT is true if the immediate prefix is
4485 parse_immediate (char **str, int *val, int min, int max,
4486 bfd_boolean prefix_opt)
4489 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4490 if (exp.X_op != O_constant)
4492 inst.error = _("constant expression required");
4496 if (exp.X_add_number < min || exp.X_add_number > max)
4498 inst.error = _("immediate value out of range");
4502 *val = exp.X_add_number;
4506 /* Less-generic immediate-value read function with the possibility of loading a
4507 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4508 instructions. Puts the result directly in inst.operands[i]. */
4511 parse_big_immediate (char **str, int i)
4516 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4518 if (exp.X_op == O_constant)
4520 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4521 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4522 O_constant. We have to be careful not to break compilation for
4523 32-bit X_add_number, though. */
4524 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4526 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4527 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4528 inst.operands[i].regisimm = 1;
4531 else if (exp.X_op == O_big
4532 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4534 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4536 /* Bignums have their least significant bits in
4537 generic_bignum[0]. Make sure we put 32 bits in imm and
4538 32 bits in reg, in a (hopefully) portable way. */
4539 gas_assert (parts != 0);
4541 /* Make sure that the number is not too big.
4542 PR 11972: Bignums can now be sign-extended to the
4543 size of a .octa so check that the out of range bits
4544 are all zero or all one. */
4545 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4547 LITTLENUM_TYPE m = -1;
4549 if (generic_bignum[parts * 2] != 0
4550 && generic_bignum[parts * 2] != m)
4553 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4554 if (generic_bignum[j] != generic_bignum[j-1])
4558 inst.operands[i].imm = 0;
4559 for (j = 0; j < parts; j++, idx++)
4560 inst.operands[i].imm |= generic_bignum[idx]
4561 << (LITTLENUM_NUMBER_OF_BITS * j);
4562 inst.operands[i].reg = 0;
4563 for (j = 0; j < parts; j++, idx++)
4564 inst.operands[i].reg |= generic_bignum[idx]
4565 << (LITTLENUM_NUMBER_OF_BITS * j);
4566 inst.operands[i].regisimm = 1;
4576 /* Returns the pseudo-register number of an FPA immediate constant,
4577 or FAIL if there isn't a valid constant here. */
4580 parse_fpa_immediate (char ** str)
4582 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4588 /* First try and match exact strings, this is to guarantee
4589 that some formats will work even for cross assembly. */
4591 for (i = 0; fp_const[i]; i++)
4593 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4597 *str += strlen (fp_const[i]);
4598 if (is_end_of_line[(unsigned char) **str])
4604 /* Just because we didn't get a match doesn't mean that the constant
4605 isn't valid, just that it is in a format that we don't
4606 automatically recognize. Try parsing it with the standard
4607 expression routines. */
4609 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4611 /* Look for a raw floating point number. */
4612 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4613 && is_end_of_line[(unsigned char) *save_in])
4615 for (i = 0; i < NUM_FLOAT_VALS; i++)
4617 for (j = 0; j < MAX_LITTLENUMS; j++)
4619 if (words[j] != fp_values[i][j])
4623 if (j == MAX_LITTLENUMS)
4631 /* Try and parse a more complex expression, this will probably fail
4632 unless the code uses a floating point prefix (eg "0f"). */
4633 save_in = input_line_pointer;
4634 input_line_pointer = *str;
4635 if (expression (&exp) == absolute_section
4636 && exp.X_op == O_big
4637 && exp.X_add_number < 0)
4639 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4641 if (gen_to_words (words, 5, (long) 15) == 0)
4643 for (i = 0; i < NUM_FLOAT_VALS; i++)
4645 for (j = 0; j < MAX_LITTLENUMS; j++)
4647 if (words[j] != fp_values[i][j])
4651 if (j == MAX_LITTLENUMS)
4653 *str = input_line_pointer;
4654 input_line_pointer = save_in;
4661 *str = input_line_pointer;
4662 input_line_pointer = save_in;
4663 inst.error = _("invalid FPA immediate expression");
4667 /* Returns 1 if a number has "quarter-precision" float format
4668 0baBbbbbbc defgh000 00000000 00000000. */
4671 is_quarter_float (unsigned imm)
4673 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4674 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4677 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4678 0baBbbbbbc defgh000 00000000 00000000.
4679 The zero and minus-zero cases need special handling, since they can't be
4680 encoded in the "quarter-precision" float format, but can nonetheless be
4681 loaded as integer constants. */
4684 parse_qfloat_immediate (char **ccp, int *immed)
4688 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4689 int found_fpchar = 0;
4691 skip_past_char (&str, '#');
4693 /* We must not accidentally parse an integer as a floating-point number. Make
4694 sure that the value we parse is not an integer by checking for special
4695 characters '.' or 'e'.
4696 FIXME: This is a horrible hack, but doing better is tricky because type
4697 information isn't in a very usable state at parse time. */
4699 skip_whitespace (fpnum);
4701 if (strncmp (fpnum, "0x", 2) == 0)
4705 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4706 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4716 if ((str = atof_ieee (str, 's', words)) != NULL)
4718 unsigned fpword = 0;
4721 /* Our FP word must be 32 bits (single-precision FP). */
4722 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4724 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4728 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4741 /* Shift operands. */
4744 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4747 struct asm_shift_name
4750 enum shift_kind kind;
4753 /* Third argument to parse_shift. */
4754 enum parse_shift_mode
4756 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4757 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4758 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4759 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4760 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4763 /* Parse a <shift> specifier on an ARM data processing instruction.
4764 This has three forms:
4766 (LSL|LSR|ASL|ASR|ROR) Rs
4767 (LSL|LSR|ASL|ASR|ROR) #imm
4770 Note that ASL is assimilated to LSL in the instruction encoding, and
4771 RRX to ROR #0 (which cannot be written as such). */
4774 parse_shift (char **str, int i, enum parse_shift_mode mode)
4776 const struct asm_shift_name *shift_name;
4777 enum shift_kind shift;
4782 for (p = *str; ISALPHA (*p); p++)
4787 inst.error = _("shift expression expected");
4791 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4794 if (shift_name == NULL)
4796 inst.error = _("shift expression expected");
4800 shift = shift_name->kind;
4804 case NO_SHIFT_RESTRICT:
4805 case SHIFT_IMMEDIATE: break;
4807 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4808 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4810 inst.error = _("'LSL' or 'ASR' required");
4815 case SHIFT_LSL_IMMEDIATE:
4816 if (shift != SHIFT_LSL)
4818 inst.error = _("'LSL' required");
4823 case SHIFT_ASR_IMMEDIATE:
4824 if (shift != SHIFT_ASR)
4826 inst.error = _("'ASR' required");
4834 if (shift != SHIFT_RRX)
4836 /* Whitespace can appear here if the next thing is a bare digit. */
4837 skip_whitespace (p);
4839 if (mode == NO_SHIFT_RESTRICT
4840 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4842 inst.operands[i].imm = reg;
4843 inst.operands[i].immisreg = 1;
4845 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4848 inst.operands[i].shift_kind = shift;
4849 inst.operands[i].shifted = 1;
4854 /* Parse a <shifter_operand> for an ARM data processing instruction:
4857 #<immediate>, <rotate>
4861 where <shift> is defined by parse_shift above, and <rotate> is a
4862 multiple of 2 between 0 and 30. Validation of immediate operands
4863 is deferred to md_apply_fix. */
4866 parse_shifter_operand (char **str, int i)
4871 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4873 inst.operands[i].reg = value;
4874 inst.operands[i].isreg = 1;
4876 /* parse_shift will override this if appropriate */
4877 inst.reloc.exp.X_op = O_constant;
4878 inst.reloc.exp.X_add_number = 0;
4880 if (skip_past_comma (str) == FAIL)
4883 /* Shift operation on register. */
4884 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4887 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4890 if (skip_past_comma (str) == SUCCESS)
4892 /* #x, y -- ie explicit rotation by Y. */
4893 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4896 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4898 inst.error = _("constant expression expected");
4902 value = exp.X_add_number;
4903 if (value < 0 || value > 30 || value % 2 != 0)
4905 inst.error = _("invalid rotation");
4908 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4910 inst.error = _("invalid constant");
4914 /* Encode as specified. */
4915 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4919 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4920 inst.reloc.pc_rel = 0;
4924 /* Group relocation information. Each entry in the table contains the
4925 textual name of the relocation as may appear in assembler source
4926 and must end with a colon.
4927 Along with this textual name are the relocation codes to be used if
4928 the corresponding instruction is an ALU instruction (ADD or SUB only),
4929 an LDR, an LDRS, or an LDC. */
4931 struct group_reloc_table_entry
4942 /* Varieties of non-ALU group relocation. */
4949 static struct group_reloc_table_entry group_reloc_table[] =
4950 { /* Program counter relative: */
4952 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4957 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4958 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4959 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4960 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4962 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4967 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4968 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4969 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4970 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4972 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4973 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4974 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4975 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4976 /* Section base relative */
4978 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4983 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4984 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4985 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4986 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4988 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4993 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4994 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4995 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4996 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4998 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4999 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5000 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5001 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5003 /* Given the address of a pointer pointing to the textual name of a group
5004 relocation as may appear in assembler source, attempt to find its details
5005 in group_reloc_table. The pointer will be updated to the character after
5006 the trailing colon. On failure, FAIL will be returned; SUCCESS
5007 otherwise. On success, *entry will be updated to point at the relevant
5008 group_reloc_table entry. */
5011 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5014 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5016 int length = strlen (group_reloc_table[i].name);
5018 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5019 && (*str)[length] == ':')
5021 *out = &group_reloc_table[i];
5022 *str += (length + 1);
5030 /* Parse a <shifter_operand> for an ARM data processing instruction
5031 (as for parse_shifter_operand) where group relocations are allowed:
5034 #<immediate>, <rotate>
5035 #:<group_reloc>:<expression>
5039 where <group_reloc> is one of the strings defined in group_reloc_table.
5040 The hashes are optional.
5042 Everything else is as for parse_shifter_operand. */
5044 static parse_operand_result
5045 parse_shifter_operand_group_reloc (char **str, int i)
5047 /* Determine if we have the sequence of characters #: or just :
5048 coming next. If we do, then we check for a group relocation.
5049 If we don't, punt the whole lot to parse_shifter_operand. */
5051 if (((*str)[0] == '#' && (*str)[1] == ':')
5052 || (*str)[0] == ':')
5054 struct group_reloc_table_entry *entry;
5056 if ((*str)[0] == '#')
5061 /* Try to parse a group relocation. Anything else is an error. */
5062 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5064 inst.error = _("unknown group relocation");
5065 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5068 /* We now have the group relocation table entry corresponding to
5069 the name in the assembler source. Next, we parse the expression. */
5070 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5071 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5073 /* Record the relocation type (always the ALU variant here). */
5074 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5075 gas_assert (inst.reloc.type != 0);
5077 return PARSE_OPERAND_SUCCESS;
5080 return parse_shifter_operand (str, i) == SUCCESS
5081 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5083 /* Never reached. */
5086 /* Parse a Neon alignment expression. Information is written to
5087 inst.operands[i]. We assume the initial ':' has been skipped.
5089 align .imm = align << 8, .immisalign=1, .preind=0 */
5090 static parse_operand_result
5091 parse_neon_alignment (char **str, int i)
5096 my_get_expression (&exp, &p, GE_NO_PREFIX);
5098 if (exp.X_op != O_constant)
5100 inst.error = _("alignment must be constant");
5101 return PARSE_OPERAND_FAIL;
5104 inst.operands[i].imm = exp.X_add_number << 8;
5105 inst.operands[i].immisalign = 1;
5106 /* Alignments are not pre-indexes. */
5107 inst.operands[i].preind = 0;
5110 return PARSE_OPERAND_SUCCESS;
5113 /* Parse all forms of an ARM address expression. Information is written
5114 to inst.operands[i] and/or inst.reloc.
5116 Preindexed addressing (.preind=1):
5118 [Rn, #offset] .reg=Rn .reloc.exp=offset
5119 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5120 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5121 .shift_kind=shift .reloc.exp=shift_imm
5123 These three may have a trailing ! which causes .writeback to be set also.
5125 Postindexed addressing (.postind=1, .writeback=1):
5127 [Rn], #offset .reg=Rn .reloc.exp=offset
5128 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5129 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5130 .shift_kind=shift .reloc.exp=shift_imm
5132 Unindexed addressing (.preind=0, .postind=0):
5134 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5138 [Rn]{!} shorthand for [Rn,#0]{!}
5139 =immediate .isreg=0 .reloc.exp=immediate
5140 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5142 It is the caller's responsibility to check for addressing modes not
5143 supported by the instruction, and to set inst.reloc.type. */
5145 static parse_operand_result
5146 parse_address_main (char **str, int i, int group_relocations,
5147 group_reloc_type group_type)
5152 if (skip_past_char (&p, '[') == FAIL)
5154 if (skip_past_char (&p, '=') == FAIL)
5156 /* Bare address - translate to PC-relative offset. */
5157 inst.reloc.pc_rel = 1;
5158 inst.operands[i].reg = REG_PC;
5159 inst.operands[i].isreg = 1;
5160 inst.operands[i].preind = 1;
5162 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5164 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5165 return PARSE_OPERAND_FAIL;
5168 return PARSE_OPERAND_SUCCESS;
5171 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5173 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5174 return PARSE_OPERAND_FAIL;
5176 inst.operands[i].reg = reg;
5177 inst.operands[i].isreg = 1;
5179 if (skip_past_comma (&p) == SUCCESS)
5181 inst.operands[i].preind = 1;
5184 else if (*p == '-') p++, inst.operands[i].negative = 1;
5186 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5188 inst.operands[i].imm = reg;
5189 inst.operands[i].immisreg = 1;
5191 if (skip_past_comma (&p) == SUCCESS)
5192 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5193 return PARSE_OPERAND_FAIL;
5195 else if (skip_past_char (&p, ':') == SUCCESS)
5197 /* FIXME: '@' should be used here, but it's filtered out by generic
5198 code before we get to see it here. This may be subject to
5200 parse_operand_result result = parse_neon_alignment (&p, i);
5202 if (result != PARSE_OPERAND_SUCCESS)
5207 if (inst.operands[i].negative)
5209 inst.operands[i].negative = 0;
5213 if (group_relocations
5214 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5216 struct group_reloc_table_entry *entry;
5218 /* Skip over the #: or : sequence. */
5224 /* Try to parse a group relocation. Anything else is an
5226 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5228 inst.error = _("unknown group relocation");
5229 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5232 /* We now have the group relocation table entry corresponding to
5233 the name in the assembler source. Next, we parse the
5235 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5236 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5238 /* Record the relocation type. */
5242 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5246 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5250 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5257 if (inst.reloc.type == 0)
5259 inst.error = _("this group relocation is not allowed on this instruction");
5260 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5266 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5267 return PARSE_OPERAND_FAIL;
5268 /* If the offset is 0, find out if it's a +0 or -0. */
5269 if (inst.reloc.exp.X_op == O_constant
5270 && inst.reloc.exp.X_add_number == 0)
5272 skip_whitespace (q);
5276 skip_whitespace (q);
5279 inst.operands[i].negative = 1;
5284 else if (skip_past_char (&p, ':') == SUCCESS)
5286 /* FIXME: '@' should be used here, but it's filtered out by generic code
5287 before we get to see it here. This may be subject to change. */
5288 parse_operand_result result = parse_neon_alignment (&p, i);
5290 if (result != PARSE_OPERAND_SUCCESS)
5294 /* PR gas/14987: Allow for whitespace before the closing bracket. */
5295 skip_whitespace (p);
5297 if (skip_past_char (&p, ']') == FAIL)
5299 inst.error = _("']' expected");
5300 return PARSE_OPERAND_FAIL;
5303 if (skip_past_char (&p, '!') == SUCCESS)
5304 inst.operands[i].writeback = 1;
5306 else if (skip_past_comma (&p) == SUCCESS)
5308 if (skip_past_char (&p, '{') == SUCCESS)
5310 /* [Rn], {expr} - unindexed, with option */
5311 if (parse_immediate (&p, &inst.operands[i].imm,
5312 0, 255, TRUE) == FAIL)
5313 return PARSE_OPERAND_FAIL;
5315 if (skip_past_char (&p, '}') == FAIL)
5317 inst.error = _("'}' expected at end of 'option' field");
5318 return PARSE_OPERAND_FAIL;
5320 if (inst.operands[i].preind)
5322 inst.error = _("cannot combine index with option");
5323 return PARSE_OPERAND_FAIL;
5326 return PARSE_OPERAND_SUCCESS;
5330 inst.operands[i].postind = 1;
5331 inst.operands[i].writeback = 1;
5333 if (inst.operands[i].preind)
5335 inst.error = _("cannot combine pre- and post-indexing");
5336 return PARSE_OPERAND_FAIL;
5340 else if (*p == '-') p++, inst.operands[i].negative = 1;
5342 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5344 /* We might be using the immediate for alignment already. If we
5345 are, OR the register number into the low-order bits. */
5346 if (inst.operands[i].immisalign)
5347 inst.operands[i].imm |= reg;
5349 inst.operands[i].imm = reg;
5350 inst.operands[i].immisreg = 1;
5352 if (skip_past_comma (&p) == SUCCESS)
5353 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5354 return PARSE_OPERAND_FAIL;
5359 if (inst.operands[i].negative)
5361 inst.operands[i].negative = 0;
5364 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5365 return PARSE_OPERAND_FAIL;
5366 /* If the offset is 0, find out if it's a +0 or -0. */
5367 if (inst.reloc.exp.X_op == O_constant
5368 && inst.reloc.exp.X_add_number == 0)
5370 skip_whitespace (q);
5374 skip_whitespace (q);
5377 inst.operands[i].negative = 1;
5383 /* If at this point neither .preind nor .postind is set, we have a
5384 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5385 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5387 inst.operands[i].preind = 1;
5388 inst.reloc.exp.X_op = O_constant;
5389 inst.reloc.exp.X_add_number = 0;
5392 return PARSE_OPERAND_SUCCESS;
5396 parse_address (char **str, int i)
5398 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5402 static parse_operand_result
5403 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5405 return parse_address_main (str, i, 1, type);
5408 /* Parse an operand for a MOVW or MOVT instruction. */
5410 parse_half (char **str)
5415 skip_past_char (&p, '#');
5416 if (strncasecmp (p, ":lower16:", 9) == 0)
5417 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5418 else if (strncasecmp (p, ":upper16:", 9) == 0)
5419 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5421 if (inst.reloc.type != BFD_RELOC_UNUSED)
5424 skip_whitespace (p);
5427 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5430 if (inst.reloc.type == BFD_RELOC_UNUSED)
5432 if (inst.reloc.exp.X_op != O_constant)
5434 inst.error = _("constant expression expected");
5437 if (inst.reloc.exp.X_add_number < 0
5438 || inst.reloc.exp.X_add_number > 0xffff)
5440 inst.error = _("immediate value out of range");
5448 /* Miscellaneous. */
5450 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5451 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5453 parse_psr (char **str, bfd_boolean lhs)
5456 unsigned long psr_field;
5457 const struct asm_psr *psr;
5459 bfd_boolean is_apsr = FALSE;
5460 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5462 /* PR gas/12698: If the user has specified -march=all then m_profile will
5463 be TRUE, but we want to ignore it in this case as we are building for any
5464 CPU type, including non-m variants. */
5465 if (selected_cpu.core == arm_arch_any.core)
5468 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5469 feature for ease of use and backwards compatibility. */
5471 if (strncasecmp (p, "SPSR", 4) == 0)
5474 goto unsupported_psr;
5476 psr_field = SPSR_BIT;
5478 else if (strncasecmp (p, "CPSR", 4) == 0)
5481 goto unsupported_psr;
5485 else if (strncasecmp (p, "APSR", 4) == 0)
5487 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5488 and ARMv7-R architecture CPUs. */
5497 while (ISALNUM (*p) || *p == '_');
5499 if (strncasecmp (start, "iapsr", 5) == 0
5500 || strncasecmp (start, "eapsr", 5) == 0
5501 || strncasecmp (start, "xpsr", 4) == 0
5502 || strncasecmp (start, "psr", 3) == 0)
5503 p = start + strcspn (start, "rR") + 1;
5505 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5511 /* If APSR is being written, a bitfield may be specified. Note that
5512 APSR itself is handled above. */
5513 if (psr->field <= 3)
5515 psr_field = psr->field;
5521 /* M-profile MSR instructions have the mask field set to "10", except
5522 *PSR variants which modify APSR, which may use a different mask (and
5523 have been handled already). Do that by setting the PSR_f field
5525 return psr->field | (lhs ? PSR_f : 0);
5528 goto unsupported_psr;
5534 /* A suffix follows. */
5540 while (ISALNUM (*p) || *p == '_');
5544 /* APSR uses a notation for bits, rather than fields. */
5545 unsigned int nzcvq_bits = 0;
5546 unsigned int g_bit = 0;
5549 for (bit = start; bit != p; bit++)
5551 switch (TOLOWER (*bit))
5554 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5558 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5562 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5566 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5570 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5574 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5578 inst.error = _("unexpected bit specified after APSR");
5583 if (nzcvq_bits == 0x1f)
5588 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5590 inst.error = _("selected processor does not "
5591 "support DSP extension");
5598 if ((nzcvq_bits & 0x20) != 0
5599 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5600 || (g_bit & 0x2) != 0)
5602 inst.error = _("bad bitmask specified after APSR");
5608 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5613 psr_field |= psr->field;
5619 goto error; /* Garbage after "[CS]PSR". */
5621 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5622 is deprecated, but allow it anyway. */
5626 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5629 else if (!m_profile)
5630 /* These bits are never right for M-profile devices: don't set them
5631 (only code paths which read/write APSR reach here). */
5632 psr_field |= (PSR_c | PSR_f);
5638 inst.error = _("selected processor does not support requested special "
5639 "purpose register");
5643 inst.error = _("flag for {c}psr instruction expected");
5647 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5648 value suitable for splatting into the AIF field of the instruction. */
5651 parse_cps_flags (char **str)
5660 case '\0': case ',':
5663 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5664 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5665 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5668 inst.error = _("unrecognized CPS flag");
5673 if (saw_a_flag == 0)
5675 inst.error = _("missing CPS flags");
5683 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5684 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5687 parse_endian_specifier (char **str)
5692 if (strncasecmp (s, "BE", 2))
5694 else if (strncasecmp (s, "LE", 2))
5698 inst.error = _("valid endian specifiers are be or le");
5702 if (ISALNUM (s[2]) || s[2] == '_')
5704 inst.error = _("valid endian specifiers are be or le");
5709 return little_endian;
5712 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5713 value suitable for poking into the rotate field of an sxt or sxta
5714 instruction, or FAIL on error. */
5717 parse_ror (char **str)
5722 if (strncasecmp (s, "ROR", 3) == 0)
5726 inst.error = _("missing rotation field after comma");
5730 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5735 case 0: *str = s; return 0x0;
5736 case 8: *str = s; return 0x1;
5737 case 16: *str = s; return 0x2;
5738 case 24: *str = s; return 0x3;
5741 inst.error = _("rotation can only be 0, 8, 16, or 24");
5746 /* Parse a conditional code (from conds[] below). The value returned is in the
5747 range 0 .. 14, or FAIL. */
5749 parse_cond (char **str)
5752 const struct asm_cond *c;
5754 /* Condition codes are always 2 characters, so matching up to
5755 3 characters is sufficient. */
5760 while (ISALPHA (*q) && n < 3)
5762 cond[n] = TOLOWER (*q);
5767 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5770 inst.error = _("condition required");
5778 /* If the given feature available in the selected CPU, mark it as used.
5779 Returns TRUE iff feature is available. */
5781 mark_feature_used (const arm_feature_set *feature)
5783 /* Ensure the option is valid on the current architecture. */
5784 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5787 /* Add the appropriate architecture feature for the barrier option used.
5790 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5792 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5797 /* Parse an option for a barrier instruction. Returns the encoding for the
5800 parse_barrier (char **str)
5803 const struct asm_barrier_opt *o;
5806 while (ISALPHA (*q))
5809 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5814 if (!mark_feature_used (&o->arch))
5821 /* Parse the operands of a table branch instruction. Similar to a memory
5824 parse_tb (char **str)
5829 if (skip_past_char (&p, '[') == FAIL)
5831 inst.error = _("'[' expected");
5835 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5837 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5840 inst.operands[0].reg = reg;
5842 if (skip_past_comma (&p) == FAIL)
5844 inst.error = _("',' expected");
5848 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5850 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5853 inst.operands[0].imm = reg;
5855 if (skip_past_comma (&p) == SUCCESS)
5857 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5859 if (inst.reloc.exp.X_add_number != 1)
5861 inst.error = _("invalid shift");
5864 inst.operands[0].shifted = 1;
5867 if (skip_past_char (&p, ']') == FAIL)
5869 inst.error = _("']' expected");
5876 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5877 information on the types the operands can take and how they are encoded.
5878 Up to four operands may be read; this function handles setting the
5879 ".present" field for each read operand itself.
5880 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5881 else returns FAIL. */
5884 parse_neon_mov (char **str, int *which_operand)
5886 int i = *which_operand, val;
5887 enum arm_reg_type rtype;
5889 struct neon_type_el optype;
5891 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5893 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5894 inst.operands[i].reg = val;
5895 inst.operands[i].isscalar = 1;
5896 inst.operands[i].vectype = optype;
5897 inst.operands[i++].present = 1;
5899 if (skip_past_comma (&ptr) == FAIL)
5902 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5905 inst.operands[i].reg = val;
5906 inst.operands[i].isreg = 1;
5907 inst.operands[i].present = 1;
5909 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5912 /* Cases 0, 1, 2, 3, 5 (D only). */
5913 if (skip_past_comma (&ptr) == FAIL)
5916 inst.operands[i].reg = val;
5917 inst.operands[i].isreg = 1;
5918 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5919 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5920 inst.operands[i].isvec = 1;
5921 inst.operands[i].vectype = optype;
5922 inst.operands[i++].present = 1;
5924 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5926 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5927 Case 13: VMOV <Sd>, <Rm> */
5928 inst.operands[i].reg = val;
5929 inst.operands[i].isreg = 1;
5930 inst.operands[i].present = 1;
5932 if (rtype == REG_TYPE_NQ)
5934 first_error (_("can't use Neon quad register here"));
5937 else if (rtype != REG_TYPE_VFS)
5940 if (skip_past_comma (&ptr) == FAIL)
5942 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5944 inst.operands[i].reg = val;
5945 inst.operands[i].isreg = 1;
5946 inst.operands[i].present = 1;
5949 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5952 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5953 Case 1: VMOV<c><q> <Dd>, <Dm>
5954 Case 8: VMOV.F32 <Sd>, <Sm>
5955 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5957 inst.operands[i].reg = val;
5958 inst.operands[i].isreg = 1;
5959 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5960 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5961 inst.operands[i].isvec = 1;
5962 inst.operands[i].vectype = optype;
5963 inst.operands[i].present = 1;
5965 if (skip_past_comma (&ptr) == SUCCESS)
5970 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5973 inst.operands[i].reg = val;
5974 inst.operands[i].isreg = 1;
5975 inst.operands[i++].present = 1;
5977 if (skip_past_comma (&ptr) == FAIL)
5980 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5983 inst.operands[i].reg = val;
5984 inst.operands[i].isreg = 1;
5985 inst.operands[i].present = 1;
5988 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5989 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5990 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5991 Case 10: VMOV.F32 <Sd>, #<imm>
5992 Case 11: VMOV.F64 <Dd>, #<imm> */
5993 inst.operands[i].immisfloat = 1;
5994 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5995 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5996 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6000 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6004 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6007 inst.operands[i].reg = val;
6008 inst.operands[i].isreg = 1;
6009 inst.operands[i++].present = 1;
6011 if (skip_past_comma (&ptr) == FAIL)
6014 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6016 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6017 inst.operands[i].reg = val;
6018 inst.operands[i].isscalar = 1;
6019 inst.operands[i].present = 1;
6020 inst.operands[i].vectype = optype;
6022 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6024 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6025 inst.operands[i].reg = val;
6026 inst.operands[i].isreg = 1;
6027 inst.operands[i++].present = 1;
6029 if (skip_past_comma (&ptr) == FAIL)
6032 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6035 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6039 inst.operands[i].reg = val;
6040 inst.operands[i].isreg = 1;
6041 inst.operands[i].isvec = 1;
6042 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6043 inst.operands[i].vectype = optype;
6044 inst.operands[i].present = 1;
6046 if (rtype == REG_TYPE_VFS)
6050 if (skip_past_comma (&ptr) == FAIL)
6052 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6055 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6058 inst.operands[i].reg = val;
6059 inst.operands[i].isreg = 1;
6060 inst.operands[i].isvec = 1;
6061 inst.operands[i].issingle = 1;
6062 inst.operands[i].vectype = optype;
6063 inst.operands[i].present = 1;
6066 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6070 inst.operands[i].reg = val;
6071 inst.operands[i].isreg = 1;
6072 inst.operands[i].isvec = 1;
6073 inst.operands[i].issingle = 1;
6074 inst.operands[i].vectype = optype;
6075 inst.operands[i].present = 1;
6080 first_error (_("parse error"));
6084 /* Successfully parsed the operands. Update args. */
6090 first_error (_("expected comma"));
6094 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6098 /* Use this macro when the operand constraints are different
6099 for ARM and THUMB (e.g. ldrd). */
6100 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6101 ((arm_operand) | ((thumb_operand) << 16))
6103 /* Matcher codes for parse_operands. */
6104 enum operand_parse_code
6106 OP_stop, /* end of line */
6108 OP_RR, /* ARM register */
6109 OP_RRnpc, /* ARM register, not r15 */
6110 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6111 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6112 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6113 optional trailing ! */
6114 OP_RRw, /* ARM register, not r15, optional trailing ! */
6115 OP_RCP, /* Coprocessor number */
6116 OP_RCN, /* Coprocessor register */
6117 OP_RF, /* FPA register */
6118 OP_RVS, /* VFP single precision register */
6119 OP_RVD, /* VFP double precision register (0..15) */
6120 OP_RND, /* Neon double precision register (0..31) */
6121 OP_RNQ, /* Neon quad precision register */
6122 OP_RVSD, /* VFP single or double precision register */
6123 OP_RNDQ, /* Neon double or quad precision register */
6124 OP_RNSDQ, /* Neon single, double or quad precision register */
6125 OP_RNSC, /* Neon scalar D[X] */
6126 OP_RVC, /* VFP control register */
6127 OP_RMF, /* Maverick F register */
6128 OP_RMD, /* Maverick D register */
6129 OP_RMFX, /* Maverick FX register */
6130 OP_RMDX, /* Maverick DX register */
6131 OP_RMAX, /* Maverick AX register */
6132 OP_RMDS, /* Maverick DSPSC register */
6133 OP_RIWR, /* iWMMXt wR register */
6134 OP_RIWC, /* iWMMXt wC register */
6135 OP_RIWG, /* iWMMXt wCG register */
6136 OP_RXA, /* XScale accumulator register */
6138 OP_REGLST, /* ARM register list */
6139 OP_VRSLST, /* VFP single-precision register list */
6140 OP_VRDLST, /* VFP double-precision register list */
6141 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6142 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6143 OP_NSTRLST, /* Neon element/structure list */
6145 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6146 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6147 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6148 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6149 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6150 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6151 OP_VMOV, /* Neon VMOV operands. */
6152 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6153 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6154 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6156 OP_I0, /* immediate zero */
6157 OP_I7, /* immediate value 0 .. 7 */
6158 OP_I15, /* 0 .. 15 */
6159 OP_I16, /* 1 .. 16 */
6160 OP_I16z, /* 0 .. 16 */
6161 OP_I31, /* 0 .. 31 */
6162 OP_I31w, /* 0 .. 31, optional trailing ! */
6163 OP_I32, /* 1 .. 32 */
6164 OP_I32z, /* 0 .. 32 */
6165 OP_I63, /* 0 .. 63 */
6166 OP_I63s, /* -64 .. 63 */
6167 OP_I64, /* 1 .. 64 */
6168 OP_I64z, /* 0 .. 64 */
6169 OP_I255, /* 0 .. 255 */
6171 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6172 OP_I7b, /* 0 .. 7 */
6173 OP_I15b, /* 0 .. 15 */
6174 OP_I31b, /* 0 .. 31 */
6176 OP_SH, /* shifter operand */
6177 OP_SHG, /* shifter operand with possible group relocation */
6178 OP_ADDR, /* Memory address expression (any mode) */
6179 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6180 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6181 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6182 OP_EXP, /* arbitrary expression */
6183 OP_EXPi, /* same, with optional immediate prefix */
6184 OP_EXPr, /* same, with optional relocation suffix */
6185 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6187 OP_CPSF, /* CPS flags */
6188 OP_ENDI, /* Endianness specifier */
6189 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6190 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6191 OP_COND, /* conditional code */
6192 OP_TB, /* Table branch. */
6194 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6196 OP_RRnpc_I0, /* ARM register or literal 0 */
6197 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6198 OP_RR_EXi, /* ARM register or expression with imm prefix */
6199 OP_RF_IF, /* FPA register or immediate */
6200 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6201 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6203 /* Optional operands. */
6204 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6205 OP_oI31b, /* 0 .. 31 */
6206 OP_oI32b, /* 1 .. 32 */
6207 OP_oI32z, /* 0 .. 32 */
6208 OP_oIffffb, /* 0 .. 65535 */
6209 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6211 OP_oRR, /* ARM register */
6212 OP_oRRnpc, /* ARM register, not the PC */
6213 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6214 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6215 OP_oRND, /* Optional Neon double precision register */
6216 OP_oRNQ, /* Optional Neon quad precision register */
6217 OP_oRNDQ, /* Optional Neon double or quad precision register */
6218 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6219 OP_oSHll, /* LSL immediate */
6220 OP_oSHar, /* ASR immediate */
6221 OP_oSHllar, /* LSL or ASR immediate */
6222 OP_oROR, /* ROR 0/8/16/24 */
6223 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6225 /* Some pre-defined mixed (ARM/THUMB) operands. */
6226 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6227 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6228 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6230 OP_FIRST_OPTIONAL = OP_oI7b
6233 /* Generic instruction operand parser. This does no encoding and no
6234 semantic validation; it merely squirrels values away in the inst
6235 structure. Returns SUCCESS or FAIL depending on whether the
6236 specified grammar matched. */
6238 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6240 unsigned const int *upat = pattern;
6241 char *backtrack_pos = 0;
6242 const char *backtrack_error = 0;
6243 int i, val = 0, backtrack_index = 0;
6244 enum arm_reg_type rtype;
6245 parse_operand_result result;
6246 unsigned int op_parse_code;
6248 #define po_char_or_fail(chr) \
6251 if (skip_past_char (&str, chr) == FAIL) \
6256 #define po_reg_or_fail(regtype) \
6259 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6260 & inst.operands[i].vectype); \
6263 first_error (_(reg_expected_msgs[regtype])); \
6266 inst.operands[i].reg = val; \
6267 inst.operands[i].isreg = 1; \
6268 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6269 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6270 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6271 || rtype == REG_TYPE_VFD \
6272 || rtype == REG_TYPE_NQ); \
6276 #define po_reg_or_goto(regtype, label) \
6279 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6280 & inst.operands[i].vectype); \
6284 inst.operands[i].reg = val; \
6285 inst.operands[i].isreg = 1; \
6286 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6287 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6288 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6289 || rtype == REG_TYPE_VFD \
6290 || rtype == REG_TYPE_NQ); \
6294 #define po_imm_or_fail(min, max, popt) \
6297 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6299 inst.operands[i].imm = val; \
6303 #define po_scalar_or_goto(elsz, label) \
6306 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6309 inst.operands[i].reg = val; \
6310 inst.operands[i].isscalar = 1; \
6314 #define po_misc_or_fail(expr) \
6322 #define po_misc_or_fail_no_backtrack(expr) \
6326 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6327 backtrack_pos = 0; \
6328 if (result != PARSE_OPERAND_SUCCESS) \
6333 #define po_barrier_or_imm(str) \
6336 val = parse_barrier (&str); \
6339 if (ISALPHA (*str)) \
6346 if ((inst.instruction & 0xf0) == 0x60 \
6349 /* ISB can only take SY as an option. */ \
6350 inst.error = _("invalid barrier type"); \
6357 skip_whitespace (str);
6359 for (i = 0; upat[i] != OP_stop; i++)
6361 op_parse_code = upat[i];
6362 if (op_parse_code >= 1<<16)
6363 op_parse_code = thumb ? (op_parse_code >> 16)
6364 : (op_parse_code & ((1<<16)-1));
6366 if (op_parse_code >= OP_FIRST_OPTIONAL)
6368 /* Remember where we are in case we need to backtrack. */
6369 gas_assert (!backtrack_pos);
6370 backtrack_pos = str;
6371 backtrack_error = inst.error;
6372 backtrack_index = i;
6375 if (i > 0 && (i > 1 || inst.operands[0].present))
6376 po_char_or_fail (',');
6378 switch (op_parse_code)
6386 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6387 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6388 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6389 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6390 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6391 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6393 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6395 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6397 /* Also accept generic coprocessor regs for unknown registers. */
6399 po_reg_or_fail (REG_TYPE_CN);
6401 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6402 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6403 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6404 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6405 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6406 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6407 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6408 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6409 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6410 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6412 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6414 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6415 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6417 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6419 /* Neon scalar. Using an element size of 8 means that some invalid
6420 scalars are accepted here, so deal with those in later code. */
6421 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6425 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6428 po_imm_or_fail (0, 0, TRUE);
6433 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6438 po_scalar_or_goto (8, try_rr);
6441 po_reg_or_fail (REG_TYPE_RN);
6447 po_scalar_or_goto (8, try_nsdq);
6450 po_reg_or_fail (REG_TYPE_NSDQ);
6456 po_scalar_or_goto (8, try_ndq);
6459 po_reg_or_fail (REG_TYPE_NDQ);
6465 po_scalar_or_goto (8, try_vfd);
6468 po_reg_or_fail (REG_TYPE_VFD);
6473 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6474 not careful then bad things might happen. */
6475 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6480 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6483 /* There's a possibility of getting a 64-bit immediate here, so
6484 we need special handling. */
6485 if (parse_big_immediate (&str, i) == FAIL)
6487 inst.error = _("immediate value is out of range");
6495 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6498 po_imm_or_fail (0, 63, TRUE);
6503 po_char_or_fail ('[');
6504 po_reg_or_fail (REG_TYPE_RN);
6505 po_char_or_fail (']');
6511 po_reg_or_fail (REG_TYPE_RN);
6512 if (skip_past_char (&str, '!') == SUCCESS)
6513 inst.operands[i].writeback = 1;
6517 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6518 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6519 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6520 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6521 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6522 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6523 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6524 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6525 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6526 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6527 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6528 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6530 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6532 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6533 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6535 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6536 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6537 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6538 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6540 /* Immediate variants */
6542 po_char_or_fail ('{');
6543 po_imm_or_fail (0, 255, TRUE);
6544 po_char_or_fail ('}');
6548 /* The expression parser chokes on a trailing !, so we have
6549 to find it first and zap it. */
6552 while (*s && *s != ',')
6557 inst.operands[i].writeback = 1;
6559 po_imm_or_fail (0, 31, TRUE);
6567 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6572 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6577 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6579 if (inst.reloc.exp.X_op == O_symbol)
6581 val = parse_reloc (&str);
6584 inst.error = _("unrecognized relocation suffix");
6587 else if (val != BFD_RELOC_UNUSED)
6589 inst.operands[i].imm = val;
6590 inst.operands[i].hasreloc = 1;
6595 /* Operand for MOVW or MOVT. */
6597 po_misc_or_fail (parse_half (&str));
6600 /* Register or expression. */
6601 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6602 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6604 /* Register or immediate. */
6605 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6606 I0: po_imm_or_fail (0, 0, FALSE); break;
6608 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6610 if (!is_immediate_prefix (*str))
6613 val = parse_fpa_immediate (&str);
6616 /* FPA immediates are encoded as registers 8-15.
6617 parse_fpa_immediate has already applied the offset. */
6618 inst.operands[i].reg = val;
6619 inst.operands[i].isreg = 1;
6622 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6623 I32z: po_imm_or_fail (0, 32, FALSE); break;
6625 /* Two kinds of register. */
6628 struct reg_entry *rege = arm_reg_parse_multi (&str);
6630 || (rege->type != REG_TYPE_MMXWR
6631 && rege->type != REG_TYPE_MMXWC
6632 && rege->type != REG_TYPE_MMXWCG))
6634 inst.error = _("iWMMXt data or control register expected");
6637 inst.operands[i].reg = rege->number;
6638 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6644 struct reg_entry *rege = arm_reg_parse_multi (&str);
6646 || (rege->type != REG_TYPE_MMXWC
6647 && rege->type != REG_TYPE_MMXWCG))
6649 inst.error = _("iWMMXt control register expected");
6652 inst.operands[i].reg = rege->number;
6653 inst.operands[i].isreg = 1;
6658 case OP_CPSF: val = parse_cps_flags (&str); break;
6659 case OP_ENDI: val = parse_endian_specifier (&str); break;
6660 case OP_oROR: val = parse_ror (&str); break;
6661 case OP_COND: val = parse_cond (&str); break;
6662 case OP_oBARRIER_I15:
6663 po_barrier_or_imm (str); break;
6665 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6671 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6672 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6674 inst.error = _("Banked registers are not available with this "
6680 val = parse_psr (&str, op_parse_code == OP_wPSR);
6684 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6687 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6689 if (strncasecmp (str, "APSR_", 5) == 0)
6696 case 'c': found = (found & 1) ? 16 : found | 1; break;
6697 case 'n': found = (found & 2) ? 16 : found | 2; break;
6698 case 'z': found = (found & 4) ? 16 : found | 4; break;
6699 case 'v': found = (found & 8) ? 16 : found | 8; break;
6700 default: found = 16;
6704 inst.operands[i].isvec = 1;
6705 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6706 inst.operands[i].reg = REG_PC;
6713 po_misc_or_fail (parse_tb (&str));
6716 /* Register lists. */
6718 val = parse_reg_list (&str);
6721 inst.operands[1].writeback = 1;
6727 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6731 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6735 /* Allow Q registers too. */
6736 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6741 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6743 inst.operands[i].issingle = 1;
6748 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6753 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6754 &inst.operands[i].vectype);
6757 /* Addressing modes */
6759 po_misc_or_fail (parse_address (&str, i));
6763 po_misc_or_fail_no_backtrack (
6764 parse_address_group_reloc (&str, i, GROUP_LDR));
6768 po_misc_or_fail_no_backtrack (
6769 parse_address_group_reloc (&str, i, GROUP_LDRS));
6773 po_misc_or_fail_no_backtrack (
6774 parse_address_group_reloc (&str, i, GROUP_LDC));
6778 po_misc_or_fail (parse_shifter_operand (&str, i));
6782 po_misc_or_fail_no_backtrack (
6783 parse_shifter_operand_group_reloc (&str, i));
6787 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6791 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6795 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6799 as_fatal (_("unhandled operand code %d"), op_parse_code);
6802 /* Various value-based sanity checks and shared operations. We
6803 do not signal immediate failures for the register constraints;
6804 this allows a syntax error to take precedence. */
6805 switch (op_parse_code)
6813 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6814 inst.error = BAD_PC;
6819 if (inst.operands[i].isreg)
6821 if (inst.operands[i].reg == REG_PC)
6822 inst.error = BAD_PC;
6823 else if (inst.operands[i].reg == REG_SP)
6824 inst.error = BAD_SP;
6829 if (inst.operands[i].isreg
6830 && inst.operands[i].reg == REG_PC
6831 && (inst.operands[i].writeback || thumb))
6832 inst.error = BAD_PC;
6841 case OP_oBARRIER_I15:
6850 inst.operands[i].imm = val;
6857 /* If we get here, this operand was successfully parsed. */
6858 inst.operands[i].present = 1;
6862 inst.error = BAD_ARGS;
6867 /* The parse routine should already have set inst.error, but set a
6868 default here just in case. */
6870 inst.error = _("syntax error");
6874 /* Do not backtrack over a trailing optional argument that
6875 absorbed some text. We will only fail again, with the
6876 'garbage following instruction' error message, which is
6877 probably less helpful than the current one. */
6878 if (backtrack_index == i && backtrack_pos != str
6879 && upat[i+1] == OP_stop)
6882 inst.error = _("syntax error");
6886 /* Try again, skipping the optional argument at backtrack_pos. */
6887 str = backtrack_pos;
6888 inst.error = backtrack_error;
6889 inst.operands[backtrack_index].present = 0;
6890 i = backtrack_index;
6894 /* Check that we have parsed all the arguments. */
6895 if (*str != '\0' && !inst.error)
6896 inst.error = _("garbage following instruction");
6898 return inst.error ? FAIL : SUCCESS;
6901 #undef po_char_or_fail
6902 #undef po_reg_or_fail
6903 #undef po_reg_or_goto
6904 #undef po_imm_or_fail
6905 #undef po_scalar_or_fail
6906 #undef po_barrier_or_imm
6908 /* Shorthand macro for instruction encoding functions issuing errors. */
6909 #define constraint(expr, err) \
6920 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6921 instructions are unpredictable if these registers are used. This
6922 is the BadReg predicate in ARM's Thumb-2 documentation. */
6923 #define reject_bad_reg(reg) \
6925 if (reg == REG_SP || reg == REG_PC) \
6927 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6932 /* If REG is R13 (the stack pointer), warn that its use is
6934 #define warn_deprecated_sp(reg) \
6936 if (warn_on_deprecated && reg == REG_SP) \
6937 as_warn (_("use of r13 is deprecated")); \
6940 /* Functions for operand encoding. ARM, then Thumb. */
6942 #define rotate_left(v, n) (v << n | v >> (32 - n))
6944 /* If VAL can be encoded in the immediate field of an ARM instruction,
6945 return the encoded form. Otherwise, return FAIL. */
6948 encode_arm_immediate (unsigned int val)
6952 for (i = 0; i < 32; i += 2)
6953 if ((a = rotate_left (val, i)) <= 0xff)
6954 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6959 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6960 return the encoded form. Otherwise, return FAIL. */
6962 encode_thumb32_immediate (unsigned int val)
6969 for (i = 1; i <= 24; i++)
6972 if ((val & ~(0xff << i)) == 0)
6973 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6977 if (val == ((a << 16) | a))
6979 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6983 if (val == ((a << 16) | a))
6984 return 0x200 | (a >> 8);
6988 /* Encode a VFP SP or DP register number into inst.instruction. */
6991 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6993 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6996 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6999 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7002 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7007 first_error (_("D register out of range for selected VFP version"));
7015 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7019 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7023 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7027 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7031 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7035 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7043 /* Encode a <shift> in an ARM-format instruction. The immediate,
7044 if any, is handled by md_apply_fix. */
7046 encode_arm_shift (int i)
7048 if (inst.operands[i].shift_kind == SHIFT_RRX)
7049 inst.instruction |= SHIFT_ROR << 5;
7052 inst.instruction |= inst.operands[i].shift_kind << 5;
7053 if (inst.operands[i].immisreg)
7055 inst.instruction |= SHIFT_BY_REG;
7056 inst.instruction |= inst.operands[i].imm << 8;
7059 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7064 encode_arm_shifter_operand (int i)
7066 if (inst.operands[i].isreg)
7068 inst.instruction |= inst.operands[i].reg;
7069 encode_arm_shift (i);
7073 inst.instruction |= INST_IMMEDIATE;
7074 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7075 inst.instruction |= inst.operands[i].imm;
7079 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7081 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7084 Generate an error if the operand is not a register. */
7085 constraint (!inst.operands[i].isreg,
7086 _("Instruction does not support =N addresses"));
7088 inst.instruction |= inst.operands[i].reg << 16;
7090 if (inst.operands[i].preind)
7094 inst.error = _("instruction does not accept preindexed addressing");
7097 inst.instruction |= PRE_INDEX;
7098 if (inst.operands[i].writeback)
7099 inst.instruction |= WRITE_BACK;
7102 else if (inst.operands[i].postind)
7104 gas_assert (inst.operands[i].writeback);
7106 inst.instruction |= WRITE_BACK;
7108 else /* unindexed - only for coprocessor */
7110 inst.error = _("instruction does not accept unindexed addressing");
7114 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7115 && (((inst.instruction & 0x000f0000) >> 16)
7116 == ((inst.instruction & 0x0000f000) >> 12)))
7117 as_warn ((inst.instruction & LOAD_BIT)
7118 ? _("destination register same as write-back base")
7119 : _("source register same as write-back base"));
7122 /* inst.operands[i] was set up by parse_address. Encode it into an
7123 ARM-format mode 2 load or store instruction. If is_t is true,
7124 reject forms that cannot be used with a T instruction (i.e. not
7127 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7129 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7131 encode_arm_addr_mode_common (i, is_t);
7133 if (inst.operands[i].immisreg)
7135 constraint ((inst.operands[i].imm == REG_PC
7136 || (is_pc && inst.operands[i].writeback)),
7138 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7139 inst.instruction |= inst.operands[i].imm;
7140 if (!inst.operands[i].negative)
7141 inst.instruction |= INDEX_UP;
7142 if (inst.operands[i].shifted)
7144 if (inst.operands[i].shift_kind == SHIFT_RRX)
7145 inst.instruction |= SHIFT_ROR << 5;
7148 inst.instruction |= inst.operands[i].shift_kind << 5;
7149 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7153 else /* immediate offset in inst.reloc */
7155 if (is_pc && !inst.reloc.pc_rel)
7157 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7159 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7160 cannot use PC in addressing.
7161 PC cannot be used in writeback addressing, either. */
7162 constraint ((is_t || inst.operands[i].writeback),
7165 /* Use of PC in str is deprecated for ARMv7. */
7166 if (warn_on_deprecated
7168 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7169 as_warn (_("use of PC in this instruction is deprecated"));
7172 if (inst.reloc.type == BFD_RELOC_UNUSED)
7174 /* Prefer + for zero encoded value. */
7175 if (!inst.operands[i].negative)
7176 inst.instruction |= INDEX_UP;
7177 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7182 /* inst.operands[i] was set up by parse_address. Encode it into an
7183 ARM-format mode 3 load or store instruction. Reject forms that
7184 cannot be used with such instructions. If is_t is true, reject
7185 forms that cannot be used with a T instruction (i.e. not
7188 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7190 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7192 inst.error = _("instruction does not accept scaled register index");
7196 encode_arm_addr_mode_common (i, is_t);
7198 if (inst.operands[i].immisreg)
7200 constraint ((inst.operands[i].imm == REG_PC
7201 || inst.operands[i].reg == REG_PC),
7203 inst.instruction |= inst.operands[i].imm;
7204 if (!inst.operands[i].negative)
7205 inst.instruction |= INDEX_UP;
7207 else /* immediate offset in inst.reloc */
7209 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7210 && inst.operands[i].writeback),
7212 inst.instruction |= HWOFFSET_IMM;
7213 if (inst.reloc.type == BFD_RELOC_UNUSED)
7215 /* Prefer + for zero encoded value. */
7216 if (!inst.operands[i].negative)
7217 inst.instruction |= INDEX_UP;
7219 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7224 /* inst.operands[i] was set up by parse_address. Encode it into an
7225 ARM-format instruction. Reject all forms which cannot be encoded
7226 into a coprocessor load/store instruction. If wb_ok is false,
7227 reject use of writeback; if unind_ok is false, reject use of
7228 unindexed addressing. If reloc_override is not 0, use it instead
7229 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7230 (in which case it is preserved). */
7233 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7235 inst.instruction |= inst.operands[i].reg << 16;
7237 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7239 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7241 gas_assert (!inst.operands[i].writeback);
7244 inst.error = _("instruction does not support unindexed addressing");
7247 inst.instruction |= inst.operands[i].imm;
7248 inst.instruction |= INDEX_UP;
7252 if (inst.operands[i].preind)
7253 inst.instruction |= PRE_INDEX;
7255 if (inst.operands[i].writeback)
7257 if (inst.operands[i].reg == REG_PC)
7259 inst.error = _("pc may not be used with write-back");
7264 inst.error = _("instruction does not support writeback");
7267 inst.instruction |= WRITE_BACK;
7271 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7272 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7273 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7274 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7277 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7279 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7282 /* Prefer + for zero encoded value. */
7283 if (!inst.operands[i].negative)
7284 inst.instruction |= INDEX_UP;
7289 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7290 Determine whether it can be performed with a move instruction; if
7291 it can, convert inst.instruction to that move instruction and
7292 return TRUE; if it can't, convert inst.instruction to a literal-pool
7293 load and return FALSE. If this is not a valid thing to do in the
7294 current context, set inst.error and return TRUE.
7296 inst.operands[i] describes the destination register. */
7299 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7304 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7308 if ((inst.instruction & tbit) == 0)
7310 inst.error = _("invalid pseudo operation");
7313 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7315 inst.error = _("constant expression expected");
7318 if (inst.reloc.exp.X_op == O_constant)
7322 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7324 /* This can be done with a mov(1) instruction. */
7325 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7326 inst.instruction |= inst.reloc.exp.X_add_number;
7332 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7335 /* This can be done with a mov instruction. */
7336 inst.instruction &= LITERAL_MASK;
7337 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7338 inst.instruction |= value & 0xfff;
7342 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7345 /* This can be done with a mvn instruction. */
7346 inst.instruction &= LITERAL_MASK;
7347 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7348 inst.instruction |= value & 0xfff;
7354 if (add_to_lit_pool () == FAIL)
7356 inst.error = _("literal pool insertion failed");
7359 inst.operands[1].reg = REG_PC;
7360 inst.operands[1].isreg = 1;
7361 inst.operands[1].preind = 1;
7362 inst.reloc.pc_rel = 1;
7363 inst.reloc.type = (thumb_p
7364 ? BFD_RELOC_ARM_THUMB_OFFSET
7366 ? BFD_RELOC_ARM_HWLITERAL
7367 : BFD_RELOC_ARM_LITERAL));
7371 /* Functions for instruction encoding, sorted by sub-architecture.
7372 First some generics; their names are taken from the conventional
7373 bit positions for register arguments in ARM format instructions. */
7383 inst.instruction |= inst.operands[0].reg << 12;
7389 inst.instruction |= inst.operands[0].reg << 12;
7390 inst.instruction |= inst.operands[1].reg;
7396 inst.instruction |= inst.operands[0].reg;
7397 inst.instruction |= inst.operands[1].reg << 16;
7403 inst.instruction |= inst.operands[0].reg << 12;
7404 inst.instruction |= inst.operands[1].reg << 16;
7410 inst.instruction |= inst.operands[0].reg << 16;
7411 inst.instruction |= inst.operands[1].reg << 12;
7415 check_obsolete (const arm_feature_set *feature, const char *msg)
7417 if (ARM_CPU_IS_ANY (cpu_variant))
7419 as_warn ("%s", msg);
7422 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7434 unsigned Rn = inst.operands[2].reg;
7435 /* Enforce restrictions on SWP instruction. */
7436 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7438 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7439 _("Rn must not overlap other operands"));
7441 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7443 if (!check_obsolete (&arm_ext_v8,
7444 _("swp{b} use is obsoleted for ARMv8 and later"))
7445 && warn_on_deprecated
7446 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7447 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7450 inst.instruction |= inst.operands[0].reg << 12;
7451 inst.instruction |= inst.operands[1].reg;
7452 inst.instruction |= Rn << 16;
7458 inst.instruction |= inst.operands[0].reg << 12;
7459 inst.instruction |= inst.operands[1].reg << 16;
7460 inst.instruction |= inst.operands[2].reg;
7466 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7467 constraint (((inst.reloc.exp.X_op != O_constant
7468 && inst.reloc.exp.X_op != O_illegal)
7469 || inst.reloc.exp.X_add_number != 0),
7471 inst.instruction |= inst.operands[0].reg;
7472 inst.instruction |= inst.operands[1].reg << 12;
7473 inst.instruction |= inst.operands[2].reg << 16;
7479 inst.instruction |= inst.operands[0].imm;
7485 inst.instruction |= inst.operands[0].reg << 12;
7486 encode_arm_cp_address (1, TRUE, TRUE, 0);
7489 /* ARM instructions, in alphabetical order by function name (except
7490 that wrapper functions appear immediately after the function they
7493 /* This is a pseudo-op of the form "adr rd, label" to be converted
7494 into a relative address of the form "add rd, pc, #label-.-8". */
7499 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7501 /* Frag hacking will turn this into a sub instruction if the offset turns
7502 out to be negative. */
7503 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7504 inst.reloc.pc_rel = 1;
7505 inst.reloc.exp.X_add_number -= 8;
7508 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7509 into a relative address of the form:
7510 add rd, pc, #low(label-.-8)"
7511 add rd, rd, #high(label-.-8)" */
7516 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7518 /* Frag hacking will turn this into a sub instruction if the offset turns
7519 out to be negative. */
7520 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7521 inst.reloc.pc_rel = 1;
7522 inst.size = INSN_SIZE * 2;
7523 inst.reloc.exp.X_add_number -= 8;
7529 if (!inst.operands[1].present)
7530 inst.operands[1].reg = inst.operands[0].reg;
7531 inst.instruction |= inst.operands[0].reg << 12;
7532 inst.instruction |= inst.operands[1].reg << 16;
7533 encode_arm_shifter_operand (2);
7539 if (inst.operands[0].present)
7541 constraint ((inst.instruction & 0xf0) != 0x40
7542 && inst.operands[0].imm > 0xf
7543 && inst.operands[0].imm < 0x0,
7544 _("bad barrier type"));
7545 inst.instruction |= inst.operands[0].imm;
7548 inst.instruction |= 0xf;
7554 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7555 constraint (msb > 32, _("bit-field extends past end of register"));
7556 /* The instruction encoding stores the LSB and MSB,
7557 not the LSB and width. */
7558 inst.instruction |= inst.operands[0].reg << 12;
7559 inst.instruction |= inst.operands[1].imm << 7;
7560 inst.instruction |= (msb - 1) << 16;
7568 /* #0 in second position is alternative syntax for bfc, which is
7569 the same instruction but with REG_PC in the Rm field. */
7570 if (!inst.operands[1].isreg)
7571 inst.operands[1].reg = REG_PC;
7573 msb = inst.operands[2].imm + inst.operands[3].imm;
7574 constraint (msb > 32, _("bit-field extends past end of register"));
7575 /* The instruction encoding stores the LSB and MSB,
7576 not the LSB and width. */
7577 inst.instruction |= inst.operands[0].reg << 12;
7578 inst.instruction |= inst.operands[1].reg;
7579 inst.instruction |= inst.operands[2].imm << 7;
7580 inst.instruction |= (msb - 1) << 16;
7586 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7587 _("bit-field extends past end of register"));
7588 inst.instruction |= inst.operands[0].reg << 12;
7589 inst.instruction |= inst.operands[1].reg;
7590 inst.instruction |= inst.operands[2].imm << 7;
7591 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7594 /* ARM V5 breakpoint instruction (argument parse)
7595 BKPT <16 bit unsigned immediate>
7596 Instruction is not conditional.
7597 The bit pattern given in insns[] has the COND_ALWAYS condition,
7598 and it is an error if the caller tried to override that. */
7603 /* Top 12 of 16 bits to bits 19:8. */
7604 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7606 /* Bottom 4 of 16 bits to bits 3:0. */
7607 inst.instruction |= inst.operands[0].imm & 0xf;
7611 encode_branch (int default_reloc)
7613 if (inst.operands[0].hasreloc)
7615 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7616 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7617 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7618 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7619 ? BFD_RELOC_ARM_PLT32
7620 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7623 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7624 inst.reloc.pc_rel = 1;
7631 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7632 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7635 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7642 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7644 if (inst.cond == COND_ALWAYS)
7645 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7647 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7651 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7654 /* ARM V5 branch-link-exchange instruction (argument parse)
7655 BLX <target_addr> ie BLX(1)
7656 BLX{<condition>} <Rm> ie BLX(2)
7657 Unfortunately, there are two different opcodes for this mnemonic.
7658 So, the insns[].value is not used, and the code here zaps values
7659 into inst.instruction.
7660 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7665 if (inst.operands[0].isreg)
7667 /* Arg is a register; the opcode provided by insns[] is correct.
7668 It is not illegal to do "blx pc", just useless. */
7669 if (inst.operands[0].reg == REG_PC)
7670 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7672 inst.instruction |= inst.operands[0].reg;
7676 /* Arg is an address; this instruction cannot be executed
7677 conditionally, and the opcode must be adjusted.
7678 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7679 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7680 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7681 inst.instruction = 0xfa000000;
7682 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7689 bfd_boolean want_reloc;
7691 if (inst.operands[0].reg == REG_PC)
7692 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7694 inst.instruction |= inst.operands[0].reg;
7695 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7696 it is for ARMv4t or earlier. */
7697 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7698 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7702 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7707 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7711 /* ARM v5TEJ. Jump to Jazelle code. */
7716 if (inst.operands[0].reg == REG_PC)
7717 as_tsktsk (_("use of r15 in bxj is not really useful"));
7719 inst.instruction |= inst.operands[0].reg;
7722 /* Co-processor data operation:
7723 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7724 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7728 inst.instruction |= inst.operands[0].reg << 8;
7729 inst.instruction |= inst.operands[1].imm << 20;
7730 inst.instruction |= inst.operands[2].reg << 12;
7731 inst.instruction |= inst.operands[3].reg << 16;
7732 inst.instruction |= inst.operands[4].reg;
7733 inst.instruction |= inst.operands[5].imm << 5;
7739 inst.instruction |= inst.operands[0].reg << 16;
7740 encode_arm_shifter_operand (1);
7743 /* Transfer between coprocessor and ARM registers.
7744 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7749 No special properties. */
7751 struct deprecated_coproc_regs_s
7758 arm_feature_set deprecated;
7759 arm_feature_set obsoleted;
7760 const char *dep_msg;
7761 const char *obs_msg;
7764 #define DEPR_ACCESS_V8 \
7765 N_("This coprocessor register access is deprecated in ARMv8")
7767 /* Table of all deprecated coprocessor registers. */
7768 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7770 {15, 0, 7, 10, 5, /* CP15DMB. */
7771 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7772 DEPR_ACCESS_V8, NULL},
7773 {15, 0, 7, 10, 4, /* CP15DSB. */
7774 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7775 DEPR_ACCESS_V8, NULL},
7776 {15, 0, 7, 5, 4, /* CP15ISB. */
7777 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8, NULL},
7779 {14, 6, 1, 0, 0, /* TEEHBR. */
7780 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8, NULL},
7782 {14, 6, 0, 0, 0, /* TEECR. */
7783 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7784 DEPR_ACCESS_V8, NULL},
7787 #undef DEPR_ACCESS_V8
7789 static const size_t deprecated_coproc_reg_count =
7790 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7798 Rd = inst.operands[2].reg;
7801 if (inst.instruction == 0xee000010
7802 || inst.instruction == 0xfe000010)
7804 reject_bad_reg (Rd);
7807 constraint (Rd == REG_SP, BAD_SP);
7812 if (inst.instruction == 0xe000010)
7813 constraint (Rd == REG_PC, BAD_PC);
7816 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7818 const struct deprecated_coproc_regs_s *r =
7819 deprecated_coproc_regs + i;
7821 if (inst.operands[0].reg == r->cp
7822 && inst.operands[1].imm == r->opc1
7823 && inst.operands[3].reg == r->crn
7824 && inst.operands[4].reg == r->crm
7825 && inst.operands[5].imm == r->opc2)
7827 if (!check_obsolete (&r->obsoleted, r->obs_msg)
7828 && warn_on_deprecated
7829 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7830 as_warn ("%s", r->dep_msg);
7834 inst.instruction |= inst.operands[0].reg << 8;
7835 inst.instruction |= inst.operands[1].imm << 21;
7836 inst.instruction |= Rd << 12;
7837 inst.instruction |= inst.operands[3].reg << 16;
7838 inst.instruction |= inst.operands[4].reg;
7839 inst.instruction |= inst.operands[5].imm << 5;
7842 /* Transfer between coprocessor register and pair of ARM registers.
7843 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7848 Two XScale instructions are special cases of these:
7850 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7851 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7853 Result unpredictable if Rd or Rn is R15. */
7860 Rd = inst.operands[2].reg;
7861 Rn = inst.operands[3].reg;
7865 reject_bad_reg (Rd);
7866 reject_bad_reg (Rn);
7870 constraint (Rd == REG_PC, BAD_PC);
7871 constraint (Rn == REG_PC, BAD_PC);
7874 inst.instruction |= inst.operands[0].reg << 8;
7875 inst.instruction |= inst.operands[1].imm << 4;
7876 inst.instruction |= Rd << 12;
7877 inst.instruction |= Rn << 16;
7878 inst.instruction |= inst.operands[4].reg;
7884 inst.instruction |= inst.operands[0].imm << 6;
7885 if (inst.operands[1].present)
7887 inst.instruction |= CPSI_MMOD;
7888 inst.instruction |= inst.operands[1].imm;
7895 inst.instruction |= inst.operands[0].imm;
7901 unsigned Rd, Rn, Rm;
7903 Rd = inst.operands[0].reg;
7904 Rn = (inst.operands[1].present
7905 ? inst.operands[1].reg : Rd);
7906 Rm = inst.operands[2].reg;
7908 constraint ((Rd == REG_PC), BAD_PC);
7909 constraint ((Rn == REG_PC), BAD_PC);
7910 constraint ((Rm == REG_PC), BAD_PC);
7912 inst.instruction |= Rd << 16;
7913 inst.instruction |= Rn << 0;
7914 inst.instruction |= Rm << 8;
7920 /* There is no IT instruction in ARM mode. We
7921 process it to do the validation as if in
7922 thumb mode, just in case the code gets
7923 assembled for thumb using the unified syntax. */
7928 set_it_insn_type (IT_INSN);
7929 now_it.mask = (inst.instruction & 0xf) | 0x10;
7930 now_it.cc = inst.operands[0].imm;
7934 /* If there is only one register in the register list,
7935 then return its register number. Otherwise return -1. */
7937 only_one_reg_in_list (int range)
7939 int i = ffs (range) - 1;
7940 return (i > 15 || range != (1 << i)) ? -1 : i;
7944 encode_ldmstm(int from_push_pop_mnem)
7946 int base_reg = inst.operands[0].reg;
7947 int range = inst.operands[1].imm;
7950 inst.instruction |= base_reg << 16;
7951 inst.instruction |= range;
7953 if (inst.operands[1].writeback)
7954 inst.instruction |= LDM_TYPE_2_OR_3;
7956 if (inst.operands[0].writeback)
7958 inst.instruction |= WRITE_BACK;
7959 /* Check for unpredictable uses of writeback. */
7960 if (inst.instruction & LOAD_BIT)
7962 /* Not allowed in LDM type 2. */
7963 if ((inst.instruction & LDM_TYPE_2_OR_3)
7964 && ((range & (1 << REG_PC)) == 0))
7965 as_warn (_("writeback of base register is UNPREDICTABLE"));
7966 /* Only allowed if base reg not in list for other types. */
7967 else if (range & (1 << base_reg))
7968 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7972 /* Not allowed for type 2. */
7973 if (inst.instruction & LDM_TYPE_2_OR_3)
7974 as_warn (_("writeback of base register is UNPREDICTABLE"));
7975 /* Only allowed if base reg not in list, or first in list. */
7976 else if ((range & (1 << base_reg))
7977 && (range & ((1 << base_reg) - 1)))
7978 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7982 /* If PUSH/POP has only one register, then use the A2 encoding. */
7983 one_reg = only_one_reg_in_list (range);
7984 if (from_push_pop_mnem && one_reg >= 0)
7986 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7988 inst.instruction &= A_COND_MASK;
7989 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7990 inst.instruction |= one_reg << 12;
7997 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8000 /* ARMv5TE load-consecutive (argument parse)
8009 constraint (inst.operands[0].reg % 2 != 0,
8010 _("first transfer register must be even"));
8011 constraint (inst.operands[1].present
8012 && inst.operands[1].reg != inst.operands[0].reg + 1,
8013 _("can only transfer two consecutive registers"));
8014 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8015 constraint (!inst.operands[2].isreg, _("'[' expected"));
8017 if (!inst.operands[1].present)
8018 inst.operands[1].reg = inst.operands[0].reg + 1;
8020 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8021 register and the first register written; we have to diagnose
8022 overlap between the base and the second register written here. */
8024 if (inst.operands[2].reg == inst.operands[1].reg
8025 && (inst.operands[2].writeback || inst.operands[2].postind))
8026 as_warn (_("base register written back, and overlaps "
8027 "second transfer register"));
8029 if (!(inst.instruction & V4_STR_BIT))
8031 /* For an index-register load, the index register must not overlap the
8032 destination (even if not write-back). */
8033 if (inst.operands[2].immisreg
8034 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8035 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8036 as_warn (_("index register overlaps transfer register"));
8038 inst.instruction |= inst.operands[0].reg << 12;
8039 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8045 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8046 || inst.operands[1].postind || inst.operands[1].writeback
8047 || inst.operands[1].immisreg || inst.operands[1].shifted
8048 || inst.operands[1].negative
8049 /* This can arise if the programmer has written
8051 or if they have mistakenly used a register name as the last
8054 It is very difficult to distinguish between these two cases
8055 because "rX" might actually be a label. ie the register
8056 name has been occluded by a symbol of the same name. So we
8057 just generate a general 'bad addressing mode' type error
8058 message and leave it up to the programmer to discover the
8059 true cause and fix their mistake. */
8060 || (inst.operands[1].reg == REG_PC),
8063 constraint (inst.reloc.exp.X_op != O_constant
8064 || inst.reloc.exp.X_add_number != 0,
8065 _("offset must be zero in ARM encoding"));
8067 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8069 inst.instruction |= inst.operands[0].reg << 12;
8070 inst.instruction |= inst.operands[1].reg << 16;
8071 inst.reloc.type = BFD_RELOC_UNUSED;
8077 constraint (inst.operands[0].reg % 2 != 0,
8078 _("even register required"));
8079 constraint (inst.operands[1].present
8080 && inst.operands[1].reg != inst.operands[0].reg + 1,
8081 _("can only load two consecutive registers"));
8082 /* If op 1 were present and equal to PC, this function wouldn't
8083 have been called in the first place. */
8084 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8086 inst.instruction |= inst.operands[0].reg << 12;
8087 inst.instruction |= inst.operands[2].reg << 16;
8090 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8091 which is not a multiple of four is UNPREDICTABLE. */
8093 check_ldr_r15_aligned (void)
8095 constraint (!(inst.operands[1].immisreg)
8096 && (inst.operands[0].reg == REG_PC
8097 && inst.operands[1].reg == REG_PC
8098 && (inst.reloc.exp.X_add_number & 0x3)),
8099 _("ldr to register 15 must be 4-byte alligned"));
8105 inst.instruction |= inst.operands[0].reg << 12;
8106 if (!inst.operands[1].isreg)
8107 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8109 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8110 check_ldr_r15_aligned ();
8116 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8118 if (inst.operands[1].preind)
8120 constraint (inst.reloc.exp.X_op != O_constant
8121 || inst.reloc.exp.X_add_number != 0,
8122 _("this instruction requires a post-indexed address"));
8124 inst.operands[1].preind = 0;
8125 inst.operands[1].postind = 1;
8126 inst.operands[1].writeback = 1;
8128 inst.instruction |= inst.operands[0].reg << 12;
8129 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8132 /* Halfword and signed-byte load/store operations. */
8137 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8138 inst.instruction |= inst.operands[0].reg << 12;
8139 if (!inst.operands[1].isreg)
8140 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8142 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8148 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8150 if (inst.operands[1].preind)
8152 constraint (inst.reloc.exp.X_op != O_constant
8153 || inst.reloc.exp.X_add_number != 0,
8154 _("this instruction requires a post-indexed address"));
8156 inst.operands[1].preind = 0;
8157 inst.operands[1].postind = 1;
8158 inst.operands[1].writeback = 1;
8160 inst.instruction |= inst.operands[0].reg << 12;
8161 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8164 /* Co-processor register load/store.
8165 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8169 inst.instruction |= inst.operands[0].reg << 8;
8170 inst.instruction |= inst.operands[1].reg << 12;
8171 encode_arm_cp_address (2, TRUE, TRUE, 0);
8177 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8178 if (inst.operands[0].reg == inst.operands[1].reg
8179 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8180 && !(inst.instruction & 0x00400000))
8181 as_tsktsk (_("Rd and Rm should be different in mla"));
8183 inst.instruction |= inst.operands[0].reg << 16;
8184 inst.instruction |= inst.operands[1].reg;
8185 inst.instruction |= inst.operands[2].reg << 8;
8186 inst.instruction |= inst.operands[3].reg << 12;
8192 inst.instruction |= inst.operands[0].reg << 12;
8193 encode_arm_shifter_operand (1);
8196 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8203 top = (inst.instruction & 0x00400000) != 0;
8204 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8205 _(":lower16: not allowed this instruction"));
8206 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8207 _(":upper16: not allowed instruction"));
8208 inst.instruction |= inst.operands[0].reg << 12;
8209 if (inst.reloc.type == BFD_RELOC_UNUSED)
8211 imm = inst.reloc.exp.X_add_number;
8212 /* The value is in two pieces: 0:11, 16:19. */
8213 inst.instruction |= (imm & 0x00000fff);
8214 inst.instruction |= (imm & 0x0000f000) << 4;
8218 static void do_vfp_nsyn_opcode (const char *);
8221 do_vfp_nsyn_mrs (void)
8223 if (inst.operands[0].isvec)
8225 if (inst.operands[1].reg != 1)
8226 first_error (_("operand 1 must be FPSCR"));
8227 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8228 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8229 do_vfp_nsyn_opcode ("fmstat");
8231 else if (inst.operands[1].isvec)
8232 do_vfp_nsyn_opcode ("fmrx");
8240 do_vfp_nsyn_msr (void)
8242 if (inst.operands[0].isvec)
8243 do_vfp_nsyn_opcode ("fmxr");
8253 unsigned Rt = inst.operands[0].reg;
8255 if (thumb_mode && inst.operands[0].reg == REG_SP)
8257 inst.error = BAD_SP;
8261 /* APSR_ sets isvec. All other refs to PC are illegal. */
8262 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8264 inst.error = BAD_PC;
8268 switch (inst.operands[1].reg)
8275 inst.instruction |= (inst.operands[1].reg << 16);
8278 first_error (_("operand 1 must be a VFP extension System Register"));
8281 inst.instruction |= (Rt << 12);
8287 unsigned Rt = inst.operands[1].reg;
8290 reject_bad_reg (Rt);
8291 else if (Rt == REG_PC)
8293 inst.error = BAD_PC;
8297 switch (inst.operands[0].reg)
8302 inst.instruction |= (inst.operands[0].reg << 16);
8305 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8308 inst.instruction |= (Rt << 12);
8316 if (do_vfp_nsyn_mrs () == SUCCESS)
8319 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8320 inst.instruction |= inst.operands[0].reg << 12;
8322 if (inst.operands[1].isreg)
8324 br = inst.operands[1].reg;
8325 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8326 as_bad (_("bad register for mrs"));
8330 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8331 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8333 _("'APSR', 'CPSR' or 'SPSR' expected"));
8334 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8337 inst.instruction |= br;
8340 /* Two possible forms:
8341 "{C|S}PSR_<field>, Rm",
8342 "{C|S}PSR_f, #expression". */
8347 if (do_vfp_nsyn_msr () == SUCCESS)
8350 inst.instruction |= inst.operands[0].imm;
8351 if (inst.operands[1].isreg)
8352 inst.instruction |= inst.operands[1].reg;
8355 inst.instruction |= INST_IMMEDIATE;
8356 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8357 inst.reloc.pc_rel = 0;
8364 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8366 if (!inst.operands[2].present)
8367 inst.operands[2].reg = inst.operands[0].reg;
8368 inst.instruction |= inst.operands[0].reg << 16;
8369 inst.instruction |= inst.operands[1].reg;
8370 inst.instruction |= inst.operands[2].reg << 8;
8372 if (inst.operands[0].reg == inst.operands[1].reg
8373 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8374 as_tsktsk (_("Rd and Rm should be different in mul"));
8377 /* Long Multiply Parser
8378 UMULL RdLo, RdHi, Rm, Rs
8379 SMULL RdLo, RdHi, Rm, Rs
8380 UMLAL RdLo, RdHi, Rm, Rs
8381 SMLAL RdLo, RdHi, Rm, Rs. */
8386 inst.instruction |= inst.operands[0].reg << 12;
8387 inst.instruction |= inst.operands[1].reg << 16;
8388 inst.instruction |= inst.operands[2].reg;
8389 inst.instruction |= inst.operands[3].reg << 8;
8391 /* rdhi and rdlo must be different. */
8392 if (inst.operands[0].reg == inst.operands[1].reg)
8393 as_tsktsk (_("rdhi and rdlo must be different"));
8395 /* rdhi, rdlo and rm must all be different before armv6. */
8396 if ((inst.operands[0].reg == inst.operands[2].reg
8397 || inst.operands[1].reg == inst.operands[2].reg)
8398 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8399 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8405 if (inst.operands[0].present
8406 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8408 /* Architectural NOP hints are CPSR sets with no bits selected. */
8409 inst.instruction &= 0xf0000000;
8410 inst.instruction |= 0x0320f000;
8411 if (inst.operands[0].present)
8412 inst.instruction |= inst.operands[0].imm;
8416 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8417 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8418 Condition defaults to COND_ALWAYS.
8419 Error if Rd, Rn or Rm are R15. */
8424 inst.instruction |= inst.operands[0].reg << 12;
8425 inst.instruction |= inst.operands[1].reg << 16;
8426 inst.instruction |= inst.operands[2].reg;
8427 if (inst.operands[3].present)
8428 encode_arm_shift (3);
8431 /* ARM V6 PKHTB (Argument Parse). */
8436 if (!inst.operands[3].present)
8438 /* If the shift specifier is omitted, turn the instruction
8439 into pkhbt rd, rm, rn. */
8440 inst.instruction &= 0xfff00010;
8441 inst.instruction |= inst.operands[0].reg << 12;
8442 inst.instruction |= inst.operands[1].reg;
8443 inst.instruction |= inst.operands[2].reg << 16;
8447 inst.instruction |= inst.operands[0].reg << 12;
8448 inst.instruction |= inst.operands[1].reg << 16;
8449 inst.instruction |= inst.operands[2].reg;
8450 encode_arm_shift (3);
8454 /* ARMv5TE: Preload-Cache
8455 MP Extensions: Preload for write
8459 Syntactically, like LDR with B=1, W=0, L=1. */
8464 constraint (!inst.operands[0].isreg,
8465 _("'[' expected after PLD mnemonic"));
8466 constraint (inst.operands[0].postind,
8467 _("post-indexed expression used in preload instruction"));
8468 constraint (inst.operands[0].writeback,
8469 _("writeback used in preload instruction"));
8470 constraint (!inst.operands[0].preind,
8471 _("unindexed addressing used in preload instruction"));
8472 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8475 /* ARMv7: PLI <addr_mode> */
8479 constraint (!inst.operands[0].isreg,
8480 _("'[' expected after PLI mnemonic"));
8481 constraint (inst.operands[0].postind,
8482 _("post-indexed expression used in preload instruction"));
8483 constraint (inst.operands[0].writeback,
8484 _("writeback used in preload instruction"));
8485 constraint (!inst.operands[0].preind,
8486 _("unindexed addressing used in preload instruction"));
8487 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8488 inst.instruction &= ~PRE_INDEX;
8494 inst.operands[1] = inst.operands[0];
8495 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8496 inst.operands[0].isreg = 1;
8497 inst.operands[0].writeback = 1;
8498 inst.operands[0].reg = REG_SP;
8499 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8502 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8503 word at the specified address and the following word
8505 Unconditionally executed.
8506 Error if Rn is R15. */
8511 inst.instruction |= inst.operands[0].reg << 16;
8512 if (inst.operands[0].writeback)
8513 inst.instruction |= WRITE_BACK;
8516 /* ARM V6 ssat (argument parse). */
8521 inst.instruction |= inst.operands[0].reg << 12;
8522 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8523 inst.instruction |= inst.operands[2].reg;
8525 if (inst.operands[3].present)
8526 encode_arm_shift (3);
8529 /* ARM V6 usat (argument parse). */
8534 inst.instruction |= inst.operands[0].reg << 12;
8535 inst.instruction |= inst.operands[1].imm << 16;
8536 inst.instruction |= inst.operands[2].reg;
8538 if (inst.operands[3].present)
8539 encode_arm_shift (3);
8542 /* ARM V6 ssat16 (argument parse). */
8547 inst.instruction |= inst.operands[0].reg << 12;
8548 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8549 inst.instruction |= inst.operands[2].reg;
8555 inst.instruction |= inst.operands[0].reg << 12;
8556 inst.instruction |= inst.operands[1].imm << 16;
8557 inst.instruction |= inst.operands[2].reg;
8560 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8561 preserving the other bits.
8563 setend <endian_specifier>, where <endian_specifier> is either
8569 if (warn_on_deprecated
8570 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8571 as_warn (_("setend use is deprecated for ARMv8"));
8573 if (inst.operands[0].imm)
8574 inst.instruction |= 0x200;
8580 unsigned int Rm = (inst.operands[1].present
8581 ? inst.operands[1].reg
8582 : inst.operands[0].reg);
8584 inst.instruction |= inst.operands[0].reg << 12;
8585 inst.instruction |= Rm;
8586 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8588 inst.instruction |= inst.operands[2].reg << 8;
8589 inst.instruction |= SHIFT_BY_REG;
8590 /* PR 12854: Error on extraneous shifts. */
8591 constraint (inst.operands[2].shifted,
8592 _("extraneous shift as part of operand to shift insn"));
8595 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8601 inst.reloc.type = BFD_RELOC_ARM_SMC;
8602 inst.reloc.pc_rel = 0;
8608 inst.reloc.type = BFD_RELOC_ARM_HVC;
8609 inst.reloc.pc_rel = 0;
8615 inst.reloc.type = BFD_RELOC_ARM_SWI;
8616 inst.reloc.pc_rel = 0;
8619 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8620 SMLAxy{cond} Rd,Rm,Rs,Rn
8621 SMLAWy{cond} Rd,Rm,Rs,Rn
8622 Error if any register is R15. */
8627 inst.instruction |= inst.operands[0].reg << 16;
8628 inst.instruction |= inst.operands[1].reg;
8629 inst.instruction |= inst.operands[2].reg << 8;
8630 inst.instruction |= inst.operands[3].reg << 12;
8633 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8634 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8635 Error if any register is R15.
8636 Warning if Rdlo == Rdhi. */
8641 inst.instruction |= inst.operands[0].reg << 12;
8642 inst.instruction |= inst.operands[1].reg << 16;
8643 inst.instruction |= inst.operands[2].reg;
8644 inst.instruction |= inst.operands[3].reg << 8;
8646 if (inst.operands[0].reg == inst.operands[1].reg)
8647 as_tsktsk (_("rdhi and rdlo must be different"));
8650 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8651 SMULxy{cond} Rd,Rm,Rs
8652 Error if any register is R15. */
8657 inst.instruction |= inst.operands[0].reg << 16;
8658 inst.instruction |= inst.operands[1].reg;
8659 inst.instruction |= inst.operands[2].reg << 8;
8662 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8663 the same for both ARM and Thumb-2. */
8670 if (inst.operands[0].present)
8672 reg = inst.operands[0].reg;
8673 constraint (reg != REG_SP, _("SRS base register must be r13"));
8678 inst.instruction |= reg << 16;
8679 inst.instruction |= inst.operands[1].imm;
8680 if (inst.operands[0].writeback || inst.operands[1].writeback)
8681 inst.instruction |= WRITE_BACK;
8684 /* ARM V6 strex (argument parse). */
8689 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8690 || inst.operands[2].postind || inst.operands[2].writeback
8691 || inst.operands[2].immisreg || inst.operands[2].shifted
8692 || inst.operands[2].negative
8693 /* See comment in do_ldrex(). */
8694 || (inst.operands[2].reg == REG_PC),
8697 constraint (inst.operands[0].reg == inst.operands[1].reg
8698 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8700 constraint (inst.reloc.exp.X_op != O_constant
8701 || inst.reloc.exp.X_add_number != 0,
8702 _("offset must be zero in ARM encoding"));
8704 inst.instruction |= inst.operands[0].reg << 12;
8705 inst.instruction |= inst.operands[1].reg;
8706 inst.instruction |= inst.operands[2].reg << 16;
8707 inst.reloc.type = BFD_RELOC_UNUSED;
8713 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8714 || inst.operands[2].postind || inst.operands[2].writeback
8715 || inst.operands[2].immisreg || inst.operands[2].shifted
8716 || inst.operands[2].negative,
8719 constraint (inst.operands[0].reg == inst.operands[1].reg
8720 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8728 constraint (inst.operands[1].reg % 2 != 0,
8729 _("even register required"));
8730 constraint (inst.operands[2].present
8731 && inst.operands[2].reg != inst.operands[1].reg + 1,
8732 _("can only store two consecutive registers"));
8733 /* If op 2 were present and equal to PC, this function wouldn't
8734 have been called in the first place. */
8735 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8737 constraint (inst.operands[0].reg == inst.operands[1].reg
8738 || inst.operands[0].reg == inst.operands[1].reg + 1
8739 || inst.operands[0].reg == inst.operands[3].reg,
8742 inst.instruction |= inst.operands[0].reg << 12;
8743 inst.instruction |= inst.operands[1].reg;
8744 inst.instruction |= inst.operands[3].reg << 16;
8751 constraint (inst.operands[0].reg == inst.operands[1].reg
8752 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8760 constraint (inst.operands[0].reg == inst.operands[1].reg
8761 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8766 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8767 extends it to 32-bits, and adds the result to a value in another
8768 register. You can specify a rotation by 0, 8, 16, or 24 bits
8769 before extracting the 16-bit value.
8770 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8771 Condition defaults to COND_ALWAYS.
8772 Error if any register uses R15. */
8777 inst.instruction |= inst.operands[0].reg << 12;
8778 inst.instruction |= inst.operands[1].reg << 16;
8779 inst.instruction |= inst.operands[2].reg;
8780 inst.instruction |= inst.operands[3].imm << 10;
8785 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8786 Condition defaults to COND_ALWAYS.
8787 Error if any register uses R15. */
8792 inst.instruction |= inst.operands[0].reg << 12;
8793 inst.instruction |= inst.operands[1].reg;
8794 inst.instruction |= inst.operands[2].imm << 10;
8797 /* VFP instructions. In a logical order: SP variant first, monad
8798 before dyad, arithmetic then move then load/store. */
8801 do_vfp_sp_monadic (void)
8803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8804 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8808 do_vfp_sp_dyadic (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8812 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8816 do_vfp_sp_compare_z (void)
8818 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8822 do_vfp_dp_sp_cvt (void)
8824 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8825 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8829 do_vfp_sp_dp_cvt (void)
8831 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8832 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8836 do_vfp_reg_from_sp (void)
8838 inst.instruction |= inst.operands[0].reg << 12;
8839 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8843 do_vfp_reg2_from_sp2 (void)
8845 constraint (inst.operands[2].imm != 2,
8846 _("only two consecutive VFP SP registers allowed here"));
8847 inst.instruction |= inst.operands[0].reg << 12;
8848 inst.instruction |= inst.operands[1].reg << 16;
8849 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8853 do_vfp_sp_from_reg (void)
8855 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8856 inst.instruction |= inst.operands[1].reg << 12;
8860 do_vfp_sp2_from_reg2 (void)
8862 constraint (inst.operands[0].imm != 2,
8863 _("only two consecutive VFP SP registers allowed here"));
8864 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8865 inst.instruction |= inst.operands[1].reg << 12;
8866 inst.instruction |= inst.operands[2].reg << 16;
8870 do_vfp_sp_ldst (void)
8872 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8873 encode_arm_cp_address (1, FALSE, TRUE, 0);
8877 do_vfp_dp_ldst (void)
8879 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8880 encode_arm_cp_address (1, FALSE, TRUE, 0);
8885 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8887 if (inst.operands[0].writeback)
8888 inst.instruction |= WRITE_BACK;
8890 constraint (ldstm_type != VFP_LDSTMIA,
8891 _("this addressing mode requires base-register writeback"));
8892 inst.instruction |= inst.operands[0].reg << 16;
8893 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8894 inst.instruction |= inst.operands[1].imm;
8898 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8902 if (inst.operands[0].writeback)
8903 inst.instruction |= WRITE_BACK;
8905 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8906 _("this addressing mode requires base-register writeback"));
8908 inst.instruction |= inst.operands[0].reg << 16;
8909 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8911 count = inst.operands[1].imm << 1;
8912 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8915 inst.instruction |= count;
8919 do_vfp_sp_ldstmia (void)
8921 vfp_sp_ldstm (VFP_LDSTMIA);
8925 do_vfp_sp_ldstmdb (void)
8927 vfp_sp_ldstm (VFP_LDSTMDB);
8931 do_vfp_dp_ldstmia (void)
8933 vfp_dp_ldstm (VFP_LDSTMIA);
8937 do_vfp_dp_ldstmdb (void)
8939 vfp_dp_ldstm (VFP_LDSTMDB);
8943 do_vfp_xp_ldstmia (void)
8945 vfp_dp_ldstm (VFP_LDSTMIAX);
8949 do_vfp_xp_ldstmdb (void)
8951 vfp_dp_ldstm (VFP_LDSTMDBX);
8955 do_vfp_dp_rd_rm (void)
8957 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8958 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8962 do_vfp_dp_rn_rd (void)
8964 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8965 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8969 do_vfp_dp_rd_rn (void)
8971 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8972 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8976 do_vfp_dp_rd_rn_rm (void)
8978 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8979 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8980 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8986 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8990 do_vfp_dp_rm_rd_rn (void)
8992 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8993 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8994 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8997 /* VFPv3 instructions. */
8999 do_vfp_sp_const (void)
9001 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9002 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9003 inst.instruction |= (inst.operands[1].imm & 0x0f);
9007 do_vfp_dp_const (void)
9009 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9010 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9011 inst.instruction |= (inst.operands[1].imm & 0x0f);
9015 vfp_conv (int srcsize)
9017 int immbits = srcsize - inst.operands[1].imm;
9019 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9021 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9022 i.e. immbits must be in range 0 - 16. */
9023 inst.error = _("immediate value out of range, expected range [0, 16]");
9026 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9028 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9029 i.e. immbits must be in range 0 - 31. */
9030 inst.error = _("immediate value out of range, expected range [1, 32]");
9034 inst.instruction |= (immbits & 1) << 5;
9035 inst.instruction |= (immbits >> 1);
9039 do_vfp_sp_conv_16 (void)
9041 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9046 do_vfp_dp_conv_16 (void)
9048 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9053 do_vfp_sp_conv_32 (void)
9055 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9060 do_vfp_dp_conv_32 (void)
9062 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9066 /* FPA instructions. Also in a logical order. */
9071 inst.instruction |= inst.operands[0].reg << 16;
9072 inst.instruction |= inst.operands[1].reg;
9076 do_fpa_ldmstm (void)
9078 inst.instruction |= inst.operands[0].reg << 12;
9079 switch (inst.operands[1].imm)
9081 case 1: inst.instruction |= CP_T_X; break;
9082 case 2: inst.instruction |= CP_T_Y; break;
9083 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9088 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9090 /* The instruction specified "ea" or "fd", so we can only accept
9091 [Rn]{!}. The instruction does not really support stacking or
9092 unstacking, so we have to emulate these by setting appropriate
9093 bits and offsets. */
9094 constraint (inst.reloc.exp.X_op != O_constant
9095 || inst.reloc.exp.X_add_number != 0,
9096 _("this instruction does not support indexing"));
9098 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9099 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9101 if (!(inst.instruction & INDEX_UP))
9102 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9104 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9106 inst.operands[2].preind = 0;
9107 inst.operands[2].postind = 1;
9111 encode_arm_cp_address (2, TRUE, TRUE, 0);
9114 /* iWMMXt instructions: strictly in alphabetical order. */
9117 do_iwmmxt_tandorc (void)
9119 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9123 do_iwmmxt_textrc (void)
9125 inst.instruction |= inst.operands[0].reg << 12;
9126 inst.instruction |= inst.operands[1].imm;
9130 do_iwmmxt_textrm (void)
9132 inst.instruction |= inst.operands[0].reg << 12;
9133 inst.instruction |= inst.operands[1].reg << 16;
9134 inst.instruction |= inst.operands[2].imm;
9138 do_iwmmxt_tinsr (void)
9140 inst.instruction |= inst.operands[0].reg << 16;
9141 inst.instruction |= inst.operands[1].reg << 12;
9142 inst.instruction |= inst.operands[2].imm;
9146 do_iwmmxt_tmia (void)
9148 inst.instruction |= inst.operands[0].reg << 5;
9149 inst.instruction |= inst.operands[1].reg;
9150 inst.instruction |= inst.operands[2].reg << 12;
9154 do_iwmmxt_waligni (void)
9156 inst.instruction |= inst.operands[0].reg << 12;
9157 inst.instruction |= inst.operands[1].reg << 16;
9158 inst.instruction |= inst.operands[2].reg;
9159 inst.instruction |= inst.operands[3].imm << 20;
9163 do_iwmmxt_wmerge (void)
9165 inst.instruction |= inst.operands[0].reg << 12;
9166 inst.instruction |= inst.operands[1].reg << 16;
9167 inst.instruction |= inst.operands[2].reg;
9168 inst.instruction |= inst.operands[3].imm << 21;
9172 do_iwmmxt_wmov (void)
9174 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9175 inst.instruction |= inst.operands[0].reg << 12;
9176 inst.instruction |= inst.operands[1].reg << 16;
9177 inst.instruction |= inst.operands[1].reg;
9181 do_iwmmxt_wldstbh (void)
9184 inst.instruction |= inst.operands[0].reg << 12;
9186 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9188 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9189 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9193 do_iwmmxt_wldstw (void)
9195 /* RIWR_RIWC clears .isreg for a control register. */
9196 if (!inst.operands[0].isreg)
9198 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9199 inst.instruction |= 0xf0000000;
9202 inst.instruction |= inst.operands[0].reg << 12;
9203 encode_arm_cp_address (1, TRUE, TRUE, 0);
9207 do_iwmmxt_wldstd (void)
9209 inst.instruction |= inst.operands[0].reg << 12;
9210 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9211 && inst.operands[1].immisreg)
9213 inst.instruction &= ~0x1a000ff;
9214 inst.instruction |= (0xf << 28);
9215 if (inst.operands[1].preind)
9216 inst.instruction |= PRE_INDEX;
9217 if (!inst.operands[1].negative)
9218 inst.instruction |= INDEX_UP;
9219 if (inst.operands[1].writeback)
9220 inst.instruction |= WRITE_BACK;
9221 inst.instruction |= inst.operands[1].reg << 16;
9222 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9223 inst.instruction |= inst.operands[1].imm;
9226 encode_arm_cp_address (1, TRUE, FALSE, 0);
9230 do_iwmmxt_wshufh (void)
9232 inst.instruction |= inst.operands[0].reg << 12;
9233 inst.instruction |= inst.operands[1].reg << 16;
9234 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9235 inst.instruction |= (inst.operands[2].imm & 0x0f);
9239 do_iwmmxt_wzero (void)
9241 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9242 inst.instruction |= inst.operands[0].reg;
9243 inst.instruction |= inst.operands[0].reg << 12;
9244 inst.instruction |= inst.operands[0].reg << 16;
9248 do_iwmmxt_wrwrwr_or_imm5 (void)
9250 if (inst.operands[2].isreg)
9253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9254 _("immediate operand requires iWMMXt2"));
9256 if (inst.operands[2].imm == 0)
9258 switch ((inst.instruction >> 20) & 0xf)
9264 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9265 inst.operands[2].imm = 16;
9266 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9272 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9273 inst.operands[2].imm = 32;
9274 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9281 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9283 wrn = (inst.instruction >> 16) & 0xf;
9284 inst.instruction &= 0xff0fff0f;
9285 inst.instruction |= wrn;
9286 /* Bail out here; the instruction is now assembled. */
9291 /* Map 32 -> 0, etc. */
9292 inst.operands[2].imm &= 0x1f;
9293 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9297 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9298 operations first, then control, shift, and load/store. */
9300 /* Insns like "foo X,Y,Z". */
9303 do_mav_triple (void)
9305 inst.instruction |= inst.operands[0].reg << 16;
9306 inst.instruction |= inst.operands[1].reg;
9307 inst.instruction |= inst.operands[2].reg << 12;
9310 /* Insns like "foo W,X,Y,Z".
9311 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9316 inst.instruction |= inst.operands[0].reg << 5;
9317 inst.instruction |= inst.operands[1].reg << 12;
9318 inst.instruction |= inst.operands[2].reg << 16;
9319 inst.instruction |= inst.operands[3].reg;
9322 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9326 inst.instruction |= inst.operands[1].reg << 12;
9329 /* Maverick shift immediate instructions.
9330 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9331 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9336 int imm = inst.operands[2].imm;
9338 inst.instruction |= inst.operands[0].reg << 12;
9339 inst.instruction |= inst.operands[1].reg << 16;
9341 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9342 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9343 Bit 4 should be 0. */
9344 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9346 inst.instruction |= imm;
9349 /* XScale instructions. Also sorted arithmetic before move. */
9351 /* Xscale multiply-accumulate (argument parse)
9354 MIAxycc acc0,Rm,Rs. */
9359 inst.instruction |= inst.operands[1].reg;
9360 inst.instruction |= inst.operands[2].reg << 12;
9363 /* Xscale move-accumulator-register (argument parse)
9365 MARcc acc0,RdLo,RdHi. */
9370 inst.instruction |= inst.operands[1].reg << 12;
9371 inst.instruction |= inst.operands[2].reg << 16;
9374 /* Xscale move-register-accumulator (argument parse)
9376 MRAcc RdLo,RdHi,acc0. */
9381 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9382 inst.instruction |= inst.operands[0].reg << 12;
9383 inst.instruction |= inst.operands[1].reg << 16;
9386 /* Encoding functions relevant only to Thumb. */
9388 /* inst.operands[i] is a shifted-register operand; encode
9389 it into inst.instruction in the format used by Thumb32. */
9392 encode_thumb32_shifted_operand (int i)
9394 unsigned int value = inst.reloc.exp.X_add_number;
9395 unsigned int shift = inst.operands[i].shift_kind;
9397 constraint (inst.operands[i].immisreg,
9398 _("shift by register not allowed in thumb mode"));
9399 inst.instruction |= inst.operands[i].reg;
9400 if (shift == SHIFT_RRX)
9401 inst.instruction |= SHIFT_ROR << 4;
9404 constraint (inst.reloc.exp.X_op != O_constant,
9405 _("expression too complex"));
9407 constraint (value > 32
9408 || (value == 32 && (shift == SHIFT_LSL
9409 || shift == SHIFT_ROR)),
9410 _("shift expression is too large"));
9414 else if (value == 32)
9417 inst.instruction |= shift << 4;
9418 inst.instruction |= (value & 0x1c) << 10;
9419 inst.instruction |= (value & 0x03) << 6;
9424 /* inst.operands[i] was set up by parse_address. Encode it into a
9425 Thumb32 format load or store instruction. Reject forms that cannot
9426 be used with such instructions. If is_t is true, reject forms that
9427 cannot be used with a T instruction; if is_d is true, reject forms
9428 that cannot be used with a D instruction. If it is a store insn,
9432 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9434 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9436 constraint (!inst.operands[i].isreg,
9437 _("Instruction does not support =N addresses"));
9439 inst.instruction |= inst.operands[i].reg << 16;
9440 if (inst.operands[i].immisreg)
9442 constraint (is_pc, BAD_PC_ADDRESSING);
9443 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9444 constraint (inst.operands[i].negative,
9445 _("Thumb does not support negative register indexing"));
9446 constraint (inst.operands[i].postind,
9447 _("Thumb does not support register post-indexing"));
9448 constraint (inst.operands[i].writeback,
9449 _("Thumb does not support register indexing with writeback"));
9450 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9451 _("Thumb supports only LSL in shifted register indexing"));
9453 inst.instruction |= inst.operands[i].imm;
9454 if (inst.operands[i].shifted)
9456 constraint (inst.reloc.exp.X_op != O_constant,
9457 _("expression too complex"));
9458 constraint (inst.reloc.exp.X_add_number < 0
9459 || inst.reloc.exp.X_add_number > 3,
9460 _("shift out of range"));
9461 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9463 inst.reloc.type = BFD_RELOC_UNUSED;
9465 else if (inst.operands[i].preind)
9467 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9468 constraint (is_t && inst.operands[i].writeback,
9469 _("cannot use writeback with this instruction"));
9470 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9471 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9475 inst.instruction |= 0x01000000;
9476 if (inst.operands[i].writeback)
9477 inst.instruction |= 0x00200000;
9481 inst.instruction |= 0x00000c00;
9482 if (inst.operands[i].writeback)
9483 inst.instruction |= 0x00000100;
9485 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9487 else if (inst.operands[i].postind)
9489 gas_assert (inst.operands[i].writeback);
9490 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9491 constraint (is_t, _("cannot use post-indexing with this instruction"));
9494 inst.instruction |= 0x00200000;
9496 inst.instruction |= 0x00000900;
9497 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9499 else /* unindexed - only for coprocessor */
9500 inst.error = _("instruction does not accept unindexed addressing");
9503 /* Table of Thumb instructions which exist in both 16- and 32-bit
9504 encodings (the latter only in post-V6T2 cores). The index is the
9505 value used in the insns table below. When there is more than one
9506 possible 16-bit encoding for the instruction, this table always
9508 Also contains several pseudo-instructions used during relaxation. */
9509 #define T16_32_TAB \
9510 X(_adc, 4140, eb400000), \
9511 X(_adcs, 4140, eb500000), \
9512 X(_add, 1c00, eb000000), \
9513 X(_adds, 1c00, eb100000), \
9514 X(_addi, 0000, f1000000), \
9515 X(_addis, 0000, f1100000), \
9516 X(_add_pc,000f, f20f0000), \
9517 X(_add_sp,000d, f10d0000), \
9518 X(_adr, 000f, f20f0000), \
9519 X(_and, 4000, ea000000), \
9520 X(_ands, 4000, ea100000), \
9521 X(_asr, 1000, fa40f000), \
9522 X(_asrs, 1000, fa50f000), \
9523 X(_b, e000, f000b000), \
9524 X(_bcond, d000, f0008000), \
9525 X(_bic, 4380, ea200000), \
9526 X(_bics, 4380, ea300000), \
9527 X(_cmn, 42c0, eb100f00), \
9528 X(_cmp, 2800, ebb00f00), \
9529 X(_cpsie, b660, f3af8400), \
9530 X(_cpsid, b670, f3af8600), \
9531 X(_cpy, 4600, ea4f0000), \
9532 X(_dec_sp,80dd, f1ad0d00), \
9533 X(_eor, 4040, ea800000), \
9534 X(_eors, 4040, ea900000), \
9535 X(_inc_sp,00dd, f10d0d00), \
9536 X(_ldmia, c800, e8900000), \
9537 X(_ldr, 6800, f8500000), \
9538 X(_ldrb, 7800, f8100000), \
9539 X(_ldrh, 8800, f8300000), \
9540 X(_ldrsb, 5600, f9100000), \
9541 X(_ldrsh, 5e00, f9300000), \
9542 X(_ldr_pc,4800, f85f0000), \
9543 X(_ldr_pc2,4800, f85f0000), \
9544 X(_ldr_sp,9800, f85d0000), \
9545 X(_lsl, 0000, fa00f000), \
9546 X(_lsls, 0000, fa10f000), \
9547 X(_lsr, 0800, fa20f000), \
9548 X(_lsrs, 0800, fa30f000), \
9549 X(_mov, 2000, ea4f0000), \
9550 X(_movs, 2000, ea5f0000), \
9551 X(_mul, 4340, fb00f000), \
9552 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9553 X(_mvn, 43c0, ea6f0000), \
9554 X(_mvns, 43c0, ea7f0000), \
9555 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9556 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9557 X(_orr, 4300, ea400000), \
9558 X(_orrs, 4300, ea500000), \
9559 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9560 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9561 X(_rev, ba00, fa90f080), \
9562 X(_rev16, ba40, fa90f090), \
9563 X(_revsh, bac0, fa90f0b0), \
9564 X(_ror, 41c0, fa60f000), \
9565 X(_rors, 41c0, fa70f000), \
9566 X(_sbc, 4180, eb600000), \
9567 X(_sbcs, 4180, eb700000), \
9568 X(_stmia, c000, e8800000), \
9569 X(_str, 6000, f8400000), \
9570 X(_strb, 7000, f8000000), \
9571 X(_strh, 8000, f8200000), \
9572 X(_str_sp,9000, f84d0000), \
9573 X(_sub, 1e00, eba00000), \
9574 X(_subs, 1e00, ebb00000), \
9575 X(_subi, 8000, f1a00000), \
9576 X(_subis, 8000, f1b00000), \
9577 X(_sxtb, b240, fa4ff080), \
9578 X(_sxth, b200, fa0ff080), \
9579 X(_tst, 4200, ea100f00), \
9580 X(_uxtb, b2c0, fa5ff080), \
9581 X(_uxth, b280, fa1ff080), \
9582 X(_nop, bf00, f3af8000), \
9583 X(_yield, bf10, f3af8001), \
9584 X(_wfe, bf20, f3af8002), \
9585 X(_wfi, bf30, f3af8003), \
9586 X(_sev, bf40, f3af8004), \
9587 X(_sevl, bf50, f3af8005)
9589 /* To catch errors in encoding functions, the codes are all offset by
9590 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9591 as 16-bit instructions. */
9592 #define X(a,b,c) T_MNEM##a
9593 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9596 #define X(a,b,c) 0x##b
9597 static const unsigned short thumb_op16[] = { T16_32_TAB };
9598 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9601 #define X(a,b,c) 0x##c
9602 static const unsigned int thumb_op32[] = { T16_32_TAB };
9603 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9604 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9608 /* Thumb instruction encoders, in alphabetical order. */
9613 do_t_add_sub_w (void)
9617 Rd = inst.operands[0].reg;
9618 Rn = inst.operands[1].reg;
9620 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9621 is the SP-{plus,minus}-immediate form of the instruction. */
9623 constraint (Rd == REG_PC, BAD_PC);
9625 reject_bad_reg (Rd);
9627 inst.instruction |= (Rn << 16) | (Rd << 8);
9628 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9631 /* Parse an add or subtract instruction. We get here with inst.instruction
9632 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9639 Rd = inst.operands[0].reg;
9640 Rs = (inst.operands[1].present
9641 ? inst.operands[1].reg /* Rd, Rs, foo */
9642 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9645 set_it_insn_type_last ();
9653 flags = (inst.instruction == T_MNEM_adds
9654 || inst.instruction == T_MNEM_subs);
9656 narrow = !in_it_block ();
9658 narrow = in_it_block ();
9659 if (!inst.operands[2].isreg)
9663 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9665 add = (inst.instruction == T_MNEM_add
9666 || inst.instruction == T_MNEM_adds);
9668 if (inst.size_req != 4)
9670 /* Attempt to use a narrow opcode, with relaxation if
9672 if (Rd == REG_SP && Rs == REG_SP && !flags)
9673 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9674 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9675 opcode = T_MNEM_add_sp;
9676 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9677 opcode = T_MNEM_add_pc;
9678 else if (Rd <= 7 && Rs <= 7 && narrow)
9681 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9683 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9687 inst.instruction = THUMB_OP16(opcode);
9688 inst.instruction |= (Rd << 4) | Rs;
9689 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9690 if (inst.size_req != 2)
9691 inst.relax = opcode;
9694 constraint (inst.size_req == 2, BAD_HIREG);
9696 if (inst.size_req == 4
9697 || (inst.size_req != 2 && !opcode))
9701 constraint (add, BAD_PC);
9702 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9703 _("only SUBS PC, LR, #const allowed"));
9704 constraint (inst.reloc.exp.X_op != O_constant,
9705 _("expression too complex"));
9706 constraint (inst.reloc.exp.X_add_number < 0
9707 || inst.reloc.exp.X_add_number > 0xff,
9708 _("immediate value out of range"));
9709 inst.instruction = T2_SUBS_PC_LR
9710 | inst.reloc.exp.X_add_number;
9711 inst.reloc.type = BFD_RELOC_UNUSED;
9714 else if (Rs == REG_PC)
9716 /* Always use addw/subw. */
9717 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9718 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9722 inst.instruction = THUMB_OP32 (inst.instruction);
9723 inst.instruction = (inst.instruction & 0xe1ffffff)
9726 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9728 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9730 inst.instruction |= Rd << 8;
9731 inst.instruction |= Rs << 16;
9736 unsigned int value = inst.reloc.exp.X_add_number;
9737 unsigned int shift = inst.operands[2].shift_kind;
9739 Rn = inst.operands[2].reg;
9740 /* See if we can do this with a 16-bit instruction. */
9741 if (!inst.operands[2].shifted && inst.size_req != 4)
9743 if (Rd > 7 || Rs > 7 || Rn > 7)
9748 inst.instruction = ((inst.instruction == T_MNEM_adds
9749 || inst.instruction == T_MNEM_add)
9752 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9756 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9758 /* Thumb-1 cores (except v6-M) require at least one high
9759 register in a narrow non flag setting add. */
9760 if (Rd > 7 || Rn > 7
9761 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9762 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9769 inst.instruction = T_OPCODE_ADD_HI;
9770 inst.instruction |= (Rd & 8) << 4;
9771 inst.instruction |= (Rd & 7);
9772 inst.instruction |= Rn << 3;
9778 constraint (Rd == REG_PC, BAD_PC);
9779 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9780 constraint (Rs == REG_PC, BAD_PC);
9781 reject_bad_reg (Rn);
9783 /* If we get here, it can't be done in 16 bits. */
9784 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9785 _("shift must be constant"));
9786 inst.instruction = THUMB_OP32 (inst.instruction);
9787 inst.instruction |= Rd << 8;
9788 inst.instruction |= Rs << 16;
9789 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9790 _("shift value over 3 not allowed in thumb mode"));
9791 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9792 _("only LSL shift allowed in thumb mode"));
9793 encode_thumb32_shifted_operand (2);
9798 constraint (inst.instruction == T_MNEM_adds
9799 || inst.instruction == T_MNEM_subs,
9802 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9804 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9805 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9808 inst.instruction = (inst.instruction == T_MNEM_add
9810 inst.instruction |= (Rd << 4) | Rs;
9811 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9815 Rn = inst.operands[2].reg;
9816 constraint (inst.operands[2].shifted, _("unshifted register required"));
9818 /* We now have Rd, Rs, and Rn set to registers. */
9819 if (Rd > 7 || Rs > 7 || Rn > 7)
9821 /* Can't do this for SUB. */
9822 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9823 inst.instruction = T_OPCODE_ADD_HI;
9824 inst.instruction |= (Rd & 8) << 4;
9825 inst.instruction |= (Rd & 7);
9827 inst.instruction |= Rn << 3;
9829 inst.instruction |= Rs << 3;
9831 constraint (1, _("dest must overlap one source register"));
9835 inst.instruction = (inst.instruction == T_MNEM_add
9836 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9837 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9847 Rd = inst.operands[0].reg;
9848 reject_bad_reg (Rd);
9850 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9852 /* Defer to section relaxation. */
9853 inst.relax = inst.instruction;
9854 inst.instruction = THUMB_OP16 (inst.instruction);
9855 inst.instruction |= Rd << 4;
9857 else if (unified_syntax && inst.size_req != 2)
9859 /* Generate a 32-bit opcode. */
9860 inst.instruction = THUMB_OP32 (inst.instruction);
9861 inst.instruction |= Rd << 8;
9862 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9863 inst.reloc.pc_rel = 1;
9867 /* Generate a 16-bit opcode. */
9868 inst.instruction = THUMB_OP16 (inst.instruction);
9869 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9870 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9871 inst.reloc.pc_rel = 1;
9873 inst.instruction |= Rd << 4;
9877 /* Arithmetic instructions for which there is just one 16-bit
9878 instruction encoding, and it allows only two low registers.
9879 For maximal compatibility with ARM syntax, we allow three register
9880 operands even when Thumb-32 instructions are not available, as long
9881 as the first two are identical. For instance, both "sbc r0,r1" and
9882 "sbc r0,r0,r1" are allowed. */
9888 Rd = inst.operands[0].reg;
9889 Rs = (inst.operands[1].present
9890 ? inst.operands[1].reg /* Rd, Rs, foo */
9891 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9892 Rn = inst.operands[2].reg;
9894 reject_bad_reg (Rd);
9895 reject_bad_reg (Rs);
9896 if (inst.operands[2].isreg)
9897 reject_bad_reg (Rn);
9901 if (!inst.operands[2].isreg)
9903 /* For an immediate, we always generate a 32-bit opcode;
9904 section relaxation will shrink it later if possible. */
9905 inst.instruction = THUMB_OP32 (inst.instruction);
9906 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9907 inst.instruction |= Rd << 8;
9908 inst.instruction |= Rs << 16;
9909 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9915 /* See if we can do this with a 16-bit instruction. */
9916 if (THUMB_SETS_FLAGS (inst.instruction))
9917 narrow = !in_it_block ();
9919 narrow = in_it_block ();
9921 if (Rd > 7 || Rn > 7 || Rs > 7)
9923 if (inst.operands[2].shifted)
9925 if (inst.size_req == 4)
9931 inst.instruction = THUMB_OP16 (inst.instruction);
9932 inst.instruction |= Rd;
9933 inst.instruction |= Rn << 3;
9937 /* If we get here, it can't be done in 16 bits. */
9938 constraint (inst.operands[2].shifted
9939 && inst.operands[2].immisreg,
9940 _("shift must be constant"));
9941 inst.instruction = THUMB_OP32 (inst.instruction);
9942 inst.instruction |= Rd << 8;
9943 inst.instruction |= Rs << 16;
9944 encode_thumb32_shifted_operand (2);
9949 /* On its face this is a lie - the instruction does set the
9950 flags. However, the only supported mnemonic in this mode
9952 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9954 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9955 _("unshifted register required"));
9956 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9957 constraint (Rd != Rs,
9958 _("dest and source1 must be the same register"));
9960 inst.instruction = THUMB_OP16 (inst.instruction);
9961 inst.instruction |= Rd;
9962 inst.instruction |= Rn << 3;
9966 /* Similarly, but for instructions where the arithmetic operation is
9967 commutative, so we can allow either of them to be different from
9968 the destination operand in a 16-bit instruction. For instance, all
9969 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9976 Rd = inst.operands[0].reg;
9977 Rs = (inst.operands[1].present
9978 ? inst.operands[1].reg /* Rd, Rs, foo */
9979 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9980 Rn = inst.operands[2].reg;
9982 reject_bad_reg (Rd);
9983 reject_bad_reg (Rs);
9984 if (inst.operands[2].isreg)
9985 reject_bad_reg (Rn);
9989 if (!inst.operands[2].isreg)
9991 /* For an immediate, we always generate a 32-bit opcode;
9992 section relaxation will shrink it later if possible. */
9993 inst.instruction = THUMB_OP32 (inst.instruction);
9994 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9995 inst.instruction |= Rd << 8;
9996 inst.instruction |= Rs << 16;
9997 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10001 bfd_boolean narrow;
10003 /* See if we can do this with a 16-bit instruction. */
10004 if (THUMB_SETS_FLAGS (inst.instruction))
10005 narrow = !in_it_block ();
10007 narrow = in_it_block ();
10009 if (Rd > 7 || Rn > 7 || Rs > 7)
10011 if (inst.operands[2].shifted)
10013 if (inst.size_req == 4)
10020 inst.instruction = THUMB_OP16 (inst.instruction);
10021 inst.instruction |= Rd;
10022 inst.instruction |= Rn << 3;
10027 inst.instruction = THUMB_OP16 (inst.instruction);
10028 inst.instruction |= Rd;
10029 inst.instruction |= Rs << 3;
10034 /* If we get here, it can't be done in 16 bits. */
10035 constraint (inst.operands[2].shifted
10036 && inst.operands[2].immisreg,
10037 _("shift must be constant"));
10038 inst.instruction = THUMB_OP32 (inst.instruction);
10039 inst.instruction |= Rd << 8;
10040 inst.instruction |= Rs << 16;
10041 encode_thumb32_shifted_operand (2);
10046 /* On its face this is a lie - the instruction does set the
10047 flags. However, the only supported mnemonic in this mode
10048 says it doesn't. */
10049 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10051 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10052 _("unshifted register required"));
10053 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10055 inst.instruction = THUMB_OP16 (inst.instruction);
10056 inst.instruction |= Rd;
10059 inst.instruction |= Rn << 3;
10061 inst.instruction |= Rs << 3;
10063 constraint (1, _("dest must overlap one source register"));
10068 do_t_barrier (void)
10070 if (inst.operands[0].present)
10072 constraint ((inst.instruction & 0xf0) != 0x40
10073 && inst.operands[0].imm > 0xf
10074 && inst.operands[0].imm < 0x0,
10075 _("bad barrier type"));
10076 inst.instruction |= inst.operands[0].imm;
10079 inst.instruction |= 0xf;
10086 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10087 constraint (msb > 32, _("bit-field extends past end of register"));
10088 /* The instruction encoding stores the LSB and MSB,
10089 not the LSB and width. */
10090 Rd = inst.operands[0].reg;
10091 reject_bad_reg (Rd);
10092 inst.instruction |= Rd << 8;
10093 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10094 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10095 inst.instruction |= msb - 1;
10104 Rd = inst.operands[0].reg;
10105 reject_bad_reg (Rd);
10107 /* #0 in second position is alternative syntax for bfc, which is
10108 the same instruction but with REG_PC in the Rm field. */
10109 if (!inst.operands[1].isreg)
10113 Rn = inst.operands[1].reg;
10114 reject_bad_reg (Rn);
10117 msb = inst.operands[2].imm + inst.operands[3].imm;
10118 constraint (msb > 32, _("bit-field extends past end of register"));
10119 /* The instruction encoding stores the LSB and MSB,
10120 not the LSB and width. */
10121 inst.instruction |= Rd << 8;
10122 inst.instruction |= Rn << 16;
10123 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10124 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10125 inst.instruction |= msb - 1;
10133 Rd = inst.operands[0].reg;
10134 Rn = inst.operands[1].reg;
10136 reject_bad_reg (Rd);
10137 reject_bad_reg (Rn);
10139 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10140 _("bit-field extends past end of register"));
10141 inst.instruction |= Rd << 8;
10142 inst.instruction |= Rn << 16;
10143 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10144 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10145 inst.instruction |= inst.operands[3].imm - 1;
10148 /* ARM V5 Thumb BLX (argument parse)
10149 BLX <target_addr> which is BLX(1)
10150 BLX <Rm> which is BLX(2)
10151 Unfortunately, there are two different opcodes for this mnemonic.
10152 So, the insns[].value is not used, and the code here zaps values
10153 into inst.instruction.
10155 ??? How to take advantage of the additional two bits of displacement
10156 available in Thumb32 mode? Need new relocation? */
10161 set_it_insn_type_last ();
10163 if (inst.operands[0].isreg)
10165 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10166 /* We have a register, so this is BLX(2). */
10167 inst.instruction |= inst.operands[0].reg << 3;
10171 /* No register. This must be BLX(1). */
10172 inst.instruction = 0xf000e800;
10173 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10185 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10187 if (in_it_block ())
10189 /* Conditional branches inside IT blocks are encoded as unconditional
10191 cond = COND_ALWAYS;
10196 if (cond != COND_ALWAYS)
10197 opcode = T_MNEM_bcond;
10199 opcode = inst.instruction;
10202 && (inst.size_req == 4
10203 || (inst.size_req != 2
10204 && (inst.operands[0].hasreloc
10205 || inst.reloc.exp.X_op == O_constant))))
10207 inst.instruction = THUMB_OP32(opcode);
10208 if (cond == COND_ALWAYS)
10209 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10212 gas_assert (cond != 0xF);
10213 inst.instruction |= cond << 22;
10214 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10219 inst.instruction = THUMB_OP16(opcode);
10220 if (cond == COND_ALWAYS)
10221 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10224 inst.instruction |= cond << 8;
10225 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10227 /* Allow section relaxation. */
10228 if (unified_syntax && inst.size_req != 2)
10229 inst.relax = opcode;
10231 inst.reloc.type = reloc;
10232 inst.reloc.pc_rel = 1;
10235 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10236 between the two is the maximum immediate allowed - which is passed in
10239 do_t_bkpt_hlt1 (int range)
10241 constraint (inst.cond != COND_ALWAYS,
10242 _("instruction is always unconditional"));
10243 if (inst.operands[0].present)
10245 constraint (inst.operands[0].imm > range,
10246 _("immediate value out of range"));
10247 inst.instruction |= inst.operands[0].imm;
10250 set_it_insn_type (NEUTRAL_IT_INSN);
10256 do_t_bkpt_hlt1 (63);
10262 do_t_bkpt_hlt1 (255);
10266 do_t_branch23 (void)
10268 set_it_insn_type_last ();
10269 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10271 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10272 this file. We used to simply ignore the PLT reloc type here --
10273 the branch encoding is now needed to deal with TLSCALL relocs.
10274 So if we see a PLT reloc now, put it back to how it used to be to
10275 keep the preexisting behaviour. */
10276 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10277 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10279 #if defined(OBJ_COFF)
10280 /* If the destination of the branch is a defined symbol which does not have
10281 the THUMB_FUNC attribute, then we must be calling a function which has
10282 the (interfacearm) attribute. We look for the Thumb entry point to that
10283 function and change the branch to refer to that function instead. */
10284 if ( inst.reloc.exp.X_op == O_symbol
10285 && inst.reloc.exp.X_add_symbol != NULL
10286 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10287 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10288 inst.reloc.exp.X_add_symbol =
10289 find_real_start (inst.reloc.exp.X_add_symbol);
10296 set_it_insn_type_last ();
10297 inst.instruction |= inst.operands[0].reg << 3;
10298 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10299 should cause the alignment to be checked once it is known. This is
10300 because BX PC only works if the instruction is word aligned. */
10308 set_it_insn_type_last ();
10309 Rm = inst.operands[0].reg;
10310 reject_bad_reg (Rm);
10311 inst.instruction |= Rm << 16;
10320 Rd = inst.operands[0].reg;
10321 Rm = inst.operands[1].reg;
10323 reject_bad_reg (Rd);
10324 reject_bad_reg (Rm);
10326 inst.instruction |= Rd << 8;
10327 inst.instruction |= Rm << 16;
10328 inst.instruction |= Rm;
10334 set_it_insn_type (OUTSIDE_IT_INSN);
10335 inst.instruction |= inst.operands[0].imm;
10341 set_it_insn_type (OUTSIDE_IT_INSN);
10343 && (inst.operands[1].present || inst.size_req == 4)
10344 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10346 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10347 inst.instruction = 0xf3af8000;
10348 inst.instruction |= imod << 9;
10349 inst.instruction |= inst.operands[0].imm << 5;
10350 if (inst.operands[1].present)
10351 inst.instruction |= 0x100 | inst.operands[1].imm;
10355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10356 && (inst.operands[0].imm & 4),
10357 _("selected processor does not support 'A' form "
10358 "of this instruction"));
10359 constraint (inst.operands[1].present || inst.size_req == 4,
10360 _("Thumb does not support the 2-argument "
10361 "form of this instruction"));
10362 inst.instruction |= inst.operands[0].imm;
10366 /* THUMB CPY instruction (argument parse). */
10371 if (inst.size_req == 4)
10373 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10374 inst.instruction |= inst.operands[0].reg << 8;
10375 inst.instruction |= inst.operands[1].reg;
10379 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10380 inst.instruction |= (inst.operands[0].reg & 0x7);
10381 inst.instruction |= inst.operands[1].reg << 3;
10388 set_it_insn_type (OUTSIDE_IT_INSN);
10389 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10390 inst.instruction |= inst.operands[0].reg;
10391 inst.reloc.pc_rel = 1;
10392 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10398 inst.instruction |= inst.operands[0].imm;
10404 unsigned Rd, Rn, Rm;
10406 Rd = inst.operands[0].reg;
10407 Rn = (inst.operands[1].present
10408 ? inst.operands[1].reg : Rd);
10409 Rm = inst.operands[2].reg;
10411 reject_bad_reg (Rd);
10412 reject_bad_reg (Rn);
10413 reject_bad_reg (Rm);
10415 inst.instruction |= Rd << 8;
10416 inst.instruction |= Rn << 16;
10417 inst.instruction |= Rm;
10423 if (unified_syntax && inst.size_req == 4)
10424 inst.instruction = THUMB_OP32 (inst.instruction);
10426 inst.instruction = THUMB_OP16 (inst.instruction);
10432 unsigned int cond = inst.operands[0].imm;
10434 set_it_insn_type (IT_INSN);
10435 now_it.mask = (inst.instruction & 0xf) | 0x10;
10437 now_it.warn_deprecated = FALSE;
10439 /* If the condition is a negative condition, invert the mask. */
10440 if ((cond & 0x1) == 0x0)
10442 unsigned int mask = inst.instruction & 0x000f;
10444 if ((mask & 0x7) == 0)
10446 /* No conversion needed. */
10447 now_it.block_length = 1;
10449 else if ((mask & 0x3) == 0)
10452 now_it.block_length = 2;
10454 else if ((mask & 0x1) == 0)
10457 now_it.block_length = 3;
10462 now_it.block_length = 4;
10465 inst.instruction &= 0xfff0;
10466 inst.instruction |= mask;
10469 inst.instruction |= cond << 4;
10472 /* Helper function used for both push/pop and ldm/stm. */
10474 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10478 load = (inst.instruction & (1 << 20)) != 0;
10480 if (mask & (1 << 13))
10481 inst.error = _("SP not allowed in register list");
10483 if ((mask & (1 << base)) != 0
10485 inst.error = _("having the base register in the register list when "
10486 "using write back is UNPREDICTABLE");
10490 if (mask & (1 << 15))
10492 if (mask & (1 << 14))
10493 inst.error = _("LR and PC should not both be in register list");
10495 set_it_insn_type_last ();
10500 if (mask & (1 << 15))
10501 inst.error = _("PC not allowed in register list");
10504 if ((mask & (mask - 1)) == 0)
10506 /* Single register transfers implemented as str/ldr. */
10509 if (inst.instruction & (1 << 23))
10510 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10512 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10516 if (inst.instruction & (1 << 23))
10517 inst.instruction = 0x00800000; /* ia -> [base] */
10519 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10522 inst.instruction |= 0xf8400000;
10524 inst.instruction |= 0x00100000;
10526 mask = ffs (mask) - 1;
10529 else if (writeback)
10530 inst.instruction |= WRITE_BACK;
10532 inst.instruction |= mask;
10533 inst.instruction |= base << 16;
10539 /* This really doesn't seem worth it. */
10540 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10541 _("expression too complex"));
10542 constraint (inst.operands[1].writeback,
10543 _("Thumb load/store multiple does not support {reglist}^"));
10545 if (unified_syntax)
10547 bfd_boolean narrow;
10551 /* See if we can use a 16-bit instruction. */
10552 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10553 && inst.size_req != 4
10554 && !(inst.operands[1].imm & ~0xff))
10556 mask = 1 << inst.operands[0].reg;
10558 if (inst.operands[0].reg <= 7)
10560 if (inst.instruction == T_MNEM_stmia
10561 ? inst.operands[0].writeback
10562 : (inst.operands[0].writeback
10563 == !(inst.operands[1].imm & mask)))
10565 if (inst.instruction == T_MNEM_stmia
10566 && (inst.operands[1].imm & mask)
10567 && (inst.operands[1].imm & (mask - 1)))
10568 as_warn (_("value stored for r%d is UNKNOWN"),
10569 inst.operands[0].reg);
10571 inst.instruction = THUMB_OP16 (inst.instruction);
10572 inst.instruction |= inst.operands[0].reg << 8;
10573 inst.instruction |= inst.operands[1].imm;
10576 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10578 /* This means 1 register in reg list one of 3 situations:
10579 1. Instruction is stmia, but without writeback.
10580 2. lmdia without writeback, but with Rn not in
10582 3. ldmia with writeback, but with Rn in reglist.
10583 Case 3 is UNPREDICTABLE behaviour, so we handle
10584 case 1 and 2 which can be converted into a 16-bit
10585 str or ldr. The SP cases are handled below. */
10586 unsigned long opcode;
10587 /* First, record an error for Case 3. */
10588 if (inst.operands[1].imm & mask
10589 && inst.operands[0].writeback)
10591 _("having the base register in the register list when "
10592 "using write back is UNPREDICTABLE");
10594 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10596 inst.instruction = THUMB_OP16 (opcode);
10597 inst.instruction |= inst.operands[0].reg << 3;
10598 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10602 else if (inst.operands[0] .reg == REG_SP)
10604 if (inst.operands[0].writeback)
10607 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10608 ? T_MNEM_push : T_MNEM_pop);
10609 inst.instruction |= inst.operands[1].imm;
10612 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10615 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10616 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10617 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10625 if (inst.instruction < 0xffff)
10626 inst.instruction = THUMB_OP32 (inst.instruction);
10628 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10629 inst.operands[0].writeback);
10634 constraint (inst.operands[0].reg > 7
10635 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10636 constraint (inst.instruction != T_MNEM_ldmia
10637 && inst.instruction != T_MNEM_stmia,
10638 _("Thumb-2 instruction only valid in unified syntax"));
10639 if (inst.instruction == T_MNEM_stmia)
10641 if (!inst.operands[0].writeback)
10642 as_warn (_("this instruction will write back the base register"));
10643 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10644 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10645 as_warn (_("value stored for r%d is UNKNOWN"),
10646 inst.operands[0].reg);
10650 if (!inst.operands[0].writeback
10651 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10652 as_warn (_("this instruction will write back the base register"));
10653 else if (inst.operands[0].writeback
10654 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10655 as_warn (_("this instruction will not write back the base register"));
10658 inst.instruction = THUMB_OP16 (inst.instruction);
10659 inst.instruction |= inst.operands[0].reg << 8;
10660 inst.instruction |= inst.operands[1].imm;
10667 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10668 || inst.operands[1].postind || inst.operands[1].writeback
10669 || inst.operands[1].immisreg || inst.operands[1].shifted
10670 || inst.operands[1].negative,
10673 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10675 inst.instruction |= inst.operands[0].reg << 12;
10676 inst.instruction |= inst.operands[1].reg << 16;
10677 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10683 if (!inst.operands[1].present)
10685 constraint (inst.operands[0].reg == REG_LR,
10686 _("r14 not allowed as first register "
10687 "when second register is omitted"));
10688 inst.operands[1].reg = inst.operands[0].reg + 1;
10690 constraint (inst.operands[0].reg == inst.operands[1].reg,
10693 inst.instruction |= inst.operands[0].reg << 12;
10694 inst.instruction |= inst.operands[1].reg << 8;
10695 inst.instruction |= inst.operands[2].reg << 16;
10701 unsigned long opcode;
10704 if (inst.operands[0].isreg
10705 && !inst.operands[0].preind
10706 && inst.operands[0].reg == REG_PC)
10707 set_it_insn_type_last ();
10709 opcode = inst.instruction;
10710 if (unified_syntax)
10712 if (!inst.operands[1].isreg)
10714 if (opcode <= 0xffff)
10715 inst.instruction = THUMB_OP32 (opcode);
10716 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10719 if (inst.operands[1].isreg
10720 && !inst.operands[1].writeback
10721 && !inst.operands[1].shifted && !inst.operands[1].postind
10722 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10723 && opcode <= 0xffff
10724 && inst.size_req != 4)
10726 /* Insn may have a 16-bit form. */
10727 Rn = inst.operands[1].reg;
10728 if (inst.operands[1].immisreg)
10730 inst.instruction = THUMB_OP16 (opcode);
10732 if (Rn <= 7 && inst.operands[1].imm <= 7)
10734 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10735 reject_bad_reg (inst.operands[1].imm);
10737 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10738 && opcode != T_MNEM_ldrsb)
10739 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10740 || (Rn == REG_SP && opcode == T_MNEM_str))
10747 if (inst.reloc.pc_rel)
10748 opcode = T_MNEM_ldr_pc2;
10750 opcode = T_MNEM_ldr_pc;
10754 if (opcode == T_MNEM_ldr)
10755 opcode = T_MNEM_ldr_sp;
10757 opcode = T_MNEM_str_sp;
10759 inst.instruction = inst.operands[0].reg << 8;
10763 inst.instruction = inst.operands[0].reg;
10764 inst.instruction |= inst.operands[1].reg << 3;
10766 inst.instruction |= THUMB_OP16 (opcode);
10767 if (inst.size_req == 2)
10768 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10770 inst.relax = opcode;
10774 /* Definitely a 32-bit variant. */
10776 /* Warning for Erratum 752419. */
10777 if (opcode == T_MNEM_ldr
10778 && inst.operands[0].reg == REG_SP
10779 && inst.operands[1].writeback == 1
10780 && !inst.operands[1].immisreg)
10782 if (no_cpu_selected ()
10783 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10784 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10785 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10786 as_warn (_("This instruction may be unpredictable "
10787 "if executed on M-profile cores "
10788 "with interrupts enabled."));
10791 /* Do some validations regarding addressing modes. */
10792 if (inst.operands[1].immisreg)
10793 reject_bad_reg (inst.operands[1].imm);
10795 constraint (inst.operands[1].writeback == 1
10796 && inst.operands[0].reg == inst.operands[1].reg,
10799 inst.instruction = THUMB_OP32 (opcode);
10800 inst.instruction |= inst.operands[0].reg << 12;
10801 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10802 check_ldr_r15_aligned ();
10806 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10808 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10810 /* Only [Rn,Rm] is acceptable. */
10811 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10812 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10813 || inst.operands[1].postind || inst.operands[1].shifted
10814 || inst.operands[1].negative,
10815 _("Thumb does not support this addressing mode"));
10816 inst.instruction = THUMB_OP16 (inst.instruction);
10820 inst.instruction = THUMB_OP16 (inst.instruction);
10821 if (!inst.operands[1].isreg)
10822 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10825 constraint (!inst.operands[1].preind
10826 || inst.operands[1].shifted
10827 || inst.operands[1].writeback,
10828 _("Thumb does not support this addressing mode"));
10829 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10831 constraint (inst.instruction & 0x0600,
10832 _("byte or halfword not valid for base register"));
10833 constraint (inst.operands[1].reg == REG_PC
10834 && !(inst.instruction & THUMB_LOAD_BIT),
10835 _("r15 based store not allowed"));
10836 constraint (inst.operands[1].immisreg,
10837 _("invalid base register for register offset"));
10839 if (inst.operands[1].reg == REG_PC)
10840 inst.instruction = T_OPCODE_LDR_PC;
10841 else if (inst.instruction & THUMB_LOAD_BIT)
10842 inst.instruction = T_OPCODE_LDR_SP;
10844 inst.instruction = T_OPCODE_STR_SP;
10846 inst.instruction |= inst.operands[0].reg << 8;
10847 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10851 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10852 if (!inst.operands[1].immisreg)
10854 /* Immediate offset. */
10855 inst.instruction |= inst.operands[0].reg;
10856 inst.instruction |= inst.operands[1].reg << 3;
10857 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10861 /* Register offset. */
10862 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10863 constraint (inst.operands[1].negative,
10864 _("Thumb does not support this addressing mode"));
10867 switch (inst.instruction)
10869 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10870 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10871 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10872 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10873 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10874 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10875 case 0x5600 /* ldrsb */:
10876 case 0x5e00 /* ldrsh */: break;
10880 inst.instruction |= inst.operands[0].reg;
10881 inst.instruction |= inst.operands[1].reg << 3;
10882 inst.instruction |= inst.operands[1].imm << 6;
10888 if (!inst.operands[1].present)
10890 inst.operands[1].reg = inst.operands[0].reg + 1;
10891 constraint (inst.operands[0].reg == REG_LR,
10892 _("r14 not allowed here"));
10893 constraint (inst.operands[0].reg == REG_R12,
10894 _("r12 not allowed here"));
10897 if (inst.operands[2].writeback
10898 && (inst.operands[0].reg == inst.operands[2].reg
10899 || inst.operands[1].reg == inst.operands[2].reg))
10900 as_warn (_("base register written back, and overlaps "
10901 "one of transfer registers"));
10903 inst.instruction |= inst.operands[0].reg << 12;
10904 inst.instruction |= inst.operands[1].reg << 8;
10905 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10911 inst.instruction |= inst.operands[0].reg << 12;
10912 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10918 unsigned Rd, Rn, Rm, Ra;
10920 Rd = inst.operands[0].reg;
10921 Rn = inst.operands[1].reg;
10922 Rm = inst.operands[2].reg;
10923 Ra = inst.operands[3].reg;
10925 reject_bad_reg (Rd);
10926 reject_bad_reg (Rn);
10927 reject_bad_reg (Rm);
10928 reject_bad_reg (Ra);
10930 inst.instruction |= Rd << 8;
10931 inst.instruction |= Rn << 16;
10932 inst.instruction |= Rm;
10933 inst.instruction |= Ra << 12;
10939 unsigned RdLo, RdHi, Rn, Rm;
10941 RdLo = inst.operands[0].reg;
10942 RdHi = inst.operands[1].reg;
10943 Rn = inst.operands[2].reg;
10944 Rm = inst.operands[3].reg;
10946 reject_bad_reg (RdLo);
10947 reject_bad_reg (RdHi);
10948 reject_bad_reg (Rn);
10949 reject_bad_reg (Rm);
10951 inst.instruction |= RdLo << 12;
10952 inst.instruction |= RdHi << 8;
10953 inst.instruction |= Rn << 16;
10954 inst.instruction |= Rm;
10958 do_t_mov_cmp (void)
10962 Rn = inst.operands[0].reg;
10963 Rm = inst.operands[1].reg;
10966 set_it_insn_type_last ();
10968 if (unified_syntax)
10970 int r0off = (inst.instruction == T_MNEM_mov
10971 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10972 unsigned long opcode;
10973 bfd_boolean narrow;
10974 bfd_boolean low_regs;
10976 low_regs = (Rn <= 7 && Rm <= 7);
10977 opcode = inst.instruction;
10978 if (in_it_block ())
10979 narrow = opcode != T_MNEM_movs;
10981 narrow = opcode != T_MNEM_movs || low_regs;
10982 if (inst.size_req == 4
10983 || inst.operands[1].shifted)
10986 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10987 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10988 && !inst.operands[1].shifted
10992 inst.instruction = T2_SUBS_PC_LR;
10996 if (opcode == T_MNEM_cmp)
10998 constraint (Rn == REG_PC, BAD_PC);
11001 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11003 warn_deprecated_sp (Rm);
11004 /* R15 was documented as a valid choice for Rm in ARMv6,
11005 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11006 tools reject R15, so we do too. */
11007 constraint (Rm == REG_PC, BAD_PC);
11010 reject_bad_reg (Rm);
11012 else if (opcode == T_MNEM_mov
11013 || opcode == T_MNEM_movs)
11015 if (inst.operands[1].isreg)
11017 if (opcode == T_MNEM_movs)
11019 reject_bad_reg (Rn);
11020 reject_bad_reg (Rm);
11024 /* This is mov.n. */
11025 if ((Rn == REG_SP || Rn == REG_PC)
11026 && (Rm == REG_SP || Rm == REG_PC))
11028 as_warn (_("Use of r%u as a source register is "
11029 "deprecated when r%u is the destination "
11030 "register."), Rm, Rn);
11035 /* This is mov.w. */
11036 constraint (Rn == REG_PC, BAD_PC);
11037 constraint (Rm == REG_PC, BAD_PC);
11038 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11042 reject_bad_reg (Rn);
11045 if (!inst.operands[1].isreg)
11047 /* Immediate operand. */
11048 if (!in_it_block () && opcode == T_MNEM_mov)
11050 if (low_regs && narrow)
11052 inst.instruction = THUMB_OP16 (opcode);
11053 inst.instruction |= Rn << 8;
11054 if (inst.size_req == 2)
11055 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11057 inst.relax = opcode;
11061 inst.instruction = THUMB_OP32 (inst.instruction);
11062 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11063 inst.instruction |= Rn << r0off;
11064 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11067 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11068 && (inst.instruction == T_MNEM_mov
11069 || inst.instruction == T_MNEM_movs))
11071 /* Register shifts are encoded as separate shift instructions. */
11072 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11074 if (in_it_block ())
11079 if (inst.size_req == 4)
11082 if (!low_regs || inst.operands[1].imm > 7)
11088 switch (inst.operands[1].shift_kind)
11091 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11094 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11097 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11100 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11106 inst.instruction = opcode;
11109 inst.instruction |= Rn;
11110 inst.instruction |= inst.operands[1].imm << 3;
11115 inst.instruction |= CONDS_BIT;
11117 inst.instruction |= Rn << 8;
11118 inst.instruction |= Rm << 16;
11119 inst.instruction |= inst.operands[1].imm;
11124 /* Some mov with immediate shift have narrow variants.
11125 Register shifts are handled above. */
11126 if (low_regs && inst.operands[1].shifted
11127 && (inst.instruction == T_MNEM_mov
11128 || inst.instruction == T_MNEM_movs))
11130 if (in_it_block ())
11131 narrow = (inst.instruction == T_MNEM_mov);
11133 narrow = (inst.instruction == T_MNEM_movs);
11138 switch (inst.operands[1].shift_kind)
11140 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11141 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11142 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11143 default: narrow = FALSE; break;
11149 inst.instruction |= Rn;
11150 inst.instruction |= Rm << 3;
11151 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11155 inst.instruction = THUMB_OP32 (inst.instruction);
11156 inst.instruction |= Rn << r0off;
11157 encode_thumb32_shifted_operand (1);
11161 switch (inst.instruction)
11164 /* In v4t or v5t a move of two lowregs produces unpredictable
11165 results. Don't allow this. */
11168 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11169 "MOV Rd, Rs with two low registers is not "
11170 "permitted on this architecture");
11171 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11175 inst.instruction = T_OPCODE_MOV_HR;
11176 inst.instruction |= (Rn & 0x8) << 4;
11177 inst.instruction |= (Rn & 0x7);
11178 inst.instruction |= Rm << 3;
11182 /* We know we have low registers at this point.
11183 Generate LSLS Rd, Rs, #0. */
11184 inst.instruction = T_OPCODE_LSL_I;
11185 inst.instruction |= Rn;
11186 inst.instruction |= Rm << 3;
11192 inst.instruction = T_OPCODE_CMP_LR;
11193 inst.instruction |= Rn;
11194 inst.instruction |= Rm << 3;
11198 inst.instruction = T_OPCODE_CMP_HR;
11199 inst.instruction |= (Rn & 0x8) << 4;
11200 inst.instruction |= (Rn & 0x7);
11201 inst.instruction |= Rm << 3;
11208 inst.instruction = THUMB_OP16 (inst.instruction);
11210 /* PR 10443: Do not silently ignore shifted operands. */
11211 constraint (inst.operands[1].shifted,
11212 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11214 if (inst.operands[1].isreg)
11216 if (Rn < 8 && Rm < 8)
11218 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11219 since a MOV instruction produces unpredictable results. */
11220 if (inst.instruction == T_OPCODE_MOV_I8)
11221 inst.instruction = T_OPCODE_ADD_I3;
11223 inst.instruction = T_OPCODE_CMP_LR;
11225 inst.instruction |= Rn;
11226 inst.instruction |= Rm << 3;
11230 if (inst.instruction == T_OPCODE_MOV_I8)
11231 inst.instruction = T_OPCODE_MOV_HR;
11233 inst.instruction = T_OPCODE_CMP_HR;
11239 constraint (Rn > 7,
11240 _("only lo regs allowed with immediate"));
11241 inst.instruction |= Rn << 8;
11242 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11253 top = (inst.instruction & 0x00800000) != 0;
11254 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11256 constraint (top, _(":lower16: not allowed this instruction"));
11257 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11259 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11261 constraint (!top, _(":upper16: not allowed this instruction"));
11262 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11265 Rd = inst.operands[0].reg;
11266 reject_bad_reg (Rd);
11268 inst.instruction |= Rd << 8;
11269 if (inst.reloc.type == BFD_RELOC_UNUSED)
11271 imm = inst.reloc.exp.X_add_number;
11272 inst.instruction |= (imm & 0xf000) << 4;
11273 inst.instruction |= (imm & 0x0800) << 15;
11274 inst.instruction |= (imm & 0x0700) << 4;
11275 inst.instruction |= (imm & 0x00ff);
11280 do_t_mvn_tst (void)
11284 Rn = inst.operands[0].reg;
11285 Rm = inst.operands[1].reg;
11287 if (inst.instruction == T_MNEM_cmp
11288 || inst.instruction == T_MNEM_cmn)
11289 constraint (Rn == REG_PC, BAD_PC);
11291 reject_bad_reg (Rn);
11292 reject_bad_reg (Rm);
11294 if (unified_syntax)
11296 int r0off = (inst.instruction == T_MNEM_mvn
11297 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11298 bfd_boolean narrow;
11300 if (inst.size_req == 4
11301 || inst.instruction > 0xffff
11302 || inst.operands[1].shifted
11303 || Rn > 7 || Rm > 7)
11305 else if (inst.instruction == T_MNEM_cmn)
11307 else if (THUMB_SETS_FLAGS (inst.instruction))
11308 narrow = !in_it_block ();
11310 narrow = in_it_block ();
11312 if (!inst.operands[1].isreg)
11314 /* For an immediate, we always generate a 32-bit opcode;
11315 section relaxation will shrink it later if possible. */
11316 if (inst.instruction < 0xffff)
11317 inst.instruction = THUMB_OP32 (inst.instruction);
11318 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11319 inst.instruction |= Rn << r0off;
11320 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11324 /* See if we can do this with a 16-bit instruction. */
11327 inst.instruction = THUMB_OP16 (inst.instruction);
11328 inst.instruction |= Rn;
11329 inst.instruction |= Rm << 3;
11333 constraint (inst.operands[1].shifted
11334 && inst.operands[1].immisreg,
11335 _("shift must be constant"));
11336 if (inst.instruction < 0xffff)
11337 inst.instruction = THUMB_OP32 (inst.instruction);
11338 inst.instruction |= Rn << r0off;
11339 encode_thumb32_shifted_operand (1);
11345 constraint (inst.instruction > 0xffff
11346 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11347 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11348 _("unshifted register required"));
11349 constraint (Rn > 7 || Rm > 7,
11352 inst.instruction = THUMB_OP16 (inst.instruction);
11353 inst.instruction |= Rn;
11354 inst.instruction |= Rm << 3;
11363 if (do_vfp_nsyn_mrs () == SUCCESS)
11366 Rd = inst.operands[0].reg;
11367 reject_bad_reg (Rd);
11368 inst.instruction |= Rd << 8;
11370 if (inst.operands[1].isreg)
11372 unsigned br = inst.operands[1].reg;
11373 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11374 as_bad (_("bad register for mrs"));
11376 inst.instruction |= br & (0xf << 16);
11377 inst.instruction |= (br & 0x300) >> 4;
11378 inst.instruction |= (br & SPSR_BIT) >> 2;
11382 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11384 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11386 /* PR gas/12698: The constraint is only applied for m_profile.
11387 If the user has specified -march=all, we want to ignore it as
11388 we are building for any CPU type, including non-m variants. */
11389 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11390 constraint ((flags != 0) && m_profile, _("selected processor does "
11391 "not support requested special purpose register"));
11394 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11396 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11397 _("'APSR', 'CPSR' or 'SPSR' expected"));
11399 inst.instruction |= (flags & SPSR_BIT) >> 2;
11400 inst.instruction |= inst.operands[1].imm & 0xff;
11401 inst.instruction |= 0xf0000;
11411 if (do_vfp_nsyn_msr () == SUCCESS)
11414 constraint (!inst.operands[1].isreg,
11415 _("Thumb encoding does not support an immediate here"));
11417 if (inst.operands[0].isreg)
11418 flags = (int)(inst.operands[0].reg);
11420 flags = inst.operands[0].imm;
11422 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11424 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11426 /* PR gas/12698: The constraint is only applied for m_profile.
11427 If the user has specified -march=all, we want to ignore it as
11428 we are building for any CPU type, including non-m variants. */
11429 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11430 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11431 && (bits & ~(PSR_s | PSR_f)) != 0)
11432 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11433 && bits != PSR_f)) && m_profile,
11434 _("selected processor does not support requested special "
11435 "purpose register"));
11438 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11439 "requested special purpose register"));
11441 Rn = inst.operands[1].reg;
11442 reject_bad_reg (Rn);
11444 inst.instruction |= (flags & SPSR_BIT) >> 2;
11445 inst.instruction |= (flags & 0xf0000) >> 8;
11446 inst.instruction |= (flags & 0x300) >> 4;
11447 inst.instruction |= (flags & 0xff);
11448 inst.instruction |= Rn << 16;
11454 bfd_boolean narrow;
11455 unsigned Rd, Rn, Rm;
11457 if (!inst.operands[2].present)
11458 inst.operands[2].reg = inst.operands[0].reg;
11460 Rd = inst.operands[0].reg;
11461 Rn = inst.operands[1].reg;
11462 Rm = inst.operands[2].reg;
11464 if (unified_syntax)
11466 if (inst.size_req == 4
11472 else if (inst.instruction == T_MNEM_muls)
11473 narrow = !in_it_block ();
11475 narrow = in_it_block ();
11479 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11480 constraint (Rn > 7 || Rm > 7,
11487 /* 16-bit MULS/Conditional MUL. */
11488 inst.instruction = THUMB_OP16 (inst.instruction);
11489 inst.instruction |= Rd;
11492 inst.instruction |= Rm << 3;
11494 inst.instruction |= Rn << 3;
11496 constraint (1, _("dest must overlap one source register"));
11500 constraint (inst.instruction != T_MNEM_mul,
11501 _("Thumb-2 MUL must not set flags"));
11503 inst.instruction = THUMB_OP32 (inst.instruction);
11504 inst.instruction |= Rd << 8;
11505 inst.instruction |= Rn << 16;
11506 inst.instruction |= Rm << 0;
11508 reject_bad_reg (Rd);
11509 reject_bad_reg (Rn);
11510 reject_bad_reg (Rm);
11517 unsigned RdLo, RdHi, Rn, Rm;
11519 RdLo = inst.operands[0].reg;
11520 RdHi = inst.operands[1].reg;
11521 Rn = inst.operands[2].reg;
11522 Rm = inst.operands[3].reg;
11524 reject_bad_reg (RdLo);
11525 reject_bad_reg (RdHi);
11526 reject_bad_reg (Rn);
11527 reject_bad_reg (Rm);
11529 inst.instruction |= RdLo << 12;
11530 inst.instruction |= RdHi << 8;
11531 inst.instruction |= Rn << 16;
11532 inst.instruction |= Rm;
11535 as_tsktsk (_("rdhi and rdlo must be different"));
11541 set_it_insn_type (NEUTRAL_IT_INSN);
11543 if (unified_syntax)
11545 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11547 inst.instruction = THUMB_OP32 (inst.instruction);
11548 inst.instruction |= inst.operands[0].imm;
11552 /* PR9722: Check for Thumb2 availability before
11553 generating a thumb2 nop instruction. */
11554 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11556 inst.instruction = THUMB_OP16 (inst.instruction);
11557 inst.instruction |= inst.operands[0].imm << 4;
11560 inst.instruction = 0x46c0;
11565 constraint (inst.operands[0].present,
11566 _("Thumb does not support NOP with hints"));
11567 inst.instruction = 0x46c0;
11574 if (unified_syntax)
11576 bfd_boolean narrow;
11578 if (THUMB_SETS_FLAGS (inst.instruction))
11579 narrow = !in_it_block ();
11581 narrow = in_it_block ();
11582 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11584 if (inst.size_req == 4)
11589 inst.instruction = THUMB_OP32 (inst.instruction);
11590 inst.instruction |= inst.operands[0].reg << 8;
11591 inst.instruction |= inst.operands[1].reg << 16;
11595 inst.instruction = THUMB_OP16 (inst.instruction);
11596 inst.instruction |= inst.operands[0].reg;
11597 inst.instruction |= inst.operands[1].reg << 3;
11602 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11604 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11606 inst.instruction = THUMB_OP16 (inst.instruction);
11607 inst.instruction |= inst.operands[0].reg;
11608 inst.instruction |= inst.operands[1].reg << 3;
11617 Rd = inst.operands[0].reg;
11618 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11620 reject_bad_reg (Rd);
11621 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11622 reject_bad_reg (Rn);
11624 inst.instruction |= Rd << 8;
11625 inst.instruction |= Rn << 16;
11627 if (!inst.operands[2].isreg)
11629 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11630 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11636 Rm = inst.operands[2].reg;
11637 reject_bad_reg (Rm);
11639 constraint (inst.operands[2].shifted
11640 && inst.operands[2].immisreg,
11641 _("shift must be constant"));
11642 encode_thumb32_shifted_operand (2);
11649 unsigned Rd, Rn, Rm;
11651 Rd = inst.operands[0].reg;
11652 Rn = inst.operands[1].reg;
11653 Rm = inst.operands[2].reg;
11655 reject_bad_reg (Rd);
11656 reject_bad_reg (Rn);
11657 reject_bad_reg (Rm);
11659 inst.instruction |= Rd << 8;
11660 inst.instruction |= Rn << 16;
11661 inst.instruction |= Rm;
11662 if (inst.operands[3].present)
11664 unsigned int val = inst.reloc.exp.X_add_number;
11665 constraint (inst.reloc.exp.X_op != O_constant,
11666 _("expression too complex"));
11667 inst.instruction |= (val & 0x1c) << 10;
11668 inst.instruction |= (val & 0x03) << 6;
11675 if (!inst.operands[3].present)
11679 inst.instruction &= ~0x00000020;
11681 /* PR 10168. Swap the Rm and Rn registers. */
11682 Rtmp = inst.operands[1].reg;
11683 inst.operands[1].reg = inst.operands[2].reg;
11684 inst.operands[2].reg = Rtmp;
11692 if (inst.operands[0].immisreg)
11693 reject_bad_reg (inst.operands[0].imm);
11695 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11699 do_t_push_pop (void)
11703 constraint (inst.operands[0].writeback,
11704 _("push/pop do not support {reglist}^"));
11705 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11706 _("expression too complex"));
11708 mask = inst.operands[0].imm;
11709 if ((mask & ~0xff) == 0)
11710 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11711 else if ((inst.instruction == T_MNEM_push
11712 && (mask & ~0xff) == 1 << REG_LR)
11713 || (inst.instruction == T_MNEM_pop
11714 && (mask & ~0xff) == 1 << REG_PC))
11716 inst.instruction = THUMB_OP16 (inst.instruction);
11717 inst.instruction |= THUMB_PP_PC_LR;
11718 inst.instruction |= mask & 0xff;
11720 else if (unified_syntax)
11722 inst.instruction = THUMB_OP32 (inst.instruction);
11723 encode_thumb2_ldmstm (13, mask, TRUE);
11727 inst.error = _("invalid register list to push/pop instruction");
11737 Rd = inst.operands[0].reg;
11738 Rm = inst.operands[1].reg;
11740 reject_bad_reg (Rd);
11741 reject_bad_reg (Rm);
11743 inst.instruction |= Rd << 8;
11744 inst.instruction |= Rm << 16;
11745 inst.instruction |= Rm;
11753 Rd = inst.operands[0].reg;
11754 Rm = inst.operands[1].reg;
11756 reject_bad_reg (Rd);
11757 reject_bad_reg (Rm);
11759 if (Rd <= 7 && Rm <= 7
11760 && inst.size_req != 4)
11762 inst.instruction = THUMB_OP16 (inst.instruction);
11763 inst.instruction |= Rd;
11764 inst.instruction |= Rm << 3;
11766 else if (unified_syntax)
11768 inst.instruction = THUMB_OP32 (inst.instruction);
11769 inst.instruction |= Rd << 8;
11770 inst.instruction |= Rm << 16;
11771 inst.instruction |= Rm;
11774 inst.error = BAD_HIREG;
11782 Rd = inst.operands[0].reg;
11783 Rm = inst.operands[1].reg;
11785 reject_bad_reg (Rd);
11786 reject_bad_reg (Rm);
11788 inst.instruction |= Rd << 8;
11789 inst.instruction |= Rm;
11797 Rd = inst.operands[0].reg;
11798 Rs = (inst.operands[1].present
11799 ? inst.operands[1].reg /* Rd, Rs, foo */
11800 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11802 reject_bad_reg (Rd);
11803 reject_bad_reg (Rs);
11804 if (inst.operands[2].isreg)
11805 reject_bad_reg (inst.operands[2].reg);
11807 inst.instruction |= Rd << 8;
11808 inst.instruction |= Rs << 16;
11809 if (!inst.operands[2].isreg)
11811 bfd_boolean narrow;
11813 if ((inst.instruction & 0x00100000) != 0)
11814 narrow = !in_it_block ();
11816 narrow = in_it_block ();
11818 if (Rd > 7 || Rs > 7)
11821 if (inst.size_req == 4 || !unified_syntax)
11824 if (inst.reloc.exp.X_op != O_constant
11825 || inst.reloc.exp.X_add_number != 0)
11828 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11829 relaxation, but it doesn't seem worth the hassle. */
11832 inst.reloc.type = BFD_RELOC_UNUSED;
11833 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11834 inst.instruction |= Rs << 3;
11835 inst.instruction |= Rd;
11839 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11840 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11844 encode_thumb32_shifted_operand (2);
11850 if (warn_on_deprecated
11851 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11852 as_warn (_("setend use is deprecated for ARMv8"));
11854 set_it_insn_type (OUTSIDE_IT_INSN);
11855 if (inst.operands[0].imm)
11856 inst.instruction |= 0x8;
11862 if (!inst.operands[1].present)
11863 inst.operands[1].reg = inst.operands[0].reg;
11865 if (unified_syntax)
11867 bfd_boolean narrow;
11870 switch (inst.instruction)
11873 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11875 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11877 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11879 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11883 if (THUMB_SETS_FLAGS (inst.instruction))
11884 narrow = !in_it_block ();
11886 narrow = in_it_block ();
11887 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11889 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11891 if (inst.operands[2].isreg
11892 && (inst.operands[1].reg != inst.operands[0].reg
11893 || inst.operands[2].reg > 7))
11895 if (inst.size_req == 4)
11898 reject_bad_reg (inst.operands[0].reg);
11899 reject_bad_reg (inst.operands[1].reg);
11903 if (inst.operands[2].isreg)
11905 reject_bad_reg (inst.operands[2].reg);
11906 inst.instruction = THUMB_OP32 (inst.instruction);
11907 inst.instruction |= inst.operands[0].reg << 8;
11908 inst.instruction |= inst.operands[1].reg << 16;
11909 inst.instruction |= inst.operands[2].reg;
11911 /* PR 12854: Error on extraneous shifts. */
11912 constraint (inst.operands[2].shifted,
11913 _("extraneous shift as part of operand to shift insn"));
11917 inst.operands[1].shifted = 1;
11918 inst.operands[1].shift_kind = shift_kind;
11919 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11920 ? T_MNEM_movs : T_MNEM_mov);
11921 inst.instruction |= inst.operands[0].reg << 8;
11922 encode_thumb32_shifted_operand (1);
11923 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11924 inst.reloc.type = BFD_RELOC_UNUSED;
11929 if (inst.operands[2].isreg)
11931 switch (shift_kind)
11933 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11934 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11935 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11936 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11940 inst.instruction |= inst.operands[0].reg;
11941 inst.instruction |= inst.operands[2].reg << 3;
11943 /* PR 12854: Error on extraneous shifts. */
11944 constraint (inst.operands[2].shifted,
11945 _("extraneous shift as part of operand to shift insn"));
11949 switch (shift_kind)
11951 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11952 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11953 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11956 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11957 inst.instruction |= inst.operands[0].reg;
11958 inst.instruction |= inst.operands[1].reg << 3;
11964 constraint (inst.operands[0].reg > 7
11965 || inst.operands[1].reg > 7, BAD_HIREG);
11966 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11968 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11970 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11971 constraint (inst.operands[0].reg != inst.operands[1].reg,
11972 _("source1 and dest must be same register"));
11974 switch (inst.instruction)
11976 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11977 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11978 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11979 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11983 inst.instruction |= inst.operands[0].reg;
11984 inst.instruction |= inst.operands[2].reg << 3;
11986 /* PR 12854: Error on extraneous shifts. */
11987 constraint (inst.operands[2].shifted,
11988 _("extraneous shift as part of operand to shift insn"));
11992 switch (inst.instruction)
11994 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11995 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11996 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11997 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12000 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12001 inst.instruction |= inst.operands[0].reg;
12002 inst.instruction |= inst.operands[1].reg << 3;
12010 unsigned Rd, Rn, Rm;
12012 Rd = inst.operands[0].reg;
12013 Rn = inst.operands[1].reg;
12014 Rm = inst.operands[2].reg;
12016 reject_bad_reg (Rd);
12017 reject_bad_reg (Rn);
12018 reject_bad_reg (Rm);
12020 inst.instruction |= Rd << 8;
12021 inst.instruction |= Rn << 16;
12022 inst.instruction |= Rm;
12028 unsigned Rd, Rn, Rm;
12030 Rd = inst.operands[0].reg;
12031 Rm = inst.operands[1].reg;
12032 Rn = inst.operands[2].reg;
12034 reject_bad_reg (Rd);
12035 reject_bad_reg (Rn);
12036 reject_bad_reg (Rm);
12038 inst.instruction |= Rd << 8;
12039 inst.instruction |= Rn << 16;
12040 inst.instruction |= Rm;
12046 unsigned int value = inst.reloc.exp.X_add_number;
12047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12048 _("SMC is not permitted on this architecture"));
12049 constraint (inst.reloc.exp.X_op != O_constant,
12050 _("expression too complex"));
12051 inst.reloc.type = BFD_RELOC_UNUSED;
12052 inst.instruction |= (value & 0xf000) >> 12;
12053 inst.instruction |= (value & 0x0ff0);
12054 inst.instruction |= (value & 0x000f) << 16;
12060 unsigned int value = inst.reloc.exp.X_add_number;
12062 inst.reloc.type = BFD_RELOC_UNUSED;
12063 inst.instruction |= (value & 0x0fff);
12064 inst.instruction |= (value & 0xf000) << 4;
12068 do_t_ssat_usat (int bias)
12072 Rd = inst.operands[0].reg;
12073 Rn = inst.operands[2].reg;
12075 reject_bad_reg (Rd);
12076 reject_bad_reg (Rn);
12078 inst.instruction |= Rd << 8;
12079 inst.instruction |= inst.operands[1].imm - bias;
12080 inst.instruction |= Rn << 16;
12082 if (inst.operands[3].present)
12084 offsetT shift_amount = inst.reloc.exp.X_add_number;
12086 inst.reloc.type = BFD_RELOC_UNUSED;
12088 constraint (inst.reloc.exp.X_op != O_constant,
12089 _("expression too complex"));
12091 if (shift_amount != 0)
12093 constraint (shift_amount > 31,
12094 _("shift expression is too large"));
12096 if (inst.operands[3].shift_kind == SHIFT_ASR)
12097 inst.instruction |= 0x00200000; /* sh bit. */
12099 inst.instruction |= (shift_amount & 0x1c) << 10;
12100 inst.instruction |= (shift_amount & 0x03) << 6;
12108 do_t_ssat_usat (1);
12116 Rd = inst.operands[0].reg;
12117 Rn = inst.operands[2].reg;
12119 reject_bad_reg (Rd);
12120 reject_bad_reg (Rn);
12122 inst.instruction |= Rd << 8;
12123 inst.instruction |= inst.operands[1].imm - 1;
12124 inst.instruction |= Rn << 16;
12130 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12131 || inst.operands[2].postind || inst.operands[2].writeback
12132 || inst.operands[2].immisreg || inst.operands[2].shifted
12133 || inst.operands[2].negative,
12136 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12138 inst.instruction |= inst.operands[0].reg << 8;
12139 inst.instruction |= inst.operands[1].reg << 12;
12140 inst.instruction |= inst.operands[2].reg << 16;
12141 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12147 if (!inst.operands[2].present)
12148 inst.operands[2].reg = inst.operands[1].reg + 1;
12150 constraint (inst.operands[0].reg == inst.operands[1].reg
12151 || inst.operands[0].reg == inst.operands[2].reg
12152 || inst.operands[0].reg == inst.operands[3].reg,
12155 inst.instruction |= inst.operands[0].reg;
12156 inst.instruction |= inst.operands[1].reg << 12;
12157 inst.instruction |= inst.operands[2].reg << 8;
12158 inst.instruction |= inst.operands[3].reg << 16;
12164 unsigned Rd, Rn, Rm;
12166 Rd = inst.operands[0].reg;
12167 Rn = inst.operands[1].reg;
12168 Rm = inst.operands[2].reg;
12170 reject_bad_reg (Rd);
12171 reject_bad_reg (Rn);
12172 reject_bad_reg (Rm);
12174 inst.instruction |= Rd << 8;
12175 inst.instruction |= Rn << 16;
12176 inst.instruction |= Rm;
12177 inst.instruction |= inst.operands[3].imm << 4;
12185 Rd = inst.operands[0].reg;
12186 Rm = inst.operands[1].reg;
12188 reject_bad_reg (Rd);
12189 reject_bad_reg (Rm);
12191 if (inst.instruction <= 0xffff
12192 && inst.size_req != 4
12193 && Rd <= 7 && Rm <= 7
12194 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12196 inst.instruction = THUMB_OP16 (inst.instruction);
12197 inst.instruction |= Rd;
12198 inst.instruction |= Rm << 3;
12200 else if (unified_syntax)
12202 if (inst.instruction <= 0xffff)
12203 inst.instruction = THUMB_OP32 (inst.instruction);
12204 inst.instruction |= Rd << 8;
12205 inst.instruction |= Rm;
12206 inst.instruction |= inst.operands[2].imm << 4;
12210 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12211 _("Thumb encoding does not support rotation"));
12212 constraint (1, BAD_HIREG);
12219 /* We have to do the following check manually as ARM_EXT_OS only applies
12221 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12223 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12224 /* This only applies to the v6m howver, not later architectures. */
12225 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12226 as_bad (_("SVC is not permitted on this architecture"));
12227 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12230 inst.reloc.type = BFD_RELOC_ARM_SWI;
12239 half = (inst.instruction & 0x10) != 0;
12240 set_it_insn_type_last ();
12241 constraint (inst.operands[0].immisreg,
12242 _("instruction requires register index"));
12244 Rn = inst.operands[0].reg;
12245 Rm = inst.operands[0].imm;
12247 constraint (Rn == REG_SP, BAD_SP);
12248 reject_bad_reg (Rm);
12250 constraint (!half && inst.operands[0].shifted,
12251 _("instruction does not allow shifted index"));
12252 inst.instruction |= (Rn << 16) | Rm;
12258 do_t_ssat_usat (0);
12266 Rd = inst.operands[0].reg;
12267 Rn = inst.operands[2].reg;
12269 reject_bad_reg (Rd);
12270 reject_bad_reg (Rn);
12272 inst.instruction |= Rd << 8;
12273 inst.instruction |= inst.operands[1].imm;
12274 inst.instruction |= Rn << 16;
12277 /* Neon instruction encoder helpers. */
12279 /* Encodings for the different types for various Neon opcodes. */
12281 /* An "invalid" code for the following tables. */
12284 struct neon_tab_entry
12287 unsigned float_or_poly;
12288 unsigned scalar_or_imm;
12291 /* Map overloaded Neon opcodes to their respective encodings. */
12292 #define NEON_ENC_TAB \
12293 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12294 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12295 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12296 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12297 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12298 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12299 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12300 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12301 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12302 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12303 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12304 /* Register variants of the following two instructions are encoded as
12305 vcge / vcgt with the operands reversed. */ \
12306 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12307 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12308 X(vfma, N_INV, 0x0000c10, N_INV), \
12309 X(vfms, N_INV, 0x0200c10, N_INV), \
12310 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12311 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12312 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12313 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12314 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12315 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12316 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12317 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12318 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12319 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12320 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12321 X(vshl, 0x0000400, N_INV, 0x0800510), \
12322 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12323 X(vand, 0x0000110, N_INV, 0x0800030), \
12324 X(vbic, 0x0100110, N_INV, 0x0800030), \
12325 X(veor, 0x1000110, N_INV, N_INV), \
12326 X(vorn, 0x0300110, N_INV, 0x0800010), \
12327 X(vorr, 0x0200110, N_INV, 0x0800010), \
12328 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12329 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12330 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12331 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12332 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12333 X(vst1, 0x0000000, 0x0800000, N_INV), \
12334 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12335 X(vst2, 0x0000100, 0x0800100, N_INV), \
12336 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12337 X(vst3, 0x0000200, 0x0800200, N_INV), \
12338 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12339 X(vst4, 0x0000300, 0x0800300, N_INV), \
12340 X(vmovn, 0x1b20200, N_INV, N_INV), \
12341 X(vtrn, 0x1b20080, N_INV, N_INV), \
12342 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12343 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12344 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12345 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12346 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12347 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12348 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12349 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12350 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12351 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12352 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12353 X(vseleq, 0xe000a00, N_INV, N_INV), \
12354 X(vselvs, 0xe100a00, N_INV, N_INV), \
12355 X(vselge, 0xe200a00, N_INV, N_INV), \
12356 X(vselgt, 0xe300a00, N_INV, N_INV), \
12357 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12358 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12359 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12360 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12361 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12362 X(aes, 0x3b00300, N_INV, N_INV), \
12363 X(sha3op, 0x2000c00, N_INV, N_INV), \
12364 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12365 X(sha2op, 0x3ba0380, N_INV, N_INV)
12369 #define X(OPC,I,F,S) N_MNEM_##OPC
12374 static const struct neon_tab_entry neon_enc_tab[] =
12376 #define X(OPC,I,F,S) { (I), (F), (S) }
12381 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12382 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12383 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12384 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12385 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12386 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12387 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12388 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12389 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12390 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12391 #define NEON_ENC_SINGLE_(X) \
12392 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12393 #define NEON_ENC_DOUBLE_(X) \
12394 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12395 #define NEON_ENC_FPV8_(X) \
12396 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12398 #define NEON_ENCODE(type, inst) \
12401 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12402 inst.is_neon = 1; \
12406 #define check_neon_suffixes \
12409 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12411 as_bad (_("invalid neon suffix for non neon instruction")); \
12417 /* Define shapes for instruction operands. The following mnemonic characters
12418 are used in this table:
12420 F - VFP S<n> register
12421 D - Neon D<n> register
12422 Q - Neon Q<n> register
12426 L - D<n> register list
12428 This table is used to generate various data:
12429 - enumerations of the form NS_DDR to be used as arguments to
12431 - a table classifying shapes into single, double, quad, mixed.
12432 - a table used to drive neon_select_shape. */
12434 #define NEON_SHAPE_DEF \
12435 X(3, (D, D, D), DOUBLE), \
12436 X(3, (Q, Q, Q), QUAD), \
12437 X(3, (D, D, I), DOUBLE), \
12438 X(3, (Q, Q, I), QUAD), \
12439 X(3, (D, D, S), DOUBLE), \
12440 X(3, (Q, Q, S), QUAD), \
12441 X(2, (D, D), DOUBLE), \
12442 X(2, (Q, Q), QUAD), \
12443 X(2, (D, S), DOUBLE), \
12444 X(2, (Q, S), QUAD), \
12445 X(2, (D, R), DOUBLE), \
12446 X(2, (Q, R), QUAD), \
12447 X(2, (D, I), DOUBLE), \
12448 X(2, (Q, I), QUAD), \
12449 X(3, (D, L, D), DOUBLE), \
12450 X(2, (D, Q), MIXED), \
12451 X(2, (Q, D), MIXED), \
12452 X(3, (D, Q, I), MIXED), \
12453 X(3, (Q, D, I), MIXED), \
12454 X(3, (Q, D, D), MIXED), \
12455 X(3, (D, Q, Q), MIXED), \
12456 X(3, (Q, Q, D), MIXED), \
12457 X(3, (Q, D, S), MIXED), \
12458 X(3, (D, Q, S), MIXED), \
12459 X(4, (D, D, D, I), DOUBLE), \
12460 X(4, (Q, Q, Q, I), QUAD), \
12461 X(2, (F, F), SINGLE), \
12462 X(3, (F, F, F), SINGLE), \
12463 X(2, (F, I), SINGLE), \
12464 X(2, (F, D), MIXED), \
12465 X(2, (D, F), MIXED), \
12466 X(3, (F, F, I), MIXED), \
12467 X(4, (R, R, F, F), SINGLE), \
12468 X(4, (F, F, R, R), SINGLE), \
12469 X(3, (D, R, R), DOUBLE), \
12470 X(3, (R, R, D), DOUBLE), \
12471 X(2, (S, R), SINGLE), \
12472 X(2, (R, S), SINGLE), \
12473 X(2, (F, R), SINGLE), \
12474 X(2, (R, F), SINGLE)
12476 #define S2(A,B) NS_##A##B
12477 #define S3(A,B,C) NS_##A##B##C
12478 #define S4(A,B,C,D) NS_##A##B##C##D
12480 #define X(N, L, C) S##N L
12493 enum neon_shape_class
12501 #define X(N, L, C) SC_##C
12503 static enum neon_shape_class neon_shape_class[] =
12521 /* Register widths of above. */
12522 static unsigned neon_shape_el_size[] =
12533 struct neon_shape_info
12536 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12539 #define S2(A,B) { SE_##A, SE_##B }
12540 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12541 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12543 #define X(N, L, C) { N, S##N L }
12545 static struct neon_shape_info neon_shape_tab[] =
12555 /* Bit masks used in type checking given instructions.
12556 'N_EQK' means the type must be the same as (or based on in some way) the key
12557 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12558 set, various other bits can be set as well in order to modify the meaning of
12559 the type constraint. */
12561 enum neon_type_mask
12585 N_KEY = 0x1000000, /* Key element (main type specifier). */
12586 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12587 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12588 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12589 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12590 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12591 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12592 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12593 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12594 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12595 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12597 N_MAX_NONSPECIAL = N_P64
12600 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12602 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12603 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12604 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12605 #define N_SUF_32 (N_SU_32 | N_F32)
12606 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12607 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12609 /* Pass this as the first type argument to neon_check_type to ignore types
12611 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12613 /* Select a "shape" for the current instruction (describing register types or
12614 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12615 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12616 function of operand parsing, so this function doesn't need to be called.
12617 Shapes should be listed in order of decreasing length. */
12619 static enum neon_shape
12620 neon_select_shape (enum neon_shape shape, ...)
12623 enum neon_shape first_shape = shape;
12625 /* Fix missing optional operands. FIXME: we don't know at this point how
12626 many arguments we should have, so this makes the assumption that we have
12627 > 1. This is true of all current Neon opcodes, I think, but may not be
12628 true in the future. */
12629 if (!inst.operands[1].present)
12630 inst.operands[1] = inst.operands[0];
12632 va_start (ap, shape);
12634 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12639 for (j = 0; j < neon_shape_tab[shape].els; j++)
12641 if (!inst.operands[j].present)
12647 switch (neon_shape_tab[shape].el[j])
12650 if (!(inst.operands[j].isreg
12651 && inst.operands[j].isvec
12652 && inst.operands[j].issingle
12653 && !inst.operands[j].isquad))
12658 if (!(inst.operands[j].isreg
12659 && inst.operands[j].isvec
12660 && !inst.operands[j].isquad
12661 && !inst.operands[j].issingle))
12666 if (!(inst.operands[j].isreg
12667 && !inst.operands[j].isvec))
12672 if (!(inst.operands[j].isreg
12673 && inst.operands[j].isvec
12674 && inst.operands[j].isquad
12675 && !inst.operands[j].issingle))
12680 if (!(!inst.operands[j].isreg
12681 && !inst.operands[j].isscalar))
12686 if (!(!inst.operands[j].isreg
12687 && inst.operands[j].isscalar))
12697 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12698 /* We've matched all the entries in the shape table, and we don't
12699 have any left over operands which have not been matched. */
12705 if (shape == NS_NULL && first_shape != NS_NULL)
12706 first_error (_("invalid instruction shape"));
12711 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12712 means the Q bit should be set). */
12715 neon_quad (enum neon_shape shape)
12717 return neon_shape_class[shape] == SC_QUAD;
12721 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12724 /* Allow modification to be made to types which are constrained to be
12725 based on the key element, based on bits set alongside N_EQK. */
12726 if ((typebits & N_EQK) != 0)
12728 if ((typebits & N_HLF) != 0)
12730 else if ((typebits & N_DBL) != 0)
12732 if ((typebits & N_SGN) != 0)
12733 *g_type = NT_signed;
12734 else if ((typebits & N_UNS) != 0)
12735 *g_type = NT_unsigned;
12736 else if ((typebits & N_INT) != 0)
12737 *g_type = NT_integer;
12738 else if ((typebits & N_FLT) != 0)
12739 *g_type = NT_float;
12740 else if ((typebits & N_SIZ) != 0)
12741 *g_type = NT_untyped;
12745 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12746 operand type, i.e. the single type specified in a Neon instruction when it
12747 is the only one given. */
12749 static struct neon_type_el
12750 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12752 struct neon_type_el dest = *key;
12754 gas_assert ((thisarg & N_EQK) != 0);
12756 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12761 /* Convert Neon type and size into compact bitmask representation. */
12763 static enum neon_type_mask
12764 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12771 case 8: return N_8;
12772 case 16: return N_16;
12773 case 32: return N_32;
12774 case 64: return N_64;
12782 case 8: return N_I8;
12783 case 16: return N_I16;
12784 case 32: return N_I32;
12785 case 64: return N_I64;
12793 case 16: return N_F16;
12794 case 32: return N_F32;
12795 case 64: return N_F64;
12803 case 8: return N_P8;
12804 case 16: return N_P16;
12805 case 64: return N_P64;
12813 case 8: return N_S8;
12814 case 16: return N_S16;
12815 case 32: return N_S32;
12816 case 64: return N_S64;
12824 case 8: return N_U8;
12825 case 16: return N_U16;
12826 case 32: return N_U32;
12827 case 64: return N_U64;
12838 /* Convert compact Neon bitmask type representation to a type and size. Only
12839 handles the case where a single bit is set in the mask. */
12842 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12843 enum neon_type_mask mask)
12845 if ((mask & N_EQK) != 0)
12848 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12850 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12852 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12854 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12859 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12861 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12862 *type = NT_unsigned;
12863 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12864 *type = NT_integer;
12865 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12866 *type = NT_untyped;
12867 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12869 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12877 /* Modify a bitmask of allowed types. This is only needed for type
12881 modify_types_allowed (unsigned allowed, unsigned mods)
12884 enum neon_el_type type;
12890 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12892 if (el_type_of_type_chk (&type, &size,
12893 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12895 neon_modify_type_size (mods, &type, &size);
12896 destmask |= type_chk_of_el_type (type, size);
12903 /* Check type and return type classification.
12904 The manual states (paraphrase): If one datatype is given, it indicates the
12906 - the second operand, if there is one
12907 - the operand, if there is no second operand
12908 - the result, if there are no operands.
12909 This isn't quite good enough though, so we use a concept of a "key" datatype
12910 which is set on a per-instruction basis, which is the one which matters when
12911 only one data type is written.
12912 Note: this function has side-effects (e.g. filling in missing operands). All
12913 Neon instructions should call it before performing bit encoding. */
12915 static struct neon_type_el
12916 neon_check_type (unsigned els, enum neon_shape ns, ...)
12919 unsigned i, pass, key_el = 0;
12920 unsigned types[NEON_MAX_TYPE_ELS];
12921 enum neon_el_type k_type = NT_invtype;
12922 unsigned k_size = -1u;
12923 struct neon_type_el badtype = {NT_invtype, -1};
12924 unsigned key_allowed = 0;
12926 /* Optional registers in Neon instructions are always (not) in operand 1.
12927 Fill in the missing operand here, if it was omitted. */
12928 if (els > 1 && !inst.operands[1].present)
12929 inst.operands[1] = inst.operands[0];
12931 /* Suck up all the varargs. */
12933 for (i = 0; i < els; i++)
12935 unsigned thisarg = va_arg (ap, unsigned);
12936 if (thisarg == N_IGNORE_TYPE)
12941 types[i] = thisarg;
12942 if ((thisarg & N_KEY) != 0)
12947 if (inst.vectype.elems > 0)
12948 for (i = 0; i < els; i++)
12949 if (inst.operands[i].vectype.type != NT_invtype)
12951 first_error (_("types specified in both the mnemonic and operands"));
12955 /* Duplicate inst.vectype elements here as necessary.
12956 FIXME: No idea if this is exactly the same as the ARM assembler,
12957 particularly when an insn takes one register and one non-register
12959 if (inst.vectype.elems == 1 && els > 1)
12962 inst.vectype.elems = els;
12963 inst.vectype.el[key_el] = inst.vectype.el[0];
12964 for (j = 0; j < els; j++)
12966 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12969 else if (inst.vectype.elems == 0 && els > 0)
12972 /* No types were given after the mnemonic, so look for types specified
12973 after each operand. We allow some flexibility here; as long as the
12974 "key" operand has a type, we can infer the others. */
12975 for (j = 0; j < els; j++)
12976 if (inst.operands[j].vectype.type != NT_invtype)
12977 inst.vectype.el[j] = inst.operands[j].vectype;
12979 if (inst.operands[key_el].vectype.type != NT_invtype)
12981 for (j = 0; j < els; j++)
12982 if (inst.operands[j].vectype.type == NT_invtype)
12983 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12988 first_error (_("operand types can't be inferred"));
12992 else if (inst.vectype.elems != els)
12994 first_error (_("type specifier has the wrong number of parts"));
12998 for (pass = 0; pass < 2; pass++)
13000 for (i = 0; i < els; i++)
13002 unsigned thisarg = types[i];
13003 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13004 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13005 enum neon_el_type g_type = inst.vectype.el[i].type;
13006 unsigned g_size = inst.vectype.el[i].size;
13008 /* Decay more-specific signed & unsigned types to sign-insensitive
13009 integer types if sign-specific variants are unavailable. */
13010 if ((g_type == NT_signed || g_type == NT_unsigned)
13011 && (types_allowed & N_SU_ALL) == 0)
13012 g_type = NT_integer;
13014 /* If only untyped args are allowed, decay any more specific types to
13015 them. Some instructions only care about signs for some element
13016 sizes, so handle that properly. */
13017 if (((types_allowed & N_UNT) == 0)
13018 && ((g_size == 8 && (types_allowed & N_8) != 0)
13019 || (g_size == 16 && (types_allowed & N_16) != 0)
13020 || (g_size == 32 && (types_allowed & N_32) != 0)
13021 || (g_size == 64 && (types_allowed & N_64) != 0)))
13022 g_type = NT_untyped;
13026 if ((thisarg & N_KEY) != 0)
13030 key_allowed = thisarg & ~N_KEY;
13035 if ((thisarg & N_VFP) != 0)
13037 enum neon_shape_el regshape;
13038 unsigned regwidth, match;
13040 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13043 first_error (_("invalid instruction shape"));
13046 regshape = neon_shape_tab[ns].el[i];
13047 regwidth = neon_shape_el_size[regshape];
13049 /* In VFP mode, operands must match register widths. If we
13050 have a key operand, use its width, else use the width of
13051 the current operand. */
13057 if (regwidth != match)
13059 first_error (_("operand size must match register width"));
13064 if ((thisarg & N_EQK) == 0)
13066 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13068 if ((given_type & types_allowed) == 0)
13070 first_error (_("bad type in Neon instruction"));
13076 enum neon_el_type mod_k_type = k_type;
13077 unsigned mod_k_size = k_size;
13078 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13079 if (g_type != mod_k_type || g_size != mod_k_size)
13081 first_error (_("inconsistent types in Neon instruction"));
13089 return inst.vectype.el[key_el];
13092 /* Neon-style VFP instruction forwarding. */
13094 /* Thumb VFP instructions have 0xE in the condition field. */
13097 do_vfp_cond_or_thumb (void)
13102 inst.instruction |= 0xe0000000;
13104 inst.instruction |= inst.cond << 28;
13107 /* Look up and encode a simple mnemonic, for use as a helper function for the
13108 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13109 etc. It is assumed that operand parsing has already been done, and that the
13110 operands are in the form expected by the given opcode (this isn't necessarily
13111 the same as the form in which they were parsed, hence some massaging must
13112 take place before this function is called).
13113 Checks current arch version against that in the looked-up opcode. */
13116 do_vfp_nsyn_opcode (const char *opname)
13118 const struct asm_opcode *opcode;
13120 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13126 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13133 inst.instruction = opcode->tvalue;
13134 opcode->tencode ();
13138 inst.instruction = (inst.cond << 28) | opcode->avalue;
13139 opcode->aencode ();
13144 do_vfp_nsyn_add_sub (enum neon_shape rs)
13146 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13151 do_vfp_nsyn_opcode ("fadds");
13153 do_vfp_nsyn_opcode ("fsubs");
13158 do_vfp_nsyn_opcode ("faddd");
13160 do_vfp_nsyn_opcode ("fsubd");
13164 /* Check operand types to see if this is a VFP instruction, and if so call
13168 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13170 enum neon_shape rs;
13171 struct neon_type_el et;
13176 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13177 et = neon_check_type (2, rs,
13178 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13182 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13183 et = neon_check_type (3, rs,
13184 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13191 if (et.type != NT_invtype)
13202 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13204 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13209 do_vfp_nsyn_opcode ("fmacs");
13211 do_vfp_nsyn_opcode ("fnmacs");
13216 do_vfp_nsyn_opcode ("fmacd");
13218 do_vfp_nsyn_opcode ("fnmacd");
13223 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13225 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13230 do_vfp_nsyn_opcode ("ffmas");
13232 do_vfp_nsyn_opcode ("ffnmas");
13237 do_vfp_nsyn_opcode ("ffmad");
13239 do_vfp_nsyn_opcode ("ffnmad");
13244 do_vfp_nsyn_mul (enum neon_shape rs)
13247 do_vfp_nsyn_opcode ("fmuls");
13249 do_vfp_nsyn_opcode ("fmuld");
13253 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13255 int is_neg = (inst.instruction & 0x80) != 0;
13256 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13261 do_vfp_nsyn_opcode ("fnegs");
13263 do_vfp_nsyn_opcode ("fabss");
13268 do_vfp_nsyn_opcode ("fnegd");
13270 do_vfp_nsyn_opcode ("fabsd");
13274 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13275 insns belong to Neon, and are handled elsewhere. */
13278 do_vfp_nsyn_ldm_stm (int is_dbmode)
13280 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13284 do_vfp_nsyn_opcode ("fldmdbs");
13286 do_vfp_nsyn_opcode ("fldmias");
13291 do_vfp_nsyn_opcode ("fstmdbs");
13293 do_vfp_nsyn_opcode ("fstmias");
13298 do_vfp_nsyn_sqrt (void)
13300 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13301 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13304 do_vfp_nsyn_opcode ("fsqrts");
13306 do_vfp_nsyn_opcode ("fsqrtd");
13310 do_vfp_nsyn_div (void)
13312 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13313 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13314 N_F32 | N_F64 | N_KEY | N_VFP);
13317 do_vfp_nsyn_opcode ("fdivs");
13319 do_vfp_nsyn_opcode ("fdivd");
13323 do_vfp_nsyn_nmul (void)
13325 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13326 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13327 N_F32 | N_F64 | N_KEY | N_VFP);
13331 NEON_ENCODE (SINGLE, inst);
13332 do_vfp_sp_dyadic ();
13336 NEON_ENCODE (DOUBLE, inst);
13337 do_vfp_dp_rd_rn_rm ();
13339 do_vfp_cond_or_thumb ();
13343 do_vfp_nsyn_cmp (void)
13345 if (inst.operands[1].isreg)
13347 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13348 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13352 NEON_ENCODE (SINGLE, inst);
13353 do_vfp_sp_monadic ();
13357 NEON_ENCODE (DOUBLE, inst);
13358 do_vfp_dp_rd_rm ();
13363 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13364 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13366 switch (inst.instruction & 0x0fffffff)
13369 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13372 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13380 NEON_ENCODE (SINGLE, inst);
13381 do_vfp_sp_compare_z ();
13385 NEON_ENCODE (DOUBLE, inst);
13389 do_vfp_cond_or_thumb ();
13393 nsyn_insert_sp (void)
13395 inst.operands[1] = inst.operands[0];
13396 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13397 inst.operands[0].reg = REG_SP;
13398 inst.operands[0].isreg = 1;
13399 inst.operands[0].writeback = 1;
13400 inst.operands[0].present = 1;
13404 do_vfp_nsyn_push (void)
13407 if (inst.operands[1].issingle)
13408 do_vfp_nsyn_opcode ("fstmdbs");
13410 do_vfp_nsyn_opcode ("fstmdbd");
13414 do_vfp_nsyn_pop (void)
13417 if (inst.operands[1].issingle)
13418 do_vfp_nsyn_opcode ("fldmias");
13420 do_vfp_nsyn_opcode ("fldmiad");
13423 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13424 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13427 neon_dp_fixup (struct arm_it* insn)
13429 unsigned int i = insn->instruction;
13434 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13445 insn->instruction = i;
13448 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13452 neon_logbits (unsigned x)
13454 return ffs (x) - 4;
13457 #define LOW4(R) ((R) & 0xf)
13458 #define HI1(R) (((R) >> 4) & 1)
13460 /* Encode insns with bit pattern:
13462 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13463 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13465 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13466 different meaning for some instruction. */
13469 neon_three_same (int isquad, int ubit, int size)
13471 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13472 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13473 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13474 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13475 inst.instruction |= LOW4 (inst.operands[2].reg);
13476 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13477 inst.instruction |= (isquad != 0) << 6;
13478 inst.instruction |= (ubit != 0) << 24;
13480 inst.instruction |= neon_logbits (size) << 20;
13482 neon_dp_fixup (&inst);
13485 /* Encode instructions of the form:
13487 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13488 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13490 Don't write size if SIZE == -1. */
13493 neon_two_same (int qbit, int ubit, int size)
13495 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13496 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13497 inst.instruction |= LOW4 (inst.operands[1].reg);
13498 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13499 inst.instruction |= (qbit != 0) << 6;
13500 inst.instruction |= (ubit != 0) << 24;
13503 inst.instruction |= neon_logbits (size) << 18;
13505 neon_dp_fixup (&inst);
13508 /* Neon instruction encoders, in approximate order of appearance. */
13511 do_neon_dyadic_i_su (void)
13513 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13514 struct neon_type_el et = neon_check_type (3, rs,
13515 N_EQK, N_EQK, N_SU_32 | N_KEY);
13516 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13520 do_neon_dyadic_i64_su (void)
13522 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13523 struct neon_type_el et = neon_check_type (3, rs,
13524 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13525 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13529 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13532 unsigned size = et.size >> 3;
13533 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13534 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13535 inst.instruction |= LOW4 (inst.operands[1].reg);
13536 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13537 inst.instruction |= (isquad != 0) << 6;
13538 inst.instruction |= immbits << 16;
13539 inst.instruction |= (size >> 3) << 7;
13540 inst.instruction |= (size & 0x7) << 19;
13542 inst.instruction |= (uval != 0) << 24;
13544 neon_dp_fixup (&inst);
13548 do_neon_shl_imm (void)
13550 if (!inst.operands[2].isreg)
13552 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13553 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13554 NEON_ENCODE (IMMED, inst);
13555 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13559 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13560 struct neon_type_el et = neon_check_type (3, rs,
13561 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13564 /* VSHL/VQSHL 3-register variants have syntax such as:
13566 whereas other 3-register operations encoded by neon_three_same have
13569 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13571 tmp = inst.operands[2].reg;
13572 inst.operands[2].reg = inst.operands[1].reg;
13573 inst.operands[1].reg = tmp;
13574 NEON_ENCODE (INTEGER, inst);
13575 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13580 do_neon_qshl_imm (void)
13582 if (!inst.operands[2].isreg)
13584 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13585 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13587 NEON_ENCODE (IMMED, inst);
13588 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13589 inst.operands[2].imm);
13593 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13594 struct neon_type_el et = neon_check_type (3, rs,
13595 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13598 /* See note in do_neon_shl_imm. */
13599 tmp = inst.operands[2].reg;
13600 inst.operands[2].reg = inst.operands[1].reg;
13601 inst.operands[1].reg = tmp;
13602 NEON_ENCODE (INTEGER, inst);
13603 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13608 do_neon_rshl (void)
13610 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13611 struct neon_type_el et = neon_check_type (3, rs,
13612 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13615 tmp = inst.operands[2].reg;
13616 inst.operands[2].reg = inst.operands[1].reg;
13617 inst.operands[1].reg = tmp;
13618 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13622 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13624 /* Handle .I8 pseudo-instructions. */
13627 /* Unfortunately, this will make everything apart from zero out-of-range.
13628 FIXME is this the intended semantics? There doesn't seem much point in
13629 accepting .I8 if so. */
13630 immediate |= immediate << 8;
13636 if (immediate == (immediate & 0x000000ff))
13638 *immbits = immediate;
13641 else if (immediate == (immediate & 0x0000ff00))
13643 *immbits = immediate >> 8;
13646 else if (immediate == (immediate & 0x00ff0000))
13648 *immbits = immediate >> 16;
13651 else if (immediate == (immediate & 0xff000000))
13653 *immbits = immediate >> 24;
13656 if ((immediate & 0xffff) != (immediate >> 16))
13657 goto bad_immediate;
13658 immediate &= 0xffff;
13661 if (immediate == (immediate & 0x000000ff))
13663 *immbits = immediate;
13666 else if (immediate == (immediate & 0x0000ff00))
13668 *immbits = immediate >> 8;
13673 first_error (_("immediate value out of range"));
13677 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13681 neon_bits_same_in_bytes (unsigned imm)
13683 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13684 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13685 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13686 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13689 /* For immediate of above form, return 0bABCD. */
13692 neon_squash_bits (unsigned imm)
13694 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13695 | ((imm & 0x01000000) >> 21);
13698 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13701 neon_qfloat_bits (unsigned imm)
13703 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13706 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13707 the instruction. *OP is passed as the initial value of the op field, and
13708 may be set to a different value depending on the constant (i.e.
13709 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13710 MVN). If the immediate looks like a repeated pattern then also
13711 try smaller element sizes. */
13714 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13715 unsigned *immbits, int *op, int size,
13716 enum neon_el_type type)
13718 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13720 if (type == NT_float && !float_p)
13723 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13725 if (size != 32 || *op == 1)
13727 *immbits = neon_qfloat_bits (immlo);
13733 if (neon_bits_same_in_bytes (immhi)
13734 && neon_bits_same_in_bytes (immlo))
13738 *immbits = (neon_squash_bits (immhi) << 4)
13739 | neon_squash_bits (immlo);
13744 if (immhi != immlo)
13750 if (immlo == (immlo & 0x000000ff))
13755 else if (immlo == (immlo & 0x0000ff00))
13757 *immbits = immlo >> 8;
13760 else if (immlo == (immlo & 0x00ff0000))
13762 *immbits = immlo >> 16;
13765 else if (immlo == (immlo & 0xff000000))
13767 *immbits = immlo >> 24;
13770 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13772 *immbits = (immlo >> 8) & 0xff;
13775 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13777 *immbits = (immlo >> 16) & 0xff;
13781 if ((immlo & 0xffff) != (immlo >> 16))
13788 if (immlo == (immlo & 0x000000ff))
13793 else if (immlo == (immlo & 0x0000ff00))
13795 *immbits = immlo >> 8;
13799 if ((immlo & 0xff) != (immlo >> 8))
13804 if (immlo == (immlo & 0x000000ff))
13806 /* Don't allow MVN with 8-bit immediate. */
13816 /* Write immediate bits [7:0] to the following locations:
13818 |28/24|23 19|18 16|15 4|3 0|
13819 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13821 This function is used by VMOV/VMVN/VORR/VBIC. */
13824 neon_write_immbits (unsigned immbits)
13826 inst.instruction |= immbits & 0xf;
13827 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13828 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13831 /* Invert low-order SIZE bits of XHI:XLO. */
13834 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13836 unsigned immlo = xlo ? *xlo : 0;
13837 unsigned immhi = xhi ? *xhi : 0;
13842 immlo = (~immlo) & 0xff;
13846 immlo = (~immlo) & 0xffff;
13850 immhi = (~immhi) & 0xffffffff;
13851 /* fall through. */
13854 immlo = (~immlo) & 0xffffffff;
13869 do_neon_logic (void)
13871 if (inst.operands[2].present && inst.operands[2].isreg)
13873 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13874 neon_check_type (3, rs, N_IGNORE_TYPE);
13875 /* U bit and size field were set as part of the bitmask. */
13876 NEON_ENCODE (INTEGER, inst);
13877 neon_three_same (neon_quad (rs), 0, -1);
13881 const int three_ops_form = (inst.operands[2].present
13882 && !inst.operands[2].isreg);
13883 const int immoperand = (three_ops_form ? 2 : 1);
13884 enum neon_shape rs = (three_ops_form
13885 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13886 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13887 struct neon_type_el et = neon_check_type (2, rs,
13888 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13889 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13893 if (et.type == NT_invtype)
13896 if (three_ops_form)
13897 constraint (inst.operands[0].reg != inst.operands[1].reg,
13898 _("first and second operands shall be the same register"));
13900 NEON_ENCODE (IMMED, inst);
13902 immbits = inst.operands[immoperand].imm;
13905 /* .i64 is a pseudo-op, so the immediate must be a repeating
13907 if (immbits != (inst.operands[immoperand].regisimm ?
13908 inst.operands[immoperand].reg : 0))
13910 /* Set immbits to an invalid constant. */
13911 immbits = 0xdeadbeef;
13918 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13922 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13926 /* Pseudo-instruction for VBIC. */
13927 neon_invert_size (&immbits, 0, et.size);
13928 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13932 /* Pseudo-instruction for VORR. */
13933 neon_invert_size (&immbits, 0, et.size);
13934 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13944 inst.instruction |= neon_quad (rs) << 6;
13945 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13946 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13947 inst.instruction |= cmode << 8;
13948 neon_write_immbits (immbits);
13950 neon_dp_fixup (&inst);
13955 do_neon_bitfield (void)
13957 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13958 neon_check_type (3, rs, N_IGNORE_TYPE);
13959 neon_three_same (neon_quad (rs), 0, -1);
13963 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13966 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13967 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13969 if (et.type == NT_float)
13971 NEON_ENCODE (FLOAT, inst);
13972 neon_three_same (neon_quad (rs), 0, -1);
13976 NEON_ENCODE (INTEGER, inst);
13977 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13982 do_neon_dyadic_if_su (void)
13984 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13988 do_neon_dyadic_if_su_d (void)
13990 /* This version only allow D registers, but that constraint is enforced during
13991 operand parsing so we don't need to do anything extra here. */
13992 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13996 do_neon_dyadic_if_i_d (void)
13998 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13999 affected if we specify unsigned args. */
14000 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14003 enum vfp_or_neon_is_neon_bits
14006 NEON_CHECK_ARCH = 2,
14007 NEON_CHECK_ARCH8 = 4
14010 /* Call this function if an instruction which may have belonged to the VFP or
14011 Neon instruction sets, but turned out to be a Neon instruction (due to the
14012 operand types involved, etc.). We have to check and/or fix-up a couple of
14015 - Make sure the user hasn't attempted to make a Neon instruction
14017 - Alter the value in the condition code field if necessary.
14018 - Make sure that the arch supports Neon instructions.
14020 Which of these operations take place depends on bits from enum
14021 vfp_or_neon_is_neon_bits.
14023 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14024 current instruction's condition is COND_ALWAYS, the condition field is
14025 changed to inst.uncond_value. This is necessary because instructions shared
14026 between VFP and Neon may be conditional for the VFP variants only, and the
14027 unconditional Neon version must have, e.g., 0xF in the condition field. */
14030 vfp_or_neon_is_neon (unsigned check)
14032 /* Conditions are always legal in Thumb mode (IT blocks). */
14033 if (!thumb_mode && (check & NEON_CHECK_CC))
14035 if (inst.cond != COND_ALWAYS)
14037 first_error (_(BAD_COND));
14040 if (inst.uncond_value != -1)
14041 inst.instruction |= inst.uncond_value << 28;
14044 if ((check & NEON_CHECK_ARCH)
14045 && !mark_feature_used (&fpu_neon_ext_v1))
14047 first_error (_(BAD_FPU));
14051 if ((check & NEON_CHECK_ARCH8)
14052 && !mark_feature_used (&fpu_neon_ext_armv8))
14054 first_error (_(BAD_FPU));
14062 do_neon_addsub_if_i (void)
14064 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14067 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14070 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14071 affected if we specify unsigned args. */
14072 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14075 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14077 V<op> A,B (A is operand 0, B is operand 2)
14082 so handle that case specially. */
14085 neon_exchange_operands (void)
14087 void *scratch = alloca (sizeof (inst.operands[0]));
14088 if (inst.operands[1].present)
14090 /* Swap operands[1] and operands[2]. */
14091 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14092 inst.operands[1] = inst.operands[2];
14093 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14097 inst.operands[1] = inst.operands[2];
14098 inst.operands[2] = inst.operands[0];
14103 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14105 if (inst.operands[2].isreg)
14108 neon_exchange_operands ();
14109 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14113 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14114 struct neon_type_el et = neon_check_type (2, rs,
14115 N_EQK | N_SIZ, immtypes | N_KEY);
14117 NEON_ENCODE (IMMED, inst);
14118 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14119 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14120 inst.instruction |= LOW4 (inst.operands[1].reg);
14121 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14122 inst.instruction |= neon_quad (rs) << 6;
14123 inst.instruction |= (et.type == NT_float) << 10;
14124 inst.instruction |= neon_logbits (et.size) << 18;
14126 neon_dp_fixup (&inst);
14133 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14137 do_neon_cmp_inv (void)
14139 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14145 neon_compare (N_IF_32, N_IF_32, FALSE);
14148 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14149 scalars, which are encoded in 5 bits, M : Rm.
14150 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14151 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14155 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14157 unsigned regno = NEON_SCALAR_REG (scalar);
14158 unsigned elno = NEON_SCALAR_INDEX (scalar);
14163 if (regno > 7 || elno > 3)
14165 return regno | (elno << 3);
14168 if (regno > 15 || elno > 1)
14170 return regno | (elno << 4);
14174 first_error (_("scalar out of range for multiply instruction"));
14180 /* Encode multiply / multiply-accumulate scalar instructions. */
14183 neon_mul_mac (struct neon_type_el et, int ubit)
14187 /* Give a more helpful error message if we have an invalid type. */
14188 if (et.type == NT_invtype)
14191 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14192 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14193 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14194 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14195 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14196 inst.instruction |= LOW4 (scalar);
14197 inst.instruction |= HI1 (scalar) << 5;
14198 inst.instruction |= (et.type == NT_float) << 8;
14199 inst.instruction |= neon_logbits (et.size) << 20;
14200 inst.instruction |= (ubit != 0) << 24;
14202 neon_dp_fixup (&inst);
14206 do_neon_mac_maybe_scalar (void)
14208 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14211 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14214 if (inst.operands[2].isscalar)
14216 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14217 struct neon_type_el et = neon_check_type (3, rs,
14218 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14219 NEON_ENCODE (SCALAR, inst);
14220 neon_mul_mac (et, neon_quad (rs));
14224 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14225 affected if we specify unsigned args. */
14226 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14231 do_neon_fmac (void)
14233 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14236 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14239 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14245 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14246 struct neon_type_el et = neon_check_type (3, rs,
14247 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14248 neon_three_same (neon_quad (rs), 0, et.size);
14251 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14252 same types as the MAC equivalents. The polynomial type for this instruction
14253 is encoded the same as the integer type. */
14258 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14261 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14264 if (inst.operands[2].isscalar)
14265 do_neon_mac_maybe_scalar ();
14267 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14271 do_neon_qdmulh (void)
14273 if (inst.operands[2].isscalar)
14275 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14276 struct neon_type_el et = neon_check_type (3, rs,
14277 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14278 NEON_ENCODE (SCALAR, inst);
14279 neon_mul_mac (et, neon_quad (rs));
14283 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14284 struct neon_type_el et = neon_check_type (3, rs,
14285 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14286 NEON_ENCODE (INTEGER, inst);
14287 /* The U bit (rounding) comes from bit mask. */
14288 neon_three_same (neon_quad (rs), 0, et.size);
14293 do_neon_fcmp_absolute (void)
14295 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14296 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14297 /* Size field comes from bit mask. */
14298 neon_three_same (neon_quad (rs), 1, -1);
14302 do_neon_fcmp_absolute_inv (void)
14304 neon_exchange_operands ();
14305 do_neon_fcmp_absolute ();
14309 do_neon_step (void)
14311 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14312 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14313 neon_three_same (neon_quad (rs), 0, -1);
14317 do_neon_abs_neg (void)
14319 enum neon_shape rs;
14320 struct neon_type_el et;
14322 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14325 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14328 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14329 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14331 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14332 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14333 inst.instruction |= LOW4 (inst.operands[1].reg);
14334 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14335 inst.instruction |= neon_quad (rs) << 6;
14336 inst.instruction |= (et.type == NT_float) << 10;
14337 inst.instruction |= neon_logbits (et.size) << 18;
14339 neon_dp_fixup (&inst);
14345 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14346 struct neon_type_el et = neon_check_type (2, rs,
14347 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14348 int imm = inst.operands[2].imm;
14349 constraint (imm < 0 || (unsigned)imm >= et.size,
14350 _("immediate out of range for insert"));
14351 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14357 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14358 struct neon_type_el et = neon_check_type (2, rs,
14359 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14360 int imm = inst.operands[2].imm;
14361 constraint (imm < 1 || (unsigned)imm > et.size,
14362 _("immediate out of range for insert"));
14363 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14367 do_neon_qshlu_imm (void)
14369 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14370 struct neon_type_el et = neon_check_type (2, rs,
14371 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14372 int imm = inst.operands[2].imm;
14373 constraint (imm < 0 || (unsigned)imm >= et.size,
14374 _("immediate out of range for shift"));
14375 /* Only encodes the 'U present' variant of the instruction.
14376 In this case, signed types have OP (bit 8) set to 0.
14377 Unsigned types have OP set to 1. */
14378 inst.instruction |= (et.type == NT_unsigned) << 8;
14379 /* The rest of the bits are the same as other immediate shifts. */
14380 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14384 do_neon_qmovn (void)
14386 struct neon_type_el et = neon_check_type (2, NS_DQ,
14387 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14388 /* Saturating move where operands can be signed or unsigned, and the
14389 destination has the same signedness. */
14390 NEON_ENCODE (INTEGER, inst);
14391 if (et.type == NT_unsigned)
14392 inst.instruction |= 0xc0;
14394 inst.instruction |= 0x80;
14395 neon_two_same (0, 1, et.size / 2);
14399 do_neon_qmovun (void)
14401 struct neon_type_el et = neon_check_type (2, NS_DQ,
14402 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14403 /* Saturating move with unsigned results. Operands must be signed. */
14404 NEON_ENCODE (INTEGER, inst);
14405 neon_two_same (0, 1, et.size / 2);
14409 do_neon_rshift_sat_narrow (void)
14411 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14412 or unsigned. If operands are unsigned, results must also be unsigned. */
14413 struct neon_type_el et = neon_check_type (2, NS_DQI,
14414 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14415 int imm = inst.operands[2].imm;
14416 /* This gets the bounds check, size encoding and immediate bits calculation
14420 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14421 VQMOVN.I<size> <Dd>, <Qm>. */
14424 inst.operands[2].present = 0;
14425 inst.instruction = N_MNEM_vqmovn;
14430 constraint (imm < 1 || (unsigned)imm > et.size,
14431 _("immediate out of range"));
14432 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14436 do_neon_rshift_sat_narrow_u (void)
14438 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14439 or unsigned. If operands are unsigned, results must also be unsigned. */
14440 struct neon_type_el et = neon_check_type (2, NS_DQI,
14441 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14442 int imm = inst.operands[2].imm;
14443 /* This gets the bounds check, size encoding and immediate bits calculation
14447 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14448 VQMOVUN.I<size> <Dd>, <Qm>. */
14451 inst.operands[2].present = 0;
14452 inst.instruction = N_MNEM_vqmovun;
14457 constraint (imm < 1 || (unsigned)imm > et.size,
14458 _("immediate out of range"));
14459 /* FIXME: The manual is kind of unclear about what value U should have in
14460 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14462 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14466 do_neon_movn (void)
14468 struct neon_type_el et = neon_check_type (2, NS_DQ,
14469 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14470 NEON_ENCODE (INTEGER, inst);
14471 neon_two_same (0, 1, et.size / 2);
14475 do_neon_rshift_narrow (void)
14477 struct neon_type_el et = neon_check_type (2, NS_DQI,
14478 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14479 int imm = inst.operands[2].imm;
14480 /* This gets the bounds check, size encoding and immediate bits calculation
14484 /* If immediate is zero then we are a pseudo-instruction for
14485 VMOVN.I<size> <Dd>, <Qm> */
14488 inst.operands[2].present = 0;
14489 inst.instruction = N_MNEM_vmovn;
14494 constraint (imm < 1 || (unsigned)imm > et.size,
14495 _("immediate out of range for narrowing operation"));
14496 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14500 do_neon_shll (void)
14502 /* FIXME: Type checking when lengthening. */
14503 struct neon_type_el et = neon_check_type (2, NS_QDI,
14504 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14505 unsigned imm = inst.operands[2].imm;
14507 if (imm == et.size)
14509 /* Maximum shift variant. */
14510 NEON_ENCODE (INTEGER, inst);
14511 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14512 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14513 inst.instruction |= LOW4 (inst.operands[1].reg);
14514 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14515 inst.instruction |= neon_logbits (et.size) << 18;
14517 neon_dp_fixup (&inst);
14521 /* A more-specific type check for non-max versions. */
14522 et = neon_check_type (2, NS_QDI,
14523 N_EQK | N_DBL, N_SU_32 | N_KEY);
14524 NEON_ENCODE (IMMED, inst);
14525 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14529 /* Check the various types for the VCVT instruction, and return which version
14530 the current instruction is. */
14532 #define CVT_FLAVOUR_VAR \
14533 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14534 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14535 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14536 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14537 /* Half-precision conversions. */ \
14538 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14539 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14540 /* VFP instructions. */ \
14541 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14542 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14543 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14544 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14545 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14546 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14547 /* VFP instructions with bitshift. */ \
14548 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14549 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14550 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14551 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14552 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14553 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14554 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14555 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14557 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14558 neon_cvt_flavour_##C,
14560 /* The different types of conversions we can do. */
14561 enum neon_cvt_flavour
14564 neon_cvt_flavour_invalid,
14565 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14570 static enum neon_cvt_flavour
14571 get_neon_cvt_flavour (enum neon_shape rs)
14573 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14574 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14575 if (et.type != NT_invtype) \
14577 inst.error = NULL; \
14578 return (neon_cvt_flavour_##C); \
14581 struct neon_type_el et;
14582 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14583 || rs == NS_FF) ? N_VFP : 0;
14584 /* The instruction versions which take an immediate take one register
14585 argument, which is extended to the width of the full register. Thus the
14586 "source" and "destination" registers must have the same width. Hack that
14587 here by making the size equal to the key (wider, in this case) operand. */
14588 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14592 return neon_cvt_flavour_invalid;
14607 /* Neon-syntax VFP conversions. */
14610 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14612 const char *opname = 0;
14614 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14616 /* Conversions with immediate bitshift. */
14617 const char *enc[] =
14619 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14625 if (flavour < (int) ARRAY_SIZE (enc))
14627 opname = enc[flavour];
14628 constraint (inst.operands[0].reg != inst.operands[1].reg,
14629 _("operands 0 and 1 must be the same register"));
14630 inst.operands[1] = inst.operands[2];
14631 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14636 /* Conversions without bitshift. */
14637 const char *enc[] =
14639 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14645 if (flavour < (int) ARRAY_SIZE (enc))
14646 opname = enc[flavour];
14650 do_vfp_nsyn_opcode (opname);
14654 do_vfp_nsyn_cvtz (void)
14656 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14657 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14658 const char *enc[] =
14660 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14666 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14667 do_vfp_nsyn_opcode (enc[flavour]);
14671 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14672 enum neon_cvt_mode mode)
14677 set_it_insn_type (OUTSIDE_IT_INSN);
14681 case neon_cvt_flavour_s32_f64:
14685 case neon_cvt_flavour_s32_f32:
14689 case neon_cvt_flavour_u32_f64:
14693 case neon_cvt_flavour_u32_f32:
14698 first_error (_("invalid instruction shape"));
14704 case neon_cvt_mode_a: rm = 0; break;
14705 case neon_cvt_mode_n: rm = 1; break;
14706 case neon_cvt_mode_p: rm = 2; break;
14707 case neon_cvt_mode_m: rm = 3; break;
14708 default: first_error (_("invalid rounding mode")); return;
14711 NEON_ENCODE (FPV8, inst);
14712 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14713 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14714 inst.instruction |= sz << 8;
14715 inst.instruction |= op << 7;
14716 inst.instruction |= rm << 16;
14717 inst.instruction |= 0xf0000000;
14718 inst.is_neon = TRUE;
14722 do_neon_cvt_1 (enum neon_cvt_mode mode)
14724 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14725 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14726 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14728 /* PR11109: Handle round-to-zero for VCVT conversions. */
14729 if (mode == neon_cvt_mode_z
14730 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14731 && (flavour == neon_cvt_flavour_s32_f32
14732 || flavour == neon_cvt_flavour_u32_f32
14733 || flavour == neon_cvt_flavour_s32_f64
14734 || flavour == neon_cvt_flavour_u32_f64)
14735 && (rs == NS_FD || rs == NS_FF))
14737 do_vfp_nsyn_cvtz ();
14741 /* VFP rather than Neon conversions. */
14742 if (flavour >= neon_cvt_flavour_first_fp)
14744 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14745 do_vfp_nsyn_cvt (rs, flavour);
14747 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14758 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14760 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14763 /* Fixed-point conversion with #0 immediate is encoded as an
14764 integer conversion. */
14765 if (inst.operands[2].present && inst.operands[2].imm == 0)
14767 immbits = 32 - inst.operands[2].imm;
14768 NEON_ENCODE (IMMED, inst);
14769 if (flavour != neon_cvt_flavour_invalid)
14770 inst.instruction |= enctab[flavour];
14771 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14772 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14773 inst.instruction |= LOW4 (inst.operands[1].reg);
14774 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14775 inst.instruction |= neon_quad (rs) << 6;
14776 inst.instruction |= 1 << 21;
14777 inst.instruction |= immbits << 16;
14779 neon_dp_fixup (&inst);
14785 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14787 NEON_ENCODE (FLOAT, inst);
14788 set_it_insn_type (OUTSIDE_IT_INSN);
14790 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14793 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14794 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14795 inst.instruction |= LOW4 (inst.operands[1].reg);
14796 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14797 inst.instruction |= neon_quad (rs) << 6;
14798 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14799 inst.instruction |= mode << 8;
14801 inst.instruction |= 0xfc000000;
14803 inst.instruction |= 0xf0000000;
14809 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14811 NEON_ENCODE (INTEGER, inst);
14813 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14816 if (flavour != neon_cvt_flavour_invalid)
14817 inst.instruction |= enctab[flavour];
14819 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14820 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14821 inst.instruction |= LOW4 (inst.operands[1].reg);
14822 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14823 inst.instruction |= neon_quad (rs) << 6;
14824 inst.instruction |= 2 << 18;
14826 neon_dp_fixup (&inst);
14831 /* Half-precision conversions for Advanced SIMD -- neon. */
14836 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14838 as_bad (_("operand size must match register width"));
14843 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14845 as_bad (_("operand size must match register width"));
14850 inst.instruction = 0x3b60600;
14852 inst.instruction = 0x3b60700;
14854 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14855 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14856 inst.instruction |= LOW4 (inst.operands[1].reg);
14857 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14858 neon_dp_fixup (&inst);
14862 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14863 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14864 do_vfp_nsyn_cvt (rs, flavour);
14866 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14871 do_neon_cvtr (void)
14873 do_neon_cvt_1 (neon_cvt_mode_x);
14879 do_neon_cvt_1 (neon_cvt_mode_z);
14883 do_neon_cvta (void)
14885 do_neon_cvt_1 (neon_cvt_mode_a);
14889 do_neon_cvtn (void)
14891 do_neon_cvt_1 (neon_cvt_mode_n);
14895 do_neon_cvtp (void)
14897 do_neon_cvt_1 (neon_cvt_mode_p);
14901 do_neon_cvtm (void)
14903 do_neon_cvt_1 (neon_cvt_mode_m);
14907 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14910 mark_feature_used (&fpu_vfp_ext_armv8);
14912 encode_arm_vfp_reg (inst.operands[0].reg,
14913 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14914 encode_arm_vfp_reg (inst.operands[1].reg,
14915 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14916 inst.instruction |= to ? 0x10000 : 0;
14917 inst.instruction |= t ? 0x80 : 0;
14918 inst.instruction |= is_double ? 0x100 : 0;
14919 do_vfp_cond_or_thumb ();
14923 do_neon_cvttb_1 (bfd_boolean t)
14925 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14929 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14932 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14934 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14937 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14939 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14942 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14944 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14947 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14954 do_neon_cvtb (void)
14956 do_neon_cvttb_1 (FALSE);
14961 do_neon_cvtt (void)
14963 do_neon_cvttb_1 (TRUE);
14967 neon_move_immediate (void)
14969 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14970 struct neon_type_el et = neon_check_type (2, rs,
14971 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14972 unsigned immlo, immhi = 0, immbits;
14973 int op, cmode, float_p;
14975 constraint (et.type == NT_invtype,
14976 _("operand size must be specified for immediate VMOV"));
14978 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14979 op = (inst.instruction & (1 << 5)) != 0;
14981 immlo = inst.operands[1].imm;
14982 if (inst.operands[1].regisimm)
14983 immhi = inst.operands[1].reg;
14985 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14986 _("immediate has bits set outside the operand size"));
14988 float_p = inst.operands[1].immisfloat;
14990 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14991 et.size, et.type)) == FAIL)
14993 /* Invert relevant bits only. */
14994 neon_invert_size (&immlo, &immhi, et.size);
14995 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14996 with one or the other; those cases are caught by
14997 neon_cmode_for_move_imm. */
14999 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15000 &op, et.size, et.type)) == FAIL)
15002 first_error (_("immediate out of range"));
15007 inst.instruction &= ~(1 << 5);
15008 inst.instruction |= op << 5;
15010 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15011 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15012 inst.instruction |= neon_quad (rs) << 6;
15013 inst.instruction |= cmode << 8;
15015 neon_write_immbits (immbits);
15021 if (inst.operands[1].isreg)
15023 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15025 NEON_ENCODE (INTEGER, inst);
15026 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15027 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15028 inst.instruction |= LOW4 (inst.operands[1].reg);
15029 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15030 inst.instruction |= neon_quad (rs) << 6;
15034 NEON_ENCODE (IMMED, inst);
15035 neon_move_immediate ();
15038 neon_dp_fixup (&inst);
15041 /* Encode instructions of form:
15043 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15044 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15047 neon_mixed_length (struct neon_type_el et, unsigned size)
15049 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15050 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15051 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15052 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15053 inst.instruction |= LOW4 (inst.operands[2].reg);
15054 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15055 inst.instruction |= (et.type == NT_unsigned) << 24;
15056 inst.instruction |= neon_logbits (size) << 20;
15058 neon_dp_fixup (&inst);
15062 do_neon_dyadic_long (void)
15064 /* FIXME: Type checking for lengthening op. */
15065 struct neon_type_el et = neon_check_type (3, NS_QDD,
15066 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15067 neon_mixed_length (et, et.size);
15071 do_neon_abal (void)
15073 struct neon_type_el et = neon_check_type (3, NS_QDD,
15074 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15075 neon_mixed_length (et, et.size);
15079 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15081 if (inst.operands[2].isscalar)
15083 struct neon_type_el et = neon_check_type (3, NS_QDS,
15084 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15085 NEON_ENCODE (SCALAR, inst);
15086 neon_mul_mac (et, et.type == NT_unsigned);
15090 struct neon_type_el et = neon_check_type (3, NS_QDD,
15091 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15092 NEON_ENCODE (INTEGER, inst);
15093 neon_mixed_length (et, et.size);
15098 do_neon_mac_maybe_scalar_long (void)
15100 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15104 do_neon_dyadic_wide (void)
15106 struct neon_type_el et = neon_check_type (3, NS_QQD,
15107 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15108 neon_mixed_length (et, et.size);
15112 do_neon_dyadic_narrow (void)
15114 struct neon_type_el et = neon_check_type (3, NS_QDD,
15115 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15116 /* Operand sign is unimportant, and the U bit is part of the opcode,
15117 so force the operand type to integer. */
15118 et.type = NT_integer;
15119 neon_mixed_length (et, et.size / 2);
15123 do_neon_mul_sat_scalar_long (void)
15125 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15129 do_neon_vmull (void)
15131 if (inst.operands[2].isscalar)
15132 do_neon_mac_maybe_scalar_long ();
15135 struct neon_type_el et = neon_check_type (3, NS_QDD,
15136 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15138 if (et.type == NT_poly)
15139 NEON_ENCODE (POLY, inst);
15141 NEON_ENCODE (INTEGER, inst);
15143 /* For polynomial encoding the U bit must be zero, and the size must
15144 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15145 obviously, as 0b10). */
15148 /* Check we're on the correct architecture. */
15149 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15151 _("Instruction form not available on this architecture.");
15156 neon_mixed_length (et, et.size);
15163 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15164 struct neon_type_el et = neon_check_type (3, rs,
15165 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15166 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15168 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15169 _("shift out of range"));
15170 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15171 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15172 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15173 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15174 inst.instruction |= LOW4 (inst.operands[2].reg);
15175 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15176 inst.instruction |= neon_quad (rs) << 6;
15177 inst.instruction |= imm << 8;
15179 neon_dp_fixup (&inst);
15185 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15186 struct neon_type_el et = neon_check_type (2, rs,
15187 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15188 unsigned op = (inst.instruction >> 7) & 3;
15189 /* N (width of reversed regions) is encoded as part of the bitmask. We
15190 extract it here to check the elements to be reversed are smaller.
15191 Otherwise we'd get a reserved instruction. */
15192 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15193 gas_assert (elsize != 0);
15194 constraint (et.size >= elsize,
15195 _("elements must be smaller than reversal region"));
15196 neon_two_same (neon_quad (rs), 1, et.size);
15202 if (inst.operands[1].isscalar)
15204 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15205 struct neon_type_el et = neon_check_type (2, rs,
15206 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15207 unsigned sizebits = et.size >> 3;
15208 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15209 int logsize = neon_logbits (et.size);
15210 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15212 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15215 NEON_ENCODE (SCALAR, inst);
15216 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15217 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15218 inst.instruction |= LOW4 (dm);
15219 inst.instruction |= HI1 (dm) << 5;
15220 inst.instruction |= neon_quad (rs) << 6;
15221 inst.instruction |= x << 17;
15222 inst.instruction |= sizebits << 16;
15224 neon_dp_fixup (&inst);
15228 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15229 struct neon_type_el et = neon_check_type (2, rs,
15230 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15231 /* Duplicate ARM register to lanes of vector. */
15232 NEON_ENCODE (ARMREG, inst);
15235 case 8: inst.instruction |= 0x400000; break;
15236 case 16: inst.instruction |= 0x000020; break;
15237 case 32: inst.instruction |= 0x000000; break;
15240 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15241 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15242 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15243 inst.instruction |= neon_quad (rs) << 21;
15244 /* The encoding for this instruction is identical for the ARM and Thumb
15245 variants, except for the condition field. */
15246 do_vfp_cond_or_thumb ();
15250 /* VMOV has particularly many variations. It can be one of:
15251 0. VMOV<c><q> <Qd>, <Qm>
15252 1. VMOV<c><q> <Dd>, <Dm>
15253 (Register operations, which are VORR with Rm = Rn.)
15254 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15255 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15257 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15258 (ARM register to scalar.)
15259 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15260 (Two ARM registers to vector.)
15261 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15262 (Scalar to ARM register.)
15263 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15264 (Vector to two ARM registers.)
15265 8. VMOV.F32 <Sd>, <Sm>
15266 9. VMOV.F64 <Dd>, <Dm>
15267 (VFP register moves.)
15268 10. VMOV.F32 <Sd>, #imm
15269 11. VMOV.F64 <Dd>, #imm
15270 (VFP float immediate load.)
15271 12. VMOV <Rd>, <Sm>
15272 (VFP single to ARM reg.)
15273 13. VMOV <Sd>, <Rm>
15274 (ARM reg to VFP single.)
15275 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15276 (Two ARM regs to two VFP singles.)
15277 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15278 (Two VFP singles to two ARM regs.)
15280 These cases can be disambiguated using neon_select_shape, except cases 1/9
15281 and 3/11 which depend on the operand type too.
15283 All the encoded bits are hardcoded by this function.
15285 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15286 Cases 5, 7 may be used with VFPv2 and above.
15288 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15289 can specify a type where it doesn't make sense to, and is ignored). */
15294 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15295 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15297 struct neon_type_el et;
15298 const char *ldconst = 0;
15302 case NS_DD: /* case 1/9. */
15303 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15304 /* It is not an error here if no type is given. */
15306 if (et.type == NT_float && et.size == 64)
15308 do_vfp_nsyn_opcode ("fcpyd");
15311 /* fall through. */
15313 case NS_QQ: /* case 0/1. */
15315 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15317 /* The architecture manual I have doesn't explicitly state which
15318 value the U bit should have for register->register moves, but
15319 the equivalent VORR instruction has U = 0, so do that. */
15320 inst.instruction = 0x0200110;
15321 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15322 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15323 inst.instruction |= LOW4 (inst.operands[1].reg);
15324 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15325 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15326 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15327 inst.instruction |= neon_quad (rs) << 6;
15329 neon_dp_fixup (&inst);
15333 case NS_DI: /* case 3/11. */
15334 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15336 if (et.type == NT_float && et.size == 64)
15338 /* case 11 (fconstd). */
15339 ldconst = "fconstd";
15340 goto encode_fconstd;
15342 /* fall through. */
15344 case NS_QI: /* case 2/3. */
15345 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15347 inst.instruction = 0x0800010;
15348 neon_move_immediate ();
15349 neon_dp_fixup (&inst);
15352 case NS_SR: /* case 4. */
15354 unsigned bcdebits = 0;
15356 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15357 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15359 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15360 logsize = neon_logbits (et.size);
15362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15364 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15365 && et.size != 32, _(BAD_FPU));
15366 constraint (et.type == NT_invtype, _("bad type for scalar"));
15367 constraint (x >= 64 / et.size, _("scalar index out of range"));
15371 case 8: bcdebits = 0x8; break;
15372 case 16: bcdebits = 0x1; break;
15373 case 32: bcdebits = 0x0; break;
15377 bcdebits |= x << logsize;
15379 inst.instruction = 0xe000b10;
15380 do_vfp_cond_or_thumb ();
15381 inst.instruction |= LOW4 (dn) << 16;
15382 inst.instruction |= HI1 (dn) << 7;
15383 inst.instruction |= inst.operands[1].reg << 12;
15384 inst.instruction |= (bcdebits & 3) << 5;
15385 inst.instruction |= (bcdebits >> 2) << 21;
15389 case NS_DRR: /* case 5 (fmdrr). */
15390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15393 inst.instruction = 0xc400b10;
15394 do_vfp_cond_or_thumb ();
15395 inst.instruction |= LOW4 (inst.operands[0].reg);
15396 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15397 inst.instruction |= inst.operands[1].reg << 12;
15398 inst.instruction |= inst.operands[2].reg << 16;
15401 case NS_RS: /* case 6. */
15404 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15405 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15406 unsigned abcdebits = 0;
15408 et = neon_check_type (2, NS_NULL,
15409 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15410 logsize = neon_logbits (et.size);
15412 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15414 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15415 && et.size != 32, _(BAD_FPU));
15416 constraint (et.type == NT_invtype, _("bad type for scalar"));
15417 constraint (x >= 64 / et.size, _("scalar index out of range"));
15421 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15422 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15423 case 32: abcdebits = 0x00; break;
15427 abcdebits |= x << logsize;
15428 inst.instruction = 0xe100b10;
15429 do_vfp_cond_or_thumb ();
15430 inst.instruction |= LOW4 (dn) << 16;
15431 inst.instruction |= HI1 (dn) << 7;
15432 inst.instruction |= inst.operands[0].reg << 12;
15433 inst.instruction |= (abcdebits & 3) << 5;
15434 inst.instruction |= (abcdebits >> 2) << 21;
15438 case NS_RRD: /* case 7 (fmrrd). */
15439 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15442 inst.instruction = 0xc500b10;
15443 do_vfp_cond_or_thumb ();
15444 inst.instruction |= inst.operands[0].reg << 12;
15445 inst.instruction |= inst.operands[1].reg << 16;
15446 inst.instruction |= LOW4 (inst.operands[2].reg);
15447 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15450 case NS_FF: /* case 8 (fcpys). */
15451 do_vfp_nsyn_opcode ("fcpys");
15454 case NS_FI: /* case 10 (fconsts). */
15455 ldconst = "fconsts";
15457 if (is_quarter_float (inst.operands[1].imm))
15459 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15460 do_vfp_nsyn_opcode (ldconst);
15463 first_error (_("immediate out of range"));
15466 case NS_RF: /* case 12 (fmrs). */
15467 do_vfp_nsyn_opcode ("fmrs");
15470 case NS_FR: /* case 13 (fmsr). */
15471 do_vfp_nsyn_opcode ("fmsr");
15474 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15475 (one of which is a list), but we have parsed four. Do some fiddling to
15476 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15478 case NS_RRFF: /* case 14 (fmrrs). */
15479 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15480 _("VFP registers must be adjacent"));
15481 inst.operands[2].imm = 2;
15482 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15483 do_vfp_nsyn_opcode ("fmrrs");
15486 case NS_FFRR: /* case 15 (fmsrr). */
15487 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15488 _("VFP registers must be adjacent"));
15489 inst.operands[1] = inst.operands[2];
15490 inst.operands[2] = inst.operands[3];
15491 inst.operands[0].imm = 2;
15492 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15493 do_vfp_nsyn_opcode ("fmsrr");
15502 do_neon_rshift_round_imm (void)
15504 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15505 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15506 int imm = inst.operands[2].imm;
15508 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15511 inst.operands[2].present = 0;
15516 constraint (imm < 1 || (unsigned)imm > et.size,
15517 _("immediate out of range for shift"));
15518 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15523 do_neon_movl (void)
15525 struct neon_type_el et = neon_check_type (2, NS_QD,
15526 N_EQK | N_DBL, N_SU_32 | N_KEY);
15527 unsigned sizebits = et.size >> 3;
15528 inst.instruction |= sizebits << 19;
15529 neon_two_same (0, et.type == NT_unsigned, -1);
15535 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15536 struct neon_type_el et = neon_check_type (2, rs,
15537 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15538 NEON_ENCODE (INTEGER, inst);
15539 neon_two_same (neon_quad (rs), 1, et.size);
15543 do_neon_zip_uzp (void)
15545 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15546 struct neon_type_el et = neon_check_type (2, rs,
15547 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15548 if (rs == NS_DD && et.size == 32)
15550 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15551 inst.instruction = N_MNEM_vtrn;
15555 neon_two_same (neon_quad (rs), 1, et.size);
15559 do_neon_sat_abs_neg (void)
15561 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15562 struct neon_type_el et = neon_check_type (2, rs,
15563 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15564 neon_two_same (neon_quad (rs), 1, et.size);
15568 do_neon_pair_long (void)
15570 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15571 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15572 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15573 inst.instruction |= (et.type == NT_unsigned) << 7;
15574 neon_two_same (neon_quad (rs), 1, et.size);
15578 do_neon_recip_est (void)
15580 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15581 struct neon_type_el et = neon_check_type (2, rs,
15582 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15583 inst.instruction |= (et.type == NT_float) << 8;
15584 neon_two_same (neon_quad (rs), 1, et.size);
15590 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15591 struct neon_type_el et = neon_check_type (2, rs,
15592 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15593 neon_two_same (neon_quad (rs), 1, et.size);
15599 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15600 struct neon_type_el et = neon_check_type (2, rs,
15601 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15602 neon_two_same (neon_quad (rs), 1, et.size);
15608 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15609 struct neon_type_el et = neon_check_type (2, rs,
15610 N_EQK | N_INT, N_8 | N_KEY);
15611 neon_two_same (neon_quad (rs), 1, et.size);
15617 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15618 neon_two_same (neon_quad (rs), 1, -1);
15622 do_neon_tbl_tbx (void)
15624 unsigned listlenbits;
15625 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15627 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15629 first_error (_("bad list length for table lookup"));
15633 listlenbits = inst.operands[1].imm - 1;
15634 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15635 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15636 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15637 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15638 inst.instruction |= LOW4 (inst.operands[2].reg);
15639 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15640 inst.instruction |= listlenbits << 8;
15642 neon_dp_fixup (&inst);
15646 do_neon_ldm_stm (void)
15648 /* P, U and L bits are part of bitmask. */
15649 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15650 unsigned offsetbits = inst.operands[1].imm * 2;
15652 if (inst.operands[1].issingle)
15654 do_vfp_nsyn_ldm_stm (is_dbmode);
15658 constraint (is_dbmode && !inst.operands[0].writeback,
15659 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15661 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15662 _("register list must contain at least 1 and at most 16 "
15665 inst.instruction |= inst.operands[0].reg << 16;
15666 inst.instruction |= inst.operands[0].writeback << 21;
15667 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15668 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15670 inst.instruction |= offsetbits;
15672 do_vfp_cond_or_thumb ();
15676 do_neon_ldr_str (void)
15678 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15680 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15681 And is UNPREDICTABLE in thumb mode. */
15683 && inst.operands[1].reg == REG_PC
15684 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15686 if (!thumb_mode && warn_on_deprecated)
15687 as_warn (_("Use of PC here is deprecated"));
15689 inst.error = _("Use of PC here is UNPREDICTABLE");
15692 if (inst.operands[0].issingle)
15695 do_vfp_nsyn_opcode ("flds");
15697 do_vfp_nsyn_opcode ("fsts");
15702 do_vfp_nsyn_opcode ("fldd");
15704 do_vfp_nsyn_opcode ("fstd");
15708 /* "interleave" version also handles non-interleaving register VLD1/VST1
15712 do_neon_ld_st_interleave (void)
15714 struct neon_type_el et = neon_check_type (1, NS_NULL,
15715 N_8 | N_16 | N_32 | N_64);
15716 unsigned alignbits = 0;
15718 /* The bits in this table go:
15719 0: register stride of one (0) or two (1)
15720 1,2: register list length, minus one (1, 2, 3, 4).
15721 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15722 We use -1 for invalid entries. */
15723 const int typetable[] =
15725 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15726 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15727 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15728 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15732 if (et.type == NT_invtype)
15735 if (inst.operands[1].immisalign)
15736 switch (inst.operands[1].imm >> 8)
15738 case 64: alignbits = 1; break;
15740 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15741 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15742 goto bad_alignment;
15746 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15747 goto bad_alignment;
15752 first_error (_("bad alignment"));
15756 inst.instruction |= alignbits << 4;
15757 inst.instruction |= neon_logbits (et.size) << 6;
15759 /* Bits [4:6] of the immediate in a list specifier encode register stride
15760 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15761 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15762 up the right value for "type" in a table based on this value and the given
15763 list style, then stick it back. */
15764 idx = ((inst.operands[0].imm >> 4) & 7)
15765 | (((inst.instruction >> 8) & 3) << 3);
15767 typebits = typetable[idx];
15769 constraint (typebits == -1, _("bad list type for instruction"));
15771 inst.instruction &= ~0xf00;
15772 inst.instruction |= typebits << 8;
15775 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15776 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15777 otherwise. The variable arguments are a list of pairs of legal (size, align)
15778 values, terminated with -1. */
15781 neon_alignment_bit (int size, int align, int *do_align, ...)
15784 int result = FAIL, thissize, thisalign;
15786 if (!inst.operands[1].immisalign)
15792 va_start (ap, do_align);
15796 thissize = va_arg (ap, int);
15797 if (thissize == -1)
15799 thisalign = va_arg (ap, int);
15801 if (size == thissize && align == thisalign)
15804 while (result != SUCCESS);
15808 if (result == SUCCESS)
15811 first_error (_("unsupported alignment for instruction"));
15817 do_neon_ld_st_lane (void)
15819 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15820 int align_good, do_align = 0;
15821 int logsize = neon_logbits (et.size);
15822 int align = inst.operands[1].imm >> 8;
15823 int n = (inst.instruction >> 8) & 3;
15824 int max_el = 64 / et.size;
15826 if (et.type == NT_invtype)
15829 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15830 _("bad list length"));
15831 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15832 _("scalar index out of range"));
15833 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15835 _("stride of 2 unavailable when element size is 8"));
15839 case 0: /* VLD1 / VST1. */
15840 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15842 if (align_good == FAIL)
15846 unsigned alignbits = 0;
15849 case 16: alignbits = 0x1; break;
15850 case 32: alignbits = 0x3; break;
15853 inst.instruction |= alignbits << 4;
15857 case 1: /* VLD2 / VST2. */
15858 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15860 if (align_good == FAIL)
15863 inst.instruction |= 1 << 4;
15866 case 2: /* VLD3 / VST3. */
15867 constraint (inst.operands[1].immisalign,
15868 _("can't use alignment with this instruction"));
15871 case 3: /* VLD4 / VST4. */
15872 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15873 16, 64, 32, 64, 32, 128, -1);
15874 if (align_good == FAIL)
15878 unsigned alignbits = 0;
15881 case 8: alignbits = 0x1; break;
15882 case 16: alignbits = 0x1; break;
15883 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15886 inst.instruction |= alignbits << 4;
15893 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15894 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15895 inst.instruction |= 1 << (4 + logsize);
15897 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15898 inst.instruction |= logsize << 10;
15901 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15904 do_neon_ld_dup (void)
15906 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15907 int align_good, do_align = 0;
15909 if (et.type == NT_invtype)
15912 switch ((inst.instruction >> 8) & 3)
15914 case 0: /* VLD1. */
15915 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15916 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15917 &do_align, 16, 16, 32, 32, -1);
15918 if (align_good == FAIL)
15920 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15923 case 2: inst.instruction |= 1 << 5; break;
15924 default: first_error (_("bad list length")); return;
15926 inst.instruction |= neon_logbits (et.size) << 6;
15929 case 1: /* VLD2. */
15930 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15931 &do_align, 8, 16, 16, 32, 32, 64, -1);
15932 if (align_good == FAIL)
15934 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15935 _("bad list length"));
15936 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15937 inst.instruction |= 1 << 5;
15938 inst.instruction |= neon_logbits (et.size) << 6;
15941 case 2: /* VLD3. */
15942 constraint (inst.operands[1].immisalign,
15943 _("can't use alignment with this instruction"));
15944 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15945 _("bad list length"));
15946 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15947 inst.instruction |= 1 << 5;
15948 inst.instruction |= neon_logbits (et.size) << 6;
15951 case 3: /* VLD4. */
15953 int align = inst.operands[1].imm >> 8;
15954 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15955 16, 64, 32, 64, 32, 128, -1);
15956 if (align_good == FAIL)
15958 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15959 _("bad list length"));
15960 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15961 inst.instruction |= 1 << 5;
15962 if (et.size == 32 && align == 128)
15963 inst.instruction |= 0x3 << 6;
15965 inst.instruction |= neon_logbits (et.size) << 6;
15972 inst.instruction |= do_align << 4;
15975 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15976 apart from bits [11:4]. */
15979 do_neon_ldx_stx (void)
15981 if (inst.operands[1].isreg)
15982 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15984 switch (NEON_LANE (inst.operands[0].imm))
15986 case NEON_INTERLEAVE_LANES:
15987 NEON_ENCODE (INTERLV, inst);
15988 do_neon_ld_st_interleave ();
15991 case NEON_ALL_LANES:
15992 NEON_ENCODE (DUP, inst);
15997 NEON_ENCODE (LANE, inst);
15998 do_neon_ld_st_lane ();
16001 /* L bit comes from bit mask. */
16002 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16003 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16004 inst.instruction |= inst.operands[1].reg << 16;
16006 if (inst.operands[1].postind)
16008 int postreg = inst.operands[1].imm & 0xf;
16009 constraint (!inst.operands[1].immisreg,
16010 _("post-index must be a register"));
16011 constraint (postreg == 0xd || postreg == 0xf,
16012 _("bad register for post-index"));
16013 inst.instruction |= postreg;
16015 else if (inst.operands[1].writeback)
16017 inst.instruction |= 0xd;
16020 inst.instruction |= 0xf;
16023 inst.instruction |= 0xf9000000;
16025 inst.instruction |= 0xf4000000;
16030 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16032 NEON_ENCODE (FPV8, inst);
16035 do_vfp_sp_dyadic ();
16037 do_vfp_dp_rd_rn_rm ();
16040 inst.instruction |= 0x100;
16042 inst.instruction |= 0xf0000000;
16048 set_it_insn_type (OUTSIDE_IT_INSN);
16050 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16051 first_error (_("invalid instruction shape"));
16057 set_it_insn_type (OUTSIDE_IT_INSN);
16059 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16062 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16065 neon_dyadic_misc (NT_untyped, N_F32, 0);
16069 do_vrint_1 (enum neon_cvt_mode mode)
16071 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16072 struct neon_type_el et;
16077 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16078 if (et.type != NT_invtype)
16080 /* VFP encodings. */
16081 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16082 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16083 set_it_insn_type (OUTSIDE_IT_INSN);
16085 NEON_ENCODE (FPV8, inst);
16087 do_vfp_sp_monadic ();
16089 do_vfp_dp_rd_rm ();
16093 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16094 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16095 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16096 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16097 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16098 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16099 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16103 inst.instruction |= (rs == NS_DD) << 8;
16104 do_vfp_cond_or_thumb ();
16108 /* Neon encodings (or something broken...). */
16110 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16112 if (et.type == NT_invtype)
16115 set_it_insn_type (OUTSIDE_IT_INSN);
16116 NEON_ENCODE (FLOAT, inst);
16118 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16121 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16122 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16123 inst.instruction |= LOW4 (inst.operands[1].reg);
16124 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16125 inst.instruction |= neon_quad (rs) << 6;
16128 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16129 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16130 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16131 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16132 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16133 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16134 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16139 inst.instruction |= 0xfc000000;
16141 inst.instruction |= 0xf0000000;
16148 do_vrint_1 (neon_cvt_mode_x);
16154 do_vrint_1 (neon_cvt_mode_z);
16160 do_vrint_1 (neon_cvt_mode_r);
16166 do_vrint_1 (neon_cvt_mode_a);
16172 do_vrint_1 (neon_cvt_mode_n);
16178 do_vrint_1 (neon_cvt_mode_p);
16184 do_vrint_1 (neon_cvt_mode_m);
16187 /* Crypto v1 instructions. */
16189 do_crypto_2op_1 (unsigned elttype, int op)
16191 set_it_insn_type (OUTSIDE_IT_INSN);
16193 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16199 NEON_ENCODE (INTEGER, inst);
16200 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16201 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16202 inst.instruction |= LOW4 (inst.operands[1].reg);
16203 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16205 inst.instruction |= op << 6;
16208 inst.instruction |= 0xfc000000;
16210 inst.instruction |= 0xf0000000;
16214 do_crypto_3op_1 (int u, int op)
16216 set_it_insn_type (OUTSIDE_IT_INSN);
16218 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16219 N_32 | N_UNT | N_KEY).type == NT_invtype)
16224 NEON_ENCODE (INTEGER, inst);
16225 neon_three_same (1, u, 8 << op);
16231 do_crypto_2op_1 (N_8, 0);
16237 do_crypto_2op_1 (N_8, 1);
16243 do_crypto_2op_1 (N_8, 2);
16249 do_crypto_2op_1 (N_8, 3);
16255 do_crypto_3op_1 (0, 0);
16261 do_crypto_3op_1 (0, 1);
16267 do_crypto_3op_1 (0, 2);
16273 do_crypto_3op_1 (0, 3);
16279 do_crypto_3op_1 (1, 0);
16285 do_crypto_3op_1 (1, 1);
16289 do_sha256su1 (void)
16291 do_crypto_3op_1 (1, 2);
16297 do_crypto_2op_1 (N_32, -1);
16303 do_crypto_2op_1 (N_32, 0);
16307 do_sha256su0 (void)
16309 do_crypto_2op_1 (N_32, 1);
16312 /* Overall per-instruction processing. */
16314 /* We need to be able to fix up arbitrary expressions in some statements.
16315 This is so that we can handle symbols that are an arbitrary distance from
16316 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16317 which returns part of an address in a form which will be valid for
16318 a data instruction. We do this by pushing the expression into a symbol
16319 in the expr_section, and creating a fix for that. */
16322 fix_new_arm (fragS * frag,
16336 /* Create an absolute valued symbol, so we have something to
16337 refer to in the object file. Unfortunately for us, gas's
16338 generic expression parsing will already have folded out
16339 any use of .set foo/.type foo %function that may have
16340 been used to set type information of the target location,
16341 that's being specified symbolically. We have to presume
16342 the user knows what they are doing. */
16346 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16348 symbol = symbol_find_or_make (name);
16349 S_SET_SEGMENT (symbol, absolute_section);
16350 symbol_set_frag (symbol, &zero_address_frag);
16351 S_SET_VALUE (symbol, exp->X_add_number);
16352 exp->X_op = O_symbol;
16353 exp->X_add_symbol = symbol;
16354 exp->X_add_number = 0;
16360 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16361 (enum bfd_reloc_code_real) reloc);
16365 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16366 pc_rel, (enum bfd_reloc_code_real) reloc);
16370 /* Mark whether the fix is to a THUMB instruction, or an ARM
16372 new_fix->tc_fix_data = thumb_mode;
16375 /* Create a frg for an instruction requiring relaxation. */
16377 output_relax_insn (void)
16383 /* The size of the instruction is unknown, so tie the debug info to the
16384 start of the instruction. */
16385 dwarf2_emit_insn (0);
16387 switch (inst.reloc.exp.X_op)
16390 sym = inst.reloc.exp.X_add_symbol;
16391 offset = inst.reloc.exp.X_add_number;
16395 offset = inst.reloc.exp.X_add_number;
16398 sym = make_expr_symbol (&inst.reloc.exp);
16402 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16403 inst.relax, sym, offset, NULL/*offset, opcode*/);
16404 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16407 /* Write a 32-bit thumb instruction to buf. */
16409 put_thumb32_insn (char * buf, unsigned long insn)
16411 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16412 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16416 output_inst (const char * str)
16422 as_bad ("%s -- `%s'", inst.error, str);
16427 output_relax_insn ();
16430 if (inst.size == 0)
16433 to = frag_more (inst.size);
16434 /* PR 9814: Record the thumb mode into the current frag so that we know
16435 what type of NOP padding to use, if necessary. We override any previous
16436 setting so that if the mode has changed then the NOPS that we use will
16437 match the encoding of the last instruction in the frag. */
16438 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16440 if (thumb_mode && (inst.size > THUMB_SIZE))
16442 gas_assert (inst.size == (2 * THUMB_SIZE));
16443 put_thumb32_insn (to, inst.instruction);
16445 else if (inst.size > INSN_SIZE)
16447 gas_assert (inst.size == (2 * INSN_SIZE));
16448 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16449 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16452 md_number_to_chars (to, inst.instruction, inst.size);
16454 if (inst.reloc.type != BFD_RELOC_UNUSED)
16455 fix_new_arm (frag_now, to - frag_now->fr_literal,
16456 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16459 dwarf2_emit_insn (inst.size);
16463 output_it_inst (int cond, int mask, char * to)
16465 unsigned long instruction = 0xbf00;
16468 instruction |= mask;
16469 instruction |= cond << 4;
16473 to = frag_more (2);
16475 dwarf2_emit_insn (2);
16479 md_number_to_chars (to, instruction, 2);
16484 /* Tag values used in struct asm_opcode's tag field. */
16487 OT_unconditional, /* Instruction cannot be conditionalized.
16488 The ARM condition field is still 0xE. */
16489 OT_unconditionalF, /* Instruction cannot be conditionalized
16490 and carries 0xF in its ARM condition field. */
16491 OT_csuffix, /* Instruction takes a conditional suffix. */
16492 OT_csuffixF, /* Some forms of the instruction take a conditional
16493 suffix, others place 0xF where the condition field
16495 OT_cinfix3, /* Instruction takes a conditional infix,
16496 beginning at character index 3. (In
16497 unified mode, it becomes a suffix.) */
16498 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16499 tsts, cmps, cmns, and teqs. */
16500 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16501 character index 3, even in unified mode. Used for
16502 legacy instructions where suffix and infix forms
16503 may be ambiguous. */
16504 OT_csuf_or_in3, /* Instruction takes either a conditional
16505 suffix or an infix at character index 3. */
16506 OT_odd_infix_unc, /* This is the unconditional variant of an
16507 instruction that takes a conditional infix
16508 at an unusual position. In unified mode,
16509 this variant will accept a suffix. */
16510 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16511 are the conditional variants of instructions that
16512 take conditional infixes in unusual positions.
16513 The infix appears at character index
16514 (tag - OT_odd_infix_0). These are not accepted
16515 in unified mode. */
16518 /* Subroutine of md_assemble, responsible for looking up the primary
16519 opcode from the mnemonic the user wrote. STR points to the
16520 beginning of the mnemonic.
16522 This is not simply a hash table lookup, because of conditional
16523 variants. Most instructions have conditional variants, which are
16524 expressed with a _conditional affix_ to the mnemonic. If we were
16525 to encode each conditional variant as a literal string in the opcode
16526 table, it would have approximately 20,000 entries.
16528 Most mnemonics take this affix as a suffix, and in unified syntax,
16529 'most' is upgraded to 'all'. However, in the divided syntax, some
16530 instructions take the affix as an infix, notably the s-variants of
16531 the arithmetic instructions. Of those instructions, all but six
16532 have the infix appear after the third character of the mnemonic.
16534 Accordingly, the algorithm for looking up primary opcodes given
16537 1. Look up the identifier in the opcode table.
16538 If we find a match, go to step U.
16540 2. Look up the last two characters of the identifier in the
16541 conditions table. If we find a match, look up the first N-2
16542 characters of the identifier in the opcode table. If we
16543 find a match, go to step CE.
16545 3. Look up the fourth and fifth characters of the identifier in
16546 the conditions table. If we find a match, extract those
16547 characters from the identifier, and look up the remaining
16548 characters in the opcode table. If we find a match, go
16553 U. Examine the tag field of the opcode structure, in case this is
16554 one of the six instructions with its conditional infix in an
16555 unusual place. If it is, the tag tells us where to find the
16556 infix; look it up in the conditions table and set inst.cond
16557 accordingly. Otherwise, this is an unconditional instruction.
16558 Again set inst.cond accordingly. Return the opcode structure.
16560 CE. Examine the tag field to make sure this is an instruction that
16561 should receive a conditional suffix. If it is not, fail.
16562 Otherwise, set inst.cond from the suffix we already looked up,
16563 and return the opcode structure.
16565 CM. Examine the tag field to make sure this is an instruction that
16566 should receive a conditional infix after the third character.
16567 If it is not, fail. Otherwise, undo the edits to the current
16568 line of input and proceed as for case CE. */
16570 static const struct asm_opcode *
16571 opcode_lookup (char **str)
16575 const struct asm_opcode *opcode;
16576 const struct asm_cond *cond;
16579 /* Scan up to the end of the mnemonic, which must end in white space,
16580 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16581 for (base = end = *str; *end != '\0'; end++)
16582 if (*end == ' ' || *end == '.')
16588 /* Handle a possible width suffix and/or Neon type suffix. */
16593 /* The .w and .n suffixes are only valid if the unified syntax is in
16595 if (unified_syntax && end[1] == 'w')
16597 else if (unified_syntax && end[1] == 'n')
16602 inst.vectype.elems = 0;
16604 *str = end + offset;
16606 if (end[offset] == '.')
16608 /* See if we have a Neon type suffix (possible in either unified or
16609 non-unified ARM syntax mode). */
16610 if (parse_neon_type (&inst.vectype, str) == FAIL)
16613 else if (end[offset] != '\0' && end[offset] != ' ')
16619 /* Look for unaffixed or special-case affixed mnemonic. */
16620 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16625 if (opcode->tag < OT_odd_infix_0)
16627 inst.cond = COND_ALWAYS;
16631 if (warn_on_deprecated && unified_syntax)
16632 as_warn (_("conditional infixes are deprecated in unified syntax"));
16633 affix = base + (opcode->tag - OT_odd_infix_0);
16634 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16637 inst.cond = cond->value;
16641 /* Cannot have a conditional suffix on a mnemonic of less than two
16643 if (end - base < 3)
16646 /* Look for suffixed mnemonic. */
16648 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16649 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16651 if (opcode && cond)
16654 switch (opcode->tag)
16656 case OT_cinfix3_legacy:
16657 /* Ignore conditional suffixes matched on infix only mnemonics. */
16661 case OT_cinfix3_deprecated:
16662 case OT_odd_infix_unc:
16663 if (!unified_syntax)
16665 /* else fall through */
16669 case OT_csuf_or_in3:
16670 inst.cond = cond->value;
16673 case OT_unconditional:
16674 case OT_unconditionalF:
16676 inst.cond = cond->value;
16679 /* Delayed diagnostic. */
16680 inst.error = BAD_COND;
16681 inst.cond = COND_ALWAYS;
16690 /* Cannot have a usual-position infix on a mnemonic of less than
16691 six characters (five would be a suffix). */
16692 if (end - base < 6)
16695 /* Look for infixed mnemonic in the usual position. */
16697 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16701 memcpy (save, affix, 2);
16702 memmove (affix, affix + 2, (end - affix) - 2);
16703 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16705 memmove (affix + 2, affix, (end - affix) - 2);
16706 memcpy (affix, save, 2);
16709 && (opcode->tag == OT_cinfix3
16710 || opcode->tag == OT_cinfix3_deprecated
16711 || opcode->tag == OT_csuf_or_in3
16712 || opcode->tag == OT_cinfix3_legacy))
16715 if (warn_on_deprecated && unified_syntax
16716 && (opcode->tag == OT_cinfix3
16717 || opcode->tag == OT_cinfix3_deprecated))
16718 as_warn (_("conditional infixes are deprecated in unified syntax"));
16720 inst.cond = cond->value;
16727 /* This function generates an initial IT instruction, leaving its block
16728 virtually open for the new instructions. Eventually,
16729 the mask will be updated by now_it_add_mask () each time
16730 a new instruction needs to be included in the IT block.
16731 Finally, the block is closed with close_automatic_it_block ().
16732 The block closure can be requested either from md_assemble (),
16733 a tencode (), or due to a label hook. */
16736 new_automatic_it_block (int cond)
16738 now_it.state = AUTOMATIC_IT_BLOCK;
16739 now_it.mask = 0x18;
16741 now_it.block_length = 1;
16742 mapping_state (MAP_THUMB);
16743 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16744 now_it.warn_deprecated = FALSE;
16745 now_it.insn_cond = TRUE;
16748 /* Close an automatic IT block.
16749 See comments in new_automatic_it_block (). */
16752 close_automatic_it_block (void)
16754 now_it.mask = 0x10;
16755 now_it.block_length = 0;
16758 /* Update the mask of the current automatically-generated IT
16759 instruction. See comments in new_automatic_it_block (). */
16762 now_it_add_mask (int cond)
16764 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16765 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16766 | ((bitvalue) << (nbit)))
16767 const int resulting_bit = (cond & 1);
16769 now_it.mask &= 0xf;
16770 now_it.mask = SET_BIT_VALUE (now_it.mask,
16772 (5 - now_it.block_length));
16773 now_it.mask = SET_BIT_VALUE (now_it.mask,
16775 ((5 - now_it.block_length) - 1) );
16776 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16779 #undef SET_BIT_VALUE
16782 /* The IT blocks handling machinery is accessed through the these functions:
16783 it_fsm_pre_encode () from md_assemble ()
16784 set_it_insn_type () optional, from the tencode functions
16785 set_it_insn_type_last () ditto
16786 in_it_block () ditto
16787 it_fsm_post_encode () from md_assemble ()
16788 force_automatic_it_block_close () from label habdling functions
16791 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16792 initializing the IT insn type with a generic initial value depending
16793 on the inst.condition.
16794 2) During the tencode function, two things may happen:
16795 a) The tencode function overrides the IT insn type by
16796 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16797 b) The tencode function queries the IT block state by
16798 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16800 Both set_it_insn_type and in_it_block run the internal FSM state
16801 handling function (handle_it_state), because: a) setting the IT insn
16802 type may incur in an invalid state (exiting the function),
16803 and b) querying the state requires the FSM to be updated.
16804 Specifically we want to avoid creating an IT block for conditional
16805 branches, so it_fsm_pre_encode is actually a guess and we can't
16806 determine whether an IT block is required until the tencode () routine
16807 has decided what type of instruction this actually it.
16808 Because of this, if set_it_insn_type and in_it_block have to be used,
16809 set_it_insn_type has to be called first.
16811 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16812 determines the insn IT type depending on the inst.cond code.
16813 When a tencode () routine encodes an instruction that can be
16814 either outside an IT block, or, in the case of being inside, has to be
16815 the last one, set_it_insn_type_last () will determine the proper
16816 IT instruction type based on the inst.cond code. Otherwise,
16817 set_it_insn_type can be called for overriding that logic or
16818 for covering other cases.
16820 Calling handle_it_state () may not transition the IT block state to
16821 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16822 still queried. Instead, if the FSM determines that the state should
16823 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16824 after the tencode () function: that's what it_fsm_post_encode () does.
16826 Since in_it_block () calls the state handling function to get an
16827 updated state, an error may occur (due to invalid insns combination).
16828 In that case, inst.error is set.
16829 Therefore, inst.error has to be checked after the execution of
16830 the tencode () routine.
16832 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16833 any pending state change (if any) that didn't take place in
16834 handle_it_state () as explained above. */
16837 it_fsm_pre_encode (void)
16839 if (inst.cond != COND_ALWAYS)
16840 inst.it_insn_type = INSIDE_IT_INSN;
16842 inst.it_insn_type = OUTSIDE_IT_INSN;
16844 now_it.state_handled = 0;
16847 /* IT state FSM handling function. */
16850 handle_it_state (void)
16852 now_it.state_handled = 1;
16853 now_it.insn_cond = FALSE;
16855 switch (now_it.state)
16857 case OUTSIDE_IT_BLOCK:
16858 switch (inst.it_insn_type)
16860 case OUTSIDE_IT_INSN:
16863 case INSIDE_IT_INSN:
16864 case INSIDE_IT_LAST_INSN:
16865 if (thumb_mode == 0)
16868 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16869 as_tsktsk (_("Warning: conditional outside an IT block"\
16874 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16875 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16877 /* Automatically generate the IT instruction. */
16878 new_automatic_it_block (inst.cond);
16879 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16880 close_automatic_it_block ();
16884 inst.error = BAD_OUT_IT;
16890 case IF_INSIDE_IT_LAST_INSN:
16891 case NEUTRAL_IT_INSN:
16895 now_it.state = MANUAL_IT_BLOCK;
16896 now_it.block_length = 0;
16901 case AUTOMATIC_IT_BLOCK:
16902 /* Three things may happen now:
16903 a) We should increment current it block size;
16904 b) We should close current it block (closing insn or 4 insns);
16905 c) We should close current it block and start a new one (due
16906 to incompatible conditions or
16907 4 insns-length block reached). */
16909 switch (inst.it_insn_type)
16911 case OUTSIDE_IT_INSN:
16912 /* The closure of the block shall happen immediatelly,
16913 so any in_it_block () call reports the block as closed. */
16914 force_automatic_it_block_close ();
16917 case INSIDE_IT_INSN:
16918 case INSIDE_IT_LAST_INSN:
16919 case IF_INSIDE_IT_LAST_INSN:
16920 now_it.block_length++;
16922 if (now_it.block_length > 4
16923 || !now_it_compatible (inst.cond))
16925 force_automatic_it_block_close ();
16926 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16927 new_automatic_it_block (inst.cond);
16931 now_it.insn_cond = TRUE;
16932 now_it_add_mask (inst.cond);
16935 if (now_it.state == AUTOMATIC_IT_BLOCK
16936 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16937 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16938 close_automatic_it_block ();
16941 case NEUTRAL_IT_INSN:
16942 now_it.block_length++;
16943 now_it.insn_cond = TRUE;
16945 if (now_it.block_length > 4)
16946 force_automatic_it_block_close ();
16948 now_it_add_mask (now_it.cc & 1);
16952 close_automatic_it_block ();
16953 now_it.state = MANUAL_IT_BLOCK;
16958 case MANUAL_IT_BLOCK:
16960 /* Check conditional suffixes. */
16961 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16964 now_it.mask &= 0x1f;
16965 is_last = (now_it.mask == 0x10);
16966 now_it.insn_cond = TRUE;
16968 switch (inst.it_insn_type)
16970 case OUTSIDE_IT_INSN:
16971 inst.error = BAD_NOT_IT;
16974 case INSIDE_IT_INSN:
16975 if (cond != inst.cond)
16977 inst.error = BAD_IT_COND;
16982 case INSIDE_IT_LAST_INSN:
16983 case IF_INSIDE_IT_LAST_INSN:
16984 if (cond != inst.cond)
16986 inst.error = BAD_IT_COND;
16991 inst.error = BAD_BRANCH;
16996 case NEUTRAL_IT_INSN:
16997 /* The BKPT instruction is unconditional even in an IT block. */
17001 inst.error = BAD_IT_IT;
17011 struct depr_insn_mask
17013 unsigned long pattern;
17014 unsigned long mask;
17015 const char* description;
17018 /* List of 16-bit instruction patterns deprecated in an IT block in
17020 static const struct depr_insn_mask depr_it_insns[] = {
17021 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17022 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17023 { 0xa000, 0xb800, N_("ADR") },
17024 { 0x4800, 0xf800, N_("Literal loads") },
17025 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17026 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17031 it_fsm_post_encode (void)
17035 if (!now_it.state_handled)
17036 handle_it_state ();
17038 if (now_it.insn_cond
17039 && !now_it.warn_deprecated
17040 && warn_on_deprecated
17041 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17043 if (inst.instruction >= 0x10000)
17045 as_warn (_("it blocks containing wide Thumb instructions are "
17046 "deprecated in ARMv8"));
17047 now_it.warn_deprecated = TRUE;
17051 const struct depr_insn_mask *p = depr_it_insns;
17053 while (p->mask != 0)
17055 if ((inst.instruction & p->mask) == p->pattern)
17057 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17058 "of the following class are deprecated in ARMv8: "
17059 "%s"), p->description);
17060 now_it.warn_deprecated = TRUE;
17068 if (now_it.block_length > 1)
17070 as_warn (_("it blocks of more than one conditional instruction are "
17071 "deprecated in ARMv8"));
17072 now_it.warn_deprecated = TRUE;
17076 is_last = (now_it.mask == 0x10);
17079 now_it.state = OUTSIDE_IT_BLOCK;
17085 force_automatic_it_block_close (void)
17087 if (now_it.state == AUTOMATIC_IT_BLOCK)
17089 close_automatic_it_block ();
17090 now_it.state = OUTSIDE_IT_BLOCK;
17098 if (!now_it.state_handled)
17099 handle_it_state ();
17101 return now_it.state != OUTSIDE_IT_BLOCK;
17105 md_assemble (char *str)
17108 const struct asm_opcode * opcode;
17110 /* Align the previous label if needed. */
17111 if (last_label_seen != NULL)
17113 symbol_set_frag (last_label_seen, frag_now);
17114 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17115 S_SET_SEGMENT (last_label_seen, now_seg);
17118 memset (&inst, '\0', sizeof (inst));
17119 inst.reloc.type = BFD_RELOC_UNUSED;
17121 opcode = opcode_lookup (&p);
17124 /* It wasn't an instruction, but it might be a register alias of
17125 the form alias .req reg, or a Neon .dn/.qn directive. */
17126 if (! create_register_alias (str, p)
17127 && ! create_neon_reg_alias (str, p))
17128 as_bad (_("bad instruction `%s'"), str);
17133 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17134 as_warn (_("s suffix on comparison instruction is deprecated"));
17136 /* The value which unconditional instructions should have in place of the
17137 condition field. */
17138 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17142 arm_feature_set variant;
17144 variant = cpu_variant;
17145 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17146 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17147 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17148 /* Check that this instruction is supported for this CPU. */
17149 if (!opcode->tvariant
17150 || (thumb_mode == 1
17151 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17153 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17156 if (inst.cond != COND_ALWAYS && !unified_syntax
17157 && opcode->tencode != do_t_branch)
17159 as_bad (_("Thumb does not support conditional execution"));
17163 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17165 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17166 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17167 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17169 /* Two things are addressed here.
17170 1) Implicit require narrow instructions on Thumb-1.
17171 This avoids relaxation accidentally introducing Thumb-2
17173 2) Reject wide instructions in non Thumb-2 cores. */
17174 if (inst.size_req == 0)
17176 else if (inst.size_req == 4)
17178 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17184 inst.instruction = opcode->tvalue;
17186 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17188 /* Prepare the it_insn_type for those encodings that don't set
17190 it_fsm_pre_encode ();
17192 opcode->tencode ();
17194 it_fsm_post_encode ();
17197 if (!(inst.error || inst.relax))
17199 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17200 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17201 if (inst.size_req && inst.size_req != inst.size)
17203 as_bad (_("cannot honor width suffix -- `%s'"), str);
17208 /* Something has gone badly wrong if we try to relax a fixed size
17210 gas_assert (inst.size_req == 0 || !inst.relax);
17212 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17213 *opcode->tvariant);
17214 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17215 set those bits when Thumb-2 32-bit instructions are seen. ie.
17216 anything other than bl/blx and v6-M instructions.
17217 This is overly pessimistic for relaxable instructions. */
17218 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17220 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17221 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17222 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17225 check_neon_suffixes;
17229 mapping_state (MAP_THUMB);
17232 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17236 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17237 is_bx = (opcode->aencode == do_bx);
17239 /* Check that this instruction is supported for this CPU. */
17240 if (!(is_bx && fix_v4bx)
17241 && !(opcode->avariant &&
17242 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17244 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17249 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17253 inst.instruction = opcode->avalue;
17254 if (opcode->tag == OT_unconditionalF)
17255 inst.instruction |= 0xF << 28;
17257 inst.instruction |= inst.cond << 28;
17258 inst.size = INSN_SIZE;
17259 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17261 it_fsm_pre_encode ();
17262 opcode->aencode ();
17263 it_fsm_post_encode ();
17265 /* Arm mode bx is marked as both v4T and v5 because it's still required
17266 on a hypothetical non-thumb v5 core. */
17268 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17270 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17271 *opcode->avariant);
17273 check_neon_suffixes;
17277 mapping_state (MAP_ARM);
17282 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17290 check_it_blocks_finished (void)
17295 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17296 if (seg_info (sect)->tc_segment_info_data.current_it.state
17297 == MANUAL_IT_BLOCK)
17299 as_warn (_("section '%s' finished with an open IT block."),
17303 if (now_it.state == MANUAL_IT_BLOCK)
17304 as_warn (_("file finished with an open IT block."));
17308 /* Various frobbings of labels and their addresses. */
17311 arm_start_line_hook (void)
17313 last_label_seen = NULL;
17317 arm_frob_label (symbolS * sym)
17319 last_label_seen = sym;
17321 ARM_SET_THUMB (sym, thumb_mode);
17323 #if defined OBJ_COFF || defined OBJ_ELF
17324 ARM_SET_INTERWORK (sym, support_interwork);
17327 force_automatic_it_block_close ();
17329 /* Note - do not allow local symbols (.Lxxx) to be labelled
17330 as Thumb functions. This is because these labels, whilst
17331 they exist inside Thumb code, are not the entry points for
17332 possible ARM->Thumb calls. Also, these labels can be used
17333 as part of a computed goto or switch statement. eg gcc
17334 can generate code that looks like this:
17336 ldr r2, [pc, .Laaa]
17346 The first instruction loads the address of the jump table.
17347 The second instruction converts a table index into a byte offset.
17348 The third instruction gets the jump address out of the table.
17349 The fourth instruction performs the jump.
17351 If the address stored at .Laaa is that of a symbol which has the
17352 Thumb_Func bit set, then the linker will arrange for this address
17353 to have the bottom bit set, which in turn would mean that the
17354 address computation performed by the third instruction would end
17355 up with the bottom bit set. Since the ARM is capable of unaligned
17356 word loads, the instruction would then load the incorrect address
17357 out of the jump table, and chaos would ensue. */
17358 if (label_is_thumb_function_name
17359 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17360 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17362 /* When the address of a Thumb function is taken the bottom
17363 bit of that address should be set. This will allow
17364 interworking between Arm and Thumb functions to work
17367 THUMB_SET_FUNC (sym, 1);
17369 label_is_thumb_function_name = FALSE;
17372 dwarf2_emit_label (sym);
17376 arm_data_in_code (void)
17378 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17380 *input_line_pointer = '/';
17381 input_line_pointer += 5;
17382 *input_line_pointer = 0;
17390 arm_canonicalize_symbol_name (char * name)
17394 if (thumb_mode && (len = strlen (name)) > 5
17395 && streq (name + len - 5, "/data"))
17396 *(name + len - 5) = 0;
17401 /* Table of all register names defined by default. The user can
17402 define additional names with .req. Note that all register names
17403 should appear in both upper and lowercase variants. Some registers
17404 also have mixed-case names. */
17406 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17407 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17408 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17409 #define REGSET(p,t) \
17410 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17411 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17412 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17413 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17414 #define REGSETH(p,t) \
17415 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17416 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17417 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17418 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17419 #define REGSET2(p,t) \
17420 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17421 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17422 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17423 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17424 #define SPLRBANK(base,bank,t) \
17425 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17426 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17427 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17428 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17429 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17430 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17432 static const struct reg_entry reg_names[] =
17434 /* ARM integer registers. */
17435 REGSET(r, RN), REGSET(R, RN),
17437 /* ATPCS synonyms. */
17438 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17439 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17440 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17442 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17443 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17444 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17446 /* Well-known aliases. */
17447 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17448 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17450 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17451 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17453 /* Coprocessor numbers. */
17454 REGSET(p, CP), REGSET(P, CP),
17456 /* Coprocessor register numbers. The "cr" variants are for backward
17458 REGSET(c, CN), REGSET(C, CN),
17459 REGSET(cr, CN), REGSET(CR, CN),
17461 /* ARM banked registers. */
17462 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17463 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17464 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17465 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17466 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17467 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17468 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17470 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17471 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17472 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17473 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17474 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17475 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
17476 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17477 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17479 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17480 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17481 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17482 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17483 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17484 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17485 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17486 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17487 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17489 /* FPA registers. */
17490 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17491 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17493 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17494 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17496 /* VFP SP registers. */
17497 REGSET(s,VFS), REGSET(S,VFS),
17498 REGSETH(s,VFS), REGSETH(S,VFS),
17500 /* VFP DP Registers. */
17501 REGSET(d,VFD), REGSET(D,VFD),
17502 /* Extra Neon DP registers. */
17503 REGSETH(d,VFD), REGSETH(D,VFD),
17505 /* Neon QP registers. */
17506 REGSET2(q,NQ), REGSET2(Q,NQ),
17508 /* VFP control registers. */
17509 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17510 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17511 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17512 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17513 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17514 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17516 /* Maverick DSP coprocessor registers. */
17517 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17518 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17520 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17521 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17522 REGDEF(dspsc,0,DSPSC),
17524 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17525 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17526 REGDEF(DSPSC,0,DSPSC),
17528 /* iWMMXt data registers - p0, c0-15. */
17529 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17531 /* iWMMXt control registers - p1, c0-3. */
17532 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17533 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17534 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17535 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17537 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17538 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17539 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17540 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17541 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17543 /* XScale accumulator registers. */
17544 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17550 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17551 within psr_required_here. */
17552 static const struct asm_psr psrs[] =
17554 /* Backward compatibility notation. Note that "all" is no longer
17555 truly all possible PSR bits. */
17556 {"all", PSR_c | PSR_f},
17560 /* Individual flags. */
17566 /* Combinations of flags. */
17567 {"fs", PSR_f | PSR_s},
17568 {"fx", PSR_f | PSR_x},
17569 {"fc", PSR_f | PSR_c},
17570 {"sf", PSR_s | PSR_f},
17571 {"sx", PSR_s | PSR_x},
17572 {"sc", PSR_s | PSR_c},
17573 {"xf", PSR_x | PSR_f},
17574 {"xs", PSR_x | PSR_s},
17575 {"xc", PSR_x | PSR_c},
17576 {"cf", PSR_c | PSR_f},
17577 {"cs", PSR_c | PSR_s},
17578 {"cx", PSR_c | PSR_x},
17579 {"fsx", PSR_f | PSR_s | PSR_x},
17580 {"fsc", PSR_f | PSR_s | PSR_c},
17581 {"fxs", PSR_f | PSR_x | PSR_s},
17582 {"fxc", PSR_f | PSR_x | PSR_c},
17583 {"fcs", PSR_f | PSR_c | PSR_s},
17584 {"fcx", PSR_f | PSR_c | PSR_x},
17585 {"sfx", PSR_s | PSR_f | PSR_x},
17586 {"sfc", PSR_s | PSR_f | PSR_c},
17587 {"sxf", PSR_s | PSR_x | PSR_f},
17588 {"sxc", PSR_s | PSR_x | PSR_c},
17589 {"scf", PSR_s | PSR_c | PSR_f},
17590 {"scx", PSR_s | PSR_c | PSR_x},
17591 {"xfs", PSR_x | PSR_f | PSR_s},
17592 {"xfc", PSR_x | PSR_f | PSR_c},
17593 {"xsf", PSR_x | PSR_s | PSR_f},
17594 {"xsc", PSR_x | PSR_s | PSR_c},
17595 {"xcf", PSR_x | PSR_c | PSR_f},
17596 {"xcs", PSR_x | PSR_c | PSR_s},
17597 {"cfs", PSR_c | PSR_f | PSR_s},
17598 {"cfx", PSR_c | PSR_f | PSR_x},
17599 {"csf", PSR_c | PSR_s | PSR_f},
17600 {"csx", PSR_c | PSR_s | PSR_x},
17601 {"cxf", PSR_c | PSR_x | PSR_f},
17602 {"cxs", PSR_c | PSR_x | PSR_s},
17603 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17604 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17605 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17606 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17607 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17608 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17609 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17610 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17611 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17612 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17613 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17614 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17615 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17616 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17617 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17618 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17619 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17620 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17621 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17622 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17623 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17624 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17625 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17626 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17629 /* Table of V7M psr names. */
17630 static const struct asm_psr v7m_psrs[] =
17632 {"apsr", 0 }, {"APSR", 0 },
17633 {"iapsr", 1 }, {"IAPSR", 1 },
17634 {"eapsr", 2 }, {"EAPSR", 2 },
17635 {"psr", 3 }, {"PSR", 3 },
17636 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17637 {"ipsr", 5 }, {"IPSR", 5 },
17638 {"epsr", 6 }, {"EPSR", 6 },
17639 {"iepsr", 7 }, {"IEPSR", 7 },
17640 {"msp", 8 }, {"MSP", 8 },
17641 {"psp", 9 }, {"PSP", 9 },
17642 {"primask", 16}, {"PRIMASK", 16},
17643 {"basepri", 17}, {"BASEPRI", 17},
17644 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17645 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17646 {"faultmask", 19}, {"FAULTMASK", 19},
17647 {"control", 20}, {"CONTROL", 20}
17650 /* Table of all shift-in-operand names. */
17651 static const struct asm_shift_name shift_names [] =
17653 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17654 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17655 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17656 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17657 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17658 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17661 /* Table of all explicit relocation names. */
17663 static struct reloc_entry reloc_names[] =
17665 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17666 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17667 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17668 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17669 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17670 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17671 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17672 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17673 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17674 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17675 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17676 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17677 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17678 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17679 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17680 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17681 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17682 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17686 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17687 static const struct asm_cond conds[] =
17691 {"cs", 0x2}, {"hs", 0x2},
17692 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17706 #define UL_BARRIER(L,U,CODE,FEAT) \
17707 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17708 { U, CODE, ARM_FEATURE (FEAT, 0) }
17710 static struct asm_barrier_opt barrier_opt_names[] =
17712 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17713 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17714 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17715 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17716 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17717 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17718 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17719 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17720 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17721 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17722 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17723 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17724 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17725 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17726 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17727 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17732 /* Table of ARM-format instructions. */
17734 /* Macros for gluing together operand strings. N.B. In all cases
17735 other than OPS0, the trailing OP_stop comes from default
17736 zero-initialization of the unspecified elements of the array. */
17737 #define OPS0() { OP_stop, }
17738 #define OPS1(a) { OP_##a, }
17739 #define OPS2(a,b) { OP_##a,OP_##b, }
17740 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17741 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17742 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17743 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17745 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17746 This is useful when mixing operands for ARM and THUMB, i.e. using the
17747 MIX_ARM_THUMB_OPERANDS macro.
17748 In order to use these macros, prefix the number of operands with _
17750 #define OPS_1(a) { a, }
17751 #define OPS_2(a,b) { a,b, }
17752 #define OPS_3(a,b,c) { a,b,c, }
17753 #define OPS_4(a,b,c,d) { a,b,c,d, }
17754 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17755 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17757 /* These macros abstract out the exact format of the mnemonic table and
17758 save some repeated characters. */
17760 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17761 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17762 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17763 THUMB_VARIANT, do_##ae, do_##te }
17765 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17766 a T_MNEM_xyz enumerator. */
17767 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17768 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17769 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17770 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17772 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17773 infix after the third character. */
17774 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17775 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17776 THUMB_VARIANT, do_##ae, do_##te }
17777 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17778 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17779 THUMB_VARIANT, do_##ae, do_##te }
17780 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17781 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17782 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17783 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17784 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17785 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17786 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17787 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17789 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17790 field is still 0xE. Many of the Thumb variants can be executed
17791 conditionally, so this is checked separately. */
17792 #define TUE(mnem, op, top, nops, ops, ae, te) \
17793 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17794 THUMB_VARIANT, do_##ae, do_##te }
17796 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17797 condition code field. */
17798 #define TUF(mnem, op, top, nops, ops, ae, te) \
17799 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17800 THUMB_VARIANT, do_##ae, do_##te }
17802 /* ARM-only variants of all the above. */
17803 #define CE(mnem, op, nops, ops, ae) \
17804 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17806 #define C3(mnem, op, nops, ops, ae) \
17807 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17809 /* Legacy mnemonics that always have conditional infix after the third
17811 #define CL(mnem, op, nops, ops, ae) \
17812 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17813 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17815 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17816 #define cCE(mnem, op, nops, ops, ae) \
17817 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17819 /* Legacy coprocessor instructions where conditional infix and conditional
17820 suffix are ambiguous. For consistency this includes all FPA instructions,
17821 not just the potentially ambiguous ones. */
17822 #define cCL(mnem, op, nops, ops, ae) \
17823 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17824 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17826 /* Coprocessor, takes either a suffix or a position-3 infix
17827 (for an FPA corner case). */
17828 #define C3E(mnem, op, nops, ops, ae) \
17829 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17830 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17832 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17833 { m1 #m2 m3, OPS##nops ops, \
17834 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17835 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17837 #define CM(m1, m2, op, nops, ops, ae) \
17838 xCM_ (m1, , m2, op, nops, ops, ae), \
17839 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17840 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17841 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17842 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17843 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17844 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17845 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17846 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17847 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17848 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17849 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17850 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17851 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17852 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17853 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17854 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17855 xCM_ (m1, le, m2, op, nops, ops, ae), \
17856 xCM_ (m1, al, m2, op, nops, ops, ae)
17858 #define UE(mnem, op, nops, ops, ae) \
17859 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17861 #define UF(mnem, op, nops, ops, ae) \
17862 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17864 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17865 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17866 use the same encoding function for each. */
17867 #define NUF(mnem, op, nops, ops, enc) \
17868 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17869 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17871 /* Neon data processing, version which indirects through neon_enc_tab for
17872 the various overloaded versions of opcodes. */
17873 #define nUF(mnem, op, nops, ops, enc) \
17874 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17875 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17877 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17879 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17880 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17881 THUMB_VARIANT, do_##enc, do_##enc }
17883 #define NCE(mnem, op, nops, ops, enc) \
17884 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17886 #define NCEF(mnem, op, nops, ops, enc) \
17887 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17889 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17890 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17891 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17892 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17894 #define nCE(mnem, op, nops, ops, enc) \
17895 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17897 #define nCEF(mnem, op, nops, ops, enc) \
17898 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17902 static const struct asm_opcode insns[] =
17904 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17905 #define THUMB_VARIANT &arm_ext_v4t
17906 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17907 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17908 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17909 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17910 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17911 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17912 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17913 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17914 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17915 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17916 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17917 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17918 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17919 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17920 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17921 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17923 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17924 for setting PSR flag bits. They are obsolete in V6 and do not
17925 have Thumb equivalents. */
17926 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17927 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17928 CL("tstp", 110f000, 2, (RR, SH), cmp),
17929 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17930 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17931 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17932 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17933 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17934 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17936 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17937 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17938 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17939 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17941 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17942 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17943 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17945 OP_ADDRGLDR),ldst, t_ldst),
17946 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17948 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17949 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17950 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17951 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17952 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17953 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17955 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17956 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17957 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17958 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17961 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17962 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17963 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17965 /* Thumb-compatibility pseudo ops. */
17966 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17967 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17968 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17969 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17970 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17971 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17972 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17973 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17974 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17975 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17976 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17977 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17979 /* These may simplify to neg. */
17980 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17981 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17983 #undef THUMB_VARIANT
17984 #define THUMB_VARIANT & arm_ext_v6
17986 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17988 /* V1 instructions with no Thumb analogue prior to V6T2. */
17989 #undef THUMB_VARIANT
17990 #define THUMB_VARIANT & arm_ext_v6t2
17992 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17993 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17994 CL("teqp", 130f000, 2, (RR, SH), cmp),
17996 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17997 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17998 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17999 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18001 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18002 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18004 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18005 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18007 /* V1 instructions with no Thumb analogue at all. */
18008 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18009 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18011 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18012 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18013 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18014 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18015 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18016 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18017 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18018 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18021 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18022 #undef THUMB_VARIANT
18023 #define THUMB_VARIANT & arm_ext_v4t
18025 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18026 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18028 #undef THUMB_VARIANT
18029 #define THUMB_VARIANT & arm_ext_v6t2
18031 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18032 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18034 /* Generic coprocessor instructions. */
18035 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18036 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18037 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18038 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18039 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18040 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18041 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18044 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18046 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18047 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18050 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18051 #undef THUMB_VARIANT
18052 #define THUMB_VARIANT & arm_ext_msr
18054 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18055 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18058 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18059 #undef THUMB_VARIANT
18060 #define THUMB_VARIANT & arm_ext_v6t2
18062 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18063 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18064 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18065 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18066 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18067 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18068 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18069 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18072 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18073 #undef THUMB_VARIANT
18074 #define THUMB_VARIANT & arm_ext_v4t
18076 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18077 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18078 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18079 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18080 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18081 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18084 #define ARM_VARIANT & arm_ext_v4t_5
18086 /* ARM Architecture 4T. */
18087 /* Note: bx (and blx) are required on V5, even if the processor does
18088 not support Thumb. */
18089 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18092 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18093 #undef THUMB_VARIANT
18094 #define THUMB_VARIANT & arm_ext_v5t
18096 /* Note: blx has 2 variants; the .value coded here is for
18097 BLX(2). Only this variant has conditional execution. */
18098 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18099 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18101 #undef THUMB_VARIANT
18102 #define THUMB_VARIANT & arm_ext_v6t2
18104 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18105 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18106 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18107 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18108 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18109 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18110 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18111 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18114 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18115 #undef THUMB_VARIANT
18116 #define THUMB_VARIANT &arm_ext_v5exp
18118 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18119 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18120 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18121 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18123 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18124 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18126 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18127 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18128 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18129 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18131 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18132 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18133 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18134 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18136 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18137 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18139 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18140 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18141 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18142 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18145 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18146 #undef THUMB_VARIANT
18147 #define THUMB_VARIANT &arm_ext_v6t2
18149 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18150 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18152 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18153 ADDRGLDRS), ldrd, t_ldstd),
18155 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18156 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18159 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18161 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18164 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18165 #undef THUMB_VARIANT
18166 #define THUMB_VARIANT & arm_ext_v6
18168 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18169 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18170 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18171 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18172 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18173 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18174 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18175 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18176 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18177 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18179 #undef THUMB_VARIANT
18180 #define THUMB_VARIANT & arm_ext_v6t2
18182 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18183 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18185 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18186 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18188 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18189 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18191 /* ARM V6 not included in V7M. */
18192 #undef THUMB_VARIANT
18193 #define THUMB_VARIANT & arm_ext_v6_notm
18194 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18195 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18196 UF(rfeib, 9900a00, 1, (RRw), rfe),
18197 UF(rfeda, 8100a00, 1, (RRw), rfe),
18198 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18199 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18200 UF(rfefa, 8100a00, 1, (RRw), rfe),
18201 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18202 UF(rfeed, 9900a00, 1, (RRw), rfe),
18203 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18204 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18205 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18206 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18207 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18208 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18209 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18210 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18211 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18213 /* ARM V6 not included in V7M (eg. integer SIMD). */
18214 #undef THUMB_VARIANT
18215 #define THUMB_VARIANT & arm_ext_v6_dsp
18216 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18217 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18218 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18219 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18220 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18221 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18222 /* Old name for QASX. */
18223 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18224 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18225 /* Old name for QSAX. */
18226 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18227 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18228 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18229 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18230 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18231 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18232 /* Old name for SASX. */
18233 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18234 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18235 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18236 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18237 /* Old name for SHASX. */
18238 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18239 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18240 /* Old name for SHSAX. */
18241 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18242 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18243 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18244 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18245 /* Old name for SSAX. */
18246 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18247 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18248 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18249 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18250 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18251 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18252 /* Old name for UASX. */
18253 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18254 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18255 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18256 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18257 /* Old name for UHASX. */
18258 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18259 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18260 /* Old name for UHSAX. */
18261 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18262 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18263 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18264 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18265 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18266 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18267 /* Old name for UQASX. */
18268 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18269 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18270 /* Old name for UQSAX. */
18271 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18272 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18273 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18274 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18275 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18276 /* Old name for USAX. */
18277 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18278 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18279 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18280 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18281 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18282 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18283 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18284 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18285 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18286 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18287 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18288 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18289 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18290 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18291 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18292 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18293 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18294 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18295 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18296 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18297 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18298 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18299 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18300 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18301 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18302 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18303 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18304 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18305 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18306 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18307 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18308 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18309 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18310 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18313 #define ARM_VARIANT & arm_ext_v6k
18314 #undef THUMB_VARIANT
18315 #define THUMB_VARIANT & arm_ext_v6k
18317 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18318 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18319 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18320 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18322 #undef THUMB_VARIANT
18323 #define THUMB_VARIANT & arm_ext_v6_notm
18324 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18326 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18327 RRnpcb), strexd, t_strexd),
18329 #undef THUMB_VARIANT
18330 #define THUMB_VARIANT & arm_ext_v6t2
18331 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18333 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18335 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18337 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18339 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18342 #define ARM_VARIANT & arm_ext_sec
18343 #undef THUMB_VARIANT
18344 #define THUMB_VARIANT & arm_ext_sec
18346 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18349 #define ARM_VARIANT & arm_ext_virt
18350 #undef THUMB_VARIANT
18351 #define THUMB_VARIANT & arm_ext_virt
18353 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18354 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18357 #define ARM_VARIANT & arm_ext_v6t2
18358 #undef THUMB_VARIANT
18359 #define THUMB_VARIANT & arm_ext_v6t2
18361 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18362 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18363 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18364 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18366 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18367 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18368 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18369 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18371 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18372 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18373 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18374 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18376 /* Thumb-only instructions. */
18378 #define ARM_VARIANT NULL
18379 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18380 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18382 /* ARM does not really have an IT instruction, so always allow it.
18383 The opcode is copied from Thumb in order to allow warnings in
18384 -mimplicit-it=[never | arm] modes. */
18386 #define ARM_VARIANT & arm_ext_v1
18388 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18389 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18390 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18391 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18392 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18393 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18394 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18395 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18396 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18397 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18398 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18399 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18400 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18401 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18402 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18403 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18404 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18405 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18407 /* Thumb2 only instructions. */
18409 #define ARM_VARIANT NULL
18411 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18412 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18413 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18414 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18415 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18416 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18418 /* Hardware division instructions. */
18420 #define ARM_VARIANT & arm_ext_adiv
18421 #undef THUMB_VARIANT
18422 #define THUMB_VARIANT & arm_ext_div
18424 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18425 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18427 /* ARM V6M/V7 instructions. */
18429 #define ARM_VARIANT & arm_ext_barrier
18430 #undef THUMB_VARIANT
18431 #define THUMB_VARIANT & arm_ext_barrier
18433 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18434 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18435 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18437 /* ARM V7 instructions. */
18439 #define ARM_VARIANT & arm_ext_v7
18440 #undef THUMB_VARIANT
18441 #define THUMB_VARIANT & arm_ext_v7
18443 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18444 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18447 #define ARM_VARIANT & arm_ext_mp
18448 #undef THUMB_VARIANT
18449 #define THUMB_VARIANT & arm_ext_mp
18451 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18453 /* AArchv8 instructions. */
18455 #define ARM_VARIANT & arm_ext_v8
18456 #undef THUMB_VARIANT
18457 #define THUMB_VARIANT & arm_ext_v8
18459 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18460 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18461 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18462 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18464 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18465 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18466 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18468 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18470 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18472 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18474 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18475 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18476 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18477 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18478 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18479 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18481 /* ARMv8 T32 only. */
18483 #define ARM_VARIANT NULL
18484 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18485 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18486 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18488 /* FP for ARMv8. */
18490 #define ARM_VARIANT & fpu_vfp_ext_armv8
18491 #undef THUMB_VARIANT
18492 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18494 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18495 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18496 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18497 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18498 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18499 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18500 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18501 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18502 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18503 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18504 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18505 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18506 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18507 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18508 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18509 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18510 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18512 /* Crypto v1 extensions. */
18514 #define ARM_VARIANT & fpu_crypto_ext_armv8
18515 #undef THUMB_VARIANT
18516 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18518 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18519 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18520 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18521 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18522 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18523 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18524 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18525 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18526 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18527 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18528 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18529 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18530 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18531 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18534 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18535 #undef THUMB_VARIANT
18536 #define THUMB_VARIANT NULL
18538 cCE("wfs", e200110, 1, (RR), rd),
18539 cCE("rfs", e300110, 1, (RR), rd),
18540 cCE("wfc", e400110, 1, (RR), rd),
18541 cCE("rfc", e500110, 1, (RR), rd),
18543 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18544 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18545 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18546 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18548 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18549 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18550 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18551 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18553 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18554 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18555 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18556 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18557 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18558 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18559 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18560 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18561 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18562 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18563 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18564 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18566 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18567 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18568 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18569 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18570 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18571 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18572 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18573 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18574 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18575 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18576 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18577 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18579 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18580 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18581 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18582 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18583 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18584 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18585 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18586 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18587 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18588 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18589 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18590 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18592 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18593 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18594 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18595 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18596 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18597 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18598 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18599 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18600 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18601 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18602 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18603 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18605 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18606 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18607 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18608 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18609 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18610 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18611 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18612 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18613 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18614 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18615 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18616 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18618 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18619 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18620 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18621 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18622 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18623 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18624 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18625 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18626 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18627 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18628 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18629 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18631 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18632 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18633 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18634 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18635 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18636 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18637 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18638 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18639 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18640 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18641 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18642 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18644 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18645 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18646 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18647 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18648 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18649 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18650 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18651 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18652 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18653 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18654 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18655 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18657 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18658 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18659 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18660 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18661 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18662 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18663 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18664 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18665 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18666 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18667 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18668 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18670 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18671 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18672 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18673 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18674 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18675 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18676 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18677 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18678 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18679 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18680 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18681 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18683 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18684 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18685 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18686 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18687 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18688 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18689 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18690 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18691 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18692 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18693 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18694 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18696 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18697 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18698 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18699 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18700 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18701 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18702 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18703 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18704 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18705 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18706 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18707 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18709 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18710 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18711 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18712 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18713 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18714 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18715 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18716 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18717 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18718 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18719 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18720 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18722 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18723 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18724 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18725 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18726 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18727 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18728 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18729 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18730 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18731 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18732 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18733 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18735 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18736 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18737 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18738 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18739 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18740 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18741 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18742 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18743 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18744 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18745 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18746 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18748 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18749 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18750 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18751 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18752 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18753 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18754 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18755 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18756 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18757 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18758 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18759 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18761 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18762 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18763 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18764 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18765 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18766 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18767 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18768 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18769 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18770 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18771 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18772 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18774 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18775 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18776 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18777 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18778 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18779 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18780 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18781 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18782 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18783 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18784 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18785 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18787 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18788 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18789 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18790 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18791 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18792 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18793 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18794 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18795 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18796 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18797 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18798 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18800 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18801 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18802 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18803 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18804 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18805 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18806 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18807 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18808 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18809 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18810 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18811 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18813 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18814 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18815 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18816 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18817 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18818 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18819 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18820 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18821 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18822 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18823 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18824 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18826 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18827 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18828 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18829 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18830 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18831 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18832 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18833 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18834 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18835 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18836 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18837 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18839 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18840 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18841 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18842 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18843 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18844 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18845 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18846 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18847 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18848 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18849 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18850 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18852 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18857 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18858 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18859 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18863 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18865 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18931 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18932 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18933 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18935 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18936 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18937 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18938 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18939 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18940 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18941 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18942 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18943 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18944 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18945 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18946 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18948 /* The implementation of the FIX instruction is broken on some
18949 assemblers, in that it accepts a precision specifier as well as a
18950 rounding specifier, despite the fact that this is meaningless.
18951 To be more compatible, we accept it as well, though of course it
18952 does not set any bits. */
18953 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18954 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18955 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18956 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18957 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18958 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18959 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18960 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18961 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18962 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18963 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18964 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18965 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18967 /* Instructions that were new with the real FPA, call them V2. */
18969 #define ARM_VARIANT & fpu_fpa_ext_v2
18971 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18972 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18973 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18974 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18975 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18976 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18979 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18981 /* Moves and type conversions. */
18982 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18983 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18984 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18985 cCE("fmstat", ef1fa10, 0, (), noargs),
18986 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18987 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18988 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18989 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18990 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18991 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18992 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18993 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18994 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18995 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18997 /* Memory operations. */
18998 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18999 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19000 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19001 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19002 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19003 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19004 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19005 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19006 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19007 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19008 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19009 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19010 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19011 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19012 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19013 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19014 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19015 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19017 /* Monadic operations. */
19018 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19019 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19020 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19022 /* Dyadic operations. */
19023 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19024 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19025 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19026 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19027 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19028 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19029 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19030 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19031 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19034 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19035 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19036 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19037 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19039 /* Double precision load/store are still present on single precision
19040 implementations. */
19041 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19042 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19043 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19044 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19045 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19046 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19047 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19048 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19049 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19050 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19053 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19055 /* Moves and type conversions. */
19056 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19057 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19058 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19059 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19060 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19061 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19062 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19063 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19064 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19065 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19066 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19067 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19068 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19070 /* Monadic operations. */
19071 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19072 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19073 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19075 /* Dyadic operations. */
19076 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19077 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19078 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19079 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19080 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19081 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19082 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19083 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19084 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19087 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19088 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19089 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19090 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19093 #define ARM_VARIANT & fpu_vfp_ext_v2
19095 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19096 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19097 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19098 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19100 /* Instructions which may belong to either the Neon or VFP instruction sets.
19101 Individual encoder functions perform additional architecture checks. */
19103 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19104 #undef THUMB_VARIANT
19105 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19107 /* These mnemonics are unique to VFP. */
19108 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19109 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19110 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19111 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19112 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19113 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19114 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19115 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19116 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19117 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19119 /* Mnemonics shared by Neon and VFP. */
19120 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19121 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19122 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19124 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19125 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19127 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19128 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19130 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19131 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19132 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19133 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19134 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19135 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19136 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19137 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19139 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19140 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19141 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19142 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19145 /* NOTE: All VMOV encoding is special-cased! */
19146 NCE(vmov, 0, 1, (VMOV), neon_mov),
19147 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19149 #undef THUMB_VARIANT
19150 #define THUMB_VARIANT & fpu_neon_ext_v1
19152 #define ARM_VARIANT & fpu_neon_ext_v1
19154 /* Data processing with three registers of the same length. */
19155 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19156 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19157 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19158 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19159 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19160 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19161 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19162 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19163 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19164 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19165 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19166 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19167 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19168 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19169 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19170 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19171 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19172 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19173 /* If not immediate, fall back to neon_dyadic_i64_su.
19174 shl_imm should accept I8 I16 I32 I64,
19175 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19176 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19177 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19178 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19179 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19180 /* Logic ops, types optional & ignored. */
19181 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19182 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19183 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19184 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19185 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19186 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19187 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19188 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19189 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19190 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19191 /* Bitfield ops, untyped. */
19192 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19193 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19194 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19195 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19196 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19197 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19198 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19199 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19200 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19201 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19202 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19203 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19204 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19205 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19206 back to neon_dyadic_if_su. */
19207 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19208 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19209 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19210 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19211 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19212 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19213 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19214 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19215 /* Comparison. Type I8 I16 I32 F32. */
19216 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19217 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19218 /* As above, D registers only. */
19219 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19220 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19221 /* Int and float variants, signedness unimportant. */
19222 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19223 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19224 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19225 /* Add/sub take types I8 I16 I32 I64 F32. */
19226 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19227 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19228 /* vtst takes sizes 8, 16, 32. */
19229 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19230 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19231 /* VMUL takes I8 I16 I32 F32 P8. */
19232 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19233 /* VQD{R}MULH takes S16 S32. */
19234 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19235 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19236 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19237 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19238 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19239 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19240 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19241 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19242 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19243 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19244 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19245 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19246 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19247 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19248 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19249 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19251 /* Two address, int/float. Types S8 S16 S32 F32. */
19252 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19253 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19255 /* Data processing with two registers and a shift amount. */
19256 /* Right shifts, and variants with rounding.
19257 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19258 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19259 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19260 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19261 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19262 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19263 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19264 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19265 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19266 /* Shift and insert. Sizes accepted 8 16 32 64. */
19267 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19268 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19269 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19270 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19271 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19272 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19273 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19274 /* Right shift immediate, saturating & narrowing, with rounding variants.
19275 Types accepted S16 S32 S64 U16 U32 U64. */
19276 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19277 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19278 /* As above, unsigned. Types accepted S16 S32 S64. */
19279 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19280 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19281 /* Right shift narrowing. Types accepted I16 I32 I64. */
19282 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19283 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19284 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19285 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19286 /* CVT with optional immediate for fixed-point variant. */
19287 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19289 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19290 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19292 /* Data processing, three registers of different lengths. */
19293 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19294 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19295 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19296 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19297 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19298 /* If not scalar, fall back to neon_dyadic_long.
19299 Vector types as above, scalar types S16 S32 U16 U32. */
19300 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19301 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19302 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19303 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19304 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19305 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19306 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19307 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19308 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19309 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19310 /* Saturating doubling multiplies. Types S16 S32. */
19311 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19312 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19313 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19314 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19315 S16 S32 U16 U32. */
19316 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19318 /* Extract. Size 8. */
19319 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19320 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19322 /* Two registers, miscellaneous. */
19323 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19324 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19325 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19326 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19327 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19328 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19329 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19330 /* Vector replicate. Sizes 8 16 32. */
19331 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19332 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19333 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19334 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19335 /* VMOVN. Types I16 I32 I64. */
19336 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19337 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19338 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19339 /* VQMOVUN. Types S16 S32 S64. */
19340 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19341 /* VZIP / VUZP. Sizes 8 16 32. */
19342 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19343 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19344 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19345 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19346 /* VQABS / VQNEG. Types S8 S16 S32. */
19347 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19348 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19349 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19350 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19351 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19352 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19353 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19354 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19355 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19356 /* Reciprocal estimates. Types U32 F32. */
19357 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19358 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19359 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19360 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19361 /* VCLS. Types S8 S16 S32. */
19362 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19363 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19364 /* VCLZ. Types I8 I16 I32. */
19365 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19366 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19367 /* VCNT. Size 8. */
19368 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19369 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19370 /* Two address, untyped. */
19371 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19372 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19373 /* VTRN. Sizes 8 16 32. */
19374 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19375 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19377 /* Table lookup. Size 8. */
19378 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19379 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19381 #undef THUMB_VARIANT
19382 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19384 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19386 /* Neon element/structure load/store. */
19387 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19388 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19389 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19390 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19391 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19392 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19393 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19394 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19396 #undef THUMB_VARIANT
19397 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19399 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19400 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19401 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19402 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19403 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19404 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19405 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19406 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19407 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19408 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19410 #undef THUMB_VARIANT
19411 #define THUMB_VARIANT & fpu_vfp_ext_v3
19413 #define ARM_VARIANT & fpu_vfp_ext_v3
19415 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19416 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19417 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19418 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19419 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19420 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19421 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19422 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19423 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19426 #define ARM_VARIANT &fpu_vfp_ext_fma
19427 #undef THUMB_VARIANT
19428 #define THUMB_VARIANT &fpu_vfp_ext_fma
19429 /* Mnemonics shared by Neon and VFP. These are included in the
19430 VFP FMA variant; NEON and VFP FMA always includes the NEON
19431 FMA instructions. */
19432 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19433 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19434 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19435 the v form should always be used. */
19436 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19437 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19438 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19439 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19440 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19441 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19443 #undef THUMB_VARIANT
19445 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19447 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19448 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19449 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19450 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19451 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19452 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19453 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19454 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19457 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19459 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19460 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19461 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19462 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19463 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19464 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19465 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19466 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19467 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19468 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19469 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19470 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19471 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19472 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19473 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19474 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19475 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19476 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19477 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19478 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19479 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19480 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19481 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19482 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19483 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19484 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19485 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19486 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19487 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19488 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19489 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19490 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19491 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19492 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19493 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19494 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19495 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19496 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19497 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19498 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19499 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19500 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19501 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19502 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19503 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19504 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19505 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19506 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19507 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19508 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19509 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19510 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19511 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19512 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19513 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19514 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19515 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19516 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19517 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19518 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19519 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19520 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19521 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19522 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19523 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19524 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19525 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19526 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19527 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19528 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19529 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19530 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19531 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19532 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19533 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19534 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19535 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19536 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19537 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19538 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19539 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19540 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19541 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19542 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19543 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19544 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19545 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19546 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19547 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19548 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19549 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19550 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19551 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19552 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19553 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19554 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19555 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19556 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19557 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19558 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19559 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19560 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19561 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19562 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19563 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19564 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19565 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19566 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19567 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19568 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19569 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19570 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19571 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19572 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19573 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19574 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19575 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19576 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19577 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19578 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19579 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19580 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19581 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19582 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19583 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19584 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19585 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19586 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19587 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19588 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19589 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19590 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19591 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19592 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19593 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19597 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19598 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19599 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19600 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19601 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19602 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19603 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19604 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19605 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19606 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19607 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19611 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19612 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19613 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19614 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19615 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19616 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19623 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19625 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19626 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19627 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19628 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19629 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19630 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19631 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19641 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19642 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19643 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19644 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19646 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19651 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19652 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19653 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19654 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19655 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19656 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19666 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19667 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19668 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19669 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19670 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19671 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19675 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19676 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19677 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19678 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19679 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19680 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19681 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19684 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19686 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19687 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19688 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19689 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19690 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19691 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19692 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19693 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19694 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19695 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19696 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19697 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19698 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19699 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19700 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19701 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19702 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19703 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19704 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19705 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19706 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19707 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19708 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19709 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19710 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19711 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19712 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19713 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19714 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19715 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19716 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19717 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19718 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19719 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19720 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19721 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19722 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19723 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19724 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19725 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19726 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19727 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19728 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19729 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19730 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19731 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19732 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19733 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19734 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19735 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19736 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19737 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19738 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19739 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19740 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19741 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19742 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19743 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19744 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19745 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19746 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19747 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19748 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19749 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19750 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19751 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19752 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19753 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19754 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19755 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19756 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19757 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19758 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19759 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19760 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19761 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19764 #undef THUMB_VARIANT
19790 /* MD interface: bits in the object file. */
19792 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19793 for use in the a.out file, and stores them in the array pointed to by buf.
19794 This knows about the endian-ness of the target machine and does
19795 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19796 2 (short) and 4 (long) Floating numbers are put out as a series of
19797 LITTLENUMS (shorts, here at least). */
19800 md_number_to_chars (char * buf, valueT val, int n)
19802 if (target_big_endian)
19803 number_to_chars_bigendian (buf, val, n);
19805 number_to_chars_littleendian (buf, val, n);
19809 md_chars_to_number (char * buf, int n)
19812 unsigned char * where = (unsigned char *) buf;
19814 if (target_big_endian)
19819 result |= (*where++ & 255);
19827 result |= (where[n] & 255);
19834 /* MD interface: Sections. */
19836 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19837 that an rs_machine_dependent frag may reach. */
19840 arm_frag_max_var (fragS *fragp)
19842 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19843 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19845 Note that we generate relaxable instructions even for cases that don't
19846 really need it, like an immediate that's a trivial constant. So we're
19847 overestimating the instruction size for some of those cases. Rather
19848 than putting more intelligence here, it would probably be better to
19849 avoid generating a relaxation frag in the first place when it can be
19850 determined up front that a short instruction will suffice. */
19852 gas_assert (fragp->fr_type == rs_machine_dependent);
19856 /* Estimate the size of a frag before relaxing. Assume everything fits in
19860 md_estimate_size_before_relax (fragS * fragp,
19861 segT segtype ATTRIBUTE_UNUSED)
19867 /* Convert a machine dependent frag. */
19870 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19872 unsigned long insn;
19873 unsigned long old_op;
19881 buf = fragp->fr_literal + fragp->fr_fix;
19883 old_op = bfd_get_16(abfd, buf);
19884 if (fragp->fr_symbol)
19886 exp.X_op = O_symbol;
19887 exp.X_add_symbol = fragp->fr_symbol;
19891 exp.X_op = O_constant;
19893 exp.X_add_number = fragp->fr_offset;
19894 opcode = fragp->fr_subtype;
19897 case T_MNEM_ldr_pc:
19898 case T_MNEM_ldr_pc2:
19899 case T_MNEM_ldr_sp:
19900 case T_MNEM_str_sp:
19907 if (fragp->fr_var == 4)
19909 insn = THUMB_OP32 (opcode);
19910 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19912 insn |= (old_op & 0x700) << 4;
19916 insn |= (old_op & 7) << 12;
19917 insn |= (old_op & 0x38) << 13;
19919 insn |= 0x00000c00;
19920 put_thumb32_insn (buf, insn);
19921 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19925 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19927 pc_rel = (opcode == T_MNEM_ldr_pc2);
19930 if (fragp->fr_var == 4)
19932 insn = THUMB_OP32 (opcode);
19933 insn |= (old_op & 0xf0) << 4;
19934 put_thumb32_insn (buf, insn);
19935 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19939 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19940 exp.X_add_number -= 4;
19948 if (fragp->fr_var == 4)
19950 int r0off = (opcode == T_MNEM_mov
19951 || opcode == T_MNEM_movs) ? 0 : 8;
19952 insn = THUMB_OP32 (opcode);
19953 insn = (insn & 0xe1ffffff) | 0x10000000;
19954 insn |= (old_op & 0x700) << r0off;
19955 put_thumb32_insn (buf, insn);
19956 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19960 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19965 if (fragp->fr_var == 4)
19967 insn = THUMB_OP32(opcode);
19968 put_thumb32_insn (buf, insn);
19969 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19972 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19976 if (fragp->fr_var == 4)
19978 insn = THUMB_OP32(opcode);
19979 insn |= (old_op & 0xf00) << 14;
19980 put_thumb32_insn (buf, insn);
19981 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19984 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19987 case T_MNEM_add_sp:
19988 case T_MNEM_add_pc:
19989 case T_MNEM_inc_sp:
19990 case T_MNEM_dec_sp:
19991 if (fragp->fr_var == 4)
19993 /* ??? Choose between add and addw. */
19994 insn = THUMB_OP32 (opcode);
19995 insn |= (old_op & 0xf0) << 4;
19996 put_thumb32_insn (buf, insn);
19997 if (opcode == T_MNEM_add_pc)
19998 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20000 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20003 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20011 if (fragp->fr_var == 4)
20013 insn = THUMB_OP32 (opcode);
20014 insn |= (old_op & 0xf0) << 4;
20015 insn |= (old_op & 0xf) << 16;
20016 put_thumb32_insn (buf, insn);
20017 if (insn & (1 << 20))
20018 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20020 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20023 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20029 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20030 (enum bfd_reloc_code_real) reloc_type);
20031 fixp->fx_file = fragp->fr_file;
20032 fixp->fx_line = fragp->fr_line;
20033 fragp->fr_fix += fragp->fr_var;
20036 /* Return the size of a relaxable immediate operand instruction.
20037 SHIFT and SIZE specify the form of the allowable immediate. */
20039 relax_immediate (fragS *fragp, int size, int shift)
20045 /* ??? Should be able to do better than this. */
20046 if (fragp->fr_symbol)
20049 low = (1 << shift) - 1;
20050 mask = (1 << (shift + size)) - (1 << shift);
20051 offset = fragp->fr_offset;
20052 /* Force misaligned offsets to 32-bit variant. */
20055 if (offset & ~mask)
20060 /* Get the address of a symbol during relaxation. */
20062 relaxed_symbol_addr (fragS *fragp, long stretch)
20068 sym = fragp->fr_symbol;
20069 sym_frag = symbol_get_frag (sym);
20070 know (S_GET_SEGMENT (sym) != absolute_section
20071 || sym_frag == &zero_address_frag);
20072 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20074 /* If frag has yet to be reached on this pass, assume it will
20075 move by STRETCH just as we did. If this is not so, it will
20076 be because some frag between grows, and that will force
20080 && sym_frag->relax_marker != fragp->relax_marker)
20084 /* Adjust stretch for any alignment frag. Note that if have
20085 been expanding the earlier code, the symbol may be
20086 defined in what appears to be an earlier frag. FIXME:
20087 This doesn't handle the fr_subtype field, which specifies
20088 a maximum number of bytes to skip when doing an
20090 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20092 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20095 stretch = - ((- stretch)
20096 & ~ ((1 << (int) f->fr_offset) - 1));
20098 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20110 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20113 relax_adr (fragS *fragp, asection *sec, long stretch)
20118 /* Assume worst case for symbols not known to be in the same section. */
20119 if (fragp->fr_symbol == NULL
20120 || !S_IS_DEFINED (fragp->fr_symbol)
20121 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20122 || S_IS_WEAK (fragp->fr_symbol))
20125 val = relaxed_symbol_addr (fragp, stretch);
20126 addr = fragp->fr_address + fragp->fr_fix;
20127 addr = (addr + 4) & ~3;
20128 /* Force misaligned targets to 32-bit variant. */
20132 if (val < 0 || val > 1020)
20137 /* Return the size of a relaxable add/sub immediate instruction. */
20139 relax_addsub (fragS *fragp, asection *sec)
20144 buf = fragp->fr_literal + fragp->fr_fix;
20145 op = bfd_get_16(sec->owner, buf);
20146 if ((op & 0xf) == ((op >> 4) & 0xf))
20147 return relax_immediate (fragp, 8, 0);
20149 return relax_immediate (fragp, 3, 0);
20153 /* Return the size of a relaxable branch instruction. BITS is the
20154 size of the offset field in the narrow instruction. */
20157 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20163 /* Assume worst case for symbols not known to be in the same section. */
20164 if (!S_IS_DEFINED (fragp->fr_symbol)
20165 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20166 || S_IS_WEAK (fragp->fr_symbol))
20170 if (S_IS_DEFINED (fragp->fr_symbol)
20171 && ARM_IS_FUNC (fragp->fr_symbol))
20174 /* PR 12532. Global symbols with default visibility might
20175 be preempted, so do not relax relocations to them. */
20176 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
20177 && (! S_IS_LOCAL (fragp->fr_symbol)))
20181 val = relaxed_symbol_addr (fragp, stretch);
20182 addr = fragp->fr_address + fragp->fr_fix + 4;
20185 /* Offset is a signed value *2 */
20187 if (val >= limit || val < -limit)
20193 /* Relax a machine dependent frag. This returns the amount by which
20194 the current size of the frag should change. */
20197 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20202 oldsize = fragp->fr_var;
20203 switch (fragp->fr_subtype)
20205 case T_MNEM_ldr_pc2:
20206 newsize = relax_adr (fragp, sec, stretch);
20208 case T_MNEM_ldr_pc:
20209 case T_MNEM_ldr_sp:
20210 case T_MNEM_str_sp:
20211 newsize = relax_immediate (fragp, 8, 2);
20215 newsize = relax_immediate (fragp, 5, 2);
20219 newsize = relax_immediate (fragp, 5, 1);
20223 newsize = relax_immediate (fragp, 5, 0);
20226 newsize = relax_adr (fragp, sec, stretch);
20232 newsize = relax_immediate (fragp, 8, 0);
20235 newsize = relax_branch (fragp, sec, 11, stretch);
20238 newsize = relax_branch (fragp, sec, 8, stretch);
20240 case T_MNEM_add_sp:
20241 case T_MNEM_add_pc:
20242 newsize = relax_immediate (fragp, 8, 2);
20244 case T_MNEM_inc_sp:
20245 case T_MNEM_dec_sp:
20246 newsize = relax_immediate (fragp, 7, 2);
20252 newsize = relax_addsub (fragp, sec);
20258 fragp->fr_var = newsize;
20259 /* Freeze wide instructions that are at or before the same location as
20260 in the previous pass. This avoids infinite loops.
20261 Don't freeze them unconditionally because targets may be artificially
20262 misaligned by the expansion of preceding frags. */
20263 if (stretch <= 0 && newsize > 2)
20265 md_convert_frag (sec->owner, sec, fragp);
20269 return newsize - oldsize;
20272 /* Round up a section size to the appropriate boundary. */
20275 md_section_align (segT segment ATTRIBUTE_UNUSED,
20278 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20279 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20281 /* For a.out, force the section size to be aligned. If we don't do
20282 this, BFD will align it for us, but it will not write out the
20283 final bytes of the section. This may be a bug in BFD, but it is
20284 easier to fix it here since that is how the other a.out targets
20288 align = bfd_get_section_alignment (stdoutput, segment);
20289 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20296 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20297 of an rs_align_code fragment. */
20300 arm_handle_align (fragS * fragP)
20302 static char const arm_noop[2][2][4] =
20305 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20306 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20309 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20310 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20313 static char const thumb_noop[2][2][2] =
20316 {0xc0, 0x46}, /* LE */
20317 {0x46, 0xc0}, /* BE */
20320 {0x00, 0xbf}, /* LE */
20321 {0xbf, 0x00} /* BE */
20324 static char const wide_thumb_noop[2][4] =
20325 { /* Wide Thumb-2 */
20326 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20327 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20330 unsigned bytes, fix, noop_size;
20333 const char *narrow_noop = NULL;
20338 if (fragP->fr_type != rs_align_code)
20341 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20342 p = fragP->fr_literal + fragP->fr_fix;
20345 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20346 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20348 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20350 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20352 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20354 narrow_noop = thumb_noop[1][target_big_endian];
20355 noop = wide_thumb_noop[target_big_endian];
20358 noop = thumb_noop[0][target_big_endian];
20366 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20367 [target_big_endian];
20374 fragP->fr_var = noop_size;
20376 if (bytes & (noop_size - 1))
20378 fix = bytes & (noop_size - 1);
20380 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20382 memset (p, 0, fix);
20389 if (bytes & noop_size)
20391 /* Insert a narrow noop. */
20392 memcpy (p, narrow_noop, noop_size);
20394 bytes -= noop_size;
20398 /* Use wide noops for the remainder */
20402 while (bytes >= noop_size)
20404 memcpy (p, noop, noop_size);
20406 bytes -= noop_size;
20410 fragP->fr_fix += fix;
20413 /* Called from md_do_align. Used to create an alignment
20414 frag in a code section. */
20417 arm_frag_align_code (int n, int max)
20421 /* We assume that there will never be a requirement
20422 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20423 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20428 _("alignments greater than %d bytes not supported in .text sections."),
20429 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20430 as_fatal ("%s", err_msg);
20433 p = frag_var (rs_align_code,
20434 MAX_MEM_FOR_RS_ALIGN_CODE,
20436 (relax_substateT) max,
20443 /* Perform target specific initialisation of a frag.
20444 Note - despite the name this initialisation is not done when the frag
20445 is created, but only when its type is assigned. A frag can be created
20446 and used a long time before its type is set, so beware of assuming that
20447 this initialisationis performed first. */
20451 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20453 /* Record whether this frag is in an ARM or a THUMB area. */
20454 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20457 #else /* OBJ_ELF is defined. */
20459 arm_init_frag (fragS * fragP, int max_chars)
20461 /* If the current ARM vs THUMB mode has not already
20462 been recorded into this frag then do so now. */
20463 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20465 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20467 /* Record a mapping symbol for alignment frags. We will delete this
20468 later if the alignment ends up empty. */
20469 switch (fragP->fr_type)
20472 case rs_align_test:
20474 mapping_state_2 (MAP_DATA, max_chars);
20476 case rs_align_code:
20477 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20485 /* When we change sections we need to issue a new mapping symbol. */
20488 arm_elf_change_section (void)
20490 /* Link an unlinked unwind index table section to the .text section. */
20491 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20492 && elf_linked_to_section (now_seg) == NULL)
20493 elf_linked_to_section (now_seg) = text_section;
20497 arm_elf_section_type (const char * str, size_t len)
20499 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20500 return SHT_ARM_EXIDX;
20505 /* Code to deal with unwinding tables. */
20507 static void add_unwind_adjustsp (offsetT);
20509 /* Generate any deferred unwind frame offset. */
20512 flush_pending_unwind (void)
20516 offset = unwind.pending_offset;
20517 unwind.pending_offset = 0;
20519 add_unwind_adjustsp (offset);
20522 /* Add an opcode to this list for this function. Two-byte opcodes should
20523 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20527 add_unwind_opcode (valueT op, int length)
20529 /* Add any deferred stack adjustment. */
20530 if (unwind.pending_offset)
20531 flush_pending_unwind ();
20533 unwind.sp_restored = 0;
20535 if (unwind.opcode_count + length > unwind.opcode_alloc)
20537 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20538 if (unwind.opcodes)
20539 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20540 unwind.opcode_alloc);
20542 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20547 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20549 unwind.opcode_count++;
20553 /* Add unwind opcodes to adjust the stack pointer. */
20556 add_unwind_adjustsp (offsetT offset)
20560 if (offset > 0x200)
20562 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20567 /* Long form: 0xb2, uleb128. */
20568 /* This might not fit in a word so add the individual bytes,
20569 remembering the list is built in reverse order. */
20570 o = (valueT) ((offset - 0x204) >> 2);
20572 add_unwind_opcode (0, 1);
20574 /* Calculate the uleb128 encoding of the offset. */
20578 bytes[n] = o & 0x7f;
20584 /* Add the insn. */
20586 add_unwind_opcode (bytes[n - 1], 1);
20587 add_unwind_opcode (0xb2, 1);
20589 else if (offset > 0x100)
20591 /* Two short opcodes. */
20592 add_unwind_opcode (0x3f, 1);
20593 op = (offset - 0x104) >> 2;
20594 add_unwind_opcode (op, 1);
20596 else if (offset > 0)
20598 /* Short opcode. */
20599 op = (offset - 4) >> 2;
20600 add_unwind_opcode (op, 1);
20602 else if (offset < 0)
20605 while (offset > 0x100)
20607 add_unwind_opcode (0x7f, 1);
20610 op = ((offset - 4) >> 2) | 0x40;
20611 add_unwind_opcode (op, 1);
20615 /* Finish the list of unwind opcodes for this function. */
20617 finish_unwind_opcodes (void)
20621 if (unwind.fp_used)
20623 /* Adjust sp as necessary. */
20624 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20625 flush_pending_unwind ();
20627 /* After restoring sp from the frame pointer. */
20628 op = 0x90 | unwind.fp_reg;
20629 add_unwind_opcode (op, 1);
20632 flush_pending_unwind ();
20636 /* Start an exception table entry. If idx is nonzero this is an index table
20640 start_unwind_section (const segT text_seg, int idx)
20642 const char * text_name;
20643 const char * prefix;
20644 const char * prefix_once;
20645 const char * group_name;
20649 size_t sec_name_len;
20656 prefix = ELF_STRING_ARM_unwind;
20657 prefix_once = ELF_STRING_ARM_unwind_once;
20658 type = SHT_ARM_EXIDX;
20662 prefix = ELF_STRING_ARM_unwind_info;
20663 prefix_once = ELF_STRING_ARM_unwind_info_once;
20664 type = SHT_PROGBITS;
20667 text_name = segment_name (text_seg);
20668 if (streq (text_name, ".text"))
20671 if (strncmp (text_name, ".gnu.linkonce.t.",
20672 strlen (".gnu.linkonce.t.")) == 0)
20674 prefix = prefix_once;
20675 text_name += strlen (".gnu.linkonce.t.");
20678 prefix_len = strlen (prefix);
20679 text_len = strlen (text_name);
20680 sec_name_len = prefix_len + text_len;
20681 sec_name = (char *) xmalloc (sec_name_len + 1);
20682 memcpy (sec_name, prefix, prefix_len);
20683 memcpy (sec_name + prefix_len, text_name, text_len);
20684 sec_name[prefix_len + text_len] = '\0';
20690 /* Handle COMDAT group. */
20691 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20693 group_name = elf_group_name (text_seg);
20694 if (group_name == NULL)
20696 as_bad (_("Group section `%s' has no group signature"),
20697 segment_name (text_seg));
20698 ignore_rest_of_line ();
20701 flags |= SHF_GROUP;
20705 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20707 /* Set the section link for index tables. */
20709 elf_linked_to_section (now_seg) = text_seg;
20713 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20714 personality routine data. Returns zero, or the index table value for
20715 and inline entry. */
20718 create_unwind_entry (int have_data)
20723 /* The current word of data. */
20725 /* The number of bytes left in this word. */
20728 finish_unwind_opcodes ();
20730 /* Remember the current text section. */
20731 unwind.saved_seg = now_seg;
20732 unwind.saved_subseg = now_subseg;
20734 start_unwind_section (now_seg, 0);
20736 if (unwind.personality_routine == NULL)
20738 if (unwind.personality_index == -2)
20741 as_bad (_("handlerdata in cantunwind frame"));
20742 return 1; /* EXIDX_CANTUNWIND. */
20745 /* Use a default personality routine if none is specified. */
20746 if (unwind.personality_index == -1)
20748 if (unwind.opcode_count > 3)
20749 unwind.personality_index = 1;
20751 unwind.personality_index = 0;
20754 /* Space for the personality routine entry. */
20755 if (unwind.personality_index == 0)
20757 if (unwind.opcode_count > 3)
20758 as_bad (_("too many unwind opcodes for personality routine 0"));
20762 /* All the data is inline in the index table. */
20765 while (unwind.opcode_count > 0)
20767 unwind.opcode_count--;
20768 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20772 /* Pad with "finish" opcodes. */
20774 data = (data << 8) | 0xb0;
20781 /* We get two opcodes "free" in the first word. */
20782 size = unwind.opcode_count - 2;
20786 gas_assert (unwind.personality_index == -1);
20788 /* An extra byte is required for the opcode count. */
20789 size = unwind.opcode_count + 1;
20792 size = (size + 3) >> 2;
20794 as_bad (_("too many unwind opcodes"));
20796 frag_align (2, 0, 0);
20797 record_alignment (now_seg, 2);
20798 unwind.table_entry = expr_build_dot ();
20800 /* Allocate the table entry. */
20801 ptr = frag_more ((size << 2) + 4);
20802 /* PR 13449: Zero the table entries in case some of them are not used. */
20803 memset (ptr, 0, (size << 2) + 4);
20804 where = frag_now_fix () - ((size << 2) + 4);
20806 switch (unwind.personality_index)
20809 /* ??? Should this be a PLT generating relocation? */
20810 /* Custom personality routine. */
20811 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20812 BFD_RELOC_ARM_PREL31);
20817 /* Set the first byte to the number of additional words. */
20818 data = size > 0 ? size - 1 : 0;
20822 /* ABI defined personality routines. */
20824 /* Three opcodes bytes are packed into the first word. */
20831 /* The size and first two opcode bytes go in the first word. */
20832 data = ((0x80 + unwind.personality_index) << 8) | size;
20837 /* Should never happen. */
20841 /* Pack the opcodes into words (MSB first), reversing the list at the same
20843 while (unwind.opcode_count > 0)
20847 md_number_to_chars (ptr, data, 4);
20852 unwind.opcode_count--;
20854 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20857 /* Finish off the last word. */
20860 /* Pad with "finish" opcodes. */
20862 data = (data << 8) | 0xb0;
20864 md_number_to_chars (ptr, data, 4);
20869 /* Add an empty descriptor if there is no user-specified data. */
20870 ptr = frag_more (4);
20871 md_number_to_chars (ptr, 0, 4);
20878 /* Initialize the DWARF-2 unwind information for this procedure. */
20881 tc_arm_frame_initial_instructions (void)
20883 cfi_add_CFA_def_cfa (REG_SP, 0);
20885 #endif /* OBJ_ELF */
20887 /* Convert REGNAME to a DWARF-2 register number. */
20890 tc_arm_regname_to_dw2regnum (char *regname)
20892 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20902 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20906 exp.X_op = O_secrel;
20907 exp.X_add_symbol = symbol;
20908 exp.X_add_number = 0;
20909 emit_expr (&exp, size);
20913 /* MD interface: Symbol and relocation handling. */
20915 /* Return the address within the segment that a PC-relative fixup is
20916 relative to. For ARM, PC-relative fixups applied to instructions
20917 are generally relative to the location of the fixup plus 8 bytes.
20918 Thumb branches are offset by 4, and Thumb loads relative to PC
20919 require special handling. */
20922 md_pcrel_from_section (fixS * fixP, segT seg)
20924 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20926 /* If this is pc-relative and we are going to emit a relocation
20927 then we just want to put out any pipeline compensation that the linker
20928 will need. Otherwise we want to use the calculated base.
20929 For WinCE we skip the bias for externals as well, since this
20930 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20932 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20933 || (arm_force_relocation (fixP)
20935 && !S_IS_EXTERNAL (fixP->fx_addsy)
20941 switch (fixP->fx_r_type)
20943 /* PC relative addressing on the Thumb is slightly odd as the
20944 bottom two bits of the PC are forced to zero for the
20945 calculation. This happens *after* application of the
20946 pipeline offset. However, Thumb adrl already adjusts for
20947 this, so we need not do it again. */
20948 case BFD_RELOC_ARM_THUMB_ADD:
20951 case BFD_RELOC_ARM_THUMB_OFFSET:
20952 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20953 case BFD_RELOC_ARM_T32_ADD_PC12:
20954 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20955 return (base + 4) & ~3;
20957 /* Thumb branches are simply offset by +4. */
20958 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20959 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20960 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20961 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20962 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20965 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20967 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20968 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20969 && ARM_IS_FUNC (fixP->fx_addsy)
20970 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20971 base = fixP->fx_where + fixP->fx_frag->fr_address;
20974 /* BLX is like branches above, but forces the low two bits of PC to
20976 case BFD_RELOC_THUMB_PCREL_BLX:
20978 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20979 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20980 && THUMB_IS_FUNC (fixP->fx_addsy)
20981 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20982 base = fixP->fx_where + fixP->fx_frag->fr_address;
20983 return (base + 4) & ~3;
20985 /* ARM mode branches are offset by +8. However, the Windows CE
20986 loader expects the relocation not to take this into account. */
20987 case BFD_RELOC_ARM_PCREL_BLX:
20989 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20990 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20991 && ARM_IS_FUNC (fixP->fx_addsy)
20992 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20993 base = fixP->fx_where + fixP->fx_frag->fr_address;
20996 case BFD_RELOC_ARM_PCREL_CALL:
20998 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20999 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21000 && THUMB_IS_FUNC (fixP->fx_addsy)
21001 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21002 base = fixP->fx_where + fixP->fx_frag->fr_address;
21005 case BFD_RELOC_ARM_PCREL_BRANCH:
21006 case BFD_RELOC_ARM_PCREL_JUMP:
21007 case BFD_RELOC_ARM_PLT32:
21009 /* When handling fixups immediately, because we have already
21010 discovered the value of a symbol, or the address of the frag involved
21011 we must account for the offset by +8, as the OS loader will never see the reloc.
21012 see fixup_segment() in write.c
21013 The S_IS_EXTERNAL test handles the case of global symbols.
21014 Those need the calculated base, not just the pipe compensation the linker will need. */
21016 && fixP->fx_addsy != NULL
21017 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21018 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21026 /* ARM mode loads relative to PC are also offset by +8. Unlike
21027 branches, the Windows CE loader *does* expect the relocation
21028 to take this into account. */
21029 case BFD_RELOC_ARM_OFFSET_IMM:
21030 case BFD_RELOC_ARM_OFFSET_IMM8:
21031 case BFD_RELOC_ARM_HWLITERAL:
21032 case BFD_RELOC_ARM_LITERAL:
21033 case BFD_RELOC_ARM_CP_OFF_IMM:
21037 /* Other PC-relative relocations are un-offset. */
21043 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21044 Otherwise we have no need to default values of symbols. */
21047 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21050 if (name[0] == '_' && name[1] == 'G'
21051 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21055 if (symbol_find (name))
21056 as_bad (_("GOT already in the symbol table"));
21058 GOT_symbol = symbol_new (name, undefined_section,
21059 (valueT) 0, & zero_address_frag);
21069 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21070 computed as two separate immediate values, added together. We
21071 already know that this value cannot be computed by just one ARM
21074 static unsigned int
21075 validate_immediate_twopart (unsigned int val,
21076 unsigned int * highpart)
21081 for (i = 0; i < 32; i += 2)
21082 if (((a = rotate_left (val, i)) & 0xff) != 0)
21088 * highpart = (a >> 8) | ((i + 24) << 7);
21090 else if (a & 0xff0000)
21092 if (a & 0xff000000)
21094 * highpart = (a >> 16) | ((i + 16) << 7);
21098 gas_assert (a & 0xff000000);
21099 * highpart = (a >> 24) | ((i + 8) << 7);
21102 return (a & 0xff) | (i << 7);
21109 validate_offset_imm (unsigned int val, int hwse)
21111 if ((hwse && val > 255) || val > 4095)
21116 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21117 negative immediate constant by altering the instruction. A bit of
21122 by inverting the second operand, and
21125 by negating the second operand. */
21128 negate_data_op (unsigned long * instruction,
21129 unsigned long value)
21132 unsigned long negated, inverted;
21134 negated = encode_arm_immediate (-value);
21135 inverted = encode_arm_immediate (~value);
21137 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21140 /* First negates. */
21141 case OPCODE_SUB: /* ADD <-> SUB */
21142 new_inst = OPCODE_ADD;
21147 new_inst = OPCODE_SUB;
21151 case OPCODE_CMP: /* CMP <-> CMN */
21152 new_inst = OPCODE_CMN;
21157 new_inst = OPCODE_CMP;
21161 /* Now Inverted ops. */
21162 case OPCODE_MOV: /* MOV <-> MVN */
21163 new_inst = OPCODE_MVN;
21168 new_inst = OPCODE_MOV;
21172 case OPCODE_AND: /* AND <-> BIC */
21173 new_inst = OPCODE_BIC;
21178 new_inst = OPCODE_AND;
21182 case OPCODE_ADC: /* ADC <-> SBC */
21183 new_inst = OPCODE_SBC;
21188 new_inst = OPCODE_ADC;
21192 /* We cannot do anything. */
21197 if (value == (unsigned) FAIL)
21200 *instruction &= OPCODE_MASK;
21201 *instruction |= new_inst << DATA_OP_SHIFT;
21205 /* Like negate_data_op, but for Thumb-2. */
21207 static unsigned int
21208 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21212 unsigned int negated, inverted;
21214 negated = encode_thumb32_immediate (-value);
21215 inverted = encode_thumb32_immediate (~value);
21217 rd = (*instruction >> 8) & 0xf;
21218 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21221 /* ADD <-> SUB. Includes CMP <-> CMN. */
21222 case T2_OPCODE_SUB:
21223 new_inst = T2_OPCODE_ADD;
21227 case T2_OPCODE_ADD:
21228 new_inst = T2_OPCODE_SUB;
21232 /* ORR <-> ORN. Includes MOV <-> MVN. */
21233 case T2_OPCODE_ORR:
21234 new_inst = T2_OPCODE_ORN;
21238 case T2_OPCODE_ORN:
21239 new_inst = T2_OPCODE_ORR;
21243 /* AND <-> BIC. TST has no inverted equivalent. */
21244 case T2_OPCODE_AND:
21245 new_inst = T2_OPCODE_BIC;
21252 case T2_OPCODE_BIC:
21253 new_inst = T2_OPCODE_AND;
21258 case T2_OPCODE_ADC:
21259 new_inst = T2_OPCODE_SBC;
21263 case T2_OPCODE_SBC:
21264 new_inst = T2_OPCODE_ADC;
21268 /* We cannot do anything. */
21273 if (value == (unsigned int)FAIL)
21276 *instruction &= T2_OPCODE_MASK;
21277 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21281 /* Read a 32-bit thumb instruction from buf. */
21282 static unsigned long
21283 get_thumb32_insn (char * buf)
21285 unsigned long insn;
21286 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21287 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21293 /* We usually want to set the low bit on the address of thumb function
21294 symbols. In particular .word foo - . should have the low bit set.
21295 Generic code tries to fold the difference of two symbols to
21296 a constant. Prevent this and force a relocation when the first symbols
21297 is a thumb function. */
21300 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21302 if (op == O_subtract
21303 && l->X_op == O_symbol
21304 && r->X_op == O_symbol
21305 && THUMB_IS_FUNC (l->X_add_symbol))
21307 l->X_op = O_subtract;
21308 l->X_op_symbol = r->X_add_symbol;
21309 l->X_add_number -= r->X_add_number;
21313 /* Process as normal. */
21317 /* Encode Thumb2 unconditional branches and calls. The encoding
21318 for the 2 are identical for the immediate values. */
21321 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21323 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21326 addressT S, I1, I2, lo, hi;
21328 S = (value >> 24) & 0x01;
21329 I1 = (value >> 23) & 0x01;
21330 I2 = (value >> 22) & 0x01;
21331 hi = (value >> 12) & 0x3ff;
21332 lo = (value >> 1) & 0x7ff;
21333 newval = md_chars_to_number (buf, THUMB_SIZE);
21334 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21335 newval |= (S << 10) | hi;
21336 newval2 &= ~T2I1I2MASK;
21337 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21338 md_number_to_chars (buf, newval, THUMB_SIZE);
21339 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21343 md_apply_fix (fixS * fixP,
21347 offsetT value = * valP;
21349 unsigned int newimm;
21350 unsigned long temp;
21352 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21354 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21356 /* Note whether this will delete the relocation. */
21358 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21361 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21362 consistency with the behaviour on 32-bit hosts. Remember value
21364 value &= 0xffffffff;
21365 value ^= 0x80000000;
21366 value -= 0x80000000;
21369 fixP->fx_addnumber = value;
21371 /* Same treatment for fixP->fx_offset. */
21372 fixP->fx_offset &= 0xffffffff;
21373 fixP->fx_offset ^= 0x80000000;
21374 fixP->fx_offset -= 0x80000000;
21376 switch (fixP->fx_r_type)
21378 case BFD_RELOC_NONE:
21379 /* This will need to go in the object file. */
21383 case BFD_RELOC_ARM_IMMEDIATE:
21384 /* We claim that this fixup has been processed here,
21385 even if in fact we generate an error because we do
21386 not have a reloc for it, so tc_gen_reloc will reject it. */
21389 if (fixP->fx_addsy)
21391 const char *msg = 0;
21393 if (! S_IS_DEFINED (fixP->fx_addsy))
21394 msg = _("undefined symbol %s used as an immediate value");
21395 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21396 msg = _("symbol %s is in a different section");
21397 else if (S_IS_WEAK (fixP->fx_addsy))
21398 msg = _("symbol %s is weak and may be overridden later");
21402 as_bad_where (fixP->fx_file, fixP->fx_line,
21403 msg, S_GET_NAME (fixP->fx_addsy));
21408 temp = md_chars_to_number (buf, INSN_SIZE);
21410 /* If the offset is negative, we should use encoding A2 for ADR. */
21411 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21412 newimm = negate_data_op (&temp, value);
21415 newimm = encode_arm_immediate (value);
21417 /* If the instruction will fail, see if we can fix things up by
21418 changing the opcode. */
21419 if (newimm == (unsigned int) FAIL)
21420 newimm = negate_data_op (&temp, value);
21423 if (newimm == (unsigned int) FAIL)
21425 as_bad_where (fixP->fx_file, fixP->fx_line,
21426 _("invalid constant (%lx) after fixup"),
21427 (unsigned long) value);
21431 newimm |= (temp & 0xfffff000);
21432 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21435 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21437 unsigned int highpart = 0;
21438 unsigned int newinsn = 0xe1a00000; /* nop. */
21440 if (fixP->fx_addsy)
21442 const char *msg = 0;
21444 if (! S_IS_DEFINED (fixP->fx_addsy))
21445 msg = _("undefined symbol %s used as an immediate value");
21446 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21447 msg = _("symbol %s is in a different section");
21448 else if (S_IS_WEAK (fixP->fx_addsy))
21449 msg = _("symbol %s is weak and may be overridden later");
21453 as_bad_where (fixP->fx_file, fixP->fx_line,
21454 msg, S_GET_NAME (fixP->fx_addsy));
21459 newimm = encode_arm_immediate (value);
21460 temp = md_chars_to_number (buf, INSN_SIZE);
21462 /* If the instruction will fail, see if we can fix things up by
21463 changing the opcode. */
21464 if (newimm == (unsigned int) FAIL
21465 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21467 /* No ? OK - try using two ADD instructions to generate
21469 newimm = validate_immediate_twopart (value, & highpart);
21471 /* Yes - then make sure that the second instruction is
21473 if (newimm != (unsigned int) FAIL)
21475 /* Still No ? Try using a negated value. */
21476 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21477 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21478 /* Otherwise - give up. */
21481 as_bad_where (fixP->fx_file, fixP->fx_line,
21482 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21487 /* Replace the first operand in the 2nd instruction (which
21488 is the PC) with the destination register. We have
21489 already added in the PC in the first instruction and we
21490 do not want to do it again. */
21491 newinsn &= ~ 0xf0000;
21492 newinsn |= ((newinsn & 0x0f000) << 4);
21495 newimm |= (temp & 0xfffff000);
21496 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21498 highpart |= (newinsn & 0xfffff000);
21499 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21503 case BFD_RELOC_ARM_OFFSET_IMM:
21504 if (!fixP->fx_done && seg->use_rela_p)
21507 case BFD_RELOC_ARM_LITERAL:
21513 if (validate_offset_imm (value, 0) == FAIL)
21515 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21516 as_bad_where (fixP->fx_file, fixP->fx_line,
21517 _("invalid literal constant: pool needs to be closer"));
21519 as_bad_where (fixP->fx_file, fixP->fx_line,
21520 _("bad immediate value for offset (%ld)"),
21525 newval = md_chars_to_number (buf, INSN_SIZE);
21527 newval &= 0xfffff000;
21530 newval &= 0xff7ff000;
21531 newval |= value | (sign ? INDEX_UP : 0);
21533 md_number_to_chars (buf, newval, INSN_SIZE);
21536 case BFD_RELOC_ARM_OFFSET_IMM8:
21537 case BFD_RELOC_ARM_HWLITERAL:
21543 if (validate_offset_imm (value, 1) == FAIL)
21545 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21546 as_bad_where (fixP->fx_file, fixP->fx_line,
21547 _("invalid literal constant: pool needs to be closer"));
21549 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
21554 newval = md_chars_to_number (buf, INSN_SIZE);
21556 newval &= 0xfffff0f0;
21559 newval &= 0xff7ff0f0;
21560 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21562 md_number_to_chars (buf, newval, INSN_SIZE);
21565 case BFD_RELOC_ARM_T32_OFFSET_U8:
21566 if (value < 0 || value > 1020 || value % 4 != 0)
21567 as_bad_where (fixP->fx_file, fixP->fx_line,
21568 _("bad immediate value for offset (%ld)"), (long) value);
21571 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21573 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21576 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21577 /* This is a complicated relocation used for all varieties of Thumb32
21578 load/store instruction with immediate offset:
21580 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21581 *4, optional writeback(W)
21582 (doubleword load/store)
21584 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21585 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21586 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21587 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21588 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21590 Uppercase letters indicate bits that are already encoded at
21591 this point. Lowercase letters are our problem. For the
21592 second block of instructions, the secondary opcode nybble
21593 (bits 8..11) is present, and bit 23 is zero, even if this is
21594 a PC-relative operation. */
21595 newval = md_chars_to_number (buf, THUMB_SIZE);
21597 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21599 if ((newval & 0xf0000000) == 0xe0000000)
21601 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21603 newval |= (1 << 23);
21606 if (value % 4 != 0)
21608 as_bad_where (fixP->fx_file, fixP->fx_line,
21609 _("offset not a multiple of 4"));
21615 as_bad_where (fixP->fx_file, fixP->fx_line,
21616 _("offset out of range"));
21621 else if ((newval & 0x000f0000) == 0x000f0000)
21623 /* PC-relative, 12-bit offset. */
21625 newval |= (1 << 23);
21630 as_bad_where (fixP->fx_file, fixP->fx_line,
21631 _("offset out of range"));
21636 else if ((newval & 0x00000100) == 0x00000100)
21638 /* Writeback: 8-bit, +/- offset. */
21640 newval |= (1 << 9);
21645 as_bad_where (fixP->fx_file, fixP->fx_line,
21646 _("offset out of range"));
21651 else if ((newval & 0x00000f00) == 0x00000e00)
21653 /* T-instruction: positive 8-bit offset. */
21654 if (value < 0 || value > 0xff)
21656 as_bad_where (fixP->fx_file, fixP->fx_line,
21657 _("offset out of range"));
21665 /* Positive 12-bit or negative 8-bit offset. */
21669 newval |= (1 << 23);
21679 as_bad_where (fixP->fx_file, fixP->fx_line,
21680 _("offset out of range"));
21687 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21688 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21691 case BFD_RELOC_ARM_SHIFT_IMM:
21692 newval = md_chars_to_number (buf, INSN_SIZE);
21693 if (((unsigned long) value) > 32
21695 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21697 as_bad_where (fixP->fx_file, fixP->fx_line,
21698 _("shift expression is too large"));
21703 /* Shifts of zero must be done as lsl. */
21705 else if (value == 32)
21707 newval &= 0xfffff07f;
21708 newval |= (value & 0x1f) << 7;
21709 md_number_to_chars (buf, newval, INSN_SIZE);
21712 case BFD_RELOC_ARM_T32_IMMEDIATE:
21713 case BFD_RELOC_ARM_T32_ADD_IMM:
21714 case BFD_RELOC_ARM_T32_IMM12:
21715 case BFD_RELOC_ARM_T32_ADD_PC12:
21716 /* We claim that this fixup has been processed here,
21717 even if in fact we generate an error because we do
21718 not have a reloc for it, so tc_gen_reloc will reject it. */
21722 && ! S_IS_DEFINED (fixP->fx_addsy))
21724 as_bad_where (fixP->fx_file, fixP->fx_line,
21725 _("undefined symbol %s used as an immediate value"),
21726 S_GET_NAME (fixP->fx_addsy));
21730 newval = md_chars_to_number (buf, THUMB_SIZE);
21732 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21735 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21736 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21738 newimm = encode_thumb32_immediate (value);
21739 if (newimm == (unsigned int) FAIL)
21740 newimm = thumb32_negate_data_op (&newval, value);
21742 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21743 && newimm == (unsigned int) FAIL)
21745 /* Turn add/sum into addw/subw. */
21746 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21747 newval = (newval & 0xfeffffff) | 0x02000000;
21748 /* No flat 12-bit imm encoding for addsw/subsw. */
21749 if ((newval & 0x00100000) == 0)
21751 /* 12 bit immediate for addw/subw. */
21755 newval ^= 0x00a00000;
21758 newimm = (unsigned int) FAIL;
21764 if (newimm == (unsigned int)FAIL)
21766 as_bad_where (fixP->fx_file, fixP->fx_line,
21767 _("invalid constant (%lx) after fixup"),
21768 (unsigned long) value);
21772 newval |= (newimm & 0x800) << 15;
21773 newval |= (newimm & 0x700) << 4;
21774 newval |= (newimm & 0x0ff);
21776 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21777 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21780 case BFD_RELOC_ARM_SMC:
21781 if (((unsigned long) value) > 0xffff)
21782 as_bad_where (fixP->fx_file, fixP->fx_line,
21783 _("invalid smc expression"));
21784 newval = md_chars_to_number (buf, INSN_SIZE);
21785 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21786 md_number_to_chars (buf, newval, INSN_SIZE);
21789 case BFD_RELOC_ARM_HVC:
21790 if (((unsigned long) value) > 0xffff)
21791 as_bad_where (fixP->fx_file, fixP->fx_line,
21792 _("invalid hvc expression"));
21793 newval = md_chars_to_number (buf, INSN_SIZE);
21794 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21795 md_number_to_chars (buf, newval, INSN_SIZE);
21798 case BFD_RELOC_ARM_SWI:
21799 if (fixP->tc_fix_data != 0)
21801 if (((unsigned long) value) > 0xff)
21802 as_bad_where (fixP->fx_file, fixP->fx_line,
21803 _("invalid swi expression"));
21804 newval = md_chars_to_number (buf, THUMB_SIZE);
21806 md_number_to_chars (buf, newval, THUMB_SIZE);
21810 if (((unsigned long) value) > 0x00ffffff)
21811 as_bad_where (fixP->fx_file, fixP->fx_line,
21812 _("invalid swi expression"));
21813 newval = md_chars_to_number (buf, INSN_SIZE);
21815 md_number_to_chars (buf, newval, INSN_SIZE);
21819 case BFD_RELOC_ARM_MULTI:
21820 if (((unsigned long) value) > 0xffff)
21821 as_bad_where (fixP->fx_file, fixP->fx_line,
21822 _("invalid expression in load/store multiple"));
21823 newval = value | md_chars_to_number (buf, INSN_SIZE);
21824 md_number_to_chars (buf, newval, INSN_SIZE);
21828 case BFD_RELOC_ARM_PCREL_CALL:
21830 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21832 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21833 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21834 && THUMB_IS_FUNC (fixP->fx_addsy))
21835 /* Flip the bl to blx. This is a simple flip
21836 bit here because we generate PCREL_CALL for
21837 unconditional bls. */
21839 newval = md_chars_to_number (buf, INSN_SIZE);
21840 newval = newval | 0x10000000;
21841 md_number_to_chars (buf, newval, INSN_SIZE);
21847 goto arm_branch_common;
21849 case BFD_RELOC_ARM_PCREL_JUMP:
21850 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21852 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21853 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21854 && THUMB_IS_FUNC (fixP->fx_addsy))
21856 /* This would map to a bl<cond>, b<cond>,
21857 b<always> to a Thumb function. We
21858 need to force a relocation for this particular
21860 newval = md_chars_to_number (buf, INSN_SIZE);
21864 case BFD_RELOC_ARM_PLT32:
21866 case BFD_RELOC_ARM_PCREL_BRANCH:
21868 goto arm_branch_common;
21870 case BFD_RELOC_ARM_PCREL_BLX:
21873 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21875 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21876 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21877 && ARM_IS_FUNC (fixP->fx_addsy))
21879 /* Flip the blx to a bl and warn. */
21880 const char *name = S_GET_NAME (fixP->fx_addsy);
21881 newval = 0xeb000000;
21882 as_warn_where (fixP->fx_file, fixP->fx_line,
21883 _("blx to '%s' an ARM ISA state function changed to bl"),
21885 md_number_to_chars (buf, newval, INSN_SIZE);
21891 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21892 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21896 /* We are going to store value (shifted right by two) in the
21897 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21898 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21899 also be be clear. */
21901 as_bad_where (fixP->fx_file, fixP->fx_line,
21902 _("misaligned branch destination"));
21903 if ((value & (offsetT)0xfe000000) != (offsetT)0
21904 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21905 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21907 if (fixP->fx_done || !seg->use_rela_p)
21909 newval = md_chars_to_number (buf, INSN_SIZE);
21910 newval |= (value >> 2) & 0x00ffffff;
21911 /* Set the H bit on BLX instructions. */
21915 newval |= 0x01000000;
21917 newval &= ~0x01000000;
21919 md_number_to_chars (buf, newval, INSN_SIZE);
21923 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21924 /* CBZ can only branch forward. */
21926 /* Attempts to use CBZ to branch to the next instruction
21927 (which, strictly speaking, are prohibited) will be turned into
21930 FIXME: It may be better to remove the instruction completely and
21931 perform relaxation. */
21934 newval = md_chars_to_number (buf, THUMB_SIZE);
21935 newval = 0xbf00; /* NOP encoding T1 */
21936 md_number_to_chars (buf, newval, THUMB_SIZE);
21941 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21943 if (fixP->fx_done || !seg->use_rela_p)
21945 newval = md_chars_to_number (buf, THUMB_SIZE);
21946 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21947 md_number_to_chars (buf, newval, THUMB_SIZE);
21952 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21953 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21954 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21956 if (fixP->fx_done || !seg->use_rela_p)
21958 newval = md_chars_to_number (buf, THUMB_SIZE);
21959 newval |= (value & 0x1ff) >> 1;
21960 md_number_to_chars (buf, newval, THUMB_SIZE);
21964 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21965 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21966 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21968 if (fixP->fx_done || !seg->use_rela_p)
21970 newval = md_chars_to_number (buf, THUMB_SIZE);
21971 newval |= (value & 0xfff) >> 1;
21972 md_number_to_chars (buf, newval, THUMB_SIZE);
21976 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21978 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21979 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21980 && ARM_IS_FUNC (fixP->fx_addsy)
21981 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21983 /* Force a relocation for a branch 20 bits wide. */
21986 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21987 as_bad_where (fixP->fx_file, fixP->fx_line,
21988 _("conditional branch out of range"));
21990 if (fixP->fx_done || !seg->use_rela_p)
21993 addressT S, J1, J2, lo, hi;
21995 S = (value & 0x00100000) >> 20;
21996 J2 = (value & 0x00080000) >> 19;
21997 J1 = (value & 0x00040000) >> 18;
21998 hi = (value & 0x0003f000) >> 12;
21999 lo = (value & 0x00000ffe) >> 1;
22001 newval = md_chars_to_number (buf, THUMB_SIZE);
22002 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22003 newval |= (S << 10) | hi;
22004 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22005 md_number_to_chars (buf, newval, THUMB_SIZE);
22006 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22010 case BFD_RELOC_THUMB_PCREL_BLX:
22011 /* If there is a blx from a thumb state function to
22012 another thumb function flip this to a bl and warn
22016 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22017 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22018 && THUMB_IS_FUNC (fixP->fx_addsy))
22020 const char *name = S_GET_NAME (fixP->fx_addsy);
22021 as_warn_where (fixP->fx_file, fixP->fx_line,
22022 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22024 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22025 newval = newval | 0x1000;
22026 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22027 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22032 goto thumb_bl_common;
22034 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22035 /* A bl from Thumb state ISA to an internal ARM state function
22036 is converted to a blx. */
22038 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22039 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22040 && ARM_IS_FUNC (fixP->fx_addsy)
22041 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22043 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22044 newval = newval & ~0x1000;
22045 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22046 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22052 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22053 /* For a BLX instruction, make sure that the relocation is rounded up
22054 to a word boundary. This follows the semantics of the instruction
22055 which specifies that bit 1 of the target address will come from bit
22056 1 of the base address. */
22057 value = (value + 3) & ~ 3;
22060 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22061 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22062 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22065 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22067 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22068 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22069 else if ((value & ~0x1ffffff)
22070 && ((value & ~0x1ffffff) != ~0x1ffffff))
22071 as_bad_where (fixP->fx_file, fixP->fx_line,
22072 _("Thumb2 branch out of range"));
22075 if (fixP->fx_done || !seg->use_rela_p)
22076 encode_thumb2_b_bl_offset (buf, value);
22080 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22081 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22082 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22084 if (fixP->fx_done || !seg->use_rela_p)
22085 encode_thumb2_b_bl_offset (buf, value);
22090 if (fixP->fx_done || !seg->use_rela_p)
22091 md_number_to_chars (buf, value, 1);
22095 if (fixP->fx_done || !seg->use_rela_p)
22096 md_number_to_chars (buf, value, 2);
22100 case BFD_RELOC_ARM_TLS_CALL:
22101 case BFD_RELOC_ARM_THM_TLS_CALL:
22102 case BFD_RELOC_ARM_TLS_DESCSEQ:
22103 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22104 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22107 case BFD_RELOC_ARM_TLS_GOTDESC:
22108 case BFD_RELOC_ARM_TLS_GD32:
22109 case BFD_RELOC_ARM_TLS_LE32:
22110 case BFD_RELOC_ARM_TLS_IE32:
22111 case BFD_RELOC_ARM_TLS_LDM32:
22112 case BFD_RELOC_ARM_TLS_LDO32:
22113 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22116 case BFD_RELOC_ARM_GOT32:
22117 case BFD_RELOC_ARM_GOTOFF:
22118 if (fixP->fx_done || !seg->use_rela_p)
22119 md_number_to_chars (buf, 0, 4);
22122 case BFD_RELOC_ARM_GOT_PREL:
22123 if (fixP->fx_done || !seg->use_rela_p)
22124 md_number_to_chars (buf, value, 4);
22127 case BFD_RELOC_ARM_TARGET2:
22128 /* TARGET2 is not partial-inplace, so we need to write the
22129 addend here for REL targets, because it won't be written out
22130 during reloc processing later. */
22131 if (fixP->fx_done || !seg->use_rela_p)
22132 md_number_to_chars (buf, fixP->fx_offset, 4);
22136 case BFD_RELOC_RVA:
22138 case BFD_RELOC_ARM_TARGET1:
22139 case BFD_RELOC_ARM_ROSEGREL32:
22140 case BFD_RELOC_ARM_SBREL32:
22141 case BFD_RELOC_32_PCREL:
22143 case BFD_RELOC_32_SECREL:
22145 if (fixP->fx_done || !seg->use_rela_p)
22147 /* For WinCE we only do this for pcrel fixups. */
22148 if (fixP->fx_done || fixP->fx_pcrel)
22150 md_number_to_chars (buf, value, 4);
22154 case BFD_RELOC_ARM_PREL31:
22155 if (fixP->fx_done || !seg->use_rela_p)
22157 newval = md_chars_to_number (buf, 4) & 0x80000000;
22158 if ((value ^ (value >> 1)) & 0x40000000)
22160 as_bad_where (fixP->fx_file, fixP->fx_line,
22161 _("rel31 relocation overflow"));
22163 newval |= value & 0x7fffffff;
22164 md_number_to_chars (buf, newval, 4);
22169 case BFD_RELOC_ARM_CP_OFF_IMM:
22170 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22171 if (value < -1023 || value > 1023 || (value & 3))
22172 as_bad_where (fixP->fx_file, fixP->fx_line,
22173 _("co-processor offset out of range"));
22178 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22179 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22180 newval = md_chars_to_number (buf, INSN_SIZE);
22182 newval = get_thumb32_insn (buf);
22184 newval &= 0xffffff00;
22187 newval &= 0xff7fff00;
22188 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22190 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22191 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22192 md_number_to_chars (buf, newval, INSN_SIZE);
22194 put_thumb32_insn (buf, newval);
22197 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22198 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22199 if (value < -255 || value > 255)
22200 as_bad_where (fixP->fx_file, fixP->fx_line,
22201 _("co-processor offset out of range"));
22203 goto cp_off_common;
22205 case BFD_RELOC_ARM_THUMB_OFFSET:
22206 newval = md_chars_to_number (buf, THUMB_SIZE);
22207 /* Exactly what ranges, and where the offset is inserted depends
22208 on the type of instruction, we can establish this from the
22210 switch (newval >> 12)
22212 case 4: /* PC load. */
22213 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22214 forced to zero for these loads; md_pcrel_from has already
22215 compensated for this. */
22217 as_bad_where (fixP->fx_file, fixP->fx_line,
22218 _("invalid offset, target not word aligned (0x%08lX)"),
22219 (((unsigned long) fixP->fx_frag->fr_address
22220 + (unsigned long) fixP->fx_where) & ~3)
22221 + (unsigned long) value);
22223 if (value & ~0x3fc)
22224 as_bad_where (fixP->fx_file, fixP->fx_line,
22225 _("invalid offset, value too big (0x%08lX)"),
22228 newval |= value >> 2;
22231 case 9: /* SP load/store. */
22232 if (value & ~0x3fc)
22233 as_bad_where (fixP->fx_file, fixP->fx_line,
22234 _("invalid offset, value too big (0x%08lX)"),
22236 newval |= value >> 2;
22239 case 6: /* Word load/store. */
22241 as_bad_where (fixP->fx_file, fixP->fx_line,
22242 _("invalid offset, value too big (0x%08lX)"),
22244 newval |= value << 4; /* 6 - 2. */
22247 case 7: /* Byte load/store. */
22249 as_bad_where (fixP->fx_file, fixP->fx_line,
22250 _("invalid offset, value too big (0x%08lX)"),
22252 newval |= value << 6;
22255 case 8: /* Halfword load/store. */
22257 as_bad_where (fixP->fx_file, fixP->fx_line,
22258 _("invalid offset, value too big (0x%08lX)"),
22260 newval |= value << 5; /* 6 - 1. */
22264 as_bad_where (fixP->fx_file, fixP->fx_line,
22265 "Unable to process relocation for thumb opcode: %lx",
22266 (unsigned long) newval);
22269 md_number_to_chars (buf, newval, THUMB_SIZE);
22272 case BFD_RELOC_ARM_THUMB_ADD:
22273 /* This is a complicated relocation, since we use it for all of
22274 the following immediate relocations:
22278 9bit ADD/SUB SP word-aligned
22279 10bit ADD PC/SP word-aligned
22281 The type of instruction being processed is encoded in the
22288 newval = md_chars_to_number (buf, THUMB_SIZE);
22290 int rd = (newval >> 4) & 0xf;
22291 int rs = newval & 0xf;
22292 int subtract = !!(newval & 0x8000);
22294 /* Check for HI regs, only very restricted cases allowed:
22295 Adjusting SP, and using PC or SP to get an address. */
22296 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22297 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22298 as_bad_where (fixP->fx_file, fixP->fx_line,
22299 _("invalid Hi register with immediate"));
22301 /* If value is negative, choose the opposite instruction. */
22305 subtract = !subtract;
22307 as_bad_where (fixP->fx_file, fixP->fx_line,
22308 _("immediate value out of range"));
22313 if (value & ~0x1fc)
22314 as_bad_where (fixP->fx_file, fixP->fx_line,
22315 _("invalid immediate for stack address calculation"));
22316 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22317 newval |= value >> 2;
22319 else if (rs == REG_PC || rs == REG_SP)
22321 if (subtract || value & ~0x3fc)
22322 as_bad_where (fixP->fx_file, fixP->fx_line,
22323 _("invalid immediate for address calculation (value = 0x%08lX)"),
22324 (unsigned long) value);
22325 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22327 newval |= value >> 2;
22332 as_bad_where (fixP->fx_file, fixP->fx_line,
22333 _("immediate value out of range"));
22334 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22335 newval |= (rd << 8) | value;
22340 as_bad_where (fixP->fx_file, fixP->fx_line,
22341 _("immediate value out of range"));
22342 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22343 newval |= rd | (rs << 3) | (value << 6);
22346 md_number_to_chars (buf, newval, THUMB_SIZE);
22349 case BFD_RELOC_ARM_THUMB_IMM:
22350 newval = md_chars_to_number (buf, THUMB_SIZE);
22351 if (value < 0 || value > 255)
22352 as_bad_where (fixP->fx_file, fixP->fx_line,
22353 _("invalid immediate: %ld is out of range"),
22356 md_number_to_chars (buf, newval, THUMB_SIZE);
22359 case BFD_RELOC_ARM_THUMB_SHIFT:
22360 /* 5bit shift value (0..32). LSL cannot take 32. */
22361 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22362 temp = newval & 0xf800;
22363 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22364 as_bad_where (fixP->fx_file, fixP->fx_line,
22365 _("invalid shift value: %ld"), (long) value);
22366 /* Shifts of zero must be encoded as LSL. */
22368 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22369 /* Shifts of 32 are encoded as zero. */
22370 else if (value == 32)
22372 newval |= value << 6;
22373 md_number_to_chars (buf, newval, THUMB_SIZE);
22376 case BFD_RELOC_VTABLE_INHERIT:
22377 case BFD_RELOC_VTABLE_ENTRY:
22381 case BFD_RELOC_ARM_MOVW:
22382 case BFD_RELOC_ARM_MOVT:
22383 case BFD_RELOC_ARM_THUMB_MOVW:
22384 case BFD_RELOC_ARM_THUMB_MOVT:
22385 if (fixP->fx_done || !seg->use_rela_p)
22387 /* REL format relocations are limited to a 16-bit addend. */
22388 if (!fixP->fx_done)
22390 if (value < -0x8000 || value > 0x7fff)
22391 as_bad_where (fixP->fx_file, fixP->fx_line,
22392 _("offset out of range"));
22394 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22395 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22400 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22401 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22403 newval = get_thumb32_insn (buf);
22404 newval &= 0xfbf08f00;
22405 newval |= (value & 0xf000) << 4;
22406 newval |= (value & 0x0800) << 15;
22407 newval |= (value & 0x0700) << 4;
22408 newval |= (value & 0x00ff);
22409 put_thumb32_insn (buf, newval);
22413 newval = md_chars_to_number (buf, 4);
22414 newval &= 0xfff0f000;
22415 newval |= value & 0x0fff;
22416 newval |= (value & 0xf000) << 4;
22417 md_number_to_chars (buf, newval, 4);
22422 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22423 case BFD_RELOC_ARM_ALU_PC_G0:
22424 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22425 case BFD_RELOC_ARM_ALU_PC_G1:
22426 case BFD_RELOC_ARM_ALU_PC_G2:
22427 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22428 case BFD_RELOC_ARM_ALU_SB_G0:
22429 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22430 case BFD_RELOC_ARM_ALU_SB_G1:
22431 case BFD_RELOC_ARM_ALU_SB_G2:
22432 gas_assert (!fixP->fx_done);
22433 if (!seg->use_rela_p)
22436 bfd_vma encoded_addend;
22437 bfd_vma addend_abs = abs (value);
22439 /* Check that the absolute value of the addend can be
22440 expressed as an 8-bit constant plus a rotation. */
22441 encoded_addend = encode_arm_immediate (addend_abs);
22442 if (encoded_addend == (unsigned int) FAIL)
22443 as_bad_where (fixP->fx_file, fixP->fx_line,
22444 _("the offset 0x%08lX is not representable"),
22445 (unsigned long) addend_abs);
22447 /* Extract the instruction. */
22448 insn = md_chars_to_number (buf, INSN_SIZE);
22450 /* If the addend is positive, use an ADD instruction.
22451 Otherwise use a SUB. Take care not to destroy the S bit. */
22452 insn &= 0xff1fffff;
22458 /* Place the encoded addend into the first 12 bits of the
22460 insn &= 0xfffff000;
22461 insn |= encoded_addend;
22463 /* Update the instruction. */
22464 md_number_to_chars (buf, insn, INSN_SIZE);
22468 case BFD_RELOC_ARM_LDR_PC_G0:
22469 case BFD_RELOC_ARM_LDR_PC_G1:
22470 case BFD_RELOC_ARM_LDR_PC_G2:
22471 case BFD_RELOC_ARM_LDR_SB_G0:
22472 case BFD_RELOC_ARM_LDR_SB_G1:
22473 case BFD_RELOC_ARM_LDR_SB_G2:
22474 gas_assert (!fixP->fx_done);
22475 if (!seg->use_rela_p)
22478 bfd_vma addend_abs = abs (value);
22480 /* Check that the absolute value of the addend can be
22481 encoded in 12 bits. */
22482 if (addend_abs >= 0x1000)
22483 as_bad_where (fixP->fx_file, fixP->fx_line,
22484 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22485 (unsigned long) addend_abs);
22487 /* Extract the instruction. */
22488 insn = md_chars_to_number (buf, INSN_SIZE);
22490 /* If the addend is negative, clear bit 23 of the instruction.
22491 Otherwise set it. */
22493 insn &= ~(1 << 23);
22497 /* Place the absolute value of the addend into the first 12 bits
22498 of the instruction. */
22499 insn &= 0xfffff000;
22500 insn |= addend_abs;
22502 /* Update the instruction. */
22503 md_number_to_chars (buf, insn, INSN_SIZE);
22507 case BFD_RELOC_ARM_LDRS_PC_G0:
22508 case BFD_RELOC_ARM_LDRS_PC_G1:
22509 case BFD_RELOC_ARM_LDRS_PC_G2:
22510 case BFD_RELOC_ARM_LDRS_SB_G0:
22511 case BFD_RELOC_ARM_LDRS_SB_G1:
22512 case BFD_RELOC_ARM_LDRS_SB_G2:
22513 gas_assert (!fixP->fx_done);
22514 if (!seg->use_rela_p)
22517 bfd_vma addend_abs = abs (value);
22519 /* Check that the absolute value of the addend can be
22520 encoded in 8 bits. */
22521 if (addend_abs >= 0x100)
22522 as_bad_where (fixP->fx_file, fixP->fx_line,
22523 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22524 (unsigned long) addend_abs);
22526 /* Extract the instruction. */
22527 insn = md_chars_to_number (buf, INSN_SIZE);
22529 /* If the addend is negative, clear bit 23 of the instruction.
22530 Otherwise set it. */
22532 insn &= ~(1 << 23);
22536 /* Place the first four bits of the absolute value of the addend
22537 into the first 4 bits of the instruction, and the remaining
22538 four into bits 8 .. 11. */
22539 insn &= 0xfffff0f0;
22540 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22542 /* Update the instruction. */
22543 md_number_to_chars (buf, insn, INSN_SIZE);
22547 case BFD_RELOC_ARM_LDC_PC_G0:
22548 case BFD_RELOC_ARM_LDC_PC_G1:
22549 case BFD_RELOC_ARM_LDC_PC_G2:
22550 case BFD_RELOC_ARM_LDC_SB_G0:
22551 case BFD_RELOC_ARM_LDC_SB_G1:
22552 case BFD_RELOC_ARM_LDC_SB_G2:
22553 gas_assert (!fixP->fx_done);
22554 if (!seg->use_rela_p)
22557 bfd_vma addend_abs = abs (value);
22559 /* Check that the absolute value of the addend is a multiple of
22560 four and, when divided by four, fits in 8 bits. */
22561 if (addend_abs & 0x3)
22562 as_bad_where (fixP->fx_file, fixP->fx_line,
22563 _("bad offset 0x%08lX (must be word-aligned)"),
22564 (unsigned long) addend_abs);
22566 if ((addend_abs >> 2) > 0xff)
22567 as_bad_where (fixP->fx_file, fixP->fx_line,
22568 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22569 (unsigned long) addend_abs);
22571 /* Extract the instruction. */
22572 insn = md_chars_to_number (buf, INSN_SIZE);
22574 /* If the addend is negative, clear bit 23 of the instruction.
22575 Otherwise set it. */
22577 insn &= ~(1 << 23);
22581 /* Place the addend (divided by four) into the first eight
22582 bits of the instruction. */
22583 insn &= 0xfffffff0;
22584 insn |= addend_abs >> 2;
22586 /* Update the instruction. */
22587 md_number_to_chars (buf, insn, INSN_SIZE);
22591 case BFD_RELOC_ARM_V4BX:
22592 /* This will need to go in the object file. */
22596 case BFD_RELOC_UNUSED:
22598 as_bad_where (fixP->fx_file, fixP->fx_line,
22599 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22603 /* Translate internal representation of relocation info to BFD target
22607 tc_gen_reloc (asection *section, fixS *fixp)
22610 bfd_reloc_code_real_type code;
22612 reloc = (arelent *) xmalloc (sizeof (arelent));
22614 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22615 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22616 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22618 if (fixp->fx_pcrel)
22620 if (section->use_rela_p)
22621 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22623 fixp->fx_offset = reloc->address;
22625 reloc->addend = fixp->fx_offset;
22627 switch (fixp->fx_r_type)
22630 if (fixp->fx_pcrel)
22632 code = BFD_RELOC_8_PCREL;
22637 if (fixp->fx_pcrel)
22639 code = BFD_RELOC_16_PCREL;
22644 if (fixp->fx_pcrel)
22646 code = BFD_RELOC_32_PCREL;
22650 case BFD_RELOC_ARM_MOVW:
22651 if (fixp->fx_pcrel)
22653 code = BFD_RELOC_ARM_MOVW_PCREL;
22657 case BFD_RELOC_ARM_MOVT:
22658 if (fixp->fx_pcrel)
22660 code = BFD_RELOC_ARM_MOVT_PCREL;
22664 case BFD_RELOC_ARM_THUMB_MOVW:
22665 if (fixp->fx_pcrel)
22667 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22671 case BFD_RELOC_ARM_THUMB_MOVT:
22672 if (fixp->fx_pcrel)
22674 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22678 case BFD_RELOC_NONE:
22679 case BFD_RELOC_ARM_PCREL_BRANCH:
22680 case BFD_RELOC_ARM_PCREL_BLX:
22681 case BFD_RELOC_RVA:
22682 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22683 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22684 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22685 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22686 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22687 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22688 case BFD_RELOC_VTABLE_ENTRY:
22689 case BFD_RELOC_VTABLE_INHERIT:
22691 case BFD_RELOC_32_SECREL:
22693 code = fixp->fx_r_type;
22696 case BFD_RELOC_THUMB_PCREL_BLX:
22698 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22699 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22702 code = BFD_RELOC_THUMB_PCREL_BLX;
22705 case BFD_RELOC_ARM_LITERAL:
22706 case BFD_RELOC_ARM_HWLITERAL:
22707 /* If this is called then the a literal has
22708 been referenced across a section boundary. */
22709 as_bad_where (fixp->fx_file, fixp->fx_line,
22710 _("literal referenced across section boundary"));
22714 case BFD_RELOC_ARM_TLS_CALL:
22715 case BFD_RELOC_ARM_THM_TLS_CALL:
22716 case BFD_RELOC_ARM_TLS_DESCSEQ:
22717 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22718 case BFD_RELOC_ARM_GOT32:
22719 case BFD_RELOC_ARM_GOTOFF:
22720 case BFD_RELOC_ARM_GOT_PREL:
22721 case BFD_RELOC_ARM_PLT32:
22722 case BFD_RELOC_ARM_TARGET1:
22723 case BFD_RELOC_ARM_ROSEGREL32:
22724 case BFD_RELOC_ARM_SBREL32:
22725 case BFD_RELOC_ARM_PREL31:
22726 case BFD_RELOC_ARM_TARGET2:
22727 case BFD_RELOC_ARM_TLS_LE32:
22728 case BFD_RELOC_ARM_TLS_LDO32:
22729 case BFD_RELOC_ARM_PCREL_CALL:
22730 case BFD_RELOC_ARM_PCREL_JUMP:
22731 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22732 case BFD_RELOC_ARM_ALU_PC_G0:
22733 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22734 case BFD_RELOC_ARM_ALU_PC_G1:
22735 case BFD_RELOC_ARM_ALU_PC_G2:
22736 case BFD_RELOC_ARM_LDR_PC_G0:
22737 case BFD_RELOC_ARM_LDR_PC_G1:
22738 case BFD_RELOC_ARM_LDR_PC_G2:
22739 case BFD_RELOC_ARM_LDRS_PC_G0:
22740 case BFD_RELOC_ARM_LDRS_PC_G1:
22741 case BFD_RELOC_ARM_LDRS_PC_G2:
22742 case BFD_RELOC_ARM_LDC_PC_G0:
22743 case BFD_RELOC_ARM_LDC_PC_G1:
22744 case BFD_RELOC_ARM_LDC_PC_G2:
22745 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22746 case BFD_RELOC_ARM_ALU_SB_G0:
22747 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22748 case BFD_RELOC_ARM_ALU_SB_G1:
22749 case BFD_RELOC_ARM_ALU_SB_G2:
22750 case BFD_RELOC_ARM_LDR_SB_G0:
22751 case BFD_RELOC_ARM_LDR_SB_G1:
22752 case BFD_RELOC_ARM_LDR_SB_G2:
22753 case BFD_RELOC_ARM_LDRS_SB_G0:
22754 case BFD_RELOC_ARM_LDRS_SB_G1:
22755 case BFD_RELOC_ARM_LDRS_SB_G2:
22756 case BFD_RELOC_ARM_LDC_SB_G0:
22757 case BFD_RELOC_ARM_LDC_SB_G1:
22758 case BFD_RELOC_ARM_LDC_SB_G2:
22759 case BFD_RELOC_ARM_V4BX:
22760 code = fixp->fx_r_type;
22763 case BFD_RELOC_ARM_TLS_GOTDESC:
22764 case BFD_RELOC_ARM_TLS_GD32:
22765 case BFD_RELOC_ARM_TLS_IE32:
22766 case BFD_RELOC_ARM_TLS_LDM32:
22767 /* BFD will include the symbol's address in the addend.
22768 But we don't want that, so subtract it out again here. */
22769 if (!S_IS_COMMON (fixp->fx_addsy))
22770 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22771 code = fixp->fx_r_type;
22775 case BFD_RELOC_ARM_IMMEDIATE:
22776 as_bad_where (fixp->fx_file, fixp->fx_line,
22777 _("internal relocation (type: IMMEDIATE) not fixed up"));
22780 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22781 as_bad_where (fixp->fx_file, fixp->fx_line,
22782 _("ADRL used for a symbol not defined in the same file"));
22785 case BFD_RELOC_ARM_OFFSET_IMM:
22786 if (section->use_rela_p)
22788 code = fixp->fx_r_type;
22792 if (fixp->fx_addsy != NULL
22793 && !S_IS_DEFINED (fixp->fx_addsy)
22794 && S_IS_LOCAL (fixp->fx_addsy))
22796 as_bad_where (fixp->fx_file, fixp->fx_line,
22797 _("undefined local label `%s'"),
22798 S_GET_NAME (fixp->fx_addsy));
22802 as_bad_where (fixp->fx_file, fixp->fx_line,
22803 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22810 switch (fixp->fx_r_type)
22812 case BFD_RELOC_NONE: type = "NONE"; break;
22813 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22814 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22815 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22816 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22817 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22818 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22819 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22820 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22821 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22822 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22823 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22824 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22825 default: type = _("<unknown>"); break;
22827 as_bad_where (fixp->fx_file, fixp->fx_line,
22828 _("cannot represent %s relocation in this object file format"),
22835 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22837 && fixp->fx_addsy == GOT_symbol)
22839 code = BFD_RELOC_ARM_GOTPC;
22840 reloc->addend = fixp->fx_offset = reloc->address;
22844 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22846 if (reloc->howto == NULL)
22848 as_bad_where (fixp->fx_file, fixp->fx_line,
22849 _("cannot represent %s relocation in this object file format"),
22850 bfd_get_reloc_code_name (code));
22854 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22855 vtable entry to be used in the relocation's section offset. */
22856 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22857 reloc->address = fixp->fx_offset;
22862 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22865 cons_fix_new_arm (fragS * frag,
22870 bfd_reloc_code_real_type type;
22874 FIXME: @@ Should look at CPU word size. */
22878 type = BFD_RELOC_8;
22881 type = BFD_RELOC_16;
22885 type = BFD_RELOC_32;
22888 type = BFD_RELOC_64;
22893 if (exp->X_op == O_secrel)
22895 exp->X_op = O_symbol;
22896 type = BFD_RELOC_32_SECREL;
22900 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22903 #if defined (OBJ_COFF)
22905 arm_validate_fix (fixS * fixP)
22907 /* If the destination of the branch is a defined symbol which does not have
22908 the THUMB_FUNC attribute, then we must be calling a function which has
22909 the (interfacearm) attribute. We look for the Thumb entry point to that
22910 function and change the branch to refer to that function instead. */
22911 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22912 && fixP->fx_addsy != NULL
22913 && S_IS_DEFINED (fixP->fx_addsy)
22914 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22916 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22923 arm_force_relocation (struct fix * fixp)
22925 #if defined (OBJ_COFF) && defined (TE_PE)
22926 if (fixp->fx_r_type == BFD_RELOC_RVA)
22930 /* In case we have a call or a branch to a function in ARM ISA mode from
22931 a thumb function or vice-versa force the relocation. These relocations
22932 are cleared off for some cores that might have blx and simple transformations
22936 switch (fixp->fx_r_type)
22938 case BFD_RELOC_ARM_PCREL_JUMP:
22939 case BFD_RELOC_ARM_PCREL_CALL:
22940 case BFD_RELOC_THUMB_PCREL_BLX:
22941 if (THUMB_IS_FUNC (fixp->fx_addsy))
22945 case BFD_RELOC_ARM_PCREL_BLX:
22946 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22947 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22948 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22949 if (ARM_IS_FUNC (fixp->fx_addsy))
22958 /* Resolve these relocations even if the symbol is extern or weak.
22959 Technically this is probably wrong due to symbol preemption.
22960 In practice these relocations do not have enough range to be useful
22961 at dynamic link time, and some code (e.g. in the Linux kernel)
22962 expects these references to be resolved. */
22963 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22964 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22965 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22966 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22967 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22968 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22969 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22970 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22971 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22972 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22973 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22974 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22975 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22976 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22979 /* Always leave these relocations for the linker. */
22980 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22981 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22982 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22985 /* Always generate relocations against function symbols. */
22986 if (fixp->fx_r_type == BFD_RELOC_32
22988 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22991 return generic_force_reloc (fixp);
22994 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22995 /* Relocations against function names must be left unadjusted,
22996 so that the linker can use this information to generate interworking
22997 stubs. The MIPS version of this function
22998 also prevents relocations that are mips-16 specific, but I do not
22999 know why it does this.
23002 There is one other problem that ought to be addressed here, but
23003 which currently is not: Taking the address of a label (rather
23004 than a function) and then later jumping to that address. Such
23005 addresses also ought to have their bottom bit set (assuming that
23006 they reside in Thumb code), but at the moment they will not. */
23009 arm_fix_adjustable (fixS * fixP)
23011 if (fixP->fx_addsy == NULL)
23014 /* Preserve relocations against symbols with function type. */
23015 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23018 if (THUMB_IS_FUNC (fixP->fx_addsy)
23019 && fixP->fx_subsy == NULL)
23022 /* We need the symbol name for the VTABLE entries. */
23023 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23024 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23027 /* Don't allow symbols to be discarded on GOT related relocs. */
23028 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23029 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23030 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23031 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23032 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23033 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23034 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23035 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23036 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23037 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23038 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23039 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23040 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23041 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23044 /* Similarly for group relocations. */
23045 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23046 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23047 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23050 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23051 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23052 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23053 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23054 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23055 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23056 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23057 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23058 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23063 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23068 elf32_arm_target_format (void)
23071 return (target_big_endian
23072 ? "elf32-bigarm-symbian"
23073 : "elf32-littlearm-symbian");
23074 #elif defined (TE_VXWORKS)
23075 return (target_big_endian
23076 ? "elf32-bigarm-vxworks"
23077 : "elf32-littlearm-vxworks");
23078 #elif defined (TE_NACL)
23079 return (target_big_endian
23080 ? "elf32-bigarm-nacl"
23081 : "elf32-littlearm-nacl");
23083 if (target_big_endian)
23084 return "elf32-bigarm";
23086 return "elf32-littlearm";
23091 armelf_frob_symbol (symbolS * symp,
23094 elf_frob_symbol (symp, puntp);
23098 /* MD interface: Finalization. */
23103 literal_pool * pool;
23105 /* Ensure that all the IT blocks are properly closed. */
23106 check_it_blocks_finished ();
23108 for (pool = list_of_pools; pool; pool = pool->next)
23110 /* Put it at the end of the relevant section. */
23111 subseg_set (pool->section, pool->sub_section);
23113 arm_elf_change_section ();
23120 /* Remove any excess mapping symbols generated for alignment frags in
23121 SEC. We may have created a mapping symbol before a zero byte
23122 alignment; remove it if there's a mapping symbol after the
23125 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23126 void *dummy ATTRIBUTE_UNUSED)
23128 segment_info_type *seginfo = seg_info (sec);
23131 if (seginfo == NULL || seginfo->frchainP == NULL)
23134 for (fragp = seginfo->frchainP->frch_root;
23136 fragp = fragp->fr_next)
23138 symbolS *sym = fragp->tc_frag_data.last_map;
23139 fragS *next = fragp->fr_next;
23141 /* Variable-sized frags have been converted to fixed size by
23142 this point. But if this was variable-sized to start with,
23143 there will be a fixed-size frag after it. So don't handle
23145 if (sym == NULL || next == NULL)
23148 if (S_GET_VALUE (sym) < next->fr_address)
23149 /* Not at the end of this frag. */
23151 know (S_GET_VALUE (sym) == next->fr_address);
23155 if (next->tc_frag_data.first_map != NULL)
23157 /* Next frag starts with a mapping symbol. Discard this
23159 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23163 if (next->fr_next == NULL)
23165 /* This mapping symbol is at the end of the section. Discard
23167 know (next->fr_fix == 0 && next->fr_var == 0);
23168 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23172 /* As long as we have empty frags without any mapping symbols,
23174 /* If the next frag is non-empty and does not start with a
23175 mapping symbol, then this mapping symbol is required. */
23176 if (next->fr_address != next->fr_next->fr_address)
23179 next = next->fr_next;
23181 while (next != NULL);
23186 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23190 arm_adjust_symtab (void)
23195 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23197 if (ARM_IS_THUMB (sym))
23199 if (THUMB_IS_FUNC (sym))
23201 /* Mark the symbol as a Thumb function. */
23202 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23203 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23204 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23206 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23207 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23209 as_bad (_("%s: unexpected function type: %d"),
23210 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23212 else switch (S_GET_STORAGE_CLASS (sym))
23215 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23218 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23221 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23229 if (ARM_IS_INTERWORK (sym))
23230 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23237 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23239 if (ARM_IS_THUMB (sym))
23241 elf_symbol_type * elf_sym;
23243 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23244 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23246 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23247 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23249 /* If it's a .thumb_func, declare it as so,
23250 otherwise tag label as .code 16. */
23251 if (THUMB_IS_FUNC (sym))
23252 elf_sym->internal_elf_sym.st_target_internal
23253 = ST_BRANCH_TO_THUMB;
23254 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23255 elf_sym->internal_elf_sym.st_info =
23256 ELF_ST_INFO (bind, STT_ARM_16BIT);
23261 /* Remove any overlapping mapping symbols generated by alignment frags. */
23262 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23263 /* Now do generic ELF adjustments. */
23264 elf_adjust_symtab ();
23268 /* MD interface: Initialization. */
23271 set_constant_flonums (void)
23275 for (i = 0; i < NUM_FLOAT_VALS; i++)
23276 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23280 /* Auto-select Thumb mode if it's the only available instruction set for the
23281 given architecture. */
23284 autoselect_thumb_from_cpu_variant (void)
23286 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23287 opcode_select (16);
23296 if ( (arm_ops_hsh = hash_new ()) == NULL
23297 || (arm_cond_hsh = hash_new ()) == NULL
23298 || (arm_shift_hsh = hash_new ()) == NULL
23299 || (arm_psr_hsh = hash_new ()) == NULL
23300 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23301 || (arm_reg_hsh = hash_new ()) == NULL
23302 || (arm_reloc_hsh = hash_new ()) == NULL
23303 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23304 as_fatal (_("virtual memory exhausted"));
23306 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23307 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23308 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23309 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23310 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23311 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23312 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23313 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23314 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23315 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23316 (void *) (v7m_psrs + i));
23317 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23318 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23320 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23322 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23323 (void *) (barrier_opt_names + i));
23325 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23327 struct reloc_entry * entry = reloc_names + i;
23329 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23330 /* This makes encode_branch() use the EABI versions of this relocation. */
23331 entry->reloc = BFD_RELOC_UNUSED;
23333 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23337 set_constant_flonums ();
23339 /* Set the cpu variant based on the command-line options. We prefer
23340 -mcpu= over -march= if both are set (as for GCC); and we prefer
23341 -mfpu= over any other way of setting the floating point unit.
23342 Use of legacy options with new options are faulted. */
23345 if (mcpu_cpu_opt || march_cpu_opt)
23346 as_bad (_("use of old and new-style options to set CPU type"));
23348 mcpu_cpu_opt = legacy_cpu;
23350 else if (!mcpu_cpu_opt)
23351 mcpu_cpu_opt = march_cpu_opt;
23356 as_bad (_("use of old and new-style options to set FPU type"));
23358 mfpu_opt = legacy_fpu;
23360 else if (!mfpu_opt)
23362 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23363 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23364 /* Some environments specify a default FPU. If they don't, infer it
23365 from the processor. */
23367 mfpu_opt = mcpu_fpu_opt;
23369 mfpu_opt = march_fpu_opt;
23371 mfpu_opt = &fpu_default;
23377 if (mcpu_cpu_opt != NULL)
23378 mfpu_opt = &fpu_default;
23379 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23380 mfpu_opt = &fpu_arch_vfp_v2;
23382 mfpu_opt = &fpu_arch_fpa;
23388 mcpu_cpu_opt = &cpu_default;
23389 selected_cpu = cpu_default;
23393 selected_cpu = *mcpu_cpu_opt;
23395 mcpu_cpu_opt = &arm_arch_any;
23398 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23400 autoselect_thumb_from_cpu_variant ();
23402 arm_arch_used = thumb_arch_used = arm_arch_none;
23404 #if defined OBJ_COFF || defined OBJ_ELF
23406 unsigned int flags = 0;
23408 #if defined OBJ_ELF
23409 flags = meabi_flags;
23411 switch (meabi_flags)
23413 case EF_ARM_EABI_UNKNOWN:
23415 /* Set the flags in the private structure. */
23416 if (uses_apcs_26) flags |= F_APCS26;
23417 if (support_interwork) flags |= F_INTERWORK;
23418 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23419 if (pic_code) flags |= F_PIC;
23420 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23421 flags |= F_SOFT_FLOAT;
23423 switch (mfloat_abi_opt)
23425 case ARM_FLOAT_ABI_SOFT:
23426 case ARM_FLOAT_ABI_SOFTFP:
23427 flags |= F_SOFT_FLOAT;
23430 case ARM_FLOAT_ABI_HARD:
23431 if (flags & F_SOFT_FLOAT)
23432 as_bad (_("hard-float conflicts with specified fpu"));
23436 /* Using pure-endian doubles (even if soft-float). */
23437 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23438 flags |= F_VFP_FLOAT;
23440 #if defined OBJ_ELF
23441 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23442 flags |= EF_ARM_MAVERICK_FLOAT;
23445 case EF_ARM_EABI_VER4:
23446 case EF_ARM_EABI_VER5:
23447 /* No additional flags to set. */
23454 bfd_set_private_flags (stdoutput, flags);
23456 /* We have run out flags in the COFF header to encode the
23457 status of ATPCS support, so instead we create a dummy,
23458 empty, debug section called .arm.atpcs. */
23463 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23467 bfd_set_section_flags
23468 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23469 bfd_set_section_size (stdoutput, sec, 0);
23470 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23476 /* Record the CPU type as well. */
23477 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23478 mach = bfd_mach_arm_iWMMXt2;
23479 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23480 mach = bfd_mach_arm_iWMMXt;
23481 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23482 mach = bfd_mach_arm_XScale;
23483 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23484 mach = bfd_mach_arm_ep9312;
23485 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23486 mach = bfd_mach_arm_5TE;
23487 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23489 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23490 mach = bfd_mach_arm_5T;
23492 mach = bfd_mach_arm_5;
23494 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23496 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23497 mach = bfd_mach_arm_4T;
23499 mach = bfd_mach_arm_4;
23501 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23502 mach = bfd_mach_arm_3M;
23503 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23504 mach = bfd_mach_arm_3;
23505 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23506 mach = bfd_mach_arm_2a;
23507 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23508 mach = bfd_mach_arm_2;
23510 mach = bfd_mach_arm_unknown;
23512 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23515 /* Command line processing. */
23518 Invocation line includes a switch not recognized by the base assembler.
23519 See if it's a processor-specific option.
23521 This routine is somewhat complicated by the need for backwards
23522 compatibility (since older releases of gcc can't be changed).
23523 The new options try to make the interface as compatible as
23526 New options (supported) are:
23528 -mcpu=<cpu name> Assemble for selected processor
23529 -march=<architecture name> Assemble for selected architecture
23530 -mfpu=<fpu architecture> Assemble for selected FPU.
23531 -EB/-mbig-endian Big-endian
23532 -EL/-mlittle-endian Little-endian
23533 -k Generate PIC code
23534 -mthumb Start in Thumb mode
23535 -mthumb-interwork Code supports ARM/Thumb interworking
23537 -m[no-]warn-deprecated Warn about deprecated features
23539 For now we will also provide support for:
23541 -mapcs-32 32-bit Program counter
23542 -mapcs-26 26-bit Program counter
23543 -macps-float Floats passed in FP registers
23544 -mapcs-reentrant Reentrant code
23546 (sometime these will probably be replaced with -mapcs=<list of options>
23547 and -matpcs=<list of options>)
23549 The remaining options are only supported for back-wards compatibility.
23550 Cpu variants, the arm part is optional:
23551 -m[arm]1 Currently not supported.
23552 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23553 -m[arm]3 Arm 3 processor
23554 -m[arm]6[xx], Arm 6 processors
23555 -m[arm]7[xx][t][[d]m] Arm 7 processors
23556 -m[arm]8[10] Arm 8 processors
23557 -m[arm]9[20][tdmi] Arm 9 processors
23558 -mstrongarm[110[0]] StrongARM processors
23559 -mxscale XScale processors
23560 -m[arm]v[2345[t[e]]] Arm architectures
23561 -mall All (except the ARM1)
23563 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23564 -mfpe-old (No float load/store multiples)
23565 -mvfpxd VFP Single precision
23567 -mno-fpu Disable all floating point instructions
23569 The following CPU names are recognized:
23570 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23571 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23572 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23573 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23574 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23575 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23576 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23580 const char * md_shortopts = "m:k";
23582 #ifdef ARM_BI_ENDIAN
23583 #define OPTION_EB (OPTION_MD_BASE + 0)
23584 #define OPTION_EL (OPTION_MD_BASE + 1)
23586 #if TARGET_BYTES_BIG_ENDIAN
23587 #define OPTION_EB (OPTION_MD_BASE + 0)
23589 #define OPTION_EL (OPTION_MD_BASE + 1)
23592 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23594 struct option md_longopts[] =
23597 {"EB", no_argument, NULL, OPTION_EB},
23600 {"EL", no_argument, NULL, OPTION_EL},
23602 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23603 {NULL, no_argument, NULL, 0}
23606 size_t md_longopts_size = sizeof (md_longopts);
23608 struct arm_option_table
23610 char *option; /* Option name to match. */
23611 char *help; /* Help information. */
23612 int *var; /* Variable to change. */
23613 int value; /* What to change it to. */
23614 char *deprecated; /* If non-null, print this message. */
23617 struct arm_option_table arm_opts[] =
23619 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23620 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23621 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23622 &support_interwork, 1, NULL},
23623 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23624 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23625 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23627 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23628 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23629 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23630 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23633 /* These are recognized by the assembler, but have no affect on code. */
23634 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23635 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23637 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23638 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23639 &warn_on_deprecated, 0, NULL},
23640 {NULL, NULL, NULL, 0, NULL}
23643 struct arm_legacy_option_table
23645 char *option; /* Option name to match. */
23646 const arm_feature_set **var; /* Variable to change. */
23647 const arm_feature_set value; /* What to change it to. */
23648 char *deprecated; /* If non-null, print this message. */
23651 const struct arm_legacy_option_table arm_legacy_opts[] =
23653 /* DON'T add any new processors to this list -- we want the whole list
23654 to go away... Add them to the processors table instead. */
23655 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23656 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23657 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23658 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23659 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23660 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23661 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23662 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23663 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23664 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23665 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23666 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23667 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23668 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23669 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23670 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23671 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23672 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23673 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23674 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23675 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23676 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23677 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23678 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23679 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23680 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23681 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23682 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23683 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23684 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23685 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23686 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23687 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23688 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23689 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23690 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23691 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23692 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23693 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23694 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23695 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23696 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23697 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23698 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23699 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23700 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23701 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23702 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23703 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23704 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23705 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23706 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23707 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23708 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23709 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23710 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23711 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23712 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23713 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23714 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23715 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23716 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23717 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23718 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23719 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23720 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23721 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23722 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23723 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23724 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23725 N_("use -mcpu=strongarm110")},
23726 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23727 N_("use -mcpu=strongarm1100")},
23728 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23729 N_("use -mcpu=strongarm1110")},
23730 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23731 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23732 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23734 /* Architecture variants -- don't add any more to this list either. */
23735 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23736 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23737 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23738 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23739 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23740 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23741 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23742 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23743 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23744 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23745 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23746 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23747 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23748 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23749 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23750 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23751 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23752 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23754 /* Floating point variants -- don't add any more to this list either. */
23755 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23756 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23757 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23758 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23759 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23761 {NULL, NULL, ARM_ARCH_NONE, NULL}
23764 struct arm_cpu_option_table
23768 const arm_feature_set value;
23769 /* For some CPUs we assume an FPU unless the user explicitly sets
23771 const arm_feature_set default_fpu;
23772 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23774 const char *canonical_name;
23777 /* This list should, at a minimum, contain all the cpu names
23778 recognized by GCC. */
23779 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23780 static const struct arm_cpu_option_table arm_cpus[] =
23782 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23783 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23784 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23785 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23786 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23787 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23788 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23789 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23790 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23791 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23792 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23793 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23794 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23795 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23796 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23797 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23798 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23799 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23800 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23801 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23802 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23803 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23804 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23805 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23806 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23807 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23808 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23809 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23810 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23811 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23812 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23813 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23814 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23815 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23816 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23817 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23818 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23819 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23820 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23821 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23822 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23823 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23824 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23825 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23826 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23827 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23828 /* For V5 or later processors we default to using VFP; but the user
23829 should really set the FPU type explicitly. */
23830 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23831 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23832 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23833 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23834 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23835 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23836 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23837 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23838 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23839 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23840 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23841 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23842 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23843 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23844 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23845 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23846 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23847 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23848 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23849 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23851 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23852 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23853 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23854 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23855 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23856 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23857 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23858 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23859 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23861 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23862 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23863 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23864 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23865 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23866 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23867 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23868 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23869 FPU_NONE, "Cortex-A5"),
23870 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23871 FPU_ARCH_NEON_VFP_V4,
23873 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23874 ARM_FEATURE (0, FPU_VFP_V3
23875 | FPU_NEON_EXT_V1),
23877 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23878 ARM_FEATURE (0, FPU_VFP_V3
23879 | FPU_NEON_EXT_V1),
23881 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23882 FPU_ARCH_NEON_VFP_V4,
23884 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23885 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23887 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23888 FPU_NONE, "Cortex-R5"),
23889 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23890 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23891 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23892 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23893 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23894 /* ??? XSCALE is really an architecture. */
23895 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23896 /* ??? iwmmxt is not a processor. */
23897 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23898 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23899 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23901 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23904 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23908 struct arm_arch_option_table
23912 const arm_feature_set value;
23913 const arm_feature_set default_fpu;
23916 /* This list should, at a minimum, contain all the architecture names
23917 recognized by GCC. */
23918 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23919 static const struct arm_arch_option_table arm_archs[] =
23921 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23922 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23923 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23924 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23925 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23926 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23927 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23928 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23929 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23930 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23931 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23932 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23933 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23934 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23935 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23936 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23937 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23938 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23939 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23940 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23941 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23942 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23943 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23944 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23945 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23946 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23947 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23948 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23949 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23950 /* The official spelling of the ARMv7 profile variants is the dashed form.
23951 Accept the non-dashed form for compatibility with old toolchains. */
23952 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23953 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23954 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23955 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23956 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23957 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23958 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23959 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23960 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23961 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23962 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23963 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23965 #undef ARM_ARCH_OPT
23967 /* ISA extensions in the co-processor and main instruction set space. */
23968 struct arm_option_extension_value_table
23972 const arm_feature_set value;
23973 const arm_feature_set allowed_archs;
23976 /* The following table must be in alphabetical order with a NULL last entry.
23978 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23979 static const struct arm_option_extension_value_table arm_extensions[] =
23981 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23982 ARM_FEATURE (ARM_EXT_V8, 0)),
23983 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23984 ARM_FEATURE (ARM_EXT_V8, 0)),
23985 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23986 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23987 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23988 ARM_EXT_OPT ("iwmmxt2",
23989 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23990 ARM_EXT_OPT ("maverick",
23991 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23992 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23993 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23994 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23995 ARM_FEATURE (ARM_EXT_V8, 0)),
23996 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23997 ARM_FEATURE (ARM_EXT_V6M, 0)),
23998 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23999 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24000 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24002 ARM_FEATURE (ARM_EXT_V7A, 0)),
24003 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24004 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24008 /* ISA floating-point and Advanced SIMD extensions. */
24009 struct arm_option_fpu_value_table
24012 const arm_feature_set value;
24015 /* This list should, at a minimum, contain all the fpu names
24016 recognized by GCC. */
24017 static const struct arm_option_fpu_value_table arm_fpus[] =
24019 {"softfpa", FPU_NONE},
24020 {"fpe", FPU_ARCH_FPE},
24021 {"fpe2", FPU_ARCH_FPE},
24022 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24023 {"fpa", FPU_ARCH_FPA},
24024 {"fpa10", FPU_ARCH_FPA},
24025 {"fpa11", FPU_ARCH_FPA},
24026 {"arm7500fe", FPU_ARCH_FPA},
24027 {"softvfp", FPU_ARCH_VFP},
24028 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24029 {"vfp", FPU_ARCH_VFP_V2},
24030 {"vfp9", FPU_ARCH_VFP_V2},
24031 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24032 {"vfp10", FPU_ARCH_VFP_V2},
24033 {"vfp10-r0", FPU_ARCH_VFP_V1},
24034 {"vfpxd", FPU_ARCH_VFP_V1xD},
24035 {"vfpv2", FPU_ARCH_VFP_V2},
24036 {"vfpv3", FPU_ARCH_VFP_V3},
24037 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24038 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24039 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24040 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24041 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24042 {"arm1020t", FPU_ARCH_VFP_V1},
24043 {"arm1020e", FPU_ARCH_VFP_V2},
24044 {"arm1136jfs", FPU_ARCH_VFP_V2},
24045 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24046 {"maverick", FPU_ARCH_MAVERICK},
24047 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24048 {"neon-fp16", FPU_ARCH_NEON_FP16},
24049 {"vfpv4", FPU_ARCH_VFP_V4},
24050 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24051 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24052 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24053 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24054 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24055 {"crypto-neon-fp-armv8",
24056 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24057 {NULL, ARM_ARCH_NONE}
24060 struct arm_option_value_table
24066 static const struct arm_option_value_table arm_float_abis[] =
24068 {"hard", ARM_FLOAT_ABI_HARD},
24069 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24070 {"soft", ARM_FLOAT_ABI_SOFT},
24075 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24076 static const struct arm_option_value_table arm_eabis[] =
24078 {"gnu", EF_ARM_EABI_UNKNOWN},
24079 {"4", EF_ARM_EABI_VER4},
24080 {"5", EF_ARM_EABI_VER5},
24085 struct arm_long_option_table
24087 char * option; /* Substring to match. */
24088 char * help; /* Help information. */
24089 int (* func) (char * subopt); /* Function to decode sub-option. */
24090 char * deprecated; /* If non-null, print this message. */
24094 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24096 arm_feature_set *ext_set = (arm_feature_set *)
24097 xmalloc (sizeof (arm_feature_set));
24099 /* We insist on extensions being specified in alphabetical order, and with
24100 extensions being added before being removed. We achieve this by having
24101 the global ARM_EXTENSIONS table in alphabetical order, and using the
24102 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24103 or removing it (0) and only allowing it to change in the order
24105 const struct arm_option_extension_value_table * opt = NULL;
24106 int adding_value = -1;
24108 /* Copy the feature set, so that we can modify it. */
24109 *ext_set = **opt_p;
24112 while (str != NULL && *str != 0)
24119 as_bad (_("invalid architectural extension"));
24124 ext = strchr (str, '+');
24129 len = strlen (str);
24131 if (len >= 2 && strncmp (str, "no", 2) == 0)
24133 if (adding_value != 0)
24136 opt = arm_extensions;
24144 if (adding_value == -1)
24147 opt = arm_extensions;
24149 else if (adding_value != 1)
24151 as_bad (_("must specify extensions to add before specifying "
24152 "those to remove"));
24159 as_bad (_("missing architectural extension"));
24163 gas_assert (adding_value != -1);
24164 gas_assert (opt != NULL);
24166 /* Scan over the options table trying to find an exact match. */
24167 for (; opt->name != NULL; opt++)
24168 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24170 /* Check we can apply the extension to this architecture. */
24171 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24173 as_bad (_("extension does not apply to the base architecture"));
24177 /* Add or remove the extension. */
24179 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24181 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24186 if (opt->name == NULL)
24188 /* Did we fail to find an extension because it wasn't specified in
24189 alphabetical order, or because it does not exist? */
24191 for (opt = arm_extensions; opt->name != NULL; opt++)
24192 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24195 if (opt->name == NULL)
24196 as_bad (_("unknown architectural extension `%s'"), str);
24198 as_bad (_("architectural extensions must be specified in "
24199 "alphabetical order"));
24205 /* We should skip the extension we've just matched the next time
24217 arm_parse_cpu (char *str)
24219 const struct arm_cpu_option_table *opt;
24220 char *ext = strchr (str, '+');
24226 len = strlen (str);
24230 as_bad (_("missing cpu name `%s'"), str);
24234 for (opt = arm_cpus; opt->name != NULL; opt++)
24235 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24237 mcpu_cpu_opt = &opt->value;
24238 mcpu_fpu_opt = &opt->default_fpu;
24239 if (opt->canonical_name)
24240 strcpy (selected_cpu_name, opt->canonical_name);
24245 for (i = 0; i < len; i++)
24246 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24247 selected_cpu_name[i] = 0;
24251 return arm_parse_extension (ext, &mcpu_cpu_opt);
24256 as_bad (_("unknown cpu `%s'"), str);
24261 arm_parse_arch (char *str)
24263 const struct arm_arch_option_table *opt;
24264 char *ext = strchr (str, '+');
24270 len = strlen (str);
24274 as_bad (_("missing architecture name `%s'"), str);
24278 for (opt = arm_archs; opt->name != NULL; opt++)
24279 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24281 march_cpu_opt = &opt->value;
24282 march_fpu_opt = &opt->default_fpu;
24283 strcpy (selected_cpu_name, opt->name);
24286 return arm_parse_extension (ext, &march_cpu_opt);
24291 as_bad (_("unknown architecture `%s'\n"), str);
24296 arm_parse_fpu (char * str)
24298 const struct arm_option_fpu_value_table * opt;
24300 for (opt = arm_fpus; opt->name != NULL; opt++)
24301 if (streq (opt->name, str))
24303 mfpu_opt = &opt->value;
24307 as_bad (_("unknown floating point format `%s'\n"), str);
24312 arm_parse_float_abi (char * str)
24314 const struct arm_option_value_table * opt;
24316 for (opt = arm_float_abis; opt->name != NULL; opt++)
24317 if (streq (opt->name, str))
24319 mfloat_abi_opt = opt->value;
24323 as_bad (_("unknown floating point abi `%s'\n"), str);
24329 arm_parse_eabi (char * str)
24331 const struct arm_option_value_table *opt;
24333 for (opt = arm_eabis; opt->name != NULL; opt++)
24334 if (streq (opt->name, str))
24336 meabi_flags = opt->value;
24339 as_bad (_("unknown EABI `%s'\n"), str);
24345 arm_parse_it_mode (char * str)
24347 bfd_boolean ret = TRUE;
24349 if (streq ("arm", str))
24350 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24351 else if (streq ("thumb", str))
24352 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24353 else if (streq ("always", str))
24354 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24355 else if (streq ("never", str))
24356 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24359 as_bad (_("unknown implicit IT mode `%s', should be "\
24360 "arm, thumb, always, or never."), str);
24367 struct arm_long_option_table arm_long_opts[] =
24369 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24370 arm_parse_cpu, NULL},
24371 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24372 arm_parse_arch, NULL},
24373 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24374 arm_parse_fpu, NULL},
24375 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24376 arm_parse_float_abi, NULL},
24378 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24379 arm_parse_eabi, NULL},
24381 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24382 arm_parse_it_mode, NULL},
24383 {NULL, NULL, 0, NULL}
24387 md_parse_option (int c, char * arg)
24389 struct arm_option_table *opt;
24390 const struct arm_legacy_option_table *fopt;
24391 struct arm_long_option_table *lopt;
24397 target_big_endian = 1;
24403 target_big_endian = 0;
24407 case OPTION_FIX_V4BX:
24412 /* Listing option. Just ignore these, we don't support additional
24417 for (opt = arm_opts; opt->option != NULL; opt++)
24419 if (c == opt->option[0]
24420 && ((arg == NULL && opt->option[1] == 0)
24421 || streq (arg, opt->option + 1)))
24423 /* If the option is deprecated, tell the user. */
24424 if (warn_on_deprecated && opt->deprecated != NULL)
24425 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24426 arg ? arg : "", _(opt->deprecated));
24428 if (opt->var != NULL)
24429 *opt->var = opt->value;
24435 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24437 if (c == fopt->option[0]
24438 && ((arg == NULL && fopt->option[1] == 0)
24439 || streq (arg, fopt->option + 1)))
24441 /* If the option is deprecated, tell the user. */
24442 if (warn_on_deprecated && fopt->deprecated != NULL)
24443 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24444 arg ? arg : "", _(fopt->deprecated));
24446 if (fopt->var != NULL)
24447 *fopt->var = &fopt->value;
24453 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24455 /* These options are expected to have an argument. */
24456 if (c == lopt->option[0]
24458 && strncmp (arg, lopt->option + 1,
24459 strlen (lopt->option + 1)) == 0)
24461 /* If the option is deprecated, tell the user. */
24462 if (warn_on_deprecated && lopt->deprecated != NULL)
24463 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24464 _(lopt->deprecated));
24466 /* Call the sup-option parser. */
24467 return lopt->func (arg + strlen (lopt->option) - 1);
24478 md_show_usage (FILE * fp)
24480 struct arm_option_table *opt;
24481 struct arm_long_option_table *lopt;
24483 fprintf (fp, _(" ARM-specific assembler options:\n"));
24485 for (opt = arm_opts; opt->option != NULL; opt++)
24486 if (opt->help != NULL)
24487 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24489 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24490 if (lopt->help != NULL)
24491 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24495 -EB assemble code for a big-endian cpu\n"));
24500 -EL assemble code for a little-endian cpu\n"));
24504 --fix-v4bx Allow BX in ARMv4 code\n"));
24512 arm_feature_set flags;
24513 } cpu_arch_ver_table;
24515 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24516 least features first. */
24517 static const cpu_arch_ver_table cpu_arch_ver[] =
24523 {4, ARM_ARCH_V5TE},
24524 {5, ARM_ARCH_V5TEJ},
24528 {11, ARM_ARCH_V6M},
24529 {12, ARM_ARCH_V6SM},
24530 {8, ARM_ARCH_V6T2},
24531 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24532 {10, ARM_ARCH_V7R},
24533 {10, ARM_ARCH_V7M},
24534 {14, ARM_ARCH_V8A},
24538 /* Set an attribute if it has not already been set by the user. */
24540 aeabi_set_attribute_int (int tag, int value)
24543 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24544 || !attributes_set_explicitly[tag])
24545 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24549 aeabi_set_attribute_string (int tag, const char *value)
24552 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24553 || !attributes_set_explicitly[tag])
24554 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24557 /* Set the public EABI object attributes. */
24559 aeabi_set_public_attributes (void)
24564 int fp16_optional = 0;
24565 arm_feature_set flags;
24566 arm_feature_set tmp;
24567 const cpu_arch_ver_table *p;
24569 /* Choose the architecture based on the capabilities of the requested cpu
24570 (if any) and/or the instructions actually used. */
24571 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24572 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24573 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24575 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24576 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24578 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24579 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24581 /* Allow the user to override the reported architecture. */
24584 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24585 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24588 /* We need to make sure that the attributes do not identify us as v6S-M
24589 when the only v6S-M feature in use is the Operating System Extensions. */
24590 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24591 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24592 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24596 for (p = cpu_arch_ver; p->val; p++)
24598 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24601 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24605 /* The table lookup above finds the last architecture to contribute
24606 a new feature. Unfortunately, Tag13 is a subset of the union of
24607 v6T2 and v7-M, so it is never seen as contributing a new feature.
24608 We can not search for the last entry which is entirely used,
24609 because if no CPU is specified we build up only those flags
24610 actually used. Perhaps we should separate out the specified
24611 and implicit cases. Avoid taking this path for -march=all by
24612 checking for contradictory v7-A / v7-M features. */
24614 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24615 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24616 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24619 /* Tag_CPU_name. */
24620 if (selected_cpu_name[0])
24624 q = selected_cpu_name;
24625 if (strncmp (q, "armv", 4) == 0)
24630 for (i = 0; q[i]; i++)
24631 q[i] = TOUPPER (q[i]);
24633 aeabi_set_attribute_string (Tag_CPU_name, q);
24636 /* Tag_CPU_arch. */
24637 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24639 /* Tag_CPU_arch_profile. */
24640 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24642 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24644 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24649 if (profile != '\0')
24650 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24652 /* Tag_ARM_ISA_use. */
24653 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24655 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24657 /* Tag_THUMB_ISA_use. */
24658 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24660 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24661 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24663 /* Tag_VFP_arch. */
24664 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24665 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24666 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24667 aeabi_set_attribute_int (Tag_VFP_arch,
24668 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24670 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24673 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24675 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24677 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24680 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24681 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24682 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24683 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24684 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24686 /* Tag_ABI_HardFP_use. */
24687 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24688 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24689 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24691 /* Tag_WMMX_arch. */
24692 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24693 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24694 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24695 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24697 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24698 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24699 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24700 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24702 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24704 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24708 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24713 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24714 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24715 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24719 We set Tag_DIV_use to two when integer divide instructions have been used
24720 in ARM state, or when Thumb integer divide instructions have been used,
24721 but we have no architecture profile set, nor have we any ARM instructions.
24723 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24726 For new architectures we will have to check these tests. */
24727 gas_assert (arch <= TAG_CPU_ARCH_V8);
24728 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24729 aeabi_set_attribute_int (Tag_DIV_use, 0);
24730 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24731 || (profile == '\0'
24732 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24733 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24734 aeabi_set_attribute_int (Tag_DIV_use, 2);
24736 /* Tag_MP_extension_use. */
24737 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24738 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24740 /* Tag Virtualization_use. */
24741 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24743 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24746 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24749 /* Add the default contents for the .ARM.attributes section. */
24753 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24756 aeabi_set_public_attributes ();
24758 #endif /* OBJ_ELF */
24761 /* Parse a .cpu directive. */
24764 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24766 const struct arm_cpu_option_table *opt;
24770 name = input_line_pointer;
24771 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24772 input_line_pointer++;
24773 saved_char = *input_line_pointer;
24774 *input_line_pointer = 0;
24776 /* Skip the first "all" entry. */
24777 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24778 if (streq (opt->name, name))
24780 mcpu_cpu_opt = &opt->value;
24781 selected_cpu = opt->value;
24782 if (opt->canonical_name)
24783 strcpy (selected_cpu_name, opt->canonical_name);
24787 for (i = 0; opt->name[i]; i++)
24788 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24790 selected_cpu_name[i] = 0;
24792 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24793 *input_line_pointer = saved_char;
24794 demand_empty_rest_of_line ();
24797 as_bad (_("unknown cpu `%s'"), name);
24798 *input_line_pointer = saved_char;
24799 ignore_rest_of_line ();
24803 /* Parse a .arch directive. */
24806 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24808 const struct arm_arch_option_table *opt;
24812 name = input_line_pointer;
24813 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24814 input_line_pointer++;
24815 saved_char = *input_line_pointer;
24816 *input_line_pointer = 0;
24818 /* Skip the first "all" entry. */
24819 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24820 if (streq (opt->name, name))
24822 mcpu_cpu_opt = &opt->value;
24823 selected_cpu = opt->value;
24824 strcpy (selected_cpu_name, opt->name);
24825 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24826 *input_line_pointer = saved_char;
24827 demand_empty_rest_of_line ();
24831 as_bad (_("unknown architecture `%s'\n"), name);
24832 *input_line_pointer = saved_char;
24833 ignore_rest_of_line ();
24837 /* Parse a .object_arch directive. */
24840 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24842 const struct arm_arch_option_table *opt;
24846 name = input_line_pointer;
24847 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24848 input_line_pointer++;
24849 saved_char = *input_line_pointer;
24850 *input_line_pointer = 0;
24852 /* Skip the first "all" entry. */
24853 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24854 if (streq (opt->name, name))
24856 object_arch = &opt->value;
24857 *input_line_pointer = saved_char;
24858 demand_empty_rest_of_line ();
24862 as_bad (_("unknown architecture `%s'\n"), name);
24863 *input_line_pointer = saved_char;
24864 ignore_rest_of_line ();
24867 /* Parse a .arch_extension directive. */
24870 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24872 const struct arm_option_extension_value_table *opt;
24875 int adding_value = 1;
24877 name = input_line_pointer;
24878 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24879 input_line_pointer++;
24880 saved_char = *input_line_pointer;
24881 *input_line_pointer = 0;
24883 if (strlen (name) >= 2
24884 && strncmp (name, "no", 2) == 0)
24890 for (opt = arm_extensions; opt->name != NULL; opt++)
24891 if (streq (opt->name, name))
24893 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24895 as_bad (_("architectural extension `%s' is not allowed for the "
24896 "current base architecture"), name);
24901 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24903 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24905 mcpu_cpu_opt = &selected_cpu;
24906 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24907 *input_line_pointer = saved_char;
24908 demand_empty_rest_of_line ();
24912 if (opt->name == NULL)
24913 as_bad (_("unknown architecture `%s'\n"), name);
24915 *input_line_pointer = saved_char;
24916 ignore_rest_of_line ();
24919 /* Parse a .fpu directive. */
24922 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24924 const struct arm_option_fpu_value_table *opt;
24928 name = input_line_pointer;
24929 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24930 input_line_pointer++;
24931 saved_char = *input_line_pointer;
24932 *input_line_pointer = 0;
24934 for (opt = arm_fpus; opt->name != NULL; opt++)
24935 if (streq (opt->name, name))
24937 mfpu_opt = &opt->value;
24938 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24939 *input_line_pointer = saved_char;
24940 demand_empty_rest_of_line ();
24944 as_bad (_("unknown floating point format `%s'\n"), name);
24945 *input_line_pointer = saved_char;
24946 ignore_rest_of_line ();
24949 /* Copy symbol information. */
24952 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24954 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24958 /* Given a symbolic attribute NAME, return the proper integer value.
24959 Returns -1 if the attribute is not known. */
24962 arm_convert_symbolic_attribute (const char *name)
24964 static const struct
24969 attribute_table[] =
24971 /* When you modify this table you should
24972 also modify the list in doc/c-arm.texi. */
24973 #define T(tag) {#tag, tag}
24974 T (Tag_CPU_raw_name),
24977 T (Tag_CPU_arch_profile),
24978 T (Tag_ARM_ISA_use),
24979 T (Tag_THUMB_ISA_use),
24983 T (Tag_Advanced_SIMD_arch),
24984 T (Tag_PCS_config),
24985 T (Tag_ABI_PCS_R9_use),
24986 T (Tag_ABI_PCS_RW_data),
24987 T (Tag_ABI_PCS_RO_data),
24988 T (Tag_ABI_PCS_GOT_use),
24989 T (Tag_ABI_PCS_wchar_t),
24990 T (Tag_ABI_FP_rounding),
24991 T (Tag_ABI_FP_denormal),
24992 T (Tag_ABI_FP_exceptions),
24993 T (Tag_ABI_FP_user_exceptions),
24994 T (Tag_ABI_FP_number_model),
24995 T (Tag_ABI_align_needed),
24996 T (Tag_ABI_align8_needed),
24997 T (Tag_ABI_align_preserved),
24998 T (Tag_ABI_align8_preserved),
24999 T (Tag_ABI_enum_size),
25000 T (Tag_ABI_HardFP_use),
25001 T (Tag_ABI_VFP_args),
25002 T (Tag_ABI_WMMX_args),
25003 T (Tag_ABI_optimization_goals),
25004 T (Tag_ABI_FP_optimization_goals),
25005 T (Tag_compatibility),
25006 T (Tag_CPU_unaligned_access),
25007 T (Tag_FP_HP_extension),
25008 T (Tag_VFP_HP_extension),
25009 T (Tag_ABI_FP_16bit_format),
25010 T (Tag_MPextension_use),
25012 T (Tag_nodefaults),
25013 T (Tag_also_compatible_with),
25014 T (Tag_conformance),
25016 T (Tag_Virtualization_use),
25017 /* We deliberately do not include Tag_MPextension_use_legacy. */
25025 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25026 if (streq (name, attribute_table[i].name))
25027 return attribute_table[i].tag;
25033 /* Apply sym value for relocations only in the case that
25034 they are for local symbols and you have the respective
25035 architectural feature for blx and simple switches. */
25037 arm_apply_sym_value (struct fix * fixP)
25040 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25041 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25043 switch (fixP->fx_r_type)
25045 case BFD_RELOC_ARM_PCREL_BLX:
25046 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25047 if (ARM_IS_FUNC (fixP->fx_addsy))
25051 case BFD_RELOC_ARM_PCREL_CALL:
25052 case BFD_RELOC_THUMB_PCREL_BLX:
25053 if (THUMB_IS_FUNC (fixP->fx_addsy))
25064 #endif /* OBJ_ELF */