1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used;
136 static arm_feature_set thumb_arch_used;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26 = FALSE;
140 static int atpcs = FALSE;
141 static int support_interwork = FALSE;
142 static int uses_apcs_float = FALSE;
143 static int pic_code = FALSE;
144 static int fix_v4bx = FALSE;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated = TRUE;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax = FALSE;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set *legacy_cpu = NULL;
158 static const arm_feature_set *legacy_fpu = NULL;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set *mcpu_cpu_opt = NULL;
162 static arm_feature_set *mcpu_ext_opt = NULL;
163 static const arm_feature_set *mcpu_fpu_opt = NULL;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set *march_cpu_opt = NULL;
167 static arm_feature_set *march_ext_opt = NULL;
168 static const arm_feature_set *march_fpu_opt = NULL;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set *mfpu_opt = NULL;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default = FPU_DEFAULT;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
176 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
179 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
182 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
184 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
187 static const arm_feature_set cpu_default = CPU_DEFAULT;
190 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
191 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
192 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
198 static const arm_feature_set arm_ext_v4t_5 =
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
210 static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212 static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214 static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216 static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
225 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
226 static const arm_feature_set arm_ext_m =
227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
229 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
234 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
235 static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
236 static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
238 static const arm_feature_set arm_ext_v8_1m_main =
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
243 static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
253 static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
258 static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
260 static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
262 static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
264 static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
266 static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
269 static const arm_feature_set arm_arch_any = ARM_ANY;
271 static const arm_feature_set fpu_any = FPU_ANY;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
277 static const arm_feature_set arm_cext_iwmmxt2 =
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
279 static const arm_feature_set arm_cext_iwmmxt =
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
281 static const arm_feature_set arm_cext_xscale =
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
283 static const arm_feature_set arm_cext_maverick =
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285 static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287 static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
289 static const arm_feature_set fpu_vfp_ext_v1xd =
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291 static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293 static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295 static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297 static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
299 static const arm_feature_set fpu_vfp_ext_d32 =
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301 static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
305 static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307 static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
310 static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312 static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
315 static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
317 static const arm_feature_set fpu_vfp_ext_armv8 =
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
319 static const arm_feature_set fpu_vfp_ext_armv8xd =
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
321 static const arm_feature_set fpu_neon_ext_armv8 =
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
323 static const arm_feature_set fpu_crypto_ext_armv8 =
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
325 static const arm_feature_set crc_ext_armv8 =
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
327 static const arm_feature_set fpu_neon_ext_v8_1 =
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
329 static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
332 static int mfloat_abi_opt = -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch = ARM_ARCH_NONE;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext = ARM_ARCH_NONE;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu = FPU_NONE;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name[20];
350 extern FLONUM_TYPE generic_floating_point_number;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
361 static int meabi_flags = EABI_DEFAULT;
363 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
366 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS * GOT_symbol;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode = 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
398 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax = FALSE;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars[] = "#[]{}";
444 enum neon_el_type type;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type;
500 } relocs[ARM_IT_MAX_RELOCS];
502 enum pred_instruction_type pred_insn_type;
508 struct neon_type_el vectype;
509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad : 1; /* Operand is SIMD quad register. */
524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
525 unsigned iszr : 1; /* Operand is ZR register. */
526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
533 } operands[ARM_IT_MAX_OPERANDS];
536 static struct arm_it inst;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name;
569 #define COND_ALWAYS 0xE
573 const char * template_name;
577 struct asm_barrier_opt
579 const char * template_name;
581 const arm_feature_set arch;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc;
601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined;
618 struct neon_type_el eltype;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs[] =
669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name;
711 /* Parameters to instruction. */
712 unsigned int operands[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control * arm_ops_hsh;
906 static struct hash_control * arm_cond_hsh;
907 static struct hash_control * arm_vcond_hsh;
908 static struct hash_control * arm_shift_hsh;
909 static struct hash_control * arm_psr_hsh;
910 static struct hash_control * arm_v7m_psr_hsh;
911 static struct hash_control * arm_reg_hsh;
912 static struct hash_control * arm_reloc_hsh;
913 static struct hash_control * arm_barrier_opt_hsh;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS * last_label_seen;
925 static int label_is_thumb_function_name = FALSE;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
942 struct literal_pool * next;
943 unsigned int alignment;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool * list_of_pools = NULL;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME,
956 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred;
965 now_pred_compatible (int cond)
967 return (cond & ~1) == (now_pred.cc & ~1);
971 conditional_insn (void)
973 return inst.cond != COND_ALWAYS;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars[] = "#";
1027 char arm_line_separator_chars[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str, char c)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS * sp)
1071 if (symbol_get_value_expression (sp)->X_op == O_big)
1074 if (symbol_get_value_expression (sp)->X_add_symbol)
1076 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1077 || (symbol_get_value_expression (sp)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1084 static bfd_boolean in_my_get_expression = FALSE;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1104 switch (prefix_mode)
1106 case GE_NO_PREFIX: break;
1108 if (!is_immediate_prefix (**str))
1110 inst.error = _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG:
1117 if (is_immediate_prefix (**str))
1124 memset (ep, 0, sizeof (expressionS));
1126 save_in = input_line_pointer;
1127 input_line_pointer = *str;
1128 in_my_get_expression = TRUE;
1130 in_my_get_expression = FALSE;
1132 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str = input_line_pointer;
1136 input_line_pointer = save_in;
1137 if (inst.error == NULL)
1138 inst.error = (ep->X_op == O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode != GE_OPT_PREFIX_BIG
1147 && (ep->X_op == O_big
1148 || (ep->X_add_symbol
1149 && (walk_no_bignums (ep->X_add_symbol)
1151 && walk_no_bignums (ep->X_op_symbol))))))
1153 inst.error = _("invalid constant");
1154 *str = input_line_pointer;
1155 input_line_pointer = save_in;
1159 *str = input_line_pointer;
1160 input_line_pointer = save_in;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type, char * litP, int * sizeP)
1182 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t = atof_ieee (input_line_pointer, type, words);
1219 input_line_pointer = t;
1220 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1222 if (target_big_endian)
1224 for (i = 0; i < prec; i++)
1226 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1227 litP += sizeof (LITTLENUM_TYPE);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1233 for (i = prec - 1; i >= 0; i--)
1235 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1236 litP += sizeof (LITTLENUM_TYPE);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i = 0; i < prec; i += 2)
1243 md_number_to_chars (litP, (valueT) words[i + 1],
1244 sizeof (LITTLENUM_TYPE));
1245 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1246 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1247 litP += 2 * sizeof (LITTLENUM_TYPE);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS * exp)
1260 if (in_my_get_expression)
1261 exp->X_op = O_illegal;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val)
1275 exp.X_op = O_illegal;
1277 if (is_immediate_prefix (*input_line_pointer))
1279 input_line_pointer++;
1283 if (exp.X_op != O_constant)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val = exp.X_add_number;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry *
1302 arm_reg_parse_multi (char **ccp)
1306 struct reg_entry *reg;
1308 skip_whitespace (start);
1310 #ifdef REGISTER_PREFIX
1311 if (*start != REGISTER_PREFIX)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start == OPTIONAL_REGISTER_PREFIX)
1321 if (!ISALPHA (*p) || !is_name_beginner (*p))
1326 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1328 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1338 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1339 enum arm_reg_type type)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg && reg->type == REG_TYPE_CN)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor = strtoul (start, ccp, 10);
1357 if (*ccp != start && processor <= 15)
1362 case REG_TYPE_MMXWC:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg && reg->type == REG_TYPE_MMXWCG)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp, enum arm_reg_type type)
1383 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1390 if (reg && reg->type == type)
1393 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type *type, char **str)
1422 while (type->elems < NEON_MAX_TYPE_ELS)
1424 enum neon_el_type thistype = NT_untyped;
1425 unsigned thissize = -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr))
1438 case 'i': thistype = NT_integer; break;
1439 case 'f': thistype = NT_float; break;
1440 case 'p': thistype = NT_poly; break;
1441 case 's': thistype = NT_signed; break;
1442 case 'u': thistype = NT_unsigned; break;
1444 thistype = NT_float;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype == NT_float && !ISDIGIT (*ptr))
1461 thissize = strtoul (ptr, &ptr, 10);
1463 if (thissize != 8 && thissize != 16 && thissize != 32
1466 as_bad (_("bad size %d in type specifier"), thissize);
1474 type->el[type->elems].type = thistype;
1475 type->el[type->elems].size = thissize;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type->elems == 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1506 struct neon_type optype;
1510 if (parse_neon_type (&optype, &str) == SUCCESS)
1512 if (optype.elems == 1)
1513 *vectype = optype.el[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set *feature)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set *feature)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1559 && ARM_CPU_IS_ANY (cpu_variant))
1561 first_error (BAD_MVE_AUTO);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1582 enum arm_reg_type *rtype,
1583 struct neon_typed_alias *typeinfo)
1586 struct reg_entry *reg = arm_reg_parse_multi (&str);
1587 struct neon_typed_alias atype;
1588 struct neon_type_el parsetype;
1592 atype.eltype.type = NT_invtype;
1593 atype.eltype.size = -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type == REG_TYPE_NDQ
1609 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1610 || (type == REG_TYPE_VFSD
1611 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1612 || (type == REG_TYPE_NSDQ
1613 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1614 || reg->type == REG_TYPE_NQ))
1615 || (type == REG_TYPE_NSD
1616 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1617 || (type == REG_TYPE_MMXWC
1618 && (reg->type == REG_TYPE_MMXWCG)))
1619 type = (enum arm_reg_type) reg->type;
1621 if (type == REG_TYPE_MQ)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1626 if (!reg || reg->type != REG_TYPE_NQ)
1629 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1637 && (type == REG_TYPE_NQ))
1641 if (type != reg->type)
1647 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1649 if ((atype.defined & NTA_HASTYPE) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype.defined |= NTA_HASTYPE;
1655 atype.eltype = parsetype;
1658 if (skip_past_char (&str, '[') == SUCCESS)
1660 if (type != REG_TYPE_VFD
1661 && !(type == REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1663 && !(type == REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype.defined & NTA_HASINDEX) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype.defined |= NTA_HASINDEX;
1681 if (skip_past_char (&str, ']') == SUCCESS)
1682 atype.index = NEON_ALL_LANES;
1687 my_get_expression (&exp, &str, GE_NO_PREFIX);
1689 if (exp.X_op != O_constant)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str, ']') == FAIL)
1698 atype.index = exp.X_add_number;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1722 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1724 struct neon_typed_alias atype;
1726 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype.defined & NTA_HASINDEX) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype = atype.eltype;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1759 arm_reg_type reg_type)
1763 struct neon_typed_alias atype;
1766 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1784 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1787 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
1789 first_error (_("scalar must have an index"));
1792 else if (atype.index >= reg_size / elsize)
1794 first_error (_("scalar index out of range"));
1799 *type = atype.eltype;
1803 return reg * 16 + atype.index;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp, enum reg_list_els etype)
1828 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str);
1846 const char apsr_str[] = "apsr";
1847 int apsr_str_len = strlen (apsr_str);
1849 reg = arm_reg_parse (&str, REGLIST_RN);
1850 if (etype == REGLIST_CLRM)
1852 if (reg == REG_SP || reg == REG_PC)
1854 else if (reg == FAIL
1855 && !strncasecmp (str, apsr_str, apsr_str_len)
1856 && !ISALPHA (*(str + apsr_str_len)))
1859 str += apsr_str_len;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs[REGLIST_RN]));
1883 first_error (_("bad range in register list"));
1887 for (i = cur_reg + 1; i < reg; i++)
1889 if (range & (1 << i))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range & (1 << reg))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg <= cur_reg)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str) != FAIL
1909 || (in_range = 1, *str++ == '-'));
1912 if (skip_past_char (&str, '}') == FAIL)
1914 first_error (_("missing `}'"));
1918 else if (etype == REGLIST_RN)
1922 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1925 if (exp.X_op == O_constant)
1927 if (exp.X_add_number
1928 != (exp.X_add_number & 0x0000ffff))
1930 inst.error = _("invalid register mask");
1934 if ((range & exp.X_add_number) != 0)
1936 int regno = range & exp.X_add_number;
1939 regno = (1 << regno) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range |= exp.X_add_number;
1949 if (inst.relocs[0].type != 0)
1951 inst.error = _("expression too complex");
1955 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1956 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1957 inst.relocs[0].pc_rel = 0;
1961 if (*str == '|' || *str == '+')
1967 while (another_range);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
1990 bfd_boolean *partial_match)
1995 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1999 unsigned long mask = 0;
2001 bfd_boolean vpr_seen = FALSE;
2002 bfd_boolean expect_vpr =
2003 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
2005 if (skip_past_char (&str, '{') == FAIL)
2007 inst.error = _("expecting {");
2014 case REGLIST_VFP_S_VPR:
2015 regtype = REG_TYPE_VFS;
2020 case REGLIST_VFP_D_VPR:
2021 regtype = REG_TYPE_VFD;
2024 case REGLIST_NEON_D:
2025 regtype = REG_TYPE_NDQ;
2032 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2049 base_reg = max_regs;
2050 *partial_match = FALSE;
2054 int setmask = 1, addregs = 1;
2055 const char vpr_str[] = "vpr";
2056 int vpr_str_len = strlen (vpr_str);
2058 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
2062 if (new_base == FAIL
2063 && !strncasecmp (str, vpr_str, vpr_str_len)
2064 && !ISALPHA (*(str + vpr_str_len))
2070 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base == FAIL)
2079 if (regtype == REG_TYPE_VFS)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base == FAIL)
2090 first_error (_(reg_expected_msgs[regtype]));
2094 *partial_match = TRUE;
2098 if (new_base >= max_regs)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype == REG_TYPE_NQ)
2111 if (new_base < base_reg)
2112 base_reg = new_base;
2114 if (mask & (setmask << new_base))
2116 first_error (_("invalid register list"));
2120 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask |= setmask << new_base;
2129 if (*str == '-') /* We have the start of a range expression */
2135 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
2138 inst.error = gettext (reg_expected_msgs[regtype]);
2142 if (high_range >= max_regs)
2144 first_error (_("register out of range in list"));
2148 if (regtype == REG_TYPE_NQ)
2149 high_range = high_range + 1;
2151 if (high_range <= new_base)
2153 inst.error = _("register range not in ascending order");
2157 for (new_base += addregs; new_base <= high_range; new_base += addregs)
2159 if (mask & (setmask << new_base))
2161 inst.error = _("invalid register list");
2165 mask |= setmask << new_base;
2170 while (skip_past_comma (&str) != FAIL);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen && count == 0) || count > max_regs)
2180 if (expect_vpr && !vpr_seen)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i = 0; i < count; i++)
2190 if ((mask & (1u << i)) == 0)
2192 inst.error = _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2213 if (a->defined != b->defined)
2216 if ((a->defined & NTA_HASTYPE) != 0
2217 && (a->eltype.type != b->eltype.type
2218 || a->eltype.size != b->eltype.size))
2221 if ((a->defined & NTA_HASINDEX) != 0
2222 && (a->index != b->index))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str, unsigned *pbase,
2243 struct neon_type_el *eltype)
2250 int leading_brace = 0;
2251 enum arm_reg_type rtype = REG_TYPE_NDQ;
2252 const char *const incr_error = mve ? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error = _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype;
2256 firsttype.defined = 0;
2257 firsttype.eltype.type = NT_invtype;
2258 firsttype.eltype.size = -1;
2259 firsttype.index = -1;
2261 if (skip_past_char (&ptr, '{') == SUCCESS)
2266 struct neon_typed_alias atype;
2268 rtype = REG_TYPE_MQ;
2269 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2273 first_error (_(reg_expected_msgs[rtype]));
2280 if (rtype == REG_TYPE_NQ)
2286 else if (reg_incr == -1)
2288 reg_incr = getreg - base_reg;
2289 if (reg_incr < 1 || reg_incr > 2)
2291 first_error (_(incr_error));
2295 else if (getreg != base_reg + reg_incr * count)
2297 first_error (_(incr_error));
2301 if (! neon_alias_types_same (&atype, &firsttype))
2303 first_error (_(type_error));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype;
2312 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2314 lane = NEON_INTERLEAVE_LANES;
2315 else if (lane != NEON_INTERLEAVE_LANES)
2317 first_error (_(type_error));
2322 else if (reg_incr != 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2331 first_error (_(reg_expected_msgs[rtype]));
2334 if (! neon_alias_types_same (&htype, &firsttype))
2336 first_error (_(type_error));
2339 count += hireg + dregs - getreg;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype == REG_TYPE_NQ)
2350 if ((atype.defined & NTA_HASINDEX) != 0)
2354 else if (lane != atype.index)
2356 first_error (_(type_error));
2360 else if (lane == -1)
2361 lane = NEON_INTERLEAVE_LANES;
2362 else if (lane != NEON_INTERLEAVE_LANES)
2364 first_error (_(type_error));
2369 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane = NEON_INTERLEAVE_LANES;
2376 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
2377 || (count > 1 && reg_incr == -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2385 first_error (_("expected }"));
2393 *eltype = firsttype.eltype;
2398 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str)
2410 struct reloc_entry *r;
2414 return BFD_RELOC_UNUSED;
2419 while (*q && *q != ')' && *q != ',')
2424 if ((r = (struct reloc_entry *)
2425 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2432 /* Directives: register aliases. */
2434 static struct reg_entry *
2435 insert_reg_alias (char *str, unsigned number, int type)
2437 struct reg_entry *new_reg;
2440 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2442 if (new_reg->builtin)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg->number != number || new_reg->type != type)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2453 name = xstrdup (str);
2454 new_reg = XNEW (struct reg_entry);
2456 new_reg->name = name;
2457 new_reg->number = number;
2458 new_reg->type = type;
2459 new_reg->builtin = FALSE;
2460 new_reg->neon = NULL;
2462 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2469 insert_neon_reg_alias (char *str, int number, int type,
2470 struct neon_typed_alias *atype)
2472 struct reg_entry *reg = insert_reg_alias (str, number, type);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg->neon = XNEW (struct neon_typed_alias);
2483 *reg->neon = *atype;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname, char *p)
2497 struct reg_entry *old;
2498 char *oldname, *nbuf;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname, " .req ", 6) != 0)
2508 if (*oldname == '\0')
2511 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname = original_case_string;
2525 nlen = strlen (newname);
2528 nbuf = xmemdup0 (newname, nlen);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2535 for (p = nbuf; *p; p++)
2538 if (strncmp (nbuf, newname, nlen))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2556 for (p = nbuf; *p; p++)
2559 if (strncmp (nbuf, newname, nlen))
2560 insert_reg_alias (nbuf, old->number, old->type);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname, char *p)
2580 enum arm_reg_type basetype;
2581 struct reg_entry *basereg;
2582 struct reg_entry mybasereg;
2583 struct neon_type ntype;
2584 struct neon_typed_alias typeinfo;
2585 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2588 typeinfo.defined = 0;
2589 typeinfo.eltype.type = NT_invtype;
2590 typeinfo.eltype.size = -1;
2591 typeinfo.index = -1;
2595 if (strncmp (p, " .dn ", 5) == 0)
2596 basetype = REG_TYPE_VFD;
2597 else if (strncmp (p, " .qn ", 5) == 0)
2598 basetype = REG_TYPE_NQ;
2607 basereg = arm_reg_parse_multi (&p);
2609 if (basereg && basereg->type != basetype)
2611 as_bad (_("bad type for register"));
2615 if (basereg == NULL)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp, &p, GE_NO_PREFIX);
2620 if (exp.X_op != O_constant)
2622 as_bad (_("expression must be constant"));
2625 basereg = &mybasereg;
2626 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2632 typeinfo = *basereg->neon;
2634 if (parse_neon_type (&ntype, &p) == SUCCESS)
2636 /* We got a type. */
2637 if (typeinfo.defined & NTA_HASTYPE)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo.defined |= NTA_HASTYPE;
2644 if (ntype.elems != 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo.eltype = ntype.el[0];
2652 if (skip_past_char (&p, '[') == SUCCESS)
2655 /* We got a scalar index. */
2657 if (typeinfo.defined & NTA_HASINDEX)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp, &p, GE_NO_PREFIX);
2665 if (exp.X_op != O_constant)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo.defined |= NTA_HASINDEX;
2672 typeinfo.index = exp.X_add_number;
2674 if (skip_past_char (&p, ']') == FAIL)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen = nameend - newname;
2687 newname = original_case_string;
2688 namelen = strlen (newname);
2691 namebuf = xmemdup0 (newname, namelen);
2693 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2694 typeinfo.defined != 0 ? &typeinfo : NULL);
2696 /* Insert name in all uppercase. */
2697 for (p = namebuf; *p; p++)
2700 if (strncmp (namebuf, newname, namelen))
2701 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2702 typeinfo.defined != 0 ? &typeinfo : NULL);
2704 /* Insert name in all lowercase. */
2705 for (p = namebuf; *p; p++)
2708 if (strncmp (namebuf, newname, namelen))
2709 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2710 typeinfo.defined != 0 ? &typeinfo : NULL);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED)
2749 name = input_line_pointer;
2751 while (*input_line_pointer != 0
2752 && *input_line_pointer != ' '
2753 && *input_line_pointer != '\n')
2754 ++input_line_pointer;
2756 saved_char = *input_line_pointer;
2757 *input_line_pointer = 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2767 as_bad (_("unknown register alias '%s'"), name);
2768 else if (reg->builtin)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh, name, FALSE);
2777 free ((char *) reg->name);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf = strdup (name);
2787 for (p = nbuf; *p; p++)
2789 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2792 hash_delete (arm_reg_hsh, nbuf, FALSE);
2793 free ((char *) reg->name);
2799 for (p = nbuf; *p; p++)
2801 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2804 hash_delete (arm_reg_hsh, nbuf, FALSE);
2805 free ((char *) reg->name);
2815 *input_line_pointer = saved_char;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2833 const char * symname;
2840 type = BSF_NO_FLAGS;
2844 type = BSF_NO_FLAGS;
2848 type = BSF_NO_FLAGS;
2854 symbolP = symbol_new (symname, now_seg, value, frag);
2855 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2860 THUMB_SET_FUNC (symbolP, 0);
2861 ARM_SET_THUMB (symbolP, 0);
2862 ARM_SET_INTERWORK (symbolP, support_interwork);
2866 THUMB_SET_FUNC (symbolP, 1);
2867 ARM_SET_THUMB (symbolP, 1);
2868 ARM_SET_INTERWORK (symbolP, support_interwork);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag->tc_frag_data.first_map != NULL)
2889 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2890 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2892 frag->tc_frag_data.first_map = symbolP;
2894 if (frag->tc_frag_data.last_map != NULL)
2896 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2897 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2898 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2900 frag->tc_frag_data.last_map = symbolP;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state,
2909 valueT value, fragS *frag, offsetT bytes)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag->tc_frag_data.last_map != NULL
2913 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2915 symbolS *symp = frag->tc_frag_data.last_map;
2919 know (frag->tc_frag_data.first_map == symp);
2920 frag->tc_frag_data.first_map = NULL;
2922 frag->tc_frag_data.last_map = NULL;
2923 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2926 make_mapping_symbol (MAP_DATA, value, frag);
2927 make_mapping_symbol (state, value + bytes, frag);
2930 static void mapping_state_2 (enum mstate state, int max_chars);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state)
2939 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2941 if (mapstate == state)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state == MAP_ARM || state == MAP_THUMB)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state, int max_chars)
2975 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2977 if (!SEG_NORMAL (now_seg))
2980 if (mapstate == state)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2986 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2988 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2989 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2995 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2996 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS * symbolP)
3011 const char * name = S_GET_NAME (symbolP);
3012 symbolS * new_target;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP) || name[0] == '.')
3028 real_start = concat (STUB_NAME, name, NULL);
3029 new_target = symbol_find (real_start);
3032 if (new_target == NULL)
3034 as_warn (_("Failed to find real start of function: %s\n"), name);
3035 new_target = symbolP;
3043 opcode_select (int width)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width);
3081 s_arm (int ignore ATTRIBUTE_UNUSED)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED)
3099 temp = get_absolute_expression ();
3104 opcode_select (temp);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name = TRUE;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim = get_symbol_name (& name);
3157 end_name = input_line_pointer;
3158 (void) restore_line_pointer (delim);
3160 if (*input_line_pointer != ',')
3163 as_bad (_("expected comma after name \"%s\""), name);
3165 ignore_rest_of_line ();
3169 input_line_pointer++;
3172 if (name[0] == '.' && name[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP = symbol_find (name)) == NULL
3179 && (symbolP = md_undefined_symbol (name)) == NULL)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing & LISTING_SYMBOLS)
3187 extern struct list_info_struct * listing_tail;
3188 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
3190 memset (dummy_frag, 0, sizeof (fragS));
3191 dummy_frag->fr_type = rs_fill;
3192 dummy_frag->line = listing_tail;
3193 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3194 dummy_frag->fr_symbol = symbolP;
3198 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP);
3211 && S_IS_DEFINED (symbolP)
3212 && S_GET_SEGMENT (symbolP) != reg_section)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3215 pseudo_set (symbolP);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP, 1);
3222 ARM_SET_THUMB (symbolP, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP, support_interwork);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED)
3238 delim = get_symbol_name (& name);
3240 if (!strcasecmp (name, "unified"))
3241 unified_syntax = TRUE;
3242 else if (!strcasecmp (name, "divided"))
3243 unified_syntax = FALSE;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name);
3249 (void) restore_line_pointer (delim);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3286 if (codecomposer_syntax)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name)
3297 static const char * last_name = NULL;
3301 gas_assert (last_name == NULL);
3304 if (debug_type == DEBUG_STABS)
3305 stabs_generate_asm_func (name, name);
3309 gas_assert (last_name != NULL);
3311 if (debug_type == DEBUG_STABS)
3312 stabs_generate_asm_endfunc (last_name, last_name);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3321 if (codecomposer_syntax)
3323 switch (asmfunc_state)
3325 case OUTSIDE_ASMFUNC:
3326 asmfunc_state = WAITING_ASMFUNC_NAME;
3329 case WAITING_ASMFUNC_NAME:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3346 if (codecomposer_syntax)
3348 switch (asmfunc_state)
3350 case OUTSIDE_ASMFUNC:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC:
3359 asmfunc_state = OUTSIDE_ASMFUNC;
3360 asmfunc_debug (NULL);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name)
3372 if (codecomposer_syntax)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool *
3381 find_literal_pool (void)
3383 literal_pool * pool;
3385 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3387 if (pool->section == now_seg
3388 && pool->sub_section == now_subseg)
3395 static literal_pool *
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num = 1;
3400 literal_pool * pool;
3402 pool = find_literal_pool ();
3406 /* Create a new pool. */
3407 pool = XNEW (literal_pool);
3411 pool->next_free_entry = 0;
3412 pool->section = now_seg;
3413 pool->sub_section = now_subseg;
3414 pool->next = list_of_pools;
3415 pool->symbol = NULL;
3416 pool->alignment = 2;
3418 /* Add it to the list. */
3419 list_of_pools = pool;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool->symbol == NULL)
3425 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3426 (valueT) 0, &zero_address_frag);
3427 pool->id = latest_pool_num ++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool * pool;
3443 unsigned int entry, pool_size = 0;
3444 bfd_boolean padding_slot_p = FALSE;
3450 imm1 = inst.operands[1].imm;
3451 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3452 : inst.relocs[0].exp.X_unsigned ? 0
3453 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3454 if (target_big_endian)
3457 imm2 = inst.operands[1].imm;
3461 pool = find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry = 0; entry < pool->next_free_entry; entry ++)
3468 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3469 && (inst.relocs[0].exp.X_op == O_constant)
3470 && (pool->literals[entry].X_add_number
3471 == inst.relocs[0].exp.X_add_number)
3472 && (pool->literals[entry].X_md == nbytes)
3473 && (pool->literals[entry].X_unsigned
3474 == inst.relocs[0].exp.X_unsigned))
3477 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3478 && (inst.relocs[0].exp.X_op == O_symbol)
3479 && (pool->literals[entry].X_add_number
3480 == inst.relocs[0].exp.X_add_number)
3481 && (pool->literals[entry].X_add_symbol
3482 == inst.relocs[0].exp.X_add_symbol)
3483 && (pool->literals[entry].X_op_symbol
3484 == inst.relocs[0].exp.X_op_symbol)
3485 && (pool->literals[entry].X_md == nbytes))
3488 else if ((nbytes == 8)
3489 && !(pool_size & 0x7)
3490 && ((entry + 1) != pool->next_free_entry)
3491 && (pool->literals[entry].X_op == O_constant)
3492 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3493 && (pool->literals[entry].X_unsigned
3494 == inst.relocs[0].exp.X_unsigned)
3495 && (pool->literals[entry + 1].X_op == O_constant)
3496 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3497 && (pool->literals[entry + 1].X_unsigned
3498 == inst.relocs[0].exp.X_unsigned))
3501 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3502 if (padding_slot_p && (nbytes == 4))
3508 /* Do we need to create a new entry? */
3509 if (entry == pool->next_free_entry)
3511 if (entry >= MAX_LITERAL_POOL_SIZE)
3513 inst.error = _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst.relocs[0].exp.X_op == O_constant
3531 || inst.relocs[0].exp.X_op == O_big))
3533 inst.error = _("invalid type for literal pool");
3536 else if (pool_size & 0x7)
3538 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3540 inst.error = _("literal pool overflow");
3544 pool->literals[entry] = inst.relocs[0].exp;
3545 pool->literals[entry].X_op = O_constant;
3546 pool->literals[entry].X_add_number = 0;
3547 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3548 pool->next_free_entry += 1;
3551 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3553 inst.error = _("literal pool overflow");
3557 pool->literals[entry] = inst.relocs[0].exp;
3558 pool->literals[entry].X_op = O_constant;
3559 pool->literals[entry].X_add_number = imm1;
3560 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3561 pool->literals[entry++].X_md = 4;
3562 pool->literals[entry] = inst.relocs[0].exp;
3563 pool->literals[entry].X_op = O_constant;
3564 pool->literals[entry].X_add_number = imm2;
3565 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3566 pool->literals[entry].X_md = 4;
3567 pool->alignment = 3;
3568 pool->next_free_entry += 1;
3572 pool->literals[entry] = inst.relocs[0].exp;
3573 pool->literals[entry].X_md = 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type == DEBUG_DWARF2)
3582 dwarf2_where (pool->locs + entry);
3584 pool->next_free_entry += 1;
3586 else if (padding_slot_p)
3588 pool->literals[entry] = inst.relocs[0].exp;
3589 pool->literals[entry].X_md = nbytes;
3592 inst.relocs[0].exp.X_op = O_symbol;
3593 inst.relocs[0].exp.X_add_number = pool_size;
3594 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret = TRUE;
3604 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3606 const char *label = input_line_pointer;
3608 while (!is_end_of_line[(int) label[-1]])
3613 as_bad (_("Invalid label '%s'"), label);
3617 asmfunc_debug (label);
3619 asmfunc_state = WAITING_ENDASMFUNC;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS * symbolP,
3630 const char * name, /* It is copied, the caller can modify. */
3631 segT segment, /* Segment identifier (SEG_<something>). */
3632 valueT valu, /* Symbol value. */
3633 fragS * frag) /* Associated fragment. */
3636 char * preserved_copy_of_name;
3638 name_length = strlen (name) + 1; /* +1 for \0. */
3639 obstack_grow (¬es, name, name_length);
3640 preserved_copy_of_name = (char *) obstack_finish (¬es);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name =
3644 tc_canonicalize_symbol_name (preserved_copy_of_name);
3647 S_SET_NAME (symbolP, preserved_copy_of_name);
3649 S_SET_SEGMENT (symbolP, segment);
3650 S_SET_VALUE (symbolP, valu);
3651 symbol_clear_list_pointers (symbolP);
3653 symbol_set_frag (symbolP, frag);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen;
3659 if (symbol_table_frozen)
3663 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3665 obj_symbol_new_hook (symbolP);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP);
3672 verify_symbol_chain (symbol_rootP, symbol_lastP);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3680 literal_pool * pool;
3683 pool = find_literal_pool ();
3685 || pool->symbol == NULL
3686 || pool->next_free_entry == 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool->alignment, 0, 0);
3694 record_alignment (now_seg, 2);
3697 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3698 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3700 sprintf (sym_name, "$$lit_\002%x", pool->id);
3702 symbol_locate (pool->symbol, sym_name, now_seg,
3703 (valueT) frag_now_fix (), frag_now);
3704 symbol_table_insert (pool->symbol);
3706 ARM_SET_THUMB (pool->symbol, thumb_mode);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3712 for (entry = 0; entry < pool->next_free_entry; entry ++)
3715 if (debug_type == DEBUG_DWARF2)
3716 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool->literals[entry]),
3720 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3723 /* Mark the pool as empty. */
3724 pool->next_free_entry = 0;
3725 pool->symbol = NULL;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3732 static valueT create_unwind_entry (int);
3733 static void start_unwind_section (const segT, int);
3734 static void add_unwind_opcode (valueT, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes);
3758 mapping_state (MAP_DATA);
3762 char *base = input_line_pointer;
3766 if (exp.X_op != O_symbol)
3767 emit_expr (&exp, (unsigned int) nbytes);
3770 char *before_reloc = input_line_pointer;
3771 reloc = parse_reloc (&input_line_pointer);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc == BFD_RELOC_UNUSED)
3779 emit_expr (&exp, (unsigned int) nbytes);
3782 reloc_howto_type *howto = (reloc_howto_type *)
3783 bfd_reloc_type_lookup (stdoutput,
3784 (bfd_reloc_code_real_type) reloc);
3785 int size = bfd_get_reloc_size (howto);
3787 if (reloc == BFD_RELOC_ARM_PLT32)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc = BFD_RELOC_UNUSED;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto->name, nbytes);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p = input_line_pointer;
3807 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3809 memcpy (save_buf, base, input_line_pointer - base);
3810 memmove (base + (input_line_pointer - before_reloc),
3811 base, before_reloc - base);
3813 input_line_pointer = base + (input_line_pointer-before_reloc);
3815 memcpy (base, save_buf, p - base);
3817 offset = nbytes - size;
3818 p = frag_more (nbytes);
3819 memset (p, 0, nbytes);
3820 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3821 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3827 while (*input_line_pointer++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer --;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS * exp)
3840 expressionS exp_high = *exp;
3842 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3843 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3844 exp->X_add_number &= 0xffff;
3845 emit_expr (exp, (unsigned int) THUMB_SIZE);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode)
3853 if ((unsigned int) opcode < 0xe800u)
3855 else if ((unsigned int) opcode >= 0xe8000000u)
3862 emit_insn (expressionS *exp, int nbytes)
3866 if (exp->X_op == O_constant)
3871 size = thumb_insn_size (exp->X_add_number);
3875 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3888 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3889 emit_thumb32_expr (exp);
3891 emit_expr (exp, (unsigned int) size);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM);
3943 if (! emit_insn (& exp, nbytes))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer --;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3966 if (*input_line_pointer == '1')
3967 highbit = 0x80000000;
3968 else if (*input_line_pointer != '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer++;
3972 if (*input_line_pointer != ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA);
3989 md_number_to_chars (p, highbit, 4);
3990 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3991 BFD_RELOC_ARM_PREL31);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4003 demand_empty_rest_of_line ();
4004 if (unwind.proc_start)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind.proc_start = expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind.opcode_count = 0;
4015 unwind.table_entry = NULL;
4016 unwind.personality_routine = NULL;
4017 unwind.personality_index = -1;
4018 unwind.frame_size = 0;
4019 unwind.fp_offset = 0;
4020 unwind.fp_reg = REG_SP;
4022 unwind.sp_restored = 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4032 demand_empty_rest_of_line ();
4033 if (!unwind.proc_start)
4034 as_bad (MISSING_FNSTART);
4036 if (unwind.table_entry)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4050 unsigned int marked_pr_dependency;
4052 demand_empty_rest_of_line ();
4054 if (!unwind.proc_start)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind.table_entry == NULL)
4062 val = create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind.saved_seg, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg, 2);
4071 ptr = frag_more (8);
4073 where = frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4077 BFD_RELOC_ARM_PREL31);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
4083 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4084 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4086 static const char *const name[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4093 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
4094 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
4095 |= 1 << unwind.personality_index;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr + 4, val, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4104 BFD_RELOC_ARM_PREL31);
4106 /* Restore the original section. */
4107 subseg_set (unwind.saved_seg, unwind.saved_subseg);
4109 unwind.proc_start = NULL;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4118 demand_empty_rest_of_line ();
4119 if (!unwind.proc_start)
4120 as_bad (MISSING_FNSTART);
4122 if (unwind.personality_routine || unwind.personality_index != -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind.personality_index = -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4136 if (!unwind.proc_start)
4137 as_bad (MISSING_FNSTART);
4139 if (unwind.personality_routine || unwind.personality_index != -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp.X_op != O_constant
4145 || exp.X_add_number < 0 || exp.X_add_number > 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind.personality_index = exp.X_add_number;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4165 if (!unwind.proc_start)
4166 as_bad (MISSING_FNSTART);
4168 if (unwind.personality_routine || unwind.personality_index != -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c = get_symbol_name (& name);
4172 p = input_line_pointer;
4174 ++ input_line_pointer;
4175 unwind.personality_routine = symbol_find_or_make (name);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind.sp_restored && unwind.fp_reg == 12
4204 && (range & 0x3000) == 0x1000)
4206 unwind.opcode_count--;
4207 unwind.sp_restored = 0;
4208 range = (range | 0x2000) & ~0x1000;
4209 unwind.pending_offset = 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n = 0; n < 8; n++)
4219 /* Break at the first non-saved register. */
4220 if ((range & (1 << (n + 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op = 0x8000 | ((range >> 4) & 0xfff);
4228 add_unwind_opcode (op, 2);
4232 /* Use the short form. */
4234 op = 0xa8; /* Pop r14. */
4236 op = 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op, 1);
4245 op = 0xb100 | (range & 0xf);
4246 add_unwind_opcode (op, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n = 0; n < 16; n++)
4252 if (range & (1 << n))
4253 unwind.frame_size += 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer) != FAIL)
4271 exp.X_op = O_illegal;
4273 if (exp.X_op != O_constant)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs = exp.X_add_number;
4282 if (num_regs < 1 || num_regs > 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op = 0xb4 | (num_regs - 1);
4295 add_unwind_opcode (op, 1);
4300 op = 0xc800 | (reg << 4) | (num_regs - 1);
4301 add_unwind_opcode (op, 2);
4303 unwind.frame_size += num_regs * 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs = 0;
4316 int num_regs_below_16;
4317 bfd_boolean partial_match;
4319 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs = count;
4336 else if (start + count > 16)
4337 num_vfpv3_regs = start + count - 16;
4339 if (num_vfpv3_regs > 0)
4341 int start_offset = start > 16 ? start - 16 : 0;
4342 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4343 add_unwind_opcode (op, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4348 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4349 if (num_regs_below_16 > 0)
4351 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4352 add_unwind_opcode (op, 2);
4355 unwind.frame_size += count * 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match;
4369 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op = 0xb8 | (count - 1);
4384 add_unwind_opcode (op, 1);
4389 op = 0xb300 | (reg << 4) | (count - 1);
4390 add_unwind_opcode (op, 2);
4392 unwind.frame_size += count * 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer == '{')
4408 input_line_pointer++;
4412 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4416 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer == '-')
4426 input_line_pointer++;
4427 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4430 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4433 else if (reg >= hi_reg)
4435 as_bad (_("bad register range"));
4438 for (; reg < hi_reg; reg++)
4442 while (skip_past_comma (&input_line_pointer) != FAIL);
4444 skip_past_char (&input_line_pointer, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i = 0; i < 16; i++)
4454 if (mask & (1 << i))
4455 unwind.frame_size += 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind.opcode_count > 0)
4463 i = unwind.opcodes[unwind.opcode_count - 1];
4464 if ((i & 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask & 0xfe00) == (1 << 9))
4472 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4473 unwind.opcode_count--;
4476 else if (i == 6 && unwind.opcode_count >= 2)
4478 i = unwind.opcodes[unwind.opcode_count - 2];
4482 op = 0xffff << (reg - 1);
4484 && ((mask & op) == (1u << (reg - 1))))
4486 op = (1 << (reg + i + 1)) - 1;
4487 op &= ~((1 << reg) - 1);
4489 unwind.opcode_count -= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg = 15; reg >= -1; reg--)
4500 /* Save registers in blocks. */
4502 || !(mask & (1 << reg)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op = 0xc0 | (hi_reg - 10);
4512 add_unwind_opcode (op, 1);
4517 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4518 add_unwind_opcode (op, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer == '{')
4539 input_line_pointer++;
4541 skip_whitespace (input_line_pointer);
4545 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4549 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer == '-')
4560 input_line_pointer++;
4561 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4564 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4567 else if (reg >= hi_reg)
4569 as_bad (_("bad register range"));
4572 for (; reg < hi_reg; reg++)
4576 while (skip_past_comma (&input_line_pointer) != FAIL);
4578 skip_past_char (&input_line_pointer, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg = 0; reg < 16; reg++)
4588 if (mask & (1 << reg))
4589 unwind.frame_size += 4;
4592 add_unwind_opcode (op, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6)
4606 struct reg_entry *reg;
4607 bfd_boolean had_brace = FALSE;
4609 if (!unwind.proc_start)
4610 as_bad (MISSING_FNSTART);
4612 /* Figure out what sort of save we have. */
4613 peek = input_line_pointer;
4621 reg = arm_reg_parse_multi (&peek);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer = peek;
4640 s_arm_unwind_save_fpa (reg->number);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4678 if (!unwind.proc_start)
4679 as_bad (MISSING_FNSTART);
4681 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4684 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer) != FAIL)
4692 if (immediate_for_directive (&offset) == FAIL)
4698 demand_empty_rest_of_line ();
4700 if (reg == REG_SP || reg == REG_PC)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind.fp_reg != REG_SP)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op, 1);
4713 /* Record the information for later. */
4714 unwind.fp_reg = reg;
4715 unwind.fp_offset = unwind.frame_size - offset;
4716 unwind.sp_restored = 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4726 if (!unwind.proc_start)
4727 as_bad (MISSING_FNSTART);
4729 if (immediate_for_directive (&offset) == FAIL)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind.frame_size += offset;
4741 unwind.pending_offset += offset;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4755 if (!unwind.proc_start)
4756 as_bad (MISSING_FNSTART);
4758 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4759 if (skip_past_comma (&input_line_pointer) == FAIL)
4762 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4764 if (fp_reg == FAIL || sp_reg == FAIL)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer) != FAIL)
4774 if (immediate_for_directive (&offset) == FAIL)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind.fp_reg = fp_reg;
4792 if (sp_reg == REG_SP)
4793 unwind.fp_offset = unwind.frame_size - offset;
4795 unwind.fp_offset -= offset;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4804 /* This is an arbitrary limit. */
4805 unsigned char op[16];
4808 if (!unwind.proc_start)
4809 as_bad (MISSING_FNSTART);
4812 if (exp.X_op == O_constant
4813 && skip_past_comma (&input_line_pointer) != FAIL)
4815 unwind.frame_size += exp.X_add_number;
4819 exp.X_op = O_illegal;
4821 if (exp.X_op != O_constant)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op[count++] = exp.X_add_number;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer) == FAIL)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op[count], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4866 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4868 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4869 attributes_set_explicitly[tag] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p = obstack_next_free (&frchain_now->frch_obstack);
4891 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4892 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4913 if (exp.X_op == O_symbol)
4914 exp.X_op = O_secrel;
4916 emit_expr (&exp, 4);
4918 while (*input_line_pointer++ == ',');
4920 input_line_pointer--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq, 0 },
4939 { "bss", s_bss, 0 },
4940 { "align", s_align_ptwo, 2 },
4941 { "arm", s_arm, 0 },
4942 { "thumb", s_thumb, 0 },
4943 { "code", s_code, 0 },
4944 { "force_thumb", s_force_thumb, 0 },
4945 { "thumb_func", s_thumb_func, 0 },
4946 { "thumb_set", s_thumb_set, 0 },
4947 { "even", s_even, 0 },
4948 { "ltorg", s_ltorg, 0 },
4949 { "pool", s_ltorg, 0 },
4950 { "syntax", s_syntax, 0 },
4951 { "cpu", s_arm_cpu, 0 },
4952 { "arch", s_arm_arch, 0 },
4953 { "object_arch", s_arm_object_arch, 0 },
4954 { "fpu", s_arm_fpu, 0 },
4955 { "arch_extension", s_arm_arch_extension, 0 },
4957 { "word", s_arm_elf_cons, 4 },
4958 { "long", s_arm_elf_cons, 4 },
4959 { "inst.n", s_arm_elf_inst, 2 },
4960 { "inst.w", s_arm_elf_inst, 4 },
4961 { "inst", s_arm_elf_inst, 0 },
4962 { "rel31", s_arm_rel31, 0 },
4963 { "fnstart", s_arm_unwind_fnstart, 0 },
4964 { "fnend", s_arm_unwind_fnend, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4966 { "personality", s_arm_unwind_personality, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4969 { "save", s_arm_unwind_save, 0 },
4970 { "vsave", s_arm_unwind_save, 1 },
4971 { "movsp", s_arm_unwind_movsp, 0 },
4972 { "pad", s_arm_unwind_pad, 0 },
4973 { "setfp", s_arm_unwind_setfp, 0 },
4974 { "unwind_raw", s_arm_unwind_raw, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file, 0 },
4986 { "loc", dwarf2_directive_loc, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4989 { "extend", float_cons, 'x' },
4990 { "ldouble", float_cons, 'x' },
4991 { "packed", float_cons, 'p' },
4993 {"secrel32", pe_directive_secrel, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref, 0},
4998 {"def", s_ccs_def, 0},
4999 {"asmfunc", s_ccs_asmfunc, 0},
5000 {"endasmfunc", s_ccs_endasmfunc, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str, int *val, int min, int max,
5015 bfd_boolean prefix_opt)
5019 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5020 if (exp.X_op != O_constant)
5022 inst.error = _("constant expression required");
5026 if (exp.X_add_number < min || exp.X_add_number > max)
5028 inst.error = _("immediate value out of range");
5032 *val = exp.X_add_number;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str, int i, expressionS *in_exp,
5042 bfd_boolean allow_symbol_p)
5045 expressionS *exp_p = in_exp ? in_exp : &exp;
5048 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5050 if (exp_p->X_op == O_constant)
5052 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5061 inst.operands[i].regisimm = 1;
5064 else if (exp_p->X_op == O_big
5065 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5067 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts != 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
5080 LITTLENUM_TYPE m = -1;
5082 if (generic_bignum[parts * 2] != 0
5083 && generic_bignum[parts * 2] != m)
5086 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
5087 if (generic_bignum[j] != generic_bignum[j-1])
5091 inst.operands[i].imm = 0;
5092 for (j = 0; j < parts; j++, idx++)
5093 inst.operands[i].imm |= generic_bignum[idx]
5094 << (LITTLENUM_NUMBER_OF_BITS * j);
5095 inst.operands[i].reg = 0;
5096 for (j = 0; j < parts; j++, idx++)
5097 inst.operands[i].reg |= generic_bignum[idx]
5098 << (LITTLENUM_NUMBER_OF_BITS * j);
5099 inst.operands[i].regisimm = 1;
5101 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str)
5115 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i = 0; fp_const[i]; i++)
5126 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
5130 *str += strlen (fp_const[i]);
5131 if (is_end_of_line[(unsigned char) **str])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
5144 /* Look for a raw floating point number. */
5145 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5146 && is_end_of_line[(unsigned char) *save_in])
5148 for (i = 0; i < NUM_FLOAT_VALS; i++)
5150 for (j = 0; j < MAX_LITTLENUMS; j++)
5152 if (words[j] != fp_values[i][j])
5156 if (j == MAX_LITTLENUMS)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in = input_line_pointer;
5167 input_line_pointer = *str;
5168 if (expression (&exp) == absolute_section
5169 && exp.X_op == O_big
5170 && exp.X_add_number < 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
5178 for (i = 0; i < NUM_FLOAT_VALS; i++)
5180 for (j = 0; j < MAX_LITTLENUMS; j++)
5182 if (words[j] != fp_values[i][j])
5186 if (j == MAX_LITTLENUMS)
5188 *str = input_line_pointer;
5189 input_line_pointer = save_in;
5196 *str = input_line_pointer;
5197 input_line_pointer = save_in;
5198 inst.error = _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm)
5208 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in)
5221 if (!is_immediate_prefix (**in))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in, "0x", 2) == 0)
5234 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5239 error_code = atof_generic (in, ".", EXP_CHARS,
5240 &generic_floating_point_number);
5243 && generic_floating_point_number.sign == '+'
5244 && (generic_floating_point_number.low
5245 > generic_floating_point_number.leader))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp, int *immed)
5262 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5263 int found_fpchar = 0;
5265 skip_past_char (&str, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum);
5275 if (strncmp (fpnum, "0x", 2) == 0)
5279 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5280 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5290 if ((str = atof_ieee (str, 's', words)) != NULL)
5292 unsigned fpword = 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5298 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5302 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str, int i, enum parse_shift_mode mode)
5351 const struct asm_shift_name *shift_name;
5352 enum shift_kind shift;
5357 for (p = *str; ISALPHA (*p); p++)
5362 inst.error = _("shift expression expected");
5366 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5369 if (shift_name == NULL)
5371 inst.error = _("shift expression expected");
5375 shift = shift_name->kind;
5379 case NO_SHIFT_RESTRICT:
5380 case SHIFT_IMMEDIATE:
5381 if (shift == SHIFT_UXTW)
5383 inst.error = _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5389 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5391 inst.error = _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE:
5397 if (shift != SHIFT_LSL)
5399 inst.error = _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE:
5405 if (shift != SHIFT_ASR)
5407 inst.error = _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE:
5412 if (shift != SHIFT_UXTW)
5414 inst.error = _("'UXTW' required");
5422 if (shift != SHIFT_RRX)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p);
5427 if (mode == NO_SHIFT_RESTRICT
5428 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5430 inst.operands[i].imm = reg;
5431 inst.operands[i].immisreg = 1;
5433 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5436 inst.operands[i].shift_kind = shift;
5437 inst.operands[i].shifted = 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str, int i)
5459 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5461 inst.operands[i].reg = value;
5462 inst.operands[i].isreg = 1;
5464 /* parse_shift will override this if appropriate */
5465 inst.relocs[0].exp.X_op = O_constant;
5466 inst.relocs[0].exp.X_add_number = 0;
5468 if (skip_past_comma (str) == FAIL)
5471 /* Shift operation on register. */
5472 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5475 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5478 if (skip_past_comma (str) == SUCCESS)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5484 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5486 inst.error = _("constant expression expected");
5490 value = exp.X_add_number;
5491 if (value < 0 || value > 30 || value % 2 != 0)
5493 inst.error = _("invalid rotation");
5496 if (inst.relocs[0].exp.X_add_number < 0
5497 || inst.relocs[0].exp.X_add_number > 255)
5499 inst.error = _("invalid constant");
5503 /* Encode as specified. */
5504 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5508 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5509 inst.relocs[0].pc_rel = 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5625 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5627 int length = strlen (group_reloc_table[i].name);
5629 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5630 && (*str)[length] == ':')
5632 *out = &group_reloc_table[i];
5633 *str += (length + 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str, int i)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str)[0] == '#' && (*str)[1] == ':')
5663 || (*str)[0] == ':')
5665 struct group_reloc_table_entry *entry;
5667 if ((*str)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5675 inst.error = _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5686 gas_assert (inst.relocs[0].type != 0);
5688 return PARSE_OPERAND_SUCCESS;
5691 return parse_shifter_operand (str, i) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str, int i)
5707 my_get_expression (&exp, &p, GE_NO_PREFIX);
5709 if (exp.X_op != O_constant)
5711 inst.error = _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL;
5715 inst.operands[i].imm = exp.X_add_number << 8;
5716 inst.operands[i].immisalign = 1;
5717 /* Alignments are not pre-indexes. */
5718 inst.operands[i].preind = 0;
5721 return PARSE_OPERAND_SUCCESS;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str, int i, int group_relocations,
5758 group_reloc_type group_type)
5763 if (skip_past_char (&p, '[') == FAIL)
5765 if (skip_past_char (&p, '=') == FAIL)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst.relocs[0].pc_rel = 1;
5769 inst.operands[i].reg = REG_PC;
5770 inst.operands[i].isreg = 1;
5771 inst.operands[i].preind = 1;
5773 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5774 return PARSE_OPERAND_FAIL;
5776 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5777 /*allow_symbol_p=*/TRUE))
5778 return PARSE_OPERAND_FAIL;
5781 return PARSE_OPERAND_SUCCESS;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p);
5787 if (group_type == GROUP_MVE)
5789 enum arm_reg_type rtype = REG_TYPE_MQ;
5790 struct neon_type_el et;
5791 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5793 inst.operands[i].isquad = 1;
5795 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5797 inst.error = BAD_ADDR_MODE;
5798 return PARSE_OPERAND_FAIL;
5801 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5803 if (group_type == GROUP_MVE)
5804 inst.error = BAD_ADDR_MODE;
5806 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5807 return PARSE_OPERAND_FAIL;
5809 inst.operands[i].reg = reg;
5810 inst.operands[i].isreg = 1;
5812 if (skip_past_comma (&p) == SUCCESS)
5814 inst.operands[i].preind = 1;
5817 else if (*p == '-') p++, inst.operands[i].negative = 1;
5819 enum arm_reg_type rtype = REG_TYPE_MQ;
5820 struct neon_type_el et;
5821 if (group_type == GROUP_MVE
5822 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5824 inst.operands[i].immisreg = 2;
5825 inst.operands[i].imm = reg;
5827 if (skip_past_comma (&p) == SUCCESS)
5829 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5831 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5832 inst.relocs[0].exp.X_add_number = 0;
5835 return PARSE_OPERAND_FAIL;
5838 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5840 inst.operands[i].imm = reg;
5841 inst.operands[i].immisreg = 1;
5843 if (skip_past_comma (&p) == SUCCESS)
5844 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5845 return PARSE_OPERAND_FAIL;
5847 else if (skip_past_char (&p, ':') == SUCCESS)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result = parse_neon_alignment (&p, i);
5854 if (result != PARSE_OPERAND_SUCCESS)
5859 if (inst.operands[i].negative)
5861 inst.operands[i].negative = 0;
5865 if (group_relocations
5866 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5868 struct group_reloc_table_entry *entry;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5880 inst.error = _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type) entry->ldr_code;
5900 = (bfd_reloc_code_real_type) entry->ldrs_code;
5905 = (bfd_reloc_code_real_type) entry->ldc_code;
5912 if (inst.relocs[0].type == 0)
5914 inst.error = _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5922 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5923 return PARSE_OPERAND_FAIL;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst.relocs[0].exp.X_op == O_constant
5926 && inst.relocs[0].exp.X_add_number == 0)
5928 skip_whitespace (q);
5932 skip_whitespace (q);
5935 inst.operands[i].negative = 1;
5940 else if (skip_past_char (&p, ':') == SUCCESS)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result = parse_neon_alignment (&p, i);
5946 if (result != PARSE_OPERAND_SUCCESS)
5950 if (skip_past_char (&p, ']') == FAIL)
5952 inst.error = _("']' expected");
5953 return PARSE_OPERAND_FAIL;
5956 if (skip_past_char (&p, '!') == SUCCESS)
5957 inst.operands[i].writeback = 1;
5959 else if (skip_past_comma (&p) == SUCCESS)
5961 if (skip_past_char (&p, '{') == SUCCESS)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p, &inst.operands[i].imm,
5965 0, 255, TRUE) == FAIL)
5966 return PARSE_OPERAND_FAIL;
5968 if (skip_past_char (&p, '}') == FAIL)
5970 inst.error = _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL;
5973 if (inst.operands[i].preind)
5975 inst.error = _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL;
5979 return PARSE_OPERAND_SUCCESS;
5983 inst.operands[i].postind = 1;
5984 inst.operands[i].writeback = 1;
5986 if (inst.operands[i].preind)
5988 inst.error = _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL;
5993 else if (*p == '-') p++, inst.operands[i].negative = 1;
5995 enum arm_reg_type rtype = REG_TYPE_MQ;
5996 struct neon_type_el et;
5997 if (group_type == GROUP_MVE
5998 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6000 inst.operands[i].immisreg = 2;
6001 inst.operands[i].imm = reg;
6003 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst.operands[i].immisalign)
6008 inst.operands[i].imm |= reg;
6010 inst.operands[i].imm = reg;
6011 inst.operands[i].immisreg = 1;
6013 if (skip_past_comma (&p) == SUCCESS)
6014 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6015 return PARSE_OPERAND_FAIL;
6021 if (inst.operands[i].negative)
6023 inst.operands[i].negative = 0;
6026 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6027 return PARSE_OPERAND_FAIL;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst.relocs[0].exp.X_op == O_constant
6030 && inst.relocs[0].exp.X_add_number == 0)
6032 skip_whitespace (q);
6036 skip_whitespace (q);
6039 inst.operands[i].negative = 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6049 inst.operands[i].preind = 1;
6050 inst.relocs[0].exp.X_op = O_constant;
6051 inst.relocs[0].exp.X_add_number = 0;
6054 return PARSE_OPERAND_SUCCESS;
6058 parse_address (char **str, int i)
6060 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str, int i, group_reloc_type type)
6067 return parse_address_main (str, i, 1, type);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str)
6077 skip_past_char (&p, '#');
6078 if (strncasecmp (p, ":lower16:", 9) == 0)
6079 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6080 else if (strncasecmp (p, ":upper16:", 9) == 0)
6081 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6083 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6086 skip_whitespace (p);
6089 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6092 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6094 if (inst.relocs[0].exp.X_op != O_constant)
6096 inst.error = _("constant expression expected");
6099 if (inst.relocs[0].exp.X_add_number < 0
6100 || inst.relocs[0].exp.X_add_number > 0xffff)
6102 inst.error = _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str, bfd_boolean lhs)
6118 unsigned long psr_field;
6119 const struct asm_psr *psr;
6121 bfd_boolean is_apsr = FALSE;
6122 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p, "SPSR", 4) == 0)
6136 goto unsupported_psr;
6138 psr_field = SPSR_BIT;
6140 else if (strncasecmp (p, "CPSR", 4) == 0)
6143 goto unsupported_psr;
6147 else if (strncasecmp (p, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p) || *p == '_');
6161 if (strncasecmp (start, "iapsr", 5) == 0
6162 || strncasecmp (start, "eapsr", 5) == 0
6163 || strncasecmp (start, "xpsr", 4) == 0
6164 || strncasecmp (start, "psr", 3) == 0)
6165 p = start + strcspn (start, "rR") + 1;
6167 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr->field <= 3)
6177 psr_field = psr->field;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr->field | (lhs ? PSR_f : 0);
6190 goto unsupported_psr;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p) || *p == '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits = 0;
6208 unsigned int g_bit = 0;
6211 for (bit = start; bit != p; bit++)
6213 switch (TOLOWER (*bit))
6216 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6236 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6240 inst.error = _("unexpected bit specified after APSR");
6245 if (nzcvq_bits == 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
6252 inst.error = _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits & 0x20) != 0
6261 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6262 || (g_bit & 0x2) != 0)
6264 inst.error = _("bad bitmask specified after APSR");
6270 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
6275 psr_field |= psr->field;
6281 goto error; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field |= (PSR_c | PSR_f);
6300 inst.error = _("selected processor does not support requested special "
6301 "purpose register");
6305 inst.error = _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end = strchr (*str, ',');
6327 size_t op_strlen = op_end - *str;
6329 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6331 if (!strncmp (*str, sysregs[i].name, op_strlen))
6333 val = sysregs[i].regl | (sysregs[i].regh << 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6359 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6360 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6363 inst.error = _("unrecognized CPS flag");
6368 if (saw_a_flag == 0)
6370 inst.error = _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str)
6387 if (strncasecmp (s, "BE", 2))
6389 else if (strncasecmp (s, "LE", 2))
6393 inst.error = _("valid endian specifiers are be or le");
6397 if (ISALNUM (s[2]) || s[2] == '_')
6399 inst.error = _("valid endian specifiers are be or le");
6404 return little_endian;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str)
6417 if (strncasecmp (s, "ROR", 3) == 0)
6421 inst.error = _("missing rotation field after comma");
6425 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6430 case 0: *str = s; return 0x0;
6431 case 8: *str = s; return 0x1;
6432 case 16: *str = s; return 0x2;
6433 case 24: *str = s; return 0x3;
6436 inst.error = _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str)
6447 const struct asm_cond *c;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q) && n < 3)
6457 cond[n] = TOLOWER (*q);
6462 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6465 inst.error = _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str)
6479 const struct asm_barrier_opt *o;
6482 while (ISALPHA (*q))
6485 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6490 if (!mark_feature_used (&o->arch))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str)
6505 if (skip_past_char (&p, '[') == FAIL)
6507 inst.error = _("'[' expected");
6511 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6513 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6516 inst.operands[0].reg = reg;
6518 if (skip_past_comma (&p) == FAIL)
6520 inst.error = _("',' expected");
6524 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6526 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6529 inst.operands[0].imm = reg;
6531 if (skip_past_comma (&p) == SUCCESS)
6533 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6535 if (inst.relocs[0].exp.X_add_number != 1)
6537 inst.error = _("invalid shift");
6540 inst.operands[0].shifted = 1;
6543 if (skip_past_char (&p, ']') == FAIL)
6545 inst.error = _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str, int *which_operand)
6562 int i = *which_operand, val;
6563 enum arm_reg_type rtype;
6565 struct neon_type_el optype;
6567 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6569 /* Cases 17 or 19. */
6570 inst.operands[i].reg = val;
6571 inst.operands[i].isvec = 1;
6572 inst.operands[i].isscalar = 2;
6573 inst.operands[i].vectype = optype;
6574 inst.operands[i++].present = 1;
6576 if (skip_past_comma (&ptr) == FAIL)
6579 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst.operands[i].reg = val;
6583 inst.operands[i].isreg = 1;
6584 inst.operands[i].present = 1;
6586 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst.operands[i].reg = val;
6590 inst.operands[i].isvec = 1;
6591 inst.operands[i].isscalar = 2;
6592 inst.operands[i].vectype = optype;
6593 inst.operands[i++].present = 1;
6595 if (skip_past_comma (&ptr) == FAIL)
6598 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6601 inst.operands[i].reg = val;
6602 inst.operands[i].isreg = 1;
6603 inst.operands[i++].present = 1;
6605 if (skip_past_comma (&ptr) == FAIL)
6608 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6611 inst.operands[i].reg = val;
6612 inst.operands[i].isreg = 1;
6613 inst.operands[i].present = 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst.operands[i].reg = val;
6625 inst.operands[i].isscalar = 1;
6626 inst.operands[i].vectype = optype;
6627 inst.operands[i++].present = 1;
6629 if (skip_past_comma (&ptr) == FAIL)
6632 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6635 inst.operands[i].reg = val;
6636 inst.operands[i].isreg = 1;
6637 inst.operands[i].present = 1;
6639 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6641 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr) == FAIL)
6648 inst.operands[i].reg = val;
6649 inst.operands[i].isreg = 1;
6650 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6651 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6652 inst.operands[i].isvec = 1;
6653 inst.operands[i].vectype = optype;
6654 inst.operands[i++].present = 1;
6656 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst.operands[i].reg = val;
6661 inst.operands[i].isreg = 1;
6662 inst.operands[i].present = 1;
6664 if (rtype == REG_TYPE_NQ)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype != REG_TYPE_VFS)
6672 if (skip_past_comma (&ptr) == FAIL)
6674 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6681 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst.operands[i].reg = val;
6690 inst.operands[i].isreg = 1;
6691 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6692 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6693 inst.operands[i].isvec = 1;
6694 inst.operands[i].vectype = optype;
6695 inst.operands[i].present = 1;
6697 if (skip_past_comma (&ptr) == SUCCESS)
6702 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6705 inst.operands[i].reg = val;
6706 inst.operands[i].isreg = 1;
6707 inst.operands[i++].present = 1;
6709 if (skip_past_comma (&ptr) == FAIL)
6712 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6715 inst.operands[i].reg = val;
6716 inst.operands[i].isreg = 1;
6717 inst.operands[i].present = 1;
6720 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst.operands[i].immisfloat = 1;
6726 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6739 /* Cases 6, 7, 16, 18. */
6740 inst.operands[i].reg = val;
6741 inst.operands[i].isreg = 1;
6742 inst.operands[i++].present = 1;
6744 if (skip_past_comma (&ptr) == FAIL)
6747 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst.operands[i].reg = val;
6751 inst.operands[i].isscalar = 2;
6752 inst.operands[i].present = 1;
6753 inst.operands[i].vectype = optype;
6755 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst.operands[i].reg = val;
6759 inst.operands[i].isscalar = 1;
6760 inst.operands[i].present = 1;
6761 inst.operands[i].vectype = optype;
6763 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6765 inst.operands[i].reg = val;
6766 inst.operands[i].isreg = 1;
6767 inst.operands[i++].present = 1;
6769 if (skip_past_comma (&ptr) == FAIL)
6772 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst.operands[i].reg = val;
6778 inst.operands[i].isreg = 1;
6779 inst.operands[i].isvec = 1;
6780 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6781 inst.operands[i].vectype = optype;
6782 inst.operands[i].present = 1;
6784 if (rtype == REG_TYPE_VFS)
6788 if (skip_past_comma (&ptr) == FAIL)
6790 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6793 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6796 inst.operands[i].reg = val;
6797 inst.operands[i].isreg = 1;
6798 inst.operands[i].isvec = 1;
6799 inst.operands[i].issingle = 1;
6800 inst.operands[i].vectype = optype;
6801 inst.operands[i].present = 1;
6806 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst.operands[i].reg = val;
6811 inst.operands[i].isvec = 1;
6812 inst.operands[i].isscalar = 2;
6813 inst.operands[i].vectype = optype;
6814 inst.operands[i++].present = 1;
6816 if (skip_past_comma (&ptr) == FAIL)
6819 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6822 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6825 inst.operands[i].reg = val;
6826 inst.operands[i].isvec = 1;
6827 inst.operands[i].isscalar = 2;
6828 inst.operands[i].vectype = optype;
6829 inst.operands[i].present = 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6843 inst.operands[i].reg = val;
6844 inst.operands[i].isreg = 1;
6845 inst.operands[i].isvec = 1;
6846 inst.operands[i].issingle = 1;
6847 inst.operands[i].vectype = optype;
6848 inst.operands[i].present = 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop, /* end of line */
6881 OP_RR, /* ARM register */
6882 OP_RRnpc, /* ARM register, not r15 */
6883 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP, /* Coprocessor number */
6889 OP_RCN, /* Coprocessor register */
6890 OP_RF, /* FPA register */
6891 OP_RVS, /* VFP single precision register */
6892 OP_RVD, /* VFP double precision register (0..15) */
6893 OP_RND, /* Neon double precision register (0..31) */
6894 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ, /* Neon quad precision register */
6898 OP_RNQMQ, /* Neon quad or MVE vector register. */
6899 OP_RVSD, /* VFP single or double precision register */
6900 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD, /* Neon single or double precision register */
6903 OP_RNDQ, /* Neon double or quad precision register */
6904 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ, /* Neon single, double or quad precision register */
6907 OP_RNSC, /* Neon scalar D[X] */
6908 OP_RVC, /* VFP control register */
6909 OP_RMF, /* Maverick F register */
6910 OP_RMD, /* Maverick D register */
6911 OP_RMFX, /* Maverick FX register */
6912 OP_RMDX, /* Maverick DX register */
6913 OP_RMAX, /* Maverick AX register */
6914 OP_RMDS, /* Maverick DSPSC register */
6915 OP_RIWR, /* iWMMXt wR register */
6916 OP_RIWC, /* iWMMXt wC register */
6917 OP_RIWG, /* iWMMXt wCG register */
6918 OP_RXA, /* XScale accumulator register */
6920 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ, /* MVE vector register. */
6925 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR, /* ARM LR register */
6930 OP_RRe, /* ARM register, only even numbered. */
6931 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST, /* ARM register list */
6935 OP_CLRMLST, /* CLRM register list */
6936 OP_VRSLST, /* VFP single-precision register list */
6937 OP_VRDLST, /* VFP double-precision register list */
6938 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST, /* Neon element/structure list */
6941 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2, /* MVE vector list with two elements. */
6943 OP_MSTRLST4, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
6970 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6971 OP_VLDR, /* VLDR operand. */
6973 OP_I0, /* immediate zero */
6974 OP_I7, /* immediate value 0 .. 7 */
6975 OP_I15, /* 0 .. 15 */
6976 OP_I16, /* 1 .. 16 */
6977 OP_I16z, /* 0 .. 16 */
6978 OP_I31, /* 0 .. 31 */
6979 OP_I31w, /* 0 .. 31, optional trailing ! */
6980 OP_I32, /* 1 .. 32 */
6981 OP_I32z, /* 0 .. 32 */
6982 OP_I63, /* 0 .. 63 */
6983 OP_I63s, /* -64 .. 63 */
6984 OP_I64, /* 1 .. 64 */
6985 OP_I64z, /* 0 .. 64 */
6986 OP_I255, /* 0 .. 255 */
6988 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6989 OP_I7b, /* 0 .. 7 */
6990 OP_I15b, /* 0 .. 15 */
6991 OP_I31b, /* 0 .. 31 */
6993 OP_SH, /* shifter operand */
6994 OP_SHG, /* shifter operand with possible group relocation */
6995 OP_ADDR, /* Memory address expression (any mode) */
6996 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
6997 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6998 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6999 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
7000 OP_EXP, /* arbitrary expression */
7001 OP_EXPi, /* same, with optional immediate prefix */
7002 OP_EXPr, /* same, with optional relocation suffix */
7003 OP_EXPs, /* same, with optional non-first operand relocation suffix */
7004 OP_HALF, /* 0 .. 65535 or low/high reloc. */
7005 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7006 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7008 OP_CPSF, /* CPS flags */
7009 OP_ENDI, /* Endianness specifier */
7010 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7011 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
7012 OP_COND, /* conditional code */
7013 OP_TB, /* Table branch. */
7015 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7017 OP_RRnpc_I0, /* ARM register or literal 0 */
7018 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
7019 OP_RR_EXi, /* ARM register or expression with imm prefix */
7020 OP_RF_IF, /* FPA register or immediate */
7021 OP_RIWR_RIWC, /* iWMMXt R or C reg */
7022 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
7024 /* Optional operands. */
7025 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7026 OP_oI31b, /* 0 .. 31 */
7027 OP_oI32b, /* 1 .. 32 */
7028 OP_oI32z, /* 0 .. 32 */
7029 OP_oIffffb, /* 0 .. 65535 */
7030 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7032 OP_oRR, /* ARM register */
7033 OP_oLR, /* ARM LR register */
7034 OP_oRRnpc, /* ARM register, not the PC */
7035 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7036 OP_oRRw, /* ARM register, not r15, optional trailing ! */
7037 OP_oRND, /* Optional Neon double precision register */
7038 OP_oRNQ, /* Optional Neon quad precision register */
7039 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
7040 OP_oRNDQ, /* Optional Neon double or quad precision register */
7041 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
7042 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7044 OP_oSHll, /* LSL immediate */
7045 OP_oSHar, /* ASR immediate */
7046 OP_oSHllar, /* LSL or ASR immediate */
7047 OP_oROR, /* ROR 0/8/16/24 */
7048 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
7050 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7052 /* Some pre-defined mixed (ARM/THUMB) operands. */
7053 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7054 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7055 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7057 OP_FIRST_OPTIONAL = OP_oI7b
7060 /* Generic instruction operand parser. This does no encoding and no
7061 semantic validation; it merely squirrels values away in the inst
7062 structure. Returns SUCCESS or FAIL depending on whether the
7063 specified grammar matched. */
7065 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
7067 unsigned const int *upat = pattern;
7068 char *backtrack_pos = 0;
7069 const char *backtrack_error = 0;
7070 int i, val = 0, backtrack_index = 0;
7071 enum arm_reg_type rtype;
7072 parse_operand_result result;
7073 unsigned int op_parse_code;
7074 bfd_boolean partial_match;
7076 #define po_char_or_fail(chr) \
7079 if (skip_past_char (&str, chr) == FAIL) \
7084 #define po_reg_or_fail(regtype) \
7087 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7088 & inst.operands[i].vectype); \
7091 first_error (_(reg_expected_msgs[regtype])); \
7094 inst.operands[i].reg = val; \
7095 inst.operands[i].isreg = 1; \
7096 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7097 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7098 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7099 || rtype == REG_TYPE_VFD \
7100 || rtype == REG_TYPE_NQ); \
7101 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7105 #define po_reg_or_goto(regtype, label) \
7108 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7109 & inst.operands[i].vectype); \
7113 inst.operands[i].reg = val; \
7114 inst.operands[i].isreg = 1; \
7115 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7116 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7117 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7118 || rtype == REG_TYPE_VFD \
7119 || rtype == REG_TYPE_NQ); \
7120 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7124 #define po_imm_or_fail(min, max, popt) \
7127 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7129 inst.operands[i].imm = val; \
7133 #define po_scalar_or_goto(elsz, label, reg_type) \
7136 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7140 inst.operands[i].reg = val; \
7141 inst.operands[i].isscalar = 1; \
7145 #define po_misc_or_fail(expr) \
7153 #define po_misc_or_fail_no_backtrack(expr) \
7157 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7158 backtrack_pos = 0; \
7159 if (result != PARSE_OPERAND_SUCCESS) \
7164 #define po_barrier_or_imm(str) \
7167 val = parse_barrier (&str); \
7168 if (val == FAIL && ! ISALPHA (*str)) \
7171 /* ISB can only take SY as an option. */ \
7172 || ((inst.instruction & 0xf0) == 0x60 \
7175 inst.error = _("invalid barrier type"); \
7176 backtrack_pos = 0; \
7182 skip_whitespace (str);
7184 for (i = 0; upat[i] != OP_stop; i++)
7186 op_parse_code = upat[i];
7187 if (op_parse_code >= 1<<16)
7188 op_parse_code = thumb ? (op_parse_code >> 16)
7189 : (op_parse_code & ((1<<16)-1));
7191 if (op_parse_code >= OP_FIRST_OPTIONAL)
7193 /* Remember where we are in case we need to backtrack. */
7194 backtrack_pos = str;
7195 backtrack_error = inst.error;
7196 backtrack_index = i;
7199 if (i > 0 && (i > 1 || inst.operands[0].present))
7200 po_char_or_fail (',');
7202 switch (op_parse_code)
7214 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7215 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7216 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7217 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7218 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7219 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
7222 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7226 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7229 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
7231 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7233 /* Also accept generic coprocessor regs for unknown registers. */
7235 po_reg_or_fail (REG_TYPE_CN);
7237 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7238 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7239 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7240 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7241 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7242 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7243 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7244 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7245 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7246 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
7249 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7252 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
7253 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7255 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7260 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7264 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
7266 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7269 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
7271 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7274 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
7276 po_reg_or_goto (REG_TYPE_RN, try_mq);
7281 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7284 po_reg_or_fail (REG_TYPE_NSDQ);
7288 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7292 po_reg_or_fail (REG_TYPE_MQ);
7294 /* Neon scalar. Using an element size of 8 means that some invalid
7295 scalars are accepted here, so deal with those in later code. */
7296 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
7300 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7303 po_imm_or_fail (0, 0, TRUE);
7308 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7312 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7317 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7320 if (parse_ifimm_zero (&str))
7321 inst.operands[i].imm = 0;
7325 = _("only floating point zero is allowed as immediate value");
7333 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
7336 po_reg_or_fail (REG_TYPE_RN);
7340 case OP_RNSDQ_RNSC_MQ_RR:
7341 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7344 case OP_RNSDQ_RNSC_MQ:
7345 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7350 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7354 po_reg_or_fail (REG_TYPE_NSDQ);
7361 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
7364 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
7367 po_reg_or_fail (REG_TYPE_NSD);
7371 case OP_RNDQMQ_RNSC_RR:
7372 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7375 case OP_RNDQ_RNSC_RR:
7376 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7378 case OP_RNDQMQ_RNSC:
7379 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7384 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
7387 po_reg_or_fail (REG_TYPE_NDQ);
7393 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
7396 po_reg_or_fail (REG_TYPE_VFD);
7401 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7402 not careful then bad things might happen. */
7403 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7406 case OP_RNDQMQ_Ibig:
7407 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7412 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7415 /* There's a possibility of getting a 64-bit immediate here, so
7416 we need special handling. */
7417 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7420 inst.error = _("immediate value is out of range");
7426 case OP_RNDQMQ_I63b_RR:
7427 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7430 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7435 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7438 po_imm_or_fail (0, 63, TRUE);
7443 po_char_or_fail ('[');
7444 po_reg_or_fail (REG_TYPE_RN);
7445 po_char_or_fail (']');
7451 po_reg_or_fail (REG_TYPE_RN);
7452 if (skip_past_char (&str, '!') == SUCCESS)
7453 inst.operands[i].writeback = 1;
7457 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7458 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7459 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
7460 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
7461 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7462 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
7463 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
7464 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
7465 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7466 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7467 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
7468 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
7470 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7472 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7473 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7475 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
7476 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7477 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
7478 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7480 /* Immediate variants */
7482 po_char_or_fail ('{');
7483 po_imm_or_fail (0, 255, TRUE);
7484 po_char_or_fail ('}');
7488 /* The expression parser chokes on a trailing !, so we have
7489 to find it first and zap it. */
7492 while (*s && *s != ',')
7497 inst.operands[i].writeback = 1;
7499 po_imm_or_fail (0, 31, TRUE);
7507 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7512 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7517 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7519 if (inst.relocs[0].exp.X_op == O_symbol)
7521 val = parse_reloc (&str);
7524 inst.error = _("unrecognized relocation suffix");
7527 else if (val != BFD_RELOC_UNUSED)
7529 inst.operands[i].imm = val;
7530 inst.operands[i].hasreloc = 1;
7536 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7538 if (inst.relocs[i].exp.X_op == O_symbol)
7540 inst.operands[i].hasreloc = 1;
7542 else if (inst.relocs[i].exp.X_op == O_constant)
7544 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7545 inst.operands[i].hasreloc = 0;
7549 /* Operand for MOVW or MOVT. */
7551 po_misc_or_fail (parse_half (&str));
7554 /* Register or expression. */
7555 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7556 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7558 /* Register or immediate. */
7559 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7560 I0: po_imm_or_fail (0, 0, FALSE); break;
7562 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7564 if (!is_immediate_prefix (*str))
7567 val = parse_fpa_immediate (&str);
7570 /* FPA immediates are encoded as registers 8-15.
7571 parse_fpa_immediate has already applied the offset. */
7572 inst.operands[i].reg = val;
7573 inst.operands[i].isreg = 1;
7576 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7577 I32z: po_imm_or_fail (0, 32, FALSE); break;
7579 /* Two kinds of register. */
7582 struct reg_entry *rege = arm_reg_parse_multi (&str);
7584 || (rege->type != REG_TYPE_MMXWR
7585 && rege->type != REG_TYPE_MMXWC
7586 && rege->type != REG_TYPE_MMXWCG))
7588 inst.error = _("iWMMXt data or control register expected");
7591 inst.operands[i].reg = rege->number;
7592 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7598 struct reg_entry *rege = arm_reg_parse_multi (&str);
7600 || (rege->type != REG_TYPE_MMXWC
7601 && rege->type != REG_TYPE_MMXWCG))
7603 inst.error = _("iWMMXt control register expected");
7606 inst.operands[i].reg = rege->number;
7607 inst.operands[i].isreg = 1;
7612 case OP_CPSF: val = parse_cps_flags (&str); break;
7613 case OP_ENDI: val = parse_endian_specifier (&str); break;
7614 case OP_oROR: val = parse_ror (&str); break;
7616 case OP_COND: val = parse_cond (&str); break;
7617 case OP_oBARRIER_I15:
7618 po_barrier_or_imm (str); break;
7620 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7626 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7627 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7629 inst.error = _("Banked registers are not available with this "
7635 val = parse_psr (&str, op_parse_code == OP_wPSR);
7639 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7642 val = parse_sys_vldr_vstr (&str);
7646 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7651 if (strncasecmp (str, "APSR_", 5) == 0)
7658 case 'c': found = (found & 1) ? 16 : found | 1; break;
7659 case 'n': found = (found & 2) ? 16 : found | 2; break;
7660 case 'z': found = (found & 4) ? 16 : found | 4; break;
7661 case 'v': found = (found & 8) ? 16 : found | 8; break;
7662 default: found = 16;
7666 inst.operands[i].isvec = 1;
7667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7668 inst.operands[i].reg = REG_PC;
7675 po_misc_or_fail (parse_tb (&str));
7678 /* Register lists. */
7680 val = parse_reg_list (&str, REGLIST_RN);
7683 inst.operands[i].writeback = 1;
7689 val = parse_reg_list (&str, REGLIST_CLRM);
7693 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7698 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7703 /* Allow Q registers too. */
7704 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7705 REGLIST_NEON_D, &partial_match);
7709 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7710 REGLIST_VFP_S, &partial_match);
7711 inst.operands[i].issingle = 1;
7716 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7717 REGLIST_VFP_D_VPR, &partial_match);
7718 if (val == FAIL && !partial_match)
7721 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7722 REGLIST_VFP_S_VPR, &partial_match);
7723 inst.operands[i].issingle = 1;
7728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7729 REGLIST_NEON_D, &partial_match);
7734 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7735 1, &inst.operands[i].vectype);
7736 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7740 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7741 0, &inst.operands[i].vectype);
7744 /* Addressing modes */
7746 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7750 po_misc_or_fail (parse_address (&str, i));
7754 po_misc_or_fail_no_backtrack (
7755 parse_address_group_reloc (&str, i, GROUP_LDR));
7759 po_misc_or_fail_no_backtrack (
7760 parse_address_group_reloc (&str, i, GROUP_LDRS));
7764 po_misc_or_fail_no_backtrack (
7765 parse_address_group_reloc (&str, i, GROUP_LDC));
7769 po_misc_or_fail (parse_shifter_operand (&str, i));
7773 po_misc_or_fail_no_backtrack (
7774 parse_shifter_operand_group_reloc (&str, i));
7778 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7782 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7786 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7791 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7794 po_reg_or_goto (REG_TYPE_RN, ZR);
7797 po_reg_or_fail (REG_TYPE_ZR);
7801 as_fatal (_("unhandled operand code %d"), op_parse_code);
7804 /* Various value-based sanity checks and shared operations. We
7805 do not signal immediate failures for the register constraints;
7806 this allows a syntax error to take precedence. */
7807 switch (op_parse_code)
7815 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7816 inst.error = BAD_PC;
7821 if (inst.operands[i].isreg)
7823 if (inst.operands[i].reg == REG_PC)
7824 inst.error = BAD_PC;
7825 else if (inst.operands[i].reg == REG_SP
7826 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7827 relaxed since ARMv8-A. */
7828 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7831 inst.error = BAD_SP;
7837 if (inst.operands[i].isreg
7838 && inst.operands[i].reg == REG_PC
7839 && (inst.operands[i].writeback || thumb))
7840 inst.error = BAD_PC;
7845 if (inst.operands[i].isreg)
7855 case OP_oBARRIER_I15:
7868 inst.operands[i].imm = val;
7873 if (inst.operands[i].reg != REG_LR)
7874 inst.error = _("operand must be LR register");
7879 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7880 inst.error = BAD_PC;
7884 if (inst.operands[i].isreg
7885 && (inst.operands[i].reg & 0x00000001) != 0)
7886 inst.error = BAD_ODD;
7890 if (inst.operands[i].isreg)
7892 if ((inst.operands[i].reg & 0x00000001) != 1)
7893 inst.error = BAD_EVEN;
7894 else if (inst.operands[i].reg == REG_SP)
7895 as_tsktsk (MVE_BAD_SP);
7896 else if (inst.operands[i].reg == REG_PC)
7897 inst.error = BAD_PC;
7905 /* If we get here, this operand was successfully parsed. */
7906 inst.operands[i].present = 1;
7910 inst.error = BAD_ARGS;
7915 /* The parse routine should already have set inst.error, but set a
7916 default here just in case. */
7918 inst.error = BAD_SYNTAX;
7922 /* Do not backtrack over a trailing optional argument that
7923 absorbed some text. We will only fail again, with the
7924 'garbage following instruction' error message, which is
7925 probably less helpful than the current one. */
7926 if (backtrack_index == i && backtrack_pos != str
7927 && upat[i+1] == OP_stop)
7930 inst.error = BAD_SYNTAX;
7934 /* Try again, skipping the optional argument at backtrack_pos. */
7935 str = backtrack_pos;
7936 inst.error = backtrack_error;
7937 inst.operands[backtrack_index].present = 0;
7938 i = backtrack_index;
7942 /* Check that we have parsed all the arguments. */
7943 if (*str != '\0' && !inst.error)
7944 inst.error = _("garbage following instruction");
7946 return inst.error ? FAIL : SUCCESS;
7949 #undef po_char_or_fail
7950 #undef po_reg_or_fail
7951 #undef po_reg_or_goto
7952 #undef po_imm_or_fail
7953 #undef po_scalar_or_fail
7954 #undef po_barrier_or_imm
7956 /* Shorthand macro for instruction encoding functions issuing errors. */
7957 #define constraint(expr, err) \
7968 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7969 instructions are unpredictable if these registers are used. This
7970 is the BadReg predicate in ARM's Thumb-2 documentation.
7972 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7973 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7974 #define reject_bad_reg(reg) \
7976 if (reg == REG_PC) \
7978 inst.error = BAD_PC; \
7981 else if (reg == REG_SP \
7982 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7984 inst.error = BAD_SP; \
7989 /* If REG is R13 (the stack pointer), warn that its use is
7991 #define warn_deprecated_sp(reg) \
7993 if (warn_on_deprecated && reg == REG_SP) \
7994 as_tsktsk (_("use of r13 is deprecated")); \
7997 /* Functions for operand encoding. ARM, then Thumb. */
7999 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8001 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8003 The only binary encoding difference is the Coprocessor number. Coprocessor
8004 9 is used for half-precision calculations or conversions. The format of the
8005 instruction is the same as the equivalent Coprocessor 10 instruction that
8006 exists for Single-Precision operation. */
8009 do_scalar_fp16_v82_encode (void)
8011 if (inst.cond < COND_ALWAYS)
8012 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8013 " the behaviour is UNPREDICTABLE"));
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8017 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8018 mark_feature_used (&arm_ext_fp16);
8021 /* If VAL can be encoded in the immediate field of an ARM instruction,
8022 return the encoded form. Otherwise, return FAIL. */
8025 encode_arm_immediate (unsigned int val)
8032 for (i = 2; i < 32; i += 2)
8033 if ((a = rotate_left (val, i)) <= 0xff)
8034 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8039 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8040 return the encoded form. Otherwise, return FAIL. */
8042 encode_thumb32_immediate (unsigned int val)
8049 for (i = 1; i <= 24; i++)
8052 if ((val & ~(0xff << i)) == 0)
8053 return ((val >> i) & 0x7f) | ((32 - i) << 7);
8057 if (val == ((a << 16) | a))
8059 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8063 if (val == ((a << 16) | a))
8064 return 0x200 | (a >> 8);
8068 /* Encode a VFP SP or DP register number into inst.instruction. */
8071 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8073 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8076 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
8079 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8082 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8087 first_error (_("D register out of range for selected VFP version"));
8095 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8099 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8103 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8107 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8111 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8115 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8123 /* Encode a <shift> in an ARM-format instruction. The immediate,
8124 if any, is handled by md_apply_fix. */
8126 encode_arm_shift (int i)
8128 /* register-shifted register. */
8129 if (inst.operands[i].immisreg)
8132 for (op_index = 0; op_index <= i; ++op_index)
8134 /* Check the operand only when it's presented. In pre-UAL syntax,
8135 if the destination register is the same as the first operand, two
8136 register form of the instruction can be used. */
8137 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8138 && inst.operands[op_index].reg == REG_PC)
8139 as_warn (UNPRED_REG ("r15"));
8142 if (inst.operands[i].imm == REG_PC)
8143 as_warn (UNPRED_REG ("r15"));
8146 if (inst.operands[i].shift_kind == SHIFT_RRX)
8147 inst.instruction |= SHIFT_ROR << 5;
8150 inst.instruction |= inst.operands[i].shift_kind << 5;
8151 if (inst.operands[i].immisreg)
8153 inst.instruction |= SHIFT_BY_REG;
8154 inst.instruction |= inst.operands[i].imm << 8;
8157 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8162 encode_arm_shifter_operand (int i)
8164 if (inst.operands[i].isreg)
8166 inst.instruction |= inst.operands[i].reg;
8167 encode_arm_shift (i);
8171 inst.instruction |= INST_IMMEDIATE;
8172 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8173 inst.instruction |= inst.operands[i].imm;
8177 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8179 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
8182 Generate an error if the operand is not a register. */
8183 constraint (!inst.operands[i].isreg,
8184 _("Instruction does not support =N addresses"));
8186 inst.instruction |= inst.operands[i].reg << 16;
8188 if (inst.operands[i].preind)
8192 inst.error = _("instruction does not accept preindexed addressing");
8195 inst.instruction |= PRE_INDEX;
8196 if (inst.operands[i].writeback)
8197 inst.instruction |= WRITE_BACK;
8200 else if (inst.operands[i].postind)
8202 gas_assert (inst.operands[i].writeback);
8204 inst.instruction |= WRITE_BACK;
8206 else /* unindexed - only for coprocessor */
8208 inst.error = _("instruction does not accept unindexed addressing");
8212 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8213 && (((inst.instruction & 0x000f0000) >> 16)
8214 == ((inst.instruction & 0x0000f000) >> 12)))
8215 as_warn ((inst.instruction & LOAD_BIT)
8216 ? _("destination register same as write-back base")
8217 : _("source register same as write-back base"));
8220 /* inst.operands[i] was set up by parse_address. Encode it into an
8221 ARM-format mode 2 load or store instruction. If is_t is true,
8222 reject forms that cannot be used with a T instruction (i.e. not
8225 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
8227 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8229 encode_arm_addr_mode_common (i, is_t);
8231 if (inst.operands[i].immisreg)
8233 constraint ((inst.operands[i].imm == REG_PC
8234 || (is_pc && inst.operands[i].writeback)),
8236 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8237 inst.instruction |= inst.operands[i].imm;
8238 if (!inst.operands[i].negative)
8239 inst.instruction |= INDEX_UP;
8240 if (inst.operands[i].shifted)
8242 if (inst.operands[i].shift_kind == SHIFT_RRX)
8243 inst.instruction |= SHIFT_ROR << 5;
8246 inst.instruction |= inst.operands[i].shift_kind << 5;
8247 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8251 else /* immediate offset in inst.relocs[0] */
8253 if (is_pc && !inst.relocs[0].pc_rel)
8255 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
8257 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8258 cannot use PC in addressing.
8259 PC cannot be used in writeback addressing, either. */
8260 constraint ((is_t || inst.operands[i].writeback),
8263 /* Use of PC in str is deprecated for ARMv7. */
8264 if (warn_on_deprecated
8266 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
8267 as_tsktsk (_("use of PC in this instruction is deprecated"));
8270 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8272 /* Prefer + for zero encoded value. */
8273 if (!inst.operands[i].negative)
8274 inst.instruction |= INDEX_UP;
8275 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8280 /* inst.operands[i] was set up by parse_address. Encode it into an
8281 ARM-format mode 3 load or store instruction. Reject forms that
8282 cannot be used with such instructions. If is_t is true, reject
8283 forms that cannot be used with a T instruction (i.e. not
8286 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
8288 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8290 inst.error = _("instruction does not accept scaled register index");
8294 encode_arm_addr_mode_common (i, is_t);
8296 if (inst.operands[i].immisreg)
8298 constraint ((inst.operands[i].imm == REG_PC
8299 || (is_t && inst.operands[i].reg == REG_PC)),
8301 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8303 inst.instruction |= inst.operands[i].imm;
8304 if (!inst.operands[i].negative)
8305 inst.instruction |= INDEX_UP;
8307 else /* immediate offset in inst.relocs[0] */
8309 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8310 && inst.operands[i].writeback),
8312 inst.instruction |= HWOFFSET_IMM;
8313 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8315 /* Prefer + for zero encoded value. */
8316 if (!inst.operands[i].negative)
8317 inst.instruction |= INDEX_UP;
8319 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8324 /* Write immediate bits [7:0] to the following locations:
8326 |28/24|23 19|18 16|15 4|3 0|
8327 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8329 This function is used by VMOV/VMVN/VORR/VBIC. */
8332 neon_write_immbits (unsigned immbits)
8334 inst.instruction |= immbits & 0xf;
8335 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8336 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8339 /* Invert low-order SIZE bits of XHI:XLO. */
8342 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8344 unsigned immlo = xlo ? *xlo : 0;
8345 unsigned immhi = xhi ? *xhi : 0;
8350 immlo = (~immlo) & 0xff;
8354 immlo = (~immlo) & 0xffff;
8358 immhi = (~immhi) & 0xffffffff;
8362 immlo = (~immlo) & 0xffffffff;
8376 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8380 neon_bits_same_in_bytes (unsigned imm)
8382 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8383 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8384 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8385 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8388 /* For immediate of above form, return 0bABCD. */
8391 neon_squash_bits (unsigned imm)
8393 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8394 | ((imm & 0x01000000) >> 21);
8397 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8400 neon_qfloat_bits (unsigned imm)
8402 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8405 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8406 the instruction. *OP is passed as the initial value of the op field, and
8407 may be set to a different value depending on the constant (i.e.
8408 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8409 MVN). If the immediate looks like a repeated pattern then also
8410 try smaller element sizes. */
8413 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8414 unsigned *immbits, int *op, int size,
8415 enum neon_el_type type)
8417 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8419 if (type == NT_float && !float_p)
8422 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
8424 if (size != 32 || *op == 1)
8426 *immbits = neon_qfloat_bits (immlo);
8432 if (neon_bits_same_in_bytes (immhi)
8433 && neon_bits_same_in_bytes (immlo))
8437 *immbits = (neon_squash_bits (immhi) << 4)
8438 | neon_squash_bits (immlo);
8449 if (immlo == (immlo & 0x000000ff))
8454 else if (immlo == (immlo & 0x0000ff00))
8456 *immbits = immlo >> 8;
8459 else if (immlo == (immlo & 0x00ff0000))
8461 *immbits = immlo >> 16;
8464 else if (immlo == (immlo & 0xff000000))
8466 *immbits = immlo >> 24;
8469 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8471 *immbits = (immlo >> 8) & 0xff;
8474 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8476 *immbits = (immlo >> 16) & 0xff;
8480 if ((immlo & 0xffff) != (immlo >> 16))
8487 if (immlo == (immlo & 0x000000ff))
8492 else if (immlo == (immlo & 0x0000ff00))
8494 *immbits = immlo >> 8;
8498 if ((immlo & 0xff) != (immlo >> 8))
8503 if (immlo == (immlo & 0x000000ff))
8505 /* Don't allow MVN with 8-bit immediate. */
8515 #if defined BFD_HOST_64_BIT
8516 /* Returns TRUE if double precision value V may be cast
8517 to single precision without loss of accuracy. */
8520 is_double_a_single (bfd_int64_t v)
8522 int exp = (int)((v >> 52) & 0x7FF);
8523 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8525 return (exp == 0 || exp == 0x7FF
8526 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8527 && (mantissa & 0x1FFFFFFFl) == 0;
8530 /* Returns a double precision value casted to single precision
8531 (ignoring the least significant bits in exponent and mantissa). */
8534 double_to_single (bfd_int64_t v)
8536 int sign = (int) ((v >> 63) & 1l);
8537 int exp = (int) ((v >> 52) & 0x7FF);
8538 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8544 exp = exp - 1023 + 127;
8553 /* No denormalized numbers. */
8559 return (sign << 31) | (exp << 23) | mantissa;
8561 #endif /* BFD_HOST_64_BIT */
8570 static void do_vfp_nsyn_opcode (const char *);
8572 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8573 Determine whether it can be performed with a move instruction; if
8574 it can, convert inst.instruction to that move instruction and
8575 return TRUE; if it can't, convert inst.instruction to a literal-pool
8576 load and return FALSE. If this is not a valid thing to do in the
8577 current context, set inst.error and return TRUE.
8579 inst.operands[i] describes the destination register. */
8582 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
8585 bfd_boolean thumb_p = (t == CONST_THUMB);
8586 bfd_boolean arm_p = (t == CONST_ARM);
8589 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8593 if ((inst.instruction & tbit) == 0)
8595 inst.error = _("invalid pseudo operation");
8599 if (inst.relocs[0].exp.X_op != O_constant
8600 && inst.relocs[0].exp.X_op != O_symbol
8601 && inst.relocs[0].exp.X_op != O_big)
8603 inst.error = _("constant expression expected");
8607 if (inst.relocs[0].exp.X_op == O_constant
8608 || inst.relocs[0].exp.X_op == O_big)
8610 #if defined BFD_HOST_64_BIT
8615 if (inst.relocs[0].exp.X_op == O_big)
8617 LITTLENUM_TYPE w[X_PRECISION];
8620 if (inst.relocs[0].exp.X_add_number == -1)
8622 gen_to_words (w, X_PRECISION, E_PRECISION);
8624 /* FIXME: Should we check words w[2..5] ? */
8629 #if defined BFD_HOST_64_BIT
8631 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8632 << LITTLENUM_NUMBER_OF_BITS)
8633 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8634 << LITTLENUM_NUMBER_OF_BITS)
8635 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8636 << LITTLENUM_NUMBER_OF_BITS)
8637 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8639 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8640 | (l[0] & LITTLENUM_MASK);
8644 v = inst.relocs[0].exp.X_add_number;
8646 if (!inst.operands[i].issingle)
8650 /* LDR should not use lead in a flag-setting instruction being
8651 chosen so we do not check whether movs can be used. */
8653 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8654 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8655 && inst.operands[i].reg != 13
8656 && inst.operands[i].reg != 15)
8658 /* Check if on thumb2 it can be done with a mov.w, mvn or
8659 movw instruction. */
8660 unsigned int newimm;
8661 bfd_boolean isNegated;
8663 newimm = encode_thumb32_immediate (v);
8664 if (newimm != (unsigned int) FAIL)
8668 newimm = encode_thumb32_immediate (~v);
8669 if (newimm != (unsigned int) FAIL)
8673 /* The number can be loaded with a mov.w or mvn
8675 if (newimm != (unsigned int) FAIL
8676 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8678 inst.instruction = (0xf04f0000 /* MOV.W. */
8679 | (inst.operands[i].reg << 8));
8680 /* Change to MOVN. */
8681 inst.instruction |= (isNegated ? 0x200000 : 0);
8682 inst.instruction |= (newimm & 0x800) << 15;
8683 inst.instruction |= (newimm & 0x700) << 4;
8684 inst.instruction |= (newimm & 0x0ff);
8687 /* The number can be loaded with a movw instruction. */
8688 else if ((v & ~0xFFFF) == 0
8689 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8691 int imm = v & 0xFFFF;
8693 inst.instruction = 0xf2400000; /* MOVW. */
8694 inst.instruction |= (inst.operands[i].reg << 8);
8695 inst.instruction |= (imm & 0xf000) << 4;
8696 inst.instruction |= (imm & 0x0800) << 15;
8697 inst.instruction |= (imm & 0x0700) << 4;
8698 inst.instruction |= (imm & 0x00ff);
8705 int value = encode_arm_immediate (v);
8709 /* This can be done with a mov instruction. */
8710 inst.instruction &= LITERAL_MASK;
8711 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8712 inst.instruction |= value & 0xfff;
8716 value = encode_arm_immediate (~ v);
8719 /* This can be done with a mvn instruction. */
8720 inst.instruction &= LITERAL_MASK;
8721 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8722 inst.instruction |= value & 0xfff;
8726 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8729 unsigned immbits = 0;
8730 unsigned immlo = inst.operands[1].imm;
8731 unsigned immhi = inst.operands[1].regisimm
8732 ? inst.operands[1].reg
8733 : inst.relocs[0].exp.X_unsigned
8735 : ((bfd_int64_t)((int) immlo)) >> 32;
8736 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8737 &op, 64, NT_invtype);
8741 neon_invert_size (&immlo, &immhi, 64);
8743 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8744 &op, 64, NT_invtype);
8749 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8755 /* Fill other bits in vmov encoding for both thumb and arm. */
8757 inst.instruction |= (0x7U << 29) | (0xF << 24);
8759 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8760 neon_write_immbits (immbits);
8768 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8769 if (inst.operands[i].issingle
8770 && is_quarter_float (inst.operands[1].imm)
8771 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8773 inst.operands[1].imm =
8774 neon_qfloat_bits (v);
8775 do_vfp_nsyn_opcode ("fconsts");
8779 /* If our host does not support a 64-bit type then we cannot perform
8780 the following optimization. This mean that there will be a
8781 discrepancy between the output produced by an assembler built for
8782 a 32-bit-only host and the output produced from a 64-bit host, but
8783 this cannot be helped. */
8784 #if defined BFD_HOST_64_BIT
8785 else if (!inst.operands[1].issingle
8786 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8788 if (is_double_a_single (v)
8789 && is_quarter_float (double_to_single (v)))
8791 inst.operands[1].imm =
8792 neon_qfloat_bits (double_to_single (v));
8793 do_vfp_nsyn_opcode ("fconstd");
8801 if (add_to_lit_pool ((!inst.operands[i].isvec
8802 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8805 inst.operands[1].reg = REG_PC;
8806 inst.operands[1].isreg = 1;
8807 inst.operands[1].preind = 1;
8808 inst.relocs[0].pc_rel = 1;
8809 inst.relocs[0].type = (thumb_p
8810 ? BFD_RELOC_ARM_THUMB_OFFSET
8812 ? BFD_RELOC_ARM_HWLITERAL
8813 : BFD_RELOC_ARM_LITERAL));
8817 /* inst.operands[i] was set up by parse_address. Encode it into an
8818 ARM-format instruction. Reject all forms which cannot be encoded
8819 into a coprocessor load/store instruction. If wb_ok is false,
8820 reject use of writeback; if unind_ok is false, reject use of
8821 unindexed addressing. If reloc_override is not 0, use it instead
8822 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8823 (in which case it is preserved). */
8826 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8828 if (!inst.operands[i].isreg)
8831 if (! inst.operands[0].isvec)
8833 inst.error = _("invalid co-processor operand");
8836 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8840 inst.instruction |= inst.operands[i].reg << 16;
8842 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8844 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8846 gas_assert (!inst.operands[i].writeback);
8849 inst.error = _("instruction does not support unindexed addressing");
8852 inst.instruction |= inst.operands[i].imm;
8853 inst.instruction |= INDEX_UP;
8857 if (inst.operands[i].preind)
8858 inst.instruction |= PRE_INDEX;
8860 if (inst.operands[i].writeback)
8862 if (inst.operands[i].reg == REG_PC)
8864 inst.error = _("pc may not be used with write-back");
8869 inst.error = _("instruction does not support writeback");
8872 inst.instruction |= WRITE_BACK;
8876 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8877 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8878 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8879 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
8882 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8884 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
8887 /* Prefer + for zero encoded value. */
8888 if (!inst.operands[i].negative)
8889 inst.instruction |= INDEX_UP;
8894 /* Functions for instruction encoding, sorted by sub-architecture.
8895 First some generics; their names are taken from the conventional
8896 bit positions for register arguments in ARM format instructions. */
8906 inst.instruction |= inst.operands[0].reg << 12;
8912 inst.instruction |= inst.operands[0].reg << 16;
8918 inst.instruction |= inst.operands[0].reg << 12;
8919 inst.instruction |= inst.operands[1].reg;
8925 inst.instruction |= inst.operands[0].reg;
8926 inst.instruction |= inst.operands[1].reg << 16;
8932 inst.instruction |= inst.operands[0].reg << 12;
8933 inst.instruction |= inst.operands[1].reg << 16;
8939 inst.instruction |= inst.operands[0].reg << 16;
8940 inst.instruction |= inst.operands[1].reg << 12;
8946 inst.instruction |= inst.operands[0].reg << 8;
8947 inst.instruction |= inst.operands[1].reg << 16;
8951 check_obsolete (const arm_feature_set *feature, const char *msg)
8953 if (ARM_CPU_IS_ANY (cpu_variant))
8955 as_tsktsk ("%s", msg);
8958 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8970 unsigned Rn = inst.operands[2].reg;
8971 /* Enforce restrictions on SWP instruction. */
8972 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8974 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8975 _("Rn must not overlap other operands"));
8977 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8979 if (!check_obsolete (&arm_ext_v8,
8980 _("swp{b} use is obsoleted for ARMv8 and later"))
8981 && warn_on_deprecated
8982 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8983 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8986 inst.instruction |= inst.operands[0].reg << 12;
8987 inst.instruction |= inst.operands[1].reg;
8988 inst.instruction |= Rn << 16;
8994 inst.instruction |= inst.operands[0].reg << 12;
8995 inst.instruction |= inst.operands[1].reg << 16;
8996 inst.instruction |= inst.operands[2].reg;
9002 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
9003 constraint (((inst.relocs[0].exp.X_op != O_constant
9004 && inst.relocs[0].exp.X_op != O_illegal)
9005 || inst.relocs[0].exp.X_add_number != 0),
9007 inst.instruction |= inst.operands[0].reg;
9008 inst.instruction |= inst.operands[1].reg << 12;
9009 inst.instruction |= inst.operands[2].reg << 16;
9015 inst.instruction |= inst.operands[0].imm;
9021 inst.instruction |= inst.operands[0].reg << 12;
9022 encode_arm_cp_address (1, TRUE, TRUE, 0);
9025 /* ARM instructions, in alphabetical order by function name (except
9026 that wrapper functions appear immediately after the function they
9029 /* This is a pseudo-op of the form "adr rd, label" to be converted
9030 into a relative address of the form "add rd, pc, #label-.-8". */
9035 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9037 /* Frag hacking will turn this into a sub instruction if the offset turns
9038 out to be negative. */
9039 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9040 inst.relocs[0].pc_rel = 1;
9041 inst.relocs[0].exp.X_add_number -= 8;
9043 if (support_interwork
9044 && inst.relocs[0].exp.X_op == O_symbol
9045 && inst.relocs[0].exp.X_add_symbol != NULL
9046 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9047 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9048 inst.relocs[0].exp.X_add_number |= 1;
9051 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9052 into a relative address of the form:
9053 add rd, pc, #low(label-.-8)"
9054 add rd, rd, #high(label-.-8)" */
9059 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9061 /* Frag hacking will turn this into a sub instruction if the offset turns
9062 out to be negative. */
9063 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9064 inst.relocs[0].pc_rel = 1;
9065 inst.size = INSN_SIZE * 2;
9066 inst.relocs[0].exp.X_add_number -= 8;
9068 if (support_interwork
9069 && inst.relocs[0].exp.X_op == O_symbol
9070 && inst.relocs[0].exp.X_add_symbol != NULL
9071 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9072 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9073 inst.relocs[0].exp.X_add_number |= 1;
9079 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9080 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9082 if (!inst.operands[1].present)
9083 inst.operands[1].reg = inst.operands[0].reg;
9084 inst.instruction |= inst.operands[0].reg << 12;
9085 inst.instruction |= inst.operands[1].reg << 16;
9086 encode_arm_shifter_operand (2);
9092 if (inst.operands[0].present)
9093 inst.instruction |= inst.operands[0].imm;
9095 inst.instruction |= 0xf;
9101 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9102 constraint (msb > 32, _("bit-field extends past end of register"));
9103 /* The instruction encoding stores the LSB and MSB,
9104 not the LSB and width. */
9105 inst.instruction |= inst.operands[0].reg << 12;
9106 inst.instruction |= inst.operands[1].imm << 7;
9107 inst.instruction |= (msb - 1) << 16;
9115 /* #0 in second position is alternative syntax for bfc, which is
9116 the same instruction but with REG_PC in the Rm field. */
9117 if (!inst.operands[1].isreg)
9118 inst.operands[1].reg = REG_PC;
9120 msb = inst.operands[2].imm + inst.operands[3].imm;
9121 constraint (msb > 32, _("bit-field extends past end of register"));
9122 /* The instruction encoding stores the LSB and MSB,
9123 not the LSB and width. */
9124 inst.instruction |= inst.operands[0].reg << 12;
9125 inst.instruction |= inst.operands[1].reg;
9126 inst.instruction |= inst.operands[2].imm << 7;
9127 inst.instruction |= (msb - 1) << 16;
9133 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9134 _("bit-field extends past end of register"));
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 inst.instruction |= inst.operands[1].reg;
9137 inst.instruction |= inst.operands[2].imm << 7;
9138 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9141 /* ARM V5 breakpoint instruction (argument parse)
9142 BKPT <16 bit unsigned immediate>
9143 Instruction is not conditional.
9144 The bit pattern given in insns[] has the COND_ALWAYS condition,
9145 and it is an error if the caller tried to override that. */
9150 /* Top 12 of 16 bits to bits 19:8. */
9151 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9153 /* Bottom 4 of 16 bits to bits 3:0. */
9154 inst.instruction |= inst.operands[0].imm & 0xf;
9158 encode_branch (int default_reloc)
9160 if (inst.operands[0].hasreloc)
9162 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9163 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9164 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9165 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9166 ? BFD_RELOC_ARM_PLT32
9167 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
9170 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9171 inst.relocs[0].pc_rel = 1;
9178 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9179 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9182 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9189 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9191 if (inst.cond == COND_ALWAYS)
9192 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9194 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9201 /* ARM V5 branch-link-exchange instruction (argument parse)
9202 BLX <target_addr> ie BLX(1)
9203 BLX{<condition>} <Rm> ie BLX(2)
9204 Unfortunately, there are two different opcodes for this mnemonic.
9205 So, the insns[].value is not used, and the code here zaps values
9206 into inst.instruction.
9207 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9212 if (inst.operands[0].isreg)
9214 /* Arg is a register; the opcode provided by insns[] is correct.
9215 It is not illegal to do "blx pc", just useless. */
9216 if (inst.operands[0].reg == REG_PC)
9217 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9219 inst.instruction |= inst.operands[0].reg;
9223 /* Arg is an address; this instruction cannot be executed
9224 conditionally, and the opcode must be adjusted.
9225 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9226 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9227 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9228 inst.instruction = 0xfa000000;
9229 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
9236 bfd_boolean want_reloc;
9238 if (inst.operands[0].reg == REG_PC)
9239 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9241 inst.instruction |= inst.operands[0].reg;
9242 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9243 it is for ARMv4t or earlier. */
9244 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
9245 if (!ARM_FEATURE_ZERO (selected_object_arch)
9246 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
9250 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
9255 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9259 /* ARM v5TEJ. Jump to Jazelle code. */
9264 if (inst.operands[0].reg == REG_PC)
9265 as_tsktsk (_("use of r15 in bxj is not really useful"));
9267 inst.instruction |= inst.operands[0].reg;
9270 /* Co-processor data operation:
9271 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9272 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9276 inst.instruction |= inst.operands[0].reg << 8;
9277 inst.instruction |= inst.operands[1].imm << 20;
9278 inst.instruction |= inst.operands[2].reg << 12;
9279 inst.instruction |= inst.operands[3].reg << 16;
9280 inst.instruction |= inst.operands[4].reg;
9281 inst.instruction |= inst.operands[5].imm << 5;
9287 inst.instruction |= inst.operands[0].reg << 16;
9288 encode_arm_shifter_operand (1);
9291 /* Transfer between coprocessor and ARM registers.
9292 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9297 No special properties. */
9299 struct deprecated_coproc_regs_s
9306 arm_feature_set deprecated;
9307 arm_feature_set obsoleted;
9308 const char *dep_msg;
9309 const char *obs_msg;
9312 #define DEPR_ACCESS_V8 \
9313 N_("This coprocessor register access is deprecated in ARMv8")
9315 /* Table of all deprecated coprocessor registers. */
9316 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9318 {15, 0, 7, 10, 5, /* CP15DMB. */
9319 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9320 DEPR_ACCESS_V8, NULL},
9321 {15, 0, 7, 10, 4, /* CP15DSB. */
9322 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9323 DEPR_ACCESS_V8, NULL},
9324 {15, 0, 7, 5, 4, /* CP15ISB. */
9325 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9326 DEPR_ACCESS_V8, NULL},
9327 {14, 6, 1, 0, 0, /* TEEHBR. */
9328 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9329 DEPR_ACCESS_V8, NULL},
9330 {14, 6, 0, 0, 0, /* TEECR. */
9331 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9332 DEPR_ACCESS_V8, NULL},
9335 #undef DEPR_ACCESS_V8
9337 static const size_t deprecated_coproc_reg_count =
9338 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9346 Rd = inst.operands[2].reg;
9349 if (inst.instruction == 0xee000010
9350 || inst.instruction == 0xfe000010)
9352 reject_bad_reg (Rd);
9353 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9355 constraint (Rd == REG_SP, BAD_SP);
9360 if (inst.instruction == 0xe000010)
9361 constraint (Rd == REG_PC, BAD_PC);
9364 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9366 const struct deprecated_coproc_regs_s *r =
9367 deprecated_coproc_regs + i;
9369 if (inst.operands[0].reg == r->cp
9370 && inst.operands[1].imm == r->opc1
9371 && inst.operands[3].reg == r->crn
9372 && inst.operands[4].reg == r->crm
9373 && inst.operands[5].imm == r->opc2)
9375 if (! ARM_CPU_IS_ANY (cpu_variant)
9376 && warn_on_deprecated
9377 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
9378 as_tsktsk ("%s", r->dep_msg);
9382 inst.instruction |= inst.operands[0].reg << 8;
9383 inst.instruction |= inst.operands[1].imm << 21;
9384 inst.instruction |= Rd << 12;
9385 inst.instruction |= inst.operands[3].reg << 16;
9386 inst.instruction |= inst.operands[4].reg;
9387 inst.instruction |= inst.operands[5].imm << 5;
9390 /* Transfer between coprocessor register and pair of ARM registers.
9391 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9396 Two XScale instructions are special cases of these:
9398 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9399 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9401 Result unpredictable if Rd or Rn is R15. */
9408 Rd = inst.operands[2].reg;
9409 Rn = inst.operands[3].reg;
9413 reject_bad_reg (Rd);
9414 reject_bad_reg (Rn);
9418 constraint (Rd == REG_PC, BAD_PC);
9419 constraint (Rn == REG_PC, BAD_PC);
9422 /* Only check the MRRC{2} variants. */
9423 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9425 /* If Rd == Rn, error that the operation is
9426 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9427 constraint (Rd == Rn, BAD_OVERLAP);
9430 inst.instruction |= inst.operands[0].reg << 8;
9431 inst.instruction |= inst.operands[1].imm << 4;
9432 inst.instruction |= Rd << 12;
9433 inst.instruction |= Rn << 16;
9434 inst.instruction |= inst.operands[4].reg;
9440 inst.instruction |= inst.operands[0].imm << 6;
9441 if (inst.operands[1].present)
9443 inst.instruction |= CPSI_MMOD;
9444 inst.instruction |= inst.operands[1].imm;
9451 inst.instruction |= inst.operands[0].imm;
9457 unsigned Rd, Rn, Rm;
9459 Rd = inst.operands[0].reg;
9460 Rn = (inst.operands[1].present
9461 ? inst.operands[1].reg : Rd);
9462 Rm = inst.operands[2].reg;
9464 constraint ((Rd == REG_PC), BAD_PC);
9465 constraint ((Rn == REG_PC), BAD_PC);
9466 constraint ((Rm == REG_PC), BAD_PC);
9468 inst.instruction |= Rd << 16;
9469 inst.instruction |= Rn << 0;
9470 inst.instruction |= Rm << 8;
9476 /* There is no IT instruction in ARM mode. We
9477 process it to do the validation as if in
9478 thumb mode, just in case the code gets
9479 assembled for thumb using the unified syntax. */
9484 set_pred_insn_type (IT_INSN);
9485 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9486 now_pred.cc = inst.operands[0].imm;
9490 /* If there is only one register in the register list,
9491 then return its register number. Otherwise return -1. */
9493 only_one_reg_in_list (int range)
9495 int i = ffs (range) - 1;
9496 return (i > 15 || range != (1 << i)) ? -1 : i;
9500 encode_ldmstm(int from_push_pop_mnem)
9502 int base_reg = inst.operands[0].reg;
9503 int range = inst.operands[1].imm;
9506 inst.instruction |= base_reg << 16;
9507 inst.instruction |= range;
9509 if (inst.operands[1].writeback)
9510 inst.instruction |= LDM_TYPE_2_OR_3;
9512 if (inst.operands[0].writeback)
9514 inst.instruction |= WRITE_BACK;
9515 /* Check for unpredictable uses of writeback. */
9516 if (inst.instruction & LOAD_BIT)
9518 /* Not allowed in LDM type 2. */
9519 if ((inst.instruction & LDM_TYPE_2_OR_3)
9520 && ((range & (1 << REG_PC)) == 0))
9521 as_warn (_("writeback of base register is UNPREDICTABLE"));
9522 /* Only allowed if base reg not in list for other types. */
9523 else if (range & (1 << base_reg))
9524 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9528 /* Not allowed for type 2. */
9529 if (inst.instruction & LDM_TYPE_2_OR_3)
9530 as_warn (_("writeback of base register is UNPREDICTABLE"));
9531 /* Only allowed if base reg not in list, or first in list. */
9532 else if ((range & (1 << base_reg))
9533 && (range & ((1 << base_reg) - 1)))
9534 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9538 /* If PUSH/POP has only one register, then use the A2 encoding. */
9539 one_reg = only_one_reg_in_list (range);
9540 if (from_push_pop_mnem && one_reg >= 0)
9542 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9544 if (is_push && one_reg == 13 /* SP */)
9545 /* PR 22483: The A2 encoding cannot be used when
9546 pushing the stack pointer as this is UNPREDICTABLE. */
9549 inst.instruction &= A_COND_MASK;
9550 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9551 inst.instruction |= one_reg << 12;
9558 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
9561 /* ARMv5TE load-consecutive (argument parse)
9570 constraint (inst.operands[0].reg % 2 != 0,
9571 _("first transfer register must be even"));
9572 constraint (inst.operands[1].present
9573 && inst.operands[1].reg != inst.operands[0].reg + 1,
9574 _("can only transfer two consecutive registers"));
9575 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9576 constraint (!inst.operands[2].isreg, _("'[' expected"));
9578 if (!inst.operands[1].present)
9579 inst.operands[1].reg = inst.operands[0].reg + 1;
9581 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9582 register and the first register written; we have to diagnose
9583 overlap between the base and the second register written here. */
9585 if (inst.operands[2].reg == inst.operands[1].reg
9586 && (inst.operands[2].writeback || inst.operands[2].postind))
9587 as_warn (_("base register written back, and overlaps "
9588 "second transfer register"));
9590 if (!(inst.instruction & V4_STR_BIT))
9592 /* For an index-register load, the index register must not overlap the
9593 destination (even if not write-back). */
9594 if (inst.operands[2].immisreg
9595 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9596 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9597 as_warn (_("index register overlaps transfer register"));
9599 inst.instruction |= inst.operands[0].reg << 12;
9600 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
9606 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9607 || inst.operands[1].postind || inst.operands[1].writeback
9608 || inst.operands[1].immisreg || inst.operands[1].shifted
9609 || inst.operands[1].negative
9610 /* This can arise if the programmer has written
9612 or if they have mistakenly used a register name as the last
9615 It is very difficult to distinguish between these two cases
9616 because "rX" might actually be a label. ie the register
9617 name has been occluded by a symbol of the same name. So we
9618 just generate a general 'bad addressing mode' type error
9619 message and leave it up to the programmer to discover the
9620 true cause and fix their mistake. */
9621 || (inst.operands[1].reg == REG_PC),
9624 constraint (inst.relocs[0].exp.X_op != O_constant
9625 || inst.relocs[0].exp.X_add_number != 0,
9626 _("offset must be zero in ARM encoding"));
9628 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9630 inst.instruction |= inst.operands[0].reg << 12;
9631 inst.instruction |= inst.operands[1].reg << 16;
9632 inst.relocs[0].type = BFD_RELOC_UNUSED;
9638 constraint (inst.operands[0].reg % 2 != 0,
9639 _("even register required"));
9640 constraint (inst.operands[1].present
9641 && inst.operands[1].reg != inst.operands[0].reg + 1,
9642 _("can only load two consecutive registers"));
9643 /* If op 1 were present and equal to PC, this function wouldn't
9644 have been called in the first place. */
9645 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9647 inst.instruction |= inst.operands[0].reg << 12;
9648 inst.instruction |= inst.operands[2].reg << 16;
9651 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9652 which is not a multiple of four is UNPREDICTABLE. */
9654 check_ldr_r15_aligned (void)
9656 constraint (!(inst.operands[1].immisreg)
9657 && (inst.operands[0].reg == REG_PC
9658 && inst.operands[1].reg == REG_PC
9659 && (inst.relocs[0].exp.X_add_number & 0x3)),
9660 _("ldr to register 15 must be 4-byte aligned"));
9666 inst.instruction |= inst.operands[0].reg << 12;
9667 if (!inst.operands[1].isreg)
9668 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
9670 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
9671 check_ldr_r15_aligned ();
9677 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9679 if (inst.operands[1].preind)
9681 constraint (inst.relocs[0].exp.X_op != O_constant
9682 || inst.relocs[0].exp.X_add_number != 0,
9683 _("this instruction requires a post-indexed address"));
9685 inst.operands[1].preind = 0;
9686 inst.operands[1].postind = 1;
9687 inst.operands[1].writeback = 1;
9689 inst.instruction |= inst.operands[0].reg << 12;
9690 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9693 /* Halfword and signed-byte load/store operations. */
9698 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9699 inst.instruction |= inst.operands[0].reg << 12;
9700 if (!inst.operands[1].isreg)
9701 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
9703 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
9709 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9711 if (inst.operands[1].preind)
9713 constraint (inst.relocs[0].exp.X_op != O_constant
9714 || inst.relocs[0].exp.X_add_number != 0,
9715 _("this instruction requires a post-indexed address"));
9717 inst.operands[1].preind = 0;
9718 inst.operands[1].postind = 1;
9719 inst.operands[1].writeback = 1;
9721 inst.instruction |= inst.operands[0].reg << 12;
9722 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9725 /* Co-processor register load/store.
9726 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9730 inst.instruction |= inst.operands[0].reg << 8;
9731 inst.instruction |= inst.operands[1].reg << 12;
9732 encode_arm_cp_address (2, TRUE, TRUE, 0);
9738 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9739 if (inst.operands[0].reg == inst.operands[1].reg
9740 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
9741 && !(inst.instruction & 0x00400000))
9742 as_tsktsk (_("Rd and Rm should be different in mla"));
9744 inst.instruction |= inst.operands[0].reg << 16;
9745 inst.instruction |= inst.operands[1].reg;
9746 inst.instruction |= inst.operands[2].reg << 8;
9747 inst.instruction |= inst.operands[3].reg << 12;
9753 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9754 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9756 inst.instruction |= inst.operands[0].reg << 12;
9757 encode_arm_shifter_operand (1);
9760 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9767 top = (inst.instruction & 0x00400000) != 0;
9768 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
9769 _(":lower16: not allowed in this instruction"));
9770 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
9771 _(":upper16: not allowed in this instruction"));
9772 inst.instruction |= inst.operands[0].reg << 12;
9773 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
9775 imm = inst.relocs[0].exp.X_add_number;
9776 /* The value is in two pieces: 0:11, 16:19. */
9777 inst.instruction |= (imm & 0x00000fff);
9778 inst.instruction |= (imm & 0x0000f000) << 4;
9783 do_vfp_nsyn_mrs (void)
9785 if (inst.operands[0].isvec)
9787 if (inst.operands[1].reg != 1)
9788 first_error (_("operand 1 must be FPSCR"));
9789 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9790 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9791 do_vfp_nsyn_opcode ("fmstat");
9793 else if (inst.operands[1].isvec)
9794 do_vfp_nsyn_opcode ("fmrx");
9802 do_vfp_nsyn_msr (void)
9804 if (inst.operands[0].isvec)
9805 do_vfp_nsyn_opcode ("fmxr");
9815 unsigned Rt = inst.operands[0].reg;
9817 if (thumb_mode && Rt == REG_SP)
9819 inst.error = BAD_SP;
9823 /* MVFR2 is only valid at ARMv8-A. */
9824 if (inst.operands[1].reg == 5)
9825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9828 /* APSR_ sets isvec. All other refs to PC are illegal. */
9829 if (!inst.operands[0].isvec && Rt == REG_PC)
9831 inst.error = BAD_PC;
9835 /* If we get through parsing the register name, we just insert the number
9836 generated into the instruction without further validation. */
9837 inst.instruction |= (inst.operands[1].reg << 16);
9838 inst.instruction |= (Rt << 12);
9844 unsigned Rt = inst.operands[1].reg;
9847 reject_bad_reg (Rt);
9848 else if (Rt == REG_PC)
9850 inst.error = BAD_PC;
9854 /* MVFR2 is only valid for ARMv8-A. */
9855 if (inst.operands[0].reg == 5)
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9859 /* If we get through parsing the register name, we just insert the number
9860 generated into the instruction without further validation. */
9861 inst.instruction |= (inst.operands[0].reg << 16);
9862 inst.instruction |= (Rt << 12);
9870 if (do_vfp_nsyn_mrs () == SUCCESS)
9873 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9874 inst.instruction |= inst.operands[0].reg << 12;
9876 if (inst.operands[1].isreg)
9878 br = inst.operands[1].reg;
9879 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
9880 as_bad (_("bad register for mrs"));
9884 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9885 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9887 _("'APSR', 'CPSR' or 'SPSR' expected"));
9888 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9891 inst.instruction |= br;
9894 /* Two possible forms:
9895 "{C|S}PSR_<field>, Rm",
9896 "{C|S}PSR_f, #expression". */
9901 if (do_vfp_nsyn_msr () == SUCCESS)
9904 inst.instruction |= inst.operands[0].imm;
9905 if (inst.operands[1].isreg)
9906 inst.instruction |= inst.operands[1].reg;
9909 inst.instruction |= INST_IMMEDIATE;
9910 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9911 inst.relocs[0].pc_rel = 0;
9918 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9920 if (!inst.operands[2].present)
9921 inst.operands[2].reg = inst.operands[0].reg;
9922 inst.instruction |= inst.operands[0].reg << 16;
9923 inst.instruction |= inst.operands[1].reg;
9924 inst.instruction |= inst.operands[2].reg << 8;
9926 if (inst.operands[0].reg == inst.operands[1].reg
9927 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9928 as_tsktsk (_("Rd and Rm should be different in mul"));
9931 /* Long Multiply Parser
9932 UMULL RdLo, RdHi, Rm, Rs
9933 SMULL RdLo, RdHi, Rm, Rs
9934 UMLAL RdLo, RdHi, Rm, Rs
9935 SMLAL RdLo, RdHi, Rm, Rs. */
9940 inst.instruction |= inst.operands[0].reg << 12;
9941 inst.instruction |= inst.operands[1].reg << 16;
9942 inst.instruction |= inst.operands[2].reg;
9943 inst.instruction |= inst.operands[3].reg << 8;
9945 /* rdhi and rdlo must be different. */
9946 if (inst.operands[0].reg == inst.operands[1].reg)
9947 as_tsktsk (_("rdhi and rdlo must be different"));
9949 /* rdhi, rdlo and rm must all be different before armv6. */
9950 if ((inst.operands[0].reg == inst.operands[2].reg
9951 || inst.operands[1].reg == inst.operands[2].reg)
9952 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9953 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9959 if (inst.operands[0].present
9960 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9962 /* Architectural NOP hints are CPSR sets with no bits selected. */
9963 inst.instruction &= 0xf0000000;
9964 inst.instruction |= 0x0320f000;
9965 if (inst.operands[0].present)
9966 inst.instruction |= inst.operands[0].imm;
9970 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9971 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9972 Condition defaults to COND_ALWAYS.
9973 Error if Rd, Rn or Rm are R15. */
9978 inst.instruction |= inst.operands[0].reg << 12;
9979 inst.instruction |= inst.operands[1].reg << 16;
9980 inst.instruction |= inst.operands[2].reg;
9981 if (inst.operands[3].present)
9982 encode_arm_shift (3);
9985 /* ARM V6 PKHTB (Argument Parse). */
9990 if (!inst.operands[3].present)
9992 /* If the shift specifier is omitted, turn the instruction
9993 into pkhbt rd, rm, rn. */
9994 inst.instruction &= 0xfff00010;
9995 inst.instruction |= inst.operands[0].reg << 12;
9996 inst.instruction |= inst.operands[1].reg;
9997 inst.instruction |= inst.operands[2].reg << 16;
10001 inst.instruction |= inst.operands[0].reg << 12;
10002 inst.instruction |= inst.operands[1].reg << 16;
10003 inst.instruction |= inst.operands[2].reg;
10004 encode_arm_shift (3);
10008 /* ARMv5TE: Preload-Cache
10009 MP Extensions: Preload for write
10013 Syntactically, like LDR with B=1, W=0, L=1. */
10018 constraint (!inst.operands[0].isreg,
10019 _("'[' expected after PLD mnemonic"));
10020 constraint (inst.operands[0].postind,
10021 _("post-indexed expression used in preload instruction"));
10022 constraint (inst.operands[0].writeback,
10023 _("writeback used in preload instruction"));
10024 constraint (!inst.operands[0].preind,
10025 _("unindexed addressing used in preload instruction"));
10026 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10029 /* ARMv7: PLI <addr_mode> */
10033 constraint (!inst.operands[0].isreg,
10034 _("'[' expected after PLI mnemonic"));
10035 constraint (inst.operands[0].postind,
10036 _("post-indexed expression used in preload instruction"));
10037 constraint (inst.operands[0].writeback,
10038 _("writeback used in preload instruction"));
10039 constraint (!inst.operands[0].preind,
10040 _("unindexed addressing used in preload instruction"));
10041 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10042 inst.instruction &= ~PRE_INDEX;
10048 constraint (inst.operands[0].writeback,
10049 _("push/pop do not support {reglist}^"));
10050 inst.operands[1] = inst.operands[0];
10051 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10052 inst.operands[0].isreg = 1;
10053 inst.operands[0].writeback = 1;
10054 inst.operands[0].reg = REG_SP;
10055 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
10058 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10059 word at the specified address and the following word
10061 Unconditionally executed.
10062 Error if Rn is R15. */
10067 inst.instruction |= inst.operands[0].reg << 16;
10068 if (inst.operands[0].writeback)
10069 inst.instruction |= WRITE_BACK;
10072 /* ARM V6 ssat (argument parse). */
10077 inst.instruction |= inst.operands[0].reg << 12;
10078 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10079 inst.instruction |= inst.operands[2].reg;
10081 if (inst.operands[3].present)
10082 encode_arm_shift (3);
10085 /* ARM V6 usat (argument parse). */
10090 inst.instruction |= inst.operands[0].reg << 12;
10091 inst.instruction |= inst.operands[1].imm << 16;
10092 inst.instruction |= inst.operands[2].reg;
10094 if (inst.operands[3].present)
10095 encode_arm_shift (3);
10098 /* ARM V6 ssat16 (argument parse). */
10103 inst.instruction |= inst.operands[0].reg << 12;
10104 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10105 inst.instruction |= inst.operands[2].reg;
10111 inst.instruction |= inst.operands[0].reg << 12;
10112 inst.instruction |= inst.operands[1].imm << 16;
10113 inst.instruction |= inst.operands[2].reg;
10116 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10117 preserving the other bits.
10119 setend <endian_specifier>, where <endian_specifier> is either
10125 if (warn_on_deprecated
10126 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10127 as_tsktsk (_("setend use is deprecated for ARMv8"));
10129 if (inst.operands[0].imm)
10130 inst.instruction |= 0x200;
10136 unsigned int Rm = (inst.operands[1].present
10137 ? inst.operands[1].reg
10138 : inst.operands[0].reg);
10140 inst.instruction |= inst.operands[0].reg << 12;
10141 inst.instruction |= Rm;
10142 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10144 inst.instruction |= inst.operands[2].reg << 8;
10145 inst.instruction |= SHIFT_BY_REG;
10146 /* PR 12854: Error on extraneous shifts. */
10147 constraint (inst.operands[2].shifted,
10148 _("extraneous shift as part of operand to shift insn"));
10151 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10157 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10158 inst.relocs[0].pc_rel = 0;
10164 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10165 inst.relocs[0].pc_rel = 0;
10171 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10172 inst.relocs[0].pc_rel = 0;
10178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10179 _("selected processor does not support SETPAN instruction"));
10181 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10188 _("selected processor does not support SETPAN instruction"));
10190 inst.instruction |= (inst.operands[0].imm << 3);
10193 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10194 SMLAxy{cond} Rd,Rm,Rs,Rn
10195 SMLAWy{cond} Rd,Rm,Rs,Rn
10196 Error if any register is R15. */
10201 inst.instruction |= inst.operands[0].reg << 16;
10202 inst.instruction |= inst.operands[1].reg;
10203 inst.instruction |= inst.operands[2].reg << 8;
10204 inst.instruction |= inst.operands[3].reg << 12;
10207 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10208 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10209 Error if any register is R15.
10210 Warning if Rdlo == Rdhi. */
10215 inst.instruction |= inst.operands[0].reg << 12;
10216 inst.instruction |= inst.operands[1].reg << 16;
10217 inst.instruction |= inst.operands[2].reg;
10218 inst.instruction |= inst.operands[3].reg << 8;
10220 if (inst.operands[0].reg == inst.operands[1].reg)
10221 as_tsktsk (_("rdhi and rdlo must be different"));
10224 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10225 SMULxy{cond} Rd,Rm,Rs
10226 Error if any register is R15. */
10231 inst.instruction |= inst.operands[0].reg << 16;
10232 inst.instruction |= inst.operands[1].reg;
10233 inst.instruction |= inst.operands[2].reg << 8;
10236 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10237 the same for both ARM and Thumb-2. */
10244 if (inst.operands[0].present)
10246 reg = inst.operands[0].reg;
10247 constraint (reg != REG_SP, _("SRS base register must be r13"));
10252 inst.instruction |= reg << 16;
10253 inst.instruction |= inst.operands[1].imm;
10254 if (inst.operands[0].writeback || inst.operands[1].writeback)
10255 inst.instruction |= WRITE_BACK;
10258 /* ARM V6 strex (argument parse). */
10263 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10264 || inst.operands[2].postind || inst.operands[2].writeback
10265 || inst.operands[2].immisreg || inst.operands[2].shifted
10266 || inst.operands[2].negative
10267 /* See comment in do_ldrex(). */
10268 || (inst.operands[2].reg == REG_PC),
10271 constraint (inst.operands[0].reg == inst.operands[1].reg
10272 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10274 constraint (inst.relocs[0].exp.X_op != O_constant
10275 || inst.relocs[0].exp.X_add_number != 0,
10276 _("offset must be zero in ARM encoding"));
10278 inst.instruction |= inst.operands[0].reg << 12;
10279 inst.instruction |= inst.operands[1].reg;
10280 inst.instruction |= inst.operands[2].reg << 16;
10281 inst.relocs[0].type = BFD_RELOC_UNUSED;
10285 do_t_strexbh (void)
10287 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10288 || inst.operands[2].postind || inst.operands[2].writeback
10289 || inst.operands[2].immisreg || inst.operands[2].shifted
10290 || inst.operands[2].negative,
10293 constraint (inst.operands[0].reg == inst.operands[1].reg
10294 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10302 constraint (inst.operands[1].reg % 2 != 0,
10303 _("even register required"));
10304 constraint (inst.operands[2].present
10305 && inst.operands[2].reg != inst.operands[1].reg + 1,
10306 _("can only store two consecutive registers"));
10307 /* If op 2 were present and equal to PC, this function wouldn't
10308 have been called in the first place. */
10309 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10311 constraint (inst.operands[0].reg == inst.operands[1].reg
10312 || inst.operands[0].reg == inst.operands[1].reg + 1
10313 || inst.operands[0].reg == inst.operands[3].reg,
10316 inst.instruction |= inst.operands[0].reg << 12;
10317 inst.instruction |= inst.operands[1].reg;
10318 inst.instruction |= inst.operands[3].reg << 16;
10325 constraint (inst.operands[0].reg == inst.operands[1].reg
10326 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10334 constraint (inst.operands[0].reg == inst.operands[1].reg
10335 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10340 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10341 extends it to 32-bits, and adds the result to a value in another
10342 register. You can specify a rotation by 0, 8, 16, or 24 bits
10343 before extracting the 16-bit value.
10344 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10345 Condition defaults to COND_ALWAYS.
10346 Error if any register uses R15. */
10351 inst.instruction |= inst.operands[0].reg << 12;
10352 inst.instruction |= inst.operands[1].reg << 16;
10353 inst.instruction |= inst.operands[2].reg;
10354 inst.instruction |= inst.operands[3].imm << 10;
10359 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10360 Condition defaults to COND_ALWAYS.
10361 Error if any register uses R15. */
10366 inst.instruction |= inst.operands[0].reg << 12;
10367 inst.instruction |= inst.operands[1].reg;
10368 inst.instruction |= inst.operands[2].imm << 10;
10371 /* VFP instructions. In a logical order: SP variant first, monad
10372 before dyad, arithmetic then move then load/store. */
10375 do_vfp_sp_monadic (void)
10377 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10378 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10381 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10382 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10386 do_vfp_sp_dyadic (void)
10388 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10389 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10390 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10394 do_vfp_sp_compare_z (void)
10396 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10400 do_vfp_dp_sp_cvt (void)
10402 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10403 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10407 do_vfp_sp_dp_cvt (void)
10409 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10410 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10414 do_vfp_reg_from_sp (void)
10416 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10417 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10420 inst.instruction |= inst.operands[0].reg << 12;
10421 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10425 do_vfp_reg2_from_sp2 (void)
10427 constraint (inst.operands[2].imm != 2,
10428 _("only two consecutive VFP SP registers allowed here"));
10429 inst.instruction |= inst.operands[0].reg << 12;
10430 inst.instruction |= inst.operands[1].reg << 16;
10431 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10435 do_vfp_sp_from_reg (void)
10437 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10438 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10441 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10442 inst.instruction |= inst.operands[1].reg << 12;
10446 do_vfp_sp2_from_reg2 (void)
10448 constraint (inst.operands[0].imm != 2,
10449 _("only two consecutive VFP SP registers allowed here"));
10450 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10451 inst.instruction |= inst.operands[1].reg << 12;
10452 inst.instruction |= inst.operands[2].reg << 16;
10456 do_vfp_sp_ldst (void)
10458 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10459 encode_arm_cp_address (1, FALSE, TRUE, 0);
10463 do_vfp_dp_ldst (void)
10465 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10466 encode_arm_cp_address (1, FALSE, TRUE, 0);
10471 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
10473 if (inst.operands[0].writeback)
10474 inst.instruction |= WRITE_BACK;
10476 constraint (ldstm_type != VFP_LDSTMIA,
10477 _("this addressing mode requires base-register writeback"));
10478 inst.instruction |= inst.operands[0].reg << 16;
10479 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10480 inst.instruction |= inst.operands[1].imm;
10484 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
10488 if (inst.operands[0].writeback)
10489 inst.instruction |= WRITE_BACK;
10491 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10492 _("this addressing mode requires base-register writeback"));
10494 inst.instruction |= inst.operands[0].reg << 16;
10495 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10497 count = inst.operands[1].imm << 1;
10498 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10501 inst.instruction |= count;
10505 do_vfp_sp_ldstmia (void)
10507 vfp_sp_ldstm (VFP_LDSTMIA);
10511 do_vfp_sp_ldstmdb (void)
10513 vfp_sp_ldstm (VFP_LDSTMDB);
10517 do_vfp_dp_ldstmia (void)
10519 vfp_dp_ldstm (VFP_LDSTMIA);
10523 do_vfp_dp_ldstmdb (void)
10525 vfp_dp_ldstm (VFP_LDSTMDB);
10529 do_vfp_xp_ldstmia (void)
10531 vfp_dp_ldstm (VFP_LDSTMIAX);
10535 do_vfp_xp_ldstmdb (void)
10537 vfp_dp_ldstm (VFP_LDSTMDBX);
10541 do_vfp_dp_rd_rm (void)
10543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10544 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10547 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10548 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10552 do_vfp_dp_rn_rd (void)
10554 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10555 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10559 do_vfp_dp_rd_rn (void)
10561 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10562 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10566 do_vfp_dp_rd_rn_rm (void)
10568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10569 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10572 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10573 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10574 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10578 do_vfp_dp_rd (void)
10580 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10584 do_vfp_dp_rm_rd_rn (void)
10586 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10587 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10592 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10595 /* VFPv3 instructions. */
10597 do_vfp_sp_const (void)
10599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10600 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10601 inst.instruction |= (inst.operands[1].imm & 0x0f);
10605 do_vfp_dp_const (void)
10607 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10608 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10609 inst.instruction |= (inst.operands[1].imm & 0x0f);
10613 vfp_conv (int srcsize)
10615 int immbits = srcsize - inst.operands[1].imm;
10617 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10619 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10620 i.e. immbits must be in range 0 - 16. */
10621 inst.error = _("immediate value out of range, expected range [0, 16]");
10624 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
10626 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10627 i.e. immbits must be in range 0 - 31. */
10628 inst.error = _("immediate value out of range, expected range [1, 32]");
10632 inst.instruction |= (immbits & 1) << 5;
10633 inst.instruction |= (immbits >> 1);
10637 do_vfp_sp_conv_16 (void)
10639 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10644 do_vfp_dp_conv_16 (void)
10646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10651 do_vfp_sp_conv_32 (void)
10653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10658 do_vfp_dp_conv_32 (void)
10660 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10664 /* FPA instructions. Also in a logical order. */
10669 inst.instruction |= inst.operands[0].reg << 16;
10670 inst.instruction |= inst.operands[1].reg;
10674 do_fpa_ldmstm (void)
10676 inst.instruction |= inst.operands[0].reg << 12;
10677 switch (inst.operands[1].imm)
10679 case 1: inst.instruction |= CP_T_X; break;
10680 case 2: inst.instruction |= CP_T_Y; break;
10681 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10686 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10688 /* The instruction specified "ea" or "fd", so we can only accept
10689 [Rn]{!}. The instruction does not really support stacking or
10690 unstacking, so we have to emulate these by setting appropriate
10691 bits and offsets. */
10692 constraint (inst.relocs[0].exp.X_op != O_constant
10693 || inst.relocs[0].exp.X_add_number != 0,
10694 _("this instruction does not support indexing"));
10696 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
10697 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
10699 if (!(inst.instruction & INDEX_UP))
10700 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
10702 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10704 inst.operands[2].preind = 0;
10705 inst.operands[2].postind = 1;
10709 encode_arm_cp_address (2, TRUE, TRUE, 0);
10712 /* iWMMXt instructions: strictly in alphabetical order. */
10715 do_iwmmxt_tandorc (void)
10717 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10721 do_iwmmxt_textrc (void)
10723 inst.instruction |= inst.operands[0].reg << 12;
10724 inst.instruction |= inst.operands[1].imm;
10728 do_iwmmxt_textrm (void)
10730 inst.instruction |= inst.operands[0].reg << 12;
10731 inst.instruction |= inst.operands[1].reg << 16;
10732 inst.instruction |= inst.operands[2].imm;
10736 do_iwmmxt_tinsr (void)
10738 inst.instruction |= inst.operands[0].reg << 16;
10739 inst.instruction |= inst.operands[1].reg << 12;
10740 inst.instruction |= inst.operands[2].imm;
10744 do_iwmmxt_tmia (void)
10746 inst.instruction |= inst.operands[0].reg << 5;
10747 inst.instruction |= inst.operands[1].reg;
10748 inst.instruction |= inst.operands[2].reg << 12;
10752 do_iwmmxt_waligni (void)
10754 inst.instruction |= inst.operands[0].reg << 12;
10755 inst.instruction |= inst.operands[1].reg << 16;
10756 inst.instruction |= inst.operands[2].reg;
10757 inst.instruction |= inst.operands[3].imm << 20;
10761 do_iwmmxt_wmerge (void)
10763 inst.instruction |= inst.operands[0].reg << 12;
10764 inst.instruction |= inst.operands[1].reg << 16;
10765 inst.instruction |= inst.operands[2].reg;
10766 inst.instruction |= inst.operands[3].imm << 21;
10770 do_iwmmxt_wmov (void)
10772 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10773 inst.instruction |= inst.operands[0].reg << 12;
10774 inst.instruction |= inst.operands[1].reg << 16;
10775 inst.instruction |= inst.operands[1].reg;
10779 do_iwmmxt_wldstbh (void)
10782 inst.instruction |= inst.operands[0].reg << 12;
10784 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10786 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10787 encode_arm_cp_address (1, TRUE, FALSE, reloc);
10791 do_iwmmxt_wldstw (void)
10793 /* RIWR_RIWC clears .isreg for a control register. */
10794 if (!inst.operands[0].isreg)
10796 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10797 inst.instruction |= 0xf0000000;
10800 inst.instruction |= inst.operands[0].reg << 12;
10801 encode_arm_cp_address (1, TRUE, TRUE, 0);
10805 do_iwmmxt_wldstd (void)
10807 inst.instruction |= inst.operands[0].reg << 12;
10808 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10809 && inst.operands[1].immisreg)
10811 inst.instruction &= ~0x1a000ff;
10812 inst.instruction |= (0xfU << 28);
10813 if (inst.operands[1].preind)
10814 inst.instruction |= PRE_INDEX;
10815 if (!inst.operands[1].negative)
10816 inst.instruction |= INDEX_UP;
10817 if (inst.operands[1].writeback)
10818 inst.instruction |= WRITE_BACK;
10819 inst.instruction |= inst.operands[1].reg << 16;
10820 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
10821 inst.instruction |= inst.operands[1].imm;
10824 encode_arm_cp_address (1, TRUE, FALSE, 0);
10828 do_iwmmxt_wshufh (void)
10830 inst.instruction |= inst.operands[0].reg << 12;
10831 inst.instruction |= inst.operands[1].reg << 16;
10832 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10833 inst.instruction |= (inst.operands[2].imm & 0x0f);
10837 do_iwmmxt_wzero (void)
10839 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10840 inst.instruction |= inst.operands[0].reg;
10841 inst.instruction |= inst.operands[0].reg << 12;
10842 inst.instruction |= inst.operands[0].reg << 16;
10846 do_iwmmxt_wrwrwr_or_imm5 (void)
10848 if (inst.operands[2].isreg)
10851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10852 _("immediate operand requires iWMMXt2"));
10854 if (inst.operands[2].imm == 0)
10856 switch ((inst.instruction >> 20) & 0xf)
10862 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10863 inst.operands[2].imm = 16;
10864 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10870 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10871 inst.operands[2].imm = 32;
10872 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10879 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10881 wrn = (inst.instruction >> 16) & 0xf;
10882 inst.instruction &= 0xff0fff0f;
10883 inst.instruction |= wrn;
10884 /* Bail out here; the instruction is now assembled. */
10889 /* Map 32 -> 0, etc. */
10890 inst.operands[2].imm &= 0x1f;
10891 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10895 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10896 operations first, then control, shift, and load/store. */
10898 /* Insns like "foo X,Y,Z". */
10901 do_mav_triple (void)
10903 inst.instruction |= inst.operands[0].reg << 16;
10904 inst.instruction |= inst.operands[1].reg;
10905 inst.instruction |= inst.operands[2].reg << 12;
10908 /* Insns like "foo W,X,Y,Z".
10909 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10914 inst.instruction |= inst.operands[0].reg << 5;
10915 inst.instruction |= inst.operands[1].reg << 12;
10916 inst.instruction |= inst.operands[2].reg << 16;
10917 inst.instruction |= inst.operands[3].reg;
10920 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10922 do_mav_dspsc (void)
10924 inst.instruction |= inst.operands[1].reg << 12;
10927 /* Maverick shift immediate instructions.
10928 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10929 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10932 do_mav_shift (void)
10934 int imm = inst.operands[2].imm;
10936 inst.instruction |= inst.operands[0].reg << 12;
10937 inst.instruction |= inst.operands[1].reg << 16;
10939 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10940 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10941 Bit 4 should be 0. */
10942 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10944 inst.instruction |= imm;
10947 /* XScale instructions. Also sorted arithmetic before move. */
10949 /* Xscale multiply-accumulate (argument parse)
10952 MIAxycc acc0,Rm,Rs. */
10957 inst.instruction |= inst.operands[1].reg;
10958 inst.instruction |= inst.operands[2].reg << 12;
10961 /* Xscale move-accumulator-register (argument parse)
10963 MARcc acc0,RdLo,RdHi. */
10968 inst.instruction |= inst.operands[1].reg << 12;
10969 inst.instruction |= inst.operands[2].reg << 16;
10972 /* Xscale move-register-accumulator (argument parse)
10974 MRAcc RdLo,RdHi,acc0. */
10979 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10980 inst.instruction |= inst.operands[0].reg << 12;
10981 inst.instruction |= inst.operands[1].reg << 16;
10984 /* Encoding functions relevant only to Thumb. */
10986 /* inst.operands[i] is a shifted-register operand; encode
10987 it into inst.instruction in the format used by Thumb32. */
10990 encode_thumb32_shifted_operand (int i)
10992 unsigned int value = inst.relocs[0].exp.X_add_number;
10993 unsigned int shift = inst.operands[i].shift_kind;
10995 constraint (inst.operands[i].immisreg,
10996 _("shift by register not allowed in thumb mode"));
10997 inst.instruction |= inst.operands[i].reg;
10998 if (shift == SHIFT_RRX)
10999 inst.instruction |= SHIFT_ROR << 4;
11002 constraint (inst.relocs[0].exp.X_op != O_constant,
11003 _("expression too complex"));
11005 constraint (value > 32
11006 || (value == 32 && (shift == SHIFT_LSL
11007 || shift == SHIFT_ROR)),
11008 _("shift expression is too large"));
11012 else if (value == 32)
11015 inst.instruction |= shift << 4;
11016 inst.instruction |= (value & 0x1c) << 10;
11017 inst.instruction |= (value & 0x03) << 6;
11022 /* inst.operands[i] was set up by parse_address. Encode it into a
11023 Thumb32 format load or store instruction. Reject forms that cannot
11024 be used with such instructions. If is_t is true, reject forms that
11025 cannot be used with a T instruction; if is_d is true, reject forms
11026 that cannot be used with a D instruction. If it is a store insn,
11027 reject PC in Rn. */
11030 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11032 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
11034 constraint (!inst.operands[i].isreg,
11035 _("Instruction does not support =N addresses"));
11037 inst.instruction |= inst.operands[i].reg << 16;
11038 if (inst.operands[i].immisreg)
11040 constraint (is_pc, BAD_PC_ADDRESSING);
11041 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11042 constraint (inst.operands[i].negative,
11043 _("Thumb does not support negative register indexing"));
11044 constraint (inst.operands[i].postind,
11045 _("Thumb does not support register post-indexing"));
11046 constraint (inst.operands[i].writeback,
11047 _("Thumb does not support register indexing with writeback"));
11048 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11049 _("Thumb supports only LSL in shifted register indexing"));
11051 inst.instruction |= inst.operands[i].imm;
11052 if (inst.operands[i].shifted)
11054 constraint (inst.relocs[0].exp.X_op != O_constant,
11055 _("expression too complex"));
11056 constraint (inst.relocs[0].exp.X_add_number < 0
11057 || inst.relocs[0].exp.X_add_number > 3,
11058 _("shift out of range"));
11059 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11061 inst.relocs[0].type = BFD_RELOC_UNUSED;
11063 else if (inst.operands[i].preind)
11065 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11066 constraint (is_t && inst.operands[i].writeback,
11067 _("cannot use writeback with this instruction"));
11068 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11069 BAD_PC_ADDRESSING);
11073 inst.instruction |= 0x01000000;
11074 if (inst.operands[i].writeback)
11075 inst.instruction |= 0x00200000;
11079 inst.instruction |= 0x00000c00;
11080 if (inst.operands[i].writeback)
11081 inst.instruction |= 0x00000100;
11083 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11085 else if (inst.operands[i].postind)
11087 gas_assert (inst.operands[i].writeback);
11088 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11089 constraint (is_t, _("cannot use post-indexing with this instruction"));
11092 inst.instruction |= 0x00200000;
11094 inst.instruction |= 0x00000900;
11095 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11097 else /* unindexed - only for coprocessor */
11098 inst.error = _("instruction does not accept unindexed addressing");
11101 /* Table of Thumb instructions which exist in both 16- and 32-bit
11102 encodings (the latter only in post-V6T2 cores). The index is the
11103 value used in the insns table below. When there is more than one
11104 possible 16-bit encoding for the instruction, this table always
11106 Also contains several pseudo-instructions used during relaxation. */
11107 #define T16_32_TAB \
11108 X(_adc, 4140, eb400000), \
11109 X(_adcs, 4140, eb500000), \
11110 X(_add, 1c00, eb000000), \
11111 X(_adds, 1c00, eb100000), \
11112 X(_addi, 0000, f1000000), \
11113 X(_addis, 0000, f1100000), \
11114 X(_add_pc,000f, f20f0000), \
11115 X(_add_sp,000d, f10d0000), \
11116 X(_adr, 000f, f20f0000), \
11117 X(_and, 4000, ea000000), \
11118 X(_ands, 4000, ea100000), \
11119 X(_asr, 1000, fa40f000), \
11120 X(_asrs, 1000, fa50f000), \
11121 X(_b, e000, f000b000), \
11122 X(_bcond, d000, f0008000), \
11123 X(_bf, 0000, f040e001), \
11124 X(_bfcsel,0000, f000e001), \
11125 X(_bfx, 0000, f060e001), \
11126 X(_bfl, 0000, f000c001), \
11127 X(_bflx, 0000, f070e001), \
11128 X(_bic, 4380, ea200000), \
11129 X(_bics, 4380, ea300000), \
11130 X(_cmn, 42c0, eb100f00), \
11131 X(_cmp, 2800, ebb00f00), \
11132 X(_cpsie, b660, f3af8400), \
11133 X(_cpsid, b670, f3af8600), \
11134 X(_cpy, 4600, ea4f0000), \
11135 X(_dec_sp,80dd, f1ad0d00), \
11136 X(_dls, 0000, f040e001), \
11137 X(_eor, 4040, ea800000), \
11138 X(_eors, 4040, ea900000), \
11139 X(_inc_sp,00dd, f10d0d00), \
11140 X(_ldmia, c800, e8900000), \
11141 X(_ldr, 6800, f8500000), \
11142 X(_ldrb, 7800, f8100000), \
11143 X(_ldrh, 8800, f8300000), \
11144 X(_ldrsb, 5600, f9100000), \
11145 X(_ldrsh, 5e00, f9300000), \
11146 X(_ldr_pc,4800, f85f0000), \
11147 X(_ldr_pc2,4800, f85f0000), \
11148 X(_ldr_sp,9800, f85d0000), \
11149 X(_le, 0000, f00fc001), \
11150 X(_lsl, 0000, fa00f000), \
11151 X(_lsls, 0000, fa10f000), \
11152 X(_lsr, 0800, fa20f000), \
11153 X(_lsrs, 0800, fa30f000), \
11154 X(_mov, 2000, ea4f0000), \
11155 X(_movs, 2000, ea5f0000), \
11156 X(_mul, 4340, fb00f000), \
11157 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11158 X(_mvn, 43c0, ea6f0000), \
11159 X(_mvns, 43c0, ea7f0000), \
11160 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11161 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11162 X(_orr, 4300, ea400000), \
11163 X(_orrs, 4300, ea500000), \
11164 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11165 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11166 X(_rev, ba00, fa90f080), \
11167 X(_rev16, ba40, fa90f090), \
11168 X(_revsh, bac0, fa90f0b0), \
11169 X(_ror, 41c0, fa60f000), \
11170 X(_rors, 41c0, fa70f000), \
11171 X(_sbc, 4180, eb600000), \
11172 X(_sbcs, 4180, eb700000), \
11173 X(_stmia, c000, e8800000), \
11174 X(_str, 6000, f8400000), \
11175 X(_strb, 7000, f8000000), \
11176 X(_strh, 8000, f8200000), \
11177 X(_str_sp,9000, f84d0000), \
11178 X(_sub, 1e00, eba00000), \
11179 X(_subs, 1e00, ebb00000), \
11180 X(_subi, 8000, f1a00000), \
11181 X(_subis, 8000, f1b00000), \
11182 X(_sxtb, b240, fa4ff080), \
11183 X(_sxth, b200, fa0ff080), \
11184 X(_tst, 4200, ea100f00), \
11185 X(_uxtb, b2c0, fa5ff080), \
11186 X(_uxth, b280, fa1ff080), \
11187 X(_nop, bf00, f3af8000), \
11188 X(_yield, bf10, f3af8001), \
11189 X(_wfe, bf20, f3af8002), \
11190 X(_wfi, bf30, f3af8003), \
11191 X(_wls, 0000, f040c001), \
11192 X(_sev, bf40, f3af8004), \
11193 X(_sevl, bf50, f3af8005), \
11194 X(_udf, de00, f7f0a000)
11196 /* To catch errors in encoding functions, the codes are all offset by
11197 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11198 as 16-bit instructions. */
11199 #define X(a,b,c) T_MNEM##a
11200 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11203 #define X(a,b,c) 0x##b
11204 static const unsigned short thumb_op16[] = { T16_32_TAB };
11205 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11208 #define X(a,b,c) 0x##c
11209 static const unsigned int thumb_op32[] = { T16_32_TAB };
11210 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11211 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11215 /* Thumb instruction encoders, in alphabetical order. */
11217 /* ADDW or SUBW. */
11220 do_t_add_sub_w (void)
11224 Rd = inst.operands[0].reg;
11225 Rn = inst.operands[1].reg;
11227 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11228 is the SP-{plus,minus}-immediate form of the instruction. */
11230 constraint (Rd == REG_PC, BAD_PC);
11232 reject_bad_reg (Rd);
11234 inst.instruction |= (Rn << 16) | (Rd << 8);
11235 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11238 /* Parse an add or subtract instruction. We get here with inst.instruction
11239 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11242 do_t_add_sub (void)
11246 Rd = inst.operands[0].reg;
11247 Rs = (inst.operands[1].present
11248 ? inst.operands[1].reg /* Rd, Rs, foo */
11249 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11252 set_pred_insn_type_last ();
11254 if (unified_syntax)
11257 bfd_boolean narrow;
11260 flags = (inst.instruction == T_MNEM_adds
11261 || inst.instruction == T_MNEM_subs);
11263 narrow = !in_pred_block ();
11265 narrow = in_pred_block ();
11266 if (!inst.operands[2].isreg)
11270 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11271 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11273 add = (inst.instruction == T_MNEM_add
11274 || inst.instruction == T_MNEM_adds);
11276 if (inst.size_req != 4)
11278 /* Attempt to use a narrow opcode, with relaxation if
11280 if (Rd == REG_SP && Rs == REG_SP && !flags)
11281 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11282 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11283 opcode = T_MNEM_add_sp;
11284 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11285 opcode = T_MNEM_add_pc;
11286 else if (Rd <= 7 && Rs <= 7 && narrow)
11289 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11291 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11295 inst.instruction = THUMB_OP16(opcode);
11296 inst.instruction |= (Rd << 4) | Rs;
11297 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11298 || (inst.relocs[0].type
11299 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
11301 if (inst.size_req == 2)
11302 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11304 inst.relax = opcode;
11308 constraint (inst.size_req == 2, BAD_HIREG);
11310 if (inst.size_req == 4
11311 || (inst.size_req != 2 && !opcode))
11313 constraint ((inst.relocs[0].type
11314 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11315 && (inst.relocs[0].type
11316 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
11317 THUMB1_RELOC_ONLY);
11320 constraint (add, BAD_PC);
11321 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11322 _("only SUBS PC, LR, #const allowed"));
11323 constraint (inst.relocs[0].exp.X_op != O_constant,
11324 _("expression too complex"));
11325 constraint (inst.relocs[0].exp.X_add_number < 0
11326 || inst.relocs[0].exp.X_add_number > 0xff,
11327 _("immediate value out of range"));
11328 inst.instruction = T2_SUBS_PC_LR
11329 | inst.relocs[0].exp.X_add_number;
11330 inst.relocs[0].type = BFD_RELOC_UNUSED;
11333 else if (Rs == REG_PC)
11335 /* Always use addw/subw. */
11336 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11337 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11341 inst.instruction = THUMB_OP32 (inst.instruction);
11342 inst.instruction = (inst.instruction & 0xe1ffffff)
11345 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11347 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11349 inst.instruction |= Rd << 8;
11350 inst.instruction |= Rs << 16;
11355 unsigned int value = inst.relocs[0].exp.X_add_number;
11356 unsigned int shift = inst.operands[2].shift_kind;
11358 Rn = inst.operands[2].reg;
11359 /* See if we can do this with a 16-bit instruction. */
11360 if (!inst.operands[2].shifted && inst.size_req != 4)
11362 if (Rd > 7 || Rs > 7 || Rn > 7)
11367 inst.instruction = ((inst.instruction == T_MNEM_adds
11368 || inst.instruction == T_MNEM_add)
11370 : T_OPCODE_SUB_R3);
11371 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11375 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11377 /* Thumb-1 cores (except v6-M) require at least one high
11378 register in a narrow non flag setting add. */
11379 if (Rd > 7 || Rn > 7
11380 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11381 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
11388 inst.instruction = T_OPCODE_ADD_HI;
11389 inst.instruction |= (Rd & 8) << 4;
11390 inst.instruction |= (Rd & 7);
11391 inst.instruction |= Rn << 3;
11397 constraint (Rd == REG_PC, BAD_PC);
11398 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11399 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11400 constraint (Rs == REG_PC, BAD_PC);
11401 reject_bad_reg (Rn);
11403 /* If we get here, it can't be done in 16 bits. */
11404 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11405 _("shift must be constant"));
11406 inst.instruction = THUMB_OP32 (inst.instruction);
11407 inst.instruction |= Rd << 8;
11408 inst.instruction |= Rs << 16;
11409 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11410 _("shift value over 3 not allowed in thumb mode"));
11411 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11412 _("only LSL shift allowed in thumb mode"));
11413 encode_thumb32_shifted_operand (2);
11418 constraint (inst.instruction == T_MNEM_adds
11419 || inst.instruction == T_MNEM_subs,
11422 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11424 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11425 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11428 inst.instruction = (inst.instruction == T_MNEM_add
11429 ? 0x0000 : 0x8000);
11430 inst.instruction |= (Rd << 4) | Rs;
11431 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11435 Rn = inst.operands[2].reg;
11436 constraint (inst.operands[2].shifted, _("unshifted register required"));
11438 /* We now have Rd, Rs, and Rn set to registers. */
11439 if (Rd > 7 || Rs > 7 || Rn > 7)
11441 /* Can't do this for SUB. */
11442 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11443 inst.instruction = T_OPCODE_ADD_HI;
11444 inst.instruction |= (Rd & 8) << 4;
11445 inst.instruction |= (Rd & 7);
11447 inst.instruction |= Rn << 3;
11449 inst.instruction |= Rs << 3;
11451 constraint (1, _("dest must overlap one source register"));
11455 inst.instruction = (inst.instruction == T_MNEM_add
11456 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11457 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11467 Rd = inst.operands[0].reg;
11468 reject_bad_reg (Rd);
11470 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11472 /* Defer to section relaxation. */
11473 inst.relax = inst.instruction;
11474 inst.instruction = THUMB_OP16 (inst.instruction);
11475 inst.instruction |= Rd << 4;
11477 else if (unified_syntax && inst.size_req != 2)
11479 /* Generate a 32-bit opcode. */
11480 inst.instruction = THUMB_OP32 (inst.instruction);
11481 inst.instruction |= Rd << 8;
11482 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11483 inst.relocs[0].pc_rel = 1;
11487 /* Generate a 16-bit opcode. */
11488 inst.instruction = THUMB_OP16 (inst.instruction);
11489 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11490 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11491 inst.relocs[0].pc_rel = 1;
11492 inst.instruction |= Rd << 4;
11495 if (inst.relocs[0].exp.X_op == O_symbol
11496 && inst.relocs[0].exp.X_add_symbol != NULL
11497 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11498 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11499 inst.relocs[0].exp.X_add_number += 1;
11502 /* Arithmetic instructions for which there is just one 16-bit
11503 instruction encoding, and it allows only two low registers.
11504 For maximal compatibility with ARM syntax, we allow three register
11505 operands even when Thumb-32 instructions are not available, as long
11506 as the first two are identical. For instance, both "sbc r0,r1" and
11507 "sbc r0,r0,r1" are allowed. */
11513 Rd = inst.operands[0].reg;
11514 Rs = (inst.operands[1].present
11515 ? inst.operands[1].reg /* Rd, Rs, foo */
11516 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11517 Rn = inst.operands[2].reg;
11519 reject_bad_reg (Rd);
11520 reject_bad_reg (Rs);
11521 if (inst.operands[2].isreg)
11522 reject_bad_reg (Rn);
11524 if (unified_syntax)
11526 if (!inst.operands[2].isreg)
11528 /* For an immediate, we always generate a 32-bit opcode;
11529 section relaxation will shrink it later if possible. */
11530 inst.instruction = THUMB_OP32 (inst.instruction);
11531 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11532 inst.instruction |= Rd << 8;
11533 inst.instruction |= Rs << 16;
11534 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11538 bfd_boolean narrow;
11540 /* See if we can do this with a 16-bit instruction. */
11541 if (THUMB_SETS_FLAGS (inst.instruction))
11542 narrow = !in_pred_block ();
11544 narrow = in_pred_block ();
11546 if (Rd > 7 || Rn > 7 || Rs > 7)
11548 if (inst.operands[2].shifted)
11550 if (inst.size_req == 4)
11556 inst.instruction = THUMB_OP16 (inst.instruction);
11557 inst.instruction |= Rd;
11558 inst.instruction |= Rn << 3;
11562 /* If we get here, it can't be done in 16 bits. */
11563 constraint (inst.operands[2].shifted
11564 && inst.operands[2].immisreg,
11565 _("shift must be constant"));
11566 inst.instruction = THUMB_OP32 (inst.instruction);
11567 inst.instruction |= Rd << 8;
11568 inst.instruction |= Rs << 16;
11569 encode_thumb32_shifted_operand (2);
11574 /* On its face this is a lie - the instruction does set the
11575 flags. However, the only supported mnemonic in this mode
11576 says it doesn't. */
11577 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11579 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11580 _("unshifted register required"));
11581 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11582 constraint (Rd != Rs,
11583 _("dest and source1 must be the same register"));
11585 inst.instruction = THUMB_OP16 (inst.instruction);
11586 inst.instruction |= Rd;
11587 inst.instruction |= Rn << 3;
11591 /* Similarly, but for instructions where the arithmetic operation is
11592 commutative, so we can allow either of them to be different from
11593 the destination operand in a 16-bit instruction. For instance, all
11594 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11601 Rd = inst.operands[0].reg;
11602 Rs = (inst.operands[1].present
11603 ? inst.operands[1].reg /* Rd, Rs, foo */
11604 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11605 Rn = inst.operands[2].reg;
11607 reject_bad_reg (Rd);
11608 reject_bad_reg (Rs);
11609 if (inst.operands[2].isreg)
11610 reject_bad_reg (Rn);
11612 if (unified_syntax)
11614 if (!inst.operands[2].isreg)
11616 /* For an immediate, we always generate a 32-bit opcode;
11617 section relaxation will shrink it later if possible. */
11618 inst.instruction = THUMB_OP32 (inst.instruction);
11619 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11620 inst.instruction |= Rd << 8;
11621 inst.instruction |= Rs << 16;
11622 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11626 bfd_boolean narrow;
11628 /* See if we can do this with a 16-bit instruction. */
11629 if (THUMB_SETS_FLAGS (inst.instruction))
11630 narrow = !in_pred_block ();
11632 narrow = in_pred_block ();
11634 if (Rd > 7 || Rn > 7 || Rs > 7)
11636 if (inst.operands[2].shifted)
11638 if (inst.size_req == 4)
11645 inst.instruction = THUMB_OP16 (inst.instruction);
11646 inst.instruction |= Rd;
11647 inst.instruction |= Rn << 3;
11652 inst.instruction = THUMB_OP16 (inst.instruction);
11653 inst.instruction |= Rd;
11654 inst.instruction |= Rs << 3;
11659 /* If we get here, it can't be done in 16 bits. */
11660 constraint (inst.operands[2].shifted
11661 && inst.operands[2].immisreg,
11662 _("shift must be constant"));
11663 inst.instruction = THUMB_OP32 (inst.instruction);
11664 inst.instruction |= Rd << 8;
11665 inst.instruction |= Rs << 16;
11666 encode_thumb32_shifted_operand (2);
11671 /* On its face this is a lie - the instruction does set the
11672 flags. However, the only supported mnemonic in this mode
11673 says it doesn't. */
11674 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11676 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11677 _("unshifted register required"));
11678 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11680 inst.instruction = THUMB_OP16 (inst.instruction);
11681 inst.instruction |= Rd;
11684 inst.instruction |= Rn << 3;
11686 inst.instruction |= Rs << 3;
11688 constraint (1, _("dest must overlap one source register"));
11696 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11697 constraint (msb > 32, _("bit-field extends past end of register"));
11698 /* The instruction encoding stores the LSB and MSB,
11699 not the LSB and width. */
11700 Rd = inst.operands[0].reg;
11701 reject_bad_reg (Rd);
11702 inst.instruction |= Rd << 8;
11703 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11704 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11705 inst.instruction |= msb - 1;
11714 Rd = inst.operands[0].reg;
11715 reject_bad_reg (Rd);
11717 /* #0 in second position is alternative syntax for bfc, which is
11718 the same instruction but with REG_PC in the Rm field. */
11719 if (!inst.operands[1].isreg)
11723 Rn = inst.operands[1].reg;
11724 reject_bad_reg (Rn);
11727 msb = inst.operands[2].imm + inst.operands[3].imm;
11728 constraint (msb > 32, _("bit-field extends past end of register"));
11729 /* The instruction encoding stores the LSB and MSB,
11730 not the LSB and width. */
11731 inst.instruction |= Rd << 8;
11732 inst.instruction |= Rn << 16;
11733 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11734 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11735 inst.instruction |= msb - 1;
11743 Rd = inst.operands[0].reg;
11744 Rn = inst.operands[1].reg;
11746 reject_bad_reg (Rd);
11747 reject_bad_reg (Rn);
11749 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11750 _("bit-field extends past end of register"));
11751 inst.instruction |= Rd << 8;
11752 inst.instruction |= Rn << 16;
11753 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11754 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11755 inst.instruction |= inst.operands[3].imm - 1;
11758 /* ARM V5 Thumb BLX (argument parse)
11759 BLX <target_addr> which is BLX(1)
11760 BLX <Rm> which is BLX(2)
11761 Unfortunately, there are two different opcodes for this mnemonic.
11762 So, the insns[].value is not used, and the code here zaps values
11763 into inst.instruction.
11765 ??? How to take advantage of the additional two bits of displacement
11766 available in Thumb32 mode? Need new relocation? */
11771 set_pred_insn_type_last ();
11773 if (inst.operands[0].isreg)
11775 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11776 /* We have a register, so this is BLX(2). */
11777 inst.instruction |= inst.operands[0].reg << 3;
11781 /* No register. This must be BLX(1). */
11782 inst.instruction = 0xf000e800;
11783 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
11792 bfd_reloc_code_real_type reloc;
11795 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
11797 if (in_pred_block ())
11799 /* Conditional branches inside IT blocks are encoded as unconditional
11801 cond = COND_ALWAYS;
11806 if (cond != COND_ALWAYS)
11807 opcode = T_MNEM_bcond;
11809 opcode = inst.instruction;
11812 && (inst.size_req == 4
11813 || (inst.size_req != 2
11814 && (inst.operands[0].hasreloc
11815 || inst.relocs[0].exp.X_op == O_constant))))
11817 inst.instruction = THUMB_OP32(opcode);
11818 if (cond == COND_ALWAYS)
11819 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11822 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11823 _("selected architecture does not support "
11824 "wide conditional branch instruction"));
11826 gas_assert (cond != 0xF);
11827 inst.instruction |= cond << 22;
11828 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11833 inst.instruction = THUMB_OP16(opcode);
11834 if (cond == COND_ALWAYS)
11835 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11838 inst.instruction |= cond << 8;
11839 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11841 /* Allow section relaxation. */
11842 if (unified_syntax && inst.size_req != 2)
11843 inst.relax = opcode;
11845 inst.relocs[0].type = reloc;
11846 inst.relocs[0].pc_rel = 1;
11849 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11850 between the two is the maximum immediate allowed - which is passed in
11853 do_t_bkpt_hlt1 (int range)
11855 constraint (inst.cond != COND_ALWAYS,
11856 _("instruction is always unconditional"));
11857 if (inst.operands[0].present)
11859 constraint (inst.operands[0].imm > range,
11860 _("immediate value out of range"));
11861 inst.instruction |= inst.operands[0].imm;
11864 set_pred_insn_type (NEUTRAL_IT_INSN);
11870 do_t_bkpt_hlt1 (63);
11876 do_t_bkpt_hlt1 (255);
11880 do_t_branch23 (void)
11882 set_pred_insn_type_last ();
11883 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11885 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11886 this file. We used to simply ignore the PLT reloc type here --
11887 the branch encoding is now needed to deal with TLSCALL relocs.
11888 So if we see a PLT reloc now, put it back to how it used to be to
11889 keep the preexisting behaviour. */
11890 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
11891 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11893 #if defined(OBJ_COFF)
11894 /* If the destination of the branch is a defined symbol which does not have
11895 the THUMB_FUNC attribute, then we must be calling a function which has
11896 the (interfacearm) attribute. We look for the Thumb entry point to that
11897 function and change the branch to refer to that function instead. */
11898 if ( inst.relocs[0].exp.X_op == O_symbol
11899 && inst.relocs[0].exp.X_add_symbol != NULL
11900 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11901 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11902 inst.relocs[0].exp.X_add_symbol
11903 = find_real_start (inst.relocs[0].exp.X_add_symbol);
11910 set_pred_insn_type_last ();
11911 inst.instruction |= inst.operands[0].reg << 3;
11912 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11913 should cause the alignment to be checked once it is known. This is
11914 because BX PC only works if the instruction is word aligned. */
11922 set_pred_insn_type_last ();
11923 Rm = inst.operands[0].reg;
11924 reject_bad_reg (Rm);
11925 inst.instruction |= Rm << 16;
11934 Rd = inst.operands[0].reg;
11935 Rm = inst.operands[1].reg;
11937 reject_bad_reg (Rd);
11938 reject_bad_reg (Rm);
11940 inst.instruction |= Rd << 8;
11941 inst.instruction |= Rm << 16;
11942 inst.instruction |= Rm;
11948 set_pred_insn_type (OUTSIDE_PRED_INSN);
11954 set_pred_insn_type (OUTSIDE_PRED_INSN);
11955 inst.instruction |= inst.operands[0].imm;
11961 set_pred_insn_type (OUTSIDE_PRED_INSN);
11963 && (inst.operands[1].present || inst.size_req == 4)
11964 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11966 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11967 inst.instruction = 0xf3af8000;
11968 inst.instruction |= imod << 9;
11969 inst.instruction |= inst.operands[0].imm << 5;
11970 if (inst.operands[1].present)
11971 inst.instruction |= 0x100 | inst.operands[1].imm;
11975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11976 && (inst.operands[0].imm & 4),
11977 _("selected processor does not support 'A' form "
11978 "of this instruction"));
11979 constraint (inst.operands[1].present || inst.size_req == 4,
11980 _("Thumb does not support the 2-argument "
11981 "form of this instruction"));
11982 inst.instruction |= inst.operands[0].imm;
11986 /* THUMB CPY instruction (argument parse). */
11991 if (inst.size_req == 4)
11993 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11994 inst.instruction |= inst.operands[0].reg << 8;
11995 inst.instruction |= inst.operands[1].reg;
11999 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12000 inst.instruction |= (inst.operands[0].reg & 0x7);
12001 inst.instruction |= inst.operands[1].reg << 3;
12008 set_pred_insn_type (OUTSIDE_PRED_INSN);
12009 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12010 inst.instruction |= inst.operands[0].reg;
12011 inst.relocs[0].pc_rel = 1;
12012 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
12018 inst.instruction |= inst.operands[0].imm;
12024 unsigned Rd, Rn, Rm;
12026 Rd = inst.operands[0].reg;
12027 Rn = (inst.operands[1].present
12028 ? inst.operands[1].reg : Rd);
12029 Rm = inst.operands[2].reg;
12031 reject_bad_reg (Rd);
12032 reject_bad_reg (Rn);
12033 reject_bad_reg (Rm);
12035 inst.instruction |= Rd << 8;
12036 inst.instruction |= Rn << 16;
12037 inst.instruction |= Rm;
12043 if (unified_syntax && inst.size_req == 4)
12044 inst.instruction = THUMB_OP32 (inst.instruction);
12046 inst.instruction = THUMB_OP16 (inst.instruction);
12052 unsigned int cond = inst.operands[0].imm;
12054 set_pred_insn_type (IT_INSN);
12055 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12056 now_pred.cc = cond;
12057 now_pred.warn_deprecated = FALSE;
12058 now_pred.type = SCALAR_PRED;
12060 /* If the condition is a negative condition, invert the mask. */
12061 if ((cond & 0x1) == 0x0)
12063 unsigned int mask = inst.instruction & 0x000f;
12065 if ((mask & 0x7) == 0)
12067 /* No conversion needed. */
12068 now_pred.block_length = 1;
12070 else if ((mask & 0x3) == 0)
12073 now_pred.block_length = 2;
12075 else if ((mask & 0x1) == 0)
12078 now_pred.block_length = 3;
12083 now_pred.block_length = 4;
12086 inst.instruction &= 0xfff0;
12087 inst.instruction |= mask;
12090 inst.instruction |= cond << 4;
12093 /* Helper function used for both push/pop and ldm/stm. */
12095 encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12096 bfd_boolean writeback)
12098 bfd_boolean load, store;
12100 gas_assert (base != -1 || !do_io);
12101 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12102 store = do_io && !load;
12104 if (mask & (1 << 13))
12105 inst.error = _("SP not allowed in register list");
12107 if (do_io && (mask & (1 << base)) != 0
12109 inst.error = _("having the base register in the register list when "
12110 "using write back is UNPREDICTABLE");
12114 if (mask & (1 << 15))
12116 if (mask & (1 << 14))
12117 inst.error = _("LR and PC should not both be in register list");
12119 set_pred_insn_type_last ();
12124 if (mask & (1 << 15))
12125 inst.error = _("PC not allowed in register list");
12128 if (do_io && ((mask & (mask - 1)) == 0))
12130 /* Single register transfers implemented as str/ldr. */
12133 if (inst.instruction & (1 << 23))
12134 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12136 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12140 if (inst.instruction & (1 << 23))
12141 inst.instruction = 0x00800000; /* ia -> [base] */
12143 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12146 inst.instruction |= 0xf8400000;
12148 inst.instruction |= 0x00100000;
12150 mask = ffs (mask) - 1;
12153 else if (writeback)
12154 inst.instruction |= WRITE_BACK;
12156 inst.instruction |= mask;
12158 inst.instruction |= base << 16;
12164 /* This really doesn't seem worth it. */
12165 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12166 _("expression too complex"));
12167 constraint (inst.operands[1].writeback,
12168 _("Thumb load/store multiple does not support {reglist}^"));
12170 if (unified_syntax)
12172 bfd_boolean narrow;
12176 /* See if we can use a 16-bit instruction. */
12177 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12178 && inst.size_req != 4
12179 && !(inst.operands[1].imm & ~0xff))
12181 mask = 1 << inst.operands[0].reg;
12183 if (inst.operands[0].reg <= 7)
12185 if (inst.instruction == T_MNEM_stmia
12186 ? inst.operands[0].writeback
12187 : (inst.operands[0].writeback
12188 == !(inst.operands[1].imm & mask)))
12190 if (inst.instruction == T_MNEM_stmia
12191 && (inst.operands[1].imm & mask)
12192 && (inst.operands[1].imm & (mask - 1)))
12193 as_warn (_("value stored for r%d is UNKNOWN"),
12194 inst.operands[0].reg);
12196 inst.instruction = THUMB_OP16 (inst.instruction);
12197 inst.instruction |= inst.operands[0].reg << 8;
12198 inst.instruction |= inst.operands[1].imm;
12201 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12203 /* This means 1 register in reg list one of 3 situations:
12204 1. Instruction is stmia, but without writeback.
12205 2. lmdia without writeback, but with Rn not in
12207 3. ldmia with writeback, but with Rn in reglist.
12208 Case 3 is UNPREDICTABLE behaviour, so we handle
12209 case 1 and 2 which can be converted into a 16-bit
12210 str or ldr. The SP cases are handled below. */
12211 unsigned long opcode;
12212 /* First, record an error for Case 3. */
12213 if (inst.operands[1].imm & mask
12214 && inst.operands[0].writeback)
12216 _("having the base register in the register list when "
12217 "using write back is UNPREDICTABLE");
12219 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
12221 inst.instruction = THUMB_OP16 (opcode);
12222 inst.instruction |= inst.operands[0].reg << 3;
12223 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12227 else if (inst.operands[0] .reg == REG_SP)
12229 if (inst.operands[0].writeback)
12232 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12233 ? T_MNEM_push : T_MNEM_pop);
12234 inst.instruction |= inst.operands[1].imm;
12237 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12240 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12241 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
12242 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
12250 if (inst.instruction < 0xffff)
12251 inst.instruction = THUMB_OP32 (inst.instruction);
12253 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12254 inst.operands[1].imm,
12255 inst.operands[0].writeback);
12260 constraint (inst.operands[0].reg > 7
12261 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12262 constraint (inst.instruction != T_MNEM_ldmia
12263 && inst.instruction != T_MNEM_stmia,
12264 _("Thumb-2 instruction only valid in unified syntax"));
12265 if (inst.instruction == T_MNEM_stmia)
12267 if (!inst.operands[0].writeback)
12268 as_warn (_("this instruction will write back the base register"));
12269 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12270 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12271 as_warn (_("value stored for r%d is UNKNOWN"),
12272 inst.operands[0].reg);
12276 if (!inst.operands[0].writeback
12277 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12278 as_warn (_("this instruction will write back the base register"));
12279 else if (inst.operands[0].writeback
12280 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12281 as_warn (_("this instruction will not write back the base register"));
12284 inst.instruction = THUMB_OP16 (inst.instruction);
12285 inst.instruction |= inst.operands[0].reg << 8;
12286 inst.instruction |= inst.operands[1].imm;
12293 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12294 || inst.operands[1].postind || inst.operands[1].writeback
12295 || inst.operands[1].immisreg || inst.operands[1].shifted
12296 || inst.operands[1].negative,
12299 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12301 inst.instruction |= inst.operands[0].reg << 12;
12302 inst.instruction |= inst.operands[1].reg << 16;
12303 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12309 if (!inst.operands[1].present)
12311 constraint (inst.operands[0].reg == REG_LR,
12312 _("r14 not allowed as first register "
12313 "when second register is omitted"));
12314 inst.operands[1].reg = inst.operands[0].reg + 1;
12316 constraint (inst.operands[0].reg == inst.operands[1].reg,
12319 inst.instruction |= inst.operands[0].reg << 12;
12320 inst.instruction |= inst.operands[1].reg << 8;
12321 inst.instruction |= inst.operands[2].reg << 16;
12327 unsigned long opcode;
12330 if (inst.operands[0].isreg
12331 && !inst.operands[0].preind
12332 && inst.operands[0].reg == REG_PC)
12333 set_pred_insn_type_last ();
12335 opcode = inst.instruction;
12336 if (unified_syntax)
12338 if (!inst.operands[1].isreg)
12340 if (opcode <= 0xffff)
12341 inst.instruction = THUMB_OP32 (opcode);
12342 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12345 if (inst.operands[1].isreg
12346 && !inst.operands[1].writeback
12347 && !inst.operands[1].shifted && !inst.operands[1].postind
12348 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12349 && opcode <= 0xffff
12350 && inst.size_req != 4)
12352 /* Insn may have a 16-bit form. */
12353 Rn = inst.operands[1].reg;
12354 if (inst.operands[1].immisreg)
12356 inst.instruction = THUMB_OP16 (opcode);
12358 if (Rn <= 7 && inst.operands[1].imm <= 7)
12360 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12361 reject_bad_reg (inst.operands[1].imm);
12363 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12364 && opcode != T_MNEM_ldrsb)
12365 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12366 || (Rn == REG_SP && opcode == T_MNEM_str))
12373 if (inst.relocs[0].pc_rel)
12374 opcode = T_MNEM_ldr_pc2;
12376 opcode = T_MNEM_ldr_pc;
12380 if (opcode == T_MNEM_ldr)
12381 opcode = T_MNEM_ldr_sp;
12383 opcode = T_MNEM_str_sp;
12385 inst.instruction = inst.operands[0].reg << 8;
12389 inst.instruction = inst.operands[0].reg;
12390 inst.instruction |= inst.operands[1].reg << 3;
12392 inst.instruction |= THUMB_OP16 (opcode);
12393 if (inst.size_req == 2)
12394 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12396 inst.relax = opcode;
12400 /* Definitely a 32-bit variant. */
12402 /* Warning for Erratum 752419. */
12403 if (opcode == T_MNEM_ldr
12404 && inst.operands[0].reg == REG_SP
12405 && inst.operands[1].writeback == 1
12406 && !inst.operands[1].immisreg)
12408 if (no_cpu_selected ()
12409 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
12410 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12411 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
12412 as_warn (_("This instruction may be unpredictable "
12413 "if executed on M-profile cores "
12414 "with interrupts enabled."));
12417 /* Do some validations regarding addressing modes. */
12418 if (inst.operands[1].immisreg)
12419 reject_bad_reg (inst.operands[1].imm);
12421 constraint (inst.operands[1].writeback == 1
12422 && inst.operands[0].reg == inst.operands[1].reg,
12425 inst.instruction = THUMB_OP32 (opcode);
12426 inst.instruction |= inst.operands[0].reg << 12;
12427 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
12428 check_ldr_r15_aligned ();
12432 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12434 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12436 /* Only [Rn,Rm] is acceptable. */
12437 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12438 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12439 || inst.operands[1].postind || inst.operands[1].shifted
12440 || inst.operands[1].negative,
12441 _("Thumb does not support this addressing mode"));
12442 inst.instruction = THUMB_OP16 (inst.instruction);
12446 inst.instruction = THUMB_OP16 (inst.instruction);
12447 if (!inst.operands[1].isreg)
12448 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12451 constraint (!inst.operands[1].preind
12452 || inst.operands[1].shifted
12453 || inst.operands[1].writeback,
12454 _("Thumb does not support this addressing mode"));
12455 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12457 constraint (inst.instruction & 0x0600,
12458 _("byte or halfword not valid for base register"));
12459 constraint (inst.operands[1].reg == REG_PC
12460 && !(inst.instruction & THUMB_LOAD_BIT),
12461 _("r15 based store not allowed"));
12462 constraint (inst.operands[1].immisreg,
12463 _("invalid base register for register offset"));
12465 if (inst.operands[1].reg == REG_PC)
12466 inst.instruction = T_OPCODE_LDR_PC;
12467 else if (inst.instruction & THUMB_LOAD_BIT)
12468 inst.instruction = T_OPCODE_LDR_SP;
12470 inst.instruction = T_OPCODE_STR_SP;
12472 inst.instruction |= inst.operands[0].reg << 8;
12473 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12477 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12478 if (!inst.operands[1].immisreg)
12480 /* Immediate offset. */
12481 inst.instruction |= inst.operands[0].reg;
12482 inst.instruction |= inst.operands[1].reg << 3;
12483 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12487 /* Register offset. */
12488 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12489 constraint (inst.operands[1].negative,
12490 _("Thumb does not support this addressing mode"));
12493 switch (inst.instruction)
12495 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12496 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12497 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12498 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12499 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12500 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12501 case 0x5600 /* ldrsb */:
12502 case 0x5e00 /* ldrsh */: break;
12506 inst.instruction |= inst.operands[0].reg;
12507 inst.instruction |= inst.operands[1].reg << 3;
12508 inst.instruction |= inst.operands[1].imm << 6;
12514 if (!inst.operands[1].present)
12516 inst.operands[1].reg = inst.operands[0].reg + 1;
12517 constraint (inst.operands[0].reg == REG_LR,
12518 _("r14 not allowed here"));
12519 constraint (inst.operands[0].reg == REG_R12,
12520 _("r12 not allowed here"));
12523 if (inst.operands[2].writeback
12524 && (inst.operands[0].reg == inst.operands[2].reg
12525 || inst.operands[1].reg == inst.operands[2].reg))
12526 as_warn (_("base register written back, and overlaps "
12527 "one of transfer registers"));
12529 inst.instruction |= inst.operands[0].reg << 12;
12530 inst.instruction |= inst.operands[1].reg << 8;
12531 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
12537 inst.instruction |= inst.operands[0].reg << 12;
12538 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12544 unsigned Rd, Rn, Rm, Ra;
12546 Rd = inst.operands[0].reg;
12547 Rn = inst.operands[1].reg;
12548 Rm = inst.operands[2].reg;
12549 Ra = inst.operands[3].reg;
12551 reject_bad_reg (Rd);
12552 reject_bad_reg (Rn);
12553 reject_bad_reg (Rm);
12554 reject_bad_reg (Ra);
12556 inst.instruction |= Rd << 8;
12557 inst.instruction |= Rn << 16;
12558 inst.instruction |= Rm;
12559 inst.instruction |= Ra << 12;
12565 unsigned RdLo, RdHi, Rn, Rm;
12567 RdLo = inst.operands[0].reg;
12568 RdHi = inst.operands[1].reg;
12569 Rn = inst.operands[2].reg;
12570 Rm = inst.operands[3].reg;
12572 reject_bad_reg (RdLo);
12573 reject_bad_reg (RdHi);
12574 reject_bad_reg (Rn);
12575 reject_bad_reg (Rm);
12577 inst.instruction |= RdLo << 12;
12578 inst.instruction |= RdHi << 8;
12579 inst.instruction |= Rn << 16;
12580 inst.instruction |= Rm;
12584 do_t_mov_cmp (void)
12588 Rn = inst.operands[0].reg;
12589 Rm = inst.operands[1].reg;
12592 set_pred_insn_type_last ();
12594 if (unified_syntax)
12596 int r0off = (inst.instruction == T_MNEM_mov
12597 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12598 unsigned long opcode;
12599 bfd_boolean narrow;
12600 bfd_boolean low_regs;
12602 low_regs = (Rn <= 7 && Rm <= 7);
12603 opcode = inst.instruction;
12604 if (in_pred_block ())
12605 narrow = opcode != T_MNEM_movs;
12607 narrow = opcode != T_MNEM_movs || low_regs;
12608 if (inst.size_req == 4
12609 || inst.operands[1].shifted)
12612 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12613 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12614 && !inst.operands[1].shifted
12618 inst.instruction = T2_SUBS_PC_LR;
12622 if (opcode == T_MNEM_cmp)
12624 constraint (Rn == REG_PC, BAD_PC);
12627 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12629 warn_deprecated_sp (Rm);
12630 /* R15 was documented as a valid choice for Rm in ARMv6,
12631 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12632 tools reject R15, so we do too. */
12633 constraint (Rm == REG_PC, BAD_PC);
12636 reject_bad_reg (Rm);
12638 else if (opcode == T_MNEM_mov
12639 || opcode == T_MNEM_movs)
12641 if (inst.operands[1].isreg)
12643 if (opcode == T_MNEM_movs)
12645 reject_bad_reg (Rn);
12646 reject_bad_reg (Rm);
12650 /* This is mov.n. */
12651 if ((Rn == REG_SP || Rn == REG_PC)
12652 && (Rm == REG_SP || Rm == REG_PC))
12654 as_tsktsk (_("Use of r%u as a source register is "
12655 "deprecated when r%u is the destination "
12656 "register."), Rm, Rn);
12661 /* This is mov.w. */
12662 constraint (Rn == REG_PC, BAD_PC);
12663 constraint (Rm == REG_PC, BAD_PC);
12664 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12665 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12669 reject_bad_reg (Rn);
12672 if (!inst.operands[1].isreg)
12674 /* Immediate operand. */
12675 if (!in_pred_block () && opcode == T_MNEM_mov)
12677 if (low_regs && narrow)
12679 inst.instruction = THUMB_OP16 (opcode);
12680 inst.instruction |= Rn << 8;
12681 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12682 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12684 if (inst.size_req == 2)
12685 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12687 inst.relax = opcode;
12692 constraint ((inst.relocs[0].type
12693 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12694 && (inst.relocs[0].type
12695 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
12696 THUMB1_RELOC_ONLY);
12698 inst.instruction = THUMB_OP32 (inst.instruction);
12699 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12700 inst.instruction |= Rn << r0off;
12701 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12704 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12705 && (inst.instruction == T_MNEM_mov
12706 || inst.instruction == T_MNEM_movs))
12708 /* Register shifts are encoded as separate shift instructions. */
12709 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12711 if (in_pred_block ())
12716 if (inst.size_req == 4)
12719 if (!low_regs || inst.operands[1].imm > 7)
12725 switch (inst.operands[1].shift_kind)
12728 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12731 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12734 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12737 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12743 inst.instruction = opcode;
12746 inst.instruction |= Rn;
12747 inst.instruction |= inst.operands[1].imm << 3;
12752 inst.instruction |= CONDS_BIT;
12754 inst.instruction |= Rn << 8;
12755 inst.instruction |= Rm << 16;
12756 inst.instruction |= inst.operands[1].imm;
12761 /* Some mov with immediate shift have narrow variants.
12762 Register shifts are handled above. */
12763 if (low_regs && inst.operands[1].shifted
12764 && (inst.instruction == T_MNEM_mov
12765 || inst.instruction == T_MNEM_movs))
12767 if (in_pred_block ())
12768 narrow = (inst.instruction == T_MNEM_mov);
12770 narrow = (inst.instruction == T_MNEM_movs);
12775 switch (inst.operands[1].shift_kind)
12777 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12778 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12779 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12780 default: narrow = FALSE; break;
12786 inst.instruction |= Rn;
12787 inst.instruction |= Rm << 3;
12788 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
12792 inst.instruction = THUMB_OP32 (inst.instruction);
12793 inst.instruction |= Rn << r0off;
12794 encode_thumb32_shifted_operand (1);
12798 switch (inst.instruction)
12801 /* In v4t or v5t a move of two lowregs produces unpredictable
12802 results. Don't allow this. */
12805 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
12806 "MOV Rd, Rs with two low registers is not "
12807 "permitted on this architecture");
12808 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
12812 inst.instruction = T_OPCODE_MOV_HR;
12813 inst.instruction |= (Rn & 0x8) << 4;
12814 inst.instruction |= (Rn & 0x7);
12815 inst.instruction |= Rm << 3;
12819 /* We know we have low registers at this point.
12820 Generate LSLS Rd, Rs, #0. */
12821 inst.instruction = T_OPCODE_LSL_I;
12822 inst.instruction |= Rn;
12823 inst.instruction |= Rm << 3;
12829 inst.instruction = T_OPCODE_CMP_LR;
12830 inst.instruction |= Rn;
12831 inst.instruction |= Rm << 3;
12835 inst.instruction = T_OPCODE_CMP_HR;
12836 inst.instruction |= (Rn & 0x8) << 4;
12837 inst.instruction |= (Rn & 0x7);
12838 inst.instruction |= Rm << 3;
12845 inst.instruction = THUMB_OP16 (inst.instruction);
12847 /* PR 10443: Do not silently ignore shifted operands. */
12848 constraint (inst.operands[1].shifted,
12849 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12851 if (inst.operands[1].isreg)
12853 if (Rn < 8 && Rm < 8)
12855 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12856 since a MOV instruction produces unpredictable results. */
12857 if (inst.instruction == T_OPCODE_MOV_I8)
12858 inst.instruction = T_OPCODE_ADD_I3;
12860 inst.instruction = T_OPCODE_CMP_LR;
12862 inst.instruction |= Rn;
12863 inst.instruction |= Rm << 3;
12867 if (inst.instruction == T_OPCODE_MOV_I8)
12868 inst.instruction = T_OPCODE_MOV_HR;
12870 inst.instruction = T_OPCODE_CMP_HR;
12876 constraint (Rn > 7,
12877 _("only lo regs allowed with immediate"));
12878 inst.instruction |= Rn << 8;
12879 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12890 top = (inst.instruction & 0x00800000) != 0;
12891 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
12893 constraint (top, _(":lower16: not allowed in this instruction"));
12894 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
12896 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
12898 constraint (!top, _(":upper16: not allowed in this instruction"));
12899 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
12902 Rd = inst.operands[0].reg;
12903 reject_bad_reg (Rd);
12905 inst.instruction |= Rd << 8;
12906 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
12908 imm = inst.relocs[0].exp.X_add_number;
12909 inst.instruction |= (imm & 0xf000) << 4;
12910 inst.instruction |= (imm & 0x0800) << 15;
12911 inst.instruction |= (imm & 0x0700) << 4;
12912 inst.instruction |= (imm & 0x00ff);
12917 do_t_mvn_tst (void)
12921 Rn = inst.operands[0].reg;
12922 Rm = inst.operands[1].reg;
12924 if (inst.instruction == T_MNEM_cmp
12925 || inst.instruction == T_MNEM_cmn)
12926 constraint (Rn == REG_PC, BAD_PC);
12928 reject_bad_reg (Rn);
12929 reject_bad_reg (Rm);
12931 if (unified_syntax)
12933 int r0off = (inst.instruction == T_MNEM_mvn
12934 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12935 bfd_boolean narrow;
12937 if (inst.size_req == 4
12938 || inst.instruction > 0xffff
12939 || inst.operands[1].shifted
12940 || Rn > 7 || Rm > 7)
12942 else if (inst.instruction == T_MNEM_cmn
12943 || inst.instruction == T_MNEM_tst)
12945 else if (THUMB_SETS_FLAGS (inst.instruction))
12946 narrow = !in_pred_block ();
12948 narrow = in_pred_block ();
12950 if (!inst.operands[1].isreg)
12952 /* For an immediate, we always generate a 32-bit opcode;
12953 section relaxation will shrink it later if possible. */
12954 if (inst.instruction < 0xffff)
12955 inst.instruction = THUMB_OP32 (inst.instruction);
12956 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12957 inst.instruction |= Rn << r0off;
12958 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12962 /* See if we can do this with a 16-bit instruction. */
12965 inst.instruction = THUMB_OP16 (inst.instruction);
12966 inst.instruction |= Rn;
12967 inst.instruction |= Rm << 3;
12971 constraint (inst.operands[1].shifted
12972 && inst.operands[1].immisreg,
12973 _("shift must be constant"));
12974 if (inst.instruction < 0xffff)
12975 inst.instruction = THUMB_OP32 (inst.instruction);
12976 inst.instruction |= Rn << r0off;
12977 encode_thumb32_shifted_operand (1);
12983 constraint (inst.instruction > 0xffff
12984 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12985 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12986 _("unshifted register required"));
12987 constraint (Rn > 7 || Rm > 7,
12990 inst.instruction = THUMB_OP16 (inst.instruction);
12991 inst.instruction |= Rn;
12992 inst.instruction |= Rm << 3;
13001 if (do_vfp_nsyn_mrs () == SUCCESS)
13004 Rd = inst.operands[0].reg;
13005 reject_bad_reg (Rd);
13006 inst.instruction |= Rd << 8;
13008 if (inst.operands[1].isreg)
13010 unsigned br = inst.operands[1].reg;
13011 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13012 as_bad (_("bad register for mrs"));
13014 inst.instruction |= br & (0xf << 16);
13015 inst.instruction |= (br & 0x300) >> 4;
13016 inst.instruction |= (br & SPSR_BIT) >> 2;
13020 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13022 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13024 /* PR gas/12698: The constraint is only applied for m_profile.
13025 If the user has specified -march=all, we want to ignore it as
13026 we are building for any CPU type, including non-m variants. */
13027 bfd_boolean m_profile =
13028 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13029 constraint ((flags != 0) && m_profile, _("selected processor does "
13030 "not support requested special purpose register"));
13033 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13035 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13036 _("'APSR', 'CPSR' or 'SPSR' expected"));
13038 inst.instruction |= (flags & SPSR_BIT) >> 2;
13039 inst.instruction |= inst.operands[1].imm & 0xff;
13040 inst.instruction |= 0xf0000;
13050 if (do_vfp_nsyn_msr () == SUCCESS)
13053 constraint (!inst.operands[1].isreg,
13054 _("Thumb encoding does not support an immediate here"));
13056 if (inst.operands[0].isreg)
13057 flags = (int)(inst.operands[0].reg);
13059 flags = inst.operands[0].imm;
13061 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13063 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13065 /* PR gas/12698: The constraint is only applied for m_profile.
13066 If the user has specified -march=all, we want to ignore it as
13067 we are building for any CPU type, including non-m variants. */
13068 bfd_boolean m_profile =
13069 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13070 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13071 && (bits & ~(PSR_s | PSR_f)) != 0)
13072 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13073 && bits != PSR_f)) && m_profile,
13074 _("selected processor does not support requested special "
13075 "purpose register"));
13078 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13079 "requested special purpose register"));
13081 Rn = inst.operands[1].reg;
13082 reject_bad_reg (Rn);
13084 inst.instruction |= (flags & SPSR_BIT) >> 2;
13085 inst.instruction |= (flags & 0xf0000) >> 8;
13086 inst.instruction |= (flags & 0x300) >> 4;
13087 inst.instruction |= (flags & 0xff);
13088 inst.instruction |= Rn << 16;
13094 bfd_boolean narrow;
13095 unsigned Rd, Rn, Rm;
13097 if (!inst.operands[2].present)
13098 inst.operands[2].reg = inst.operands[0].reg;
13100 Rd = inst.operands[0].reg;
13101 Rn = inst.operands[1].reg;
13102 Rm = inst.operands[2].reg;
13104 if (unified_syntax)
13106 if (inst.size_req == 4
13112 else if (inst.instruction == T_MNEM_muls)
13113 narrow = !in_pred_block ();
13115 narrow = in_pred_block ();
13119 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13120 constraint (Rn > 7 || Rm > 7,
13127 /* 16-bit MULS/Conditional MUL. */
13128 inst.instruction = THUMB_OP16 (inst.instruction);
13129 inst.instruction |= Rd;
13132 inst.instruction |= Rm << 3;
13134 inst.instruction |= Rn << 3;
13136 constraint (1, _("dest must overlap one source register"));
13140 constraint (inst.instruction != T_MNEM_mul,
13141 _("Thumb-2 MUL must not set flags"));
13143 inst.instruction = THUMB_OP32 (inst.instruction);
13144 inst.instruction |= Rd << 8;
13145 inst.instruction |= Rn << 16;
13146 inst.instruction |= Rm << 0;
13148 reject_bad_reg (Rd);
13149 reject_bad_reg (Rn);
13150 reject_bad_reg (Rm);
13157 unsigned RdLo, RdHi, Rn, Rm;
13159 RdLo = inst.operands[0].reg;
13160 RdHi = inst.operands[1].reg;
13161 Rn = inst.operands[2].reg;
13162 Rm = inst.operands[3].reg;
13164 reject_bad_reg (RdLo);
13165 reject_bad_reg (RdHi);
13166 reject_bad_reg (Rn);
13167 reject_bad_reg (Rm);
13169 inst.instruction |= RdLo << 12;
13170 inst.instruction |= RdHi << 8;
13171 inst.instruction |= Rn << 16;
13172 inst.instruction |= Rm;
13175 as_tsktsk (_("rdhi and rdlo must be different"));
13181 set_pred_insn_type (NEUTRAL_IT_INSN);
13183 if (unified_syntax)
13185 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13187 inst.instruction = THUMB_OP32 (inst.instruction);
13188 inst.instruction |= inst.operands[0].imm;
13192 /* PR9722: Check for Thumb2 availability before
13193 generating a thumb2 nop instruction. */
13194 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
13196 inst.instruction = THUMB_OP16 (inst.instruction);
13197 inst.instruction |= inst.operands[0].imm << 4;
13200 inst.instruction = 0x46c0;
13205 constraint (inst.operands[0].present,
13206 _("Thumb does not support NOP with hints"));
13207 inst.instruction = 0x46c0;
13214 if (unified_syntax)
13216 bfd_boolean narrow;
13218 if (THUMB_SETS_FLAGS (inst.instruction))
13219 narrow = !in_pred_block ();
13221 narrow = in_pred_block ();
13222 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13224 if (inst.size_req == 4)
13229 inst.instruction = THUMB_OP32 (inst.instruction);
13230 inst.instruction |= inst.operands[0].reg << 8;
13231 inst.instruction |= inst.operands[1].reg << 16;
13235 inst.instruction = THUMB_OP16 (inst.instruction);
13236 inst.instruction |= inst.operands[0].reg;
13237 inst.instruction |= inst.operands[1].reg << 3;
13242 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13244 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13246 inst.instruction = THUMB_OP16 (inst.instruction);
13247 inst.instruction |= inst.operands[0].reg;
13248 inst.instruction |= inst.operands[1].reg << 3;
13257 Rd = inst.operands[0].reg;
13258 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13260 reject_bad_reg (Rd);
13261 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13262 reject_bad_reg (Rn);
13264 inst.instruction |= Rd << 8;
13265 inst.instruction |= Rn << 16;
13267 if (!inst.operands[2].isreg)
13269 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13270 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13276 Rm = inst.operands[2].reg;
13277 reject_bad_reg (Rm);
13279 constraint (inst.operands[2].shifted
13280 && inst.operands[2].immisreg,
13281 _("shift must be constant"));
13282 encode_thumb32_shifted_operand (2);
13289 unsigned Rd, Rn, Rm;
13291 Rd = inst.operands[0].reg;
13292 Rn = inst.operands[1].reg;
13293 Rm = inst.operands[2].reg;
13295 reject_bad_reg (Rd);
13296 reject_bad_reg (Rn);
13297 reject_bad_reg (Rm);
13299 inst.instruction |= Rd << 8;
13300 inst.instruction |= Rn << 16;
13301 inst.instruction |= Rm;
13302 if (inst.operands[3].present)
13304 unsigned int val = inst.relocs[0].exp.X_add_number;
13305 constraint (inst.relocs[0].exp.X_op != O_constant,
13306 _("expression too complex"));
13307 inst.instruction |= (val & 0x1c) << 10;
13308 inst.instruction |= (val & 0x03) << 6;
13315 if (!inst.operands[3].present)
13319 inst.instruction &= ~0x00000020;
13321 /* PR 10168. Swap the Rm and Rn registers. */
13322 Rtmp = inst.operands[1].reg;
13323 inst.operands[1].reg = inst.operands[2].reg;
13324 inst.operands[2].reg = Rtmp;
13332 if (inst.operands[0].immisreg)
13333 reject_bad_reg (inst.operands[0].imm);
13335 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13339 do_t_push_pop (void)
13343 constraint (inst.operands[0].writeback,
13344 _("push/pop do not support {reglist}^"));
13345 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13346 _("expression too complex"));
13348 mask = inst.operands[0].imm;
13349 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13350 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13351 else if (inst.size_req != 4
13352 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13353 ? REG_LR : REG_PC)))
13355 inst.instruction = THUMB_OP16 (inst.instruction);
13356 inst.instruction |= THUMB_PP_PC_LR;
13357 inst.instruction |= mask & 0xff;
13359 else if (unified_syntax)
13361 inst.instruction = THUMB_OP32 (inst.instruction);
13362 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13366 inst.error = _("invalid register list to push/pop instruction");
13374 if (unified_syntax)
13375 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
13378 inst.error = _("invalid register list to push/pop instruction");
13384 do_t_vscclrm (void)
13386 if (inst.operands[0].issingle)
13388 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13389 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13390 inst.instruction |= inst.operands[0].imm;
13394 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13395 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13396 inst.instruction |= 1 << 8;
13397 inst.instruction |= inst.operands[0].imm << 1;
13406 Rd = inst.operands[0].reg;
13407 Rm = inst.operands[1].reg;
13409 reject_bad_reg (Rd);
13410 reject_bad_reg (Rm);
13412 inst.instruction |= Rd << 8;
13413 inst.instruction |= Rm << 16;
13414 inst.instruction |= Rm;
13422 Rd = inst.operands[0].reg;
13423 Rm = inst.operands[1].reg;
13425 reject_bad_reg (Rd);
13426 reject_bad_reg (Rm);
13428 if (Rd <= 7 && Rm <= 7
13429 && inst.size_req != 4)
13431 inst.instruction = THUMB_OP16 (inst.instruction);
13432 inst.instruction |= Rd;
13433 inst.instruction |= Rm << 3;
13435 else if (unified_syntax)
13437 inst.instruction = THUMB_OP32 (inst.instruction);
13438 inst.instruction |= Rd << 8;
13439 inst.instruction |= Rm << 16;
13440 inst.instruction |= Rm;
13443 inst.error = BAD_HIREG;
13451 Rd = inst.operands[0].reg;
13452 Rm = inst.operands[1].reg;
13454 reject_bad_reg (Rd);
13455 reject_bad_reg (Rm);
13457 inst.instruction |= Rd << 8;
13458 inst.instruction |= Rm;
13466 Rd = inst.operands[0].reg;
13467 Rs = (inst.operands[1].present
13468 ? inst.operands[1].reg /* Rd, Rs, foo */
13469 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13471 reject_bad_reg (Rd);
13472 reject_bad_reg (Rs);
13473 if (inst.operands[2].isreg)
13474 reject_bad_reg (inst.operands[2].reg);
13476 inst.instruction |= Rd << 8;
13477 inst.instruction |= Rs << 16;
13478 if (!inst.operands[2].isreg)
13480 bfd_boolean narrow;
13482 if ((inst.instruction & 0x00100000) != 0)
13483 narrow = !in_pred_block ();
13485 narrow = in_pred_block ();
13487 if (Rd > 7 || Rs > 7)
13490 if (inst.size_req == 4 || !unified_syntax)
13493 if (inst.relocs[0].exp.X_op != O_constant
13494 || inst.relocs[0].exp.X_add_number != 0)
13497 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13498 relaxation, but it doesn't seem worth the hassle. */
13501 inst.relocs[0].type = BFD_RELOC_UNUSED;
13502 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13503 inst.instruction |= Rs << 3;
13504 inst.instruction |= Rd;
13508 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13509 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13513 encode_thumb32_shifted_operand (2);
13519 if (warn_on_deprecated
13520 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13521 as_tsktsk (_("setend use is deprecated for ARMv8"));
13523 set_pred_insn_type (OUTSIDE_PRED_INSN);
13524 if (inst.operands[0].imm)
13525 inst.instruction |= 0x8;
13531 if (!inst.operands[1].present)
13532 inst.operands[1].reg = inst.operands[0].reg;
13534 if (unified_syntax)
13536 bfd_boolean narrow;
13539 switch (inst.instruction)
13542 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13544 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13546 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13548 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13552 if (THUMB_SETS_FLAGS (inst.instruction))
13553 narrow = !in_pred_block ();
13555 narrow = in_pred_block ();
13556 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13558 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13560 if (inst.operands[2].isreg
13561 && (inst.operands[1].reg != inst.operands[0].reg
13562 || inst.operands[2].reg > 7))
13564 if (inst.size_req == 4)
13567 reject_bad_reg (inst.operands[0].reg);
13568 reject_bad_reg (inst.operands[1].reg);
13572 if (inst.operands[2].isreg)
13574 reject_bad_reg (inst.operands[2].reg);
13575 inst.instruction = THUMB_OP32 (inst.instruction);
13576 inst.instruction |= inst.operands[0].reg << 8;
13577 inst.instruction |= inst.operands[1].reg << 16;
13578 inst.instruction |= inst.operands[2].reg;
13580 /* PR 12854: Error on extraneous shifts. */
13581 constraint (inst.operands[2].shifted,
13582 _("extraneous shift as part of operand to shift insn"));
13586 inst.operands[1].shifted = 1;
13587 inst.operands[1].shift_kind = shift_kind;
13588 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13589 ? T_MNEM_movs : T_MNEM_mov);
13590 inst.instruction |= inst.operands[0].reg << 8;
13591 encode_thumb32_shifted_operand (1);
13592 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13593 inst.relocs[0].type = BFD_RELOC_UNUSED;
13598 if (inst.operands[2].isreg)
13600 switch (shift_kind)
13602 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13603 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13604 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13605 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13609 inst.instruction |= inst.operands[0].reg;
13610 inst.instruction |= inst.operands[2].reg << 3;
13612 /* PR 12854: Error on extraneous shifts. */
13613 constraint (inst.operands[2].shifted,
13614 _("extraneous shift as part of operand to shift insn"));
13618 switch (shift_kind)
13620 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13621 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13622 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13625 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13626 inst.instruction |= inst.operands[0].reg;
13627 inst.instruction |= inst.operands[1].reg << 3;
13633 constraint (inst.operands[0].reg > 7
13634 || inst.operands[1].reg > 7, BAD_HIREG);
13635 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13637 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13639 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13640 constraint (inst.operands[0].reg != inst.operands[1].reg,
13641 _("source1 and dest must be same register"));
13643 switch (inst.instruction)
13645 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13646 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13647 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13648 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13652 inst.instruction |= inst.operands[0].reg;
13653 inst.instruction |= inst.operands[2].reg << 3;
13655 /* PR 12854: Error on extraneous shifts. */
13656 constraint (inst.operands[2].shifted,
13657 _("extraneous shift as part of operand to shift insn"));
13661 switch (inst.instruction)
13663 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13664 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13665 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13666 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13669 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13670 inst.instruction |= inst.operands[0].reg;
13671 inst.instruction |= inst.operands[1].reg << 3;
13679 unsigned Rd, Rn, Rm;
13681 Rd = inst.operands[0].reg;
13682 Rn = inst.operands[1].reg;
13683 Rm = inst.operands[2].reg;
13685 reject_bad_reg (Rd);
13686 reject_bad_reg (Rn);
13687 reject_bad_reg (Rm);
13689 inst.instruction |= Rd << 8;
13690 inst.instruction |= Rn << 16;
13691 inst.instruction |= Rm;
13697 unsigned Rd, Rn, Rm;
13699 Rd = inst.operands[0].reg;
13700 Rm = inst.operands[1].reg;
13701 Rn = inst.operands[2].reg;
13703 reject_bad_reg (Rd);
13704 reject_bad_reg (Rn);
13705 reject_bad_reg (Rm);
13707 inst.instruction |= Rd << 8;
13708 inst.instruction |= Rn << 16;
13709 inst.instruction |= Rm;
13715 unsigned int value = inst.relocs[0].exp.X_add_number;
13716 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13717 _("SMC is not permitted on this architecture"));
13718 constraint (inst.relocs[0].exp.X_op != O_constant,
13719 _("expression too complex"));
13720 inst.relocs[0].type = BFD_RELOC_UNUSED;
13721 inst.instruction |= (value & 0xf000) >> 12;
13722 inst.instruction |= (value & 0x0ff0);
13723 inst.instruction |= (value & 0x000f) << 16;
13724 /* PR gas/15623: SMC instructions must be last in an IT block. */
13725 set_pred_insn_type_last ();
13731 unsigned int value = inst.relocs[0].exp.X_add_number;
13733 inst.relocs[0].type = BFD_RELOC_UNUSED;
13734 inst.instruction |= (value & 0x0fff);
13735 inst.instruction |= (value & 0xf000) << 4;
13739 do_t_ssat_usat (int bias)
13743 Rd = inst.operands[0].reg;
13744 Rn = inst.operands[2].reg;
13746 reject_bad_reg (Rd);
13747 reject_bad_reg (Rn);
13749 inst.instruction |= Rd << 8;
13750 inst.instruction |= inst.operands[1].imm - bias;
13751 inst.instruction |= Rn << 16;
13753 if (inst.operands[3].present)
13755 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
13757 inst.relocs[0].type = BFD_RELOC_UNUSED;
13759 constraint (inst.relocs[0].exp.X_op != O_constant,
13760 _("expression too complex"));
13762 if (shift_amount != 0)
13764 constraint (shift_amount > 31,
13765 _("shift expression is too large"));
13767 if (inst.operands[3].shift_kind == SHIFT_ASR)
13768 inst.instruction |= 0x00200000; /* sh bit. */
13770 inst.instruction |= (shift_amount & 0x1c) << 10;
13771 inst.instruction |= (shift_amount & 0x03) << 6;
13779 do_t_ssat_usat (1);
13787 Rd = inst.operands[0].reg;
13788 Rn = inst.operands[2].reg;
13790 reject_bad_reg (Rd);
13791 reject_bad_reg (Rn);
13793 inst.instruction |= Rd << 8;
13794 inst.instruction |= inst.operands[1].imm - 1;
13795 inst.instruction |= Rn << 16;
13801 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
13802 || inst.operands[2].postind || inst.operands[2].writeback
13803 || inst.operands[2].immisreg || inst.operands[2].shifted
13804 || inst.operands[2].negative,
13807 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
13809 inst.instruction |= inst.operands[0].reg << 8;
13810 inst.instruction |= inst.operands[1].reg << 12;
13811 inst.instruction |= inst.operands[2].reg << 16;
13812 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
13818 if (!inst.operands[2].present)
13819 inst.operands[2].reg = inst.operands[1].reg + 1;
13821 constraint (inst.operands[0].reg == inst.operands[1].reg
13822 || inst.operands[0].reg == inst.operands[2].reg
13823 || inst.operands[0].reg == inst.operands[3].reg,
13826 inst.instruction |= inst.operands[0].reg;
13827 inst.instruction |= inst.operands[1].reg << 12;
13828 inst.instruction |= inst.operands[2].reg << 8;
13829 inst.instruction |= inst.operands[3].reg << 16;
13835 unsigned Rd, Rn, Rm;
13837 Rd = inst.operands[0].reg;
13838 Rn = inst.operands[1].reg;
13839 Rm = inst.operands[2].reg;
13841 reject_bad_reg (Rd);
13842 reject_bad_reg (Rn);
13843 reject_bad_reg (Rm);
13845 inst.instruction |= Rd << 8;
13846 inst.instruction |= Rn << 16;
13847 inst.instruction |= Rm;
13848 inst.instruction |= inst.operands[3].imm << 4;
13856 Rd = inst.operands[0].reg;
13857 Rm = inst.operands[1].reg;
13859 reject_bad_reg (Rd);
13860 reject_bad_reg (Rm);
13862 if (inst.instruction <= 0xffff
13863 && inst.size_req != 4
13864 && Rd <= 7 && Rm <= 7
13865 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13867 inst.instruction = THUMB_OP16 (inst.instruction);
13868 inst.instruction |= Rd;
13869 inst.instruction |= Rm << 3;
13871 else if (unified_syntax)
13873 if (inst.instruction <= 0xffff)
13874 inst.instruction = THUMB_OP32 (inst.instruction);
13875 inst.instruction |= Rd << 8;
13876 inst.instruction |= Rm;
13877 inst.instruction |= inst.operands[2].imm << 4;
13881 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13882 _("Thumb encoding does not support rotation"));
13883 constraint (1, BAD_HIREG);
13890 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
13899 half = (inst.instruction & 0x10) != 0;
13900 set_pred_insn_type_last ();
13901 constraint (inst.operands[0].immisreg,
13902 _("instruction requires register index"));
13904 Rn = inst.operands[0].reg;
13905 Rm = inst.operands[0].imm;
13907 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13908 constraint (Rn == REG_SP, BAD_SP);
13909 reject_bad_reg (Rm);
13911 constraint (!half && inst.operands[0].shifted,
13912 _("instruction does not allow shifted index"));
13913 inst.instruction |= (Rn << 16) | Rm;
13919 if (!inst.operands[0].present)
13920 inst.operands[0].imm = 0;
13922 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13924 constraint (inst.size_req == 2,
13925 _("immediate value out of range"));
13926 inst.instruction = THUMB_OP32 (inst.instruction);
13927 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13928 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13932 inst.instruction = THUMB_OP16 (inst.instruction);
13933 inst.instruction |= inst.operands[0].imm;
13936 set_pred_insn_type (NEUTRAL_IT_INSN);
13943 do_t_ssat_usat (0);
13951 Rd = inst.operands[0].reg;
13952 Rn = inst.operands[2].reg;
13954 reject_bad_reg (Rd);
13955 reject_bad_reg (Rn);
13957 inst.instruction |= Rd << 8;
13958 inst.instruction |= inst.operands[1].imm;
13959 inst.instruction |= Rn << 16;
13962 /* Checking the range of the branch offset (VAL) with NBITS bits
13963 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13965 v8_1_branch_value_check (int val, int nbits, int is_signed)
13967 gas_assert (nbits > 0 && nbits <= 32);
13970 int cmp = (1 << (nbits - 1));
13971 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
13976 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
13982 /* For branches in Armv8.1-M Mainline. */
13984 do_t_branch_future (void)
13986 unsigned long insn = inst.instruction;
13988 inst.instruction = THUMB_OP32 (inst.instruction);
13989 if (inst.operands[0].hasreloc == 0)
13991 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
13992 as_bad (BAD_BRANCH_OFF);
13994 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
13998 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
13999 inst.relocs[0].pc_rel = 1;
14005 if (inst.operands[1].hasreloc == 0)
14007 int val = inst.operands[1].imm;
14008 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14009 as_bad (BAD_BRANCH_OFF);
14011 int immA = (val & 0x0001f000) >> 12;
14012 int immB = (val & 0x00000ffc) >> 2;
14013 int immC = (val & 0x00000002) >> 1;
14014 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14018 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14019 inst.relocs[1].pc_rel = 1;
14024 if (inst.operands[1].hasreloc == 0)
14026 int val = inst.operands[1].imm;
14027 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14028 as_bad (BAD_BRANCH_OFF);
14030 int immA = (val & 0x0007f000) >> 12;
14031 int immB = (val & 0x00000ffc) >> 2;
14032 int immC = (val & 0x00000002) >> 1;
14033 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14037 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14038 inst.relocs[1].pc_rel = 1;
14042 case T_MNEM_bfcsel:
14044 if (inst.operands[1].hasreloc == 0)
14046 int val = inst.operands[1].imm;
14047 int immA = (val & 0x00001000) >> 12;
14048 int immB = (val & 0x00000ffc) >> 2;
14049 int immC = (val & 0x00000002) >> 1;
14050 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14054 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14055 inst.relocs[1].pc_rel = 1;
14059 if (inst.operands[2].hasreloc == 0)
14061 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14062 int val2 = inst.operands[2].imm;
14063 int val0 = inst.operands[0].imm & 0x1f;
14064 int diff = val2 - val0;
14066 inst.instruction |= 1 << 17; /* T bit. */
14067 else if (diff != 2)
14068 as_bad (_("out of range label-relative fixup value"));
14072 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14073 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14074 inst.relocs[2].pc_rel = 1;
14078 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14079 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14084 inst.instruction |= inst.operands[1].reg << 16;
14091 /* Helper function for do_t_loloop to handle relocations. */
14093 v8_1_loop_reloc (int is_le)
14095 if (inst.relocs[0].exp.X_op == O_constant)
14097 int value = inst.relocs[0].exp.X_add_number;
14098 value = (is_le) ? -value : value;
14100 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14101 as_bad (BAD_BRANCH_OFF);
14105 immh = (value & 0x00000ffc) >> 2;
14106 imml = (value & 0x00000002) >> 1;
14108 inst.instruction |= (imml << 11) | (immh << 1);
14112 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14113 inst.relocs[0].pc_rel = 1;
14117 /* To handle the Scalar Low Overhead Loop instructions
14118 in Armv8.1-M Mainline. */
14122 unsigned long insn = inst.instruction;
14124 set_pred_insn_type (OUTSIDE_PRED_INSN);
14125 inst.instruction = THUMB_OP32 (inst.instruction);
14131 if (!inst.operands[0].present)
14132 inst.instruction |= 1 << 21;
14134 v8_1_loop_reloc (TRUE);
14138 v8_1_loop_reloc (FALSE);
14139 /* Fall through. */
14141 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
14142 inst.instruction |= (inst.operands[1].reg << 16);
14149 /* MVE instruction encoder helpers. */
14150 #define M_MNEM_vabav 0xee800f01
14151 #define M_MNEM_vmladav 0xeef00e00
14152 #define M_MNEM_vmladava 0xeef00e20
14153 #define M_MNEM_vmladavx 0xeef01e00
14154 #define M_MNEM_vmladavax 0xeef01e20
14155 #define M_MNEM_vmlsdav 0xeef00e01
14156 #define M_MNEM_vmlsdava 0xeef00e21
14157 #define M_MNEM_vmlsdavx 0xeef01e01
14158 #define M_MNEM_vmlsdavax 0xeef01e21
14159 #define M_MNEM_vmullt 0xee011e00
14160 #define M_MNEM_vmullb 0xee010e00
14161 #define M_MNEM_vst20 0xfc801e00
14162 #define M_MNEM_vst21 0xfc801e20
14163 #define M_MNEM_vst40 0xfc801e01
14164 #define M_MNEM_vst41 0xfc801e21
14165 #define M_MNEM_vst42 0xfc801e41
14166 #define M_MNEM_vst43 0xfc801e61
14167 #define M_MNEM_vld20 0xfc901e00
14168 #define M_MNEM_vld21 0xfc901e20
14169 #define M_MNEM_vld40 0xfc901e01
14170 #define M_MNEM_vld41 0xfc901e21
14171 #define M_MNEM_vld42 0xfc901e41
14172 #define M_MNEM_vld43 0xfc901e61
14173 #define M_MNEM_vstrb 0xec000e00
14174 #define M_MNEM_vstrh 0xec000e10
14175 #define M_MNEM_vstrw 0xec000e40
14176 #define M_MNEM_vstrd 0xec000e50
14177 #define M_MNEM_vldrb 0xec100e00
14178 #define M_MNEM_vldrh 0xec100e10
14179 #define M_MNEM_vldrw 0xec100e40
14180 #define M_MNEM_vldrd 0xec100e50
14181 #define M_MNEM_vmovlt 0xeea01f40
14182 #define M_MNEM_vmovlb 0xeea00f40
14183 #define M_MNEM_vmovnt 0xfe311e81
14184 #define M_MNEM_vmovnb 0xfe310e81
14185 #define M_MNEM_vadc 0xee300f00
14186 #define M_MNEM_vadci 0xee301f00
14187 #define M_MNEM_vbrsr 0xfe011e60
14188 #define M_MNEM_vaddlv 0xee890f00
14189 #define M_MNEM_vaddlva 0xee890f20
14190 #define M_MNEM_vaddv 0xeef10f00
14191 #define M_MNEM_vaddva 0xeef10f20
14192 #define M_MNEM_vddup 0xee011f6e
14193 #define M_MNEM_vdwdup 0xee011f60
14194 #define M_MNEM_vidup 0xee010f6e
14195 #define M_MNEM_viwdup 0xee010f60
14196 #define M_MNEM_vmaxv 0xeee20f00
14197 #define M_MNEM_vmaxav 0xeee00f00
14198 #define M_MNEM_vminv 0xeee20f80
14199 #define M_MNEM_vminav 0xeee00f80
14200 #define M_MNEM_vmlaldav 0xee800e00
14201 #define M_MNEM_vmlaldava 0xee800e20
14202 #define M_MNEM_vmlaldavx 0xee801e00
14203 #define M_MNEM_vmlaldavax 0xee801e20
14204 #define M_MNEM_vmlsldav 0xee800e01
14205 #define M_MNEM_vmlsldava 0xee800e21
14206 #define M_MNEM_vmlsldavx 0xee801e01
14207 #define M_MNEM_vmlsldavax 0xee801e21
14208 #define M_MNEM_vrmlaldavhx 0xee801f00
14209 #define M_MNEM_vrmlaldavhax 0xee801f20
14210 #define M_MNEM_vrmlsldavh 0xfe800e01
14211 #define M_MNEM_vrmlsldavha 0xfe800e21
14212 #define M_MNEM_vrmlsldavhx 0xfe801e01
14213 #define M_MNEM_vrmlsldavhax 0xfe801e21
14214 #define M_MNEM_vqmovnt 0xee331e01
14215 #define M_MNEM_vqmovnb 0xee330e01
14216 #define M_MNEM_vqmovunt 0xee311e81
14217 #define M_MNEM_vqmovunb 0xee310e81
14218 #define M_MNEM_vshrnt 0xee801fc1
14219 #define M_MNEM_vshrnb 0xee800fc1
14220 #define M_MNEM_vrshrnt 0xfe801fc1
14221 #define M_MNEM_vqshrnt 0xee801f40
14222 #define M_MNEM_vqshrnb 0xee800f40
14223 #define M_MNEM_vqshrunt 0xee801fc0
14224 #define M_MNEM_vqshrunb 0xee800fc0
14225 #define M_MNEM_vrshrnb 0xfe800fc1
14226 #define M_MNEM_vqrshrnt 0xee801f41
14227 #define M_MNEM_vqrshrnb 0xee800f41
14228 #define M_MNEM_vqrshrunt 0xfe801fc0
14229 #define M_MNEM_vqrshrunb 0xfe800fc0
14231 /* Neon instruction encoder helpers. */
14233 /* Encodings for the different types for various Neon opcodes. */
14235 /* An "invalid" code for the following tables. */
14238 struct neon_tab_entry
14241 unsigned float_or_poly;
14242 unsigned scalar_or_imm;
14245 /* Map overloaded Neon opcodes to their respective encodings. */
14246 #define NEON_ENC_TAB \
14247 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14248 X(vabdl, 0x0800700, N_INV, N_INV), \
14249 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14250 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14251 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14252 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14253 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14254 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14255 X(vaddl, 0x0800000, N_INV, N_INV), \
14256 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14257 X(vsubl, 0x0800200, N_INV, N_INV), \
14258 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14259 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14260 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14261 /* Register variants of the following two instructions are encoded as
14262 vcge / vcgt with the operands reversed. */ \
14263 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14264 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14265 X(vfma, N_INV, 0x0000c10, N_INV), \
14266 X(vfms, N_INV, 0x0200c10, N_INV), \
14267 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14268 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14269 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14270 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14271 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14272 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14273 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14274 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14275 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14276 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14277 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14278 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14279 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14280 X(vshl, 0x0000400, N_INV, 0x0800510), \
14281 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14282 X(vand, 0x0000110, N_INV, 0x0800030), \
14283 X(vbic, 0x0100110, N_INV, 0x0800030), \
14284 X(veor, 0x1000110, N_INV, N_INV), \
14285 X(vorn, 0x0300110, N_INV, 0x0800010), \
14286 X(vorr, 0x0200110, N_INV, 0x0800010), \
14287 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14288 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14289 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14290 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14291 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14292 X(vst1, 0x0000000, 0x0800000, N_INV), \
14293 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14294 X(vst2, 0x0000100, 0x0800100, N_INV), \
14295 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14296 X(vst3, 0x0000200, 0x0800200, N_INV), \
14297 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14298 X(vst4, 0x0000300, 0x0800300, N_INV), \
14299 X(vmovn, 0x1b20200, N_INV, N_INV), \
14300 X(vtrn, 0x1b20080, N_INV, N_INV), \
14301 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14302 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14303 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14304 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14305 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14306 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14307 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14308 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14309 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14310 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14311 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14312 X(vseleq, 0xe000a00, N_INV, N_INV), \
14313 X(vselvs, 0xe100a00, N_INV, N_INV), \
14314 X(vselge, 0xe200a00, N_INV, N_INV), \
14315 X(vselgt, 0xe300a00, N_INV, N_INV), \
14316 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14317 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14318 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14319 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14320 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14321 X(aes, 0x3b00300, N_INV, N_INV), \
14322 X(sha3op, 0x2000c00, N_INV, N_INV), \
14323 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14324 X(sha2op, 0x3ba0380, N_INV, N_INV)
14328 #define X(OPC,I,F,S) N_MNEM_##OPC
14333 static const struct neon_tab_entry neon_enc_tab[] =
14335 #define X(OPC,I,F,S) { (I), (F), (S) }
14340 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14341 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14342 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14343 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14344 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14345 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14346 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14347 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14348 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14349 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14350 #define NEON_ENC_SINGLE_(X) \
14351 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14352 #define NEON_ENC_DOUBLE_(X) \
14353 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14354 #define NEON_ENC_FPV8_(X) \
14355 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14357 #define NEON_ENCODE(type, inst) \
14360 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14361 inst.is_neon = 1; \
14365 #define check_neon_suffixes \
14368 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14370 as_bad (_("invalid neon suffix for non neon instruction")); \
14376 /* Define shapes for instruction operands. The following mnemonic characters
14377 are used in this table:
14379 F - VFP S<n> register
14380 D - Neon D<n> register
14381 Q - Neon Q<n> register
14385 L - D<n> register list
14387 This table is used to generate various data:
14388 - enumerations of the form NS_DDR to be used as arguments to
14390 - a table classifying shapes into single, double, quad, mixed.
14391 - a table used to drive neon_select_shape. */
14393 #define NEON_SHAPE_DEF \
14394 X(4, (R, R, Q, Q), QUAD), \
14395 X(4, (Q, R, R, I), QUAD), \
14396 X(4, (R, R, S, S), QUAD), \
14397 X(4, (S, S, R, R), QUAD), \
14398 X(3, (Q, R, I), QUAD), \
14399 X(3, (I, Q, Q), QUAD), \
14400 X(3, (I, Q, R), QUAD), \
14401 X(3, (R, Q, Q), QUAD), \
14402 X(3, (D, D, D), DOUBLE), \
14403 X(3, (Q, Q, Q), QUAD), \
14404 X(3, (D, D, I), DOUBLE), \
14405 X(3, (Q, Q, I), QUAD), \
14406 X(3, (D, D, S), DOUBLE), \
14407 X(3, (Q, Q, S), QUAD), \
14408 X(3, (Q, Q, R), QUAD), \
14409 X(3, (R, R, Q), QUAD), \
14410 X(2, (R, Q), QUAD), \
14411 X(2, (D, D), DOUBLE), \
14412 X(2, (Q, Q), QUAD), \
14413 X(2, (D, S), DOUBLE), \
14414 X(2, (Q, S), QUAD), \
14415 X(2, (D, R), DOUBLE), \
14416 X(2, (Q, R), QUAD), \
14417 X(2, (D, I), DOUBLE), \
14418 X(2, (Q, I), QUAD), \
14419 X(3, (D, L, D), DOUBLE), \
14420 X(2, (D, Q), MIXED), \
14421 X(2, (Q, D), MIXED), \
14422 X(3, (D, Q, I), MIXED), \
14423 X(3, (Q, D, I), MIXED), \
14424 X(3, (Q, D, D), MIXED), \
14425 X(3, (D, Q, Q), MIXED), \
14426 X(3, (Q, Q, D), MIXED), \
14427 X(3, (Q, D, S), MIXED), \
14428 X(3, (D, Q, S), MIXED), \
14429 X(4, (D, D, D, I), DOUBLE), \
14430 X(4, (Q, Q, Q, I), QUAD), \
14431 X(4, (D, D, S, I), DOUBLE), \
14432 X(4, (Q, Q, S, I), QUAD), \
14433 X(2, (F, F), SINGLE), \
14434 X(3, (F, F, F), SINGLE), \
14435 X(2, (F, I), SINGLE), \
14436 X(2, (F, D), MIXED), \
14437 X(2, (D, F), MIXED), \
14438 X(3, (F, F, I), MIXED), \
14439 X(4, (R, R, F, F), SINGLE), \
14440 X(4, (F, F, R, R), SINGLE), \
14441 X(3, (D, R, R), DOUBLE), \
14442 X(3, (R, R, D), DOUBLE), \
14443 X(2, (S, R), SINGLE), \
14444 X(2, (R, S), SINGLE), \
14445 X(2, (F, R), SINGLE), \
14446 X(2, (R, F), SINGLE), \
14447 /* Half float shape supported so far. */\
14448 X (2, (H, D), MIXED), \
14449 X (2, (D, H), MIXED), \
14450 X (2, (H, F), MIXED), \
14451 X (2, (F, H), MIXED), \
14452 X (2, (H, H), HALF), \
14453 X (2, (H, R), HALF), \
14454 X (2, (R, H), HALF), \
14455 X (2, (H, I), HALF), \
14456 X (3, (H, H, H), HALF), \
14457 X (3, (H, F, I), MIXED), \
14458 X (3, (F, H, I), MIXED), \
14459 X (3, (D, H, H), MIXED), \
14460 X (3, (D, H, S), MIXED)
14462 #define S2(A,B) NS_##A##B
14463 #define S3(A,B,C) NS_##A##B##C
14464 #define S4(A,B,C,D) NS_##A##B##C##D
14466 #define X(N, L, C) S##N L
14479 enum neon_shape_class
14488 #define X(N, L, C) SC_##C
14490 static enum neon_shape_class neon_shape_class[] =
14509 /* Register widths of above. */
14510 static unsigned neon_shape_el_size[] =
14522 struct neon_shape_info
14525 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14528 #define S2(A,B) { SE_##A, SE_##B }
14529 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14530 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14532 #define X(N, L, C) { N, S##N L }
14534 static struct neon_shape_info neon_shape_tab[] =
14544 /* Bit masks used in type checking given instructions.
14545 'N_EQK' means the type must be the same as (or based on in some way) the key
14546 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14547 set, various other bits can be set as well in order to modify the meaning of
14548 the type constraint. */
14550 enum neon_type_mask
14574 N_KEY = 0x1000000, /* Key element (main type specifier). */
14575 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
14576 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
14577 N_UNT = 0x8000000, /* Must be explicitly untyped. */
14578 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14579 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14580 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14581 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14582 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14583 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14584 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14586 N_MAX_NONSPECIAL = N_P64
14589 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14591 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14592 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14593 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14594 #define N_S_32 (N_S8 | N_S16 | N_S32)
14595 #define N_F_16_32 (N_F16 | N_F32)
14596 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14597 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14598 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14599 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14600 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14601 #define N_F_MVE (N_F16 | N_F32)
14602 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14604 /* Pass this as the first type argument to neon_check_type to ignore types
14606 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14608 /* Select a "shape" for the current instruction (describing register types or
14609 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14610 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14611 function of operand parsing, so this function doesn't need to be called.
14612 Shapes should be listed in order of decreasing length. */
14614 static enum neon_shape
14615 neon_select_shape (enum neon_shape shape, ...)
14618 enum neon_shape first_shape = shape;
14620 /* Fix missing optional operands. FIXME: we don't know at this point how
14621 many arguments we should have, so this makes the assumption that we have
14622 > 1. This is true of all current Neon opcodes, I think, but may not be
14623 true in the future. */
14624 if (!inst.operands[1].present)
14625 inst.operands[1] = inst.operands[0];
14627 va_start (ap, shape);
14629 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
14634 for (j = 0; j < neon_shape_tab[shape].els; j++)
14636 if (!inst.operands[j].present)
14642 switch (neon_shape_tab[shape].el[j])
14644 /* If a .f16, .16, .u16, .s16 type specifier is given over
14645 a VFP single precision register operand, it's essentially
14646 means only half of the register is used.
14648 If the type specifier is given after the mnemonics, the
14649 information is stored in inst.vectype. If the type specifier
14650 is given after register operand, the information is stored
14651 in inst.operands[].vectype.
14653 When there is only one type specifier, and all the register
14654 operands are the same type of hardware register, the type
14655 specifier applies to all register operands.
14657 If no type specifier is given, the shape is inferred from
14658 operand information.
14661 vadd.f16 s0, s1, s2: NS_HHH
14662 vabs.f16 s0, s1: NS_HH
14663 vmov.f16 s0, r1: NS_HR
14664 vmov.f16 r0, s1: NS_RH
14665 vcvt.f16 r0, s1: NS_RH
14666 vcvt.f16.s32 s2, s2, #29: NS_HFI
14667 vcvt.f16.s32 s2, s2: NS_HF
14670 if (!(inst.operands[j].isreg
14671 && inst.operands[j].isvec
14672 && inst.operands[j].issingle
14673 && !inst.operands[j].isquad
14674 && ((inst.vectype.elems == 1
14675 && inst.vectype.el[0].size == 16)
14676 || (inst.vectype.elems > 1
14677 && inst.vectype.el[j].size == 16)
14678 || (inst.vectype.elems == 0
14679 && inst.operands[j].vectype.type != NT_invtype
14680 && inst.operands[j].vectype.size == 16))))
14685 if (!(inst.operands[j].isreg
14686 && inst.operands[j].isvec
14687 && inst.operands[j].issingle
14688 && !inst.operands[j].isquad
14689 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14690 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14691 || (inst.vectype.elems == 0
14692 && (inst.operands[j].vectype.size == 32
14693 || inst.operands[j].vectype.type == NT_invtype)))))
14698 if (!(inst.operands[j].isreg
14699 && inst.operands[j].isvec
14700 && !inst.operands[j].isquad
14701 && !inst.operands[j].issingle))
14706 if (!(inst.operands[j].isreg
14707 && !inst.operands[j].isvec))
14712 if (!(inst.operands[j].isreg
14713 && inst.operands[j].isvec
14714 && inst.operands[j].isquad
14715 && !inst.operands[j].issingle))
14720 if (!(!inst.operands[j].isreg
14721 && !inst.operands[j].isscalar))
14726 if (!(!inst.operands[j].isreg
14727 && inst.operands[j].isscalar))
14737 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
14738 /* We've matched all the entries in the shape table, and we don't
14739 have any left over operands which have not been matched. */
14745 if (shape == NS_NULL && first_shape != NS_NULL)
14746 first_error (_("invalid instruction shape"));
14751 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14752 means the Q bit should be set). */
14755 neon_quad (enum neon_shape shape)
14757 return neon_shape_class[shape] == SC_QUAD;
14761 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
14764 /* Allow modification to be made to types which are constrained to be
14765 based on the key element, based on bits set alongside N_EQK. */
14766 if ((typebits & N_EQK) != 0)
14768 if ((typebits & N_HLF) != 0)
14770 else if ((typebits & N_DBL) != 0)
14772 if ((typebits & N_SGN) != 0)
14773 *g_type = NT_signed;
14774 else if ((typebits & N_UNS) != 0)
14775 *g_type = NT_unsigned;
14776 else if ((typebits & N_INT) != 0)
14777 *g_type = NT_integer;
14778 else if ((typebits & N_FLT) != 0)
14779 *g_type = NT_float;
14780 else if ((typebits & N_SIZ) != 0)
14781 *g_type = NT_untyped;
14785 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14786 operand type, i.e. the single type specified in a Neon instruction when it
14787 is the only one given. */
14789 static struct neon_type_el
14790 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
14792 struct neon_type_el dest = *key;
14794 gas_assert ((thisarg & N_EQK) != 0);
14796 neon_modify_type_size (thisarg, &dest.type, &dest.size);
14801 /* Convert Neon type and size into compact bitmask representation. */
14803 static enum neon_type_mask
14804 type_chk_of_el_type (enum neon_el_type type, unsigned size)
14811 case 8: return N_8;
14812 case 16: return N_16;
14813 case 32: return N_32;
14814 case 64: return N_64;
14822 case 8: return N_I8;
14823 case 16: return N_I16;
14824 case 32: return N_I32;
14825 case 64: return N_I64;
14833 case 16: return N_F16;
14834 case 32: return N_F32;
14835 case 64: return N_F64;
14843 case 8: return N_P8;
14844 case 16: return N_P16;
14845 case 64: return N_P64;
14853 case 8: return N_S8;
14854 case 16: return N_S16;
14855 case 32: return N_S32;
14856 case 64: return N_S64;
14864 case 8: return N_U8;
14865 case 16: return N_U16;
14866 case 32: return N_U32;
14867 case 64: return N_U64;
14878 /* Convert compact Neon bitmask type representation to a type and size. Only
14879 handles the case where a single bit is set in the mask. */
14882 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
14883 enum neon_type_mask mask)
14885 if ((mask & N_EQK) != 0)
14888 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
14890 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
14892 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
14894 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
14899 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
14901 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
14902 *type = NT_unsigned;
14903 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
14904 *type = NT_integer;
14905 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
14906 *type = NT_untyped;
14907 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
14909 else if ((mask & (N_F_ALL)) != 0)
14917 /* Modify a bitmask of allowed types. This is only needed for type
14921 modify_types_allowed (unsigned allowed, unsigned mods)
14924 enum neon_el_type type;
14930 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
14932 if (el_type_of_type_chk (&type, &size,
14933 (enum neon_type_mask) (allowed & i)) == SUCCESS)
14935 neon_modify_type_size (mods, &type, &size);
14936 destmask |= type_chk_of_el_type (type, size);
14943 /* Check type and return type classification.
14944 The manual states (paraphrase): If one datatype is given, it indicates the
14946 - the second operand, if there is one
14947 - the operand, if there is no second operand
14948 - the result, if there are no operands.
14949 This isn't quite good enough though, so we use a concept of a "key" datatype
14950 which is set on a per-instruction basis, which is the one which matters when
14951 only one data type is written.
14952 Note: this function has side-effects (e.g. filling in missing operands). All
14953 Neon instructions should call it before performing bit encoding. */
14955 static struct neon_type_el
14956 neon_check_type (unsigned els, enum neon_shape ns, ...)
14959 unsigned i, pass, key_el = 0;
14960 unsigned types[NEON_MAX_TYPE_ELS];
14961 enum neon_el_type k_type = NT_invtype;
14962 unsigned k_size = -1u;
14963 struct neon_type_el badtype = {NT_invtype, -1};
14964 unsigned key_allowed = 0;
14966 /* Optional registers in Neon instructions are always (not) in operand 1.
14967 Fill in the missing operand here, if it was omitted. */
14968 if (els > 1 && !inst.operands[1].present)
14969 inst.operands[1] = inst.operands[0];
14971 /* Suck up all the varargs. */
14973 for (i = 0; i < els; i++)
14975 unsigned thisarg = va_arg (ap, unsigned);
14976 if (thisarg == N_IGNORE_TYPE)
14981 types[i] = thisarg;
14982 if ((thisarg & N_KEY) != 0)
14987 if (inst.vectype.elems > 0)
14988 for (i = 0; i < els; i++)
14989 if (inst.operands[i].vectype.type != NT_invtype)
14991 first_error (_("types specified in both the mnemonic and operands"));
14995 /* Duplicate inst.vectype elements here as necessary.
14996 FIXME: No idea if this is exactly the same as the ARM assembler,
14997 particularly when an insn takes one register and one non-register
14999 if (inst.vectype.elems == 1 && els > 1)
15002 inst.vectype.elems = els;
15003 inst.vectype.el[key_el] = inst.vectype.el[0];
15004 for (j = 0; j < els; j++)
15006 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15009 else if (inst.vectype.elems == 0 && els > 0)
15012 /* No types were given after the mnemonic, so look for types specified
15013 after each operand. We allow some flexibility here; as long as the
15014 "key" operand has a type, we can infer the others. */
15015 for (j = 0; j < els; j++)
15016 if (inst.operands[j].vectype.type != NT_invtype)
15017 inst.vectype.el[j] = inst.operands[j].vectype;
15019 if (inst.operands[key_el].vectype.type != NT_invtype)
15021 for (j = 0; j < els; j++)
15022 if (inst.operands[j].vectype.type == NT_invtype)
15023 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15028 first_error (_("operand types can't be inferred"));
15032 else if (inst.vectype.elems != els)
15034 first_error (_("type specifier has the wrong number of parts"));
15038 for (pass = 0; pass < 2; pass++)
15040 for (i = 0; i < els; i++)
15042 unsigned thisarg = types[i];
15043 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15044 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15045 enum neon_el_type g_type = inst.vectype.el[i].type;
15046 unsigned g_size = inst.vectype.el[i].size;
15048 /* Decay more-specific signed & unsigned types to sign-insensitive
15049 integer types if sign-specific variants are unavailable. */
15050 if ((g_type == NT_signed || g_type == NT_unsigned)
15051 && (types_allowed & N_SU_ALL) == 0)
15052 g_type = NT_integer;
15054 /* If only untyped args are allowed, decay any more specific types to
15055 them. Some instructions only care about signs for some element
15056 sizes, so handle that properly. */
15057 if (((types_allowed & N_UNT) == 0)
15058 && ((g_size == 8 && (types_allowed & N_8) != 0)
15059 || (g_size == 16 && (types_allowed & N_16) != 0)
15060 || (g_size == 32 && (types_allowed & N_32) != 0)
15061 || (g_size == 64 && (types_allowed & N_64) != 0)))
15062 g_type = NT_untyped;
15066 if ((thisarg & N_KEY) != 0)
15070 key_allowed = thisarg & ~N_KEY;
15072 /* Check architecture constraint on FP16 extension. */
15074 && k_type == NT_float
15075 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15077 inst.error = _(BAD_FP16);
15084 if ((thisarg & N_VFP) != 0)
15086 enum neon_shape_el regshape;
15087 unsigned regwidth, match;
15089 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15092 first_error (_("invalid instruction shape"));
15095 regshape = neon_shape_tab[ns].el[i];
15096 regwidth = neon_shape_el_size[regshape];
15098 /* In VFP mode, operands must match register widths. If we
15099 have a key operand, use its width, else use the width of
15100 the current operand. */
15106 /* FP16 will use a single precision register. */
15107 if (regwidth == 32 && match == 16)
15109 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15113 inst.error = _(BAD_FP16);
15118 if (regwidth != match)
15120 first_error (_("operand size must match register width"));
15125 if ((thisarg & N_EQK) == 0)
15127 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15129 if ((given_type & types_allowed) == 0)
15131 first_error (BAD_SIMD_TYPE);
15137 enum neon_el_type mod_k_type = k_type;
15138 unsigned mod_k_size = k_size;
15139 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15140 if (g_type != mod_k_type || g_size != mod_k_size)
15142 first_error (_("inconsistent types in Neon instruction"));
15150 return inst.vectype.el[key_el];
15153 /* Neon-style VFP instruction forwarding. */
15155 /* Thumb VFP instructions have 0xE in the condition field. */
15158 do_vfp_cond_or_thumb (void)
15163 inst.instruction |= 0xe0000000;
15165 inst.instruction |= inst.cond << 28;
15168 /* Look up and encode a simple mnemonic, for use as a helper function for the
15169 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15170 etc. It is assumed that operand parsing has already been done, and that the
15171 operands are in the form expected by the given opcode (this isn't necessarily
15172 the same as the form in which they were parsed, hence some massaging must
15173 take place before this function is called).
15174 Checks current arch version against that in the looked-up opcode. */
15177 do_vfp_nsyn_opcode (const char *opname)
15179 const struct asm_opcode *opcode;
15181 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
15186 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
15187 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15194 inst.instruction = opcode->tvalue;
15195 opcode->tencode ();
15199 inst.instruction = (inst.cond << 28) | opcode->avalue;
15200 opcode->aencode ();
15205 do_vfp_nsyn_add_sub (enum neon_shape rs)
15207 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15209 if (rs == NS_FFF || rs == NS_HHH)
15212 do_vfp_nsyn_opcode ("fadds");
15214 do_vfp_nsyn_opcode ("fsubs");
15216 /* ARMv8.2 fp16 instruction. */
15218 do_scalar_fp16_v82_encode ();
15223 do_vfp_nsyn_opcode ("faddd");
15225 do_vfp_nsyn_opcode ("fsubd");
15229 /* Check operand types to see if this is a VFP instruction, and if so call
15233 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15235 enum neon_shape rs;
15236 struct neon_type_el et;
15241 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15242 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15246 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15247 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15248 N_F_ALL | N_KEY | N_VFP);
15255 if (et.type != NT_invtype)
15266 do_vfp_nsyn_mla_mls (enum neon_shape rs)
15268 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15270 if (rs == NS_FFF || rs == NS_HHH)
15273 do_vfp_nsyn_opcode ("fmacs");
15275 do_vfp_nsyn_opcode ("fnmacs");
15277 /* ARMv8.2 fp16 instruction. */
15279 do_scalar_fp16_v82_encode ();
15284 do_vfp_nsyn_opcode ("fmacd");
15286 do_vfp_nsyn_opcode ("fnmacd");
15291 do_vfp_nsyn_fma_fms (enum neon_shape rs)
15293 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15295 if (rs == NS_FFF || rs == NS_HHH)
15298 do_vfp_nsyn_opcode ("ffmas");
15300 do_vfp_nsyn_opcode ("ffnmas");
15302 /* ARMv8.2 fp16 instruction. */
15304 do_scalar_fp16_v82_encode ();
15309 do_vfp_nsyn_opcode ("ffmad");
15311 do_vfp_nsyn_opcode ("ffnmad");
15316 do_vfp_nsyn_mul (enum neon_shape rs)
15318 if (rs == NS_FFF || rs == NS_HHH)
15320 do_vfp_nsyn_opcode ("fmuls");
15322 /* ARMv8.2 fp16 instruction. */
15324 do_scalar_fp16_v82_encode ();
15327 do_vfp_nsyn_opcode ("fmuld");
15331 do_vfp_nsyn_abs_neg (enum neon_shape rs)
15333 int is_neg = (inst.instruction & 0x80) != 0;
15334 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
15336 if (rs == NS_FF || rs == NS_HH)
15339 do_vfp_nsyn_opcode ("fnegs");
15341 do_vfp_nsyn_opcode ("fabss");
15343 /* ARMv8.2 fp16 instruction. */
15345 do_scalar_fp16_v82_encode ();
15350 do_vfp_nsyn_opcode ("fnegd");
15352 do_vfp_nsyn_opcode ("fabsd");
15356 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15357 insns belong to Neon, and are handled elsewhere. */
15360 do_vfp_nsyn_ldm_stm (int is_dbmode)
15362 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15366 do_vfp_nsyn_opcode ("fldmdbs");
15368 do_vfp_nsyn_opcode ("fldmias");
15373 do_vfp_nsyn_opcode ("fstmdbs");
15375 do_vfp_nsyn_opcode ("fstmias");
15380 do_vfp_nsyn_sqrt (void)
15382 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15383 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15385 if (rs == NS_FF || rs == NS_HH)
15387 do_vfp_nsyn_opcode ("fsqrts");
15389 /* ARMv8.2 fp16 instruction. */
15391 do_scalar_fp16_v82_encode ();
15394 do_vfp_nsyn_opcode ("fsqrtd");
15398 do_vfp_nsyn_div (void)
15400 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15401 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15402 N_F_ALL | N_KEY | N_VFP);
15404 if (rs == NS_FFF || rs == NS_HHH)
15406 do_vfp_nsyn_opcode ("fdivs");
15408 /* ARMv8.2 fp16 instruction. */
15410 do_scalar_fp16_v82_encode ();
15413 do_vfp_nsyn_opcode ("fdivd");
15417 do_vfp_nsyn_nmul (void)
15419 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15420 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15421 N_F_ALL | N_KEY | N_VFP);
15423 if (rs == NS_FFF || rs == NS_HHH)
15425 NEON_ENCODE (SINGLE, inst);
15426 do_vfp_sp_dyadic ();
15428 /* ARMv8.2 fp16 instruction. */
15430 do_scalar_fp16_v82_encode ();
15434 NEON_ENCODE (DOUBLE, inst);
15435 do_vfp_dp_rd_rn_rm ();
15437 do_vfp_cond_or_thumb ();
15441 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15445 neon_logbits (unsigned x)
15447 return ffs (x) - 4;
15450 #define LOW4(R) ((R) & 0xf)
15451 #define HI1(R) (((R) >> 4) & 1)
15454 mve_get_vcmp_vpt_cond (struct neon_type_el et)
15459 first_error (BAD_EL_TYPE);
15462 switch (inst.operands[0].imm)
15465 first_error (_("invalid condition"));
15487 /* only accept eq and ne. */
15488 if (inst.operands[0].imm > 1)
15490 first_error (_("invalid condition"));
15493 return inst.operands[0].imm;
15495 if (inst.operands[0].imm == 0x2)
15497 else if (inst.operands[0].imm == 0x8)
15501 first_error (_("invalid condition"));
15505 switch (inst.operands[0].imm)
15508 first_error (_("invalid condition"));
15524 /* Should be unreachable. */
15531 /* We are dealing with a vector predicated block. */
15532 if (inst.operands[0].present)
15534 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15535 struct neon_type_el et
15536 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15539 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15541 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15543 if (et.type == NT_invtype)
15546 if (et.type == NT_float)
15548 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15550 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15551 inst.instruction |= (et.size == 16) << 28;
15552 inst.instruction |= 0x3 << 20;
15556 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15558 inst.instruction |= 1 << 28;
15559 inst.instruction |= neon_logbits (et.size) << 20;
15562 if (inst.operands[2].isquad)
15564 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15565 inst.instruction |= LOW4 (inst.operands[2].reg);
15566 inst.instruction |= (fcond & 0x2) >> 1;
15570 if (inst.operands[2].reg == REG_SP)
15571 as_tsktsk (MVE_BAD_SP);
15572 inst.instruction |= 1 << 6;
15573 inst.instruction |= (fcond & 0x2) << 4;
15574 inst.instruction |= inst.operands[2].reg;
15576 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15577 inst.instruction |= (fcond & 0x4) << 10;
15578 inst.instruction |= (fcond & 0x1) << 7;
15581 set_pred_insn_type (VPT_INSN);
15583 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15584 | ((inst.instruction & 0xe000) >> 13);
15585 now_pred.warn_deprecated = FALSE;
15586 now_pred.type = VECTOR_PRED;
15593 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15594 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15595 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15596 if (!inst.operands[2].present)
15597 first_error (_("MVE vector or ARM register expected"));
15598 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15600 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15601 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15602 && inst.operands[1].isquad)
15604 inst.instruction = N_MNEM_vcmp;
15608 if (inst.cond > COND_ALWAYS)
15609 inst.pred_insn_type = INSIDE_VPT_INSN;
15611 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15613 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15614 struct neon_type_el et
15615 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15618 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15619 && !inst.operands[2].iszr, BAD_PC);
15621 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15623 inst.instruction = 0xee010f00;
15624 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15625 inst.instruction |= (fcond & 0x4) << 10;
15626 inst.instruction |= (fcond & 0x1) << 7;
15627 if (et.type == NT_float)
15629 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15631 inst.instruction |= (et.size == 16) << 28;
15632 inst.instruction |= 0x3 << 20;
15636 inst.instruction |= 1 << 28;
15637 inst.instruction |= neon_logbits (et.size) << 20;
15639 if (inst.operands[2].isquad)
15641 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15642 inst.instruction |= (fcond & 0x2) >> 1;
15643 inst.instruction |= LOW4 (inst.operands[2].reg);
15647 if (inst.operands[2].reg == REG_SP)
15648 as_tsktsk (MVE_BAD_SP);
15649 inst.instruction |= 1 << 6;
15650 inst.instruction |= (fcond & 0x2) << 4;
15651 inst.instruction |= inst.operands[2].reg;
15659 do_mve_vmaxa_vmina (void)
15661 if (inst.cond > COND_ALWAYS)
15662 inst.pred_insn_type = INSIDE_VPT_INSN;
15664 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15666 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15667 struct neon_type_el et
15668 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15670 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15671 inst.instruction |= neon_logbits (et.size) << 18;
15672 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15673 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15674 inst.instruction |= LOW4 (inst.operands[1].reg);
15679 do_mve_vfmas (void)
15681 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15682 struct neon_type_el et
15683 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15685 if (inst.cond > COND_ALWAYS)
15686 inst.pred_insn_type = INSIDE_VPT_INSN;
15688 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15690 if (inst.operands[2].reg == REG_SP)
15691 as_tsktsk (MVE_BAD_SP);
15692 else if (inst.operands[2].reg == REG_PC)
15693 as_tsktsk (MVE_BAD_PC);
15695 inst.instruction |= (et.size == 16) << 28;
15696 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15697 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15698 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15699 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15700 inst.instruction |= inst.operands[2].reg;
15705 do_mve_viddup (void)
15707 if (inst.cond > COND_ALWAYS)
15708 inst.pred_insn_type = INSIDE_VPT_INSN;
15710 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15712 unsigned imm = inst.relocs[0].exp.X_add_number;
15713 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
15714 _("immediate must be either 1, 2, 4 or 8"));
15716 enum neon_shape rs;
15717 struct neon_type_el et;
15719 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
15721 rs = neon_select_shape (NS_QRI, NS_NULL);
15722 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
15727 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
15728 if (inst.operands[2].reg == REG_SP)
15729 as_tsktsk (MVE_BAD_SP);
15730 else if (inst.operands[2].reg == REG_PC)
15731 first_error (BAD_PC);
15733 rs = neon_select_shape (NS_QRRI, NS_NULL);
15734 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
15735 Rm = inst.operands[2].reg >> 1;
15737 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15738 inst.instruction |= neon_logbits (et.size) << 20;
15739 inst.instruction |= inst.operands[1].reg << 16;
15740 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15741 inst.instruction |= (imm > 2) << 7;
15742 inst.instruction |= Rm << 1;
15743 inst.instruction |= (imm == 2 || imm == 8);
15748 do_mve_vmlas (void)
15750 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15751 struct neon_type_el et
15752 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
15754 if (inst.operands[2].reg == REG_PC)
15755 as_tsktsk (MVE_BAD_PC);
15756 else if (inst.operands[2].reg == REG_SP)
15757 as_tsktsk (MVE_BAD_SP);
15759 if (inst.cond > COND_ALWAYS)
15760 inst.pred_insn_type = INSIDE_VPT_INSN;
15762 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15764 inst.instruction |= (et.type == NT_unsigned) << 28;
15765 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15766 inst.instruction |= neon_logbits (et.size) << 20;
15767 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15768 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15769 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15770 inst.instruction |= inst.operands[2].reg;
15775 do_mve_vshrn (void)
15778 switch (inst.instruction)
15780 case M_MNEM_vshrnt:
15781 case M_MNEM_vshrnb:
15782 case M_MNEM_vrshrnt:
15783 case M_MNEM_vrshrnb:
15784 types = N_I16 | N_I32;
15786 case M_MNEM_vqshrnt:
15787 case M_MNEM_vqshrnb:
15788 case M_MNEM_vqrshrnt:
15789 case M_MNEM_vqrshrnb:
15790 types = N_U16 | N_U32 | N_S16 | N_S32;
15792 case M_MNEM_vqshrunt:
15793 case M_MNEM_vqshrunb:
15794 case M_MNEM_vqrshrunt:
15795 case M_MNEM_vqrshrunb:
15796 types = N_S16 | N_S32;
15802 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
15804 if (inst.cond > COND_ALWAYS)
15805 inst.pred_insn_type = INSIDE_VPT_INSN;
15807 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15809 unsigned Qd = inst.operands[0].reg;
15810 unsigned Qm = inst.operands[1].reg;
15811 unsigned imm = inst.operands[2].imm;
15812 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
15814 ? _("immediate operand expected in the range [1,8]")
15815 : _("immediate operand expected in the range [1,16]"));
15817 inst.instruction |= (et.type == NT_unsigned) << 28;
15818 inst.instruction |= HI1 (Qd) << 22;
15819 inst.instruction |= (et.size - imm) << 16;
15820 inst.instruction |= LOW4 (Qd) << 12;
15821 inst.instruction |= HI1 (Qm) << 5;
15822 inst.instruction |= LOW4 (Qm);
15827 do_mve_vqmovn (void)
15829 struct neon_type_el et;
15830 if (inst.instruction == M_MNEM_vqmovnt
15831 || inst.instruction == M_MNEM_vqmovnb)
15832 et = neon_check_type (2, NS_QQ, N_EQK,
15833 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
15835 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
15837 if (inst.cond > COND_ALWAYS)
15838 inst.pred_insn_type = INSIDE_VPT_INSN;
15840 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15842 inst.instruction |= (et.type == NT_unsigned) << 28;
15843 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15844 inst.instruction |= (et.size == 32) << 18;
15845 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15846 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15847 inst.instruction |= LOW4 (inst.operands[1].reg);
15852 do_mve_vpsel (void)
15854 neon_select_shape (NS_QQQ, NS_NULL);
15856 if (inst.cond > COND_ALWAYS)
15857 inst.pred_insn_type = INSIDE_VPT_INSN;
15859 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15861 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15862 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15863 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15864 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15865 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15866 inst.instruction |= LOW4 (inst.operands[2].reg);
15871 do_mve_vpnot (void)
15873 if (inst.cond > COND_ALWAYS)
15874 inst.pred_insn_type = INSIDE_VPT_INSN;
15876 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15880 do_mve_vmaxnma_vminnma (void)
15882 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15883 struct neon_type_el et
15884 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
15886 if (inst.cond > COND_ALWAYS)
15887 inst.pred_insn_type = INSIDE_VPT_INSN;
15889 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15891 inst.instruction |= (et.size == 16) << 28;
15892 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15893 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15894 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15895 inst.instruction |= LOW4 (inst.operands[1].reg);
15900 do_mve_vcmul (void)
15902 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
15903 struct neon_type_el et
15904 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
15906 if (inst.cond > COND_ALWAYS)
15907 inst.pred_insn_type = INSIDE_VPT_INSN;
15909 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15911 unsigned rot = inst.relocs[0].exp.X_add_number;
15912 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
15913 _("immediate out of range"));
15915 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
15916 || inst.operands[0].reg == inst.operands[2].reg))
15917 as_tsktsk (BAD_MVE_SRCDEST);
15919 inst.instruction |= (et.size == 32) << 28;
15920 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15921 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15922 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15923 inst.instruction |= (rot > 90) << 12;
15924 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15925 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15926 inst.instruction |= LOW4 (inst.operands[2].reg);
15927 inst.instruction |= (rot == 90 || rot == 270);
15932 do_vfp_nsyn_cmp (void)
15934 enum neon_shape rs;
15935 if (!inst.operands[0].isreg)
15942 constraint (inst.operands[2].present, BAD_SYNTAX);
15943 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
15947 if (inst.operands[1].isreg)
15949 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15950 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15952 if (rs == NS_FF || rs == NS_HH)
15954 NEON_ENCODE (SINGLE, inst);
15955 do_vfp_sp_monadic ();
15959 NEON_ENCODE (DOUBLE, inst);
15960 do_vfp_dp_rd_rm ();
15965 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
15966 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
15968 switch (inst.instruction & 0x0fffffff)
15971 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
15974 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
15980 if (rs == NS_FI || rs == NS_HI)
15982 NEON_ENCODE (SINGLE, inst);
15983 do_vfp_sp_compare_z ();
15987 NEON_ENCODE (DOUBLE, inst);
15991 do_vfp_cond_or_thumb ();
15993 /* ARMv8.2 fp16 instruction. */
15994 if (rs == NS_HI || rs == NS_HH)
15995 do_scalar_fp16_v82_encode ();
15999 nsyn_insert_sp (void)
16001 inst.operands[1] = inst.operands[0];
16002 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
16003 inst.operands[0].reg = REG_SP;
16004 inst.operands[0].isreg = 1;
16005 inst.operands[0].writeback = 1;
16006 inst.operands[0].present = 1;
16010 do_vfp_nsyn_push (void)
16014 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16015 _("register list must contain at least 1 and at most 16 "
16018 if (inst.operands[1].issingle)
16019 do_vfp_nsyn_opcode ("fstmdbs");
16021 do_vfp_nsyn_opcode ("fstmdbd");
16025 do_vfp_nsyn_pop (void)
16029 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16030 _("register list must contain at least 1 and at most 16 "
16033 if (inst.operands[1].issingle)
16034 do_vfp_nsyn_opcode ("fldmias");
16036 do_vfp_nsyn_opcode ("fldmiad");
16039 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16040 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16043 neon_dp_fixup (struct arm_it* insn)
16045 unsigned int i = insn->instruction;
16050 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16061 insn->instruction = i;
16065 mve_encode_qqr (int size, int U, int fp)
16067 if (inst.operands[2].reg == REG_SP)
16068 as_tsktsk (MVE_BAD_SP);
16069 else if (inst.operands[2].reg == REG_PC)
16070 as_tsktsk (MVE_BAD_PC);
16075 if (((unsigned)inst.instruction) == 0xd00)
16076 inst.instruction = 0xee300f40;
16078 else if (((unsigned)inst.instruction) == 0x200d00)
16079 inst.instruction = 0xee301f40;
16081 else if (((unsigned)inst.instruction) == 0x1000d10)
16082 inst.instruction = 0xee310e60;
16084 /* Setting size which is 1 for F16 and 0 for F32. */
16085 inst.instruction |= (size == 16) << 28;
16090 if (((unsigned)inst.instruction) == 0x800)
16091 inst.instruction = 0xee010f40;
16093 else if (((unsigned)inst.instruction) == 0x1000800)
16094 inst.instruction = 0xee011f40;
16096 else if (((unsigned)inst.instruction) == 0)
16097 inst.instruction = 0xee000f40;
16099 else if (((unsigned)inst.instruction) == 0x200)
16100 inst.instruction = 0xee001f40;
16102 else if (((unsigned)inst.instruction) == 0x900)
16103 inst.instruction = 0xee010e40;
16105 else if (((unsigned)inst.instruction) == 0x910)
16106 inst.instruction = 0xee011e60;
16108 else if (((unsigned)inst.instruction) == 0x10)
16109 inst.instruction = 0xee000f60;
16111 else if (((unsigned)inst.instruction) == 0x210)
16112 inst.instruction = 0xee001f60;
16114 else if (((unsigned)inst.instruction) == 0x3000b10)
16115 inst.instruction = 0xee000e40;
16117 else if (((unsigned)inst.instruction) == 0x0000b00)
16118 inst.instruction = 0xee010e60;
16120 else if (((unsigned)inst.instruction) == 0x1000b00)
16121 inst.instruction = 0xfe010e60;
16124 inst.instruction |= U << 28;
16126 /* Setting bits for size. */
16127 inst.instruction |= neon_logbits (size) << 20;
16129 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16130 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16131 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16132 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16133 inst.instruction |= inst.operands[2].reg;
16138 mve_encode_rqq (unsigned bit28, unsigned size)
16140 inst.instruction |= bit28 << 28;
16141 inst.instruction |= neon_logbits (size) << 20;
16142 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16143 inst.instruction |= inst.operands[0].reg << 12;
16144 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16145 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16146 inst.instruction |= LOW4 (inst.operands[2].reg);
16151 mve_encode_qqq (int ubit, int size)
16154 inst.instruction |= (ubit != 0) << 28;
16155 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16156 inst.instruction |= neon_logbits (size) << 20;
16157 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16158 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16159 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16160 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16161 inst.instruction |= LOW4 (inst.operands[2].reg);
16167 mve_encode_rq (unsigned bit28, unsigned size)
16169 inst.instruction |= bit28 << 28;
16170 inst.instruction |= neon_logbits (size) << 18;
16171 inst.instruction |= inst.operands[0].reg << 12;
16172 inst.instruction |= LOW4 (inst.operands[1].reg);
16177 mve_encode_rrqq (unsigned U, unsigned size)
16179 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16181 inst.instruction |= U << 28;
16182 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16183 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16184 inst.instruction |= (size == 32) << 16;
16185 inst.instruction |= inst.operands[0].reg << 12;
16186 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16187 inst.instruction |= inst.operands[3].reg;
16191 /* Encode insns with bit pattern:
16193 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16194 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16196 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16197 different meaning for some instruction. */
16200 neon_three_same (int isquad, int ubit, int size)
16202 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16203 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16204 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16205 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16206 inst.instruction |= LOW4 (inst.operands[2].reg);
16207 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16208 inst.instruction |= (isquad != 0) << 6;
16209 inst.instruction |= (ubit != 0) << 24;
16211 inst.instruction |= neon_logbits (size) << 20;
16213 neon_dp_fixup (&inst);
16216 /* Encode instructions of the form:
16218 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16219 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16221 Don't write size if SIZE == -1. */
16224 neon_two_same (int qbit, int ubit, int size)
16226 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16227 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16228 inst.instruction |= LOW4 (inst.operands[1].reg);
16229 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16230 inst.instruction |= (qbit != 0) << 6;
16231 inst.instruction |= (ubit != 0) << 24;
16234 inst.instruction |= neon_logbits (size) << 18;
16236 neon_dp_fixup (&inst);
16239 enum vfp_or_neon_is_neon_bits
16242 NEON_CHECK_ARCH = 2,
16243 NEON_CHECK_ARCH8 = 4
16246 /* Call this function if an instruction which may have belonged to the VFP or
16247 Neon instruction sets, but turned out to be a Neon instruction (due to the
16248 operand types involved, etc.). We have to check and/or fix-up a couple of
16251 - Make sure the user hasn't attempted to make a Neon instruction
16253 - Alter the value in the condition code field if necessary.
16254 - Make sure that the arch supports Neon instructions.
16256 Which of these operations take place depends on bits from enum
16257 vfp_or_neon_is_neon_bits.
16259 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16260 current instruction's condition is COND_ALWAYS, the condition field is
16261 changed to inst.uncond_value. This is necessary because instructions shared
16262 between VFP and Neon may be conditional for the VFP variants only, and the
16263 unconditional Neon version must have, e.g., 0xF in the condition field. */
16266 vfp_or_neon_is_neon (unsigned check)
16268 /* Conditions are always legal in Thumb mode (IT blocks). */
16269 if (!thumb_mode && (check & NEON_CHECK_CC))
16271 if (inst.cond != COND_ALWAYS)
16273 first_error (_(BAD_COND));
16276 if (inst.uncond_value != -1)
16277 inst.instruction |= inst.uncond_value << 28;
16281 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16282 || ((check & NEON_CHECK_ARCH8)
16283 && !mark_feature_used (&fpu_neon_ext_armv8)))
16285 first_error (_(BAD_FPU));
16293 check_simd_pred_availability (int fp, unsigned check)
16295 if (inst.cond > COND_ALWAYS)
16297 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16299 inst.error = BAD_FPU;
16302 inst.pred_insn_type = INSIDE_VPT_INSN;
16304 else if (inst.cond < COND_ALWAYS)
16306 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16307 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16308 else if (vfp_or_neon_is_neon (check) == FAIL)
16313 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16314 && vfp_or_neon_is_neon (check) == FAIL)
16317 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16318 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16323 /* Neon instruction encoders, in approximate order of appearance. */
16326 do_neon_dyadic_i_su (void)
16328 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16331 enum neon_shape rs;
16332 struct neon_type_el et;
16333 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16334 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16336 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16338 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16342 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16344 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16348 do_neon_dyadic_i64_su (void)
16350 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
16352 enum neon_shape rs;
16353 struct neon_type_el et;
16354 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16356 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16357 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16361 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16362 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16365 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16367 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16371 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
16374 unsigned size = et.size >> 3;
16375 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16376 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16377 inst.instruction |= LOW4 (inst.operands[1].reg);
16378 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16379 inst.instruction |= (isquad != 0) << 6;
16380 inst.instruction |= immbits << 16;
16381 inst.instruction |= (size >> 3) << 7;
16382 inst.instruction |= (size & 0x7) << 19;
16384 inst.instruction |= (uval != 0) << 24;
16386 neon_dp_fixup (&inst);
16392 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16395 if (!inst.operands[2].isreg)
16397 enum neon_shape rs;
16398 struct neon_type_el et;
16399 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16401 rs = neon_select_shape (NS_QQI, NS_NULL);
16402 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16406 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16407 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16409 int imm = inst.operands[2].imm;
16411 constraint (imm < 0 || (unsigned)imm >= et.size,
16412 _("immediate out of range for shift"));
16413 NEON_ENCODE (IMMED, inst);
16414 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
16418 enum neon_shape rs;
16419 struct neon_type_el et;
16420 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16422 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16423 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16427 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16428 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16434 constraint (inst.operands[0].reg != inst.operands[1].reg,
16435 _("invalid instruction shape"));
16436 if (inst.operands[2].reg == REG_SP)
16437 as_tsktsk (MVE_BAD_SP);
16438 else if (inst.operands[2].reg == REG_PC)
16439 as_tsktsk (MVE_BAD_PC);
16441 inst.instruction = 0xee311e60;
16442 inst.instruction |= (et.type == NT_unsigned) << 28;
16443 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16444 inst.instruction |= neon_logbits (et.size) << 18;
16445 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16446 inst.instruction |= inst.operands[2].reg;
16453 /* VSHL/VQSHL 3-register variants have syntax such as:
16455 whereas other 3-register operations encoded by neon_three_same have
16458 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16459 operands[2].reg here. */
16460 tmp = inst.operands[2].reg;
16461 inst.operands[2].reg = inst.operands[1].reg;
16462 inst.operands[1].reg = tmp;
16463 NEON_ENCODE (INTEGER, inst);
16464 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16470 do_neon_qshl (void)
16472 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16475 if (!inst.operands[2].isreg)
16477 enum neon_shape rs;
16478 struct neon_type_el et;
16479 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16481 rs = neon_select_shape (NS_QQI, NS_NULL);
16482 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
16486 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16487 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16489 int imm = inst.operands[2].imm;
16491 constraint (imm < 0 || (unsigned)imm >= et.size,
16492 _("immediate out of range for shift"));
16493 NEON_ENCODE (IMMED, inst);
16494 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
16498 enum neon_shape rs;
16499 struct neon_type_el et;
16501 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16503 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16504 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16508 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16509 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16514 constraint (inst.operands[0].reg != inst.operands[1].reg,
16515 _("invalid instruction shape"));
16516 if (inst.operands[2].reg == REG_SP)
16517 as_tsktsk (MVE_BAD_SP);
16518 else if (inst.operands[2].reg == REG_PC)
16519 as_tsktsk (MVE_BAD_PC);
16521 inst.instruction = 0xee311ee0;
16522 inst.instruction |= (et.type == NT_unsigned) << 28;
16523 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16524 inst.instruction |= neon_logbits (et.size) << 18;
16525 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16526 inst.instruction |= inst.operands[2].reg;
16533 /* See note in do_neon_shl. */
16534 tmp = inst.operands[2].reg;
16535 inst.operands[2].reg = inst.operands[1].reg;
16536 inst.operands[1].reg = tmp;
16537 NEON_ENCODE (INTEGER, inst);
16538 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16544 do_neon_rshl (void)
16546 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
16549 enum neon_shape rs;
16550 struct neon_type_el et;
16551 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16553 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16554 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16558 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16559 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16566 if (inst.operands[2].reg == REG_PC)
16567 as_tsktsk (MVE_BAD_PC);
16568 else if (inst.operands[2].reg == REG_SP)
16569 as_tsktsk (MVE_BAD_SP);
16571 constraint (inst.operands[0].reg != inst.operands[1].reg,
16572 _("invalid instruction shape"));
16574 if (inst.instruction == 0x0000510)
16575 /* We are dealing with vqrshl. */
16576 inst.instruction = 0xee331ee0;
16578 /* We are dealing with vrshl. */
16579 inst.instruction = 0xee331e60;
16581 inst.instruction |= (et.type == NT_unsigned) << 28;
16582 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16583 inst.instruction |= neon_logbits (et.size) << 18;
16584 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16585 inst.instruction |= inst.operands[2].reg;
16590 tmp = inst.operands[2].reg;
16591 inst.operands[2].reg = inst.operands[1].reg;
16592 inst.operands[1].reg = tmp;
16593 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16598 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
16600 /* Handle .I8 pseudo-instructions. */
16603 /* Unfortunately, this will make everything apart from zero out-of-range.
16604 FIXME is this the intended semantics? There doesn't seem much point in
16605 accepting .I8 if so. */
16606 immediate |= immediate << 8;
16612 if (immediate == (immediate & 0x000000ff))
16614 *immbits = immediate;
16617 else if (immediate == (immediate & 0x0000ff00))
16619 *immbits = immediate >> 8;
16622 else if (immediate == (immediate & 0x00ff0000))
16624 *immbits = immediate >> 16;
16627 else if (immediate == (immediate & 0xff000000))
16629 *immbits = immediate >> 24;
16632 if ((immediate & 0xffff) != (immediate >> 16))
16633 goto bad_immediate;
16634 immediate &= 0xffff;
16637 if (immediate == (immediate & 0x000000ff))
16639 *immbits = immediate;
16642 else if (immediate == (immediate & 0x0000ff00))
16644 *immbits = immediate >> 8;
16649 first_error (_("immediate value out of range"));
16654 do_neon_logic (void)
16656 if (inst.operands[2].present && inst.operands[2].isreg)
16658 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16660 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16663 else if (rs != NS_QQQ
16664 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16665 first_error (BAD_FPU);
16667 neon_check_type (3, rs, N_IGNORE_TYPE);
16668 /* U bit and size field were set as part of the bitmask. */
16669 NEON_ENCODE (INTEGER, inst);
16670 neon_three_same (neon_quad (rs), 0, -1);
16674 const int three_ops_form = (inst.operands[2].present
16675 && !inst.operands[2].isreg);
16676 const int immoperand = (three_ops_form ? 2 : 1);
16677 enum neon_shape rs = (three_ops_form
16678 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
16679 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
16680 /* Because neon_select_shape makes the second operand a copy of the first
16681 if the second operand is not present. */
16683 && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
16686 else if (rs != NS_QQI
16687 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
16688 first_error (BAD_FPU);
16690 struct neon_type_el et;
16691 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16692 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
16694 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
16697 if (et.type == NT_invtype)
16699 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
16704 if (three_ops_form)
16705 constraint (inst.operands[0].reg != inst.operands[1].reg,
16706 _("first and second operands shall be the same register"));
16708 NEON_ENCODE (IMMED, inst);
16710 immbits = inst.operands[immoperand].imm;
16713 /* .i64 is a pseudo-op, so the immediate must be a repeating
16715 if (immbits != (inst.operands[immoperand].regisimm ?
16716 inst.operands[immoperand].reg : 0))
16718 /* Set immbits to an invalid constant. */
16719 immbits = 0xdeadbeef;
16726 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16730 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16734 /* Pseudo-instruction for VBIC. */
16735 neon_invert_size (&immbits, 0, et.size);
16736 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16740 /* Pseudo-instruction for VORR. */
16741 neon_invert_size (&immbits, 0, et.size);
16742 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
16752 inst.instruction |= neon_quad (rs) << 6;
16753 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16754 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16755 inst.instruction |= cmode << 8;
16756 neon_write_immbits (immbits);
16758 neon_dp_fixup (&inst);
16763 do_neon_bitfield (void)
16765 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16766 neon_check_type (3, rs, N_IGNORE_TYPE);
16767 neon_three_same (neon_quad (rs), 0, -1);
16771 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
16774 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
16775 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
16777 if (et.type == NT_float)
16779 NEON_ENCODE (FLOAT, inst);
16781 mve_encode_qqr (et.size, 0, 1);
16783 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
16787 NEON_ENCODE (INTEGER, inst);
16789 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
16791 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
16797 do_neon_dyadic_if_su_d (void)
16799 /* This version only allow D registers, but that constraint is enforced during
16800 operand parsing so we don't need to do anything extra here. */
16801 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
16805 do_neon_dyadic_if_i_d (void)
16807 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16808 affected if we specify unsigned args. */
16809 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
16813 do_mve_vstr_vldr_QI (int size, int elsize, int load)
16815 constraint (size < 32, BAD_ADDR_MODE);
16816 constraint (size != elsize, BAD_EL_TYPE);
16817 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16818 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
16819 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
16820 _("destination register and offset register may not be the"
16823 int imm = inst.relocs[0].exp.X_add_number;
16830 constraint ((imm % (size / 8) != 0)
16831 || imm > (0x7f << neon_logbits (size)),
16832 (size == 32) ? _("immediate must be a multiple of 4 in the"
16833 " range of +/-[0,508]")
16834 : _("immediate must be a multiple of 8 in the"
16835 " range of +/-[0,1016]"));
16836 inst.instruction |= 0x11 << 24;
16837 inst.instruction |= add << 23;
16838 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16839 inst.instruction |= inst.operands[1].writeback << 21;
16840 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16841 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16842 inst.instruction |= 1 << 12;
16843 inst.instruction |= (size == 64) << 8;
16844 inst.instruction &= 0xffffff00;
16845 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16846 inst.instruction |= imm >> neon_logbits (size);
16850 do_mve_vstr_vldr_RQ (int size, int elsize, int load)
16852 unsigned os = inst.operands[1].imm >> 5;
16853 constraint (os != 0 && size == 8,
16854 _("can not shift offsets when accessing less than half-word"));
16855 constraint (os && os != neon_logbits (size),
16856 _("shift immediate must be 1, 2 or 3 for half-word, word"
16857 " or double-word accesses respectively"));
16858 if (inst.operands[1].reg == REG_PC)
16859 as_tsktsk (MVE_BAD_PC);
16864 constraint (elsize >= 64, BAD_EL_TYPE);
16867 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16871 constraint (elsize != size, BAD_EL_TYPE);
16876 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
16880 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
16881 _("destination register and offset register may not be"
16883 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
16885 constraint (inst.vectype.el[0].type != NT_unsigned
16886 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
16887 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
16891 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
16894 inst.instruction |= 1 << 23;
16895 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16896 inst.instruction |= inst.operands[1].reg << 16;
16897 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16898 inst.instruction |= neon_logbits (elsize) << 7;
16899 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
16900 inst.instruction |= LOW4 (inst.operands[1].imm);
16901 inst.instruction |= !!os;
16905 do_mve_vstr_vldr_RI (int size, int elsize, int load)
16907 enum neon_el_type type = inst.vectype.el[0].type;
16909 constraint (size >= 64, BAD_ADDR_MODE);
16913 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
16916 constraint (elsize != size, BAD_EL_TYPE);
16923 constraint (elsize != size && type != NT_unsigned
16924 && type != NT_signed, BAD_EL_TYPE);
16928 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
16931 int imm = inst.relocs[0].exp.X_add_number;
16939 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
16944 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16947 constraint (1, _("immediate must be a multiple of 2 in the"
16948 " range of +/-[0,254]"));
16951 constraint (1, _("immediate must be a multiple of 4 in the"
16952 " range of +/-[0,508]"));
16957 if (size != elsize)
16959 constraint (inst.operands[1].reg > 7, BAD_HIREG);
16960 constraint (inst.operands[0].reg > 14,
16961 _("MVE vector register in the range [Q0..Q7] expected"));
16962 inst.instruction |= (load && type == NT_unsigned) << 28;
16963 inst.instruction |= (size == 16) << 19;
16964 inst.instruction |= neon_logbits (elsize) << 7;
16968 if (inst.operands[1].reg == REG_PC)
16969 as_tsktsk (MVE_BAD_PC);
16970 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
16971 as_tsktsk (MVE_BAD_SP);
16972 inst.instruction |= 1 << 12;
16973 inst.instruction |= neon_logbits (size) << 7;
16975 inst.instruction |= inst.operands[1].preind << 24;
16976 inst.instruction |= add << 23;
16977 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16978 inst.instruction |= inst.operands[1].writeback << 21;
16979 inst.instruction |= inst.operands[1].reg << 16;
16980 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16981 inst.instruction &= 0xffffff80;
16982 inst.instruction |= imm >> neon_logbits (size);
16987 do_mve_vstr_vldr (void)
16992 if (inst.cond > COND_ALWAYS)
16993 inst.pred_insn_type = INSIDE_VPT_INSN;
16995 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16997 switch (inst.instruction)
17004 /* fall through. */
17010 /* fall through. */
17016 /* fall through. */
17022 /* fall through. */
17027 unsigned elsize = inst.vectype.el[0].size;
17029 if (inst.operands[1].isquad)
17031 /* We are dealing with [Q, imm]{!} cases. */
17032 do_mve_vstr_vldr_QI (size, elsize, load);
17036 if (inst.operands[1].immisreg == 2)
17038 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17039 do_mve_vstr_vldr_RQ (size, elsize, load);
17041 else if (!inst.operands[1].immisreg)
17043 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17044 do_mve_vstr_vldr_RI (size, elsize, load);
17047 constraint (1, BAD_ADDR_MODE);
17054 do_mve_vst_vld (void)
17056 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17059 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17060 || inst.relocs[0].exp.X_add_number != 0
17061 || inst.operands[1].immisreg != 0,
17063 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17064 if (inst.operands[1].reg == REG_PC)
17065 as_tsktsk (MVE_BAD_PC);
17066 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17067 as_tsktsk (MVE_BAD_SP);
17070 /* These instructions are one of the "exceptions" mentioned in
17071 handle_pred_state. They are MVE instructions that are not VPT compatible
17072 and do not accept a VPT code, thus appending such a code is a syntax
17074 if (inst.cond > COND_ALWAYS)
17075 first_error (BAD_SYNTAX);
17076 /* If we append a scalar condition code we can set this to
17077 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17078 else if (inst.cond < COND_ALWAYS)
17079 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17081 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17083 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17084 inst.instruction |= inst.operands[1].writeback << 21;
17085 inst.instruction |= inst.operands[1].reg << 16;
17086 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17087 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17092 do_mve_vaddlv (void)
17094 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17095 struct neon_type_el et
17096 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17098 if (et.type == NT_invtype)
17099 first_error (BAD_EL_TYPE);
17101 if (inst.cond > COND_ALWAYS)
17102 inst.pred_insn_type = INSIDE_VPT_INSN;
17104 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17106 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17108 inst.instruction |= (et.type == NT_unsigned) << 28;
17109 inst.instruction |= inst.operands[1].reg << 19;
17110 inst.instruction |= inst.operands[0].reg << 12;
17111 inst.instruction |= inst.operands[2].reg;
17116 do_neon_dyadic_if_su (void)
17118 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17119 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17122 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17123 || inst.instruction == ((unsigned) N_MNEM_vmin))
17124 && et.type == NT_float
17125 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17127 if (check_simd_pred_availability (et.type == NT_float,
17128 NEON_CHECK_ARCH | NEON_CHECK_CC))
17131 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17135 do_neon_addsub_if_i (void)
17137 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17138 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
17141 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17142 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17143 N_EQK, N_IF_32 | N_I64 | N_KEY);
17145 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17146 /* If we are parsing Q registers and the element types match MVE, which NEON
17147 also supports, then we must check whether this is an instruction that can
17148 be used by both MVE/NEON. This distinction can be made based on whether
17149 they are predicated or not. */
17150 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17152 if (check_simd_pred_availability (et.type == NT_float,
17153 NEON_CHECK_ARCH | NEON_CHECK_CC))
17158 /* If they are either in a D register or are using an unsupported. */
17160 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17164 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17165 affected if we specify unsigned args. */
17166 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
17169 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17171 V<op> A,B (A is operand 0, B is operand 2)
17176 so handle that case specially. */
17179 neon_exchange_operands (void)
17181 if (inst.operands[1].present)
17183 void *scratch = xmalloc (sizeof (inst.operands[0]));
17185 /* Swap operands[1] and operands[2]. */
17186 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17187 inst.operands[1] = inst.operands[2];
17188 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
17193 inst.operands[1] = inst.operands[2];
17194 inst.operands[2] = inst.operands[0];
17199 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17201 if (inst.operands[2].isreg)
17204 neon_exchange_operands ();
17205 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
17209 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17210 struct neon_type_el et = neon_check_type (2, rs,
17211 N_EQK | N_SIZ, immtypes | N_KEY);
17213 NEON_ENCODE (IMMED, inst);
17214 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17215 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17216 inst.instruction |= LOW4 (inst.operands[1].reg);
17217 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17218 inst.instruction |= neon_quad (rs) << 6;
17219 inst.instruction |= (et.type == NT_float) << 10;
17220 inst.instruction |= neon_logbits (et.size) << 18;
17222 neon_dp_fixup (&inst);
17229 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
17233 do_neon_cmp_inv (void)
17235 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
17241 neon_compare (N_IF_32, N_IF_32, FALSE);
17244 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17245 scalars, which are encoded in 5 bits, M : Rm.
17246 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17247 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17250 Dot Product instructions are similar to multiply instructions except elsize
17251 should always be 32.
17253 This function translates SCALAR, which is GAS's internal encoding of indexed
17254 scalar register, to raw encoding. There is also register and index range
17255 check based on ELSIZE. */
17258 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17260 unsigned regno = NEON_SCALAR_REG (scalar);
17261 unsigned elno = NEON_SCALAR_INDEX (scalar);
17266 if (regno > 7 || elno > 3)
17268 return regno | (elno << 3);
17271 if (regno > 15 || elno > 1)
17273 return regno | (elno << 4);
17277 first_error (_("scalar out of range for multiply instruction"));
17283 /* Encode multiply / multiply-accumulate scalar instructions. */
17286 neon_mul_mac (struct neon_type_el et, int ubit)
17290 /* Give a more helpful error message if we have an invalid type. */
17291 if (et.type == NT_invtype)
17294 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
17295 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17296 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17297 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17298 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17299 inst.instruction |= LOW4 (scalar);
17300 inst.instruction |= HI1 (scalar) << 5;
17301 inst.instruction |= (et.type == NT_float) << 8;
17302 inst.instruction |= neon_logbits (et.size) << 20;
17303 inst.instruction |= (ubit != 0) << 24;
17305 neon_dp_fixup (&inst);
17309 do_neon_mac_maybe_scalar (void)
17311 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17314 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
17317 if (inst.operands[2].isscalar)
17319 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17320 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17321 struct neon_type_el et = neon_check_type (3, rs,
17322 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
17323 NEON_ENCODE (SCALAR, inst);
17324 neon_mul_mac (et, neon_quad (rs));
17326 else if (!inst.operands[2].isvec)
17328 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17330 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17331 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17333 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17337 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17338 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17339 affected if we specify unsigned args. */
17340 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17345 do_neon_fmac (void)
17347 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17348 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
17351 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
17354 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17356 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17357 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17362 if (inst.operands[2].reg == REG_SP)
17363 as_tsktsk (MVE_BAD_SP);
17364 else if (inst.operands[2].reg == REG_PC)
17365 as_tsktsk (MVE_BAD_PC);
17367 inst.instruction = 0xee310e40;
17368 inst.instruction |= (et.size == 16) << 28;
17369 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17370 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17371 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17372 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17373 inst.instruction |= inst.operands[2].reg;
17380 constraint (!inst.operands[2].isvec, BAD_FPU);
17383 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17389 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17390 struct neon_type_el et = neon_check_type (3, rs,
17391 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17392 neon_three_same (neon_quad (rs), 0, et.size);
17395 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17396 same types as the MAC equivalents. The polynomial type for this instruction
17397 is encoded the same as the integer type. */
17402 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17405 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
17408 if (inst.operands[2].isscalar)
17410 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17411 do_neon_mac_maybe_scalar ();
17415 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17417 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17418 struct neon_type_el et
17419 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
17420 if (et.type == NT_float)
17421 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
17424 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
17428 constraint (!inst.operands[2].isvec, BAD_FPU);
17429 neon_dyadic_misc (NT_poly,
17430 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17436 do_neon_qdmulh (void)
17438 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
17441 if (inst.operands[2].isscalar)
17443 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17444 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17445 struct neon_type_el et = neon_check_type (3, rs,
17446 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17447 NEON_ENCODE (SCALAR, inst);
17448 neon_mul_mac (et, neon_quad (rs));
17452 enum neon_shape rs;
17453 struct neon_type_el et;
17454 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17456 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17457 et = neon_check_type (3, rs,
17458 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17462 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17463 et = neon_check_type (3, rs,
17464 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17467 NEON_ENCODE (INTEGER, inst);
17469 mve_encode_qqr (et.size, 0, 0);
17471 /* The U bit (rounding) comes from bit mask. */
17472 neon_three_same (neon_quad (rs), 0, et.size);
17477 do_mve_vaddv (void)
17479 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17480 struct neon_type_el et
17481 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17483 if (et.type == NT_invtype)
17484 first_error (BAD_EL_TYPE);
17486 if (inst.cond > COND_ALWAYS)
17487 inst.pred_insn_type = INSIDE_VPT_INSN;
17489 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17491 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17493 mve_encode_rq (et.type == NT_unsigned, et.size);
17497 do_mve_vhcadd (void)
17499 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17500 struct neon_type_el et
17501 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17503 if (inst.cond > COND_ALWAYS)
17504 inst.pred_insn_type = INSIDE_VPT_INSN;
17506 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17508 unsigned rot = inst.relocs[0].exp.X_add_number;
17509 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17511 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17512 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17513 "operand makes instruction UNPREDICTABLE"));
17515 mve_encode_qqq (0, et.size);
17516 inst.instruction |= (rot == 270) << 12;
17521 do_mve_vqdmull (void)
17523 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17524 struct neon_type_el et
17525 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17528 && (inst.operands[0].reg == inst.operands[1].reg
17529 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17530 as_tsktsk (BAD_MVE_SRCDEST);
17532 if (inst.cond > COND_ALWAYS)
17533 inst.pred_insn_type = INSIDE_VPT_INSN;
17535 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17539 mve_encode_qqq (et.size == 32, 64);
17540 inst.instruction |= 1;
17544 mve_encode_qqr (64, et.size == 32, 0);
17545 inst.instruction |= 0x3 << 5;
17552 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17553 struct neon_type_el et
17554 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17556 if (et.type == NT_invtype)
17557 first_error (BAD_EL_TYPE);
17559 if (inst.cond > COND_ALWAYS)
17560 inst.pred_insn_type = INSIDE_VPT_INSN;
17562 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17564 mve_encode_qqq (0, 64);
17568 do_mve_vbrsr (void)
17570 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17571 struct neon_type_el et
17572 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17574 if (inst.cond > COND_ALWAYS)
17575 inst.pred_insn_type = INSIDE_VPT_INSN;
17577 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17579 mve_encode_qqr (et.size, 0, 0);
17585 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
17587 if (inst.cond > COND_ALWAYS)
17588 inst.pred_insn_type = INSIDE_VPT_INSN;
17590 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17592 mve_encode_qqq (1, 64);
17596 do_mve_vmulh (void)
17598 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17599 struct neon_type_el et
17600 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17602 if (inst.cond > COND_ALWAYS)
17603 inst.pred_insn_type = INSIDE_VPT_INSN;
17605 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17607 mve_encode_qqq (et.type == NT_unsigned, et.size);
17611 do_mve_vqdmlah (void)
17613 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17614 struct neon_type_el et
17615 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17617 if (inst.cond > COND_ALWAYS)
17618 inst.pred_insn_type = INSIDE_VPT_INSN;
17620 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17622 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
17626 do_mve_vqdmladh (void)
17628 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17629 struct neon_type_el et
17630 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17632 if (inst.cond > COND_ALWAYS)
17633 inst.pred_insn_type = INSIDE_VPT_INSN;
17635 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17638 && (inst.operands[0].reg == inst.operands[1].reg
17639 || inst.operands[0].reg == inst.operands[2].reg))
17640 as_tsktsk (BAD_MVE_SRCDEST);
17642 mve_encode_qqq (0, et.size);
17647 do_mve_vmull (void)
17650 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
17651 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
17652 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
17653 && inst.cond == COND_ALWAYS
17654 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
17659 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17660 N_SUF_32 | N_F64 | N_P8
17661 | N_P16 | N_I_MVE | N_KEY);
17662 if (((et.type == NT_poly) && et.size == 8
17663 && ARM_CPU_IS_ANY (cpu_variant))
17664 || (et.type == NT_integer) || (et.type == NT_float))
17671 constraint (rs != NS_QQQ, BAD_FPU);
17672 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17673 N_SU_32 | N_P8 | N_P16 | N_KEY);
17675 /* We are dealing with MVE's vmullt. */
17677 && (inst.operands[0].reg == inst.operands[1].reg
17678 || inst.operands[0].reg == inst.operands[2].reg))
17679 as_tsktsk (BAD_MVE_SRCDEST);
17681 if (inst.cond > COND_ALWAYS)
17682 inst.pred_insn_type = INSIDE_VPT_INSN;
17684 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17686 if (et.type == NT_poly)
17687 mve_encode_qqq (neon_logbits (et.size), 64);
17689 mve_encode_qqq (et.type == NT_unsigned, et.size);
17694 inst.instruction = N_MNEM_vmul;
17697 inst.pred_insn_type = INSIDE_IT_INSN;
17702 do_mve_vabav (void)
17704 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17709 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17712 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
17713 | N_S16 | N_S32 | N_U8 | N_U16
17716 if (inst.cond > COND_ALWAYS)
17717 inst.pred_insn_type = INSIDE_VPT_INSN;
17719 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17721 mve_encode_rqq (et.type == NT_unsigned, et.size);
17725 do_mve_vmladav (void)
17727 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
17728 struct neon_type_el et = neon_check_type (3, rs,
17729 N_EQK, N_EQK, N_SU_MVE | N_KEY);
17731 if (et.type == NT_unsigned
17732 && (inst.instruction == M_MNEM_vmladavx
17733 || inst.instruction == M_MNEM_vmladavax
17734 || inst.instruction == M_MNEM_vmlsdav
17735 || inst.instruction == M_MNEM_vmlsdava
17736 || inst.instruction == M_MNEM_vmlsdavx
17737 || inst.instruction == M_MNEM_vmlsdavax))
17738 first_error (BAD_SIMD_TYPE);
17740 constraint (inst.operands[2].reg > 14,
17741 _("MVE vector register in the range [Q0..Q7] expected"));
17743 if (inst.cond > COND_ALWAYS)
17744 inst.pred_insn_type = INSIDE_VPT_INSN;
17746 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17748 if (inst.instruction == M_MNEM_vmlsdav
17749 || inst.instruction == M_MNEM_vmlsdava
17750 || inst.instruction == M_MNEM_vmlsdavx
17751 || inst.instruction == M_MNEM_vmlsdavax)
17752 inst.instruction |= (et.size == 8) << 28;
17754 inst.instruction |= (et.size == 8) << 8;
17756 mve_encode_rqq (et.type == NT_unsigned, 64);
17757 inst.instruction |= (et.size == 32) << 16;
17761 do_mve_vmlaldav (void)
17763 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
17764 struct neon_type_el et
17765 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
17766 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
17768 if (et.type == NT_unsigned
17769 && (inst.instruction == M_MNEM_vmlsldav
17770 || inst.instruction == M_MNEM_vmlsldava
17771 || inst.instruction == M_MNEM_vmlsldavx
17772 || inst.instruction == M_MNEM_vmlsldavax))
17773 first_error (BAD_SIMD_TYPE);
17775 if (inst.cond > COND_ALWAYS)
17776 inst.pred_insn_type = INSIDE_VPT_INSN;
17778 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17780 mve_encode_rrqq (et.type == NT_unsigned, et.size);
17784 do_mve_vrmlaldavh (void)
17786 struct neon_type_el et;
17787 if (inst.instruction == M_MNEM_vrmlsldavh
17788 || inst.instruction == M_MNEM_vrmlsldavha
17789 || inst.instruction == M_MNEM_vrmlsldavhx
17790 || inst.instruction == M_MNEM_vrmlsldavhax)
17792 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17793 if (inst.operands[1].reg == REG_SP)
17794 as_tsktsk (MVE_BAD_SP);
17798 if (inst.instruction == M_MNEM_vrmlaldavhx
17799 || inst.instruction == M_MNEM_vrmlaldavhax)
17800 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
17802 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
17803 N_U32 | N_S32 | N_KEY);
17804 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17805 with vmax/min instructions, making the use of SP in assembly really
17806 nonsensical, so instead of issuing a warning like we do for other uses
17807 of SP for the odd register operand we error out. */
17808 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
17811 /* Make sure we still check the second operand is an odd one and that PC is
17812 disallowed. This because we are parsing for any GPR operand, to be able
17813 to distinguish between giving a warning or an error for SP as described
17815 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
17816 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
17818 if (inst.cond > COND_ALWAYS)
17819 inst.pred_insn_type = INSIDE_VPT_INSN;
17821 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17823 mve_encode_rrqq (et.type == NT_unsigned, 0);
17828 do_mve_vmaxnmv (void)
17830 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17831 struct neon_type_el et
17832 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
17834 if (inst.cond > COND_ALWAYS)
17835 inst.pred_insn_type = INSIDE_VPT_INSN;
17837 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17839 if (inst.operands[0].reg == REG_SP)
17840 as_tsktsk (MVE_BAD_SP);
17841 else if (inst.operands[0].reg == REG_PC)
17842 as_tsktsk (MVE_BAD_PC);
17844 mve_encode_rq (et.size == 16, 64);
17848 do_mve_vmaxv (void)
17850 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17851 struct neon_type_el et;
17853 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
17854 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
17856 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17858 if (inst.cond > COND_ALWAYS)
17859 inst.pred_insn_type = INSIDE_VPT_INSN;
17861 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17863 if (inst.operands[0].reg == REG_SP)
17864 as_tsktsk (MVE_BAD_SP);
17865 else if (inst.operands[0].reg == REG_PC)
17866 as_tsktsk (MVE_BAD_PC);
17868 mve_encode_rq (et.type == NT_unsigned, et.size);
17873 do_neon_qrdmlah (void)
17875 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
17877 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17879 /* Check we're on the correct architecture. */
17880 if (!mark_feature_used (&fpu_neon_ext_armv8))
17882 = _("instruction form not available on this architecture.");
17883 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
17885 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17886 record_feature_use (&fpu_neon_ext_v8_1);
17888 if (inst.operands[2].isscalar)
17890 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17891 struct neon_type_el et = neon_check_type (3, rs,
17892 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17893 NEON_ENCODE (SCALAR, inst);
17894 neon_mul_mac (et, neon_quad (rs));
17898 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17899 struct neon_type_el et = neon_check_type (3, rs,
17900 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17901 NEON_ENCODE (INTEGER, inst);
17902 /* The U bit (rounding) comes from bit mask. */
17903 neon_three_same (neon_quad (rs), 0, et.size);
17908 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17909 struct neon_type_el et
17910 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17912 NEON_ENCODE (INTEGER, inst);
17913 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
17918 do_neon_fcmp_absolute (void)
17920 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17921 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17922 N_F_16_32 | N_KEY);
17923 /* Size field comes from bit mask. */
17924 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
17928 do_neon_fcmp_absolute_inv (void)
17930 neon_exchange_operands ();
17931 do_neon_fcmp_absolute ();
17935 do_neon_step (void)
17937 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17938 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
17939 N_F_16_32 | N_KEY);
17940 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
17944 do_neon_abs_neg (void)
17946 enum neon_shape rs;
17947 struct neon_type_el et;
17949 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
17952 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
17953 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
17955 if (check_simd_pred_availability (et.type == NT_float,
17956 NEON_CHECK_ARCH | NEON_CHECK_CC))
17959 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17960 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17961 inst.instruction |= LOW4 (inst.operands[1].reg);
17962 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17963 inst.instruction |= neon_quad (rs) << 6;
17964 inst.instruction |= (et.type == NT_float) << 10;
17965 inst.instruction |= neon_logbits (et.size) << 18;
17967 neon_dp_fixup (&inst);
17973 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
17976 enum neon_shape rs;
17977 struct neon_type_el et;
17978 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17980 rs = neon_select_shape (NS_QQI, NS_NULL);
17981 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17985 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17986 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
17990 int imm = inst.operands[2].imm;
17991 constraint (imm < 0 || (unsigned)imm >= et.size,
17992 _("immediate out of range for insert"));
17993 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
17999 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
18002 enum neon_shape rs;
18003 struct neon_type_el et;
18004 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18006 rs = neon_select_shape (NS_QQI, NS_NULL);
18007 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18011 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18012 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18015 int imm = inst.operands[2].imm;
18016 constraint (imm < 1 || (unsigned)imm > et.size,
18017 _("immediate out of range for insert"));
18018 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
18022 do_neon_qshlu_imm (void)
18024 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
18027 enum neon_shape rs;
18028 struct neon_type_el et;
18029 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18031 rs = neon_select_shape (NS_QQI, NS_NULL);
18032 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18036 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18037 et = neon_check_type (2, rs, N_EQK | N_UNS,
18038 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18041 int imm = inst.operands[2].imm;
18042 constraint (imm < 0 || (unsigned)imm >= et.size,
18043 _("immediate out of range for shift"));
18044 /* Only encodes the 'U present' variant of the instruction.
18045 In this case, signed types have OP (bit 8) set to 0.
18046 Unsigned types have OP set to 1. */
18047 inst.instruction |= (et.type == NT_unsigned) << 8;
18048 /* The rest of the bits are the same as other immediate shifts. */
18049 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
18053 do_neon_qmovn (void)
18055 struct neon_type_el et = neon_check_type (2, NS_DQ,
18056 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18057 /* Saturating move where operands can be signed or unsigned, and the
18058 destination has the same signedness. */
18059 NEON_ENCODE (INTEGER, inst);
18060 if (et.type == NT_unsigned)
18061 inst.instruction |= 0xc0;
18063 inst.instruction |= 0x80;
18064 neon_two_same (0, 1, et.size / 2);
18068 do_neon_qmovun (void)
18070 struct neon_type_el et = neon_check_type (2, NS_DQ,
18071 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18072 /* Saturating move with unsigned results. Operands must be signed. */
18073 NEON_ENCODE (INTEGER, inst);
18074 neon_two_same (0, 1, et.size / 2);
18078 do_neon_rshift_sat_narrow (void)
18080 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18081 or unsigned. If operands are unsigned, results must also be unsigned. */
18082 struct neon_type_el et = neon_check_type (2, NS_DQI,
18083 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18084 int imm = inst.operands[2].imm;
18085 /* This gets the bounds check, size encoding and immediate bits calculation
18089 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18090 VQMOVN.I<size> <Dd>, <Qm>. */
18093 inst.operands[2].present = 0;
18094 inst.instruction = N_MNEM_vqmovn;
18099 constraint (imm < 1 || (unsigned)imm > et.size,
18100 _("immediate out of range"));
18101 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18105 do_neon_rshift_sat_narrow_u (void)
18107 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18108 or unsigned. If operands are unsigned, results must also be unsigned. */
18109 struct neon_type_el et = neon_check_type (2, NS_DQI,
18110 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18111 int imm = inst.operands[2].imm;
18112 /* This gets the bounds check, size encoding and immediate bits calculation
18116 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18117 VQMOVUN.I<size> <Dd>, <Qm>. */
18120 inst.operands[2].present = 0;
18121 inst.instruction = N_MNEM_vqmovun;
18126 constraint (imm < 1 || (unsigned)imm > et.size,
18127 _("immediate out of range"));
18128 /* FIXME: The manual is kind of unclear about what value U should have in
18129 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18131 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18135 do_neon_movn (void)
18137 struct neon_type_el et = neon_check_type (2, NS_DQ,
18138 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18139 NEON_ENCODE (INTEGER, inst);
18140 neon_two_same (0, 1, et.size / 2);
18144 do_neon_rshift_narrow (void)
18146 struct neon_type_el et = neon_check_type (2, NS_DQI,
18147 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18148 int imm = inst.operands[2].imm;
18149 /* This gets the bounds check, size encoding and immediate bits calculation
18153 /* If immediate is zero then we are a pseudo-instruction for
18154 VMOVN.I<size> <Dd>, <Qm> */
18157 inst.operands[2].present = 0;
18158 inst.instruction = N_MNEM_vmovn;
18163 constraint (imm < 1 || (unsigned)imm > et.size,
18164 _("immediate out of range for narrowing operation"));
18165 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18169 do_neon_shll (void)
18171 /* FIXME: Type checking when lengthening. */
18172 struct neon_type_el et = neon_check_type (2, NS_QDI,
18173 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18174 unsigned imm = inst.operands[2].imm;
18176 if (imm == et.size)
18178 /* Maximum shift variant. */
18179 NEON_ENCODE (INTEGER, inst);
18180 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18181 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18182 inst.instruction |= LOW4 (inst.operands[1].reg);
18183 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18184 inst.instruction |= neon_logbits (et.size) << 18;
18186 neon_dp_fixup (&inst);
18190 /* A more-specific type check for non-max versions. */
18191 et = neon_check_type (2, NS_QDI,
18192 N_EQK | N_DBL, N_SU_32 | N_KEY);
18193 NEON_ENCODE (IMMED, inst);
18194 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18198 /* Check the various types for the VCVT instruction, and return which version
18199 the current instruction is. */
18201 #define CVT_FLAVOUR_VAR \
18202 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18203 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18204 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18205 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18206 /* Half-precision conversions. */ \
18207 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18208 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18209 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18210 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18211 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18212 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18213 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18214 Compared with single/double precision variants, only the co-processor \
18215 field is different, so the encoding flow is reused here. */ \
18216 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18217 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18218 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18219 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18220 /* VFP instructions. */ \
18221 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18222 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18223 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18224 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18225 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18226 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18227 /* VFP instructions with bitshift. */ \
18228 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18229 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18230 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18231 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18232 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18233 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18234 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18235 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18237 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18238 neon_cvt_flavour_##C,
18240 /* The different types of conversions we can do. */
18241 enum neon_cvt_flavour
18244 neon_cvt_flavour_invalid,
18245 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18250 static enum neon_cvt_flavour
18251 get_neon_cvt_flavour (enum neon_shape rs)
18253 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18254 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18255 if (et.type != NT_invtype) \
18257 inst.error = NULL; \
18258 return (neon_cvt_flavour_##C); \
18261 struct neon_type_el et;
18262 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
18263 || rs == NS_FF) ? N_VFP : 0;
18264 /* The instruction versions which take an immediate take one register
18265 argument, which is extended to the width of the full register. Thus the
18266 "source" and "destination" registers must have the same width. Hack that
18267 here by making the size equal to the key (wider, in this case) operand. */
18268 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
18272 return neon_cvt_flavour_invalid;
18287 /* Neon-syntax VFP conversions. */
18290 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
18292 const char *opname = 0;
18294 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18295 || rs == NS_FHI || rs == NS_HFI)
18297 /* Conversions with immediate bitshift. */
18298 const char *enc[] =
18300 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18306 if (flavour < (int) ARRAY_SIZE (enc))
18308 opname = enc[flavour];
18309 constraint (inst.operands[0].reg != inst.operands[1].reg,
18310 _("operands 0 and 1 must be the same register"));
18311 inst.operands[1] = inst.operands[2];
18312 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18317 /* Conversions without bitshift. */
18318 const char *enc[] =
18320 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18326 if (flavour < (int) ARRAY_SIZE (enc))
18327 opname = enc[flavour];
18331 do_vfp_nsyn_opcode (opname);
18333 /* ARMv8.2 fp16 VCVT instruction. */
18334 if (flavour == neon_cvt_flavour_s32_f16
18335 || flavour == neon_cvt_flavour_u32_f16
18336 || flavour == neon_cvt_flavour_f16_u32
18337 || flavour == neon_cvt_flavour_f16_s32)
18338 do_scalar_fp16_v82_encode ();
18342 do_vfp_nsyn_cvtz (void)
18344 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
18345 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18346 const char *enc[] =
18348 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18354 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
18355 do_vfp_nsyn_opcode (enc[flavour]);
18359 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
18360 enum neon_cvt_mode mode)
18365 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18366 D register operands. */
18367 if (flavour == neon_cvt_flavour_s32_f64
18368 || flavour == neon_cvt_flavour_u32_f64)
18369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18372 if (flavour == neon_cvt_flavour_s32_f16
18373 || flavour == neon_cvt_flavour_u32_f16)
18374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18377 set_pred_insn_type (OUTSIDE_PRED_INSN);
18381 case neon_cvt_flavour_s32_f64:
18385 case neon_cvt_flavour_s32_f32:
18389 case neon_cvt_flavour_s32_f16:
18393 case neon_cvt_flavour_u32_f64:
18397 case neon_cvt_flavour_u32_f32:
18401 case neon_cvt_flavour_u32_f16:
18406 first_error (_("invalid instruction shape"));
18412 case neon_cvt_mode_a: rm = 0; break;
18413 case neon_cvt_mode_n: rm = 1; break;
18414 case neon_cvt_mode_p: rm = 2; break;
18415 case neon_cvt_mode_m: rm = 3; break;
18416 default: first_error (_("invalid rounding mode")); return;
18419 NEON_ENCODE (FPV8, inst);
18420 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18421 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18422 inst.instruction |= sz << 8;
18424 /* ARMv8.2 fp16 VCVT instruction. */
18425 if (flavour == neon_cvt_flavour_s32_f16
18426 ||flavour == neon_cvt_flavour_u32_f16)
18427 do_scalar_fp16_v82_encode ();
18428 inst.instruction |= op << 7;
18429 inst.instruction |= rm << 16;
18430 inst.instruction |= 0xf0000000;
18431 inst.is_neon = TRUE;
18435 do_neon_cvt_1 (enum neon_cvt_mode mode)
18437 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
18438 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
18439 NS_FH, NS_HF, NS_FHI, NS_HFI,
18441 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18443 if (flavour == neon_cvt_flavour_invalid)
18446 /* PR11109: Handle round-to-zero for VCVT conversions. */
18447 if (mode == neon_cvt_mode_z
18448 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
18449 && (flavour == neon_cvt_flavour_s16_f16
18450 || flavour == neon_cvt_flavour_u16_f16
18451 || flavour == neon_cvt_flavour_s32_f32
18452 || flavour == neon_cvt_flavour_u32_f32
18453 || flavour == neon_cvt_flavour_s32_f64
18454 || flavour == neon_cvt_flavour_u32_f64)
18455 && (rs == NS_FD || rs == NS_FF))
18457 do_vfp_nsyn_cvtz ();
18461 /* ARMv8.2 fp16 VCVT conversions. */
18462 if (mode == neon_cvt_mode_z
18463 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
18464 && (flavour == neon_cvt_flavour_s32_f16
18465 || flavour == neon_cvt_flavour_u32_f16)
18468 do_vfp_nsyn_cvtz ();
18469 do_scalar_fp16_v82_encode ();
18473 /* VFP rather than Neon conversions. */
18474 if (flavour >= neon_cvt_flavour_first_fp)
18476 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18477 do_vfp_nsyn_cvt (rs, flavour);
18479 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18487 if (mode == neon_cvt_mode_z
18488 && (flavour == neon_cvt_flavour_f16_s16
18489 || flavour == neon_cvt_flavour_f16_u16
18490 || flavour == neon_cvt_flavour_s16_f16
18491 || flavour == neon_cvt_flavour_u16_f16
18492 || flavour == neon_cvt_flavour_f32_u32
18493 || flavour == neon_cvt_flavour_f32_s32
18494 || flavour == neon_cvt_flavour_s32_f32
18495 || flavour == neon_cvt_flavour_u32_f32))
18497 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
18500 else if (mode == neon_cvt_mode_n)
18502 /* We are dealing with vcvt with the 'ne' condition. */
18504 inst.instruction = N_MNEM_vcvt;
18505 do_neon_cvt_1 (neon_cvt_mode_z);
18508 /* fall through. */
18512 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18513 0x0000100, 0x1000100, 0x0, 0x1000000};
18515 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18516 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18519 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18521 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18522 _("immediate value out of range"));
18525 case neon_cvt_flavour_f16_s16:
18526 case neon_cvt_flavour_f16_u16:
18527 case neon_cvt_flavour_s16_f16:
18528 case neon_cvt_flavour_u16_f16:
18529 constraint (inst.operands[2].imm > 16,
18530 _("immediate value out of range"));
18532 case neon_cvt_flavour_f32_u32:
18533 case neon_cvt_flavour_f32_s32:
18534 case neon_cvt_flavour_s32_f32:
18535 case neon_cvt_flavour_u32_f32:
18536 constraint (inst.operands[2].imm > 32,
18537 _("immediate value out of range"));
18540 inst.error = BAD_FPU;
18545 /* Fixed-point conversion with #0 immediate is encoded as an
18546 integer conversion. */
18547 if (inst.operands[2].present && inst.operands[2].imm == 0)
18549 NEON_ENCODE (IMMED, inst);
18550 if (flavour != neon_cvt_flavour_invalid)
18551 inst.instruction |= enctab[flavour];
18552 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18553 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18554 inst.instruction |= LOW4 (inst.operands[1].reg);
18555 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18556 inst.instruction |= neon_quad (rs) << 6;
18557 inst.instruction |= 1 << 21;
18558 if (flavour < neon_cvt_flavour_s16_f16)
18560 inst.instruction |= 1 << 21;
18561 immbits = 32 - inst.operands[2].imm;
18562 inst.instruction |= immbits << 16;
18566 inst.instruction |= 3 << 20;
18567 immbits = 16 - inst.operands[2].imm;
18568 inst.instruction |= immbits << 16;
18569 inst.instruction &= ~(1 << 9);
18572 neon_dp_fixup (&inst);
18577 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
18578 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
18579 && (flavour == neon_cvt_flavour_s16_f16
18580 || flavour == neon_cvt_flavour_u16_f16
18581 || flavour == neon_cvt_flavour_s32_f32
18582 || flavour == neon_cvt_flavour_u32_f32))
18584 if (check_simd_pred_availability (1,
18585 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18588 else if (mode == neon_cvt_mode_z
18589 && (flavour == neon_cvt_flavour_f16_s16
18590 || flavour == neon_cvt_flavour_f16_u16
18591 || flavour == neon_cvt_flavour_s16_f16
18592 || flavour == neon_cvt_flavour_u16_f16
18593 || flavour == neon_cvt_flavour_f32_u32
18594 || flavour == neon_cvt_flavour_f32_s32
18595 || flavour == neon_cvt_flavour_s32_f32
18596 || flavour == neon_cvt_flavour_u32_f32))
18598 if (check_simd_pred_availability (1,
18599 NEON_CHECK_CC | NEON_CHECK_ARCH))
18602 /* fall through. */
18604 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
18607 NEON_ENCODE (FLOAT, inst);
18608 if (check_simd_pred_availability (1,
18609 NEON_CHECK_CC | NEON_CHECK_ARCH8))
18612 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18613 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18614 inst.instruction |= LOW4 (inst.operands[1].reg);
18615 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18616 inst.instruction |= neon_quad (rs) << 6;
18617 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
18618 || flavour == neon_cvt_flavour_u32_f32) << 7;
18619 inst.instruction |= mode << 8;
18620 if (flavour == neon_cvt_flavour_u16_f16
18621 || flavour == neon_cvt_flavour_s16_f16)
18622 /* Mask off the original size bits and reencode them. */
18623 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
18626 inst.instruction |= 0xfc000000;
18628 inst.instruction |= 0xf0000000;
18634 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
18635 0x100, 0x180, 0x0, 0x080};
18637 NEON_ENCODE (INTEGER, inst);
18639 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18641 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18645 if (flavour != neon_cvt_flavour_invalid)
18646 inst.instruction |= enctab[flavour];
18648 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18649 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18650 inst.instruction |= LOW4 (inst.operands[1].reg);
18651 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18652 inst.instruction |= neon_quad (rs) << 6;
18653 if (flavour >= neon_cvt_flavour_s16_f16
18654 && flavour <= neon_cvt_flavour_f16_u16)
18655 /* Half precision. */
18656 inst.instruction |= 1 << 18;
18658 inst.instruction |= 2 << 18;
18660 neon_dp_fixup (&inst);
18665 /* Half-precision conversions for Advanced SIMD -- neon. */
18668 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18672 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
18674 as_bad (_("operand size must match register width"));
18679 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
18681 as_bad (_("operand size must match register width"));
18686 inst.instruction = 0x3b60600;
18688 inst.instruction = 0x3b60700;
18690 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18691 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18692 inst.instruction |= LOW4 (inst.operands[1].reg);
18693 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18694 neon_dp_fixup (&inst);
18698 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18699 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18700 do_vfp_nsyn_cvt (rs, flavour);
18702 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18707 do_neon_cvtr (void)
18709 do_neon_cvt_1 (neon_cvt_mode_x);
18715 do_neon_cvt_1 (neon_cvt_mode_z);
18719 do_neon_cvta (void)
18721 do_neon_cvt_1 (neon_cvt_mode_a);
18725 do_neon_cvtn (void)
18727 do_neon_cvt_1 (neon_cvt_mode_n);
18731 do_neon_cvtp (void)
18733 do_neon_cvt_1 (neon_cvt_mode_p);
18737 do_neon_cvtm (void)
18739 do_neon_cvt_1 (neon_cvt_mode_m);
18743 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
18746 mark_feature_used (&fpu_vfp_ext_armv8);
18748 encode_arm_vfp_reg (inst.operands[0].reg,
18749 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
18750 encode_arm_vfp_reg (inst.operands[1].reg,
18751 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
18752 inst.instruction |= to ? 0x10000 : 0;
18753 inst.instruction |= t ? 0x80 : 0;
18754 inst.instruction |= is_double ? 0x100 : 0;
18755 do_vfp_cond_or_thumb ();
18759 do_neon_cvttb_1 (bfd_boolean t)
18761 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
18762 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
18766 else if (rs == NS_QQ || rs == NS_QQI)
18768 int single_to_half = 0;
18769 if (check_simd_pred_availability (1, NEON_CHECK_ARCH))
18772 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18774 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18775 && (flavour == neon_cvt_flavour_u16_f16
18776 || flavour == neon_cvt_flavour_s16_f16
18777 || flavour == neon_cvt_flavour_f16_s16
18778 || flavour == neon_cvt_flavour_f16_u16
18779 || flavour == neon_cvt_flavour_u32_f32
18780 || flavour == neon_cvt_flavour_s32_f32
18781 || flavour == neon_cvt_flavour_f32_s32
18782 || flavour == neon_cvt_flavour_f32_u32))
18785 inst.instruction = N_MNEM_vcvt;
18786 set_pred_insn_type (INSIDE_VPT_INSN);
18787 do_neon_cvt_1 (neon_cvt_mode_z);
18790 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
18791 single_to_half = 1;
18792 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
18794 first_error (BAD_FPU);
18798 inst.instruction = 0xee3f0e01;
18799 inst.instruction |= single_to_half << 28;
18800 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18801 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
18802 inst.instruction |= t << 12;
18803 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18804 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
18807 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
18810 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
18812 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
18815 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
18817 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
18819 /* The VCVTB and VCVTT instructions with D-register operands
18820 don't work for SP only targets. */
18821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18825 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
18827 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
18829 /* The VCVTB and VCVTT instructions with D-register operands
18830 don't work for SP only targets. */
18831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18835 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
18842 do_neon_cvtb (void)
18844 do_neon_cvttb_1 (FALSE);
18849 do_neon_cvtt (void)
18851 do_neon_cvttb_1 (TRUE);
18855 neon_move_immediate (void)
18857 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
18858 struct neon_type_el et = neon_check_type (2, rs,
18859 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
18860 unsigned immlo, immhi = 0, immbits;
18861 int op, cmode, float_p;
18863 constraint (et.type == NT_invtype,
18864 _("operand size must be specified for immediate VMOV"));
18866 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18867 op = (inst.instruction & (1 << 5)) != 0;
18869 immlo = inst.operands[1].imm;
18870 if (inst.operands[1].regisimm)
18871 immhi = inst.operands[1].reg;
18873 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
18874 _("immediate has bits set outside the operand size"));
18876 float_p = inst.operands[1].immisfloat;
18878 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
18879 et.size, et.type)) == FAIL)
18881 /* Invert relevant bits only. */
18882 neon_invert_size (&immlo, &immhi, et.size);
18883 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18884 with one or the other; those cases are caught by
18885 neon_cmode_for_move_imm. */
18887 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
18888 &op, et.size, et.type)) == FAIL)
18890 first_error (_("immediate out of range"));
18895 inst.instruction &= ~(1 << 5);
18896 inst.instruction |= op << 5;
18898 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18899 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18900 inst.instruction |= neon_quad (rs) << 6;
18901 inst.instruction |= cmode << 8;
18903 neon_write_immbits (immbits);
18909 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
18912 if (inst.operands[1].isreg)
18914 enum neon_shape rs;
18915 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18916 rs = neon_select_shape (NS_QQ, NS_NULL);
18918 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18920 NEON_ENCODE (INTEGER, inst);
18921 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18922 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18923 inst.instruction |= LOW4 (inst.operands[1].reg);
18924 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18925 inst.instruction |= neon_quad (rs) << 6;
18929 NEON_ENCODE (IMMED, inst);
18930 neon_move_immediate ();
18933 neon_dp_fixup (&inst);
18935 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18937 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
18938 constraint ((inst.instruction & 0xd00) == 0xd00,
18939 _("immediate value out of range"));
18943 /* Encode instructions of form:
18945 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18946 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18949 neon_mixed_length (struct neon_type_el et, unsigned size)
18951 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18952 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18953 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18954 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
18955 inst.instruction |= LOW4 (inst.operands[2].reg);
18956 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
18957 inst.instruction |= (et.type == NT_unsigned) << 24;
18958 inst.instruction |= neon_logbits (size) << 20;
18960 neon_dp_fixup (&inst);
18964 do_neon_dyadic_long (void)
18966 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
18969 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
18972 NEON_ENCODE (INTEGER, inst);
18973 /* FIXME: Type checking for lengthening op. */
18974 struct neon_type_el et = neon_check_type (3, NS_QDD,
18975 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
18976 neon_mixed_length (et, et.size);
18978 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18979 && (inst.cond == 0xf || inst.cond == 0x10))
18981 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18982 in an IT block with le/lt conditions. */
18984 if (inst.cond == 0xf)
18986 else if (inst.cond == 0x10)
18989 inst.pred_insn_type = INSIDE_IT_INSN;
18991 if (inst.instruction == N_MNEM_vaddl)
18993 inst.instruction = N_MNEM_vadd;
18994 do_neon_addsub_if_i ();
18996 else if (inst.instruction == N_MNEM_vsubl)
18998 inst.instruction = N_MNEM_vsub;
18999 do_neon_addsub_if_i ();
19001 else if (inst.instruction == N_MNEM_vabdl)
19003 inst.instruction = N_MNEM_vabd;
19004 do_neon_dyadic_if_su ();
19008 first_error (BAD_FPU);
19012 do_neon_abal (void)
19014 struct neon_type_el et = neon_check_type (3, NS_QDD,
19015 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19016 neon_mixed_length (et, et.size);
19020 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19022 if (inst.operands[2].isscalar)
19024 struct neon_type_el et = neon_check_type (3, NS_QDS,
19025 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
19026 NEON_ENCODE (SCALAR, inst);
19027 neon_mul_mac (et, et.type == NT_unsigned);
19031 struct neon_type_el et = neon_check_type (3, NS_QDD,
19032 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
19033 NEON_ENCODE (INTEGER, inst);
19034 neon_mixed_length (et, et.size);
19039 do_neon_mac_maybe_scalar_long (void)
19041 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19044 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19045 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19048 neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19050 unsigned regno = NEON_SCALAR_REG (scalar);
19051 unsigned elno = NEON_SCALAR_INDEX (scalar);
19055 if (regno > 7 || elno > 3)
19058 return ((regno & 0x7)
19059 | ((elno & 0x1) << 3)
19060 | (((elno >> 1) & 0x1) << 5));
19064 if (regno > 15 || elno > 1)
19067 return (((regno & 0x1) << 5)
19068 | ((regno >> 1) & 0x7)
19069 | ((elno & 0x1) << 3));
19073 first_error (_("scalar out of range for multiply instruction"));
19078 do_neon_fmac_maybe_scalar_long (int subtype)
19080 enum neon_shape rs;
19082 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19083 field (bits[21:20]) has different meaning. For scalar index variant, it's
19084 used to differentiate add and subtract, otherwise it's with fixed value
19088 if (inst.cond != COND_ALWAYS)
19089 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19090 "behaviour is UNPREDICTABLE"));
19092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
19095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19098 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19099 be a scalar index register. */
19100 if (inst.operands[2].isscalar)
19102 high8 = 0xfe000000;
19105 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19109 high8 = 0xfc000000;
19112 inst.instruction |= (0x1 << 23);
19113 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19116 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
19118 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19119 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19120 so we simply pass -1 as size. */
19121 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19122 neon_three_same (quad_p, 0, size);
19124 /* Undo neon_dp_fixup. Redo the high eight bits. */
19125 inst.instruction &= 0x00ffffff;
19126 inst.instruction |= high8;
19128 #define LOW1(R) ((R) & 0x1)
19129 #define HI4(R) (((R) >> 1) & 0xf)
19130 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19131 whether the instruction is in Q form and whether Vm is a scalar indexed
19133 if (inst.operands[2].isscalar)
19136 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19137 inst.instruction &= 0xffffffd0;
19138 inst.instruction |= rm;
19142 /* Redo Rn as well. */
19143 inst.instruction &= 0xfff0ff7f;
19144 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19145 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19150 /* Redo Rn and Rm. */
19151 inst.instruction &= 0xfff0ff50;
19152 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19153 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19154 inst.instruction |= HI4 (inst.operands[2].reg);
19155 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19160 do_neon_vfmal (void)
19162 return do_neon_fmac_maybe_scalar_long (0);
19166 do_neon_vfmsl (void)
19168 return do_neon_fmac_maybe_scalar_long (1);
19172 do_neon_dyadic_wide (void)
19174 struct neon_type_el et = neon_check_type (3, NS_QQD,
19175 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19176 neon_mixed_length (et, et.size);
19180 do_neon_dyadic_narrow (void)
19182 struct neon_type_el et = neon_check_type (3, NS_QDD,
19183 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
19184 /* Operand sign is unimportant, and the U bit is part of the opcode,
19185 so force the operand type to integer. */
19186 et.type = NT_integer;
19187 neon_mixed_length (et, et.size / 2);
19191 do_neon_mul_sat_scalar_long (void)
19193 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19197 do_neon_vmull (void)
19199 if (inst.operands[2].isscalar)
19200 do_neon_mac_maybe_scalar_long ();
19203 struct neon_type_el et = neon_check_type (3, NS_QDD,
19204 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
19206 if (et.type == NT_poly)
19207 NEON_ENCODE (POLY, inst);
19209 NEON_ENCODE (INTEGER, inst);
19211 /* For polynomial encoding the U bit must be zero, and the size must
19212 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19213 obviously, as 0b10). */
19216 /* Check we're on the correct architecture. */
19217 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19219 _("Instruction form not available on this architecture.");
19224 neon_mixed_length (et, et.size);
19231 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
19232 struct neon_type_el et = neon_check_type (3, rs,
19233 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19234 unsigned imm = (inst.operands[3].imm * et.size) / 8;
19236 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19237 _("shift out of range"));
19238 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19239 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19240 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19241 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19242 inst.instruction |= LOW4 (inst.operands[2].reg);
19243 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19244 inst.instruction |= neon_quad (rs) << 6;
19245 inst.instruction |= imm << 8;
19247 neon_dp_fixup (&inst);
19253 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19256 enum neon_shape rs;
19257 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19258 rs = neon_select_shape (NS_QQ, NS_NULL);
19260 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19262 struct neon_type_el et = neon_check_type (2, rs,
19263 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19265 unsigned op = (inst.instruction >> 7) & 3;
19266 /* N (width of reversed regions) is encoded as part of the bitmask. We
19267 extract it here to check the elements to be reversed are smaller.
19268 Otherwise we'd get a reserved instruction. */
19269 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
19271 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19272 && inst.operands[0].reg == inst.operands[1].reg)
19273 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19274 " operands makes instruction UNPREDICTABLE"));
19276 gas_assert (elsize != 0);
19277 constraint (et.size >= elsize,
19278 _("elements must be smaller than reversal region"));
19279 neon_two_same (neon_quad (rs), 1, et.size);
19285 if (inst.operands[1].isscalar)
19287 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19289 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
19290 struct neon_type_el et = neon_check_type (2, rs,
19291 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19292 unsigned sizebits = et.size >> 3;
19293 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
19294 int logsize = neon_logbits (et.size);
19295 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
19297 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
19300 NEON_ENCODE (SCALAR, inst);
19301 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19302 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19303 inst.instruction |= LOW4 (dm);
19304 inst.instruction |= HI1 (dm) << 5;
19305 inst.instruction |= neon_quad (rs) << 6;
19306 inst.instruction |= x << 17;
19307 inst.instruction |= sizebits << 16;
19309 neon_dp_fixup (&inst);
19313 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19314 struct neon_type_el et = neon_check_type (2, rs,
19315 N_8 | N_16 | N_32 | N_KEY, N_EQK);
19318 if (check_simd_pred_availability (0, NEON_CHECK_ARCH))
19322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19325 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19327 if (inst.operands[1].reg == REG_SP)
19328 as_tsktsk (MVE_BAD_SP);
19329 else if (inst.operands[1].reg == REG_PC)
19330 as_tsktsk (MVE_BAD_PC);
19333 /* Duplicate ARM register to lanes of vector. */
19334 NEON_ENCODE (ARMREG, inst);
19337 case 8: inst.instruction |= 0x400000; break;
19338 case 16: inst.instruction |= 0x000020; break;
19339 case 32: inst.instruction |= 0x000000; break;
19342 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19343 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19344 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
19345 inst.instruction |= neon_quad (rs) << 21;
19346 /* The encoding for this instruction is identical for the ARM and Thumb
19347 variants, except for the condition field. */
19348 do_vfp_cond_or_thumb ();
19353 do_mve_mov (int toQ)
19355 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19357 if (inst.cond > COND_ALWAYS)
19358 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19360 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19369 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19370 _("Index one must be [2,3] and index two must be two less than"
19372 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
19373 _("General purpose registers may not be the same"));
19374 constraint (inst.operands[Rt].reg == REG_SP
19375 || inst.operands[Rt2].reg == REG_SP,
19377 constraint (inst.operands[Rt].reg == REG_PC
19378 || inst.operands[Rt2].reg == REG_PC,
19381 inst.instruction = 0xec000f00;
19382 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19383 inst.instruction |= !!toQ << 20;
19384 inst.instruction |= inst.operands[Rt2].reg << 16;
19385 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19386 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19387 inst.instruction |= inst.operands[Rt].reg;
19393 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19396 if (inst.cond > COND_ALWAYS)
19397 inst.pred_insn_type = INSIDE_VPT_INSN;
19399 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19401 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
19404 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19405 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19406 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19407 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19408 inst.instruction |= LOW4 (inst.operands[1].reg);
19413 /* VMOV has particularly many variations. It can be one of:
19414 0. VMOV<c><q> <Qd>, <Qm>
19415 1. VMOV<c><q> <Dd>, <Dm>
19416 (Register operations, which are VORR with Rm = Rn.)
19417 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19418 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19420 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19421 (ARM register to scalar.)
19422 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19423 (Two ARM registers to vector.)
19424 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19425 (Scalar to ARM register.)
19426 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19427 (Vector to two ARM registers.)
19428 8. VMOV.F32 <Sd>, <Sm>
19429 9. VMOV.F64 <Dd>, <Dm>
19430 (VFP register moves.)
19431 10. VMOV.F32 <Sd>, #imm
19432 11. VMOV.F64 <Dd>, #imm
19433 (VFP float immediate load.)
19434 12. VMOV <Rd>, <Sm>
19435 (VFP single to ARM reg.)
19436 13. VMOV <Sd>, <Rm>
19437 (ARM reg to VFP single.)
19438 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19439 (Two ARM regs to two VFP singles.)
19440 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19441 (Two VFP singles to two ARM regs.)
19442 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19443 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19444 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19445 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19447 These cases can be disambiguated using neon_select_shape, except cases 1/9
19448 and 3/11 which depend on the operand type too.
19450 All the encoded bits are hardcoded by this function.
19452 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19453 Cases 5, 7 may be used with VFPv2 and above.
19455 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19456 can specify a type where it doesn't make sense to, and is ignored). */
19461 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
19462 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
19463 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
19464 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
19466 struct neon_type_el et;
19467 const char *ldconst = 0;
19471 case NS_DD: /* case 1/9. */
19472 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19473 /* It is not an error here if no type is given. */
19475 if (et.type == NT_float && et.size == 64)
19477 do_vfp_nsyn_opcode ("fcpyd");
19480 /* fall through. */
19482 case NS_QQ: /* case 0/1. */
19484 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
19486 /* The architecture manual I have doesn't explicitly state which
19487 value the U bit should have for register->register moves, but
19488 the equivalent VORR instruction has U = 0, so do that. */
19489 inst.instruction = 0x0200110;
19490 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19491 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19492 inst.instruction |= LOW4 (inst.operands[1].reg);
19493 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19494 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19495 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19496 inst.instruction |= neon_quad (rs) << 6;
19498 neon_dp_fixup (&inst);
19502 case NS_DI: /* case 3/11. */
19503 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19505 if (et.type == NT_float && et.size == 64)
19507 /* case 11 (fconstd). */
19508 ldconst = "fconstd";
19509 goto encode_fconstd;
19511 /* fall through. */
19513 case NS_QI: /* case 2/3. */
19514 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
19516 inst.instruction = 0x0800010;
19517 neon_move_immediate ();
19518 neon_dp_fixup (&inst);
19521 case NS_SR: /* case 4. */
19523 unsigned bcdebits = 0;
19525 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19526 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
19528 /* .<size> is optional here, defaulting to .32. */
19529 if (inst.vectype.elems == 0
19530 && inst.operands[0].vectype.type == NT_invtype
19531 && inst.operands[1].vectype.type == NT_invtype)
19533 inst.vectype.el[0].type = NT_untyped;
19534 inst.vectype.el[0].size = 32;
19535 inst.vectype.elems = 1;
19538 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
19539 logsize = neon_logbits (et.size);
19543 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19544 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
19549 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19550 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19554 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19556 if (inst.operands[1].reg == REG_SP)
19557 as_tsktsk (MVE_BAD_SP);
19558 else if (inst.operands[1].reg == REG_PC)
19559 as_tsktsk (MVE_BAD_PC);
19561 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19563 constraint (et.type == NT_invtype, _("bad type for scalar"));
19564 constraint (x >= size / et.size, _("scalar index out of range"));
19569 case 8: bcdebits = 0x8; break;
19570 case 16: bcdebits = 0x1; break;
19571 case 32: bcdebits = 0x0; break;
19575 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19577 inst.instruction = 0xe000b10;
19578 do_vfp_cond_or_thumb ();
19579 inst.instruction |= LOW4 (dn) << 16;
19580 inst.instruction |= HI1 (dn) << 7;
19581 inst.instruction |= inst.operands[1].reg << 12;
19582 inst.instruction |= (bcdebits & 3) << 5;
19583 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
19584 inst.instruction |= (x >> (3-logsize)) << 16;
19588 case NS_DRR: /* case 5 (fmdrr). */
19589 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19590 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19593 inst.instruction = 0xc400b10;
19594 do_vfp_cond_or_thumb ();
19595 inst.instruction |= LOW4 (inst.operands[0].reg);
19596 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
19597 inst.instruction |= inst.operands[1].reg << 12;
19598 inst.instruction |= inst.operands[2].reg << 16;
19601 case NS_RS: /* case 6. */
19604 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
19605 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
19606 unsigned abcdebits = 0;
19608 /* .<dt> is optional here, defaulting to .32. */
19609 if (inst.vectype.elems == 0
19610 && inst.operands[0].vectype.type == NT_invtype
19611 && inst.operands[1].vectype.type == NT_invtype)
19613 inst.vectype.el[0].type = NT_untyped;
19614 inst.vectype.el[0].size = 32;
19615 inst.vectype.elems = 1;
19618 et = neon_check_type (2, NS_NULL,
19619 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
19620 logsize = neon_logbits (et.size);
19624 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19625 && vfp_or_neon_is_neon (NEON_CHECK_CC
19626 | NEON_CHECK_ARCH) == FAIL)
19631 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19632 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19636 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19638 if (inst.operands[0].reg == REG_SP)
19639 as_tsktsk (MVE_BAD_SP);
19640 else if (inst.operands[0].reg == REG_PC)
19641 as_tsktsk (MVE_BAD_PC);
19644 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
19646 constraint (et.type == NT_invtype, _("bad type for scalar"));
19647 constraint (x >= size / et.size, _("scalar index out of range"));
19651 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
19652 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
19653 case 32: abcdebits = 0x00; break;
19657 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
19658 inst.instruction = 0xe100b10;
19659 do_vfp_cond_or_thumb ();
19660 inst.instruction |= LOW4 (dn) << 16;
19661 inst.instruction |= HI1 (dn) << 7;
19662 inst.instruction |= inst.operands[0].reg << 12;
19663 inst.instruction |= (abcdebits & 3) << 5;
19664 inst.instruction |= (abcdebits >> 2) << 21;
19665 inst.instruction |= (x >> (3-logsize)) << 16;
19669 case NS_RRD: /* case 7 (fmrrd). */
19670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19671 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19674 inst.instruction = 0xc500b10;
19675 do_vfp_cond_or_thumb ();
19676 inst.instruction |= inst.operands[0].reg << 12;
19677 inst.instruction |= inst.operands[1].reg << 16;
19678 inst.instruction |= LOW4 (inst.operands[2].reg);
19679 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19682 case NS_FF: /* case 8 (fcpys). */
19683 do_vfp_nsyn_opcode ("fcpys");
19687 case NS_FI: /* case 10 (fconsts). */
19688 ldconst = "fconsts";
19690 if (!inst.operands[1].immisfloat)
19693 /* Immediate has to fit in 8 bits so float is enough. */
19694 float imm = (float) inst.operands[1].imm;
19695 memcpy (&new_imm, &imm, sizeof (float));
19696 /* But the assembly may have been written to provide an integer
19697 bit pattern that equates to a float, so check that the
19698 conversion has worked. */
19699 if (is_quarter_float (new_imm))
19701 if (is_quarter_float (inst.operands[1].imm))
19702 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19704 inst.operands[1].imm = new_imm;
19705 inst.operands[1].immisfloat = 1;
19709 if (is_quarter_float (inst.operands[1].imm))
19711 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
19712 do_vfp_nsyn_opcode (ldconst);
19714 /* ARMv8.2 fp16 vmov.f16 instruction. */
19716 do_scalar_fp16_v82_encode ();
19719 first_error (_("immediate out of range"));
19723 case NS_RF: /* case 12 (fmrs). */
19724 do_vfp_nsyn_opcode ("fmrs");
19725 /* ARMv8.2 fp16 vmov.f16 instruction. */
19727 do_scalar_fp16_v82_encode ();
19731 case NS_FR: /* case 13 (fmsr). */
19732 do_vfp_nsyn_opcode ("fmsr");
19733 /* ARMv8.2 fp16 vmov.f16 instruction. */
19735 do_scalar_fp16_v82_encode ();
19745 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19746 (one of which is a list), but we have parsed four. Do some fiddling to
19747 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19749 case NS_RRFF: /* case 14 (fmrrs). */
19750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19751 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19753 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
19754 _("VFP registers must be adjacent"));
19755 inst.operands[2].imm = 2;
19756 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19757 do_vfp_nsyn_opcode ("fmrrs");
19760 case NS_FFRR: /* case 15 (fmsrr). */
19761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19762 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19764 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
19765 _("VFP registers must be adjacent"));
19766 inst.operands[1] = inst.operands[2];
19767 inst.operands[2] = inst.operands[3];
19768 inst.operands[0].imm = 2;
19769 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
19770 do_vfp_nsyn_opcode ("fmsrr");
19774 /* neon_select_shape has determined that the instruction
19775 shape is wrong and has already set the error message. */
19786 if (!(inst.operands[0].present && inst.operands[0].isquad
19787 && inst.operands[1].present && inst.operands[1].isquad
19788 && !inst.operands[2].present))
19790 inst.instruction = 0;
19793 set_pred_insn_type (INSIDE_IT_INSN);
19798 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19801 if (inst.cond != COND_ALWAYS)
19802 inst.pred_insn_type = INSIDE_VPT_INSN;
19804 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
19805 | N_S16 | N_U16 | N_KEY);
19807 inst.instruction |= (et.type == NT_unsigned) << 28;
19808 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19809 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
19810 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19811 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19812 inst.instruction |= LOW4 (inst.operands[1].reg);
19817 do_neon_rshift_round_imm (void)
19819 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19822 enum neon_shape rs;
19823 struct neon_type_el et;
19825 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19827 rs = neon_select_shape (NS_QQI, NS_NULL);
19828 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
19832 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
19833 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
19835 int imm = inst.operands[2].imm;
19837 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19840 inst.operands[2].present = 0;
19845 constraint (imm < 1 || (unsigned)imm > et.size,
19846 _("immediate out of range for shift"));
19847 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
19852 do_neon_movhf (void)
19854 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
19855 constraint (rs != NS_HH, _("invalid suffix"));
19857 if (inst.cond != COND_ALWAYS)
19861 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19862 " the behaviour is UNPREDICTABLE"));
19866 inst.error = BAD_COND;
19871 do_vfp_sp_monadic ();
19874 inst.instruction |= 0xf0000000;
19878 do_neon_movl (void)
19880 struct neon_type_el et = neon_check_type (2, NS_QD,
19881 N_EQK | N_DBL, N_SU_32 | N_KEY);
19882 unsigned sizebits = et.size >> 3;
19883 inst.instruction |= sizebits << 19;
19884 neon_two_same (0, et.type == NT_unsigned, -1);
19890 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19891 struct neon_type_el et = neon_check_type (2, rs,
19892 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19893 NEON_ENCODE (INTEGER, inst);
19894 neon_two_same (neon_quad (rs), 1, et.size);
19898 do_neon_zip_uzp (void)
19900 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19901 struct neon_type_el et = neon_check_type (2, rs,
19902 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19903 if (rs == NS_DD && et.size == 32)
19905 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19906 inst.instruction = N_MNEM_vtrn;
19910 neon_two_same (neon_quad (rs), 1, et.size);
19914 do_neon_sat_abs_neg (void)
19916 if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
19919 enum neon_shape rs;
19920 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19921 rs = neon_select_shape (NS_QQ, NS_NULL);
19923 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19924 struct neon_type_el et = neon_check_type (2, rs,
19925 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19926 neon_two_same (neon_quad (rs), 1, et.size);
19930 do_neon_pair_long (void)
19932 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19933 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
19934 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19935 inst.instruction |= (et.type == NT_unsigned) << 7;
19936 neon_two_same (neon_quad (rs), 1, et.size);
19940 do_neon_recip_est (void)
19942 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19943 struct neon_type_el et = neon_check_type (2, rs,
19944 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
19945 inst.instruction |= (et.type == NT_float) << 8;
19946 neon_two_same (neon_quad (rs), 1, et.size);
19952 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19955 enum neon_shape rs;
19956 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19957 rs = neon_select_shape (NS_QQ, NS_NULL);
19959 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19961 struct neon_type_el et = neon_check_type (2, rs,
19962 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
19963 neon_two_same (neon_quad (rs), 1, et.size);
19969 if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
19972 enum neon_shape rs;
19973 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19974 rs = neon_select_shape (NS_QQ, NS_NULL);
19976 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19978 struct neon_type_el et = neon_check_type (2, rs,
19979 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
19980 neon_two_same (neon_quad (rs), 1, et.size);
19986 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19987 struct neon_type_el et = neon_check_type (2, rs,
19988 N_EQK | N_INT, N_8 | N_KEY);
19989 neon_two_same (neon_quad (rs), 1, et.size);
19995 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19996 neon_two_same (neon_quad (rs), 1, -1);
20000 do_neon_tbl_tbx (void)
20002 unsigned listlenbits;
20003 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
20005 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20007 first_error (_("bad list length for table lookup"));
20011 listlenbits = inst.operands[1].imm - 1;
20012 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20013 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20014 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20015 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20016 inst.instruction |= LOW4 (inst.operands[2].reg);
20017 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20018 inst.instruction |= listlenbits << 8;
20020 neon_dp_fixup (&inst);
20024 do_neon_ldm_stm (void)
20026 /* P, U and L bits are part of bitmask. */
20027 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20028 unsigned offsetbits = inst.operands[1].imm * 2;
20030 if (inst.operands[1].issingle)
20032 do_vfp_nsyn_ldm_stm (is_dbmode);
20036 constraint (is_dbmode && !inst.operands[0].writeback,
20037 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20039 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20040 _("register list must contain at least 1 and at most 16 "
20043 inst.instruction |= inst.operands[0].reg << 16;
20044 inst.instruction |= inst.operands[0].writeback << 21;
20045 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20046 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20048 inst.instruction |= offsetbits;
20050 do_vfp_cond_or_thumb ();
20054 do_neon_ldr_str (void)
20056 int is_ldr = (inst.instruction & (1 << 20)) != 0;
20058 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20059 And is UNPREDICTABLE in thumb mode. */
20061 && inst.operands[1].reg == REG_PC
20062 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
20065 inst.error = _("Use of PC here is UNPREDICTABLE");
20066 else if (warn_on_deprecated)
20067 as_tsktsk (_("Use of PC here is deprecated"));
20070 if (inst.operands[0].issingle)
20073 do_vfp_nsyn_opcode ("flds");
20075 do_vfp_nsyn_opcode ("fsts");
20077 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20078 if (inst.vectype.el[0].size == 16)
20079 do_scalar_fp16_v82_encode ();
20084 do_vfp_nsyn_opcode ("fldd");
20086 do_vfp_nsyn_opcode ("fstd");
20091 do_t_vldr_vstr_sysreg (void)
20093 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20094 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20096 /* Use of PC is UNPREDICTABLE. */
20097 if (inst.operands[1].reg == REG_PC)
20098 inst.error = _("Use of PC here is UNPREDICTABLE");
20100 if (inst.operands[1].immisreg)
20101 inst.error = _("instruction does not accept register index");
20103 if (!inst.operands[1].isreg)
20104 inst.error = _("instruction does not accept PC-relative addressing");
20106 if (abs (inst.operands[1].imm) >= (1 << 7))
20107 inst.error = _("immediate value out of range");
20109 inst.instruction = 0xec000f80;
20111 inst.instruction |= 1 << sysreg_vldr_bitno;
20112 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20113 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20114 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20118 do_vldr_vstr (void)
20120 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20122 /* VLDR/VSTR (System Register). */
20125 if (!mark_feature_used (&arm_ext_v8_1m_main))
20126 as_bad (_("Instruction not permitted on this architecture"));
20128 do_t_vldr_vstr_sysreg ();
20133 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
20134 as_bad (_("Instruction not permitted on this architecture"));
20135 do_neon_ldr_str ();
20139 /* "interleave" version also handles non-interleaving register VLD1/VST1
20143 do_neon_ld_st_interleave (void)
20145 struct neon_type_el et = neon_check_type (1, NS_NULL,
20146 N_8 | N_16 | N_32 | N_64);
20147 unsigned alignbits = 0;
20149 /* The bits in this table go:
20150 0: register stride of one (0) or two (1)
20151 1,2: register list length, minus one (1, 2, 3, 4).
20152 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20153 We use -1 for invalid entries. */
20154 const int typetable[] =
20156 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20157 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20158 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20159 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20163 if (et.type == NT_invtype)
20166 if (inst.operands[1].immisalign)
20167 switch (inst.operands[1].imm >> 8)
20169 case 64: alignbits = 1; break;
20171 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
20172 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20173 goto bad_alignment;
20177 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20178 goto bad_alignment;
20183 first_error (_("bad alignment"));
20187 inst.instruction |= alignbits << 4;
20188 inst.instruction |= neon_logbits (et.size) << 6;
20190 /* Bits [4:6] of the immediate in a list specifier encode register stride
20191 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20192 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20193 up the right value for "type" in a table based on this value and the given
20194 list style, then stick it back. */
20195 idx = ((inst.operands[0].imm >> 4) & 7)
20196 | (((inst.instruction >> 8) & 3) << 3);
20198 typebits = typetable[idx];
20200 constraint (typebits == -1, _("bad list type for instruction"));
20201 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
20204 inst.instruction &= ~0xf00;
20205 inst.instruction |= typebits << 8;
20208 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20209 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20210 otherwise. The variable arguments are a list of pairs of legal (size, align)
20211 values, terminated with -1. */
20214 neon_alignment_bit (int size, int align, int *do_alignment, ...)
20217 int result = FAIL, thissize, thisalign;
20219 if (!inst.operands[1].immisalign)
20225 va_start (ap, do_alignment);
20229 thissize = va_arg (ap, int);
20230 if (thissize == -1)
20232 thisalign = va_arg (ap, int);
20234 if (size == thissize && align == thisalign)
20237 while (result != SUCCESS);
20241 if (result == SUCCESS)
20244 first_error (_("unsupported alignment for instruction"));
20250 do_neon_ld_st_lane (void)
20252 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
20253 int align_good, do_alignment = 0;
20254 int logsize = neon_logbits (et.size);
20255 int align = inst.operands[1].imm >> 8;
20256 int n = (inst.instruction >> 8) & 3;
20257 int max_el = 64 / et.size;
20259 if (et.type == NT_invtype)
20262 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
20263 _("bad list length"));
20264 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
20265 _("scalar index out of range"));
20266 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
20268 _("stride of 2 unavailable when element size is 8"));
20272 case 0: /* VLD1 / VST1. */
20273 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
20275 if (align_good == FAIL)
20279 unsigned alignbits = 0;
20282 case 16: alignbits = 0x1; break;
20283 case 32: alignbits = 0x3; break;
20286 inst.instruction |= alignbits << 4;
20290 case 1: /* VLD2 / VST2. */
20291 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20292 16, 32, 32, 64, -1);
20293 if (align_good == FAIL)
20296 inst.instruction |= 1 << 4;
20299 case 2: /* VLD3 / VST3. */
20300 constraint (inst.operands[1].immisalign,
20301 _("can't use alignment with this instruction"));
20304 case 3: /* VLD4 / VST4. */
20305 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
20306 16, 64, 32, 64, 32, 128, -1);
20307 if (align_good == FAIL)
20311 unsigned alignbits = 0;
20314 case 8: alignbits = 0x1; break;
20315 case 16: alignbits = 0x1; break;
20316 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
20319 inst.instruction |= alignbits << 4;
20326 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20327 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20328 inst.instruction |= 1 << (4 + logsize);
20330 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20331 inst.instruction |= logsize << 10;
20334 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20337 do_neon_ld_dup (void)
20339 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
20340 int align_good, do_alignment = 0;
20342 if (et.type == NT_invtype)
20345 switch ((inst.instruction >> 8) & 3)
20347 case 0: /* VLD1. */
20348 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
20349 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20350 &do_alignment, 16, 16, 32, 32, -1);
20351 if (align_good == FAIL)
20353 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
20356 case 2: inst.instruction |= 1 << 5; break;
20357 default: first_error (_("bad list length")); return;
20359 inst.instruction |= neon_logbits (et.size) << 6;
20362 case 1: /* VLD2. */
20363 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20364 &do_alignment, 8, 16, 16, 32, 32, 64,
20366 if (align_good == FAIL)
20368 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
20369 _("bad list length"));
20370 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20371 inst.instruction |= 1 << 5;
20372 inst.instruction |= neon_logbits (et.size) << 6;
20375 case 2: /* VLD3. */
20376 constraint (inst.operands[1].immisalign,
20377 _("can't use alignment with this instruction"));
20378 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
20379 _("bad list length"));
20380 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20381 inst.instruction |= 1 << 5;
20382 inst.instruction |= neon_logbits (et.size) << 6;
20385 case 3: /* VLD4. */
20387 int align = inst.operands[1].imm >> 8;
20388 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
20389 16, 64, 32, 64, 32, 128, -1);
20390 if (align_good == FAIL)
20392 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20393 _("bad list length"));
20394 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20395 inst.instruction |= 1 << 5;
20396 if (et.size == 32 && align == 128)
20397 inst.instruction |= 0x3 << 6;
20399 inst.instruction |= neon_logbits (et.size) << 6;
20406 inst.instruction |= do_alignment << 4;
20409 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20410 apart from bits [11:4]. */
20413 do_neon_ldx_stx (void)
20415 if (inst.operands[1].isreg)
20416 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20418 switch (NEON_LANE (inst.operands[0].imm))
20420 case NEON_INTERLEAVE_LANES:
20421 NEON_ENCODE (INTERLV, inst);
20422 do_neon_ld_st_interleave ();
20425 case NEON_ALL_LANES:
20426 NEON_ENCODE (DUP, inst);
20427 if (inst.instruction == N_INV)
20429 first_error ("only loads support such operands");
20436 NEON_ENCODE (LANE, inst);
20437 do_neon_ld_st_lane ();
20440 /* L bit comes from bit mask. */
20441 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20442 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20443 inst.instruction |= inst.operands[1].reg << 16;
20445 if (inst.operands[1].postind)
20447 int postreg = inst.operands[1].imm & 0xf;
20448 constraint (!inst.operands[1].immisreg,
20449 _("post-index must be a register"));
20450 constraint (postreg == 0xd || postreg == 0xf,
20451 _("bad register for post-index"));
20452 inst.instruction |= postreg;
20456 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
20457 constraint (inst.relocs[0].exp.X_op != O_constant
20458 || inst.relocs[0].exp.X_add_number != 0,
20461 if (inst.operands[1].writeback)
20463 inst.instruction |= 0xd;
20466 inst.instruction |= 0xf;
20470 inst.instruction |= 0xf9000000;
20472 inst.instruction |= 0xf4000000;
20477 do_vfp_nsyn_fpv8 (enum neon_shape rs)
20479 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20480 D register operands. */
20481 if (neon_shape_class[rs] == SC_DOUBLE)
20482 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20485 NEON_ENCODE (FPV8, inst);
20487 if (rs == NS_FFF || rs == NS_HHH)
20489 do_vfp_sp_dyadic ();
20491 /* ARMv8.2 fp16 instruction. */
20493 do_scalar_fp16_v82_encode ();
20496 do_vfp_dp_rd_rn_rm ();
20499 inst.instruction |= 0x100;
20501 inst.instruction |= 0xf0000000;
20507 set_pred_insn_type (OUTSIDE_PRED_INSN);
20509 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
20510 first_error (_("invalid instruction shape"));
20516 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20517 set_pred_insn_type (OUTSIDE_PRED_INSN);
20519 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
20522 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
20525 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
20529 do_vrint_1 (enum neon_cvt_mode mode)
20531 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
20532 struct neon_type_el et;
20537 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20538 D register operands. */
20539 if (neon_shape_class[rs] == SC_DOUBLE)
20540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20543 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
20545 if (et.type != NT_invtype)
20547 /* VFP encodings. */
20548 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
20549 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
20550 set_pred_insn_type (OUTSIDE_PRED_INSN);
20552 NEON_ENCODE (FPV8, inst);
20553 if (rs == NS_FF || rs == NS_HH)
20554 do_vfp_sp_monadic ();
20556 do_vfp_dp_rd_rm ();
20560 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
20561 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
20562 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
20563 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
20564 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
20565 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
20566 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
20570 inst.instruction |= (rs == NS_DD) << 8;
20571 do_vfp_cond_or_thumb ();
20573 /* ARMv8.2 fp16 vrint instruction. */
20575 do_scalar_fp16_v82_encode ();
20579 /* Neon encodings (or something broken...). */
20581 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
20583 if (et.type == NT_invtype)
20586 if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
20589 NEON_ENCODE (FLOAT, inst);
20591 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20592 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20593 inst.instruction |= LOW4 (inst.operands[1].reg);
20594 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20595 inst.instruction |= neon_quad (rs) << 6;
20596 /* Mask off the original size bits and reencode them. */
20597 inst.instruction = ((inst.instruction & 0xfff3ffff)
20598 | neon_logbits (et.size) << 18);
20602 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
20603 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
20604 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
20605 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
20606 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
20607 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
20608 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
20613 inst.instruction |= 0xfc000000;
20615 inst.instruction |= 0xf0000000;
20622 do_vrint_1 (neon_cvt_mode_x);
20628 do_vrint_1 (neon_cvt_mode_z);
20634 do_vrint_1 (neon_cvt_mode_r);
20640 do_vrint_1 (neon_cvt_mode_a);
20646 do_vrint_1 (neon_cvt_mode_n);
20652 do_vrint_1 (neon_cvt_mode_p);
20658 do_vrint_1 (neon_cvt_mode_m);
20662 neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
20664 unsigned regno = NEON_SCALAR_REG (opnd);
20665 unsigned elno = NEON_SCALAR_INDEX (opnd);
20667 if (elsize == 16 && elno < 2 && regno < 16)
20668 return regno | (elno << 4);
20669 else if (elsize == 32 && elno == 0)
20672 first_error (_("scalar out of range"));
20679 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
20680 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20681 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20682 constraint (inst.relocs[0].exp.X_op != O_constant,
20683 _("expression too complex"));
20684 unsigned rot = inst.relocs[0].exp.X_add_number;
20685 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
20686 _("immediate out of range"));
20689 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC))
20692 if (inst.operands[2].isscalar)
20694 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20695 first_error (_("invalid instruction shape"));
20696 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
20697 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20698 N_KEY | N_F16 | N_F32).size;
20699 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
20701 inst.instruction = 0xfe000800;
20702 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20703 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20704 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20705 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20706 inst.instruction |= LOW4 (m);
20707 inst.instruction |= HI1 (m) << 5;
20708 inst.instruction |= neon_quad (rs) << 6;
20709 inst.instruction |= rot << 20;
20710 inst.instruction |= (size == 32) << 23;
20714 enum neon_shape rs;
20715 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
20716 rs = neon_select_shape (NS_QQQI, NS_NULL);
20718 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20720 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
20721 N_KEY | N_F16 | N_F32).size;
20722 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
20723 && (inst.operands[0].reg == inst.operands[1].reg
20724 || inst.operands[0].reg == inst.operands[2].reg))
20725 as_tsktsk (BAD_MVE_SRCDEST);
20727 neon_three_same (neon_quad (rs), 0, -1);
20728 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20729 inst.instruction |= 0xfc200800;
20730 inst.instruction |= rot << 23;
20731 inst.instruction |= (size == 32) << 20;
20738 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20739 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
20740 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
20741 constraint (inst.relocs[0].exp.X_op != O_constant,
20742 _("expression too complex"));
20744 unsigned rot = inst.relocs[0].exp.X_add_number;
20745 constraint (rot != 90 && rot != 270, _("immediate out of range"));
20746 enum neon_shape rs;
20747 struct neon_type_el et;
20748 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20750 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
20751 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
20755 rs = neon_select_shape (NS_QQQI, NS_NULL);
20756 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
20758 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
20759 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20760 "operand makes instruction UNPREDICTABLE"));
20763 if (et.type == NT_invtype)
20766 if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8
20770 if (et.type == NT_float)
20772 neon_three_same (neon_quad (rs), 0, -1);
20773 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
20774 inst.instruction |= 0xfc800800;
20775 inst.instruction |= (rot == 270) << 24;
20776 inst.instruction |= (et.size == 32) << 20;
20780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
20781 inst.instruction = 0xfe000f00;
20782 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20783 inst.instruction |= neon_logbits (et.size) << 20;
20784 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20785 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20786 inst.instruction |= (rot == 270) << 12;
20787 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20788 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20789 inst.instruction |= LOW4 (inst.operands[2].reg);
20794 /* Dot Product instructions encoding support. */
20797 do_neon_dotproduct (int unsigned_p)
20799 enum neon_shape rs;
20800 unsigned scalar_oprd2 = 0;
20803 if (inst.cond != COND_ALWAYS)
20804 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20805 "is UNPREDICTABLE"));
20807 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
20810 /* Dot Product instructions are in three-same D/Q register format or the third
20811 operand can be a scalar index register. */
20812 if (inst.operands[2].isscalar)
20814 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
20815 high8 = 0xfe000000;
20816 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
20820 high8 = 0xfc000000;
20821 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
20825 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
20827 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
20829 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20830 Product instruction, so we pass 0 as the "ubit" parameter. And the
20831 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20832 neon_three_same (neon_quad (rs), 0, 32);
20834 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20835 different NEON three-same encoding. */
20836 inst.instruction &= 0x00ffffff;
20837 inst.instruction |= high8;
20838 /* Encode 'U' bit which indicates signedness. */
20839 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
20840 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20841 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20842 the instruction encoding. */
20843 if (inst.operands[2].isscalar)
20845 inst.instruction &= 0xffffffd0;
20846 inst.instruction |= LOW4 (scalar_oprd2);
20847 inst.instruction |= HI1 (scalar_oprd2) << 5;
20851 /* Dot Product instructions for signed integer. */
20854 do_neon_dotproduct_s (void)
20856 return do_neon_dotproduct (0);
20859 /* Dot Product instructions for unsigned integer. */
20862 do_neon_dotproduct_u (void)
20864 return do_neon_dotproduct (1);
20867 /* Crypto v1 instructions. */
20869 do_crypto_2op_1 (unsigned elttype, int op)
20871 set_pred_insn_type (OUTSIDE_PRED_INSN);
20873 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
20879 NEON_ENCODE (INTEGER, inst);
20880 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20881 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20882 inst.instruction |= LOW4 (inst.operands[1].reg);
20883 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20885 inst.instruction |= op << 6;
20888 inst.instruction |= 0xfc000000;
20890 inst.instruction |= 0xf0000000;
20894 do_crypto_3op_1 (int u, int op)
20896 set_pred_insn_type (OUTSIDE_PRED_INSN);
20898 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
20899 N_32 | N_UNT | N_KEY).type == NT_invtype)
20904 NEON_ENCODE (INTEGER, inst);
20905 neon_three_same (1, u, 8 << op);
20911 do_crypto_2op_1 (N_8, 0);
20917 do_crypto_2op_1 (N_8, 1);
20923 do_crypto_2op_1 (N_8, 2);
20929 do_crypto_2op_1 (N_8, 3);
20935 do_crypto_3op_1 (0, 0);
20941 do_crypto_3op_1 (0, 1);
20947 do_crypto_3op_1 (0, 2);
20953 do_crypto_3op_1 (0, 3);
20959 do_crypto_3op_1 (1, 0);
20965 do_crypto_3op_1 (1, 1);
20969 do_sha256su1 (void)
20971 do_crypto_3op_1 (1, 2);
20977 do_crypto_2op_1 (N_32, -1);
20983 do_crypto_2op_1 (N_32, 0);
20987 do_sha256su0 (void)
20989 do_crypto_2op_1 (N_32, 1);
20993 do_crc32_1 (unsigned int poly, unsigned int sz)
20995 unsigned int Rd = inst.operands[0].reg;
20996 unsigned int Rn = inst.operands[1].reg;
20997 unsigned int Rm = inst.operands[2].reg;
20999 set_pred_insn_type (OUTSIDE_PRED_INSN);
21000 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
21001 inst.instruction |= LOW4 (Rn) << 16;
21002 inst.instruction |= LOW4 (Rm);
21003 inst.instruction |= sz << (thumb_mode ? 4 : 21);
21004 inst.instruction |= poly << (thumb_mode ? 20 : 9);
21006 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
21007 as_warn (UNPRED_REG ("r15"));
21049 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21051 neon_check_type (2, NS_FD, N_S32, N_F64);
21052 do_vfp_sp_dp_cvt ();
21053 do_vfp_cond_or_thumb ();
21057 /* Overall per-instruction processing. */
21059 /* We need to be able to fix up arbitrary expressions in some statements.
21060 This is so that we can handle symbols that are an arbitrary distance from
21061 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21062 which returns part of an address in a form which will be valid for
21063 a data instruction. We do this by pushing the expression into a symbol
21064 in the expr_section, and creating a fix for that. */
21067 fix_new_arm (fragS * frag,
21081 /* Create an absolute valued symbol, so we have something to
21082 refer to in the object file. Unfortunately for us, gas's
21083 generic expression parsing will already have folded out
21084 any use of .set foo/.type foo %function that may have
21085 been used to set type information of the target location,
21086 that's being specified symbolically. We have to presume
21087 the user knows what they are doing. */
21091 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
21093 symbol = symbol_find_or_make (name);
21094 S_SET_SEGMENT (symbol, absolute_section);
21095 symbol_set_frag (symbol, &zero_address_frag);
21096 S_SET_VALUE (symbol, exp->X_add_number);
21097 exp->X_op = O_symbol;
21098 exp->X_add_symbol = symbol;
21099 exp->X_add_number = 0;
21105 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
21106 (enum bfd_reloc_code_real) reloc);
21110 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
21111 pc_rel, (enum bfd_reloc_code_real) reloc);
21115 /* Mark whether the fix is to a THUMB instruction, or an ARM
21117 new_fix->tc_fix_data = thumb_mode;
21120 /* Create a frg for an instruction requiring relaxation. */
21122 output_relax_insn (void)
21128 /* The size of the instruction is unknown, so tie the debug info to the
21129 start of the instruction. */
21130 dwarf2_emit_insn (0);
21132 switch (inst.relocs[0].exp.X_op)
21135 sym = inst.relocs[0].exp.X_add_symbol;
21136 offset = inst.relocs[0].exp.X_add_number;
21140 offset = inst.relocs[0].exp.X_add_number;
21143 sym = make_expr_symbol (&inst.relocs[0].exp);
21147 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
21148 inst.relax, sym, offset, NULL/*offset, opcode*/);
21149 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
21152 /* Write a 32-bit thumb instruction to buf. */
21154 put_thumb32_insn (char * buf, unsigned long insn)
21156 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
21157 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
21161 output_inst (const char * str)
21167 as_bad ("%s -- `%s'", inst.error, str);
21172 output_relax_insn ();
21175 if (inst.size == 0)
21178 to = frag_more (inst.size);
21179 /* PR 9814: Record the thumb mode into the current frag so that we know
21180 what type of NOP padding to use, if necessary. We override any previous
21181 setting so that if the mode has changed then the NOPS that we use will
21182 match the encoding of the last instruction in the frag. */
21183 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21185 if (thumb_mode && (inst.size > THUMB_SIZE))
21187 gas_assert (inst.size == (2 * THUMB_SIZE));
21188 put_thumb32_insn (to, inst.instruction);
21190 else if (inst.size > INSN_SIZE)
21192 gas_assert (inst.size == (2 * INSN_SIZE));
21193 md_number_to_chars (to, inst.instruction, INSN_SIZE);
21194 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
21197 md_number_to_chars (to, inst.instruction, inst.size);
21200 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21202 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
21203 fix_new_arm (frag_now, to - frag_now->fr_literal,
21204 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
21205 inst.relocs[r].type);
21208 dwarf2_emit_insn (inst.size);
21212 output_it_inst (int cond, int mask, char * to)
21214 unsigned long instruction = 0xbf00;
21217 instruction |= mask;
21218 instruction |= cond << 4;
21222 to = frag_more (2);
21224 dwarf2_emit_insn (2);
21228 md_number_to_chars (to, instruction, 2);
21233 /* Tag values used in struct asm_opcode's tag field. */
21236 OT_unconditional, /* Instruction cannot be conditionalized.
21237 The ARM condition field is still 0xE. */
21238 OT_unconditionalF, /* Instruction cannot be conditionalized
21239 and carries 0xF in its ARM condition field. */
21240 OT_csuffix, /* Instruction takes a conditional suffix. */
21241 OT_csuffixF, /* Some forms of the instruction take a scalar
21242 conditional suffix, others place 0xF where the
21243 condition field would be, others take a vector
21244 conditional suffix. */
21245 OT_cinfix3, /* Instruction takes a conditional infix,
21246 beginning at character index 3. (In
21247 unified mode, it becomes a suffix.) */
21248 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
21249 tsts, cmps, cmns, and teqs. */
21250 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
21251 character index 3, even in unified mode. Used for
21252 legacy instructions where suffix and infix forms
21253 may be ambiguous. */
21254 OT_csuf_or_in3, /* Instruction takes either a conditional
21255 suffix or an infix at character index 3. */
21256 OT_odd_infix_unc, /* This is the unconditional variant of an
21257 instruction that takes a conditional infix
21258 at an unusual position. In unified mode,
21259 this variant will accept a suffix. */
21260 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
21261 are the conditional variants of instructions that
21262 take conditional infixes in unusual positions.
21263 The infix appears at character index
21264 (tag - OT_odd_infix_0). These are not accepted
21265 in unified mode. */
21268 /* Subroutine of md_assemble, responsible for looking up the primary
21269 opcode from the mnemonic the user wrote. STR points to the
21270 beginning of the mnemonic.
21272 This is not simply a hash table lookup, because of conditional
21273 variants. Most instructions have conditional variants, which are
21274 expressed with a _conditional affix_ to the mnemonic. If we were
21275 to encode each conditional variant as a literal string in the opcode
21276 table, it would have approximately 20,000 entries.
21278 Most mnemonics take this affix as a suffix, and in unified syntax,
21279 'most' is upgraded to 'all'. However, in the divided syntax, some
21280 instructions take the affix as an infix, notably the s-variants of
21281 the arithmetic instructions. Of those instructions, all but six
21282 have the infix appear after the third character of the mnemonic.
21284 Accordingly, the algorithm for looking up primary opcodes given
21287 1. Look up the identifier in the opcode table.
21288 If we find a match, go to step U.
21290 2. Look up the last two characters of the identifier in the
21291 conditions table. If we find a match, look up the first N-2
21292 characters of the identifier in the opcode table. If we
21293 find a match, go to step CE.
21295 3. Look up the fourth and fifth characters of the identifier in
21296 the conditions table. If we find a match, extract those
21297 characters from the identifier, and look up the remaining
21298 characters in the opcode table. If we find a match, go
21303 U. Examine the tag field of the opcode structure, in case this is
21304 one of the six instructions with its conditional infix in an
21305 unusual place. If it is, the tag tells us where to find the
21306 infix; look it up in the conditions table and set inst.cond
21307 accordingly. Otherwise, this is an unconditional instruction.
21308 Again set inst.cond accordingly. Return the opcode structure.
21310 CE. Examine the tag field to make sure this is an instruction that
21311 should receive a conditional suffix. If it is not, fail.
21312 Otherwise, set inst.cond from the suffix we already looked up,
21313 and return the opcode structure.
21315 CM. Examine the tag field to make sure this is an instruction that
21316 should receive a conditional infix after the third character.
21317 If it is not, fail. Otherwise, undo the edits to the current
21318 line of input and proceed as for case CE. */
21320 static const struct asm_opcode *
21321 opcode_lookup (char **str)
21325 const struct asm_opcode *opcode;
21326 const struct asm_cond *cond;
21329 /* Scan up to the end of the mnemonic, which must end in white space,
21330 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21331 for (base = end = *str; *end != '\0'; end++)
21332 if (*end == ' ' || *end == '.')
21338 /* Handle a possible width suffix and/or Neon type suffix. */
21343 /* The .w and .n suffixes are only valid if the unified syntax is in
21345 if (unified_syntax && end[1] == 'w')
21347 else if (unified_syntax && end[1] == 'n')
21352 inst.vectype.elems = 0;
21354 *str = end + offset;
21356 if (end[offset] == '.')
21358 /* See if we have a Neon type suffix (possible in either unified or
21359 non-unified ARM syntax mode). */
21360 if (parse_neon_type (&inst.vectype, str) == FAIL)
21363 else if (end[offset] != '\0' && end[offset] != ' ')
21369 /* Look for unaffixed or special-case affixed mnemonic. */
21370 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21375 if (opcode->tag < OT_odd_infix_0)
21377 inst.cond = COND_ALWAYS;
21381 if (warn_on_deprecated && unified_syntax)
21382 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21383 affix = base + (opcode->tag - OT_odd_infix_0);
21384 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21387 inst.cond = cond->value;
21390 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21392 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21394 if (end - base < 2)
21397 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
21398 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21400 /* If this opcode can not be vector predicated then don't accept it with a
21401 vector predication code. */
21402 if (opcode && !opcode->mayBeVecPred)
21405 if (!opcode || !cond)
21407 /* Cannot have a conditional suffix on a mnemonic of less than two
21409 if (end - base < 3)
21412 /* Look for suffixed mnemonic. */
21414 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21415 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21419 if (opcode && cond)
21422 switch (opcode->tag)
21424 case OT_cinfix3_legacy:
21425 /* Ignore conditional suffixes matched on infix only mnemonics. */
21429 case OT_cinfix3_deprecated:
21430 case OT_odd_infix_unc:
21431 if (!unified_syntax)
21433 /* Fall through. */
21437 case OT_csuf_or_in3:
21438 inst.cond = cond->value;
21441 case OT_unconditional:
21442 case OT_unconditionalF:
21444 inst.cond = cond->value;
21447 /* Delayed diagnostic. */
21448 inst.error = BAD_COND;
21449 inst.cond = COND_ALWAYS;
21458 /* Cannot have a usual-position infix on a mnemonic of less than
21459 six characters (five would be a suffix). */
21460 if (end - base < 6)
21463 /* Look for infixed mnemonic in the usual position. */
21465 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21469 memcpy (save, affix, 2);
21470 memmove (affix, affix + 2, (end - affix) - 2);
21471 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21473 memmove (affix + 2, affix, (end - affix) - 2);
21474 memcpy (affix, save, 2);
21477 && (opcode->tag == OT_cinfix3
21478 || opcode->tag == OT_cinfix3_deprecated
21479 || opcode->tag == OT_csuf_or_in3
21480 || opcode->tag == OT_cinfix3_legacy))
21483 if (warn_on_deprecated && unified_syntax
21484 && (opcode->tag == OT_cinfix3
21485 || opcode->tag == OT_cinfix3_deprecated))
21486 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21488 inst.cond = cond->value;
21495 /* This function generates an initial IT instruction, leaving its block
21496 virtually open for the new instructions. Eventually,
21497 the mask will be updated by now_pred_add_mask () each time
21498 a new instruction needs to be included in the IT block.
21499 Finally, the block is closed with close_automatic_it_block ().
21500 The block closure can be requested either from md_assemble (),
21501 a tencode (), or due to a label hook. */
21504 new_automatic_it_block (int cond)
21506 now_pred.state = AUTOMATIC_PRED_BLOCK;
21507 now_pred.mask = 0x18;
21508 now_pred.cc = cond;
21509 now_pred.block_length = 1;
21510 mapping_state (MAP_THUMB);
21511 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
21512 now_pred.warn_deprecated = FALSE;
21513 now_pred.insn_cond = TRUE;
21516 /* Close an automatic IT block.
21517 See comments in new_automatic_it_block (). */
21520 close_automatic_it_block (void)
21522 now_pred.mask = 0x10;
21523 now_pred.block_length = 0;
21526 /* Update the mask of the current automatically-generated IT
21527 instruction. See comments in new_automatic_it_block (). */
21530 now_pred_add_mask (int cond)
21532 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21533 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21534 | ((bitvalue) << (nbit)))
21535 const int resulting_bit = (cond & 1);
21537 now_pred.mask &= 0xf;
21538 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
21540 (5 - now_pred.block_length));
21541 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
21543 ((5 - now_pred.block_length) - 1));
21544 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
21547 #undef SET_BIT_VALUE
21550 /* The IT blocks handling machinery is accessed through the these functions:
21551 it_fsm_pre_encode () from md_assemble ()
21552 set_pred_insn_type () optional, from the tencode functions
21553 set_pred_insn_type_last () ditto
21554 in_pred_block () ditto
21555 it_fsm_post_encode () from md_assemble ()
21556 force_automatic_it_block_close () from label handling functions
21559 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21560 initializing the IT insn type with a generic initial value depending
21561 on the inst.condition.
21562 2) During the tencode function, two things may happen:
21563 a) The tencode function overrides the IT insn type by
21564 calling either set_pred_insn_type (type) or
21565 set_pred_insn_type_last ().
21566 b) The tencode function queries the IT block state by
21567 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21569 Both set_pred_insn_type and in_pred_block run the internal FSM state
21570 handling function (handle_pred_state), because: a) setting the IT insn
21571 type may incur in an invalid state (exiting the function),
21572 and b) querying the state requires the FSM to be updated.
21573 Specifically we want to avoid creating an IT block for conditional
21574 branches, so it_fsm_pre_encode is actually a guess and we can't
21575 determine whether an IT block is required until the tencode () routine
21576 has decided what type of instruction this actually it.
21577 Because of this, if set_pred_insn_type and in_pred_block have to be
21578 used, set_pred_insn_type has to be called first.
21580 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21581 that determines the insn IT type depending on the inst.cond code.
21582 When a tencode () routine encodes an instruction that can be
21583 either outside an IT block, or, in the case of being inside, has to be
21584 the last one, set_pred_insn_type_last () will determine the proper
21585 IT instruction type based on the inst.cond code. Otherwise,
21586 set_pred_insn_type can be called for overriding that logic or
21587 for covering other cases.
21589 Calling handle_pred_state () may not transition the IT block state to
21590 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21591 still queried. Instead, if the FSM determines that the state should
21592 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21593 after the tencode () function: that's what it_fsm_post_encode () does.
21595 Since in_pred_block () calls the state handling function to get an
21596 updated state, an error may occur (due to invalid insns combination).
21597 In that case, inst.error is set.
21598 Therefore, inst.error has to be checked after the execution of
21599 the tencode () routine.
21601 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21602 any pending state change (if any) that didn't take place in
21603 handle_pred_state () as explained above. */
21606 it_fsm_pre_encode (void)
21608 if (inst.cond != COND_ALWAYS)
21609 inst.pred_insn_type = INSIDE_IT_INSN;
21611 inst.pred_insn_type = OUTSIDE_PRED_INSN;
21613 now_pred.state_handled = 0;
21616 /* IT state FSM handling function. */
21617 /* MVE instructions and non-MVE instructions are handled differently because of
21618 the introduction of VPT blocks.
21619 Specifications say that any non-MVE instruction inside a VPT block is
21620 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21621 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21622 few exceptions we have MVE_UNPREDICABLE_INSN.
21623 The error messages provided depending on the different combinations possible
21624 are described in the cases below:
21625 For 'most' MVE instructions:
21626 1) In an IT block, with an IT code: syntax error
21627 2) In an IT block, with a VPT code: error: must be in a VPT block
21628 3) In an IT block, with no code: warning: UNPREDICTABLE
21629 4) In a VPT block, with an IT code: syntax error
21630 5) In a VPT block, with a VPT code: OK!
21631 6) In a VPT block, with no code: error: missing code
21632 7) Outside a pred block, with an IT code: error: syntax error
21633 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21634 9) Outside a pred block, with no code: OK!
21635 For non-MVE instructions:
21636 10) In an IT block, with an IT code: OK!
21637 11) In an IT block, with a VPT code: syntax error
21638 12) In an IT block, with no code: error: missing code
21639 13) In a VPT block, with an IT code: error: should be in an IT block
21640 14) In a VPT block, with a VPT code: syntax error
21641 15) In a VPT block, with no code: UNPREDICTABLE
21642 16) Outside a pred block, with an IT code: error: should be in an IT block
21643 17) Outside a pred block, with a VPT code: syntax error
21644 18) Outside a pred block, with no code: OK!
21649 handle_pred_state (void)
21651 now_pred.state_handled = 1;
21652 now_pred.insn_cond = FALSE;
21654 switch (now_pred.state)
21656 case OUTSIDE_PRED_BLOCK:
21657 switch (inst.pred_insn_type)
21659 case MVE_UNPREDICABLE_INSN:
21660 case MVE_OUTSIDE_PRED_INSN:
21661 if (inst.cond < COND_ALWAYS)
21663 /* Case 7: Outside a pred block, with an IT code: error: syntax
21665 inst.error = BAD_SYNTAX;
21668 /* Case 9: Outside a pred block, with no code: OK! */
21670 case OUTSIDE_PRED_INSN:
21671 if (inst.cond > COND_ALWAYS)
21673 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21675 inst.error = BAD_SYNTAX;
21678 /* Case 18: Outside a pred block, with no code: OK! */
21681 case INSIDE_VPT_INSN:
21682 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21684 inst.error = BAD_OUT_VPT;
21687 case INSIDE_IT_INSN:
21688 case INSIDE_IT_LAST_INSN:
21689 if (inst.cond < COND_ALWAYS)
21691 /* Case 16: Outside a pred block, with an IT code: error: should
21692 be in an IT block. */
21693 if (thumb_mode == 0)
21696 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
21697 as_tsktsk (_("Warning: conditional outside an IT block"\
21702 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
21703 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
21705 /* Automatically generate the IT instruction. */
21706 new_automatic_it_block (inst.cond);
21707 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
21708 close_automatic_it_block ();
21712 inst.error = BAD_OUT_IT;
21718 else if (inst.cond > COND_ALWAYS)
21720 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21722 inst.error = BAD_SYNTAX;
21727 case IF_INSIDE_IT_LAST_INSN:
21728 case NEUTRAL_IT_INSN:
21732 if (inst.cond != COND_ALWAYS)
21733 first_error (BAD_SYNTAX);
21734 now_pred.state = MANUAL_PRED_BLOCK;
21735 now_pred.block_length = 0;
21736 now_pred.type = VECTOR_PRED;
21740 now_pred.state = MANUAL_PRED_BLOCK;
21741 now_pred.block_length = 0;
21742 now_pred.type = SCALAR_PRED;
21747 case AUTOMATIC_PRED_BLOCK:
21748 /* Three things may happen now:
21749 a) We should increment current it block size;
21750 b) We should close current it block (closing insn or 4 insns);
21751 c) We should close current it block and start a new one (due
21752 to incompatible conditions or
21753 4 insns-length block reached). */
21755 switch (inst.pred_insn_type)
21757 case INSIDE_VPT_INSN:
21759 case MVE_UNPREDICABLE_INSN:
21760 case MVE_OUTSIDE_PRED_INSN:
21762 case OUTSIDE_PRED_INSN:
21763 /* The closure of the block shall happen immediately,
21764 so any in_pred_block () call reports the block as closed. */
21765 force_automatic_it_block_close ();
21768 case INSIDE_IT_INSN:
21769 case INSIDE_IT_LAST_INSN:
21770 case IF_INSIDE_IT_LAST_INSN:
21771 now_pred.block_length++;
21773 if (now_pred.block_length > 4
21774 || !now_pred_compatible (inst.cond))
21776 force_automatic_it_block_close ();
21777 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
21778 new_automatic_it_block (inst.cond);
21782 now_pred.insn_cond = TRUE;
21783 now_pred_add_mask (inst.cond);
21786 if (now_pred.state == AUTOMATIC_PRED_BLOCK
21787 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
21788 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
21789 close_automatic_it_block ();
21792 case NEUTRAL_IT_INSN:
21793 now_pred.block_length++;
21794 now_pred.insn_cond = TRUE;
21796 if (now_pred.block_length > 4)
21797 force_automatic_it_block_close ();
21799 now_pred_add_mask (now_pred.cc & 1);
21803 close_automatic_it_block ();
21804 now_pred.state = MANUAL_PRED_BLOCK;
21809 case MANUAL_PRED_BLOCK:
21812 if (now_pred.type == SCALAR_PRED)
21814 /* Check conditional suffixes. */
21815 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
21816 now_pred.mask <<= 1;
21817 now_pred.mask &= 0x1f;
21818 is_last = (now_pred.mask == 0x10);
21822 now_pred.cc ^= (now_pred.mask >> 4);
21823 cond = now_pred.cc + 0xf;
21824 now_pred.mask <<= 1;
21825 now_pred.mask &= 0x1f;
21826 is_last = now_pred.mask == 0x10;
21828 now_pred.insn_cond = TRUE;
21830 switch (inst.pred_insn_type)
21832 case OUTSIDE_PRED_INSN:
21833 if (now_pred.type == SCALAR_PRED)
21835 if (inst.cond == COND_ALWAYS)
21837 /* Case 12: In an IT block, with no code: error: missing
21839 inst.error = BAD_NOT_IT;
21842 else if (inst.cond > COND_ALWAYS)
21844 /* Case 11: In an IT block, with a VPT code: syntax error.
21846 inst.error = BAD_SYNTAX;
21849 else if (thumb_mode)
21851 /* This is for some special cases where a non-MVE
21852 instruction is not allowed in an IT block, such as cbz,
21853 but are put into one with a condition code.
21854 You could argue this should be a syntax error, but we
21855 gave the 'not allowed in IT block' diagnostic in the
21856 past so we will keep doing so. */
21857 inst.error = BAD_NOT_IT;
21864 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21865 as_tsktsk (MVE_NOT_VPT);
21868 case MVE_OUTSIDE_PRED_INSN:
21869 if (now_pred.type == SCALAR_PRED)
21871 if (inst.cond == COND_ALWAYS)
21873 /* Case 3: In an IT block, with no code: warning:
21875 as_tsktsk (MVE_NOT_IT);
21878 else if (inst.cond < COND_ALWAYS)
21880 /* Case 1: In an IT block, with an IT code: syntax error.
21882 inst.error = BAD_SYNTAX;
21890 if (inst.cond < COND_ALWAYS)
21892 /* Case 4: In a VPT block, with an IT code: syntax error.
21894 inst.error = BAD_SYNTAX;
21897 else if (inst.cond == COND_ALWAYS)
21899 /* Case 6: In a VPT block, with no code: error: missing
21901 inst.error = BAD_NOT_VPT;
21909 case MVE_UNPREDICABLE_INSN:
21910 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
21912 case INSIDE_IT_INSN:
21913 if (inst.cond > COND_ALWAYS)
21915 /* Case 11: In an IT block, with a VPT code: syntax error. */
21916 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21917 inst.error = BAD_SYNTAX;
21920 else if (now_pred.type == SCALAR_PRED)
21922 /* Case 10: In an IT block, with an IT code: OK! */
21923 if (cond != inst.cond)
21925 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
21932 /* Case 13: In a VPT block, with an IT code: error: should be
21934 inst.error = BAD_OUT_IT;
21939 case INSIDE_VPT_INSN:
21940 if (now_pred.type == SCALAR_PRED)
21942 /* Case 2: In an IT block, with a VPT code: error: must be in a
21944 inst.error = BAD_OUT_VPT;
21947 /* Case 5: In a VPT block, with a VPT code: OK! */
21948 else if (cond != inst.cond)
21950 inst.error = BAD_VPT_COND;
21954 case INSIDE_IT_LAST_INSN:
21955 case IF_INSIDE_IT_LAST_INSN:
21956 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
21958 /* Case 4: In a VPT block, with an IT code: syntax error. */
21959 /* Case 11: In an IT block, with a VPT code: syntax error. */
21960 inst.error = BAD_SYNTAX;
21963 else if (cond != inst.cond)
21965 inst.error = BAD_IT_COND;
21970 inst.error = BAD_BRANCH;
21975 case NEUTRAL_IT_INSN:
21976 /* The BKPT instruction is unconditional even in a IT or VPT
21981 if (now_pred.type == SCALAR_PRED)
21983 inst.error = BAD_IT_IT;
21986 /* fall through. */
21988 if (inst.cond == COND_ALWAYS)
21990 /* Executing a VPT/VPST instruction inside an IT block or a
21991 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21993 if (now_pred.type == SCALAR_PRED)
21994 as_tsktsk (MVE_NOT_IT);
21996 as_tsktsk (MVE_NOT_VPT);
22001 /* VPT/VPST do not accept condition codes. */
22002 inst.error = BAD_SYNTAX;
22013 struct depr_insn_mask
22015 unsigned long pattern;
22016 unsigned long mask;
22017 const char* description;
22020 /* List of 16-bit instruction patterns deprecated in an IT block in
22022 static const struct depr_insn_mask depr_it_insns[] = {
22023 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22024 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22025 { 0xa000, 0xb800, N_("ADR") },
22026 { 0x4800, 0xf800, N_("Literal loads") },
22027 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22028 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22029 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22030 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22031 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22036 it_fsm_post_encode (void)
22040 if (!now_pred.state_handled)
22041 handle_pred_state ();
22043 if (now_pred.insn_cond
22044 && !now_pred.warn_deprecated
22045 && warn_on_deprecated
22046 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
22047 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
22049 if (inst.instruction >= 0x10000)
22051 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22052 "performance deprecated in ARMv8-A and ARMv8-R"));
22053 now_pred.warn_deprecated = TRUE;
22057 const struct depr_insn_mask *p = depr_it_insns;
22059 while (p->mask != 0)
22061 if ((inst.instruction & p->mask) == p->pattern)
22063 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22064 "instructions of the following class are "
22065 "performance deprecated in ARMv8-A and "
22066 "ARMv8-R: %s"), p->description);
22067 now_pred.warn_deprecated = TRUE;
22075 if (now_pred.block_length > 1)
22077 as_tsktsk (_("IT blocks containing more than one conditional "
22078 "instruction are performance deprecated in ARMv8-A and "
22080 now_pred.warn_deprecated = TRUE;
22084 is_last = (now_pred.mask == 0x10);
22087 now_pred.state = OUTSIDE_PRED_BLOCK;
22093 force_automatic_it_block_close (void)
22095 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
22097 close_automatic_it_block ();
22098 now_pred.state = OUTSIDE_PRED_BLOCK;
22104 in_pred_block (void)
22106 if (!now_pred.state_handled)
22107 handle_pred_state ();
22109 return now_pred.state != OUTSIDE_PRED_BLOCK;
22112 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22113 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22114 here, hence the "known" in the function name. */
22117 known_t32_only_insn (const struct asm_opcode *opcode)
22119 /* Original Thumb-1 wide instruction. */
22120 if (opcode->tencode == do_t_blx
22121 || opcode->tencode == do_t_branch23
22122 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
22123 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
22126 /* Wide-only instruction added to ARMv8-M Baseline. */
22127 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
22128 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
22129 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
22130 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
22136 /* Whether wide instruction variant can be used if available for a valid OPCODE
22140 t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
22142 if (known_t32_only_insn (opcode))
22145 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22146 of variant T3 of B.W is checked in do_t_branch. */
22147 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22148 && opcode->tencode == do_t_branch)
22151 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22152 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22153 && opcode->tencode == do_t_mov_cmp
22154 /* Make sure CMP instruction is not affected. */
22155 && opcode->aencode == do_mov)
22158 /* Wide instruction variants of all instructions with narrow *and* wide
22159 variants become available with ARMv6t2. Other opcodes are either
22160 narrow-only or wide-only and are thus available if OPCODE is valid. */
22161 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
22164 /* OPCODE with narrow only instruction variant or wide variant not
22170 md_assemble (char *str)
22173 const struct asm_opcode * opcode;
22175 /* Align the previous label if needed. */
22176 if (last_label_seen != NULL)
22178 symbol_set_frag (last_label_seen, frag_now);
22179 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
22180 S_SET_SEGMENT (last_label_seen, now_seg);
22183 memset (&inst, '\0', sizeof (inst));
22185 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22186 inst.relocs[r].type = BFD_RELOC_UNUSED;
22188 opcode = opcode_lookup (&p);
22191 /* It wasn't an instruction, but it might be a register alias of
22192 the form alias .req reg, or a Neon .dn/.qn directive. */
22193 if (! create_register_alias (str, p)
22194 && ! create_neon_reg_alias (str, p))
22195 as_bad (_("bad instruction `%s'"), str);
22200 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
22201 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22203 /* The value which unconditional instructions should have in place of the
22204 condition field. */
22205 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
22209 arm_feature_set variant;
22211 variant = cpu_variant;
22212 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22213 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
22214 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
22215 /* Check that this instruction is supported for this CPU. */
22216 if (!opcode->tvariant
22217 || (thumb_mode == 1
22218 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
22220 if (opcode->tencode == do_t_swi)
22221 as_bad (_("SVC is not permitted on this architecture"));
22223 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
22226 if (inst.cond != COND_ALWAYS && !unified_syntax
22227 && opcode->tencode != do_t_branch)
22229 as_bad (_("Thumb does not support conditional execution"));
22233 /* Two things are addressed here:
22234 1) Implicit require narrow instructions on Thumb-1.
22235 This avoids relaxation accidentally introducing Thumb-2
22237 2) Reject wide instructions in non Thumb-2 cores.
22239 Only instructions with narrow and wide variants need to be handled
22240 but selecting all non wide-only instructions is easier. */
22241 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
22242 && !t32_insn_ok (variant, opcode))
22244 if (inst.size_req == 0)
22246 else if (inst.size_req == 4)
22248 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
22249 as_bad (_("selected processor does not support 32bit wide "
22250 "variant of instruction `%s'"), str);
22252 as_bad (_("selected processor does not support `%s' in "
22253 "Thumb-2 mode"), str);
22258 inst.instruction = opcode->tvalue;
22260 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
22262 /* Prepare the pred_insn_type for those encodings that don't set
22264 it_fsm_pre_encode ();
22266 opcode->tencode ();
22268 it_fsm_post_encode ();
22271 if (!(inst.error || inst.relax))
22273 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
22274 inst.size = (inst.instruction > 0xffff ? 4 : 2);
22275 if (inst.size_req && inst.size_req != inst.size)
22277 as_bad (_("cannot honor width suffix -- `%s'"), str);
22282 /* Something has gone badly wrong if we try to relax a fixed size
22284 gas_assert (inst.size_req == 0 || !inst.relax);
22286 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22287 *opcode->tvariant);
22288 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22289 set those bits when Thumb-2 32-bit instructions are seen. The impact
22290 of relaxable instructions will be considered later after we finish all
22292 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
22293 variant = arm_arch_none;
22295 variant = cpu_variant;
22296 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
22297 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22300 check_neon_suffixes;
22304 mapping_state (MAP_THUMB);
22307 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22311 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22312 is_bx = (opcode->aencode == do_bx);
22314 /* Check that this instruction is supported for this CPU. */
22315 if (!(is_bx && fix_v4bx)
22316 && !(opcode->avariant &&
22317 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
22319 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
22324 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
22328 inst.instruction = opcode->avalue;
22329 if (opcode->tag == OT_unconditionalF)
22330 inst.instruction |= 0xFU << 28;
22332 inst.instruction |= inst.cond << 28;
22333 inst.size = INSN_SIZE;
22334 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
22336 it_fsm_pre_encode ();
22337 opcode->aencode ();
22338 it_fsm_post_encode ();
22340 /* Arm mode bx is marked as both v4T and v5 because it's still required
22341 on a hypothetical non-thumb v5 core. */
22343 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
22345 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
22346 *opcode->avariant);
22348 check_neon_suffixes;
22352 mapping_state (MAP_ARM);
22357 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22365 check_pred_blocks_finished (void)
22370 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
22371 if (seg_info (sect)->tc_segment_info_data.current_pred.state
22372 == MANUAL_PRED_BLOCK)
22374 if (now_pred.type == SCALAR_PRED)
22375 as_warn (_("section '%s' finished with an open IT block."),
22378 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22382 if (now_pred.state == MANUAL_PRED_BLOCK)
22384 if (now_pred.type == SCALAR_PRED)
22385 as_warn (_("file finished with an open IT block."));
22387 as_warn (_("file finished with an open VPT/VPST block."));
22392 /* Various frobbings of labels and their addresses. */
22395 arm_start_line_hook (void)
22397 last_label_seen = NULL;
22401 arm_frob_label (symbolS * sym)
22403 last_label_seen = sym;
22405 ARM_SET_THUMB (sym, thumb_mode);
22407 #if defined OBJ_COFF || defined OBJ_ELF
22408 ARM_SET_INTERWORK (sym, support_interwork);
22411 force_automatic_it_block_close ();
22413 /* Note - do not allow local symbols (.Lxxx) to be labelled
22414 as Thumb functions. This is because these labels, whilst
22415 they exist inside Thumb code, are not the entry points for
22416 possible ARM->Thumb calls. Also, these labels can be used
22417 as part of a computed goto or switch statement. eg gcc
22418 can generate code that looks like this:
22420 ldr r2, [pc, .Laaa]
22430 The first instruction loads the address of the jump table.
22431 The second instruction converts a table index into a byte offset.
22432 The third instruction gets the jump address out of the table.
22433 The fourth instruction performs the jump.
22435 If the address stored at .Laaa is that of a symbol which has the
22436 Thumb_Func bit set, then the linker will arrange for this address
22437 to have the bottom bit set, which in turn would mean that the
22438 address computation performed by the third instruction would end
22439 up with the bottom bit set. Since the ARM is capable of unaligned
22440 word loads, the instruction would then load the incorrect address
22441 out of the jump table, and chaos would ensue. */
22442 if (label_is_thumb_function_name
22443 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
22444 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
22446 /* When the address of a Thumb function is taken the bottom
22447 bit of that address should be set. This will allow
22448 interworking between Arm and Thumb functions to work
22451 THUMB_SET_FUNC (sym, 1);
22453 label_is_thumb_function_name = FALSE;
22456 dwarf2_emit_label (sym);
22460 arm_data_in_code (void)
22462 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
22464 *input_line_pointer = '/';
22465 input_line_pointer += 5;
22466 *input_line_pointer = 0;
22474 arm_canonicalize_symbol_name (char * name)
22478 if (thumb_mode && (len = strlen (name)) > 5
22479 && streq (name + len - 5, "/data"))
22480 *(name + len - 5) = 0;
22485 /* Table of all register names defined by default. The user can
22486 define additional names with .req. Note that all register names
22487 should appear in both upper and lowercase variants. Some registers
22488 also have mixed-case names. */
22490 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22491 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22492 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22493 #define REGSET(p,t) \
22494 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22495 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22496 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22497 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22498 #define REGSETH(p,t) \
22499 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22500 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22501 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22502 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22503 #define REGSET2(p,t) \
22504 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22505 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22506 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22507 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22508 #define SPLRBANK(base,bank,t) \
22509 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22510 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22511 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22512 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22513 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22514 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22516 static const struct reg_entry reg_names[] =
22518 /* ARM integer registers. */
22519 REGSET(r, RN), REGSET(R, RN),
22521 /* ATPCS synonyms. */
22522 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
22523 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
22524 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
22526 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
22527 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
22528 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
22530 /* Well-known aliases. */
22531 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
22532 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
22534 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
22535 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
22537 /* Defining the new Zero register from ARMv8.1-M. */
22541 /* Coprocessor numbers. */
22542 REGSET(p, CP), REGSET(P, CP),
22544 /* Coprocessor register numbers. The "cr" variants are for backward
22546 REGSET(c, CN), REGSET(C, CN),
22547 REGSET(cr, CN), REGSET(CR, CN),
22549 /* ARM banked registers. */
22550 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
22551 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
22552 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
22553 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
22554 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
22555 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
22556 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
22558 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
22559 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
22560 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
22561 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
22562 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
22563 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
22564 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
22565 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
22567 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
22568 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
22569 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
22570 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
22571 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
22572 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
22573 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
22574 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
22575 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
22577 /* FPA registers. */
22578 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
22579 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
22581 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
22582 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
22584 /* VFP SP registers. */
22585 REGSET(s,VFS), REGSET(S,VFS),
22586 REGSETH(s,VFS), REGSETH(S,VFS),
22588 /* VFP DP Registers. */
22589 REGSET(d,VFD), REGSET(D,VFD),
22590 /* Extra Neon DP registers. */
22591 REGSETH(d,VFD), REGSETH(D,VFD),
22593 /* Neon QP registers. */
22594 REGSET2(q,NQ), REGSET2(Q,NQ),
22596 /* VFP control registers. */
22597 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
22598 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
22599 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
22600 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
22601 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
22602 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
22603 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
22605 /* Maverick DSP coprocessor registers. */
22606 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
22607 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
22609 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
22610 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
22611 REGDEF(dspsc,0,DSPSC),
22613 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
22614 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
22615 REGDEF(DSPSC,0,DSPSC),
22617 /* iWMMXt data registers - p0, c0-15. */
22618 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
22620 /* iWMMXt control registers - p1, c0-3. */
22621 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
22622 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
22623 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
22624 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
22626 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22627 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
22628 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
22629 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
22630 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
22632 /* XScale accumulator registers. */
22633 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
22639 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22640 within psr_required_here. */
22641 static const struct asm_psr psrs[] =
22643 /* Backward compatibility notation. Note that "all" is no longer
22644 truly all possible PSR bits. */
22645 {"all", PSR_c | PSR_f},
22649 /* Individual flags. */
22655 /* Combinations of flags. */
22656 {"fs", PSR_f | PSR_s},
22657 {"fx", PSR_f | PSR_x},
22658 {"fc", PSR_f | PSR_c},
22659 {"sf", PSR_s | PSR_f},
22660 {"sx", PSR_s | PSR_x},
22661 {"sc", PSR_s | PSR_c},
22662 {"xf", PSR_x | PSR_f},
22663 {"xs", PSR_x | PSR_s},
22664 {"xc", PSR_x | PSR_c},
22665 {"cf", PSR_c | PSR_f},
22666 {"cs", PSR_c | PSR_s},
22667 {"cx", PSR_c | PSR_x},
22668 {"fsx", PSR_f | PSR_s | PSR_x},
22669 {"fsc", PSR_f | PSR_s | PSR_c},
22670 {"fxs", PSR_f | PSR_x | PSR_s},
22671 {"fxc", PSR_f | PSR_x | PSR_c},
22672 {"fcs", PSR_f | PSR_c | PSR_s},
22673 {"fcx", PSR_f | PSR_c | PSR_x},
22674 {"sfx", PSR_s | PSR_f | PSR_x},
22675 {"sfc", PSR_s | PSR_f | PSR_c},
22676 {"sxf", PSR_s | PSR_x | PSR_f},
22677 {"sxc", PSR_s | PSR_x | PSR_c},
22678 {"scf", PSR_s | PSR_c | PSR_f},
22679 {"scx", PSR_s | PSR_c | PSR_x},
22680 {"xfs", PSR_x | PSR_f | PSR_s},
22681 {"xfc", PSR_x | PSR_f | PSR_c},
22682 {"xsf", PSR_x | PSR_s | PSR_f},
22683 {"xsc", PSR_x | PSR_s | PSR_c},
22684 {"xcf", PSR_x | PSR_c | PSR_f},
22685 {"xcs", PSR_x | PSR_c | PSR_s},
22686 {"cfs", PSR_c | PSR_f | PSR_s},
22687 {"cfx", PSR_c | PSR_f | PSR_x},
22688 {"csf", PSR_c | PSR_s | PSR_f},
22689 {"csx", PSR_c | PSR_s | PSR_x},
22690 {"cxf", PSR_c | PSR_x | PSR_f},
22691 {"cxs", PSR_c | PSR_x | PSR_s},
22692 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
22693 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
22694 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
22695 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
22696 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
22697 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
22698 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
22699 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
22700 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
22701 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
22702 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
22703 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
22704 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
22705 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
22706 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
22707 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
22708 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
22709 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
22710 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
22711 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
22712 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
22713 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
22714 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
22715 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
22718 /* Table of V7M psr names. */
22719 static const struct asm_psr v7m_psrs[] =
22721 {"apsr", 0x0 }, {"APSR", 0x0 },
22722 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22723 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22724 {"psr", 0x3 }, {"PSR", 0x3 },
22725 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22726 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22727 {"epsr", 0x6 }, {"EPSR", 0x6 },
22728 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22729 {"msp", 0x8 }, {"MSP", 0x8 },
22730 {"psp", 0x9 }, {"PSP", 0x9 },
22731 {"msplim", 0xa }, {"MSPLIM", 0xa },
22732 {"psplim", 0xb }, {"PSPLIM", 0xb },
22733 {"primask", 0x10}, {"PRIMASK", 0x10},
22734 {"basepri", 0x11}, {"BASEPRI", 0x11},
22735 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22736 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22737 {"control", 0x14}, {"CONTROL", 0x14},
22738 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22739 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22740 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22741 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22742 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22743 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22744 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22745 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22746 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22749 /* Table of all shift-in-operand names. */
22750 static const struct asm_shift_name shift_names [] =
22752 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
22753 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
22754 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
22755 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
22756 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
22757 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
22758 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
22761 /* Table of all explicit relocation names. */
22763 static struct reloc_entry reloc_names[] =
22765 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
22766 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
22767 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
22768 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
22769 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
22770 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
22771 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
22772 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
22773 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
22774 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
22775 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
22776 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
22777 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
22778 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
22779 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
22780 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
22781 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
22782 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
22783 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
22784 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
22785 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22786 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
22787 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
22788 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
22789 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
22790 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
22791 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
22795 /* Table of all conditional affixes. */
22796 static const struct asm_cond conds[] =
22800 {"cs", 0x2}, {"hs", 0x2},
22801 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22814 static const struct asm_cond vconds[] =
22820 #define UL_BARRIER(L,U,CODE,FEAT) \
22821 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22822 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22824 static struct asm_barrier_opt barrier_opt_names[] =
22826 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
22827 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
22828 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
22829 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
22830 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
22831 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
22832 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
22833 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
22834 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
22835 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
22836 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
22837 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
22838 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
22839 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
22840 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
22841 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
22846 /* Table of ARM-format instructions. */
22848 /* Macros for gluing together operand strings. N.B. In all cases
22849 other than OPS0, the trailing OP_stop comes from default
22850 zero-initialization of the unspecified elements of the array. */
22851 #define OPS0() { OP_stop, }
22852 #define OPS1(a) { OP_##a, }
22853 #define OPS2(a,b) { OP_##a,OP_##b, }
22854 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22855 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22856 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22857 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22859 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22860 This is useful when mixing operands for ARM and THUMB, i.e. using the
22861 MIX_ARM_THUMB_OPERANDS macro.
22862 In order to use these macros, prefix the number of operands with _
22864 #define OPS_1(a) { a, }
22865 #define OPS_2(a,b) { a,b, }
22866 #define OPS_3(a,b,c) { a,b,c, }
22867 #define OPS_4(a,b,c,d) { a,b,c,d, }
22868 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22869 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22871 /* These macros abstract out the exact format of the mnemonic table and
22872 save some repeated characters. */
22874 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22875 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22876 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22877 THUMB_VARIANT, do_##ae, do_##te, 0 }
22879 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22880 a T_MNEM_xyz enumerator. */
22881 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22882 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22883 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22884 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22886 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22887 infix after the third character. */
22888 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22889 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22890 THUMB_VARIANT, do_##ae, do_##te, 0 }
22891 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22892 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22893 THUMB_VARIANT, do_##ae, do_##te, 0 }
22894 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22895 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22896 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22897 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22898 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22899 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22900 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22901 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22903 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22904 field is still 0xE. Many of the Thumb variants can be executed
22905 conditionally, so this is checked separately. */
22906 #define TUE(mnem, op, top, nops, ops, ae, te) \
22907 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22908 THUMB_VARIANT, do_##ae, do_##te, 0 }
22910 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22911 Used by mnemonics that have very minimal differences in the encoding for
22912 ARM and Thumb variants and can be handled in a common function. */
22913 #define TUEc(mnem, op, top, nops, ops, en) \
22914 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22915 THUMB_VARIANT, do_##en, do_##en, 0 }
22917 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22918 condition code field. */
22919 #define TUF(mnem, op, top, nops, ops, ae, te) \
22920 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22921 THUMB_VARIANT, do_##ae, do_##te, 0 }
22923 /* ARM-only variants of all the above. */
22924 #define CE(mnem, op, nops, ops, ae) \
22925 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22927 #define C3(mnem, op, nops, ops, ae) \
22928 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22930 /* Thumb-only variants of TCE and TUE. */
22931 #define ToC(mnem, top, nops, ops, te) \
22932 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22935 #define ToU(mnem, top, nops, ops, te) \
22936 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22939 /* T_MNEM_xyz enumerator variants of ToC. */
22940 #define toC(mnem, top, nops, ops, te) \
22941 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22944 /* T_MNEM_xyz enumerator variants of ToU. */
22945 #define toU(mnem, top, nops, ops, te) \
22946 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22949 /* Legacy mnemonics that always have conditional infix after the third
22951 #define CL(mnem, op, nops, ops, ae) \
22952 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22953 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22955 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22956 #define cCE(mnem, op, nops, ops, ae) \
22957 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22959 /* mov instructions that are shared between coprocessor and MVE. */
22960 #define mcCE(mnem, op, nops, ops, ae) \
22961 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22963 /* Legacy coprocessor instructions where conditional infix and conditional
22964 suffix are ambiguous. For consistency this includes all FPA instructions,
22965 not just the potentially ambiguous ones. */
22966 #define cCL(mnem, op, nops, ops, ae) \
22967 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22968 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22970 /* Coprocessor, takes either a suffix or a position-3 infix
22971 (for an FPA corner case). */
22972 #define C3E(mnem, op, nops, ops, ae) \
22973 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22974 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22976 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22977 { m1 #m2 m3, OPS##nops ops, \
22978 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22979 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22981 #define CM(m1, m2, op, nops, ops, ae) \
22982 xCM_ (m1, , m2, op, nops, ops, ae), \
22983 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22984 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22985 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22986 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22987 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22988 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22989 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22990 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22991 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22992 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22993 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22994 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22995 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22996 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22997 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22998 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22999 xCM_ (m1, le, m2, op, nops, ops, ae), \
23000 xCM_ (m1, al, m2, op, nops, ops, ae)
23002 #define UE(mnem, op, nops, ops, ae) \
23003 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23005 #define UF(mnem, op, nops, ops, ae) \
23006 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23008 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23009 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23010 use the same encoding function for each. */
23011 #define NUF(mnem, op, nops, ops, enc) \
23012 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23013 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23015 /* Neon data processing, version which indirects through neon_enc_tab for
23016 the various overloaded versions of opcodes. */
23017 #define nUF(mnem, op, nops, ops, enc) \
23018 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23019 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23021 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23023 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23024 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23025 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23027 #define NCE(mnem, op, nops, ops, enc) \
23028 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23030 #define NCEF(mnem, op, nops, ops, enc) \
23031 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23033 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23034 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23035 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23036 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23038 #define nCE(mnem, op, nops, ops, enc) \
23039 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23041 #define nCEF(mnem, op, nops, ops, enc) \
23042 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23045 #define mCEF(mnem, op, nops, ops, enc) \
23046 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23047 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23050 /* nCEF but for MVE predicated instructions. */
23051 #define mnCEF(mnem, op, nops, ops, enc) \
23052 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23054 /* nCE but for MVE predicated instructions. */
23055 #define mnCE(mnem, op, nops, ops, enc) \
23056 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23058 /* NUF but for potentially MVE predicated instructions. */
23059 #define MNUF(mnem, op, nops, ops, enc) \
23060 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23061 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23063 /* nUF but for potentially MVE predicated instructions. */
23064 #define mnUF(mnem, op, nops, ops, enc) \
23065 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23066 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23068 /* ToC but for potentially MVE predicated instructions. */
23069 #define mToC(mnem, top, nops, ops, te) \
23070 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23073 /* NCE but for MVE predicated instructions. */
23074 #define MNCE(mnem, op, nops, ops, enc) \
23075 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23077 /* NCEF but for MVE predicated instructions. */
23078 #define MNCEF(mnem, op, nops, ops, enc) \
23079 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23082 static const struct asm_opcode insns[] =
23084 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23085 #define THUMB_VARIANT & arm_ext_v4t
23086 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
23087 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
23088 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
23089 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
23090 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
23091 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
23092 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
23093 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
23094 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
23095 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
23096 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
23097 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
23098 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
23099 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
23100 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
23101 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
23103 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23104 for setting PSR flag bits. They are obsolete in V6 and do not
23105 have Thumb equivalents. */
23106 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23107 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23108 CL("tstp", 110f000, 2, (RR, SH), cmp),
23109 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23110 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23111 CL("cmpp", 150f000, 2, (RR, SH), cmp),
23112 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23113 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23114 CL("cmnp", 170f000, 2, (RR, SH), cmp),
23116 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
23117 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
23118 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
23119 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
23121 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
23122 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
23123 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
23125 OP_ADDRGLDR),ldst, t_ldst),
23126 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
23128 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23129 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23130 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23131 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23132 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23133 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23135 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
23136 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
23139 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
23140 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
23141 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
23142 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
23144 /* Thumb-compatibility pseudo ops. */
23145 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
23146 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
23147 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
23148 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
23149 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
23150 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
23151 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
23152 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
23153 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
23154 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
23155 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
23156 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
23158 /* These may simplify to neg. */
23159 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
23160 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
23162 #undef THUMB_VARIANT
23163 #define THUMB_VARIANT & arm_ext_os
23165 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
23166 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
23168 #undef THUMB_VARIANT
23169 #define THUMB_VARIANT & arm_ext_v6
23171 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
23173 /* V1 instructions with no Thumb analogue prior to V6T2. */
23174 #undef THUMB_VARIANT
23175 #define THUMB_VARIANT & arm_ext_v6t2
23177 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23178 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23179 CL("teqp", 130f000, 2, (RR, SH), cmp),
23181 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23182 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23183 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
23184 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23186 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23187 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23189 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23190 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23192 /* V1 instructions with no Thumb analogue at all. */
23193 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
23194 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
23196 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
23197 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
23198 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
23199 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
23200 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
23201 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
23202 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
23203 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
23206 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23207 #undef THUMB_VARIANT
23208 #define THUMB_VARIANT & arm_ext_v4t
23210 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
23211 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
23213 #undef THUMB_VARIANT
23214 #define THUMB_VARIANT & arm_ext_v6t2
23216 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
23217 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
23219 /* Generic coprocessor instructions. */
23220 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23221 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23222 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23223 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23224 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23225 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23226 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
23229 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23231 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
23232 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
23235 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23236 #undef THUMB_VARIANT
23237 #define THUMB_VARIANT & arm_ext_msr
23239 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
23240 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
23243 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23244 #undef THUMB_VARIANT
23245 #define THUMB_VARIANT & arm_ext_v6t2
23247 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23248 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23249 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23250 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23251 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23252 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23253 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23254 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23257 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23258 #undef THUMB_VARIANT
23259 #define THUMB_VARIANT & arm_ext_v4t
23261 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23262 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23263 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23264 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23265 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23266 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23269 #define ARM_VARIANT & arm_ext_v4t_5
23271 /* ARM Architecture 4T. */
23272 /* Note: bx (and blx) are required on V5, even if the processor does
23273 not support Thumb. */
23274 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
23277 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23278 #undef THUMB_VARIANT
23279 #define THUMB_VARIANT & arm_ext_v5t
23281 /* Note: blx has 2 variants; the .value coded here is for
23282 BLX(2). Only this variant has conditional execution. */
23283 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
23284 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
23286 #undef THUMB_VARIANT
23287 #define THUMB_VARIANT & arm_ext_v6t2
23289 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
23290 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23291 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23292 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23293 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23294 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23295 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23296 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23299 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23300 #undef THUMB_VARIANT
23301 #define THUMB_VARIANT & arm_ext_v5exp
23303 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23304 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23305 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23306 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23308 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23309 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23311 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23312 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23313 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23314 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23316 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23317 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23318 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23319 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23321 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23322 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23324 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23325 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23326 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23327 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23330 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23331 #undef THUMB_VARIANT
23332 #define THUMB_VARIANT & arm_ext_v6t2
23334 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
23335 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
23337 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
23338 ADDRGLDRS), ldrd, t_ldstd),
23340 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23341 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23344 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23346 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
23349 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23350 #undef THUMB_VARIANT
23351 #define THUMB_VARIANT & arm_ext_v6
23353 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
23354 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
23355 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23356 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23357 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23358 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23359 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23360 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23361 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23362 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
23364 #undef THUMB_VARIANT
23365 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23367 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
23368 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23370 #undef THUMB_VARIANT
23371 #define THUMB_VARIANT & arm_ext_v6t2
23373 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23374 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23376 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
23377 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
23379 /* ARM V6 not included in V7M. */
23380 #undef THUMB_VARIANT
23381 #define THUMB_VARIANT & arm_ext_v6_notm
23382 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
23383 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
23384 UF(rfeib, 9900a00, 1, (RRw), rfe),
23385 UF(rfeda, 8100a00, 1, (RRw), rfe),
23386 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23387 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
23388 UF(rfefa, 8100a00, 1, (RRw), rfe),
23389 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23390 UF(rfeed, 9900a00, 1, (RRw), rfe),
23391 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23392 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23393 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23394 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
23395 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
23396 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
23397 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
23398 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
23399 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
23400 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
23402 /* ARM V6 not included in V7M (eg. integer SIMD). */
23403 #undef THUMB_VARIANT
23404 #define THUMB_VARIANT & arm_ext_v6_dsp
23405 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
23406 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
23407 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23408 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23409 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23410 /* Old name for QASX. */
23411 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23412 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23413 /* Old name for QSAX. */
23414 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23415 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23416 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23417 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23418 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23419 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23420 /* Old name for SASX. */
23421 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23422 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23423 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23424 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23425 /* Old name for SHASX. */
23426 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23427 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23428 /* Old name for SHSAX. */
23429 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23430 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23431 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23432 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23433 /* Old name for SSAX. */
23434 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23435 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23436 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23437 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23438 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23439 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23440 /* Old name for UASX. */
23441 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23442 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23443 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23444 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23445 /* Old name for UHASX. */
23446 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23447 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23448 /* Old name for UHSAX. */
23449 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23450 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23451 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23452 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23453 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23454 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23455 /* Old name for UQASX. */
23456 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23457 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23458 /* Old name for UQSAX. */
23459 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23460 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23461 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23462 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23463 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23464 /* Old name for USAX. */
23465 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23466 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23467 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23468 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23469 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23470 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23471 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23472 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23473 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23474 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23475 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23476 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23477 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23478 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23479 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23480 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23481 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23482 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23483 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23484 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23485 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23486 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23487 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23488 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23489 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23490 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23491 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23492 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23493 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23494 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
23495 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
23496 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23497 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23498 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
23501 #define ARM_VARIANT & arm_ext_v6k_v6t2
23502 #undef THUMB_VARIANT
23503 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23505 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
23506 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
23507 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
23508 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
23510 #undef THUMB_VARIANT
23511 #define THUMB_VARIANT & arm_ext_v6_notm
23512 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
23514 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
23515 RRnpcb), strexd, t_strexd),
23517 #undef THUMB_VARIANT
23518 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23519 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
23521 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
23523 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23525 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23527 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
23530 #define ARM_VARIANT & arm_ext_sec
23531 #undef THUMB_VARIANT
23532 #define THUMB_VARIANT & arm_ext_sec
23534 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
23537 #define ARM_VARIANT & arm_ext_virt
23538 #undef THUMB_VARIANT
23539 #define THUMB_VARIANT & arm_ext_virt
23541 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
23542 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
23545 #define ARM_VARIANT & arm_ext_pan
23546 #undef THUMB_VARIANT
23547 #define THUMB_VARIANT & arm_ext_pan
23549 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
23552 #define ARM_VARIANT & arm_ext_v6t2
23553 #undef THUMB_VARIANT
23554 #define THUMB_VARIANT & arm_ext_v6t2
23556 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
23557 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
23558 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23559 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23561 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
23562 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
23564 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23565 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23566 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23567 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23570 #define ARM_VARIANT & arm_ext_v3
23571 #undef THUMB_VARIANT
23572 #define THUMB_VARIANT & arm_ext_v6t2
23574 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
23575 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
23576 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
23579 #define ARM_VARIANT & arm_ext_v6t2
23580 #undef THUMB_VARIANT
23581 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23582 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
23583 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
23585 /* Thumb-only instructions. */
23587 #define ARM_VARIANT NULL
23588 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
23589 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
23591 /* ARM does not really have an IT instruction, so always allow it.
23592 The opcode is copied from Thumb in order to allow warnings in
23593 -mimplicit-it=[never | arm] modes. */
23595 #define ARM_VARIANT & arm_ext_v1
23596 #undef THUMB_VARIANT
23597 #define THUMB_VARIANT & arm_ext_v6t2
23599 TUE("it", bf08, bf08, 1, (COND), it, t_it),
23600 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
23601 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
23602 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
23603 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
23604 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
23605 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
23606 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
23607 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
23608 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
23609 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
23610 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
23611 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
23612 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
23613 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
23614 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23615 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
23616 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
23618 /* Thumb2 only instructions. */
23620 #define ARM_VARIANT NULL
23622 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23623 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
23624 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
23625 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
23626 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
23627 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
23629 /* Hardware division instructions. */
23631 #define ARM_VARIANT & arm_ext_adiv
23632 #undef THUMB_VARIANT
23633 #define THUMB_VARIANT & arm_ext_div
23635 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
23636 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
23638 /* ARM V6M/V7 instructions. */
23640 #define ARM_VARIANT & arm_ext_barrier
23641 #undef THUMB_VARIANT
23642 #define THUMB_VARIANT & arm_ext_barrier
23644 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
23645 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
23646 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
23648 /* ARM V7 instructions. */
23650 #define ARM_VARIANT & arm_ext_v7
23651 #undef THUMB_VARIANT
23652 #define THUMB_VARIANT & arm_ext_v7
23654 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
23655 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
23658 #define ARM_VARIANT & arm_ext_mp
23659 #undef THUMB_VARIANT
23660 #define THUMB_VARIANT & arm_ext_mp
23662 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
23664 /* AArchv8 instructions. */
23666 #define ARM_VARIANT & arm_ext_v8
23668 /* Instructions shared between armv8-a and armv8-m. */
23669 #undef THUMB_VARIANT
23670 #define THUMB_VARIANT & arm_ext_atomics
23672 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23673 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23674 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23675 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23676 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23677 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
23678 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23679 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
23680 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
23681 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
23683 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
23685 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
23687 #undef THUMB_VARIANT
23688 #define THUMB_VARIANT & arm_ext_v8
23690 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
23691 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
23693 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
23696 /* Defined in V8 but is in undefined encoding space for earlier
23697 architectures. However earlier architectures are required to treat
23698 this instuction as a semihosting trap as well. Hence while not explicitly
23699 defined as such, it is in fact correct to define the instruction for all
23701 #undef THUMB_VARIANT
23702 #define THUMB_VARIANT & arm_ext_v1
23704 #define ARM_VARIANT & arm_ext_v1
23705 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
23707 /* ARMv8 T32 only. */
23709 #define ARM_VARIANT NULL
23710 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
23711 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
23712 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
23714 /* FP for ARMv8. */
23716 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23717 #undef THUMB_VARIANT
23718 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23720 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
23721 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
23722 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
23723 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
23724 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
23725 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
23726 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
23727 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
23728 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
23729 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
23730 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
23732 /* Crypto v1 extensions. */
23734 #define ARM_VARIANT & fpu_crypto_ext_armv8
23735 #undef THUMB_VARIANT
23736 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23738 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
23739 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
23740 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
23741 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
23742 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
23743 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
23744 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
23745 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
23746 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
23747 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
23748 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
23749 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
23750 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
23751 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
23754 #define ARM_VARIANT & crc_ext_armv8
23755 #undef THUMB_VARIANT
23756 #define THUMB_VARIANT & crc_ext_armv8
23757 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
23758 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
23759 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
23760 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
23761 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
23762 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
23764 /* ARMv8.2 RAS extension. */
23766 #define ARM_VARIANT & arm_ext_ras
23767 #undef THUMB_VARIANT
23768 #define THUMB_VARIANT & arm_ext_ras
23769 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
23772 #define ARM_VARIANT & arm_ext_v8_3
23773 #undef THUMB_VARIANT
23774 #define THUMB_VARIANT & arm_ext_v8_3
23775 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
23778 #define ARM_VARIANT & fpu_neon_ext_dotprod
23779 #undef THUMB_VARIANT
23780 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23781 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
23782 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
23785 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23786 #undef THUMB_VARIANT
23787 #define THUMB_VARIANT NULL
23789 cCE("wfs", e200110, 1, (RR), rd),
23790 cCE("rfs", e300110, 1, (RR), rd),
23791 cCE("wfc", e400110, 1, (RR), rd),
23792 cCE("rfc", e500110, 1, (RR), rd),
23794 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
23795 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
23796 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
23797 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
23799 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
23800 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
23801 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
23802 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
23804 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
23805 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
23806 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
23807 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
23808 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
23809 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
23810 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
23811 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
23812 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
23813 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
23814 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
23815 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
23817 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
23818 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
23819 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
23820 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
23821 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
23822 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
23823 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
23824 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
23825 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
23826 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
23827 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
23828 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
23830 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
23831 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
23832 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
23833 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
23834 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
23835 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
23836 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
23837 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
23838 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
23839 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
23840 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
23841 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
23843 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
23844 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
23845 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
23846 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
23847 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
23848 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
23849 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
23850 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
23851 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
23852 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
23853 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
23854 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
23856 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
23857 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
23858 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
23859 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
23860 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
23861 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
23862 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
23863 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
23864 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
23865 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
23866 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
23867 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
23869 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
23870 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
23871 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
23872 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
23873 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
23874 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
23875 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
23876 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
23877 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
23878 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
23879 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
23880 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
23882 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
23883 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
23884 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
23885 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
23886 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
23887 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
23888 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
23889 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
23890 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
23891 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
23892 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
23893 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
23895 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
23896 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
23897 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
23898 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
23899 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
23900 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
23901 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
23902 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
23903 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
23904 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
23905 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
23906 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
23908 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
23909 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
23910 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
23911 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
23912 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
23913 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
23914 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
23915 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
23916 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
23917 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
23918 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
23919 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
23921 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
23922 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
23923 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
23924 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
23925 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
23926 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
23927 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
23928 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
23929 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
23930 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
23931 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
23932 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
23934 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
23935 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
23936 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
23937 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
23938 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
23939 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
23940 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
23941 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
23942 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
23943 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
23944 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
23945 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
23947 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
23948 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
23949 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
23950 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
23951 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
23952 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
23953 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
23954 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
23955 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
23956 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
23957 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
23958 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
23960 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
23961 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
23962 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
23963 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
23964 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
23965 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
23966 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
23967 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
23968 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
23969 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
23970 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
23971 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
23973 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
23974 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
23975 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
23976 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
23977 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
23978 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
23979 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
23980 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
23981 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
23982 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
23983 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
23984 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
23986 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
23987 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
23988 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
23989 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
23990 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
23991 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
23992 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
23993 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
23994 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
23995 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
23996 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
23997 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
23999 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
24000 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
24001 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
24002 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
24003 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
24004 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
24005 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
24006 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
24007 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
24008 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
24009 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
24010 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
24012 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
24013 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
24014 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
24015 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
24016 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
24017 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24018 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24019 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24020 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
24021 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
24022 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
24023 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
24025 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
24026 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
24027 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
24028 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
24029 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
24030 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24031 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24032 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24033 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
24034 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
24035 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
24036 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
24038 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
24039 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
24040 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
24041 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
24042 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
24043 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24044 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24045 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24046 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
24047 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
24048 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
24049 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
24051 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
24052 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
24053 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
24054 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
24055 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
24056 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24057 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24058 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24059 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
24060 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
24061 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
24062 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
24064 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
24065 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
24066 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
24067 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
24068 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
24069 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24070 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24071 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24072 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
24073 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
24074 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
24075 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
24077 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
24078 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
24079 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
24080 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
24081 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
24082 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24083 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24084 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24085 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
24086 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
24087 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
24088 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
24090 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
24091 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
24092 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
24093 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
24094 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
24095 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24096 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24097 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24098 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
24099 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
24100 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
24101 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
24103 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
24104 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
24105 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
24106 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
24107 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
24108 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24109 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24110 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24111 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
24112 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
24113 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
24114 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
24116 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
24117 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
24118 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
24119 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
24120 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
24121 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24122 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24123 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24124 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
24125 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
24126 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
24127 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
24129 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
24130 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
24131 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
24132 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
24133 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
24134 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24135 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24136 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24137 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
24138 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
24139 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
24140 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
24142 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24143 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24144 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24145 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24146 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24147 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24148 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24149 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24150 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24151 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24152 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24153 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24155 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24156 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24157 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24158 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24159 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24160 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24161 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24162 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24163 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24164 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24165 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24166 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24168 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24169 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24170 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24171 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24172 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24173 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24174 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24175 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24176 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24177 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24178 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24179 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24181 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
24182 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
24183 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
24184 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
24186 cCL("flts", e000110, 2, (RF, RR), rn_rd),
24187 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
24188 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
24189 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
24190 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
24191 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
24192 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
24193 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
24194 cCL("flte", e080110, 2, (RF, RR), rn_rd),
24195 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
24196 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
24197 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
24199 /* The implementation of the FIX instruction is broken on some
24200 assemblers, in that it accepts a precision specifier as well as a
24201 rounding specifier, despite the fact that this is meaningless.
24202 To be more compatible, we accept it as well, though of course it
24203 does not set any bits. */
24204 cCE("fix", e100110, 2, (RR, RF), rd_rm),
24205 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
24206 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
24207 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
24208 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
24209 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
24210 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
24211 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
24212 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
24213 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
24214 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
24215 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
24216 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
24218 /* Instructions that were new with the real FPA, call them V2. */
24220 #define ARM_VARIANT & fpu_fpa_ext_v2
24222 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24223 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24224 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24225 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24226 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24227 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24230 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24232 /* Moves and type conversions. */
24233 cCE("fmstat", ef1fa10, 0, (), noargs),
24234 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
24235 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
24236 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
24237 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
24238 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
24239 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24240 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
24241 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24242 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
24243 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
24245 /* Memory operations. */
24246 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
24247 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
24248 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24249 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24250 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24251 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24252 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24253 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24254 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24255 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24256 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24257 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24258 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24259 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24260 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24261 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24262 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24263 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24265 /* Monadic operations. */
24266 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
24267 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
24268 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
24270 /* Dyadic operations. */
24271 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24272 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24273 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24274 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24275 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24276 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24277 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24278 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24279 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24282 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
24283 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
24284 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
24285 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
24287 /* Double precision load/store are still present on single precision
24288 implementations. */
24289 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
24290 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
24291 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24292 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24293 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24294 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24295 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24296 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24297 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24298 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24301 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24303 /* Moves and type conversions. */
24304 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24305 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24306 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
24307 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
24308 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
24309 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
24310 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24311 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
24312 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24313 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24314 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24315 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24317 /* Monadic operations. */
24318 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24319 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24320 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24322 /* Dyadic operations. */
24323 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24324 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24325 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24326 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24327 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24328 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24329 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24330 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24331 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24334 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24335 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
24336 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24337 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
24339 /* Instructions which may belong to either the Neon or VFP instruction sets.
24340 Individual encoder functions perform additional architecture checks. */
24342 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24343 #undef THUMB_VARIANT
24344 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24346 /* These mnemonics are unique to VFP. */
24347 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
24348 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
24349 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24350 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24351 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24352 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
24353 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
24354 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
24356 /* Mnemonics shared by Neon and VFP. */
24357 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
24359 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24360 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24361 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24362 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24363 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24364 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24366 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
24367 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
24368 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
24369 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
24372 /* NOTE: All VMOV encoding is special-cased! */
24373 NCE(vmovq, 0, 1, (VMOV), neon_mov),
24375 #undef THUMB_VARIANT
24376 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24377 by different feature bits. Since we are setting the Thumb guard, we can
24378 require Thumb-1 which makes it a nop guard and set the right feature bit in
24379 do_vldr_vstr (). */
24380 #define THUMB_VARIANT & arm_ext_v4t
24381 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24382 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24385 #define ARM_VARIANT & arm_ext_fp16
24386 #undef THUMB_VARIANT
24387 #define THUMB_VARIANT & arm_ext_fp16
24388 /* New instructions added from v8.2, allowing the extraction and insertion of
24389 the upper 16 bits of a 32-bit vector register. */
24390 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
24391 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
24393 /* New backported fma/fms instructions optional in v8.2. */
24394 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
24395 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
24397 #undef THUMB_VARIANT
24398 #define THUMB_VARIANT & fpu_neon_ext_v1
24400 #define ARM_VARIANT & fpu_neon_ext_v1
24402 /* Data processing with three registers of the same length. */
24403 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24404 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
24405 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
24406 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24407 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24408 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24409 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24410 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
24411 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
24412 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
24413 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
24414 /* If not immediate, fall back to neon_dyadic_i64_su.
24415 shl should accept I8 I16 I32 I64,
24416 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24417 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
24418 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
24419 /* Logic ops, types optional & ignored. */
24420 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
24421 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
24422 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
24423 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
24424 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
24425 /* Bitfield ops, untyped. */
24426 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24427 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24428 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24429 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24430 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24431 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24432 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24433 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
24434 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
24435 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
24436 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24437 back to neon_dyadic_if_su. */
24438 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24439 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24440 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24441 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24442 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24443 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
24444 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24445 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
24446 /* Comparison. Type I8 I16 I32 F32. */
24447 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
24448 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
24449 /* As above, D registers only. */
24450 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
24451 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
24452 /* Int and float variants, signedness unimportant. */
24453 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24454 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24455 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
24456 /* Add/sub take types I8 I16 I32 I64 F32. */
24457 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
24458 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
24459 /* vtst takes sizes 8, 16, 32. */
24460 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
24461 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
24462 /* VMUL takes I8 I16 I32 F32 P8. */
24463 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
24464 /* VQD{R}MULH takes S16 S32. */
24465 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
24466 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
24467 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24468 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
24469 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24470 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
24471 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24472 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
24473 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24474 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
24475 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24476 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
24477 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24478 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
24479 /* ARM v8.1 extension. */
24480 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
24481 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
24482 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
24484 /* Two address, int/float. Types S8 S16 S32 F32. */
24485 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
24486 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
24488 /* Data processing with two registers and a shift amount. */
24489 /* Right shifts, and variants with rounding.
24490 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24491 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
24492 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
24493 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24494 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24495 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24496 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24497 /* Shift and insert. Sizes accepted 8 16 32 64. */
24498 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
24499 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
24500 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24501 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
24502 /* Right shift immediate, saturating & narrowing, with rounding variants.
24503 Types accepted S16 S32 S64 U16 U32 U64. */
24504 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24505 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24506 /* As above, unsigned. Types accepted S16 S32 S64. */
24507 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24508 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24509 /* Right shift narrowing. Types accepted I16 I32 I64. */
24510 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24511 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24512 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24513 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
24514 /* CVT with optional immediate for fixed-point variant. */
24515 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
24517 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
24519 /* Data processing, three registers of different lengths. */
24520 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24521 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
24522 /* If not scalar, fall back to neon_dyadic_long.
24523 Vector types as above, scalar types S16 S32 U16 U32. */
24524 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24525 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24526 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24527 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24528 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24529 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24530 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24531 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24532 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24533 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24534 /* Saturating doubling multiplies. Types S16 S32. */
24535 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24536 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24537 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24538 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24539 S16 S32 U16 U32. */
24540 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
24542 /* Extract. Size 8. */
24543 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
24544 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
24546 /* Two registers, miscellaneous. */
24547 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24548 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
24549 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
24550 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
24551 /* Vector replicate. Sizes 8 16 32. */
24552 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
24553 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24554 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
24555 /* VMOVN. Types I16 I32 I64. */
24556 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
24557 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24558 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
24559 /* VQMOVUN. Types S16 S32 S64. */
24560 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
24561 /* VZIP / VUZP. Sizes 8 16 32. */
24562 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
24563 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
24564 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
24565 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
24566 /* VQABS / VQNEG. Types S8 S16 S32. */
24567 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
24568 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
24569 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24570 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
24571 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
24572 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
24573 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
24574 /* Reciprocal estimates. Types U32 F16 F32. */
24575 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
24576 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
24577 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
24578 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
24579 /* VCLS. Types S8 S16 S32. */
24580 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
24581 /* VCLZ. Types I8 I16 I32. */
24582 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
24583 /* VCNT. Size 8. */
24584 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
24585 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
24586 /* Two address, untyped. */
24587 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
24588 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
24589 /* VTRN. Sizes 8 16 32. */
24590 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
24591 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
24593 /* Table lookup. Size 8. */
24594 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24595 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24597 #undef THUMB_VARIANT
24598 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24600 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24602 /* Neon element/structure load/store. */
24603 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24604 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
24605 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24606 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
24607 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24608 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
24609 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24610 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
24612 #undef THUMB_VARIANT
24613 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24615 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24616 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
24617 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24618 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24619 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24620 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24621 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24622 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24623 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
24624 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
24626 #undef THUMB_VARIANT
24627 #define THUMB_VARIANT & fpu_vfp_ext_v3
24629 #define ARM_VARIANT & fpu_vfp_ext_v3
24631 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
24632 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24633 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24634 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24635 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24636 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24637 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24638 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
24639 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
24642 #define ARM_VARIANT & fpu_vfp_ext_fma
24643 #undef THUMB_VARIANT
24644 #define THUMB_VARIANT & fpu_vfp_ext_fma
24645 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24646 VFP FMA variant; NEON and VFP FMA always includes the NEON
24647 FMA instructions. */
24648 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
24649 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
24651 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24652 the v form should always be used. */
24653 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24654 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24655 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24656 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24657 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24658 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24660 #undef THUMB_VARIANT
24662 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24664 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24665 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24666 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24667 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24668 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24669 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
24670 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
24671 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
24674 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24676 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
24677 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
24678 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
24679 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
24680 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
24681 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
24682 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
24683 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
24684 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
24685 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24686 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24687 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
24688 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24689 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24690 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
24691 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24692 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24693 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
24694 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
24695 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
24696 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24697 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24698 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24699 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24700 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24701 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
24702 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
24703 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
24704 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
24705 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
24706 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
24707 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
24708 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
24709 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
24710 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
24711 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
24712 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
24713 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24714 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24715 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24716 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24717 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24718 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24719 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24720 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24721 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24722 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
24723 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24724 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24725 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24726 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24727 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24728 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24729 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24730 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24731 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24732 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24733 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24734 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24735 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24736 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24737 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24738 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24739 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24740 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24741 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24742 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24743 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24744 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24745 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24746 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24747 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24748 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24749 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24750 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24751 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24752 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24753 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24754 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24755 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24756 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24757 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24758 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24759 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24760 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24761 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24762 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24763 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24764 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
24765 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24766 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24767 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24768 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24769 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24770 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24771 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24772 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24773 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24774 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24775 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24776 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24777 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24778 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24779 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24780 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24781 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24782 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24783 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24784 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24785 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24786 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
24787 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24788 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24789 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24790 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24791 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24792 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24793 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24794 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24795 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24796 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24797 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24798 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24799 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24800 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24801 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24802 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24803 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
24804 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
24805 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24806 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
24807 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
24808 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
24809 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24810 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24811 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24812 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24813 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24814 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24815 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24816 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24817 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24818 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
24819 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
24820 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
24821 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
24822 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
24823 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
24824 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24825 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24826 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24827 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
24828 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
24829 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
24830 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
24831 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
24832 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
24833 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24834 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24835 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24836 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24837 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
24840 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24842 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
24843 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
24844 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
24845 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
24846 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
24847 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
24848 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24849 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24850 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24851 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24852 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24853 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24854 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24855 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24856 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24857 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24858 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24859 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24860 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24861 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24862 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
24863 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24864 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24865 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24866 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24867 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24868 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24869 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24870 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24871 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24872 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24873 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24874 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24875 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24876 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24877 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24878 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24879 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24880 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24881 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24882 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24883 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24884 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24885 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24886 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24887 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24888 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24889 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24890 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24891 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24892 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24893 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24894 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24895 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24896 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24897 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24898 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
24901 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24903 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24904 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24905 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24906 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24907 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
24908 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
24909 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
24910 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
24911 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
24912 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
24913 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
24914 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
24915 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
24916 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
24917 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
24918 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
24919 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
24920 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
24921 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
24922 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
24923 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
24924 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
24925 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
24926 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
24927 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
24928 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
24929 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
24930 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
24931 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
24932 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
24933 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
24934 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
24935 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
24936 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
24937 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
24938 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
24939 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
24940 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
24941 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
24942 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
24943 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
24944 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
24945 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
24946 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
24947 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
24948 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
24949 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
24950 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
24951 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
24952 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
24953 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
24954 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
24955 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
24956 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
24957 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
24958 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
24959 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
24960 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
24961 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
24962 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
24963 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
24964 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
24965 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
24966 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
24967 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24968 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24969 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24970 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24971 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24972 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
24973 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24974 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
24975 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24976 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
24977 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24978 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
24980 /* ARMv8.5-A instructions. */
24982 #define ARM_VARIANT & arm_ext_sb
24983 #undef THUMB_VARIANT
24984 #define THUMB_VARIANT & arm_ext_sb
24985 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
24988 #define ARM_VARIANT & arm_ext_predres
24989 #undef THUMB_VARIANT
24990 #define THUMB_VARIANT & arm_ext_predres
24991 CE("cfprctx", e070f93, 1, (RRnpc), rd),
24992 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
24993 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
24995 /* ARMv8-M instructions. */
24997 #define ARM_VARIANT NULL
24998 #undef THUMB_VARIANT
24999 #define THUMB_VARIANT & arm_ext_v8m
25000 ToU("sg", e97fe97f, 0, (), noargs),
25001 ToC("blxns", 4784, 1, (RRnpc), t_blx),
25002 ToC("bxns", 4704, 1, (RRnpc), t_bx),
25003 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
25004 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
25005 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
25006 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
25008 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25009 instructions behave as nop if no VFP is present. */
25010 #undef THUMB_VARIANT
25011 #define THUMB_VARIANT & arm_ext_v8m_main
25012 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
25013 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
25015 /* Armv8.1-M Mainline instructions. */
25016 #undef THUMB_VARIANT
25017 #define THUMB_VARIANT & arm_ext_v8_1m_main
25018 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
25019 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
25020 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
25021 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
25022 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
25024 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
25025 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
25026 toU("le", _le, 2, (oLR, EXP), t_loloop),
25028 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
25029 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
25031 #undef THUMB_VARIANT
25032 #define THUMB_VARIANT & mve_ext
25034 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25035 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25036 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25037 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25038 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25039 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25040 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25041 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25042 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25043 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25044 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25045 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25046 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25047 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25048 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25050 ToC("vpst", fe710f4d, 0, (), mve_vpt),
25051 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
25052 ToC("vpste", fe718f4d, 0, (), mve_vpt),
25053 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
25054 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
25055 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
25056 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
25057 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
25058 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
25059 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
25060 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
25061 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
25062 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
25063 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
25064 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
25066 /* MVE and MVE FP only. */
25067 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
25068 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
25069 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
25070 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
25071 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
25072 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
25073 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
25074 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25075 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25076 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25077 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25078 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25079 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25080 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25081 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25082 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25083 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25085 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25086 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25087 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25088 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25089 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25090 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25091 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25092 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25093 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25094 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25095 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25096 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25097 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25098 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25099 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25100 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25101 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25102 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25103 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25104 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25106 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
25107 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
25108 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
25109 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
25110 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
25111 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
25112 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
25113 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
25114 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
25115 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
25116 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
25117 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
25118 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
25119 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
25120 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
25121 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
25122 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
25124 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25125 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25126 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25127 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25128 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25129 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25130 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25131 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25132 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25133 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25134 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25135 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25136 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25137 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25138 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25139 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25140 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25141 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25142 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25143 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25145 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
25146 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
25147 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
25148 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
25149 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
25151 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25152 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25153 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25154 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25155 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25156 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25157 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25158 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25159 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25160 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25161 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25162 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
25163 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
25164 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
25165 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
25166 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
25167 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
25169 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25170 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25171 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25172 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25173 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25174 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25175 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25176 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25177 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25178 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25179 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25180 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25182 #undef THUMB_VARIANT
25183 #define THUMB_VARIANT & mve_fp_ext
25184 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
25185 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
25186 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
25187 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
25188 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
25189 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
25190 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
25191 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
25194 #define ARM_VARIANT & fpu_vfp_ext_v1
25195 #undef THUMB_VARIANT
25196 #define THUMB_VARIANT & arm_ext_v6t2
25197 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
25198 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
25200 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25203 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25205 MNCE(vmov, 0, 1, (VMOV), neon_mov),
25206 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
25207 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
25208 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
25210 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
25211 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
25212 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
25214 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25215 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25217 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
25218 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
25220 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25221 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25224 #define ARM_VARIANT & fpu_vfp_ext_v2
25226 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
25227 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
25228 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
25229 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
25232 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25233 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
25234 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
25235 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
25236 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
25237 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
25238 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
25241 #define ARM_VARIANT & fpu_neon_ext_v1
25242 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25243 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
25244 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
25245 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
25246 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25247 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25248 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25249 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25250 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
25251 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
25252 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
25253 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
25254 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
25255 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
25256 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
25257 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25258 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25259 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
25260 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
25261 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
25262 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
25263 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
25264 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
25265 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
25266 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
25267 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
25268 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
25269 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25270 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25271 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
25272 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
25273 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
25274 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
25275 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
25276 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
25277 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
25278 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
25281 #define ARM_VARIANT & arm_ext_v8_3
25282 #undef THUMB_VARIANT
25283 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25284 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
25285 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
25288 #undef THUMB_VARIANT
25320 /* MD interface: bits in the object file. */
25322 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25323 for use in the a.out file, and stores them in the array pointed to by buf.
25324 This knows about the endian-ness of the target machine and does
25325 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25326 2 (short) and 4 (long) Floating numbers are put out as a series of
25327 LITTLENUMS (shorts, here at least). */
25330 md_number_to_chars (char * buf, valueT val, int n)
25332 if (target_big_endian)
25333 number_to_chars_bigendian (buf, val, n);
25335 number_to_chars_littleendian (buf, val, n);
25339 md_chars_to_number (char * buf, int n)
25342 unsigned char * where = (unsigned char *) buf;
25344 if (target_big_endian)
25349 result |= (*where++ & 255);
25357 result |= (where[n] & 255);
25364 /* MD interface: Sections. */
25366 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25367 that an rs_machine_dependent frag may reach. */
25370 arm_frag_max_var (fragS *fragp)
25372 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25373 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25375 Note that we generate relaxable instructions even for cases that don't
25376 really need it, like an immediate that's a trivial constant. So we're
25377 overestimating the instruction size for some of those cases. Rather
25378 than putting more intelligence here, it would probably be better to
25379 avoid generating a relaxation frag in the first place when it can be
25380 determined up front that a short instruction will suffice. */
25382 gas_assert (fragp->fr_type == rs_machine_dependent);
25386 /* Estimate the size of a frag before relaxing. Assume everything fits in
25390 md_estimate_size_before_relax (fragS * fragp,
25391 segT segtype ATTRIBUTE_UNUSED)
25397 /* Convert a machine dependent frag. */
25400 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
25402 unsigned long insn;
25403 unsigned long old_op;
25411 buf = fragp->fr_literal + fragp->fr_fix;
25413 old_op = bfd_get_16(abfd, buf);
25414 if (fragp->fr_symbol)
25416 exp.X_op = O_symbol;
25417 exp.X_add_symbol = fragp->fr_symbol;
25421 exp.X_op = O_constant;
25423 exp.X_add_number = fragp->fr_offset;
25424 opcode = fragp->fr_subtype;
25427 case T_MNEM_ldr_pc:
25428 case T_MNEM_ldr_pc2:
25429 case T_MNEM_ldr_sp:
25430 case T_MNEM_str_sp:
25437 if (fragp->fr_var == 4)
25439 insn = THUMB_OP32 (opcode);
25440 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
25442 insn |= (old_op & 0x700) << 4;
25446 insn |= (old_op & 7) << 12;
25447 insn |= (old_op & 0x38) << 13;
25449 insn |= 0x00000c00;
25450 put_thumb32_insn (buf, insn);
25451 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
25455 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
25457 pc_rel = (opcode == T_MNEM_ldr_pc2);
25460 if (fragp->fr_var == 4)
25462 insn = THUMB_OP32 (opcode);
25463 insn |= (old_op & 0xf0) << 4;
25464 put_thumb32_insn (buf, insn);
25465 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
25469 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25470 exp.X_add_number -= 4;
25478 if (fragp->fr_var == 4)
25480 int r0off = (opcode == T_MNEM_mov
25481 || opcode == T_MNEM_movs) ? 0 : 8;
25482 insn = THUMB_OP32 (opcode);
25483 insn = (insn & 0xe1ffffff) | 0x10000000;
25484 insn |= (old_op & 0x700) << r0off;
25485 put_thumb32_insn (buf, insn);
25486 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25490 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
25495 if (fragp->fr_var == 4)
25497 insn = THUMB_OP32(opcode);
25498 put_thumb32_insn (buf, insn);
25499 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
25502 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
25506 if (fragp->fr_var == 4)
25508 insn = THUMB_OP32(opcode);
25509 insn |= (old_op & 0xf00) << 14;
25510 put_thumb32_insn (buf, insn);
25511 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
25514 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
25517 case T_MNEM_add_sp:
25518 case T_MNEM_add_pc:
25519 case T_MNEM_inc_sp:
25520 case T_MNEM_dec_sp:
25521 if (fragp->fr_var == 4)
25523 /* ??? Choose between add and addw. */
25524 insn = THUMB_OP32 (opcode);
25525 insn |= (old_op & 0xf0) << 4;
25526 put_thumb32_insn (buf, insn);
25527 if (opcode == T_MNEM_add_pc)
25528 reloc_type = BFD_RELOC_ARM_T32_IMM12;
25530 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
25533 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25541 if (fragp->fr_var == 4)
25543 insn = THUMB_OP32 (opcode);
25544 insn |= (old_op & 0xf0) << 4;
25545 insn |= (old_op & 0xf) << 16;
25546 put_thumb32_insn (buf, insn);
25547 if (insn & (1 << 20))
25548 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
25550 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25553 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25559 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
25560 (enum bfd_reloc_code_real) reloc_type);
25561 fixp->fx_file = fragp->fr_file;
25562 fixp->fx_line = fragp->fr_line;
25563 fragp->fr_fix += fragp->fr_var;
25565 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25566 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
25567 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
25568 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
25571 /* Return the size of a relaxable immediate operand instruction.
25572 SHIFT and SIZE specify the form of the allowable immediate. */
25574 relax_immediate (fragS *fragp, int size, int shift)
25580 /* ??? Should be able to do better than this. */
25581 if (fragp->fr_symbol)
25584 low = (1 << shift) - 1;
25585 mask = (1 << (shift + size)) - (1 << shift);
25586 offset = fragp->fr_offset;
25587 /* Force misaligned offsets to 32-bit variant. */
25590 if (offset & ~mask)
25595 /* Get the address of a symbol during relaxation. */
25597 relaxed_symbol_addr (fragS *fragp, long stretch)
25603 sym = fragp->fr_symbol;
25604 sym_frag = symbol_get_frag (sym);
25605 know (S_GET_SEGMENT (sym) != absolute_section
25606 || sym_frag == &zero_address_frag);
25607 addr = S_GET_VALUE (sym) + fragp->fr_offset;
25609 /* If frag has yet to be reached on this pass, assume it will
25610 move by STRETCH just as we did. If this is not so, it will
25611 be because some frag between grows, and that will force
25615 && sym_frag->relax_marker != fragp->relax_marker)
25619 /* Adjust stretch for any alignment frag. Note that if have
25620 been expanding the earlier code, the symbol may be
25621 defined in what appears to be an earlier frag. FIXME:
25622 This doesn't handle the fr_subtype field, which specifies
25623 a maximum number of bytes to skip when doing an
25625 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
25627 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
25630 stretch = - ((- stretch)
25631 & ~ ((1 << (int) f->fr_offset) - 1));
25633 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
25645 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25648 relax_adr (fragS *fragp, asection *sec, long stretch)
25653 /* Assume worst case for symbols not known to be in the same section. */
25654 if (fragp->fr_symbol == NULL
25655 || !S_IS_DEFINED (fragp->fr_symbol)
25656 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25657 || S_IS_WEAK (fragp->fr_symbol))
25660 val = relaxed_symbol_addr (fragp, stretch);
25661 addr = fragp->fr_address + fragp->fr_fix;
25662 addr = (addr + 4) & ~3;
25663 /* Force misaligned targets to 32-bit variant. */
25667 if (val < 0 || val > 1020)
25672 /* Return the size of a relaxable add/sub immediate instruction. */
25674 relax_addsub (fragS *fragp, asection *sec)
25679 buf = fragp->fr_literal + fragp->fr_fix;
25680 op = bfd_get_16(sec->owner, buf);
25681 if ((op & 0xf) == ((op >> 4) & 0xf))
25682 return relax_immediate (fragp, 8, 0);
25684 return relax_immediate (fragp, 3, 0);
25687 /* Return TRUE iff the definition of symbol S could be pre-empted
25688 (overridden) at link or load time. */
25690 symbol_preemptible (symbolS *s)
25692 /* Weak symbols can always be pre-empted. */
25696 /* Non-global symbols cannot be pre-empted. */
25697 if (! S_IS_EXTERNAL (s))
25701 /* In ELF, a global symbol can be marked protected, or private. In that
25702 case it can't be pre-empted (other definitions in the same link unit
25703 would violate the ODR). */
25704 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
25708 /* Other global symbols might be pre-empted. */
25712 /* Return the size of a relaxable branch instruction. BITS is the
25713 size of the offset field in the narrow instruction. */
25716 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
25722 /* Assume worst case for symbols not known to be in the same section. */
25723 if (!S_IS_DEFINED (fragp->fr_symbol)
25724 || sec != S_GET_SEGMENT (fragp->fr_symbol)
25725 || S_IS_WEAK (fragp->fr_symbol))
25729 /* A branch to a function in ARM state will require interworking. */
25730 if (S_IS_DEFINED (fragp->fr_symbol)
25731 && ARM_IS_FUNC (fragp->fr_symbol))
25735 if (symbol_preemptible (fragp->fr_symbol))
25738 val = relaxed_symbol_addr (fragp, stretch);
25739 addr = fragp->fr_address + fragp->fr_fix + 4;
25742 /* Offset is a signed value *2 */
25744 if (val >= limit || val < -limit)
25750 /* Relax a machine dependent frag. This returns the amount by which
25751 the current size of the frag should change. */
25754 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
25759 oldsize = fragp->fr_var;
25760 switch (fragp->fr_subtype)
25762 case T_MNEM_ldr_pc2:
25763 newsize = relax_adr (fragp, sec, stretch);
25765 case T_MNEM_ldr_pc:
25766 case T_MNEM_ldr_sp:
25767 case T_MNEM_str_sp:
25768 newsize = relax_immediate (fragp, 8, 2);
25772 newsize = relax_immediate (fragp, 5, 2);
25776 newsize = relax_immediate (fragp, 5, 1);
25780 newsize = relax_immediate (fragp, 5, 0);
25783 newsize = relax_adr (fragp, sec, stretch);
25789 newsize = relax_immediate (fragp, 8, 0);
25792 newsize = relax_branch (fragp, sec, 11, stretch);
25795 newsize = relax_branch (fragp, sec, 8, stretch);
25797 case T_MNEM_add_sp:
25798 case T_MNEM_add_pc:
25799 newsize = relax_immediate (fragp, 8, 2);
25801 case T_MNEM_inc_sp:
25802 case T_MNEM_dec_sp:
25803 newsize = relax_immediate (fragp, 7, 2);
25809 newsize = relax_addsub (fragp, sec);
25815 fragp->fr_var = newsize;
25816 /* Freeze wide instructions that are at or before the same location as
25817 in the previous pass. This avoids infinite loops.
25818 Don't freeze them unconditionally because targets may be artificially
25819 misaligned by the expansion of preceding frags. */
25820 if (stretch <= 0 && newsize > 2)
25822 md_convert_frag (sec->owner, sec, fragp);
25826 return newsize - oldsize;
25829 /* Round up a section size to the appropriate boundary. */
25832 md_section_align (segT segment ATTRIBUTE_UNUSED,
25838 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25839 of an rs_align_code fragment. */
25842 arm_handle_align (fragS * fragP)
25844 static unsigned char const arm_noop[2][2][4] =
25847 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25848 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25851 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25852 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25855 static unsigned char const thumb_noop[2][2][2] =
25858 {0xc0, 0x46}, /* LE */
25859 {0x46, 0xc0}, /* BE */
25862 {0x00, 0xbf}, /* LE */
25863 {0xbf, 0x00} /* BE */
25866 static unsigned char const wide_thumb_noop[2][4] =
25867 { /* Wide Thumb-2 */
25868 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25869 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25872 unsigned bytes, fix, noop_size;
25874 const unsigned char * noop;
25875 const unsigned char *narrow_noop = NULL;
25880 if (fragP->fr_type != rs_align_code)
25883 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
25884 p = fragP->fr_literal + fragP->fr_fix;
25887 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
25888 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
25890 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
25892 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
25894 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25895 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
25897 narrow_noop = thumb_noop[1][target_big_endian];
25898 noop = wide_thumb_noop[target_big_endian];
25901 noop = thumb_noop[0][target_big_endian];
25909 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
25910 ? selected_cpu : arm_arch_none,
25912 [target_big_endian];
25919 fragP->fr_var = noop_size;
25921 if (bytes & (noop_size - 1))
25923 fix = bytes & (noop_size - 1);
25925 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
25927 memset (p, 0, fix);
25934 if (bytes & noop_size)
25936 /* Insert a narrow noop. */
25937 memcpy (p, narrow_noop, noop_size);
25939 bytes -= noop_size;
25943 /* Use wide noops for the remainder */
25947 while (bytes >= noop_size)
25949 memcpy (p, noop, noop_size);
25951 bytes -= noop_size;
25955 fragP->fr_fix += fix;
25958 /* Called from md_do_align. Used to create an alignment
25959 frag in a code section. */
25962 arm_frag_align_code (int n, int max)
25966 /* We assume that there will never be a requirement
25967 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25968 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
25973 _("alignments greater than %d bytes not supported in .text sections."),
25974 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
25975 as_fatal ("%s", err_msg);
25978 p = frag_var (rs_align_code,
25979 MAX_MEM_FOR_RS_ALIGN_CODE,
25981 (relax_substateT) max,
25988 /* Perform target specific initialisation of a frag.
25989 Note - despite the name this initialisation is not done when the frag
25990 is created, but only when its type is assigned. A frag can be created
25991 and used a long time before its type is set, so beware of assuming that
25992 this initialisation is performed first. */
25996 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
25998 /* Record whether this frag is in an ARM or a THUMB area. */
25999 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
26002 #else /* OBJ_ELF is defined. */
26004 arm_init_frag (fragS * fragP, int max_chars)
26006 bfd_boolean frag_thumb_mode;
26008 /* If the current ARM vs THUMB mode has not already
26009 been recorded into this frag then do so now. */
26010 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
26011 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
26013 /* PR 21809: Do not set a mapping state for debug sections
26014 - it just confuses other tools. */
26015 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
26018 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
26020 /* Record a mapping symbol for alignment frags. We will delete this
26021 later if the alignment ends up empty. */
26022 switch (fragP->fr_type)
26025 case rs_align_test:
26027 mapping_state_2 (MAP_DATA, max_chars);
26029 case rs_align_code:
26030 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
26037 /* When we change sections we need to issue a new mapping symbol. */
26040 arm_elf_change_section (void)
26042 /* Link an unlinked unwind index table section to the .text section. */
26043 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
26044 && elf_linked_to_section (now_seg) == NULL)
26045 elf_linked_to_section (now_seg) = text_section;
26049 arm_elf_section_type (const char * str, size_t len)
26051 if (len == 5 && strncmp (str, "exidx", 5) == 0)
26052 return SHT_ARM_EXIDX;
26057 /* Code to deal with unwinding tables. */
26059 static void add_unwind_adjustsp (offsetT);
26061 /* Generate any deferred unwind frame offset. */
26064 flush_pending_unwind (void)
26068 offset = unwind.pending_offset;
26069 unwind.pending_offset = 0;
26071 add_unwind_adjustsp (offset);
26074 /* Add an opcode to this list for this function. Two-byte opcodes should
26075 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26079 add_unwind_opcode (valueT op, int length)
26081 /* Add any deferred stack adjustment. */
26082 if (unwind.pending_offset)
26083 flush_pending_unwind ();
26085 unwind.sp_restored = 0;
26087 if (unwind.opcode_count + length > unwind.opcode_alloc)
26089 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
26090 if (unwind.opcodes)
26091 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
26092 unwind.opcode_alloc);
26094 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
26099 unwind.opcodes[unwind.opcode_count] = op & 0xff;
26101 unwind.opcode_count++;
26105 /* Add unwind opcodes to adjust the stack pointer. */
26108 add_unwind_adjustsp (offsetT offset)
26112 if (offset > 0x200)
26114 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26119 /* Long form: 0xb2, uleb128. */
26120 /* This might not fit in a word so add the individual bytes,
26121 remembering the list is built in reverse order. */
26122 o = (valueT) ((offset - 0x204) >> 2);
26124 add_unwind_opcode (0, 1);
26126 /* Calculate the uleb128 encoding of the offset. */
26130 bytes[n] = o & 0x7f;
26136 /* Add the insn. */
26138 add_unwind_opcode (bytes[n - 1], 1);
26139 add_unwind_opcode (0xb2, 1);
26141 else if (offset > 0x100)
26143 /* Two short opcodes. */
26144 add_unwind_opcode (0x3f, 1);
26145 op = (offset - 0x104) >> 2;
26146 add_unwind_opcode (op, 1);
26148 else if (offset > 0)
26150 /* Short opcode. */
26151 op = (offset - 4) >> 2;
26152 add_unwind_opcode (op, 1);
26154 else if (offset < 0)
26157 while (offset > 0x100)
26159 add_unwind_opcode (0x7f, 1);
26162 op = ((offset - 4) >> 2) | 0x40;
26163 add_unwind_opcode (op, 1);
26167 /* Finish the list of unwind opcodes for this function. */
26170 finish_unwind_opcodes (void)
26174 if (unwind.fp_used)
26176 /* Adjust sp as necessary. */
26177 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
26178 flush_pending_unwind ();
26180 /* After restoring sp from the frame pointer. */
26181 op = 0x90 | unwind.fp_reg;
26182 add_unwind_opcode (op, 1);
26185 flush_pending_unwind ();
26189 /* Start an exception table entry. If idx is nonzero this is an index table
26193 start_unwind_section (const segT text_seg, int idx)
26195 const char * text_name;
26196 const char * prefix;
26197 const char * prefix_once;
26198 const char * group_name;
26206 prefix = ELF_STRING_ARM_unwind;
26207 prefix_once = ELF_STRING_ARM_unwind_once;
26208 type = SHT_ARM_EXIDX;
26212 prefix = ELF_STRING_ARM_unwind_info;
26213 prefix_once = ELF_STRING_ARM_unwind_info_once;
26214 type = SHT_PROGBITS;
26217 text_name = segment_name (text_seg);
26218 if (streq (text_name, ".text"))
26221 if (strncmp (text_name, ".gnu.linkonce.t.",
26222 strlen (".gnu.linkonce.t.")) == 0)
26224 prefix = prefix_once;
26225 text_name += strlen (".gnu.linkonce.t.");
26228 sec_name = concat (prefix, text_name, (char *) NULL);
26234 /* Handle COMDAT group. */
26235 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
26237 group_name = elf_group_name (text_seg);
26238 if (group_name == NULL)
26240 as_bad (_("Group section `%s' has no group signature"),
26241 segment_name (text_seg));
26242 ignore_rest_of_line ();
26245 flags |= SHF_GROUP;
26249 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
26252 /* Set the section link for index tables. */
26254 elf_linked_to_section (now_seg) = text_seg;
26258 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26259 personality routine data. Returns zero, or the index table value for
26260 an inline entry. */
26263 create_unwind_entry (int have_data)
26268 /* The current word of data. */
26270 /* The number of bytes left in this word. */
26273 finish_unwind_opcodes ();
26275 /* Remember the current text section. */
26276 unwind.saved_seg = now_seg;
26277 unwind.saved_subseg = now_subseg;
26279 start_unwind_section (now_seg, 0);
26281 if (unwind.personality_routine == NULL)
26283 if (unwind.personality_index == -2)
26286 as_bad (_("handlerdata in cantunwind frame"));
26287 return 1; /* EXIDX_CANTUNWIND. */
26290 /* Use a default personality routine if none is specified. */
26291 if (unwind.personality_index == -1)
26293 if (unwind.opcode_count > 3)
26294 unwind.personality_index = 1;
26296 unwind.personality_index = 0;
26299 /* Space for the personality routine entry. */
26300 if (unwind.personality_index == 0)
26302 if (unwind.opcode_count > 3)
26303 as_bad (_("too many unwind opcodes for personality routine 0"));
26307 /* All the data is inline in the index table. */
26310 while (unwind.opcode_count > 0)
26312 unwind.opcode_count--;
26313 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26317 /* Pad with "finish" opcodes. */
26319 data = (data << 8) | 0xb0;
26326 /* We get two opcodes "free" in the first word. */
26327 size = unwind.opcode_count - 2;
26331 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26332 if (unwind.personality_index != -1)
26334 as_bad (_("attempt to recreate an unwind entry"));
26338 /* An extra byte is required for the opcode count. */
26339 size = unwind.opcode_count + 1;
26342 size = (size + 3) >> 2;
26344 as_bad (_("too many unwind opcodes"));
26346 frag_align (2, 0, 0);
26347 record_alignment (now_seg, 2);
26348 unwind.table_entry = expr_build_dot ();
26350 /* Allocate the table entry. */
26351 ptr = frag_more ((size << 2) + 4);
26352 /* PR 13449: Zero the table entries in case some of them are not used. */
26353 memset (ptr, 0, (size << 2) + 4);
26354 where = frag_now_fix () - ((size << 2) + 4);
26356 switch (unwind.personality_index)
26359 /* ??? Should this be a PLT generating relocation? */
26360 /* Custom personality routine. */
26361 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
26362 BFD_RELOC_ARM_PREL31);
26367 /* Set the first byte to the number of additional words. */
26368 data = size > 0 ? size - 1 : 0;
26372 /* ABI defined personality routines. */
26374 /* Three opcodes bytes are packed into the first word. */
26381 /* The size and first two opcode bytes go in the first word. */
26382 data = ((0x80 + unwind.personality_index) << 8) | size;
26387 /* Should never happen. */
26391 /* Pack the opcodes into words (MSB first), reversing the list at the same
26393 while (unwind.opcode_count > 0)
26397 md_number_to_chars (ptr, data, 4);
26402 unwind.opcode_count--;
26404 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26407 /* Finish off the last word. */
26410 /* Pad with "finish" opcodes. */
26412 data = (data << 8) | 0xb0;
26414 md_number_to_chars (ptr, data, 4);
26419 /* Add an empty descriptor if there is no user-specified data. */
26420 ptr = frag_more (4);
26421 md_number_to_chars (ptr, 0, 4);
26428 /* Initialize the DWARF-2 unwind information for this procedure. */
26431 tc_arm_frame_initial_instructions (void)
26433 cfi_add_CFA_def_cfa (REG_SP, 0);
26435 #endif /* OBJ_ELF */
26437 /* Convert REGNAME to a DWARF-2 register number. */
26440 tc_arm_regname_to_dw2regnum (char *regname)
26442 int reg = arm_reg_parse (®name, REG_TYPE_RN);
26446 /* PR 16694: Allow VFP registers as well. */
26447 reg = arm_reg_parse (®name, REG_TYPE_VFS);
26451 reg = arm_reg_parse (®name, REG_TYPE_VFD);
26460 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
26464 exp.X_op = O_secrel;
26465 exp.X_add_symbol = symbol;
26466 exp.X_add_number = 0;
26467 emit_expr (&exp, size);
26471 /* MD interface: Symbol and relocation handling. */
26473 /* Return the address within the segment that a PC-relative fixup is
26474 relative to. For ARM, PC-relative fixups applied to instructions
26475 are generally relative to the location of the fixup plus 8 bytes.
26476 Thumb branches are offset by 4, and Thumb loads relative to PC
26477 require special handling. */
26480 md_pcrel_from_section (fixS * fixP, segT seg)
26482 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
26484 /* If this is pc-relative and we are going to emit a relocation
26485 then we just want to put out any pipeline compensation that the linker
26486 will need. Otherwise we want to use the calculated base.
26487 For WinCE we skip the bias for externals as well, since this
26488 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26490 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
26491 || (arm_force_relocation (fixP)
26493 && !S_IS_EXTERNAL (fixP->fx_addsy)
26499 switch (fixP->fx_r_type)
26501 /* PC relative addressing on the Thumb is slightly odd as the
26502 bottom two bits of the PC are forced to zero for the
26503 calculation. This happens *after* application of the
26504 pipeline offset. However, Thumb adrl already adjusts for
26505 this, so we need not do it again. */
26506 case BFD_RELOC_ARM_THUMB_ADD:
26509 case BFD_RELOC_ARM_THUMB_OFFSET:
26510 case BFD_RELOC_ARM_T32_OFFSET_IMM:
26511 case BFD_RELOC_ARM_T32_ADD_PC12:
26512 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
26513 return (base + 4) & ~3;
26515 /* Thumb branches are simply offset by +4. */
26516 case BFD_RELOC_THUMB_PCREL_BRANCH5:
26517 case BFD_RELOC_THUMB_PCREL_BRANCH7:
26518 case BFD_RELOC_THUMB_PCREL_BRANCH9:
26519 case BFD_RELOC_THUMB_PCREL_BRANCH12:
26520 case BFD_RELOC_THUMB_PCREL_BRANCH20:
26521 case BFD_RELOC_THUMB_PCREL_BRANCH25:
26522 case BFD_RELOC_THUMB_PCREL_BFCSEL:
26523 case BFD_RELOC_ARM_THUMB_BF17:
26524 case BFD_RELOC_ARM_THUMB_BF19:
26525 case BFD_RELOC_ARM_THUMB_BF13:
26526 case BFD_RELOC_ARM_THUMB_LOOP12:
26529 case BFD_RELOC_THUMB_PCREL_BRANCH23:
26531 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26532 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26533 && ARM_IS_FUNC (fixP->fx_addsy)
26534 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26535 base = fixP->fx_where + fixP->fx_frag->fr_address;
26538 /* BLX is like branches above, but forces the low two bits of PC to
26540 case BFD_RELOC_THUMB_PCREL_BLX:
26542 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26543 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26544 && THUMB_IS_FUNC (fixP->fx_addsy)
26545 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26546 base = fixP->fx_where + fixP->fx_frag->fr_address;
26547 return (base + 4) & ~3;
26549 /* ARM mode branches are offset by +8. However, the Windows CE
26550 loader expects the relocation not to take this into account. */
26551 case BFD_RELOC_ARM_PCREL_BLX:
26553 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26554 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26555 && ARM_IS_FUNC (fixP->fx_addsy)
26556 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26557 base = fixP->fx_where + fixP->fx_frag->fr_address;
26560 case BFD_RELOC_ARM_PCREL_CALL:
26562 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26563 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
26564 && THUMB_IS_FUNC (fixP->fx_addsy)
26565 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26566 base = fixP->fx_where + fixP->fx_frag->fr_address;
26569 case BFD_RELOC_ARM_PCREL_BRANCH:
26570 case BFD_RELOC_ARM_PCREL_JUMP:
26571 case BFD_RELOC_ARM_PLT32:
26573 /* When handling fixups immediately, because we have already
26574 discovered the value of a symbol, or the address of the frag involved
26575 we must account for the offset by +8, as the OS loader will never see the reloc.
26576 see fixup_segment() in write.c
26577 The S_IS_EXTERNAL test handles the case of global symbols.
26578 Those need the calculated base, not just the pipe compensation the linker will need. */
26580 && fixP->fx_addsy != NULL
26581 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
26582 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
26590 /* ARM mode loads relative to PC are also offset by +8. Unlike
26591 branches, the Windows CE loader *does* expect the relocation
26592 to take this into account. */
26593 case BFD_RELOC_ARM_OFFSET_IMM:
26594 case BFD_RELOC_ARM_OFFSET_IMM8:
26595 case BFD_RELOC_ARM_HWLITERAL:
26596 case BFD_RELOC_ARM_LITERAL:
26597 case BFD_RELOC_ARM_CP_OFF_IMM:
26601 /* Other PC-relative relocations are un-offset. */
26607 static bfd_boolean flag_warn_syms = TRUE;
26610 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
26612 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26613 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26614 does mean that the resulting code might be very confusing to the reader.
26615 Also this warning can be triggered if the user omits an operand before
26616 an immediate address, eg:
26620 GAS treats this as an assignment of the value of the symbol foo to a
26621 symbol LDR, and so (without this code) it will not issue any kind of
26622 warning or error message.
26624 Note - ARM instructions are case-insensitive but the strings in the hash
26625 table are all stored in lower case, so we must first ensure that name is
26627 if (flag_warn_syms && arm_ops_hsh)
26629 char * nbuf = strdup (name);
26632 for (p = nbuf; *p; p++)
26634 if (hash_find (arm_ops_hsh, nbuf) != NULL)
26636 static struct hash_control * already_warned = NULL;
26638 if (already_warned == NULL)
26639 already_warned = hash_new ();
26640 /* Only warn about the symbol once. To keep the code
26641 simple we let hash_insert do the lookup for us. */
26642 if (hash_insert (already_warned, nbuf, NULL) == NULL)
26643 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
26652 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26653 Otherwise we have no need to default values of symbols. */
26656 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
26659 if (name[0] == '_' && name[1] == 'G'
26660 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
26664 if (symbol_find (name))
26665 as_bad (_("GOT already in the symbol table"));
26667 GOT_symbol = symbol_new (name, undefined_section,
26668 (valueT) 0, & zero_address_frag);
26678 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26679 computed as two separate immediate values, added together. We
26680 already know that this value cannot be computed by just one ARM
26683 static unsigned int
26684 validate_immediate_twopart (unsigned int val,
26685 unsigned int * highpart)
26690 for (i = 0; i < 32; i += 2)
26691 if (((a = rotate_left (val, i)) & 0xff) != 0)
26697 * highpart = (a >> 8) | ((i + 24) << 7);
26699 else if (a & 0xff0000)
26701 if (a & 0xff000000)
26703 * highpart = (a >> 16) | ((i + 16) << 7);
26707 gas_assert (a & 0xff000000);
26708 * highpart = (a >> 24) | ((i + 8) << 7);
26711 return (a & 0xff) | (i << 7);
26718 validate_offset_imm (unsigned int val, int hwse)
26720 if ((hwse && val > 255) || val > 4095)
26725 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26726 negative immediate constant by altering the instruction. A bit of
26731 by inverting the second operand, and
26734 by negating the second operand. */
26737 negate_data_op (unsigned long * instruction,
26738 unsigned long value)
26741 unsigned long negated, inverted;
26743 negated = encode_arm_immediate (-value);
26744 inverted = encode_arm_immediate (~value);
26746 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
26749 /* First negates. */
26750 case OPCODE_SUB: /* ADD <-> SUB */
26751 new_inst = OPCODE_ADD;
26756 new_inst = OPCODE_SUB;
26760 case OPCODE_CMP: /* CMP <-> CMN */
26761 new_inst = OPCODE_CMN;
26766 new_inst = OPCODE_CMP;
26770 /* Now Inverted ops. */
26771 case OPCODE_MOV: /* MOV <-> MVN */
26772 new_inst = OPCODE_MVN;
26777 new_inst = OPCODE_MOV;
26781 case OPCODE_AND: /* AND <-> BIC */
26782 new_inst = OPCODE_BIC;
26787 new_inst = OPCODE_AND;
26791 case OPCODE_ADC: /* ADC <-> SBC */
26792 new_inst = OPCODE_SBC;
26797 new_inst = OPCODE_ADC;
26801 /* We cannot do anything. */
26806 if (value == (unsigned) FAIL)
26809 *instruction &= OPCODE_MASK;
26810 *instruction |= new_inst << DATA_OP_SHIFT;
26814 /* Like negate_data_op, but for Thumb-2. */
26816 static unsigned int
26817 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
26821 unsigned int negated, inverted;
26823 negated = encode_thumb32_immediate (-value);
26824 inverted = encode_thumb32_immediate (~value);
26826 rd = (*instruction >> 8) & 0xf;
26827 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
26830 /* ADD <-> SUB. Includes CMP <-> CMN. */
26831 case T2_OPCODE_SUB:
26832 new_inst = T2_OPCODE_ADD;
26836 case T2_OPCODE_ADD:
26837 new_inst = T2_OPCODE_SUB;
26841 /* ORR <-> ORN. Includes MOV <-> MVN. */
26842 case T2_OPCODE_ORR:
26843 new_inst = T2_OPCODE_ORN;
26847 case T2_OPCODE_ORN:
26848 new_inst = T2_OPCODE_ORR;
26852 /* AND <-> BIC. TST has no inverted equivalent. */
26853 case T2_OPCODE_AND:
26854 new_inst = T2_OPCODE_BIC;
26861 case T2_OPCODE_BIC:
26862 new_inst = T2_OPCODE_AND;
26867 case T2_OPCODE_ADC:
26868 new_inst = T2_OPCODE_SBC;
26872 case T2_OPCODE_SBC:
26873 new_inst = T2_OPCODE_ADC;
26877 /* We cannot do anything. */
26882 if (value == (unsigned int)FAIL)
26885 *instruction &= T2_OPCODE_MASK;
26886 *instruction |= new_inst << T2_DATA_OP_SHIFT;
26890 /* Read a 32-bit thumb instruction from buf. */
26892 static unsigned long
26893 get_thumb32_insn (char * buf)
26895 unsigned long insn;
26896 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
26897 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26902 /* We usually want to set the low bit on the address of thumb function
26903 symbols. In particular .word foo - . should have the low bit set.
26904 Generic code tries to fold the difference of two symbols to
26905 a constant. Prevent this and force a relocation when the first symbols
26906 is a thumb function. */
26909 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
26911 if (op == O_subtract
26912 && l->X_op == O_symbol
26913 && r->X_op == O_symbol
26914 && THUMB_IS_FUNC (l->X_add_symbol))
26916 l->X_op = O_subtract;
26917 l->X_op_symbol = r->X_add_symbol;
26918 l->X_add_number -= r->X_add_number;
26922 /* Process as normal. */
26926 /* Encode Thumb2 unconditional branches and calls. The encoding
26927 for the 2 are identical for the immediate values. */
26930 encode_thumb2_b_bl_offset (char * buf, offsetT value)
26932 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26935 addressT S, I1, I2, lo, hi;
26937 S = (value >> 24) & 0x01;
26938 I1 = (value >> 23) & 0x01;
26939 I2 = (value >> 22) & 0x01;
26940 hi = (value >> 12) & 0x3ff;
26941 lo = (value >> 1) & 0x7ff;
26942 newval = md_chars_to_number (buf, THUMB_SIZE);
26943 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
26944 newval |= (S << 10) | hi;
26945 newval2 &= ~T2I1I2MASK;
26946 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
26947 md_number_to_chars (buf, newval, THUMB_SIZE);
26948 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
26952 md_apply_fix (fixS * fixP,
26956 offsetT value = * valP;
26958 unsigned int newimm;
26959 unsigned long temp;
26961 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
26963 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
26965 /* Note whether this will delete the relocation. */
26967 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
26970 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26971 consistency with the behaviour on 32-bit hosts. Remember value
26973 value &= 0xffffffff;
26974 value ^= 0x80000000;
26975 value -= 0x80000000;
26978 fixP->fx_addnumber = value;
26980 /* Same treatment for fixP->fx_offset. */
26981 fixP->fx_offset &= 0xffffffff;
26982 fixP->fx_offset ^= 0x80000000;
26983 fixP->fx_offset -= 0x80000000;
26985 switch (fixP->fx_r_type)
26987 case BFD_RELOC_NONE:
26988 /* This will need to go in the object file. */
26992 case BFD_RELOC_ARM_IMMEDIATE:
26993 /* We claim that this fixup has been processed here,
26994 even if in fact we generate an error because we do
26995 not have a reloc for it, so tc_gen_reloc will reject it. */
26998 if (fixP->fx_addsy)
27000 const char *msg = 0;
27002 if (! S_IS_DEFINED (fixP->fx_addsy))
27003 msg = _("undefined symbol %s used as an immediate value");
27004 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27005 msg = _("symbol %s is in a different section");
27006 else if (S_IS_WEAK (fixP->fx_addsy))
27007 msg = _("symbol %s is weak and may be overridden later");
27011 as_bad_where (fixP->fx_file, fixP->fx_line,
27012 msg, S_GET_NAME (fixP->fx_addsy));
27017 temp = md_chars_to_number (buf, INSN_SIZE);
27019 /* If the offset is negative, we should use encoding A2 for ADR. */
27020 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
27021 newimm = negate_data_op (&temp, value);
27024 newimm = encode_arm_immediate (value);
27026 /* If the instruction will fail, see if we can fix things up by
27027 changing the opcode. */
27028 if (newimm == (unsigned int) FAIL)
27029 newimm = negate_data_op (&temp, value);
27030 /* MOV accepts both ARM modified immediate (A1 encoding) and
27031 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27032 When disassembling, MOV is preferred when there is no encoding
27034 if (newimm == (unsigned int) FAIL
27035 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
27036 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
27037 && !((temp >> SBIT_SHIFT) & 0x1)
27038 && value >= 0 && value <= 0xffff)
27040 /* Clear bits[23:20] to change encoding from A1 to A2. */
27041 temp &= 0xff0fffff;
27042 /* Encoding high 4bits imm. Code below will encode the remaining
27044 temp |= (value & 0x0000f000) << 4;
27045 newimm = value & 0x00000fff;
27049 if (newimm == (unsigned int) FAIL)
27051 as_bad_where (fixP->fx_file, fixP->fx_line,
27052 _("invalid constant (%lx) after fixup"),
27053 (unsigned long) value);
27057 newimm |= (temp & 0xfffff000);
27058 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
27061 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
27063 unsigned int highpart = 0;
27064 unsigned int newinsn = 0xe1a00000; /* nop. */
27066 if (fixP->fx_addsy)
27068 const char *msg = 0;
27070 if (! S_IS_DEFINED (fixP->fx_addsy))
27071 msg = _("undefined symbol %s used as an immediate value");
27072 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27073 msg = _("symbol %s is in a different section");
27074 else if (S_IS_WEAK (fixP->fx_addsy))
27075 msg = _("symbol %s is weak and may be overridden later");
27079 as_bad_where (fixP->fx_file, fixP->fx_line,
27080 msg, S_GET_NAME (fixP->fx_addsy));
27085 newimm = encode_arm_immediate (value);
27086 temp = md_chars_to_number (buf, INSN_SIZE);
27088 /* If the instruction will fail, see if we can fix things up by
27089 changing the opcode. */
27090 if (newimm == (unsigned int) FAIL
27091 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
27093 /* No ? OK - try using two ADD instructions to generate
27095 newimm = validate_immediate_twopart (value, & highpart);
27097 /* Yes - then make sure that the second instruction is
27099 if (newimm != (unsigned int) FAIL)
27101 /* Still No ? Try using a negated value. */
27102 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
27103 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
27104 /* Otherwise - give up. */
27107 as_bad_where (fixP->fx_file, fixP->fx_line,
27108 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27113 /* Replace the first operand in the 2nd instruction (which
27114 is the PC) with the destination register. We have
27115 already added in the PC in the first instruction and we
27116 do not want to do it again. */
27117 newinsn &= ~ 0xf0000;
27118 newinsn |= ((newinsn & 0x0f000) << 4);
27121 newimm |= (temp & 0xfffff000);
27122 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
27124 highpart |= (newinsn & 0xfffff000);
27125 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
27129 case BFD_RELOC_ARM_OFFSET_IMM:
27130 if (!fixP->fx_done && seg->use_rela_p)
27132 /* Fall through. */
27134 case BFD_RELOC_ARM_LITERAL:
27140 if (validate_offset_imm (value, 0) == FAIL)
27142 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
27143 as_bad_where (fixP->fx_file, fixP->fx_line,
27144 _("invalid literal constant: pool needs to be closer"));
27146 as_bad_where (fixP->fx_file, fixP->fx_line,
27147 _("bad immediate value for offset (%ld)"),
27152 newval = md_chars_to_number (buf, INSN_SIZE);
27154 newval &= 0xfffff000;
27157 newval &= 0xff7ff000;
27158 newval |= value | (sign ? INDEX_UP : 0);
27160 md_number_to_chars (buf, newval, INSN_SIZE);
27163 case BFD_RELOC_ARM_OFFSET_IMM8:
27164 case BFD_RELOC_ARM_HWLITERAL:
27170 if (validate_offset_imm (value, 1) == FAIL)
27172 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
27173 as_bad_where (fixP->fx_file, fixP->fx_line,
27174 _("invalid literal constant: pool needs to be closer"));
27176 as_bad_where (fixP->fx_file, fixP->fx_line,
27177 _("bad immediate value for 8-bit offset (%ld)"),
27182 newval = md_chars_to_number (buf, INSN_SIZE);
27184 newval &= 0xfffff0f0;
27187 newval &= 0xff7ff0f0;
27188 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
27190 md_number_to_chars (buf, newval, INSN_SIZE);
27193 case BFD_RELOC_ARM_T32_OFFSET_U8:
27194 if (value < 0 || value > 1020 || value % 4 != 0)
27195 as_bad_where (fixP->fx_file, fixP->fx_line,
27196 _("bad immediate value for offset (%ld)"), (long) value);
27199 newval = md_chars_to_number (buf+2, THUMB_SIZE);
27201 md_number_to_chars (buf+2, newval, THUMB_SIZE);
27204 case BFD_RELOC_ARM_T32_OFFSET_IMM:
27205 /* This is a complicated relocation used for all varieties of Thumb32
27206 load/store instruction with immediate offset:
27208 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27209 *4, optional writeback(W)
27210 (doubleword load/store)
27212 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27213 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27214 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27215 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27216 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27218 Uppercase letters indicate bits that are already encoded at
27219 this point. Lowercase letters are our problem. For the
27220 second block of instructions, the secondary opcode nybble
27221 (bits 8..11) is present, and bit 23 is zero, even if this is
27222 a PC-relative operation. */
27223 newval = md_chars_to_number (buf, THUMB_SIZE);
27225 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
27227 if ((newval & 0xf0000000) == 0xe0000000)
27229 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27231 newval |= (1 << 23);
27234 if (value % 4 != 0)
27236 as_bad_where (fixP->fx_file, fixP->fx_line,
27237 _("offset not a multiple of 4"));
27243 as_bad_where (fixP->fx_file, fixP->fx_line,
27244 _("offset out of range"));
27249 else if ((newval & 0x000f0000) == 0x000f0000)
27251 /* PC-relative, 12-bit offset. */
27253 newval |= (1 << 23);
27258 as_bad_where (fixP->fx_file, fixP->fx_line,
27259 _("offset out of range"));
27264 else if ((newval & 0x00000100) == 0x00000100)
27266 /* Writeback: 8-bit, +/- offset. */
27268 newval |= (1 << 9);
27273 as_bad_where (fixP->fx_file, fixP->fx_line,
27274 _("offset out of range"));
27279 else if ((newval & 0x00000f00) == 0x00000e00)
27281 /* T-instruction: positive 8-bit offset. */
27282 if (value < 0 || value > 0xff)
27284 as_bad_where (fixP->fx_file, fixP->fx_line,
27285 _("offset out of range"));
27293 /* Positive 12-bit or negative 8-bit offset. */
27297 newval |= (1 << 23);
27307 as_bad_where (fixP->fx_file, fixP->fx_line,
27308 _("offset out of range"));
27315 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
27316 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
27319 case BFD_RELOC_ARM_SHIFT_IMM:
27320 newval = md_chars_to_number (buf, INSN_SIZE);
27321 if (((unsigned long) value) > 32
27323 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
27325 as_bad_where (fixP->fx_file, fixP->fx_line,
27326 _("shift expression is too large"));
27331 /* Shifts of zero must be done as lsl. */
27333 else if (value == 32)
27335 newval &= 0xfffff07f;
27336 newval |= (value & 0x1f) << 7;
27337 md_number_to_chars (buf, newval, INSN_SIZE);
27340 case BFD_RELOC_ARM_T32_IMMEDIATE:
27341 case BFD_RELOC_ARM_T32_ADD_IMM:
27342 case BFD_RELOC_ARM_T32_IMM12:
27343 case BFD_RELOC_ARM_T32_ADD_PC12:
27344 /* We claim that this fixup has been processed here,
27345 even if in fact we generate an error because we do
27346 not have a reloc for it, so tc_gen_reloc will reject it. */
27350 && ! S_IS_DEFINED (fixP->fx_addsy))
27352 as_bad_where (fixP->fx_file, fixP->fx_line,
27353 _("undefined symbol %s used as an immediate value"),
27354 S_GET_NAME (fixP->fx_addsy));
27358 newval = md_chars_to_number (buf, THUMB_SIZE);
27360 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
27363 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
27364 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27365 Thumb2 modified immediate encoding (T2). */
27366 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
27367 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
27369 newimm = encode_thumb32_immediate (value);
27370 if (newimm == (unsigned int) FAIL)
27371 newimm = thumb32_negate_data_op (&newval, value);
27373 if (newimm == (unsigned int) FAIL)
27375 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
27377 /* Turn add/sum into addw/subw. */
27378 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
27379 newval = (newval & 0xfeffffff) | 0x02000000;
27380 /* No flat 12-bit imm encoding for addsw/subsw. */
27381 if ((newval & 0x00100000) == 0)
27383 /* 12 bit immediate for addw/subw. */
27387 newval ^= 0x00a00000;
27390 newimm = (unsigned int) FAIL;
27397 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27398 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27399 disassembling, MOV is preferred when there is no encoding
27401 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
27402 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27403 but with the Rn field [19:16] set to 1111. */
27404 && (((newval >> 16) & 0xf) == 0xf)
27405 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
27406 && !((newval >> T2_SBIT_SHIFT) & 0x1)
27407 && value >= 0 && value <= 0xffff)
27409 /* Toggle bit[25] to change encoding from T2 to T3. */
27411 /* Clear bits[19:16]. */
27412 newval &= 0xfff0ffff;
27413 /* Encoding high 4bits imm. Code below will encode the
27414 remaining low 12bits. */
27415 newval |= (value & 0x0000f000) << 4;
27416 newimm = value & 0x00000fff;
27421 if (newimm == (unsigned int)FAIL)
27423 as_bad_where (fixP->fx_file, fixP->fx_line,
27424 _("invalid constant (%lx) after fixup"),
27425 (unsigned long) value);
27429 newval |= (newimm & 0x800) << 15;
27430 newval |= (newimm & 0x700) << 4;
27431 newval |= (newimm & 0x0ff);
27433 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
27434 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
27437 case BFD_RELOC_ARM_SMC:
27438 if (((unsigned long) value) > 0xffff)
27439 as_bad_where (fixP->fx_file, fixP->fx_line,
27440 _("invalid smc expression"));
27441 newval = md_chars_to_number (buf, INSN_SIZE);
27442 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27443 md_number_to_chars (buf, newval, INSN_SIZE);
27446 case BFD_RELOC_ARM_HVC:
27447 if (((unsigned long) value) > 0xffff)
27448 as_bad_where (fixP->fx_file, fixP->fx_line,
27449 _("invalid hvc expression"));
27450 newval = md_chars_to_number (buf, INSN_SIZE);
27451 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27452 md_number_to_chars (buf, newval, INSN_SIZE);
27455 case BFD_RELOC_ARM_SWI:
27456 if (fixP->tc_fix_data != 0)
27458 if (((unsigned long) value) > 0xff)
27459 as_bad_where (fixP->fx_file, fixP->fx_line,
27460 _("invalid swi expression"));
27461 newval = md_chars_to_number (buf, THUMB_SIZE);
27463 md_number_to_chars (buf, newval, THUMB_SIZE);
27467 if (((unsigned long) value) > 0x00ffffff)
27468 as_bad_where (fixP->fx_file, fixP->fx_line,
27469 _("invalid swi expression"));
27470 newval = md_chars_to_number (buf, INSN_SIZE);
27472 md_number_to_chars (buf, newval, INSN_SIZE);
27476 case BFD_RELOC_ARM_MULTI:
27477 if (((unsigned long) value) > 0xffff)
27478 as_bad_where (fixP->fx_file, fixP->fx_line,
27479 _("invalid expression in load/store multiple"));
27480 newval = value | md_chars_to_number (buf, INSN_SIZE);
27481 md_number_to_chars (buf, newval, INSN_SIZE);
27485 case BFD_RELOC_ARM_PCREL_CALL:
27487 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27489 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27490 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27491 && THUMB_IS_FUNC (fixP->fx_addsy))
27492 /* Flip the bl to blx. This is a simple flip
27493 bit here because we generate PCREL_CALL for
27494 unconditional bls. */
27496 newval = md_chars_to_number (buf, INSN_SIZE);
27497 newval = newval | 0x10000000;
27498 md_number_to_chars (buf, newval, INSN_SIZE);
27504 goto arm_branch_common;
27506 case BFD_RELOC_ARM_PCREL_JUMP:
27507 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27509 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27510 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27511 && THUMB_IS_FUNC (fixP->fx_addsy))
27513 /* This would map to a bl<cond>, b<cond>,
27514 b<always> to a Thumb function. We
27515 need to force a relocation for this particular
27517 newval = md_chars_to_number (buf, INSN_SIZE);
27520 /* Fall through. */
27522 case BFD_RELOC_ARM_PLT32:
27524 case BFD_RELOC_ARM_PCREL_BRANCH:
27526 goto arm_branch_common;
27528 case BFD_RELOC_ARM_PCREL_BLX:
27531 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27533 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27534 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27535 && ARM_IS_FUNC (fixP->fx_addsy))
27537 /* Flip the blx to a bl and warn. */
27538 const char *name = S_GET_NAME (fixP->fx_addsy);
27539 newval = 0xeb000000;
27540 as_warn_where (fixP->fx_file, fixP->fx_line,
27541 _("blx to '%s' an ARM ISA state function changed to bl"),
27543 md_number_to_chars (buf, newval, INSN_SIZE);
27549 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
27550 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
27554 /* We are going to store value (shifted right by two) in the
27555 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27556 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27559 as_bad_where (fixP->fx_file, fixP->fx_line,
27560 _("misaligned branch destination"));
27561 if ((value & (offsetT)0xfe000000) != (offsetT)0
27562 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
27563 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27565 if (fixP->fx_done || !seg->use_rela_p)
27567 newval = md_chars_to_number (buf, INSN_SIZE);
27568 newval |= (value >> 2) & 0x00ffffff;
27569 /* Set the H bit on BLX instructions. */
27573 newval |= 0x01000000;
27575 newval &= ~0x01000000;
27577 md_number_to_chars (buf, newval, INSN_SIZE);
27581 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
27582 /* CBZ can only branch forward. */
27584 /* Attempts to use CBZ to branch to the next instruction
27585 (which, strictly speaking, are prohibited) will be turned into
27588 FIXME: It may be better to remove the instruction completely and
27589 perform relaxation. */
27592 newval = md_chars_to_number (buf, THUMB_SIZE);
27593 newval = 0xbf00; /* NOP encoding T1 */
27594 md_number_to_chars (buf, newval, THUMB_SIZE);
27599 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27601 if (fixP->fx_done || !seg->use_rela_p)
27603 newval = md_chars_to_number (buf, THUMB_SIZE);
27604 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
27605 md_number_to_chars (buf, newval, THUMB_SIZE);
27610 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
27611 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
27612 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27614 if (fixP->fx_done || !seg->use_rela_p)
27616 newval = md_chars_to_number (buf, THUMB_SIZE);
27617 newval |= (value & 0x1ff) >> 1;
27618 md_number_to_chars (buf, newval, THUMB_SIZE);
27622 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
27623 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
27624 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27626 if (fixP->fx_done || !seg->use_rela_p)
27628 newval = md_chars_to_number (buf, THUMB_SIZE);
27629 newval |= (value & 0xfff) >> 1;
27630 md_number_to_chars (buf, newval, THUMB_SIZE);
27634 case BFD_RELOC_THUMB_PCREL_BRANCH20:
27636 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27637 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27638 && ARM_IS_FUNC (fixP->fx_addsy)
27639 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27641 /* Force a relocation for a branch 20 bits wide. */
27644 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
27645 as_bad_where (fixP->fx_file, fixP->fx_line,
27646 _("conditional branch out of range"));
27648 if (fixP->fx_done || !seg->use_rela_p)
27651 addressT S, J1, J2, lo, hi;
27653 S = (value & 0x00100000) >> 20;
27654 J2 = (value & 0x00080000) >> 19;
27655 J1 = (value & 0x00040000) >> 18;
27656 hi = (value & 0x0003f000) >> 12;
27657 lo = (value & 0x00000ffe) >> 1;
27659 newval = md_chars_to_number (buf, THUMB_SIZE);
27660 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27661 newval |= (S << 10) | hi;
27662 newval2 |= (J1 << 13) | (J2 << 11) | lo;
27663 md_number_to_chars (buf, newval, THUMB_SIZE);
27664 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27668 case BFD_RELOC_THUMB_PCREL_BLX:
27669 /* If there is a blx from a thumb state function to
27670 another thumb function flip this to a bl and warn
27674 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27675 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27676 && THUMB_IS_FUNC (fixP->fx_addsy))
27678 const char *name = S_GET_NAME (fixP->fx_addsy);
27679 as_warn_where (fixP->fx_file, fixP->fx_line,
27680 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27682 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27683 newval = newval | 0x1000;
27684 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27685 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27690 goto thumb_bl_common;
27692 case BFD_RELOC_THUMB_PCREL_BRANCH23:
27693 /* A bl from Thumb state ISA to an internal ARM state function
27694 is converted to a blx. */
27696 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27697 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27698 && ARM_IS_FUNC (fixP->fx_addsy)
27699 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27701 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27702 newval = newval & ~0x1000;
27703 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
27704 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
27710 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27711 /* For a BLX instruction, make sure that the relocation is rounded up
27712 to a word boundary. This follows the semantics of the instruction
27713 which specifies that bit 1 of the target address will come from bit
27714 1 of the base address. */
27715 value = (value + 3) & ~ 3;
27718 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
27719 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
27720 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
27723 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
27725 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
27726 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27727 else if ((value & ~0x1ffffff)
27728 && ((value & ~0x1ffffff) != ~0x1ffffff))
27729 as_bad_where (fixP->fx_file, fixP->fx_line,
27730 _("Thumb2 branch out of range"));
27733 if (fixP->fx_done || !seg->use_rela_p)
27734 encode_thumb2_b_bl_offset (buf, value);
27738 case BFD_RELOC_THUMB_PCREL_BRANCH25:
27739 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
27740 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
27742 if (fixP->fx_done || !seg->use_rela_p)
27743 encode_thumb2_b_bl_offset (buf, value);
27748 if (fixP->fx_done || !seg->use_rela_p)
27753 if (fixP->fx_done || !seg->use_rela_p)
27754 md_number_to_chars (buf, value, 2);
27758 case BFD_RELOC_ARM_TLS_CALL:
27759 case BFD_RELOC_ARM_THM_TLS_CALL:
27760 case BFD_RELOC_ARM_TLS_DESCSEQ:
27761 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
27762 case BFD_RELOC_ARM_TLS_GOTDESC:
27763 case BFD_RELOC_ARM_TLS_GD32:
27764 case BFD_RELOC_ARM_TLS_LE32:
27765 case BFD_RELOC_ARM_TLS_IE32:
27766 case BFD_RELOC_ARM_TLS_LDM32:
27767 case BFD_RELOC_ARM_TLS_LDO32:
27768 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27771 /* Same handling as above, but with the arm_fdpic guard. */
27772 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
27773 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
27774 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
27777 S_SET_THREAD_LOCAL (fixP->fx_addsy);
27781 as_bad_where (fixP->fx_file, fixP->fx_line,
27782 _("Relocation supported only in FDPIC mode"));
27786 case BFD_RELOC_ARM_GOT32:
27787 case BFD_RELOC_ARM_GOTOFF:
27790 case BFD_RELOC_ARM_GOT_PREL:
27791 if (fixP->fx_done || !seg->use_rela_p)
27792 md_number_to_chars (buf, value, 4);
27795 case BFD_RELOC_ARM_TARGET2:
27796 /* TARGET2 is not partial-inplace, so we need to write the
27797 addend here for REL targets, because it won't be written out
27798 during reloc processing later. */
27799 if (fixP->fx_done || !seg->use_rela_p)
27800 md_number_to_chars (buf, fixP->fx_offset, 4);
27803 /* Relocations for FDPIC. */
27804 case BFD_RELOC_ARM_GOTFUNCDESC:
27805 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
27806 case BFD_RELOC_ARM_FUNCDESC:
27809 if (fixP->fx_done || !seg->use_rela_p)
27810 md_number_to_chars (buf, 0, 4);
27814 as_bad_where (fixP->fx_file, fixP->fx_line,
27815 _("Relocation supported only in FDPIC mode"));
27820 case BFD_RELOC_RVA:
27822 case BFD_RELOC_ARM_TARGET1:
27823 case BFD_RELOC_ARM_ROSEGREL32:
27824 case BFD_RELOC_ARM_SBREL32:
27825 case BFD_RELOC_32_PCREL:
27827 case BFD_RELOC_32_SECREL:
27829 if (fixP->fx_done || !seg->use_rela_p)
27831 /* For WinCE we only do this for pcrel fixups. */
27832 if (fixP->fx_done || fixP->fx_pcrel)
27834 md_number_to_chars (buf, value, 4);
27838 case BFD_RELOC_ARM_PREL31:
27839 if (fixP->fx_done || !seg->use_rela_p)
27841 newval = md_chars_to_number (buf, 4) & 0x80000000;
27842 if ((value ^ (value >> 1)) & 0x40000000)
27844 as_bad_where (fixP->fx_file, fixP->fx_line,
27845 _("rel31 relocation overflow"));
27847 newval |= value & 0x7fffffff;
27848 md_number_to_chars (buf, newval, 4);
27853 case BFD_RELOC_ARM_CP_OFF_IMM:
27854 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
27855 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
27856 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
27857 newval = md_chars_to_number (buf, INSN_SIZE);
27859 newval = get_thumb32_insn (buf);
27860 if ((newval & 0x0f200f00) == 0x0d000900)
27862 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27863 has permitted values that are multiples of 2, in the range 0
27865 if (value < -510 || value > 510 || (value & 1))
27866 as_bad_where (fixP->fx_file, fixP->fx_line,
27867 _("co-processor offset out of range"));
27869 else if ((newval & 0xfe001f80) == 0xec000f80)
27871 if (value < -511 || value > 512 || (value & 3))
27872 as_bad_where (fixP->fx_file, fixP->fx_line,
27873 _("co-processor offset out of range"));
27875 else if (value < -1023 || value > 1023 || (value & 3))
27876 as_bad_where (fixP->fx_file, fixP->fx_line,
27877 _("co-processor offset out of range"));
27882 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27883 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27884 newval = md_chars_to_number (buf, INSN_SIZE);
27886 newval = get_thumb32_insn (buf);
27889 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27890 newval &= 0xffffff80;
27892 newval &= 0xffffff00;
27896 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
27897 newval &= 0xff7fff80;
27899 newval &= 0xff7fff00;
27900 if ((newval & 0x0f200f00) == 0x0d000900)
27902 /* This is a fp16 vstr/vldr.
27904 It requires the immediate offset in the instruction is shifted
27905 left by 1 to be a half-word offset.
27907 Here, left shift by 1 first, and later right shift by 2
27908 should get the right offset. */
27911 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
27913 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
27914 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
27915 md_number_to_chars (buf, newval, INSN_SIZE);
27917 put_thumb32_insn (buf, newval);
27920 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
27921 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
27922 if (value < -255 || value > 255)
27923 as_bad_where (fixP->fx_file, fixP->fx_line,
27924 _("co-processor offset out of range"));
27926 goto cp_off_common;
27928 case BFD_RELOC_ARM_THUMB_OFFSET:
27929 newval = md_chars_to_number (buf, THUMB_SIZE);
27930 /* Exactly what ranges, and where the offset is inserted depends
27931 on the type of instruction, we can establish this from the
27933 switch (newval >> 12)
27935 case 4: /* PC load. */
27936 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27937 forced to zero for these loads; md_pcrel_from has already
27938 compensated for this. */
27940 as_bad_where (fixP->fx_file, fixP->fx_line,
27941 _("invalid offset, target not word aligned (0x%08lX)"),
27942 (((unsigned long) fixP->fx_frag->fr_address
27943 + (unsigned long) fixP->fx_where) & ~3)
27944 + (unsigned long) value);
27946 if (value & ~0x3fc)
27947 as_bad_where (fixP->fx_file, fixP->fx_line,
27948 _("invalid offset, value too big (0x%08lX)"),
27951 newval |= value >> 2;
27954 case 9: /* SP load/store. */
27955 if (value & ~0x3fc)
27956 as_bad_where (fixP->fx_file, fixP->fx_line,
27957 _("invalid offset, value too big (0x%08lX)"),
27959 newval |= value >> 2;
27962 case 6: /* Word load/store. */
27964 as_bad_where (fixP->fx_file, fixP->fx_line,
27965 _("invalid offset, value too big (0x%08lX)"),
27967 newval |= value << 4; /* 6 - 2. */
27970 case 7: /* Byte load/store. */
27972 as_bad_where (fixP->fx_file, fixP->fx_line,
27973 _("invalid offset, value too big (0x%08lX)"),
27975 newval |= value << 6;
27978 case 8: /* Halfword load/store. */
27980 as_bad_where (fixP->fx_file, fixP->fx_line,
27981 _("invalid offset, value too big (0x%08lX)"),
27983 newval |= value << 5; /* 6 - 1. */
27987 as_bad_where (fixP->fx_file, fixP->fx_line,
27988 "Unable to process relocation for thumb opcode: %lx",
27989 (unsigned long) newval);
27992 md_number_to_chars (buf, newval, THUMB_SIZE);
27995 case BFD_RELOC_ARM_THUMB_ADD:
27996 /* This is a complicated relocation, since we use it for all of
27997 the following immediate relocations:
28001 9bit ADD/SUB SP word-aligned
28002 10bit ADD PC/SP word-aligned
28004 The type of instruction being processed is encoded in the
28011 newval = md_chars_to_number (buf, THUMB_SIZE);
28013 int rd = (newval >> 4) & 0xf;
28014 int rs = newval & 0xf;
28015 int subtract = !!(newval & 0x8000);
28017 /* Check for HI regs, only very restricted cases allowed:
28018 Adjusting SP, and using PC or SP to get an address. */
28019 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
28020 || (rs > 7 && rs != REG_SP && rs != REG_PC))
28021 as_bad_where (fixP->fx_file, fixP->fx_line,
28022 _("invalid Hi register with immediate"));
28024 /* If value is negative, choose the opposite instruction. */
28028 subtract = !subtract;
28030 as_bad_where (fixP->fx_file, fixP->fx_line,
28031 _("immediate value out of range"));
28036 if (value & ~0x1fc)
28037 as_bad_where (fixP->fx_file, fixP->fx_line,
28038 _("invalid immediate for stack address calculation"));
28039 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
28040 newval |= value >> 2;
28042 else if (rs == REG_PC || rs == REG_SP)
28044 /* PR gas/18541. If the addition is for a defined symbol
28045 within range of an ADR instruction then accept it. */
28048 && fixP->fx_addsy != NULL)
28052 if (! S_IS_DEFINED (fixP->fx_addsy)
28053 || S_GET_SEGMENT (fixP->fx_addsy) != seg
28054 || S_IS_WEAK (fixP->fx_addsy))
28056 as_bad_where (fixP->fx_file, fixP->fx_line,
28057 _("address calculation needs a strongly defined nearby symbol"));
28061 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
28063 /* Round up to the next 4-byte boundary. */
28068 v = S_GET_VALUE (fixP->fx_addsy) - v;
28072 as_bad_where (fixP->fx_file, fixP->fx_line,
28073 _("symbol too far away"));
28083 if (subtract || value & ~0x3fc)
28084 as_bad_where (fixP->fx_file, fixP->fx_line,
28085 _("invalid immediate for address calculation (value = 0x%08lX)"),
28086 (unsigned long) (subtract ? - value : value));
28087 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
28089 newval |= value >> 2;
28094 as_bad_where (fixP->fx_file, fixP->fx_line,
28095 _("immediate value out of range"));
28096 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
28097 newval |= (rd << 8) | value;
28102 as_bad_where (fixP->fx_file, fixP->fx_line,
28103 _("immediate value out of range"));
28104 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
28105 newval |= rd | (rs << 3) | (value << 6);
28108 md_number_to_chars (buf, newval, THUMB_SIZE);
28111 case BFD_RELOC_ARM_THUMB_IMM:
28112 newval = md_chars_to_number (buf, THUMB_SIZE);
28113 if (value < 0 || value > 255)
28114 as_bad_where (fixP->fx_file, fixP->fx_line,
28115 _("invalid immediate: %ld is out of range"),
28118 md_number_to_chars (buf, newval, THUMB_SIZE);
28121 case BFD_RELOC_ARM_THUMB_SHIFT:
28122 /* 5bit shift value (0..32). LSL cannot take 32. */
28123 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
28124 temp = newval & 0xf800;
28125 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
28126 as_bad_where (fixP->fx_file, fixP->fx_line,
28127 _("invalid shift value: %ld"), (long) value);
28128 /* Shifts of zero must be encoded as LSL. */
28130 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
28131 /* Shifts of 32 are encoded as zero. */
28132 else if (value == 32)
28134 newval |= value << 6;
28135 md_number_to_chars (buf, newval, THUMB_SIZE);
28138 case BFD_RELOC_VTABLE_INHERIT:
28139 case BFD_RELOC_VTABLE_ENTRY:
28143 case BFD_RELOC_ARM_MOVW:
28144 case BFD_RELOC_ARM_MOVT:
28145 case BFD_RELOC_ARM_THUMB_MOVW:
28146 case BFD_RELOC_ARM_THUMB_MOVT:
28147 if (fixP->fx_done || !seg->use_rela_p)
28149 /* REL format relocations are limited to a 16-bit addend. */
28150 if (!fixP->fx_done)
28152 if (value < -0x8000 || value > 0x7fff)
28153 as_bad_where (fixP->fx_file, fixP->fx_line,
28154 _("offset out of range"));
28156 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28157 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28162 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28163 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28165 newval = get_thumb32_insn (buf);
28166 newval &= 0xfbf08f00;
28167 newval |= (value & 0xf000) << 4;
28168 newval |= (value & 0x0800) << 15;
28169 newval |= (value & 0x0700) << 4;
28170 newval |= (value & 0x00ff);
28171 put_thumb32_insn (buf, newval);
28175 newval = md_chars_to_number (buf, 4);
28176 newval &= 0xfff0f000;
28177 newval |= value & 0x0fff;
28178 newval |= (value & 0xf000) << 4;
28179 md_number_to_chars (buf, newval, 4);
28184 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28185 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28186 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28187 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28188 gas_assert (!fixP->fx_done);
28191 bfd_boolean is_mov;
28192 bfd_vma encoded_addend = value;
28194 /* Check that addend can be encoded in instruction. */
28195 if (!seg->use_rela_p && (value < 0 || value > 255))
28196 as_bad_where (fixP->fx_file, fixP->fx_line,
28197 _("the offset 0x%08lX is not representable"),
28198 (unsigned long) encoded_addend);
28200 /* Extract the instruction. */
28201 insn = md_chars_to_number (buf, THUMB_SIZE);
28202 is_mov = (insn & 0xf800) == 0x2000;
28207 if (!seg->use_rela_p)
28208 insn |= encoded_addend;
28214 /* Extract the instruction. */
28215 /* Encoding is the following
28220 /* The following conditions must be true :
28225 rd = (insn >> 4) & 0xf;
28227 if ((insn & 0x8000) || (rd != rs) || rd > 7)
28228 as_bad_where (fixP->fx_file, fixP->fx_line,
28229 _("Unable to process relocation for thumb opcode: %lx"),
28230 (unsigned long) insn);
28232 /* Encode as ADD immediate8 thumb 1 code. */
28233 insn = 0x3000 | (rd << 8);
28235 /* Place the encoded addend into the first 8 bits of the
28237 if (!seg->use_rela_p)
28238 insn |= encoded_addend;
28241 /* Update the instruction. */
28242 md_number_to_chars (buf, insn, THUMB_SIZE);
28246 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28247 case BFD_RELOC_ARM_ALU_PC_G0:
28248 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28249 case BFD_RELOC_ARM_ALU_PC_G1:
28250 case BFD_RELOC_ARM_ALU_PC_G2:
28251 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28252 case BFD_RELOC_ARM_ALU_SB_G0:
28253 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28254 case BFD_RELOC_ARM_ALU_SB_G1:
28255 case BFD_RELOC_ARM_ALU_SB_G2:
28256 gas_assert (!fixP->fx_done);
28257 if (!seg->use_rela_p)
28260 bfd_vma encoded_addend;
28261 bfd_vma addend_abs = llabs (value);
28263 /* Check that the absolute value of the addend can be
28264 expressed as an 8-bit constant plus a rotation. */
28265 encoded_addend = encode_arm_immediate (addend_abs);
28266 if (encoded_addend == (unsigned int) FAIL)
28267 as_bad_where (fixP->fx_file, fixP->fx_line,
28268 _("the offset 0x%08lX is not representable"),
28269 (unsigned long) addend_abs);
28271 /* Extract the instruction. */
28272 insn = md_chars_to_number (buf, INSN_SIZE);
28274 /* If the addend is positive, use an ADD instruction.
28275 Otherwise use a SUB. Take care not to destroy the S bit. */
28276 insn &= 0xff1fffff;
28282 /* Place the encoded addend into the first 12 bits of the
28284 insn &= 0xfffff000;
28285 insn |= encoded_addend;
28287 /* Update the instruction. */
28288 md_number_to_chars (buf, insn, INSN_SIZE);
28292 case BFD_RELOC_ARM_LDR_PC_G0:
28293 case BFD_RELOC_ARM_LDR_PC_G1:
28294 case BFD_RELOC_ARM_LDR_PC_G2:
28295 case BFD_RELOC_ARM_LDR_SB_G0:
28296 case BFD_RELOC_ARM_LDR_SB_G1:
28297 case BFD_RELOC_ARM_LDR_SB_G2:
28298 gas_assert (!fixP->fx_done);
28299 if (!seg->use_rela_p)
28302 bfd_vma addend_abs = llabs (value);
28304 /* Check that the absolute value of the addend can be
28305 encoded in 12 bits. */
28306 if (addend_abs >= 0x1000)
28307 as_bad_where (fixP->fx_file, fixP->fx_line,
28308 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28309 (unsigned long) addend_abs);
28311 /* Extract the instruction. */
28312 insn = md_chars_to_number (buf, INSN_SIZE);
28314 /* If the addend is negative, clear bit 23 of the instruction.
28315 Otherwise set it. */
28317 insn &= ~(1 << 23);
28321 /* Place the absolute value of the addend into the first 12 bits
28322 of the instruction. */
28323 insn &= 0xfffff000;
28324 insn |= addend_abs;
28326 /* Update the instruction. */
28327 md_number_to_chars (buf, insn, INSN_SIZE);
28331 case BFD_RELOC_ARM_LDRS_PC_G0:
28332 case BFD_RELOC_ARM_LDRS_PC_G1:
28333 case BFD_RELOC_ARM_LDRS_PC_G2:
28334 case BFD_RELOC_ARM_LDRS_SB_G0:
28335 case BFD_RELOC_ARM_LDRS_SB_G1:
28336 case BFD_RELOC_ARM_LDRS_SB_G2:
28337 gas_assert (!fixP->fx_done);
28338 if (!seg->use_rela_p)
28341 bfd_vma addend_abs = llabs (value);
28343 /* Check that the absolute value of the addend can be
28344 encoded in 8 bits. */
28345 if (addend_abs >= 0x100)
28346 as_bad_where (fixP->fx_file, fixP->fx_line,
28347 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28348 (unsigned long) addend_abs);
28350 /* Extract the instruction. */
28351 insn = md_chars_to_number (buf, INSN_SIZE);
28353 /* If the addend is negative, clear bit 23 of the instruction.
28354 Otherwise set it. */
28356 insn &= ~(1 << 23);
28360 /* Place the first four bits of the absolute value of the addend
28361 into the first 4 bits of the instruction, and the remaining
28362 four into bits 8 .. 11. */
28363 insn &= 0xfffff0f0;
28364 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
28366 /* Update the instruction. */
28367 md_number_to_chars (buf, insn, INSN_SIZE);
28371 case BFD_RELOC_ARM_LDC_PC_G0:
28372 case BFD_RELOC_ARM_LDC_PC_G1:
28373 case BFD_RELOC_ARM_LDC_PC_G2:
28374 case BFD_RELOC_ARM_LDC_SB_G0:
28375 case BFD_RELOC_ARM_LDC_SB_G1:
28376 case BFD_RELOC_ARM_LDC_SB_G2:
28377 gas_assert (!fixP->fx_done);
28378 if (!seg->use_rela_p)
28381 bfd_vma addend_abs = llabs (value);
28383 /* Check that the absolute value of the addend is a multiple of
28384 four and, when divided by four, fits in 8 bits. */
28385 if (addend_abs & 0x3)
28386 as_bad_where (fixP->fx_file, fixP->fx_line,
28387 _("bad offset 0x%08lX (must be word-aligned)"),
28388 (unsigned long) addend_abs);
28390 if ((addend_abs >> 2) > 0xff)
28391 as_bad_where (fixP->fx_file, fixP->fx_line,
28392 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28393 (unsigned long) addend_abs);
28395 /* Extract the instruction. */
28396 insn = md_chars_to_number (buf, INSN_SIZE);
28398 /* If the addend is negative, clear bit 23 of the instruction.
28399 Otherwise set it. */
28401 insn &= ~(1 << 23);
28405 /* Place the addend (divided by four) into the first eight
28406 bits of the instruction. */
28407 insn &= 0xfffffff0;
28408 insn |= addend_abs >> 2;
28410 /* Update the instruction. */
28411 md_number_to_chars (buf, insn, INSN_SIZE);
28415 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28417 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28418 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28419 && ARM_IS_FUNC (fixP->fx_addsy)
28420 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28422 /* Force a relocation for a branch 5 bits wide. */
28425 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
28426 as_bad_where (fixP->fx_file, fixP->fx_line,
28429 if (fixP->fx_done || !seg->use_rela_p)
28431 addressT boff = value >> 1;
28433 newval = md_chars_to_number (buf, THUMB_SIZE);
28434 newval |= (boff << 7);
28435 md_number_to_chars (buf, newval, THUMB_SIZE);
28439 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28441 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28442 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28443 && ARM_IS_FUNC (fixP->fx_addsy)
28444 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28448 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
28449 as_bad_where (fixP->fx_file, fixP->fx_line,
28450 _("branch out of range"));
28452 if (fixP->fx_done || !seg->use_rela_p)
28454 newval = md_chars_to_number (buf, THUMB_SIZE);
28456 addressT boff = ((newval & 0x0780) >> 7) << 1;
28457 addressT diff = value - boff;
28461 newval |= 1 << 1; /* T bit. */
28463 else if (diff != 2)
28465 as_bad_where (fixP->fx_file, fixP->fx_line,
28466 _("out of range label-relative fixup value"));
28468 md_number_to_chars (buf, newval, THUMB_SIZE);
28472 case BFD_RELOC_ARM_THUMB_BF17:
28474 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28475 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28476 && ARM_IS_FUNC (fixP->fx_addsy)
28477 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28479 /* Force a relocation for a branch 17 bits wide. */
28483 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
28484 as_bad_where (fixP->fx_file, fixP->fx_line,
28487 if (fixP->fx_done || !seg->use_rela_p)
28490 addressT immA, immB, immC;
28492 immA = (value & 0x0001f000) >> 12;
28493 immB = (value & 0x00000ffc) >> 2;
28494 immC = (value & 0x00000002) >> 1;
28496 newval = md_chars_to_number (buf, THUMB_SIZE);
28497 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28499 newval2 |= (immC << 11) | (immB << 1);
28500 md_number_to_chars (buf, newval, THUMB_SIZE);
28501 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28505 case BFD_RELOC_ARM_THUMB_BF19:
28507 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28508 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28509 && ARM_IS_FUNC (fixP->fx_addsy)
28510 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28512 /* Force a relocation for a branch 19 bits wide. */
28516 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
28517 as_bad_where (fixP->fx_file, fixP->fx_line,
28520 if (fixP->fx_done || !seg->use_rela_p)
28523 addressT immA, immB, immC;
28525 immA = (value & 0x0007f000) >> 12;
28526 immB = (value & 0x00000ffc) >> 2;
28527 immC = (value & 0x00000002) >> 1;
28529 newval = md_chars_to_number (buf, THUMB_SIZE);
28530 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28532 newval2 |= (immC << 11) | (immB << 1);
28533 md_number_to_chars (buf, newval, THUMB_SIZE);
28534 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28538 case BFD_RELOC_ARM_THUMB_BF13:
28540 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28541 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28542 && ARM_IS_FUNC (fixP->fx_addsy)
28543 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28545 /* Force a relocation for a branch 13 bits wide. */
28549 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
28550 as_bad_where (fixP->fx_file, fixP->fx_line,
28553 if (fixP->fx_done || !seg->use_rela_p)
28556 addressT immA, immB, immC;
28558 immA = (value & 0x00001000) >> 12;
28559 immB = (value & 0x00000ffc) >> 2;
28560 immC = (value & 0x00000002) >> 1;
28562 newval = md_chars_to_number (buf, THUMB_SIZE);
28563 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28565 newval2 |= (immC << 11) | (immB << 1);
28566 md_number_to_chars (buf, newval, THUMB_SIZE);
28567 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28571 case BFD_RELOC_ARM_THUMB_LOOP12:
28573 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28574 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28575 && ARM_IS_FUNC (fixP->fx_addsy)
28576 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28578 /* Force a relocation for a branch 12 bits wide. */
28582 bfd_vma insn = get_thumb32_insn (buf);
28583 /* le lr, <label> or le <label> */
28584 if (((insn & 0xffffffff) == 0xf00fc001)
28585 || ((insn & 0xffffffff) == 0xf02fc001))
28588 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
28589 as_bad_where (fixP->fx_file, fixP->fx_line,
28591 if (fixP->fx_done || !seg->use_rela_p)
28593 addressT imml, immh;
28595 immh = (value & 0x00000ffc) >> 2;
28596 imml = (value & 0x00000002) >> 1;
28598 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28599 newval |= (imml << 11) | (immh << 1);
28600 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
28604 case BFD_RELOC_ARM_V4BX:
28605 /* This will need to go in the object file. */
28609 case BFD_RELOC_UNUSED:
28611 as_bad_where (fixP->fx_file, fixP->fx_line,
28612 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
28616 /* Translate internal representation of relocation info to BFD target
28620 tc_gen_reloc (asection *section, fixS *fixp)
28623 bfd_reloc_code_real_type code;
28625 reloc = XNEW (arelent);
28627 reloc->sym_ptr_ptr = XNEW (asymbol *);
28628 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
28629 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
28631 if (fixp->fx_pcrel)
28633 if (section->use_rela_p)
28634 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
28636 fixp->fx_offset = reloc->address;
28638 reloc->addend = fixp->fx_offset;
28640 switch (fixp->fx_r_type)
28643 if (fixp->fx_pcrel)
28645 code = BFD_RELOC_8_PCREL;
28648 /* Fall through. */
28651 if (fixp->fx_pcrel)
28653 code = BFD_RELOC_16_PCREL;
28656 /* Fall through. */
28659 if (fixp->fx_pcrel)
28661 code = BFD_RELOC_32_PCREL;
28664 /* Fall through. */
28666 case BFD_RELOC_ARM_MOVW:
28667 if (fixp->fx_pcrel)
28669 code = BFD_RELOC_ARM_MOVW_PCREL;
28672 /* Fall through. */
28674 case BFD_RELOC_ARM_MOVT:
28675 if (fixp->fx_pcrel)
28677 code = BFD_RELOC_ARM_MOVT_PCREL;
28680 /* Fall through. */
28682 case BFD_RELOC_ARM_THUMB_MOVW:
28683 if (fixp->fx_pcrel)
28685 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
28688 /* Fall through. */
28690 case BFD_RELOC_ARM_THUMB_MOVT:
28691 if (fixp->fx_pcrel)
28693 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
28696 /* Fall through. */
28698 case BFD_RELOC_NONE:
28699 case BFD_RELOC_ARM_PCREL_BRANCH:
28700 case BFD_RELOC_ARM_PCREL_BLX:
28701 case BFD_RELOC_RVA:
28702 case BFD_RELOC_THUMB_PCREL_BRANCH7:
28703 case BFD_RELOC_THUMB_PCREL_BRANCH9:
28704 case BFD_RELOC_THUMB_PCREL_BRANCH12:
28705 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28706 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28707 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28708 case BFD_RELOC_VTABLE_ENTRY:
28709 case BFD_RELOC_VTABLE_INHERIT:
28711 case BFD_RELOC_32_SECREL:
28713 code = fixp->fx_r_type;
28716 case BFD_RELOC_THUMB_PCREL_BLX:
28718 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
28719 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
28722 code = BFD_RELOC_THUMB_PCREL_BLX;
28725 case BFD_RELOC_ARM_LITERAL:
28726 case BFD_RELOC_ARM_HWLITERAL:
28727 /* If this is called then the a literal has
28728 been referenced across a section boundary. */
28729 as_bad_where (fixp->fx_file, fixp->fx_line,
28730 _("literal referenced across section boundary"));
28734 case BFD_RELOC_ARM_TLS_CALL:
28735 case BFD_RELOC_ARM_THM_TLS_CALL:
28736 case BFD_RELOC_ARM_TLS_DESCSEQ:
28737 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
28738 case BFD_RELOC_ARM_GOT32:
28739 case BFD_RELOC_ARM_GOTOFF:
28740 case BFD_RELOC_ARM_GOT_PREL:
28741 case BFD_RELOC_ARM_PLT32:
28742 case BFD_RELOC_ARM_TARGET1:
28743 case BFD_RELOC_ARM_ROSEGREL32:
28744 case BFD_RELOC_ARM_SBREL32:
28745 case BFD_RELOC_ARM_PREL31:
28746 case BFD_RELOC_ARM_TARGET2:
28747 case BFD_RELOC_ARM_TLS_LDO32:
28748 case BFD_RELOC_ARM_PCREL_CALL:
28749 case BFD_RELOC_ARM_PCREL_JUMP:
28750 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28751 case BFD_RELOC_ARM_ALU_PC_G0:
28752 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28753 case BFD_RELOC_ARM_ALU_PC_G1:
28754 case BFD_RELOC_ARM_ALU_PC_G2:
28755 case BFD_RELOC_ARM_LDR_PC_G0:
28756 case BFD_RELOC_ARM_LDR_PC_G1:
28757 case BFD_RELOC_ARM_LDR_PC_G2:
28758 case BFD_RELOC_ARM_LDRS_PC_G0:
28759 case BFD_RELOC_ARM_LDRS_PC_G1:
28760 case BFD_RELOC_ARM_LDRS_PC_G2:
28761 case BFD_RELOC_ARM_LDC_PC_G0:
28762 case BFD_RELOC_ARM_LDC_PC_G1:
28763 case BFD_RELOC_ARM_LDC_PC_G2:
28764 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28765 case BFD_RELOC_ARM_ALU_SB_G0:
28766 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28767 case BFD_RELOC_ARM_ALU_SB_G1:
28768 case BFD_RELOC_ARM_ALU_SB_G2:
28769 case BFD_RELOC_ARM_LDR_SB_G0:
28770 case BFD_RELOC_ARM_LDR_SB_G1:
28771 case BFD_RELOC_ARM_LDR_SB_G2:
28772 case BFD_RELOC_ARM_LDRS_SB_G0:
28773 case BFD_RELOC_ARM_LDRS_SB_G1:
28774 case BFD_RELOC_ARM_LDRS_SB_G2:
28775 case BFD_RELOC_ARM_LDC_SB_G0:
28776 case BFD_RELOC_ARM_LDC_SB_G1:
28777 case BFD_RELOC_ARM_LDC_SB_G2:
28778 case BFD_RELOC_ARM_V4BX:
28779 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28780 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28781 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28782 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28783 case BFD_RELOC_ARM_GOTFUNCDESC:
28784 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28785 case BFD_RELOC_ARM_FUNCDESC:
28786 case BFD_RELOC_ARM_THUMB_BF17:
28787 case BFD_RELOC_ARM_THUMB_BF19:
28788 case BFD_RELOC_ARM_THUMB_BF13:
28789 code = fixp->fx_r_type;
28792 case BFD_RELOC_ARM_TLS_GOTDESC:
28793 case BFD_RELOC_ARM_TLS_GD32:
28794 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28795 case BFD_RELOC_ARM_TLS_LE32:
28796 case BFD_RELOC_ARM_TLS_IE32:
28797 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28798 case BFD_RELOC_ARM_TLS_LDM32:
28799 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28800 /* BFD will include the symbol's address in the addend.
28801 But we don't want that, so subtract it out again here. */
28802 if (!S_IS_COMMON (fixp->fx_addsy))
28803 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
28804 code = fixp->fx_r_type;
28808 case BFD_RELOC_ARM_IMMEDIATE:
28809 as_bad_where (fixp->fx_file, fixp->fx_line,
28810 _("internal relocation (type: IMMEDIATE) not fixed up"));
28813 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28814 as_bad_where (fixp->fx_file, fixp->fx_line,
28815 _("ADRL used for a symbol not defined in the same file"));
28818 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28819 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28820 case BFD_RELOC_ARM_THUMB_LOOP12:
28821 as_bad_where (fixp->fx_file, fixp->fx_line,
28822 _("%s used for a symbol not defined in the same file"),
28823 bfd_get_reloc_code_name (fixp->fx_r_type));
28826 case BFD_RELOC_ARM_OFFSET_IMM:
28827 if (section->use_rela_p)
28829 code = fixp->fx_r_type;
28833 if (fixp->fx_addsy != NULL
28834 && !S_IS_DEFINED (fixp->fx_addsy)
28835 && S_IS_LOCAL (fixp->fx_addsy))
28837 as_bad_where (fixp->fx_file, fixp->fx_line,
28838 _("undefined local label `%s'"),
28839 S_GET_NAME (fixp->fx_addsy));
28843 as_bad_where (fixp->fx_file, fixp->fx_line,
28844 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28851 switch (fixp->fx_r_type)
28853 case BFD_RELOC_NONE: type = "NONE"; break;
28854 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
28855 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
28856 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
28857 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
28858 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
28859 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
28860 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
28861 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
28862 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
28863 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
28864 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
28865 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
28866 default: type = _("<unknown>"); break;
28868 as_bad_where (fixp->fx_file, fixp->fx_line,
28869 _("cannot represent %s relocation in this object file format"),
28876 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
28878 && fixp->fx_addsy == GOT_symbol)
28880 code = BFD_RELOC_ARM_GOTPC;
28881 reloc->addend = fixp->fx_offset = reloc->address;
28885 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
28887 if (reloc->howto == NULL)
28889 as_bad_where (fixp->fx_file, fixp->fx_line,
28890 _("cannot represent %s relocation in this object file format"),
28891 bfd_get_reloc_code_name (code));
28895 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28896 vtable entry to be used in the relocation's section offset. */
28897 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
28898 reloc->address = fixp->fx_offset;
28903 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28906 cons_fix_new_arm (fragS * frag,
28910 bfd_reloc_code_real_type reloc)
28915 FIXME: @@ Should look at CPU word size. */
28919 reloc = BFD_RELOC_8;
28922 reloc = BFD_RELOC_16;
28926 reloc = BFD_RELOC_32;
28929 reloc = BFD_RELOC_64;
28934 if (exp->X_op == O_secrel)
28936 exp->X_op = O_symbol;
28937 reloc = BFD_RELOC_32_SECREL;
28941 fix_new_exp (frag, where, size, exp, pcrel, reloc);
28944 #if defined (OBJ_COFF)
28946 arm_validate_fix (fixS * fixP)
28948 /* If the destination of the branch is a defined symbol which does not have
28949 the THUMB_FUNC attribute, then we must be calling a function which has
28950 the (interfacearm) attribute. We look for the Thumb entry point to that
28951 function and change the branch to refer to that function instead. */
28952 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
28953 && fixP->fx_addsy != NULL
28954 && S_IS_DEFINED (fixP->fx_addsy)
28955 && ! THUMB_IS_FUNC (fixP->fx_addsy))
28957 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
28964 arm_force_relocation (struct fix * fixp)
28966 #if defined (OBJ_COFF) && defined (TE_PE)
28967 if (fixp->fx_r_type == BFD_RELOC_RVA)
28971 /* In case we have a call or a branch to a function in ARM ISA mode from
28972 a thumb function or vice-versa force the relocation. These relocations
28973 are cleared off for some cores that might have blx and simple transformations
28977 switch (fixp->fx_r_type)
28979 case BFD_RELOC_ARM_PCREL_JUMP:
28980 case BFD_RELOC_ARM_PCREL_CALL:
28981 case BFD_RELOC_THUMB_PCREL_BLX:
28982 if (THUMB_IS_FUNC (fixp->fx_addsy))
28986 case BFD_RELOC_ARM_PCREL_BLX:
28987 case BFD_RELOC_THUMB_PCREL_BRANCH25:
28988 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28989 case BFD_RELOC_THUMB_PCREL_BRANCH23:
28990 if (ARM_IS_FUNC (fixp->fx_addsy))
28999 /* Resolve these relocations even if the symbol is extern or weak.
29000 Technically this is probably wrong due to symbol preemption.
29001 In practice these relocations do not have enough range to be useful
29002 at dynamic link time, and some code (e.g. in the Linux kernel)
29003 expects these references to be resolved. */
29004 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
29005 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
29006 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
29007 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
29008 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29009 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
29010 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
29011 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
29012 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
29013 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
29014 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
29015 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
29016 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
29017 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
29020 /* Always leave these relocations for the linker. */
29021 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29022 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29023 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
29026 /* Always generate relocations against function symbols. */
29027 if (fixp->fx_r_type == BFD_RELOC_32
29029 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
29032 return generic_force_reloc (fixp);
29035 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29036 /* Relocations against function names must be left unadjusted,
29037 so that the linker can use this information to generate interworking
29038 stubs. The MIPS version of this function
29039 also prevents relocations that are mips-16 specific, but I do not
29040 know why it does this.
29043 There is one other problem that ought to be addressed here, but
29044 which currently is not: Taking the address of a label (rather
29045 than a function) and then later jumping to that address. Such
29046 addresses also ought to have their bottom bit set (assuming that
29047 they reside in Thumb code), but at the moment they will not. */
29050 arm_fix_adjustable (fixS * fixP)
29052 if (fixP->fx_addsy == NULL)
29055 /* Preserve relocations against symbols with function type. */
29056 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
29059 if (THUMB_IS_FUNC (fixP->fx_addsy)
29060 && fixP->fx_subsy == NULL)
29063 /* We need the symbol name for the VTABLE entries. */
29064 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
29065 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
29068 /* Don't allow symbols to be discarded on GOT related relocs. */
29069 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
29070 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
29071 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
29072 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
29073 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
29074 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
29075 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
29076 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
29077 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
29078 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
29079 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
29080 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
29081 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
29082 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
29083 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
29084 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
29085 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
29088 /* Similarly for group relocations. */
29089 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29090 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29091 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
29094 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29095 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
29096 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29097 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
29098 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
29099 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29100 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
29101 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
29102 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
29105 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29106 offsets, so keep these symbols. */
29107 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29108 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
29113 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29117 elf32_arm_target_format (void)
29120 return (target_big_endian
29121 ? "elf32-bigarm-symbian"
29122 : "elf32-littlearm-symbian");
29123 #elif defined (TE_VXWORKS)
29124 return (target_big_endian
29125 ? "elf32-bigarm-vxworks"
29126 : "elf32-littlearm-vxworks");
29127 #elif defined (TE_NACL)
29128 return (target_big_endian
29129 ? "elf32-bigarm-nacl"
29130 : "elf32-littlearm-nacl");
29134 if (target_big_endian)
29135 return "elf32-bigarm-fdpic";
29137 return "elf32-littlearm-fdpic";
29141 if (target_big_endian)
29142 return "elf32-bigarm";
29144 return "elf32-littlearm";
29150 armelf_frob_symbol (symbolS * symp,
29153 elf_frob_symbol (symp, puntp);
29157 /* MD interface: Finalization. */
29162 literal_pool * pool;
29164 /* Ensure that all the predication blocks are properly closed. */
29165 check_pred_blocks_finished ();
29167 for (pool = list_of_pools; pool; pool = pool->next)
29169 /* Put it at the end of the relevant section. */
29170 subseg_set (pool->section, pool->sub_section);
29172 arm_elf_change_section ();
29179 /* Remove any excess mapping symbols generated for alignment frags in
29180 SEC. We may have created a mapping symbol before a zero byte
29181 alignment; remove it if there's a mapping symbol after the
29184 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
29185 void *dummy ATTRIBUTE_UNUSED)
29187 segment_info_type *seginfo = seg_info (sec);
29190 if (seginfo == NULL || seginfo->frchainP == NULL)
29193 for (fragp = seginfo->frchainP->frch_root;
29195 fragp = fragp->fr_next)
29197 symbolS *sym = fragp->tc_frag_data.last_map;
29198 fragS *next = fragp->fr_next;
29200 /* Variable-sized frags have been converted to fixed size by
29201 this point. But if this was variable-sized to start with,
29202 there will be a fixed-size frag after it. So don't handle
29204 if (sym == NULL || next == NULL)
29207 if (S_GET_VALUE (sym) < next->fr_address)
29208 /* Not at the end of this frag. */
29210 know (S_GET_VALUE (sym) == next->fr_address);
29214 if (next->tc_frag_data.first_map != NULL)
29216 /* Next frag starts with a mapping symbol. Discard this
29218 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29222 if (next->fr_next == NULL)
29224 /* This mapping symbol is at the end of the section. Discard
29226 know (next->fr_fix == 0 && next->fr_var == 0);
29227 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29231 /* As long as we have empty frags without any mapping symbols,
29233 /* If the next frag is non-empty and does not start with a
29234 mapping symbol, then this mapping symbol is required. */
29235 if (next->fr_address != next->fr_next->fr_address)
29238 next = next->fr_next;
29240 while (next != NULL);
29245 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29249 arm_adjust_symtab (void)
29254 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
29256 if (ARM_IS_THUMB (sym))
29258 if (THUMB_IS_FUNC (sym))
29260 /* Mark the symbol as a Thumb function. */
29261 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
29262 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
29263 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
29265 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
29266 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
29268 as_bad (_("%s: unexpected function type: %d"),
29269 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
29271 else switch (S_GET_STORAGE_CLASS (sym))
29274 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
29277 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
29280 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
29288 if (ARM_IS_INTERWORK (sym))
29289 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
29296 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
29298 if (ARM_IS_THUMB (sym))
29300 elf_symbol_type * elf_sym;
29302 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
29303 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
29305 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
29306 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
29308 /* If it's a .thumb_func, declare it as so,
29309 otherwise tag label as .code 16. */
29310 if (THUMB_IS_FUNC (sym))
29311 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
29312 ST_BRANCH_TO_THUMB);
29313 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
29314 elf_sym->internal_elf_sym.st_info =
29315 ELF_ST_INFO (bind, STT_ARM_16BIT);
29320 /* Remove any overlapping mapping symbols generated by alignment frags. */
29321 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
29322 /* Now do generic ELF adjustments. */
29323 elf_adjust_symtab ();
29327 /* MD interface: Initialization. */
29330 set_constant_flonums (void)
29334 for (i = 0; i < NUM_FLOAT_VALS; i++)
29335 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
29339 /* Auto-select Thumb mode if it's the only available instruction set for the
29340 given architecture. */
29343 autoselect_thumb_from_cpu_variant (void)
29345 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
29346 opcode_select (16);
29355 if ( (arm_ops_hsh = hash_new ()) == NULL
29356 || (arm_cond_hsh = hash_new ()) == NULL
29357 || (arm_vcond_hsh = hash_new ()) == NULL
29358 || (arm_shift_hsh = hash_new ()) == NULL
29359 || (arm_psr_hsh = hash_new ()) == NULL
29360 || (arm_v7m_psr_hsh = hash_new ()) == NULL
29361 || (arm_reg_hsh = hash_new ()) == NULL
29362 || (arm_reloc_hsh = hash_new ()) == NULL
29363 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
29364 as_fatal (_("virtual memory exhausted"));
29366 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
29367 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
29368 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
29369 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
29370 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
29371 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
29372 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
29373 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
29374 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
29375 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
29376 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
29377 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
29378 (void *) (v7m_psrs + i));
29379 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
29380 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
29382 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
29384 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
29385 (void *) (barrier_opt_names + i));
29387 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
29389 struct reloc_entry * entry = reloc_names + i;
29391 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
29392 /* This makes encode_branch() use the EABI versions of this relocation. */
29393 entry->reloc = BFD_RELOC_UNUSED;
29395 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
29399 set_constant_flonums ();
29401 /* Set the cpu variant based on the command-line options. We prefer
29402 -mcpu= over -march= if both are set (as for GCC); and we prefer
29403 -mfpu= over any other way of setting the floating point unit.
29404 Use of legacy options with new options are faulted. */
29407 if (mcpu_cpu_opt || march_cpu_opt)
29408 as_bad (_("use of old and new-style options to set CPU type"));
29410 selected_arch = *legacy_cpu;
29412 else if (mcpu_cpu_opt)
29414 selected_arch = *mcpu_cpu_opt;
29415 selected_ext = *mcpu_ext_opt;
29417 else if (march_cpu_opt)
29419 selected_arch = *march_cpu_opt;
29420 selected_ext = *march_ext_opt;
29422 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
29427 as_bad (_("use of old and new-style options to set FPU type"));
29429 selected_fpu = *legacy_fpu;
29432 selected_fpu = *mfpu_opt;
29435 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29436 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29437 /* Some environments specify a default FPU. If they don't, infer it
29438 from the processor. */
29440 selected_fpu = *mcpu_fpu_opt;
29441 else if (march_fpu_opt)
29442 selected_fpu = *march_fpu_opt;
29444 selected_fpu = fpu_default;
29448 if (ARM_FEATURE_ZERO (selected_fpu))
29450 if (!no_cpu_selected ())
29451 selected_fpu = fpu_default;
29453 selected_fpu = fpu_arch_fpa;
29457 if (ARM_FEATURE_ZERO (selected_arch))
29459 selected_arch = cpu_default;
29460 selected_cpu = selected_arch;
29462 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
29464 /* Autodection of feature mode: allow all features in cpu_variant but leave
29465 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29466 after all instruction have been processed and we can decide what CPU
29467 should be selected. */
29468 if (ARM_FEATURE_ZERO (selected_arch))
29469 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
29471 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
29474 autoselect_thumb_from_cpu_variant ();
29476 arm_arch_used = thumb_arch_used = arm_arch_none;
29478 #if defined OBJ_COFF || defined OBJ_ELF
29480 unsigned int flags = 0;
29482 #if defined OBJ_ELF
29483 flags = meabi_flags;
29485 switch (meabi_flags)
29487 case EF_ARM_EABI_UNKNOWN:
29489 /* Set the flags in the private structure. */
29490 if (uses_apcs_26) flags |= F_APCS26;
29491 if (support_interwork) flags |= F_INTERWORK;
29492 if (uses_apcs_float) flags |= F_APCS_FLOAT;
29493 if (pic_code) flags |= F_PIC;
29494 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
29495 flags |= F_SOFT_FLOAT;
29497 switch (mfloat_abi_opt)
29499 case ARM_FLOAT_ABI_SOFT:
29500 case ARM_FLOAT_ABI_SOFTFP:
29501 flags |= F_SOFT_FLOAT;
29504 case ARM_FLOAT_ABI_HARD:
29505 if (flags & F_SOFT_FLOAT)
29506 as_bad (_("hard-float conflicts with specified fpu"));
29510 /* Using pure-endian doubles (even if soft-float). */
29511 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
29512 flags |= F_VFP_FLOAT;
29514 #if defined OBJ_ELF
29515 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
29516 flags |= EF_ARM_MAVERICK_FLOAT;
29519 case EF_ARM_EABI_VER4:
29520 case EF_ARM_EABI_VER5:
29521 /* No additional flags to set. */
29528 bfd_set_private_flags (stdoutput, flags);
29530 /* We have run out flags in the COFF header to encode the
29531 status of ATPCS support, so instead we create a dummy,
29532 empty, debug section called .arm.atpcs. */
29537 sec = bfd_make_section (stdoutput, ".arm.atpcs");
29541 bfd_set_section_flags
29542 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
29543 bfd_set_section_size (stdoutput, sec, 0);
29544 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
29550 /* Record the CPU type as well. */
29551 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
29552 mach = bfd_mach_arm_iWMMXt2;
29553 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
29554 mach = bfd_mach_arm_iWMMXt;
29555 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
29556 mach = bfd_mach_arm_XScale;
29557 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
29558 mach = bfd_mach_arm_ep9312;
29559 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
29560 mach = bfd_mach_arm_5TE;
29561 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
29563 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
29564 mach = bfd_mach_arm_5T;
29566 mach = bfd_mach_arm_5;
29568 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
29570 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
29571 mach = bfd_mach_arm_4T;
29573 mach = bfd_mach_arm_4;
29575 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
29576 mach = bfd_mach_arm_3M;
29577 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
29578 mach = bfd_mach_arm_3;
29579 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
29580 mach = bfd_mach_arm_2a;
29581 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
29582 mach = bfd_mach_arm_2;
29584 mach = bfd_mach_arm_unknown;
29586 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
29589 /* Command line processing. */
29592 Invocation line includes a switch not recognized by the base assembler.
29593 See if it's a processor-specific option.
29595 This routine is somewhat complicated by the need for backwards
29596 compatibility (since older releases of gcc can't be changed).
29597 The new options try to make the interface as compatible as
29600 New options (supported) are:
29602 -mcpu=<cpu name> Assemble for selected processor
29603 -march=<architecture name> Assemble for selected architecture
29604 -mfpu=<fpu architecture> Assemble for selected FPU.
29605 -EB/-mbig-endian Big-endian
29606 -EL/-mlittle-endian Little-endian
29607 -k Generate PIC code
29608 -mthumb Start in Thumb mode
29609 -mthumb-interwork Code supports ARM/Thumb interworking
29611 -m[no-]warn-deprecated Warn about deprecated features
29612 -m[no-]warn-syms Warn when symbols match instructions
29614 For now we will also provide support for:
29616 -mapcs-32 32-bit Program counter
29617 -mapcs-26 26-bit Program counter
29618 -macps-float Floats passed in FP registers
29619 -mapcs-reentrant Reentrant code
29621 (sometime these will probably be replaced with -mapcs=<list of options>
29622 and -matpcs=<list of options>)
29624 The remaining options are only supported for back-wards compatibility.
29625 Cpu variants, the arm part is optional:
29626 -m[arm]1 Currently not supported.
29627 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29628 -m[arm]3 Arm 3 processor
29629 -m[arm]6[xx], Arm 6 processors
29630 -m[arm]7[xx][t][[d]m] Arm 7 processors
29631 -m[arm]8[10] Arm 8 processors
29632 -m[arm]9[20][tdmi] Arm 9 processors
29633 -mstrongarm[110[0]] StrongARM processors
29634 -mxscale XScale processors
29635 -m[arm]v[2345[t[e]]] Arm architectures
29636 -mall All (except the ARM1)
29638 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29639 -mfpe-old (No float load/store multiples)
29640 -mvfpxd VFP Single precision
29642 -mno-fpu Disable all floating point instructions
29644 The following CPU names are recognized:
29645 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29646 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29647 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29648 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29649 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29650 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29651 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29655 const char * md_shortopts = "m:k";
29657 #ifdef ARM_BI_ENDIAN
29658 #define OPTION_EB (OPTION_MD_BASE + 0)
29659 #define OPTION_EL (OPTION_MD_BASE + 1)
29661 #if TARGET_BYTES_BIG_ENDIAN
29662 #define OPTION_EB (OPTION_MD_BASE + 0)
29664 #define OPTION_EL (OPTION_MD_BASE + 1)
29667 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29668 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29670 struct option md_longopts[] =
29673 {"EB", no_argument, NULL, OPTION_EB},
29676 {"EL", no_argument, NULL, OPTION_EL},
29678 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
29680 {"fdpic", no_argument, NULL, OPTION_FDPIC},
29682 {NULL, no_argument, NULL, 0}
29685 size_t md_longopts_size = sizeof (md_longopts);
29687 struct arm_option_table
29689 const char * option; /* Option name to match. */
29690 const char * help; /* Help information. */
29691 int * var; /* Variable to change. */
29692 int value; /* What to change it to. */
29693 const char * deprecated; /* If non-null, print this message. */
29696 struct arm_option_table arm_opts[] =
29698 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
29699 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
29700 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29701 &support_interwork, 1, NULL},
29702 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
29703 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
29704 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
29706 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
29707 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
29708 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
29709 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
29712 /* These are recognized by the assembler, but have no affect on code. */
29713 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
29714 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
29716 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
29717 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29718 &warn_on_deprecated, 0, NULL},
29719 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
29720 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
29721 {NULL, NULL, NULL, 0, NULL}
29724 struct arm_legacy_option_table
29726 const char * option; /* Option name to match. */
29727 const arm_feature_set ** var; /* Variable to change. */
29728 const arm_feature_set value; /* What to change it to. */
29729 const char * deprecated; /* If non-null, print this message. */
29732 const struct arm_legacy_option_table arm_legacy_opts[] =
29734 /* DON'T add any new processors to this list -- we want the whole list
29735 to go away... Add them to the processors table instead. */
29736 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29737 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
29738 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29739 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
29740 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29741 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
29742 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29743 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
29744 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29745 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
29746 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29747 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
29748 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29749 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
29750 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29751 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
29752 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29753 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
29754 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29755 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
29756 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29757 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
29758 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29759 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
29760 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29761 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
29762 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29763 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
29764 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29765 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
29766 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29767 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
29768 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29769 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
29770 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29771 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
29772 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29773 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
29774 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29775 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
29776 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29777 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
29778 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29779 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
29780 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29781 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
29782 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29783 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29784 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29785 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
29786 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29787 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
29788 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29789 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
29790 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29791 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
29792 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29793 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
29794 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29795 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
29796 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29797 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
29798 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29799 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
29800 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29801 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
29802 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29803 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
29804 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
29805 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
29806 N_("use -mcpu=strongarm110")},
29807 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
29808 N_("use -mcpu=strongarm1100")},
29809 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
29810 N_("use -mcpu=strongarm1110")},
29811 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
29812 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
29813 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
29815 /* Architecture variants -- don't add any more to this list either. */
29816 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29817 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
29818 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29819 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
29820 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29821 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
29822 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29823 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
29824 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29825 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
29826 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29827 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
29828 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29829 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
29830 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29831 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
29832 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29833 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
29835 /* Floating point variants -- don't add any more to this list either. */
29836 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
29837 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
29838 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
29839 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
29840 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29842 {NULL, NULL, ARM_ARCH_NONE, NULL}
29845 struct arm_cpu_option_table
29849 const arm_feature_set value;
29850 const arm_feature_set ext;
29851 /* For some CPUs we assume an FPU unless the user explicitly sets
29853 const arm_feature_set default_fpu;
29854 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29856 const char * canonical_name;
29859 /* This list should, at a minimum, contain all the cpu names
29860 recognized by GCC. */
29861 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29863 static const struct arm_cpu_option_table arm_cpus[] =
29865 ARM_CPU_OPT ("all", NULL, ARM_ANY,
29868 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
29871 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
29874 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
29877 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
29880 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
29883 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
29886 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
29889 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
29892 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
29895 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
29898 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
29901 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
29904 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
29907 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
29910 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
29913 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
29916 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
29919 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
29922 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
29925 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
29928 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
29931 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
29934 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
29937 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
29940 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
29943 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
29946 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
29949 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
29952 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
29955 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
29958 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
29961 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
29964 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
29967 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
29970 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
29973 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
29976 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
29979 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
29982 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
29985 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
29988 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
29991 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
29994 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
29997 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
30000 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
30004 /* For V5 or later processors we default to using VFP; but the user
30005 should really set the FPU type explicitly. */
30006 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
30009 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
30012 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30015 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30018 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
30021 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
30024 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
30027 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
30030 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
30033 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
30036 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
30039 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
30042 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
30045 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
30048 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
30051 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
30054 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
30057 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
30060 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
30063 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
30066 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
30069 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
30072 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
30075 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
30078 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
30081 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
30084 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
30087 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
30090 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
30093 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
30096 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
30099 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
30102 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
30105 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
30108 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
30111 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
30114 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
30115 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30117 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
30119 FPU_ARCH_NEON_VFP_V4),
30120 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
30121 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30122 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30123 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
30124 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30125 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30126 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
30128 FPU_ARCH_NEON_VFP_V4),
30129 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
30131 FPU_ARCH_NEON_VFP_V4),
30132 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
30134 FPU_ARCH_NEON_VFP_V4),
30135 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
30136 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30137 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30138 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
30139 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30140 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30141 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
30142 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30143 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30144 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
30145 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30146 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30147 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
30148 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30149 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30150 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
30151 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30152 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30153 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
30154 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30155 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30156 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
30157 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30158 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30159 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
30160 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30161 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30162 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
30163 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30164 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30165 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
30168 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
30170 FPU_ARCH_VFP_V3D16),
30171 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
30172 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30174 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
30175 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30176 FPU_ARCH_VFP_V3D16),
30177 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
30178 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30179 FPU_ARCH_VFP_V3D16),
30180 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
30181 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30182 FPU_ARCH_NEON_VFP_ARMV8),
30183 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
30184 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30186 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
30189 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
30192 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
30195 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
30198 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
30201 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
30204 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
30207 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
30208 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30209 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30210 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
30211 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30212 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30213 /* ??? XSCALE is really an architecture. */
30214 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
30218 /* ??? iwmmxt is not a processor. */
30219 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
30222 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
30225 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
30230 ARM_CPU_OPT ("ep9312", "ARM920T",
30231 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
30232 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
30234 /* Marvell processors. */
30235 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
30236 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30237 FPU_ARCH_VFP_V3D16),
30238 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
30239 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30240 FPU_ARCH_NEON_VFP_V4),
30242 /* APM X-Gene family. */
30243 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
30245 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30246 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
30247 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30248 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30250 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
30254 struct arm_ext_table
30258 const arm_feature_set merge;
30259 const arm_feature_set clear;
30262 struct arm_arch_option_table
30266 const arm_feature_set value;
30267 const arm_feature_set default_fpu;
30268 const struct arm_ext_table * ext_table;
30271 /* Used to add support for +E and +noE extension. */
30272 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30273 /* Used to add support for a +E extension. */
30274 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30275 /* Used to add support for a +noE extension. */
30276 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30278 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30279 ~0 & ~FPU_ENDIAN_PURE)
30281 static const struct arm_ext_table armv5te_ext_table[] =
30283 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
30284 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30287 static const struct arm_ext_table armv7_ext_table[] =
30289 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30290 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30293 static const struct arm_ext_table armv7ve_ext_table[] =
30295 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
30296 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
30297 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30298 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30299 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30300 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
30301 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30303 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
30304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30306 /* Aliases for +simd. */
30307 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30309 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30310 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30311 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30313 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30316 static const struct arm_ext_table armv7a_ext_table[] =
30318 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30319 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30320 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30321 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30322 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30323 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
30324 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30326 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
30327 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30329 /* Aliases for +simd. */
30330 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30331 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30333 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30334 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30336 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
30337 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
30338 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30341 static const struct arm_ext_table armv7r_ext_table[] =
30343 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
30344 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
30345 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30346 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30347 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
30348 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30349 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30350 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
30351 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30354 static const struct arm_ext_table armv7em_ext_table[] =
30356 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
30357 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30358 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
30359 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
30360 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30361 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
30362 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30365 static const struct arm_ext_table armv8a_ext_table[] =
30367 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30368 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30369 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30370 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30372 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30373 should use the +simd option to turn on FP. */
30374 ARM_REMOVE ("fp", ALL_FP),
30375 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30376 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30377 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30381 static const struct arm_ext_table armv81a_ext_table[] =
30383 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30384 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30385 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30387 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30388 should use the +simd option to turn on FP. */
30389 ARM_REMOVE ("fp", ALL_FP),
30390 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30391 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30392 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30395 static const struct arm_ext_table armv82a_ext_table[] =
30397 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30398 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
30399 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
30400 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30401 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30402 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30404 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30405 should use the +simd option to turn on FP. */
30406 ARM_REMOVE ("fp", ALL_FP),
30407 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30408 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30409 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30412 static const struct arm_ext_table armv84a_ext_table[] =
30414 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30415 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30416 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30417 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30419 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30420 should use the +simd option to turn on FP. */
30421 ARM_REMOVE ("fp", ALL_FP),
30422 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30423 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30424 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30427 static const struct arm_ext_table armv85a_ext_table[] =
30429 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30430 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30431 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30432 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30434 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30435 should use the +simd option to turn on FP. */
30436 ARM_REMOVE ("fp", ALL_FP),
30437 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30440 static const struct arm_ext_table armv8m_main_ext_table[] =
30442 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30443 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30444 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
30445 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30446 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30449 static const struct arm_ext_table armv8_1m_main_ext_table[] =
30451 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30452 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30454 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30455 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
30458 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30459 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
30460 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
30461 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
30463 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30464 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
30465 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
30466 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30469 static const struct arm_ext_table armv8r_ext_table[] =
30471 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30472 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30473 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30474 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30475 ARM_REMOVE ("fp", ALL_FP),
30476 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
30477 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30480 /* This list should, at a minimum, contain all the architecture names
30481 recognized by GCC. */
30482 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30483 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30484 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30486 static const struct arm_arch_option_table arm_archs[] =
30488 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
30489 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
30490 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
30491 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
30492 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
30493 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
30494 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
30495 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
30496 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
30497 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
30498 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
30499 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
30500 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
30501 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
30502 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
30503 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
30504 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
30505 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30506 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30507 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
30508 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
30509 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30510 kept to preserve existing behaviour. */
30511 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30512 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30513 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
30514 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
30515 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
30516 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30517 kept to preserve existing behaviour. */
30518 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
30519 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
30520 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
30521 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
30522 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
30523 /* The official spelling of the ARMv7 profile variants is the dashed form.
30524 Accept the non-dashed form for compatibility with old toolchains. */
30525 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30526 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
30527 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
30528 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
30529 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30530 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
30531 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
30532 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
30533 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
30534 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
30536 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
30538 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
30539 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
30540 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
30541 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
30542 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
30543 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
30544 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
30545 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
30546 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
30547 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
30548 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
30550 #undef ARM_ARCH_OPT
30552 /* ISA extensions in the co-processor and main instruction set space. */
30554 struct arm_option_extension_value_table
30558 const arm_feature_set merge_value;
30559 const arm_feature_set clear_value;
30560 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30561 indicates that an extension is available for all architectures while
30562 ARM_ANY marks an empty entry. */
30563 const arm_feature_set allowed_archs[2];
30566 /* The following table must be in alphabetical order with a NULL last entry. */
30568 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30569 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30571 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30572 use the context sensitive approach using arm_ext_table's. */
30573 static const struct arm_option_extension_value_table arm_extensions[] =
30575 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30576 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30577 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30578 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
30579 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30580 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
30581 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
30583 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30584 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30585 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
30586 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
30587 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30588 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30589 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30591 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30592 | ARM_EXT2_FP16_FML),
30593 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30594 | ARM_EXT2_FP16_FML),
30596 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30597 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30598 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30599 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
30600 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30601 Thumb divide instruction. Due to this having the same name as the
30602 previous entry, this will be ignored when doing command-line parsing and
30603 only considered by build attribute selection code. */
30604 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30605 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
30606 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
30607 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
30608 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
30609 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
30610 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
30611 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
30612 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
30613 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
30614 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
30615 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
30616 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
30617 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30618 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
30619 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
30620 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
30621 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
30622 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30623 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30624 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
30626 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
30627 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
30628 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30629 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
30630 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
30631 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
30632 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30633 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
30635 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30636 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30637 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
30638 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30639 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
30640 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
30641 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
30642 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
30644 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
30645 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
30646 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
30647 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
30648 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
30652 /* ISA floating-point and Advanced SIMD extensions. */
30653 struct arm_option_fpu_value_table
30656 const arm_feature_set value;
30659 /* This list should, at a minimum, contain all the fpu names
30660 recognized by GCC. */
30661 static const struct arm_option_fpu_value_table arm_fpus[] =
30663 {"softfpa", FPU_NONE},
30664 {"fpe", FPU_ARCH_FPE},
30665 {"fpe2", FPU_ARCH_FPE},
30666 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
30667 {"fpa", FPU_ARCH_FPA},
30668 {"fpa10", FPU_ARCH_FPA},
30669 {"fpa11", FPU_ARCH_FPA},
30670 {"arm7500fe", FPU_ARCH_FPA},
30671 {"softvfp", FPU_ARCH_VFP},
30672 {"softvfp+vfp", FPU_ARCH_VFP_V2},
30673 {"vfp", FPU_ARCH_VFP_V2},
30674 {"vfp9", FPU_ARCH_VFP_V2},
30675 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
30676 {"vfp10", FPU_ARCH_VFP_V2},
30677 {"vfp10-r0", FPU_ARCH_VFP_V1},
30678 {"vfpxd", FPU_ARCH_VFP_V1xD},
30679 {"vfpv2", FPU_ARCH_VFP_V2},
30680 {"vfpv3", FPU_ARCH_VFP_V3},
30681 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
30682 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
30683 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
30684 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
30685 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
30686 {"arm1020t", FPU_ARCH_VFP_V1},
30687 {"arm1020e", FPU_ARCH_VFP_V2},
30688 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
30689 {"arm1136jf-s", FPU_ARCH_VFP_V2},
30690 {"maverick", FPU_ARCH_MAVERICK},
30691 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30692 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
30693 {"neon-fp16", FPU_ARCH_NEON_FP16},
30694 {"vfpv4", FPU_ARCH_VFP_V4},
30695 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
30696 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
30697 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
30698 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
30699 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
30700 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
30701 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
30702 {"crypto-neon-fp-armv8",
30703 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
30704 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
30705 {"crypto-neon-fp-armv8.1",
30706 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
30707 {NULL, ARM_ARCH_NONE}
30710 struct arm_option_value_table
30716 static const struct arm_option_value_table arm_float_abis[] =
30718 {"hard", ARM_FLOAT_ABI_HARD},
30719 {"softfp", ARM_FLOAT_ABI_SOFTFP},
30720 {"soft", ARM_FLOAT_ABI_SOFT},
30725 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30726 static const struct arm_option_value_table arm_eabis[] =
30728 {"gnu", EF_ARM_EABI_UNKNOWN},
30729 {"4", EF_ARM_EABI_VER4},
30730 {"5", EF_ARM_EABI_VER5},
30735 struct arm_long_option_table
30737 const char * option; /* Substring to match. */
30738 const char * help; /* Help information. */
30739 int (* func) (const char * subopt); /* Function to decode sub-option. */
30740 const char * deprecated; /* If non-null, print this message. */
30744 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
30745 arm_feature_set *ext_set,
30746 const struct arm_ext_table *ext_table)
30748 /* We insist on extensions being specified in alphabetical order, and with
30749 extensions being added before being removed. We achieve this by having
30750 the global ARM_EXTENSIONS table in alphabetical order, and using the
30751 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30752 or removing it (0) and only allowing it to change in the order
30754 const struct arm_option_extension_value_table * opt = NULL;
30755 const arm_feature_set arm_any = ARM_ANY;
30756 int adding_value = -1;
30758 while (str != NULL && *str != 0)
30765 as_bad (_("invalid architectural extension"));
30770 ext = strchr (str, '+');
30775 len = strlen (str);
30777 if (len >= 2 && strncmp (str, "no", 2) == 0)
30779 if (adding_value != 0)
30782 opt = arm_extensions;
30790 if (adding_value == -1)
30793 opt = arm_extensions;
30795 else if (adding_value != 1)
30797 as_bad (_("must specify extensions to add before specifying "
30798 "those to remove"));
30805 as_bad (_("missing architectural extension"));
30809 gas_assert (adding_value != -1);
30810 gas_assert (opt != NULL);
30812 if (ext_table != NULL)
30814 const struct arm_ext_table * ext_opt = ext_table;
30815 bfd_boolean found = FALSE;
30816 for (; ext_opt->name != NULL; ext_opt++)
30817 if (ext_opt->name_len == len
30818 && strncmp (ext_opt->name, str, len) == 0)
30822 if (ARM_FEATURE_ZERO (ext_opt->merge))
30823 /* TODO: Option not supported. When we remove the
30824 legacy table this case should error out. */
30827 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
30831 if (ARM_FEATURE_ZERO (ext_opt->clear))
30832 /* TODO: Option not supported. When we remove the
30833 legacy table this case should error out. */
30835 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
30847 /* Scan over the options table trying to find an exact match. */
30848 for (; opt->name != NULL; opt++)
30849 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30851 int i, nb_allowed_archs =
30852 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
30853 /* Check we can apply the extension to this architecture. */
30854 for (i = 0; i < nb_allowed_archs; i++)
30857 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
30859 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
30862 if (i == nb_allowed_archs)
30864 as_bad (_("extension does not apply to the base architecture"));
30868 /* Add or remove the extension. */
30870 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
30872 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
30874 /* Allowing Thumb division instructions for ARMv7 in autodetection
30875 rely on this break so that duplicate extensions (extensions
30876 with the same name as a previous extension in the list) are not
30877 considered for command-line parsing. */
30881 if (opt->name == NULL)
30883 /* Did we fail to find an extension because it wasn't specified in
30884 alphabetical order, or because it does not exist? */
30886 for (opt = arm_extensions; opt->name != NULL; opt++)
30887 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30890 if (opt->name == NULL)
30891 as_bad (_("unknown architectural extension `%s'"), str);
30893 as_bad (_("architectural extensions must be specified in "
30894 "alphabetical order"));
30900 /* We should skip the extension we've just matched the next time
30912 arm_parse_cpu (const char *str)
30914 const struct arm_cpu_option_table *opt;
30915 const char *ext = strchr (str, '+');
30921 len = strlen (str);
30925 as_bad (_("missing cpu name `%s'"), str);
30929 for (opt = arm_cpus; opt->name != NULL; opt++)
30930 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30932 mcpu_cpu_opt = &opt->value;
30933 if (mcpu_ext_opt == NULL)
30934 mcpu_ext_opt = XNEW (arm_feature_set);
30935 *mcpu_ext_opt = opt->ext;
30936 mcpu_fpu_opt = &opt->default_fpu;
30937 if (opt->canonical_name)
30939 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
30940 strcpy (selected_cpu_name, opt->canonical_name);
30946 if (len >= sizeof selected_cpu_name)
30947 len = (sizeof selected_cpu_name) - 1;
30949 for (i = 0; i < len; i++)
30950 selected_cpu_name[i] = TOUPPER (opt->name[i]);
30951 selected_cpu_name[i] = 0;
30955 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
30960 as_bad (_("unknown cpu `%s'"), str);
30965 arm_parse_arch (const char *str)
30967 const struct arm_arch_option_table *opt;
30968 const char *ext = strchr (str, '+');
30974 len = strlen (str);
30978 as_bad (_("missing architecture name `%s'"), str);
30982 for (opt = arm_archs; opt->name != NULL; opt++)
30983 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
30985 march_cpu_opt = &opt->value;
30986 if (march_ext_opt == NULL)
30987 march_ext_opt = XNEW (arm_feature_set);
30988 *march_ext_opt = arm_arch_none;
30989 march_fpu_opt = &opt->default_fpu;
30990 strcpy (selected_cpu_name, opt->name);
30993 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
30999 as_bad (_("unknown architecture `%s'\n"), str);
31004 arm_parse_fpu (const char * str)
31006 const struct arm_option_fpu_value_table * opt;
31008 for (opt = arm_fpus; opt->name != NULL; opt++)
31009 if (streq (opt->name, str))
31011 mfpu_opt = &opt->value;
31015 as_bad (_("unknown floating point format `%s'\n"), str);
31020 arm_parse_float_abi (const char * str)
31022 const struct arm_option_value_table * opt;
31024 for (opt = arm_float_abis; opt->name != NULL; opt++)
31025 if (streq (opt->name, str))
31027 mfloat_abi_opt = opt->value;
31031 as_bad (_("unknown floating point abi `%s'\n"), str);
31037 arm_parse_eabi (const char * str)
31039 const struct arm_option_value_table *opt;
31041 for (opt = arm_eabis; opt->name != NULL; opt++)
31042 if (streq (opt->name, str))
31044 meabi_flags = opt->value;
31047 as_bad (_("unknown EABI `%s'\n"), str);
31053 arm_parse_it_mode (const char * str)
31055 bfd_boolean ret = TRUE;
31057 if (streq ("arm", str))
31058 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
31059 else if (streq ("thumb", str))
31060 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
31061 else if (streq ("always", str))
31062 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
31063 else if (streq ("never", str))
31064 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
31067 as_bad (_("unknown implicit IT mode `%s', should be "\
31068 "arm, thumb, always, or never."), str);
31076 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
31078 codecomposer_syntax = TRUE;
31079 arm_comment_chars[0] = ';';
31080 arm_line_separator_chars[0] = 0;
31084 struct arm_long_option_table arm_long_opts[] =
31086 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31087 arm_parse_cpu, NULL},
31088 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31089 arm_parse_arch, NULL},
31090 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31091 arm_parse_fpu, NULL},
31092 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31093 arm_parse_float_abi, NULL},
31095 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31096 arm_parse_eabi, NULL},
31098 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31099 arm_parse_it_mode, NULL},
31100 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31101 arm_ccs_mode, NULL},
31102 {NULL, NULL, 0, NULL}
31106 md_parse_option (int c, const char * arg)
31108 struct arm_option_table *opt;
31109 const struct arm_legacy_option_table *fopt;
31110 struct arm_long_option_table *lopt;
31116 target_big_endian = 1;
31122 target_big_endian = 0;
31126 case OPTION_FIX_V4BX:
31134 #endif /* OBJ_ELF */
31137 /* Listing option. Just ignore these, we don't support additional
31142 for (opt = arm_opts; opt->option != NULL; opt++)
31144 if (c == opt->option[0]
31145 && ((arg == NULL && opt->option[1] == 0)
31146 || streq (arg, opt->option + 1)))
31148 /* If the option is deprecated, tell the user. */
31149 if (warn_on_deprecated && opt->deprecated != NULL)
31150 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31151 arg ? arg : "", _(opt->deprecated));
31153 if (opt->var != NULL)
31154 *opt->var = opt->value;
31160 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
31162 if (c == fopt->option[0]
31163 && ((arg == NULL && fopt->option[1] == 0)
31164 || streq (arg, fopt->option + 1)))
31166 /* If the option is deprecated, tell the user. */
31167 if (warn_on_deprecated && fopt->deprecated != NULL)
31168 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31169 arg ? arg : "", _(fopt->deprecated));
31171 if (fopt->var != NULL)
31172 *fopt->var = &fopt->value;
31178 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31180 /* These options are expected to have an argument. */
31181 if (c == lopt->option[0]
31183 && strncmp (arg, lopt->option + 1,
31184 strlen (lopt->option + 1)) == 0)
31186 /* If the option is deprecated, tell the user. */
31187 if (warn_on_deprecated && lopt->deprecated != NULL)
31188 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
31189 _(lopt->deprecated));
31191 /* Call the sup-option parser. */
31192 return lopt->func (arg + strlen (lopt->option) - 1);
31203 md_show_usage (FILE * fp)
31205 struct arm_option_table *opt;
31206 struct arm_long_option_table *lopt;
31208 fprintf (fp, _(" ARM-specific assembler options:\n"));
31210 for (opt = arm_opts; opt->option != NULL; opt++)
31211 if (opt->help != NULL)
31212 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
31214 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31215 if (lopt->help != NULL)
31216 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
31220 -EB assemble code for a big-endian cpu\n"));
31225 -EL assemble code for a little-endian cpu\n"));
31229 --fix-v4bx Allow BX in ARMv4 code\n"));
31233 --fdpic generate an FDPIC object file\n"));
31234 #endif /* OBJ_ELF */
31242 arm_feature_set flags;
31243 } cpu_arch_ver_table;
31245 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31246 chronologically for architectures, with an exception for ARMv6-M and
31247 ARMv6S-M due to legacy reasons. No new architecture should have a
31248 special case. This allows for build attribute selection results to be
31249 stable when new architectures are added. */
31250 static const cpu_arch_ver_table cpu_arch_ver[] =
31252 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
31253 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
31254 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
31255 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
31256 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
31257 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
31258 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
31259 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
31260 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
31261 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
31262 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
31263 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
31264 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
31265 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
31266 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
31267 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
31268 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
31269 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
31270 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
31271 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
31272 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
31273 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
31274 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
31275 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
31277 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31278 always selected build attributes to match those of ARMv6-M
31279 (resp. ARMv6S-M). However, due to these architectures being a strict
31280 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31281 would be selected when fully respecting chronology of architectures.
31282 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31283 move them before ARMv7 architectures. */
31284 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
31285 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
31287 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
31288 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
31289 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
31290 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
31291 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
31292 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
31293 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
31294 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
31295 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
31296 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
31297 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
31298 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
31299 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
31300 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
31301 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
31302 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
31303 {-1, ARM_ARCH_NONE}
31306 /* Set an attribute if it has not already been set by the user. */
31309 aeabi_set_attribute_int (int tag, int value)
31312 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31313 || !attributes_set_explicitly[tag])
31314 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
31318 aeabi_set_attribute_string (int tag, const char *value)
31321 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31322 || !attributes_set_explicitly[tag])
31323 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
31326 /* Return whether features in the *NEEDED feature set are available via
31327 extensions for the architecture whose feature set is *ARCH_FSET. */
31330 have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
31331 const arm_feature_set *needed)
31333 int i, nb_allowed_archs;
31334 arm_feature_set ext_fset;
31335 const struct arm_option_extension_value_table *opt;
31337 ext_fset = arm_arch_none;
31338 for (opt = arm_extensions; opt->name != NULL; opt++)
31340 /* Extension does not provide any feature we need. */
31341 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
31345 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
31346 for (i = 0; i < nb_allowed_archs; i++)
31349 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
31352 /* Extension is available, add it. */
31353 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
31354 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
31358 /* Can we enable all features in *needed? */
31359 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
31362 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31363 a given architecture feature set *ARCH_EXT_FSET including extension feature
31364 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31365 - if true, check for an exact match of the architecture modulo extensions;
31366 - otherwise, select build attribute value of the first superset
31367 architecture released so that results remains stable when new architectures
31369 For -march/-mcpu=all the build attribute value of the most featureful
31370 architecture is returned. Tag_CPU_arch_profile result is returned in
31374 get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
31375 const arm_feature_set *ext_fset,
31376 char *profile, int exact_match)
31378 arm_feature_set arch_fset;
31379 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
31381 /* Select most featureful architecture with all its extensions if building
31382 for -march=all as the feature sets used to set build attributes. */
31383 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
31385 /* Force revisiting of decision for each new architecture. */
31386 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
31388 return TAG_CPU_ARCH_V8;
31391 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
31393 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
31395 arm_feature_set known_arch_fset;
31397 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
31400 /* Base architecture match user-specified architecture and
31401 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31402 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
31407 /* Base architecture match user-specified architecture only
31408 (eg. ARMv6-M in the same case as above). Record it in case we
31409 find a match with above condition. */
31410 else if (p_ver_ret == NULL
31411 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
31417 /* Architecture has all features wanted. */
31418 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
31420 arm_feature_set added_fset;
31422 /* Compute features added by this architecture over the one
31423 recorded in p_ver_ret. */
31424 if (p_ver_ret != NULL)
31425 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
31427 /* First architecture that match incl. with extensions, or the
31428 only difference in features over the recorded match is
31429 features that were optional and are now mandatory. */
31430 if (p_ver_ret == NULL
31431 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
31437 else if (p_ver_ret == NULL)
31439 arm_feature_set needed_ext_fset;
31441 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
31443 /* Architecture has all features needed when using some
31444 extensions. Record it and continue searching in case there
31445 exist an architecture providing all needed features without
31446 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31448 if (have_ext_for_needed_feat_p (&known_arch_fset,
31455 if (p_ver_ret == NULL)
31459 /* Tag_CPU_arch_profile. */
31460 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
31461 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
31462 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
31463 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
31465 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
31467 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
31471 return p_ver_ret->val;
31474 /* Set the public EABI object attributes. */
31477 aeabi_set_public_attributes (void)
31479 char profile = '\0';
31482 int fp16_optional = 0;
31483 int skip_exact_match = 0;
31484 arm_feature_set flags, flags_arch, flags_ext;
31486 /* Autodetection mode, choose the architecture based the instructions
31488 if (no_cpu_selected ())
31490 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
31492 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
31493 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
31495 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
31496 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
31498 /* Code run during relaxation relies on selected_cpu being set. */
31499 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
31500 flags_ext = arm_arch_none;
31501 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
31502 selected_ext = flags_ext;
31503 selected_cpu = flags;
31505 /* Otherwise, choose the architecture based on the capabilities of the
31509 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
31510 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
31511 flags_ext = selected_ext;
31512 flags = selected_cpu;
31514 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
31516 /* Allow the user to override the reported architecture. */
31517 if (!ARM_FEATURE_ZERO (selected_object_arch))
31519 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
31520 flags_ext = arm_arch_none;
31523 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
31525 /* When this function is run again after relaxation has happened there is no
31526 way to determine whether an architecture or CPU was specified by the user:
31527 - selected_cpu is set above for relaxation to work;
31528 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31529 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31530 Therefore, if not in -march=all case we first try an exact match and fall
31531 back to autodetection. */
31532 if (!skip_exact_match)
31533 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
31535 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
31537 as_bad (_("no architecture contains all the instructions used\n"));
31539 /* Tag_CPU_name. */
31540 if (selected_cpu_name[0])
31544 q = selected_cpu_name;
31545 if (strncmp (q, "armv", 4) == 0)
31550 for (i = 0; q[i]; i++)
31551 q[i] = TOUPPER (q[i]);
31553 aeabi_set_attribute_string (Tag_CPU_name, q);
31556 /* Tag_CPU_arch. */
31557 aeabi_set_attribute_int (Tag_CPU_arch, arch);
31559 /* Tag_CPU_arch_profile. */
31560 if (profile != '\0')
31561 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
31563 /* Tag_DSP_extension. */
31564 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
31565 aeabi_set_attribute_int (Tag_DSP_extension, 1);
31567 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
31568 /* Tag_ARM_ISA_use. */
31569 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
31570 || ARM_FEATURE_ZERO (flags_arch))
31571 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
31573 /* Tag_THUMB_ISA_use. */
31574 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
31575 || ARM_FEATURE_ZERO (flags_arch))
31579 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31580 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
31582 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
31586 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
31589 /* Tag_VFP_arch. */
31590 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
31591 aeabi_set_attribute_int (Tag_VFP_arch,
31592 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31594 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
31595 aeabi_set_attribute_int (Tag_VFP_arch,
31596 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
31598 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
31601 aeabi_set_attribute_int (Tag_VFP_arch, 3);
31603 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
31605 aeabi_set_attribute_int (Tag_VFP_arch, 4);
31608 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
31609 aeabi_set_attribute_int (Tag_VFP_arch, 2);
31610 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
31611 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
31612 aeabi_set_attribute_int (Tag_VFP_arch, 1);
31614 /* Tag_ABI_HardFP_use. */
31615 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
31616 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
31617 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
31619 /* Tag_WMMX_arch. */
31620 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
31621 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
31622 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
31623 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
31625 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31626 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
31627 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
31628 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
31629 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
31630 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
31632 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
31634 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
31638 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
31643 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
31644 aeabi_set_attribute_int (Tag_MVE_arch, 2);
31645 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
31646 aeabi_set_attribute_int (Tag_MVE_arch, 1);
31648 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31649 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
31650 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
31654 We set Tag_DIV_use to two when integer divide instructions have been used
31655 in ARM state, or when Thumb integer divide instructions have been used,
31656 but we have no architecture profile set, nor have we any ARM instructions.
31658 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31659 by the base architecture.
31661 For new architectures we will have to check these tests. */
31662 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
31663 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
31664 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
31665 aeabi_set_attribute_int (Tag_DIV_use, 0);
31666 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
31667 || (profile == '\0'
31668 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
31669 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
31670 aeabi_set_attribute_int (Tag_DIV_use, 2);
31672 /* Tag_MP_extension_use. */
31673 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
31674 aeabi_set_attribute_int (Tag_MPextension_use, 1);
31676 /* Tag Virtualization_use. */
31677 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
31679 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
31682 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
31685 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31686 finished and free extension feature bits which will not be used anymore. */
31689 arm_md_post_relax (void)
31691 aeabi_set_public_attributes ();
31692 XDELETE (mcpu_ext_opt);
31693 mcpu_ext_opt = NULL;
31694 XDELETE (march_ext_opt);
31695 march_ext_opt = NULL;
31698 /* Add the default contents for the .ARM.attributes section. */
31703 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
31706 aeabi_set_public_attributes ();
31708 #endif /* OBJ_ELF */
31710 /* Parse a .cpu directive. */
31713 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
31715 const struct arm_cpu_option_table *opt;
31719 name = input_line_pointer;
31720 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31721 input_line_pointer++;
31722 saved_char = *input_line_pointer;
31723 *input_line_pointer = 0;
31725 /* Skip the first "all" entry. */
31726 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
31727 if (streq (opt->name, name))
31729 selected_arch = opt->value;
31730 selected_ext = opt->ext;
31731 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31732 if (opt->canonical_name)
31733 strcpy (selected_cpu_name, opt->canonical_name);
31737 for (i = 0; opt->name[i]; i++)
31738 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31740 selected_cpu_name[i] = 0;
31742 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31744 *input_line_pointer = saved_char;
31745 demand_empty_rest_of_line ();
31748 as_bad (_("unknown cpu `%s'"), name);
31749 *input_line_pointer = saved_char;
31750 ignore_rest_of_line ();
31753 /* Parse a .arch directive. */
31756 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
31758 const struct arm_arch_option_table *opt;
31762 name = input_line_pointer;
31763 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31764 input_line_pointer++;
31765 saved_char = *input_line_pointer;
31766 *input_line_pointer = 0;
31768 /* Skip the first "all" entry. */
31769 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31770 if (streq (opt->name, name))
31772 selected_arch = opt->value;
31773 selected_ext = arm_arch_none;
31774 selected_cpu = selected_arch;
31775 strcpy (selected_cpu_name, opt->name);
31776 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31777 *input_line_pointer = saved_char;
31778 demand_empty_rest_of_line ();
31782 as_bad (_("unknown architecture `%s'\n"), name);
31783 *input_line_pointer = saved_char;
31784 ignore_rest_of_line ();
31787 /* Parse a .object_arch directive. */
31790 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
31792 const struct arm_arch_option_table *opt;
31796 name = input_line_pointer;
31797 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31798 input_line_pointer++;
31799 saved_char = *input_line_pointer;
31800 *input_line_pointer = 0;
31802 /* Skip the first "all" entry. */
31803 for (opt = arm_archs + 1; opt->name != NULL; opt++)
31804 if (streq (opt->name, name))
31806 selected_object_arch = opt->value;
31807 *input_line_pointer = saved_char;
31808 demand_empty_rest_of_line ();
31812 as_bad (_("unknown architecture `%s'\n"), name);
31813 *input_line_pointer = saved_char;
31814 ignore_rest_of_line ();
31817 /* Parse a .arch_extension directive. */
31820 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
31822 const struct arm_option_extension_value_table *opt;
31825 int adding_value = 1;
31827 name = input_line_pointer;
31828 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31829 input_line_pointer++;
31830 saved_char = *input_line_pointer;
31831 *input_line_pointer = 0;
31833 if (strlen (name) >= 2
31834 && strncmp (name, "no", 2) == 0)
31840 for (opt = arm_extensions; opt->name != NULL; opt++)
31841 if (streq (opt->name, name))
31843 int i, nb_allowed_archs =
31844 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
31845 for (i = 0; i < nb_allowed_archs; i++)
31848 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
31850 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
31854 if (i == nb_allowed_archs)
31856 as_bad (_("architectural extension `%s' is not allowed for the "
31857 "current base architecture"), name);
31862 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
31865 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
31867 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
31868 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31869 *input_line_pointer = saved_char;
31870 demand_empty_rest_of_line ();
31871 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31872 on this return so that duplicate extensions (extensions with the
31873 same name as a previous extension in the list) are not considered
31874 for command-line parsing. */
31878 if (opt->name == NULL)
31879 as_bad (_("unknown architecture extension `%s'\n"), name);
31881 *input_line_pointer = saved_char;
31882 ignore_rest_of_line ();
31885 /* Parse a .fpu directive. */
31888 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
31890 const struct arm_option_fpu_value_table *opt;
31894 name = input_line_pointer;
31895 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
31896 input_line_pointer++;
31897 saved_char = *input_line_pointer;
31898 *input_line_pointer = 0;
31900 for (opt = arm_fpus; opt->name != NULL; opt++)
31901 if (streq (opt->name, name))
31903 selected_fpu = opt->value;
31904 #ifndef CPU_DEFAULT
31905 if (no_cpu_selected ())
31906 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
31909 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
31910 *input_line_pointer = saved_char;
31911 demand_empty_rest_of_line ();
31915 as_bad (_("unknown floating point format `%s'\n"), name);
31916 *input_line_pointer = saved_char;
31917 ignore_rest_of_line ();
31920 /* Copy symbol information. */
31923 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
31925 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
31929 /* Given a symbolic attribute NAME, return the proper integer value.
31930 Returns -1 if the attribute is not known. */
31933 arm_convert_symbolic_attribute (const char *name)
31935 static const struct
31940 attribute_table[] =
31942 /* When you modify this table you should
31943 also modify the list in doc/c-arm.texi. */
31944 #define T(tag) {#tag, tag}
31945 T (Tag_CPU_raw_name),
31948 T (Tag_CPU_arch_profile),
31949 T (Tag_ARM_ISA_use),
31950 T (Tag_THUMB_ISA_use),
31954 T (Tag_Advanced_SIMD_arch),
31955 T (Tag_PCS_config),
31956 T (Tag_ABI_PCS_R9_use),
31957 T (Tag_ABI_PCS_RW_data),
31958 T (Tag_ABI_PCS_RO_data),
31959 T (Tag_ABI_PCS_GOT_use),
31960 T (Tag_ABI_PCS_wchar_t),
31961 T (Tag_ABI_FP_rounding),
31962 T (Tag_ABI_FP_denormal),
31963 T (Tag_ABI_FP_exceptions),
31964 T (Tag_ABI_FP_user_exceptions),
31965 T (Tag_ABI_FP_number_model),
31966 T (Tag_ABI_align_needed),
31967 T (Tag_ABI_align8_needed),
31968 T (Tag_ABI_align_preserved),
31969 T (Tag_ABI_align8_preserved),
31970 T (Tag_ABI_enum_size),
31971 T (Tag_ABI_HardFP_use),
31972 T (Tag_ABI_VFP_args),
31973 T (Tag_ABI_WMMX_args),
31974 T (Tag_ABI_optimization_goals),
31975 T (Tag_ABI_FP_optimization_goals),
31976 T (Tag_compatibility),
31977 T (Tag_CPU_unaligned_access),
31978 T (Tag_FP_HP_extension),
31979 T (Tag_VFP_HP_extension),
31980 T (Tag_ABI_FP_16bit_format),
31981 T (Tag_MPextension_use),
31983 T (Tag_nodefaults),
31984 T (Tag_also_compatible_with),
31985 T (Tag_conformance),
31987 T (Tag_Virtualization_use),
31988 T (Tag_DSP_extension),
31990 /* We deliberately do not include Tag_MPextension_use_legacy. */
31998 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
31999 if (streq (name, attribute_table[i].name))
32000 return attribute_table[i].tag;
32005 /* Apply sym value for relocations only in the case that they are for
32006 local symbols in the same segment as the fixup and you have the
32007 respective architectural feature for blx and simple switches. */
32010 arm_apply_sym_value (struct fix * fixP, segT this_seg)
32013 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
32014 /* PR 17444: If the local symbol is in a different section then a reloc
32015 will always be generated for it, so applying the symbol value now
32016 will result in a double offset being stored in the relocation. */
32017 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
32018 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
32020 switch (fixP->fx_r_type)
32022 case BFD_RELOC_ARM_PCREL_BLX:
32023 case BFD_RELOC_THUMB_PCREL_BRANCH23:
32024 if (ARM_IS_FUNC (fixP->fx_addsy))
32028 case BFD_RELOC_ARM_PCREL_CALL:
32029 case BFD_RELOC_THUMB_PCREL_BLX:
32030 if (THUMB_IS_FUNC (fixP->fx_addsy))
32041 #endif /* OBJ_ELF */