1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
354 /* The maximum number of operands we need. */
355 #define ARM_IT_MAX_OPERANDS 6
360 unsigned long instruction;
364 /* "uncond_value" is set to the value in place of the conditional field in
365 unconditional versions of the instruction, or -1 if nothing is
368 struct neon_type vectype;
369 /* This does not indicate an actual NEON instruction, only that
370 the mnemonic accepts neon-style type suffixes. */
372 /* Set to the opcode if the instruction needs relaxation.
373 Zero if the instruction is not relaxed. */
377 bfd_reloc_code_real_type type;
382 enum it_instruction_type it_insn_type;
388 struct neon_type_el vectype;
389 unsigned present : 1; /* Operand present. */
390 unsigned isreg : 1; /* Operand was a register. */
391 unsigned immisreg : 1; /* .imm field is a second register. */
392 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
393 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
394 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
395 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
396 instructions. This allows us to disambiguate ARM <-> vector insns. */
397 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
398 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
399 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
400 unsigned issingle : 1; /* Operand is VFP single-precision register. */
401 unsigned hasreloc : 1; /* Operand has relocation suffix. */
402 unsigned writeback : 1; /* Operand has trailing ! */
403 unsigned preind : 1; /* Preindexed address. */
404 unsigned postind : 1; /* Postindexed address. */
405 unsigned negative : 1; /* Index register was negated. */
406 unsigned shifted : 1; /* Shift applied to operation. */
407 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 } operands[ARM_IT_MAX_OPERANDS];
411 static struct arm_it inst;
413 #define NUM_FLOAT_VALS 8
415 const char * fp_const[] =
417 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
420 /* Number of littlenums required to hold an extended precision number. */
421 #define MAX_LITTLENUMS 6
423 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
433 #define CP_T_X 0x00008000
434 #define CP_T_Y 0x00400000
436 #define CONDS_BIT 0x00100000
437 #define LOAD_BIT 0x00100000
439 #define DOUBLE_LOAD_FLAG 0x00000001
443 const char * template_name;
447 #define COND_ALWAYS 0xE
451 const char * template_name;
455 struct asm_barrier_opt
457 const char * template_name;
461 /* The bit that distinguishes CPSR and SPSR. */
462 #define SPSR_BIT (1 << 22)
464 /* The individual PSR flag bits. */
465 #define PSR_c (1 << 16)
466 #define PSR_x (1 << 17)
467 #define PSR_s (1 << 18)
468 #define PSR_f (1 << 19)
473 bfd_reloc_code_real_type reloc;
478 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
479 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
484 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
487 /* Bits for DEFINED field in neon_typed_alias. */
488 #define NTA_HASTYPE 1
489 #define NTA_HASINDEX 2
491 struct neon_typed_alias
493 unsigned char defined;
495 struct neon_type_el eltype;
498 /* ARM register categories. This includes coprocessor numbers and various
499 architecture extensions' registers. */
526 /* Structure for a hash table entry for a register.
527 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
528 information which states whether a vector type or index is specified (for a
529 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
535 unsigned char builtin;
536 struct neon_typed_alias * neon;
539 /* Diagnostics used when we don't get a register of the expected type. */
540 const char * const reg_expected_msgs[] =
542 N_("ARM register expected"),
543 N_("bad or missing co-processor number"),
544 N_("co-processor register expected"),
545 N_("FPA register expected"),
546 N_("VFP single precision register expected"),
547 N_("VFP/Neon double precision register expected"),
548 N_("Neon quad precision register expected"),
549 N_("VFP single or double precision register expected"),
550 N_("Neon double or quad precision register expected"),
551 N_("VFP single, double or Neon quad precision register expected"),
552 N_("VFP system register expected"),
553 N_("Maverick MVF register expected"),
554 N_("Maverick MVD register expected"),
555 N_("Maverick MVFX register expected"),
556 N_("Maverick MVDX register expected"),
557 N_("Maverick MVAX register expected"),
558 N_("Maverick DSPSC register expected"),
559 N_("iWMMXt data register expected"),
560 N_("iWMMXt control register expected"),
561 N_("iWMMXt scalar register expected"),
562 N_("XScale accumulator register expected"),
565 /* Some well known registers that we refer to directly elsewhere. */
571 /* ARM instructions take 4bytes in the object file, Thumb instructions
577 /* Basic string to match. */
578 const char * template_name;
580 /* Parameters to instruction. */
581 unsigned int operands[8];
583 /* Conditional tag - see opcode_lookup. */
584 unsigned int tag : 4;
586 /* Basic instruction code. */
587 unsigned int avalue : 28;
589 /* Thumb-format instruction code. */
592 /* Which architecture variant provides this instruction. */
593 const arm_feature_set * avariant;
594 const arm_feature_set * tvariant;
596 /* Function to call to encode instruction in ARM format. */
597 void (* aencode) (void);
599 /* Function to call to encode instruction in Thumb format. */
600 void (* tencode) (void);
603 /* Defines for various bits that we will want to toggle. */
604 #define INST_IMMEDIATE 0x02000000
605 #define OFFSET_REG 0x02000000
606 #define HWOFFSET_IMM 0x00400000
607 #define SHIFT_BY_REG 0x00000010
608 #define PRE_INDEX 0x01000000
609 #define INDEX_UP 0x00800000
610 #define WRITE_BACK 0x00200000
611 #define LDM_TYPE_2_OR_3 0x00400000
612 #define CPSI_MMOD 0x00020000
614 #define LITERAL_MASK 0xf000f000
615 #define OPCODE_MASK 0xfe1fffff
616 #define V4_STR_BIT 0x00000020
618 #define T2_SUBS_PC_LR 0xf3de8f00
620 #define DATA_OP_SHIFT 21
622 #define T2_OPCODE_MASK 0xfe1fffff
623 #define T2_DATA_OP_SHIFT 21
625 /* Codes to distinguish the arithmetic instructions. */
636 #define OPCODE_CMP 10
637 #define OPCODE_CMN 11
638 #define OPCODE_ORR 12
639 #define OPCODE_MOV 13
640 #define OPCODE_BIC 14
641 #define OPCODE_MVN 15
643 #define T2_OPCODE_AND 0
644 #define T2_OPCODE_BIC 1
645 #define T2_OPCODE_ORR 2
646 #define T2_OPCODE_ORN 3
647 #define T2_OPCODE_EOR 4
648 #define T2_OPCODE_ADD 8
649 #define T2_OPCODE_ADC 10
650 #define T2_OPCODE_SBC 11
651 #define T2_OPCODE_SUB 13
652 #define T2_OPCODE_RSB 14
654 #define T_OPCODE_MUL 0x4340
655 #define T_OPCODE_TST 0x4200
656 #define T_OPCODE_CMN 0x42c0
657 #define T_OPCODE_NEG 0x4240
658 #define T_OPCODE_MVN 0x43c0
660 #define T_OPCODE_ADD_R3 0x1800
661 #define T_OPCODE_SUB_R3 0x1a00
662 #define T_OPCODE_ADD_HI 0x4400
663 #define T_OPCODE_ADD_ST 0xb000
664 #define T_OPCODE_SUB_ST 0xb080
665 #define T_OPCODE_ADD_SP 0xa800
666 #define T_OPCODE_ADD_PC 0xa000
667 #define T_OPCODE_ADD_I8 0x3000
668 #define T_OPCODE_SUB_I8 0x3800
669 #define T_OPCODE_ADD_I3 0x1c00
670 #define T_OPCODE_SUB_I3 0x1e00
672 #define T_OPCODE_ASR_R 0x4100
673 #define T_OPCODE_LSL_R 0x4080
674 #define T_OPCODE_LSR_R 0x40c0
675 #define T_OPCODE_ROR_R 0x41c0
676 #define T_OPCODE_ASR_I 0x1000
677 #define T_OPCODE_LSL_I 0x0000
678 #define T_OPCODE_LSR_I 0x0800
680 #define T_OPCODE_MOV_I8 0x2000
681 #define T_OPCODE_CMP_I8 0x2800
682 #define T_OPCODE_CMP_LR 0x4280
683 #define T_OPCODE_MOV_HR 0x4600
684 #define T_OPCODE_CMP_HR 0x4500
686 #define T_OPCODE_LDR_PC 0x4800
687 #define T_OPCODE_LDR_SP 0x9800
688 #define T_OPCODE_STR_SP 0x9000
689 #define T_OPCODE_LDR_IW 0x6800
690 #define T_OPCODE_STR_IW 0x6000
691 #define T_OPCODE_LDR_IH 0x8800
692 #define T_OPCODE_STR_IH 0x8000
693 #define T_OPCODE_LDR_IB 0x7800
694 #define T_OPCODE_STR_IB 0x7000
695 #define T_OPCODE_LDR_RW 0x5800
696 #define T_OPCODE_STR_RW 0x5000
697 #define T_OPCODE_LDR_RH 0x5a00
698 #define T_OPCODE_STR_RH 0x5200
699 #define T_OPCODE_LDR_RB 0x5c00
700 #define T_OPCODE_STR_RB 0x5400
702 #define T_OPCODE_PUSH 0xb400
703 #define T_OPCODE_POP 0xbc00
705 #define T_OPCODE_BRANCH 0xe000
707 #define THUMB_SIZE 2 /* Size of thumb instruction. */
708 #define THUMB_PP_PC_LR 0x0100
709 #define THUMB_LOAD_BIT 0x0800
710 #define THUMB2_LOAD_BIT 0x00100000
712 #define BAD_ARGS _("bad arguments to instruction")
713 #define BAD_SP _("r13 not allowed here")
714 #define BAD_PC _("r15 not allowed here")
715 #define BAD_COND _("instruction cannot be conditional")
716 #define BAD_OVERLAP _("registers may not be the same")
717 #define BAD_HIREG _("lo register required")
718 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
719 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
720 #define BAD_BRANCH _("branch must be last instruction in IT block")
721 #define BAD_NOT_IT _("instruction not allowed in IT block")
722 #define BAD_FPU _("selected FPU does not support instruction")
723 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
724 #define BAD_IT_COND _("incorrect condition in IT block")
725 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
726 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
727 #define BAD_PC_ADDRESSING \
728 _("cannot use register index with PC-relative addressing")
729 #define BAD_PC_WRITEBACK \
730 _("cannot use writeback with PC-relative addressing")
731 #define BAD_RANGE _("branch out of range")
733 static struct hash_control * arm_ops_hsh;
734 static struct hash_control * arm_cond_hsh;
735 static struct hash_control * arm_shift_hsh;
736 static struct hash_control * arm_psr_hsh;
737 static struct hash_control * arm_v7m_psr_hsh;
738 static struct hash_control * arm_reg_hsh;
739 static struct hash_control * arm_reloc_hsh;
740 static struct hash_control * arm_barrier_opt_hsh;
742 /* Stuff needed to resolve the label ambiguity
751 symbolS * last_label_seen;
752 static int label_is_thumb_function_name = FALSE;
754 /* Literal pool structure. Held on a per-section
755 and per-sub-section basis. */
757 #define MAX_LITERAL_POOL_SIZE 1024
758 typedef struct literal_pool
760 expressionS literals [MAX_LITERAL_POOL_SIZE];
761 unsigned int next_free_entry;
767 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
769 struct literal_pool * next;
772 /* Pointer to a linked list of literal pools. */
773 literal_pool * list_of_pools = NULL;
776 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
778 static struct current_it now_it;
782 now_it_compatible (int cond)
784 return (cond & ~1) == (now_it.cc & ~1);
788 conditional_insn (void)
790 return inst.cond != COND_ALWAYS;
793 static int in_it_block (void);
795 static int handle_it_state (void);
797 static void force_automatic_it_block_close (void);
799 static void it_fsm_post_encode (void);
801 #define set_it_insn_type(type) \
804 inst.it_insn_type = type; \
805 if (handle_it_state () == FAIL) \
810 #define set_it_insn_type_nonvoid(type, failret) \
813 inst.it_insn_type = type; \
814 if (handle_it_state () == FAIL) \
819 #define set_it_insn_type_last() \
822 if (inst.cond == COND_ALWAYS) \
823 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
825 set_it_insn_type (INSIDE_IT_LAST_INSN); \
831 /* This array holds the chars that always start a comment. If the
832 pre-processor is disabled, these aren't very useful. */
833 const char comment_chars[] = "@";
835 /* This array holds the chars that only start a comment at the beginning of
836 a line. If the line seems to have the form '# 123 filename'
837 .line and .file directives will appear in the pre-processed output. */
838 /* Note that input_file.c hand checks for '#' at the beginning of the
839 first line of the input file. This is because the compiler outputs
840 #NO_APP at the beginning of its output. */
841 /* Also note that comments like this one will always work. */
842 const char line_comment_chars[] = "#";
844 const char line_separator_chars[] = ";";
846 /* Chars that can be used to separate mant
847 from exp in floating point numbers. */
848 const char EXP_CHARS[] = "eE";
850 /* Chars that mean this number is a floating point constant. */
854 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
856 /* Prefix characters that indicate the start of an immediate
858 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
860 /* Separator character handling. */
862 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
865 skip_past_char (char ** str, char c)
876 #define skip_past_comma(str) skip_past_char (str, ',')
878 /* Arithmetic expressions (possibly involving symbols). */
880 /* Return TRUE if anything in the expression is a bignum. */
883 walk_no_bignums (symbolS * sp)
885 if (symbol_get_value_expression (sp)->X_op == O_big)
888 if (symbol_get_value_expression (sp)->X_add_symbol)
890 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
891 || (symbol_get_value_expression (sp)->X_op_symbol
892 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
898 static int in_my_get_expression = 0;
900 /* Third argument to my_get_expression. */
901 #define GE_NO_PREFIX 0
902 #define GE_IMM_PREFIX 1
903 #define GE_OPT_PREFIX 2
904 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
905 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
906 #define GE_OPT_PREFIX_BIG 3
909 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
914 /* In unified syntax, all prefixes are optional. */
916 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
921 case GE_NO_PREFIX: break;
923 if (!is_immediate_prefix (**str))
925 inst.error = _("immediate expression requires a # prefix");
931 case GE_OPT_PREFIX_BIG:
932 if (is_immediate_prefix (**str))
938 memset (ep, 0, sizeof (expressionS));
940 save_in = input_line_pointer;
941 input_line_pointer = *str;
942 in_my_get_expression = 1;
943 seg = expression (ep);
944 in_my_get_expression = 0;
946 if (ep->X_op == O_illegal || ep->X_op == O_absent)
948 /* We found a bad or missing expression in md_operand(). */
949 *str = input_line_pointer;
950 input_line_pointer = save_in;
951 if (inst.error == NULL)
952 inst.error = (ep->X_op == O_absent
953 ? _("missing expression") :_("bad expression"));
958 if (seg != absolute_section
959 && seg != text_section
960 && seg != data_section
961 && seg != bss_section
962 && seg != undefined_section)
964 inst.error = _("bad segment");
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
973 /* Get rid of any bignums now, so that we don't generate an error for which
974 we can't establish a line number later on. Big numbers are never valid
975 in instructions, which is where this routine is always called. */
976 if (prefix_mode != GE_OPT_PREFIX_BIG
977 && (ep->X_op == O_big
979 && (walk_no_bignums (ep->X_add_symbol)
981 && walk_no_bignums (ep->X_op_symbol))))))
983 inst.error = _("invalid constant");
984 *str = input_line_pointer;
985 input_line_pointer = save_in;
989 *str = input_line_pointer;
990 input_line_pointer = save_in;
994 /* Turn a string in input_line_pointer into a floating point constant
995 of type TYPE, and store the appropriate bytes in *LITP. The number
996 of LITTLENUMS emitted is stored in *SIZEP. An error message is
997 returned, or NULL on OK.
999 Note that fp constants aren't represent in the normal way on the ARM.
1000 In big endian mode, things are as expected. However, in little endian
1001 mode fp constants are big-endian word-wise, and little-endian byte-wise
1002 within the words. For example, (double) 1.1 in big endian mode is
1003 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1004 the byte sequence 99 99 f1 3f 9a 99 99 99.
1006 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1009 md_atof (int type, char * litP, int * sizeP)
1012 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1044 return _("Unrecognized or unsupported floating point constant");
1047 t = atof_ieee (input_line_pointer, type, words);
1049 input_line_pointer = t;
1050 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1052 if (target_big_endian)
1054 for (i = 0; i < prec; i++)
1056 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1057 litP += sizeof (LITTLENUM_TYPE);
1062 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1063 for (i = prec - 1; i >= 0; i--)
1065 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1066 litP += sizeof (LITTLENUM_TYPE);
1069 /* For a 4 byte float the order of elements in `words' is 1 0.
1070 For an 8 byte float the order is 1 0 3 2. */
1071 for (i = 0; i < prec; i += 2)
1073 md_number_to_chars (litP, (valueT) words[i + 1],
1074 sizeof (LITTLENUM_TYPE));
1075 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1076 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1077 litP += 2 * sizeof (LITTLENUM_TYPE);
1084 /* We handle all bad expressions here, so that we can report the faulty
1085 instruction in the error message. */
1087 md_operand (expressionS * exp)
1089 if (in_my_get_expression)
1090 exp->X_op = O_illegal;
1093 /* Immediate values. */
1095 /* Generic immediate-value read function for use in directives.
1096 Accepts anything that 'expression' can fold to a constant.
1097 *val receives the number. */
1100 immediate_for_directive (int *val)
1103 exp.X_op = O_illegal;
1105 if (is_immediate_prefix (*input_line_pointer))
1107 input_line_pointer++;
1111 if (exp.X_op != O_constant)
1113 as_bad (_("expected #constant"));
1114 ignore_rest_of_line ();
1117 *val = exp.X_add_number;
1122 /* Register parsing. */
1124 /* Generic register parser. CCP points to what should be the
1125 beginning of a register name. If it is indeed a valid register
1126 name, advance CCP over it and return the reg_entry structure;
1127 otherwise return NULL. Does not issue diagnostics. */
1129 static struct reg_entry *
1130 arm_reg_parse_multi (char **ccp)
1134 struct reg_entry *reg;
1136 #ifdef REGISTER_PREFIX
1137 if (*start != REGISTER_PREFIX)
1141 #ifdef OPTIONAL_REGISTER_PREFIX
1142 if (*start == OPTIONAL_REGISTER_PREFIX)
1147 if (!ISALPHA (*p) || !is_name_beginner (*p))
1152 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1154 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1164 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1165 enum arm_reg_type type)
1167 /* Alternative syntaxes are accepted for a few register classes. */
1174 /* Generic coprocessor register names are allowed for these. */
1175 if (reg && reg->type == REG_TYPE_CN)
1180 /* For backward compatibility, a bare number is valid here. */
1182 unsigned long processor = strtoul (start, ccp, 10);
1183 if (*ccp != start && processor <= 15)
1187 case REG_TYPE_MMXWC:
1188 /* WC includes WCG. ??? I'm not sure this is true for all
1189 instructions that take WC registers. */
1190 if (reg && reg->type == REG_TYPE_MMXWCG)
1201 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1202 return value is the register number or FAIL. */
1205 arm_reg_parse (char **ccp, enum arm_reg_type type)
1208 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1211 /* Do not allow a scalar (reg+index) to parse as a register. */
1212 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1215 if (reg && reg->type == type)
1218 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1225 /* Parse a Neon type specifier. *STR should point at the leading '.'
1226 character. Does no verification at this stage that the type fits the opcode
1233 Can all be legally parsed by this function.
1235 Fills in neon_type struct pointer with parsed information, and updates STR
1236 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1237 type, FAIL if not. */
1240 parse_neon_type (struct neon_type *type, char **str)
1247 while (type->elems < NEON_MAX_TYPE_ELS)
1249 enum neon_el_type thistype = NT_untyped;
1250 unsigned thissize = -1u;
1257 /* Just a size without an explicit type. */
1261 switch (TOLOWER (*ptr))
1263 case 'i': thistype = NT_integer; break;
1264 case 'f': thistype = NT_float; break;
1265 case 'p': thistype = NT_poly; break;
1266 case 's': thistype = NT_signed; break;
1267 case 'u': thistype = NT_unsigned; break;
1269 thistype = NT_float;
1274 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1280 /* .f is an abbreviation for .f32. */
1281 if (thistype == NT_float && !ISDIGIT (*ptr))
1286 thissize = strtoul (ptr, &ptr, 10);
1288 if (thissize != 8 && thissize != 16 && thissize != 32
1291 as_bad (_("bad size %d in type specifier"), thissize);
1299 type->el[type->elems].type = thistype;
1300 type->el[type->elems].size = thissize;
1305 /* Empty/missing type is not a successful parse. */
1306 if (type->elems == 0)
1314 /* Errors may be set multiple times during parsing or bit encoding
1315 (particularly in the Neon bits), but usually the earliest error which is set
1316 will be the most meaningful. Avoid overwriting it with later (cascading)
1317 errors by calling this function. */
1320 first_error (const char *err)
1326 /* Parse a single type, e.g. ".s32", leading period included. */
1328 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1331 struct neon_type optype;
1335 if (parse_neon_type (&optype, &str) == SUCCESS)
1337 if (optype.elems == 1)
1338 *vectype = optype.el[0];
1341 first_error (_("only one type should be specified for operand"));
1347 first_error (_("vector type expected"));
1359 /* Special meanings for indices (which have a range of 0-7), which will fit into
1362 #define NEON_ALL_LANES 15
1363 #define NEON_INTERLEAVE_LANES 14
1365 /* Parse either a register or a scalar, with an optional type. Return the
1366 register number, and optionally fill in the actual type of the register
1367 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1368 type/index information in *TYPEINFO. */
1371 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1372 enum arm_reg_type *rtype,
1373 struct neon_typed_alias *typeinfo)
1376 struct reg_entry *reg = arm_reg_parse_multi (&str);
1377 struct neon_typed_alias atype;
1378 struct neon_type_el parsetype;
1382 atype.eltype.type = NT_invtype;
1383 atype.eltype.size = -1;
1385 /* Try alternate syntax for some types of register. Note these are mutually
1386 exclusive with the Neon syntax extensions. */
1389 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1397 /* Undo polymorphism when a set of register types may be accepted. */
1398 if ((type == REG_TYPE_NDQ
1399 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1400 || (type == REG_TYPE_VFSD
1401 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1402 || (type == REG_TYPE_NSDQ
1403 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1404 || reg->type == REG_TYPE_NQ))
1405 || (type == REG_TYPE_MMXWC
1406 && (reg->type == REG_TYPE_MMXWCG)))
1407 type = (enum arm_reg_type) reg->type;
1409 if (type != reg->type)
1415 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1417 if ((atype.defined & NTA_HASTYPE) != 0)
1419 first_error (_("can't redefine type for operand"));
1422 atype.defined |= NTA_HASTYPE;
1423 atype.eltype = parsetype;
1426 if (skip_past_char (&str, '[') == SUCCESS)
1428 if (type != REG_TYPE_VFD)
1430 first_error (_("only D registers may be indexed"));
1434 if ((atype.defined & NTA_HASINDEX) != 0)
1436 first_error (_("can't change index for operand"));
1440 atype.defined |= NTA_HASINDEX;
1442 if (skip_past_char (&str, ']') == SUCCESS)
1443 atype.index = NEON_ALL_LANES;
1448 my_get_expression (&exp, &str, GE_NO_PREFIX);
1450 if (exp.X_op != O_constant)
1452 first_error (_("constant expression required"));
1456 if (skip_past_char (&str, ']') == FAIL)
1459 atype.index = exp.X_add_number;
1474 /* Like arm_reg_parse, but allow allow the following extra features:
1475 - If RTYPE is non-zero, return the (possibly restricted) type of the
1476 register (e.g. Neon double or quad reg when either has been requested).
1477 - If this is a Neon vector type with additional type information, fill
1478 in the struct pointed to by VECTYPE (if non-NULL).
1479 This function will fault on encountering a scalar. */
1482 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1483 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1485 struct neon_typed_alias atype;
1487 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1492 /* Do not allow regname(... to parse as a register. */
1496 /* Do not allow a scalar (reg+index) to parse as a register. */
1497 if ((atype.defined & NTA_HASINDEX) != 0)
1499 first_error (_("register operand expected, but got scalar"));
1504 *vectype = atype.eltype;
1511 #define NEON_SCALAR_REG(X) ((X) >> 4)
1512 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1514 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1515 have enough information to be able to do a good job bounds-checking. So, we
1516 just do easy checks here, and do further checks later. */
1519 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1523 struct neon_typed_alias atype;
1525 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1527 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1530 if (atype.index == NEON_ALL_LANES)
1532 first_error (_("scalar must have an index"));
1535 else if (atype.index >= 64 / elsize)
1537 first_error (_("scalar index out of range"));
1542 *type = atype.eltype;
1546 return reg * 16 + atype.index;
1549 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1552 parse_reg_list (char ** strp)
1554 char * str = * strp;
1558 /* We come back here if we get ranges concatenated by '+' or '|'. */
1573 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1575 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1585 first_error (_("bad range in register list"));
1589 for (i = cur_reg + 1; i < reg; i++)
1591 if (range & (1 << i))
1593 (_("Warning: duplicated register (r%d) in register list"),
1601 if (range & (1 << reg))
1602 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1604 else if (reg <= cur_reg)
1605 as_tsktsk (_("Warning: register range not in ascending order"));
1610 while (skip_past_comma (&str) != FAIL
1611 || (in_range = 1, *str++ == '-'));
1616 first_error (_("missing `}'"));
1624 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1627 if (exp.X_op == O_constant)
1629 if (exp.X_add_number
1630 != (exp.X_add_number & 0x0000ffff))
1632 inst.error = _("invalid register mask");
1636 if ((range & exp.X_add_number) != 0)
1638 int regno = range & exp.X_add_number;
1641 regno = (1 << regno) - 1;
1643 (_("Warning: duplicated register (r%d) in register list"),
1647 range |= exp.X_add_number;
1651 if (inst.reloc.type != 0)
1653 inst.error = _("expression too complex");
1657 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1658 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1659 inst.reloc.pc_rel = 0;
1663 if (*str == '|' || *str == '+')
1669 while (another_range);
1675 /* Types of registers in a list. */
1684 /* Parse a VFP register list. If the string is invalid return FAIL.
1685 Otherwise return the number of registers, and set PBASE to the first
1686 register. Parses registers of type ETYPE.
1687 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1688 - Q registers can be used to specify pairs of D registers
1689 - { } can be omitted from around a singleton register list
1690 FIXME: This is not implemented, as it would require backtracking in
1693 This could be done (the meaning isn't really ambiguous), but doesn't
1694 fit in well with the current parsing framework.
1695 - 32 D registers may be used (also true for VFPv3).
1696 FIXME: Types are ignored in these register lists, which is probably a
1700 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1705 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1709 unsigned long mask = 0;
1714 inst.error = _("expecting {");
1723 regtype = REG_TYPE_VFS;
1728 regtype = REG_TYPE_VFD;
1731 case REGLIST_NEON_D:
1732 regtype = REG_TYPE_NDQ;
1736 if (etype != REGLIST_VFP_S)
1738 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1739 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1743 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1746 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1753 base_reg = max_regs;
1757 int setmask = 1, addregs = 1;
1759 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1761 if (new_base == FAIL)
1763 first_error (_(reg_expected_msgs[regtype]));
1767 if (new_base >= max_regs)
1769 first_error (_("register out of range in list"));
1773 /* Note: a value of 2 * n is returned for the register Q<n>. */
1774 if (regtype == REG_TYPE_NQ)
1780 if (new_base < base_reg)
1781 base_reg = new_base;
1783 if (mask & (setmask << new_base))
1785 first_error (_("invalid register list"));
1789 if ((mask >> new_base) != 0 && ! warned)
1791 as_tsktsk (_("register list not in ascending order"));
1795 mask |= setmask << new_base;
1798 if (*str == '-') /* We have the start of a range expression */
1804 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1807 inst.error = gettext (reg_expected_msgs[regtype]);
1811 if (high_range >= max_regs)
1813 first_error (_("register out of range in list"));
1817 if (regtype == REG_TYPE_NQ)
1818 high_range = high_range + 1;
1820 if (high_range <= new_base)
1822 inst.error = _("register range not in ascending order");
1826 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1828 if (mask & (setmask << new_base))
1830 inst.error = _("invalid register list");
1834 mask |= setmask << new_base;
1839 while (skip_past_comma (&str) != FAIL);
1843 /* Sanity check -- should have raised a parse error above. */
1844 if (count == 0 || count > max_regs)
1849 /* Final test -- the registers must be consecutive. */
1851 for (i = 0; i < count; i++)
1853 if ((mask & (1u << i)) == 0)
1855 inst.error = _("non-contiguous register range");
1865 /* True if two alias types are the same. */
1868 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1876 if (a->defined != b->defined)
1879 if ((a->defined & NTA_HASTYPE) != 0
1880 && (a->eltype.type != b->eltype.type
1881 || a->eltype.size != b->eltype.size))
1884 if ((a->defined & NTA_HASINDEX) != 0
1885 && (a->index != b->index))
1891 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1892 The base register is put in *PBASE.
1893 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1895 The register stride (minus one) is put in bit 4 of the return value.
1896 Bits [6:5] encode the list length (minus one).
1897 The type of the list elements is put in *ELTYPE, if non-NULL. */
1899 #define NEON_LANE(X) ((X) & 0xf)
1900 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1901 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1904 parse_neon_el_struct_list (char **str, unsigned *pbase,
1905 struct neon_type_el *eltype)
1912 int leading_brace = 0;
1913 enum arm_reg_type rtype = REG_TYPE_NDQ;
1914 const char *const incr_error = _("register stride must be 1 or 2");
1915 const char *const type_error = _("mismatched element/structure types in list");
1916 struct neon_typed_alias firsttype;
1918 if (skip_past_char (&ptr, '{') == SUCCESS)
1923 struct neon_typed_alias atype;
1924 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1928 first_error (_(reg_expected_msgs[rtype]));
1935 if (rtype == REG_TYPE_NQ)
1941 else if (reg_incr == -1)
1943 reg_incr = getreg - base_reg;
1944 if (reg_incr < 1 || reg_incr > 2)
1946 first_error (_(incr_error));
1950 else if (getreg != base_reg + reg_incr * count)
1952 first_error (_(incr_error));
1956 if (! neon_alias_types_same (&atype, &firsttype))
1958 first_error (_(type_error));
1962 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1966 struct neon_typed_alias htype;
1967 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1969 lane = NEON_INTERLEAVE_LANES;
1970 else if (lane != NEON_INTERLEAVE_LANES)
1972 first_error (_(type_error));
1977 else if (reg_incr != 1)
1979 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1983 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1986 first_error (_(reg_expected_msgs[rtype]));
1989 if (! neon_alias_types_same (&htype, &firsttype))
1991 first_error (_(type_error));
1994 count += hireg + dregs - getreg;
1998 /* If we're using Q registers, we can't use [] or [n] syntax. */
1999 if (rtype == REG_TYPE_NQ)
2005 if ((atype.defined & NTA_HASINDEX) != 0)
2009 else if (lane != atype.index)
2011 first_error (_(type_error));
2015 else if (lane == -1)
2016 lane = NEON_INTERLEAVE_LANES;
2017 else if (lane != NEON_INTERLEAVE_LANES)
2019 first_error (_(type_error));
2024 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2026 /* No lane set by [x]. We must be interleaving structures. */
2028 lane = NEON_INTERLEAVE_LANES;
2031 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2032 || (count > 1 && reg_incr == -1))
2034 first_error (_("error parsing element/structure list"));
2038 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2040 first_error (_("expected }"));
2048 *eltype = firsttype.eltype;
2053 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2056 /* Parse an explicit relocation suffix on an expression. This is
2057 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2058 arm_reloc_hsh contains no entries, so this function can only
2059 succeed if there is no () after the word. Returns -1 on error,
2060 BFD_RELOC_UNUSED if there wasn't any suffix. */
2063 parse_reloc (char **str)
2065 struct reloc_entry *r;
2069 return BFD_RELOC_UNUSED;
2074 while (*q && *q != ')' && *q != ',')
2079 if ((r = (struct reloc_entry *)
2080 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2087 /* Directives: register aliases. */
2089 static struct reg_entry *
2090 insert_reg_alias (char *str, unsigned number, int type)
2092 struct reg_entry *new_reg;
2095 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2097 if (new_reg->builtin)
2098 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2100 /* Only warn about a redefinition if it's not defined as the
2102 else if (new_reg->number != number || new_reg->type != type)
2103 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2108 name = xstrdup (str);
2109 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2111 new_reg->name = name;
2112 new_reg->number = number;
2113 new_reg->type = type;
2114 new_reg->builtin = FALSE;
2115 new_reg->neon = NULL;
2117 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2124 insert_neon_reg_alias (char *str, int number, int type,
2125 struct neon_typed_alias *atype)
2127 struct reg_entry *reg = insert_reg_alias (str, number, type);
2131 first_error (_("attempt to redefine typed alias"));
2137 reg->neon = (struct neon_typed_alias *)
2138 xmalloc (sizeof (struct neon_typed_alias));
2139 *reg->neon = *atype;
2143 /* Look for the .req directive. This is of the form:
2145 new_register_name .req existing_register_name
2147 If we find one, or if it looks sufficiently like one that we want to
2148 handle any error here, return TRUE. Otherwise return FALSE. */
2151 create_register_alias (char * newname, char *p)
2153 struct reg_entry *old;
2154 char *oldname, *nbuf;
2157 /* The input scrubber ensures that whitespace after the mnemonic is
2158 collapsed to single spaces. */
2160 if (strncmp (oldname, " .req ", 6) != 0)
2164 if (*oldname == '\0')
2167 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2170 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2174 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2175 the desired alias name, and p points to its end. If not, then
2176 the desired alias name is in the global original_case_string. */
2177 #ifdef TC_CASE_SENSITIVE
2180 newname = original_case_string;
2181 nlen = strlen (newname);
2184 nbuf = (char *) alloca (nlen + 1);
2185 memcpy (nbuf, newname, nlen);
2188 /* Create aliases under the new name as stated; an all-lowercase
2189 version of the new name; and an all-uppercase version of the new
2191 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2193 for (p = nbuf; *p; p++)
2196 if (strncmp (nbuf, newname, nlen))
2198 /* If this attempt to create an additional alias fails, do not bother
2199 trying to create the all-lower case alias. We will fail and issue
2200 a second, duplicate error message. This situation arises when the
2201 programmer does something like:
2204 The second .req creates the "Foo" alias but then fails to create
2205 the artificial FOO alias because it has already been created by the
2207 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2211 for (p = nbuf; *p; p++)
2214 if (strncmp (nbuf, newname, nlen))
2215 insert_reg_alias (nbuf, old->number, old->type);
2221 /* Create a Neon typed/indexed register alias using directives, e.g.:
2226 These typed registers can be used instead of the types specified after the
2227 Neon mnemonic, so long as all operands given have types. Types can also be
2228 specified directly, e.g.:
2229 vadd d0.s32, d1.s32, d2.s32 */
2232 create_neon_reg_alias (char *newname, char *p)
2234 enum arm_reg_type basetype;
2235 struct reg_entry *basereg;
2236 struct reg_entry mybasereg;
2237 struct neon_type ntype;
2238 struct neon_typed_alias typeinfo;
2239 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2242 typeinfo.defined = 0;
2243 typeinfo.eltype.type = NT_invtype;
2244 typeinfo.eltype.size = -1;
2245 typeinfo.index = -1;
2249 if (strncmp (p, " .dn ", 5) == 0)
2250 basetype = REG_TYPE_VFD;
2251 else if (strncmp (p, " .qn ", 5) == 0)
2252 basetype = REG_TYPE_NQ;
2261 basereg = arm_reg_parse_multi (&p);
2263 if (basereg && basereg->type != basetype)
2265 as_bad (_("bad type for register"));
2269 if (basereg == NULL)
2272 /* Try parsing as an integer. */
2273 my_get_expression (&exp, &p, GE_NO_PREFIX);
2274 if (exp.X_op != O_constant)
2276 as_bad (_("expression must be constant"));
2279 basereg = &mybasereg;
2280 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2286 typeinfo = *basereg->neon;
2288 if (parse_neon_type (&ntype, &p) == SUCCESS)
2290 /* We got a type. */
2291 if (typeinfo.defined & NTA_HASTYPE)
2293 as_bad (_("can't redefine the type of a register alias"));
2297 typeinfo.defined |= NTA_HASTYPE;
2298 if (ntype.elems != 1)
2300 as_bad (_("you must specify a single type only"));
2303 typeinfo.eltype = ntype.el[0];
2306 if (skip_past_char (&p, '[') == SUCCESS)
2309 /* We got a scalar index. */
2311 if (typeinfo.defined & NTA_HASINDEX)
2313 as_bad (_("can't redefine the index of a scalar alias"));
2317 my_get_expression (&exp, &p, GE_NO_PREFIX);
2319 if (exp.X_op != O_constant)
2321 as_bad (_("scalar index must be constant"));
2325 typeinfo.defined |= NTA_HASINDEX;
2326 typeinfo.index = exp.X_add_number;
2328 if (skip_past_char (&p, ']') == FAIL)
2330 as_bad (_("expecting ]"));
2335 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2336 the desired alias name, and p points to its end. If not, then
2337 the desired alias name is in the global original_case_string. */
2338 #ifdef TC_CASE_SENSITIVE
2339 namelen = nameend - newname;
2341 newname = original_case_string;
2342 namelen = strlen (newname);
2345 namebuf = (char *) alloca (namelen + 1);
2346 strncpy (namebuf, newname, namelen);
2347 namebuf[namelen] = '\0';
2349 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2350 typeinfo.defined != 0 ? &typeinfo : NULL);
2352 /* Insert name in all uppercase. */
2353 for (p = namebuf; *p; p++)
2356 if (strncmp (namebuf, newname, namelen))
2357 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2358 typeinfo.defined != 0 ? &typeinfo : NULL);
2360 /* Insert name in all lowercase. */
2361 for (p = namebuf; *p; p++)
2364 if (strncmp (namebuf, newname, namelen))
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2371 /* Should never be called, as .req goes between the alias and the
2372 register name, not at the beginning of the line. */
2375 s_req (int a ATTRIBUTE_UNUSED)
2377 as_bad (_("invalid syntax for .req directive"));
2381 s_dn (int a ATTRIBUTE_UNUSED)
2383 as_bad (_("invalid syntax for .dn directive"));
2387 s_qn (int a ATTRIBUTE_UNUSED)
2389 as_bad (_("invalid syntax for .qn directive"));
2392 /* The .unreq directive deletes an alias which was previously defined
2393 by .req. For example:
2399 s_unreq (int a ATTRIBUTE_UNUSED)
2404 name = input_line_pointer;
2406 while (*input_line_pointer != 0
2407 && *input_line_pointer != ' '
2408 && *input_line_pointer != '\n')
2409 ++input_line_pointer;
2411 saved_char = *input_line_pointer;
2412 *input_line_pointer = 0;
2415 as_bad (_("invalid syntax for .unreq directive"));
2418 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2422 as_bad (_("unknown register alias '%s'"), name);
2423 else if (reg->builtin)
2424 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2431 hash_delete (arm_reg_hsh, name, FALSE);
2432 free ((char *) reg->name);
2437 /* Also locate the all upper case and all lower case versions.
2438 Do not complain if we cannot find one or the other as it
2439 was probably deleted above. */
2441 nbuf = strdup (name);
2442 for (p = nbuf; *p; p++)
2444 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2447 hash_delete (arm_reg_hsh, nbuf, FALSE);
2448 free ((char *) reg->name);
2454 for (p = nbuf; *p; p++)
2456 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2459 hash_delete (arm_reg_hsh, nbuf, FALSE);
2460 free ((char *) reg->name);
2470 *input_line_pointer = saved_char;
2471 demand_empty_rest_of_line ();
2474 /* Directives: Instruction set selection. */
2477 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2478 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2479 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2480 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2482 /* Create a new mapping symbol for the transition to STATE. */
2485 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2488 const char * symname;
2495 type = BSF_NO_FLAGS;
2499 type = BSF_NO_FLAGS;
2503 type = BSF_NO_FLAGS;
2509 symbolP = symbol_new (symname, now_seg, value, frag);
2510 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2515 THUMB_SET_FUNC (symbolP, 0);
2516 ARM_SET_THUMB (symbolP, 0);
2517 ARM_SET_INTERWORK (symbolP, support_interwork);
2521 THUMB_SET_FUNC (symbolP, 1);
2522 ARM_SET_THUMB (symbolP, 1);
2523 ARM_SET_INTERWORK (symbolP, support_interwork);
2531 /* Save the mapping symbols for future reference. Also check that
2532 we do not place two mapping symbols at the same offset within a
2533 frag. We'll handle overlap between frags in
2534 check_mapping_symbols.
2536 If .fill or other data filling directive generates zero sized data,
2537 the mapping symbol for the following code will have the same value
2538 as the one generated for the data filling directive. In this case,
2539 we replace the old symbol with the new one at the same address. */
2542 if (frag->tc_frag_data.first_map != NULL)
2544 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2545 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2547 frag->tc_frag_data.first_map = symbolP;
2549 if (frag->tc_frag_data.last_map != NULL)
2551 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2552 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2553 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2555 frag->tc_frag_data.last_map = symbolP;
2558 /* We must sometimes convert a region marked as code to data during
2559 code alignment, if an odd number of bytes have to be padded. The
2560 code mapping symbol is pushed to an aligned address. */
2563 insert_data_mapping_symbol (enum mstate state,
2564 valueT value, fragS *frag, offsetT bytes)
2566 /* If there was already a mapping symbol, remove it. */
2567 if (frag->tc_frag_data.last_map != NULL
2568 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2570 symbolS *symp = frag->tc_frag_data.last_map;
2574 know (frag->tc_frag_data.first_map == symp);
2575 frag->tc_frag_data.first_map = NULL;
2577 frag->tc_frag_data.last_map = NULL;
2578 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2581 make_mapping_symbol (MAP_DATA, value, frag);
2582 make_mapping_symbol (state, value + bytes, frag);
2585 static void mapping_state_2 (enum mstate state, int max_chars);
2587 /* Set the mapping state to STATE. Only call this when about to
2588 emit some STATE bytes to the file. */
2591 mapping_state (enum mstate state)
2593 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2595 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2597 if (mapstate == state)
2598 /* The mapping symbol has already been emitted.
2599 There is nothing else to do. */
2602 if (state == MAP_ARM || state == MAP_THUMB)
2604 All ARM instructions require 4-byte alignment.
2605 (Almost) all Thumb instructions require 2-byte alignment.
2607 When emitting instructions into any section, mark the section
2610 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2611 but themselves require 2-byte alignment; this applies to some
2612 PC- relative forms. However, these cases will invovle implicit
2613 literal pool generation or an explicit .align >=2, both of
2614 which will cause the section to me marked with sufficient
2615 alignment. Thus, we don't handle those cases here. */
2616 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2618 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2619 /* This case will be evaluated later in the next else. */
2621 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2622 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2624 /* Only add the symbol if the offset is > 0:
2625 if we're at the first frag, check it's size > 0;
2626 if we're not at the first frag, then for sure
2627 the offset is > 0. */
2628 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2629 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2632 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2635 mapping_state_2 (state, 0);
2639 /* Same as mapping_state, but MAX_CHARS bytes have already been
2640 allocated. Put the mapping symbol that far back. */
2643 mapping_state_2 (enum mstate state, int max_chars)
2645 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2647 if (!SEG_NORMAL (now_seg))
2650 if (mapstate == state)
2651 /* The mapping symbol has already been emitted.
2652 There is nothing else to do. */
2655 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2656 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2659 #define mapping_state(x) ((void)0)
2660 #define mapping_state_2(x, y) ((void)0)
2663 /* Find the real, Thumb encoded start of a Thumb function. */
2667 find_real_start (symbolS * symbolP)
2670 const char * name = S_GET_NAME (symbolP);
2671 symbolS * new_target;
2673 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2674 #define STUB_NAME ".real_start_of"
2679 /* The compiler may generate BL instructions to local labels because
2680 it needs to perform a branch to a far away location. These labels
2681 do not have a corresponding ".real_start_of" label. We check
2682 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2683 the ".real_start_of" convention for nonlocal branches. */
2684 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2687 real_start = ACONCAT ((STUB_NAME, name, NULL));
2688 new_target = symbol_find (real_start);
2690 if (new_target == NULL)
2692 as_warn (_("Failed to find real start of function: %s\n"), name);
2693 new_target = symbolP;
2701 opcode_select (int width)
2708 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2709 as_bad (_("selected processor does not support THUMB opcodes"));
2712 /* No need to force the alignment, since we will have been
2713 coming from ARM mode, which is word-aligned. */
2714 record_alignment (now_seg, 1);
2721 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2722 as_bad (_("selected processor does not support ARM opcodes"));
2727 frag_align (2, 0, 0);
2729 record_alignment (now_seg, 1);
2734 as_bad (_("invalid instruction size selected (%d)"), width);
2739 s_arm (int ignore ATTRIBUTE_UNUSED)
2742 demand_empty_rest_of_line ();
2746 s_thumb (int ignore ATTRIBUTE_UNUSED)
2749 demand_empty_rest_of_line ();
2753 s_code (int unused ATTRIBUTE_UNUSED)
2757 temp = get_absolute_expression ();
2762 opcode_select (temp);
2766 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2771 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2773 /* If we are not already in thumb mode go into it, EVEN if
2774 the target processor does not support thumb instructions.
2775 This is used by gcc/config/arm/lib1funcs.asm for example
2776 to compile interworking support functions even if the
2777 target processor should not support interworking. */
2781 record_alignment (now_seg, 1);
2784 demand_empty_rest_of_line ();
2788 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2792 /* The following label is the name/address of the start of a Thumb function.
2793 We need to know this for the interworking support. */
2794 label_is_thumb_function_name = TRUE;
2797 /* Perform a .set directive, but also mark the alias as
2798 being a thumb function. */
2801 s_thumb_set (int equiv)
2803 /* XXX the following is a duplicate of the code for s_set() in read.c
2804 We cannot just call that code as we need to get at the symbol that
2811 /* Especial apologies for the random logic:
2812 This just grew, and could be parsed much more simply!
2814 name = input_line_pointer;
2815 delim = get_symbol_end ();
2816 end_name = input_line_pointer;
2819 if (*input_line_pointer != ',')
2822 as_bad (_("expected comma after name \"%s\""), name);
2824 ignore_rest_of_line ();
2828 input_line_pointer++;
2831 if (name[0] == '.' && name[1] == '\0')
2833 /* XXX - this should not happen to .thumb_set. */
2837 if ((symbolP = symbol_find (name)) == NULL
2838 && (symbolP = md_undefined_symbol (name)) == NULL)
2841 /* When doing symbol listings, play games with dummy fragments living
2842 outside the normal fragment chain to record the file and line info
2844 if (listing & LISTING_SYMBOLS)
2846 extern struct list_info_struct * listing_tail;
2847 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2849 memset (dummy_frag, 0, sizeof (fragS));
2850 dummy_frag->fr_type = rs_fill;
2851 dummy_frag->line = listing_tail;
2852 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2853 dummy_frag->fr_symbol = symbolP;
2857 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2860 /* "set" symbols are local unless otherwise specified. */
2861 SF_SET_LOCAL (symbolP);
2862 #endif /* OBJ_COFF */
2863 } /* Make a new symbol. */
2865 symbol_table_insert (symbolP);
2870 && S_IS_DEFINED (symbolP)
2871 && S_GET_SEGMENT (symbolP) != reg_section)
2872 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2874 pseudo_set (symbolP);
2876 demand_empty_rest_of_line ();
2878 /* XXX Now we come to the Thumb specific bit of code. */
2880 THUMB_SET_FUNC (symbolP, 1);
2881 ARM_SET_THUMB (symbolP, 1);
2882 #if defined OBJ_ELF || defined OBJ_COFF
2883 ARM_SET_INTERWORK (symbolP, support_interwork);
2887 /* Directives: Mode selection. */
2889 /* .syntax [unified|divided] - choose the new unified syntax
2890 (same for Arm and Thumb encoding, modulo slight differences in what
2891 can be represented) or the old divergent syntax for each mode. */
2893 s_syntax (int unused ATTRIBUTE_UNUSED)
2897 name = input_line_pointer;
2898 delim = get_symbol_end ();
2900 if (!strcasecmp (name, "unified"))
2901 unified_syntax = TRUE;
2902 else if (!strcasecmp (name, "divided"))
2903 unified_syntax = FALSE;
2906 as_bad (_("unrecognized syntax mode \"%s\""), name);
2909 *input_line_pointer = delim;
2910 demand_empty_rest_of_line ();
2913 /* Directives: sectioning and alignment. */
2915 /* Same as s_align_ptwo but align 0 => align 2. */
2918 s_align (int unused ATTRIBUTE_UNUSED)
2923 long max_alignment = 15;
2925 temp = get_absolute_expression ();
2926 if (temp > max_alignment)
2927 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2930 as_bad (_("alignment negative. 0 assumed."));
2934 if (*input_line_pointer == ',')
2936 input_line_pointer++;
2937 temp_fill = get_absolute_expression ();
2949 /* Only make a frag if we HAVE to. */
2950 if (temp && !need_pass_2)
2952 if (!fill_p && subseg_text_p (now_seg))
2953 frag_align_code (temp, 0);
2955 frag_align (temp, (int) temp_fill, 0);
2957 demand_empty_rest_of_line ();
2959 record_alignment (now_seg, temp);
2963 s_bss (int ignore ATTRIBUTE_UNUSED)
2965 /* We don't support putting frags in the BSS segment, we fake it by
2966 marking in_bss, then looking at s_skip for clues. */
2967 subseg_set (bss_section, 0);
2968 demand_empty_rest_of_line ();
2970 #ifdef md_elf_section_change_hook
2971 md_elf_section_change_hook ();
2976 s_even (int ignore ATTRIBUTE_UNUSED)
2978 /* Never make frag if expect extra pass. */
2980 frag_align (1, 0, 0);
2982 record_alignment (now_seg, 1);
2984 demand_empty_rest_of_line ();
2987 /* Directives: Literal pools. */
2989 static literal_pool *
2990 find_literal_pool (void)
2992 literal_pool * pool;
2994 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2996 if (pool->section == now_seg
2997 && pool->sub_section == now_subseg)
3004 static literal_pool *
3005 find_or_make_literal_pool (void)
3007 /* Next literal pool ID number. */
3008 static unsigned int latest_pool_num = 1;
3009 literal_pool * pool;
3011 pool = find_literal_pool ();
3015 /* Create a new pool. */
3016 pool = (literal_pool *) xmalloc (sizeof (* pool));
3020 pool->next_free_entry = 0;
3021 pool->section = now_seg;
3022 pool->sub_section = now_subseg;
3023 pool->next = list_of_pools;
3024 pool->symbol = NULL;
3026 /* Add it to the list. */
3027 list_of_pools = pool;
3030 /* New pools, and emptied pools, will have a NULL symbol. */
3031 if (pool->symbol == NULL)
3033 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3034 (valueT) 0, &zero_address_frag);
3035 pool->id = latest_pool_num ++;
3042 /* Add the literal in the global 'inst'
3043 structure to the relevant literal pool. */
3046 add_to_lit_pool (void)
3048 literal_pool * pool;
3051 pool = find_or_make_literal_pool ();
3053 /* Check if this literal value is already in the pool. */
3054 for (entry = 0; entry < pool->next_free_entry; entry ++)
3056 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3057 && (inst.reloc.exp.X_op == O_constant)
3058 && (pool->literals[entry].X_add_number
3059 == inst.reloc.exp.X_add_number)
3060 && (pool->literals[entry].X_unsigned
3061 == inst.reloc.exp.X_unsigned))
3064 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3065 && (inst.reloc.exp.X_op == O_symbol)
3066 && (pool->literals[entry].X_add_number
3067 == inst.reloc.exp.X_add_number)
3068 && (pool->literals[entry].X_add_symbol
3069 == inst.reloc.exp.X_add_symbol)
3070 && (pool->literals[entry].X_op_symbol
3071 == inst.reloc.exp.X_op_symbol))
3075 /* Do we need to create a new entry? */
3076 if (entry == pool->next_free_entry)
3078 if (entry >= MAX_LITERAL_POOL_SIZE)
3080 inst.error = _("literal pool overflow");
3084 pool->literals[entry] = inst.reloc.exp;
3086 /* PR ld/12974: Record the location of the first source line to reference
3087 this entry in the literal pool. If it turns out during linking that the
3088 symbol does not exist we will be able to give an accurate line number for
3089 the (first use of the) missing reference. */
3090 if (debug_type == DEBUG_DWARF2)
3091 dwarf2_where (pool->locs + entry);
3093 pool->next_free_entry += 1;
3096 inst.reloc.exp.X_op = O_symbol;
3097 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3098 inst.reloc.exp.X_add_symbol = pool->symbol;
3103 /* Can't use symbol_new here, so have to create a symbol and then at
3104 a later date assign it a value. Thats what these functions do. */
3107 symbol_locate (symbolS * symbolP,
3108 const char * name, /* It is copied, the caller can modify. */
3109 segT segment, /* Segment identifier (SEG_<something>). */
3110 valueT valu, /* Symbol value. */
3111 fragS * frag) /* Associated fragment. */
3113 unsigned int name_length;
3114 char * preserved_copy_of_name;
3116 name_length = strlen (name) + 1; /* +1 for \0. */
3117 obstack_grow (¬es, name, name_length);
3118 preserved_copy_of_name = (char *) obstack_finish (¬es);
3120 #ifdef tc_canonicalize_symbol_name
3121 preserved_copy_of_name =
3122 tc_canonicalize_symbol_name (preserved_copy_of_name);
3125 S_SET_NAME (symbolP, preserved_copy_of_name);
3127 S_SET_SEGMENT (symbolP, segment);
3128 S_SET_VALUE (symbolP, valu);
3129 symbol_clear_list_pointers (symbolP);
3131 symbol_set_frag (symbolP, frag);
3133 /* Link to end of symbol chain. */
3135 extern int symbol_table_frozen;
3137 if (symbol_table_frozen)
3141 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3143 obj_symbol_new_hook (symbolP);
3145 #ifdef tc_symbol_new_hook
3146 tc_symbol_new_hook (symbolP);
3150 verify_symbol_chain (symbol_rootP, symbol_lastP);
3151 #endif /* DEBUG_SYMS */
3156 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3159 literal_pool * pool;
3162 pool = find_literal_pool ();
3164 || pool->symbol == NULL
3165 || pool->next_free_entry == 0)
3168 mapping_state (MAP_DATA);
3170 /* Align pool as you have word accesses.
3171 Only make a frag if we have to. */
3173 frag_align (2, 0, 0);
3175 record_alignment (now_seg, 2);
3177 sprintf (sym_name, "$$lit_\002%x", pool->id);
3179 symbol_locate (pool->symbol, sym_name, now_seg,
3180 (valueT) frag_now_fix (), frag_now);
3181 symbol_table_insert (pool->symbol);
3183 ARM_SET_THUMB (pool->symbol, thumb_mode);
3185 #if defined OBJ_COFF || defined OBJ_ELF
3186 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3189 for (entry = 0; entry < pool->next_free_entry; entry ++)
3192 if (debug_type == DEBUG_DWARF2)
3193 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3195 /* First output the expression in the instruction to the pool. */
3196 emit_expr (&(pool->literals[entry]), 4); /* .word */
3199 /* Mark the pool as empty. */
3200 pool->next_free_entry = 0;
3201 pool->symbol = NULL;
3205 /* Forward declarations for functions below, in the MD interface
3207 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3208 static valueT create_unwind_entry (int);
3209 static void start_unwind_section (const segT, int);
3210 static void add_unwind_opcode (valueT, int);
3211 static void flush_pending_unwind (void);
3213 /* Directives: Data. */
3216 s_arm_elf_cons (int nbytes)
3220 #ifdef md_flush_pending_output
3221 md_flush_pending_output ();
3224 if (is_it_end_of_statement ())
3226 demand_empty_rest_of_line ();
3230 #ifdef md_cons_align
3231 md_cons_align (nbytes);
3234 mapping_state (MAP_DATA);
3238 char *base = input_line_pointer;
3242 if (exp.X_op != O_symbol)
3243 emit_expr (&exp, (unsigned int) nbytes);
3246 char *before_reloc = input_line_pointer;
3247 reloc = parse_reloc (&input_line_pointer);
3250 as_bad (_("unrecognized relocation suffix"));
3251 ignore_rest_of_line ();
3254 else if (reloc == BFD_RELOC_UNUSED)
3255 emit_expr (&exp, (unsigned int) nbytes);
3258 reloc_howto_type *howto = (reloc_howto_type *)
3259 bfd_reloc_type_lookup (stdoutput,
3260 (bfd_reloc_code_real_type) reloc);
3261 int size = bfd_get_reloc_size (howto);
3263 if (reloc == BFD_RELOC_ARM_PLT32)
3265 as_bad (_("(plt) is only valid on branch targets"));
3266 reloc = BFD_RELOC_UNUSED;
3271 as_bad (_("%s relocations do not fit in %d bytes"),
3272 howto->name, nbytes);
3275 /* We've parsed an expression stopping at O_symbol.
3276 But there may be more expression left now that we
3277 have parsed the relocation marker. Parse it again.
3278 XXX Surely there is a cleaner way to do this. */
3279 char *p = input_line_pointer;
3281 char *save_buf = (char *) alloca (input_line_pointer - base);
3282 memcpy (save_buf, base, input_line_pointer - base);
3283 memmove (base + (input_line_pointer - before_reloc),
3284 base, before_reloc - base);
3286 input_line_pointer = base + (input_line_pointer-before_reloc);
3288 memcpy (base, save_buf, p - base);
3290 offset = nbytes - size;
3291 p = frag_more ((int) nbytes);
3292 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3293 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3298 while (*input_line_pointer++ == ',');
3300 /* Put terminator back into stream. */
3301 input_line_pointer --;
3302 demand_empty_rest_of_line ();
3305 /* Emit an expression containing a 32-bit thumb instruction.
3306 Implementation based on put_thumb32_insn. */
3309 emit_thumb32_expr (expressionS * exp)
3311 expressionS exp_high = *exp;
3313 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3314 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3315 exp->X_add_number &= 0xffff;
3316 emit_expr (exp, (unsigned int) THUMB_SIZE);
3319 /* Guess the instruction size based on the opcode. */
3322 thumb_insn_size (int opcode)
3324 if ((unsigned int) opcode < 0xe800u)
3326 else if ((unsigned int) opcode >= 0xe8000000u)
3333 emit_insn (expressionS *exp, int nbytes)
3337 if (exp->X_op == O_constant)
3342 size = thumb_insn_size (exp->X_add_number);
3346 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3348 as_bad (_(".inst.n operand too big. "\
3349 "Use .inst.w instead"));
3354 if (now_it.state == AUTOMATIC_IT_BLOCK)
3355 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3357 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3359 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3360 emit_thumb32_expr (exp);
3362 emit_expr (exp, (unsigned int) size);
3364 it_fsm_post_encode ();
3368 as_bad (_("cannot determine Thumb instruction size. " \
3369 "Use .inst.n/.inst.w instead"));
3372 as_bad (_("constant expression required"));
3377 /* Like s_arm_elf_cons but do not use md_cons_align and
3378 set the mapping state to MAP_ARM/MAP_THUMB. */
3381 s_arm_elf_inst (int nbytes)
3383 if (is_it_end_of_statement ())
3385 demand_empty_rest_of_line ();
3389 /* Calling mapping_state () here will not change ARM/THUMB,
3390 but will ensure not to be in DATA state. */
3393 mapping_state (MAP_THUMB);
3398 as_bad (_("width suffixes are invalid in ARM mode"));
3399 ignore_rest_of_line ();
3405 mapping_state (MAP_ARM);
3414 if (! emit_insn (& exp, nbytes))
3416 ignore_rest_of_line ();
3420 while (*input_line_pointer++ == ',');
3422 /* Put terminator back into stream. */
3423 input_line_pointer --;
3424 demand_empty_rest_of_line ();
3427 /* Parse a .rel31 directive. */
3430 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3437 if (*input_line_pointer == '1')
3438 highbit = 0x80000000;
3439 else if (*input_line_pointer != '0')
3440 as_bad (_("expected 0 or 1"));
3442 input_line_pointer++;
3443 if (*input_line_pointer != ',')
3444 as_bad (_("missing comma"));
3445 input_line_pointer++;
3447 #ifdef md_flush_pending_output
3448 md_flush_pending_output ();
3451 #ifdef md_cons_align
3455 mapping_state (MAP_DATA);
3460 md_number_to_chars (p, highbit, 4);
3461 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3462 BFD_RELOC_ARM_PREL31);
3464 demand_empty_rest_of_line ();
3467 /* Directives: AEABI stack-unwind tables. */
3469 /* Parse an unwind_fnstart directive. Simply records the current location. */
3472 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3474 demand_empty_rest_of_line ();
3475 if (unwind.proc_start)
3477 as_bad (_("duplicate .fnstart directive"));
3481 /* Mark the start of the function. */
3482 unwind.proc_start = expr_build_dot ();
3484 /* Reset the rest of the unwind info. */
3485 unwind.opcode_count = 0;
3486 unwind.table_entry = NULL;
3487 unwind.personality_routine = NULL;
3488 unwind.personality_index = -1;
3489 unwind.frame_size = 0;
3490 unwind.fp_offset = 0;
3491 unwind.fp_reg = REG_SP;
3493 unwind.sp_restored = 0;
3497 /* Parse a handlerdata directive. Creates the exception handling table entry
3498 for the function. */
3501 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3503 demand_empty_rest_of_line ();
3504 if (!unwind.proc_start)
3505 as_bad (MISSING_FNSTART);
3507 if (unwind.table_entry)
3508 as_bad (_("duplicate .handlerdata directive"));
3510 create_unwind_entry (1);
3513 /* Parse an unwind_fnend directive. Generates the index table entry. */
3516 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3521 unsigned int marked_pr_dependency;
3523 demand_empty_rest_of_line ();
3525 if (!unwind.proc_start)
3527 as_bad (_(".fnend directive without .fnstart"));
3531 /* Add eh table entry. */
3532 if (unwind.table_entry == NULL)
3533 val = create_unwind_entry (0);
3537 /* Add index table entry. This is two words. */
3538 start_unwind_section (unwind.saved_seg, 1);
3539 frag_align (2, 0, 0);
3540 record_alignment (now_seg, 2);
3542 ptr = frag_more (8);
3544 where = frag_now_fix () - 8;
3546 /* Self relative offset of the function start. */
3547 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3548 BFD_RELOC_ARM_PREL31);
3550 /* Indicate dependency on EHABI-defined personality routines to the
3551 linker, if it hasn't been done already. */
3552 marked_pr_dependency
3553 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3554 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3555 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3557 static const char *const name[] =
3559 "__aeabi_unwind_cpp_pr0",
3560 "__aeabi_unwind_cpp_pr1",
3561 "__aeabi_unwind_cpp_pr2"
3563 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3564 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3565 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3566 |= 1 << unwind.personality_index;
3570 /* Inline exception table entry. */
3571 md_number_to_chars (ptr + 4, val, 4);
3573 /* Self relative offset of the table entry. */
3574 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3575 BFD_RELOC_ARM_PREL31);
3577 /* Restore the original section. */
3578 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3580 unwind.proc_start = NULL;
3584 /* Parse an unwind_cantunwind directive. */
3587 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3589 demand_empty_rest_of_line ();
3590 if (!unwind.proc_start)
3591 as_bad (MISSING_FNSTART);
3593 if (unwind.personality_routine || unwind.personality_index != -1)
3594 as_bad (_("personality routine specified for cantunwind frame"));
3596 unwind.personality_index = -2;
3600 /* Parse a personalityindex directive. */
3603 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3607 if (!unwind.proc_start)
3608 as_bad (MISSING_FNSTART);
3610 if (unwind.personality_routine || unwind.personality_index != -1)
3611 as_bad (_("duplicate .personalityindex directive"));
3615 if (exp.X_op != O_constant
3616 || exp.X_add_number < 0 || exp.X_add_number > 15)
3618 as_bad (_("bad personality routine number"));
3619 ignore_rest_of_line ();
3623 unwind.personality_index = exp.X_add_number;
3625 demand_empty_rest_of_line ();
3629 /* Parse a personality directive. */
3632 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3636 if (!unwind.proc_start)
3637 as_bad (MISSING_FNSTART);
3639 if (unwind.personality_routine || unwind.personality_index != -1)
3640 as_bad (_("duplicate .personality directive"));
3642 name = input_line_pointer;
3643 c = get_symbol_end ();
3644 p = input_line_pointer;
3645 unwind.personality_routine = symbol_find_or_make (name);
3647 demand_empty_rest_of_line ();
3651 /* Parse a directive saving core registers. */
3654 s_arm_unwind_save_core (void)
3660 range = parse_reg_list (&input_line_pointer);
3663 as_bad (_("expected register list"));
3664 ignore_rest_of_line ();
3668 demand_empty_rest_of_line ();
3670 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3671 into .unwind_save {..., sp...}. We aren't bothered about the value of
3672 ip because it is clobbered by calls. */
3673 if (unwind.sp_restored && unwind.fp_reg == 12
3674 && (range & 0x3000) == 0x1000)
3676 unwind.opcode_count--;
3677 unwind.sp_restored = 0;
3678 range = (range | 0x2000) & ~0x1000;
3679 unwind.pending_offset = 0;
3685 /* See if we can use the short opcodes. These pop a block of up to 8
3686 registers starting with r4, plus maybe r14. */
3687 for (n = 0; n < 8; n++)
3689 /* Break at the first non-saved register. */
3690 if ((range & (1 << (n + 4))) == 0)
3693 /* See if there are any other bits set. */
3694 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3696 /* Use the long form. */
3697 op = 0x8000 | ((range >> 4) & 0xfff);
3698 add_unwind_opcode (op, 2);
3702 /* Use the short form. */
3704 op = 0xa8; /* Pop r14. */
3706 op = 0xa0; /* Do not pop r14. */
3708 add_unwind_opcode (op, 1);
3715 op = 0xb100 | (range & 0xf);
3716 add_unwind_opcode (op, 2);
3719 /* Record the number of bytes pushed. */
3720 for (n = 0; n < 16; n++)
3722 if (range & (1 << n))
3723 unwind.frame_size += 4;
3728 /* Parse a directive saving FPA registers. */
3731 s_arm_unwind_save_fpa (int reg)
3737 /* Get Number of registers to transfer. */
3738 if (skip_past_comma (&input_line_pointer) != FAIL)
3741 exp.X_op = O_illegal;
3743 if (exp.X_op != O_constant)
3745 as_bad (_("expected , <constant>"));
3746 ignore_rest_of_line ();
3750 num_regs = exp.X_add_number;
3752 if (num_regs < 1 || num_regs > 4)
3754 as_bad (_("number of registers must be in the range [1:4]"));
3755 ignore_rest_of_line ();
3759 demand_empty_rest_of_line ();
3764 op = 0xb4 | (num_regs - 1);
3765 add_unwind_opcode (op, 1);
3770 op = 0xc800 | (reg << 4) | (num_regs - 1);
3771 add_unwind_opcode (op, 2);
3773 unwind.frame_size += num_regs * 12;
3777 /* Parse a directive saving VFP registers for ARMv6 and above. */
3780 s_arm_unwind_save_vfp_armv6 (void)
3785 int num_vfpv3_regs = 0;
3786 int num_regs_below_16;
3788 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3791 as_bad (_("expected register list"));
3792 ignore_rest_of_line ();
3796 demand_empty_rest_of_line ();
3798 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3799 than FSTMX/FLDMX-style ones). */
3801 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3803 num_vfpv3_regs = count;
3804 else if (start + count > 16)
3805 num_vfpv3_regs = start + count - 16;
3807 if (num_vfpv3_regs > 0)
3809 int start_offset = start > 16 ? start - 16 : 0;
3810 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3811 add_unwind_opcode (op, 2);
3814 /* Generate opcode for registers numbered in the range 0 .. 15. */
3815 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3816 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3817 if (num_regs_below_16 > 0)
3819 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3820 add_unwind_opcode (op, 2);
3823 unwind.frame_size += count * 8;
3827 /* Parse a directive saving VFP registers for pre-ARMv6. */
3830 s_arm_unwind_save_vfp (void)
3836 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3839 as_bad (_("expected register list"));
3840 ignore_rest_of_line ();
3844 demand_empty_rest_of_line ();
3849 op = 0xb8 | (count - 1);
3850 add_unwind_opcode (op, 1);
3855 op = 0xb300 | (reg << 4) | (count - 1);
3856 add_unwind_opcode (op, 2);
3858 unwind.frame_size += count * 8 + 4;
3862 /* Parse a directive saving iWMMXt data registers. */
3865 s_arm_unwind_save_mmxwr (void)
3873 if (*input_line_pointer == '{')
3874 input_line_pointer++;
3878 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3882 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3887 as_tsktsk (_("register list not in ascending order"));
3890 if (*input_line_pointer == '-')
3892 input_line_pointer++;
3893 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3896 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3899 else if (reg >= hi_reg)
3901 as_bad (_("bad register range"));
3904 for (; reg < hi_reg; reg++)
3908 while (skip_past_comma (&input_line_pointer) != FAIL);
3910 if (*input_line_pointer == '}')
3911 input_line_pointer++;
3913 demand_empty_rest_of_line ();
3915 /* Generate any deferred opcodes because we're going to be looking at
3917 flush_pending_unwind ();
3919 for (i = 0; i < 16; i++)
3921 if (mask & (1 << i))
3922 unwind.frame_size += 8;
3925 /* Attempt to combine with a previous opcode. We do this because gcc
3926 likes to output separate unwind directives for a single block of
3928 if (unwind.opcode_count > 0)
3930 i = unwind.opcodes[unwind.opcode_count - 1];
3931 if ((i & 0xf8) == 0xc0)
3934 /* Only merge if the blocks are contiguous. */
3937 if ((mask & 0xfe00) == (1 << 9))
3939 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3940 unwind.opcode_count--;
3943 else if (i == 6 && unwind.opcode_count >= 2)
3945 i = unwind.opcodes[unwind.opcode_count - 2];
3949 op = 0xffff << (reg - 1);
3951 && ((mask & op) == (1u << (reg - 1))))
3953 op = (1 << (reg + i + 1)) - 1;
3954 op &= ~((1 << reg) - 1);
3956 unwind.opcode_count -= 2;
3963 /* We want to generate opcodes in the order the registers have been
3964 saved, ie. descending order. */
3965 for (reg = 15; reg >= -1; reg--)
3967 /* Save registers in blocks. */
3969 || !(mask & (1 << reg)))
3971 /* We found an unsaved reg. Generate opcodes to save the
3978 op = 0xc0 | (hi_reg - 10);
3979 add_unwind_opcode (op, 1);
3984 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3985 add_unwind_opcode (op, 2);
3994 ignore_rest_of_line ();
3998 s_arm_unwind_save_mmxwcg (void)
4005 if (*input_line_pointer == '{')
4006 input_line_pointer++;
4010 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4014 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4020 as_tsktsk (_("register list not in ascending order"));
4023 if (*input_line_pointer == '-')
4025 input_line_pointer++;
4026 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4029 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4032 else if (reg >= hi_reg)
4034 as_bad (_("bad register range"));
4037 for (; reg < hi_reg; reg++)
4041 while (skip_past_comma (&input_line_pointer) != FAIL);
4043 if (*input_line_pointer == '}')
4044 input_line_pointer++;
4046 demand_empty_rest_of_line ();
4048 /* Generate any deferred opcodes because we're going to be looking at
4050 flush_pending_unwind ();
4052 for (reg = 0; reg < 16; reg++)
4054 if (mask & (1 << reg))
4055 unwind.frame_size += 4;
4058 add_unwind_opcode (op, 2);
4061 ignore_rest_of_line ();
4065 /* Parse an unwind_save directive.
4066 If the argument is non-zero, this is a .vsave directive. */
4069 s_arm_unwind_save (int arch_v6)
4072 struct reg_entry *reg;
4073 bfd_boolean had_brace = FALSE;
4075 if (!unwind.proc_start)
4076 as_bad (MISSING_FNSTART);
4078 /* Figure out what sort of save we have. */
4079 peek = input_line_pointer;
4087 reg = arm_reg_parse_multi (&peek);
4091 as_bad (_("register expected"));
4092 ignore_rest_of_line ();
4101 as_bad (_("FPA .unwind_save does not take a register list"));
4102 ignore_rest_of_line ();
4105 input_line_pointer = peek;
4106 s_arm_unwind_save_fpa (reg->number);
4109 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4112 s_arm_unwind_save_vfp_armv6 ();
4114 s_arm_unwind_save_vfp ();
4116 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4117 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4120 as_bad (_(".unwind_save does not support this kind of register"));
4121 ignore_rest_of_line ();
4126 /* Parse an unwind_movsp directive. */
4129 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4135 if (!unwind.proc_start)
4136 as_bad (MISSING_FNSTART);
4138 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4141 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4142 ignore_rest_of_line ();
4146 /* Optional constant. */
4147 if (skip_past_comma (&input_line_pointer) != FAIL)
4149 if (immediate_for_directive (&offset) == FAIL)
4155 demand_empty_rest_of_line ();
4157 if (reg == REG_SP || reg == REG_PC)
4159 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4163 if (unwind.fp_reg != REG_SP)
4164 as_bad (_("unexpected .unwind_movsp directive"));
4166 /* Generate opcode to restore the value. */
4168 add_unwind_opcode (op, 1);
4170 /* Record the information for later. */
4171 unwind.fp_reg = reg;
4172 unwind.fp_offset = unwind.frame_size - offset;
4173 unwind.sp_restored = 1;
4176 /* Parse an unwind_pad directive. */
4179 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4183 if (!unwind.proc_start)
4184 as_bad (MISSING_FNSTART);
4186 if (immediate_for_directive (&offset) == FAIL)
4191 as_bad (_("stack increment must be multiple of 4"));
4192 ignore_rest_of_line ();
4196 /* Don't generate any opcodes, just record the details for later. */
4197 unwind.frame_size += offset;
4198 unwind.pending_offset += offset;
4200 demand_empty_rest_of_line ();
4203 /* Parse an unwind_setfp directive. */
4206 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4212 if (!unwind.proc_start)
4213 as_bad (MISSING_FNSTART);
4215 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4216 if (skip_past_comma (&input_line_pointer) == FAIL)
4219 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4221 if (fp_reg == FAIL || sp_reg == FAIL)
4223 as_bad (_("expected <reg>, <reg>"));
4224 ignore_rest_of_line ();
4228 /* Optional constant. */
4229 if (skip_past_comma (&input_line_pointer) != FAIL)
4231 if (immediate_for_directive (&offset) == FAIL)
4237 demand_empty_rest_of_line ();
4239 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4241 as_bad (_("register must be either sp or set by a previous"
4242 "unwind_movsp directive"));
4246 /* Don't generate any opcodes, just record the information for later. */
4247 unwind.fp_reg = fp_reg;
4249 if (sp_reg == REG_SP)
4250 unwind.fp_offset = unwind.frame_size - offset;
4252 unwind.fp_offset -= offset;
4255 /* Parse an unwind_raw directive. */
4258 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4261 /* This is an arbitrary limit. */
4262 unsigned char op[16];
4265 if (!unwind.proc_start)
4266 as_bad (MISSING_FNSTART);
4269 if (exp.X_op == O_constant
4270 && skip_past_comma (&input_line_pointer) != FAIL)
4272 unwind.frame_size += exp.X_add_number;
4276 exp.X_op = O_illegal;
4278 if (exp.X_op != O_constant)
4280 as_bad (_("expected <offset>, <opcode>"));
4281 ignore_rest_of_line ();
4287 /* Parse the opcode. */
4292 as_bad (_("unwind opcode too long"));
4293 ignore_rest_of_line ();
4295 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4297 as_bad (_("invalid unwind opcode"));
4298 ignore_rest_of_line ();
4301 op[count++] = exp.X_add_number;
4303 /* Parse the next byte. */
4304 if (skip_past_comma (&input_line_pointer) == FAIL)
4310 /* Add the opcode bytes in reverse order. */
4312 add_unwind_opcode (op[count], 1);
4314 demand_empty_rest_of_line ();
4318 /* Parse a .eabi_attribute directive. */
4321 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4323 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4325 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4326 attributes_set_explicitly[tag] = 1;
4329 /* Emit a tls fix for the symbol. */
4332 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4336 #ifdef md_flush_pending_output
4337 md_flush_pending_output ();
4340 #ifdef md_cons_align
4344 /* Since we're just labelling the code, there's no need to define a
4347 p = obstack_next_free (&frchain_now->frch_obstack);
4348 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4349 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4350 : BFD_RELOC_ARM_TLS_DESCSEQ);
4352 #endif /* OBJ_ELF */
4354 static void s_arm_arch (int);
4355 static void s_arm_object_arch (int);
4356 static void s_arm_cpu (int);
4357 static void s_arm_fpu (int);
4358 static void s_arm_arch_extension (int);
4363 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4370 if (exp.X_op == O_symbol)
4371 exp.X_op = O_secrel;
4373 emit_expr (&exp, 4);
4375 while (*input_line_pointer++ == ',');
4377 input_line_pointer--;
4378 demand_empty_rest_of_line ();
4382 /* This table describes all the machine specific pseudo-ops the assembler
4383 has to support. The fields are:
4384 pseudo-op name without dot
4385 function to call to execute this pseudo-op
4386 Integer arg to pass to the function. */
4388 const pseudo_typeS md_pseudo_table[] =
4390 /* Never called because '.req' does not start a line. */
4391 { "req", s_req, 0 },
4392 /* Following two are likewise never called. */
4395 { "unreq", s_unreq, 0 },
4396 { "bss", s_bss, 0 },
4397 { "align", s_align, 0 },
4398 { "arm", s_arm, 0 },
4399 { "thumb", s_thumb, 0 },
4400 { "code", s_code, 0 },
4401 { "force_thumb", s_force_thumb, 0 },
4402 { "thumb_func", s_thumb_func, 0 },
4403 { "thumb_set", s_thumb_set, 0 },
4404 { "even", s_even, 0 },
4405 { "ltorg", s_ltorg, 0 },
4406 { "pool", s_ltorg, 0 },
4407 { "syntax", s_syntax, 0 },
4408 { "cpu", s_arm_cpu, 0 },
4409 { "arch", s_arm_arch, 0 },
4410 { "object_arch", s_arm_object_arch, 0 },
4411 { "fpu", s_arm_fpu, 0 },
4412 { "arch_extension", s_arm_arch_extension, 0 },
4414 { "word", s_arm_elf_cons, 4 },
4415 { "long", s_arm_elf_cons, 4 },
4416 { "inst.n", s_arm_elf_inst, 2 },
4417 { "inst.w", s_arm_elf_inst, 4 },
4418 { "inst", s_arm_elf_inst, 0 },
4419 { "rel31", s_arm_rel31, 0 },
4420 { "fnstart", s_arm_unwind_fnstart, 0 },
4421 { "fnend", s_arm_unwind_fnend, 0 },
4422 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4423 { "personality", s_arm_unwind_personality, 0 },
4424 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4425 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4426 { "save", s_arm_unwind_save, 0 },
4427 { "vsave", s_arm_unwind_save, 1 },
4428 { "movsp", s_arm_unwind_movsp, 0 },
4429 { "pad", s_arm_unwind_pad, 0 },
4430 { "setfp", s_arm_unwind_setfp, 0 },
4431 { "unwind_raw", s_arm_unwind_raw, 0 },
4432 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4433 { "tlsdescseq", s_arm_tls_descseq, 0 },
4437 /* These are used for dwarf. */
4441 /* These are used for dwarf2. */
4442 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4443 { "loc", dwarf2_directive_loc, 0 },
4444 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4446 { "extend", float_cons, 'x' },
4447 { "ldouble", float_cons, 'x' },
4448 { "packed", float_cons, 'p' },
4450 {"secrel32", pe_directive_secrel, 0},
4455 /* Parser functions used exclusively in instruction operands. */
4457 /* Generic immediate-value read function for use in insn parsing.
4458 STR points to the beginning of the immediate (the leading #);
4459 VAL receives the value; if the value is outside [MIN, MAX]
4460 issue an error. PREFIX_OPT is true if the immediate prefix is
4464 parse_immediate (char **str, int *val, int min, int max,
4465 bfd_boolean prefix_opt)
4468 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4469 if (exp.X_op != O_constant)
4471 inst.error = _("constant expression required");
4475 if (exp.X_add_number < min || exp.X_add_number > max)
4477 inst.error = _("immediate value out of range");
4481 *val = exp.X_add_number;
4485 /* Less-generic immediate-value read function with the possibility of loading a
4486 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4487 instructions. Puts the result directly in inst.operands[i]. */
4490 parse_big_immediate (char **str, int i)
4495 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4497 if (exp.X_op == O_constant)
4499 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4500 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4501 O_constant. We have to be careful not to break compilation for
4502 32-bit X_add_number, though. */
4503 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4505 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4506 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4507 inst.operands[i].regisimm = 1;
4510 else if (exp.X_op == O_big
4511 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4513 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4515 /* Bignums have their least significant bits in
4516 generic_bignum[0]. Make sure we put 32 bits in imm and
4517 32 bits in reg, in a (hopefully) portable way. */
4518 gas_assert (parts != 0);
4520 /* Make sure that the number is not too big.
4521 PR 11972: Bignums can now be sign-extended to the
4522 size of a .octa so check that the out of range bits
4523 are all zero or all one. */
4524 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4526 LITTLENUM_TYPE m = -1;
4528 if (generic_bignum[parts * 2] != 0
4529 && generic_bignum[parts * 2] != m)
4532 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4533 if (generic_bignum[j] != generic_bignum[j-1])
4537 inst.operands[i].imm = 0;
4538 for (j = 0; j < parts; j++, idx++)
4539 inst.operands[i].imm |= generic_bignum[idx]
4540 << (LITTLENUM_NUMBER_OF_BITS * j);
4541 inst.operands[i].reg = 0;
4542 for (j = 0; j < parts; j++, idx++)
4543 inst.operands[i].reg |= generic_bignum[idx]
4544 << (LITTLENUM_NUMBER_OF_BITS * j);
4545 inst.operands[i].regisimm = 1;
4555 /* Returns the pseudo-register number of an FPA immediate constant,
4556 or FAIL if there isn't a valid constant here. */
4559 parse_fpa_immediate (char ** str)
4561 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4567 /* First try and match exact strings, this is to guarantee
4568 that some formats will work even for cross assembly. */
4570 for (i = 0; fp_const[i]; i++)
4572 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4576 *str += strlen (fp_const[i]);
4577 if (is_end_of_line[(unsigned char) **str])
4583 /* Just because we didn't get a match doesn't mean that the constant
4584 isn't valid, just that it is in a format that we don't
4585 automatically recognize. Try parsing it with the standard
4586 expression routines. */
4588 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4590 /* Look for a raw floating point number. */
4591 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4592 && is_end_of_line[(unsigned char) *save_in])
4594 for (i = 0; i < NUM_FLOAT_VALS; i++)
4596 for (j = 0; j < MAX_LITTLENUMS; j++)
4598 if (words[j] != fp_values[i][j])
4602 if (j == MAX_LITTLENUMS)
4610 /* Try and parse a more complex expression, this will probably fail
4611 unless the code uses a floating point prefix (eg "0f"). */
4612 save_in = input_line_pointer;
4613 input_line_pointer = *str;
4614 if (expression (&exp) == absolute_section
4615 && exp.X_op == O_big
4616 && exp.X_add_number < 0)
4618 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4620 if (gen_to_words (words, 5, (long) 15) == 0)
4622 for (i = 0; i < NUM_FLOAT_VALS; i++)
4624 for (j = 0; j < MAX_LITTLENUMS; j++)
4626 if (words[j] != fp_values[i][j])
4630 if (j == MAX_LITTLENUMS)
4632 *str = input_line_pointer;
4633 input_line_pointer = save_in;
4640 *str = input_line_pointer;
4641 input_line_pointer = save_in;
4642 inst.error = _("invalid FPA immediate expression");
4646 /* Returns 1 if a number has "quarter-precision" float format
4647 0baBbbbbbc defgh000 00000000 00000000. */
4650 is_quarter_float (unsigned imm)
4652 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4653 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4656 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4657 0baBbbbbbc defgh000 00000000 00000000.
4658 The zero and minus-zero cases need special handling, since they can't be
4659 encoded in the "quarter-precision" float format, but can nonetheless be
4660 loaded as integer constants. */
4663 parse_qfloat_immediate (char **ccp, int *immed)
4667 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4668 int found_fpchar = 0;
4670 skip_past_char (&str, '#');
4672 /* We must not accidentally parse an integer as a floating-point number. Make
4673 sure that the value we parse is not an integer by checking for special
4674 characters '.' or 'e'.
4675 FIXME: This is a horrible hack, but doing better is tricky because type
4676 information isn't in a very usable state at parse time. */
4678 skip_whitespace (fpnum);
4680 if (strncmp (fpnum, "0x", 2) == 0)
4684 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4685 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4695 if ((str = atof_ieee (str, 's', words)) != NULL)
4697 unsigned fpword = 0;
4700 /* Our FP word must be 32 bits (single-precision FP). */
4701 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4703 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4707 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4720 /* Shift operands. */
4723 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4726 struct asm_shift_name
4729 enum shift_kind kind;
4732 /* Third argument to parse_shift. */
4733 enum parse_shift_mode
4735 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4736 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4737 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4738 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4739 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4742 /* Parse a <shift> specifier on an ARM data processing instruction.
4743 This has three forms:
4745 (LSL|LSR|ASL|ASR|ROR) Rs
4746 (LSL|LSR|ASL|ASR|ROR) #imm
4749 Note that ASL is assimilated to LSL in the instruction encoding, and
4750 RRX to ROR #0 (which cannot be written as such). */
4753 parse_shift (char **str, int i, enum parse_shift_mode mode)
4755 const struct asm_shift_name *shift_name;
4756 enum shift_kind shift;
4761 for (p = *str; ISALPHA (*p); p++)
4766 inst.error = _("shift expression expected");
4770 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4773 if (shift_name == NULL)
4775 inst.error = _("shift expression expected");
4779 shift = shift_name->kind;
4783 case NO_SHIFT_RESTRICT:
4784 case SHIFT_IMMEDIATE: break;
4786 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4787 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4789 inst.error = _("'LSL' or 'ASR' required");
4794 case SHIFT_LSL_IMMEDIATE:
4795 if (shift != SHIFT_LSL)
4797 inst.error = _("'LSL' required");
4802 case SHIFT_ASR_IMMEDIATE:
4803 if (shift != SHIFT_ASR)
4805 inst.error = _("'ASR' required");
4813 if (shift != SHIFT_RRX)
4815 /* Whitespace can appear here if the next thing is a bare digit. */
4816 skip_whitespace (p);
4818 if (mode == NO_SHIFT_RESTRICT
4819 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4821 inst.operands[i].imm = reg;
4822 inst.operands[i].immisreg = 1;
4824 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4827 inst.operands[i].shift_kind = shift;
4828 inst.operands[i].shifted = 1;
4833 /* Parse a <shifter_operand> for an ARM data processing instruction:
4836 #<immediate>, <rotate>
4840 where <shift> is defined by parse_shift above, and <rotate> is a
4841 multiple of 2 between 0 and 30. Validation of immediate operands
4842 is deferred to md_apply_fix. */
4845 parse_shifter_operand (char **str, int i)
4850 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4852 inst.operands[i].reg = value;
4853 inst.operands[i].isreg = 1;
4855 /* parse_shift will override this if appropriate */
4856 inst.reloc.exp.X_op = O_constant;
4857 inst.reloc.exp.X_add_number = 0;
4859 if (skip_past_comma (str) == FAIL)
4862 /* Shift operation on register. */
4863 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4866 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4869 if (skip_past_comma (str) == SUCCESS)
4871 /* #x, y -- ie explicit rotation by Y. */
4872 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4875 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4877 inst.error = _("constant expression expected");
4881 value = exp.X_add_number;
4882 if (value < 0 || value > 30 || value % 2 != 0)
4884 inst.error = _("invalid rotation");
4887 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4889 inst.error = _("invalid constant");
4893 /* Encode as specified. */
4894 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4898 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4899 inst.reloc.pc_rel = 0;
4903 /* Group relocation information. Each entry in the table contains the
4904 textual name of the relocation as may appear in assembler source
4905 and must end with a colon.
4906 Along with this textual name are the relocation codes to be used if
4907 the corresponding instruction is an ALU instruction (ADD or SUB only),
4908 an LDR, an LDRS, or an LDC. */
4910 struct group_reloc_table_entry
4921 /* Varieties of non-ALU group relocation. */
4928 static struct group_reloc_table_entry group_reloc_table[] =
4929 { /* Program counter relative: */
4931 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4936 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4937 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4938 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4939 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4941 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4946 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4947 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4948 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4949 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4951 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4952 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4953 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4954 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4955 /* Section base relative */
4957 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4962 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4963 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4964 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4965 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4967 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4972 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4973 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4974 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4975 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4977 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4978 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4979 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4980 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4982 /* Given the address of a pointer pointing to the textual name of a group
4983 relocation as may appear in assembler source, attempt to find its details
4984 in group_reloc_table. The pointer will be updated to the character after
4985 the trailing colon. On failure, FAIL will be returned; SUCCESS
4986 otherwise. On success, *entry will be updated to point at the relevant
4987 group_reloc_table entry. */
4990 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4993 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4995 int length = strlen (group_reloc_table[i].name);
4997 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4998 && (*str)[length] == ':')
5000 *out = &group_reloc_table[i];
5001 *str += (length + 1);
5009 /* Parse a <shifter_operand> for an ARM data processing instruction
5010 (as for parse_shifter_operand) where group relocations are allowed:
5013 #<immediate>, <rotate>
5014 #:<group_reloc>:<expression>
5018 where <group_reloc> is one of the strings defined in group_reloc_table.
5019 The hashes are optional.
5021 Everything else is as for parse_shifter_operand. */
5023 static parse_operand_result
5024 parse_shifter_operand_group_reloc (char **str, int i)
5026 /* Determine if we have the sequence of characters #: or just :
5027 coming next. If we do, then we check for a group relocation.
5028 If we don't, punt the whole lot to parse_shifter_operand. */
5030 if (((*str)[0] == '#' && (*str)[1] == ':')
5031 || (*str)[0] == ':')
5033 struct group_reloc_table_entry *entry;
5035 if ((*str)[0] == '#')
5040 /* Try to parse a group relocation. Anything else is an error. */
5041 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5043 inst.error = _("unknown group relocation");
5044 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5047 /* We now have the group relocation table entry corresponding to
5048 the name in the assembler source. Next, we parse the expression. */
5049 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5050 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5052 /* Record the relocation type (always the ALU variant here). */
5053 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5054 gas_assert (inst.reloc.type != 0);
5056 return PARSE_OPERAND_SUCCESS;
5059 return parse_shifter_operand (str, i) == SUCCESS
5060 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5062 /* Never reached. */
5065 /* Parse a Neon alignment expression. Information is written to
5066 inst.operands[i]. We assume the initial ':' has been skipped.
5068 align .imm = align << 8, .immisalign=1, .preind=0 */
5069 static parse_operand_result
5070 parse_neon_alignment (char **str, int i)
5075 my_get_expression (&exp, &p, GE_NO_PREFIX);
5077 if (exp.X_op != O_constant)
5079 inst.error = _("alignment must be constant");
5080 return PARSE_OPERAND_FAIL;
5083 inst.operands[i].imm = exp.X_add_number << 8;
5084 inst.operands[i].immisalign = 1;
5085 /* Alignments are not pre-indexes. */
5086 inst.operands[i].preind = 0;
5089 return PARSE_OPERAND_SUCCESS;
5092 /* Parse all forms of an ARM address expression. Information is written
5093 to inst.operands[i] and/or inst.reloc.
5095 Preindexed addressing (.preind=1):
5097 [Rn, #offset] .reg=Rn .reloc.exp=offset
5098 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5099 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5100 .shift_kind=shift .reloc.exp=shift_imm
5102 These three may have a trailing ! which causes .writeback to be set also.
5104 Postindexed addressing (.postind=1, .writeback=1):
5106 [Rn], #offset .reg=Rn .reloc.exp=offset
5107 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5108 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5109 .shift_kind=shift .reloc.exp=shift_imm
5111 Unindexed addressing (.preind=0, .postind=0):
5113 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5117 [Rn]{!} shorthand for [Rn,#0]{!}
5118 =immediate .isreg=0 .reloc.exp=immediate
5119 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5121 It is the caller's responsibility to check for addressing modes not
5122 supported by the instruction, and to set inst.reloc.type. */
5124 static parse_operand_result
5125 parse_address_main (char **str, int i, int group_relocations,
5126 group_reloc_type group_type)
5131 if (skip_past_char (&p, '[') == FAIL)
5133 if (skip_past_char (&p, '=') == FAIL)
5135 /* Bare address - translate to PC-relative offset. */
5136 inst.reloc.pc_rel = 1;
5137 inst.operands[i].reg = REG_PC;
5138 inst.operands[i].isreg = 1;
5139 inst.operands[i].preind = 1;
5141 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5143 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5144 return PARSE_OPERAND_FAIL;
5147 return PARSE_OPERAND_SUCCESS;
5150 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5152 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5153 return PARSE_OPERAND_FAIL;
5155 inst.operands[i].reg = reg;
5156 inst.operands[i].isreg = 1;
5158 if (skip_past_comma (&p) == SUCCESS)
5160 inst.operands[i].preind = 1;
5163 else if (*p == '-') p++, inst.operands[i].negative = 1;
5165 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5167 inst.operands[i].imm = reg;
5168 inst.operands[i].immisreg = 1;
5170 if (skip_past_comma (&p) == SUCCESS)
5171 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5172 return PARSE_OPERAND_FAIL;
5174 else if (skip_past_char (&p, ':') == SUCCESS)
5176 /* FIXME: '@' should be used here, but it's filtered out by generic
5177 code before we get to see it here. This may be subject to
5179 parse_operand_result result = parse_neon_alignment (&p, i);
5181 if (result != PARSE_OPERAND_SUCCESS)
5186 if (inst.operands[i].negative)
5188 inst.operands[i].negative = 0;
5192 if (group_relocations
5193 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5195 struct group_reloc_table_entry *entry;
5197 /* Skip over the #: or : sequence. */
5203 /* Try to parse a group relocation. Anything else is an
5205 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5207 inst.error = _("unknown group relocation");
5208 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5211 /* We now have the group relocation table entry corresponding to
5212 the name in the assembler source. Next, we parse the
5214 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5215 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5217 /* Record the relocation type. */
5221 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5225 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5229 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5236 if (inst.reloc.type == 0)
5238 inst.error = _("this group relocation is not allowed on this instruction");
5239 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5245 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5246 return PARSE_OPERAND_FAIL;
5247 /* If the offset is 0, find out if it's a +0 or -0. */
5248 if (inst.reloc.exp.X_op == O_constant
5249 && inst.reloc.exp.X_add_number == 0)
5251 skip_whitespace (q);
5255 skip_whitespace (q);
5258 inst.operands[i].negative = 1;
5263 else if (skip_past_char (&p, ':') == SUCCESS)
5265 /* FIXME: '@' should be used here, but it's filtered out by generic code
5266 before we get to see it here. This may be subject to change. */
5267 parse_operand_result result = parse_neon_alignment (&p, i);
5269 if (result != PARSE_OPERAND_SUCCESS)
5273 if (skip_past_char (&p, ']') == FAIL)
5275 inst.error = _("']' expected");
5276 return PARSE_OPERAND_FAIL;
5279 if (skip_past_char (&p, '!') == SUCCESS)
5280 inst.operands[i].writeback = 1;
5282 else if (skip_past_comma (&p) == SUCCESS)
5284 if (skip_past_char (&p, '{') == SUCCESS)
5286 /* [Rn], {expr} - unindexed, with option */
5287 if (parse_immediate (&p, &inst.operands[i].imm,
5288 0, 255, TRUE) == FAIL)
5289 return PARSE_OPERAND_FAIL;
5291 if (skip_past_char (&p, '}') == FAIL)
5293 inst.error = _("'}' expected at end of 'option' field");
5294 return PARSE_OPERAND_FAIL;
5296 if (inst.operands[i].preind)
5298 inst.error = _("cannot combine index with option");
5299 return PARSE_OPERAND_FAIL;
5302 return PARSE_OPERAND_SUCCESS;
5306 inst.operands[i].postind = 1;
5307 inst.operands[i].writeback = 1;
5309 if (inst.operands[i].preind)
5311 inst.error = _("cannot combine pre- and post-indexing");
5312 return PARSE_OPERAND_FAIL;
5316 else if (*p == '-') p++, inst.operands[i].negative = 1;
5318 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5320 /* We might be using the immediate for alignment already. If we
5321 are, OR the register number into the low-order bits. */
5322 if (inst.operands[i].immisalign)
5323 inst.operands[i].imm |= reg;
5325 inst.operands[i].imm = reg;
5326 inst.operands[i].immisreg = 1;
5328 if (skip_past_comma (&p) == SUCCESS)
5329 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5330 return PARSE_OPERAND_FAIL;
5335 if (inst.operands[i].negative)
5337 inst.operands[i].negative = 0;
5340 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5341 return PARSE_OPERAND_FAIL;
5342 /* If the offset is 0, find out if it's a +0 or -0. */
5343 if (inst.reloc.exp.X_op == O_constant
5344 && inst.reloc.exp.X_add_number == 0)
5346 skip_whitespace (q);
5350 skip_whitespace (q);
5353 inst.operands[i].negative = 1;
5359 /* If at this point neither .preind nor .postind is set, we have a
5360 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5361 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5363 inst.operands[i].preind = 1;
5364 inst.reloc.exp.X_op = O_constant;
5365 inst.reloc.exp.X_add_number = 0;
5368 return PARSE_OPERAND_SUCCESS;
5372 parse_address (char **str, int i)
5374 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5378 static parse_operand_result
5379 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5381 return parse_address_main (str, i, 1, type);
5384 /* Parse an operand for a MOVW or MOVT instruction. */
5386 parse_half (char **str)
5391 skip_past_char (&p, '#');
5392 if (strncasecmp (p, ":lower16:", 9) == 0)
5393 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5394 else if (strncasecmp (p, ":upper16:", 9) == 0)
5395 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5397 if (inst.reloc.type != BFD_RELOC_UNUSED)
5400 skip_whitespace (p);
5403 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5406 if (inst.reloc.type == BFD_RELOC_UNUSED)
5408 if (inst.reloc.exp.X_op != O_constant)
5410 inst.error = _("constant expression expected");
5413 if (inst.reloc.exp.X_add_number < 0
5414 || inst.reloc.exp.X_add_number > 0xffff)
5416 inst.error = _("immediate value out of range");
5424 /* Miscellaneous. */
5426 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5427 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5429 parse_psr (char **str, bfd_boolean lhs)
5432 unsigned long psr_field;
5433 const struct asm_psr *psr;
5435 bfd_boolean is_apsr = FALSE;
5436 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5438 /* PR gas/12698: If the user has specified -march=all then m_profile will
5439 be TRUE, but we want to ignore it in this case as we are building for any
5440 CPU type, including non-m variants. */
5441 if (selected_cpu.core == arm_arch_any.core)
5444 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5445 feature for ease of use and backwards compatibility. */
5447 if (strncasecmp (p, "SPSR", 4) == 0)
5450 goto unsupported_psr;
5452 psr_field = SPSR_BIT;
5454 else if (strncasecmp (p, "CPSR", 4) == 0)
5457 goto unsupported_psr;
5461 else if (strncasecmp (p, "APSR", 4) == 0)
5463 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5464 and ARMv7-R architecture CPUs. */
5473 while (ISALNUM (*p) || *p == '_');
5475 if (strncasecmp (start, "iapsr", 5) == 0
5476 || strncasecmp (start, "eapsr", 5) == 0
5477 || strncasecmp (start, "xpsr", 4) == 0
5478 || strncasecmp (start, "psr", 3) == 0)
5479 p = start + strcspn (start, "rR") + 1;
5481 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5487 /* If APSR is being written, a bitfield may be specified. Note that
5488 APSR itself is handled above. */
5489 if (psr->field <= 3)
5491 psr_field = psr->field;
5497 /* M-profile MSR instructions have the mask field set to "10", except
5498 *PSR variants which modify APSR, which may use a different mask (and
5499 have been handled already). Do that by setting the PSR_f field
5501 return psr->field | (lhs ? PSR_f : 0);
5504 goto unsupported_psr;
5510 /* A suffix follows. */
5516 while (ISALNUM (*p) || *p == '_');
5520 /* APSR uses a notation for bits, rather than fields. */
5521 unsigned int nzcvq_bits = 0;
5522 unsigned int g_bit = 0;
5525 for (bit = start; bit != p; bit++)
5527 switch (TOLOWER (*bit))
5530 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5534 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5538 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5542 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5546 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5550 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5554 inst.error = _("unexpected bit specified after APSR");
5559 if (nzcvq_bits == 0x1f)
5564 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5566 inst.error = _("selected processor does not "
5567 "support DSP extension");
5574 if ((nzcvq_bits & 0x20) != 0
5575 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5576 || (g_bit & 0x2) != 0)
5578 inst.error = _("bad bitmask specified after APSR");
5584 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5589 psr_field |= psr->field;
5595 goto error; /* Garbage after "[CS]PSR". */
5597 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5598 is deprecated, but allow it anyway. */
5602 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5605 else if (!m_profile)
5606 /* These bits are never right for M-profile devices: don't set them
5607 (only code paths which read/write APSR reach here). */
5608 psr_field |= (PSR_c | PSR_f);
5614 inst.error = _("selected processor does not support requested special "
5615 "purpose register");
5619 inst.error = _("flag for {c}psr instruction expected");
5623 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5624 value suitable for splatting into the AIF field of the instruction. */
5627 parse_cps_flags (char **str)
5636 case '\0': case ',':
5639 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5640 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5641 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5644 inst.error = _("unrecognized CPS flag");
5649 if (saw_a_flag == 0)
5651 inst.error = _("missing CPS flags");
5659 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5660 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5663 parse_endian_specifier (char **str)
5668 if (strncasecmp (s, "BE", 2))
5670 else if (strncasecmp (s, "LE", 2))
5674 inst.error = _("valid endian specifiers are be or le");
5678 if (ISALNUM (s[2]) || s[2] == '_')
5680 inst.error = _("valid endian specifiers are be or le");
5685 return little_endian;
5688 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5689 value suitable for poking into the rotate field of an sxt or sxta
5690 instruction, or FAIL on error. */
5693 parse_ror (char **str)
5698 if (strncasecmp (s, "ROR", 3) == 0)
5702 inst.error = _("missing rotation field after comma");
5706 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5711 case 0: *str = s; return 0x0;
5712 case 8: *str = s; return 0x1;
5713 case 16: *str = s; return 0x2;
5714 case 24: *str = s; return 0x3;
5717 inst.error = _("rotation can only be 0, 8, 16, or 24");
5722 /* Parse a conditional code (from conds[] below). The value returned is in the
5723 range 0 .. 14, or FAIL. */
5725 parse_cond (char **str)
5728 const struct asm_cond *c;
5730 /* Condition codes are always 2 characters, so matching up to
5731 3 characters is sufficient. */
5736 while (ISALPHA (*q) && n < 3)
5738 cond[n] = TOLOWER (*q);
5743 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5746 inst.error = _("condition required");
5754 /* Parse an option for a barrier instruction. Returns the encoding for the
5757 parse_barrier (char **str)
5760 const struct asm_barrier_opt *o;
5763 while (ISALPHA (*q))
5766 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5775 /* Parse the operands of a table branch instruction. Similar to a memory
5778 parse_tb (char **str)
5783 if (skip_past_char (&p, '[') == FAIL)
5785 inst.error = _("'[' expected");
5789 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5791 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5794 inst.operands[0].reg = reg;
5796 if (skip_past_comma (&p) == FAIL)
5798 inst.error = _("',' expected");
5802 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5804 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5807 inst.operands[0].imm = reg;
5809 if (skip_past_comma (&p) == SUCCESS)
5811 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5813 if (inst.reloc.exp.X_add_number != 1)
5815 inst.error = _("invalid shift");
5818 inst.operands[0].shifted = 1;
5821 if (skip_past_char (&p, ']') == FAIL)
5823 inst.error = _("']' expected");
5830 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5831 information on the types the operands can take and how they are encoded.
5832 Up to four operands may be read; this function handles setting the
5833 ".present" field for each read operand itself.
5834 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5835 else returns FAIL. */
5838 parse_neon_mov (char **str, int *which_operand)
5840 int i = *which_operand, val;
5841 enum arm_reg_type rtype;
5843 struct neon_type_el optype;
5845 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5847 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5848 inst.operands[i].reg = val;
5849 inst.operands[i].isscalar = 1;
5850 inst.operands[i].vectype = optype;
5851 inst.operands[i++].present = 1;
5853 if (skip_past_comma (&ptr) == FAIL)
5856 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5859 inst.operands[i].reg = val;
5860 inst.operands[i].isreg = 1;
5861 inst.operands[i].present = 1;
5863 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5866 /* Cases 0, 1, 2, 3, 5 (D only). */
5867 if (skip_past_comma (&ptr) == FAIL)
5870 inst.operands[i].reg = val;
5871 inst.operands[i].isreg = 1;
5872 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5873 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5874 inst.operands[i].isvec = 1;
5875 inst.operands[i].vectype = optype;
5876 inst.operands[i++].present = 1;
5878 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5880 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5881 Case 13: VMOV <Sd>, <Rm> */
5882 inst.operands[i].reg = val;
5883 inst.operands[i].isreg = 1;
5884 inst.operands[i].present = 1;
5886 if (rtype == REG_TYPE_NQ)
5888 first_error (_("can't use Neon quad register here"));
5891 else if (rtype != REG_TYPE_VFS)
5894 if (skip_past_comma (&ptr) == FAIL)
5896 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5898 inst.operands[i].reg = val;
5899 inst.operands[i].isreg = 1;
5900 inst.operands[i].present = 1;
5903 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5906 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5907 Case 1: VMOV<c><q> <Dd>, <Dm>
5908 Case 8: VMOV.F32 <Sd>, <Sm>
5909 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5911 inst.operands[i].reg = val;
5912 inst.operands[i].isreg = 1;
5913 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5914 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5915 inst.operands[i].isvec = 1;
5916 inst.operands[i].vectype = optype;
5917 inst.operands[i].present = 1;
5919 if (skip_past_comma (&ptr) == SUCCESS)
5924 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5927 inst.operands[i].reg = val;
5928 inst.operands[i].isreg = 1;
5929 inst.operands[i++].present = 1;
5931 if (skip_past_comma (&ptr) == FAIL)
5934 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5937 inst.operands[i].reg = val;
5938 inst.operands[i].isreg = 1;
5939 inst.operands[i].present = 1;
5942 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5943 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5944 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5945 Case 10: VMOV.F32 <Sd>, #<imm>
5946 Case 11: VMOV.F64 <Dd>, #<imm> */
5947 inst.operands[i].immisfloat = 1;
5948 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5949 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5950 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5954 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5958 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5961 inst.operands[i].reg = val;
5962 inst.operands[i].isreg = 1;
5963 inst.operands[i++].present = 1;
5965 if (skip_past_comma (&ptr) == FAIL)
5968 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5970 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5971 inst.operands[i].reg = val;
5972 inst.operands[i].isscalar = 1;
5973 inst.operands[i].present = 1;
5974 inst.operands[i].vectype = optype;
5976 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5978 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5979 inst.operands[i].reg = val;
5980 inst.operands[i].isreg = 1;
5981 inst.operands[i++].present = 1;
5983 if (skip_past_comma (&ptr) == FAIL)
5986 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5989 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5993 inst.operands[i].reg = val;
5994 inst.operands[i].isreg = 1;
5995 inst.operands[i].isvec = 1;
5996 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5997 inst.operands[i].vectype = optype;
5998 inst.operands[i].present = 1;
6000 if (rtype == REG_TYPE_VFS)
6004 if (skip_past_comma (&ptr) == FAIL)
6006 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6009 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6012 inst.operands[i].reg = val;
6013 inst.operands[i].isreg = 1;
6014 inst.operands[i].isvec = 1;
6015 inst.operands[i].issingle = 1;
6016 inst.operands[i].vectype = optype;
6017 inst.operands[i].present = 1;
6020 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6024 inst.operands[i].reg = val;
6025 inst.operands[i].isreg = 1;
6026 inst.operands[i].isvec = 1;
6027 inst.operands[i].issingle = 1;
6028 inst.operands[i].vectype = optype;
6029 inst.operands[i].present = 1;
6034 first_error (_("parse error"));
6038 /* Successfully parsed the operands. Update args. */
6044 first_error (_("expected comma"));
6048 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6052 /* Use this macro when the operand constraints are different
6053 for ARM and THUMB (e.g. ldrd). */
6054 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6055 ((arm_operand) | ((thumb_operand) << 16))
6057 /* Matcher codes for parse_operands. */
6058 enum operand_parse_code
6060 OP_stop, /* end of line */
6062 OP_RR, /* ARM register */
6063 OP_RRnpc, /* ARM register, not r15 */
6064 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6065 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6066 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6067 optional trailing ! */
6068 OP_RRw, /* ARM register, not r15, optional trailing ! */
6069 OP_RCP, /* Coprocessor number */
6070 OP_RCN, /* Coprocessor register */
6071 OP_RF, /* FPA register */
6072 OP_RVS, /* VFP single precision register */
6073 OP_RVD, /* VFP double precision register (0..15) */
6074 OP_RND, /* Neon double precision register (0..31) */
6075 OP_RNQ, /* Neon quad precision register */
6076 OP_RVSD, /* VFP single or double precision register */
6077 OP_RNDQ, /* Neon double or quad precision register */
6078 OP_RNSDQ, /* Neon single, double or quad precision register */
6079 OP_RNSC, /* Neon scalar D[X] */
6080 OP_RVC, /* VFP control register */
6081 OP_RMF, /* Maverick F register */
6082 OP_RMD, /* Maverick D register */
6083 OP_RMFX, /* Maverick FX register */
6084 OP_RMDX, /* Maverick DX register */
6085 OP_RMAX, /* Maverick AX register */
6086 OP_RMDS, /* Maverick DSPSC register */
6087 OP_RIWR, /* iWMMXt wR register */
6088 OP_RIWC, /* iWMMXt wC register */
6089 OP_RIWG, /* iWMMXt wCG register */
6090 OP_RXA, /* XScale accumulator register */
6092 OP_REGLST, /* ARM register list */
6093 OP_VRSLST, /* VFP single-precision register list */
6094 OP_VRDLST, /* VFP double-precision register list */
6095 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6096 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6097 OP_NSTRLST, /* Neon element/structure list */
6099 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6100 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6101 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6102 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6103 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6104 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6105 OP_VMOV, /* Neon VMOV operands. */
6106 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6107 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6108 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6110 OP_I0, /* immediate zero */
6111 OP_I7, /* immediate value 0 .. 7 */
6112 OP_I15, /* 0 .. 15 */
6113 OP_I16, /* 1 .. 16 */
6114 OP_I16z, /* 0 .. 16 */
6115 OP_I31, /* 0 .. 31 */
6116 OP_I31w, /* 0 .. 31, optional trailing ! */
6117 OP_I32, /* 1 .. 32 */
6118 OP_I32z, /* 0 .. 32 */
6119 OP_I63, /* 0 .. 63 */
6120 OP_I63s, /* -64 .. 63 */
6121 OP_I64, /* 1 .. 64 */
6122 OP_I64z, /* 0 .. 64 */
6123 OP_I255, /* 0 .. 255 */
6125 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6126 OP_I7b, /* 0 .. 7 */
6127 OP_I15b, /* 0 .. 15 */
6128 OP_I31b, /* 0 .. 31 */
6130 OP_SH, /* shifter operand */
6131 OP_SHG, /* shifter operand with possible group relocation */
6132 OP_ADDR, /* Memory address expression (any mode) */
6133 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6134 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6135 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6136 OP_EXP, /* arbitrary expression */
6137 OP_EXPi, /* same, with optional immediate prefix */
6138 OP_EXPr, /* same, with optional relocation suffix */
6139 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6141 OP_CPSF, /* CPS flags */
6142 OP_ENDI, /* Endianness specifier */
6143 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6144 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6145 OP_COND, /* conditional code */
6146 OP_TB, /* Table branch. */
6148 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6150 OP_RRnpc_I0, /* ARM register or literal 0 */
6151 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6152 OP_RR_EXi, /* ARM register or expression with imm prefix */
6153 OP_RF_IF, /* FPA register or immediate */
6154 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6155 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6157 /* Optional operands. */
6158 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6159 OP_oI31b, /* 0 .. 31 */
6160 OP_oI32b, /* 1 .. 32 */
6161 OP_oI32z, /* 0 .. 32 */
6162 OP_oIffffb, /* 0 .. 65535 */
6163 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6165 OP_oRR, /* ARM register */
6166 OP_oRRnpc, /* ARM register, not the PC */
6167 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6168 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6169 OP_oRND, /* Optional Neon double precision register */
6170 OP_oRNQ, /* Optional Neon quad precision register */
6171 OP_oRNDQ, /* Optional Neon double or quad precision register */
6172 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6173 OP_oSHll, /* LSL immediate */
6174 OP_oSHar, /* ASR immediate */
6175 OP_oSHllar, /* LSL or ASR immediate */
6176 OP_oROR, /* ROR 0/8/16/24 */
6177 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6179 /* Some pre-defined mixed (ARM/THUMB) operands. */
6180 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6181 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6182 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6184 OP_FIRST_OPTIONAL = OP_oI7b
6187 /* Generic instruction operand parser. This does no encoding and no
6188 semantic validation; it merely squirrels values away in the inst
6189 structure. Returns SUCCESS or FAIL depending on whether the
6190 specified grammar matched. */
6192 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6194 unsigned const int *upat = pattern;
6195 char *backtrack_pos = 0;
6196 const char *backtrack_error = 0;
6197 int i, val, backtrack_index = 0;
6198 enum arm_reg_type rtype;
6199 parse_operand_result result;
6200 unsigned int op_parse_code;
6202 #define po_char_or_fail(chr) \
6205 if (skip_past_char (&str, chr) == FAIL) \
6210 #define po_reg_or_fail(regtype) \
6213 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6214 & inst.operands[i].vectype); \
6217 first_error (_(reg_expected_msgs[regtype])); \
6220 inst.operands[i].reg = val; \
6221 inst.operands[i].isreg = 1; \
6222 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6223 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6224 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6225 || rtype == REG_TYPE_VFD \
6226 || rtype == REG_TYPE_NQ); \
6230 #define po_reg_or_goto(regtype, label) \
6233 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6234 & inst.operands[i].vectype); \
6238 inst.operands[i].reg = val; \
6239 inst.operands[i].isreg = 1; \
6240 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6241 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6242 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6243 || rtype == REG_TYPE_VFD \
6244 || rtype == REG_TYPE_NQ); \
6248 #define po_imm_or_fail(min, max, popt) \
6251 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6253 inst.operands[i].imm = val; \
6257 #define po_scalar_or_goto(elsz, label) \
6260 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6263 inst.operands[i].reg = val; \
6264 inst.operands[i].isscalar = 1; \
6268 #define po_misc_or_fail(expr) \
6276 #define po_misc_or_fail_no_backtrack(expr) \
6280 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6281 backtrack_pos = 0; \
6282 if (result != PARSE_OPERAND_SUCCESS) \
6287 #define po_barrier_or_imm(str) \
6290 val = parse_barrier (&str); \
6293 if (ISALPHA (*str)) \
6300 if ((inst.instruction & 0xf0) == 0x60 \
6303 /* ISB can only take SY as an option. */ \
6304 inst.error = _("invalid barrier type"); \
6311 skip_whitespace (str);
6313 for (i = 0; upat[i] != OP_stop; i++)
6315 op_parse_code = upat[i];
6316 if (op_parse_code >= 1<<16)
6317 op_parse_code = thumb ? (op_parse_code >> 16)
6318 : (op_parse_code & ((1<<16)-1));
6320 if (op_parse_code >= OP_FIRST_OPTIONAL)
6322 /* Remember where we are in case we need to backtrack. */
6323 gas_assert (!backtrack_pos);
6324 backtrack_pos = str;
6325 backtrack_error = inst.error;
6326 backtrack_index = i;
6329 if (i > 0 && (i > 1 || inst.operands[0].present))
6330 po_char_or_fail (',');
6332 switch (op_parse_code)
6340 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6341 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6342 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6343 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6344 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6345 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6347 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6349 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6351 /* Also accept generic coprocessor regs for unknown registers. */
6353 po_reg_or_fail (REG_TYPE_CN);
6355 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6356 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6357 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6358 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6359 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6360 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6361 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6362 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6363 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6364 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6366 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6368 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6369 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6371 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6373 /* Neon scalar. Using an element size of 8 means that some invalid
6374 scalars are accepted here, so deal with those in later code. */
6375 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6379 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6382 po_imm_or_fail (0, 0, TRUE);
6387 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6392 po_scalar_or_goto (8, try_rr);
6395 po_reg_or_fail (REG_TYPE_RN);
6401 po_scalar_or_goto (8, try_nsdq);
6404 po_reg_or_fail (REG_TYPE_NSDQ);
6410 po_scalar_or_goto (8, try_ndq);
6413 po_reg_or_fail (REG_TYPE_NDQ);
6419 po_scalar_or_goto (8, try_vfd);
6422 po_reg_or_fail (REG_TYPE_VFD);
6427 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6428 not careful then bad things might happen. */
6429 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6434 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6437 /* There's a possibility of getting a 64-bit immediate here, so
6438 we need special handling. */
6439 if (parse_big_immediate (&str, i) == FAIL)
6441 inst.error = _("immediate value is out of range");
6449 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6452 po_imm_or_fail (0, 63, TRUE);
6457 po_char_or_fail ('[');
6458 po_reg_or_fail (REG_TYPE_RN);
6459 po_char_or_fail (']');
6465 po_reg_or_fail (REG_TYPE_RN);
6466 if (skip_past_char (&str, '!') == SUCCESS)
6467 inst.operands[i].writeback = 1;
6471 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6472 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6473 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6474 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6475 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6476 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6477 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6478 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6479 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6480 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6481 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6482 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6484 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6486 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6487 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6489 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6490 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6491 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6492 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6494 /* Immediate variants */
6496 po_char_or_fail ('{');
6497 po_imm_or_fail (0, 255, TRUE);
6498 po_char_or_fail ('}');
6502 /* The expression parser chokes on a trailing !, so we have
6503 to find it first and zap it. */
6506 while (*s && *s != ',')
6511 inst.operands[i].writeback = 1;
6513 po_imm_or_fail (0, 31, TRUE);
6521 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6526 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6531 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6533 if (inst.reloc.exp.X_op == O_symbol)
6535 val = parse_reloc (&str);
6538 inst.error = _("unrecognized relocation suffix");
6541 else if (val != BFD_RELOC_UNUSED)
6543 inst.operands[i].imm = val;
6544 inst.operands[i].hasreloc = 1;
6549 /* Operand for MOVW or MOVT. */
6551 po_misc_or_fail (parse_half (&str));
6554 /* Register or expression. */
6555 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6556 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6558 /* Register or immediate. */
6559 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6560 I0: po_imm_or_fail (0, 0, FALSE); break;
6562 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6564 if (!is_immediate_prefix (*str))
6567 val = parse_fpa_immediate (&str);
6570 /* FPA immediates are encoded as registers 8-15.
6571 parse_fpa_immediate has already applied the offset. */
6572 inst.operands[i].reg = val;
6573 inst.operands[i].isreg = 1;
6576 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6577 I32z: po_imm_or_fail (0, 32, FALSE); break;
6579 /* Two kinds of register. */
6582 struct reg_entry *rege = arm_reg_parse_multi (&str);
6584 || (rege->type != REG_TYPE_MMXWR
6585 && rege->type != REG_TYPE_MMXWC
6586 && rege->type != REG_TYPE_MMXWCG))
6588 inst.error = _("iWMMXt data or control register expected");
6591 inst.operands[i].reg = rege->number;
6592 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6598 struct reg_entry *rege = arm_reg_parse_multi (&str);
6600 || (rege->type != REG_TYPE_MMXWC
6601 && rege->type != REG_TYPE_MMXWCG))
6603 inst.error = _("iWMMXt control register expected");
6606 inst.operands[i].reg = rege->number;
6607 inst.operands[i].isreg = 1;
6612 case OP_CPSF: val = parse_cps_flags (&str); break;
6613 case OP_ENDI: val = parse_endian_specifier (&str); break;
6614 case OP_oROR: val = parse_ror (&str); break;
6615 case OP_COND: val = parse_cond (&str); break;
6616 case OP_oBARRIER_I15:
6617 po_barrier_or_imm (str); break;
6619 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6625 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6626 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6628 inst.error = _("Banked registers are not available with this "
6634 val = parse_psr (&str, op_parse_code == OP_wPSR);
6638 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6641 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6643 if (strncasecmp (str, "APSR_", 5) == 0)
6650 case 'c': found = (found & 1) ? 16 : found | 1; break;
6651 case 'n': found = (found & 2) ? 16 : found | 2; break;
6652 case 'z': found = (found & 4) ? 16 : found | 4; break;
6653 case 'v': found = (found & 8) ? 16 : found | 8; break;
6654 default: found = 16;
6658 inst.operands[i].isvec = 1;
6659 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6660 inst.operands[i].reg = REG_PC;
6667 po_misc_or_fail (parse_tb (&str));
6670 /* Register lists. */
6672 val = parse_reg_list (&str);
6675 inst.operands[1].writeback = 1;
6681 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6685 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6689 /* Allow Q registers too. */
6690 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6695 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6697 inst.operands[i].issingle = 1;
6702 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6707 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6708 &inst.operands[i].vectype);
6711 /* Addressing modes */
6713 po_misc_or_fail (parse_address (&str, i));
6717 po_misc_or_fail_no_backtrack (
6718 parse_address_group_reloc (&str, i, GROUP_LDR));
6722 po_misc_or_fail_no_backtrack (
6723 parse_address_group_reloc (&str, i, GROUP_LDRS));
6727 po_misc_or_fail_no_backtrack (
6728 parse_address_group_reloc (&str, i, GROUP_LDC));
6732 po_misc_or_fail (parse_shifter_operand (&str, i));
6736 po_misc_or_fail_no_backtrack (
6737 parse_shifter_operand_group_reloc (&str, i));
6741 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6745 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6749 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6753 as_fatal (_("unhandled operand code %d"), op_parse_code);
6756 /* Various value-based sanity checks and shared operations. We
6757 do not signal immediate failures for the register constraints;
6758 this allows a syntax error to take precedence. */
6759 switch (op_parse_code)
6767 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6768 inst.error = BAD_PC;
6773 if (inst.operands[i].isreg)
6775 if (inst.operands[i].reg == REG_PC)
6776 inst.error = BAD_PC;
6777 else if (inst.operands[i].reg == REG_SP)
6778 inst.error = BAD_SP;
6783 if (inst.operands[i].isreg
6784 && inst.operands[i].reg == REG_PC
6785 && (inst.operands[i].writeback || thumb))
6786 inst.error = BAD_PC;
6795 case OP_oBARRIER_I15:
6804 inst.operands[i].imm = val;
6811 /* If we get here, this operand was successfully parsed. */
6812 inst.operands[i].present = 1;
6816 inst.error = BAD_ARGS;
6821 /* The parse routine should already have set inst.error, but set a
6822 default here just in case. */
6824 inst.error = _("syntax error");
6828 /* Do not backtrack over a trailing optional argument that
6829 absorbed some text. We will only fail again, with the
6830 'garbage following instruction' error message, which is
6831 probably less helpful than the current one. */
6832 if (backtrack_index == i && backtrack_pos != str
6833 && upat[i+1] == OP_stop)
6836 inst.error = _("syntax error");
6840 /* Try again, skipping the optional argument at backtrack_pos. */
6841 str = backtrack_pos;
6842 inst.error = backtrack_error;
6843 inst.operands[backtrack_index].present = 0;
6844 i = backtrack_index;
6848 /* Check that we have parsed all the arguments. */
6849 if (*str != '\0' && !inst.error)
6850 inst.error = _("garbage following instruction");
6852 return inst.error ? FAIL : SUCCESS;
6855 #undef po_char_or_fail
6856 #undef po_reg_or_fail
6857 #undef po_reg_or_goto
6858 #undef po_imm_or_fail
6859 #undef po_scalar_or_fail
6860 #undef po_barrier_or_imm
6862 /* Shorthand macro for instruction encoding functions issuing errors. */
6863 #define constraint(expr, err) \
6874 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6875 instructions are unpredictable if these registers are used. This
6876 is the BadReg predicate in ARM's Thumb-2 documentation. */
6877 #define reject_bad_reg(reg) \
6879 if (reg == REG_SP || reg == REG_PC) \
6881 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6886 /* If REG is R13 (the stack pointer), warn that its use is
6888 #define warn_deprecated_sp(reg) \
6890 if (warn_on_deprecated && reg == REG_SP) \
6891 as_warn (_("use of r13 is deprecated")); \
6894 /* Functions for operand encoding. ARM, then Thumb. */
6896 #define rotate_left(v, n) (v << n | v >> (32 - n))
6898 /* If VAL can be encoded in the immediate field of an ARM instruction,
6899 return the encoded form. Otherwise, return FAIL. */
6902 encode_arm_immediate (unsigned int val)
6906 for (i = 0; i < 32; i += 2)
6907 if ((a = rotate_left (val, i)) <= 0xff)
6908 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6913 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6914 return the encoded form. Otherwise, return FAIL. */
6916 encode_thumb32_immediate (unsigned int val)
6923 for (i = 1; i <= 24; i++)
6926 if ((val & ~(0xff << i)) == 0)
6927 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6931 if (val == ((a << 16) | a))
6933 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6937 if (val == ((a << 16) | a))
6938 return 0x200 | (a >> 8);
6942 /* Encode a VFP SP or DP register number into inst.instruction. */
6945 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6947 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6950 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6953 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6956 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6961 first_error (_("D register out of range for selected VFP version"));
6969 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6973 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6977 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6981 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6985 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6989 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6997 /* Encode a <shift> in an ARM-format instruction. The immediate,
6998 if any, is handled by md_apply_fix. */
7000 encode_arm_shift (int i)
7002 if (inst.operands[i].shift_kind == SHIFT_RRX)
7003 inst.instruction |= SHIFT_ROR << 5;
7006 inst.instruction |= inst.operands[i].shift_kind << 5;
7007 if (inst.operands[i].immisreg)
7009 inst.instruction |= SHIFT_BY_REG;
7010 inst.instruction |= inst.operands[i].imm << 8;
7013 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7018 encode_arm_shifter_operand (int i)
7020 if (inst.operands[i].isreg)
7022 inst.instruction |= inst.operands[i].reg;
7023 encode_arm_shift (i);
7027 inst.instruction |= INST_IMMEDIATE;
7028 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7029 inst.instruction |= inst.operands[i].imm;
7033 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7035 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7037 gas_assert (inst.operands[i].isreg);
7038 inst.instruction |= inst.operands[i].reg << 16;
7040 if (inst.operands[i].preind)
7044 inst.error = _("instruction does not accept preindexed addressing");
7047 inst.instruction |= PRE_INDEX;
7048 if (inst.operands[i].writeback)
7049 inst.instruction |= WRITE_BACK;
7052 else if (inst.operands[i].postind)
7054 gas_assert (inst.operands[i].writeback);
7056 inst.instruction |= WRITE_BACK;
7058 else /* unindexed - only for coprocessor */
7060 inst.error = _("instruction does not accept unindexed addressing");
7064 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7065 && (((inst.instruction & 0x000f0000) >> 16)
7066 == ((inst.instruction & 0x0000f000) >> 12)))
7067 as_warn ((inst.instruction & LOAD_BIT)
7068 ? _("destination register same as write-back base")
7069 : _("source register same as write-back base"));
7072 /* inst.operands[i] was set up by parse_address. Encode it into an
7073 ARM-format mode 2 load or store instruction. If is_t is true,
7074 reject forms that cannot be used with a T instruction (i.e. not
7077 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7079 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7081 encode_arm_addr_mode_common (i, is_t);
7083 if (inst.operands[i].immisreg)
7085 constraint ((inst.operands[i].imm == REG_PC
7086 || (is_pc && inst.operands[i].writeback)),
7088 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7089 inst.instruction |= inst.operands[i].imm;
7090 if (!inst.operands[i].negative)
7091 inst.instruction |= INDEX_UP;
7092 if (inst.operands[i].shifted)
7094 if (inst.operands[i].shift_kind == SHIFT_RRX)
7095 inst.instruction |= SHIFT_ROR << 5;
7098 inst.instruction |= inst.operands[i].shift_kind << 5;
7099 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7103 else /* immediate offset in inst.reloc */
7105 if (is_pc && !inst.reloc.pc_rel)
7107 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7109 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7110 cannot use PC in addressing.
7111 PC cannot be used in writeback addressing, either. */
7112 constraint ((is_t || inst.operands[i].writeback),
7115 /* Use of PC in str is deprecated for ARMv7. */
7116 if (warn_on_deprecated
7118 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7119 as_warn (_("use of PC in this instruction is deprecated"));
7122 if (inst.reloc.type == BFD_RELOC_UNUSED)
7124 /* Prefer + for zero encoded value. */
7125 if (!inst.operands[i].negative)
7126 inst.instruction |= INDEX_UP;
7127 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7132 /* inst.operands[i] was set up by parse_address. Encode it into an
7133 ARM-format mode 3 load or store instruction. Reject forms that
7134 cannot be used with such instructions. If is_t is true, reject
7135 forms that cannot be used with a T instruction (i.e. not
7138 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7140 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7142 inst.error = _("instruction does not accept scaled register index");
7146 encode_arm_addr_mode_common (i, is_t);
7148 if (inst.operands[i].immisreg)
7150 constraint ((inst.operands[i].imm == REG_PC
7151 || inst.operands[i].reg == REG_PC),
7153 inst.instruction |= inst.operands[i].imm;
7154 if (!inst.operands[i].negative)
7155 inst.instruction |= INDEX_UP;
7157 else /* immediate offset in inst.reloc */
7159 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7160 && inst.operands[i].writeback),
7162 inst.instruction |= HWOFFSET_IMM;
7163 if (inst.reloc.type == BFD_RELOC_UNUSED)
7165 /* Prefer + for zero encoded value. */
7166 if (!inst.operands[i].negative)
7167 inst.instruction |= INDEX_UP;
7169 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7174 /* inst.operands[i] was set up by parse_address. Encode it into an
7175 ARM-format instruction. Reject all forms which cannot be encoded
7176 into a coprocessor load/store instruction. If wb_ok is false,
7177 reject use of writeback; if unind_ok is false, reject use of
7178 unindexed addressing. If reloc_override is not 0, use it instead
7179 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7180 (in which case it is preserved). */
7183 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7185 inst.instruction |= inst.operands[i].reg << 16;
7187 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7189 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7191 gas_assert (!inst.operands[i].writeback);
7194 inst.error = _("instruction does not support unindexed addressing");
7197 inst.instruction |= inst.operands[i].imm;
7198 inst.instruction |= INDEX_UP;
7202 if (inst.operands[i].preind)
7203 inst.instruction |= PRE_INDEX;
7205 if (inst.operands[i].writeback)
7207 if (inst.operands[i].reg == REG_PC)
7209 inst.error = _("pc may not be used with write-back");
7214 inst.error = _("instruction does not support writeback");
7217 inst.instruction |= WRITE_BACK;
7221 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7222 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7223 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7224 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7227 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7229 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7232 /* Prefer + for zero encoded value. */
7233 if (!inst.operands[i].negative)
7234 inst.instruction |= INDEX_UP;
7239 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7240 Determine whether it can be performed with a move instruction; if
7241 it can, convert inst.instruction to that move instruction and
7242 return TRUE; if it can't, convert inst.instruction to a literal-pool
7243 load and return FALSE. If this is not a valid thing to do in the
7244 current context, set inst.error and return TRUE.
7246 inst.operands[i] describes the destination register. */
7249 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7254 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7258 if ((inst.instruction & tbit) == 0)
7260 inst.error = _("invalid pseudo operation");
7263 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7265 inst.error = _("constant expression expected");
7268 if (inst.reloc.exp.X_op == O_constant)
7272 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7274 /* This can be done with a mov(1) instruction. */
7275 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7276 inst.instruction |= inst.reloc.exp.X_add_number;
7282 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7285 /* This can be done with a mov instruction. */
7286 inst.instruction &= LITERAL_MASK;
7287 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7288 inst.instruction |= value & 0xfff;
7292 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7295 /* This can be done with a mvn instruction. */
7296 inst.instruction &= LITERAL_MASK;
7297 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7298 inst.instruction |= value & 0xfff;
7304 if (add_to_lit_pool () == FAIL)
7306 inst.error = _("literal pool insertion failed");
7309 inst.operands[1].reg = REG_PC;
7310 inst.operands[1].isreg = 1;
7311 inst.operands[1].preind = 1;
7312 inst.reloc.pc_rel = 1;
7313 inst.reloc.type = (thumb_p
7314 ? BFD_RELOC_ARM_THUMB_OFFSET
7316 ? BFD_RELOC_ARM_HWLITERAL
7317 : BFD_RELOC_ARM_LITERAL));
7321 /* Functions for instruction encoding, sorted by sub-architecture.
7322 First some generics; their names are taken from the conventional
7323 bit positions for register arguments in ARM format instructions. */
7333 inst.instruction |= inst.operands[0].reg << 12;
7339 inst.instruction |= inst.operands[0].reg << 12;
7340 inst.instruction |= inst.operands[1].reg;
7346 inst.instruction |= inst.operands[0].reg << 12;
7347 inst.instruction |= inst.operands[1].reg << 16;
7353 inst.instruction |= inst.operands[0].reg << 16;
7354 inst.instruction |= inst.operands[1].reg << 12;
7360 unsigned Rn = inst.operands[2].reg;
7361 /* Enforce restrictions on SWP instruction. */
7362 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7364 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7365 _("Rn must not overlap other operands"));
7367 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7368 if (warn_on_deprecated
7369 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7370 as_warn (_("swp{b} use is deprecated for this architecture"));
7373 inst.instruction |= inst.operands[0].reg << 12;
7374 inst.instruction |= inst.operands[1].reg;
7375 inst.instruction |= Rn << 16;
7381 inst.instruction |= inst.operands[0].reg << 12;
7382 inst.instruction |= inst.operands[1].reg << 16;
7383 inst.instruction |= inst.operands[2].reg;
7389 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7390 constraint (((inst.reloc.exp.X_op != O_constant
7391 && inst.reloc.exp.X_op != O_illegal)
7392 || inst.reloc.exp.X_add_number != 0),
7394 inst.instruction |= inst.operands[0].reg;
7395 inst.instruction |= inst.operands[1].reg << 12;
7396 inst.instruction |= inst.operands[2].reg << 16;
7402 inst.instruction |= inst.operands[0].imm;
7408 inst.instruction |= inst.operands[0].reg << 12;
7409 encode_arm_cp_address (1, TRUE, TRUE, 0);
7412 /* ARM instructions, in alphabetical order by function name (except
7413 that wrapper functions appear immediately after the function they
7416 /* This is a pseudo-op of the form "adr rd, label" to be converted
7417 into a relative address of the form "add rd, pc, #label-.-8". */
7422 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7424 /* Frag hacking will turn this into a sub instruction if the offset turns
7425 out to be negative. */
7426 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7427 inst.reloc.pc_rel = 1;
7428 inst.reloc.exp.X_add_number -= 8;
7431 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7432 into a relative address of the form:
7433 add rd, pc, #low(label-.-8)"
7434 add rd, rd, #high(label-.-8)" */
7439 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7441 /* Frag hacking will turn this into a sub instruction if the offset turns
7442 out to be negative. */
7443 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7444 inst.reloc.pc_rel = 1;
7445 inst.size = INSN_SIZE * 2;
7446 inst.reloc.exp.X_add_number -= 8;
7452 if (!inst.operands[1].present)
7453 inst.operands[1].reg = inst.operands[0].reg;
7454 inst.instruction |= inst.operands[0].reg << 12;
7455 inst.instruction |= inst.operands[1].reg << 16;
7456 encode_arm_shifter_operand (2);
7462 if (inst.operands[0].present)
7464 constraint ((inst.instruction & 0xf0) != 0x40
7465 && inst.operands[0].imm > 0xf
7466 && inst.operands[0].imm < 0x0,
7467 _("bad barrier type"));
7468 inst.instruction |= inst.operands[0].imm;
7471 inst.instruction |= 0xf;
7477 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7478 constraint (msb > 32, _("bit-field extends past end of register"));
7479 /* The instruction encoding stores the LSB and MSB,
7480 not the LSB and width. */
7481 inst.instruction |= inst.operands[0].reg << 12;
7482 inst.instruction |= inst.operands[1].imm << 7;
7483 inst.instruction |= (msb - 1) << 16;
7491 /* #0 in second position is alternative syntax for bfc, which is
7492 the same instruction but with REG_PC in the Rm field. */
7493 if (!inst.operands[1].isreg)
7494 inst.operands[1].reg = REG_PC;
7496 msb = inst.operands[2].imm + inst.operands[3].imm;
7497 constraint (msb > 32, _("bit-field extends past end of register"));
7498 /* The instruction encoding stores the LSB and MSB,
7499 not the LSB and width. */
7500 inst.instruction |= inst.operands[0].reg << 12;
7501 inst.instruction |= inst.operands[1].reg;
7502 inst.instruction |= inst.operands[2].imm << 7;
7503 inst.instruction |= (msb - 1) << 16;
7509 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7510 _("bit-field extends past end of register"));
7511 inst.instruction |= inst.operands[0].reg << 12;
7512 inst.instruction |= inst.operands[1].reg;
7513 inst.instruction |= inst.operands[2].imm << 7;
7514 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7517 /* ARM V5 breakpoint instruction (argument parse)
7518 BKPT <16 bit unsigned immediate>
7519 Instruction is not conditional.
7520 The bit pattern given in insns[] has the COND_ALWAYS condition,
7521 and it is an error if the caller tried to override that. */
7526 /* Top 12 of 16 bits to bits 19:8. */
7527 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7529 /* Bottom 4 of 16 bits to bits 3:0. */
7530 inst.instruction |= inst.operands[0].imm & 0xf;
7534 encode_branch (int default_reloc)
7536 if (inst.operands[0].hasreloc)
7538 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7539 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7540 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7541 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7542 ? BFD_RELOC_ARM_PLT32
7543 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7546 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7547 inst.reloc.pc_rel = 1;
7554 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7555 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7558 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7565 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7567 if (inst.cond == COND_ALWAYS)
7568 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7570 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7574 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7577 /* ARM V5 branch-link-exchange instruction (argument parse)
7578 BLX <target_addr> ie BLX(1)
7579 BLX{<condition>} <Rm> ie BLX(2)
7580 Unfortunately, there are two different opcodes for this mnemonic.
7581 So, the insns[].value is not used, and the code here zaps values
7582 into inst.instruction.
7583 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7588 if (inst.operands[0].isreg)
7590 /* Arg is a register; the opcode provided by insns[] is correct.
7591 It is not illegal to do "blx pc", just useless. */
7592 if (inst.operands[0].reg == REG_PC)
7593 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7595 inst.instruction |= inst.operands[0].reg;
7599 /* Arg is an address; this instruction cannot be executed
7600 conditionally, and the opcode must be adjusted.
7601 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7602 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7603 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7604 inst.instruction = 0xfa000000;
7605 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7612 bfd_boolean want_reloc;
7614 if (inst.operands[0].reg == REG_PC)
7615 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7617 inst.instruction |= inst.operands[0].reg;
7618 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7619 it is for ARMv4t or earlier. */
7620 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7621 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7625 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7630 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7634 /* ARM v5TEJ. Jump to Jazelle code. */
7639 if (inst.operands[0].reg == REG_PC)
7640 as_tsktsk (_("use of r15 in bxj is not really useful"));
7642 inst.instruction |= inst.operands[0].reg;
7645 /* Co-processor data operation:
7646 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7647 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7651 inst.instruction |= inst.operands[0].reg << 8;
7652 inst.instruction |= inst.operands[1].imm << 20;
7653 inst.instruction |= inst.operands[2].reg << 12;
7654 inst.instruction |= inst.operands[3].reg << 16;
7655 inst.instruction |= inst.operands[4].reg;
7656 inst.instruction |= inst.operands[5].imm << 5;
7662 inst.instruction |= inst.operands[0].reg << 16;
7663 encode_arm_shifter_operand (1);
7666 /* Transfer between coprocessor and ARM registers.
7667 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7672 No special properties. */
7679 Rd = inst.operands[2].reg;
7682 if (inst.instruction == 0xee000010
7683 || inst.instruction == 0xfe000010)
7685 reject_bad_reg (Rd);
7688 constraint (Rd == REG_SP, BAD_SP);
7693 if (inst.instruction == 0xe000010)
7694 constraint (Rd == REG_PC, BAD_PC);
7698 inst.instruction |= inst.operands[0].reg << 8;
7699 inst.instruction |= inst.operands[1].imm << 21;
7700 inst.instruction |= Rd << 12;
7701 inst.instruction |= inst.operands[3].reg << 16;
7702 inst.instruction |= inst.operands[4].reg;
7703 inst.instruction |= inst.operands[5].imm << 5;
7706 /* Transfer between coprocessor register and pair of ARM registers.
7707 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7712 Two XScale instructions are special cases of these:
7714 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7715 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7717 Result unpredictable if Rd or Rn is R15. */
7724 Rd = inst.operands[2].reg;
7725 Rn = inst.operands[3].reg;
7729 reject_bad_reg (Rd);
7730 reject_bad_reg (Rn);
7734 constraint (Rd == REG_PC, BAD_PC);
7735 constraint (Rn == REG_PC, BAD_PC);
7738 inst.instruction |= inst.operands[0].reg << 8;
7739 inst.instruction |= inst.operands[1].imm << 4;
7740 inst.instruction |= Rd << 12;
7741 inst.instruction |= Rn << 16;
7742 inst.instruction |= inst.operands[4].reg;
7748 inst.instruction |= inst.operands[0].imm << 6;
7749 if (inst.operands[1].present)
7751 inst.instruction |= CPSI_MMOD;
7752 inst.instruction |= inst.operands[1].imm;
7759 inst.instruction |= inst.operands[0].imm;
7765 unsigned Rd, Rn, Rm;
7767 Rd = inst.operands[0].reg;
7768 Rn = (inst.operands[1].present
7769 ? inst.operands[1].reg : Rd);
7770 Rm = inst.operands[2].reg;
7772 constraint ((Rd == REG_PC), BAD_PC);
7773 constraint ((Rn == REG_PC), BAD_PC);
7774 constraint ((Rm == REG_PC), BAD_PC);
7776 inst.instruction |= Rd << 16;
7777 inst.instruction |= Rn << 0;
7778 inst.instruction |= Rm << 8;
7784 /* There is no IT instruction in ARM mode. We
7785 process it to do the validation as if in
7786 thumb mode, just in case the code gets
7787 assembled for thumb using the unified syntax. */
7792 set_it_insn_type (IT_INSN);
7793 now_it.mask = (inst.instruction & 0xf) | 0x10;
7794 now_it.cc = inst.operands[0].imm;
7801 int base_reg = inst.operands[0].reg;
7802 int range = inst.operands[1].imm;
7804 inst.instruction |= base_reg << 16;
7805 inst.instruction |= range;
7807 if (inst.operands[1].writeback)
7808 inst.instruction |= LDM_TYPE_2_OR_3;
7810 if (inst.operands[0].writeback)
7812 inst.instruction |= WRITE_BACK;
7813 /* Check for unpredictable uses of writeback. */
7814 if (inst.instruction & LOAD_BIT)
7816 /* Not allowed in LDM type 2. */
7817 if ((inst.instruction & LDM_TYPE_2_OR_3)
7818 && ((range & (1 << REG_PC)) == 0))
7819 as_warn (_("writeback of base register is UNPREDICTABLE"));
7820 /* Only allowed if base reg not in list for other types. */
7821 else if (range & (1 << base_reg))
7822 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7826 /* Not allowed for type 2. */
7827 if (inst.instruction & LDM_TYPE_2_OR_3)
7828 as_warn (_("writeback of base register is UNPREDICTABLE"));
7829 /* Only allowed if base reg not in list, or first in list. */
7830 else if ((range & (1 << base_reg))
7831 && (range & ((1 << base_reg) - 1)))
7832 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7837 /* ARMv5TE load-consecutive (argument parse)
7846 constraint (inst.operands[0].reg % 2 != 0,
7847 _("first transfer register must be even"));
7848 constraint (inst.operands[1].present
7849 && inst.operands[1].reg != inst.operands[0].reg + 1,
7850 _("can only transfer two consecutive registers"));
7851 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7852 constraint (!inst.operands[2].isreg, _("'[' expected"));
7854 if (!inst.operands[1].present)
7855 inst.operands[1].reg = inst.operands[0].reg + 1;
7857 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7858 register and the first register written; we have to diagnose
7859 overlap between the base and the second register written here. */
7861 if (inst.operands[2].reg == inst.operands[1].reg
7862 && (inst.operands[2].writeback || inst.operands[2].postind))
7863 as_warn (_("base register written back, and overlaps "
7864 "second transfer register"));
7866 if (!(inst.instruction & V4_STR_BIT))
7868 /* For an index-register load, the index register must not overlap the
7869 destination (even if not write-back). */
7870 if (inst.operands[2].immisreg
7871 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7872 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7873 as_warn (_("index register overlaps transfer register"));
7875 inst.instruction |= inst.operands[0].reg << 12;
7876 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7882 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7883 || inst.operands[1].postind || inst.operands[1].writeback
7884 || inst.operands[1].immisreg || inst.operands[1].shifted
7885 || inst.operands[1].negative
7886 /* This can arise if the programmer has written
7888 or if they have mistakenly used a register name as the last
7891 It is very difficult to distinguish between these two cases
7892 because "rX" might actually be a label. ie the register
7893 name has been occluded by a symbol of the same name. So we
7894 just generate a general 'bad addressing mode' type error
7895 message and leave it up to the programmer to discover the
7896 true cause and fix their mistake. */
7897 || (inst.operands[1].reg == REG_PC),
7900 constraint (inst.reloc.exp.X_op != O_constant
7901 || inst.reloc.exp.X_add_number != 0,
7902 _("offset must be zero in ARM encoding"));
7904 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7906 inst.instruction |= inst.operands[0].reg << 12;
7907 inst.instruction |= inst.operands[1].reg << 16;
7908 inst.reloc.type = BFD_RELOC_UNUSED;
7914 constraint (inst.operands[0].reg % 2 != 0,
7915 _("even register required"));
7916 constraint (inst.operands[1].present
7917 && inst.operands[1].reg != inst.operands[0].reg + 1,
7918 _("can only load two consecutive registers"));
7919 /* If op 1 were present and equal to PC, this function wouldn't
7920 have been called in the first place. */
7921 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7923 inst.instruction |= inst.operands[0].reg << 12;
7924 inst.instruction |= inst.operands[2].reg << 16;
7927 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7928 which is not a multiple of four is UNPREDICTABLE. */
7930 check_ldr_r15_aligned (void)
7932 constraint (!(inst.operands[1].immisreg)
7933 && (inst.operands[0].reg == REG_PC
7934 && inst.operands[1].reg == REG_PC
7935 && (inst.reloc.exp.X_add_number & 0x3)),
7936 _("ldr to register 15 must be 4-byte alligned"));
7942 inst.instruction |= inst.operands[0].reg << 12;
7943 if (!inst.operands[1].isreg)
7944 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7946 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7947 check_ldr_r15_aligned ();
7953 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7955 if (inst.operands[1].preind)
7957 constraint (inst.reloc.exp.X_op != O_constant
7958 || inst.reloc.exp.X_add_number != 0,
7959 _("this instruction requires a post-indexed address"));
7961 inst.operands[1].preind = 0;
7962 inst.operands[1].postind = 1;
7963 inst.operands[1].writeback = 1;
7965 inst.instruction |= inst.operands[0].reg << 12;
7966 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7969 /* Halfword and signed-byte load/store operations. */
7974 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7975 inst.instruction |= inst.operands[0].reg << 12;
7976 if (!inst.operands[1].isreg)
7977 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7979 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7985 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7987 if (inst.operands[1].preind)
7989 constraint (inst.reloc.exp.X_op != O_constant
7990 || inst.reloc.exp.X_add_number != 0,
7991 _("this instruction requires a post-indexed address"));
7993 inst.operands[1].preind = 0;
7994 inst.operands[1].postind = 1;
7995 inst.operands[1].writeback = 1;
7997 inst.instruction |= inst.operands[0].reg << 12;
7998 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8001 /* Co-processor register load/store.
8002 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8006 inst.instruction |= inst.operands[0].reg << 8;
8007 inst.instruction |= inst.operands[1].reg << 12;
8008 encode_arm_cp_address (2, TRUE, TRUE, 0);
8014 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8015 if (inst.operands[0].reg == inst.operands[1].reg
8016 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8017 && !(inst.instruction & 0x00400000))
8018 as_tsktsk (_("Rd and Rm should be different in mla"));
8020 inst.instruction |= inst.operands[0].reg << 16;
8021 inst.instruction |= inst.operands[1].reg;
8022 inst.instruction |= inst.operands[2].reg << 8;
8023 inst.instruction |= inst.operands[3].reg << 12;
8029 inst.instruction |= inst.operands[0].reg << 12;
8030 encode_arm_shifter_operand (1);
8033 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8040 top = (inst.instruction & 0x00400000) != 0;
8041 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8042 _(":lower16: not allowed this instruction"));
8043 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8044 _(":upper16: not allowed instruction"));
8045 inst.instruction |= inst.operands[0].reg << 12;
8046 if (inst.reloc.type == BFD_RELOC_UNUSED)
8048 imm = inst.reloc.exp.X_add_number;
8049 /* The value is in two pieces: 0:11, 16:19. */
8050 inst.instruction |= (imm & 0x00000fff);
8051 inst.instruction |= (imm & 0x0000f000) << 4;
8055 static void do_vfp_nsyn_opcode (const char *);
8058 do_vfp_nsyn_mrs (void)
8060 if (inst.operands[0].isvec)
8062 if (inst.operands[1].reg != 1)
8063 first_error (_("operand 1 must be FPSCR"));
8064 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8065 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8066 do_vfp_nsyn_opcode ("fmstat");
8068 else if (inst.operands[1].isvec)
8069 do_vfp_nsyn_opcode ("fmrx");
8077 do_vfp_nsyn_msr (void)
8079 if (inst.operands[0].isvec)
8080 do_vfp_nsyn_opcode ("fmxr");
8090 unsigned Rt = inst.operands[0].reg;
8092 if (thumb_mode && inst.operands[0].reg == REG_SP)
8094 inst.error = BAD_SP;
8098 /* APSR_ sets isvec. All other refs to PC are illegal. */
8099 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8101 inst.error = BAD_PC;
8105 if (inst.operands[1].reg != 1)
8106 first_error (_("operand 1 must be FPSCR"));
8108 inst.instruction |= (Rt << 12);
8114 unsigned Rt = inst.operands[1].reg;
8117 reject_bad_reg (Rt);
8118 else if (Rt == REG_PC)
8120 inst.error = BAD_PC;
8124 if (inst.operands[0].reg != 1)
8125 first_error (_("operand 0 must be FPSCR"));
8127 inst.instruction |= (Rt << 12);
8135 if (do_vfp_nsyn_mrs () == SUCCESS)
8138 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8139 inst.instruction |= inst.operands[0].reg << 12;
8141 if (inst.operands[1].isreg)
8143 br = inst.operands[1].reg;
8144 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8145 as_bad (_("bad register for mrs"));
8149 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8150 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8152 _("'APSR', 'CPSR' or 'SPSR' expected"));
8153 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8156 inst.instruction |= br;
8159 /* Two possible forms:
8160 "{C|S}PSR_<field>, Rm",
8161 "{C|S}PSR_f, #expression". */
8166 if (do_vfp_nsyn_msr () == SUCCESS)
8169 inst.instruction |= inst.operands[0].imm;
8170 if (inst.operands[1].isreg)
8171 inst.instruction |= inst.operands[1].reg;
8174 inst.instruction |= INST_IMMEDIATE;
8175 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8176 inst.reloc.pc_rel = 0;
8183 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8185 if (!inst.operands[2].present)
8186 inst.operands[2].reg = inst.operands[0].reg;
8187 inst.instruction |= inst.operands[0].reg << 16;
8188 inst.instruction |= inst.operands[1].reg;
8189 inst.instruction |= inst.operands[2].reg << 8;
8191 if (inst.operands[0].reg == inst.operands[1].reg
8192 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8193 as_tsktsk (_("Rd and Rm should be different in mul"));
8196 /* Long Multiply Parser
8197 UMULL RdLo, RdHi, Rm, Rs
8198 SMULL RdLo, RdHi, Rm, Rs
8199 UMLAL RdLo, RdHi, Rm, Rs
8200 SMLAL RdLo, RdHi, Rm, Rs. */
8205 inst.instruction |= inst.operands[0].reg << 12;
8206 inst.instruction |= inst.operands[1].reg << 16;
8207 inst.instruction |= inst.operands[2].reg;
8208 inst.instruction |= inst.operands[3].reg << 8;
8210 /* rdhi and rdlo must be different. */
8211 if (inst.operands[0].reg == inst.operands[1].reg)
8212 as_tsktsk (_("rdhi and rdlo must be different"));
8214 /* rdhi, rdlo and rm must all be different before armv6. */
8215 if ((inst.operands[0].reg == inst.operands[2].reg
8216 || inst.operands[1].reg == inst.operands[2].reg)
8217 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8218 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8224 if (inst.operands[0].present
8225 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8227 /* Architectural NOP hints are CPSR sets with no bits selected. */
8228 inst.instruction &= 0xf0000000;
8229 inst.instruction |= 0x0320f000;
8230 if (inst.operands[0].present)
8231 inst.instruction |= inst.operands[0].imm;
8235 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8236 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8237 Condition defaults to COND_ALWAYS.
8238 Error if Rd, Rn or Rm are R15. */
8243 inst.instruction |= inst.operands[0].reg << 12;
8244 inst.instruction |= inst.operands[1].reg << 16;
8245 inst.instruction |= inst.operands[2].reg;
8246 if (inst.operands[3].present)
8247 encode_arm_shift (3);
8250 /* ARM V6 PKHTB (Argument Parse). */
8255 if (!inst.operands[3].present)
8257 /* If the shift specifier is omitted, turn the instruction
8258 into pkhbt rd, rm, rn. */
8259 inst.instruction &= 0xfff00010;
8260 inst.instruction |= inst.operands[0].reg << 12;
8261 inst.instruction |= inst.operands[1].reg;
8262 inst.instruction |= inst.operands[2].reg << 16;
8266 inst.instruction |= inst.operands[0].reg << 12;
8267 inst.instruction |= inst.operands[1].reg << 16;
8268 inst.instruction |= inst.operands[2].reg;
8269 encode_arm_shift (3);
8273 /* ARMv5TE: Preload-Cache
8274 MP Extensions: Preload for write
8278 Syntactically, like LDR with B=1, W=0, L=1. */
8283 constraint (!inst.operands[0].isreg,
8284 _("'[' expected after PLD mnemonic"));
8285 constraint (inst.operands[0].postind,
8286 _("post-indexed expression used in preload instruction"));
8287 constraint (inst.operands[0].writeback,
8288 _("writeback used in preload instruction"));
8289 constraint (!inst.operands[0].preind,
8290 _("unindexed addressing used in preload instruction"));
8291 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8294 /* ARMv7: PLI <addr_mode> */
8298 constraint (!inst.operands[0].isreg,
8299 _("'[' expected after PLI mnemonic"));
8300 constraint (inst.operands[0].postind,
8301 _("post-indexed expression used in preload instruction"));
8302 constraint (inst.operands[0].writeback,
8303 _("writeback used in preload instruction"));
8304 constraint (!inst.operands[0].preind,
8305 _("unindexed addressing used in preload instruction"));
8306 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8307 inst.instruction &= ~PRE_INDEX;
8313 inst.operands[1] = inst.operands[0];
8314 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8315 inst.operands[0].isreg = 1;
8316 inst.operands[0].writeback = 1;
8317 inst.operands[0].reg = REG_SP;
8321 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8322 word at the specified address and the following word
8324 Unconditionally executed.
8325 Error if Rn is R15. */
8330 inst.instruction |= inst.operands[0].reg << 16;
8331 if (inst.operands[0].writeback)
8332 inst.instruction |= WRITE_BACK;
8335 /* ARM V6 ssat (argument parse). */
8340 inst.instruction |= inst.operands[0].reg << 12;
8341 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8342 inst.instruction |= inst.operands[2].reg;
8344 if (inst.operands[3].present)
8345 encode_arm_shift (3);
8348 /* ARM V6 usat (argument parse). */
8353 inst.instruction |= inst.operands[0].reg << 12;
8354 inst.instruction |= inst.operands[1].imm << 16;
8355 inst.instruction |= inst.operands[2].reg;
8357 if (inst.operands[3].present)
8358 encode_arm_shift (3);
8361 /* ARM V6 ssat16 (argument parse). */
8366 inst.instruction |= inst.operands[0].reg << 12;
8367 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8368 inst.instruction |= inst.operands[2].reg;
8374 inst.instruction |= inst.operands[0].reg << 12;
8375 inst.instruction |= inst.operands[1].imm << 16;
8376 inst.instruction |= inst.operands[2].reg;
8379 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8380 preserving the other bits.
8382 setend <endian_specifier>, where <endian_specifier> is either
8388 if (inst.operands[0].imm)
8389 inst.instruction |= 0x200;
8395 unsigned int Rm = (inst.operands[1].present
8396 ? inst.operands[1].reg
8397 : inst.operands[0].reg);
8399 inst.instruction |= inst.operands[0].reg << 12;
8400 inst.instruction |= Rm;
8401 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8403 inst.instruction |= inst.operands[2].reg << 8;
8404 inst.instruction |= SHIFT_BY_REG;
8405 /* PR 12854: Error on extraneous shifts. */
8406 constraint (inst.operands[2].shifted,
8407 _("extraneous shift as part of operand to shift insn"));
8410 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8416 inst.reloc.type = BFD_RELOC_ARM_SMC;
8417 inst.reloc.pc_rel = 0;
8423 inst.reloc.type = BFD_RELOC_ARM_HVC;
8424 inst.reloc.pc_rel = 0;
8430 inst.reloc.type = BFD_RELOC_ARM_SWI;
8431 inst.reloc.pc_rel = 0;
8434 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8435 SMLAxy{cond} Rd,Rm,Rs,Rn
8436 SMLAWy{cond} Rd,Rm,Rs,Rn
8437 Error if any register is R15. */
8442 inst.instruction |= inst.operands[0].reg << 16;
8443 inst.instruction |= inst.operands[1].reg;
8444 inst.instruction |= inst.operands[2].reg << 8;
8445 inst.instruction |= inst.operands[3].reg << 12;
8448 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8449 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8450 Error if any register is R15.
8451 Warning if Rdlo == Rdhi. */
8456 inst.instruction |= inst.operands[0].reg << 12;
8457 inst.instruction |= inst.operands[1].reg << 16;
8458 inst.instruction |= inst.operands[2].reg;
8459 inst.instruction |= inst.operands[3].reg << 8;
8461 if (inst.operands[0].reg == inst.operands[1].reg)
8462 as_tsktsk (_("rdhi and rdlo must be different"));
8465 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8466 SMULxy{cond} Rd,Rm,Rs
8467 Error if any register is R15. */
8472 inst.instruction |= inst.operands[0].reg << 16;
8473 inst.instruction |= inst.operands[1].reg;
8474 inst.instruction |= inst.operands[2].reg << 8;
8477 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8478 the same for both ARM and Thumb-2. */
8485 if (inst.operands[0].present)
8487 reg = inst.operands[0].reg;
8488 constraint (reg != REG_SP, _("SRS base register must be r13"));
8493 inst.instruction |= reg << 16;
8494 inst.instruction |= inst.operands[1].imm;
8495 if (inst.operands[0].writeback || inst.operands[1].writeback)
8496 inst.instruction |= WRITE_BACK;
8499 /* ARM V6 strex (argument parse). */
8504 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8505 || inst.operands[2].postind || inst.operands[2].writeback
8506 || inst.operands[2].immisreg || inst.operands[2].shifted
8507 || inst.operands[2].negative
8508 /* See comment in do_ldrex(). */
8509 || (inst.operands[2].reg == REG_PC),
8512 constraint (inst.operands[0].reg == inst.operands[1].reg
8513 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8515 constraint (inst.reloc.exp.X_op != O_constant
8516 || inst.reloc.exp.X_add_number != 0,
8517 _("offset must be zero in ARM encoding"));
8519 inst.instruction |= inst.operands[0].reg << 12;
8520 inst.instruction |= inst.operands[1].reg;
8521 inst.instruction |= inst.operands[2].reg << 16;
8522 inst.reloc.type = BFD_RELOC_UNUSED;
8528 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8529 || inst.operands[2].postind || inst.operands[2].writeback
8530 || inst.operands[2].immisreg || inst.operands[2].shifted
8531 || inst.operands[2].negative,
8534 constraint (inst.operands[0].reg == inst.operands[1].reg
8535 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8543 constraint (inst.operands[1].reg % 2 != 0,
8544 _("even register required"));
8545 constraint (inst.operands[2].present
8546 && inst.operands[2].reg != inst.operands[1].reg + 1,
8547 _("can only store two consecutive registers"));
8548 /* If op 2 were present and equal to PC, this function wouldn't
8549 have been called in the first place. */
8550 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8552 constraint (inst.operands[0].reg == inst.operands[1].reg
8553 || inst.operands[0].reg == inst.operands[1].reg + 1
8554 || inst.operands[0].reg == inst.operands[3].reg,
8557 inst.instruction |= inst.operands[0].reg << 12;
8558 inst.instruction |= inst.operands[1].reg;
8559 inst.instruction |= inst.operands[3].reg << 16;
8562 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8563 extends it to 32-bits, and adds the result to a value in another
8564 register. You can specify a rotation by 0, 8, 16, or 24 bits
8565 before extracting the 16-bit value.
8566 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8567 Condition defaults to COND_ALWAYS.
8568 Error if any register uses R15. */
8573 inst.instruction |= inst.operands[0].reg << 12;
8574 inst.instruction |= inst.operands[1].reg << 16;
8575 inst.instruction |= inst.operands[2].reg;
8576 inst.instruction |= inst.operands[3].imm << 10;
8581 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8582 Condition defaults to COND_ALWAYS.
8583 Error if any register uses R15. */
8588 inst.instruction |= inst.operands[0].reg << 12;
8589 inst.instruction |= inst.operands[1].reg;
8590 inst.instruction |= inst.operands[2].imm << 10;
8593 /* VFP instructions. In a logical order: SP variant first, monad
8594 before dyad, arithmetic then move then load/store. */
8597 do_vfp_sp_monadic (void)
8599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8600 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8604 do_vfp_sp_dyadic (void)
8606 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8607 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8608 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8612 do_vfp_sp_compare_z (void)
8614 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8618 do_vfp_dp_sp_cvt (void)
8620 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8621 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8625 do_vfp_sp_dp_cvt (void)
8627 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8628 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8632 do_vfp_reg_from_sp (void)
8634 inst.instruction |= inst.operands[0].reg << 12;
8635 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8639 do_vfp_reg2_from_sp2 (void)
8641 constraint (inst.operands[2].imm != 2,
8642 _("only two consecutive VFP SP registers allowed here"));
8643 inst.instruction |= inst.operands[0].reg << 12;
8644 inst.instruction |= inst.operands[1].reg << 16;
8645 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8649 do_vfp_sp_from_reg (void)
8651 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8652 inst.instruction |= inst.operands[1].reg << 12;
8656 do_vfp_sp2_from_reg2 (void)
8658 constraint (inst.operands[0].imm != 2,
8659 _("only two consecutive VFP SP registers allowed here"));
8660 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8661 inst.instruction |= inst.operands[1].reg << 12;
8662 inst.instruction |= inst.operands[2].reg << 16;
8666 do_vfp_sp_ldst (void)
8668 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8669 encode_arm_cp_address (1, FALSE, TRUE, 0);
8673 do_vfp_dp_ldst (void)
8675 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8676 encode_arm_cp_address (1, FALSE, TRUE, 0);
8681 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8683 if (inst.operands[0].writeback)
8684 inst.instruction |= WRITE_BACK;
8686 constraint (ldstm_type != VFP_LDSTMIA,
8687 _("this addressing mode requires base-register writeback"));
8688 inst.instruction |= inst.operands[0].reg << 16;
8689 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8690 inst.instruction |= inst.operands[1].imm;
8694 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8698 if (inst.operands[0].writeback)
8699 inst.instruction |= WRITE_BACK;
8701 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8702 _("this addressing mode requires base-register writeback"));
8704 inst.instruction |= inst.operands[0].reg << 16;
8705 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8707 count = inst.operands[1].imm << 1;
8708 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8711 inst.instruction |= count;
8715 do_vfp_sp_ldstmia (void)
8717 vfp_sp_ldstm (VFP_LDSTMIA);
8721 do_vfp_sp_ldstmdb (void)
8723 vfp_sp_ldstm (VFP_LDSTMDB);
8727 do_vfp_dp_ldstmia (void)
8729 vfp_dp_ldstm (VFP_LDSTMIA);
8733 do_vfp_dp_ldstmdb (void)
8735 vfp_dp_ldstm (VFP_LDSTMDB);
8739 do_vfp_xp_ldstmia (void)
8741 vfp_dp_ldstm (VFP_LDSTMIAX);
8745 do_vfp_xp_ldstmdb (void)
8747 vfp_dp_ldstm (VFP_LDSTMDBX);
8751 do_vfp_dp_rd_rm (void)
8753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8754 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8758 do_vfp_dp_rn_rd (void)
8760 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8761 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8765 do_vfp_dp_rd_rn (void)
8767 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8768 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8772 do_vfp_dp_rd_rn_rm (void)
8774 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8775 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8776 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8786 do_vfp_dp_rm_rd_rn (void)
8788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8789 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8790 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8793 /* VFPv3 instructions. */
8795 do_vfp_sp_const (void)
8797 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8798 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8799 inst.instruction |= (inst.operands[1].imm & 0x0f);
8803 do_vfp_dp_const (void)
8805 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8806 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8807 inst.instruction |= (inst.operands[1].imm & 0x0f);
8811 vfp_conv (int srcsize)
8813 int immbits = srcsize - inst.operands[1].imm;
8815 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8817 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8818 i.e. immbits must be in range 0 - 16. */
8819 inst.error = _("immediate value out of range, expected range [0, 16]");
8822 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8824 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8825 i.e. immbits must be in range 0 - 31. */
8826 inst.error = _("immediate value out of range, expected range [1, 32]");
8830 inst.instruction |= (immbits & 1) << 5;
8831 inst.instruction |= (immbits >> 1);
8835 do_vfp_sp_conv_16 (void)
8837 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8842 do_vfp_dp_conv_16 (void)
8844 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8849 do_vfp_sp_conv_32 (void)
8851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8856 do_vfp_dp_conv_32 (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8862 /* FPA instructions. Also in a logical order. */
8867 inst.instruction |= inst.operands[0].reg << 16;
8868 inst.instruction |= inst.operands[1].reg;
8872 do_fpa_ldmstm (void)
8874 inst.instruction |= inst.operands[0].reg << 12;
8875 switch (inst.operands[1].imm)
8877 case 1: inst.instruction |= CP_T_X; break;
8878 case 2: inst.instruction |= CP_T_Y; break;
8879 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8884 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8886 /* The instruction specified "ea" or "fd", so we can only accept
8887 [Rn]{!}. The instruction does not really support stacking or
8888 unstacking, so we have to emulate these by setting appropriate
8889 bits and offsets. */
8890 constraint (inst.reloc.exp.X_op != O_constant
8891 || inst.reloc.exp.X_add_number != 0,
8892 _("this instruction does not support indexing"));
8894 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8895 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8897 if (!(inst.instruction & INDEX_UP))
8898 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8900 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8902 inst.operands[2].preind = 0;
8903 inst.operands[2].postind = 1;
8907 encode_arm_cp_address (2, TRUE, TRUE, 0);
8910 /* iWMMXt instructions: strictly in alphabetical order. */
8913 do_iwmmxt_tandorc (void)
8915 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8919 do_iwmmxt_textrc (void)
8921 inst.instruction |= inst.operands[0].reg << 12;
8922 inst.instruction |= inst.operands[1].imm;
8926 do_iwmmxt_textrm (void)
8928 inst.instruction |= inst.operands[0].reg << 12;
8929 inst.instruction |= inst.operands[1].reg << 16;
8930 inst.instruction |= inst.operands[2].imm;
8934 do_iwmmxt_tinsr (void)
8936 inst.instruction |= inst.operands[0].reg << 16;
8937 inst.instruction |= inst.operands[1].reg << 12;
8938 inst.instruction |= inst.operands[2].imm;
8942 do_iwmmxt_tmia (void)
8944 inst.instruction |= inst.operands[0].reg << 5;
8945 inst.instruction |= inst.operands[1].reg;
8946 inst.instruction |= inst.operands[2].reg << 12;
8950 do_iwmmxt_waligni (void)
8952 inst.instruction |= inst.operands[0].reg << 12;
8953 inst.instruction |= inst.operands[1].reg << 16;
8954 inst.instruction |= inst.operands[2].reg;
8955 inst.instruction |= inst.operands[3].imm << 20;
8959 do_iwmmxt_wmerge (void)
8961 inst.instruction |= inst.operands[0].reg << 12;
8962 inst.instruction |= inst.operands[1].reg << 16;
8963 inst.instruction |= inst.operands[2].reg;
8964 inst.instruction |= inst.operands[3].imm << 21;
8968 do_iwmmxt_wmov (void)
8970 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8971 inst.instruction |= inst.operands[0].reg << 12;
8972 inst.instruction |= inst.operands[1].reg << 16;
8973 inst.instruction |= inst.operands[1].reg;
8977 do_iwmmxt_wldstbh (void)
8980 inst.instruction |= inst.operands[0].reg << 12;
8982 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8984 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8985 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8989 do_iwmmxt_wldstw (void)
8991 /* RIWR_RIWC clears .isreg for a control register. */
8992 if (!inst.operands[0].isreg)
8994 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8995 inst.instruction |= 0xf0000000;
8998 inst.instruction |= inst.operands[0].reg << 12;
8999 encode_arm_cp_address (1, TRUE, TRUE, 0);
9003 do_iwmmxt_wldstd (void)
9005 inst.instruction |= inst.operands[0].reg << 12;
9006 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9007 && inst.operands[1].immisreg)
9009 inst.instruction &= ~0x1a000ff;
9010 inst.instruction |= (0xf << 28);
9011 if (inst.operands[1].preind)
9012 inst.instruction |= PRE_INDEX;
9013 if (!inst.operands[1].negative)
9014 inst.instruction |= INDEX_UP;
9015 if (inst.operands[1].writeback)
9016 inst.instruction |= WRITE_BACK;
9017 inst.instruction |= inst.operands[1].reg << 16;
9018 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9019 inst.instruction |= inst.operands[1].imm;
9022 encode_arm_cp_address (1, TRUE, FALSE, 0);
9026 do_iwmmxt_wshufh (void)
9028 inst.instruction |= inst.operands[0].reg << 12;
9029 inst.instruction |= inst.operands[1].reg << 16;
9030 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9031 inst.instruction |= (inst.operands[2].imm & 0x0f);
9035 do_iwmmxt_wzero (void)
9037 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9038 inst.instruction |= inst.operands[0].reg;
9039 inst.instruction |= inst.operands[0].reg << 12;
9040 inst.instruction |= inst.operands[0].reg << 16;
9044 do_iwmmxt_wrwrwr_or_imm5 (void)
9046 if (inst.operands[2].isreg)
9049 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9050 _("immediate operand requires iWMMXt2"));
9052 if (inst.operands[2].imm == 0)
9054 switch ((inst.instruction >> 20) & 0xf)
9060 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9061 inst.operands[2].imm = 16;
9062 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9068 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9069 inst.operands[2].imm = 32;
9070 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9077 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9079 wrn = (inst.instruction >> 16) & 0xf;
9080 inst.instruction &= 0xff0fff0f;
9081 inst.instruction |= wrn;
9082 /* Bail out here; the instruction is now assembled. */
9087 /* Map 32 -> 0, etc. */
9088 inst.operands[2].imm &= 0x1f;
9089 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9093 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9094 operations first, then control, shift, and load/store. */
9096 /* Insns like "foo X,Y,Z". */
9099 do_mav_triple (void)
9101 inst.instruction |= inst.operands[0].reg << 16;
9102 inst.instruction |= inst.operands[1].reg;
9103 inst.instruction |= inst.operands[2].reg << 12;
9106 /* Insns like "foo W,X,Y,Z".
9107 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9112 inst.instruction |= inst.operands[0].reg << 5;
9113 inst.instruction |= inst.operands[1].reg << 12;
9114 inst.instruction |= inst.operands[2].reg << 16;
9115 inst.instruction |= inst.operands[3].reg;
9118 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9122 inst.instruction |= inst.operands[1].reg << 12;
9125 /* Maverick shift immediate instructions.
9126 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9127 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9132 int imm = inst.operands[2].imm;
9134 inst.instruction |= inst.operands[0].reg << 12;
9135 inst.instruction |= inst.operands[1].reg << 16;
9137 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9138 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9139 Bit 4 should be 0. */
9140 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9142 inst.instruction |= imm;
9145 /* XScale instructions. Also sorted arithmetic before move. */
9147 /* Xscale multiply-accumulate (argument parse)
9150 MIAxycc acc0,Rm,Rs. */
9155 inst.instruction |= inst.operands[1].reg;
9156 inst.instruction |= inst.operands[2].reg << 12;
9159 /* Xscale move-accumulator-register (argument parse)
9161 MARcc acc0,RdLo,RdHi. */
9166 inst.instruction |= inst.operands[1].reg << 12;
9167 inst.instruction |= inst.operands[2].reg << 16;
9170 /* Xscale move-register-accumulator (argument parse)
9172 MRAcc RdLo,RdHi,acc0. */
9177 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9178 inst.instruction |= inst.operands[0].reg << 12;
9179 inst.instruction |= inst.operands[1].reg << 16;
9182 /* Encoding functions relevant only to Thumb. */
9184 /* inst.operands[i] is a shifted-register operand; encode
9185 it into inst.instruction in the format used by Thumb32. */
9188 encode_thumb32_shifted_operand (int i)
9190 unsigned int value = inst.reloc.exp.X_add_number;
9191 unsigned int shift = inst.operands[i].shift_kind;
9193 constraint (inst.operands[i].immisreg,
9194 _("shift by register not allowed in thumb mode"));
9195 inst.instruction |= inst.operands[i].reg;
9196 if (shift == SHIFT_RRX)
9197 inst.instruction |= SHIFT_ROR << 4;
9200 constraint (inst.reloc.exp.X_op != O_constant,
9201 _("expression too complex"));
9203 constraint (value > 32
9204 || (value == 32 && (shift == SHIFT_LSL
9205 || shift == SHIFT_ROR)),
9206 _("shift expression is too large"));
9210 else if (value == 32)
9213 inst.instruction |= shift << 4;
9214 inst.instruction |= (value & 0x1c) << 10;
9215 inst.instruction |= (value & 0x03) << 6;
9220 /* inst.operands[i] was set up by parse_address. Encode it into a
9221 Thumb32 format load or store instruction. Reject forms that cannot
9222 be used with such instructions. If is_t is true, reject forms that
9223 cannot be used with a T instruction; if is_d is true, reject forms
9224 that cannot be used with a D instruction. If it is a store insn,
9228 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9230 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9232 constraint (!inst.operands[i].isreg,
9233 _("Instruction does not support =N addresses"));
9235 inst.instruction |= inst.operands[i].reg << 16;
9236 if (inst.operands[i].immisreg)
9238 constraint (is_pc, BAD_PC_ADDRESSING);
9239 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9240 constraint (inst.operands[i].negative,
9241 _("Thumb does not support negative register indexing"));
9242 constraint (inst.operands[i].postind,
9243 _("Thumb does not support register post-indexing"));
9244 constraint (inst.operands[i].writeback,
9245 _("Thumb does not support register indexing with writeback"));
9246 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9247 _("Thumb supports only LSL in shifted register indexing"));
9249 inst.instruction |= inst.operands[i].imm;
9250 if (inst.operands[i].shifted)
9252 constraint (inst.reloc.exp.X_op != O_constant,
9253 _("expression too complex"));
9254 constraint (inst.reloc.exp.X_add_number < 0
9255 || inst.reloc.exp.X_add_number > 3,
9256 _("shift out of range"));
9257 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9259 inst.reloc.type = BFD_RELOC_UNUSED;
9261 else if (inst.operands[i].preind)
9263 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9264 constraint (is_t && inst.operands[i].writeback,
9265 _("cannot use writeback with this instruction"));
9266 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9267 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9271 inst.instruction |= 0x01000000;
9272 if (inst.operands[i].writeback)
9273 inst.instruction |= 0x00200000;
9277 inst.instruction |= 0x00000c00;
9278 if (inst.operands[i].writeback)
9279 inst.instruction |= 0x00000100;
9281 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9283 else if (inst.operands[i].postind)
9285 gas_assert (inst.operands[i].writeback);
9286 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9287 constraint (is_t, _("cannot use post-indexing with this instruction"));
9290 inst.instruction |= 0x00200000;
9292 inst.instruction |= 0x00000900;
9293 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9295 else /* unindexed - only for coprocessor */
9296 inst.error = _("instruction does not accept unindexed addressing");
9299 /* Table of Thumb instructions which exist in both 16- and 32-bit
9300 encodings (the latter only in post-V6T2 cores). The index is the
9301 value used in the insns table below. When there is more than one
9302 possible 16-bit encoding for the instruction, this table always
9304 Also contains several pseudo-instructions used during relaxation. */
9305 #define T16_32_TAB \
9306 X(_adc, 4140, eb400000), \
9307 X(_adcs, 4140, eb500000), \
9308 X(_add, 1c00, eb000000), \
9309 X(_adds, 1c00, eb100000), \
9310 X(_addi, 0000, f1000000), \
9311 X(_addis, 0000, f1100000), \
9312 X(_add_pc,000f, f20f0000), \
9313 X(_add_sp,000d, f10d0000), \
9314 X(_adr, 000f, f20f0000), \
9315 X(_and, 4000, ea000000), \
9316 X(_ands, 4000, ea100000), \
9317 X(_asr, 1000, fa40f000), \
9318 X(_asrs, 1000, fa50f000), \
9319 X(_b, e000, f000b000), \
9320 X(_bcond, d000, f0008000), \
9321 X(_bic, 4380, ea200000), \
9322 X(_bics, 4380, ea300000), \
9323 X(_cmn, 42c0, eb100f00), \
9324 X(_cmp, 2800, ebb00f00), \
9325 X(_cpsie, b660, f3af8400), \
9326 X(_cpsid, b670, f3af8600), \
9327 X(_cpy, 4600, ea4f0000), \
9328 X(_dec_sp,80dd, f1ad0d00), \
9329 X(_eor, 4040, ea800000), \
9330 X(_eors, 4040, ea900000), \
9331 X(_inc_sp,00dd, f10d0d00), \
9332 X(_ldmia, c800, e8900000), \
9333 X(_ldr, 6800, f8500000), \
9334 X(_ldrb, 7800, f8100000), \
9335 X(_ldrh, 8800, f8300000), \
9336 X(_ldrsb, 5600, f9100000), \
9337 X(_ldrsh, 5e00, f9300000), \
9338 X(_ldr_pc,4800, f85f0000), \
9339 X(_ldr_pc2,4800, f85f0000), \
9340 X(_ldr_sp,9800, f85d0000), \
9341 X(_lsl, 0000, fa00f000), \
9342 X(_lsls, 0000, fa10f000), \
9343 X(_lsr, 0800, fa20f000), \
9344 X(_lsrs, 0800, fa30f000), \
9345 X(_mov, 2000, ea4f0000), \
9346 X(_movs, 2000, ea5f0000), \
9347 X(_mul, 4340, fb00f000), \
9348 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9349 X(_mvn, 43c0, ea6f0000), \
9350 X(_mvns, 43c0, ea7f0000), \
9351 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9352 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9353 X(_orr, 4300, ea400000), \
9354 X(_orrs, 4300, ea500000), \
9355 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9356 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9357 X(_rev, ba00, fa90f080), \
9358 X(_rev16, ba40, fa90f090), \
9359 X(_revsh, bac0, fa90f0b0), \
9360 X(_ror, 41c0, fa60f000), \
9361 X(_rors, 41c0, fa70f000), \
9362 X(_sbc, 4180, eb600000), \
9363 X(_sbcs, 4180, eb700000), \
9364 X(_stmia, c000, e8800000), \
9365 X(_str, 6000, f8400000), \
9366 X(_strb, 7000, f8000000), \
9367 X(_strh, 8000, f8200000), \
9368 X(_str_sp,9000, f84d0000), \
9369 X(_sub, 1e00, eba00000), \
9370 X(_subs, 1e00, ebb00000), \
9371 X(_subi, 8000, f1a00000), \
9372 X(_subis, 8000, f1b00000), \
9373 X(_sxtb, b240, fa4ff080), \
9374 X(_sxth, b200, fa0ff080), \
9375 X(_tst, 4200, ea100f00), \
9376 X(_uxtb, b2c0, fa5ff080), \
9377 X(_uxth, b280, fa1ff080), \
9378 X(_nop, bf00, f3af8000), \
9379 X(_yield, bf10, f3af8001), \
9380 X(_wfe, bf20, f3af8002), \
9381 X(_wfi, bf30, f3af8003), \
9382 X(_sev, bf40, f3af8004),
9384 /* To catch errors in encoding functions, the codes are all offset by
9385 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9386 as 16-bit instructions. */
9387 #define X(a,b,c) T_MNEM##a
9388 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9391 #define X(a,b,c) 0x##b
9392 static const unsigned short thumb_op16[] = { T16_32_TAB };
9393 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9396 #define X(a,b,c) 0x##c
9397 static const unsigned int thumb_op32[] = { T16_32_TAB };
9398 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9399 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9403 /* Thumb instruction encoders, in alphabetical order. */
9408 do_t_add_sub_w (void)
9412 Rd = inst.operands[0].reg;
9413 Rn = inst.operands[1].reg;
9415 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9416 is the SP-{plus,minus}-immediate form of the instruction. */
9418 constraint (Rd == REG_PC, BAD_PC);
9420 reject_bad_reg (Rd);
9422 inst.instruction |= (Rn << 16) | (Rd << 8);
9423 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9426 /* Parse an add or subtract instruction. We get here with inst.instruction
9427 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9434 Rd = inst.operands[0].reg;
9435 Rs = (inst.operands[1].present
9436 ? inst.operands[1].reg /* Rd, Rs, foo */
9437 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9440 set_it_insn_type_last ();
9448 flags = (inst.instruction == T_MNEM_adds
9449 || inst.instruction == T_MNEM_subs);
9451 narrow = !in_it_block ();
9453 narrow = in_it_block ();
9454 if (!inst.operands[2].isreg)
9458 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9460 add = (inst.instruction == T_MNEM_add
9461 || inst.instruction == T_MNEM_adds);
9463 if (inst.size_req != 4)
9465 /* Attempt to use a narrow opcode, with relaxation if
9467 if (Rd == REG_SP && Rs == REG_SP && !flags)
9468 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9469 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9470 opcode = T_MNEM_add_sp;
9471 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9472 opcode = T_MNEM_add_pc;
9473 else if (Rd <= 7 && Rs <= 7 && narrow)
9476 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9478 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9482 inst.instruction = THUMB_OP16(opcode);
9483 inst.instruction |= (Rd << 4) | Rs;
9484 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9485 if (inst.size_req != 2)
9486 inst.relax = opcode;
9489 constraint (inst.size_req == 2, BAD_HIREG);
9491 if (inst.size_req == 4
9492 || (inst.size_req != 2 && !opcode))
9496 constraint (add, BAD_PC);
9497 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9498 _("only SUBS PC, LR, #const allowed"));
9499 constraint (inst.reloc.exp.X_op != O_constant,
9500 _("expression too complex"));
9501 constraint (inst.reloc.exp.X_add_number < 0
9502 || inst.reloc.exp.X_add_number > 0xff,
9503 _("immediate value out of range"));
9504 inst.instruction = T2_SUBS_PC_LR
9505 | inst.reloc.exp.X_add_number;
9506 inst.reloc.type = BFD_RELOC_UNUSED;
9509 else if (Rs == REG_PC)
9511 /* Always use addw/subw. */
9512 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9513 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9517 inst.instruction = THUMB_OP32 (inst.instruction);
9518 inst.instruction = (inst.instruction & 0xe1ffffff)
9521 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9523 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9525 inst.instruction |= Rd << 8;
9526 inst.instruction |= Rs << 16;
9531 unsigned int value = inst.reloc.exp.X_add_number;
9532 unsigned int shift = inst.operands[2].shift_kind;
9534 Rn = inst.operands[2].reg;
9535 /* See if we can do this with a 16-bit instruction. */
9536 if (!inst.operands[2].shifted && inst.size_req != 4)
9538 if (Rd > 7 || Rs > 7 || Rn > 7)
9543 inst.instruction = ((inst.instruction == T_MNEM_adds
9544 || inst.instruction == T_MNEM_add)
9547 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9551 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9553 /* Thumb-1 cores (except v6-M) require at least one high
9554 register in a narrow non flag setting add. */
9555 if (Rd > 7 || Rn > 7
9556 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9557 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9564 inst.instruction = T_OPCODE_ADD_HI;
9565 inst.instruction |= (Rd & 8) << 4;
9566 inst.instruction |= (Rd & 7);
9567 inst.instruction |= Rn << 3;
9573 constraint (Rd == REG_PC, BAD_PC);
9574 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9575 constraint (Rs == REG_PC, BAD_PC);
9576 reject_bad_reg (Rn);
9578 /* If we get here, it can't be done in 16 bits. */
9579 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9580 _("shift must be constant"));
9581 inst.instruction = THUMB_OP32 (inst.instruction);
9582 inst.instruction |= Rd << 8;
9583 inst.instruction |= Rs << 16;
9584 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9585 _("shift value over 3 not allowed in thumb mode"));
9586 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9587 _("only LSL shift allowed in thumb mode"));
9588 encode_thumb32_shifted_operand (2);
9593 constraint (inst.instruction == T_MNEM_adds
9594 || inst.instruction == T_MNEM_subs,
9597 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9599 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9600 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9603 inst.instruction = (inst.instruction == T_MNEM_add
9605 inst.instruction |= (Rd << 4) | Rs;
9606 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9610 Rn = inst.operands[2].reg;
9611 constraint (inst.operands[2].shifted, _("unshifted register required"));
9613 /* We now have Rd, Rs, and Rn set to registers. */
9614 if (Rd > 7 || Rs > 7 || Rn > 7)
9616 /* Can't do this for SUB. */
9617 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9618 inst.instruction = T_OPCODE_ADD_HI;
9619 inst.instruction |= (Rd & 8) << 4;
9620 inst.instruction |= (Rd & 7);
9622 inst.instruction |= Rn << 3;
9624 inst.instruction |= Rs << 3;
9626 constraint (1, _("dest must overlap one source register"));
9630 inst.instruction = (inst.instruction == T_MNEM_add
9631 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9632 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9642 Rd = inst.operands[0].reg;
9643 reject_bad_reg (Rd);
9645 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9647 /* Defer to section relaxation. */
9648 inst.relax = inst.instruction;
9649 inst.instruction = THUMB_OP16 (inst.instruction);
9650 inst.instruction |= Rd << 4;
9652 else if (unified_syntax && inst.size_req != 2)
9654 /* Generate a 32-bit opcode. */
9655 inst.instruction = THUMB_OP32 (inst.instruction);
9656 inst.instruction |= Rd << 8;
9657 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9658 inst.reloc.pc_rel = 1;
9662 /* Generate a 16-bit opcode. */
9663 inst.instruction = THUMB_OP16 (inst.instruction);
9664 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9665 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9666 inst.reloc.pc_rel = 1;
9668 inst.instruction |= Rd << 4;
9672 /* Arithmetic instructions for which there is just one 16-bit
9673 instruction encoding, and it allows only two low registers.
9674 For maximal compatibility with ARM syntax, we allow three register
9675 operands even when Thumb-32 instructions are not available, as long
9676 as the first two are identical. For instance, both "sbc r0,r1" and
9677 "sbc r0,r0,r1" are allowed. */
9683 Rd = inst.operands[0].reg;
9684 Rs = (inst.operands[1].present
9685 ? inst.operands[1].reg /* Rd, Rs, foo */
9686 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9687 Rn = inst.operands[2].reg;
9689 reject_bad_reg (Rd);
9690 reject_bad_reg (Rs);
9691 if (inst.operands[2].isreg)
9692 reject_bad_reg (Rn);
9696 if (!inst.operands[2].isreg)
9698 /* For an immediate, we always generate a 32-bit opcode;
9699 section relaxation will shrink it later if possible. */
9700 inst.instruction = THUMB_OP32 (inst.instruction);
9701 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9702 inst.instruction |= Rd << 8;
9703 inst.instruction |= Rs << 16;
9704 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9710 /* See if we can do this with a 16-bit instruction. */
9711 if (THUMB_SETS_FLAGS (inst.instruction))
9712 narrow = !in_it_block ();
9714 narrow = in_it_block ();
9716 if (Rd > 7 || Rn > 7 || Rs > 7)
9718 if (inst.operands[2].shifted)
9720 if (inst.size_req == 4)
9726 inst.instruction = THUMB_OP16 (inst.instruction);
9727 inst.instruction |= Rd;
9728 inst.instruction |= Rn << 3;
9732 /* If we get here, it can't be done in 16 bits. */
9733 constraint (inst.operands[2].shifted
9734 && inst.operands[2].immisreg,
9735 _("shift must be constant"));
9736 inst.instruction = THUMB_OP32 (inst.instruction);
9737 inst.instruction |= Rd << 8;
9738 inst.instruction |= Rs << 16;
9739 encode_thumb32_shifted_operand (2);
9744 /* On its face this is a lie - the instruction does set the
9745 flags. However, the only supported mnemonic in this mode
9747 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9749 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9750 _("unshifted register required"));
9751 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9752 constraint (Rd != Rs,
9753 _("dest and source1 must be the same register"));
9755 inst.instruction = THUMB_OP16 (inst.instruction);
9756 inst.instruction |= Rd;
9757 inst.instruction |= Rn << 3;
9761 /* Similarly, but for instructions where the arithmetic operation is
9762 commutative, so we can allow either of them to be different from
9763 the destination operand in a 16-bit instruction. For instance, all
9764 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9771 Rd = inst.operands[0].reg;
9772 Rs = (inst.operands[1].present
9773 ? inst.operands[1].reg /* Rd, Rs, foo */
9774 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9775 Rn = inst.operands[2].reg;
9777 reject_bad_reg (Rd);
9778 reject_bad_reg (Rs);
9779 if (inst.operands[2].isreg)
9780 reject_bad_reg (Rn);
9784 if (!inst.operands[2].isreg)
9786 /* For an immediate, we always generate a 32-bit opcode;
9787 section relaxation will shrink it later if possible. */
9788 inst.instruction = THUMB_OP32 (inst.instruction);
9789 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9790 inst.instruction |= Rd << 8;
9791 inst.instruction |= Rs << 16;
9792 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9798 /* See if we can do this with a 16-bit instruction. */
9799 if (THUMB_SETS_FLAGS (inst.instruction))
9800 narrow = !in_it_block ();
9802 narrow = in_it_block ();
9804 if (Rd > 7 || Rn > 7 || Rs > 7)
9806 if (inst.operands[2].shifted)
9808 if (inst.size_req == 4)
9815 inst.instruction = THUMB_OP16 (inst.instruction);
9816 inst.instruction |= Rd;
9817 inst.instruction |= Rn << 3;
9822 inst.instruction = THUMB_OP16 (inst.instruction);
9823 inst.instruction |= Rd;
9824 inst.instruction |= Rs << 3;
9829 /* If we get here, it can't be done in 16 bits. */
9830 constraint (inst.operands[2].shifted
9831 && inst.operands[2].immisreg,
9832 _("shift must be constant"));
9833 inst.instruction = THUMB_OP32 (inst.instruction);
9834 inst.instruction |= Rd << 8;
9835 inst.instruction |= Rs << 16;
9836 encode_thumb32_shifted_operand (2);
9841 /* On its face this is a lie - the instruction does set the
9842 flags. However, the only supported mnemonic in this mode
9844 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9846 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9847 _("unshifted register required"));
9848 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9850 inst.instruction = THUMB_OP16 (inst.instruction);
9851 inst.instruction |= Rd;
9854 inst.instruction |= Rn << 3;
9856 inst.instruction |= Rs << 3;
9858 constraint (1, _("dest must overlap one source register"));
9865 if (inst.operands[0].present)
9867 constraint ((inst.instruction & 0xf0) != 0x40
9868 && inst.operands[0].imm > 0xf
9869 && inst.operands[0].imm < 0x0,
9870 _("bad barrier type"));
9871 inst.instruction |= inst.operands[0].imm;
9874 inst.instruction |= 0xf;
9881 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9882 constraint (msb > 32, _("bit-field extends past end of register"));
9883 /* The instruction encoding stores the LSB and MSB,
9884 not the LSB and width. */
9885 Rd = inst.operands[0].reg;
9886 reject_bad_reg (Rd);
9887 inst.instruction |= Rd << 8;
9888 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9889 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9890 inst.instruction |= msb - 1;
9899 Rd = inst.operands[0].reg;
9900 reject_bad_reg (Rd);
9902 /* #0 in second position is alternative syntax for bfc, which is
9903 the same instruction but with REG_PC in the Rm field. */
9904 if (!inst.operands[1].isreg)
9908 Rn = inst.operands[1].reg;
9909 reject_bad_reg (Rn);
9912 msb = inst.operands[2].imm + inst.operands[3].imm;
9913 constraint (msb > 32, _("bit-field extends past end of register"));
9914 /* The instruction encoding stores the LSB and MSB,
9915 not the LSB and width. */
9916 inst.instruction |= Rd << 8;
9917 inst.instruction |= Rn << 16;
9918 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9919 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9920 inst.instruction |= msb - 1;
9928 Rd = inst.operands[0].reg;
9929 Rn = inst.operands[1].reg;
9931 reject_bad_reg (Rd);
9932 reject_bad_reg (Rn);
9934 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9935 _("bit-field extends past end of register"));
9936 inst.instruction |= Rd << 8;
9937 inst.instruction |= Rn << 16;
9938 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9939 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9940 inst.instruction |= inst.operands[3].imm - 1;
9943 /* ARM V5 Thumb BLX (argument parse)
9944 BLX <target_addr> which is BLX(1)
9945 BLX <Rm> which is BLX(2)
9946 Unfortunately, there are two different opcodes for this mnemonic.
9947 So, the insns[].value is not used, and the code here zaps values
9948 into inst.instruction.
9950 ??? How to take advantage of the additional two bits of displacement
9951 available in Thumb32 mode? Need new relocation? */
9956 set_it_insn_type_last ();
9958 if (inst.operands[0].isreg)
9960 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9961 /* We have a register, so this is BLX(2). */
9962 inst.instruction |= inst.operands[0].reg << 3;
9966 /* No register. This must be BLX(1). */
9967 inst.instruction = 0xf000e800;
9968 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9980 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9984 /* Conditional branches inside IT blocks are encoded as unconditional
9991 if (cond != COND_ALWAYS)
9992 opcode = T_MNEM_bcond;
9994 opcode = inst.instruction;
9997 && (inst.size_req == 4
9998 || (inst.size_req != 2
9999 && (inst.operands[0].hasreloc
10000 || inst.reloc.exp.X_op == O_constant))))
10002 inst.instruction = THUMB_OP32(opcode);
10003 if (cond == COND_ALWAYS)
10004 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10007 gas_assert (cond != 0xF);
10008 inst.instruction |= cond << 22;
10009 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10014 inst.instruction = THUMB_OP16(opcode);
10015 if (cond == COND_ALWAYS)
10016 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10019 inst.instruction |= cond << 8;
10020 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10022 /* Allow section relaxation. */
10023 if (unified_syntax && inst.size_req != 2)
10024 inst.relax = opcode;
10026 inst.reloc.type = reloc;
10027 inst.reloc.pc_rel = 1;
10033 constraint (inst.cond != COND_ALWAYS,
10034 _("instruction is always unconditional"));
10035 if (inst.operands[0].present)
10037 constraint (inst.operands[0].imm > 255,
10038 _("immediate value out of range"));
10039 inst.instruction |= inst.operands[0].imm;
10040 set_it_insn_type (NEUTRAL_IT_INSN);
10045 do_t_branch23 (void)
10047 set_it_insn_type_last ();
10048 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10050 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10051 this file. We used to simply ignore the PLT reloc type here --
10052 the branch encoding is now needed to deal with TLSCALL relocs.
10053 So if we see a PLT reloc now, put it back to how it used to be to
10054 keep the preexisting behaviour. */
10055 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10056 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10058 #if defined(OBJ_COFF)
10059 /* If the destination of the branch is a defined symbol which does not have
10060 the THUMB_FUNC attribute, then we must be calling a function which has
10061 the (interfacearm) attribute. We look for the Thumb entry point to that
10062 function and change the branch to refer to that function instead. */
10063 if ( inst.reloc.exp.X_op == O_symbol
10064 && inst.reloc.exp.X_add_symbol != NULL
10065 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10066 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10067 inst.reloc.exp.X_add_symbol =
10068 find_real_start (inst.reloc.exp.X_add_symbol);
10075 set_it_insn_type_last ();
10076 inst.instruction |= inst.operands[0].reg << 3;
10077 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10078 should cause the alignment to be checked once it is known. This is
10079 because BX PC only works if the instruction is word aligned. */
10087 set_it_insn_type_last ();
10088 Rm = inst.operands[0].reg;
10089 reject_bad_reg (Rm);
10090 inst.instruction |= Rm << 16;
10099 Rd = inst.operands[0].reg;
10100 Rm = inst.operands[1].reg;
10102 reject_bad_reg (Rd);
10103 reject_bad_reg (Rm);
10105 inst.instruction |= Rd << 8;
10106 inst.instruction |= Rm << 16;
10107 inst.instruction |= Rm;
10113 set_it_insn_type (OUTSIDE_IT_INSN);
10114 inst.instruction |= inst.operands[0].imm;
10120 set_it_insn_type (OUTSIDE_IT_INSN);
10122 && (inst.operands[1].present || inst.size_req == 4)
10123 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10125 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10126 inst.instruction = 0xf3af8000;
10127 inst.instruction |= imod << 9;
10128 inst.instruction |= inst.operands[0].imm << 5;
10129 if (inst.operands[1].present)
10130 inst.instruction |= 0x100 | inst.operands[1].imm;
10134 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10135 && (inst.operands[0].imm & 4),
10136 _("selected processor does not support 'A' form "
10137 "of this instruction"));
10138 constraint (inst.operands[1].present || inst.size_req == 4,
10139 _("Thumb does not support the 2-argument "
10140 "form of this instruction"));
10141 inst.instruction |= inst.operands[0].imm;
10145 /* THUMB CPY instruction (argument parse). */
10150 if (inst.size_req == 4)
10152 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10153 inst.instruction |= inst.operands[0].reg << 8;
10154 inst.instruction |= inst.operands[1].reg;
10158 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10159 inst.instruction |= (inst.operands[0].reg & 0x7);
10160 inst.instruction |= inst.operands[1].reg << 3;
10167 set_it_insn_type (OUTSIDE_IT_INSN);
10168 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10169 inst.instruction |= inst.operands[0].reg;
10170 inst.reloc.pc_rel = 1;
10171 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10177 inst.instruction |= inst.operands[0].imm;
10183 unsigned Rd, Rn, Rm;
10185 Rd = inst.operands[0].reg;
10186 Rn = (inst.operands[1].present
10187 ? inst.operands[1].reg : Rd);
10188 Rm = inst.operands[2].reg;
10190 reject_bad_reg (Rd);
10191 reject_bad_reg (Rn);
10192 reject_bad_reg (Rm);
10194 inst.instruction |= Rd << 8;
10195 inst.instruction |= Rn << 16;
10196 inst.instruction |= Rm;
10202 if (unified_syntax && inst.size_req == 4)
10203 inst.instruction = THUMB_OP32 (inst.instruction);
10205 inst.instruction = THUMB_OP16 (inst.instruction);
10211 unsigned int cond = inst.operands[0].imm;
10213 set_it_insn_type (IT_INSN);
10214 now_it.mask = (inst.instruction & 0xf) | 0x10;
10217 /* If the condition is a negative condition, invert the mask. */
10218 if ((cond & 0x1) == 0x0)
10220 unsigned int mask = inst.instruction & 0x000f;
10222 if ((mask & 0x7) == 0)
10223 /* no conversion needed */;
10224 else if ((mask & 0x3) == 0)
10226 else if ((mask & 0x1) == 0)
10231 inst.instruction &= 0xfff0;
10232 inst.instruction |= mask;
10235 inst.instruction |= cond << 4;
10238 /* Helper function used for both push/pop and ldm/stm. */
10240 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10244 load = (inst.instruction & (1 << 20)) != 0;
10246 if (mask & (1 << 13))
10247 inst.error = _("SP not allowed in register list");
10249 if ((mask & (1 << base)) != 0
10251 inst.error = _("having the base register in the register list when "
10252 "using write back is UNPREDICTABLE");
10256 if (mask & (1 << 15))
10258 if (mask & (1 << 14))
10259 inst.error = _("LR and PC should not both be in register list");
10261 set_it_insn_type_last ();
10266 if (mask & (1 << 15))
10267 inst.error = _("PC not allowed in register list");
10270 if ((mask & (mask - 1)) == 0)
10272 /* Single register transfers implemented as str/ldr. */
10275 if (inst.instruction & (1 << 23))
10276 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10278 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10282 if (inst.instruction & (1 << 23))
10283 inst.instruction = 0x00800000; /* ia -> [base] */
10285 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10288 inst.instruction |= 0xf8400000;
10290 inst.instruction |= 0x00100000;
10292 mask = ffs (mask) - 1;
10295 else if (writeback)
10296 inst.instruction |= WRITE_BACK;
10298 inst.instruction |= mask;
10299 inst.instruction |= base << 16;
10305 /* This really doesn't seem worth it. */
10306 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10307 _("expression too complex"));
10308 constraint (inst.operands[1].writeback,
10309 _("Thumb load/store multiple does not support {reglist}^"));
10311 if (unified_syntax)
10313 bfd_boolean narrow;
10317 /* See if we can use a 16-bit instruction. */
10318 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10319 && inst.size_req != 4
10320 && !(inst.operands[1].imm & ~0xff))
10322 mask = 1 << inst.operands[0].reg;
10324 if (inst.operands[0].reg <= 7)
10326 if (inst.instruction == T_MNEM_stmia
10327 ? inst.operands[0].writeback
10328 : (inst.operands[0].writeback
10329 == !(inst.operands[1].imm & mask)))
10331 if (inst.instruction == T_MNEM_stmia
10332 && (inst.operands[1].imm & mask)
10333 && (inst.operands[1].imm & (mask - 1)))
10334 as_warn (_("value stored for r%d is UNKNOWN"),
10335 inst.operands[0].reg);
10337 inst.instruction = THUMB_OP16 (inst.instruction);
10338 inst.instruction |= inst.operands[0].reg << 8;
10339 inst.instruction |= inst.operands[1].imm;
10342 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10344 /* This means 1 register in reg list one of 3 situations:
10345 1. Instruction is stmia, but without writeback.
10346 2. lmdia without writeback, but with Rn not in
10348 3. ldmia with writeback, but with Rn in reglist.
10349 Case 3 is UNPREDICTABLE behaviour, so we handle
10350 case 1 and 2 which can be converted into a 16-bit
10351 str or ldr. The SP cases are handled below. */
10352 unsigned long opcode;
10353 /* First, record an error for Case 3. */
10354 if (inst.operands[1].imm & mask
10355 && inst.operands[0].writeback)
10357 _("having the base register in the register list when "
10358 "using write back is UNPREDICTABLE");
10360 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10362 inst.instruction = THUMB_OP16 (opcode);
10363 inst.instruction |= inst.operands[0].reg << 3;
10364 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10368 else if (inst.operands[0] .reg == REG_SP)
10370 if (inst.operands[0].writeback)
10373 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10374 ? T_MNEM_push : T_MNEM_pop);
10375 inst.instruction |= inst.operands[1].imm;
10378 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10381 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10382 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10383 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10391 if (inst.instruction < 0xffff)
10392 inst.instruction = THUMB_OP32 (inst.instruction);
10394 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10395 inst.operands[0].writeback);
10400 constraint (inst.operands[0].reg > 7
10401 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10402 constraint (inst.instruction != T_MNEM_ldmia
10403 && inst.instruction != T_MNEM_stmia,
10404 _("Thumb-2 instruction only valid in unified syntax"));
10405 if (inst.instruction == T_MNEM_stmia)
10407 if (!inst.operands[0].writeback)
10408 as_warn (_("this instruction will write back the base register"));
10409 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10410 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10411 as_warn (_("value stored for r%d is UNKNOWN"),
10412 inst.operands[0].reg);
10416 if (!inst.operands[0].writeback
10417 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10418 as_warn (_("this instruction will write back the base register"));
10419 else if (inst.operands[0].writeback
10420 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10421 as_warn (_("this instruction will not write back the base register"));
10424 inst.instruction = THUMB_OP16 (inst.instruction);
10425 inst.instruction |= inst.operands[0].reg << 8;
10426 inst.instruction |= inst.operands[1].imm;
10433 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10434 || inst.operands[1].postind || inst.operands[1].writeback
10435 || inst.operands[1].immisreg || inst.operands[1].shifted
10436 || inst.operands[1].negative,
10439 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10441 inst.instruction |= inst.operands[0].reg << 12;
10442 inst.instruction |= inst.operands[1].reg << 16;
10443 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10449 if (!inst.operands[1].present)
10451 constraint (inst.operands[0].reg == REG_LR,
10452 _("r14 not allowed as first register "
10453 "when second register is omitted"));
10454 inst.operands[1].reg = inst.operands[0].reg + 1;
10456 constraint (inst.operands[0].reg == inst.operands[1].reg,
10459 inst.instruction |= inst.operands[0].reg << 12;
10460 inst.instruction |= inst.operands[1].reg << 8;
10461 inst.instruction |= inst.operands[2].reg << 16;
10467 unsigned long opcode;
10470 if (inst.operands[0].isreg
10471 && !inst.operands[0].preind
10472 && inst.operands[0].reg == REG_PC)
10473 set_it_insn_type_last ();
10475 opcode = inst.instruction;
10476 if (unified_syntax)
10478 if (!inst.operands[1].isreg)
10480 if (opcode <= 0xffff)
10481 inst.instruction = THUMB_OP32 (opcode);
10482 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10485 if (inst.operands[1].isreg
10486 && !inst.operands[1].writeback
10487 && !inst.operands[1].shifted && !inst.operands[1].postind
10488 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10489 && opcode <= 0xffff
10490 && inst.size_req != 4)
10492 /* Insn may have a 16-bit form. */
10493 Rn = inst.operands[1].reg;
10494 if (inst.operands[1].immisreg)
10496 inst.instruction = THUMB_OP16 (opcode);
10498 if (Rn <= 7 && inst.operands[1].imm <= 7)
10500 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10501 reject_bad_reg (inst.operands[1].imm);
10503 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10504 && opcode != T_MNEM_ldrsb)
10505 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10506 || (Rn == REG_SP && opcode == T_MNEM_str))
10513 if (inst.reloc.pc_rel)
10514 opcode = T_MNEM_ldr_pc2;
10516 opcode = T_MNEM_ldr_pc;
10520 if (opcode == T_MNEM_ldr)
10521 opcode = T_MNEM_ldr_sp;
10523 opcode = T_MNEM_str_sp;
10525 inst.instruction = inst.operands[0].reg << 8;
10529 inst.instruction = inst.operands[0].reg;
10530 inst.instruction |= inst.operands[1].reg << 3;
10532 inst.instruction |= THUMB_OP16 (opcode);
10533 if (inst.size_req == 2)
10534 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10536 inst.relax = opcode;
10540 /* Definitely a 32-bit variant. */
10542 /* Warning for Erratum 752419. */
10543 if (opcode == T_MNEM_ldr
10544 && inst.operands[0].reg == REG_SP
10545 && inst.operands[1].writeback == 1
10546 && !inst.operands[1].immisreg)
10548 if (no_cpu_selected ()
10549 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10550 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10551 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10552 as_warn (_("This instruction may be unpredictable "
10553 "if executed on M-profile cores "
10554 "with interrupts enabled."));
10557 /* Do some validations regarding addressing modes. */
10558 if (inst.operands[1].immisreg)
10559 reject_bad_reg (inst.operands[1].imm);
10561 constraint (inst.operands[1].writeback == 1
10562 && inst.operands[0].reg == inst.operands[1].reg,
10565 inst.instruction = THUMB_OP32 (opcode);
10566 inst.instruction |= inst.operands[0].reg << 12;
10567 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10568 check_ldr_r15_aligned ();
10572 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10574 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10576 /* Only [Rn,Rm] is acceptable. */
10577 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10578 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10579 || inst.operands[1].postind || inst.operands[1].shifted
10580 || inst.operands[1].negative,
10581 _("Thumb does not support this addressing mode"));
10582 inst.instruction = THUMB_OP16 (inst.instruction);
10586 inst.instruction = THUMB_OP16 (inst.instruction);
10587 if (!inst.operands[1].isreg)
10588 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10591 constraint (!inst.operands[1].preind
10592 || inst.operands[1].shifted
10593 || inst.operands[1].writeback,
10594 _("Thumb does not support this addressing mode"));
10595 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10597 constraint (inst.instruction & 0x0600,
10598 _("byte or halfword not valid for base register"));
10599 constraint (inst.operands[1].reg == REG_PC
10600 && !(inst.instruction & THUMB_LOAD_BIT),
10601 _("r15 based store not allowed"));
10602 constraint (inst.operands[1].immisreg,
10603 _("invalid base register for register offset"));
10605 if (inst.operands[1].reg == REG_PC)
10606 inst.instruction = T_OPCODE_LDR_PC;
10607 else if (inst.instruction & THUMB_LOAD_BIT)
10608 inst.instruction = T_OPCODE_LDR_SP;
10610 inst.instruction = T_OPCODE_STR_SP;
10612 inst.instruction |= inst.operands[0].reg << 8;
10613 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10617 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10618 if (!inst.operands[1].immisreg)
10620 /* Immediate offset. */
10621 inst.instruction |= inst.operands[0].reg;
10622 inst.instruction |= inst.operands[1].reg << 3;
10623 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10627 /* Register offset. */
10628 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10629 constraint (inst.operands[1].negative,
10630 _("Thumb does not support this addressing mode"));
10633 switch (inst.instruction)
10635 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10636 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10637 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10638 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10639 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10640 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10641 case 0x5600 /* ldrsb */:
10642 case 0x5e00 /* ldrsh */: break;
10646 inst.instruction |= inst.operands[0].reg;
10647 inst.instruction |= inst.operands[1].reg << 3;
10648 inst.instruction |= inst.operands[1].imm << 6;
10654 if (!inst.operands[1].present)
10656 inst.operands[1].reg = inst.operands[0].reg + 1;
10657 constraint (inst.operands[0].reg == REG_LR,
10658 _("r14 not allowed here"));
10659 constraint (inst.operands[0].reg == REG_R12,
10660 _("r12 not allowed here"));
10663 if (inst.operands[2].writeback
10664 && (inst.operands[0].reg == inst.operands[2].reg
10665 || inst.operands[1].reg == inst.operands[2].reg))
10666 as_warn (_("base register written back, and overlaps "
10667 "one of transfer registers"));
10669 inst.instruction |= inst.operands[0].reg << 12;
10670 inst.instruction |= inst.operands[1].reg << 8;
10671 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10677 inst.instruction |= inst.operands[0].reg << 12;
10678 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10684 unsigned Rd, Rn, Rm, Ra;
10686 Rd = inst.operands[0].reg;
10687 Rn = inst.operands[1].reg;
10688 Rm = inst.operands[2].reg;
10689 Ra = inst.operands[3].reg;
10691 reject_bad_reg (Rd);
10692 reject_bad_reg (Rn);
10693 reject_bad_reg (Rm);
10694 reject_bad_reg (Ra);
10696 inst.instruction |= Rd << 8;
10697 inst.instruction |= Rn << 16;
10698 inst.instruction |= Rm;
10699 inst.instruction |= Ra << 12;
10705 unsigned RdLo, RdHi, Rn, Rm;
10707 RdLo = inst.operands[0].reg;
10708 RdHi = inst.operands[1].reg;
10709 Rn = inst.operands[2].reg;
10710 Rm = inst.operands[3].reg;
10712 reject_bad_reg (RdLo);
10713 reject_bad_reg (RdHi);
10714 reject_bad_reg (Rn);
10715 reject_bad_reg (Rm);
10717 inst.instruction |= RdLo << 12;
10718 inst.instruction |= RdHi << 8;
10719 inst.instruction |= Rn << 16;
10720 inst.instruction |= Rm;
10724 do_t_mov_cmp (void)
10728 Rn = inst.operands[0].reg;
10729 Rm = inst.operands[1].reg;
10732 set_it_insn_type_last ();
10734 if (unified_syntax)
10736 int r0off = (inst.instruction == T_MNEM_mov
10737 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10738 unsigned long opcode;
10739 bfd_boolean narrow;
10740 bfd_boolean low_regs;
10742 low_regs = (Rn <= 7 && Rm <= 7);
10743 opcode = inst.instruction;
10744 if (in_it_block ())
10745 narrow = opcode != T_MNEM_movs;
10747 narrow = opcode != T_MNEM_movs || low_regs;
10748 if (inst.size_req == 4
10749 || inst.operands[1].shifted)
10752 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10753 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10754 && !inst.operands[1].shifted
10758 inst.instruction = T2_SUBS_PC_LR;
10762 if (opcode == T_MNEM_cmp)
10764 constraint (Rn == REG_PC, BAD_PC);
10767 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10769 warn_deprecated_sp (Rm);
10770 /* R15 was documented as a valid choice for Rm in ARMv6,
10771 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10772 tools reject R15, so we do too. */
10773 constraint (Rm == REG_PC, BAD_PC);
10776 reject_bad_reg (Rm);
10778 else if (opcode == T_MNEM_mov
10779 || opcode == T_MNEM_movs)
10781 if (inst.operands[1].isreg)
10783 if (opcode == T_MNEM_movs)
10785 reject_bad_reg (Rn);
10786 reject_bad_reg (Rm);
10790 /* This is mov.n. */
10791 if ((Rn == REG_SP || Rn == REG_PC)
10792 && (Rm == REG_SP || Rm == REG_PC))
10794 as_warn (_("Use of r%u as a source register is "
10795 "deprecated when r%u is the destination "
10796 "register."), Rm, Rn);
10801 /* This is mov.w. */
10802 constraint (Rn == REG_PC, BAD_PC);
10803 constraint (Rm == REG_PC, BAD_PC);
10804 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10808 reject_bad_reg (Rn);
10811 if (!inst.operands[1].isreg)
10813 /* Immediate operand. */
10814 if (!in_it_block () && opcode == T_MNEM_mov)
10816 if (low_regs && narrow)
10818 inst.instruction = THUMB_OP16 (opcode);
10819 inst.instruction |= Rn << 8;
10820 if (inst.size_req == 2)
10821 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10823 inst.relax = opcode;
10827 inst.instruction = THUMB_OP32 (inst.instruction);
10828 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10829 inst.instruction |= Rn << r0off;
10830 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10833 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10834 && (inst.instruction == T_MNEM_mov
10835 || inst.instruction == T_MNEM_movs))
10837 /* Register shifts are encoded as separate shift instructions. */
10838 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10840 if (in_it_block ())
10845 if (inst.size_req == 4)
10848 if (!low_regs || inst.operands[1].imm > 7)
10854 switch (inst.operands[1].shift_kind)
10857 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10860 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10863 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10866 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10872 inst.instruction = opcode;
10875 inst.instruction |= Rn;
10876 inst.instruction |= inst.operands[1].imm << 3;
10881 inst.instruction |= CONDS_BIT;
10883 inst.instruction |= Rn << 8;
10884 inst.instruction |= Rm << 16;
10885 inst.instruction |= inst.operands[1].imm;
10890 /* Some mov with immediate shift have narrow variants.
10891 Register shifts are handled above. */
10892 if (low_regs && inst.operands[1].shifted
10893 && (inst.instruction == T_MNEM_mov
10894 || inst.instruction == T_MNEM_movs))
10896 if (in_it_block ())
10897 narrow = (inst.instruction == T_MNEM_mov);
10899 narrow = (inst.instruction == T_MNEM_movs);
10904 switch (inst.operands[1].shift_kind)
10906 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10907 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10908 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10909 default: narrow = FALSE; break;
10915 inst.instruction |= Rn;
10916 inst.instruction |= Rm << 3;
10917 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10921 inst.instruction = THUMB_OP32 (inst.instruction);
10922 inst.instruction |= Rn << r0off;
10923 encode_thumb32_shifted_operand (1);
10927 switch (inst.instruction)
10930 /* In v4t or v5t a move of two lowregs produces unpredictable
10931 results. Don't allow this. */
10934 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
10935 "MOV Rd, Rs with two low registers is not "
10936 "permitted on this architecture");
10937 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
10941 inst.instruction = T_OPCODE_MOV_HR;
10942 inst.instruction |= (Rn & 0x8) << 4;
10943 inst.instruction |= (Rn & 0x7);
10944 inst.instruction |= Rm << 3;
10948 /* We know we have low registers at this point.
10949 Generate LSLS Rd, Rs, #0. */
10950 inst.instruction = T_OPCODE_LSL_I;
10951 inst.instruction |= Rn;
10952 inst.instruction |= Rm << 3;
10958 inst.instruction = T_OPCODE_CMP_LR;
10959 inst.instruction |= Rn;
10960 inst.instruction |= Rm << 3;
10964 inst.instruction = T_OPCODE_CMP_HR;
10965 inst.instruction |= (Rn & 0x8) << 4;
10966 inst.instruction |= (Rn & 0x7);
10967 inst.instruction |= Rm << 3;
10974 inst.instruction = THUMB_OP16 (inst.instruction);
10976 /* PR 10443: Do not silently ignore shifted operands. */
10977 constraint (inst.operands[1].shifted,
10978 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10980 if (inst.operands[1].isreg)
10982 if (Rn < 8 && Rm < 8)
10984 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10985 since a MOV instruction produces unpredictable results. */
10986 if (inst.instruction == T_OPCODE_MOV_I8)
10987 inst.instruction = T_OPCODE_ADD_I3;
10989 inst.instruction = T_OPCODE_CMP_LR;
10991 inst.instruction |= Rn;
10992 inst.instruction |= Rm << 3;
10996 if (inst.instruction == T_OPCODE_MOV_I8)
10997 inst.instruction = T_OPCODE_MOV_HR;
10999 inst.instruction = T_OPCODE_CMP_HR;
11005 constraint (Rn > 7,
11006 _("only lo regs allowed with immediate"));
11007 inst.instruction |= Rn << 8;
11008 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11019 top = (inst.instruction & 0x00800000) != 0;
11020 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11022 constraint (top, _(":lower16: not allowed this instruction"));
11023 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11025 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11027 constraint (!top, _(":upper16: not allowed this instruction"));
11028 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11031 Rd = inst.operands[0].reg;
11032 reject_bad_reg (Rd);
11034 inst.instruction |= Rd << 8;
11035 if (inst.reloc.type == BFD_RELOC_UNUSED)
11037 imm = inst.reloc.exp.X_add_number;
11038 inst.instruction |= (imm & 0xf000) << 4;
11039 inst.instruction |= (imm & 0x0800) << 15;
11040 inst.instruction |= (imm & 0x0700) << 4;
11041 inst.instruction |= (imm & 0x00ff);
11046 do_t_mvn_tst (void)
11050 Rn = inst.operands[0].reg;
11051 Rm = inst.operands[1].reg;
11053 if (inst.instruction == T_MNEM_cmp
11054 || inst.instruction == T_MNEM_cmn)
11055 constraint (Rn == REG_PC, BAD_PC);
11057 reject_bad_reg (Rn);
11058 reject_bad_reg (Rm);
11060 if (unified_syntax)
11062 int r0off = (inst.instruction == T_MNEM_mvn
11063 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11064 bfd_boolean narrow;
11066 if (inst.size_req == 4
11067 || inst.instruction > 0xffff
11068 || inst.operands[1].shifted
11069 || Rn > 7 || Rm > 7)
11071 else if (inst.instruction == T_MNEM_cmn)
11073 else if (THUMB_SETS_FLAGS (inst.instruction))
11074 narrow = !in_it_block ();
11076 narrow = in_it_block ();
11078 if (!inst.operands[1].isreg)
11080 /* For an immediate, we always generate a 32-bit opcode;
11081 section relaxation will shrink it later if possible. */
11082 if (inst.instruction < 0xffff)
11083 inst.instruction = THUMB_OP32 (inst.instruction);
11084 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11085 inst.instruction |= Rn << r0off;
11086 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11090 /* See if we can do this with a 16-bit instruction. */
11093 inst.instruction = THUMB_OP16 (inst.instruction);
11094 inst.instruction |= Rn;
11095 inst.instruction |= Rm << 3;
11099 constraint (inst.operands[1].shifted
11100 && inst.operands[1].immisreg,
11101 _("shift must be constant"));
11102 if (inst.instruction < 0xffff)
11103 inst.instruction = THUMB_OP32 (inst.instruction);
11104 inst.instruction |= Rn << r0off;
11105 encode_thumb32_shifted_operand (1);
11111 constraint (inst.instruction > 0xffff
11112 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11113 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11114 _("unshifted register required"));
11115 constraint (Rn > 7 || Rm > 7,
11118 inst.instruction = THUMB_OP16 (inst.instruction);
11119 inst.instruction |= Rn;
11120 inst.instruction |= Rm << 3;
11129 if (do_vfp_nsyn_mrs () == SUCCESS)
11132 Rd = inst.operands[0].reg;
11133 reject_bad_reg (Rd);
11134 inst.instruction |= Rd << 8;
11136 if (inst.operands[1].isreg)
11138 unsigned br = inst.operands[1].reg;
11139 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11140 as_bad (_("bad register for mrs"));
11142 inst.instruction |= br & (0xf << 16);
11143 inst.instruction |= (br & 0x300) >> 4;
11144 inst.instruction |= (br & SPSR_BIT) >> 2;
11148 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11150 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11151 constraint (flags != 0, _("selected processor does not support "
11152 "requested special purpose register"));
11154 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11156 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11157 _("'APSR', 'CPSR' or 'SPSR' expected"));
11159 inst.instruction |= (flags & SPSR_BIT) >> 2;
11160 inst.instruction |= inst.operands[1].imm & 0xff;
11161 inst.instruction |= 0xf0000;
11171 if (do_vfp_nsyn_msr () == SUCCESS)
11174 constraint (!inst.operands[1].isreg,
11175 _("Thumb encoding does not support an immediate here"));
11177 if (inst.operands[0].isreg)
11178 flags = (int)(inst.operands[0].reg);
11180 flags = inst.operands[0].imm;
11182 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11184 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11186 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11187 && (bits & ~(PSR_s | PSR_f)) != 0)
11188 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11190 _("selected processor does not support requested special "
11191 "purpose register"));
11194 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11195 "requested special purpose register"));
11197 Rn = inst.operands[1].reg;
11198 reject_bad_reg (Rn);
11200 inst.instruction |= (flags & SPSR_BIT) >> 2;
11201 inst.instruction |= (flags & 0xf0000) >> 8;
11202 inst.instruction |= (flags & 0x300) >> 4;
11203 inst.instruction |= (flags & 0xff);
11204 inst.instruction |= Rn << 16;
11210 bfd_boolean narrow;
11211 unsigned Rd, Rn, Rm;
11213 if (!inst.operands[2].present)
11214 inst.operands[2].reg = inst.operands[0].reg;
11216 Rd = inst.operands[0].reg;
11217 Rn = inst.operands[1].reg;
11218 Rm = inst.operands[2].reg;
11220 if (unified_syntax)
11222 if (inst.size_req == 4
11228 else if (inst.instruction == T_MNEM_muls)
11229 narrow = !in_it_block ();
11231 narrow = in_it_block ();
11235 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11236 constraint (Rn > 7 || Rm > 7,
11243 /* 16-bit MULS/Conditional MUL. */
11244 inst.instruction = THUMB_OP16 (inst.instruction);
11245 inst.instruction |= Rd;
11248 inst.instruction |= Rm << 3;
11250 inst.instruction |= Rn << 3;
11252 constraint (1, _("dest must overlap one source register"));
11256 constraint (inst.instruction != T_MNEM_mul,
11257 _("Thumb-2 MUL must not set flags"));
11259 inst.instruction = THUMB_OP32 (inst.instruction);
11260 inst.instruction |= Rd << 8;
11261 inst.instruction |= Rn << 16;
11262 inst.instruction |= Rm << 0;
11264 reject_bad_reg (Rd);
11265 reject_bad_reg (Rn);
11266 reject_bad_reg (Rm);
11273 unsigned RdLo, RdHi, Rn, Rm;
11275 RdLo = inst.operands[0].reg;
11276 RdHi = inst.operands[1].reg;
11277 Rn = inst.operands[2].reg;
11278 Rm = inst.operands[3].reg;
11280 reject_bad_reg (RdLo);
11281 reject_bad_reg (RdHi);
11282 reject_bad_reg (Rn);
11283 reject_bad_reg (Rm);
11285 inst.instruction |= RdLo << 12;
11286 inst.instruction |= RdHi << 8;
11287 inst.instruction |= Rn << 16;
11288 inst.instruction |= Rm;
11291 as_tsktsk (_("rdhi and rdlo must be different"));
11297 set_it_insn_type (NEUTRAL_IT_INSN);
11299 if (unified_syntax)
11301 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11303 inst.instruction = THUMB_OP32 (inst.instruction);
11304 inst.instruction |= inst.operands[0].imm;
11308 /* PR9722: Check for Thumb2 availability before
11309 generating a thumb2 nop instruction. */
11310 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11312 inst.instruction = THUMB_OP16 (inst.instruction);
11313 inst.instruction |= inst.operands[0].imm << 4;
11316 inst.instruction = 0x46c0;
11321 constraint (inst.operands[0].present,
11322 _("Thumb does not support NOP with hints"));
11323 inst.instruction = 0x46c0;
11330 if (unified_syntax)
11332 bfd_boolean narrow;
11334 if (THUMB_SETS_FLAGS (inst.instruction))
11335 narrow = !in_it_block ();
11337 narrow = in_it_block ();
11338 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11340 if (inst.size_req == 4)
11345 inst.instruction = THUMB_OP32 (inst.instruction);
11346 inst.instruction |= inst.operands[0].reg << 8;
11347 inst.instruction |= inst.operands[1].reg << 16;
11351 inst.instruction = THUMB_OP16 (inst.instruction);
11352 inst.instruction |= inst.operands[0].reg;
11353 inst.instruction |= inst.operands[1].reg << 3;
11358 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11360 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11362 inst.instruction = THUMB_OP16 (inst.instruction);
11363 inst.instruction |= inst.operands[0].reg;
11364 inst.instruction |= inst.operands[1].reg << 3;
11373 Rd = inst.operands[0].reg;
11374 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11376 reject_bad_reg (Rd);
11377 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11378 reject_bad_reg (Rn);
11380 inst.instruction |= Rd << 8;
11381 inst.instruction |= Rn << 16;
11383 if (!inst.operands[2].isreg)
11385 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11386 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11392 Rm = inst.operands[2].reg;
11393 reject_bad_reg (Rm);
11395 constraint (inst.operands[2].shifted
11396 && inst.operands[2].immisreg,
11397 _("shift must be constant"));
11398 encode_thumb32_shifted_operand (2);
11405 unsigned Rd, Rn, Rm;
11407 Rd = inst.operands[0].reg;
11408 Rn = inst.operands[1].reg;
11409 Rm = inst.operands[2].reg;
11411 reject_bad_reg (Rd);
11412 reject_bad_reg (Rn);
11413 reject_bad_reg (Rm);
11415 inst.instruction |= Rd << 8;
11416 inst.instruction |= Rn << 16;
11417 inst.instruction |= Rm;
11418 if (inst.operands[3].present)
11420 unsigned int val = inst.reloc.exp.X_add_number;
11421 constraint (inst.reloc.exp.X_op != O_constant,
11422 _("expression too complex"));
11423 inst.instruction |= (val & 0x1c) << 10;
11424 inst.instruction |= (val & 0x03) << 6;
11431 if (!inst.operands[3].present)
11435 inst.instruction &= ~0x00000020;
11437 /* PR 10168. Swap the Rm and Rn registers. */
11438 Rtmp = inst.operands[1].reg;
11439 inst.operands[1].reg = inst.operands[2].reg;
11440 inst.operands[2].reg = Rtmp;
11448 if (inst.operands[0].immisreg)
11449 reject_bad_reg (inst.operands[0].imm);
11451 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11455 do_t_push_pop (void)
11459 constraint (inst.operands[0].writeback,
11460 _("push/pop do not support {reglist}^"));
11461 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11462 _("expression too complex"));
11464 mask = inst.operands[0].imm;
11465 if ((mask & ~0xff) == 0)
11466 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11467 else if ((inst.instruction == T_MNEM_push
11468 && (mask & ~0xff) == 1 << REG_LR)
11469 || (inst.instruction == T_MNEM_pop
11470 && (mask & ~0xff) == 1 << REG_PC))
11472 inst.instruction = THUMB_OP16 (inst.instruction);
11473 inst.instruction |= THUMB_PP_PC_LR;
11474 inst.instruction |= mask & 0xff;
11476 else if (unified_syntax)
11478 inst.instruction = THUMB_OP32 (inst.instruction);
11479 encode_thumb2_ldmstm (13, mask, TRUE);
11483 inst.error = _("invalid register list to push/pop instruction");
11493 Rd = inst.operands[0].reg;
11494 Rm = inst.operands[1].reg;
11496 reject_bad_reg (Rd);
11497 reject_bad_reg (Rm);
11499 inst.instruction |= Rd << 8;
11500 inst.instruction |= Rm << 16;
11501 inst.instruction |= Rm;
11509 Rd = inst.operands[0].reg;
11510 Rm = inst.operands[1].reg;
11512 reject_bad_reg (Rd);
11513 reject_bad_reg (Rm);
11515 if (Rd <= 7 && Rm <= 7
11516 && inst.size_req != 4)
11518 inst.instruction = THUMB_OP16 (inst.instruction);
11519 inst.instruction |= Rd;
11520 inst.instruction |= Rm << 3;
11522 else if (unified_syntax)
11524 inst.instruction = THUMB_OP32 (inst.instruction);
11525 inst.instruction |= Rd << 8;
11526 inst.instruction |= Rm << 16;
11527 inst.instruction |= Rm;
11530 inst.error = BAD_HIREG;
11538 Rd = inst.operands[0].reg;
11539 Rm = inst.operands[1].reg;
11541 reject_bad_reg (Rd);
11542 reject_bad_reg (Rm);
11544 inst.instruction |= Rd << 8;
11545 inst.instruction |= Rm;
11553 Rd = inst.operands[0].reg;
11554 Rs = (inst.operands[1].present
11555 ? inst.operands[1].reg /* Rd, Rs, foo */
11556 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11558 reject_bad_reg (Rd);
11559 reject_bad_reg (Rs);
11560 if (inst.operands[2].isreg)
11561 reject_bad_reg (inst.operands[2].reg);
11563 inst.instruction |= Rd << 8;
11564 inst.instruction |= Rs << 16;
11565 if (!inst.operands[2].isreg)
11567 bfd_boolean narrow;
11569 if ((inst.instruction & 0x00100000) != 0)
11570 narrow = !in_it_block ();
11572 narrow = in_it_block ();
11574 if (Rd > 7 || Rs > 7)
11577 if (inst.size_req == 4 || !unified_syntax)
11580 if (inst.reloc.exp.X_op != O_constant
11581 || inst.reloc.exp.X_add_number != 0)
11584 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11585 relaxation, but it doesn't seem worth the hassle. */
11588 inst.reloc.type = BFD_RELOC_UNUSED;
11589 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11590 inst.instruction |= Rs << 3;
11591 inst.instruction |= Rd;
11595 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11596 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11600 encode_thumb32_shifted_operand (2);
11606 set_it_insn_type (OUTSIDE_IT_INSN);
11607 if (inst.operands[0].imm)
11608 inst.instruction |= 0x8;
11614 if (!inst.operands[1].present)
11615 inst.operands[1].reg = inst.operands[0].reg;
11617 if (unified_syntax)
11619 bfd_boolean narrow;
11622 switch (inst.instruction)
11625 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11627 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11629 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11631 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11635 if (THUMB_SETS_FLAGS (inst.instruction))
11636 narrow = !in_it_block ();
11638 narrow = in_it_block ();
11639 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11641 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11643 if (inst.operands[2].isreg
11644 && (inst.operands[1].reg != inst.operands[0].reg
11645 || inst.operands[2].reg > 7))
11647 if (inst.size_req == 4)
11650 reject_bad_reg (inst.operands[0].reg);
11651 reject_bad_reg (inst.operands[1].reg);
11655 if (inst.operands[2].isreg)
11657 reject_bad_reg (inst.operands[2].reg);
11658 inst.instruction = THUMB_OP32 (inst.instruction);
11659 inst.instruction |= inst.operands[0].reg << 8;
11660 inst.instruction |= inst.operands[1].reg << 16;
11661 inst.instruction |= inst.operands[2].reg;
11663 /* PR 12854: Error on extraneous shifts. */
11664 constraint (inst.operands[2].shifted,
11665 _("extraneous shift as part of operand to shift insn"));
11669 inst.operands[1].shifted = 1;
11670 inst.operands[1].shift_kind = shift_kind;
11671 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11672 ? T_MNEM_movs : T_MNEM_mov);
11673 inst.instruction |= inst.operands[0].reg << 8;
11674 encode_thumb32_shifted_operand (1);
11675 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11676 inst.reloc.type = BFD_RELOC_UNUSED;
11681 if (inst.operands[2].isreg)
11683 switch (shift_kind)
11685 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11686 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11687 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11688 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11692 inst.instruction |= inst.operands[0].reg;
11693 inst.instruction |= inst.operands[2].reg << 3;
11695 /* PR 12854: Error on extraneous shifts. */
11696 constraint (inst.operands[2].shifted,
11697 _("extraneous shift as part of operand to shift insn"));
11701 switch (shift_kind)
11703 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11704 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11705 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11708 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11709 inst.instruction |= inst.operands[0].reg;
11710 inst.instruction |= inst.operands[1].reg << 3;
11716 constraint (inst.operands[0].reg > 7
11717 || inst.operands[1].reg > 7, BAD_HIREG);
11718 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11720 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11722 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11723 constraint (inst.operands[0].reg != inst.operands[1].reg,
11724 _("source1 and dest must be same register"));
11726 switch (inst.instruction)
11728 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11729 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11730 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11731 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11735 inst.instruction |= inst.operands[0].reg;
11736 inst.instruction |= inst.operands[2].reg << 3;
11738 /* PR 12854: Error on extraneous shifts. */
11739 constraint (inst.operands[2].shifted,
11740 _("extraneous shift as part of operand to shift insn"));
11744 switch (inst.instruction)
11746 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11747 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11748 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11749 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11752 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11753 inst.instruction |= inst.operands[0].reg;
11754 inst.instruction |= inst.operands[1].reg << 3;
11762 unsigned Rd, Rn, Rm;
11764 Rd = inst.operands[0].reg;
11765 Rn = inst.operands[1].reg;
11766 Rm = inst.operands[2].reg;
11768 reject_bad_reg (Rd);
11769 reject_bad_reg (Rn);
11770 reject_bad_reg (Rm);
11772 inst.instruction |= Rd << 8;
11773 inst.instruction |= Rn << 16;
11774 inst.instruction |= Rm;
11780 unsigned Rd, Rn, Rm;
11782 Rd = inst.operands[0].reg;
11783 Rm = inst.operands[1].reg;
11784 Rn = inst.operands[2].reg;
11786 reject_bad_reg (Rd);
11787 reject_bad_reg (Rn);
11788 reject_bad_reg (Rm);
11790 inst.instruction |= Rd << 8;
11791 inst.instruction |= Rn << 16;
11792 inst.instruction |= Rm;
11798 unsigned int value = inst.reloc.exp.X_add_number;
11799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11800 _("SMC is not permitted on this architecture"));
11801 constraint (inst.reloc.exp.X_op != O_constant,
11802 _("expression too complex"));
11803 inst.reloc.type = BFD_RELOC_UNUSED;
11804 inst.instruction |= (value & 0xf000) >> 12;
11805 inst.instruction |= (value & 0x0ff0);
11806 inst.instruction |= (value & 0x000f) << 16;
11812 unsigned int value = inst.reloc.exp.X_add_number;
11814 inst.reloc.type = BFD_RELOC_UNUSED;
11815 inst.instruction |= (value & 0x0fff);
11816 inst.instruction |= (value & 0xf000) << 4;
11820 do_t_ssat_usat (int bias)
11824 Rd = inst.operands[0].reg;
11825 Rn = inst.operands[2].reg;
11827 reject_bad_reg (Rd);
11828 reject_bad_reg (Rn);
11830 inst.instruction |= Rd << 8;
11831 inst.instruction |= inst.operands[1].imm - bias;
11832 inst.instruction |= Rn << 16;
11834 if (inst.operands[3].present)
11836 offsetT shift_amount = inst.reloc.exp.X_add_number;
11838 inst.reloc.type = BFD_RELOC_UNUSED;
11840 constraint (inst.reloc.exp.X_op != O_constant,
11841 _("expression too complex"));
11843 if (shift_amount != 0)
11845 constraint (shift_amount > 31,
11846 _("shift expression is too large"));
11848 if (inst.operands[3].shift_kind == SHIFT_ASR)
11849 inst.instruction |= 0x00200000; /* sh bit. */
11851 inst.instruction |= (shift_amount & 0x1c) << 10;
11852 inst.instruction |= (shift_amount & 0x03) << 6;
11860 do_t_ssat_usat (1);
11868 Rd = inst.operands[0].reg;
11869 Rn = inst.operands[2].reg;
11871 reject_bad_reg (Rd);
11872 reject_bad_reg (Rn);
11874 inst.instruction |= Rd << 8;
11875 inst.instruction |= inst.operands[1].imm - 1;
11876 inst.instruction |= Rn << 16;
11882 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11883 || inst.operands[2].postind || inst.operands[2].writeback
11884 || inst.operands[2].immisreg || inst.operands[2].shifted
11885 || inst.operands[2].negative,
11888 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11890 inst.instruction |= inst.operands[0].reg << 8;
11891 inst.instruction |= inst.operands[1].reg << 12;
11892 inst.instruction |= inst.operands[2].reg << 16;
11893 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11899 if (!inst.operands[2].present)
11900 inst.operands[2].reg = inst.operands[1].reg + 1;
11902 constraint (inst.operands[0].reg == inst.operands[1].reg
11903 || inst.operands[0].reg == inst.operands[2].reg
11904 || inst.operands[0].reg == inst.operands[3].reg,
11907 inst.instruction |= inst.operands[0].reg;
11908 inst.instruction |= inst.operands[1].reg << 12;
11909 inst.instruction |= inst.operands[2].reg << 8;
11910 inst.instruction |= inst.operands[3].reg << 16;
11916 unsigned Rd, Rn, Rm;
11918 Rd = inst.operands[0].reg;
11919 Rn = inst.operands[1].reg;
11920 Rm = inst.operands[2].reg;
11922 reject_bad_reg (Rd);
11923 reject_bad_reg (Rn);
11924 reject_bad_reg (Rm);
11926 inst.instruction |= Rd << 8;
11927 inst.instruction |= Rn << 16;
11928 inst.instruction |= Rm;
11929 inst.instruction |= inst.operands[3].imm << 4;
11937 Rd = inst.operands[0].reg;
11938 Rm = inst.operands[1].reg;
11940 reject_bad_reg (Rd);
11941 reject_bad_reg (Rm);
11943 if (inst.instruction <= 0xffff
11944 && inst.size_req != 4
11945 && Rd <= 7 && Rm <= 7
11946 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11948 inst.instruction = THUMB_OP16 (inst.instruction);
11949 inst.instruction |= Rd;
11950 inst.instruction |= Rm << 3;
11952 else if (unified_syntax)
11954 if (inst.instruction <= 0xffff)
11955 inst.instruction = THUMB_OP32 (inst.instruction);
11956 inst.instruction |= Rd << 8;
11957 inst.instruction |= Rm;
11958 inst.instruction |= inst.operands[2].imm << 4;
11962 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11963 _("Thumb encoding does not support rotation"));
11964 constraint (1, BAD_HIREG);
11971 /* We have to do the following check manually as ARM_EXT_OS only applies
11973 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11975 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11976 /* This only applies to the v6m howver, not later architectures. */
11977 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11978 as_bad (_("SVC is not permitted on this architecture"));
11979 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11982 inst.reloc.type = BFD_RELOC_ARM_SWI;
11991 half = (inst.instruction & 0x10) != 0;
11992 set_it_insn_type_last ();
11993 constraint (inst.operands[0].immisreg,
11994 _("instruction requires register index"));
11996 Rn = inst.operands[0].reg;
11997 Rm = inst.operands[0].imm;
11999 constraint (Rn == REG_SP, BAD_SP);
12000 reject_bad_reg (Rm);
12002 constraint (!half && inst.operands[0].shifted,
12003 _("instruction does not allow shifted index"));
12004 inst.instruction |= (Rn << 16) | Rm;
12010 do_t_ssat_usat (0);
12018 Rd = inst.operands[0].reg;
12019 Rn = inst.operands[2].reg;
12021 reject_bad_reg (Rd);
12022 reject_bad_reg (Rn);
12024 inst.instruction |= Rd << 8;
12025 inst.instruction |= inst.operands[1].imm;
12026 inst.instruction |= Rn << 16;
12029 /* Neon instruction encoder helpers. */
12031 /* Encodings for the different types for various Neon opcodes. */
12033 /* An "invalid" code for the following tables. */
12036 struct neon_tab_entry
12039 unsigned float_or_poly;
12040 unsigned scalar_or_imm;
12043 /* Map overloaded Neon opcodes to their respective encodings. */
12044 #define NEON_ENC_TAB \
12045 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12046 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12047 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12048 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12049 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12050 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12051 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12052 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12053 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12054 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12055 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12056 /* Register variants of the following two instructions are encoded as
12057 vcge / vcgt with the operands reversed. */ \
12058 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12059 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12060 X(vfma, N_INV, 0x0000c10, N_INV), \
12061 X(vfms, N_INV, 0x0200c10, N_INV), \
12062 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12063 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12064 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12065 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12066 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12067 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12068 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12069 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12070 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12071 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12072 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12073 X(vshl, 0x0000400, N_INV, 0x0800510), \
12074 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12075 X(vand, 0x0000110, N_INV, 0x0800030), \
12076 X(vbic, 0x0100110, N_INV, 0x0800030), \
12077 X(veor, 0x1000110, N_INV, N_INV), \
12078 X(vorn, 0x0300110, N_INV, 0x0800010), \
12079 X(vorr, 0x0200110, N_INV, 0x0800010), \
12080 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12081 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12082 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12083 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12084 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12085 X(vst1, 0x0000000, 0x0800000, N_INV), \
12086 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12087 X(vst2, 0x0000100, 0x0800100, N_INV), \
12088 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12089 X(vst3, 0x0000200, 0x0800200, N_INV), \
12090 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12091 X(vst4, 0x0000300, 0x0800300, N_INV), \
12092 X(vmovn, 0x1b20200, N_INV, N_INV), \
12093 X(vtrn, 0x1b20080, N_INV, N_INV), \
12094 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12095 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12096 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12097 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12098 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12099 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12100 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12101 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12102 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12103 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12104 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12108 #define X(OPC,I,F,S) N_MNEM_##OPC
12113 static const struct neon_tab_entry neon_enc_tab[] =
12115 #define X(OPC,I,F,S) { (I), (F), (S) }
12120 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12121 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12122 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12123 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12124 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12125 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12126 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12127 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12128 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12129 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12130 #define NEON_ENC_SINGLE_(X) \
12131 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12132 #define NEON_ENC_DOUBLE_(X) \
12133 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12135 #define NEON_ENCODE(type, inst) \
12138 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12139 inst.is_neon = 1; \
12143 #define check_neon_suffixes \
12146 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12148 as_bad (_("invalid neon suffix for non neon instruction")); \
12154 /* Define shapes for instruction operands. The following mnemonic characters
12155 are used in this table:
12157 F - VFP S<n> register
12158 D - Neon D<n> register
12159 Q - Neon Q<n> register
12163 L - D<n> register list
12165 This table is used to generate various data:
12166 - enumerations of the form NS_DDR to be used as arguments to
12168 - a table classifying shapes into single, double, quad, mixed.
12169 - a table used to drive neon_select_shape. */
12171 #define NEON_SHAPE_DEF \
12172 X(3, (D, D, D), DOUBLE), \
12173 X(3, (Q, Q, Q), QUAD), \
12174 X(3, (D, D, I), DOUBLE), \
12175 X(3, (Q, Q, I), QUAD), \
12176 X(3, (D, D, S), DOUBLE), \
12177 X(3, (Q, Q, S), QUAD), \
12178 X(2, (D, D), DOUBLE), \
12179 X(2, (Q, Q), QUAD), \
12180 X(2, (D, S), DOUBLE), \
12181 X(2, (Q, S), QUAD), \
12182 X(2, (D, R), DOUBLE), \
12183 X(2, (Q, R), QUAD), \
12184 X(2, (D, I), DOUBLE), \
12185 X(2, (Q, I), QUAD), \
12186 X(3, (D, L, D), DOUBLE), \
12187 X(2, (D, Q), MIXED), \
12188 X(2, (Q, D), MIXED), \
12189 X(3, (D, Q, I), MIXED), \
12190 X(3, (Q, D, I), MIXED), \
12191 X(3, (Q, D, D), MIXED), \
12192 X(3, (D, Q, Q), MIXED), \
12193 X(3, (Q, Q, D), MIXED), \
12194 X(3, (Q, D, S), MIXED), \
12195 X(3, (D, Q, S), MIXED), \
12196 X(4, (D, D, D, I), DOUBLE), \
12197 X(4, (Q, Q, Q, I), QUAD), \
12198 X(2, (F, F), SINGLE), \
12199 X(3, (F, F, F), SINGLE), \
12200 X(2, (F, I), SINGLE), \
12201 X(2, (F, D), MIXED), \
12202 X(2, (D, F), MIXED), \
12203 X(3, (F, F, I), MIXED), \
12204 X(4, (R, R, F, F), SINGLE), \
12205 X(4, (F, F, R, R), SINGLE), \
12206 X(3, (D, R, R), DOUBLE), \
12207 X(3, (R, R, D), DOUBLE), \
12208 X(2, (S, R), SINGLE), \
12209 X(2, (R, S), SINGLE), \
12210 X(2, (F, R), SINGLE), \
12211 X(2, (R, F), SINGLE)
12213 #define S2(A,B) NS_##A##B
12214 #define S3(A,B,C) NS_##A##B##C
12215 #define S4(A,B,C,D) NS_##A##B##C##D
12217 #define X(N, L, C) S##N L
12230 enum neon_shape_class
12238 #define X(N, L, C) SC_##C
12240 static enum neon_shape_class neon_shape_class[] =
12258 /* Register widths of above. */
12259 static unsigned neon_shape_el_size[] =
12270 struct neon_shape_info
12273 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12276 #define S2(A,B) { SE_##A, SE_##B }
12277 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12278 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12280 #define X(N, L, C) { N, S##N L }
12282 static struct neon_shape_info neon_shape_tab[] =
12292 /* Bit masks used in type checking given instructions.
12293 'N_EQK' means the type must be the same as (or based on in some way) the key
12294 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12295 set, various other bits can be set as well in order to modify the meaning of
12296 the type constraint. */
12298 enum neon_type_mask
12321 N_KEY = 0x1000000, /* Key element (main type specifier). */
12322 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12323 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12324 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12325 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12326 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12327 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12328 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12329 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12330 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12332 N_MAX_NONSPECIAL = N_F64
12335 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12337 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12338 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12339 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12340 #define N_SUF_32 (N_SU_32 | N_F32)
12341 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12342 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12344 /* Pass this as the first type argument to neon_check_type to ignore types
12346 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12348 /* Select a "shape" for the current instruction (describing register types or
12349 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12350 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12351 function of operand parsing, so this function doesn't need to be called.
12352 Shapes should be listed in order of decreasing length. */
12354 static enum neon_shape
12355 neon_select_shape (enum neon_shape shape, ...)
12358 enum neon_shape first_shape = shape;
12360 /* Fix missing optional operands. FIXME: we don't know at this point how
12361 many arguments we should have, so this makes the assumption that we have
12362 > 1. This is true of all current Neon opcodes, I think, but may not be
12363 true in the future. */
12364 if (!inst.operands[1].present)
12365 inst.operands[1] = inst.operands[0];
12367 va_start (ap, shape);
12369 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12374 for (j = 0; j < neon_shape_tab[shape].els; j++)
12376 if (!inst.operands[j].present)
12382 switch (neon_shape_tab[shape].el[j])
12385 if (!(inst.operands[j].isreg
12386 && inst.operands[j].isvec
12387 && inst.operands[j].issingle
12388 && !inst.operands[j].isquad))
12393 if (!(inst.operands[j].isreg
12394 && inst.operands[j].isvec
12395 && !inst.operands[j].isquad
12396 && !inst.operands[j].issingle))
12401 if (!(inst.operands[j].isreg
12402 && !inst.operands[j].isvec))
12407 if (!(inst.operands[j].isreg
12408 && inst.operands[j].isvec
12409 && inst.operands[j].isquad
12410 && !inst.operands[j].issingle))
12415 if (!(!inst.operands[j].isreg
12416 && !inst.operands[j].isscalar))
12421 if (!(!inst.operands[j].isreg
12422 && inst.operands[j].isscalar))
12432 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12433 /* We've matched all the entries in the shape table, and we don't
12434 have any left over operands which have not been matched. */
12440 if (shape == NS_NULL && first_shape != NS_NULL)
12441 first_error (_("invalid instruction shape"));
12446 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12447 means the Q bit should be set). */
12450 neon_quad (enum neon_shape shape)
12452 return neon_shape_class[shape] == SC_QUAD;
12456 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12459 /* Allow modification to be made to types which are constrained to be
12460 based on the key element, based on bits set alongside N_EQK. */
12461 if ((typebits & N_EQK) != 0)
12463 if ((typebits & N_HLF) != 0)
12465 else if ((typebits & N_DBL) != 0)
12467 if ((typebits & N_SGN) != 0)
12468 *g_type = NT_signed;
12469 else if ((typebits & N_UNS) != 0)
12470 *g_type = NT_unsigned;
12471 else if ((typebits & N_INT) != 0)
12472 *g_type = NT_integer;
12473 else if ((typebits & N_FLT) != 0)
12474 *g_type = NT_float;
12475 else if ((typebits & N_SIZ) != 0)
12476 *g_type = NT_untyped;
12480 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12481 operand type, i.e. the single type specified in a Neon instruction when it
12482 is the only one given. */
12484 static struct neon_type_el
12485 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12487 struct neon_type_el dest = *key;
12489 gas_assert ((thisarg & N_EQK) != 0);
12491 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12496 /* Convert Neon type and size into compact bitmask representation. */
12498 static enum neon_type_mask
12499 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12506 case 8: return N_8;
12507 case 16: return N_16;
12508 case 32: return N_32;
12509 case 64: return N_64;
12517 case 8: return N_I8;
12518 case 16: return N_I16;
12519 case 32: return N_I32;
12520 case 64: return N_I64;
12528 case 16: return N_F16;
12529 case 32: return N_F32;
12530 case 64: return N_F64;
12538 case 8: return N_P8;
12539 case 16: return N_P16;
12547 case 8: return N_S8;
12548 case 16: return N_S16;
12549 case 32: return N_S32;
12550 case 64: return N_S64;
12558 case 8: return N_U8;
12559 case 16: return N_U16;
12560 case 32: return N_U32;
12561 case 64: return N_U64;
12572 /* Convert compact Neon bitmask type representation to a type and size. Only
12573 handles the case where a single bit is set in the mask. */
12576 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12577 enum neon_type_mask mask)
12579 if ((mask & N_EQK) != 0)
12582 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12584 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12586 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12588 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12593 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12595 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12596 *type = NT_unsigned;
12597 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12598 *type = NT_integer;
12599 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12600 *type = NT_untyped;
12601 else if ((mask & (N_P8 | N_P16)) != 0)
12603 else if ((mask & (N_F32 | N_F64)) != 0)
12611 /* Modify a bitmask of allowed types. This is only needed for type
12615 modify_types_allowed (unsigned allowed, unsigned mods)
12618 enum neon_el_type type;
12624 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12626 if (el_type_of_type_chk (&type, &size,
12627 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12629 neon_modify_type_size (mods, &type, &size);
12630 destmask |= type_chk_of_el_type (type, size);
12637 /* Check type and return type classification.
12638 The manual states (paraphrase): If one datatype is given, it indicates the
12640 - the second operand, if there is one
12641 - the operand, if there is no second operand
12642 - the result, if there are no operands.
12643 This isn't quite good enough though, so we use a concept of a "key" datatype
12644 which is set on a per-instruction basis, which is the one which matters when
12645 only one data type is written.
12646 Note: this function has side-effects (e.g. filling in missing operands). All
12647 Neon instructions should call it before performing bit encoding. */
12649 static struct neon_type_el
12650 neon_check_type (unsigned els, enum neon_shape ns, ...)
12653 unsigned i, pass, key_el = 0;
12654 unsigned types[NEON_MAX_TYPE_ELS];
12655 enum neon_el_type k_type = NT_invtype;
12656 unsigned k_size = -1u;
12657 struct neon_type_el badtype = {NT_invtype, -1};
12658 unsigned key_allowed = 0;
12660 /* Optional registers in Neon instructions are always (not) in operand 1.
12661 Fill in the missing operand here, if it was omitted. */
12662 if (els > 1 && !inst.operands[1].present)
12663 inst.operands[1] = inst.operands[0];
12665 /* Suck up all the varargs. */
12667 for (i = 0; i < els; i++)
12669 unsigned thisarg = va_arg (ap, unsigned);
12670 if (thisarg == N_IGNORE_TYPE)
12675 types[i] = thisarg;
12676 if ((thisarg & N_KEY) != 0)
12681 if (inst.vectype.elems > 0)
12682 for (i = 0; i < els; i++)
12683 if (inst.operands[i].vectype.type != NT_invtype)
12685 first_error (_("types specified in both the mnemonic and operands"));
12689 /* Duplicate inst.vectype elements here as necessary.
12690 FIXME: No idea if this is exactly the same as the ARM assembler,
12691 particularly when an insn takes one register and one non-register
12693 if (inst.vectype.elems == 1 && els > 1)
12696 inst.vectype.elems = els;
12697 inst.vectype.el[key_el] = inst.vectype.el[0];
12698 for (j = 0; j < els; j++)
12700 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12703 else if (inst.vectype.elems == 0 && els > 0)
12706 /* No types were given after the mnemonic, so look for types specified
12707 after each operand. We allow some flexibility here; as long as the
12708 "key" operand has a type, we can infer the others. */
12709 for (j = 0; j < els; j++)
12710 if (inst.operands[j].vectype.type != NT_invtype)
12711 inst.vectype.el[j] = inst.operands[j].vectype;
12713 if (inst.operands[key_el].vectype.type != NT_invtype)
12715 for (j = 0; j < els; j++)
12716 if (inst.operands[j].vectype.type == NT_invtype)
12717 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12722 first_error (_("operand types can't be inferred"));
12726 else if (inst.vectype.elems != els)
12728 first_error (_("type specifier has the wrong number of parts"));
12732 for (pass = 0; pass < 2; pass++)
12734 for (i = 0; i < els; i++)
12736 unsigned thisarg = types[i];
12737 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12738 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12739 enum neon_el_type g_type = inst.vectype.el[i].type;
12740 unsigned g_size = inst.vectype.el[i].size;
12742 /* Decay more-specific signed & unsigned types to sign-insensitive
12743 integer types if sign-specific variants are unavailable. */
12744 if ((g_type == NT_signed || g_type == NT_unsigned)
12745 && (types_allowed & N_SU_ALL) == 0)
12746 g_type = NT_integer;
12748 /* If only untyped args are allowed, decay any more specific types to
12749 them. Some instructions only care about signs for some element
12750 sizes, so handle that properly. */
12751 if ((g_size == 8 && (types_allowed & N_8) != 0)
12752 || (g_size == 16 && (types_allowed & N_16) != 0)
12753 || (g_size == 32 && (types_allowed & N_32) != 0)
12754 || (g_size == 64 && (types_allowed & N_64) != 0))
12755 g_type = NT_untyped;
12759 if ((thisarg & N_KEY) != 0)
12763 key_allowed = thisarg & ~N_KEY;
12768 if ((thisarg & N_VFP) != 0)
12770 enum neon_shape_el regshape;
12771 unsigned regwidth, match;
12773 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12776 first_error (_("invalid instruction shape"));
12779 regshape = neon_shape_tab[ns].el[i];
12780 regwidth = neon_shape_el_size[regshape];
12782 /* In VFP mode, operands must match register widths. If we
12783 have a key operand, use its width, else use the width of
12784 the current operand. */
12790 if (regwidth != match)
12792 first_error (_("operand size must match register width"));
12797 if ((thisarg & N_EQK) == 0)
12799 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12801 if ((given_type & types_allowed) == 0)
12803 first_error (_("bad type in Neon instruction"));
12809 enum neon_el_type mod_k_type = k_type;
12810 unsigned mod_k_size = k_size;
12811 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12812 if (g_type != mod_k_type || g_size != mod_k_size)
12814 first_error (_("inconsistent types in Neon instruction"));
12822 return inst.vectype.el[key_el];
12825 /* Neon-style VFP instruction forwarding. */
12827 /* Thumb VFP instructions have 0xE in the condition field. */
12830 do_vfp_cond_or_thumb (void)
12835 inst.instruction |= 0xe0000000;
12837 inst.instruction |= inst.cond << 28;
12840 /* Look up and encode a simple mnemonic, for use as a helper function for the
12841 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12842 etc. It is assumed that operand parsing has already been done, and that the
12843 operands are in the form expected by the given opcode (this isn't necessarily
12844 the same as the form in which they were parsed, hence some massaging must
12845 take place before this function is called).
12846 Checks current arch version against that in the looked-up opcode. */
12849 do_vfp_nsyn_opcode (const char *opname)
12851 const struct asm_opcode *opcode;
12853 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12858 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12859 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12866 inst.instruction = opcode->tvalue;
12867 opcode->tencode ();
12871 inst.instruction = (inst.cond << 28) | opcode->avalue;
12872 opcode->aencode ();
12877 do_vfp_nsyn_add_sub (enum neon_shape rs)
12879 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12884 do_vfp_nsyn_opcode ("fadds");
12886 do_vfp_nsyn_opcode ("fsubs");
12891 do_vfp_nsyn_opcode ("faddd");
12893 do_vfp_nsyn_opcode ("fsubd");
12897 /* Check operand types to see if this is a VFP instruction, and if so call
12901 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12903 enum neon_shape rs;
12904 struct neon_type_el et;
12909 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12910 et = neon_check_type (2, rs,
12911 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12915 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12916 et = neon_check_type (3, rs,
12917 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12924 if (et.type != NT_invtype)
12935 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12937 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12942 do_vfp_nsyn_opcode ("fmacs");
12944 do_vfp_nsyn_opcode ("fnmacs");
12949 do_vfp_nsyn_opcode ("fmacd");
12951 do_vfp_nsyn_opcode ("fnmacd");
12956 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12958 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12963 do_vfp_nsyn_opcode ("ffmas");
12965 do_vfp_nsyn_opcode ("ffnmas");
12970 do_vfp_nsyn_opcode ("ffmad");
12972 do_vfp_nsyn_opcode ("ffnmad");
12977 do_vfp_nsyn_mul (enum neon_shape rs)
12980 do_vfp_nsyn_opcode ("fmuls");
12982 do_vfp_nsyn_opcode ("fmuld");
12986 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12988 int is_neg = (inst.instruction & 0x80) != 0;
12989 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12994 do_vfp_nsyn_opcode ("fnegs");
12996 do_vfp_nsyn_opcode ("fabss");
13001 do_vfp_nsyn_opcode ("fnegd");
13003 do_vfp_nsyn_opcode ("fabsd");
13007 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13008 insns belong to Neon, and are handled elsewhere. */
13011 do_vfp_nsyn_ldm_stm (int is_dbmode)
13013 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13017 do_vfp_nsyn_opcode ("fldmdbs");
13019 do_vfp_nsyn_opcode ("fldmias");
13024 do_vfp_nsyn_opcode ("fstmdbs");
13026 do_vfp_nsyn_opcode ("fstmias");
13031 do_vfp_nsyn_sqrt (void)
13033 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13034 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13037 do_vfp_nsyn_opcode ("fsqrts");
13039 do_vfp_nsyn_opcode ("fsqrtd");
13043 do_vfp_nsyn_div (void)
13045 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13046 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13047 N_F32 | N_F64 | N_KEY | N_VFP);
13050 do_vfp_nsyn_opcode ("fdivs");
13052 do_vfp_nsyn_opcode ("fdivd");
13056 do_vfp_nsyn_nmul (void)
13058 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13059 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13060 N_F32 | N_F64 | N_KEY | N_VFP);
13064 NEON_ENCODE (SINGLE, inst);
13065 do_vfp_sp_dyadic ();
13069 NEON_ENCODE (DOUBLE, inst);
13070 do_vfp_dp_rd_rn_rm ();
13072 do_vfp_cond_or_thumb ();
13076 do_vfp_nsyn_cmp (void)
13078 if (inst.operands[1].isreg)
13080 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13081 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13085 NEON_ENCODE (SINGLE, inst);
13086 do_vfp_sp_monadic ();
13090 NEON_ENCODE (DOUBLE, inst);
13091 do_vfp_dp_rd_rm ();
13096 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13097 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13099 switch (inst.instruction & 0x0fffffff)
13102 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13105 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13113 NEON_ENCODE (SINGLE, inst);
13114 do_vfp_sp_compare_z ();
13118 NEON_ENCODE (DOUBLE, inst);
13122 do_vfp_cond_or_thumb ();
13126 nsyn_insert_sp (void)
13128 inst.operands[1] = inst.operands[0];
13129 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13130 inst.operands[0].reg = REG_SP;
13131 inst.operands[0].isreg = 1;
13132 inst.operands[0].writeback = 1;
13133 inst.operands[0].present = 1;
13137 do_vfp_nsyn_push (void)
13140 if (inst.operands[1].issingle)
13141 do_vfp_nsyn_opcode ("fstmdbs");
13143 do_vfp_nsyn_opcode ("fstmdbd");
13147 do_vfp_nsyn_pop (void)
13150 if (inst.operands[1].issingle)
13151 do_vfp_nsyn_opcode ("fldmias");
13153 do_vfp_nsyn_opcode ("fldmiad");
13156 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13157 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13160 neon_dp_fixup (struct arm_it* insn)
13162 unsigned int i = insn->instruction;
13167 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13178 insn->instruction = i;
13181 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13185 neon_logbits (unsigned x)
13187 return ffs (x) - 4;
13190 #define LOW4(R) ((R) & 0xf)
13191 #define HI1(R) (((R) >> 4) & 1)
13193 /* Encode insns with bit pattern:
13195 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13196 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13198 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13199 different meaning for some instruction. */
13202 neon_three_same (int isquad, int ubit, int size)
13204 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13205 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13206 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13207 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13208 inst.instruction |= LOW4 (inst.operands[2].reg);
13209 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13210 inst.instruction |= (isquad != 0) << 6;
13211 inst.instruction |= (ubit != 0) << 24;
13213 inst.instruction |= neon_logbits (size) << 20;
13215 neon_dp_fixup (&inst);
13218 /* Encode instructions of the form:
13220 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13221 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13223 Don't write size if SIZE == -1. */
13226 neon_two_same (int qbit, int ubit, int size)
13228 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13229 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13230 inst.instruction |= LOW4 (inst.operands[1].reg);
13231 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13232 inst.instruction |= (qbit != 0) << 6;
13233 inst.instruction |= (ubit != 0) << 24;
13236 inst.instruction |= neon_logbits (size) << 18;
13238 neon_dp_fixup (&inst);
13241 /* Neon instruction encoders, in approximate order of appearance. */
13244 do_neon_dyadic_i_su (void)
13246 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13247 struct neon_type_el et = neon_check_type (3, rs,
13248 N_EQK, N_EQK, N_SU_32 | N_KEY);
13249 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13253 do_neon_dyadic_i64_su (void)
13255 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13256 struct neon_type_el et = neon_check_type (3, rs,
13257 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13258 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13262 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13265 unsigned size = et.size >> 3;
13266 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13267 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13268 inst.instruction |= LOW4 (inst.operands[1].reg);
13269 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13270 inst.instruction |= (isquad != 0) << 6;
13271 inst.instruction |= immbits << 16;
13272 inst.instruction |= (size >> 3) << 7;
13273 inst.instruction |= (size & 0x7) << 19;
13275 inst.instruction |= (uval != 0) << 24;
13277 neon_dp_fixup (&inst);
13281 do_neon_shl_imm (void)
13283 if (!inst.operands[2].isreg)
13285 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13286 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13287 NEON_ENCODE (IMMED, inst);
13288 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13292 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13293 struct neon_type_el et = neon_check_type (3, rs,
13294 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13297 /* VSHL/VQSHL 3-register variants have syntax such as:
13299 whereas other 3-register operations encoded by neon_three_same have
13302 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13304 tmp = inst.operands[2].reg;
13305 inst.operands[2].reg = inst.operands[1].reg;
13306 inst.operands[1].reg = tmp;
13307 NEON_ENCODE (INTEGER, inst);
13308 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13313 do_neon_qshl_imm (void)
13315 if (!inst.operands[2].isreg)
13317 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13318 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13320 NEON_ENCODE (IMMED, inst);
13321 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13322 inst.operands[2].imm);
13326 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13327 struct neon_type_el et = neon_check_type (3, rs,
13328 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13331 /* See note in do_neon_shl_imm. */
13332 tmp = inst.operands[2].reg;
13333 inst.operands[2].reg = inst.operands[1].reg;
13334 inst.operands[1].reg = tmp;
13335 NEON_ENCODE (INTEGER, inst);
13336 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13341 do_neon_rshl (void)
13343 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13344 struct neon_type_el et = neon_check_type (3, rs,
13345 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13348 tmp = inst.operands[2].reg;
13349 inst.operands[2].reg = inst.operands[1].reg;
13350 inst.operands[1].reg = tmp;
13351 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13355 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13357 /* Handle .I8 pseudo-instructions. */
13360 /* Unfortunately, this will make everything apart from zero out-of-range.
13361 FIXME is this the intended semantics? There doesn't seem much point in
13362 accepting .I8 if so. */
13363 immediate |= immediate << 8;
13369 if (immediate == (immediate & 0x000000ff))
13371 *immbits = immediate;
13374 else if (immediate == (immediate & 0x0000ff00))
13376 *immbits = immediate >> 8;
13379 else if (immediate == (immediate & 0x00ff0000))
13381 *immbits = immediate >> 16;
13384 else if (immediate == (immediate & 0xff000000))
13386 *immbits = immediate >> 24;
13389 if ((immediate & 0xffff) != (immediate >> 16))
13390 goto bad_immediate;
13391 immediate &= 0xffff;
13394 if (immediate == (immediate & 0x000000ff))
13396 *immbits = immediate;
13399 else if (immediate == (immediate & 0x0000ff00))
13401 *immbits = immediate >> 8;
13406 first_error (_("immediate value out of range"));
13410 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13414 neon_bits_same_in_bytes (unsigned imm)
13416 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13417 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13418 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13419 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13422 /* For immediate of above form, return 0bABCD. */
13425 neon_squash_bits (unsigned imm)
13427 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13428 | ((imm & 0x01000000) >> 21);
13431 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13434 neon_qfloat_bits (unsigned imm)
13436 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13439 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13440 the instruction. *OP is passed as the initial value of the op field, and
13441 may be set to a different value depending on the constant (i.e.
13442 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13443 MVN). If the immediate looks like a repeated pattern then also
13444 try smaller element sizes. */
13447 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13448 unsigned *immbits, int *op, int size,
13449 enum neon_el_type type)
13451 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13453 if (type == NT_float && !float_p)
13456 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13458 if (size != 32 || *op == 1)
13460 *immbits = neon_qfloat_bits (immlo);
13466 if (neon_bits_same_in_bytes (immhi)
13467 && neon_bits_same_in_bytes (immlo))
13471 *immbits = (neon_squash_bits (immhi) << 4)
13472 | neon_squash_bits (immlo);
13477 if (immhi != immlo)
13483 if (immlo == (immlo & 0x000000ff))
13488 else if (immlo == (immlo & 0x0000ff00))
13490 *immbits = immlo >> 8;
13493 else if (immlo == (immlo & 0x00ff0000))
13495 *immbits = immlo >> 16;
13498 else if (immlo == (immlo & 0xff000000))
13500 *immbits = immlo >> 24;
13503 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13505 *immbits = (immlo >> 8) & 0xff;
13508 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13510 *immbits = (immlo >> 16) & 0xff;
13514 if ((immlo & 0xffff) != (immlo >> 16))
13521 if (immlo == (immlo & 0x000000ff))
13526 else if (immlo == (immlo & 0x0000ff00))
13528 *immbits = immlo >> 8;
13532 if ((immlo & 0xff) != (immlo >> 8))
13537 if (immlo == (immlo & 0x000000ff))
13539 /* Don't allow MVN with 8-bit immediate. */
13549 /* Write immediate bits [7:0] to the following locations:
13551 |28/24|23 19|18 16|15 4|3 0|
13552 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13554 This function is used by VMOV/VMVN/VORR/VBIC. */
13557 neon_write_immbits (unsigned immbits)
13559 inst.instruction |= immbits & 0xf;
13560 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13561 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13564 /* Invert low-order SIZE bits of XHI:XLO. */
13567 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13569 unsigned immlo = xlo ? *xlo : 0;
13570 unsigned immhi = xhi ? *xhi : 0;
13575 immlo = (~immlo) & 0xff;
13579 immlo = (~immlo) & 0xffff;
13583 immhi = (~immhi) & 0xffffffff;
13584 /* fall through. */
13587 immlo = (~immlo) & 0xffffffff;
13602 do_neon_logic (void)
13604 if (inst.operands[2].present && inst.operands[2].isreg)
13606 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13607 neon_check_type (3, rs, N_IGNORE_TYPE);
13608 /* U bit and size field were set as part of the bitmask. */
13609 NEON_ENCODE (INTEGER, inst);
13610 neon_three_same (neon_quad (rs), 0, -1);
13614 const int three_ops_form = (inst.operands[2].present
13615 && !inst.operands[2].isreg);
13616 const int immoperand = (three_ops_form ? 2 : 1);
13617 enum neon_shape rs = (three_ops_form
13618 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13619 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13620 struct neon_type_el et = neon_check_type (2, rs,
13621 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13622 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13626 if (et.type == NT_invtype)
13629 if (three_ops_form)
13630 constraint (inst.operands[0].reg != inst.operands[1].reg,
13631 _("first and second operands shall be the same register"));
13633 NEON_ENCODE (IMMED, inst);
13635 immbits = inst.operands[immoperand].imm;
13638 /* .i64 is a pseudo-op, so the immediate must be a repeating
13640 if (immbits != (inst.operands[immoperand].regisimm ?
13641 inst.operands[immoperand].reg : 0))
13643 /* Set immbits to an invalid constant. */
13644 immbits = 0xdeadbeef;
13651 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13655 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13659 /* Pseudo-instruction for VBIC. */
13660 neon_invert_size (&immbits, 0, et.size);
13661 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13665 /* Pseudo-instruction for VORR. */
13666 neon_invert_size (&immbits, 0, et.size);
13667 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13677 inst.instruction |= neon_quad (rs) << 6;
13678 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13679 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13680 inst.instruction |= cmode << 8;
13681 neon_write_immbits (immbits);
13683 neon_dp_fixup (&inst);
13688 do_neon_bitfield (void)
13690 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13691 neon_check_type (3, rs, N_IGNORE_TYPE);
13692 neon_three_same (neon_quad (rs), 0, -1);
13696 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13699 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13700 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13702 if (et.type == NT_float)
13704 NEON_ENCODE (FLOAT, inst);
13705 neon_three_same (neon_quad (rs), 0, -1);
13709 NEON_ENCODE (INTEGER, inst);
13710 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13715 do_neon_dyadic_if_su (void)
13717 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13721 do_neon_dyadic_if_su_d (void)
13723 /* This version only allow D registers, but that constraint is enforced during
13724 operand parsing so we don't need to do anything extra here. */
13725 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13729 do_neon_dyadic_if_i_d (void)
13731 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13732 affected if we specify unsigned args. */
13733 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13736 enum vfp_or_neon_is_neon_bits
13739 NEON_CHECK_ARCH = 2
13742 /* Call this function if an instruction which may have belonged to the VFP or
13743 Neon instruction sets, but turned out to be a Neon instruction (due to the
13744 operand types involved, etc.). We have to check and/or fix-up a couple of
13747 - Make sure the user hasn't attempted to make a Neon instruction
13749 - Alter the value in the condition code field if necessary.
13750 - Make sure that the arch supports Neon instructions.
13752 Which of these operations take place depends on bits from enum
13753 vfp_or_neon_is_neon_bits.
13755 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13756 current instruction's condition is COND_ALWAYS, the condition field is
13757 changed to inst.uncond_value. This is necessary because instructions shared
13758 between VFP and Neon may be conditional for the VFP variants only, and the
13759 unconditional Neon version must have, e.g., 0xF in the condition field. */
13762 vfp_or_neon_is_neon (unsigned check)
13764 /* Conditions are always legal in Thumb mode (IT blocks). */
13765 if (!thumb_mode && (check & NEON_CHECK_CC))
13767 if (inst.cond != COND_ALWAYS)
13769 first_error (_(BAD_COND));
13772 if (inst.uncond_value != -1)
13773 inst.instruction |= inst.uncond_value << 28;
13776 if ((check & NEON_CHECK_ARCH)
13777 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13779 first_error (_(BAD_FPU));
13787 do_neon_addsub_if_i (void)
13789 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13792 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13795 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13796 affected if we specify unsigned args. */
13797 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13800 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13802 V<op> A,B (A is operand 0, B is operand 2)
13807 so handle that case specially. */
13810 neon_exchange_operands (void)
13812 void *scratch = alloca (sizeof (inst.operands[0]));
13813 if (inst.operands[1].present)
13815 /* Swap operands[1] and operands[2]. */
13816 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13817 inst.operands[1] = inst.operands[2];
13818 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13822 inst.operands[1] = inst.operands[2];
13823 inst.operands[2] = inst.operands[0];
13828 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13830 if (inst.operands[2].isreg)
13833 neon_exchange_operands ();
13834 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13838 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13839 struct neon_type_el et = neon_check_type (2, rs,
13840 N_EQK | N_SIZ, immtypes | N_KEY);
13842 NEON_ENCODE (IMMED, inst);
13843 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13844 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13845 inst.instruction |= LOW4 (inst.operands[1].reg);
13846 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13847 inst.instruction |= neon_quad (rs) << 6;
13848 inst.instruction |= (et.type == NT_float) << 10;
13849 inst.instruction |= neon_logbits (et.size) << 18;
13851 neon_dp_fixup (&inst);
13858 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13862 do_neon_cmp_inv (void)
13864 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13870 neon_compare (N_IF_32, N_IF_32, FALSE);
13873 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13874 scalars, which are encoded in 5 bits, M : Rm.
13875 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13876 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13880 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13882 unsigned regno = NEON_SCALAR_REG (scalar);
13883 unsigned elno = NEON_SCALAR_INDEX (scalar);
13888 if (regno > 7 || elno > 3)
13890 return regno | (elno << 3);
13893 if (regno > 15 || elno > 1)
13895 return regno | (elno << 4);
13899 first_error (_("scalar out of range for multiply instruction"));
13905 /* Encode multiply / multiply-accumulate scalar instructions. */
13908 neon_mul_mac (struct neon_type_el et, int ubit)
13912 /* Give a more helpful error message if we have an invalid type. */
13913 if (et.type == NT_invtype)
13916 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13917 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13918 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13919 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13920 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13921 inst.instruction |= LOW4 (scalar);
13922 inst.instruction |= HI1 (scalar) << 5;
13923 inst.instruction |= (et.type == NT_float) << 8;
13924 inst.instruction |= neon_logbits (et.size) << 20;
13925 inst.instruction |= (ubit != 0) << 24;
13927 neon_dp_fixup (&inst);
13931 do_neon_mac_maybe_scalar (void)
13933 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13936 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13939 if (inst.operands[2].isscalar)
13941 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13942 struct neon_type_el et = neon_check_type (3, rs,
13943 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13944 NEON_ENCODE (SCALAR, inst);
13945 neon_mul_mac (et, neon_quad (rs));
13949 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13950 affected if we specify unsigned args. */
13951 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13956 do_neon_fmac (void)
13958 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13961 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13964 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13970 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13971 struct neon_type_el et = neon_check_type (3, rs,
13972 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13973 neon_three_same (neon_quad (rs), 0, et.size);
13976 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13977 same types as the MAC equivalents. The polynomial type for this instruction
13978 is encoded the same as the integer type. */
13983 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13986 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13989 if (inst.operands[2].isscalar)
13990 do_neon_mac_maybe_scalar ();
13992 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13996 do_neon_qdmulh (void)
13998 if (inst.operands[2].isscalar)
14000 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14001 struct neon_type_el et = neon_check_type (3, rs,
14002 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14003 NEON_ENCODE (SCALAR, inst);
14004 neon_mul_mac (et, neon_quad (rs));
14008 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14009 struct neon_type_el et = neon_check_type (3, rs,
14010 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14011 NEON_ENCODE (INTEGER, inst);
14012 /* The U bit (rounding) comes from bit mask. */
14013 neon_three_same (neon_quad (rs), 0, et.size);
14018 do_neon_fcmp_absolute (void)
14020 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14021 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14022 /* Size field comes from bit mask. */
14023 neon_three_same (neon_quad (rs), 1, -1);
14027 do_neon_fcmp_absolute_inv (void)
14029 neon_exchange_operands ();
14030 do_neon_fcmp_absolute ();
14034 do_neon_step (void)
14036 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14037 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14038 neon_three_same (neon_quad (rs), 0, -1);
14042 do_neon_abs_neg (void)
14044 enum neon_shape rs;
14045 struct neon_type_el et;
14047 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14050 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14053 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14054 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14056 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14057 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14058 inst.instruction |= LOW4 (inst.operands[1].reg);
14059 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14060 inst.instruction |= neon_quad (rs) << 6;
14061 inst.instruction |= (et.type == NT_float) << 10;
14062 inst.instruction |= neon_logbits (et.size) << 18;
14064 neon_dp_fixup (&inst);
14070 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14071 struct neon_type_el et = neon_check_type (2, rs,
14072 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14073 int imm = inst.operands[2].imm;
14074 constraint (imm < 0 || (unsigned)imm >= et.size,
14075 _("immediate out of range for insert"));
14076 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14082 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14083 struct neon_type_el et = neon_check_type (2, rs,
14084 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14085 int imm = inst.operands[2].imm;
14086 constraint (imm < 1 || (unsigned)imm > et.size,
14087 _("immediate out of range for insert"));
14088 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14092 do_neon_qshlu_imm (void)
14094 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14095 struct neon_type_el et = neon_check_type (2, rs,
14096 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14097 int imm = inst.operands[2].imm;
14098 constraint (imm < 0 || (unsigned)imm >= et.size,
14099 _("immediate out of range for shift"));
14100 /* Only encodes the 'U present' variant of the instruction.
14101 In this case, signed types have OP (bit 8) set to 0.
14102 Unsigned types have OP set to 1. */
14103 inst.instruction |= (et.type == NT_unsigned) << 8;
14104 /* The rest of the bits are the same as other immediate shifts. */
14105 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14109 do_neon_qmovn (void)
14111 struct neon_type_el et = neon_check_type (2, NS_DQ,
14112 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14113 /* Saturating move where operands can be signed or unsigned, and the
14114 destination has the same signedness. */
14115 NEON_ENCODE (INTEGER, inst);
14116 if (et.type == NT_unsigned)
14117 inst.instruction |= 0xc0;
14119 inst.instruction |= 0x80;
14120 neon_two_same (0, 1, et.size / 2);
14124 do_neon_qmovun (void)
14126 struct neon_type_el et = neon_check_type (2, NS_DQ,
14127 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14128 /* Saturating move with unsigned results. Operands must be signed. */
14129 NEON_ENCODE (INTEGER, inst);
14130 neon_two_same (0, 1, et.size / 2);
14134 do_neon_rshift_sat_narrow (void)
14136 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14137 or unsigned. If operands are unsigned, results must also be unsigned. */
14138 struct neon_type_el et = neon_check_type (2, NS_DQI,
14139 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14140 int imm = inst.operands[2].imm;
14141 /* This gets the bounds check, size encoding and immediate bits calculation
14145 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14146 VQMOVN.I<size> <Dd>, <Qm>. */
14149 inst.operands[2].present = 0;
14150 inst.instruction = N_MNEM_vqmovn;
14155 constraint (imm < 1 || (unsigned)imm > et.size,
14156 _("immediate out of range"));
14157 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14161 do_neon_rshift_sat_narrow_u (void)
14163 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14164 or unsigned. If operands are unsigned, results must also be unsigned. */
14165 struct neon_type_el et = neon_check_type (2, NS_DQI,
14166 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14167 int imm = inst.operands[2].imm;
14168 /* This gets the bounds check, size encoding and immediate bits calculation
14172 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14173 VQMOVUN.I<size> <Dd>, <Qm>. */
14176 inst.operands[2].present = 0;
14177 inst.instruction = N_MNEM_vqmovun;
14182 constraint (imm < 1 || (unsigned)imm > et.size,
14183 _("immediate out of range"));
14184 /* FIXME: The manual is kind of unclear about what value U should have in
14185 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14187 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14191 do_neon_movn (void)
14193 struct neon_type_el et = neon_check_type (2, NS_DQ,
14194 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14195 NEON_ENCODE (INTEGER, inst);
14196 neon_two_same (0, 1, et.size / 2);
14200 do_neon_rshift_narrow (void)
14202 struct neon_type_el et = neon_check_type (2, NS_DQI,
14203 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14204 int imm = inst.operands[2].imm;
14205 /* This gets the bounds check, size encoding and immediate bits calculation
14209 /* If immediate is zero then we are a pseudo-instruction for
14210 VMOVN.I<size> <Dd>, <Qm> */
14213 inst.operands[2].present = 0;
14214 inst.instruction = N_MNEM_vmovn;
14219 constraint (imm < 1 || (unsigned)imm > et.size,
14220 _("immediate out of range for narrowing operation"));
14221 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14225 do_neon_shll (void)
14227 /* FIXME: Type checking when lengthening. */
14228 struct neon_type_el et = neon_check_type (2, NS_QDI,
14229 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14230 unsigned imm = inst.operands[2].imm;
14232 if (imm == et.size)
14234 /* Maximum shift variant. */
14235 NEON_ENCODE (INTEGER, inst);
14236 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14237 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14238 inst.instruction |= LOW4 (inst.operands[1].reg);
14239 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14240 inst.instruction |= neon_logbits (et.size) << 18;
14242 neon_dp_fixup (&inst);
14246 /* A more-specific type check for non-max versions. */
14247 et = neon_check_type (2, NS_QDI,
14248 N_EQK | N_DBL, N_SU_32 | N_KEY);
14249 NEON_ENCODE (IMMED, inst);
14250 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14254 /* Check the various types for the VCVT instruction, and return which version
14255 the current instruction is. */
14258 neon_cvt_flavour (enum neon_shape rs)
14260 #define CVT_VAR(C,X,Y) \
14261 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14262 if (et.type != NT_invtype) \
14264 inst.error = NULL; \
14267 struct neon_type_el et;
14268 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14269 || rs == NS_FF) ? N_VFP : 0;
14270 /* The instruction versions which take an immediate take one register
14271 argument, which is extended to the width of the full register. Thus the
14272 "source" and "destination" registers must have the same width. Hack that
14273 here by making the size equal to the key (wider, in this case) operand. */
14274 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14276 CVT_VAR (0, N_S32, N_F32);
14277 CVT_VAR (1, N_U32, N_F32);
14278 CVT_VAR (2, N_F32, N_S32);
14279 CVT_VAR (3, N_F32, N_U32);
14280 /* Half-precision conversions. */
14281 CVT_VAR (4, N_F32, N_F16);
14282 CVT_VAR (5, N_F16, N_F32);
14286 /* VFP instructions. */
14287 CVT_VAR (6, N_F32, N_F64);
14288 CVT_VAR (7, N_F64, N_F32);
14289 CVT_VAR (8, N_S32, N_F64 | key);
14290 CVT_VAR (9, N_U32, N_F64 | key);
14291 CVT_VAR (10, N_F64 | key, N_S32);
14292 CVT_VAR (11, N_F64 | key, N_U32);
14293 /* VFP instructions with bitshift. */
14294 CVT_VAR (12, N_F32 | key, N_S16);
14295 CVT_VAR (13, N_F32 | key, N_U16);
14296 CVT_VAR (14, N_F64 | key, N_S16);
14297 CVT_VAR (15, N_F64 | key, N_U16);
14298 CVT_VAR (16, N_S16, N_F32 | key);
14299 CVT_VAR (17, N_U16, N_F32 | key);
14300 CVT_VAR (18, N_S16, N_F64 | key);
14301 CVT_VAR (19, N_U16, N_F64 | key);
14307 /* Neon-syntax VFP conversions. */
14310 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14312 const char *opname = 0;
14314 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14316 /* Conversions with immediate bitshift. */
14317 const char *enc[] =
14341 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14343 opname = enc[flavour];
14344 constraint (inst.operands[0].reg != inst.operands[1].reg,
14345 _("operands 0 and 1 must be the same register"));
14346 inst.operands[1] = inst.operands[2];
14347 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14352 /* Conversions without bitshift. */
14353 const char *enc[] =
14369 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14370 opname = enc[flavour];
14374 do_vfp_nsyn_opcode (opname);
14378 do_vfp_nsyn_cvtz (void)
14380 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14381 int flavour = neon_cvt_flavour (rs);
14382 const char *enc[] =
14396 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14397 do_vfp_nsyn_opcode (enc[flavour]);
14401 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14403 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14404 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14405 int flavour = neon_cvt_flavour (rs);
14407 /* PR11109: Handle round-to-zero for VCVT conversions. */
14409 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14410 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14411 && (rs == NS_FD || rs == NS_FF))
14413 do_vfp_nsyn_cvtz ();
14417 /* VFP rather than Neon conversions. */
14420 do_vfp_nsyn_cvt (rs, flavour);
14430 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14432 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14435 /* Fixed-point conversion with #0 immediate is encoded as an
14436 integer conversion. */
14437 if (inst.operands[2].present && inst.operands[2].imm == 0)
14439 immbits = 32 - inst.operands[2].imm;
14440 NEON_ENCODE (IMMED, inst);
14442 inst.instruction |= enctab[flavour];
14443 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14444 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14445 inst.instruction |= LOW4 (inst.operands[1].reg);
14446 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14447 inst.instruction |= neon_quad (rs) << 6;
14448 inst.instruction |= 1 << 21;
14449 inst.instruction |= immbits << 16;
14451 neon_dp_fixup (&inst);
14459 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14461 NEON_ENCODE (INTEGER, inst);
14463 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14467 inst.instruction |= enctab[flavour];
14469 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14470 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14471 inst.instruction |= LOW4 (inst.operands[1].reg);
14472 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14473 inst.instruction |= neon_quad (rs) << 6;
14474 inst.instruction |= 2 << 18;
14476 neon_dp_fixup (&inst);
14480 /* Half-precision conversions for Advanced SIMD -- neon. */
14485 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14487 as_bad (_("operand size must match register width"));
14492 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14494 as_bad (_("operand size must match register width"));
14499 inst.instruction = 0x3b60600;
14501 inst.instruction = 0x3b60700;
14503 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14504 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14505 inst.instruction |= LOW4 (inst.operands[1].reg);
14506 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14507 neon_dp_fixup (&inst);
14511 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14512 do_vfp_nsyn_cvt (rs, flavour);
14517 do_neon_cvtr (void)
14519 do_neon_cvt_1 (FALSE);
14525 do_neon_cvt_1 (TRUE);
14529 do_neon_cvtb (void)
14531 inst.instruction = 0xeb20a40;
14533 /* The sizes are attached to the mnemonic. */
14534 if (inst.vectype.el[0].type != NT_invtype
14535 && inst.vectype.el[0].size == 16)
14536 inst.instruction |= 0x00010000;
14538 /* Programmer's syntax: the sizes are attached to the operands. */
14539 else if (inst.operands[0].vectype.type != NT_invtype
14540 && inst.operands[0].vectype.size == 16)
14541 inst.instruction |= 0x00010000;
14543 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14544 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14545 do_vfp_cond_or_thumb ();
14550 do_neon_cvtt (void)
14553 inst.instruction |= 0x80;
14557 neon_move_immediate (void)
14559 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14560 struct neon_type_el et = neon_check_type (2, rs,
14561 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14562 unsigned immlo, immhi = 0, immbits;
14563 int op, cmode, float_p;
14565 constraint (et.type == NT_invtype,
14566 _("operand size must be specified for immediate VMOV"));
14568 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14569 op = (inst.instruction & (1 << 5)) != 0;
14571 immlo = inst.operands[1].imm;
14572 if (inst.operands[1].regisimm)
14573 immhi = inst.operands[1].reg;
14575 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14576 _("immediate has bits set outside the operand size"));
14578 float_p = inst.operands[1].immisfloat;
14580 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14581 et.size, et.type)) == FAIL)
14583 /* Invert relevant bits only. */
14584 neon_invert_size (&immlo, &immhi, et.size);
14585 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14586 with one or the other; those cases are caught by
14587 neon_cmode_for_move_imm. */
14589 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14590 &op, et.size, et.type)) == FAIL)
14592 first_error (_("immediate out of range"));
14597 inst.instruction &= ~(1 << 5);
14598 inst.instruction |= op << 5;
14600 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14601 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14602 inst.instruction |= neon_quad (rs) << 6;
14603 inst.instruction |= cmode << 8;
14605 neon_write_immbits (immbits);
14611 if (inst.operands[1].isreg)
14613 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14615 NEON_ENCODE (INTEGER, inst);
14616 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14617 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14618 inst.instruction |= LOW4 (inst.operands[1].reg);
14619 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14620 inst.instruction |= neon_quad (rs) << 6;
14624 NEON_ENCODE (IMMED, inst);
14625 neon_move_immediate ();
14628 neon_dp_fixup (&inst);
14631 /* Encode instructions of form:
14633 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14634 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14637 neon_mixed_length (struct neon_type_el et, unsigned size)
14639 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14640 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14641 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14642 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14643 inst.instruction |= LOW4 (inst.operands[2].reg);
14644 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14645 inst.instruction |= (et.type == NT_unsigned) << 24;
14646 inst.instruction |= neon_logbits (size) << 20;
14648 neon_dp_fixup (&inst);
14652 do_neon_dyadic_long (void)
14654 /* FIXME: Type checking for lengthening op. */
14655 struct neon_type_el et = neon_check_type (3, NS_QDD,
14656 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14657 neon_mixed_length (et, et.size);
14661 do_neon_abal (void)
14663 struct neon_type_el et = neon_check_type (3, NS_QDD,
14664 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14665 neon_mixed_length (et, et.size);
14669 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14671 if (inst.operands[2].isscalar)
14673 struct neon_type_el et = neon_check_type (3, NS_QDS,
14674 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14675 NEON_ENCODE (SCALAR, inst);
14676 neon_mul_mac (et, et.type == NT_unsigned);
14680 struct neon_type_el et = neon_check_type (3, NS_QDD,
14681 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14682 NEON_ENCODE (INTEGER, inst);
14683 neon_mixed_length (et, et.size);
14688 do_neon_mac_maybe_scalar_long (void)
14690 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14694 do_neon_dyadic_wide (void)
14696 struct neon_type_el et = neon_check_type (3, NS_QQD,
14697 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14698 neon_mixed_length (et, et.size);
14702 do_neon_dyadic_narrow (void)
14704 struct neon_type_el et = neon_check_type (3, NS_QDD,
14705 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14706 /* Operand sign is unimportant, and the U bit is part of the opcode,
14707 so force the operand type to integer. */
14708 et.type = NT_integer;
14709 neon_mixed_length (et, et.size / 2);
14713 do_neon_mul_sat_scalar_long (void)
14715 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14719 do_neon_vmull (void)
14721 if (inst.operands[2].isscalar)
14722 do_neon_mac_maybe_scalar_long ();
14725 struct neon_type_el et = neon_check_type (3, NS_QDD,
14726 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14727 if (et.type == NT_poly)
14728 NEON_ENCODE (POLY, inst);
14730 NEON_ENCODE (INTEGER, inst);
14731 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14732 zero. Should be OK as-is. */
14733 neon_mixed_length (et, et.size);
14740 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14741 struct neon_type_el et = neon_check_type (3, rs,
14742 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14743 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14745 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14746 _("shift out of range"));
14747 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14748 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14749 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14750 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14751 inst.instruction |= LOW4 (inst.operands[2].reg);
14752 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14753 inst.instruction |= neon_quad (rs) << 6;
14754 inst.instruction |= imm << 8;
14756 neon_dp_fixup (&inst);
14762 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14763 struct neon_type_el et = neon_check_type (2, rs,
14764 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14765 unsigned op = (inst.instruction >> 7) & 3;
14766 /* N (width of reversed regions) is encoded as part of the bitmask. We
14767 extract it here to check the elements to be reversed are smaller.
14768 Otherwise we'd get a reserved instruction. */
14769 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14770 gas_assert (elsize != 0);
14771 constraint (et.size >= elsize,
14772 _("elements must be smaller than reversal region"));
14773 neon_two_same (neon_quad (rs), 1, et.size);
14779 if (inst.operands[1].isscalar)
14781 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14782 struct neon_type_el et = neon_check_type (2, rs,
14783 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14784 unsigned sizebits = et.size >> 3;
14785 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14786 int logsize = neon_logbits (et.size);
14787 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14789 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14792 NEON_ENCODE (SCALAR, inst);
14793 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14794 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14795 inst.instruction |= LOW4 (dm);
14796 inst.instruction |= HI1 (dm) << 5;
14797 inst.instruction |= neon_quad (rs) << 6;
14798 inst.instruction |= x << 17;
14799 inst.instruction |= sizebits << 16;
14801 neon_dp_fixup (&inst);
14805 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14806 struct neon_type_el et = neon_check_type (2, rs,
14807 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14808 /* Duplicate ARM register to lanes of vector. */
14809 NEON_ENCODE (ARMREG, inst);
14812 case 8: inst.instruction |= 0x400000; break;
14813 case 16: inst.instruction |= 0x000020; break;
14814 case 32: inst.instruction |= 0x000000; break;
14817 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14818 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14819 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14820 inst.instruction |= neon_quad (rs) << 21;
14821 /* The encoding for this instruction is identical for the ARM and Thumb
14822 variants, except for the condition field. */
14823 do_vfp_cond_or_thumb ();
14827 /* VMOV has particularly many variations. It can be one of:
14828 0. VMOV<c><q> <Qd>, <Qm>
14829 1. VMOV<c><q> <Dd>, <Dm>
14830 (Register operations, which are VORR with Rm = Rn.)
14831 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14832 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14834 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14835 (ARM register to scalar.)
14836 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14837 (Two ARM registers to vector.)
14838 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14839 (Scalar to ARM register.)
14840 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14841 (Vector to two ARM registers.)
14842 8. VMOV.F32 <Sd>, <Sm>
14843 9. VMOV.F64 <Dd>, <Dm>
14844 (VFP register moves.)
14845 10. VMOV.F32 <Sd>, #imm
14846 11. VMOV.F64 <Dd>, #imm
14847 (VFP float immediate load.)
14848 12. VMOV <Rd>, <Sm>
14849 (VFP single to ARM reg.)
14850 13. VMOV <Sd>, <Rm>
14851 (ARM reg to VFP single.)
14852 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14853 (Two ARM regs to two VFP singles.)
14854 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14855 (Two VFP singles to two ARM regs.)
14857 These cases can be disambiguated using neon_select_shape, except cases 1/9
14858 and 3/11 which depend on the operand type too.
14860 All the encoded bits are hardcoded by this function.
14862 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14863 Cases 5, 7 may be used with VFPv2 and above.
14865 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14866 can specify a type where it doesn't make sense to, and is ignored). */
14871 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14872 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14874 struct neon_type_el et;
14875 const char *ldconst = 0;
14879 case NS_DD: /* case 1/9. */
14880 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14881 /* It is not an error here if no type is given. */
14883 if (et.type == NT_float && et.size == 64)
14885 do_vfp_nsyn_opcode ("fcpyd");
14888 /* fall through. */
14890 case NS_QQ: /* case 0/1. */
14892 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14894 /* The architecture manual I have doesn't explicitly state which
14895 value the U bit should have for register->register moves, but
14896 the equivalent VORR instruction has U = 0, so do that. */
14897 inst.instruction = 0x0200110;
14898 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14899 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14900 inst.instruction |= LOW4 (inst.operands[1].reg);
14901 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14902 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14903 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14904 inst.instruction |= neon_quad (rs) << 6;
14906 neon_dp_fixup (&inst);
14910 case NS_DI: /* case 3/11. */
14911 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14913 if (et.type == NT_float && et.size == 64)
14915 /* case 11 (fconstd). */
14916 ldconst = "fconstd";
14917 goto encode_fconstd;
14919 /* fall through. */
14921 case NS_QI: /* case 2/3. */
14922 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14924 inst.instruction = 0x0800010;
14925 neon_move_immediate ();
14926 neon_dp_fixup (&inst);
14929 case NS_SR: /* case 4. */
14931 unsigned bcdebits = 0;
14933 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14934 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14936 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14937 logsize = neon_logbits (et.size);
14939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14942 && et.size != 32, _(BAD_FPU));
14943 constraint (et.type == NT_invtype, _("bad type for scalar"));
14944 constraint (x >= 64 / et.size, _("scalar index out of range"));
14948 case 8: bcdebits = 0x8; break;
14949 case 16: bcdebits = 0x1; break;
14950 case 32: bcdebits = 0x0; break;
14954 bcdebits |= x << logsize;
14956 inst.instruction = 0xe000b10;
14957 do_vfp_cond_or_thumb ();
14958 inst.instruction |= LOW4 (dn) << 16;
14959 inst.instruction |= HI1 (dn) << 7;
14960 inst.instruction |= inst.operands[1].reg << 12;
14961 inst.instruction |= (bcdebits & 3) << 5;
14962 inst.instruction |= (bcdebits >> 2) << 21;
14966 case NS_DRR: /* case 5 (fmdrr). */
14967 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14970 inst.instruction = 0xc400b10;
14971 do_vfp_cond_or_thumb ();
14972 inst.instruction |= LOW4 (inst.operands[0].reg);
14973 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14974 inst.instruction |= inst.operands[1].reg << 12;
14975 inst.instruction |= inst.operands[2].reg << 16;
14978 case NS_RS: /* case 6. */
14981 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14982 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14983 unsigned abcdebits = 0;
14985 et = neon_check_type (2, NS_NULL,
14986 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14987 logsize = neon_logbits (et.size);
14989 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14992 && et.size != 32, _(BAD_FPU));
14993 constraint (et.type == NT_invtype, _("bad type for scalar"));
14994 constraint (x >= 64 / et.size, _("scalar index out of range"));
14998 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14999 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15000 case 32: abcdebits = 0x00; break;
15004 abcdebits |= x << logsize;
15005 inst.instruction = 0xe100b10;
15006 do_vfp_cond_or_thumb ();
15007 inst.instruction |= LOW4 (dn) << 16;
15008 inst.instruction |= HI1 (dn) << 7;
15009 inst.instruction |= inst.operands[0].reg << 12;
15010 inst.instruction |= (abcdebits & 3) << 5;
15011 inst.instruction |= (abcdebits >> 2) << 21;
15015 case NS_RRD: /* case 7 (fmrrd). */
15016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15019 inst.instruction = 0xc500b10;
15020 do_vfp_cond_or_thumb ();
15021 inst.instruction |= inst.operands[0].reg << 12;
15022 inst.instruction |= inst.operands[1].reg << 16;
15023 inst.instruction |= LOW4 (inst.operands[2].reg);
15024 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15027 case NS_FF: /* case 8 (fcpys). */
15028 do_vfp_nsyn_opcode ("fcpys");
15031 case NS_FI: /* case 10 (fconsts). */
15032 ldconst = "fconsts";
15034 if (is_quarter_float (inst.operands[1].imm))
15036 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15037 do_vfp_nsyn_opcode (ldconst);
15040 first_error (_("immediate out of range"));
15043 case NS_RF: /* case 12 (fmrs). */
15044 do_vfp_nsyn_opcode ("fmrs");
15047 case NS_FR: /* case 13 (fmsr). */
15048 do_vfp_nsyn_opcode ("fmsr");
15051 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15052 (one of which is a list), but we have parsed four. Do some fiddling to
15053 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15055 case NS_RRFF: /* case 14 (fmrrs). */
15056 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15057 _("VFP registers must be adjacent"));
15058 inst.operands[2].imm = 2;
15059 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15060 do_vfp_nsyn_opcode ("fmrrs");
15063 case NS_FFRR: /* case 15 (fmsrr). */
15064 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15065 _("VFP registers must be adjacent"));
15066 inst.operands[1] = inst.operands[2];
15067 inst.operands[2] = inst.operands[3];
15068 inst.operands[0].imm = 2;
15069 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15070 do_vfp_nsyn_opcode ("fmsrr");
15079 do_neon_rshift_round_imm (void)
15081 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15082 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15083 int imm = inst.operands[2].imm;
15085 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15088 inst.operands[2].present = 0;
15093 constraint (imm < 1 || (unsigned)imm > et.size,
15094 _("immediate out of range for shift"));
15095 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15100 do_neon_movl (void)
15102 struct neon_type_el et = neon_check_type (2, NS_QD,
15103 N_EQK | N_DBL, N_SU_32 | N_KEY);
15104 unsigned sizebits = et.size >> 3;
15105 inst.instruction |= sizebits << 19;
15106 neon_two_same (0, et.type == NT_unsigned, -1);
15112 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15113 struct neon_type_el et = neon_check_type (2, rs,
15114 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15115 NEON_ENCODE (INTEGER, inst);
15116 neon_two_same (neon_quad (rs), 1, et.size);
15120 do_neon_zip_uzp (void)
15122 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15123 struct neon_type_el et = neon_check_type (2, rs,
15124 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15125 if (rs == NS_DD && et.size == 32)
15127 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15128 inst.instruction = N_MNEM_vtrn;
15132 neon_two_same (neon_quad (rs), 1, et.size);
15136 do_neon_sat_abs_neg (void)
15138 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15139 struct neon_type_el et = neon_check_type (2, rs,
15140 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15141 neon_two_same (neon_quad (rs), 1, et.size);
15145 do_neon_pair_long (void)
15147 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15148 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15149 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15150 inst.instruction |= (et.type == NT_unsigned) << 7;
15151 neon_two_same (neon_quad (rs), 1, et.size);
15155 do_neon_recip_est (void)
15157 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15158 struct neon_type_el et = neon_check_type (2, rs,
15159 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15160 inst.instruction |= (et.type == NT_float) << 8;
15161 neon_two_same (neon_quad (rs), 1, et.size);
15167 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15168 struct neon_type_el et = neon_check_type (2, rs,
15169 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15170 neon_two_same (neon_quad (rs), 1, et.size);
15176 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15177 struct neon_type_el et = neon_check_type (2, rs,
15178 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15179 neon_two_same (neon_quad (rs), 1, et.size);
15185 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15186 struct neon_type_el et = neon_check_type (2, rs,
15187 N_EQK | N_INT, N_8 | N_KEY);
15188 neon_two_same (neon_quad (rs), 1, et.size);
15194 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15195 neon_two_same (neon_quad (rs), 1, -1);
15199 do_neon_tbl_tbx (void)
15201 unsigned listlenbits;
15202 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15204 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15206 first_error (_("bad list length for table lookup"));
15210 listlenbits = inst.operands[1].imm - 1;
15211 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15212 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15213 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15214 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15215 inst.instruction |= LOW4 (inst.operands[2].reg);
15216 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15217 inst.instruction |= listlenbits << 8;
15219 neon_dp_fixup (&inst);
15223 do_neon_ldm_stm (void)
15225 /* P, U and L bits are part of bitmask. */
15226 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15227 unsigned offsetbits = inst.operands[1].imm * 2;
15229 if (inst.operands[1].issingle)
15231 do_vfp_nsyn_ldm_stm (is_dbmode);
15235 constraint (is_dbmode && !inst.operands[0].writeback,
15236 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15238 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15239 _("register list must contain at least 1 and at most 16 "
15242 inst.instruction |= inst.operands[0].reg << 16;
15243 inst.instruction |= inst.operands[0].writeback << 21;
15244 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15245 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15247 inst.instruction |= offsetbits;
15249 do_vfp_cond_or_thumb ();
15253 do_neon_ldr_str (void)
15255 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15257 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15258 And is UNPREDICTABLE in thumb mode. */
15260 && inst.operands[1].reg == REG_PC
15261 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15263 if (!thumb_mode && warn_on_deprecated)
15264 as_warn (_("Use of PC here is deprecated"));
15266 inst.error = _("Use of PC here is UNPREDICTABLE");
15269 if (inst.operands[0].issingle)
15272 do_vfp_nsyn_opcode ("flds");
15274 do_vfp_nsyn_opcode ("fsts");
15279 do_vfp_nsyn_opcode ("fldd");
15281 do_vfp_nsyn_opcode ("fstd");
15285 /* "interleave" version also handles non-interleaving register VLD1/VST1
15289 do_neon_ld_st_interleave (void)
15291 struct neon_type_el et = neon_check_type (1, NS_NULL,
15292 N_8 | N_16 | N_32 | N_64);
15293 unsigned alignbits = 0;
15295 /* The bits in this table go:
15296 0: register stride of one (0) or two (1)
15297 1,2: register list length, minus one (1, 2, 3, 4).
15298 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15299 We use -1 for invalid entries. */
15300 const int typetable[] =
15302 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15303 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15304 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15305 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15309 if (et.type == NT_invtype)
15312 if (inst.operands[1].immisalign)
15313 switch (inst.operands[1].imm >> 8)
15315 case 64: alignbits = 1; break;
15317 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15318 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15319 goto bad_alignment;
15323 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15324 goto bad_alignment;
15329 first_error (_("bad alignment"));
15333 inst.instruction |= alignbits << 4;
15334 inst.instruction |= neon_logbits (et.size) << 6;
15336 /* Bits [4:6] of the immediate in a list specifier encode register stride
15337 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15338 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15339 up the right value for "type" in a table based on this value and the given
15340 list style, then stick it back. */
15341 idx = ((inst.operands[0].imm >> 4) & 7)
15342 | (((inst.instruction >> 8) & 3) << 3);
15344 typebits = typetable[idx];
15346 constraint (typebits == -1, _("bad list type for instruction"));
15348 inst.instruction &= ~0xf00;
15349 inst.instruction |= typebits << 8;
15352 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15353 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15354 otherwise. The variable arguments are a list of pairs of legal (size, align)
15355 values, terminated with -1. */
15358 neon_alignment_bit (int size, int align, int *do_align, ...)
15361 int result = FAIL, thissize, thisalign;
15363 if (!inst.operands[1].immisalign)
15369 va_start (ap, do_align);
15373 thissize = va_arg (ap, int);
15374 if (thissize == -1)
15376 thisalign = va_arg (ap, int);
15378 if (size == thissize && align == thisalign)
15381 while (result != SUCCESS);
15385 if (result == SUCCESS)
15388 first_error (_("unsupported alignment for instruction"));
15394 do_neon_ld_st_lane (void)
15396 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15397 int align_good, do_align = 0;
15398 int logsize = neon_logbits (et.size);
15399 int align = inst.operands[1].imm >> 8;
15400 int n = (inst.instruction >> 8) & 3;
15401 int max_el = 64 / et.size;
15403 if (et.type == NT_invtype)
15406 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15407 _("bad list length"));
15408 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15409 _("scalar index out of range"));
15410 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15412 _("stride of 2 unavailable when element size is 8"));
15416 case 0: /* VLD1 / VST1. */
15417 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15419 if (align_good == FAIL)
15423 unsigned alignbits = 0;
15426 case 16: alignbits = 0x1; break;
15427 case 32: alignbits = 0x3; break;
15430 inst.instruction |= alignbits << 4;
15434 case 1: /* VLD2 / VST2. */
15435 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15437 if (align_good == FAIL)
15440 inst.instruction |= 1 << 4;
15443 case 2: /* VLD3 / VST3. */
15444 constraint (inst.operands[1].immisalign,
15445 _("can't use alignment with this instruction"));
15448 case 3: /* VLD4 / VST4. */
15449 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15450 16, 64, 32, 64, 32, 128, -1);
15451 if (align_good == FAIL)
15455 unsigned alignbits = 0;
15458 case 8: alignbits = 0x1; break;
15459 case 16: alignbits = 0x1; break;
15460 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15463 inst.instruction |= alignbits << 4;
15470 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15471 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15472 inst.instruction |= 1 << (4 + logsize);
15474 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15475 inst.instruction |= logsize << 10;
15478 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15481 do_neon_ld_dup (void)
15483 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15484 int align_good, do_align = 0;
15486 if (et.type == NT_invtype)
15489 switch ((inst.instruction >> 8) & 3)
15491 case 0: /* VLD1. */
15492 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15493 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15494 &do_align, 16, 16, 32, 32, -1);
15495 if (align_good == FAIL)
15497 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15500 case 2: inst.instruction |= 1 << 5; break;
15501 default: first_error (_("bad list length")); return;
15503 inst.instruction |= neon_logbits (et.size) << 6;
15506 case 1: /* VLD2. */
15507 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15508 &do_align, 8, 16, 16, 32, 32, 64, -1);
15509 if (align_good == FAIL)
15511 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15512 _("bad list length"));
15513 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15514 inst.instruction |= 1 << 5;
15515 inst.instruction |= neon_logbits (et.size) << 6;
15518 case 2: /* VLD3. */
15519 constraint (inst.operands[1].immisalign,
15520 _("can't use alignment with this instruction"));
15521 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15522 _("bad list length"));
15523 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15524 inst.instruction |= 1 << 5;
15525 inst.instruction |= neon_logbits (et.size) << 6;
15528 case 3: /* VLD4. */
15530 int align = inst.operands[1].imm >> 8;
15531 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15532 16, 64, 32, 64, 32, 128, -1);
15533 if (align_good == FAIL)
15535 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15536 _("bad list length"));
15537 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15538 inst.instruction |= 1 << 5;
15539 if (et.size == 32 && align == 128)
15540 inst.instruction |= 0x3 << 6;
15542 inst.instruction |= neon_logbits (et.size) << 6;
15549 inst.instruction |= do_align << 4;
15552 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15553 apart from bits [11:4]. */
15556 do_neon_ldx_stx (void)
15558 if (inst.operands[1].isreg)
15559 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15561 switch (NEON_LANE (inst.operands[0].imm))
15563 case NEON_INTERLEAVE_LANES:
15564 NEON_ENCODE (INTERLV, inst);
15565 do_neon_ld_st_interleave ();
15568 case NEON_ALL_LANES:
15569 NEON_ENCODE (DUP, inst);
15574 NEON_ENCODE (LANE, inst);
15575 do_neon_ld_st_lane ();
15578 /* L bit comes from bit mask. */
15579 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15580 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15581 inst.instruction |= inst.operands[1].reg << 16;
15583 if (inst.operands[1].postind)
15585 int postreg = inst.operands[1].imm & 0xf;
15586 constraint (!inst.operands[1].immisreg,
15587 _("post-index must be a register"));
15588 constraint (postreg == 0xd || postreg == 0xf,
15589 _("bad register for post-index"));
15590 inst.instruction |= postreg;
15592 else if (inst.operands[1].writeback)
15594 inst.instruction |= 0xd;
15597 inst.instruction |= 0xf;
15600 inst.instruction |= 0xf9000000;
15602 inst.instruction |= 0xf4000000;
15605 /* Overall per-instruction processing. */
15607 /* We need to be able to fix up arbitrary expressions in some statements.
15608 This is so that we can handle symbols that are an arbitrary distance from
15609 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15610 which returns part of an address in a form which will be valid for
15611 a data instruction. We do this by pushing the expression into a symbol
15612 in the expr_section, and creating a fix for that. */
15615 fix_new_arm (fragS * frag,
15629 /* Create an absolute valued symbol, so we have something to
15630 refer to in the object file. Unfortunately for us, gas's
15631 generic expression parsing will already have folded out
15632 any use of .set foo/.type foo %function that may have
15633 been used to set type information of the target location,
15634 that's being specified symbolically. We have to presume
15635 the user knows what they are doing. */
15639 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15641 symbol = symbol_find_or_make (name);
15642 S_SET_SEGMENT (symbol, absolute_section);
15643 symbol_set_frag (symbol, &zero_address_frag);
15644 S_SET_VALUE (symbol, exp->X_add_number);
15645 exp->X_op = O_symbol;
15646 exp->X_add_symbol = symbol;
15647 exp->X_add_number = 0;
15653 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15654 (enum bfd_reloc_code_real) reloc);
15658 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15659 pc_rel, (enum bfd_reloc_code_real) reloc);
15663 /* Mark whether the fix is to a THUMB instruction, or an ARM
15665 new_fix->tc_fix_data = thumb_mode;
15668 /* Create a frg for an instruction requiring relaxation. */
15670 output_relax_insn (void)
15676 /* The size of the instruction is unknown, so tie the debug info to the
15677 start of the instruction. */
15678 dwarf2_emit_insn (0);
15680 switch (inst.reloc.exp.X_op)
15683 sym = inst.reloc.exp.X_add_symbol;
15684 offset = inst.reloc.exp.X_add_number;
15688 offset = inst.reloc.exp.X_add_number;
15691 sym = make_expr_symbol (&inst.reloc.exp);
15695 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15696 inst.relax, sym, offset, NULL/*offset, opcode*/);
15697 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15700 /* Write a 32-bit thumb instruction to buf. */
15702 put_thumb32_insn (char * buf, unsigned long insn)
15704 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15705 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15709 output_inst (const char * str)
15715 as_bad ("%s -- `%s'", inst.error, str);
15720 output_relax_insn ();
15723 if (inst.size == 0)
15726 to = frag_more (inst.size);
15727 /* PR 9814: Record the thumb mode into the current frag so that we know
15728 what type of NOP padding to use, if necessary. We override any previous
15729 setting so that if the mode has changed then the NOPS that we use will
15730 match the encoding of the last instruction in the frag. */
15731 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15733 if (thumb_mode && (inst.size > THUMB_SIZE))
15735 gas_assert (inst.size == (2 * THUMB_SIZE));
15736 put_thumb32_insn (to, inst.instruction);
15738 else if (inst.size > INSN_SIZE)
15740 gas_assert (inst.size == (2 * INSN_SIZE));
15741 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15742 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15745 md_number_to_chars (to, inst.instruction, inst.size);
15747 if (inst.reloc.type != BFD_RELOC_UNUSED)
15748 fix_new_arm (frag_now, to - frag_now->fr_literal,
15749 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15752 dwarf2_emit_insn (inst.size);
15756 output_it_inst (int cond, int mask, char * to)
15758 unsigned long instruction = 0xbf00;
15761 instruction |= mask;
15762 instruction |= cond << 4;
15766 to = frag_more (2);
15768 dwarf2_emit_insn (2);
15772 md_number_to_chars (to, instruction, 2);
15777 /* Tag values used in struct asm_opcode's tag field. */
15780 OT_unconditional, /* Instruction cannot be conditionalized.
15781 The ARM condition field is still 0xE. */
15782 OT_unconditionalF, /* Instruction cannot be conditionalized
15783 and carries 0xF in its ARM condition field. */
15784 OT_csuffix, /* Instruction takes a conditional suffix. */
15785 OT_csuffixF, /* Some forms of the instruction take a conditional
15786 suffix, others place 0xF where the condition field
15788 OT_cinfix3, /* Instruction takes a conditional infix,
15789 beginning at character index 3. (In
15790 unified mode, it becomes a suffix.) */
15791 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15792 tsts, cmps, cmns, and teqs. */
15793 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15794 character index 3, even in unified mode. Used for
15795 legacy instructions where suffix and infix forms
15796 may be ambiguous. */
15797 OT_csuf_or_in3, /* Instruction takes either a conditional
15798 suffix or an infix at character index 3. */
15799 OT_odd_infix_unc, /* This is the unconditional variant of an
15800 instruction that takes a conditional infix
15801 at an unusual position. In unified mode,
15802 this variant will accept a suffix. */
15803 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15804 are the conditional variants of instructions that
15805 take conditional infixes in unusual positions.
15806 The infix appears at character index
15807 (tag - OT_odd_infix_0). These are not accepted
15808 in unified mode. */
15811 /* Subroutine of md_assemble, responsible for looking up the primary
15812 opcode from the mnemonic the user wrote. STR points to the
15813 beginning of the mnemonic.
15815 This is not simply a hash table lookup, because of conditional
15816 variants. Most instructions have conditional variants, which are
15817 expressed with a _conditional affix_ to the mnemonic. If we were
15818 to encode each conditional variant as a literal string in the opcode
15819 table, it would have approximately 20,000 entries.
15821 Most mnemonics take this affix as a suffix, and in unified syntax,
15822 'most' is upgraded to 'all'. However, in the divided syntax, some
15823 instructions take the affix as an infix, notably the s-variants of
15824 the arithmetic instructions. Of those instructions, all but six
15825 have the infix appear after the third character of the mnemonic.
15827 Accordingly, the algorithm for looking up primary opcodes given
15830 1. Look up the identifier in the opcode table.
15831 If we find a match, go to step U.
15833 2. Look up the last two characters of the identifier in the
15834 conditions table. If we find a match, look up the first N-2
15835 characters of the identifier in the opcode table. If we
15836 find a match, go to step CE.
15838 3. Look up the fourth and fifth characters of the identifier in
15839 the conditions table. If we find a match, extract those
15840 characters from the identifier, and look up the remaining
15841 characters in the opcode table. If we find a match, go
15846 U. Examine the tag field of the opcode structure, in case this is
15847 one of the six instructions with its conditional infix in an
15848 unusual place. If it is, the tag tells us where to find the
15849 infix; look it up in the conditions table and set inst.cond
15850 accordingly. Otherwise, this is an unconditional instruction.
15851 Again set inst.cond accordingly. Return the opcode structure.
15853 CE. Examine the tag field to make sure this is an instruction that
15854 should receive a conditional suffix. If it is not, fail.
15855 Otherwise, set inst.cond from the suffix we already looked up,
15856 and return the opcode structure.
15858 CM. Examine the tag field to make sure this is an instruction that
15859 should receive a conditional infix after the third character.
15860 If it is not, fail. Otherwise, undo the edits to the current
15861 line of input and proceed as for case CE. */
15863 static const struct asm_opcode *
15864 opcode_lookup (char **str)
15868 const struct asm_opcode *opcode;
15869 const struct asm_cond *cond;
15872 /* Scan up to the end of the mnemonic, which must end in white space,
15873 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15874 for (base = end = *str; *end != '\0'; end++)
15875 if (*end == ' ' || *end == '.')
15881 /* Handle a possible width suffix and/or Neon type suffix. */
15886 /* The .w and .n suffixes are only valid if the unified syntax is in
15888 if (unified_syntax && end[1] == 'w')
15890 else if (unified_syntax && end[1] == 'n')
15895 inst.vectype.elems = 0;
15897 *str = end + offset;
15899 if (end[offset] == '.')
15901 /* See if we have a Neon type suffix (possible in either unified or
15902 non-unified ARM syntax mode). */
15903 if (parse_neon_type (&inst.vectype, str) == FAIL)
15906 else if (end[offset] != '\0' && end[offset] != ' ')
15912 /* Look for unaffixed or special-case affixed mnemonic. */
15913 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15918 if (opcode->tag < OT_odd_infix_0)
15920 inst.cond = COND_ALWAYS;
15924 if (warn_on_deprecated && unified_syntax)
15925 as_warn (_("conditional infixes are deprecated in unified syntax"));
15926 affix = base + (opcode->tag - OT_odd_infix_0);
15927 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15930 inst.cond = cond->value;
15934 /* Cannot have a conditional suffix on a mnemonic of less than two
15936 if (end - base < 3)
15939 /* Look for suffixed mnemonic. */
15941 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15942 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15944 if (opcode && cond)
15947 switch (opcode->tag)
15949 case OT_cinfix3_legacy:
15950 /* Ignore conditional suffixes matched on infix only mnemonics. */
15954 case OT_cinfix3_deprecated:
15955 case OT_odd_infix_unc:
15956 if (!unified_syntax)
15958 /* else fall through */
15962 case OT_csuf_or_in3:
15963 inst.cond = cond->value;
15966 case OT_unconditional:
15967 case OT_unconditionalF:
15969 inst.cond = cond->value;
15972 /* Delayed diagnostic. */
15973 inst.error = BAD_COND;
15974 inst.cond = COND_ALWAYS;
15983 /* Cannot have a usual-position infix on a mnemonic of less than
15984 six characters (five would be a suffix). */
15985 if (end - base < 6)
15988 /* Look for infixed mnemonic in the usual position. */
15990 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15994 memcpy (save, affix, 2);
15995 memmove (affix, affix + 2, (end - affix) - 2);
15996 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15998 memmove (affix + 2, affix, (end - affix) - 2);
15999 memcpy (affix, save, 2);
16002 && (opcode->tag == OT_cinfix3
16003 || opcode->tag == OT_cinfix3_deprecated
16004 || opcode->tag == OT_csuf_or_in3
16005 || opcode->tag == OT_cinfix3_legacy))
16008 if (warn_on_deprecated && unified_syntax
16009 && (opcode->tag == OT_cinfix3
16010 || opcode->tag == OT_cinfix3_deprecated))
16011 as_warn (_("conditional infixes are deprecated in unified syntax"));
16013 inst.cond = cond->value;
16020 /* This function generates an initial IT instruction, leaving its block
16021 virtually open for the new instructions. Eventually,
16022 the mask will be updated by now_it_add_mask () each time
16023 a new instruction needs to be included in the IT block.
16024 Finally, the block is closed with close_automatic_it_block ().
16025 The block closure can be requested either from md_assemble (),
16026 a tencode (), or due to a label hook. */
16029 new_automatic_it_block (int cond)
16031 now_it.state = AUTOMATIC_IT_BLOCK;
16032 now_it.mask = 0x18;
16034 now_it.block_length = 1;
16035 mapping_state (MAP_THUMB);
16036 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16039 /* Close an automatic IT block.
16040 See comments in new_automatic_it_block (). */
16043 close_automatic_it_block (void)
16045 now_it.mask = 0x10;
16046 now_it.block_length = 0;
16049 /* Update the mask of the current automatically-generated IT
16050 instruction. See comments in new_automatic_it_block (). */
16053 now_it_add_mask (int cond)
16055 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16056 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16057 | ((bitvalue) << (nbit)))
16058 const int resulting_bit = (cond & 1);
16060 now_it.mask &= 0xf;
16061 now_it.mask = SET_BIT_VALUE (now_it.mask,
16063 (5 - now_it.block_length));
16064 now_it.mask = SET_BIT_VALUE (now_it.mask,
16066 ((5 - now_it.block_length) - 1) );
16067 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16070 #undef SET_BIT_VALUE
16073 /* The IT blocks handling machinery is accessed through the these functions:
16074 it_fsm_pre_encode () from md_assemble ()
16075 set_it_insn_type () optional, from the tencode functions
16076 set_it_insn_type_last () ditto
16077 in_it_block () ditto
16078 it_fsm_post_encode () from md_assemble ()
16079 force_automatic_it_block_close () from label habdling functions
16082 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16083 initializing the IT insn type with a generic initial value depending
16084 on the inst.condition.
16085 2) During the tencode function, two things may happen:
16086 a) The tencode function overrides the IT insn type by
16087 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16088 b) The tencode function queries the IT block state by
16089 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16091 Both set_it_insn_type and in_it_block run the internal FSM state
16092 handling function (handle_it_state), because: a) setting the IT insn
16093 type may incur in an invalid state (exiting the function),
16094 and b) querying the state requires the FSM to be updated.
16095 Specifically we want to avoid creating an IT block for conditional
16096 branches, so it_fsm_pre_encode is actually a guess and we can't
16097 determine whether an IT block is required until the tencode () routine
16098 has decided what type of instruction this actually it.
16099 Because of this, if set_it_insn_type and in_it_block have to be used,
16100 set_it_insn_type has to be called first.
16102 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16103 determines the insn IT type depending on the inst.cond code.
16104 When a tencode () routine encodes an instruction that can be
16105 either outside an IT block, or, in the case of being inside, has to be
16106 the last one, set_it_insn_type_last () will determine the proper
16107 IT instruction type based on the inst.cond code. Otherwise,
16108 set_it_insn_type can be called for overriding that logic or
16109 for covering other cases.
16111 Calling handle_it_state () may not transition the IT block state to
16112 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16113 still queried. Instead, if the FSM determines that the state should
16114 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16115 after the tencode () function: that's what it_fsm_post_encode () does.
16117 Since in_it_block () calls the state handling function to get an
16118 updated state, an error may occur (due to invalid insns combination).
16119 In that case, inst.error is set.
16120 Therefore, inst.error has to be checked after the execution of
16121 the tencode () routine.
16123 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16124 any pending state change (if any) that didn't take place in
16125 handle_it_state () as explained above. */
16128 it_fsm_pre_encode (void)
16130 if (inst.cond != COND_ALWAYS)
16131 inst.it_insn_type = INSIDE_IT_INSN;
16133 inst.it_insn_type = OUTSIDE_IT_INSN;
16135 now_it.state_handled = 0;
16138 /* IT state FSM handling function. */
16141 handle_it_state (void)
16143 now_it.state_handled = 1;
16145 switch (now_it.state)
16147 case OUTSIDE_IT_BLOCK:
16148 switch (inst.it_insn_type)
16150 case OUTSIDE_IT_INSN:
16153 case INSIDE_IT_INSN:
16154 case INSIDE_IT_LAST_INSN:
16155 if (thumb_mode == 0)
16158 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16159 as_tsktsk (_("Warning: conditional outside an IT block"\
16164 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16165 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16167 /* Automatically generate the IT instruction. */
16168 new_automatic_it_block (inst.cond);
16169 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16170 close_automatic_it_block ();
16174 inst.error = BAD_OUT_IT;
16180 case IF_INSIDE_IT_LAST_INSN:
16181 case NEUTRAL_IT_INSN:
16185 now_it.state = MANUAL_IT_BLOCK;
16186 now_it.block_length = 0;
16191 case AUTOMATIC_IT_BLOCK:
16192 /* Three things may happen now:
16193 a) We should increment current it block size;
16194 b) We should close current it block (closing insn or 4 insns);
16195 c) We should close current it block and start a new one (due
16196 to incompatible conditions or
16197 4 insns-length block reached). */
16199 switch (inst.it_insn_type)
16201 case OUTSIDE_IT_INSN:
16202 /* The closure of the block shall happen immediatelly,
16203 so any in_it_block () call reports the block as closed. */
16204 force_automatic_it_block_close ();
16207 case INSIDE_IT_INSN:
16208 case INSIDE_IT_LAST_INSN:
16209 case IF_INSIDE_IT_LAST_INSN:
16210 now_it.block_length++;
16212 if (now_it.block_length > 4
16213 || !now_it_compatible (inst.cond))
16215 force_automatic_it_block_close ();
16216 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16217 new_automatic_it_block (inst.cond);
16221 now_it_add_mask (inst.cond);
16224 if (now_it.state == AUTOMATIC_IT_BLOCK
16225 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16226 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16227 close_automatic_it_block ();
16230 case NEUTRAL_IT_INSN:
16231 now_it.block_length++;
16233 if (now_it.block_length > 4)
16234 force_automatic_it_block_close ();
16236 now_it_add_mask (now_it.cc & 1);
16240 close_automatic_it_block ();
16241 now_it.state = MANUAL_IT_BLOCK;
16246 case MANUAL_IT_BLOCK:
16248 /* Check conditional suffixes. */
16249 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16252 now_it.mask &= 0x1f;
16253 is_last = (now_it.mask == 0x10);
16255 switch (inst.it_insn_type)
16257 case OUTSIDE_IT_INSN:
16258 inst.error = BAD_NOT_IT;
16261 case INSIDE_IT_INSN:
16262 if (cond != inst.cond)
16264 inst.error = BAD_IT_COND;
16269 case INSIDE_IT_LAST_INSN:
16270 case IF_INSIDE_IT_LAST_INSN:
16271 if (cond != inst.cond)
16273 inst.error = BAD_IT_COND;
16278 inst.error = BAD_BRANCH;
16283 case NEUTRAL_IT_INSN:
16284 /* The BKPT instruction is unconditional even in an IT block. */
16288 inst.error = BAD_IT_IT;
16299 it_fsm_post_encode (void)
16303 if (!now_it.state_handled)
16304 handle_it_state ();
16306 is_last = (now_it.mask == 0x10);
16309 now_it.state = OUTSIDE_IT_BLOCK;
16315 force_automatic_it_block_close (void)
16317 if (now_it.state == AUTOMATIC_IT_BLOCK)
16319 close_automatic_it_block ();
16320 now_it.state = OUTSIDE_IT_BLOCK;
16328 if (!now_it.state_handled)
16329 handle_it_state ();
16331 return now_it.state != OUTSIDE_IT_BLOCK;
16335 md_assemble (char *str)
16338 const struct asm_opcode * opcode;
16340 /* Align the previous label if needed. */
16341 if (last_label_seen != NULL)
16343 symbol_set_frag (last_label_seen, frag_now);
16344 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16345 S_SET_SEGMENT (last_label_seen, now_seg);
16348 memset (&inst, '\0', sizeof (inst));
16349 inst.reloc.type = BFD_RELOC_UNUSED;
16351 opcode = opcode_lookup (&p);
16354 /* It wasn't an instruction, but it might be a register alias of
16355 the form alias .req reg, or a Neon .dn/.qn directive. */
16356 if (! create_register_alias (str, p)
16357 && ! create_neon_reg_alias (str, p))
16358 as_bad (_("bad instruction `%s'"), str);
16363 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16364 as_warn (_("s suffix on comparison instruction is deprecated"));
16366 /* The value which unconditional instructions should have in place of the
16367 condition field. */
16368 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16372 arm_feature_set variant;
16374 variant = cpu_variant;
16375 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16376 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16377 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16378 /* Check that this instruction is supported for this CPU. */
16379 if (!opcode->tvariant
16380 || (thumb_mode == 1
16381 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16383 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16386 if (inst.cond != COND_ALWAYS && !unified_syntax
16387 && opcode->tencode != do_t_branch)
16389 as_bad (_("Thumb does not support conditional execution"));
16393 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16395 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16396 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16397 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16399 /* Two things are addressed here.
16400 1) Implicit require narrow instructions on Thumb-1.
16401 This avoids relaxation accidentally introducing Thumb-2
16403 2) Reject wide instructions in non Thumb-2 cores. */
16404 if (inst.size_req == 0)
16406 else if (inst.size_req == 4)
16408 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16414 inst.instruction = opcode->tvalue;
16416 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16418 /* Prepare the it_insn_type for those encodings that don't set
16420 it_fsm_pre_encode ();
16422 opcode->tencode ();
16424 it_fsm_post_encode ();
16427 if (!(inst.error || inst.relax))
16429 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16430 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16431 if (inst.size_req && inst.size_req != inst.size)
16433 as_bad (_("cannot honor width suffix -- `%s'"), str);
16438 /* Something has gone badly wrong if we try to relax a fixed size
16440 gas_assert (inst.size_req == 0 || !inst.relax);
16442 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16443 *opcode->tvariant);
16444 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16445 set those bits when Thumb-2 32-bit instructions are seen. ie.
16446 anything other than bl/blx and v6-M instructions.
16447 This is overly pessimistic for relaxable instructions. */
16448 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16450 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16451 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16452 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16455 check_neon_suffixes;
16459 mapping_state (MAP_THUMB);
16462 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16466 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16467 is_bx = (opcode->aencode == do_bx);
16469 /* Check that this instruction is supported for this CPU. */
16470 if (!(is_bx && fix_v4bx)
16471 && !(opcode->avariant &&
16472 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16474 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16479 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16483 inst.instruction = opcode->avalue;
16484 if (opcode->tag == OT_unconditionalF)
16485 inst.instruction |= 0xF << 28;
16487 inst.instruction |= inst.cond << 28;
16488 inst.size = INSN_SIZE;
16489 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16491 it_fsm_pre_encode ();
16492 opcode->aencode ();
16493 it_fsm_post_encode ();
16495 /* Arm mode bx is marked as both v4T and v5 because it's still required
16496 on a hypothetical non-thumb v5 core. */
16498 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16500 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16501 *opcode->avariant);
16503 check_neon_suffixes;
16507 mapping_state (MAP_ARM);
16512 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16520 check_it_blocks_finished (void)
16525 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16526 if (seg_info (sect)->tc_segment_info_data.current_it.state
16527 == MANUAL_IT_BLOCK)
16529 as_warn (_("section '%s' finished with an open IT block."),
16533 if (now_it.state == MANUAL_IT_BLOCK)
16534 as_warn (_("file finished with an open IT block."));
16538 /* Various frobbings of labels and their addresses. */
16541 arm_start_line_hook (void)
16543 last_label_seen = NULL;
16547 arm_frob_label (symbolS * sym)
16549 last_label_seen = sym;
16551 ARM_SET_THUMB (sym, thumb_mode);
16553 #if defined OBJ_COFF || defined OBJ_ELF
16554 ARM_SET_INTERWORK (sym, support_interwork);
16557 force_automatic_it_block_close ();
16559 /* Note - do not allow local symbols (.Lxxx) to be labelled
16560 as Thumb functions. This is because these labels, whilst
16561 they exist inside Thumb code, are not the entry points for
16562 possible ARM->Thumb calls. Also, these labels can be used
16563 as part of a computed goto or switch statement. eg gcc
16564 can generate code that looks like this:
16566 ldr r2, [pc, .Laaa]
16576 The first instruction loads the address of the jump table.
16577 The second instruction converts a table index into a byte offset.
16578 The third instruction gets the jump address out of the table.
16579 The fourth instruction performs the jump.
16581 If the address stored at .Laaa is that of a symbol which has the
16582 Thumb_Func bit set, then the linker will arrange for this address
16583 to have the bottom bit set, which in turn would mean that the
16584 address computation performed by the third instruction would end
16585 up with the bottom bit set. Since the ARM is capable of unaligned
16586 word loads, the instruction would then load the incorrect address
16587 out of the jump table, and chaos would ensue. */
16588 if (label_is_thumb_function_name
16589 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16590 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16592 /* When the address of a Thumb function is taken the bottom
16593 bit of that address should be set. This will allow
16594 interworking between Arm and Thumb functions to work
16597 THUMB_SET_FUNC (sym, 1);
16599 label_is_thumb_function_name = FALSE;
16602 dwarf2_emit_label (sym);
16606 arm_data_in_code (void)
16608 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16610 *input_line_pointer = '/';
16611 input_line_pointer += 5;
16612 *input_line_pointer = 0;
16620 arm_canonicalize_symbol_name (char * name)
16624 if (thumb_mode && (len = strlen (name)) > 5
16625 && streq (name + len - 5, "/data"))
16626 *(name + len - 5) = 0;
16631 /* Table of all register names defined by default. The user can
16632 define additional names with .req. Note that all register names
16633 should appear in both upper and lowercase variants. Some registers
16634 also have mixed-case names. */
16636 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16637 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16638 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16639 #define REGSET(p,t) \
16640 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16641 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16642 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16643 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16644 #define REGSETH(p,t) \
16645 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16646 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16647 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16648 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16649 #define REGSET2(p,t) \
16650 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16651 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16652 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16653 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16654 #define SPLRBANK(base,bank,t) \
16655 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16656 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16657 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16658 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16659 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16660 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16662 static const struct reg_entry reg_names[] =
16664 /* ARM integer registers. */
16665 REGSET(r, RN), REGSET(R, RN),
16667 /* ATPCS synonyms. */
16668 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16669 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16670 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16672 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16673 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16674 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16676 /* Well-known aliases. */
16677 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16678 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16680 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16681 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16683 /* Coprocessor numbers. */
16684 REGSET(p, CP), REGSET(P, CP),
16686 /* Coprocessor register numbers. The "cr" variants are for backward
16688 REGSET(c, CN), REGSET(C, CN),
16689 REGSET(cr, CN), REGSET(CR, CN),
16691 /* ARM banked registers. */
16692 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16693 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16694 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16695 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16696 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16697 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16698 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16700 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16701 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16702 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16703 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16704 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16705 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16706 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16707 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16709 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16710 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16711 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16712 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16713 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16714 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16715 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16716 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16717 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16719 /* FPA registers. */
16720 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16721 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16723 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16724 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16726 /* VFP SP registers. */
16727 REGSET(s,VFS), REGSET(S,VFS),
16728 REGSETH(s,VFS), REGSETH(S,VFS),
16730 /* VFP DP Registers. */
16731 REGSET(d,VFD), REGSET(D,VFD),
16732 /* Extra Neon DP registers. */
16733 REGSETH(d,VFD), REGSETH(D,VFD),
16735 /* Neon QP registers. */
16736 REGSET2(q,NQ), REGSET2(Q,NQ),
16738 /* VFP control registers. */
16739 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16740 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16741 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16742 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16743 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16744 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16746 /* Maverick DSP coprocessor registers. */
16747 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16748 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16750 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16751 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16752 REGDEF(dspsc,0,DSPSC),
16754 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16755 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16756 REGDEF(DSPSC,0,DSPSC),
16758 /* iWMMXt data registers - p0, c0-15. */
16759 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16761 /* iWMMXt control registers - p1, c0-3. */
16762 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16763 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16764 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16765 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16767 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16768 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16769 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16770 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16771 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16773 /* XScale accumulator registers. */
16774 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16780 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16781 within psr_required_here. */
16782 static const struct asm_psr psrs[] =
16784 /* Backward compatibility notation. Note that "all" is no longer
16785 truly all possible PSR bits. */
16786 {"all", PSR_c | PSR_f},
16790 /* Individual flags. */
16796 /* Combinations of flags. */
16797 {"fs", PSR_f | PSR_s},
16798 {"fx", PSR_f | PSR_x},
16799 {"fc", PSR_f | PSR_c},
16800 {"sf", PSR_s | PSR_f},
16801 {"sx", PSR_s | PSR_x},
16802 {"sc", PSR_s | PSR_c},
16803 {"xf", PSR_x | PSR_f},
16804 {"xs", PSR_x | PSR_s},
16805 {"xc", PSR_x | PSR_c},
16806 {"cf", PSR_c | PSR_f},
16807 {"cs", PSR_c | PSR_s},
16808 {"cx", PSR_c | PSR_x},
16809 {"fsx", PSR_f | PSR_s | PSR_x},
16810 {"fsc", PSR_f | PSR_s | PSR_c},
16811 {"fxs", PSR_f | PSR_x | PSR_s},
16812 {"fxc", PSR_f | PSR_x | PSR_c},
16813 {"fcs", PSR_f | PSR_c | PSR_s},
16814 {"fcx", PSR_f | PSR_c | PSR_x},
16815 {"sfx", PSR_s | PSR_f | PSR_x},
16816 {"sfc", PSR_s | PSR_f | PSR_c},
16817 {"sxf", PSR_s | PSR_x | PSR_f},
16818 {"sxc", PSR_s | PSR_x | PSR_c},
16819 {"scf", PSR_s | PSR_c | PSR_f},
16820 {"scx", PSR_s | PSR_c | PSR_x},
16821 {"xfs", PSR_x | PSR_f | PSR_s},
16822 {"xfc", PSR_x | PSR_f | PSR_c},
16823 {"xsf", PSR_x | PSR_s | PSR_f},
16824 {"xsc", PSR_x | PSR_s | PSR_c},
16825 {"xcf", PSR_x | PSR_c | PSR_f},
16826 {"xcs", PSR_x | PSR_c | PSR_s},
16827 {"cfs", PSR_c | PSR_f | PSR_s},
16828 {"cfx", PSR_c | PSR_f | PSR_x},
16829 {"csf", PSR_c | PSR_s | PSR_f},
16830 {"csx", PSR_c | PSR_s | PSR_x},
16831 {"cxf", PSR_c | PSR_x | PSR_f},
16832 {"cxs", PSR_c | PSR_x | PSR_s},
16833 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16834 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16835 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16836 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16837 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16838 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16839 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16840 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16841 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16842 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16843 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16844 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16845 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16846 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16847 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16848 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16849 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16850 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16851 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16852 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16853 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16854 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16855 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16856 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16859 /* Table of V7M psr names. */
16860 static const struct asm_psr v7m_psrs[] =
16862 {"apsr", 0 }, {"APSR", 0 },
16863 {"iapsr", 1 }, {"IAPSR", 1 },
16864 {"eapsr", 2 }, {"EAPSR", 2 },
16865 {"psr", 3 }, {"PSR", 3 },
16866 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16867 {"ipsr", 5 }, {"IPSR", 5 },
16868 {"epsr", 6 }, {"EPSR", 6 },
16869 {"iepsr", 7 }, {"IEPSR", 7 },
16870 {"msp", 8 }, {"MSP", 8 },
16871 {"psp", 9 }, {"PSP", 9 },
16872 {"primask", 16}, {"PRIMASK", 16},
16873 {"basepri", 17}, {"BASEPRI", 17},
16874 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16875 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16876 {"faultmask", 19}, {"FAULTMASK", 19},
16877 {"control", 20}, {"CONTROL", 20}
16880 /* Table of all shift-in-operand names. */
16881 static const struct asm_shift_name shift_names [] =
16883 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16884 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16885 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16886 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16887 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16888 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16891 /* Table of all explicit relocation names. */
16893 static struct reloc_entry reloc_names[] =
16895 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16896 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16897 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16898 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16899 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16900 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16901 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16902 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16903 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16904 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16905 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16906 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16907 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16908 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16909 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16910 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16911 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16912 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16916 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16917 static const struct asm_cond conds[] =
16921 {"cs", 0x2}, {"hs", 0x2},
16922 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16936 static struct asm_barrier_opt barrier_opt_names[] =
16938 { "sy", 0xf }, { "SY", 0xf },
16939 { "un", 0x7 }, { "UN", 0x7 },
16940 { "st", 0xe }, { "ST", 0xe },
16941 { "unst", 0x6 }, { "UNST", 0x6 },
16942 { "ish", 0xb }, { "ISH", 0xb },
16943 { "sh", 0xb }, { "SH", 0xb },
16944 { "ishst", 0xa }, { "ISHST", 0xa },
16945 { "shst", 0xa }, { "SHST", 0xa },
16946 { "nsh", 0x7 }, { "NSH", 0x7 },
16947 { "nshst", 0x6 }, { "NSHST", 0x6 },
16948 { "osh", 0x3 }, { "OSH", 0x3 },
16949 { "oshst", 0x2 }, { "OSHST", 0x2 }
16952 /* Table of ARM-format instructions. */
16954 /* Macros for gluing together operand strings. N.B. In all cases
16955 other than OPS0, the trailing OP_stop comes from default
16956 zero-initialization of the unspecified elements of the array. */
16957 #define OPS0() { OP_stop, }
16958 #define OPS1(a) { OP_##a, }
16959 #define OPS2(a,b) { OP_##a,OP_##b, }
16960 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16961 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16962 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16963 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16965 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16966 This is useful when mixing operands for ARM and THUMB, i.e. using the
16967 MIX_ARM_THUMB_OPERANDS macro.
16968 In order to use these macros, prefix the number of operands with _
16970 #define OPS_1(a) { a, }
16971 #define OPS_2(a,b) { a,b, }
16972 #define OPS_3(a,b,c) { a,b,c, }
16973 #define OPS_4(a,b,c,d) { a,b,c,d, }
16974 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16975 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16977 /* These macros abstract out the exact format of the mnemonic table and
16978 save some repeated characters. */
16980 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16981 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16982 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16983 THUMB_VARIANT, do_##ae, do_##te }
16985 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16986 a T_MNEM_xyz enumerator. */
16987 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16988 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16989 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16990 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16992 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16993 infix after the third character. */
16994 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16995 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16996 THUMB_VARIANT, do_##ae, do_##te }
16997 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16998 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16999 THUMB_VARIANT, do_##ae, do_##te }
17000 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17001 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17002 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17003 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17004 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17005 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17006 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17007 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17009 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17010 appear in the condition table. */
17011 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17012 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17013 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17015 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17016 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17017 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17018 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17019 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17020 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17021 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17022 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17023 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17024 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17025 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17026 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17027 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17028 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17029 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17030 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17031 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17032 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17033 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17034 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17036 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17037 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17038 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17039 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17041 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17042 field is still 0xE. Many of the Thumb variants can be executed
17043 conditionally, so this is checked separately. */
17044 #define TUE(mnem, op, top, nops, ops, ae, te) \
17045 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17046 THUMB_VARIANT, do_##ae, do_##te }
17048 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17049 condition code field. */
17050 #define TUF(mnem, op, top, nops, ops, ae, te) \
17051 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17052 THUMB_VARIANT, do_##ae, do_##te }
17054 /* ARM-only variants of all the above. */
17055 #define CE(mnem, op, nops, ops, ae) \
17056 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17058 #define C3(mnem, op, nops, ops, ae) \
17059 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17061 /* Legacy mnemonics that always have conditional infix after the third
17063 #define CL(mnem, op, nops, ops, ae) \
17064 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17065 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17067 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17068 #define cCE(mnem, op, nops, ops, ae) \
17069 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17071 /* Legacy coprocessor instructions where conditional infix and conditional
17072 suffix are ambiguous. For consistency this includes all FPA instructions,
17073 not just the potentially ambiguous ones. */
17074 #define cCL(mnem, op, nops, ops, ae) \
17075 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17076 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17078 /* Coprocessor, takes either a suffix or a position-3 infix
17079 (for an FPA corner case). */
17080 #define C3E(mnem, op, nops, ops, ae) \
17081 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17082 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17084 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17085 { m1 #m2 m3, OPS##nops ops, \
17086 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17087 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17089 #define CM(m1, m2, op, nops, ops, ae) \
17090 xCM_ (m1, , m2, op, nops, ops, ae), \
17091 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17092 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17093 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17094 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17095 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17096 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17097 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17098 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17099 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17100 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17101 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17102 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17103 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17104 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17105 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17106 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17107 xCM_ (m1, le, m2, op, nops, ops, ae), \
17108 xCM_ (m1, al, m2, op, nops, ops, ae)
17110 #define UE(mnem, op, nops, ops, ae) \
17111 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17113 #define UF(mnem, op, nops, ops, ae) \
17114 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17116 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17117 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17118 use the same encoding function for each. */
17119 #define NUF(mnem, op, nops, ops, enc) \
17120 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17121 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17123 /* Neon data processing, version which indirects through neon_enc_tab for
17124 the various overloaded versions of opcodes. */
17125 #define nUF(mnem, op, nops, ops, enc) \
17126 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17127 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17129 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17131 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17132 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17133 THUMB_VARIANT, do_##enc, do_##enc }
17135 #define NCE(mnem, op, nops, ops, enc) \
17136 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17138 #define NCEF(mnem, op, nops, ops, enc) \
17139 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17141 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17142 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17143 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17144 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17146 #define nCE(mnem, op, nops, ops, enc) \
17147 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17149 #define nCEF(mnem, op, nops, ops, enc) \
17150 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17154 static const struct asm_opcode insns[] =
17156 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17157 #define THUMB_VARIANT &arm_ext_v4t
17158 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17159 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17160 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17161 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17162 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17163 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17164 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17165 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17166 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17167 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17168 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17169 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17170 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17171 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17172 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17173 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17175 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17176 for setting PSR flag bits. They are obsolete in V6 and do not
17177 have Thumb equivalents. */
17178 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17179 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17180 CL("tstp", 110f000, 2, (RR, SH), cmp),
17181 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17182 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17183 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17184 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17185 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17186 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17188 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17189 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17190 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17191 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17193 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17194 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17195 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17197 OP_ADDRGLDR),ldst, t_ldst),
17198 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17200 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17201 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17202 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17203 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17204 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17205 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17207 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17208 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17209 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17210 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17213 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17214 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17215 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17217 /* Thumb-compatibility pseudo ops. */
17218 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17219 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17220 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17221 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17222 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17223 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17224 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17225 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17226 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17227 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17228 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17229 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17231 /* These may simplify to neg. */
17232 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17233 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17235 #undef THUMB_VARIANT
17236 #define THUMB_VARIANT & arm_ext_v6
17238 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17240 /* V1 instructions with no Thumb analogue prior to V6T2. */
17241 #undef THUMB_VARIANT
17242 #define THUMB_VARIANT & arm_ext_v6t2
17244 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17245 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17246 CL("teqp", 130f000, 2, (RR, SH), cmp),
17248 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17249 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17250 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17251 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17253 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17254 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17256 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17257 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17259 /* V1 instructions with no Thumb analogue at all. */
17260 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17261 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17263 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17264 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17265 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17266 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17267 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17268 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17269 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17270 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17273 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17274 #undef THUMB_VARIANT
17275 #define THUMB_VARIANT & arm_ext_v4t
17277 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17278 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17280 #undef THUMB_VARIANT
17281 #define THUMB_VARIANT & arm_ext_v6t2
17283 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17284 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17286 /* Generic coprocessor instructions. */
17287 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17288 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17289 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17290 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17291 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17292 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17293 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17296 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17298 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17299 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17302 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17303 #undef THUMB_VARIANT
17304 #define THUMB_VARIANT & arm_ext_msr
17306 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17307 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17310 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17311 #undef THUMB_VARIANT
17312 #define THUMB_VARIANT & arm_ext_v6t2
17314 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17315 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17316 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17317 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17318 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17319 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17320 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17321 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17324 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17325 #undef THUMB_VARIANT
17326 #define THUMB_VARIANT & arm_ext_v4t
17328 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17329 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17330 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17331 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17332 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17333 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17336 #define ARM_VARIANT & arm_ext_v4t_5
17338 /* ARM Architecture 4T. */
17339 /* Note: bx (and blx) are required on V5, even if the processor does
17340 not support Thumb. */
17341 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17344 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17345 #undef THUMB_VARIANT
17346 #define THUMB_VARIANT & arm_ext_v5t
17348 /* Note: blx has 2 variants; the .value coded here is for
17349 BLX(2). Only this variant has conditional execution. */
17350 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17351 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17353 #undef THUMB_VARIANT
17354 #define THUMB_VARIANT & arm_ext_v6t2
17356 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17357 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17358 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17359 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17360 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17361 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17362 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17363 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17366 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17367 #undef THUMB_VARIANT
17368 #define THUMB_VARIANT &arm_ext_v5exp
17370 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17371 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17372 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17373 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17375 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17376 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17378 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17379 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17380 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17381 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17383 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17384 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17385 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17386 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17388 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17389 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17391 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17392 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17393 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17394 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17397 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17398 #undef THUMB_VARIANT
17399 #define THUMB_VARIANT &arm_ext_v6t2
17401 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17402 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17404 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17405 ADDRGLDRS), ldrd, t_ldstd),
17407 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17408 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17411 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17413 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17416 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17417 #undef THUMB_VARIANT
17418 #define THUMB_VARIANT & arm_ext_v6
17420 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17421 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17422 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17423 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17424 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17425 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17426 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17427 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17428 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17429 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17431 #undef THUMB_VARIANT
17432 #define THUMB_VARIANT & arm_ext_v6t2
17434 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17435 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17437 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17438 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17440 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17441 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17443 /* ARM V6 not included in V7M. */
17444 #undef THUMB_VARIANT
17445 #define THUMB_VARIANT & arm_ext_v6_notm
17446 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17447 UF(rfeib, 9900a00, 1, (RRw), rfe),
17448 UF(rfeda, 8100a00, 1, (RRw), rfe),
17449 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17450 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17451 UF(rfefa, 9900a00, 1, (RRw), rfe),
17452 UF(rfeea, 8100a00, 1, (RRw), rfe),
17453 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17454 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17455 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17456 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17457 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17459 /* ARM V6 not included in V7M (eg. integer SIMD). */
17460 #undef THUMB_VARIANT
17461 #define THUMB_VARIANT & arm_ext_v6_dsp
17462 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17463 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17464 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17465 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17466 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17467 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17468 /* Old name for QASX. */
17469 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17470 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17471 /* Old name for QSAX. */
17472 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17473 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17474 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17475 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17476 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17477 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17478 /* Old name for SASX. */
17479 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17480 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17481 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17482 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17483 /* Old name for SHASX. */
17484 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17485 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17486 /* Old name for SHSAX. */
17487 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17488 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17489 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17490 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17491 /* Old name for SSAX. */
17492 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17493 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17494 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17495 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17496 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17497 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17498 /* Old name for UASX. */
17499 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17500 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17501 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17502 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17503 /* Old name for UHASX. */
17504 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17505 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17506 /* Old name for UHSAX. */
17507 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17508 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17509 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17510 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17511 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17512 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17513 /* Old name for UQASX. */
17514 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17515 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17516 /* Old name for UQSAX. */
17517 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17518 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17519 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17520 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17521 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17522 /* Old name for USAX. */
17523 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17524 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17525 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17526 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17527 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17528 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17529 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17530 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17531 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17532 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17533 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17534 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17535 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17536 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17537 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17538 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17539 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17540 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17541 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17542 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17543 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17544 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17545 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17546 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17547 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17548 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17549 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17550 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17551 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17552 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17553 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17554 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17555 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17556 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17559 #define ARM_VARIANT & arm_ext_v6k
17560 #undef THUMB_VARIANT
17561 #define THUMB_VARIANT & arm_ext_v6k
17563 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17564 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17565 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17566 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17568 #undef THUMB_VARIANT
17569 #define THUMB_VARIANT & arm_ext_v6_notm
17570 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17572 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17573 RRnpcb), strexd, t_strexd),
17575 #undef THUMB_VARIANT
17576 #define THUMB_VARIANT & arm_ext_v6t2
17577 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17579 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17581 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17583 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17585 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17588 #define ARM_VARIANT & arm_ext_sec
17589 #undef THUMB_VARIANT
17590 #define THUMB_VARIANT & arm_ext_sec
17592 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17595 #define ARM_VARIANT & arm_ext_virt
17596 #undef THUMB_VARIANT
17597 #define THUMB_VARIANT & arm_ext_virt
17599 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17600 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17603 #define ARM_VARIANT & arm_ext_v6t2
17604 #undef THUMB_VARIANT
17605 #define THUMB_VARIANT & arm_ext_v6t2
17607 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17608 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17609 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17610 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17612 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17613 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17614 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17615 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17617 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17618 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17619 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17620 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17622 /* Thumb-only instructions. */
17624 #define ARM_VARIANT NULL
17625 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17626 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17628 /* ARM does not really have an IT instruction, so always allow it.
17629 The opcode is copied from Thumb in order to allow warnings in
17630 -mimplicit-it=[never | arm] modes. */
17632 #define ARM_VARIANT & arm_ext_v1
17634 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17635 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17636 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17637 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17638 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17639 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17640 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17641 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17642 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17643 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17644 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17645 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17646 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17647 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17648 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17649 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17650 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17651 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17653 /* Thumb2 only instructions. */
17655 #define ARM_VARIANT NULL
17657 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17658 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17659 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17660 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17661 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17662 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17664 /* Hardware division instructions. */
17666 #define ARM_VARIANT & arm_ext_adiv
17667 #undef THUMB_VARIANT
17668 #define THUMB_VARIANT & arm_ext_div
17670 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17671 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17673 /* ARM V6M/V7 instructions. */
17675 #define ARM_VARIANT & arm_ext_barrier
17676 #undef THUMB_VARIANT
17677 #define THUMB_VARIANT & arm_ext_barrier
17679 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17680 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17681 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17683 /* ARM V7 instructions. */
17685 #define ARM_VARIANT & arm_ext_v7
17686 #undef THUMB_VARIANT
17687 #define THUMB_VARIANT & arm_ext_v7
17689 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17690 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17693 #define ARM_VARIANT & arm_ext_mp
17694 #undef THUMB_VARIANT
17695 #define THUMB_VARIANT & arm_ext_mp
17697 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17700 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17702 cCE("wfs", e200110, 1, (RR), rd),
17703 cCE("rfs", e300110, 1, (RR), rd),
17704 cCE("wfc", e400110, 1, (RR), rd),
17705 cCE("rfc", e500110, 1, (RR), rd),
17707 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17708 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17709 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17710 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17712 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17713 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17714 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17715 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17717 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17718 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17719 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17720 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17721 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17722 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17723 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17724 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17725 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17726 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17727 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17728 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17730 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17731 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17732 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17733 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17734 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17735 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17736 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17737 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17738 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17739 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17740 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17741 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17743 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17744 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17745 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17746 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17747 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17748 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17749 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17750 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17751 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17752 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17753 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17754 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17756 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17757 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17758 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17759 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17760 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17761 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17762 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17763 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17764 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17765 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17766 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17767 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17769 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17770 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17771 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17772 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17773 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17774 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17775 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17776 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17777 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17778 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17779 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17780 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17782 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17783 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17784 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17785 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17786 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17787 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17788 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17789 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17790 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17791 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17792 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17793 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17795 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17796 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17797 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17798 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17799 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17800 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17801 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17802 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17803 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17804 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17805 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17806 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17808 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17809 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17810 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17811 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17812 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17813 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17814 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17815 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17816 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17817 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17818 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17819 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17821 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17822 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17823 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17824 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17825 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17826 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17827 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17828 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17829 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17830 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17831 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17832 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17834 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17835 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17836 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17837 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17838 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17839 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17840 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17841 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17842 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17843 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17844 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17845 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17847 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17848 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17849 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17850 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17851 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17852 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17853 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17854 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17855 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17856 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17857 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17858 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17860 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17861 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17862 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17863 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17864 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17865 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17866 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17867 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17868 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17869 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17870 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17871 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17873 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17874 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17875 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17876 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17877 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17878 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17879 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17880 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17881 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17882 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17883 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17884 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17886 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17887 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17888 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17889 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17890 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17891 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17892 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17893 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17894 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17895 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17896 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17897 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17899 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17900 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17901 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17902 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17903 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17904 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17905 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17906 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17907 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17908 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17909 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17910 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17912 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17913 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17914 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17915 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17916 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17917 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17918 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17919 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17920 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17921 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17922 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17923 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17925 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17958 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17960 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17961 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17962 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17965 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17971 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17973 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17974 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17975 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17978 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17984 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17986 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17987 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17988 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18065 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18069 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18070 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18077 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18078 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18079 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18082 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18083 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18090 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18091 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18092 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18094 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18095 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18096 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18097 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18099 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18100 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18101 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18102 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18103 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18104 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18105 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18106 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18107 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18108 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18109 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18110 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18112 /* The implementation of the FIX instruction is broken on some
18113 assemblers, in that it accepts a precision specifier as well as a
18114 rounding specifier, despite the fact that this is meaningless.
18115 To be more compatible, we accept it as well, though of course it
18116 does not set any bits. */
18117 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18118 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18119 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18120 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18121 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18122 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18123 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18124 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18125 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18126 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18127 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18128 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18129 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18131 /* Instructions that were new with the real FPA, call them V2. */
18133 #define ARM_VARIANT & fpu_fpa_ext_v2
18135 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18136 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18137 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18138 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18139 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18140 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18143 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18145 /* Moves and type conversions. */
18146 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18147 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18148 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18149 cCE("fmstat", ef1fa10, 0, (), noargs),
18150 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18151 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18152 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18153 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18154 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18155 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18156 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18157 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18158 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18159 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18161 /* Memory operations. */
18162 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18163 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18164 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18165 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18166 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18167 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18168 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18169 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18170 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18171 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18172 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18173 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18174 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18175 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18176 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18177 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18178 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18179 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18181 /* Monadic operations. */
18182 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18183 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18184 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18186 /* Dyadic operations. */
18187 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18188 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18189 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18190 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18191 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18192 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18193 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18194 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18195 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18198 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18199 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18200 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18201 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18203 /* Double precision load/store are still present on single precision
18204 implementations. */
18205 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18206 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18207 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18208 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18209 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18210 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18211 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18212 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18213 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18214 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18217 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18219 /* Moves and type conversions. */
18220 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18221 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18222 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18223 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18224 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18225 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18226 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18227 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18228 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18229 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18230 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18231 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18232 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18234 /* Monadic operations. */
18235 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18236 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18237 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18239 /* Dyadic operations. */
18240 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18241 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18242 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18243 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18244 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18245 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18246 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18247 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18248 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18251 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18252 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18253 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18254 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18257 #define ARM_VARIANT & fpu_vfp_ext_v2
18259 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18260 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18261 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18262 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18264 /* Instructions which may belong to either the Neon or VFP instruction sets.
18265 Individual encoder functions perform additional architecture checks. */
18267 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18268 #undef THUMB_VARIANT
18269 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18271 /* These mnemonics are unique to VFP. */
18272 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18273 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18274 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18275 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18276 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18277 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18278 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18279 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18280 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18281 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18283 /* Mnemonics shared by Neon and VFP. */
18284 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18285 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18286 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18288 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18289 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18291 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18292 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18294 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18295 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18296 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18297 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18298 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18299 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18300 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18301 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18303 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18304 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18305 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18306 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18309 /* NOTE: All VMOV encoding is special-cased! */
18310 NCE(vmov, 0, 1, (VMOV), neon_mov),
18311 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18313 #undef THUMB_VARIANT
18314 #define THUMB_VARIANT & fpu_neon_ext_v1
18316 #define ARM_VARIANT & fpu_neon_ext_v1
18318 /* Data processing with three registers of the same length. */
18319 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18320 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18321 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18322 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18323 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18324 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18325 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18326 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18327 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18328 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18329 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18330 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18331 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18332 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18333 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18334 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18335 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18336 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18337 /* If not immediate, fall back to neon_dyadic_i64_su.
18338 shl_imm should accept I8 I16 I32 I64,
18339 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18340 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18341 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18342 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18343 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18344 /* Logic ops, types optional & ignored. */
18345 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18346 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18347 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18348 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18349 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18350 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18351 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18352 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18353 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18354 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18355 /* Bitfield ops, untyped. */
18356 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18357 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18358 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18359 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18360 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18361 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18362 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18363 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18364 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18365 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18366 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18367 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18368 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18369 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18370 back to neon_dyadic_if_su. */
18371 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18372 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18373 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18374 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18375 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18376 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18377 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18378 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18379 /* Comparison. Type I8 I16 I32 F32. */
18380 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18381 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18382 /* As above, D registers only. */
18383 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18384 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18385 /* Int and float variants, signedness unimportant. */
18386 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18387 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18388 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18389 /* Add/sub take types I8 I16 I32 I64 F32. */
18390 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18391 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18392 /* vtst takes sizes 8, 16, 32. */
18393 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18394 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18395 /* VMUL takes I8 I16 I32 F32 P8. */
18396 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18397 /* VQD{R}MULH takes S16 S32. */
18398 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18399 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18400 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18401 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18402 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18403 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18404 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18405 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18406 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18407 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18408 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18409 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18410 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18411 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18412 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18413 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18415 /* Two address, int/float. Types S8 S16 S32 F32. */
18416 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18417 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18419 /* Data processing with two registers and a shift amount. */
18420 /* Right shifts, and variants with rounding.
18421 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18422 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18423 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18424 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18425 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18426 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18427 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18428 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18429 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18430 /* Shift and insert. Sizes accepted 8 16 32 64. */
18431 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18432 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18433 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18434 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18435 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18436 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18437 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18438 /* Right shift immediate, saturating & narrowing, with rounding variants.
18439 Types accepted S16 S32 S64 U16 U32 U64. */
18440 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18441 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18442 /* As above, unsigned. Types accepted S16 S32 S64. */
18443 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18444 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18445 /* Right shift narrowing. Types accepted I16 I32 I64. */
18446 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18447 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18448 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18449 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18450 /* CVT with optional immediate for fixed-point variant. */
18451 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18453 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18454 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18456 /* Data processing, three registers of different lengths. */
18457 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18458 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18459 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18460 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18461 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18462 /* If not scalar, fall back to neon_dyadic_long.
18463 Vector types as above, scalar types S16 S32 U16 U32. */
18464 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18465 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18466 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18467 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18468 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18469 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18470 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18471 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18472 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18473 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18474 /* Saturating doubling multiplies. Types S16 S32. */
18475 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18476 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18477 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18478 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18479 S16 S32 U16 U32. */
18480 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18482 /* Extract. Size 8. */
18483 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18484 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18486 /* Two registers, miscellaneous. */
18487 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18488 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18489 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18490 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18491 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18492 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18493 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18494 /* Vector replicate. Sizes 8 16 32. */
18495 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18496 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18497 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18498 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18499 /* VMOVN. Types I16 I32 I64. */
18500 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18501 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18502 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18503 /* VQMOVUN. Types S16 S32 S64. */
18504 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18505 /* VZIP / VUZP. Sizes 8 16 32. */
18506 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18507 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18508 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18509 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18510 /* VQABS / VQNEG. Types S8 S16 S32. */
18511 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18512 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18513 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18514 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18515 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18516 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18517 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18518 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18519 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18520 /* Reciprocal estimates. Types U32 F32. */
18521 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18522 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18523 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18524 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18525 /* VCLS. Types S8 S16 S32. */
18526 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18527 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18528 /* VCLZ. Types I8 I16 I32. */
18529 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18530 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18531 /* VCNT. Size 8. */
18532 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18533 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18534 /* Two address, untyped. */
18535 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18536 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18537 /* VTRN. Sizes 8 16 32. */
18538 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18539 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18541 /* Table lookup. Size 8. */
18542 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18543 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18545 #undef THUMB_VARIANT
18546 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18548 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18550 /* Neon element/structure load/store. */
18551 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18552 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18553 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18554 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18555 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18556 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18557 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18558 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18560 #undef THUMB_VARIANT
18561 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18563 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18564 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18565 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18566 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18567 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18568 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18569 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18570 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18571 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18572 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18574 #undef THUMB_VARIANT
18575 #define THUMB_VARIANT & fpu_vfp_ext_v3
18577 #define ARM_VARIANT & fpu_vfp_ext_v3
18579 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18580 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18581 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18582 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18583 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18584 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18585 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18586 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18587 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18590 #define ARM_VARIANT &fpu_vfp_ext_fma
18591 #undef THUMB_VARIANT
18592 #define THUMB_VARIANT &fpu_vfp_ext_fma
18593 /* Mnemonics shared by Neon and VFP. These are included in the
18594 VFP FMA variant; NEON and VFP FMA always includes the NEON
18595 FMA instructions. */
18596 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18597 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18598 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18599 the v form should always be used. */
18600 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18601 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18602 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18603 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18604 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18605 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18607 #undef THUMB_VARIANT
18609 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18611 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18612 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18613 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18614 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18615 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18616 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18617 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18618 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18621 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18623 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18624 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18625 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18626 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18627 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18628 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18629 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18630 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18631 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18632 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18633 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18634 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18635 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18636 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18637 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18638 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18639 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18640 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18641 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18642 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18643 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18644 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18645 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18646 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18647 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18648 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18649 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18650 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18651 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18652 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18653 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18654 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18655 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18656 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18657 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18658 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18659 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18660 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18662 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18670 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18690 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18691 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18692 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18693 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18696 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18703 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18704 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18706 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18707 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18708 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18709 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18710 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18711 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18712 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18713 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18714 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18715 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18716 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18717 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18718 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18719 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18720 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18721 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18722 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18723 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18724 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18725 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18726 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18727 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18728 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18729 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18733 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18734 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18735 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18736 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18737 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18738 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18739 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18740 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18741 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18742 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18743 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18744 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18745 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18746 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18747 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18748 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18749 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18750 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18751 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18752 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18753 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18754 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18755 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18756 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18759 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18760 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18764 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18766 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18767 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18768 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18769 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18770 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18771 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18775 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18776 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18777 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18778 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18779 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18780 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18787 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18789 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18790 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18791 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18792 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18793 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18794 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18795 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18806 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18809 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18810 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18818 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18819 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18821 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18822 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18823 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18829 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18830 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18831 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18832 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18833 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18834 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18835 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18836 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18837 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18838 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18839 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18840 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18841 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18842 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18843 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18844 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18845 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18848 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18850 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18851 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18852 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18853 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18854 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18855 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18856 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18857 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18858 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18859 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18860 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18861 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18862 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18863 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18864 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18865 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18866 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18867 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18868 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18869 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18870 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18871 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18872 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18873 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18874 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18875 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18876 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18877 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18878 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18879 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18880 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18881 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18882 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18883 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18884 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18885 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18886 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18887 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18888 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18889 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18890 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18891 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18892 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18893 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18894 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18895 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18896 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18897 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18898 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18899 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18900 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18901 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18902 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18903 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18904 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18905 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18906 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18907 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18908 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18909 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18910 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18911 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18912 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18913 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18914 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18915 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18916 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18917 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18918 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18919 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18920 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18921 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18922 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18923 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18924 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18925 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18928 #undef THUMB_VARIANT
18955 /* MD interface: bits in the object file. */
18957 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18958 for use in the a.out file, and stores them in the array pointed to by buf.
18959 This knows about the endian-ness of the target machine and does
18960 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18961 2 (short) and 4 (long) Floating numbers are put out as a series of
18962 LITTLENUMS (shorts, here at least). */
18965 md_number_to_chars (char * buf, valueT val, int n)
18967 if (target_big_endian)
18968 number_to_chars_bigendian (buf, val, n);
18970 number_to_chars_littleendian (buf, val, n);
18974 md_chars_to_number (char * buf, int n)
18977 unsigned char * where = (unsigned char *) buf;
18979 if (target_big_endian)
18984 result |= (*where++ & 255);
18992 result |= (where[n] & 255);
18999 /* MD interface: Sections. */
19001 /* Estimate the size of a frag before relaxing. Assume everything fits in
19005 md_estimate_size_before_relax (fragS * fragp,
19006 segT segtype ATTRIBUTE_UNUSED)
19012 /* Convert a machine dependent frag. */
19015 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19017 unsigned long insn;
19018 unsigned long old_op;
19026 buf = fragp->fr_literal + fragp->fr_fix;
19028 old_op = bfd_get_16(abfd, buf);
19029 if (fragp->fr_symbol)
19031 exp.X_op = O_symbol;
19032 exp.X_add_symbol = fragp->fr_symbol;
19036 exp.X_op = O_constant;
19038 exp.X_add_number = fragp->fr_offset;
19039 opcode = fragp->fr_subtype;
19042 case T_MNEM_ldr_pc:
19043 case T_MNEM_ldr_pc2:
19044 case T_MNEM_ldr_sp:
19045 case T_MNEM_str_sp:
19052 if (fragp->fr_var == 4)
19054 insn = THUMB_OP32 (opcode);
19055 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19057 insn |= (old_op & 0x700) << 4;
19061 insn |= (old_op & 7) << 12;
19062 insn |= (old_op & 0x38) << 13;
19064 insn |= 0x00000c00;
19065 put_thumb32_insn (buf, insn);
19066 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19070 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19072 pc_rel = (opcode == T_MNEM_ldr_pc2);
19075 if (fragp->fr_var == 4)
19077 insn = THUMB_OP32 (opcode);
19078 insn |= (old_op & 0xf0) << 4;
19079 put_thumb32_insn (buf, insn);
19080 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19084 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19085 exp.X_add_number -= 4;
19093 if (fragp->fr_var == 4)
19095 int r0off = (opcode == T_MNEM_mov
19096 || opcode == T_MNEM_movs) ? 0 : 8;
19097 insn = THUMB_OP32 (opcode);
19098 insn = (insn & 0xe1ffffff) | 0x10000000;
19099 insn |= (old_op & 0x700) << r0off;
19100 put_thumb32_insn (buf, insn);
19101 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19105 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19110 if (fragp->fr_var == 4)
19112 insn = THUMB_OP32(opcode);
19113 put_thumb32_insn (buf, insn);
19114 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19117 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19121 if (fragp->fr_var == 4)
19123 insn = THUMB_OP32(opcode);
19124 insn |= (old_op & 0xf00) << 14;
19125 put_thumb32_insn (buf, insn);
19126 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19129 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19132 case T_MNEM_add_sp:
19133 case T_MNEM_add_pc:
19134 case T_MNEM_inc_sp:
19135 case T_MNEM_dec_sp:
19136 if (fragp->fr_var == 4)
19138 /* ??? Choose between add and addw. */
19139 insn = THUMB_OP32 (opcode);
19140 insn |= (old_op & 0xf0) << 4;
19141 put_thumb32_insn (buf, insn);
19142 if (opcode == T_MNEM_add_pc)
19143 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19145 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19148 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19156 if (fragp->fr_var == 4)
19158 insn = THUMB_OP32 (opcode);
19159 insn |= (old_op & 0xf0) << 4;
19160 insn |= (old_op & 0xf) << 16;
19161 put_thumb32_insn (buf, insn);
19162 if (insn & (1 << 20))
19163 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19165 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19168 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19174 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19175 (enum bfd_reloc_code_real) reloc_type);
19176 fixp->fx_file = fragp->fr_file;
19177 fixp->fx_line = fragp->fr_line;
19178 fragp->fr_fix += fragp->fr_var;
19181 /* Return the size of a relaxable immediate operand instruction.
19182 SHIFT and SIZE specify the form of the allowable immediate. */
19184 relax_immediate (fragS *fragp, int size, int shift)
19190 /* ??? Should be able to do better than this. */
19191 if (fragp->fr_symbol)
19194 low = (1 << shift) - 1;
19195 mask = (1 << (shift + size)) - (1 << shift);
19196 offset = fragp->fr_offset;
19197 /* Force misaligned offsets to 32-bit variant. */
19200 if (offset & ~mask)
19205 /* Get the address of a symbol during relaxation. */
19207 relaxed_symbol_addr (fragS *fragp, long stretch)
19213 sym = fragp->fr_symbol;
19214 sym_frag = symbol_get_frag (sym);
19215 know (S_GET_SEGMENT (sym) != absolute_section
19216 || sym_frag == &zero_address_frag);
19217 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19219 /* If frag has yet to be reached on this pass, assume it will
19220 move by STRETCH just as we did. If this is not so, it will
19221 be because some frag between grows, and that will force
19225 && sym_frag->relax_marker != fragp->relax_marker)
19229 /* Adjust stretch for any alignment frag. Note that if have
19230 been expanding the earlier code, the symbol may be
19231 defined in what appears to be an earlier frag. FIXME:
19232 This doesn't handle the fr_subtype field, which specifies
19233 a maximum number of bytes to skip when doing an
19235 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19237 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19240 stretch = - ((- stretch)
19241 & ~ ((1 << (int) f->fr_offset) - 1));
19243 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19255 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19258 relax_adr (fragS *fragp, asection *sec, long stretch)
19263 /* Assume worst case for symbols not known to be in the same section. */
19264 if (fragp->fr_symbol == NULL
19265 || !S_IS_DEFINED (fragp->fr_symbol)
19266 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19267 || S_IS_WEAK (fragp->fr_symbol))
19270 val = relaxed_symbol_addr (fragp, stretch);
19271 addr = fragp->fr_address + fragp->fr_fix;
19272 addr = (addr + 4) & ~3;
19273 /* Force misaligned targets to 32-bit variant. */
19277 if (val < 0 || val > 1020)
19282 /* Return the size of a relaxable add/sub immediate instruction. */
19284 relax_addsub (fragS *fragp, asection *sec)
19289 buf = fragp->fr_literal + fragp->fr_fix;
19290 op = bfd_get_16(sec->owner, buf);
19291 if ((op & 0xf) == ((op >> 4) & 0xf))
19292 return relax_immediate (fragp, 8, 0);
19294 return relax_immediate (fragp, 3, 0);
19298 /* Return the size of a relaxable branch instruction. BITS is the
19299 size of the offset field in the narrow instruction. */
19302 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19308 /* Assume worst case for symbols not known to be in the same section. */
19309 if (!S_IS_DEFINED (fragp->fr_symbol)
19310 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19311 || S_IS_WEAK (fragp->fr_symbol))
19315 if (S_IS_DEFINED (fragp->fr_symbol)
19316 && ARM_IS_FUNC (fragp->fr_symbol))
19319 /* PR 12532. Global symbols with default visibility might
19320 be preempted, so do not relax relocations to them. */
19321 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19322 && (! S_IS_LOCAL (fragp->fr_symbol)))
19326 val = relaxed_symbol_addr (fragp, stretch);
19327 addr = fragp->fr_address + fragp->fr_fix + 4;
19330 /* Offset is a signed value *2 */
19332 if (val >= limit || val < -limit)
19338 /* Relax a machine dependent frag. This returns the amount by which
19339 the current size of the frag should change. */
19342 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19347 oldsize = fragp->fr_var;
19348 switch (fragp->fr_subtype)
19350 case T_MNEM_ldr_pc2:
19351 newsize = relax_adr (fragp, sec, stretch);
19353 case T_MNEM_ldr_pc:
19354 case T_MNEM_ldr_sp:
19355 case T_MNEM_str_sp:
19356 newsize = relax_immediate (fragp, 8, 2);
19360 newsize = relax_immediate (fragp, 5, 2);
19364 newsize = relax_immediate (fragp, 5, 1);
19368 newsize = relax_immediate (fragp, 5, 0);
19371 newsize = relax_adr (fragp, sec, stretch);
19377 newsize = relax_immediate (fragp, 8, 0);
19380 newsize = relax_branch (fragp, sec, 11, stretch);
19383 newsize = relax_branch (fragp, sec, 8, stretch);
19385 case T_MNEM_add_sp:
19386 case T_MNEM_add_pc:
19387 newsize = relax_immediate (fragp, 8, 2);
19389 case T_MNEM_inc_sp:
19390 case T_MNEM_dec_sp:
19391 newsize = relax_immediate (fragp, 7, 2);
19397 newsize = relax_addsub (fragp, sec);
19403 fragp->fr_var = newsize;
19404 /* Freeze wide instructions that are at or before the same location as
19405 in the previous pass. This avoids infinite loops.
19406 Don't freeze them unconditionally because targets may be artificially
19407 misaligned by the expansion of preceding frags. */
19408 if (stretch <= 0 && newsize > 2)
19410 md_convert_frag (sec->owner, sec, fragp);
19414 return newsize - oldsize;
19417 /* Round up a section size to the appropriate boundary. */
19420 md_section_align (segT segment ATTRIBUTE_UNUSED,
19423 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19424 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19426 /* For a.out, force the section size to be aligned. If we don't do
19427 this, BFD will align it for us, but it will not write out the
19428 final bytes of the section. This may be a bug in BFD, but it is
19429 easier to fix it here since that is how the other a.out targets
19433 align = bfd_get_section_alignment (stdoutput, segment);
19434 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19441 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19442 of an rs_align_code fragment. */
19445 arm_handle_align (fragS * fragP)
19447 static char const arm_noop[2][2][4] =
19450 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19451 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19454 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19455 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19458 static char const thumb_noop[2][2][2] =
19461 {0xc0, 0x46}, /* LE */
19462 {0x46, 0xc0}, /* BE */
19465 {0x00, 0xbf}, /* LE */
19466 {0xbf, 0x00} /* BE */
19469 static char const wide_thumb_noop[2][4] =
19470 { /* Wide Thumb-2 */
19471 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19472 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19475 unsigned bytes, fix, noop_size;
19478 const char *narrow_noop = NULL;
19483 if (fragP->fr_type != rs_align_code)
19486 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19487 p = fragP->fr_literal + fragP->fr_fix;
19490 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19491 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19493 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19495 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19497 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19499 narrow_noop = thumb_noop[1][target_big_endian];
19500 noop = wide_thumb_noop[target_big_endian];
19503 noop = thumb_noop[0][target_big_endian];
19511 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19512 [target_big_endian];
19519 fragP->fr_var = noop_size;
19521 if (bytes & (noop_size - 1))
19523 fix = bytes & (noop_size - 1);
19525 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19527 memset (p, 0, fix);
19534 if (bytes & noop_size)
19536 /* Insert a narrow noop. */
19537 memcpy (p, narrow_noop, noop_size);
19539 bytes -= noop_size;
19543 /* Use wide noops for the remainder */
19547 while (bytes >= noop_size)
19549 memcpy (p, noop, noop_size);
19551 bytes -= noop_size;
19555 fragP->fr_fix += fix;
19558 /* Called from md_do_align. Used to create an alignment
19559 frag in a code section. */
19562 arm_frag_align_code (int n, int max)
19566 /* We assume that there will never be a requirement
19567 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19568 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19573 _("alignments greater than %d bytes not supported in .text sections."),
19574 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19575 as_fatal ("%s", err_msg);
19578 p = frag_var (rs_align_code,
19579 MAX_MEM_FOR_RS_ALIGN_CODE,
19581 (relax_substateT) max,
19588 /* Perform target specific initialisation of a frag.
19589 Note - despite the name this initialisation is not done when the frag
19590 is created, but only when its type is assigned. A frag can be created
19591 and used a long time before its type is set, so beware of assuming that
19592 this initialisationis performed first. */
19596 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19598 /* Record whether this frag is in an ARM or a THUMB area. */
19599 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19602 #else /* OBJ_ELF is defined. */
19604 arm_init_frag (fragS * fragP, int max_chars)
19606 /* If the current ARM vs THUMB mode has not already
19607 been recorded into this frag then do so now. */
19608 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19610 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19612 /* Record a mapping symbol for alignment frags. We will delete this
19613 later if the alignment ends up empty. */
19614 switch (fragP->fr_type)
19617 case rs_align_test:
19619 mapping_state_2 (MAP_DATA, max_chars);
19621 case rs_align_code:
19622 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19630 /* When we change sections we need to issue a new mapping symbol. */
19633 arm_elf_change_section (void)
19635 /* Link an unlinked unwind index table section to the .text section. */
19636 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19637 && elf_linked_to_section (now_seg) == NULL)
19638 elf_linked_to_section (now_seg) = text_section;
19642 arm_elf_section_type (const char * str, size_t len)
19644 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19645 return SHT_ARM_EXIDX;
19650 /* Code to deal with unwinding tables. */
19652 static void add_unwind_adjustsp (offsetT);
19654 /* Generate any deferred unwind frame offset. */
19657 flush_pending_unwind (void)
19661 offset = unwind.pending_offset;
19662 unwind.pending_offset = 0;
19664 add_unwind_adjustsp (offset);
19667 /* Add an opcode to this list for this function. Two-byte opcodes should
19668 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19672 add_unwind_opcode (valueT op, int length)
19674 /* Add any deferred stack adjustment. */
19675 if (unwind.pending_offset)
19676 flush_pending_unwind ();
19678 unwind.sp_restored = 0;
19680 if (unwind.opcode_count + length > unwind.opcode_alloc)
19682 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19683 if (unwind.opcodes)
19684 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19685 unwind.opcode_alloc);
19687 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19692 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19694 unwind.opcode_count++;
19698 /* Add unwind opcodes to adjust the stack pointer. */
19701 add_unwind_adjustsp (offsetT offset)
19705 if (offset > 0x200)
19707 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19712 /* Long form: 0xb2, uleb128. */
19713 /* This might not fit in a word so add the individual bytes,
19714 remembering the list is built in reverse order. */
19715 o = (valueT) ((offset - 0x204) >> 2);
19717 add_unwind_opcode (0, 1);
19719 /* Calculate the uleb128 encoding of the offset. */
19723 bytes[n] = o & 0x7f;
19729 /* Add the insn. */
19731 add_unwind_opcode (bytes[n - 1], 1);
19732 add_unwind_opcode (0xb2, 1);
19734 else if (offset > 0x100)
19736 /* Two short opcodes. */
19737 add_unwind_opcode (0x3f, 1);
19738 op = (offset - 0x104) >> 2;
19739 add_unwind_opcode (op, 1);
19741 else if (offset > 0)
19743 /* Short opcode. */
19744 op = (offset - 4) >> 2;
19745 add_unwind_opcode (op, 1);
19747 else if (offset < 0)
19750 while (offset > 0x100)
19752 add_unwind_opcode (0x7f, 1);
19755 op = ((offset - 4) >> 2) | 0x40;
19756 add_unwind_opcode (op, 1);
19760 /* Finish the list of unwind opcodes for this function. */
19762 finish_unwind_opcodes (void)
19766 if (unwind.fp_used)
19768 /* Adjust sp as necessary. */
19769 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19770 flush_pending_unwind ();
19772 /* After restoring sp from the frame pointer. */
19773 op = 0x90 | unwind.fp_reg;
19774 add_unwind_opcode (op, 1);
19777 flush_pending_unwind ();
19781 /* Start an exception table entry. If idx is nonzero this is an index table
19785 start_unwind_section (const segT text_seg, int idx)
19787 const char * text_name;
19788 const char * prefix;
19789 const char * prefix_once;
19790 const char * group_name;
19794 size_t sec_name_len;
19801 prefix = ELF_STRING_ARM_unwind;
19802 prefix_once = ELF_STRING_ARM_unwind_once;
19803 type = SHT_ARM_EXIDX;
19807 prefix = ELF_STRING_ARM_unwind_info;
19808 prefix_once = ELF_STRING_ARM_unwind_info_once;
19809 type = SHT_PROGBITS;
19812 text_name = segment_name (text_seg);
19813 if (streq (text_name, ".text"))
19816 if (strncmp (text_name, ".gnu.linkonce.t.",
19817 strlen (".gnu.linkonce.t.")) == 0)
19819 prefix = prefix_once;
19820 text_name += strlen (".gnu.linkonce.t.");
19823 prefix_len = strlen (prefix);
19824 text_len = strlen (text_name);
19825 sec_name_len = prefix_len + text_len;
19826 sec_name = (char *) xmalloc (sec_name_len + 1);
19827 memcpy (sec_name, prefix, prefix_len);
19828 memcpy (sec_name + prefix_len, text_name, text_len);
19829 sec_name[prefix_len + text_len] = '\0';
19835 /* Handle COMDAT group. */
19836 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19838 group_name = elf_group_name (text_seg);
19839 if (group_name == NULL)
19841 as_bad (_("Group section `%s' has no group signature"),
19842 segment_name (text_seg));
19843 ignore_rest_of_line ();
19846 flags |= SHF_GROUP;
19850 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19852 /* Set the section link for index tables. */
19854 elf_linked_to_section (now_seg) = text_seg;
19858 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19859 personality routine data. Returns zero, or the index table value for
19860 and inline entry. */
19863 create_unwind_entry (int have_data)
19868 /* The current word of data. */
19870 /* The number of bytes left in this word. */
19873 finish_unwind_opcodes ();
19875 /* Remember the current text section. */
19876 unwind.saved_seg = now_seg;
19877 unwind.saved_subseg = now_subseg;
19879 start_unwind_section (now_seg, 0);
19881 if (unwind.personality_routine == NULL)
19883 if (unwind.personality_index == -2)
19886 as_bad (_("handlerdata in cantunwind frame"));
19887 return 1; /* EXIDX_CANTUNWIND. */
19890 /* Use a default personality routine if none is specified. */
19891 if (unwind.personality_index == -1)
19893 if (unwind.opcode_count > 3)
19894 unwind.personality_index = 1;
19896 unwind.personality_index = 0;
19899 /* Space for the personality routine entry. */
19900 if (unwind.personality_index == 0)
19902 if (unwind.opcode_count > 3)
19903 as_bad (_("too many unwind opcodes for personality routine 0"));
19907 /* All the data is inline in the index table. */
19910 while (unwind.opcode_count > 0)
19912 unwind.opcode_count--;
19913 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19917 /* Pad with "finish" opcodes. */
19919 data = (data << 8) | 0xb0;
19926 /* We get two opcodes "free" in the first word. */
19927 size = unwind.opcode_count - 2;
19931 gas_assert (unwind.personality_index == -1);
19933 /* An extra byte is required for the opcode count. */
19934 size = unwind.opcode_count + 1;
19937 size = (size + 3) >> 2;
19939 as_bad (_("too many unwind opcodes"));
19941 frag_align (2, 0, 0);
19942 record_alignment (now_seg, 2);
19943 unwind.table_entry = expr_build_dot ();
19945 /* Allocate the table entry. */
19946 ptr = frag_more ((size << 2) + 4);
19947 where = frag_now_fix () - ((size << 2) + 4);
19949 switch (unwind.personality_index)
19952 /* ??? Should this be a PLT generating relocation? */
19953 /* Custom personality routine. */
19954 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19955 BFD_RELOC_ARM_PREL31);
19960 /* Set the first byte to the number of additional words. */
19961 data = size > 0 ? size - 1 : 0;
19965 /* ABI defined personality routines. */
19967 /* Three opcodes bytes are packed into the first word. */
19974 /* The size and first two opcode bytes go in the first word. */
19975 data = ((0x80 + unwind.personality_index) << 8) | size;
19980 /* Should never happen. */
19984 /* Pack the opcodes into words (MSB first), reversing the list at the same
19986 while (unwind.opcode_count > 0)
19990 md_number_to_chars (ptr, data, 4);
19995 unwind.opcode_count--;
19997 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20000 /* Finish off the last word. */
20003 /* Pad with "finish" opcodes. */
20005 data = (data << 8) | 0xb0;
20007 md_number_to_chars (ptr, data, 4);
20012 /* Add an empty descriptor if there is no user-specified data. */
20013 ptr = frag_more (4);
20014 md_number_to_chars (ptr, 0, 4);
20021 /* Initialize the DWARF-2 unwind information for this procedure. */
20024 tc_arm_frame_initial_instructions (void)
20026 cfi_add_CFA_def_cfa (REG_SP, 0);
20028 #endif /* OBJ_ELF */
20030 /* Convert REGNAME to a DWARF-2 register number. */
20033 tc_arm_regname_to_dw2regnum (char *regname)
20035 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20045 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20049 exp.X_op = O_secrel;
20050 exp.X_add_symbol = symbol;
20051 exp.X_add_number = 0;
20052 emit_expr (&exp, size);
20056 /* MD interface: Symbol and relocation handling. */
20058 /* Return the address within the segment that a PC-relative fixup is
20059 relative to. For ARM, PC-relative fixups applied to instructions
20060 are generally relative to the location of the fixup plus 8 bytes.
20061 Thumb branches are offset by 4, and Thumb loads relative to PC
20062 require special handling. */
20065 md_pcrel_from_section (fixS * fixP, segT seg)
20067 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20069 /* If this is pc-relative and we are going to emit a relocation
20070 then we just want to put out any pipeline compensation that the linker
20071 will need. Otherwise we want to use the calculated base.
20072 For WinCE we skip the bias for externals as well, since this
20073 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20075 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20076 || (arm_force_relocation (fixP)
20078 && !S_IS_EXTERNAL (fixP->fx_addsy)
20084 switch (fixP->fx_r_type)
20086 /* PC relative addressing on the Thumb is slightly odd as the
20087 bottom two bits of the PC are forced to zero for the
20088 calculation. This happens *after* application of the
20089 pipeline offset. However, Thumb adrl already adjusts for
20090 this, so we need not do it again. */
20091 case BFD_RELOC_ARM_THUMB_ADD:
20094 case BFD_RELOC_ARM_THUMB_OFFSET:
20095 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20096 case BFD_RELOC_ARM_T32_ADD_PC12:
20097 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20098 return (base + 4) & ~3;
20100 /* Thumb branches are simply offset by +4. */
20101 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20102 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20103 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20104 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20105 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20108 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20110 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20111 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20112 && ARM_IS_FUNC (fixP->fx_addsy)
20113 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20114 base = fixP->fx_where + fixP->fx_frag->fr_address;
20117 /* BLX is like branches above, but forces the low two bits of PC to
20119 case BFD_RELOC_THUMB_PCREL_BLX:
20121 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20122 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20123 && THUMB_IS_FUNC (fixP->fx_addsy)
20124 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20125 base = fixP->fx_where + fixP->fx_frag->fr_address;
20126 return (base + 4) & ~3;
20128 /* ARM mode branches are offset by +8. However, the Windows CE
20129 loader expects the relocation not to take this into account. */
20130 case BFD_RELOC_ARM_PCREL_BLX:
20132 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20133 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20134 && ARM_IS_FUNC (fixP->fx_addsy)
20135 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20136 base = fixP->fx_where + fixP->fx_frag->fr_address;
20139 case BFD_RELOC_ARM_PCREL_CALL:
20141 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20142 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20143 && THUMB_IS_FUNC (fixP->fx_addsy)
20144 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20145 base = fixP->fx_where + fixP->fx_frag->fr_address;
20148 case BFD_RELOC_ARM_PCREL_BRANCH:
20149 case BFD_RELOC_ARM_PCREL_JUMP:
20150 case BFD_RELOC_ARM_PLT32:
20152 /* When handling fixups immediately, because we have already
20153 discovered the value of a symbol, or the address of the frag involved
20154 we must account for the offset by +8, as the OS loader will never see the reloc.
20155 see fixup_segment() in write.c
20156 The S_IS_EXTERNAL test handles the case of global symbols.
20157 Those need the calculated base, not just the pipe compensation the linker will need. */
20159 && fixP->fx_addsy != NULL
20160 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20161 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20169 /* ARM mode loads relative to PC are also offset by +8. Unlike
20170 branches, the Windows CE loader *does* expect the relocation
20171 to take this into account. */
20172 case BFD_RELOC_ARM_OFFSET_IMM:
20173 case BFD_RELOC_ARM_OFFSET_IMM8:
20174 case BFD_RELOC_ARM_HWLITERAL:
20175 case BFD_RELOC_ARM_LITERAL:
20176 case BFD_RELOC_ARM_CP_OFF_IMM:
20180 /* Other PC-relative relocations are un-offset. */
20186 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20187 Otherwise we have no need to default values of symbols. */
20190 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20193 if (name[0] == '_' && name[1] == 'G'
20194 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20198 if (symbol_find (name))
20199 as_bad (_("GOT already in the symbol table"));
20201 GOT_symbol = symbol_new (name, undefined_section,
20202 (valueT) 0, & zero_address_frag);
20212 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20213 computed as two separate immediate values, added together. We
20214 already know that this value cannot be computed by just one ARM
20217 static unsigned int
20218 validate_immediate_twopart (unsigned int val,
20219 unsigned int * highpart)
20224 for (i = 0; i < 32; i += 2)
20225 if (((a = rotate_left (val, i)) & 0xff) != 0)
20231 * highpart = (a >> 8) | ((i + 24) << 7);
20233 else if (a & 0xff0000)
20235 if (a & 0xff000000)
20237 * highpart = (a >> 16) | ((i + 16) << 7);
20241 gas_assert (a & 0xff000000);
20242 * highpart = (a >> 24) | ((i + 8) << 7);
20245 return (a & 0xff) | (i << 7);
20252 validate_offset_imm (unsigned int val, int hwse)
20254 if ((hwse && val > 255) || val > 4095)
20259 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20260 negative immediate constant by altering the instruction. A bit of
20265 by inverting the second operand, and
20268 by negating the second operand. */
20271 negate_data_op (unsigned long * instruction,
20272 unsigned long value)
20275 unsigned long negated, inverted;
20277 negated = encode_arm_immediate (-value);
20278 inverted = encode_arm_immediate (~value);
20280 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20283 /* First negates. */
20284 case OPCODE_SUB: /* ADD <-> SUB */
20285 new_inst = OPCODE_ADD;
20290 new_inst = OPCODE_SUB;
20294 case OPCODE_CMP: /* CMP <-> CMN */
20295 new_inst = OPCODE_CMN;
20300 new_inst = OPCODE_CMP;
20304 /* Now Inverted ops. */
20305 case OPCODE_MOV: /* MOV <-> MVN */
20306 new_inst = OPCODE_MVN;
20311 new_inst = OPCODE_MOV;
20315 case OPCODE_AND: /* AND <-> BIC */
20316 new_inst = OPCODE_BIC;
20321 new_inst = OPCODE_AND;
20325 case OPCODE_ADC: /* ADC <-> SBC */
20326 new_inst = OPCODE_SBC;
20331 new_inst = OPCODE_ADC;
20335 /* We cannot do anything. */
20340 if (value == (unsigned) FAIL)
20343 *instruction &= OPCODE_MASK;
20344 *instruction |= new_inst << DATA_OP_SHIFT;
20348 /* Like negate_data_op, but for Thumb-2. */
20350 static unsigned int
20351 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20355 unsigned int negated, inverted;
20357 negated = encode_thumb32_immediate (-value);
20358 inverted = encode_thumb32_immediate (~value);
20360 rd = (*instruction >> 8) & 0xf;
20361 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20364 /* ADD <-> SUB. Includes CMP <-> CMN. */
20365 case T2_OPCODE_SUB:
20366 new_inst = T2_OPCODE_ADD;
20370 case T2_OPCODE_ADD:
20371 new_inst = T2_OPCODE_SUB;
20375 /* ORR <-> ORN. Includes MOV <-> MVN. */
20376 case T2_OPCODE_ORR:
20377 new_inst = T2_OPCODE_ORN;
20381 case T2_OPCODE_ORN:
20382 new_inst = T2_OPCODE_ORR;
20386 /* AND <-> BIC. TST has no inverted equivalent. */
20387 case T2_OPCODE_AND:
20388 new_inst = T2_OPCODE_BIC;
20395 case T2_OPCODE_BIC:
20396 new_inst = T2_OPCODE_AND;
20401 case T2_OPCODE_ADC:
20402 new_inst = T2_OPCODE_SBC;
20406 case T2_OPCODE_SBC:
20407 new_inst = T2_OPCODE_ADC;
20411 /* We cannot do anything. */
20416 if (value == (unsigned int)FAIL)
20419 *instruction &= T2_OPCODE_MASK;
20420 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20424 /* Read a 32-bit thumb instruction from buf. */
20425 static unsigned long
20426 get_thumb32_insn (char * buf)
20428 unsigned long insn;
20429 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20430 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20436 /* We usually want to set the low bit on the address of thumb function
20437 symbols. In particular .word foo - . should have the low bit set.
20438 Generic code tries to fold the difference of two symbols to
20439 a constant. Prevent this and force a relocation when the first symbols
20440 is a thumb function. */
20443 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20445 if (op == O_subtract
20446 && l->X_op == O_symbol
20447 && r->X_op == O_symbol
20448 && THUMB_IS_FUNC (l->X_add_symbol))
20450 l->X_op = O_subtract;
20451 l->X_op_symbol = r->X_add_symbol;
20452 l->X_add_number -= r->X_add_number;
20456 /* Process as normal. */
20460 /* Encode Thumb2 unconditional branches and calls. The encoding
20461 for the 2 are identical for the immediate values. */
20464 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20466 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20469 addressT S, I1, I2, lo, hi;
20471 S = (value >> 24) & 0x01;
20472 I1 = (value >> 23) & 0x01;
20473 I2 = (value >> 22) & 0x01;
20474 hi = (value >> 12) & 0x3ff;
20475 lo = (value >> 1) & 0x7ff;
20476 newval = md_chars_to_number (buf, THUMB_SIZE);
20477 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20478 newval |= (S << 10) | hi;
20479 newval2 &= ~T2I1I2MASK;
20480 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20481 md_number_to_chars (buf, newval, THUMB_SIZE);
20482 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20486 md_apply_fix (fixS * fixP,
20490 offsetT value = * valP;
20492 unsigned int newimm;
20493 unsigned long temp;
20495 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20497 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20499 /* Note whether this will delete the relocation. */
20501 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20504 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20505 consistency with the behaviour on 32-bit hosts. Remember value
20507 value &= 0xffffffff;
20508 value ^= 0x80000000;
20509 value -= 0x80000000;
20512 fixP->fx_addnumber = value;
20514 /* Same treatment for fixP->fx_offset. */
20515 fixP->fx_offset &= 0xffffffff;
20516 fixP->fx_offset ^= 0x80000000;
20517 fixP->fx_offset -= 0x80000000;
20519 switch (fixP->fx_r_type)
20521 case BFD_RELOC_NONE:
20522 /* This will need to go in the object file. */
20526 case BFD_RELOC_ARM_IMMEDIATE:
20527 /* We claim that this fixup has been processed here,
20528 even if in fact we generate an error because we do
20529 not have a reloc for it, so tc_gen_reloc will reject it. */
20532 if (fixP->fx_addsy)
20534 const char *msg = 0;
20536 if (! S_IS_DEFINED (fixP->fx_addsy))
20537 msg = _("undefined symbol %s used as an immediate value");
20538 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20539 msg = _("symbol %s is in a different section");
20540 else if (S_IS_WEAK (fixP->fx_addsy))
20541 msg = _("symbol %s is weak and may be overridden later");
20545 as_bad_where (fixP->fx_file, fixP->fx_line,
20546 msg, S_GET_NAME (fixP->fx_addsy));
20551 newimm = encode_arm_immediate (value);
20552 temp = md_chars_to_number (buf, INSN_SIZE);
20554 /* If the instruction will fail, see if we can fix things up by
20555 changing the opcode. */
20556 if (newimm == (unsigned int) FAIL
20557 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20559 as_bad_where (fixP->fx_file, fixP->fx_line,
20560 _("invalid constant (%lx) after fixup"),
20561 (unsigned long) value);
20565 newimm |= (temp & 0xfffff000);
20566 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20569 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20571 unsigned int highpart = 0;
20572 unsigned int newinsn = 0xe1a00000; /* nop. */
20574 if (fixP->fx_addsy)
20576 const char *msg = 0;
20578 if (! S_IS_DEFINED (fixP->fx_addsy))
20579 msg = _("undefined symbol %s used as an immediate value");
20580 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20581 msg = _("symbol %s is in a different section");
20582 else if (S_IS_WEAK (fixP->fx_addsy))
20583 msg = _("symbol %s is weak and may be overridden later");
20587 as_bad_where (fixP->fx_file, fixP->fx_line,
20588 msg, S_GET_NAME (fixP->fx_addsy));
20593 newimm = encode_arm_immediate (value);
20594 temp = md_chars_to_number (buf, INSN_SIZE);
20596 /* If the instruction will fail, see if we can fix things up by
20597 changing the opcode. */
20598 if (newimm == (unsigned int) FAIL
20599 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20601 /* No ? OK - try using two ADD instructions to generate
20603 newimm = validate_immediate_twopart (value, & highpart);
20605 /* Yes - then make sure that the second instruction is
20607 if (newimm != (unsigned int) FAIL)
20609 /* Still No ? Try using a negated value. */
20610 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20611 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20612 /* Otherwise - give up. */
20615 as_bad_where (fixP->fx_file, fixP->fx_line,
20616 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20621 /* Replace the first operand in the 2nd instruction (which
20622 is the PC) with the destination register. We have
20623 already added in the PC in the first instruction and we
20624 do not want to do it again. */
20625 newinsn &= ~ 0xf0000;
20626 newinsn |= ((newinsn & 0x0f000) << 4);
20629 newimm |= (temp & 0xfffff000);
20630 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20632 highpart |= (newinsn & 0xfffff000);
20633 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20637 case BFD_RELOC_ARM_OFFSET_IMM:
20638 if (!fixP->fx_done && seg->use_rela_p)
20641 case BFD_RELOC_ARM_LITERAL:
20647 if (validate_offset_imm (value, 0) == FAIL)
20649 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20650 as_bad_where (fixP->fx_file, fixP->fx_line,
20651 _("invalid literal constant: pool needs to be closer"));
20653 as_bad_where (fixP->fx_file, fixP->fx_line,
20654 _("bad immediate value for offset (%ld)"),
20659 newval = md_chars_to_number (buf, INSN_SIZE);
20661 newval &= 0xfffff000;
20664 newval &= 0xff7ff000;
20665 newval |= value | (sign ? INDEX_UP : 0);
20667 md_number_to_chars (buf, newval, INSN_SIZE);
20670 case BFD_RELOC_ARM_OFFSET_IMM8:
20671 case BFD_RELOC_ARM_HWLITERAL:
20677 if (validate_offset_imm (value, 1) == FAIL)
20679 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20680 as_bad_where (fixP->fx_file, fixP->fx_line,
20681 _("invalid literal constant: pool needs to be closer"));
20683 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20688 newval = md_chars_to_number (buf, INSN_SIZE);
20690 newval &= 0xfffff0f0;
20693 newval &= 0xff7ff0f0;
20694 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20696 md_number_to_chars (buf, newval, INSN_SIZE);
20699 case BFD_RELOC_ARM_T32_OFFSET_U8:
20700 if (value < 0 || value > 1020 || value % 4 != 0)
20701 as_bad_where (fixP->fx_file, fixP->fx_line,
20702 _("bad immediate value for offset (%ld)"), (long) value);
20705 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20707 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20710 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20711 /* This is a complicated relocation used for all varieties of Thumb32
20712 load/store instruction with immediate offset:
20714 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20715 *4, optional writeback(W)
20716 (doubleword load/store)
20718 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20719 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20720 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20721 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20722 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20724 Uppercase letters indicate bits that are already encoded at
20725 this point. Lowercase letters are our problem. For the
20726 second block of instructions, the secondary opcode nybble
20727 (bits 8..11) is present, and bit 23 is zero, even if this is
20728 a PC-relative operation. */
20729 newval = md_chars_to_number (buf, THUMB_SIZE);
20731 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20733 if ((newval & 0xf0000000) == 0xe0000000)
20735 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20737 newval |= (1 << 23);
20740 if (value % 4 != 0)
20742 as_bad_where (fixP->fx_file, fixP->fx_line,
20743 _("offset not a multiple of 4"));
20749 as_bad_where (fixP->fx_file, fixP->fx_line,
20750 _("offset out of range"));
20755 else if ((newval & 0x000f0000) == 0x000f0000)
20757 /* PC-relative, 12-bit offset. */
20759 newval |= (1 << 23);
20764 as_bad_where (fixP->fx_file, fixP->fx_line,
20765 _("offset out of range"));
20770 else if ((newval & 0x00000100) == 0x00000100)
20772 /* Writeback: 8-bit, +/- offset. */
20774 newval |= (1 << 9);
20779 as_bad_where (fixP->fx_file, fixP->fx_line,
20780 _("offset out of range"));
20785 else if ((newval & 0x00000f00) == 0x00000e00)
20787 /* T-instruction: positive 8-bit offset. */
20788 if (value < 0 || value > 0xff)
20790 as_bad_where (fixP->fx_file, fixP->fx_line,
20791 _("offset out of range"));
20799 /* Positive 12-bit or negative 8-bit offset. */
20803 newval |= (1 << 23);
20813 as_bad_where (fixP->fx_file, fixP->fx_line,
20814 _("offset out of range"));
20821 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20822 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20825 case BFD_RELOC_ARM_SHIFT_IMM:
20826 newval = md_chars_to_number (buf, INSN_SIZE);
20827 if (((unsigned long) value) > 32
20829 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20831 as_bad_where (fixP->fx_file, fixP->fx_line,
20832 _("shift expression is too large"));
20837 /* Shifts of zero must be done as lsl. */
20839 else if (value == 32)
20841 newval &= 0xfffff07f;
20842 newval |= (value & 0x1f) << 7;
20843 md_number_to_chars (buf, newval, INSN_SIZE);
20846 case BFD_RELOC_ARM_T32_IMMEDIATE:
20847 case BFD_RELOC_ARM_T32_ADD_IMM:
20848 case BFD_RELOC_ARM_T32_IMM12:
20849 case BFD_RELOC_ARM_T32_ADD_PC12:
20850 /* We claim that this fixup has been processed here,
20851 even if in fact we generate an error because we do
20852 not have a reloc for it, so tc_gen_reloc will reject it. */
20856 && ! S_IS_DEFINED (fixP->fx_addsy))
20858 as_bad_where (fixP->fx_file, fixP->fx_line,
20859 _("undefined symbol %s used as an immediate value"),
20860 S_GET_NAME (fixP->fx_addsy));
20864 newval = md_chars_to_number (buf, THUMB_SIZE);
20866 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20869 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20870 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20872 newimm = encode_thumb32_immediate (value);
20873 if (newimm == (unsigned int) FAIL)
20874 newimm = thumb32_negate_data_op (&newval, value);
20876 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20877 && newimm == (unsigned int) FAIL)
20879 /* Turn add/sum into addw/subw. */
20880 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20881 newval = (newval & 0xfeffffff) | 0x02000000;
20882 /* No flat 12-bit imm encoding for addsw/subsw. */
20883 if ((newval & 0x00100000) == 0)
20885 /* 12 bit immediate for addw/subw. */
20889 newval ^= 0x00a00000;
20892 newimm = (unsigned int) FAIL;
20898 if (newimm == (unsigned int)FAIL)
20900 as_bad_where (fixP->fx_file, fixP->fx_line,
20901 _("invalid constant (%lx) after fixup"),
20902 (unsigned long) value);
20906 newval |= (newimm & 0x800) << 15;
20907 newval |= (newimm & 0x700) << 4;
20908 newval |= (newimm & 0x0ff);
20910 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20911 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20914 case BFD_RELOC_ARM_SMC:
20915 if (((unsigned long) value) > 0xffff)
20916 as_bad_where (fixP->fx_file, fixP->fx_line,
20917 _("invalid smc expression"));
20918 newval = md_chars_to_number (buf, INSN_SIZE);
20919 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20920 md_number_to_chars (buf, newval, INSN_SIZE);
20923 case BFD_RELOC_ARM_HVC:
20924 if (((unsigned long) value) > 0xffff)
20925 as_bad_where (fixP->fx_file, fixP->fx_line,
20926 _("invalid hvc expression"));
20927 newval = md_chars_to_number (buf, INSN_SIZE);
20928 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20929 md_number_to_chars (buf, newval, INSN_SIZE);
20932 case BFD_RELOC_ARM_SWI:
20933 if (fixP->tc_fix_data != 0)
20935 if (((unsigned long) value) > 0xff)
20936 as_bad_where (fixP->fx_file, fixP->fx_line,
20937 _("invalid swi expression"));
20938 newval = md_chars_to_number (buf, THUMB_SIZE);
20940 md_number_to_chars (buf, newval, THUMB_SIZE);
20944 if (((unsigned long) value) > 0x00ffffff)
20945 as_bad_where (fixP->fx_file, fixP->fx_line,
20946 _("invalid swi expression"));
20947 newval = md_chars_to_number (buf, INSN_SIZE);
20949 md_number_to_chars (buf, newval, INSN_SIZE);
20953 case BFD_RELOC_ARM_MULTI:
20954 if (((unsigned long) value) > 0xffff)
20955 as_bad_where (fixP->fx_file, fixP->fx_line,
20956 _("invalid expression in load/store multiple"));
20957 newval = value | md_chars_to_number (buf, INSN_SIZE);
20958 md_number_to_chars (buf, newval, INSN_SIZE);
20962 case BFD_RELOC_ARM_PCREL_CALL:
20964 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20966 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20967 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20968 && THUMB_IS_FUNC (fixP->fx_addsy))
20969 /* Flip the bl to blx. This is a simple flip
20970 bit here because we generate PCREL_CALL for
20971 unconditional bls. */
20973 newval = md_chars_to_number (buf, INSN_SIZE);
20974 newval = newval | 0x10000000;
20975 md_number_to_chars (buf, newval, INSN_SIZE);
20981 goto arm_branch_common;
20983 case BFD_RELOC_ARM_PCREL_JUMP:
20984 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20986 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20987 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20988 && THUMB_IS_FUNC (fixP->fx_addsy))
20990 /* This would map to a bl<cond>, b<cond>,
20991 b<always> to a Thumb function. We
20992 need to force a relocation for this particular
20994 newval = md_chars_to_number (buf, INSN_SIZE);
20998 case BFD_RELOC_ARM_PLT32:
21000 case BFD_RELOC_ARM_PCREL_BRANCH:
21002 goto arm_branch_common;
21004 case BFD_RELOC_ARM_PCREL_BLX:
21007 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21009 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21010 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21011 && ARM_IS_FUNC (fixP->fx_addsy))
21013 /* Flip the blx to a bl and warn. */
21014 const char *name = S_GET_NAME (fixP->fx_addsy);
21015 newval = 0xeb000000;
21016 as_warn_where (fixP->fx_file, fixP->fx_line,
21017 _("blx to '%s' an ARM ISA state function changed to bl"),
21019 md_number_to_chars (buf, newval, INSN_SIZE);
21025 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21026 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21030 /* We are going to store value (shifted right by two) in the
21031 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21032 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21033 also be be clear. */
21035 as_bad_where (fixP->fx_file, fixP->fx_line,
21036 _("misaligned branch destination"));
21037 if ((value & (offsetT)0xfe000000) != (offsetT)0
21038 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21039 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21041 if (fixP->fx_done || !seg->use_rela_p)
21043 newval = md_chars_to_number (buf, INSN_SIZE);
21044 newval |= (value >> 2) & 0x00ffffff;
21045 /* Set the H bit on BLX instructions. */
21049 newval |= 0x01000000;
21051 newval &= ~0x01000000;
21053 md_number_to_chars (buf, newval, INSN_SIZE);
21057 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21058 /* CBZ can only branch forward. */
21060 /* Attempts to use CBZ to branch to the next instruction
21061 (which, strictly speaking, are prohibited) will be turned into
21064 FIXME: It may be better to remove the instruction completely and
21065 perform relaxation. */
21068 newval = md_chars_to_number (buf, THUMB_SIZE);
21069 newval = 0xbf00; /* NOP encoding T1 */
21070 md_number_to_chars (buf, newval, THUMB_SIZE);
21075 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21077 if (fixP->fx_done || !seg->use_rela_p)
21079 newval = md_chars_to_number (buf, THUMB_SIZE);
21080 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21081 md_number_to_chars (buf, newval, THUMB_SIZE);
21086 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21087 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21088 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21090 if (fixP->fx_done || !seg->use_rela_p)
21092 newval = md_chars_to_number (buf, THUMB_SIZE);
21093 newval |= (value & 0x1ff) >> 1;
21094 md_number_to_chars (buf, newval, THUMB_SIZE);
21098 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21099 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21100 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21102 if (fixP->fx_done || !seg->use_rela_p)
21104 newval = md_chars_to_number (buf, THUMB_SIZE);
21105 newval |= (value & 0xfff) >> 1;
21106 md_number_to_chars (buf, newval, THUMB_SIZE);
21110 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21112 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21113 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21114 && ARM_IS_FUNC (fixP->fx_addsy)
21115 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21117 /* Force a relocation for a branch 20 bits wide. */
21120 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21121 as_bad_where (fixP->fx_file, fixP->fx_line,
21122 _("conditional branch out of range"));
21124 if (fixP->fx_done || !seg->use_rela_p)
21127 addressT S, J1, J2, lo, hi;
21129 S = (value & 0x00100000) >> 20;
21130 J2 = (value & 0x00080000) >> 19;
21131 J1 = (value & 0x00040000) >> 18;
21132 hi = (value & 0x0003f000) >> 12;
21133 lo = (value & 0x00000ffe) >> 1;
21135 newval = md_chars_to_number (buf, THUMB_SIZE);
21136 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21137 newval |= (S << 10) | hi;
21138 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21139 md_number_to_chars (buf, newval, THUMB_SIZE);
21140 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21144 case BFD_RELOC_THUMB_PCREL_BLX:
21145 /* If there is a blx from a thumb state function to
21146 another thumb function flip this to a bl and warn
21150 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21151 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21152 && THUMB_IS_FUNC (fixP->fx_addsy))
21154 const char *name = S_GET_NAME (fixP->fx_addsy);
21155 as_warn_where (fixP->fx_file, fixP->fx_line,
21156 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21158 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21159 newval = newval | 0x1000;
21160 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21161 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21166 goto thumb_bl_common;
21168 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21169 /* A bl from Thumb state ISA to an internal ARM state function
21170 is converted to a blx. */
21172 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21173 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21174 && ARM_IS_FUNC (fixP->fx_addsy)
21175 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21177 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21178 newval = newval & ~0x1000;
21179 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21180 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21187 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21188 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21189 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21192 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21193 /* For a BLX instruction, make sure that the relocation is rounded up
21194 to a word boundary. This follows the semantics of the instruction
21195 which specifies that bit 1 of the target address will come from bit
21196 1 of the base address. */
21197 value = (value + 1) & ~ 1;
21199 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21201 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21202 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21203 else if ((value & ~0x1ffffff)
21204 && ((value & ~0x1ffffff) != ~0x1ffffff))
21205 as_bad_where (fixP->fx_file, fixP->fx_line,
21206 _("Thumb2 branch out of range"));
21209 if (fixP->fx_done || !seg->use_rela_p)
21210 encode_thumb2_b_bl_offset (buf, value);
21214 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21215 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21216 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21218 if (fixP->fx_done || !seg->use_rela_p)
21219 encode_thumb2_b_bl_offset (buf, value);
21224 if (fixP->fx_done || !seg->use_rela_p)
21225 md_number_to_chars (buf, value, 1);
21229 if (fixP->fx_done || !seg->use_rela_p)
21230 md_number_to_chars (buf, value, 2);
21234 case BFD_RELOC_ARM_TLS_CALL:
21235 case BFD_RELOC_ARM_THM_TLS_CALL:
21236 case BFD_RELOC_ARM_TLS_DESCSEQ:
21237 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21238 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21241 case BFD_RELOC_ARM_TLS_GOTDESC:
21242 case BFD_RELOC_ARM_TLS_GD32:
21243 case BFD_RELOC_ARM_TLS_LE32:
21244 case BFD_RELOC_ARM_TLS_IE32:
21245 case BFD_RELOC_ARM_TLS_LDM32:
21246 case BFD_RELOC_ARM_TLS_LDO32:
21247 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21250 case BFD_RELOC_ARM_GOT32:
21251 case BFD_RELOC_ARM_GOTOFF:
21252 if (fixP->fx_done || !seg->use_rela_p)
21253 md_number_to_chars (buf, 0, 4);
21256 case BFD_RELOC_ARM_GOT_PREL:
21257 if (fixP->fx_done || !seg->use_rela_p)
21258 md_number_to_chars (buf, value, 4);
21261 case BFD_RELOC_ARM_TARGET2:
21262 /* TARGET2 is not partial-inplace, so we need to write the
21263 addend here for REL targets, because it won't be written out
21264 during reloc processing later. */
21265 if (fixP->fx_done || !seg->use_rela_p)
21266 md_number_to_chars (buf, fixP->fx_offset, 4);
21270 case BFD_RELOC_RVA:
21272 case BFD_RELOC_ARM_TARGET1:
21273 case BFD_RELOC_ARM_ROSEGREL32:
21274 case BFD_RELOC_ARM_SBREL32:
21275 case BFD_RELOC_32_PCREL:
21277 case BFD_RELOC_32_SECREL:
21279 if (fixP->fx_done || !seg->use_rela_p)
21281 /* For WinCE we only do this for pcrel fixups. */
21282 if (fixP->fx_done || fixP->fx_pcrel)
21284 md_number_to_chars (buf, value, 4);
21288 case BFD_RELOC_ARM_PREL31:
21289 if (fixP->fx_done || !seg->use_rela_p)
21291 newval = md_chars_to_number (buf, 4) & 0x80000000;
21292 if ((value ^ (value >> 1)) & 0x40000000)
21294 as_bad_where (fixP->fx_file, fixP->fx_line,
21295 _("rel31 relocation overflow"));
21297 newval |= value & 0x7fffffff;
21298 md_number_to_chars (buf, newval, 4);
21303 case BFD_RELOC_ARM_CP_OFF_IMM:
21304 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21305 if (value < -1023 || value > 1023 || (value & 3))
21306 as_bad_where (fixP->fx_file, fixP->fx_line,
21307 _("co-processor offset out of range"));
21312 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21313 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21314 newval = md_chars_to_number (buf, INSN_SIZE);
21316 newval = get_thumb32_insn (buf);
21318 newval &= 0xffffff00;
21321 newval &= 0xff7fff00;
21322 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21324 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21325 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21326 md_number_to_chars (buf, newval, INSN_SIZE);
21328 put_thumb32_insn (buf, newval);
21331 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21332 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21333 if (value < -255 || value > 255)
21334 as_bad_where (fixP->fx_file, fixP->fx_line,
21335 _("co-processor offset out of range"));
21337 goto cp_off_common;
21339 case BFD_RELOC_ARM_THUMB_OFFSET:
21340 newval = md_chars_to_number (buf, THUMB_SIZE);
21341 /* Exactly what ranges, and where the offset is inserted depends
21342 on the type of instruction, we can establish this from the
21344 switch (newval >> 12)
21346 case 4: /* PC load. */
21347 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21348 forced to zero for these loads; md_pcrel_from has already
21349 compensated for this. */
21351 as_bad_where (fixP->fx_file, fixP->fx_line,
21352 _("invalid offset, target not word aligned (0x%08lX)"),
21353 (((unsigned long) fixP->fx_frag->fr_address
21354 + (unsigned long) fixP->fx_where) & ~3)
21355 + (unsigned long) value);
21357 if (value & ~0x3fc)
21358 as_bad_where (fixP->fx_file, fixP->fx_line,
21359 _("invalid offset, value too big (0x%08lX)"),
21362 newval |= value >> 2;
21365 case 9: /* SP load/store. */
21366 if (value & ~0x3fc)
21367 as_bad_where (fixP->fx_file, fixP->fx_line,
21368 _("invalid offset, value too big (0x%08lX)"),
21370 newval |= value >> 2;
21373 case 6: /* Word load/store. */
21375 as_bad_where (fixP->fx_file, fixP->fx_line,
21376 _("invalid offset, value too big (0x%08lX)"),
21378 newval |= value << 4; /* 6 - 2. */
21381 case 7: /* Byte load/store. */
21383 as_bad_where (fixP->fx_file, fixP->fx_line,
21384 _("invalid offset, value too big (0x%08lX)"),
21386 newval |= value << 6;
21389 case 8: /* Halfword load/store. */
21391 as_bad_where (fixP->fx_file, fixP->fx_line,
21392 _("invalid offset, value too big (0x%08lX)"),
21394 newval |= value << 5; /* 6 - 1. */
21398 as_bad_where (fixP->fx_file, fixP->fx_line,
21399 "Unable to process relocation for thumb opcode: %lx",
21400 (unsigned long) newval);
21403 md_number_to_chars (buf, newval, THUMB_SIZE);
21406 case BFD_RELOC_ARM_THUMB_ADD:
21407 /* This is a complicated relocation, since we use it for all of
21408 the following immediate relocations:
21412 9bit ADD/SUB SP word-aligned
21413 10bit ADD PC/SP word-aligned
21415 The type of instruction being processed is encoded in the
21422 newval = md_chars_to_number (buf, THUMB_SIZE);
21424 int rd = (newval >> 4) & 0xf;
21425 int rs = newval & 0xf;
21426 int subtract = !!(newval & 0x8000);
21428 /* Check for HI regs, only very restricted cases allowed:
21429 Adjusting SP, and using PC or SP to get an address. */
21430 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21431 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21432 as_bad_where (fixP->fx_file, fixP->fx_line,
21433 _("invalid Hi register with immediate"));
21435 /* If value is negative, choose the opposite instruction. */
21439 subtract = !subtract;
21441 as_bad_where (fixP->fx_file, fixP->fx_line,
21442 _("immediate value out of range"));
21447 if (value & ~0x1fc)
21448 as_bad_where (fixP->fx_file, fixP->fx_line,
21449 _("invalid immediate for stack address calculation"));
21450 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21451 newval |= value >> 2;
21453 else if (rs == REG_PC || rs == REG_SP)
21455 if (subtract || value & ~0x3fc)
21456 as_bad_where (fixP->fx_file, fixP->fx_line,
21457 _("invalid immediate for address calculation (value = 0x%08lX)"),
21458 (unsigned long) value);
21459 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21461 newval |= value >> 2;
21466 as_bad_where (fixP->fx_file, fixP->fx_line,
21467 _("immediate value out of range"));
21468 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21469 newval |= (rd << 8) | value;
21474 as_bad_where (fixP->fx_file, fixP->fx_line,
21475 _("immediate value out of range"));
21476 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21477 newval |= rd | (rs << 3) | (value << 6);
21480 md_number_to_chars (buf, newval, THUMB_SIZE);
21483 case BFD_RELOC_ARM_THUMB_IMM:
21484 newval = md_chars_to_number (buf, THUMB_SIZE);
21485 if (value < 0 || value > 255)
21486 as_bad_where (fixP->fx_file, fixP->fx_line,
21487 _("invalid immediate: %ld is out of range"),
21490 md_number_to_chars (buf, newval, THUMB_SIZE);
21493 case BFD_RELOC_ARM_THUMB_SHIFT:
21494 /* 5bit shift value (0..32). LSL cannot take 32. */
21495 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21496 temp = newval & 0xf800;
21497 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21498 as_bad_where (fixP->fx_file, fixP->fx_line,
21499 _("invalid shift value: %ld"), (long) value);
21500 /* Shifts of zero must be encoded as LSL. */
21502 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21503 /* Shifts of 32 are encoded as zero. */
21504 else if (value == 32)
21506 newval |= value << 6;
21507 md_number_to_chars (buf, newval, THUMB_SIZE);
21510 case BFD_RELOC_VTABLE_INHERIT:
21511 case BFD_RELOC_VTABLE_ENTRY:
21515 case BFD_RELOC_ARM_MOVW:
21516 case BFD_RELOC_ARM_MOVT:
21517 case BFD_RELOC_ARM_THUMB_MOVW:
21518 case BFD_RELOC_ARM_THUMB_MOVT:
21519 if (fixP->fx_done || !seg->use_rela_p)
21521 /* REL format relocations are limited to a 16-bit addend. */
21522 if (!fixP->fx_done)
21524 if (value < -0x8000 || value > 0x7fff)
21525 as_bad_where (fixP->fx_file, fixP->fx_line,
21526 _("offset out of range"));
21528 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21529 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21534 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21535 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21537 newval = get_thumb32_insn (buf);
21538 newval &= 0xfbf08f00;
21539 newval |= (value & 0xf000) << 4;
21540 newval |= (value & 0x0800) << 15;
21541 newval |= (value & 0x0700) << 4;
21542 newval |= (value & 0x00ff);
21543 put_thumb32_insn (buf, newval);
21547 newval = md_chars_to_number (buf, 4);
21548 newval &= 0xfff0f000;
21549 newval |= value & 0x0fff;
21550 newval |= (value & 0xf000) << 4;
21551 md_number_to_chars (buf, newval, 4);
21556 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21557 case BFD_RELOC_ARM_ALU_PC_G0:
21558 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21559 case BFD_RELOC_ARM_ALU_PC_G1:
21560 case BFD_RELOC_ARM_ALU_PC_G2:
21561 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21562 case BFD_RELOC_ARM_ALU_SB_G0:
21563 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21564 case BFD_RELOC_ARM_ALU_SB_G1:
21565 case BFD_RELOC_ARM_ALU_SB_G2:
21566 gas_assert (!fixP->fx_done);
21567 if (!seg->use_rela_p)
21570 bfd_vma encoded_addend;
21571 bfd_vma addend_abs = abs (value);
21573 /* Check that the absolute value of the addend can be
21574 expressed as an 8-bit constant plus a rotation. */
21575 encoded_addend = encode_arm_immediate (addend_abs);
21576 if (encoded_addend == (unsigned int) FAIL)
21577 as_bad_where (fixP->fx_file, fixP->fx_line,
21578 _("the offset 0x%08lX is not representable"),
21579 (unsigned long) addend_abs);
21581 /* Extract the instruction. */
21582 insn = md_chars_to_number (buf, INSN_SIZE);
21584 /* If the addend is positive, use an ADD instruction.
21585 Otherwise use a SUB. Take care not to destroy the S bit. */
21586 insn &= 0xff1fffff;
21592 /* Place the encoded addend into the first 12 bits of the
21594 insn &= 0xfffff000;
21595 insn |= encoded_addend;
21597 /* Update the instruction. */
21598 md_number_to_chars (buf, insn, INSN_SIZE);
21602 case BFD_RELOC_ARM_LDR_PC_G0:
21603 case BFD_RELOC_ARM_LDR_PC_G1:
21604 case BFD_RELOC_ARM_LDR_PC_G2:
21605 case BFD_RELOC_ARM_LDR_SB_G0:
21606 case BFD_RELOC_ARM_LDR_SB_G1:
21607 case BFD_RELOC_ARM_LDR_SB_G2:
21608 gas_assert (!fixP->fx_done);
21609 if (!seg->use_rela_p)
21612 bfd_vma addend_abs = abs (value);
21614 /* Check that the absolute value of the addend can be
21615 encoded in 12 bits. */
21616 if (addend_abs >= 0x1000)
21617 as_bad_where (fixP->fx_file, fixP->fx_line,
21618 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21619 (unsigned long) addend_abs);
21621 /* Extract the instruction. */
21622 insn = md_chars_to_number (buf, INSN_SIZE);
21624 /* If the addend is negative, clear bit 23 of the instruction.
21625 Otherwise set it. */
21627 insn &= ~(1 << 23);
21631 /* Place the absolute value of the addend into the first 12 bits
21632 of the instruction. */
21633 insn &= 0xfffff000;
21634 insn |= addend_abs;
21636 /* Update the instruction. */
21637 md_number_to_chars (buf, insn, INSN_SIZE);
21641 case BFD_RELOC_ARM_LDRS_PC_G0:
21642 case BFD_RELOC_ARM_LDRS_PC_G1:
21643 case BFD_RELOC_ARM_LDRS_PC_G2:
21644 case BFD_RELOC_ARM_LDRS_SB_G0:
21645 case BFD_RELOC_ARM_LDRS_SB_G1:
21646 case BFD_RELOC_ARM_LDRS_SB_G2:
21647 gas_assert (!fixP->fx_done);
21648 if (!seg->use_rela_p)
21651 bfd_vma addend_abs = abs (value);
21653 /* Check that the absolute value of the addend can be
21654 encoded in 8 bits. */
21655 if (addend_abs >= 0x100)
21656 as_bad_where (fixP->fx_file, fixP->fx_line,
21657 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21658 (unsigned long) addend_abs);
21660 /* Extract the instruction. */
21661 insn = md_chars_to_number (buf, INSN_SIZE);
21663 /* If the addend is negative, clear bit 23 of the instruction.
21664 Otherwise set it. */
21666 insn &= ~(1 << 23);
21670 /* Place the first four bits of the absolute value of the addend
21671 into the first 4 bits of the instruction, and the remaining
21672 four into bits 8 .. 11. */
21673 insn &= 0xfffff0f0;
21674 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21676 /* Update the instruction. */
21677 md_number_to_chars (buf, insn, INSN_SIZE);
21681 case BFD_RELOC_ARM_LDC_PC_G0:
21682 case BFD_RELOC_ARM_LDC_PC_G1:
21683 case BFD_RELOC_ARM_LDC_PC_G2:
21684 case BFD_RELOC_ARM_LDC_SB_G0:
21685 case BFD_RELOC_ARM_LDC_SB_G1:
21686 case BFD_RELOC_ARM_LDC_SB_G2:
21687 gas_assert (!fixP->fx_done);
21688 if (!seg->use_rela_p)
21691 bfd_vma addend_abs = abs (value);
21693 /* Check that the absolute value of the addend is a multiple of
21694 four and, when divided by four, fits in 8 bits. */
21695 if (addend_abs & 0x3)
21696 as_bad_where (fixP->fx_file, fixP->fx_line,
21697 _("bad offset 0x%08lX (must be word-aligned)"),
21698 (unsigned long) addend_abs);
21700 if ((addend_abs >> 2) > 0xff)
21701 as_bad_where (fixP->fx_file, fixP->fx_line,
21702 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21703 (unsigned long) addend_abs);
21705 /* Extract the instruction. */
21706 insn = md_chars_to_number (buf, INSN_SIZE);
21708 /* If the addend is negative, clear bit 23 of the instruction.
21709 Otherwise set it. */
21711 insn &= ~(1 << 23);
21715 /* Place the addend (divided by four) into the first eight
21716 bits of the instruction. */
21717 insn &= 0xfffffff0;
21718 insn |= addend_abs >> 2;
21720 /* Update the instruction. */
21721 md_number_to_chars (buf, insn, INSN_SIZE);
21725 case BFD_RELOC_ARM_V4BX:
21726 /* This will need to go in the object file. */
21730 case BFD_RELOC_UNUSED:
21732 as_bad_where (fixP->fx_file, fixP->fx_line,
21733 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21737 /* Translate internal representation of relocation info to BFD target
21741 tc_gen_reloc (asection *section, fixS *fixp)
21744 bfd_reloc_code_real_type code;
21746 reloc = (arelent *) xmalloc (sizeof (arelent));
21748 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21749 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21750 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21752 if (fixp->fx_pcrel)
21754 if (section->use_rela_p)
21755 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21757 fixp->fx_offset = reloc->address;
21759 reloc->addend = fixp->fx_offset;
21761 switch (fixp->fx_r_type)
21764 if (fixp->fx_pcrel)
21766 code = BFD_RELOC_8_PCREL;
21771 if (fixp->fx_pcrel)
21773 code = BFD_RELOC_16_PCREL;
21778 if (fixp->fx_pcrel)
21780 code = BFD_RELOC_32_PCREL;
21784 case BFD_RELOC_ARM_MOVW:
21785 if (fixp->fx_pcrel)
21787 code = BFD_RELOC_ARM_MOVW_PCREL;
21791 case BFD_RELOC_ARM_MOVT:
21792 if (fixp->fx_pcrel)
21794 code = BFD_RELOC_ARM_MOVT_PCREL;
21798 case BFD_RELOC_ARM_THUMB_MOVW:
21799 if (fixp->fx_pcrel)
21801 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21805 case BFD_RELOC_ARM_THUMB_MOVT:
21806 if (fixp->fx_pcrel)
21808 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21812 case BFD_RELOC_NONE:
21813 case BFD_RELOC_ARM_PCREL_BRANCH:
21814 case BFD_RELOC_ARM_PCREL_BLX:
21815 case BFD_RELOC_RVA:
21816 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21817 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21818 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21819 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21820 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21821 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21822 case BFD_RELOC_VTABLE_ENTRY:
21823 case BFD_RELOC_VTABLE_INHERIT:
21825 case BFD_RELOC_32_SECREL:
21827 code = fixp->fx_r_type;
21830 case BFD_RELOC_THUMB_PCREL_BLX:
21832 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21833 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21836 code = BFD_RELOC_THUMB_PCREL_BLX;
21839 case BFD_RELOC_ARM_LITERAL:
21840 case BFD_RELOC_ARM_HWLITERAL:
21841 /* If this is called then the a literal has
21842 been referenced across a section boundary. */
21843 as_bad_where (fixp->fx_file, fixp->fx_line,
21844 _("literal referenced across section boundary"));
21848 case BFD_RELOC_ARM_TLS_CALL:
21849 case BFD_RELOC_ARM_THM_TLS_CALL:
21850 case BFD_RELOC_ARM_TLS_DESCSEQ:
21851 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21852 case BFD_RELOC_ARM_GOT32:
21853 case BFD_RELOC_ARM_GOTOFF:
21854 case BFD_RELOC_ARM_GOT_PREL:
21855 case BFD_RELOC_ARM_PLT32:
21856 case BFD_RELOC_ARM_TARGET1:
21857 case BFD_RELOC_ARM_ROSEGREL32:
21858 case BFD_RELOC_ARM_SBREL32:
21859 case BFD_RELOC_ARM_PREL31:
21860 case BFD_RELOC_ARM_TARGET2:
21861 case BFD_RELOC_ARM_TLS_LE32:
21862 case BFD_RELOC_ARM_TLS_LDO32:
21863 case BFD_RELOC_ARM_PCREL_CALL:
21864 case BFD_RELOC_ARM_PCREL_JUMP:
21865 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21866 case BFD_RELOC_ARM_ALU_PC_G0:
21867 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21868 case BFD_RELOC_ARM_ALU_PC_G1:
21869 case BFD_RELOC_ARM_ALU_PC_G2:
21870 case BFD_RELOC_ARM_LDR_PC_G0:
21871 case BFD_RELOC_ARM_LDR_PC_G1:
21872 case BFD_RELOC_ARM_LDR_PC_G2:
21873 case BFD_RELOC_ARM_LDRS_PC_G0:
21874 case BFD_RELOC_ARM_LDRS_PC_G1:
21875 case BFD_RELOC_ARM_LDRS_PC_G2:
21876 case BFD_RELOC_ARM_LDC_PC_G0:
21877 case BFD_RELOC_ARM_LDC_PC_G1:
21878 case BFD_RELOC_ARM_LDC_PC_G2:
21879 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21880 case BFD_RELOC_ARM_ALU_SB_G0:
21881 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21882 case BFD_RELOC_ARM_ALU_SB_G1:
21883 case BFD_RELOC_ARM_ALU_SB_G2:
21884 case BFD_RELOC_ARM_LDR_SB_G0:
21885 case BFD_RELOC_ARM_LDR_SB_G1:
21886 case BFD_RELOC_ARM_LDR_SB_G2:
21887 case BFD_RELOC_ARM_LDRS_SB_G0:
21888 case BFD_RELOC_ARM_LDRS_SB_G1:
21889 case BFD_RELOC_ARM_LDRS_SB_G2:
21890 case BFD_RELOC_ARM_LDC_SB_G0:
21891 case BFD_RELOC_ARM_LDC_SB_G1:
21892 case BFD_RELOC_ARM_LDC_SB_G2:
21893 case BFD_RELOC_ARM_V4BX:
21894 code = fixp->fx_r_type;
21897 case BFD_RELOC_ARM_TLS_GOTDESC:
21898 case BFD_RELOC_ARM_TLS_GD32:
21899 case BFD_RELOC_ARM_TLS_IE32:
21900 case BFD_RELOC_ARM_TLS_LDM32:
21901 /* BFD will include the symbol's address in the addend.
21902 But we don't want that, so subtract it out again here. */
21903 if (!S_IS_COMMON (fixp->fx_addsy))
21904 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21905 code = fixp->fx_r_type;
21909 case BFD_RELOC_ARM_IMMEDIATE:
21910 as_bad_where (fixp->fx_file, fixp->fx_line,
21911 _("internal relocation (type: IMMEDIATE) not fixed up"));
21914 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21915 as_bad_where (fixp->fx_file, fixp->fx_line,
21916 _("ADRL used for a symbol not defined in the same file"));
21919 case BFD_RELOC_ARM_OFFSET_IMM:
21920 if (section->use_rela_p)
21922 code = fixp->fx_r_type;
21926 if (fixp->fx_addsy != NULL
21927 && !S_IS_DEFINED (fixp->fx_addsy)
21928 && S_IS_LOCAL (fixp->fx_addsy))
21930 as_bad_where (fixp->fx_file, fixp->fx_line,
21931 _("undefined local label `%s'"),
21932 S_GET_NAME (fixp->fx_addsy));
21936 as_bad_where (fixp->fx_file, fixp->fx_line,
21937 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21944 switch (fixp->fx_r_type)
21946 case BFD_RELOC_NONE: type = "NONE"; break;
21947 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21948 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21949 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21950 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21951 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21952 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21953 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21954 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21955 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21956 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21957 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21958 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21959 default: type = _("<unknown>"); break;
21961 as_bad_where (fixp->fx_file, fixp->fx_line,
21962 _("cannot represent %s relocation in this object file format"),
21969 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21971 && fixp->fx_addsy == GOT_symbol)
21973 code = BFD_RELOC_ARM_GOTPC;
21974 reloc->addend = fixp->fx_offset = reloc->address;
21978 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21980 if (reloc->howto == NULL)
21982 as_bad_where (fixp->fx_file, fixp->fx_line,
21983 _("cannot represent %s relocation in this object file format"),
21984 bfd_get_reloc_code_name (code));
21988 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21989 vtable entry to be used in the relocation's section offset. */
21990 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21991 reloc->address = fixp->fx_offset;
21996 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21999 cons_fix_new_arm (fragS * frag,
22004 bfd_reloc_code_real_type type;
22008 FIXME: @@ Should look at CPU word size. */
22012 type = BFD_RELOC_8;
22015 type = BFD_RELOC_16;
22019 type = BFD_RELOC_32;
22022 type = BFD_RELOC_64;
22027 if (exp->X_op == O_secrel)
22029 exp->X_op = O_symbol;
22030 type = BFD_RELOC_32_SECREL;
22034 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22037 #if defined (OBJ_COFF)
22039 arm_validate_fix (fixS * fixP)
22041 /* If the destination of the branch is a defined symbol which does not have
22042 the THUMB_FUNC attribute, then we must be calling a function which has
22043 the (interfacearm) attribute. We look for the Thumb entry point to that
22044 function and change the branch to refer to that function instead. */
22045 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22046 && fixP->fx_addsy != NULL
22047 && S_IS_DEFINED (fixP->fx_addsy)
22048 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22050 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22057 arm_force_relocation (struct fix * fixp)
22059 #if defined (OBJ_COFF) && defined (TE_PE)
22060 if (fixp->fx_r_type == BFD_RELOC_RVA)
22064 /* In case we have a call or a branch to a function in ARM ISA mode from
22065 a thumb function or vice-versa force the relocation. These relocations
22066 are cleared off for some cores that might have blx and simple transformations
22070 switch (fixp->fx_r_type)
22072 case BFD_RELOC_ARM_PCREL_JUMP:
22073 case BFD_RELOC_ARM_PCREL_CALL:
22074 case BFD_RELOC_THUMB_PCREL_BLX:
22075 if (THUMB_IS_FUNC (fixp->fx_addsy))
22079 case BFD_RELOC_ARM_PCREL_BLX:
22080 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22081 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22082 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22083 if (ARM_IS_FUNC (fixp->fx_addsy))
22092 /* Resolve these relocations even if the symbol is extern or weak.
22093 Technically this is probably wrong due to symbol preemption.
22094 In practice these relocations do not have enough range to be useful
22095 at dynamic link time, and some code (e.g. in the Linux kernel)
22096 expects these references to be resolved. */
22097 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22098 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22099 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22100 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22101 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22102 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22103 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22104 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22105 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22106 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22107 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22108 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22109 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22110 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22113 /* Always leave these relocations for the linker. */
22114 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22115 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22116 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22119 /* Always generate relocations against function symbols. */
22120 if (fixp->fx_r_type == BFD_RELOC_32
22122 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22125 return generic_force_reloc (fixp);
22128 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22129 /* Relocations against function names must be left unadjusted,
22130 so that the linker can use this information to generate interworking
22131 stubs. The MIPS version of this function
22132 also prevents relocations that are mips-16 specific, but I do not
22133 know why it does this.
22136 There is one other problem that ought to be addressed here, but
22137 which currently is not: Taking the address of a label (rather
22138 than a function) and then later jumping to that address. Such
22139 addresses also ought to have their bottom bit set (assuming that
22140 they reside in Thumb code), but at the moment they will not. */
22143 arm_fix_adjustable (fixS * fixP)
22145 if (fixP->fx_addsy == NULL)
22148 /* Preserve relocations against symbols with function type. */
22149 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22152 if (THUMB_IS_FUNC (fixP->fx_addsy)
22153 && fixP->fx_subsy == NULL)
22156 /* We need the symbol name for the VTABLE entries. */
22157 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22158 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22161 /* Don't allow symbols to be discarded on GOT related relocs. */
22162 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22163 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22164 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22165 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22166 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22167 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22168 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22169 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22170 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22171 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22172 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22173 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22174 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22175 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22178 /* Similarly for group relocations. */
22179 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22180 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22181 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22184 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22185 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22186 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22187 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22188 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22189 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22190 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22191 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22192 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22197 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22202 elf32_arm_target_format (void)
22205 return (target_big_endian
22206 ? "elf32-bigarm-symbian"
22207 : "elf32-littlearm-symbian");
22208 #elif defined (TE_VXWORKS)
22209 return (target_big_endian
22210 ? "elf32-bigarm-vxworks"
22211 : "elf32-littlearm-vxworks");
22213 if (target_big_endian)
22214 return "elf32-bigarm";
22216 return "elf32-littlearm";
22221 armelf_frob_symbol (symbolS * symp,
22224 elf_frob_symbol (symp, puntp);
22228 /* MD interface: Finalization. */
22233 literal_pool * pool;
22235 /* Ensure that all the IT blocks are properly closed. */
22236 check_it_blocks_finished ();
22238 for (pool = list_of_pools; pool; pool = pool->next)
22240 /* Put it at the end of the relevant section. */
22241 subseg_set (pool->section, pool->sub_section);
22243 arm_elf_change_section ();
22250 /* Remove any excess mapping symbols generated for alignment frags in
22251 SEC. We may have created a mapping symbol before a zero byte
22252 alignment; remove it if there's a mapping symbol after the
22255 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22256 void *dummy ATTRIBUTE_UNUSED)
22258 segment_info_type *seginfo = seg_info (sec);
22261 if (seginfo == NULL || seginfo->frchainP == NULL)
22264 for (fragp = seginfo->frchainP->frch_root;
22266 fragp = fragp->fr_next)
22268 symbolS *sym = fragp->tc_frag_data.last_map;
22269 fragS *next = fragp->fr_next;
22271 /* Variable-sized frags have been converted to fixed size by
22272 this point. But if this was variable-sized to start with,
22273 there will be a fixed-size frag after it. So don't handle
22275 if (sym == NULL || next == NULL)
22278 if (S_GET_VALUE (sym) < next->fr_address)
22279 /* Not at the end of this frag. */
22281 know (S_GET_VALUE (sym) == next->fr_address);
22285 if (next->tc_frag_data.first_map != NULL)
22287 /* Next frag starts with a mapping symbol. Discard this
22289 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22293 if (next->fr_next == NULL)
22295 /* This mapping symbol is at the end of the section. Discard
22297 know (next->fr_fix == 0 && next->fr_var == 0);
22298 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22302 /* As long as we have empty frags without any mapping symbols,
22304 /* If the next frag is non-empty and does not start with a
22305 mapping symbol, then this mapping symbol is required. */
22306 if (next->fr_address != next->fr_next->fr_address)
22309 next = next->fr_next;
22311 while (next != NULL);
22316 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22320 arm_adjust_symtab (void)
22325 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22327 if (ARM_IS_THUMB (sym))
22329 if (THUMB_IS_FUNC (sym))
22331 /* Mark the symbol as a Thumb function. */
22332 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22333 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22334 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22336 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22337 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22339 as_bad (_("%s: unexpected function type: %d"),
22340 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22342 else switch (S_GET_STORAGE_CLASS (sym))
22345 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22348 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22351 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22359 if (ARM_IS_INTERWORK (sym))
22360 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22367 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22369 if (ARM_IS_THUMB (sym))
22371 elf_symbol_type * elf_sym;
22373 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22374 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22376 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22377 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22379 /* If it's a .thumb_func, declare it as so,
22380 otherwise tag label as .code 16. */
22381 if (THUMB_IS_FUNC (sym))
22382 elf_sym->internal_elf_sym.st_target_internal
22383 = ST_BRANCH_TO_THUMB;
22384 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22385 elf_sym->internal_elf_sym.st_info =
22386 ELF_ST_INFO (bind, STT_ARM_16BIT);
22391 /* Remove any overlapping mapping symbols generated by alignment frags. */
22392 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22393 /* Now do generic ELF adjustments. */
22394 elf_adjust_symtab ();
22398 /* MD interface: Initialization. */
22401 set_constant_flonums (void)
22405 for (i = 0; i < NUM_FLOAT_VALS; i++)
22406 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22410 /* Auto-select Thumb mode if it's the only available instruction set for the
22411 given architecture. */
22414 autoselect_thumb_from_cpu_variant (void)
22416 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22417 opcode_select (16);
22426 if ( (arm_ops_hsh = hash_new ()) == NULL
22427 || (arm_cond_hsh = hash_new ()) == NULL
22428 || (arm_shift_hsh = hash_new ()) == NULL
22429 || (arm_psr_hsh = hash_new ()) == NULL
22430 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22431 || (arm_reg_hsh = hash_new ()) == NULL
22432 || (arm_reloc_hsh = hash_new ()) == NULL
22433 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22434 as_fatal (_("virtual memory exhausted"));
22436 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22437 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22438 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22439 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22440 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22441 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22442 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22443 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22444 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22445 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22446 (void *) (v7m_psrs + i));
22447 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22448 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22450 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22452 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22453 (void *) (barrier_opt_names + i));
22455 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22457 struct reloc_entry * entry = reloc_names + i;
22459 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22460 /* This makes encode_branch() use the EABI versions of this relocation. */
22461 entry->reloc = BFD_RELOC_UNUSED;
22463 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22467 set_constant_flonums ();
22469 /* Set the cpu variant based on the command-line options. We prefer
22470 -mcpu= over -march= if both are set (as for GCC); and we prefer
22471 -mfpu= over any other way of setting the floating point unit.
22472 Use of legacy options with new options are faulted. */
22475 if (mcpu_cpu_opt || march_cpu_opt)
22476 as_bad (_("use of old and new-style options to set CPU type"));
22478 mcpu_cpu_opt = legacy_cpu;
22480 else if (!mcpu_cpu_opt)
22481 mcpu_cpu_opt = march_cpu_opt;
22486 as_bad (_("use of old and new-style options to set FPU type"));
22488 mfpu_opt = legacy_fpu;
22490 else if (!mfpu_opt)
22492 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22493 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22494 /* Some environments specify a default FPU. If they don't, infer it
22495 from the processor. */
22497 mfpu_opt = mcpu_fpu_opt;
22499 mfpu_opt = march_fpu_opt;
22501 mfpu_opt = &fpu_default;
22507 if (mcpu_cpu_opt != NULL)
22508 mfpu_opt = &fpu_default;
22509 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22510 mfpu_opt = &fpu_arch_vfp_v2;
22512 mfpu_opt = &fpu_arch_fpa;
22518 mcpu_cpu_opt = &cpu_default;
22519 selected_cpu = cpu_default;
22523 selected_cpu = *mcpu_cpu_opt;
22525 mcpu_cpu_opt = &arm_arch_any;
22528 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22530 autoselect_thumb_from_cpu_variant ();
22532 arm_arch_used = thumb_arch_used = arm_arch_none;
22534 #if defined OBJ_COFF || defined OBJ_ELF
22536 unsigned int flags = 0;
22538 #if defined OBJ_ELF
22539 flags = meabi_flags;
22541 switch (meabi_flags)
22543 case EF_ARM_EABI_UNKNOWN:
22545 /* Set the flags in the private structure. */
22546 if (uses_apcs_26) flags |= F_APCS26;
22547 if (support_interwork) flags |= F_INTERWORK;
22548 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22549 if (pic_code) flags |= F_PIC;
22550 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22551 flags |= F_SOFT_FLOAT;
22553 switch (mfloat_abi_opt)
22555 case ARM_FLOAT_ABI_SOFT:
22556 case ARM_FLOAT_ABI_SOFTFP:
22557 flags |= F_SOFT_FLOAT;
22560 case ARM_FLOAT_ABI_HARD:
22561 if (flags & F_SOFT_FLOAT)
22562 as_bad (_("hard-float conflicts with specified fpu"));
22566 /* Using pure-endian doubles (even if soft-float). */
22567 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22568 flags |= F_VFP_FLOAT;
22570 #if defined OBJ_ELF
22571 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22572 flags |= EF_ARM_MAVERICK_FLOAT;
22575 case EF_ARM_EABI_VER4:
22576 case EF_ARM_EABI_VER5:
22577 /* No additional flags to set. */
22584 bfd_set_private_flags (stdoutput, flags);
22586 /* We have run out flags in the COFF header to encode the
22587 status of ATPCS support, so instead we create a dummy,
22588 empty, debug section called .arm.atpcs. */
22593 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22597 bfd_set_section_flags
22598 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22599 bfd_set_section_size (stdoutput, sec, 0);
22600 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22606 /* Record the CPU type as well. */
22607 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22608 mach = bfd_mach_arm_iWMMXt2;
22609 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22610 mach = bfd_mach_arm_iWMMXt;
22611 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22612 mach = bfd_mach_arm_XScale;
22613 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22614 mach = bfd_mach_arm_ep9312;
22615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22616 mach = bfd_mach_arm_5TE;
22617 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22619 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22620 mach = bfd_mach_arm_5T;
22622 mach = bfd_mach_arm_5;
22624 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22626 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22627 mach = bfd_mach_arm_4T;
22629 mach = bfd_mach_arm_4;
22631 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22632 mach = bfd_mach_arm_3M;
22633 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22634 mach = bfd_mach_arm_3;
22635 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22636 mach = bfd_mach_arm_2a;
22637 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22638 mach = bfd_mach_arm_2;
22640 mach = bfd_mach_arm_unknown;
22642 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22645 /* Command line processing. */
22648 Invocation line includes a switch not recognized by the base assembler.
22649 See if it's a processor-specific option.
22651 This routine is somewhat complicated by the need for backwards
22652 compatibility (since older releases of gcc can't be changed).
22653 The new options try to make the interface as compatible as
22656 New options (supported) are:
22658 -mcpu=<cpu name> Assemble for selected processor
22659 -march=<architecture name> Assemble for selected architecture
22660 -mfpu=<fpu architecture> Assemble for selected FPU.
22661 -EB/-mbig-endian Big-endian
22662 -EL/-mlittle-endian Little-endian
22663 -k Generate PIC code
22664 -mthumb Start in Thumb mode
22665 -mthumb-interwork Code supports ARM/Thumb interworking
22667 -m[no-]warn-deprecated Warn about deprecated features
22669 For now we will also provide support for:
22671 -mapcs-32 32-bit Program counter
22672 -mapcs-26 26-bit Program counter
22673 -macps-float Floats passed in FP registers
22674 -mapcs-reentrant Reentrant code
22676 (sometime these will probably be replaced with -mapcs=<list of options>
22677 and -matpcs=<list of options>)
22679 The remaining options are only supported for back-wards compatibility.
22680 Cpu variants, the arm part is optional:
22681 -m[arm]1 Currently not supported.
22682 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22683 -m[arm]3 Arm 3 processor
22684 -m[arm]6[xx], Arm 6 processors
22685 -m[arm]7[xx][t][[d]m] Arm 7 processors
22686 -m[arm]8[10] Arm 8 processors
22687 -m[arm]9[20][tdmi] Arm 9 processors
22688 -mstrongarm[110[0]] StrongARM processors
22689 -mxscale XScale processors
22690 -m[arm]v[2345[t[e]]] Arm architectures
22691 -mall All (except the ARM1)
22693 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22694 -mfpe-old (No float load/store multiples)
22695 -mvfpxd VFP Single precision
22697 -mno-fpu Disable all floating point instructions
22699 The following CPU names are recognized:
22700 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22701 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22702 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22703 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22704 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22705 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22706 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22710 const char * md_shortopts = "m:k";
22712 #ifdef ARM_BI_ENDIAN
22713 #define OPTION_EB (OPTION_MD_BASE + 0)
22714 #define OPTION_EL (OPTION_MD_BASE + 1)
22716 #if TARGET_BYTES_BIG_ENDIAN
22717 #define OPTION_EB (OPTION_MD_BASE + 0)
22719 #define OPTION_EL (OPTION_MD_BASE + 1)
22722 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22724 struct option md_longopts[] =
22727 {"EB", no_argument, NULL, OPTION_EB},
22730 {"EL", no_argument, NULL, OPTION_EL},
22732 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22733 {NULL, no_argument, NULL, 0}
22736 size_t md_longopts_size = sizeof (md_longopts);
22738 struct arm_option_table
22740 char *option; /* Option name to match. */
22741 char *help; /* Help information. */
22742 int *var; /* Variable to change. */
22743 int value; /* What to change it to. */
22744 char *deprecated; /* If non-null, print this message. */
22747 struct arm_option_table arm_opts[] =
22749 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22750 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22751 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22752 &support_interwork, 1, NULL},
22753 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22754 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22755 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22757 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22758 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22759 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22760 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22763 /* These are recognized by the assembler, but have no affect on code. */
22764 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22765 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22767 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22768 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22769 &warn_on_deprecated, 0, NULL},
22770 {NULL, NULL, NULL, 0, NULL}
22773 struct arm_legacy_option_table
22775 char *option; /* Option name to match. */
22776 const arm_feature_set **var; /* Variable to change. */
22777 const arm_feature_set value; /* What to change it to. */
22778 char *deprecated; /* If non-null, print this message. */
22781 const struct arm_legacy_option_table arm_legacy_opts[] =
22783 /* DON'T add any new processors to this list -- we want the whole list
22784 to go away... Add them to the processors table instead. */
22785 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22786 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22787 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22788 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22789 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22790 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22791 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22792 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22793 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22794 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22795 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22796 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22797 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22798 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22799 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22800 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22801 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22802 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22803 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22804 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22805 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22806 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22807 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22808 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22809 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22810 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22811 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22812 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22813 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22814 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22815 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22816 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22817 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22818 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22819 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22820 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22821 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22822 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22823 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22824 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22825 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22826 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22827 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22828 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22829 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22830 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22831 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22832 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22833 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22834 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22835 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22836 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22837 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22838 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22839 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22840 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22841 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22842 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22843 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22844 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22845 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22846 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22847 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22848 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22849 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22850 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22851 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22852 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22853 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22854 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22855 N_("use -mcpu=strongarm110")},
22856 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22857 N_("use -mcpu=strongarm1100")},
22858 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22859 N_("use -mcpu=strongarm1110")},
22860 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22861 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22862 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22864 /* Architecture variants -- don't add any more to this list either. */
22865 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22866 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22867 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22868 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22869 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22870 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22871 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22872 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22873 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22874 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22875 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22876 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22877 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22878 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22879 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22880 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22881 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22882 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22884 /* Floating point variants -- don't add any more to this list either. */
22885 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22886 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22887 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22888 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22889 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22891 {NULL, NULL, ARM_ARCH_NONE, NULL}
22894 struct arm_cpu_option_table
22898 const arm_feature_set value;
22899 /* For some CPUs we assume an FPU unless the user explicitly sets
22901 const arm_feature_set default_fpu;
22902 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22904 const char *canonical_name;
22907 /* This list should, at a minimum, contain all the cpu names
22908 recognized by GCC. */
22909 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
22910 static const struct arm_cpu_option_table arm_cpus[] =
22912 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
22913 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
22914 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
22915 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
22916 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
22917 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22918 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22919 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22920 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22921 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22922 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22923 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22924 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22925 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22926 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22927 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22928 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22929 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22930 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22931 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22932 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22933 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22934 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22935 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22936 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22937 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22938 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22939 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22940 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22941 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22942 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22943 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22944 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22945 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22946 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22947 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22948 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22949 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22950 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22951 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
22952 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22953 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22954 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22955 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22956 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22957 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22958 /* For V5 or later processors we default to using VFP; but the user
22959 should really set the FPU type explicitly. */
22960 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22961 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22962 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
22963 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
22964 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
22965 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22966 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
22967 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22968 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22969 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
22970 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22971 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22972 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22973 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22974 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22975 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
22976 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22977 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22978 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22979 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
22981 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
22982 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22983 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22984 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22985 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22986 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22987 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
22988 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
22989 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
22991 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
22992 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
22993 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
22994 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
22995 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
22996 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
22997 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
22998 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
22999 FPU_NONE, "Cortex-A5"),
23000 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23001 FPU_ARCH_NEON_VFP_V4,
23003 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23004 ARM_FEATURE (0, FPU_VFP_V3
23005 | FPU_NEON_EXT_V1),
23007 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23008 ARM_FEATURE (0, FPU_VFP_V3
23009 | FPU_NEON_EXT_V1),
23011 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23012 FPU_ARCH_NEON_VFP_V4,
23014 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23015 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23017 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23018 FPU_NONE, "Cortex-R5"),
23019 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23020 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23021 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23022 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23023 /* ??? XSCALE is really an architecture. */
23024 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23025 /* ??? iwmmxt is not a processor. */
23026 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23027 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23028 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23030 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23033 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23037 struct arm_arch_option_table
23041 const arm_feature_set value;
23042 const arm_feature_set default_fpu;
23045 /* This list should, at a minimum, contain all the architecture names
23046 recognized by GCC. */
23047 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23048 static const struct arm_arch_option_table arm_archs[] =
23050 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23051 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23052 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23053 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23054 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23055 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23056 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23057 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23058 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23059 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23060 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23061 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23062 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23063 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23064 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23065 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23066 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23067 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23068 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23069 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23070 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23071 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23072 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23073 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23074 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23075 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23076 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23077 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23078 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23079 /* The official spelling of the ARMv7 profile variants is the dashed form.
23080 Accept the non-dashed form for compatibility with old toolchains. */
23081 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23082 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23083 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23084 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23085 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23086 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23087 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23088 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23089 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23090 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23091 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23093 #undef ARM_ARCH_OPT
23095 /* ISA extensions in the co-processor and main instruction set space. */
23096 struct arm_option_extension_value_table
23100 const arm_feature_set value;
23101 const arm_feature_set allowed_archs;
23104 /* The following table must be in alphabetical order with a NULL last entry.
23106 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23107 static const struct arm_option_extension_value_table arm_extensions[] =
23109 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23110 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23111 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23112 ARM_EXT_OPT ("iwmmxt2",
23113 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23114 ARM_EXT_OPT ("maverick",
23115 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23116 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23117 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23118 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23119 ARM_FEATURE (ARM_EXT_V6M, 0)),
23120 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23121 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23122 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23124 ARM_FEATURE (ARM_EXT_V7A, 0)),
23125 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23126 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23130 /* ISA floating-point and Advanced SIMD extensions. */
23131 struct arm_option_fpu_value_table
23134 const arm_feature_set value;
23137 /* This list should, at a minimum, contain all the fpu names
23138 recognized by GCC. */
23139 static const struct arm_option_fpu_value_table arm_fpus[] =
23141 {"softfpa", FPU_NONE},
23142 {"fpe", FPU_ARCH_FPE},
23143 {"fpe2", FPU_ARCH_FPE},
23144 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23145 {"fpa", FPU_ARCH_FPA},
23146 {"fpa10", FPU_ARCH_FPA},
23147 {"fpa11", FPU_ARCH_FPA},
23148 {"arm7500fe", FPU_ARCH_FPA},
23149 {"softvfp", FPU_ARCH_VFP},
23150 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23151 {"vfp", FPU_ARCH_VFP_V2},
23152 {"vfp9", FPU_ARCH_VFP_V2},
23153 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23154 {"vfp10", FPU_ARCH_VFP_V2},
23155 {"vfp10-r0", FPU_ARCH_VFP_V1},
23156 {"vfpxd", FPU_ARCH_VFP_V1xD},
23157 {"vfpv2", FPU_ARCH_VFP_V2},
23158 {"vfpv3", FPU_ARCH_VFP_V3},
23159 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23160 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23161 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23162 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23163 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23164 {"arm1020t", FPU_ARCH_VFP_V1},
23165 {"arm1020e", FPU_ARCH_VFP_V2},
23166 {"arm1136jfs", FPU_ARCH_VFP_V2},
23167 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23168 {"maverick", FPU_ARCH_MAVERICK},
23169 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23170 {"neon-fp16", FPU_ARCH_NEON_FP16},
23171 {"vfpv4", FPU_ARCH_VFP_V4},
23172 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23173 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23174 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23175 {NULL, ARM_ARCH_NONE}
23178 struct arm_option_value_table
23184 static const struct arm_option_value_table arm_float_abis[] =
23186 {"hard", ARM_FLOAT_ABI_HARD},
23187 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23188 {"soft", ARM_FLOAT_ABI_SOFT},
23193 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23194 static const struct arm_option_value_table arm_eabis[] =
23196 {"gnu", EF_ARM_EABI_UNKNOWN},
23197 {"4", EF_ARM_EABI_VER4},
23198 {"5", EF_ARM_EABI_VER5},
23203 struct arm_long_option_table
23205 char * option; /* Substring to match. */
23206 char * help; /* Help information. */
23207 int (* func) (char * subopt); /* Function to decode sub-option. */
23208 char * deprecated; /* If non-null, print this message. */
23212 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23214 arm_feature_set *ext_set = (arm_feature_set *)
23215 xmalloc (sizeof (arm_feature_set));
23217 /* We insist on extensions being specified in alphabetical order, and with
23218 extensions being added before being removed. We achieve this by having
23219 the global ARM_EXTENSIONS table in alphabetical order, and using the
23220 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23221 or removing it (0) and only allowing it to change in the order
23223 const struct arm_option_extension_value_table * opt = NULL;
23224 int adding_value = -1;
23226 /* Copy the feature set, so that we can modify it. */
23227 *ext_set = **opt_p;
23230 while (str != NULL && *str != 0)
23237 as_bad (_("invalid architectural extension"));
23242 ext = strchr (str, '+');
23247 len = strlen (str);
23249 if (len >= 2 && strncmp (str, "no", 2) == 0)
23251 if (adding_value != 0)
23254 opt = arm_extensions;
23262 if (adding_value == -1)
23265 opt = arm_extensions;
23267 else if (adding_value != 1)
23269 as_bad (_("must specify extensions to add before specifying "
23270 "those to remove"));
23277 as_bad (_("missing architectural extension"));
23281 gas_assert (adding_value != -1);
23282 gas_assert (opt != NULL);
23284 /* Scan over the options table trying to find an exact match. */
23285 for (; opt->name != NULL; opt++)
23286 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23288 /* Check we can apply the extension to this architecture. */
23289 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23291 as_bad (_("extension does not apply to the base architecture"));
23295 /* Add or remove the extension. */
23297 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23299 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23304 if (opt->name == NULL)
23306 /* Did we fail to find an extension because it wasn't specified in
23307 alphabetical order, or because it does not exist? */
23309 for (opt = arm_extensions; opt->name != NULL; opt++)
23310 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23313 if (opt->name == NULL)
23314 as_bad (_("unknown architectural extension `%s'"), str);
23316 as_bad (_("architectural extensions must be specified in "
23317 "alphabetical order"));
23323 /* We should skip the extension we've just matched the next time
23335 arm_parse_cpu (char *str)
23337 const struct arm_cpu_option_table *opt;
23338 char *ext = strchr (str, '+');
23344 len = strlen (str);
23348 as_bad (_("missing cpu name `%s'"), str);
23352 for (opt = arm_cpus; opt->name != NULL; opt++)
23353 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23355 mcpu_cpu_opt = &opt->value;
23356 mcpu_fpu_opt = &opt->default_fpu;
23357 if (opt->canonical_name)
23358 strcpy (selected_cpu_name, opt->canonical_name);
23363 for (i = 0; i < len; i++)
23364 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23365 selected_cpu_name[i] = 0;
23369 return arm_parse_extension (ext, &mcpu_cpu_opt);
23374 as_bad (_("unknown cpu `%s'"), str);
23379 arm_parse_arch (char *str)
23381 const struct arm_arch_option_table *opt;
23382 char *ext = strchr (str, '+');
23388 len = strlen (str);
23392 as_bad (_("missing architecture name `%s'"), str);
23396 for (opt = arm_archs; opt->name != NULL; opt++)
23397 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23399 march_cpu_opt = &opt->value;
23400 march_fpu_opt = &opt->default_fpu;
23401 strcpy (selected_cpu_name, opt->name);
23404 return arm_parse_extension (ext, &march_cpu_opt);
23409 as_bad (_("unknown architecture `%s'\n"), str);
23414 arm_parse_fpu (char * str)
23416 const struct arm_option_fpu_value_table * opt;
23418 for (opt = arm_fpus; opt->name != NULL; opt++)
23419 if (streq (opt->name, str))
23421 mfpu_opt = &opt->value;
23425 as_bad (_("unknown floating point format `%s'\n"), str);
23430 arm_parse_float_abi (char * str)
23432 const struct arm_option_value_table * opt;
23434 for (opt = arm_float_abis; opt->name != NULL; opt++)
23435 if (streq (opt->name, str))
23437 mfloat_abi_opt = opt->value;
23441 as_bad (_("unknown floating point abi `%s'\n"), str);
23447 arm_parse_eabi (char * str)
23449 const struct arm_option_value_table *opt;
23451 for (opt = arm_eabis; opt->name != NULL; opt++)
23452 if (streq (opt->name, str))
23454 meabi_flags = opt->value;
23457 as_bad (_("unknown EABI `%s'\n"), str);
23463 arm_parse_it_mode (char * str)
23465 bfd_boolean ret = TRUE;
23467 if (streq ("arm", str))
23468 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23469 else if (streq ("thumb", str))
23470 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23471 else if (streq ("always", str))
23472 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23473 else if (streq ("never", str))
23474 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23477 as_bad (_("unknown implicit IT mode `%s', should be "\
23478 "arm, thumb, always, or never."), str);
23485 struct arm_long_option_table arm_long_opts[] =
23487 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23488 arm_parse_cpu, NULL},
23489 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23490 arm_parse_arch, NULL},
23491 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23492 arm_parse_fpu, NULL},
23493 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23494 arm_parse_float_abi, NULL},
23496 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23497 arm_parse_eabi, NULL},
23499 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23500 arm_parse_it_mode, NULL},
23501 {NULL, NULL, 0, NULL}
23505 md_parse_option (int c, char * arg)
23507 struct arm_option_table *opt;
23508 const struct arm_legacy_option_table *fopt;
23509 struct arm_long_option_table *lopt;
23515 target_big_endian = 1;
23521 target_big_endian = 0;
23525 case OPTION_FIX_V4BX:
23530 /* Listing option. Just ignore these, we don't support additional
23535 for (opt = arm_opts; opt->option != NULL; opt++)
23537 if (c == opt->option[0]
23538 && ((arg == NULL && opt->option[1] == 0)
23539 || streq (arg, opt->option + 1)))
23541 /* If the option is deprecated, tell the user. */
23542 if (warn_on_deprecated && opt->deprecated != NULL)
23543 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23544 arg ? arg : "", _(opt->deprecated));
23546 if (opt->var != NULL)
23547 *opt->var = opt->value;
23553 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23555 if (c == fopt->option[0]
23556 && ((arg == NULL && fopt->option[1] == 0)
23557 || streq (arg, fopt->option + 1)))
23559 /* If the option is deprecated, tell the user. */
23560 if (warn_on_deprecated && fopt->deprecated != NULL)
23561 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23562 arg ? arg : "", _(fopt->deprecated));
23564 if (fopt->var != NULL)
23565 *fopt->var = &fopt->value;
23571 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23573 /* These options are expected to have an argument. */
23574 if (c == lopt->option[0]
23576 && strncmp (arg, lopt->option + 1,
23577 strlen (lopt->option + 1)) == 0)
23579 /* If the option is deprecated, tell the user. */
23580 if (warn_on_deprecated && lopt->deprecated != NULL)
23581 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23582 _(lopt->deprecated));
23584 /* Call the sup-option parser. */
23585 return lopt->func (arg + strlen (lopt->option) - 1);
23596 md_show_usage (FILE * fp)
23598 struct arm_option_table *opt;
23599 struct arm_long_option_table *lopt;
23601 fprintf (fp, _(" ARM-specific assembler options:\n"));
23603 for (opt = arm_opts; opt->option != NULL; opt++)
23604 if (opt->help != NULL)
23605 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23607 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23608 if (lopt->help != NULL)
23609 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23613 -EB assemble code for a big-endian cpu\n"));
23618 -EL assemble code for a little-endian cpu\n"));
23622 --fix-v4bx Allow BX in ARMv4 code\n"));
23630 arm_feature_set flags;
23631 } cpu_arch_ver_table;
23633 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23634 least features first. */
23635 static const cpu_arch_ver_table cpu_arch_ver[] =
23641 {4, ARM_ARCH_V5TE},
23642 {5, ARM_ARCH_V5TEJ},
23646 {11, ARM_ARCH_V6M},
23647 {12, ARM_ARCH_V6SM},
23648 {8, ARM_ARCH_V6T2},
23649 {10, ARM_ARCH_V7A},
23650 {10, ARM_ARCH_V7R},
23651 {10, ARM_ARCH_V7M},
23655 /* Set an attribute if it has not already been set by the user. */
23657 aeabi_set_attribute_int (int tag, int value)
23660 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23661 || !attributes_set_explicitly[tag])
23662 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23666 aeabi_set_attribute_string (int tag, const char *value)
23669 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23670 || !attributes_set_explicitly[tag])
23671 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23674 /* Set the public EABI object attributes. */
23676 aeabi_set_public_attributes (void)
23680 arm_feature_set flags;
23681 arm_feature_set tmp;
23682 const cpu_arch_ver_table *p;
23684 /* Choose the architecture based on the capabilities of the requested cpu
23685 (if any) and/or the instructions actually used. */
23686 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23687 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23688 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23690 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23691 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23693 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23694 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23696 /* Allow the user to override the reported architecture. */
23699 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23700 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23703 /* We need to make sure that the attributes do not identify us as v6S-M
23704 when the only v6S-M feature in use is the Operating System Extensions. */
23705 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23706 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23707 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23711 for (p = cpu_arch_ver; p->val; p++)
23713 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23716 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23720 /* The table lookup above finds the last architecture to contribute
23721 a new feature. Unfortunately, Tag13 is a subset of the union of
23722 v6T2 and v7-M, so it is never seen as contributing a new feature.
23723 We can not search for the last entry which is entirely used,
23724 because if no CPU is specified we build up only those flags
23725 actually used. Perhaps we should separate out the specified
23726 and implicit cases. Avoid taking this path for -march=all by
23727 checking for contradictory v7-A / v7-M features. */
23729 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23730 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23731 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23734 /* Tag_CPU_name. */
23735 if (selected_cpu_name[0])
23739 q = selected_cpu_name;
23740 if (strncmp (q, "armv", 4) == 0)
23745 for (i = 0; q[i]; i++)
23746 q[i] = TOUPPER (q[i]);
23748 aeabi_set_attribute_string (Tag_CPU_name, q);
23751 /* Tag_CPU_arch. */
23752 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23754 /* Tag_CPU_arch_profile. */
23755 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23756 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23757 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23758 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23759 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23760 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23762 /* Tag_ARM_ISA_use. */
23763 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23765 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23767 /* Tag_THUMB_ISA_use. */
23768 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23770 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23771 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23773 /* Tag_VFP_arch. */
23774 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23775 aeabi_set_attribute_int (Tag_VFP_arch,
23776 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23778 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23779 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23780 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23781 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23782 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23783 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23784 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23785 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23786 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23788 /* Tag_ABI_HardFP_use. */
23789 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23790 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23791 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23793 /* Tag_WMMX_arch. */
23794 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23795 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23796 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23797 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23799 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23800 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23801 aeabi_set_attribute_int
23802 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23805 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23806 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23807 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23810 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23811 aeabi_set_attribute_int (Tag_DIV_use, 2);
23812 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23813 aeabi_set_attribute_int (Tag_DIV_use, 0);
23815 aeabi_set_attribute_int (Tag_DIV_use, 1);
23817 /* Tag_MP_extension_use. */
23818 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23819 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23821 /* Tag Virtualization_use. */
23822 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23824 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23827 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23830 /* Add the default contents for the .ARM.attributes section. */
23834 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23837 aeabi_set_public_attributes ();
23839 #endif /* OBJ_ELF */
23842 /* Parse a .cpu directive. */
23845 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23847 const struct arm_cpu_option_table *opt;
23851 name = input_line_pointer;
23852 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23853 input_line_pointer++;
23854 saved_char = *input_line_pointer;
23855 *input_line_pointer = 0;
23857 /* Skip the first "all" entry. */
23858 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23859 if (streq (opt->name, name))
23861 mcpu_cpu_opt = &opt->value;
23862 selected_cpu = opt->value;
23863 if (opt->canonical_name)
23864 strcpy (selected_cpu_name, opt->canonical_name);
23868 for (i = 0; opt->name[i]; i++)
23869 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23871 selected_cpu_name[i] = 0;
23873 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23874 *input_line_pointer = saved_char;
23875 demand_empty_rest_of_line ();
23878 as_bad (_("unknown cpu `%s'"), name);
23879 *input_line_pointer = saved_char;
23880 ignore_rest_of_line ();
23884 /* Parse a .arch directive. */
23887 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23889 const struct arm_arch_option_table *opt;
23893 name = input_line_pointer;
23894 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23895 input_line_pointer++;
23896 saved_char = *input_line_pointer;
23897 *input_line_pointer = 0;
23899 /* Skip the first "all" entry. */
23900 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23901 if (streq (opt->name, name))
23903 mcpu_cpu_opt = &opt->value;
23904 selected_cpu = opt->value;
23905 strcpy (selected_cpu_name, opt->name);
23906 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23907 *input_line_pointer = saved_char;
23908 demand_empty_rest_of_line ();
23912 as_bad (_("unknown architecture `%s'\n"), name);
23913 *input_line_pointer = saved_char;
23914 ignore_rest_of_line ();
23918 /* Parse a .object_arch directive. */
23921 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23923 const struct arm_arch_option_table *opt;
23927 name = input_line_pointer;
23928 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23929 input_line_pointer++;
23930 saved_char = *input_line_pointer;
23931 *input_line_pointer = 0;
23933 /* Skip the first "all" entry. */
23934 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23935 if (streq (opt->name, name))
23937 object_arch = &opt->value;
23938 *input_line_pointer = saved_char;
23939 demand_empty_rest_of_line ();
23943 as_bad (_("unknown architecture `%s'\n"), name);
23944 *input_line_pointer = saved_char;
23945 ignore_rest_of_line ();
23948 /* Parse a .arch_extension directive. */
23951 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23953 const struct arm_option_extension_value_table *opt;
23956 int adding_value = 1;
23958 name = input_line_pointer;
23959 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23960 input_line_pointer++;
23961 saved_char = *input_line_pointer;
23962 *input_line_pointer = 0;
23964 if (strlen (name) >= 2
23965 && strncmp (name, "no", 2) == 0)
23971 for (opt = arm_extensions; opt->name != NULL; opt++)
23972 if (streq (opt->name, name))
23974 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23976 as_bad (_("architectural extension `%s' is not allowed for the "
23977 "current base architecture"), name);
23982 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23984 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23986 mcpu_cpu_opt = &selected_cpu;
23987 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23988 *input_line_pointer = saved_char;
23989 demand_empty_rest_of_line ();
23993 if (opt->name == NULL)
23994 as_bad (_("unknown architecture `%s'\n"), name);
23996 *input_line_pointer = saved_char;
23997 ignore_rest_of_line ();
24000 /* Parse a .fpu directive. */
24003 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24005 const struct arm_option_fpu_value_table *opt;
24009 name = input_line_pointer;
24010 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24011 input_line_pointer++;
24012 saved_char = *input_line_pointer;
24013 *input_line_pointer = 0;
24015 for (opt = arm_fpus; opt->name != NULL; opt++)
24016 if (streq (opt->name, name))
24018 mfpu_opt = &opt->value;
24019 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24020 *input_line_pointer = saved_char;
24021 demand_empty_rest_of_line ();
24025 as_bad (_("unknown floating point format `%s'\n"), name);
24026 *input_line_pointer = saved_char;
24027 ignore_rest_of_line ();
24030 /* Copy symbol information. */
24033 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24035 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24039 /* Given a symbolic attribute NAME, return the proper integer value.
24040 Returns -1 if the attribute is not known. */
24043 arm_convert_symbolic_attribute (const char *name)
24045 static const struct
24050 attribute_table[] =
24052 /* When you modify this table you should
24053 also modify the list in doc/c-arm.texi. */
24054 #define T(tag) {#tag, tag}
24055 T (Tag_CPU_raw_name),
24058 T (Tag_CPU_arch_profile),
24059 T (Tag_ARM_ISA_use),
24060 T (Tag_THUMB_ISA_use),
24064 T (Tag_Advanced_SIMD_arch),
24065 T (Tag_PCS_config),
24066 T (Tag_ABI_PCS_R9_use),
24067 T (Tag_ABI_PCS_RW_data),
24068 T (Tag_ABI_PCS_RO_data),
24069 T (Tag_ABI_PCS_GOT_use),
24070 T (Tag_ABI_PCS_wchar_t),
24071 T (Tag_ABI_FP_rounding),
24072 T (Tag_ABI_FP_denormal),
24073 T (Tag_ABI_FP_exceptions),
24074 T (Tag_ABI_FP_user_exceptions),
24075 T (Tag_ABI_FP_number_model),
24076 T (Tag_ABI_align_needed),
24077 T (Tag_ABI_align8_needed),
24078 T (Tag_ABI_align_preserved),
24079 T (Tag_ABI_align8_preserved),
24080 T (Tag_ABI_enum_size),
24081 T (Tag_ABI_HardFP_use),
24082 T (Tag_ABI_VFP_args),
24083 T (Tag_ABI_WMMX_args),
24084 T (Tag_ABI_optimization_goals),
24085 T (Tag_ABI_FP_optimization_goals),
24086 T (Tag_compatibility),
24087 T (Tag_CPU_unaligned_access),
24088 T (Tag_FP_HP_extension),
24089 T (Tag_VFP_HP_extension),
24090 T (Tag_ABI_FP_16bit_format),
24091 T (Tag_MPextension_use),
24093 T (Tag_nodefaults),
24094 T (Tag_also_compatible_with),
24095 T (Tag_conformance),
24097 T (Tag_Virtualization_use),
24098 /* We deliberately do not include Tag_MPextension_use_legacy. */
24106 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24107 if (streq (name, attribute_table[i].name))
24108 return attribute_table[i].tag;
24114 /* Apply sym value for relocations only in the case that
24115 they are for local symbols and you have the respective
24116 architectural feature for blx and simple switches. */
24118 arm_apply_sym_value (struct fix * fixP)
24121 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24122 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24124 switch (fixP->fx_r_type)
24126 case BFD_RELOC_ARM_PCREL_BLX:
24127 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24128 if (ARM_IS_FUNC (fixP->fx_addsy))
24132 case BFD_RELOC_ARM_PCREL_CALL:
24133 case BFD_RELOC_THUMB_PCREL_BLX:
24134 if (THUMB_IS_FUNC (fixP->fx_addsy))
24145 #endif /* OBJ_ELF */