1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld.
327 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
328 const char arm_symbol_chars[] = "#[]{}";
343 enum neon_el_type type;
347 #define NEON_MAX_TYPE_ELS 4
351 struct neon_type_el el[NEON_MAX_TYPE_ELS];
355 enum it_instruction_type
360 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
361 if inside, should be the last one. */
362 NEUTRAL_IT_INSN, /* This could be either inside or outside,
363 i.e. BKPT and NOP. */
364 IT_INSN /* The IT insn has been parsed. */
367 /* The maximum number of operands we need. */
368 #define ARM_IT_MAX_OPERANDS 6
373 unsigned long instruction;
377 /* "uncond_value" is set to the value in place of the conditional field in
378 unconditional versions of the instruction, or -1 if nothing is
381 struct neon_type vectype;
382 /* This does not indicate an actual NEON instruction, only that
383 the mnemonic accepts neon-style type suffixes. */
385 /* Set to the opcode if the instruction needs relaxation.
386 Zero if the instruction is not relaxed. */
390 bfd_reloc_code_real_type type;
395 enum it_instruction_type it_insn_type;
401 struct neon_type_el vectype;
402 unsigned present : 1; /* Operand present. */
403 unsigned isreg : 1; /* Operand was a register. */
404 unsigned immisreg : 1; /* .imm field is a second register. */
405 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
406 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
407 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
408 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
409 instructions. This allows us to disambiguate ARM <-> vector insns. */
410 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
411 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
412 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
413 unsigned issingle : 1; /* Operand is VFP single-precision register. */
414 unsigned hasreloc : 1; /* Operand has relocation suffix. */
415 unsigned writeback : 1; /* Operand has trailing ! */
416 unsigned preind : 1; /* Preindexed address. */
417 unsigned postind : 1; /* Postindexed address. */
418 unsigned negative : 1; /* Index register was negated. */
419 unsigned shifted : 1; /* Shift applied to operation. */
420 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
421 } operands[ARM_IT_MAX_OPERANDS];
424 static struct arm_it inst;
426 #define NUM_FLOAT_VALS 8
428 const char * fp_const[] =
430 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
433 /* Number of littlenums required to hold an extended precision number. */
434 #define MAX_LITTLENUMS 6
436 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
446 #define CP_T_X 0x00008000
447 #define CP_T_Y 0x00400000
449 #define CONDS_BIT 0x00100000
450 #define LOAD_BIT 0x00100000
452 #define DOUBLE_LOAD_FLAG 0x00000001
456 const char * template_name;
460 #define COND_ALWAYS 0xE
464 const char * template_name;
468 struct asm_barrier_opt
470 const char * template_name;
472 const arm_feature_set arch;
475 /* The bit that distinguishes CPSR and SPSR. */
476 #define SPSR_BIT (1 << 22)
478 /* The individual PSR flag bits. */
479 #define PSR_c (1 << 16)
480 #define PSR_x (1 << 17)
481 #define PSR_s (1 << 18)
482 #define PSR_f (1 << 19)
487 bfd_reloc_code_real_type reloc;
492 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
493 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
498 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
501 /* Bits for DEFINED field in neon_typed_alias. */
502 #define NTA_HASTYPE 1
503 #define NTA_HASINDEX 2
505 struct neon_typed_alias
507 unsigned char defined;
509 struct neon_type_el eltype;
512 /* ARM register categories. This includes coprocessor numbers and various
513 architecture extensions' registers. */
540 /* Structure for a hash table entry for a register.
541 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
542 information which states whether a vector type or index is specified (for a
543 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
549 unsigned char builtin;
550 struct neon_typed_alias * neon;
553 /* Diagnostics used when we don't get a register of the expected type. */
554 const char * const reg_expected_msgs[] =
556 N_("ARM register expected"),
557 N_("bad or missing co-processor number"),
558 N_("co-processor register expected"),
559 N_("FPA register expected"),
560 N_("VFP single precision register expected"),
561 N_("VFP/Neon double precision register expected"),
562 N_("Neon quad precision register expected"),
563 N_("VFP single or double precision register expected"),
564 N_("Neon double or quad precision register expected"),
565 N_("VFP single, double or Neon quad precision register expected"),
566 N_("VFP system register expected"),
567 N_("Maverick MVF register expected"),
568 N_("Maverick MVD register expected"),
569 N_("Maverick MVFX register expected"),
570 N_("Maverick MVDX register expected"),
571 N_("Maverick MVAX register expected"),
572 N_("Maverick DSPSC register expected"),
573 N_("iWMMXt data register expected"),
574 N_("iWMMXt control register expected"),
575 N_("iWMMXt scalar register expected"),
576 N_("XScale accumulator register expected"),
579 /* Some well known registers that we refer to directly elsewhere. */
585 /* ARM instructions take 4bytes in the object file, Thumb instructions
591 /* Basic string to match. */
592 const char * template_name;
594 /* Parameters to instruction. */
595 unsigned int operands[8];
597 /* Conditional tag - see opcode_lookup. */
598 unsigned int tag : 4;
600 /* Basic instruction code. */
601 unsigned int avalue : 28;
603 /* Thumb-format instruction code. */
606 /* Which architecture variant provides this instruction. */
607 const arm_feature_set * avariant;
608 const arm_feature_set * tvariant;
610 /* Function to call to encode instruction in ARM format. */
611 void (* aencode) (void);
613 /* Function to call to encode instruction in Thumb format. */
614 void (* tencode) (void);
617 /* Defines for various bits that we will want to toggle. */
618 #define INST_IMMEDIATE 0x02000000
619 #define OFFSET_REG 0x02000000
620 #define HWOFFSET_IMM 0x00400000
621 #define SHIFT_BY_REG 0x00000010
622 #define PRE_INDEX 0x01000000
623 #define INDEX_UP 0x00800000
624 #define WRITE_BACK 0x00200000
625 #define LDM_TYPE_2_OR_3 0x00400000
626 #define CPSI_MMOD 0x00020000
628 #define LITERAL_MASK 0xf000f000
629 #define OPCODE_MASK 0xfe1fffff
630 #define V4_STR_BIT 0x00000020
632 #define T2_SUBS_PC_LR 0xf3de8f00
634 #define DATA_OP_SHIFT 21
636 #define T2_OPCODE_MASK 0xfe1fffff
637 #define T2_DATA_OP_SHIFT 21
639 #define A_COND_MASK 0xf0000000
640 #define A_PUSH_POP_OP_MASK 0x0fff0000
642 /* Opcodes for pushing/poping registers to/from the stack. */
643 #define A1_OPCODE_PUSH 0x092d0000
644 #define A2_OPCODE_PUSH 0x052d0004
645 #define A2_OPCODE_POP 0x049d0004
647 /* Codes to distinguish the arithmetic instructions. */
658 #define OPCODE_CMP 10
659 #define OPCODE_CMN 11
660 #define OPCODE_ORR 12
661 #define OPCODE_MOV 13
662 #define OPCODE_BIC 14
663 #define OPCODE_MVN 15
665 #define T2_OPCODE_AND 0
666 #define T2_OPCODE_BIC 1
667 #define T2_OPCODE_ORR 2
668 #define T2_OPCODE_ORN 3
669 #define T2_OPCODE_EOR 4
670 #define T2_OPCODE_ADD 8
671 #define T2_OPCODE_ADC 10
672 #define T2_OPCODE_SBC 11
673 #define T2_OPCODE_SUB 13
674 #define T2_OPCODE_RSB 14
676 #define T_OPCODE_MUL 0x4340
677 #define T_OPCODE_TST 0x4200
678 #define T_OPCODE_CMN 0x42c0
679 #define T_OPCODE_NEG 0x4240
680 #define T_OPCODE_MVN 0x43c0
682 #define T_OPCODE_ADD_R3 0x1800
683 #define T_OPCODE_SUB_R3 0x1a00
684 #define T_OPCODE_ADD_HI 0x4400
685 #define T_OPCODE_ADD_ST 0xb000
686 #define T_OPCODE_SUB_ST 0xb080
687 #define T_OPCODE_ADD_SP 0xa800
688 #define T_OPCODE_ADD_PC 0xa000
689 #define T_OPCODE_ADD_I8 0x3000
690 #define T_OPCODE_SUB_I8 0x3800
691 #define T_OPCODE_ADD_I3 0x1c00
692 #define T_OPCODE_SUB_I3 0x1e00
694 #define T_OPCODE_ASR_R 0x4100
695 #define T_OPCODE_LSL_R 0x4080
696 #define T_OPCODE_LSR_R 0x40c0
697 #define T_OPCODE_ROR_R 0x41c0
698 #define T_OPCODE_ASR_I 0x1000
699 #define T_OPCODE_LSL_I 0x0000
700 #define T_OPCODE_LSR_I 0x0800
702 #define T_OPCODE_MOV_I8 0x2000
703 #define T_OPCODE_CMP_I8 0x2800
704 #define T_OPCODE_CMP_LR 0x4280
705 #define T_OPCODE_MOV_HR 0x4600
706 #define T_OPCODE_CMP_HR 0x4500
708 #define T_OPCODE_LDR_PC 0x4800
709 #define T_OPCODE_LDR_SP 0x9800
710 #define T_OPCODE_STR_SP 0x9000
711 #define T_OPCODE_LDR_IW 0x6800
712 #define T_OPCODE_STR_IW 0x6000
713 #define T_OPCODE_LDR_IH 0x8800
714 #define T_OPCODE_STR_IH 0x8000
715 #define T_OPCODE_LDR_IB 0x7800
716 #define T_OPCODE_STR_IB 0x7000
717 #define T_OPCODE_LDR_RW 0x5800
718 #define T_OPCODE_STR_RW 0x5000
719 #define T_OPCODE_LDR_RH 0x5a00
720 #define T_OPCODE_STR_RH 0x5200
721 #define T_OPCODE_LDR_RB 0x5c00
722 #define T_OPCODE_STR_RB 0x5400
724 #define T_OPCODE_PUSH 0xb400
725 #define T_OPCODE_POP 0xbc00
727 #define T_OPCODE_BRANCH 0xe000
729 #define THUMB_SIZE 2 /* Size of thumb instruction. */
730 #define THUMB_PP_PC_LR 0x0100
731 #define THUMB_LOAD_BIT 0x0800
732 #define THUMB2_LOAD_BIT 0x00100000
734 #define BAD_ARGS _("bad arguments to instruction")
735 #define BAD_SP _("r13 not allowed here")
736 #define BAD_PC _("r15 not allowed here")
737 #define BAD_COND _("instruction cannot be conditional")
738 #define BAD_OVERLAP _("registers may not be the same")
739 #define BAD_HIREG _("lo register required")
740 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
741 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
742 #define BAD_BRANCH _("branch must be last instruction in IT block")
743 #define BAD_NOT_IT _("instruction not allowed in IT block")
744 #define BAD_FPU _("selected FPU does not support instruction")
745 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
746 #define BAD_IT_COND _("incorrect condition in IT block")
747 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
748 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
749 #define BAD_PC_ADDRESSING \
750 _("cannot use register index with PC-relative addressing")
751 #define BAD_PC_WRITEBACK \
752 _("cannot use writeback with PC-relative addressing")
753 #define BAD_RANGE _("branch out of range")
754 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
756 static struct hash_control * arm_ops_hsh;
757 static struct hash_control * arm_cond_hsh;
758 static struct hash_control * arm_shift_hsh;
759 static struct hash_control * arm_psr_hsh;
760 static struct hash_control * arm_v7m_psr_hsh;
761 static struct hash_control * arm_reg_hsh;
762 static struct hash_control * arm_reloc_hsh;
763 static struct hash_control * arm_barrier_opt_hsh;
765 /* Stuff needed to resolve the label ambiguity
774 symbolS * last_label_seen;
775 static int label_is_thumb_function_name = FALSE;
777 /* Literal pool structure. Held on a per-section
778 and per-sub-section basis. */
780 #define MAX_LITERAL_POOL_SIZE 1024
781 typedef struct literal_pool
783 expressionS literals [MAX_LITERAL_POOL_SIZE];
784 unsigned int next_free_entry;
790 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
792 struct literal_pool * next;
795 /* Pointer to a linked list of literal pools. */
796 literal_pool * list_of_pools = NULL;
799 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
801 static struct current_it now_it;
805 now_it_compatible (int cond)
807 return (cond & ~1) == (now_it.cc & ~1);
811 conditional_insn (void)
813 return inst.cond != COND_ALWAYS;
816 static int in_it_block (void);
818 static int handle_it_state (void);
820 static void force_automatic_it_block_close (void);
822 static void it_fsm_post_encode (void);
824 #define set_it_insn_type(type) \
827 inst.it_insn_type = type; \
828 if (handle_it_state () == FAIL) \
833 #define set_it_insn_type_nonvoid(type, failret) \
836 inst.it_insn_type = type; \
837 if (handle_it_state () == FAIL) \
842 #define set_it_insn_type_last() \
845 if (inst.cond == COND_ALWAYS) \
846 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
848 set_it_insn_type (INSIDE_IT_LAST_INSN); \
854 /* This array holds the chars that always start a comment. If the
855 pre-processor is disabled, these aren't very useful. */
856 const char comment_chars[] = "@";
858 /* This array holds the chars that only start a comment at the beginning of
859 a line. If the line seems to have the form '# 123 filename'
860 .line and .file directives will appear in the pre-processed output. */
861 /* Note that input_file.c hand checks for '#' at the beginning of the
862 first line of the input file. This is because the compiler outputs
863 #NO_APP at the beginning of its output. */
864 /* Also note that comments like this one will always work. */
865 const char line_comment_chars[] = "#";
867 const char line_separator_chars[] = ";";
869 /* Chars that can be used to separate mant
870 from exp in floating point numbers. */
871 const char EXP_CHARS[] = "eE";
873 /* Chars that mean this number is a floating point constant. */
877 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
879 /* Prefix characters that indicate the start of an immediate
881 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
883 /* Separator character handling. */
885 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
888 skip_past_char (char ** str, char c)
890 /* PR gas/14987: Allow for whitespace before the expected character. */
891 skip_whitespace (*str);
902 #define skip_past_comma(str) skip_past_char (str, ',')
904 /* Arithmetic expressions (possibly involving symbols). */
906 /* Return TRUE if anything in the expression is a bignum. */
909 walk_no_bignums (symbolS * sp)
911 if (symbol_get_value_expression (sp)->X_op == O_big)
914 if (symbol_get_value_expression (sp)->X_add_symbol)
916 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
917 || (symbol_get_value_expression (sp)->X_op_symbol
918 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
924 static int in_my_get_expression = 0;
926 /* Third argument to my_get_expression. */
927 #define GE_NO_PREFIX 0
928 #define GE_IMM_PREFIX 1
929 #define GE_OPT_PREFIX 2
930 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
931 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
932 #define GE_OPT_PREFIX_BIG 3
935 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
940 /* In unified syntax, all prefixes are optional. */
942 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
947 case GE_NO_PREFIX: break;
949 if (!is_immediate_prefix (**str))
951 inst.error = _("immediate expression requires a # prefix");
957 case GE_OPT_PREFIX_BIG:
958 if (is_immediate_prefix (**str))
964 memset (ep, 0, sizeof (expressionS));
966 save_in = input_line_pointer;
967 input_line_pointer = *str;
968 in_my_get_expression = 1;
969 seg = expression (ep);
970 in_my_get_expression = 0;
972 if (ep->X_op == O_illegal || ep->X_op == O_absent)
974 /* We found a bad or missing expression in md_operand(). */
975 *str = input_line_pointer;
976 input_line_pointer = save_in;
977 if (inst.error == NULL)
978 inst.error = (ep->X_op == O_absent
979 ? _("missing expression") :_("bad expression"));
984 if (seg != absolute_section
985 && seg != text_section
986 && seg != data_section
987 && seg != bss_section
988 && seg != undefined_section)
990 inst.error = _("bad segment");
991 *str = input_line_pointer;
992 input_line_pointer = save_in;
999 /* Get rid of any bignums now, so that we don't generate an error for which
1000 we can't establish a line number later on. Big numbers are never valid
1001 in instructions, which is where this routine is always called. */
1002 if (prefix_mode != GE_OPT_PREFIX_BIG
1003 && (ep->X_op == O_big
1004 || (ep->X_add_symbol
1005 && (walk_no_bignums (ep->X_add_symbol)
1007 && walk_no_bignums (ep->X_op_symbol))))))
1009 inst.error = _("invalid constant");
1010 *str = input_line_pointer;
1011 input_line_pointer = save_in;
1015 *str = input_line_pointer;
1016 input_line_pointer = save_in;
1020 /* Turn a string in input_line_pointer into a floating point constant
1021 of type TYPE, and store the appropriate bytes in *LITP. The number
1022 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1023 returned, or NULL on OK.
1025 Note that fp constants aren't represent in the normal way on the ARM.
1026 In big endian mode, things are as expected. However, in little endian
1027 mode fp constants are big-endian word-wise, and little-endian byte-wise
1028 within the words. For example, (double) 1.1 in big endian mode is
1029 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1030 the byte sequence 99 99 f1 3f 9a 99 99 99.
1032 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1035 md_atof (int type, char * litP, int * sizeP)
1038 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1070 return _("Unrecognized or unsupported floating point constant");
1073 t = atof_ieee (input_line_pointer, type, words);
1075 input_line_pointer = t;
1076 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1078 if (target_big_endian)
1080 for (i = 0; i < prec; i++)
1082 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1083 litP += sizeof (LITTLENUM_TYPE);
1088 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1089 for (i = prec - 1; i >= 0; i--)
1091 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += sizeof (LITTLENUM_TYPE);
1095 /* For a 4 byte float the order of elements in `words' is 1 0.
1096 For an 8 byte float the order is 1 0 3 2. */
1097 for (i = 0; i < prec; i += 2)
1099 md_number_to_chars (litP, (valueT) words[i + 1],
1100 sizeof (LITTLENUM_TYPE));
1101 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1102 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1103 litP += 2 * sizeof (LITTLENUM_TYPE);
1110 /* We handle all bad expressions here, so that we can report the faulty
1111 instruction in the error message. */
1113 md_operand (expressionS * exp)
1115 if (in_my_get_expression)
1116 exp->X_op = O_illegal;
1119 /* Immediate values. */
1121 /* Generic immediate-value read function for use in directives.
1122 Accepts anything that 'expression' can fold to a constant.
1123 *val receives the number. */
1126 immediate_for_directive (int *val)
1129 exp.X_op = O_illegal;
1131 if (is_immediate_prefix (*input_line_pointer))
1133 input_line_pointer++;
1137 if (exp.X_op != O_constant)
1139 as_bad (_("expected #constant"));
1140 ignore_rest_of_line ();
1143 *val = exp.X_add_number;
1148 /* Register parsing. */
1150 /* Generic register parser. CCP points to what should be the
1151 beginning of a register name. If it is indeed a valid register
1152 name, advance CCP over it and return the reg_entry structure;
1153 otherwise return NULL. Does not issue diagnostics. */
1155 static struct reg_entry *
1156 arm_reg_parse_multi (char **ccp)
1160 struct reg_entry *reg;
1162 skip_whitespace (start);
1164 #ifdef REGISTER_PREFIX
1165 if (*start != REGISTER_PREFIX)
1169 #ifdef OPTIONAL_REGISTER_PREFIX
1170 if (*start == OPTIONAL_REGISTER_PREFIX)
1175 if (!ISALPHA (*p) || !is_name_beginner (*p))
1180 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1182 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1192 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1193 enum arm_reg_type type)
1195 /* Alternative syntaxes are accepted for a few register classes. */
1202 /* Generic coprocessor register names are allowed for these. */
1203 if (reg && reg->type == REG_TYPE_CN)
1208 /* For backward compatibility, a bare number is valid here. */
1210 unsigned long processor = strtoul (start, ccp, 10);
1211 if (*ccp != start && processor <= 15)
1215 case REG_TYPE_MMXWC:
1216 /* WC includes WCG. ??? I'm not sure this is true for all
1217 instructions that take WC registers. */
1218 if (reg && reg->type == REG_TYPE_MMXWCG)
1229 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1230 return value is the register number or FAIL. */
1233 arm_reg_parse (char **ccp, enum arm_reg_type type)
1236 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1239 /* Do not allow a scalar (reg+index) to parse as a register. */
1240 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1243 if (reg && reg->type == type)
1246 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1253 /* Parse a Neon type specifier. *STR should point at the leading '.'
1254 character. Does no verification at this stage that the type fits the opcode
1261 Can all be legally parsed by this function.
1263 Fills in neon_type struct pointer with parsed information, and updates STR
1264 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1265 type, FAIL if not. */
1268 parse_neon_type (struct neon_type *type, char **str)
1275 while (type->elems < NEON_MAX_TYPE_ELS)
1277 enum neon_el_type thistype = NT_untyped;
1278 unsigned thissize = -1u;
1285 /* Just a size without an explicit type. */
1289 switch (TOLOWER (*ptr))
1291 case 'i': thistype = NT_integer; break;
1292 case 'f': thistype = NT_float; break;
1293 case 'p': thistype = NT_poly; break;
1294 case 's': thistype = NT_signed; break;
1295 case 'u': thistype = NT_unsigned; break;
1297 thistype = NT_float;
1302 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1308 /* .f is an abbreviation for .f32. */
1309 if (thistype == NT_float && !ISDIGIT (*ptr))
1314 thissize = strtoul (ptr, &ptr, 10);
1316 if (thissize != 8 && thissize != 16 && thissize != 32
1319 as_bad (_("bad size %d in type specifier"), thissize);
1327 type->el[type->elems].type = thistype;
1328 type->el[type->elems].size = thissize;
1333 /* Empty/missing type is not a successful parse. */
1334 if (type->elems == 0)
1342 /* Errors may be set multiple times during parsing or bit encoding
1343 (particularly in the Neon bits), but usually the earliest error which is set
1344 will be the most meaningful. Avoid overwriting it with later (cascading)
1345 errors by calling this function. */
1348 first_error (const char *err)
1354 /* Parse a single type, e.g. ".s32", leading period included. */
1356 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1359 struct neon_type optype;
1363 if (parse_neon_type (&optype, &str) == SUCCESS)
1365 if (optype.elems == 1)
1366 *vectype = optype.el[0];
1369 first_error (_("only one type should be specified for operand"));
1375 first_error (_("vector type expected"));
1387 /* Special meanings for indices (which have a range of 0-7), which will fit into
1390 #define NEON_ALL_LANES 15
1391 #define NEON_INTERLEAVE_LANES 14
1393 /* Parse either a register or a scalar, with an optional type. Return the
1394 register number, and optionally fill in the actual type of the register
1395 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1396 type/index information in *TYPEINFO. */
1399 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1400 enum arm_reg_type *rtype,
1401 struct neon_typed_alias *typeinfo)
1404 struct reg_entry *reg = arm_reg_parse_multi (&str);
1405 struct neon_typed_alias atype;
1406 struct neon_type_el parsetype;
1410 atype.eltype.type = NT_invtype;
1411 atype.eltype.size = -1;
1413 /* Try alternate syntax for some types of register. Note these are mutually
1414 exclusive with the Neon syntax extensions. */
1417 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1425 /* Undo polymorphism when a set of register types may be accepted. */
1426 if ((type == REG_TYPE_NDQ
1427 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1428 || (type == REG_TYPE_VFSD
1429 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1430 || (type == REG_TYPE_NSDQ
1431 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1432 || reg->type == REG_TYPE_NQ))
1433 || (type == REG_TYPE_MMXWC
1434 && (reg->type == REG_TYPE_MMXWCG)))
1435 type = (enum arm_reg_type) reg->type;
1437 if (type != reg->type)
1443 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1445 if ((atype.defined & NTA_HASTYPE) != 0)
1447 first_error (_("can't redefine type for operand"));
1450 atype.defined |= NTA_HASTYPE;
1451 atype.eltype = parsetype;
1454 if (skip_past_char (&str, '[') == SUCCESS)
1456 if (type != REG_TYPE_VFD)
1458 first_error (_("only D registers may be indexed"));
1462 if ((atype.defined & NTA_HASINDEX) != 0)
1464 first_error (_("can't change index for operand"));
1468 atype.defined |= NTA_HASINDEX;
1470 if (skip_past_char (&str, ']') == SUCCESS)
1471 atype.index = NEON_ALL_LANES;
1476 my_get_expression (&exp, &str, GE_NO_PREFIX);
1478 if (exp.X_op != O_constant)
1480 first_error (_("constant expression required"));
1484 if (skip_past_char (&str, ']') == FAIL)
1487 atype.index = exp.X_add_number;
1502 /* Like arm_reg_parse, but allow allow the following extra features:
1503 - If RTYPE is non-zero, return the (possibly restricted) type of the
1504 register (e.g. Neon double or quad reg when either has been requested).
1505 - If this is a Neon vector type with additional type information, fill
1506 in the struct pointed to by VECTYPE (if non-NULL).
1507 This function will fault on encountering a scalar. */
1510 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1511 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1513 struct neon_typed_alias atype;
1515 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1520 /* Do not allow regname(... to parse as a register. */
1524 /* Do not allow a scalar (reg+index) to parse as a register. */
1525 if ((atype.defined & NTA_HASINDEX) != 0)
1527 first_error (_("register operand expected, but got scalar"));
1532 *vectype = atype.eltype;
1539 #define NEON_SCALAR_REG(X) ((X) >> 4)
1540 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1542 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1543 have enough information to be able to do a good job bounds-checking. So, we
1544 just do easy checks here, and do further checks later. */
1547 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1551 struct neon_typed_alias atype;
1553 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1555 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1558 if (atype.index == NEON_ALL_LANES)
1560 first_error (_("scalar must have an index"));
1563 else if (atype.index >= 64 / elsize)
1565 first_error (_("scalar index out of range"));
1570 *type = atype.eltype;
1574 return reg * 16 + atype.index;
1577 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1580 parse_reg_list (char ** strp)
1582 char * str = * strp;
1586 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 skip_whitespace (str);
1603 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1605 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1615 first_error (_("bad range in register list"));
1619 for (i = cur_reg + 1; i < reg; i++)
1621 if (range & (1 << i))
1623 (_("Warning: duplicated register (r%d) in register list"),
1631 if (range & (1 << reg))
1632 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1634 else if (reg <= cur_reg)
1635 as_tsktsk (_("Warning: register range not in ascending order"));
1640 while (skip_past_comma (&str) != FAIL
1641 || (in_range = 1, *str++ == '-'));
1644 if (skip_past_char (&str, '}') == FAIL)
1646 first_error (_("missing `}'"));
1654 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1657 if (exp.X_op == O_constant)
1659 if (exp.X_add_number
1660 != (exp.X_add_number & 0x0000ffff))
1662 inst.error = _("invalid register mask");
1666 if ((range & exp.X_add_number) != 0)
1668 int regno = range & exp.X_add_number;
1671 regno = (1 << regno) - 1;
1673 (_("Warning: duplicated register (r%d) in register list"),
1677 range |= exp.X_add_number;
1681 if (inst.reloc.type != 0)
1683 inst.error = _("expression too complex");
1687 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1688 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1689 inst.reloc.pc_rel = 0;
1693 if (*str == '|' || *str == '+')
1699 while (another_range);
1705 /* Types of registers in a list. */
1714 /* Parse a VFP register list. If the string is invalid return FAIL.
1715 Otherwise return the number of registers, and set PBASE to the first
1716 register. Parses registers of type ETYPE.
1717 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1718 - Q registers can be used to specify pairs of D registers
1719 - { } can be omitted from around a singleton register list
1720 FIXME: This is not implemented, as it would require backtracking in
1723 This could be done (the meaning isn't really ambiguous), but doesn't
1724 fit in well with the current parsing framework.
1725 - 32 D registers may be used (also true for VFPv3).
1726 FIXME: Types are ignored in these register lists, which is probably a
1730 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1735 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1739 unsigned long mask = 0;
1742 if (skip_past_char (&str, '{') == FAIL)
1744 inst.error = _("expecting {");
1751 regtype = REG_TYPE_VFS;
1756 regtype = REG_TYPE_VFD;
1759 case REGLIST_NEON_D:
1760 regtype = REG_TYPE_NDQ;
1764 if (etype != REGLIST_VFP_S)
1766 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1767 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1771 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1774 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1781 base_reg = max_regs;
1785 int setmask = 1, addregs = 1;
1787 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1789 if (new_base == FAIL)
1791 first_error (_(reg_expected_msgs[regtype]));
1795 if (new_base >= max_regs)
1797 first_error (_("register out of range in list"));
1801 /* Note: a value of 2 * n is returned for the register Q<n>. */
1802 if (regtype == REG_TYPE_NQ)
1808 if (new_base < base_reg)
1809 base_reg = new_base;
1811 if (mask & (setmask << new_base))
1813 first_error (_("invalid register list"));
1817 if ((mask >> new_base) != 0 && ! warned)
1819 as_tsktsk (_("register list not in ascending order"));
1823 mask |= setmask << new_base;
1826 if (*str == '-') /* We have the start of a range expression */
1832 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1835 inst.error = gettext (reg_expected_msgs[regtype]);
1839 if (high_range >= max_regs)
1841 first_error (_("register out of range in list"));
1845 if (regtype == REG_TYPE_NQ)
1846 high_range = high_range + 1;
1848 if (high_range <= new_base)
1850 inst.error = _("register range not in ascending order");
1854 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1856 if (mask & (setmask << new_base))
1858 inst.error = _("invalid register list");
1862 mask |= setmask << new_base;
1867 while (skip_past_comma (&str) != FAIL);
1871 /* Sanity check -- should have raised a parse error above. */
1872 if (count == 0 || count > max_regs)
1877 /* Final test -- the registers must be consecutive. */
1879 for (i = 0; i < count; i++)
1881 if ((mask & (1u << i)) == 0)
1883 inst.error = _("non-contiguous register range");
1893 /* True if two alias types are the same. */
1896 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1904 if (a->defined != b->defined)
1907 if ((a->defined & NTA_HASTYPE) != 0
1908 && (a->eltype.type != b->eltype.type
1909 || a->eltype.size != b->eltype.size))
1912 if ((a->defined & NTA_HASINDEX) != 0
1913 && (a->index != b->index))
1919 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1920 The base register is put in *PBASE.
1921 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1923 The register stride (minus one) is put in bit 4 of the return value.
1924 Bits [6:5] encode the list length (minus one).
1925 The type of the list elements is put in *ELTYPE, if non-NULL. */
1927 #define NEON_LANE(X) ((X) & 0xf)
1928 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1929 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1932 parse_neon_el_struct_list (char **str, unsigned *pbase,
1933 struct neon_type_el *eltype)
1940 int leading_brace = 0;
1941 enum arm_reg_type rtype = REG_TYPE_NDQ;
1942 const char *const incr_error = _("register stride must be 1 or 2");
1943 const char *const type_error = _("mismatched element/structure types in list");
1944 struct neon_typed_alias firsttype;
1946 if (skip_past_char (&ptr, '{') == SUCCESS)
1951 struct neon_typed_alias atype;
1952 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1956 first_error (_(reg_expected_msgs[rtype]));
1963 if (rtype == REG_TYPE_NQ)
1969 else if (reg_incr == -1)
1971 reg_incr = getreg - base_reg;
1972 if (reg_incr < 1 || reg_incr > 2)
1974 first_error (_(incr_error));
1978 else if (getreg != base_reg + reg_incr * count)
1980 first_error (_(incr_error));
1984 if (! neon_alias_types_same (&atype, &firsttype))
1986 first_error (_(type_error));
1990 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1994 struct neon_typed_alias htype;
1995 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1997 lane = NEON_INTERLEAVE_LANES;
1998 else if (lane != NEON_INTERLEAVE_LANES)
2000 first_error (_(type_error));
2005 else if (reg_incr != 1)
2007 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2011 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2014 first_error (_(reg_expected_msgs[rtype]));
2017 if (! neon_alias_types_same (&htype, &firsttype))
2019 first_error (_(type_error));
2022 count += hireg + dregs - getreg;
2026 /* If we're using Q registers, we can't use [] or [n] syntax. */
2027 if (rtype == REG_TYPE_NQ)
2033 if ((atype.defined & NTA_HASINDEX) != 0)
2037 else if (lane != atype.index)
2039 first_error (_(type_error));
2043 else if (lane == -1)
2044 lane = NEON_INTERLEAVE_LANES;
2045 else if (lane != NEON_INTERLEAVE_LANES)
2047 first_error (_(type_error));
2052 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2054 /* No lane set by [x]. We must be interleaving structures. */
2056 lane = NEON_INTERLEAVE_LANES;
2059 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2060 || (count > 1 && reg_incr == -1))
2062 first_error (_("error parsing element/structure list"));
2066 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2068 first_error (_("expected }"));
2076 *eltype = firsttype.eltype;
2081 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2084 /* Parse an explicit relocation suffix on an expression. This is
2085 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2086 arm_reloc_hsh contains no entries, so this function can only
2087 succeed if there is no () after the word. Returns -1 on error,
2088 BFD_RELOC_UNUSED if there wasn't any suffix. */
2091 parse_reloc (char **str)
2093 struct reloc_entry *r;
2097 return BFD_RELOC_UNUSED;
2102 while (*q && *q != ')' && *q != ',')
2107 if ((r = (struct reloc_entry *)
2108 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2115 /* Directives: register aliases. */
2117 static struct reg_entry *
2118 insert_reg_alias (char *str, unsigned number, int type)
2120 struct reg_entry *new_reg;
2123 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2125 if (new_reg->builtin)
2126 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2128 /* Only warn about a redefinition if it's not defined as the
2130 else if (new_reg->number != number || new_reg->type != type)
2131 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2136 name = xstrdup (str);
2137 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2139 new_reg->name = name;
2140 new_reg->number = number;
2141 new_reg->type = type;
2142 new_reg->builtin = FALSE;
2143 new_reg->neon = NULL;
2145 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2152 insert_neon_reg_alias (char *str, int number, int type,
2153 struct neon_typed_alias *atype)
2155 struct reg_entry *reg = insert_reg_alias (str, number, type);
2159 first_error (_("attempt to redefine typed alias"));
2165 reg->neon = (struct neon_typed_alias *)
2166 xmalloc (sizeof (struct neon_typed_alias));
2167 *reg->neon = *atype;
2171 /* Look for the .req directive. This is of the form:
2173 new_register_name .req existing_register_name
2175 If we find one, or if it looks sufficiently like one that we want to
2176 handle any error here, return TRUE. Otherwise return FALSE. */
2179 create_register_alias (char * newname, char *p)
2181 struct reg_entry *old;
2182 char *oldname, *nbuf;
2185 /* The input scrubber ensures that whitespace after the mnemonic is
2186 collapsed to single spaces. */
2188 if (strncmp (oldname, " .req ", 6) != 0)
2192 if (*oldname == '\0')
2195 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2198 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2202 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2203 the desired alias name, and p points to its end. If not, then
2204 the desired alias name is in the global original_case_string. */
2205 #ifdef TC_CASE_SENSITIVE
2208 newname = original_case_string;
2209 nlen = strlen (newname);
2212 nbuf = (char *) alloca (nlen + 1);
2213 memcpy (nbuf, newname, nlen);
2216 /* Create aliases under the new name as stated; an all-lowercase
2217 version of the new name; and an all-uppercase version of the new
2219 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2221 for (p = nbuf; *p; p++)
2224 if (strncmp (nbuf, newname, nlen))
2226 /* If this attempt to create an additional alias fails, do not bother
2227 trying to create the all-lower case alias. We will fail and issue
2228 a second, duplicate error message. This situation arises when the
2229 programmer does something like:
2232 The second .req creates the "Foo" alias but then fails to create
2233 the artificial FOO alias because it has already been created by the
2235 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2239 for (p = nbuf; *p; p++)
2242 if (strncmp (nbuf, newname, nlen))
2243 insert_reg_alias (nbuf, old->number, old->type);
2249 /* Create a Neon typed/indexed register alias using directives, e.g.:
2254 These typed registers can be used instead of the types specified after the
2255 Neon mnemonic, so long as all operands given have types. Types can also be
2256 specified directly, e.g.:
2257 vadd d0.s32, d1.s32, d2.s32 */
2260 create_neon_reg_alias (char *newname, char *p)
2262 enum arm_reg_type basetype;
2263 struct reg_entry *basereg;
2264 struct reg_entry mybasereg;
2265 struct neon_type ntype;
2266 struct neon_typed_alias typeinfo;
2267 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2270 typeinfo.defined = 0;
2271 typeinfo.eltype.type = NT_invtype;
2272 typeinfo.eltype.size = -1;
2273 typeinfo.index = -1;
2277 if (strncmp (p, " .dn ", 5) == 0)
2278 basetype = REG_TYPE_VFD;
2279 else if (strncmp (p, " .qn ", 5) == 0)
2280 basetype = REG_TYPE_NQ;
2289 basereg = arm_reg_parse_multi (&p);
2291 if (basereg && basereg->type != basetype)
2293 as_bad (_("bad type for register"));
2297 if (basereg == NULL)
2300 /* Try parsing as an integer. */
2301 my_get_expression (&exp, &p, GE_NO_PREFIX);
2302 if (exp.X_op != O_constant)
2304 as_bad (_("expression must be constant"));
2307 basereg = &mybasereg;
2308 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2314 typeinfo = *basereg->neon;
2316 if (parse_neon_type (&ntype, &p) == SUCCESS)
2318 /* We got a type. */
2319 if (typeinfo.defined & NTA_HASTYPE)
2321 as_bad (_("can't redefine the type of a register alias"));
2325 typeinfo.defined |= NTA_HASTYPE;
2326 if (ntype.elems != 1)
2328 as_bad (_("you must specify a single type only"));
2331 typeinfo.eltype = ntype.el[0];
2334 if (skip_past_char (&p, '[') == SUCCESS)
2337 /* We got a scalar index. */
2339 if (typeinfo.defined & NTA_HASINDEX)
2341 as_bad (_("can't redefine the index of a scalar alias"));
2345 my_get_expression (&exp, &p, GE_NO_PREFIX);
2347 if (exp.X_op != O_constant)
2349 as_bad (_("scalar index must be constant"));
2353 typeinfo.defined |= NTA_HASINDEX;
2354 typeinfo.index = exp.X_add_number;
2356 if (skip_past_char (&p, ']') == FAIL)
2358 as_bad (_("expecting ]"));
2363 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2364 the desired alias name, and p points to its end. If not, then
2365 the desired alias name is in the global original_case_string. */
2366 #ifdef TC_CASE_SENSITIVE
2367 namelen = nameend - newname;
2369 newname = original_case_string;
2370 namelen = strlen (newname);
2373 namebuf = (char *) alloca (namelen + 1);
2374 strncpy (namebuf, newname, namelen);
2375 namebuf[namelen] = '\0';
2377 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2378 typeinfo.defined != 0 ? &typeinfo : NULL);
2380 /* Insert name in all uppercase. */
2381 for (p = namebuf; *p; p++)
2384 if (strncmp (namebuf, newname, namelen))
2385 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2386 typeinfo.defined != 0 ? &typeinfo : NULL);
2388 /* Insert name in all lowercase. */
2389 for (p = namebuf; *p; p++)
2392 if (strncmp (namebuf, newname, namelen))
2393 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2394 typeinfo.defined != 0 ? &typeinfo : NULL);
2399 /* Should never be called, as .req goes between the alias and the
2400 register name, not at the beginning of the line. */
2403 s_req (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .req directive"));
2409 s_dn (int a ATTRIBUTE_UNUSED)
2411 as_bad (_("invalid syntax for .dn directive"));
2415 s_qn (int a ATTRIBUTE_UNUSED)
2417 as_bad (_("invalid syntax for .qn directive"));
2420 /* The .unreq directive deletes an alias which was previously defined
2421 by .req. For example:
2427 s_unreq (int a ATTRIBUTE_UNUSED)
2432 name = input_line_pointer;
2434 while (*input_line_pointer != 0
2435 && *input_line_pointer != ' '
2436 && *input_line_pointer != '\n')
2437 ++input_line_pointer;
2439 saved_char = *input_line_pointer;
2440 *input_line_pointer = 0;
2443 as_bad (_("invalid syntax for .unreq directive"));
2446 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2450 as_bad (_("unknown register alias '%s'"), name);
2451 else if (reg->builtin)
2452 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2459 hash_delete (arm_reg_hsh, name, FALSE);
2460 free ((char *) reg->name);
2465 /* Also locate the all upper case and all lower case versions.
2466 Do not complain if we cannot find one or the other as it
2467 was probably deleted above. */
2469 nbuf = strdup (name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2482 for (p = nbuf; *p; p++)
2484 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2487 hash_delete (arm_reg_hsh, nbuf, FALSE);
2488 free ((char *) reg->name);
2498 *input_line_pointer = saved_char;
2499 demand_empty_rest_of_line ();
2502 /* Directives: Instruction set selection. */
2505 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2506 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2507 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2508 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2510 /* Create a new mapping symbol for the transition to STATE. */
2513 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2516 const char * symname;
2523 type = BSF_NO_FLAGS;
2527 type = BSF_NO_FLAGS;
2531 type = BSF_NO_FLAGS;
2537 symbolP = symbol_new (symname, now_seg, value, frag);
2538 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2543 THUMB_SET_FUNC (symbolP, 0);
2544 ARM_SET_THUMB (symbolP, 0);
2545 ARM_SET_INTERWORK (symbolP, support_interwork);
2549 THUMB_SET_FUNC (symbolP, 1);
2550 ARM_SET_THUMB (symbolP, 1);
2551 ARM_SET_INTERWORK (symbolP, support_interwork);
2559 /* Save the mapping symbols for future reference. Also check that
2560 we do not place two mapping symbols at the same offset within a
2561 frag. We'll handle overlap between frags in
2562 check_mapping_symbols.
2564 If .fill or other data filling directive generates zero sized data,
2565 the mapping symbol for the following code will have the same value
2566 as the one generated for the data filling directive. In this case,
2567 we replace the old symbol with the new one at the same address. */
2570 if (frag->tc_frag_data.first_map != NULL)
2572 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2573 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2575 frag->tc_frag_data.first_map = symbolP;
2577 if (frag->tc_frag_data.last_map != NULL)
2579 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2580 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2581 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2583 frag->tc_frag_data.last_map = symbolP;
2586 /* We must sometimes convert a region marked as code to data during
2587 code alignment, if an odd number of bytes have to be padded. The
2588 code mapping symbol is pushed to an aligned address. */
2591 insert_data_mapping_symbol (enum mstate state,
2592 valueT value, fragS *frag, offsetT bytes)
2594 /* If there was already a mapping symbol, remove it. */
2595 if (frag->tc_frag_data.last_map != NULL
2596 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2598 symbolS *symp = frag->tc_frag_data.last_map;
2602 know (frag->tc_frag_data.first_map == symp);
2603 frag->tc_frag_data.first_map = NULL;
2605 frag->tc_frag_data.last_map = NULL;
2606 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2609 make_mapping_symbol (MAP_DATA, value, frag);
2610 make_mapping_symbol (state, value + bytes, frag);
2613 static void mapping_state_2 (enum mstate state, int max_chars);
2615 /* Set the mapping state to STATE. Only call this when about to
2616 emit some STATE bytes to the file. */
2619 mapping_state (enum mstate state)
2621 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2623 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2625 if (mapstate == state)
2626 /* The mapping symbol has already been emitted.
2627 There is nothing else to do. */
2630 if (state == MAP_ARM || state == MAP_THUMB)
2632 All ARM instructions require 4-byte alignment.
2633 (Almost) all Thumb instructions require 2-byte alignment.
2635 When emitting instructions into any section, mark the section
2638 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2639 but themselves require 2-byte alignment; this applies to some
2640 PC- relative forms. However, these cases will invovle implicit
2641 literal pool generation or an explicit .align >=2, both of
2642 which will cause the section to me marked with sufficient
2643 alignment. Thus, we don't handle those cases here. */
2644 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2646 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2647 /* This case will be evaluated later in the next else. */
2649 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2650 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2652 /* Only add the symbol if the offset is > 0:
2653 if we're at the first frag, check it's size > 0;
2654 if we're not at the first frag, then for sure
2655 the offset is > 0. */
2656 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2657 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2660 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2663 mapping_state_2 (state, 0);
2667 /* Same as mapping_state, but MAX_CHARS bytes have already been
2668 allocated. Put the mapping symbol that far back. */
2671 mapping_state_2 (enum mstate state, int max_chars)
2673 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2675 if (!SEG_NORMAL (now_seg))
2678 if (mapstate == state)
2679 /* The mapping symbol has already been emitted.
2680 There is nothing else to do. */
2683 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2684 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2687 #define mapping_state(x) ((void)0)
2688 #define mapping_state_2(x, y) ((void)0)
2691 /* Find the real, Thumb encoded start of a Thumb function. */
2695 find_real_start (symbolS * symbolP)
2698 const char * name = S_GET_NAME (symbolP);
2699 symbolS * new_target;
2701 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2702 #define STUB_NAME ".real_start_of"
2707 /* The compiler may generate BL instructions to local labels because
2708 it needs to perform a branch to a far away location. These labels
2709 do not have a corresponding ".real_start_of" label. We check
2710 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2711 the ".real_start_of" convention for nonlocal branches. */
2712 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2715 real_start = ACONCAT ((STUB_NAME, name, NULL));
2716 new_target = symbol_find (real_start);
2718 if (new_target == NULL)
2720 as_warn (_("Failed to find real start of function: %s\n"), name);
2721 new_target = symbolP;
2729 opcode_select (int width)
2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2737 as_bad (_("selected processor does not support THUMB opcodes"));
2740 /* No need to force the alignment, since we will have been
2741 coming from ARM mode, which is word-aligned. */
2742 record_alignment (now_seg, 1);
2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2750 as_bad (_("selected processor does not support ARM opcodes"));
2755 frag_align (2, 0, 0);
2757 record_alignment (now_seg, 1);
2762 as_bad (_("invalid instruction size selected (%d)"), width);
2767 s_arm (int ignore ATTRIBUTE_UNUSED)
2770 demand_empty_rest_of_line ();
2774 s_thumb (int ignore ATTRIBUTE_UNUSED)
2777 demand_empty_rest_of_line ();
2781 s_code (int unused ATTRIBUTE_UNUSED)
2785 temp = get_absolute_expression ();
2790 opcode_select (temp);
2794 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2799 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2801 /* If we are not already in thumb mode go into it, EVEN if
2802 the target processor does not support thumb instructions.
2803 This is used by gcc/config/arm/lib1funcs.asm for example
2804 to compile interworking support functions even if the
2805 target processor should not support interworking. */
2809 record_alignment (now_seg, 1);
2812 demand_empty_rest_of_line ();
2816 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2820 /* The following label is the name/address of the start of a Thumb function.
2821 We need to know this for the interworking support. */
2822 label_is_thumb_function_name = TRUE;
2825 /* Perform a .set directive, but also mark the alias as
2826 being a thumb function. */
2829 s_thumb_set (int equiv)
2831 /* XXX the following is a duplicate of the code for s_set() in read.c
2832 We cannot just call that code as we need to get at the symbol that
2839 /* Especial apologies for the random logic:
2840 This just grew, and could be parsed much more simply!
2842 name = input_line_pointer;
2843 delim = get_symbol_end ();
2844 end_name = input_line_pointer;
2847 if (*input_line_pointer != ',')
2850 as_bad (_("expected comma after name \"%s\""), name);
2852 ignore_rest_of_line ();
2856 input_line_pointer++;
2859 if (name[0] == '.' && name[1] == '\0')
2861 /* XXX - this should not happen to .thumb_set. */
2865 if ((symbolP = symbol_find (name)) == NULL
2866 && (symbolP = md_undefined_symbol (name)) == NULL)
2869 /* When doing symbol listings, play games with dummy fragments living
2870 outside the normal fragment chain to record the file and line info
2872 if (listing & LISTING_SYMBOLS)
2874 extern struct list_info_struct * listing_tail;
2875 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2877 memset (dummy_frag, 0, sizeof (fragS));
2878 dummy_frag->fr_type = rs_fill;
2879 dummy_frag->line = listing_tail;
2880 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2881 dummy_frag->fr_symbol = symbolP;
2885 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2888 /* "set" symbols are local unless otherwise specified. */
2889 SF_SET_LOCAL (symbolP);
2890 #endif /* OBJ_COFF */
2891 } /* Make a new symbol. */
2893 symbol_table_insert (symbolP);
2898 && S_IS_DEFINED (symbolP)
2899 && S_GET_SEGMENT (symbolP) != reg_section)
2900 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2902 pseudo_set (symbolP);
2904 demand_empty_rest_of_line ();
2906 /* XXX Now we come to the Thumb specific bit of code. */
2908 THUMB_SET_FUNC (symbolP, 1);
2909 ARM_SET_THUMB (symbolP, 1);
2910 #if defined OBJ_ELF || defined OBJ_COFF
2911 ARM_SET_INTERWORK (symbolP, support_interwork);
2915 /* Directives: Mode selection. */
2917 /* .syntax [unified|divided] - choose the new unified syntax
2918 (same for Arm and Thumb encoding, modulo slight differences in what
2919 can be represented) or the old divergent syntax for each mode. */
2921 s_syntax (int unused ATTRIBUTE_UNUSED)
2925 name = input_line_pointer;
2926 delim = get_symbol_end ();
2928 if (!strcasecmp (name, "unified"))
2929 unified_syntax = TRUE;
2930 else if (!strcasecmp (name, "divided"))
2931 unified_syntax = FALSE;
2934 as_bad (_("unrecognized syntax mode \"%s\""), name);
2937 *input_line_pointer = delim;
2938 demand_empty_rest_of_line ();
2941 /* Directives: sectioning and alignment. */
2943 /* Same as s_align_ptwo but align 0 => align 2. */
2946 s_align (int unused ATTRIBUTE_UNUSED)
2951 long max_alignment = 15;
2953 temp = get_absolute_expression ();
2954 if (temp > max_alignment)
2955 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2958 as_bad (_("alignment negative. 0 assumed."));
2962 if (*input_line_pointer == ',')
2964 input_line_pointer++;
2965 temp_fill = get_absolute_expression ();
2977 /* Only make a frag if we HAVE to. */
2978 if (temp && !need_pass_2)
2980 if (!fill_p && subseg_text_p (now_seg))
2981 frag_align_code (temp, 0);
2983 frag_align (temp, (int) temp_fill, 0);
2985 demand_empty_rest_of_line ();
2987 record_alignment (now_seg, temp);
2991 s_bss (int ignore ATTRIBUTE_UNUSED)
2993 /* We don't support putting frags in the BSS segment, we fake it by
2994 marking in_bss, then looking at s_skip for clues. */
2995 subseg_set (bss_section, 0);
2996 demand_empty_rest_of_line ();
2998 #ifdef md_elf_section_change_hook
2999 md_elf_section_change_hook ();
3004 s_even (int ignore ATTRIBUTE_UNUSED)
3006 /* Never make frag if expect extra pass. */
3008 frag_align (1, 0, 0);
3010 record_alignment (now_seg, 1);
3012 demand_empty_rest_of_line ();
3015 /* Directives: Literal pools. */
3017 static literal_pool *
3018 find_literal_pool (void)
3020 literal_pool * pool;
3022 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3024 if (pool->section == now_seg
3025 && pool->sub_section == now_subseg)
3032 static literal_pool *
3033 find_or_make_literal_pool (void)
3035 /* Next literal pool ID number. */
3036 static unsigned int latest_pool_num = 1;
3037 literal_pool * pool;
3039 pool = find_literal_pool ();
3043 /* Create a new pool. */
3044 pool = (literal_pool *) xmalloc (sizeof (* pool));
3048 pool->next_free_entry = 0;
3049 pool->section = now_seg;
3050 pool->sub_section = now_subseg;
3051 pool->next = list_of_pools;
3052 pool->symbol = NULL;
3054 /* Add it to the list. */
3055 list_of_pools = pool;
3058 /* New pools, and emptied pools, will have a NULL symbol. */
3059 if (pool->symbol == NULL)
3061 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3062 (valueT) 0, &zero_address_frag);
3063 pool->id = latest_pool_num ++;
3070 /* Add the literal in the global 'inst'
3071 structure to the relevant literal pool. */
3074 add_to_lit_pool (void)
3076 literal_pool * pool;
3079 pool = find_or_make_literal_pool ();
3081 /* Check if this literal value is already in the pool. */
3082 for (entry = 0; entry < pool->next_free_entry; entry ++)
3084 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3085 && (inst.reloc.exp.X_op == O_constant)
3086 && (pool->literals[entry].X_add_number
3087 == inst.reloc.exp.X_add_number)
3088 && (pool->literals[entry].X_unsigned
3089 == inst.reloc.exp.X_unsigned))
3092 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3093 && (inst.reloc.exp.X_op == O_symbol)
3094 && (pool->literals[entry].X_add_number
3095 == inst.reloc.exp.X_add_number)
3096 && (pool->literals[entry].X_add_symbol
3097 == inst.reloc.exp.X_add_symbol)
3098 && (pool->literals[entry].X_op_symbol
3099 == inst.reloc.exp.X_op_symbol))
3103 /* Do we need to create a new entry? */
3104 if (entry == pool->next_free_entry)
3106 if (entry >= MAX_LITERAL_POOL_SIZE)
3108 inst.error = _("literal pool overflow");
3112 pool->literals[entry] = inst.reloc.exp;
3114 /* PR ld/12974: Record the location of the first source line to reference
3115 this entry in the literal pool. If it turns out during linking that the
3116 symbol does not exist we will be able to give an accurate line number for
3117 the (first use of the) missing reference. */
3118 if (debug_type == DEBUG_DWARF2)
3119 dwarf2_where (pool->locs + entry);
3121 pool->next_free_entry += 1;
3124 inst.reloc.exp.X_op = O_symbol;
3125 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3126 inst.reloc.exp.X_add_symbol = pool->symbol;
3131 /* Can't use symbol_new here, so have to create a symbol and then at
3132 a later date assign it a value. Thats what these functions do. */
3135 symbol_locate (symbolS * symbolP,
3136 const char * name, /* It is copied, the caller can modify. */
3137 segT segment, /* Segment identifier (SEG_<something>). */
3138 valueT valu, /* Symbol value. */
3139 fragS * frag) /* Associated fragment. */
3141 unsigned int name_length;
3142 char * preserved_copy_of_name;
3144 name_length = strlen (name) + 1; /* +1 for \0. */
3145 obstack_grow (¬es, name, name_length);
3146 preserved_copy_of_name = (char *) obstack_finish (¬es);
3148 #ifdef tc_canonicalize_symbol_name
3149 preserved_copy_of_name =
3150 tc_canonicalize_symbol_name (preserved_copy_of_name);
3153 S_SET_NAME (symbolP, preserved_copy_of_name);
3155 S_SET_SEGMENT (symbolP, segment);
3156 S_SET_VALUE (symbolP, valu);
3157 symbol_clear_list_pointers (symbolP);
3159 symbol_set_frag (symbolP, frag);
3161 /* Link to end of symbol chain. */
3163 extern int symbol_table_frozen;
3165 if (symbol_table_frozen)
3169 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3171 obj_symbol_new_hook (symbolP);
3173 #ifdef tc_symbol_new_hook
3174 tc_symbol_new_hook (symbolP);
3178 verify_symbol_chain (symbol_rootP, symbol_lastP);
3179 #endif /* DEBUG_SYMS */
3184 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3187 literal_pool * pool;
3190 pool = find_literal_pool ();
3192 || pool->symbol == NULL
3193 || pool->next_free_entry == 0)
3196 mapping_state (MAP_DATA);
3198 /* Align pool as you have word accesses.
3199 Only make a frag if we have to. */
3201 frag_align (2, 0, 0);
3203 record_alignment (now_seg, 2);
3205 sprintf (sym_name, "$$lit_\002%x", pool->id);
3207 symbol_locate (pool->symbol, sym_name, now_seg,
3208 (valueT) frag_now_fix (), frag_now);
3209 symbol_table_insert (pool->symbol);
3211 ARM_SET_THUMB (pool->symbol, thumb_mode);
3213 #if defined OBJ_COFF || defined OBJ_ELF
3214 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3217 for (entry = 0; entry < pool->next_free_entry; entry ++)
3220 if (debug_type == DEBUG_DWARF2)
3221 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3223 /* First output the expression in the instruction to the pool. */
3224 emit_expr (&(pool->literals[entry]), 4); /* .word */
3227 /* Mark the pool as empty. */
3228 pool->next_free_entry = 0;
3229 pool->symbol = NULL;
3233 /* Forward declarations for functions below, in the MD interface
3235 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3236 static valueT create_unwind_entry (int);
3237 static void start_unwind_section (const segT, int);
3238 static void add_unwind_opcode (valueT, int);
3239 static void flush_pending_unwind (void);
3241 /* Directives: Data. */
3244 s_arm_elf_cons (int nbytes)
3248 #ifdef md_flush_pending_output
3249 md_flush_pending_output ();
3252 if (is_it_end_of_statement ())
3254 demand_empty_rest_of_line ();
3258 #ifdef md_cons_align
3259 md_cons_align (nbytes);
3262 mapping_state (MAP_DATA);
3266 char *base = input_line_pointer;
3270 if (exp.X_op != O_symbol)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 char *before_reloc = input_line_pointer;
3275 reloc = parse_reloc (&input_line_pointer);
3278 as_bad (_("unrecognized relocation suffix"));
3279 ignore_rest_of_line ();
3282 else if (reloc == BFD_RELOC_UNUSED)
3283 emit_expr (&exp, (unsigned int) nbytes);
3286 reloc_howto_type *howto = (reloc_howto_type *)
3287 bfd_reloc_type_lookup (stdoutput,
3288 (bfd_reloc_code_real_type) reloc);
3289 int size = bfd_get_reloc_size (howto);
3291 if (reloc == BFD_RELOC_ARM_PLT32)
3293 as_bad (_("(plt) is only valid on branch targets"));
3294 reloc = BFD_RELOC_UNUSED;
3299 as_bad (_("%s relocations do not fit in %d bytes"),
3300 howto->name, nbytes);
3303 /* We've parsed an expression stopping at O_symbol.
3304 But there may be more expression left now that we
3305 have parsed the relocation marker. Parse it again.
3306 XXX Surely there is a cleaner way to do this. */
3307 char *p = input_line_pointer;
3309 char *save_buf = (char *) alloca (input_line_pointer - base);
3310 memcpy (save_buf, base, input_line_pointer - base);
3311 memmove (base + (input_line_pointer - before_reloc),
3312 base, before_reloc - base);
3314 input_line_pointer = base + (input_line_pointer-before_reloc);
3316 memcpy (base, save_buf, p - base);
3318 offset = nbytes - size;
3319 p = frag_more ((int) nbytes);
3320 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3321 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3326 while (*input_line_pointer++ == ',');
3328 /* Put terminator back into stream. */
3329 input_line_pointer --;
3330 demand_empty_rest_of_line ();
3333 /* Emit an expression containing a 32-bit thumb instruction.
3334 Implementation based on put_thumb32_insn. */
3337 emit_thumb32_expr (expressionS * exp)
3339 expressionS exp_high = *exp;
3341 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3342 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3343 exp->X_add_number &= 0xffff;
3344 emit_expr (exp, (unsigned int) THUMB_SIZE);
3347 /* Guess the instruction size based on the opcode. */
3350 thumb_insn_size (int opcode)
3352 if ((unsigned int) opcode < 0xe800u)
3354 else if ((unsigned int) opcode >= 0xe8000000u)
3361 emit_insn (expressionS *exp, int nbytes)
3365 if (exp->X_op == O_constant)
3370 size = thumb_insn_size (exp->X_add_number);
3374 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3376 as_bad (_(".inst.n operand too big. "\
3377 "Use .inst.w instead"));
3382 if (now_it.state == AUTOMATIC_IT_BLOCK)
3383 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3385 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3387 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3388 emit_thumb32_expr (exp);
3390 emit_expr (exp, (unsigned int) size);
3392 it_fsm_post_encode ();
3396 as_bad (_("cannot determine Thumb instruction size. " \
3397 "Use .inst.n/.inst.w instead"));
3400 as_bad (_("constant expression required"));
3405 /* Like s_arm_elf_cons but do not use md_cons_align and
3406 set the mapping state to MAP_ARM/MAP_THUMB. */
3409 s_arm_elf_inst (int nbytes)
3411 if (is_it_end_of_statement ())
3413 demand_empty_rest_of_line ();
3417 /* Calling mapping_state () here will not change ARM/THUMB,
3418 but will ensure not to be in DATA state. */
3421 mapping_state (MAP_THUMB);
3426 as_bad (_("width suffixes are invalid in ARM mode"));
3427 ignore_rest_of_line ();
3433 mapping_state (MAP_ARM);
3442 if (! emit_insn (& exp, nbytes))
3444 ignore_rest_of_line ();
3448 while (*input_line_pointer++ == ',');
3450 /* Put terminator back into stream. */
3451 input_line_pointer --;
3452 demand_empty_rest_of_line ();
3455 /* Parse a .rel31 directive. */
3458 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3465 if (*input_line_pointer == '1')
3466 highbit = 0x80000000;
3467 else if (*input_line_pointer != '0')
3468 as_bad (_("expected 0 or 1"));
3470 input_line_pointer++;
3471 if (*input_line_pointer != ',')
3472 as_bad (_("missing comma"));
3473 input_line_pointer++;
3475 #ifdef md_flush_pending_output
3476 md_flush_pending_output ();
3479 #ifdef md_cons_align
3483 mapping_state (MAP_DATA);
3488 md_number_to_chars (p, highbit, 4);
3489 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3490 BFD_RELOC_ARM_PREL31);
3492 demand_empty_rest_of_line ();
3495 /* Directives: AEABI stack-unwind tables. */
3497 /* Parse an unwind_fnstart directive. Simply records the current location. */
3500 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3502 demand_empty_rest_of_line ();
3503 if (unwind.proc_start)
3505 as_bad (_("duplicate .fnstart directive"));
3509 /* Mark the start of the function. */
3510 unwind.proc_start = expr_build_dot ();
3512 /* Reset the rest of the unwind info. */
3513 unwind.opcode_count = 0;
3514 unwind.table_entry = NULL;
3515 unwind.personality_routine = NULL;
3516 unwind.personality_index = -1;
3517 unwind.frame_size = 0;
3518 unwind.fp_offset = 0;
3519 unwind.fp_reg = REG_SP;
3521 unwind.sp_restored = 0;
3525 /* Parse a handlerdata directive. Creates the exception handling table entry
3526 for the function. */
3529 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3531 demand_empty_rest_of_line ();
3532 if (!unwind.proc_start)
3533 as_bad (MISSING_FNSTART);
3535 if (unwind.table_entry)
3536 as_bad (_("duplicate .handlerdata directive"));
3538 create_unwind_entry (1);
3541 /* Parse an unwind_fnend directive. Generates the index table entry. */
3544 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3549 unsigned int marked_pr_dependency;
3551 demand_empty_rest_of_line ();
3553 if (!unwind.proc_start)
3555 as_bad (_(".fnend directive without .fnstart"));
3559 /* Add eh table entry. */
3560 if (unwind.table_entry == NULL)
3561 val = create_unwind_entry (0);
3565 /* Add index table entry. This is two words. */
3566 start_unwind_section (unwind.saved_seg, 1);
3567 frag_align (2, 0, 0);
3568 record_alignment (now_seg, 2);
3570 ptr = frag_more (8);
3572 where = frag_now_fix () - 8;
3574 /* Self relative offset of the function start. */
3575 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3576 BFD_RELOC_ARM_PREL31);
3578 /* Indicate dependency on EHABI-defined personality routines to the
3579 linker, if it hasn't been done already. */
3580 marked_pr_dependency
3581 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3582 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3583 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3585 static const char *const name[] =
3587 "__aeabi_unwind_cpp_pr0",
3588 "__aeabi_unwind_cpp_pr1",
3589 "__aeabi_unwind_cpp_pr2"
3591 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3592 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3593 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3594 |= 1 << unwind.personality_index;
3598 /* Inline exception table entry. */
3599 md_number_to_chars (ptr + 4, val, 4);
3601 /* Self relative offset of the table entry. */
3602 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3603 BFD_RELOC_ARM_PREL31);
3605 /* Restore the original section. */
3606 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3608 unwind.proc_start = NULL;
3612 /* Parse an unwind_cantunwind directive. */
3615 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3617 demand_empty_rest_of_line ();
3618 if (!unwind.proc_start)
3619 as_bad (MISSING_FNSTART);
3621 if (unwind.personality_routine || unwind.personality_index != -1)
3622 as_bad (_("personality routine specified for cantunwind frame"));
3624 unwind.personality_index = -2;
3628 /* Parse a personalityindex directive. */
3631 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3635 if (!unwind.proc_start)
3636 as_bad (MISSING_FNSTART);
3638 if (unwind.personality_routine || unwind.personality_index != -1)
3639 as_bad (_("duplicate .personalityindex directive"));
3643 if (exp.X_op != O_constant
3644 || exp.X_add_number < 0 || exp.X_add_number > 15)
3646 as_bad (_("bad personality routine number"));
3647 ignore_rest_of_line ();
3651 unwind.personality_index = exp.X_add_number;
3653 demand_empty_rest_of_line ();
3657 /* Parse a personality directive. */
3660 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3664 if (!unwind.proc_start)
3665 as_bad (MISSING_FNSTART);
3667 if (unwind.personality_routine || unwind.personality_index != -1)
3668 as_bad (_("duplicate .personality directive"));
3670 name = input_line_pointer;
3671 c = get_symbol_end ();
3672 p = input_line_pointer;
3673 unwind.personality_routine = symbol_find_or_make (name);
3675 demand_empty_rest_of_line ();
3679 /* Parse a directive saving core registers. */
3682 s_arm_unwind_save_core (void)
3688 range = parse_reg_list (&input_line_pointer);
3691 as_bad (_("expected register list"));
3692 ignore_rest_of_line ();
3696 demand_empty_rest_of_line ();
3698 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3699 into .unwind_save {..., sp...}. We aren't bothered about the value of
3700 ip because it is clobbered by calls. */
3701 if (unwind.sp_restored && unwind.fp_reg == 12
3702 && (range & 0x3000) == 0x1000)
3704 unwind.opcode_count--;
3705 unwind.sp_restored = 0;
3706 range = (range | 0x2000) & ~0x1000;
3707 unwind.pending_offset = 0;
3713 /* See if we can use the short opcodes. These pop a block of up to 8
3714 registers starting with r4, plus maybe r14. */
3715 for (n = 0; n < 8; n++)
3717 /* Break at the first non-saved register. */
3718 if ((range & (1 << (n + 4))) == 0)
3721 /* See if there are any other bits set. */
3722 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3724 /* Use the long form. */
3725 op = 0x8000 | ((range >> 4) & 0xfff);
3726 add_unwind_opcode (op, 2);
3730 /* Use the short form. */
3732 op = 0xa8; /* Pop r14. */
3734 op = 0xa0; /* Do not pop r14. */
3736 add_unwind_opcode (op, 1);
3743 op = 0xb100 | (range & 0xf);
3744 add_unwind_opcode (op, 2);
3747 /* Record the number of bytes pushed. */
3748 for (n = 0; n < 16; n++)
3750 if (range & (1 << n))
3751 unwind.frame_size += 4;
3756 /* Parse a directive saving FPA registers. */
3759 s_arm_unwind_save_fpa (int reg)
3765 /* Get Number of registers to transfer. */
3766 if (skip_past_comma (&input_line_pointer) != FAIL)
3769 exp.X_op = O_illegal;
3771 if (exp.X_op != O_constant)
3773 as_bad (_("expected , <constant>"));
3774 ignore_rest_of_line ();
3778 num_regs = exp.X_add_number;
3780 if (num_regs < 1 || num_regs > 4)
3782 as_bad (_("number of registers must be in the range [1:4]"));
3783 ignore_rest_of_line ();
3787 demand_empty_rest_of_line ();
3792 op = 0xb4 | (num_regs - 1);
3793 add_unwind_opcode (op, 1);
3798 op = 0xc800 | (reg << 4) | (num_regs - 1);
3799 add_unwind_opcode (op, 2);
3801 unwind.frame_size += num_regs * 12;
3805 /* Parse a directive saving VFP registers for ARMv6 and above. */
3808 s_arm_unwind_save_vfp_armv6 (void)
3813 int num_vfpv3_regs = 0;
3814 int num_regs_below_16;
3816 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3819 as_bad (_("expected register list"));
3820 ignore_rest_of_line ();
3824 demand_empty_rest_of_line ();
3826 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3827 than FSTMX/FLDMX-style ones). */
3829 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3831 num_vfpv3_regs = count;
3832 else if (start + count > 16)
3833 num_vfpv3_regs = start + count - 16;
3835 if (num_vfpv3_regs > 0)
3837 int start_offset = start > 16 ? start - 16 : 0;
3838 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3839 add_unwind_opcode (op, 2);
3842 /* Generate opcode for registers numbered in the range 0 .. 15. */
3843 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3844 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3845 if (num_regs_below_16 > 0)
3847 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3848 add_unwind_opcode (op, 2);
3851 unwind.frame_size += count * 8;
3855 /* Parse a directive saving VFP registers for pre-ARMv6. */
3858 s_arm_unwind_save_vfp (void)
3864 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3867 as_bad (_("expected register list"));
3868 ignore_rest_of_line ();
3872 demand_empty_rest_of_line ();
3877 op = 0xb8 | (count - 1);
3878 add_unwind_opcode (op, 1);
3883 op = 0xb300 | (reg << 4) | (count - 1);
3884 add_unwind_opcode (op, 2);
3886 unwind.frame_size += count * 8 + 4;
3890 /* Parse a directive saving iWMMXt data registers. */
3893 s_arm_unwind_save_mmxwr (void)
3901 if (*input_line_pointer == '{')
3902 input_line_pointer++;
3906 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3910 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 as_tsktsk (_("register list not in ascending order"));
3918 if (*input_line_pointer == '-')
3920 input_line_pointer++;
3921 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3924 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3927 else if (reg >= hi_reg)
3929 as_bad (_("bad register range"));
3932 for (; reg < hi_reg; reg++)
3936 while (skip_past_comma (&input_line_pointer) != FAIL);
3938 skip_past_char (&input_line_pointer, '}');
3940 demand_empty_rest_of_line ();
3942 /* Generate any deferred opcodes because we're going to be looking at
3944 flush_pending_unwind ();
3946 for (i = 0; i < 16; i++)
3948 if (mask & (1 << i))
3949 unwind.frame_size += 8;
3952 /* Attempt to combine with a previous opcode. We do this because gcc
3953 likes to output separate unwind directives for a single block of
3955 if (unwind.opcode_count > 0)
3957 i = unwind.opcodes[unwind.opcode_count - 1];
3958 if ((i & 0xf8) == 0xc0)
3961 /* Only merge if the blocks are contiguous. */
3964 if ((mask & 0xfe00) == (1 << 9))
3966 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3967 unwind.opcode_count--;
3970 else if (i == 6 && unwind.opcode_count >= 2)
3972 i = unwind.opcodes[unwind.opcode_count - 2];
3976 op = 0xffff << (reg - 1);
3978 && ((mask & op) == (1u << (reg - 1))))
3980 op = (1 << (reg + i + 1)) - 1;
3981 op &= ~((1 << reg) - 1);
3983 unwind.opcode_count -= 2;
3990 /* We want to generate opcodes in the order the registers have been
3991 saved, ie. descending order. */
3992 for (reg = 15; reg >= -1; reg--)
3994 /* Save registers in blocks. */
3996 || !(mask & (1 << reg)))
3998 /* We found an unsaved reg. Generate opcodes to save the
4005 op = 0xc0 | (hi_reg - 10);
4006 add_unwind_opcode (op, 1);
4011 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4012 add_unwind_opcode (op, 2);
4021 ignore_rest_of_line ();
4025 s_arm_unwind_save_mmxwcg (void)
4032 if (*input_line_pointer == '{')
4033 input_line_pointer++;
4035 skip_whitespace (input_line_pointer);
4039 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4043 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4049 as_tsktsk (_("register list not in ascending order"));
4052 if (*input_line_pointer == '-')
4054 input_line_pointer++;
4055 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4058 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4061 else if (reg >= hi_reg)
4063 as_bad (_("bad register range"));
4066 for (; reg < hi_reg; reg++)
4070 while (skip_past_comma (&input_line_pointer) != FAIL);
4072 skip_past_char (&input_line_pointer, '}');
4074 demand_empty_rest_of_line ();
4076 /* Generate any deferred opcodes because we're going to be looking at
4078 flush_pending_unwind ();
4080 for (reg = 0; reg < 16; reg++)
4082 if (mask & (1 << reg))
4083 unwind.frame_size += 4;
4086 add_unwind_opcode (op, 2);
4089 ignore_rest_of_line ();
4093 /* Parse an unwind_save directive.
4094 If the argument is non-zero, this is a .vsave directive. */
4097 s_arm_unwind_save (int arch_v6)
4100 struct reg_entry *reg;
4101 bfd_boolean had_brace = FALSE;
4103 if (!unwind.proc_start)
4104 as_bad (MISSING_FNSTART);
4106 /* Figure out what sort of save we have. */
4107 peek = input_line_pointer;
4115 reg = arm_reg_parse_multi (&peek);
4119 as_bad (_("register expected"));
4120 ignore_rest_of_line ();
4129 as_bad (_("FPA .unwind_save does not take a register list"));
4130 ignore_rest_of_line ();
4133 input_line_pointer = peek;
4134 s_arm_unwind_save_fpa (reg->number);
4137 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4140 s_arm_unwind_save_vfp_armv6 ();
4142 s_arm_unwind_save_vfp ();
4144 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4145 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4148 as_bad (_(".unwind_save does not support this kind of register"));
4149 ignore_rest_of_line ();
4154 /* Parse an unwind_movsp directive. */
4157 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4163 if (!unwind.proc_start)
4164 as_bad (MISSING_FNSTART);
4166 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4169 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4170 ignore_rest_of_line ();
4174 /* Optional constant. */
4175 if (skip_past_comma (&input_line_pointer) != FAIL)
4177 if (immediate_for_directive (&offset) == FAIL)
4183 demand_empty_rest_of_line ();
4185 if (reg == REG_SP || reg == REG_PC)
4187 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4191 if (unwind.fp_reg != REG_SP)
4192 as_bad (_("unexpected .unwind_movsp directive"));
4194 /* Generate opcode to restore the value. */
4196 add_unwind_opcode (op, 1);
4198 /* Record the information for later. */
4199 unwind.fp_reg = reg;
4200 unwind.fp_offset = unwind.frame_size - offset;
4201 unwind.sp_restored = 1;
4204 /* Parse an unwind_pad directive. */
4207 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4211 if (!unwind.proc_start)
4212 as_bad (MISSING_FNSTART);
4214 if (immediate_for_directive (&offset) == FAIL)
4219 as_bad (_("stack increment must be multiple of 4"));
4220 ignore_rest_of_line ();
4224 /* Don't generate any opcodes, just record the details for later. */
4225 unwind.frame_size += offset;
4226 unwind.pending_offset += offset;
4228 demand_empty_rest_of_line ();
4231 /* Parse an unwind_setfp directive. */
4234 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4240 if (!unwind.proc_start)
4241 as_bad (MISSING_FNSTART);
4243 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4244 if (skip_past_comma (&input_line_pointer) == FAIL)
4247 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4249 if (fp_reg == FAIL || sp_reg == FAIL)
4251 as_bad (_("expected <reg>, <reg>"));
4252 ignore_rest_of_line ();
4256 /* Optional constant. */
4257 if (skip_past_comma (&input_line_pointer) != FAIL)
4259 if (immediate_for_directive (&offset) == FAIL)
4265 demand_empty_rest_of_line ();
4267 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4269 as_bad (_("register must be either sp or set by a previous"
4270 "unwind_movsp directive"));
4274 /* Don't generate any opcodes, just record the information for later. */
4275 unwind.fp_reg = fp_reg;
4277 if (sp_reg == REG_SP)
4278 unwind.fp_offset = unwind.frame_size - offset;
4280 unwind.fp_offset -= offset;
4283 /* Parse an unwind_raw directive. */
4286 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4289 /* This is an arbitrary limit. */
4290 unsigned char op[16];
4293 if (!unwind.proc_start)
4294 as_bad (MISSING_FNSTART);
4297 if (exp.X_op == O_constant
4298 && skip_past_comma (&input_line_pointer) != FAIL)
4300 unwind.frame_size += exp.X_add_number;
4304 exp.X_op = O_illegal;
4306 if (exp.X_op != O_constant)
4308 as_bad (_("expected <offset>, <opcode>"));
4309 ignore_rest_of_line ();
4315 /* Parse the opcode. */
4320 as_bad (_("unwind opcode too long"));
4321 ignore_rest_of_line ();
4323 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4325 as_bad (_("invalid unwind opcode"));
4326 ignore_rest_of_line ();
4329 op[count++] = exp.X_add_number;
4331 /* Parse the next byte. */
4332 if (skip_past_comma (&input_line_pointer) == FAIL)
4338 /* Add the opcode bytes in reverse order. */
4340 add_unwind_opcode (op[count], 1);
4342 demand_empty_rest_of_line ();
4346 /* Parse a .eabi_attribute directive. */
4349 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4351 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4353 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4354 attributes_set_explicitly[tag] = 1;
4357 /* Emit a tls fix for the symbol. */
4360 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4364 #ifdef md_flush_pending_output
4365 md_flush_pending_output ();
4368 #ifdef md_cons_align
4372 /* Since we're just labelling the code, there's no need to define a
4375 p = obstack_next_free (&frchain_now->frch_obstack);
4376 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4377 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4378 : BFD_RELOC_ARM_TLS_DESCSEQ);
4380 #endif /* OBJ_ELF */
4382 static void s_arm_arch (int);
4383 static void s_arm_object_arch (int);
4384 static void s_arm_cpu (int);
4385 static void s_arm_fpu (int);
4386 static void s_arm_arch_extension (int);
4391 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4398 if (exp.X_op == O_symbol)
4399 exp.X_op = O_secrel;
4401 emit_expr (&exp, 4);
4403 while (*input_line_pointer++ == ',');
4405 input_line_pointer--;
4406 demand_empty_rest_of_line ();
4410 /* This table describes all the machine specific pseudo-ops the assembler
4411 has to support. The fields are:
4412 pseudo-op name without dot
4413 function to call to execute this pseudo-op
4414 Integer arg to pass to the function. */
4416 const pseudo_typeS md_pseudo_table[] =
4418 /* Never called because '.req' does not start a line. */
4419 { "req", s_req, 0 },
4420 /* Following two are likewise never called. */
4423 { "unreq", s_unreq, 0 },
4424 { "bss", s_bss, 0 },
4425 { "align", s_align, 0 },
4426 { "arm", s_arm, 0 },
4427 { "thumb", s_thumb, 0 },
4428 { "code", s_code, 0 },
4429 { "force_thumb", s_force_thumb, 0 },
4430 { "thumb_func", s_thumb_func, 0 },
4431 { "thumb_set", s_thumb_set, 0 },
4432 { "even", s_even, 0 },
4433 { "ltorg", s_ltorg, 0 },
4434 { "pool", s_ltorg, 0 },
4435 { "syntax", s_syntax, 0 },
4436 { "cpu", s_arm_cpu, 0 },
4437 { "arch", s_arm_arch, 0 },
4438 { "object_arch", s_arm_object_arch, 0 },
4439 { "fpu", s_arm_fpu, 0 },
4440 { "arch_extension", s_arm_arch_extension, 0 },
4442 { "word", s_arm_elf_cons, 4 },
4443 { "long", s_arm_elf_cons, 4 },
4444 { "inst.n", s_arm_elf_inst, 2 },
4445 { "inst.w", s_arm_elf_inst, 4 },
4446 { "inst", s_arm_elf_inst, 0 },
4447 { "rel31", s_arm_rel31, 0 },
4448 { "fnstart", s_arm_unwind_fnstart, 0 },
4449 { "fnend", s_arm_unwind_fnend, 0 },
4450 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4451 { "personality", s_arm_unwind_personality, 0 },
4452 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4453 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4454 { "save", s_arm_unwind_save, 0 },
4455 { "vsave", s_arm_unwind_save, 1 },
4456 { "movsp", s_arm_unwind_movsp, 0 },
4457 { "pad", s_arm_unwind_pad, 0 },
4458 { "setfp", s_arm_unwind_setfp, 0 },
4459 { "unwind_raw", s_arm_unwind_raw, 0 },
4460 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4461 { "tlsdescseq", s_arm_tls_descseq, 0 },
4465 /* These are used for dwarf. */
4469 /* These are used for dwarf2. */
4470 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4471 { "loc", dwarf2_directive_loc, 0 },
4472 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4474 { "extend", float_cons, 'x' },
4475 { "ldouble", float_cons, 'x' },
4476 { "packed", float_cons, 'p' },
4478 {"secrel32", pe_directive_secrel, 0},
4483 /* Parser functions used exclusively in instruction operands. */
4485 /* Generic immediate-value read function for use in insn parsing.
4486 STR points to the beginning of the immediate (the leading #);
4487 VAL receives the value; if the value is outside [MIN, MAX]
4488 issue an error. PREFIX_OPT is true if the immediate prefix is
4492 parse_immediate (char **str, int *val, int min, int max,
4493 bfd_boolean prefix_opt)
4496 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4497 if (exp.X_op != O_constant)
4499 inst.error = _("constant expression required");
4503 if (exp.X_add_number < min || exp.X_add_number > max)
4505 inst.error = _("immediate value out of range");
4509 *val = exp.X_add_number;
4513 /* Less-generic immediate-value read function with the possibility of loading a
4514 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4515 instructions. Puts the result directly in inst.operands[i]. */
4518 parse_big_immediate (char **str, int i)
4523 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4525 if (exp.X_op == O_constant)
4527 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4528 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4529 O_constant. We have to be careful not to break compilation for
4530 32-bit X_add_number, though. */
4531 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4533 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4534 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4535 inst.operands[i].regisimm = 1;
4538 else if (exp.X_op == O_big
4539 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4541 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4543 /* Bignums have their least significant bits in
4544 generic_bignum[0]. Make sure we put 32 bits in imm and
4545 32 bits in reg, in a (hopefully) portable way. */
4546 gas_assert (parts != 0);
4548 /* Make sure that the number is not too big.
4549 PR 11972: Bignums can now be sign-extended to the
4550 size of a .octa so check that the out of range bits
4551 are all zero or all one. */
4552 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4554 LITTLENUM_TYPE m = -1;
4556 if (generic_bignum[parts * 2] != 0
4557 && generic_bignum[parts * 2] != m)
4560 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4561 if (generic_bignum[j] != generic_bignum[j-1])
4565 inst.operands[i].imm = 0;
4566 for (j = 0; j < parts; j++, idx++)
4567 inst.operands[i].imm |= generic_bignum[idx]
4568 << (LITTLENUM_NUMBER_OF_BITS * j);
4569 inst.operands[i].reg = 0;
4570 for (j = 0; j < parts; j++, idx++)
4571 inst.operands[i].reg |= generic_bignum[idx]
4572 << (LITTLENUM_NUMBER_OF_BITS * j);
4573 inst.operands[i].regisimm = 1;
4583 /* Returns the pseudo-register number of an FPA immediate constant,
4584 or FAIL if there isn't a valid constant here. */
4587 parse_fpa_immediate (char ** str)
4589 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4595 /* First try and match exact strings, this is to guarantee
4596 that some formats will work even for cross assembly. */
4598 for (i = 0; fp_const[i]; i++)
4600 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4604 *str += strlen (fp_const[i]);
4605 if (is_end_of_line[(unsigned char) **str])
4611 /* Just because we didn't get a match doesn't mean that the constant
4612 isn't valid, just that it is in a format that we don't
4613 automatically recognize. Try parsing it with the standard
4614 expression routines. */
4616 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4618 /* Look for a raw floating point number. */
4619 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4620 && is_end_of_line[(unsigned char) *save_in])
4622 for (i = 0; i < NUM_FLOAT_VALS; i++)
4624 for (j = 0; j < MAX_LITTLENUMS; j++)
4626 if (words[j] != fp_values[i][j])
4630 if (j == MAX_LITTLENUMS)
4638 /* Try and parse a more complex expression, this will probably fail
4639 unless the code uses a floating point prefix (eg "0f"). */
4640 save_in = input_line_pointer;
4641 input_line_pointer = *str;
4642 if (expression (&exp) == absolute_section
4643 && exp.X_op == O_big
4644 && exp.X_add_number < 0)
4646 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4648 if (gen_to_words (words, 5, (long) 15) == 0)
4650 for (i = 0; i < NUM_FLOAT_VALS; i++)
4652 for (j = 0; j < MAX_LITTLENUMS; j++)
4654 if (words[j] != fp_values[i][j])
4658 if (j == MAX_LITTLENUMS)
4660 *str = input_line_pointer;
4661 input_line_pointer = save_in;
4668 *str = input_line_pointer;
4669 input_line_pointer = save_in;
4670 inst.error = _("invalid FPA immediate expression");
4674 /* Returns 1 if a number has "quarter-precision" float format
4675 0baBbbbbbc defgh000 00000000 00000000. */
4678 is_quarter_float (unsigned imm)
4680 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4681 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4684 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4685 0baBbbbbbc defgh000 00000000 00000000.
4686 The zero and minus-zero cases need special handling, since they can't be
4687 encoded in the "quarter-precision" float format, but can nonetheless be
4688 loaded as integer constants. */
4691 parse_qfloat_immediate (char **ccp, int *immed)
4695 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4696 int found_fpchar = 0;
4698 skip_past_char (&str, '#');
4700 /* We must not accidentally parse an integer as a floating-point number. Make
4701 sure that the value we parse is not an integer by checking for special
4702 characters '.' or 'e'.
4703 FIXME: This is a horrible hack, but doing better is tricky because type
4704 information isn't in a very usable state at parse time. */
4706 skip_whitespace (fpnum);
4708 if (strncmp (fpnum, "0x", 2) == 0)
4712 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4713 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4723 if ((str = atof_ieee (str, 's', words)) != NULL)
4725 unsigned fpword = 0;
4728 /* Our FP word must be 32 bits (single-precision FP). */
4729 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4731 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4735 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4748 /* Shift operands. */
4751 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4754 struct asm_shift_name
4757 enum shift_kind kind;
4760 /* Third argument to parse_shift. */
4761 enum parse_shift_mode
4763 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4764 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4765 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4766 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4767 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4770 /* Parse a <shift> specifier on an ARM data processing instruction.
4771 This has three forms:
4773 (LSL|LSR|ASL|ASR|ROR) Rs
4774 (LSL|LSR|ASL|ASR|ROR) #imm
4777 Note that ASL is assimilated to LSL in the instruction encoding, and
4778 RRX to ROR #0 (which cannot be written as such). */
4781 parse_shift (char **str, int i, enum parse_shift_mode mode)
4783 const struct asm_shift_name *shift_name;
4784 enum shift_kind shift;
4789 for (p = *str; ISALPHA (*p); p++)
4794 inst.error = _("shift expression expected");
4798 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4801 if (shift_name == NULL)
4803 inst.error = _("shift expression expected");
4807 shift = shift_name->kind;
4811 case NO_SHIFT_RESTRICT:
4812 case SHIFT_IMMEDIATE: break;
4814 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4815 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4817 inst.error = _("'LSL' or 'ASR' required");
4822 case SHIFT_LSL_IMMEDIATE:
4823 if (shift != SHIFT_LSL)
4825 inst.error = _("'LSL' required");
4830 case SHIFT_ASR_IMMEDIATE:
4831 if (shift != SHIFT_ASR)
4833 inst.error = _("'ASR' required");
4841 if (shift != SHIFT_RRX)
4843 /* Whitespace can appear here if the next thing is a bare digit. */
4844 skip_whitespace (p);
4846 if (mode == NO_SHIFT_RESTRICT
4847 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4849 inst.operands[i].imm = reg;
4850 inst.operands[i].immisreg = 1;
4852 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4855 inst.operands[i].shift_kind = shift;
4856 inst.operands[i].shifted = 1;
4861 /* Parse a <shifter_operand> for an ARM data processing instruction:
4864 #<immediate>, <rotate>
4868 where <shift> is defined by parse_shift above, and <rotate> is a
4869 multiple of 2 between 0 and 30. Validation of immediate operands
4870 is deferred to md_apply_fix. */
4873 parse_shifter_operand (char **str, int i)
4878 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4880 inst.operands[i].reg = value;
4881 inst.operands[i].isreg = 1;
4883 /* parse_shift will override this if appropriate */
4884 inst.reloc.exp.X_op = O_constant;
4885 inst.reloc.exp.X_add_number = 0;
4887 if (skip_past_comma (str) == FAIL)
4890 /* Shift operation on register. */
4891 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4894 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4897 if (skip_past_comma (str) == SUCCESS)
4899 /* #x, y -- ie explicit rotation by Y. */
4900 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4903 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4905 inst.error = _("constant expression expected");
4909 value = exp.X_add_number;
4910 if (value < 0 || value > 30 || value % 2 != 0)
4912 inst.error = _("invalid rotation");
4915 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4917 inst.error = _("invalid constant");
4921 /* Encode as specified. */
4922 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4926 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4927 inst.reloc.pc_rel = 0;
4931 /* Group relocation information. Each entry in the table contains the
4932 textual name of the relocation as may appear in assembler source
4933 and must end with a colon.
4934 Along with this textual name are the relocation codes to be used if
4935 the corresponding instruction is an ALU instruction (ADD or SUB only),
4936 an LDR, an LDRS, or an LDC. */
4938 struct group_reloc_table_entry
4949 /* Varieties of non-ALU group relocation. */
4956 static struct group_reloc_table_entry group_reloc_table[] =
4957 { /* Program counter relative: */
4959 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4964 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4965 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4966 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4967 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4969 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4974 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4975 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4976 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4977 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4979 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4980 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4981 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4982 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4983 /* Section base relative */
4985 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4990 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4991 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4992 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4993 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4995 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5000 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5001 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5002 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5003 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5005 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5006 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5007 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5008 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5010 /* Given the address of a pointer pointing to the textual name of a group
5011 relocation as may appear in assembler source, attempt to find its details
5012 in group_reloc_table. The pointer will be updated to the character after
5013 the trailing colon. On failure, FAIL will be returned; SUCCESS
5014 otherwise. On success, *entry will be updated to point at the relevant
5015 group_reloc_table entry. */
5018 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5021 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5023 int length = strlen (group_reloc_table[i].name);
5025 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5026 && (*str)[length] == ':')
5028 *out = &group_reloc_table[i];
5029 *str += (length + 1);
5037 /* Parse a <shifter_operand> for an ARM data processing instruction
5038 (as for parse_shifter_operand) where group relocations are allowed:
5041 #<immediate>, <rotate>
5042 #:<group_reloc>:<expression>
5046 where <group_reloc> is one of the strings defined in group_reloc_table.
5047 The hashes are optional.
5049 Everything else is as for parse_shifter_operand. */
5051 static parse_operand_result
5052 parse_shifter_operand_group_reloc (char **str, int i)
5054 /* Determine if we have the sequence of characters #: or just :
5055 coming next. If we do, then we check for a group relocation.
5056 If we don't, punt the whole lot to parse_shifter_operand. */
5058 if (((*str)[0] == '#' && (*str)[1] == ':')
5059 || (*str)[0] == ':')
5061 struct group_reloc_table_entry *entry;
5063 if ((*str)[0] == '#')
5068 /* Try to parse a group relocation. Anything else is an error. */
5069 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5071 inst.error = _("unknown group relocation");
5072 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5075 /* We now have the group relocation table entry corresponding to
5076 the name in the assembler source. Next, we parse the expression. */
5077 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5078 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5080 /* Record the relocation type (always the ALU variant here). */
5081 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5082 gas_assert (inst.reloc.type != 0);
5084 return PARSE_OPERAND_SUCCESS;
5087 return parse_shifter_operand (str, i) == SUCCESS
5088 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5090 /* Never reached. */
5093 /* Parse a Neon alignment expression. Information is written to
5094 inst.operands[i]. We assume the initial ':' has been skipped.
5096 align .imm = align << 8, .immisalign=1, .preind=0 */
5097 static parse_operand_result
5098 parse_neon_alignment (char **str, int i)
5103 my_get_expression (&exp, &p, GE_NO_PREFIX);
5105 if (exp.X_op != O_constant)
5107 inst.error = _("alignment must be constant");
5108 return PARSE_OPERAND_FAIL;
5111 inst.operands[i].imm = exp.X_add_number << 8;
5112 inst.operands[i].immisalign = 1;
5113 /* Alignments are not pre-indexes. */
5114 inst.operands[i].preind = 0;
5117 return PARSE_OPERAND_SUCCESS;
5120 /* Parse all forms of an ARM address expression. Information is written
5121 to inst.operands[i] and/or inst.reloc.
5123 Preindexed addressing (.preind=1):
5125 [Rn, #offset] .reg=Rn .reloc.exp=offset
5126 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5127 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5128 .shift_kind=shift .reloc.exp=shift_imm
5130 These three may have a trailing ! which causes .writeback to be set also.
5132 Postindexed addressing (.postind=1, .writeback=1):
5134 [Rn], #offset .reg=Rn .reloc.exp=offset
5135 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5136 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5137 .shift_kind=shift .reloc.exp=shift_imm
5139 Unindexed addressing (.preind=0, .postind=0):
5141 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5145 [Rn]{!} shorthand for [Rn,#0]{!}
5146 =immediate .isreg=0 .reloc.exp=immediate
5147 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5149 It is the caller's responsibility to check for addressing modes not
5150 supported by the instruction, and to set inst.reloc.type. */
5152 static parse_operand_result
5153 parse_address_main (char **str, int i, int group_relocations,
5154 group_reloc_type group_type)
5159 if (skip_past_char (&p, '[') == FAIL)
5161 if (skip_past_char (&p, '=') == FAIL)
5163 /* Bare address - translate to PC-relative offset. */
5164 inst.reloc.pc_rel = 1;
5165 inst.operands[i].reg = REG_PC;
5166 inst.operands[i].isreg = 1;
5167 inst.operands[i].preind = 1;
5169 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5171 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5172 return PARSE_OPERAND_FAIL;
5175 return PARSE_OPERAND_SUCCESS;
5178 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5179 skip_whitespace (p);
5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5183 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5184 return PARSE_OPERAND_FAIL;
5186 inst.operands[i].reg = reg;
5187 inst.operands[i].isreg = 1;
5189 if (skip_past_comma (&p) == SUCCESS)
5191 inst.operands[i].preind = 1;
5194 else if (*p == '-') p++, inst.operands[i].negative = 1;
5196 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5198 inst.operands[i].imm = reg;
5199 inst.operands[i].immisreg = 1;
5201 if (skip_past_comma (&p) == SUCCESS)
5202 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5203 return PARSE_OPERAND_FAIL;
5205 else if (skip_past_char (&p, ':') == SUCCESS)
5207 /* FIXME: '@' should be used here, but it's filtered out by generic
5208 code before we get to see it here. This may be subject to
5210 parse_operand_result result = parse_neon_alignment (&p, i);
5212 if (result != PARSE_OPERAND_SUCCESS)
5217 if (inst.operands[i].negative)
5219 inst.operands[i].negative = 0;
5223 if (group_relocations
5224 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5226 struct group_reloc_table_entry *entry;
5228 /* Skip over the #: or : sequence. */
5234 /* Try to parse a group relocation. Anything else is an
5236 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5238 inst.error = _("unknown group relocation");
5239 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5242 /* We now have the group relocation table entry corresponding to
5243 the name in the assembler source. Next, we parse the
5245 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5246 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5248 /* Record the relocation type. */
5252 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5256 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5260 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5267 if (inst.reloc.type == 0)
5269 inst.error = _("this group relocation is not allowed on this instruction");
5270 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5276 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5277 return PARSE_OPERAND_FAIL;
5278 /* If the offset is 0, find out if it's a +0 or -0. */
5279 if (inst.reloc.exp.X_op == O_constant
5280 && inst.reloc.exp.X_add_number == 0)
5282 skip_whitespace (q);
5286 skip_whitespace (q);
5289 inst.operands[i].negative = 1;
5294 else if (skip_past_char (&p, ':') == SUCCESS)
5296 /* FIXME: '@' should be used here, but it's filtered out by generic code
5297 before we get to see it here. This may be subject to change. */
5298 parse_operand_result result = parse_neon_alignment (&p, i);
5300 if (result != PARSE_OPERAND_SUCCESS)
5304 if (skip_past_char (&p, ']') == FAIL)
5306 inst.error = _("']' expected");
5307 return PARSE_OPERAND_FAIL;
5310 if (skip_past_char (&p, '!') == SUCCESS)
5311 inst.operands[i].writeback = 1;
5313 else if (skip_past_comma (&p) == SUCCESS)
5315 if (skip_past_char (&p, '{') == SUCCESS)
5317 /* [Rn], {expr} - unindexed, with option */
5318 if (parse_immediate (&p, &inst.operands[i].imm,
5319 0, 255, TRUE) == FAIL)
5320 return PARSE_OPERAND_FAIL;
5322 if (skip_past_char (&p, '}') == FAIL)
5324 inst.error = _("'}' expected at end of 'option' field");
5325 return PARSE_OPERAND_FAIL;
5327 if (inst.operands[i].preind)
5329 inst.error = _("cannot combine index with option");
5330 return PARSE_OPERAND_FAIL;
5333 return PARSE_OPERAND_SUCCESS;
5337 inst.operands[i].postind = 1;
5338 inst.operands[i].writeback = 1;
5340 if (inst.operands[i].preind)
5342 inst.error = _("cannot combine pre- and post-indexing");
5343 return PARSE_OPERAND_FAIL;
5347 else if (*p == '-') p++, inst.operands[i].negative = 1;
5349 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5351 /* We might be using the immediate for alignment already. If we
5352 are, OR the register number into the low-order bits. */
5353 if (inst.operands[i].immisalign)
5354 inst.operands[i].imm |= reg;
5356 inst.operands[i].imm = reg;
5357 inst.operands[i].immisreg = 1;
5359 if (skip_past_comma (&p) == SUCCESS)
5360 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5361 return PARSE_OPERAND_FAIL;
5366 if (inst.operands[i].negative)
5368 inst.operands[i].negative = 0;
5371 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5372 return PARSE_OPERAND_FAIL;
5373 /* If the offset is 0, find out if it's a +0 or -0. */
5374 if (inst.reloc.exp.X_op == O_constant
5375 && inst.reloc.exp.X_add_number == 0)
5377 skip_whitespace (q);
5381 skip_whitespace (q);
5384 inst.operands[i].negative = 1;
5390 /* If at this point neither .preind nor .postind is set, we have a
5391 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5392 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5394 inst.operands[i].preind = 1;
5395 inst.reloc.exp.X_op = O_constant;
5396 inst.reloc.exp.X_add_number = 0;
5399 return PARSE_OPERAND_SUCCESS;
5403 parse_address (char **str, int i)
5405 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5409 static parse_operand_result
5410 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5412 return parse_address_main (str, i, 1, type);
5415 /* Parse an operand for a MOVW or MOVT instruction. */
5417 parse_half (char **str)
5422 skip_past_char (&p, '#');
5423 if (strncasecmp (p, ":lower16:", 9) == 0)
5424 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5425 else if (strncasecmp (p, ":upper16:", 9) == 0)
5426 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5428 if (inst.reloc.type != BFD_RELOC_UNUSED)
5431 skip_whitespace (p);
5434 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5437 if (inst.reloc.type == BFD_RELOC_UNUSED)
5439 if (inst.reloc.exp.X_op != O_constant)
5441 inst.error = _("constant expression expected");
5444 if (inst.reloc.exp.X_add_number < 0
5445 || inst.reloc.exp.X_add_number > 0xffff)
5447 inst.error = _("immediate value out of range");
5455 /* Miscellaneous. */
5457 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5458 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5460 parse_psr (char **str, bfd_boolean lhs)
5463 unsigned long psr_field;
5464 const struct asm_psr *psr;
5466 bfd_boolean is_apsr = FALSE;
5467 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5469 /* PR gas/12698: If the user has specified -march=all then m_profile will
5470 be TRUE, but we want to ignore it in this case as we are building for any
5471 CPU type, including non-m variants. */
5472 if (selected_cpu.core == arm_arch_any.core)
5475 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5476 feature for ease of use and backwards compatibility. */
5478 if (strncasecmp (p, "SPSR", 4) == 0)
5481 goto unsupported_psr;
5483 psr_field = SPSR_BIT;
5485 else if (strncasecmp (p, "CPSR", 4) == 0)
5488 goto unsupported_psr;
5492 else if (strncasecmp (p, "APSR", 4) == 0)
5494 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5495 and ARMv7-R architecture CPUs. */
5504 while (ISALNUM (*p) || *p == '_');
5506 if (strncasecmp (start, "iapsr", 5) == 0
5507 || strncasecmp (start, "eapsr", 5) == 0
5508 || strncasecmp (start, "xpsr", 4) == 0
5509 || strncasecmp (start, "psr", 3) == 0)
5510 p = start + strcspn (start, "rR") + 1;
5512 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5518 /* If APSR is being written, a bitfield may be specified. Note that
5519 APSR itself is handled above. */
5520 if (psr->field <= 3)
5522 psr_field = psr->field;
5528 /* M-profile MSR instructions have the mask field set to "10", except
5529 *PSR variants which modify APSR, which may use a different mask (and
5530 have been handled already). Do that by setting the PSR_f field
5532 return psr->field | (lhs ? PSR_f : 0);
5535 goto unsupported_psr;
5541 /* A suffix follows. */
5547 while (ISALNUM (*p) || *p == '_');
5551 /* APSR uses a notation for bits, rather than fields. */
5552 unsigned int nzcvq_bits = 0;
5553 unsigned int g_bit = 0;
5556 for (bit = start; bit != p; bit++)
5558 switch (TOLOWER (*bit))
5561 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5565 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5569 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5573 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5577 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5581 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5585 inst.error = _("unexpected bit specified after APSR");
5590 if (nzcvq_bits == 0x1f)
5595 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5597 inst.error = _("selected processor does not "
5598 "support DSP extension");
5605 if ((nzcvq_bits & 0x20) != 0
5606 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5607 || (g_bit & 0x2) != 0)
5609 inst.error = _("bad bitmask specified after APSR");
5615 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5620 psr_field |= psr->field;
5626 goto error; /* Garbage after "[CS]PSR". */
5628 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5629 is deprecated, but allow it anyway. */
5633 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5636 else if (!m_profile)
5637 /* These bits are never right for M-profile devices: don't set them
5638 (only code paths which read/write APSR reach here). */
5639 psr_field |= (PSR_c | PSR_f);
5645 inst.error = _("selected processor does not support requested special "
5646 "purpose register");
5650 inst.error = _("flag for {c}psr instruction expected");
5654 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5655 value suitable for splatting into the AIF field of the instruction. */
5658 parse_cps_flags (char **str)
5667 case '\0': case ',':
5670 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5671 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5672 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5675 inst.error = _("unrecognized CPS flag");
5680 if (saw_a_flag == 0)
5682 inst.error = _("missing CPS flags");
5690 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5691 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5694 parse_endian_specifier (char **str)
5699 if (strncasecmp (s, "BE", 2))
5701 else if (strncasecmp (s, "LE", 2))
5705 inst.error = _("valid endian specifiers are be or le");
5709 if (ISALNUM (s[2]) || s[2] == '_')
5711 inst.error = _("valid endian specifiers are be or le");
5716 return little_endian;
5719 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5720 value suitable for poking into the rotate field of an sxt or sxta
5721 instruction, or FAIL on error. */
5724 parse_ror (char **str)
5729 if (strncasecmp (s, "ROR", 3) == 0)
5733 inst.error = _("missing rotation field after comma");
5737 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5742 case 0: *str = s; return 0x0;
5743 case 8: *str = s; return 0x1;
5744 case 16: *str = s; return 0x2;
5745 case 24: *str = s; return 0x3;
5748 inst.error = _("rotation can only be 0, 8, 16, or 24");
5753 /* Parse a conditional code (from conds[] below). The value returned is in the
5754 range 0 .. 14, or FAIL. */
5756 parse_cond (char **str)
5759 const struct asm_cond *c;
5761 /* Condition codes are always 2 characters, so matching up to
5762 3 characters is sufficient. */
5767 while (ISALPHA (*q) && n < 3)
5769 cond[n] = TOLOWER (*q);
5774 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5777 inst.error = _("condition required");
5785 /* If the given feature available in the selected CPU, mark it as used.
5786 Returns TRUE iff feature is available. */
5788 mark_feature_used (const arm_feature_set *feature)
5790 /* Ensure the option is valid on the current architecture. */
5791 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5794 /* Add the appropriate architecture feature for the barrier option used.
5797 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5799 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5804 /* Parse an option for a barrier instruction. Returns the encoding for the
5807 parse_barrier (char **str)
5810 const struct asm_barrier_opt *o;
5813 while (ISALPHA (*q))
5816 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5821 if (!mark_feature_used (&o->arch))
5828 /* Parse the operands of a table branch instruction. Similar to a memory
5831 parse_tb (char **str)
5836 if (skip_past_char (&p, '[') == FAIL)
5838 inst.error = _("'[' expected");
5842 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5844 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5847 inst.operands[0].reg = reg;
5849 if (skip_past_comma (&p) == FAIL)
5851 inst.error = _("',' expected");
5855 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5857 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5860 inst.operands[0].imm = reg;
5862 if (skip_past_comma (&p) == SUCCESS)
5864 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5866 if (inst.reloc.exp.X_add_number != 1)
5868 inst.error = _("invalid shift");
5871 inst.operands[0].shifted = 1;
5874 if (skip_past_char (&p, ']') == FAIL)
5876 inst.error = _("']' expected");
5883 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5884 information on the types the operands can take and how they are encoded.
5885 Up to four operands may be read; this function handles setting the
5886 ".present" field for each read operand itself.
5887 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5888 else returns FAIL. */
5891 parse_neon_mov (char **str, int *which_operand)
5893 int i = *which_operand, val;
5894 enum arm_reg_type rtype;
5896 struct neon_type_el optype;
5898 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5900 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5901 inst.operands[i].reg = val;
5902 inst.operands[i].isscalar = 1;
5903 inst.operands[i].vectype = optype;
5904 inst.operands[i++].present = 1;
5906 if (skip_past_comma (&ptr) == FAIL)
5909 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5912 inst.operands[i].reg = val;
5913 inst.operands[i].isreg = 1;
5914 inst.operands[i].present = 1;
5916 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5919 /* Cases 0, 1, 2, 3, 5 (D only). */
5920 if (skip_past_comma (&ptr) == FAIL)
5923 inst.operands[i].reg = val;
5924 inst.operands[i].isreg = 1;
5925 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5926 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5927 inst.operands[i].isvec = 1;
5928 inst.operands[i].vectype = optype;
5929 inst.operands[i++].present = 1;
5931 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5933 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5934 Case 13: VMOV <Sd>, <Rm> */
5935 inst.operands[i].reg = val;
5936 inst.operands[i].isreg = 1;
5937 inst.operands[i].present = 1;
5939 if (rtype == REG_TYPE_NQ)
5941 first_error (_("can't use Neon quad register here"));
5944 else if (rtype != REG_TYPE_VFS)
5947 if (skip_past_comma (&ptr) == FAIL)
5949 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5951 inst.operands[i].reg = val;
5952 inst.operands[i].isreg = 1;
5953 inst.operands[i].present = 1;
5956 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5959 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5960 Case 1: VMOV<c><q> <Dd>, <Dm>
5961 Case 8: VMOV.F32 <Sd>, <Sm>
5962 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5964 inst.operands[i].reg = val;
5965 inst.operands[i].isreg = 1;
5966 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5967 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5968 inst.operands[i].isvec = 1;
5969 inst.operands[i].vectype = optype;
5970 inst.operands[i].present = 1;
5972 if (skip_past_comma (&ptr) == SUCCESS)
5977 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5980 inst.operands[i].reg = val;
5981 inst.operands[i].isreg = 1;
5982 inst.operands[i++].present = 1;
5984 if (skip_past_comma (&ptr) == FAIL)
5987 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5990 inst.operands[i].reg = val;
5991 inst.operands[i].isreg = 1;
5992 inst.operands[i].present = 1;
5995 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5996 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5997 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5998 Case 10: VMOV.F32 <Sd>, #<imm>
5999 Case 11: VMOV.F64 <Dd>, #<imm> */
6000 inst.operands[i].immisfloat = 1;
6001 else if (parse_big_immediate (&ptr, i) == SUCCESS)
6002 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6003 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6007 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6011 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6014 inst.operands[i].reg = val;
6015 inst.operands[i].isreg = 1;
6016 inst.operands[i++].present = 1;
6018 if (skip_past_comma (&ptr) == FAIL)
6021 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6023 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6024 inst.operands[i].reg = val;
6025 inst.operands[i].isscalar = 1;
6026 inst.operands[i].present = 1;
6027 inst.operands[i].vectype = optype;
6029 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6031 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6032 inst.operands[i].reg = val;
6033 inst.operands[i].isreg = 1;
6034 inst.operands[i++].present = 1;
6036 if (skip_past_comma (&ptr) == FAIL)
6039 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6042 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6046 inst.operands[i].reg = val;
6047 inst.operands[i].isreg = 1;
6048 inst.operands[i].isvec = 1;
6049 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6050 inst.operands[i].vectype = optype;
6051 inst.operands[i].present = 1;
6053 if (rtype == REG_TYPE_VFS)
6057 if (skip_past_comma (&ptr) == FAIL)
6059 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6062 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6065 inst.operands[i].reg = val;
6066 inst.operands[i].isreg = 1;
6067 inst.operands[i].isvec = 1;
6068 inst.operands[i].issingle = 1;
6069 inst.operands[i].vectype = optype;
6070 inst.operands[i].present = 1;
6073 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6077 inst.operands[i].reg = val;
6078 inst.operands[i].isreg = 1;
6079 inst.operands[i].isvec = 1;
6080 inst.operands[i].issingle = 1;
6081 inst.operands[i].vectype = optype;
6082 inst.operands[i].present = 1;
6087 first_error (_("parse error"));
6091 /* Successfully parsed the operands. Update args. */
6097 first_error (_("expected comma"));
6101 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6105 /* Use this macro when the operand constraints are different
6106 for ARM and THUMB (e.g. ldrd). */
6107 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6108 ((arm_operand) | ((thumb_operand) << 16))
6110 /* Matcher codes for parse_operands. */
6111 enum operand_parse_code
6113 OP_stop, /* end of line */
6115 OP_RR, /* ARM register */
6116 OP_RRnpc, /* ARM register, not r15 */
6117 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6118 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6119 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6120 optional trailing ! */
6121 OP_RRw, /* ARM register, not r15, optional trailing ! */
6122 OP_RCP, /* Coprocessor number */
6123 OP_RCN, /* Coprocessor register */
6124 OP_RF, /* FPA register */
6125 OP_RVS, /* VFP single precision register */
6126 OP_RVD, /* VFP double precision register (0..15) */
6127 OP_RND, /* Neon double precision register (0..31) */
6128 OP_RNQ, /* Neon quad precision register */
6129 OP_RVSD, /* VFP single or double precision register */
6130 OP_RNDQ, /* Neon double or quad precision register */
6131 OP_RNSDQ, /* Neon single, double or quad precision register */
6132 OP_RNSC, /* Neon scalar D[X] */
6133 OP_RVC, /* VFP control register */
6134 OP_RMF, /* Maverick F register */
6135 OP_RMD, /* Maverick D register */
6136 OP_RMFX, /* Maverick FX register */
6137 OP_RMDX, /* Maverick DX register */
6138 OP_RMAX, /* Maverick AX register */
6139 OP_RMDS, /* Maverick DSPSC register */
6140 OP_RIWR, /* iWMMXt wR register */
6141 OP_RIWC, /* iWMMXt wC register */
6142 OP_RIWG, /* iWMMXt wCG register */
6143 OP_RXA, /* XScale accumulator register */
6145 OP_REGLST, /* ARM register list */
6146 OP_VRSLST, /* VFP single-precision register list */
6147 OP_VRDLST, /* VFP double-precision register list */
6148 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6149 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6150 OP_NSTRLST, /* Neon element/structure list */
6152 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6153 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6154 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6155 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6156 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6157 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6158 OP_VMOV, /* Neon VMOV operands. */
6159 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6160 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6161 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6163 OP_I0, /* immediate zero */
6164 OP_I7, /* immediate value 0 .. 7 */
6165 OP_I15, /* 0 .. 15 */
6166 OP_I16, /* 1 .. 16 */
6167 OP_I16z, /* 0 .. 16 */
6168 OP_I31, /* 0 .. 31 */
6169 OP_I31w, /* 0 .. 31, optional trailing ! */
6170 OP_I32, /* 1 .. 32 */
6171 OP_I32z, /* 0 .. 32 */
6172 OP_I63, /* 0 .. 63 */
6173 OP_I63s, /* -64 .. 63 */
6174 OP_I64, /* 1 .. 64 */
6175 OP_I64z, /* 0 .. 64 */
6176 OP_I255, /* 0 .. 255 */
6178 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6179 OP_I7b, /* 0 .. 7 */
6180 OP_I15b, /* 0 .. 15 */
6181 OP_I31b, /* 0 .. 31 */
6183 OP_SH, /* shifter operand */
6184 OP_SHG, /* shifter operand with possible group relocation */
6185 OP_ADDR, /* Memory address expression (any mode) */
6186 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6187 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6188 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6189 OP_EXP, /* arbitrary expression */
6190 OP_EXPi, /* same, with optional immediate prefix */
6191 OP_EXPr, /* same, with optional relocation suffix */
6192 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6194 OP_CPSF, /* CPS flags */
6195 OP_ENDI, /* Endianness specifier */
6196 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6197 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6198 OP_COND, /* conditional code */
6199 OP_TB, /* Table branch. */
6201 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6203 OP_RRnpc_I0, /* ARM register or literal 0 */
6204 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6205 OP_RR_EXi, /* ARM register or expression with imm prefix */
6206 OP_RF_IF, /* FPA register or immediate */
6207 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6208 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6210 /* Optional operands. */
6211 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6212 OP_oI31b, /* 0 .. 31 */
6213 OP_oI32b, /* 1 .. 32 */
6214 OP_oI32z, /* 0 .. 32 */
6215 OP_oIffffb, /* 0 .. 65535 */
6216 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6218 OP_oRR, /* ARM register */
6219 OP_oRRnpc, /* ARM register, not the PC */
6220 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6221 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6222 OP_oRND, /* Optional Neon double precision register */
6223 OP_oRNQ, /* Optional Neon quad precision register */
6224 OP_oRNDQ, /* Optional Neon double or quad precision register */
6225 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6226 OP_oSHll, /* LSL immediate */
6227 OP_oSHar, /* ASR immediate */
6228 OP_oSHllar, /* LSL or ASR immediate */
6229 OP_oROR, /* ROR 0/8/16/24 */
6230 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6232 /* Some pre-defined mixed (ARM/THUMB) operands. */
6233 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6234 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6235 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6237 OP_FIRST_OPTIONAL = OP_oI7b
6240 /* Generic instruction operand parser. This does no encoding and no
6241 semantic validation; it merely squirrels values away in the inst
6242 structure. Returns SUCCESS or FAIL depending on whether the
6243 specified grammar matched. */
6245 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6247 unsigned const int *upat = pattern;
6248 char *backtrack_pos = 0;
6249 const char *backtrack_error = 0;
6250 int i, val = 0, backtrack_index = 0;
6251 enum arm_reg_type rtype;
6252 parse_operand_result result;
6253 unsigned int op_parse_code;
6255 #define po_char_or_fail(chr) \
6258 if (skip_past_char (&str, chr) == FAIL) \
6263 #define po_reg_or_fail(regtype) \
6266 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6267 & inst.operands[i].vectype); \
6270 first_error (_(reg_expected_msgs[regtype])); \
6273 inst.operands[i].reg = val; \
6274 inst.operands[i].isreg = 1; \
6275 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6276 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6277 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6278 || rtype == REG_TYPE_VFD \
6279 || rtype == REG_TYPE_NQ); \
6283 #define po_reg_or_goto(regtype, label) \
6286 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6287 & inst.operands[i].vectype); \
6291 inst.operands[i].reg = val; \
6292 inst.operands[i].isreg = 1; \
6293 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6294 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6295 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6296 || rtype == REG_TYPE_VFD \
6297 || rtype == REG_TYPE_NQ); \
6301 #define po_imm_or_fail(min, max, popt) \
6304 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6306 inst.operands[i].imm = val; \
6310 #define po_scalar_or_goto(elsz, label) \
6313 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6316 inst.operands[i].reg = val; \
6317 inst.operands[i].isscalar = 1; \
6321 #define po_misc_or_fail(expr) \
6329 #define po_misc_or_fail_no_backtrack(expr) \
6333 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6334 backtrack_pos = 0; \
6335 if (result != PARSE_OPERAND_SUCCESS) \
6340 #define po_barrier_or_imm(str) \
6343 val = parse_barrier (&str); \
6344 if (val == FAIL && ! ISALPHA (*str)) \
6347 /* ISB can only take SY as an option. */ \
6348 || ((inst.instruction & 0xf0) == 0x60 \
6351 inst.error = _("invalid barrier type"); \
6352 backtrack_pos = 0; \
6358 skip_whitespace (str);
6360 for (i = 0; upat[i] != OP_stop; i++)
6362 op_parse_code = upat[i];
6363 if (op_parse_code >= 1<<16)
6364 op_parse_code = thumb ? (op_parse_code >> 16)
6365 : (op_parse_code & ((1<<16)-1));
6367 if (op_parse_code >= OP_FIRST_OPTIONAL)
6369 /* Remember where we are in case we need to backtrack. */
6370 gas_assert (!backtrack_pos);
6371 backtrack_pos = str;
6372 backtrack_error = inst.error;
6373 backtrack_index = i;
6376 if (i > 0 && (i > 1 || inst.operands[0].present))
6377 po_char_or_fail (',');
6379 switch (op_parse_code)
6387 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6388 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6389 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6390 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6391 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6392 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6394 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6396 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6398 /* Also accept generic coprocessor regs for unknown registers. */
6400 po_reg_or_fail (REG_TYPE_CN);
6402 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6403 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6404 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6405 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6406 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6407 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6408 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6409 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6410 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6411 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6413 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6415 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6416 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6418 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6420 /* Neon scalar. Using an element size of 8 means that some invalid
6421 scalars are accepted here, so deal with those in later code. */
6422 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6426 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6429 po_imm_or_fail (0, 0, TRUE);
6434 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6439 po_scalar_or_goto (8, try_rr);
6442 po_reg_or_fail (REG_TYPE_RN);
6448 po_scalar_or_goto (8, try_nsdq);
6451 po_reg_or_fail (REG_TYPE_NSDQ);
6457 po_scalar_or_goto (8, try_ndq);
6460 po_reg_or_fail (REG_TYPE_NDQ);
6466 po_scalar_or_goto (8, try_vfd);
6469 po_reg_or_fail (REG_TYPE_VFD);
6474 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6475 not careful then bad things might happen. */
6476 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6481 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6484 /* There's a possibility of getting a 64-bit immediate here, so
6485 we need special handling. */
6486 if (parse_big_immediate (&str, i) == FAIL)
6488 inst.error = _("immediate value is out of range");
6496 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6499 po_imm_or_fail (0, 63, TRUE);
6504 po_char_or_fail ('[');
6505 po_reg_or_fail (REG_TYPE_RN);
6506 po_char_or_fail (']');
6512 po_reg_or_fail (REG_TYPE_RN);
6513 if (skip_past_char (&str, '!') == SUCCESS)
6514 inst.operands[i].writeback = 1;
6518 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6519 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6520 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6521 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6522 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6523 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6524 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6525 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6526 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6527 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6528 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6529 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6531 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6533 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6534 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6536 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6537 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6538 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6539 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6541 /* Immediate variants */
6543 po_char_or_fail ('{');
6544 po_imm_or_fail (0, 255, TRUE);
6545 po_char_or_fail ('}');
6549 /* The expression parser chokes on a trailing !, so we have
6550 to find it first and zap it. */
6553 while (*s && *s != ',')
6558 inst.operands[i].writeback = 1;
6560 po_imm_or_fail (0, 31, TRUE);
6568 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6573 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6578 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6580 if (inst.reloc.exp.X_op == O_symbol)
6582 val = parse_reloc (&str);
6585 inst.error = _("unrecognized relocation suffix");
6588 else if (val != BFD_RELOC_UNUSED)
6590 inst.operands[i].imm = val;
6591 inst.operands[i].hasreloc = 1;
6596 /* Operand for MOVW or MOVT. */
6598 po_misc_or_fail (parse_half (&str));
6601 /* Register or expression. */
6602 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6603 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6605 /* Register or immediate. */
6606 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6607 I0: po_imm_or_fail (0, 0, FALSE); break;
6609 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6611 if (!is_immediate_prefix (*str))
6614 val = parse_fpa_immediate (&str);
6617 /* FPA immediates are encoded as registers 8-15.
6618 parse_fpa_immediate has already applied the offset. */
6619 inst.operands[i].reg = val;
6620 inst.operands[i].isreg = 1;
6623 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6624 I32z: po_imm_or_fail (0, 32, FALSE); break;
6626 /* Two kinds of register. */
6629 struct reg_entry *rege = arm_reg_parse_multi (&str);
6631 || (rege->type != REG_TYPE_MMXWR
6632 && rege->type != REG_TYPE_MMXWC
6633 && rege->type != REG_TYPE_MMXWCG))
6635 inst.error = _("iWMMXt data or control register expected");
6638 inst.operands[i].reg = rege->number;
6639 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6645 struct reg_entry *rege = arm_reg_parse_multi (&str);
6647 || (rege->type != REG_TYPE_MMXWC
6648 && rege->type != REG_TYPE_MMXWCG))
6650 inst.error = _("iWMMXt control register expected");
6653 inst.operands[i].reg = rege->number;
6654 inst.operands[i].isreg = 1;
6659 case OP_CPSF: val = parse_cps_flags (&str); break;
6660 case OP_ENDI: val = parse_endian_specifier (&str); break;
6661 case OP_oROR: val = parse_ror (&str); break;
6662 case OP_COND: val = parse_cond (&str); break;
6663 case OP_oBARRIER_I15:
6664 po_barrier_or_imm (str); break;
6666 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6672 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6673 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6675 inst.error = _("Banked registers are not available with this "
6681 val = parse_psr (&str, op_parse_code == OP_wPSR);
6685 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6688 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6690 if (strncasecmp (str, "APSR_", 5) == 0)
6697 case 'c': found = (found & 1) ? 16 : found | 1; break;
6698 case 'n': found = (found & 2) ? 16 : found | 2; break;
6699 case 'z': found = (found & 4) ? 16 : found | 4; break;
6700 case 'v': found = (found & 8) ? 16 : found | 8; break;
6701 default: found = 16;
6705 inst.operands[i].isvec = 1;
6706 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6707 inst.operands[i].reg = REG_PC;
6714 po_misc_or_fail (parse_tb (&str));
6717 /* Register lists. */
6719 val = parse_reg_list (&str);
6722 inst.operands[1].writeback = 1;
6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6732 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6736 /* Allow Q registers too. */
6737 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6742 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6744 inst.operands[i].issingle = 1;
6749 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6754 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6755 &inst.operands[i].vectype);
6758 /* Addressing modes */
6760 po_misc_or_fail (parse_address (&str, i));
6764 po_misc_or_fail_no_backtrack (
6765 parse_address_group_reloc (&str, i, GROUP_LDR));
6769 po_misc_or_fail_no_backtrack (
6770 parse_address_group_reloc (&str, i, GROUP_LDRS));
6774 po_misc_or_fail_no_backtrack (
6775 parse_address_group_reloc (&str, i, GROUP_LDC));
6779 po_misc_or_fail (parse_shifter_operand (&str, i));
6783 po_misc_or_fail_no_backtrack (
6784 parse_shifter_operand_group_reloc (&str, i));
6788 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6792 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6796 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6800 as_fatal (_("unhandled operand code %d"), op_parse_code);
6803 /* Various value-based sanity checks and shared operations. We
6804 do not signal immediate failures for the register constraints;
6805 this allows a syntax error to take precedence. */
6806 switch (op_parse_code)
6814 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6815 inst.error = BAD_PC;
6820 if (inst.operands[i].isreg)
6822 if (inst.operands[i].reg == REG_PC)
6823 inst.error = BAD_PC;
6824 else if (inst.operands[i].reg == REG_SP)
6825 inst.error = BAD_SP;
6830 if (inst.operands[i].isreg
6831 && inst.operands[i].reg == REG_PC
6832 && (inst.operands[i].writeback || thumb))
6833 inst.error = BAD_PC;
6842 case OP_oBARRIER_I15:
6851 inst.operands[i].imm = val;
6858 /* If we get here, this operand was successfully parsed. */
6859 inst.operands[i].present = 1;
6863 inst.error = BAD_ARGS;
6868 /* The parse routine should already have set inst.error, but set a
6869 default here just in case. */
6871 inst.error = _("syntax error");
6875 /* Do not backtrack over a trailing optional argument that
6876 absorbed some text. We will only fail again, with the
6877 'garbage following instruction' error message, which is
6878 probably less helpful than the current one. */
6879 if (backtrack_index == i && backtrack_pos != str
6880 && upat[i+1] == OP_stop)
6883 inst.error = _("syntax error");
6887 /* Try again, skipping the optional argument at backtrack_pos. */
6888 str = backtrack_pos;
6889 inst.error = backtrack_error;
6890 inst.operands[backtrack_index].present = 0;
6891 i = backtrack_index;
6895 /* Check that we have parsed all the arguments. */
6896 if (*str != '\0' && !inst.error)
6897 inst.error = _("garbage following instruction");
6899 return inst.error ? FAIL : SUCCESS;
6902 #undef po_char_or_fail
6903 #undef po_reg_or_fail
6904 #undef po_reg_or_goto
6905 #undef po_imm_or_fail
6906 #undef po_scalar_or_fail
6907 #undef po_barrier_or_imm
6909 /* Shorthand macro for instruction encoding functions issuing errors. */
6910 #define constraint(expr, err) \
6921 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6922 instructions are unpredictable if these registers are used. This
6923 is the BadReg predicate in ARM's Thumb-2 documentation. */
6924 #define reject_bad_reg(reg) \
6926 if (reg == REG_SP || reg == REG_PC) \
6928 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6933 /* If REG is R13 (the stack pointer), warn that its use is
6935 #define warn_deprecated_sp(reg) \
6937 if (warn_on_deprecated && reg == REG_SP) \
6938 as_warn (_("use of r13 is deprecated")); \
6941 /* Functions for operand encoding. ARM, then Thumb. */
6943 #define rotate_left(v, n) (v << n | v >> (32 - n))
6945 /* If VAL can be encoded in the immediate field of an ARM instruction,
6946 return the encoded form. Otherwise, return FAIL. */
6949 encode_arm_immediate (unsigned int val)
6953 for (i = 0; i < 32; i += 2)
6954 if ((a = rotate_left (val, i)) <= 0xff)
6955 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6960 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6961 return the encoded form. Otherwise, return FAIL. */
6963 encode_thumb32_immediate (unsigned int val)
6970 for (i = 1; i <= 24; i++)
6973 if ((val & ~(0xff << i)) == 0)
6974 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6978 if (val == ((a << 16) | a))
6980 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6984 if (val == ((a << 16) | a))
6985 return 0x200 | (a >> 8);
6989 /* Encode a VFP SP or DP register number into inst.instruction. */
6992 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6994 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6997 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7000 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7003 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7008 first_error (_("D register out of range for selected VFP version"));
7016 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7020 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7024 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7028 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7032 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7036 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7044 /* Encode a <shift> in an ARM-format instruction. The immediate,
7045 if any, is handled by md_apply_fix. */
7047 encode_arm_shift (int i)
7049 if (inst.operands[i].shift_kind == SHIFT_RRX)
7050 inst.instruction |= SHIFT_ROR << 5;
7053 inst.instruction |= inst.operands[i].shift_kind << 5;
7054 if (inst.operands[i].immisreg)
7056 inst.instruction |= SHIFT_BY_REG;
7057 inst.instruction |= inst.operands[i].imm << 8;
7060 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7065 encode_arm_shifter_operand (int i)
7067 if (inst.operands[i].isreg)
7069 inst.instruction |= inst.operands[i].reg;
7070 encode_arm_shift (i);
7074 inst.instruction |= INST_IMMEDIATE;
7075 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7076 inst.instruction |= inst.operands[i].imm;
7080 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7082 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7085 Generate an error if the operand is not a register. */
7086 constraint (!inst.operands[i].isreg,
7087 _("Instruction does not support =N addresses"));
7089 inst.instruction |= inst.operands[i].reg << 16;
7091 if (inst.operands[i].preind)
7095 inst.error = _("instruction does not accept preindexed addressing");
7098 inst.instruction |= PRE_INDEX;
7099 if (inst.operands[i].writeback)
7100 inst.instruction |= WRITE_BACK;
7103 else if (inst.operands[i].postind)
7105 gas_assert (inst.operands[i].writeback);
7107 inst.instruction |= WRITE_BACK;
7109 else /* unindexed - only for coprocessor */
7111 inst.error = _("instruction does not accept unindexed addressing");
7115 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7116 && (((inst.instruction & 0x000f0000) >> 16)
7117 == ((inst.instruction & 0x0000f000) >> 12)))
7118 as_warn ((inst.instruction & LOAD_BIT)
7119 ? _("destination register same as write-back base")
7120 : _("source register same as write-back base"));
7123 /* inst.operands[i] was set up by parse_address. Encode it into an
7124 ARM-format mode 2 load or store instruction. If is_t is true,
7125 reject forms that cannot be used with a T instruction (i.e. not
7128 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7130 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7132 encode_arm_addr_mode_common (i, is_t);
7134 if (inst.operands[i].immisreg)
7136 constraint ((inst.operands[i].imm == REG_PC
7137 || (is_pc && inst.operands[i].writeback)),
7139 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7140 inst.instruction |= inst.operands[i].imm;
7141 if (!inst.operands[i].negative)
7142 inst.instruction |= INDEX_UP;
7143 if (inst.operands[i].shifted)
7145 if (inst.operands[i].shift_kind == SHIFT_RRX)
7146 inst.instruction |= SHIFT_ROR << 5;
7149 inst.instruction |= inst.operands[i].shift_kind << 5;
7150 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7154 else /* immediate offset in inst.reloc */
7156 if (is_pc && !inst.reloc.pc_rel)
7158 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7160 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7161 cannot use PC in addressing.
7162 PC cannot be used in writeback addressing, either. */
7163 constraint ((is_t || inst.operands[i].writeback),
7166 /* Use of PC in str is deprecated for ARMv7. */
7167 if (warn_on_deprecated
7169 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7170 as_warn (_("use of PC in this instruction is deprecated"));
7173 if (inst.reloc.type == BFD_RELOC_UNUSED)
7175 /* Prefer + for zero encoded value. */
7176 if (!inst.operands[i].negative)
7177 inst.instruction |= INDEX_UP;
7178 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7183 /* inst.operands[i] was set up by parse_address. Encode it into an
7184 ARM-format mode 3 load or store instruction. Reject forms that
7185 cannot be used with such instructions. If is_t is true, reject
7186 forms that cannot be used with a T instruction (i.e. not
7189 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7191 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7193 inst.error = _("instruction does not accept scaled register index");
7197 encode_arm_addr_mode_common (i, is_t);
7199 if (inst.operands[i].immisreg)
7201 constraint ((inst.operands[i].imm == REG_PC
7202 || (is_t && inst.operands[i].reg == REG_PC)),
7204 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7206 inst.instruction |= inst.operands[i].imm;
7207 if (!inst.operands[i].negative)
7208 inst.instruction |= INDEX_UP;
7210 else /* immediate offset in inst.reloc */
7212 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7213 && inst.operands[i].writeback),
7215 inst.instruction |= HWOFFSET_IMM;
7216 if (inst.reloc.type == BFD_RELOC_UNUSED)
7218 /* Prefer + for zero encoded value. */
7219 if (!inst.operands[i].negative)
7220 inst.instruction |= INDEX_UP;
7222 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7227 /* inst.operands[i] was set up by parse_address. Encode it into an
7228 ARM-format instruction. Reject all forms which cannot be encoded
7229 into a coprocessor load/store instruction. If wb_ok is false,
7230 reject use of writeback; if unind_ok is false, reject use of
7231 unindexed addressing. If reloc_override is not 0, use it instead
7232 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7233 (in which case it is preserved). */
7236 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7238 inst.instruction |= inst.operands[i].reg << 16;
7240 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7242 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7244 gas_assert (!inst.operands[i].writeback);
7247 inst.error = _("instruction does not support unindexed addressing");
7250 inst.instruction |= inst.operands[i].imm;
7251 inst.instruction |= INDEX_UP;
7255 if (inst.operands[i].preind)
7256 inst.instruction |= PRE_INDEX;
7258 if (inst.operands[i].writeback)
7260 if (inst.operands[i].reg == REG_PC)
7262 inst.error = _("pc may not be used with write-back");
7267 inst.error = _("instruction does not support writeback");
7270 inst.instruction |= WRITE_BACK;
7274 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7275 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7276 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7277 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7280 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7282 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7285 /* Prefer + for zero encoded value. */
7286 if (!inst.operands[i].negative)
7287 inst.instruction |= INDEX_UP;
7292 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7293 Determine whether it can be performed with a move instruction; if
7294 it can, convert inst.instruction to that move instruction and
7295 return TRUE; if it can't, convert inst.instruction to a literal-pool
7296 load and return FALSE. If this is not a valid thing to do in the
7297 current context, set inst.error and return TRUE.
7299 inst.operands[i] describes the destination register. */
7302 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7307 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7311 if ((inst.instruction & tbit) == 0)
7313 inst.error = _("invalid pseudo operation");
7316 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7318 inst.error = _("constant expression expected");
7321 if (inst.reloc.exp.X_op == O_constant)
7325 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7327 /* This can be done with a mov(1) instruction. */
7328 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7329 inst.instruction |= inst.reloc.exp.X_add_number;
7335 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7338 /* This can be done with a mov instruction. */
7339 inst.instruction &= LITERAL_MASK;
7340 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7341 inst.instruction |= value & 0xfff;
7345 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7348 /* This can be done with a mvn instruction. */
7349 inst.instruction &= LITERAL_MASK;
7350 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7351 inst.instruction |= value & 0xfff;
7357 if (add_to_lit_pool () == FAIL)
7359 inst.error = _("literal pool insertion failed");
7362 inst.operands[1].reg = REG_PC;
7363 inst.operands[1].isreg = 1;
7364 inst.operands[1].preind = 1;
7365 inst.reloc.pc_rel = 1;
7366 inst.reloc.type = (thumb_p
7367 ? BFD_RELOC_ARM_THUMB_OFFSET
7369 ? BFD_RELOC_ARM_HWLITERAL
7370 : BFD_RELOC_ARM_LITERAL));
7374 /* Functions for instruction encoding, sorted by sub-architecture.
7375 First some generics; their names are taken from the conventional
7376 bit positions for register arguments in ARM format instructions. */
7386 inst.instruction |= inst.operands[0].reg << 12;
7392 inst.instruction |= inst.operands[0].reg << 12;
7393 inst.instruction |= inst.operands[1].reg;
7399 inst.instruction |= inst.operands[0].reg;
7400 inst.instruction |= inst.operands[1].reg << 16;
7406 inst.instruction |= inst.operands[0].reg << 12;
7407 inst.instruction |= inst.operands[1].reg << 16;
7413 inst.instruction |= inst.operands[0].reg << 16;
7414 inst.instruction |= inst.operands[1].reg << 12;
7418 check_obsolete (const arm_feature_set *feature, const char *msg)
7420 if (ARM_CPU_IS_ANY (cpu_variant))
7422 as_warn ("%s", msg);
7425 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7437 unsigned Rn = inst.operands[2].reg;
7438 /* Enforce restrictions on SWP instruction. */
7439 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7441 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7442 _("Rn must not overlap other operands"));
7444 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7446 if (!check_obsolete (&arm_ext_v8,
7447 _("swp{b} use is obsoleted for ARMv8 and later"))
7448 && warn_on_deprecated
7449 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7450 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7453 inst.instruction |= inst.operands[0].reg << 12;
7454 inst.instruction |= inst.operands[1].reg;
7455 inst.instruction |= Rn << 16;
7461 inst.instruction |= inst.operands[0].reg << 12;
7462 inst.instruction |= inst.operands[1].reg << 16;
7463 inst.instruction |= inst.operands[2].reg;
7469 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7470 constraint (((inst.reloc.exp.X_op != O_constant
7471 && inst.reloc.exp.X_op != O_illegal)
7472 || inst.reloc.exp.X_add_number != 0),
7474 inst.instruction |= inst.operands[0].reg;
7475 inst.instruction |= inst.operands[1].reg << 12;
7476 inst.instruction |= inst.operands[2].reg << 16;
7482 inst.instruction |= inst.operands[0].imm;
7488 inst.instruction |= inst.operands[0].reg << 12;
7489 encode_arm_cp_address (1, TRUE, TRUE, 0);
7492 /* ARM instructions, in alphabetical order by function name (except
7493 that wrapper functions appear immediately after the function they
7496 /* This is a pseudo-op of the form "adr rd, label" to be converted
7497 into a relative address of the form "add rd, pc, #label-.-8". */
7502 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7504 /* Frag hacking will turn this into a sub instruction if the offset turns
7505 out to be negative. */
7506 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7507 inst.reloc.pc_rel = 1;
7508 inst.reloc.exp.X_add_number -= 8;
7511 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7512 into a relative address of the form:
7513 add rd, pc, #low(label-.-8)"
7514 add rd, rd, #high(label-.-8)" */
7519 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7521 /* Frag hacking will turn this into a sub instruction if the offset turns
7522 out to be negative. */
7523 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7524 inst.reloc.pc_rel = 1;
7525 inst.size = INSN_SIZE * 2;
7526 inst.reloc.exp.X_add_number -= 8;
7532 if (!inst.operands[1].present)
7533 inst.operands[1].reg = inst.operands[0].reg;
7534 inst.instruction |= inst.operands[0].reg << 12;
7535 inst.instruction |= inst.operands[1].reg << 16;
7536 encode_arm_shifter_operand (2);
7542 if (inst.operands[0].present)
7543 inst.instruction |= inst.operands[0].imm;
7545 inst.instruction |= 0xf;
7551 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7552 constraint (msb > 32, _("bit-field extends past end of register"));
7553 /* The instruction encoding stores the LSB and MSB,
7554 not the LSB and width. */
7555 inst.instruction |= inst.operands[0].reg << 12;
7556 inst.instruction |= inst.operands[1].imm << 7;
7557 inst.instruction |= (msb - 1) << 16;
7565 /* #0 in second position is alternative syntax for bfc, which is
7566 the same instruction but with REG_PC in the Rm field. */
7567 if (!inst.operands[1].isreg)
7568 inst.operands[1].reg = REG_PC;
7570 msb = inst.operands[2].imm + inst.operands[3].imm;
7571 constraint (msb > 32, _("bit-field extends past end of register"));
7572 /* The instruction encoding stores the LSB and MSB,
7573 not the LSB and width. */
7574 inst.instruction |= inst.operands[0].reg << 12;
7575 inst.instruction |= inst.operands[1].reg;
7576 inst.instruction |= inst.operands[2].imm << 7;
7577 inst.instruction |= (msb - 1) << 16;
7583 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7584 _("bit-field extends past end of register"));
7585 inst.instruction |= inst.operands[0].reg << 12;
7586 inst.instruction |= inst.operands[1].reg;
7587 inst.instruction |= inst.operands[2].imm << 7;
7588 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7591 /* ARM V5 breakpoint instruction (argument parse)
7592 BKPT <16 bit unsigned immediate>
7593 Instruction is not conditional.
7594 The bit pattern given in insns[] has the COND_ALWAYS condition,
7595 and it is an error if the caller tried to override that. */
7600 /* Top 12 of 16 bits to bits 19:8. */
7601 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7603 /* Bottom 4 of 16 bits to bits 3:0. */
7604 inst.instruction |= inst.operands[0].imm & 0xf;
7608 encode_branch (int default_reloc)
7610 if (inst.operands[0].hasreloc)
7612 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7613 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7614 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7615 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7616 ? BFD_RELOC_ARM_PLT32
7617 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7620 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7621 inst.reloc.pc_rel = 1;
7628 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7629 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7632 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7639 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7641 if (inst.cond == COND_ALWAYS)
7642 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7644 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7648 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7651 /* ARM V5 branch-link-exchange instruction (argument parse)
7652 BLX <target_addr> ie BLX(1)
7653 BLX{<condition>} <Rm> ie BLX(2)
7654 Unfortunately, there are two different opcodes for this mnemonic.
7655 So, the insns[].value is not used, and the code here zaps values
7656 into inst.instruction.
7657 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7662 if (inst.operands[0].isreg)
7664 /* Arg is a register; the opcode provided by insns[] is correct.
7665 It is not illegal to do "blx pc", just useless. */
7666 if (inst.operands[0].reg == REG_PC)
7667 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7669 inst.instruction |= inst.operands[0].reg;
7673 /* Arg is an address; this instruction cannot be executed
7674 conditionally, and the opcode must be adjusted.
7675 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7676 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7677 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7678 inst.instruction = 0xfa000000;
7679 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7686 bfd_boolean want_reloc;
7688 if (inst.operands[0].reg == REG_PC)
7689 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7691 inst.instruction |= inst.operands[0].reg;
7692 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7693 it is for ARMv4t or earlier. */
7694 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7695 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7699 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7704 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7708 /* ARM v5TEJ. Jump to Jazelle code. */
7713 if (inst.operands[0].reg == REG_PC)
7714 as_tsktsk (_("use of r15 in bxj is not really useful"));
7716 inst.instruction |= inst.operands[0].reg;
7719 /* Co-processor data operation:
7720 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7721 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7725 inst.instruction |= inst.operands[0].reg << 8;
7726 inst.instruction |= inst.operands[1].imm << 20;
7727 inst.instruction |= inst.operands[2].reg << 12;
7728 inst.instruction |= inst.operands[3].reg << 16;
7729 inst.instruction |= inst.operands[4].reg;
7730 inst.instruction |= inst.operands[5].imm << 5;
7736 inst.instruction |= inst.operands[0].reg << 16;
7737 encode_arm_shifter_operand (1);
7740 /* Transfer between coprocessor and ARM registers.
7741 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7746 No special properties. */
7748 struct deprecated_coproc_regs_s
7755 arm_feature_set deprecated;
7756 arm_feature_set obsoleted;
7757 const char *dep_msg;
7758 const char *obs_msg;
7761 #define DEPR_ACCESS_V8 \
7762 N_("This coprocessor register access is deprecated in ARMv8")
7764 /* Table of all deprecated coprocessor registers. */
7765 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7767 {15, 0, 7, 10, 5, /* CP15DMB. */
7768 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7769 DEPR_ACCESS_V8, NULL},
7770 {15, 0, 7, 10, 4, /* CP15DSB. */
7771 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7772 DEPR_ACCESS_V8, NULL},
7773 {15, 0, 7, 5, 4, /* CP15ISB. */
7774 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7775 DEPR_ACCESS_V8, NULL},
7776 {14, 6, 1, 0, 0, /* TEEHBR. */
7777 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8, NULL},
7779 {14, 6, 0, 0, 0, /* TEECR. */
7780 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8, NULL},
7784 #undef DEPR_ACCESS_V8
7786 static const size_t deprecated_coproc_reg_count =
7787 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7795 Rd = inst.operands[2].reg;
7798 if (inst.instruction == 0xee000010
7799 || inst.instruction == 0xfe000010)
7801 reject_bad_reg (Rd);
7804 constraint (Rd == REG_SP, BAD_SP);
7809 if (inst.instruction == 0xe000010)
7810 constraint (Rd == REG_PC, BAD_PC);
7813 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7815 const struct deprecated_coproc_regs_s *r =
7816 deprecated_coproc_regs + i;
7818 if (inst.operands[0].reg == r->cp
7819 && inst.operands[1].imm == r->opc1
7820 && inst.operands[3].reg == r->crn
7821 && inst.operands[4].reg == r->crm
7822 && inst.operands[5].imm == r->opc2)
7824 if (! ARM_CPU_IS_ANY (cpu_variant)
7825 && warn_on_deprecated
7826 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7827 as_warn ("%s", r->dep_msg);
7831 inst.instruction |= inst.operands[0].reg << 8;
7832 inst.instruction |= inst.operands[1].imm << 21;
7833 inst.instruction |= Rd << 12;
7834 inst.instruction |= inst.operands[3].reg << 16;
7835 inst.instruction |= inst.operands[4].reg;
7836 inst.instruction |= inst.operands[5].imm << 5;
7839 /* Transfer between coprocessor register and pair of ARM registers.
7840 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7845 Two XScale instructions are special cases of these:
7847 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7848 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7850 Result unpredictable if Rd or Rn is R15. */
7857 Rd = inst.operands[2].reg;
7858 Rn = inst.operands[3].reg;
7862 reject_bad_reg (Rd);
7863 reject_bad_reg (Rn);
7867 constraint (Rd == REG_PC, BAD_PC);
7868 constraint (Rn == REG_PC, BAD_PC);
7871 inst.instruction |= inst.operands[0].reg << 8;
7872 inst.instruction |= inst.operands[1].imm << 4;
7873 inst.instruction |= Rd << 12;
7874 inst.instruction |= Rn << 16;
7875 inst.instruction |= inst.operands[4].reg;
7881 inst.instruction |= inst.operands[0].imm << 6;
7882 if (inst.operands[1].present)
7884 inst.instruction |= CPSI_MMOD;
7885 inst.instruction |= inst.operands[1].imm;
7892 inst.instruction |= inst.operands[0].imm;
7898 unsigned Rd, Rn, Rm;
7900 Rd = inst.operands[0].reg;
7901 Rn = (inst.operands[1].present
7902 ? inst.operands[1].reg : Rd);
7903 Rm = inst.operands[2].reg;
7905 constraint ((Rd == REG_PC), BAD_PC);
7906 constraint ((Rn == REG_PC), BAD_PC);
7907 constraint ((Rm == REG_PC), BAD_PC);
7909 inst.instruction |= Rd << 16;
7910 inst.instruction |= Rn << 0;
7911 inst.instruction |= Rm << 8;
7917 /* There is no IT instruction in ARM mode. We
7918 process it to do the validation as if in
7919 thumb mode, just in case the code gets
7920 assembled for thumb using the unified syntax. */
7925 set_it_insn_type (IT_INSN);
7926 now_it.mask = (inst.instruction & 0xf) | 0x10;
7927 now_it.cc = inst.operands[0].imm;
7931 /* If there is only one register in the register list,
7932 then return its register number. Otherwise return -1. */
7934 only_one_reg_in_list (int range)
7936 int i = ffs (range) - 1;
7937 return (i > 15 || range != (1 << i)) ? -1 : i;
7941 encode_ldmstm(int from_push_pop_mnem)
7943 int base_reg = inst.operands[0].reg;
7944 int range = inst.operands[1].imm;
7947 inst.instruction |= base_reg << 16;
7948 inst.instruction |= range;
7950 if (inst.operands[1].writeback)
7951 inst.instruction |= LDM_TYPE_2_OR_3;
7953 if (inst.operands[0].writeback)
7955 inst.instruction |= WRITE_BACK;
7956 /* Check for unpredictable uses of writeback. */
7957 if (inst.instruction & LOAD_BIT)
7959 /* Not allowed in LDM type 2. */
7960 if ((inst.instruction & LDM_TYPE_2_OR_3)
7961 && ((range & (1 << REG_PC)) == 0))
7962 as_warn (_("writeback of base register is UNPREDICTABLE"));
7963 /* Only allowed if base reg not in list for other types. */
7964 else if (range & (1 << base_reg))
7965 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7969 /* Not allowed for type 2. */
7970 if (inst.instruction & LDM_TYPE_2_OR_3)
7971 as_warn (_("writeback of base register is UNPREDICTABLE"));
7972 /* Only allowed if base reg not in list, or first in list. */
7973 else if ((range & (1 << base_reg))
7974 && (range & ((1 << base_reg) - 1)))
7975 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7979 /* If PUSH/POP has only one register, then use the A2 encoding. */
7980 one_reg = only_one_reg_in_list (range);
7981 if (from_push_pop_mnem && one_reg >= 0)
7983 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7985 inst.instruction &= A_COND_MASK;
7986 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7987 inst.instruction |= one_reg << 12;
7994 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7997 /* ARMv5TE load-consecutive (argument parse)
8006 constraint (inst.operands[0].reg % 2 != 0,
8007 _("first transfer register must be even"));
8008 constraint (inst.operands[1].present
8009 && inst.operands[1].reg != inst.operands[0].reg + 1,
8010 _("can only transfer two consecutive registers"));
8011 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8012 constraint (!inst.operands[2].isreg, _("'[' expected"));
8014 if (!inst.operands[1].present)
8015 inst.operands[1].reg = inst.operands[0].reg + 1;
8017 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8018 register and the first register written; we have to diagnose
8019 overlap between the base and the second register written here. */
8021 if (inst.operands[2].reg == inst.operands[1].reg
8022 && (inst.operands[2].writeback || inst.operands[2].postind))
8023 as_warn (_("base register written back, and overlaps "
8024 "second transfer register"));
8026 if (!(inst.instruction & V4_STR_BIT))
8028 /* For an index-register load, the index register must not overlap the
8029 destination (even if not write-back). */
8030 if (inst.operands[2].immisreg
8031 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8032 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8033 as_warn (_("index register overlaps transfer register"));
8035 inst.instruction |= inst.operands[0].reg << 12;
8036 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8042 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8043 || inst.operands[1].postind || inst.operands[1].writeback
8044 || inst.operands[1].immisreg || inst.operands[1].shifted
8045 || inst.operands[1].negative
8046 /* This can arise if the programmer has written
8048 or if they have mistakenly used a register name as the last
8051 It is very difficult to distinguish between these two cases
8052 because "rX" might actually be a label. ie the register
8053 name has been occluded by a symbol of the same name. So we
8054 just generate a general 'bad addressing mode' type error
8055 message and leave it up to the programmer to discover the
8056 true cause and fix their mistake. */
8057 || (inst.operands[1].reg == REG_PC),
8060 constraint (inst.reloc.exp.X_op != O_constant
8061 || inst.reloc.exp.X_add_number != 0,
8062 _("offset must be zero in ARM encoding"));
8064 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8066 inst.instruction |= inst.operands[0].reg << 12;
8067 inst.instruction |= inst.operands[1].reg << 16;
8068 inst.reloc.type = BFD_RELOC_UNUSED;
8074 constraint (inst.operands[0].reg % 2 != 0,
8075 _("even register required"));
8076 constraint (inst.operands[1].present
8077 && inst.operands[1].reg != inst.operands[0].reg + 1,
8078 _("can only load two consecutive registers"));
8079 /* If op 1 were present and equal to PC, this function wouldn't
8080 have been called in the first place. */
8081 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8083 inst.instruction |= inst.operands[0].reg << 12;
8084 inst.instruction |= inst.operands[2].reg << 16;
8087 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8088 which is not a multiple of four is UNPREDICTABLE. */
8090 check_ldr_r15_aligned (void)
8092 constraint (!(inst.operands[1].immisreg)
8093 && (inst.operands[0].reg == REG_PC
8094 && inst.operands[1].reg == REG_PC
8095 && (inst.reloc.exp.X_add_number & 0x3)),
8096 _("ldr to register 15 must be 4-byte alligned"));
8102 inst.instruction |= inst.operands[0].reg << 12;
8103 if (!inst.operands[1].isreg)
8104 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8106 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8107 check_ldr_r15_aligned ();
8113 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8115 if (inst.operands[1].preind)
8117 constraint (inst.reloc.exp.X_op != O_constant
8118 || inst.reloc.exp.X_add_number != 0,
8119 _("this instruction requires a post-indexed address"));
8121 inst.operands[1].preind = 0;
8122 inst.operands[1].postind = 1;
8123 inst.operands[1].writeback = 1;
8125 inst.instruction |= inst.operands[0].reg << 12;
8126 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8129 /* Halfword and signed-byte load/store operations. */
8134 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8135 inst.instruction |= inst.operands[0].reg << 12;
8136 if (!inst.operands[1].isreg)
8137 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8139 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8145 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8147 if (inst.operands[1].preind)
8149 constraint (inst.reloc.exp.X_op != O_constant
8150 || inst.reloc.exp.X_add_number != 0,
8151 _("this instruction requires a post-indexed address"));
8153 inst.operands[1].preind = 0;
8154 inst.operands[1].postind = 1;
8155 inst.operands[1].writeback = 1;
8157 inst.instruction |= inst.operands[0].reg << 12;
8158 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8161 /* Co-processor register load/store.
8162 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8166 inst.instruction |= inst.operands[0].reg << 8;
8167 inst.instruction |= inst.operands[1].reg << 12;
8168 encode_arm_cp_address (2, TRUE, TRUE, 0);
8174 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8175 if (inst.operands[0].reg == inst.operands[1].reg
8176 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8177 && !(inst.instruction & 0x00400000))
8178 as_tsktsk (_("Rd and Rm should be different in mla"));
8180 inst.instruction |= inst.operands[0].reg << 16;
8181 inst.instruction |= inst.operands[1].reg;
8182 inst.instruction |= inst.operands[2].reg << 8;
8183 inst.instruction |= inst.operands[3].reg << 12;
8189 inst.instruction |= inst.operands[0].reg << 12;
8190 encode_arm_shifter_operand (1);
8193 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8200 top = (inst.instruction & 0x00400000) != 0;
8201 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8202 _(":lower16: not allowed this instruction"));
8203 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8204 _(":upper16: not allowed instruction"));
8205 inst.instruction |= inst.operands[0].reg << 12;
8206 if (inst.reloc.type == BFD_RELOC_UNUSED)
8208 imm = inst.reloc.exp.X_add_number;
8209 /* The value is in two pieces: 0:11, 16:19. */
8210 inst.instruction |= (imm & 0x00000fff);
8211 inst.instruction |= (imm & 0x0000f000) << 4;
8215 static void do_vfp_nsyn_opcode (const char *);
8218 do_vfp_nsyn_mrs (void)
8220 if (inst.operands[0].isvec)
8222 if (inst.operands[1].reg != 1)
8223 first_error (_("operand 1 must be FPSCR"));
8224 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8225 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8226 do_vfp_nsyn_opcode ("fmstat");
8228 else if (inst.operands[1].isvec)
8229 do_vfp_nsyn_opcode ("fmrx");
8237 do_vfp_nsyn_msr (void)
8239 if (inst.operands[0].isvec)
8240 do_vfp_nsyn_opcode ("fmxr");
8250 unsigned Rt = inst.operands[0].reg;
8252 if (thumb_mode && Rt == REG_SP)
8254 inst.error = BAD_SP;
8258 /* APSR_ sets isvec. All other refs to PC are illegal. */
8259 if (!inst.operands[0].isvec && Rt == REG_PC)
8261 inst.error = BAD_PC;
8265 /* If we get through parsing the register name, we just insert the number
8266 generated into the instruction without further validation. */
8267 inst.instruction |= (inst.operands[1].reg << 16);
8268 inst.instruction |= (Rt << 12);
8274 unsigned Rt = inst.operands[1].reg;
8277 reject_bad_reg (Rt);
8278 else if (Rt == REG_PC)
8280 inst.error = BAD_PC;
8284 /* If we get through parsing the register name, we just insert the number
8285 generated into the instruction without further validation. */
8286 inst.instruction |= (inst.operands[0].reg << 16);
8287 inst.instruction |= (Rt << 12);
8295 if (do_vfp_nsyn_mrs () == SUCCESS)
8298 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8299 inst.instruction |= inst.operands[0].reg << 12;
8301 if (inst.operands[1].isreg)
8303 br = inst.operands[1].reg;
8304 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8305 as_bad (_("bad register for mrs"));
8309 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8310 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8312 _("'APSR', 'CPSR' or 'SPSR' expected"));
8313 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8316 inst.instruction |= br;
8319 /* Two possible forms:
8320 "{C|S}PSR_<field>, Rm",
8321 "{C|S}PSR_f, #expression". */
8326 if (do_vfp_nsyn_msr () == SUCCESS)
8329 inst.instruction |= inst.operands[0].imm;
8330 if (inst.operands[1].isreg)
8331 inst.instruction |= inst.operands[1].reg;
8334 inst.instruction |= INST_IMMEDIATE;
8335 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8336 inst.reloc.pc_rel = 0;
8343 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8345 if (!inst.operands[2].present)
8346 inst.operands[2].reg = inst.operands[0].reg;
8347 inst.instruction |= inst.operands[0].reg << 16;
8348 inst.instruction |= inst.operands[1].reg;
8349 inst.instruction |= inst.operands[2].reg << 8;
8351 if (inst.operands[0].reg == inst.operands[1].reg
8352 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8353 as_tsktsk (_("Rd and Rm should be different in mul"));
8356 /* Long Multiply Parser
8357 UMULL RdLo, RdHi, Rm, Rs
8358 SMULL RdLo, RdHi, Rm, Rs
8359 UMLAL RdLo, RdHi, Rm, Rs
8360 SMLAL RdLo, RdHi, Rm, Rs. */
8365 inst.instruction |= inst.operands[0].reg << 12;
8366 inst.instruction |= inst.operands[1].reg << 16;
8367 inst.instruction |= inst.operands[2].reg;
8368 inst.instruction |= inst.operands[3].reg << 8;
8370 /* rdhi and rdlo must be different. */
8371 if (inst.operands[0].reg == inst.operands[1].reg)
8372 as_tsktsk (_("rdhi and rdlo must be different"));
8374 /* rdhi, rdlo and rm must all be different before armv6. */
8375 if ((inst.operands[0].reg == inst.operands[2].reg
8376 || inst.operands[1].reg == inst.operands[2].reg)
8377 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8378 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8384 if (inst.operands[0].present
8385 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8387 /* Architectural NOP hints are CPSR sets with no bits selected. */
8388 inst.instruction &= 0xf0000000;
8389 inst.instruction |= 0x0320f000;
8390 if (inst.operands[0].present)
8391 inst.instruction |= inst.operands[0].imm;
8395 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8396 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8397 Condition defaults to COND_ALWAYS.
8398 Error if Rd, Rn or Rm are R15. */
8403 inst.instruction |= inst.operands[0].reg << 12;
8404 inst.instruction |= inst.operands[1].reg << 16;
8405 inst.instruction |= inst.operands[2].reg;
8406 if (inst.operands[3].present)
8407 encode_arm_shift (3);
8410 /* ARM V6 PKHTB (Argument Parse). */
8415 if (!inst.operands[3].present)
8417 /* If the shift specifier is omitted, turn the instruction
8418 into pkhbt rd, rm, rn. */
8419 inst.instruction &= 0xfff00010;
8420 inst.instruction |= inst.operands[0].reg << 12;
8421 inst.instruction |= inst.operands[1].reg;
8422 inst.instruction |= inst.operands[2].reg << 16;
8426 inst.instruction |= inst.operands[0].reg << 12;
8427 inst.instruction |= inst.operands[1].reg << 16;
8428 inst.instruction |= inst.operands[2].reg;
8429 encode_arm_shift (3);
8433 /* ARMv5TE: Preload-Cache
8434 MP Extensions: Preload for write
8438 Syntactically, like LDR with B=1, W=0, L=1. */
8443 constraint (!inst.operands[0].isreg,
8444 _("'[' expected after PLD mnemonic"));
8445 constraint (inst.operands[0].postind,
8446 _("post-indexed expression used in preload instruction"));
8447 constraint (inst.operands[0].writeback,
8448 _("writeback used in preload instruction"));
8449 constraint (!inst.operands[0].preind,
8450 _("unindexed addressing used in preload instruction"));
8451 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8454 /* ARMv7: PLI <addr_mode> */
8458 constraint (!inst.operands[0].isreg,
8459 _("'[' expected after PLI mnemonic"));
8460 constraint (inst.operands[0].postind,
8461 _("post-indexed expression used in preload instruction"));
8462 constraint (inst.operands[0].writeback,
8463 _("writeback used in preload instruction"));
8464 constraint (!inst.operands[0].preind,
8465 _("unindexed addressing used in preload instruction"));
8466 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 inst.instruction &= ~PRE_INDEX;
8473 inst.operands[1] = inst.operands[0];
8474 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8475 inst.operands[0].isreg = 1;
8476 inst.operands[0].writeback = 1;
8477 inst.operands[0].reg = REG_SP;
8478 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8481 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8482 word at the specified address and the following word
8484 Unconditionally executed.
8485 Error if Rn is R15. */
8490 inst.instruction |= inst.operands[0].reg << 16;
8491 if (inst.operands[0].writeback)
8492 inst.instruction |= WRITE_BACK;
8495 /* ARM V6 ssat (argument parse). */
8500 inst.instruction |= inst.operands[0].reg << 12;
8501 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8502 inst.instruction |= inst.operands[2].reg;
8504 if (inst.operands[3].present)
8505 encode_arm_shift (3);
8508 /* ARM V6 usat (argument parse). */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= inst.operands[1].imm << 16;
8515 inst.instruction |= inst.operands[2].reg;
8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
8521 /* ARM V6 ssat16 (argument parse). */
8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8528 inst.instruction |= inst.operands[2].reg;
8534 inst.instruction |= inst.operands[0].reg << 12;
8535 inst.instruction |= inst.operands[1].imm << 16;
8536 inst.instruction |= inst.operands[2].reg;
8539 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8540 preserving the other bits.
8542 setend <endian_specifier>, where <endian_specifier> is either
8548 if (warn_on_deprecated
8549 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8550 as_warn (_("setend use is deprecated for ARMv8"));
8552 if (inst.operands[0].imm)
8553 inst.instruction |= 0x200;
8559 unsigned int Rm = (inst.operands[1].present
8560 ? inst.operands[1].reg
8561 : inst.operands[0].reg);
8563 inst.instruction |= inst.operands[0].reg << 12;
8564 inst.instruction |= Rm;
8565 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8567 inst.instruction |= inst.operands[2].reg << 8;
8568 inst.instruction |= SHIFT_BY_REG;
8569 /* PR 12854: Error on extraneous shifts. */
8570 constraint (inst.operands[2].shifted,
8571 _("extraneous shift as part of operand to shift insn"));
8574 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8580 inst.reloc.type = BFD_RELOC_ARM_SMC;
8581 inst.reloc.pc_rel = 0;
8587 inst.reloc.type = BFD_RELOC_ARM_HVC;
8588 inst.reloc.pc_rel = 0;
8594 inst.reloc.type = BFD_RELOC_ARM_SWI;
8595 inst.reloc.pc_rel = 0;
8598 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8599 SMLAxy{cond} Rd,Rm,Rs,Rn
8600 SMLAWy{cond} Rd,Rm,Rs,Rn
8601 Error if any register is R15. */
8606 inst.instruction |= inst.operands[0].reg << 16;
8607 inst.instruction |= inst.operands[1].reg;
8608 inst.instruction |= inst.operands[2].reg << 8;
8609 inst.instruction |= inst.operands[3].reg << 12;
8612 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8613 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8614 Error if any register is R15.
8615 Warning if Rdlo == Rdhi. */
8620 inst.instruction |= inst.operands[0].reg << 12;
8621 inst.instruction |= inst.operands[1].reg << 16;
8622 inst.instruction |= inst.operands[2].reg;
8623 inst.instruction |= inst.operands[3].reg << 8;
8625 if (inst.operands[0].reg == inst.operands[1].reg)
8626 as_tsktsk (_("rdhi and rdlo must be different"));
8629 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8630 SMULxy{cond} Rd,Rm,Rs
8631 Error if any register is R15. */
8636 inst.instruction |= inst.operands[0].reg << 16;
8637 inst.instruction |= inst.operands[1].reg;
8638 inst.instruction |= inst.operands[2].reg << 8;
8641 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8642 the same for both ARM and Thumb-2. */
8649 if (inst.operands[0].present)
8651 reg = inst.operands[0].reg;
8652 constraint (reg != REG_SP, _("SRS base register must be r13"));
8657 inst.instruction |= reg << 16;
8658 inst.instruction |= inst.operands[1].imm;
8659 if (inst.operands[0].writeback || inst.operands[1].writeback)
8660 inst.instruction |= WRITE_BACK;
8663 /* ARM V6 strex (argument parse). */
8668 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8669 || inst.operands[2].postind || inst.operands[2].writeback
8670 || inst.operands[2].immisreg || inst.operands[2].shifted
8671 || inst.operands[2].negative
8672 /* See comment in do_ldrex(). */
8673 || (inst.operands[2].reg == REG_PC),
8676 constraint (inst.operands[0].reg == inst.operands[1].reg
8677 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8679 constraint (inst.reloc.exp.X_op != O_constant
8680 || inst.reloc.exp.X_add_number != 0,
8681 _("offset must be zero in ARM encoding"));
8683 inst.instruction |= inst.operands[0].reg << 12;
8684 inst.instruction |= inst.operands[1].reg;
8685 inst.instruction |= inst.operands[2].reg << 16;
8686 inst.reloc.type = BFD_RELOC_UNUSED;
8692 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8693 || inst.operands[2].postind || inst.operands[2].writeback
8694 || inst.operands[2].immisreg || inst.operands[2].shifted
8695 || inst.operands[2].negative,
8698 constraint (inst.operands[0].reg == inst.operands[1].reg
8699 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8707 constraint (inst.operands[1].reg % 2 != 0,
8708 _("even register required"));
8709 constraint (inst.operands[2].present
8710 && inst.operands[2].reg != inst.operands[1].reg + 1,
8711 _("can only store two consecutive registers"));
8712 /* If op 2 were present and equal to PC, this function wouldn't
8713 have been called in the first place. */
8714 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8716 constraint (inst.operands[0].reg == inst.operands[1].reg
8717 || inst.operands[0].reg == inst.operands[1].reg + 1
8718 || inst.operands[0].reg == inst.operands[3].reg,
8721 inst.instruction |= inst.operands[0].reg << 12;
8722 inst.instruction |= inst.operands[1].reg;
8723 inst.instruction |= inst.operands[3].reg << 16;
8730 constraint (inst.operands[0].reg == inst.operands[1].reg
8731 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8739 constraint (inst.operands[0].reg == inst.operands[1].reg
8740 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8745 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8746 extends it to 32-bits, and adds the result to a value in another
8747 register. You can specify a rotation by 0, 8, 16, or 24 bits
8748 before extracting the 16-bit value.
8749 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8750 Condition defaults to COND_ALWAYS.
8751 Error if any register uses R15. */
8756 inst.instruction |= inst.operands[0].reg << 12;
8757 inst.instruction |= inst.operands[1].reg << 16;
8758 inst.instruction |= inst.operands[2].reg;
8759 inst.instruction |= inst.operands[3].imm << 10;
8764 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8765 Condition defaults to COND_ALWAYS.
8766 Error if any register uses R15. */
8771 inst.instruction |= inst.operands[0].reg << 12;
8772 inst.instruction |= inst.operands[1].reg;
8773 inst.instruction |= inst.operands[2].imm << 10;
8776 /* VFP instructions. In a logical order: SP variant first, monad
8777 before dyad, arithmetic then move then load/store. */
8780 do_vfp_sp_monadic (void)
8782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8783 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8787 do_vfp_sp_dyadic (void)
8789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8790 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8791 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8795 do_vfp_sp_compare_z (void)
8797 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8801 do_vfp_dp_sp_cvt (void)
8803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8804 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8808 do_vfp_sp_dp_cvt (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8815 do_vfp_reg_from_sp (void)
8817 inst.instruction |= inst.operands[0].reg << 12;
8818 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8822 do_vfp_reg2_from_sp2 (void)
8824 constraint (inst.operands[2].imm != 2,
8825 _("only two consecutive VFP SP registers allowed here"));
8826 inst.instruction |= inst.operands[0].reg << 12;
8827 inst.instruction |= inst.operands[1].reg << 16;
8828 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8832 do_vfp_sp_from_reg (void)
8834 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8835 inst.instruction |= inst.operands[1].reg << 12;
8839 do_vfp_sp2_from_reg2 (void)
8841 constraint (inst.operands[0].imm != 2,
8842 _("only two consecutive VFP SP registers allowed here"));
8843 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8844 inst.instruction |= inst.operands[1].reg << 12;
8845 inst.instruction |= inst.operands[2].reg << 16;
8849 do_vfp_sp_ldst (void)
8851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8852 encode_arm_cp_address (1, FALSE, TRUE, 0);
8856 do_vfp_dp_ldst (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8859 encode_arm_cp_address (1, FALSE, TRUE, 0);
8864 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8866 if (inst.operands[0].writeback)
8867 inst.instruction |= WRITE_BACK;
8869 constraint (ldstm_type != VFP_LDSTMIA,
8870 _("this addressing mode requires base-register writeback"));
8871 inst.instruction |= inst.operands[0].reg << 16;
8872 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8873 inst.instruction |= inst.operands[1].imm;
8877 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8881 if (inst.operands[0].writeback)
8882 inst.instruction |= WRITE_BACK;
8884 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8885 _("this addressing mode requires base-register writeback"));
8887 inst.instruction |= inst.operands[0].reg << 16;
8888 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8890 count = inst.operands[1].imm << 1;
8891 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8894 inst.instruction |= count;
8898 do_vfp_sp_ldstmia (void)
8900 vfp_sp_ldstm (VFP_LDSTMIA);
8904 do_vfp_sp_ldstmdb (void)
8906 vfp_sp_ldstm (VFP_LDSTMDB);
8910 do_vfp_dp_ldstmia (void)
8912 vfp_dp_ldstm (VFP_LDSTMIA);
8916 do_vfp_dp_ldstmdb (void)
8918 vfp_dp_ldstm (VFP_LDSTMDB);
8922 do_vfp_xp_ldstmia (void)
8924 vfp_dp_ldstm (VFP_LDSTMIAX);
8928 do_vfp_xp_ldstmdb (void)
8930 vfp_dp_ldstm (VFP_LDSTMDBX);
8934 do_vfp_dp_rd_rm (void)
8936 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8937 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8941 do_vfp_dp_rn_rd (void)
8943 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8944 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8948 do_vfp_dp_rd_rn (void)
8950 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8951 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8955 do_vfp_dp_rd_rn_rm (void)
8957 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8958 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8959 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8965 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8969 do_vfp_dp_rm_rd_rn (void)
8971 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8972 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8973 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8976 /* VFPv3 instructions. */
8978 do_vfp_sp_const (void)
8980 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8981 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8982 inst.instruction |= (inst.operands[1].imm & 0x0f);
8986 do_vfp_dp_const (void)
8988 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8989 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8990 inst.instruction |= (inst.operands[1].imm & 0x0f);
8994 vfp_conv (int srcsize)
8996 int immbits = srcsize - inst.operands[1].imm;
8998 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9000 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9001 i.e. immbits must be in range 0 - 16. */
9002 inst.error = _("immediate value out of range, expected range [0, 16]");
9005 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9007 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9008 i.e. immbits must be in range 0 - 31. */
9009 inst.error = _("immediate value out of range, expected range [1, 32]");
9013 inst.instruction |= (immbits & 1) << 5;
9014 inst.instruction |= (immbits >> 1);
9018 do_vfp_sp_conv_16 (void)
9020 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9025 do_vfp_dp_conv_16 (void)
9027 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9032 do_vfp_sp_conv_32 (void)
9034 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9039 do_vfp_dp_conv_32 (void)
9041 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9045 /* FPA instructions. Also in a logical order. */
9050 inst.instruction |= inst.operands[0].reg << 16;
9051 inst.instruction |= inst.operands[1].reg;
9055 do_fpa_ldmstm (void)
9057 inst.instruction |= inst.operands[0].reg << 12;
9058 switch (inst.operands[1].imm)
9060 case 1: inst.instruction |= CP_T_X; break;
9061 case 2: inst.instruction |= CP_T_Y; break;
9062 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9067 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9069 /* The instruction specified "ea" or "fd", so we can only accept
9070 [Rn]{!}. The instruction does not really support stacking or
9071 unstacking, so we have to emulate these by setting appropriate
9072 bits and offsets. */
9073 constraint (inst.reloc.exp.X_op != O_constant
9074 || inst.reloc.exp.X_add_number != 0,
9075 _("this instruction does not support indexing"));
9077 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9078 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9080 if (!(inst.instruction & INDEX_UP))
9081 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9083 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9085 inst.operands[2].preind = 0;
9086 inst.operands[2].postind = 1;
9090 encode_arm_cp_address (2, TRUE, TRUE, 0);
9093 /* iWMMXt instructions: strictly in alphabetical order. */
9096 do_iwmmxt_tandorc (void)
9098 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9102 do_iwmmxt_textrc (void)
9104 inst.instruction |= inst.operands[0].reg << 12;
9105 inst.instruction |= inst.operands[1].imm;
9109 do_iwmmxt_textrm (void)
9111 inst.instruction |= inst.operands[0].reg << 12;
9112 inst.instruction |= inst.operands[1].reg << 16;
9113 inst.instruction |= inst.operands[2].imm;
9117 do_iwmmxt_tinsr (void)
9119 inst.instruction |= inst.operands[0].reg << 16;
9120 inst.instruction |= inst.operands[1].reg << 12;
9121 inst.instruction |= inst.operands[2].imm;
9125 do_iwmmxt_tmia (void)
9127 inst.instruction |= inst.operands[0].reg << 5;
9128 inst.instruction |= inst.operands[1].reg;
9129 inst.instruction |= inst.operands[2].reg << 12;
9133 do_iwmmxt_waligni (void)
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 inst.instruction |= inst.operands[1].reg << 16;
9137 inst.instruction |= inst.operands[2].reg;
9138 inst.instruction |= inst.operands[3].imm << 20;
9142 do_iwmmxt_wmerge (void)
9144 inst.instruction |= inst.operands[0].reg << 12;
9145 inst.instruction |= inst.operands[1].reg << 16;
9146 inst.instruction |= inst.operands[2].reg;
9147 inst.instruction |= inst.operands[3].imm << 21;
9151 do_iwmmxt_wmov (void)
9153 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9154 inst.instruction |= inst.operands[0].reg << 12;
9155 inst.instruction |= inst.operands[1].reg << 16;
9156 inst.instruction |= inst.operands[1].reg;
9160 do_iwmmxt_wldstbh (void)
9163 inst.instruction |= inst.operands[0].reg << 12;
9165 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9167 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9168 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9172 do_iwmmxt_wldstw (void)
9174 /* RIWR_RIWC clears .isreg for a control register. */
9175 if (!inst.operands[0].isreg)
9177 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9178 inst.instruction |= 0xf0000000;
9181 inst.instruction |= inst.operands[0].reg << 12;
9182 encode_arm_cp_address (1, TRUE, TRUE, 0);
9186 do_iwmmxt_wldstd (void)
9188 inst.instruction |= inst.operands[0].reg << 12;
9189 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9190 && inst.operands[1].immisreg)
9192 inst.instruction &= ~0x1a000ff;
9193 inst.instruction |= (0xf << 28);
9194 if (inst.operands[1].preind)
9195 inst.instruction |= PRE_INDEX;
9196 if (!inst.operands[1].negative)
9197 inst.instruction |= INDEX_UP;
9198 if (inst.operands[1].writeback)
9199 inst.instruction |= WRITE_BACK;
9200 inst.instruction |= inst.operands[1].reg << 16;
9201 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9202 inst.instruction |= inst.operands[1].imm;
9205 encode_arm_cp_address (1, TRUE, FALSE, 0);
9209 do_iwmmxt_wshufh (void)
9211 inst.instruction |= inst.operands[0].reg << 12;
9212 inst.instruction |= inst.operands[1].reg << 16;
9213 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9214 inst.instruction |= (inst.operands[2].imm & 0x0f);
9218 do_iwmmxt_wzero (void)
9220 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9221 inst.instruction |= inst.operands[0].reg;
9222 inst.instruction |= inst.operands[0].reg << 12;
9223 inst.instruction |= inst.operands[0].reg << 16;
9227 do_iwmmxt_wrwrwr_or_imm5 (void)
9229 if (inst.operands[2].isreg)
9232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9233 _("immediate operand requires iWMMXt2"));
9235 if (inst.operands[2].imm == 0)
9237 switch ((inst.instruction >> 20) & 0xf)
9243 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9244 inst.operands[2].imm = 16;
9245 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9251 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9252 inst.operands[2].imm = 32;
9253 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9260 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9262 wrn = (inst.instruction >> 16) & 0xf;
9263 inst.instruction &= 0xff0fff0f;
9264 inst.instruction |= wrn;
9265 /* Bail out here; the instruction is now assembled. */
9270 /* Map 32 -> 0, etc. */
9271 inst.operands[2].imm &= 0x1f;
9272 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9276 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9277 operations first, then control, shift, and load/store. */
9279 /* Insns like "foo X,Y,Z". */
9282 do_mav_triple (void)
9284 inst.instruction |= inst.operands[0].reg << 16;
9285 inst.instruction |= inst.operands[1].reg;
9286 inst.instruction |= inst.operands[2].reg << 12;
9289 /* Insns like "foo W,X,Y,Z".
9290 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9295 inst.instruction |= inst.operands[0].reg << 5;
9296 inst.instruction |= inst.operands[1].reg << 12;
9297 inst.instruction |= inst.operands[2].reg << 16;
9298 inst.instruction |= inst.operands[3].reg;
9301 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9305 inst.instruction |= inst.operands[1].reg << 12;
9308 /* Maverick shift immediate instructions.
9309 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9310 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9315 int imm = inst.operands[2].imm;
9317 inst.instruction |= inst.operands[0].reg << 12;
9318 inst.instruction |= inst.operands[1].reg << 16;
9320 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9321 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9322 Bit 4 should be 0. */
9323 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9325 inst.instruction |= imm;
9328 /* XScale instructions. Also sorted arithmetic before move. */
9330 /* Xscale multiply-accumulate (argument parse)
9333 MIAxycc acc0,Rm,Rs. */
9338 inst.instruction |= inst.operands[1].reg;
9339 inst.instruction |= inst.operands[2].reg << 12;
9342 /* Xscale move-accumulator-register (argument parse)
9344 MARcc acc0,RdLo,RdHi. */
9349 inst.instruction |= inst.operands[1].reg << 12;
9350 inst.instruction |= inst.operands[2].reg << 16;
9353 /* Xscale move-register-accumulator (argument parse)
9355 MRAcc RdLo,RdHi,acc0. */
9360 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9361 inst.instruction |= inst.operands[0].reg << 12;
9362 inst.instruction |= inst.operands[1].reg << 16;
9365 /* Encoding functions relevant only to Thumb. */
9367 /* inst.operands[i] is a shifted-register operand; encode
9368 it into inst.instruction in the format used by Thumb32. */
9371 encode_thumb32_shifted_operand (int i)
9373 unsigned int value = inst.reloc.exp.X_add_number;
9374 unsigned int shift = inst.operands[i].shift_kind;
9376 constraint (inst.operands[i].immisreg,
9377 _("shift by register not allowed in thumb mode"));
9378 inst.instruction |= inst.operands[i].reg;
9379 if (shift == SHIFT_RRX)
9380 inst.instruction |= SHIFT_ROR << 4;
9383 constraint (inst.reloc.exp.X_op != O_constant,
9384 _("expression too complex"));
9386 constraint (value > 32
9387 || (value == 32 && (shift == SHIFT_LSL
9388 || shift == SHIFT_ROR)),
9389 _("shift expression is too large"));
9393 else if (value == 32)
9396 inst.instruction |= shift << 4;
9397 inst.instruction |= (value & 0x1c) << 10;
9398 inst.instruction |= (value & 0x03) << 6;
9403 /* inst.operands[i] was set up by parse_address. Encode it into a
9404 Thumb32 format load or store instruction. Reject forms that cannot
9405 be used with such instructions. If is_t is true, reject forms that
9406 cannot be used with a T instruction; if is_d is true, reject forms
9407 that cannot be used with a D instruction. If it is a store insn,
9411 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9413 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9415 constraint (!inst.operands[i].isreg,
9416 _("Instruction does not support =N addresses"));
9418 inst.instruction |= inst.operands[i].reg << 16;
9419 if (inst.operands[i].immisreg)
9421 constraint (is_pc, BAD_PC_ADDRESSING);
9422 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9423 constraint (inst.operands[i].negative,
9424 _("Thumb does not support negative register indexing"));
9425 constraint (inst.operands[i].postind,
9426 _("Thumb does not support register post-indexing"));
9427 constraint (inst.operands[i].writeback,
9428 _("Thumb does not support register indexing with writeback"));
9429 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9430 _("Thumb supports only LSL in shifted register indexing"));
9432 inst.instruction |= inst.operands[i].imm;
9433 if (inst.operands[i].shifted)
9435 constraint (inst.reloc.exp.X_op != O_constant,
9436 _("expression too complex"));
9437 constraint (inst.reloc.exp.X_add_number < 0
9438 || inst.reloc.exp.X_add_number > 3,
9439 _("shift out of range"));
9440 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9442 inst.reloc.type = BFD_RELOC_UNUSED;
9444 else if (inst.operands[i].preind)
9446 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9447 constraint (is_t && inst.operands[i].writeback,
9448 _("cannot use writeback with this instruction"));
9449 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9454 inst.instruction |= 0x01000000;
9455 if (inst.operands[i].writeback)
9456 inst.instruction |= 0x00200000;
9460 inst.instruction |= 0x00000c00;
9461 if (inst.operands[i].writeback)
9462 inst.instruction |= 0x00000100;
9464 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9466 else if (inst.operands[i].postind)
9468 gas_assert (inst.operands[i].writeback);
9469 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9470 constraint (is_t, _("cannot use post-indexing with this instruction"));
9473 inst.instruction |= 0x00200000;
9475 inst.instruction |= 0x00000900;
9476 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9478 else /* unindexed - only for coprocessor */
9479 inst.error = _("instruction does not accept unindexed addressing");
9482 /* Table of Thumb instructions which exist in both 16- and 32-bit
9483 encodings (the latter only in post-V6T2 cores). The index is the
9484 value used in the insns table below. When there is more than one
9485 possible 16-bit encoding for the instruction, this table always
9487 Also contains several pseudo-instructions used during relaxation. */
9488 #define T16_32_TAB \
9489 X(_adc, 4140, eb400000), \
9490 X(_adcs, 4140, eb500000), \
9491 X(_add, 1c00, eb000000), \
9492 X(_adds, 1c00, eb100000), \
9493 X(_addi, 0000, f1000000), \
9494 X(_addis, 0000, f1100000), \
9495 X(_add_pc,000f, f20f0000), \
9496 X(_add_sp,000d, f10d0000), \
9497 X(_adr, 000f, f20f0000), \
9498 X(_and, 4000, ea000000), \
9499 X(_ands, 4000, ea100000), \
9500 X(_asr, 1000, fa40f000), \
9501 X(_asrs, 1000, fa50f000), \
9502 X(_b, e000, f000b000), \
9503 X(_bcond, d000, f0008000), \
9504 X(_bic, 4380, ea200000), \
9505 X(_bics, 4380, ea300000), \
9506 X(_cmn, 42c0, eb100f00), \
9507 X(_cmp, 2800, ebb00f00), \
9508 X(_cpsie, b660, f3af8400), \
9509 X(_cpsid, b670, f3af8600), \
9510 X(_cpy, 4600, ea4f0000), \
9511 X(_dec_sp,80dd, f1ad0d00), \
9512 X(_eor, 4040, ea800000), \
9513 X(_eors, 4040, ea900000), \
9514 X(_inc_sp,00dd, f10d0d00), \
9515 X(_ldmia, c800, e8900000), \
9516 X(_ldr, 6800, f8500000), \
9517 X(_ldrb, 7800, f8100000), \
9518 X(_ldrh, 8800, f8300000), \
9519 X(_ldrsb, 5600, f9100000), \
9520 X(_ldrsh, 5e00, f9300000), \
9521 X(_ldr_pc,4800, f85f0000), \
9522 X(_ldr_pc2,4800, f85f0000), \
9523 X(_ldr_sp,9800, f85d0000), \
9524 X(_lsl, 0000, fa00f000), \
9525 X(_lsls, 0000, fa10f000), \
9526 X(_lsr, 0800, fa20f000), \
9527 X(_lsrs, 0800, fa30f000), \
9528 X(_mov, 2000, ea4f0000), \
9529 X(_movs, 2000, ea5f0000), \
9530 X(_mul, 4340, fb00f000), \
9531 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9532 X(_mvn, 43c0, ea6f0000), \
9533 X(_mvns, 43c0, ea7f0000), \
9534 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9535 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9536 X(_orr, 4300, ea400000), \
9537 X(_orrs, 4300, ea500000), \
9538 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9539 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9540 X(_rev, ba00, fa90f080), \
9541 X(_rev16, ba40, fa90f090), \
9542 X(_revsh, bac0, fa90f0b0), \
9543 X(_ror, 41c0, fa60f000), \
9544 X(_rors, 41c0, fa70f000), \
9545 X(_sbc, 4180, eb600000), \
9546 X(_sbcs, 4180, eb700000), \
9547 X(_stmia, c000, e8800000), \
9548 X(_str, 6000, f8400000), \
9549 X(_strb, 7000, f8000000), \
9550 X(_strh, 8000, f8200000), \
9551 X(_str_sp,9000, f84d0000), \
9552 X(_sub, 1e00, eba00000), \
9553 X(_subs, 1e00, ebb00000), \
9554 X(_subi, 8000, f1a00000), \
9555 X(_subis, 8000, f1b00000), \
9556 X(_sxtb, b240, fa4ff080), \
9557 X(_sxth, b200, fa0ff080), \
9558 X(_tst, 4200, ea100f00), \
9559 X(_uxtb, b2c0, fa5ff080), \
9560 X(_uxth, b280, fa1ff080), \
9561 X(_nop, bf00, f3af8000), \
9562 X(_yield, bf10, f3af8001), \
9563 X(_wfe, bf20, f3af8002), \
9564 X(_wfi, bf30, f3af8003), \
9565 X(_sev, bf40, f3af8004), \
9566 X(_sevl, bf50, f3af8005)
9568 /* To catch errors in encoding functions, the codes are all offset by
9569 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9570 as 16-bit instructions. */
9571 #define X(a,b,c) T_MNEM##a
9572 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9575 #define X(a,b,c) 0x##b
9576 static const unsigned short thumb_op16[] = { T16_32_TAB };
9577 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9580 #define X(a,b,c) 0x##c
9581 static const unsigned int thumb_op32[] = { T16_32_TAB };
9582 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9583 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9587 /* Thumb instruction encoders, in alphabetical order. */
9592 do_t_add_sub_w (void)
9596 Rd = inst.operands[0].reg;
9597 Rn = inst.operands[1].reg;
9599 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9600 is the SP-{plus,minus}-immediate form of the instruction. */
9602 constraint (Rd == REG_PC, BAD_PC);
9604 reject_bad_reg (Rd);
9606 inst.instruction |= (Rn << 16) | (Rd << 8);
9607 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9610 /* Parse an add or subtract instruction. We get here with inst.instruction
9611 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9618 Rd = inst.operands[0].reg;
9619 Rs = (inst.operands[1].present
9620 ? inst.operands[1].reg /* Rd, Rs, foo */
9621 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9624 set_it_insn_type_last ();
9632 flags = (inst.instruction == T_MNEM_adds
9633 || inst.instruction == T_MNEM_subs);
9635 narrow = !in_it_block ();
9637 narrow = in_it_block ();
9638 if (!inst.operands[2].isreg)
9642 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9644 add = (inst.instruction == T_MNEM_add
9645 || inst.instruction == T_MNEM_adds);
9647 if (inst.size_req != 4)
9649 /* Attempt to use a narrow opcode, with relaxation if
9651 if (Rd == REG_SP && Rs == REG_SP && !flags)
9652 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9653 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9654 opcode = T_MNEM_add_sp;
9655 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9656 opcode = T_MNEM_add_pc;
9657 else if (Rd <= 7 && Rs <= 7 && narrow)
9660 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9662 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9666 inst.instruction = THUMB_OP16(opcode);
9667 inst.instruction |= (Rd << 4) | Rs;
9668 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9669 if (inst.size_req != 2)
9670 inst.relax = opcode;
9673 constraint (inst.size_req == 2, BAD_HIREG);
9675 if (inst.size_req == 4
9676 || (inst.size_req != 2 && !opcode))
9680 constraint (add, BAD_PC);
9681 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9682 _("only SUBS PC, LR, #const allowed"));
9683 constraint (inst.reloc.exp.X_op != O_constant,
9684 _("expression too complex"));
9685 constraint (inst.reloc.exp.X_add_number < 0
9686 || inst.reloc.exp.X_add_number > 0xff,
9687 _("immediate value out of range"));
9688 inst.instruction = T2_SUBS_PC_LR
9689 | inst.reloc.exp.X_add_number;
9690 inst.reloc.type = BFD_RELOC_UNUSED;
9693 else if (Rs == REG_PC)
9695 /* Always use addw/subw. */
9696 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9697 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9701 inst.instruction = THUMB_OP32 (inst.instruction);
9702 inst.instruction = (inst.instruction & 0xe1ffffff)
9705 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9707 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9709 inst.instruction |= Rd << 8;
9710 inst.instruction |= Rs << 16;
9715 unsigned int value = inst.reloc.exp.X_add_number;
9716 unsigned int shift = inst.operands[2].shift_kind;
9718 Rn = inst.operands[2].reg;
9719 /* See if we can do this with a 16-bit instruction. */
9720 if (!inst.operands[2].shifted && inst.size_req != 4)
9722 if (Rd > 7 || Rs > 7 || Rn > 7)
9727 inst.instruction = ((inst.instruction == T_MNEM_adds
9728 || inst.instruction == T_MNEM_add)
9731 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9735 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9737 /* Thumb-1 cores (except v6-M) require at least one high
9738 register in a narrow non flag setting add. */
9739 if (Rd > 7 || Rn > 7
9740 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9741 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9748 inst.instruction = T_OPCODE_ADD_HI;
9749 inst.instruction |= (Rd & 8) << 4;
9750 inst.instruction |= (Rd & 7);
9751 inst.instruction |= Rn << 3;
9757 constraint (Rd == REG_PC, BAD_PC);
9758 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9759 constraint (Rs == REG_PC, BAD_PC);
9760 reject_bad_reg (Rn);
9762 /* If we get here, it can't be done in 16 bits. */
9763 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9764 _("shift must be constant"));
9765 inst.instruction = THUMB_OP32 (inst.instruction);
9766 inst.instruction |= Rd << 8;
9767 inst.instruction |= Rs << 16;
9768 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9769 _("shift value over 3 not allowed in thumb mode"));
9770 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9771 _("only LSL shift allowed in thumb mode"));
9772 encode_thumb32_shifted_operand (2);
9777 constraint (inst.instruction == T_MNEM_adds
9778 || inst.instruction == T_MNEM_subs,
9781 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9783 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9784 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9787 inst.instruction = (inst.instruction == T_MNEM_add
9789 inst.instruction |= (Rd << 4) | Rs;
9790 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9794 Rn = inst.operands[2].reg;
9795 constraint (inst.operands[2].shifted, _("unshifted register required"));
9797 /* We now have Rd, Rs, and Rn set to registers. */
9798 if (Rd > 7 || Rs > 7 || Rn > 7)
9800 /* Can't do this for SUB. */
9801 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9802 inst.instruction = T_OPCODE_ADD_HI;
9803 inst.instruction |= (Rd & 8) << 4;
9804 inst.instruction |= (Rd & 7);
9806 inst.instruction |= Rn << 3;
9808 inst.instruction |= Rs << 3;
9810 constraint (1, _("dest must overlap one source register"));
9814 inst.instruction = (inst.instruction == T_MNEM_add
9815 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9816 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9826 Rd = inst.operands[0].reg;
9827 reject_bad_reg (Rd);
9829 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9831 /* Defer to section relaxation. */
9832 inst.relax = inst.instruction;
9833 inst.instruction = THUMB_OP16 (inst.instruction);
9834 inst.instruction |= Rd << 4;
9836 else if (unified_syntax && inst.size_req != 2)
9838 /* Generate a 32-bit opcode. */
9839 inst.instruction = THUMB_OP32 (inst.instruction);
9840 inst.instruction |= Rd << 8;
9841 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9842 inst.reloc.pc_rel = 1;
9846 /* Generate a 16-bit opcode. */
9847 inst.instruction = THUMB_OP16 (inst.instruction);
9848 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9849 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9850 inst.reloc.pc_rel = 1;
9852 inst.instruction |= Rd << 4;
9856 /* Arithmetic instructions for which there is just one 16-bit
9857 instruction encoding, and it allows only two low registers.
9858 For maximal compatibility with ARM syntax, we allow three register
9859 operands even when Thumb-32 instructions are not available, as long
9860 as the first two are identical. For instance, both "sbc r0,r1" and
9861 "sbc r0,r0,r1" are allowed. */
9867 Rd = inst.operands[0].reg;
9868 Rs = (inst.operands[1].present
9869 ? inst.operands[1].reg /* Rd, Rs, foo */
9870 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9871 Rn = inst.operands[2].reg;
9873 reject_bad_reg (Rd);
9874 reject_bad_reg (Rs);
9875 if (inst.operands[2].isreg)
9876 reject_bad_reg (Rn);
9880 if (!inst.operands[2].isreg)
9882 /* For an immediate, we always generate a 32-bit opcode;
9883 section relaxation will shrink it later if possible. */
9884 inst.instruction = THUMB_OP32 (inst.instruction);
9885 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9886 inst.instruction |= Rd << 8;
9887 inst.instruction |= Rs << 16;
9888 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9894 /* See if we can do this with a 16-bit instruction. */
9895 if (THUMB_SETS_FLAGS (inst.instruction))
9896 narrow = !in_it_block ();
9898 narrow = in_it_block ();
9900 if (Rd > 7 || Rn > 7 || Rs > 7)
9902 if (inst.operands[2].shifted)
9904 if (inst.size_req == 4)
9910 inst.instruction = THUMB_OP16 (inst.instruction);
9911 inst.instruction |= Rd;
9912 inst.instruction |= Rn << 3;
9916 /* If we get here, it can't be done in 16 bits. */
9917 constraint (inst.operands[2].shifted
9918 && inst.operands[2].immisreg,
9919 _("shift must be constant"));
9920 inst.instruction = THUMB_OP32 (inst.instruction);
9921 inst.instruction |= Rd << 8;
9922 inst.instruction |= Rs << 16;
9923 encode_thumb32_shifted_operand (2);
9928 /* On its face this is a lie - the instruction does set the
9929 flags. However, the only supported mnemonic in this mode
9931 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9933 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9934 _("unshifted register required"));
9935 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9936 constraint (Rd != Rs,
9937 _("dest and source1 must be the same register"));
9939 inst.instruction = THUMB_OP16 (inst.instruction);
9940 inst.instruction |= Rd;
9941 inst.instruction |= Rn << 3;
9945 /* Similarly, but for instructions where the arithmetic operation is
9946 commutative, so we can allow either of them to be different from
9947 the destination operand in a 16-bit instruction. For instance, all
9948 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9955 Rd = inst.operands[0].reg;
9956 Rs = (inst.operands[1].present
9957 ? inst.operands[1].reg /* Rd, Rs, foo */
9958 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9959 Rn = inst.operands[2].reg;
9961 reject_bad_reg (Rd);
9962 reject_bad_reg (Rs);
9963 if (inst.operands[2].isreg)
9964 reject_bad_reg (Rn);
9968 if (!inst.operands[2].isreg)
9970 /* For an immediate, we always generate a 32-bit opcode;
9971 section relaxation will shrink it later if possible. */
9972 inst.instruction = THUMB_OP32 (inst.instruction);
9973 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9974 inst.instruction |= Rd << 8;
9975 inst.instruction |= Rs << 16;
9976 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9982 /* See if we can do this with a 16-bit instruction. */
9983 if (THUMB_SETS_FLAGS (inst.instruction))
9984 narrow = !in_it_block ();
9986 narrow = in_it_block ();
9988 if (Rd > 7 || Rn > 7 || Rs > 7)
9990 if (inst.operands[2].shifted)
9992 if (inst.size_req == 4)
9999 inst.instruction = THUMB_OP16 (inst.instruction);
10000 inst.instruction |= Rd;
10001 inst.instruction |= Rn << 3;
10006 inst.instruction = THUMB_OP16 (inst.instruction);
10007 inst.instruction |= Rd;
10008 inst.instruction |= Rs << 3;
10013 /* If we get here, it can't be done in 16 bits. */
10014 constraint (inst.operands[2].shifted
10015 && inst.operands[2].immisreg,
10016 _("shift must be constant"));
10017 inst.instruction = THUMB_OP32 (inst.instruction);
10018 inst.instruction |= Rd << 8;
10019 inst.instruction |= Rs << 16;
10020 encode_thumb32_shifted_operand (2);
10025 /* On its face this is a lie - the instruction does set the
10026 flags. However, the only supported mnemonic in this mode
10027 says it doesn't. */
10028 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10030 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10031 _("unshifted register required"));
10032 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10034 inst.instruction = THUMB_OP16 (inst.instruction);
10035 inst.instruction |= Rd;
10038 inst.instruction |= Rn << 3;
10040 inst.instruction |= Rs << 3;
10042 constraint (1, _("dest must overlap one source register"));
10050 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10051 constraint (msb > 32, _("bit-field extends past end of register"));
10052 /* The instruction encoding stores the LSB and MSB,
10053 not the LSB and width. */
10054 Rd = inst.operands[0].reg;
10055 reject_bad_reg (Rd);
10056 inst.instruction |= Rd << 8;
10057 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10058 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10059 inst.instruction |= msb - 1;
10068 Rd = inst.operands[0].reg;
10069 reject_bad_reg (Rd);
10071 /* #0 in second position is alternative syntax for bfc, which is
10072 the same instruction but with REG_PC in the Rm field. */
10073 if (!inst.operands[1].isreg)
10077 Rn = inst.operands[1].reg;
10078 reject_bad_reg (Rn);
10081 msb = inst.operands[2].imm + inst.operands[3].imm;
10082 constraint (msb > 32, _("bit-field extends past end of register"));
10083 /* The instruction encoding stores the LSB and MSB,
10084 not the LSB and width. */
10085 inst.instruction |= Rd << 8;
10086 inst.instruction |= Rn << 16;
10087 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10088 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10089 inst.instruction |= msb - 1;
10097 Rd = inst.operands[0].reg;
10098 Rn = inst.operands[1].reg;
10100 reject_bad_reg (Rd);
10101 reject_bad_reg (Rn);
10103 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10104 _("bit-field extends past end of register"));
10105 inst.instruction |= Rd << 8;
10106 inst.instruction |= Rn << 16;
10107 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10108 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10109 inst.instruction |= inst.operands[3].imm - 1;
10112 /* ARM V5 Thumb BLX (argument parse)
10113 BLX <target_addr> which is BLX(1)
10114 BLX <Rm> which is BLX(2)
10115 Unfortunately, there are two different opcodes for this mnemonic.
10116 So, the insns[].value is not used, and the code here zaps values
10117 into inst.instruction.
10119 ??? How to take advantage of the additional two bits of displacement
10120 available in Thumb32 mode? Need new relocation? */
10125 set_it_insn_type_last ();
10127 if (inst.operands[0].isreg)
10129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10130 /* We have a register, so this is BLX(2). */
10131 inst.instruction |= inst.operands[0].reg << 3;
10135 /* No register. This must be BLX(1). */
10136 inst.instruction = 0xf000e800;
10137 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10149 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10151 if (in_it_block ())
10153 /* Conditional branches inside IT blocks are encoded as unconditional
10155 cond = COND_ALWAYS;
10160 if (cond != COND_ALWAYS)
10161 opcode = T_MNEM_bcond;
10163 opcode = inst.instruction;
10166 && (inst.size_req == 4
10167 || (inst.size_req != 2
10168 && (inst.operands[0].hasreloc
10169 || inst.reloc.exp.X_op == O_constant))))
10171 inst.instruction = THUMB_OP32(opcode);
10172 if (cond == COND_ALWAYS)
10173 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10176 gas_assert (cond != 0xF);
10177 inst.instruction |= cond << 22;
10178 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10183 inst.instruction = THUMB_OP16(opcode);
10184 if (cond == COND_ALWAYS)
10185 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10188 inst.instruction |= cond << 8;
10189 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10191 /* Allow section relaxation. */
10192 if (unified_syntax && inst.size_req != 2)
10193 inst.relax = opcode;
10195 inst.reloc.type = reloc;
10196 inst.reloc.pc_rel = 1;
10199 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10200 between the two is the maximum immediate allowed - which is passed in
10203 do_t_bkpt_hlt1 (int range)
10205 constraint (inst.cond != COND_ALWAYS,
10206 _("instruction is always unconditional"));
10207 if (inst.operands[0].present)
10209 constraint (inst.operands[0].imm > range,
10210 _("immediate value out of range"));
10211 inst.instruction |= inst.operands[0].imm;
10214 set_it_insn_type (NEUTRAL_IT_INSN);
10220 do_t_bkpt_hlt1 (63);
10226 do_t_bkpt_hlt1 (255);
10230 do_t_branch23 (void)
10232 set_it_insn_type_last ();
10233 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10235 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10236 this file. We used to simply ignore the PLT reloc type here --
10237 the branch encoding is now needed to deal with TLSCALL relocs.
10238 So if we see a PLT reloc now, put it back to how it used to be to
10239 keep the preexisting behaviour. */
10240 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10241 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10243 #if defined(OBJ_COFF)
10244 /* If the destination of the branch is a defined symbol which does not have
10245 the THUMB_FUNC attribute, then we must be calling a function which has
10246 the (interfacearm) attribute. We look for the Thumb entry point to that
10247 function and change the branch to refer to that function instead. */
10248 if ( inst.reloc.exp.X_op == O_symbol
10249 && inst.reloc.exp.X_add_symbol != NULL
10250 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10251 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10252 inst.reloc.exp.X_add_symbol =
10253 find_real_start (inst.reloc.exp.X_add_symbol);
10260 set_it_insn_type_last ();
10261 inst.instruction |= inst.operands[0].reg << 3;
10262 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10263 should cause the alignment to be checked once it is known. This is
10264 because BX PC only works if the instruction is word aligned. */
10272 set_it_insn_type_last ();
10273 Rm = inst.operands[0].reg;
10274 reject_bad_reg (Rm);
10275 inst.instruction |= Rm << 16;
10284 Rd = inst.operands[0].reg;
10285 Rm = inst.operands[1].reg;
10287 reject_bad_reg (Rd);
10288 reject_bad_reg (Rm);
10290 inst.instruction |= Rd << 8;
10291 inst.instruction |= Rm << 16;
10292 inst.instruction |= Rm;
10298 set_it_insn_type (OUTSIDE_IT_INSN);
10299 inst.instruction |= inst.operands[0].imm;
10305 set_it_insn_type (OUTSIDE_IT_INSN);
10307 && (inst.operands[1].present || inst.size_req == 4)
10308 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10310 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10311 inst.instruction = 0xf3af8000;
10312 inst.instruction |= imod << 9;
10313 inst.instruction |= inst.operands[0].imm << 5;
10314 if (inst.operands[1].present)
10315 inst.instruction |= 0x100 | inst.operands[1].imm;
10319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10320 && (inst.operands[0].imm & 4),
10321 _("selected processor does not support 'A' form "
10322 "of this instruction"));
10323 constraint (inst.operands[1].present || inst.size_req == 4,
10324 _("Thumb does not support the 2-argument "
10325 "form of this instruction"));
10326 inst.instruction |= inst.operands[0].imm;
10330 /* THUMB CPY instruction (argument parse). */
10335 if (inst.size_req == 4)
10337 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10338 inst.instruction |= inst.operands[0].reg << 8;
10339 inst.instruction |= inst.operands[1].reg;
10343 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10344 inst.instruction |= (inst.operands[0].reg & 0x7);
10345 inst.instruction |= inst.operands[1].reg << 3;
10352 set_it_insn_type (OUTSIDE_IT_INSN);
10353 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10354 inst.instruction |= inst.operands[0].reg;
10355 inst.reloc.pc_rel = 1;
10356 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10362 inst.instruction |= inst.operands[0].imm;
10368 unsigned Rd, Rn, Rm;
10370 Rd = inst.operands[0].reg;
10371 Rn = (inst.operands[1].present
10372 ? inst.operands[1].reg : Rd);
10373 Rm = inst.operands[2].reg;
10375 reject_bad_reg (Rd);
10376 reject_bad_reg (Rn);
10377 reject_bad_reg (Rm);
10379 inst.instruction |= Rd << 8;
10380 inst.instruction |= Rn << 16;
10381 inst.instruction |= Rm;
10387 if (unified_syntax && inst.size_req == 4)
10388 inst.instruction = THUMB_OP32 (inst.instruction);
10390 inst.instruction = THUMB_OP16 (inst.instruction);
10396 unsigned int cond = inst.operands[0].imm;
10398 set_it_insn_type (IT_INSN);
10399 now_it.mask = (inst.instruction & 0xf) | 0x10;
10401 now_it.warn_deprecated = FALSE;
10403 /* If the condition is a negative condition, invert the mask. */
10404 if ((cond & 0x1) == 0x0)
10406 unsigned int mask = inst.instruction & 0x000f;
10408 if ((mask & 0x7) == 0)
10410 /* No conversion needed. */
10411 now_it.block_length = 1;
10413 else if ((mask & 0x3) == 0)
10416 now_it.block_length = 2;
10418 else if ((mask & 0x1) == 0)
10421 now_it.block_length = 3;
10426 now_it.block_length = 4;
10429 inst.instruction &= 0xfff0;
10430 inst.instruction |= mask;
10433 inst.instruction |= cond << 4;
10436 /* Helper function used for both push/pop and ldm/stm. */
10438 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10442 load = (inst.instruction & (1 << 20)) != 0;
10444 if (mask & (1 << 13))
10445 inst.error = _("SP not allowed in register list");
10447 if ((mask & (1 << base)) != 0
10449 inst.error = _("having the base register in the register list when "
10450 "using write back is UNPREDICTABLE");
10454 if (mask & (1 << 15))
10456 if (mask & (1 << 14))
10457 inst.error = _("LR and PC should not both be in register list");
10459 set_it_insn_type_last ();
10464 if (mask & (1 << 15))
10465 inst.error = _("PC not allowed in register list");
10468 if ((mask & (mask - 1)) == 0)
10470 /* Single register transfers implemented as str/ldr. */
10473 if (inst.instruction & (1 << 23))
10474 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10476 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10480 if (inst.instruction & (1 << 23))
10481 inst.instruction = 0x00800000; /* ia -> [base] */
10483 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10486 inst.instruction |= 0xf8400000;
10488 inst.instruction |= 0x00100000;
10490 mask = ffs (mask) - 1;
10493 else if (writeback)
10494 inst.instruction |= WRITE_BACK;
10496 inst.instruction |= mask;
10497 inst.instruction |= base << 16;
10503 /* This really doesn't seem worth it. */
10504 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10505 _("expression too complex"));
10506 constraint (inst.operands[1].writeback,
10507 _("Thumb load/store multiple does not support {reglist}^"));
10509 if (unified_syntax)
10511 bfd_boolean narrow;
10515 /* See if we can use a 16-bit instruction. */
10516 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10517 && inst.size_req != 4
10518 && !(inst.operands[1].imm & ~0xff))
10520 mask = 1 << inst.operands[0].reg;
10522 if (inst.operands[0].reg <= 7)
10524 if (inst.instruction == T_MNEM_stmia
10525 ? inst.operands[0].writeback
10526 : (inst.operands[0].writeback
10527 == !(inst.operands[1].imm & mask)))
10529 if (inst.instruction == T_MNEM_stmia
10530 && (inst.operands[1].imm & mask)
10531 && (inst.operands[1].imm & (mask - 1)))
10532 as_warn (_("value stored for r%d is UNKNOWN"),
10533 inst.operands[0].reg);
10535 inst.instruction = THUMB_OP16 (inst.instruction);
10536 inst.instruction |= inst.operands[0].reg << 8;
10537 inst.instruction |= inst.operands[1].imm;
10540 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10542 /* This means 1 register in reg list one of 3 situations:
10543 1. Instruction is stmia, but without writeback.
10544 2. lmdia without writeback, but with Rn not in
10546 3. ldmia with writeback, but with Rn in reglist.
10547 Case 3 is UNPREDICTABLE behaviour, so we handle
10548 case 1 and 2 which can be converted into a 16-bit
10549 str or ldr. The SP cases are handled below. */
10550 unsigned long opcode;
10551 /* First, record an error for Case 3. */
10552 if (inst.operands[1].imm & mask
10553 && inst.operands[0].writeback)
10555 _("having the base register in the register list when "
10556 "using write back is UNPREDICTABLE");
10558 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10560 inst.instruction = THUMB_OP16 (opcode);
10561 inst.instruction |= inst.operands[0].reg << 3;
10562 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10566 else if (inst.operands[0] .reg == REG_SP)
10568 if (inst.operands[0].writeback)
10571 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10572 ? T_MNEM_push : T_MNEM_pop);
10573 inst.instruction |= inst.operands[1].imm;
10576 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10579 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10580 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10581 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10589 if (inst.instruction < 0xffff)
10590 inst.instruction = THUMB_OP32 (inst.instruction);
10592 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10593 inst.operands[0].writeback);
10598 constraint (inst.operands[0].reg > 7
10599 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10600 constraint (inst.instruction != T_MNEM_ldmia
10601 && inst.instruction != T_MNEM_stmia,
10602 _("Thumb-2 instruction only valid in unified syntax"));
10603 if (inst.instruction == T_MNEM_stmia)
10605 if (!inst.operands[0].writeback)
10606 as_warn (_("this instruction will write back the base register"));
10607 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10608 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10609 as_warn (_("value stored for r%d is UNKNOWN"),
10610 inst.operands[0].reg);
10614 if (!inst.operands[0].writeback
10615 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10616 as_warn (_("this instruction will write back the base register"));
10617 else if (inst.operands[0].writeback
10618 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10619 as_warn (_("this instruction will not write back the base register"));
10622 inst.instruction = THUMB_OP16 (inst.instruction);
10623 inst.instruction |= inst.operands[0].reg << 8;
10624 inst.instruction |= inst.operands[1].imm;
10631 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10632 || inst.operands[1].postind || inst.operands[1].writeback
10633 || inst.operands[1].immisreg || inst.operands[1].shifted
10634 || inst.operands[1].negative,
10637 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10639 inst.instruction |= inst.operands[0].reg << 12;
10640 inst.instruction |= inst.operands[1].reg << 16;
10641 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10647 if (!inst.operands[1].present)
10649 constraint (inst.operands[0].reg == REG_LR,
10650 _("r14 not allowed as first register "
10651 "when second register is omitted"));
10652 inst.operands[1].reg = inst.operands[0].reg + 1;
10654 constraint (inst.operands[0].reg == inst.operands[1].reg,
10657 inst.instruction |= inst.operands[0].reg << 12;
10658 inst.instruction |= inst.operands[1].reg << 8;
10659 inst.instruction |= inst.operands[2].reg << 16;
10665 unsigned long opcode;
10668 if (inst.operands[0].isreg
10669 && !inst.operands[0].preind
10670 && inst.operands[0].reg == REG_PC)
10671 set_it_insn_type_last ();
10673 opcode = inst.instruction;
10674 if (unified_syntax)
10676 if (!inst.operands[1].isreg)
10678 if (opcode <= 0xffff)
10679 inst.instruction = THUMB_OP32 (opcode);
10680 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10683 if (inst.operands[1].isreg
10684 && !inst.operands[1].writeback
10685 && !inst.operands[1].shifted && !inst.operands[1].postind
10686 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10687 && opcode <= 0xffff
10688 && inst.size_req != 4)
10690 /* Insn may have a 16-bit form. */
10691 Rn = inst.operands[1].reg;
10692 if (inst.operands[1].immisreg)
10694 inst.instruction = THUMB_OP16 (opcode);
10696 if (Rn <= 7 && inst.operands[1].imm <= 7)
10698 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10699 reject_bad_reg (inst.operands[1].imm);
10701 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10702 && opcode != T_MNEM_ldrsb)
10703 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10704 || (Rn == REG_SP && opcode == T_MNEM_str))
10711 if (inst.reloc.pc_rel)
10712 opcode = T_MNEM_ldr_pc2;
10714 opcode = T_MNEM_ldr_pc;
10718 if (opcode == T_MNEM_ldr)
10719 opcode = T_MNEM_ldr_sp;
10721 opcode = T_MNEM_str_sp;
10723 inst.instruction = inst.operands[0].reg << 8;
10727 inst.instruction = inst.operands[0].reg;
10728 inst.instruction |= inst.operands[1].reg << 3;
10730 inst.instruction |= THUMB_OP16 (opcode);
10731 if (inst.size_req == 2)
10732 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10734 inst.relax = opcode;
10738 /* Definitely a 32-bit variant. */
10740 /* Warning for Erratum 752419. */
10741 if (opcode == T_MNEM_ldr
10742 && inst.operands[0].reg == REG_SP
10743 && inst.operands[1].writeback == 1
10744 && !inst.operands[1].immisreg)
10746 if (no_cpu_selected ()
10747 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10748 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10749 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10750 as_warn (_("This instruction may be unpredictable "
10751 "if executed on M-profile cores "
10752 "with interrupts enabled."));
10755 /* Do some validations regarding addressing modes. */
10756 if (inst.operands[1].immisreg)
10757 reject_bad_reg (inst.operands[1].imm);
10759 constraint (inst.operands[1].writeback == 1
10760 && inst.operands[0].reg == inst.operands[1].reg,
10763 inst.instruction = THUMB_OP32 (opcode);
10764 inst.instruction |= inst.operands[0].reg << 12;
10765 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10766 check_ldr_r15_aligned ();
10770 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10772 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10774 /* Only [Rn,Rm] is acceptable. */
10775 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10776 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10777 || inst.operands[1].postind || inst.operands[1].shifted
10778 || inst.operands[1].negative,
10779 _("Thumb does not support this addressing mode"));
10780 inst.instruction = THUMB_OP16 (inst.instruction);
10784 inst.instruction = THUMB_OP16 (inst.instruction);
10785 if (!inst.operands[1].isreg)
10786 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10789 constraint (!inst.operands[1].preind
10790 || inst.operands[1].shifted
10791 || inst.operands[1].writeback,
10792 _("Thumb does not support this addressing mode"));
10793 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10795 constraint (inst.instruction & 0x0600,
10796 _("byte or halfword not valid for base register"));
10797 constraint (inst.operands[1].reg == REG_PC
10798 && !(inst.instruction & THUMB_LOAD_BIT),
10799 _("r15 based store not allowed"));
10800 constraint (inst.operands[1].immisreg,
10801 _("invalid base register for register offset"));
10803 if (inst.operands[1].reg == REG_PC)
10804 inst.instruction = T_OPCODE_LDR_PC;
10805 else if (inst.instruction & THUMB_LOAD_BIT)
10806 inst.instruction = T_OPCODE_LDR_SP;
10808 inst.instruction = T_OPCODE_STR_SP;
10810 inst.instruction |= inst.operands[0].reg << 8;
10811 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10815 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10816 if (!inst.operands[1].immisreg)
10818 /* Immediate offset. */
10819 inst.instruction |= inst.operands[0].reg;
10820 inst.instruction |= inst.operands[1].reg << 3;
10821 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10825 /* Register offset. */
10826 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10827 constraint (inst.operands[1].negative,
10828 _("Thumb does not support this addressing mode"));
10831 switch (inst.instruction)
10833 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10834 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10835 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10836 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10837 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10838 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10839 case 0x5600 /* ldrsb */:
10840 case 0x5e00 /* ldrsh */: break;
10844 inst.instruction |= inst.operands[0].reg;
10845 inst.instruction |= inst.operands[1].reg << 3;
10846 inst.instruction |= inst.operands[1].imm << 6;
10852 if (!inst.operands[1].present)
10854 inst.operands[1].reg = inst.operands[0].reg + 1;
10855 constraint (inst.operands[0].reg == REG_LR,
10856 _("r14 not allowed here"));
10857 constraint (inst.operands[0].reg == REG_R12,
10858 _("r12 not allowed here"));
10861 if (inst.operands[2].writeback
10862 && (inst.operands[0].reg == inst.operands[2].reg
10863 || inst.operands[1].reg == inst.operands[2].reg))
10864 as_warn (_("base register written back, and overlaps "
10865 "one of transfer registers"));
10867 inst.instruction |= inst.operands[0].reg << 12;
10868 inst.instruction |= inst.operands[1].reg << 8;
10869 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10875 inst.instruction |= inst.operands[0].reg << 12;
10876 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10882 unsigned Rd, Rn, Rm, Ra;
10884 Rd = inst.operands[0].reg;
10885 Rn = inst.operands[1].reg;
10886 Rm = inst.operands[2].reg;
10887 Ra = inst.operands[3].reg;
10889 reject_bad_reg (Rd);
10890 reject_bad_reg (Rn);
10891 reject_bad_reg (Rm);
10892 reject_bad_reg (Ra);
10894 inst.instruction |= Rd << 8;
10895 inst.instruction |= Rn << 16;
10896 inst.instruction |= Rm;
10897 inst.instruction |= Ra << 12;
10903 unsigned RdLo, RdHi, Rn, Rm;
10905 RdLo = inst.operands[0].reg;
10906 RdHi = inst.operands[1].reg;
10907 Rn = inst.operands[2].reg;
10908 Rm = inst.operands[3].reg;
10910 reject_bad_reg (RdLo);
10911 reject_bad_reg (RdHi);
10912 reject_bad_reg (Rn);
10913 reject_bad_reg (Rm);
10915 inst.instruction |= RdLo << 12;
10916 inst.instruction |= RdHi << 8;
10917 inst.instruction |= Rn << 16;
10918 inst.instruction |= Rm;
10922 do_t_mov_cmp (void)
10926 Rn = inst.operands[0].reg;
10927 Rm = inst.operands[1].reg;
10930 set_it_insn_type_last ();
10932 if (unified_syntax)
10934 int r0off = (inst.instruction == T_MNEM_mov
10935 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10936 unsigned long opcode;
10937 bfd_boolean narrow;
10938 bfd_boolean low_regs;
10940 low_regs = (Rn <= 7 && Rm <= 7);
10941 opcode = inst.instruction;
10942 if (in_it_block ())
10943 narrow = opcode != T_MNEM_movs;
10945 narrow = opcode != T_MNEM_movs || low_regs;
10946 if (inst.size_req == 4
10947 || inst.operands[1].shifted)
10950 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10951 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10952 && !inst.operands[1].shifted
10956 inst.instruction = T2_SUBS_PC_LR;
10960 if (opcode == T_MNEM_cmp)
10962 constraint (Rn == REG_PC, BAD_PC);
10965 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10967 warn_deprecated_sp (Rm);
10968 /* R15 was documented as a valid choice for Rm in ARMv6,
10969 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10970 tools reject R15, so we do too. */
10971 constraint (Rm == REG_PC, BAD_PC);
10974 reject_bad_reg (Rm);
10976 else if (opcode == T_MNEM_mov
10977 || opcode == T_MNEM_movs)
10979 if (inst.operands[1].isreg)
10981 if (opcode == T_MNEM_movs)
10983 reject_bad_reg (Rn);
10984 reject_bad_reg (Rm);
10988 /* This is mov.n. */
10989 if ((Rn == REG_SP || Rn == REG_PC)
10990 && (Rm == REG_SP || Rm == REG_PC))
10992 as_warn (_("Use of r%u as a source register is "
10993 "deprecated when r%u is the destination "
10994 "register."), Rm, Rn);
10999 /* This is mov.w. */
11000 constraint (Rn == REG_PC, BAD_PC);
11001 constraint (Rm == REG_PC, BAD_PC);
11002 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11006 reject_bad_reg (Rn);
11009 if (!inst.operands[1].isreg)
11011 /* Immediate operand. */
11012 if (!in_it_block () && opcode == T_MNEM_mov)
11014 if (low_regs && narrow)
11016 inst.instruction = THUMB_OP16 (opcode);
11017 inst.instruction |= Rn << 8;
11018 if (inst.size_req == 2)
11019 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11021 inst.relax = opcode;
11025 inst.instruction = THUMB_OP32 (inst.instruction);
11026 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11027 inst.instruction |= Rn << r0off;
11028 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11031 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11032 && (inst.instruction == T_MNEM_mov
11033 || inst.instruction == T_MNEM_movs))
11035 /* Register shifts are encoded as separate shift instructions. */
11036 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11038 if (in_it_block ())
11043 if (inst.size_req == 4)
11046 if (!low_regs || inst.operands[1].imm > 7)
11052 switch (inst.operands[1].shift_kind)
11055 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11058 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11061 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11064 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11070 inst.instruction = opcode;
11073 inst.instruction |= Rn;
11074 inst.instruction |= inst.operands[1].imm << 3;
11079 inst.instruction |= CONDS_BIT;
11081 inst.instruction |= Rn << 8;
11082 inst.instruction |= Rm << 16;
11083 inst.instruction |= inst.operands[1].imm;
11088 /* Some mov with immediate shift have narrow variants.
11089 Register shifts are handled above. */
11090 if (low_regs && inst.operands[1].shifted
11091 && (inst.instruction == T_MNEM_mov
11092 || inst.instruction == T_MNEM_movs))
11094 if (in_it_block ())
11095 narrow = (inst.instruction == T_MNEM_mov);
11097 narrow = (inst.instruction == T_MNEM_movs);
11102 switch (inst.operands[1].shift_kind)
11104 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11105 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11106 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11107 default: narrow = FALSE; break;
11113 inst.instruction |= Rn;
11114 inst.instruction |= Rm << 3;
11115 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11119 inst.instruction = THUMB_OP32 (inst.instruction);
11120 inst.instruction |= Rn << r0off;
11121 encode_thumb32_shifted_operand (1);
11125 switch (inst.instruction)
11128 /* In v4t or v5t a move of two lowregs produces unpredictable
11129 results. Don't allow this. */
11132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11133 "MOV Rd, Rs with two low registers is not "
11134 "permitted on this architecture");
11135 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11139 inst.instruction = T_OPCODE_MOV_HR;
11140 inst.instruction |= (Rn & 0x8) << 4;
11141 inst.instruction |= (Rn & 0x7);
11142 inst.instruction |= Rm << 3;
11146 /* We know we have low registers at this point.
11147 Generate LSLS Rd, Rs, #0. */
11148 inst.instruction = T_OPCODE_LSL_I;
11149 inst.instruction |= Rn;
11150 inst.instruction |= Rm << 3;
11156 inst.instruction = T_OPCODE_CMP_LR;
11157 inst.instruction |= Rn;
11158 inst.instruction |= Rm << 3;
11162 inst.instruction = T_OPCODE_CMP_HR;
11163 inst.instruction |= (Rn & 0x8) << 4;
11164 inst.instruction |= (Rn & 0x7);
11165 inst.instruction |= Rm << 3;
11172 inst.instruction = THUMB_OP16 (inst.instruction);
11174 /* PR 10443: Do not silently ignore shifted operands. */
11175 constraint (inst.operands[1].shifted,
11176 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11178 if (inst.operands[1].isreg)
11180 if (Rn < 8 && Rm < 8)
11182 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11183 since a MOV instruction produces unpredictable results. */
11184 if (inst.instruction == T_OPCODE_MOV_I8)
11185 inst.instruction = T_OPCODE_ADD_I3;
11187 inst.instruction = T_OPCODE_CMP_LR;
11189 inst.instruction |= Rn;
11190 inst.instruction |= Rm << 3;
11194 if (inst.instruction == T_OPCODE_MOV_I8)
11195 inst.instruction = T_OPCODE_MOV_HR;
11197 inst.instruction = T_OPCODE_CMP_HR;
11203 constraint (Rn > 7,
11204 _("only lo regs allowed with immediate"));
11205 inst.instruction |= Rn << 8;
11206 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11217 top = (inst.instruction & 0x00800000) != 0;
11218 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11220 constraint (top, _(":lower16: not allowed this instruction"));
11221 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11223 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11225 constraint (!top, _(":upper16: not allowed this instruction"));
11226 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11229 Rd = inst.operands[0].reg;
11230 reject_bad_reg (Rd);
11232 inst.instruction |= Rd << 8;
11233 if (inst.reloc.type == BFD_RELOC_UNUSED)
11235 imm = inst.reloc.exp.X_add_number;
11236 inst.instruction |= (imm & 0xf000) << 4;
11237 inst.instruction |= (imm & 0x0800) << 15;
11238 inst.instruction |= (imm & 0x0700) << 4;
11239 inst.instruction |= (imm & 0x00ff);
11244 do_t_mvn_tst (void)
11248 Rn = inst.operands[0].reg;
11249 Rm = inst.operands[1].reg;
11251 if (inst.instruction == T_MNEM_cmp
11252 || inst.instruction == T_MNEM_cmn)
11253 constraint (Rn == REG_PC, BAD_PC);
11255 reject_bad_reg (Rn);
11256 reject_bad_reg (Rm);
11258 if (unified_syntax)
11260 int r0off = (inst.instruction == T_MNEM_mvn
11261 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11262 bfd_boolean narrow;
11264 if (inst.size_req == 4
11265 || inst.instruction > 0xffff
11266 || inst.operands[1].shifted
11267 || Rn > 7 || Rm > 7)
11269 else if (inst.instruction == T_MNEM_cmn)
11271 else if (THUMB_SETS_FLAGS (inst.instruction))
11272 narrow = !in_it_block ();
11274 narrow = in_it_block ();
11276 if (!inst.operands[1].isreg)
11278 /* For an immediate, we always generate a 32-bit opcode;
11279 section relaxation will shrink it later if possible. */
11280 if (inst.instruction < 0xffff)
11281 inst.instruction = THUMB_OP32 (inst.instruction);
11282 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11283 inst.instruction |= Rn << r0off;
11284 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11288 /* See if we can do this with a 16-bit instruction. */
11291 inst.instruction = THUMB_OP16 (inst.instruction);
11292 inst.instruction |= Rn;
11293 inst.instruction |= Rm << 3;
11297 constraint (inst.operands[1].shifted
11298 && inst.operands[1].immisreg,
11299 _("shift must be constant"));
11300 if (inst.instruction < 0xffff)
11301 inst.instruction = THUMB_OP32 (inst.instruction);
11302 inst.instruction |= Rn << r0off;
11303 encode_thumb32_shifted_operand (1);
11309 constraint (inst.instruction > 0xffff
11310 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11311 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11312 _("unshifted register required"));
11313 constraint (Rn > 7 || Rm > 7,
11316 inst.instruction = THUMB_OP16 (inst.instruction);
11317 inst.instruction |= Rn;
11318 inst.instruction |= Rm << 3;
11327 if (do_vfp_nsyn_mrs () == SUCCESS)
11330 Rd = inst.operands[0].reg;
11331 reject_bad_reg (Rd);
11332 inst.instruction |= Rd << 8;
11334 if (inst.operands[1].isreg)
11336 unsigned br = inst.operands[1].reg;
11337 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11338 as_bad (_("bad register for mrs"));
11340 inst.instruction |= br & (0xf << 16);
11341 inst.instruction |= (br & 0x300) >> 4;
11342 inst.instruction |= (br & SPSR_BIT) >> 2;
11346 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11348 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11350 /* PR gas/12698: The constraint is only applied for m_profile.
11351 If the user has specified -march=all, we want to ignore it as
11352 we are building for any CPU type, including non-m variants. */
11353 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11354 constraint ((flags != 0) && m_profile, _("selected processor does "
11355 "not support requested special purpose register"));
11358 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11360 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11361 _("'APSR', 'CPSR' or 'SPSR' expected"));
11363 inst.instruction |= (flags & SPSR_BIT) >> 2;
11364 inst.instruction |= inst.operands[1].imm & 0xff;
11365 inst.instruction |= 0xf0000;
11375 if (do_vfp_nsyn_msr () == SUCCESS)
11378 constraint (!inst.operands[1].isreg,
11379 _("Thumb encoding does not support an immediate here"));
11381 if (inst.operands[0].isreg)
11382 flags = (int)(inst.operands[0].reg);
11384 flags = inst.operands[0].imm;
11386 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11388 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11390 /* PR gas/12698: The constraint is only applied for m_profile.
11391 If the user has specified -march=all, we want to ignore it as
11392 we are building for any CPU type, including non-m variants. */
11393 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11394 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11395 && (bits & ~(PSR_s | PSR_f)) != 0)
11396 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11397 && bits != PSR_f)) && m_profile,
11398 _("selected processor does not support requested special "
11399 "purpose register"));
11402 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11403 "requested special purpose register"));
11405 Rn = inst.operands[1].reg;
11406 reject_bad_reg (Rn);
11408 inst.instruction |= (flags & SPSR_BIT) >> 2;
11409 inst.instruction |= (flags & 0xf0000) >> 8;
11410 inst.instruction |= (flags & 0x300) >> 4;
11411 inst.instruction |= (flags & 0xff);
11412 inst.instruction |= Rn << 16;
11418 bfd_boolean narrow;
11419 unsigned Rd, Rn, Rm;
11421 if (!inst.operands[2].present)
11422 inst.operands[2].reg = inst.operands[0].reg;
11424 Rd = inst.operands[0].reg;
11425 Rn = inst.operands[1].reg;
11426 Rm = inst.operands[2].reg;
11428 if (unified_syntax)
11430 if (inst.size_req == 4
11436 else if (inst.instruction == T_MNEM_muls)
11437 narrow = !in_it_block ();
11439 narrow = in_it_block ();
11443 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11444 constraint (Rn > 7 || Rm > 7,
11451 /* 16-bit MULS/Conditional MUL. */
11452 inst.instruction = THUMB_OP16 (inst.instruction);
11453 inst.instruction |= Rd;
11456 inst.instruction |= Rm << 3;
11458 inst.instruction |= Rn << 3;
11460 constraint (1, _("dest must overlap one source register"));
11464 constraint (inst.instruction != T_MNEM_mul,
11465 _("Thumb-2 MUL must not set flags"));
11467 inst.instruction = THUMB_OP32 (inst.instruction);
11468 inst.instruction |= Rd << 8;
11469 inst.instruction |= Rn << 16;
11470 inst.instruction |= Rm << 0;
11472 reject_bad_reg (Rd);
11473 reject_bad_reg (Rn);
11474 reject_bad_reg (Rm);
11481 unsigned RdLo, RdHi, Rn, Rm;
11483 RdLo = inst.operands[0].reg;
11484 RdHi = inst.operands[1].reg;
11485 Rn = inst.operands[2].reg;
11486 Rm = inst.operands[3].reg;
11488 reject_bad_reg (RdLo);
11489 reject_bad_reg (RdHi);
11490 reject_bad_reg (Rn);
11491 reject_bad_reg (Rm);
11493 inst.instruction |= RdLo << 12;
11494 inst.instruction |= RdHi << 8;
11495 inst.instruction |= Rn << 16;
11496 inst.instruction |= Rm;
11499 as_tsktsk (_("rdhi and rdlo must be different"));
11505 set_it_insn_type (NEUTRAL_IT_INSN);
11507 if (unified_syntax)
11509 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11511 inst.instruction = THUMB_OP32 (inst.instruction);
11512 inst.instruction |= inst.operands[0].imm;
11516 /* PR9722: Check for Thumb2 availability before
11517 generating a thumb2 nop instruction. */
11518 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11520 inst.instruction = THUMB_OP16 (inst.instruction);
11521 inst.instruction |= inst.operands[0].imm << 4;
11524 inst.instruction = 0x46c0;
11529 constraint (inst.operands[0].present,
11530 _("Thumb does not support NOP with hints"));
11531 inst.instruction = 0x46c0;
11538 if (unified_syntax)
11540 bfd_boolean narrow;
11542 if (THUMB_SETS_FLAGS (inst.instruction))
11543 narrow = !in_it_block ();
11545 narrow = in_it_block ();
11546 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11548 if (inst.size_req == 4)
11553 inst.instruction = THUMB_OP32 (inst.instruction);
11554 inst.instruction |= inst.operands[0].reg << 8;
11555 inst.instruction |= inst.operands[1].reg << 16;
11559 inst.instruction = THUMB_OP16 (inst.instruction);
11560 inst.instruction |= inst.operands[0].reg;
11561 inst.instruction |= inst.operands[1].reg << 3;
11566 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11568 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11570 inst.instruction = THUMB_OP16 (inst.instruction);
11571 inst.instruction |= inst.operands[0].reg;
11572 inst.instruction |= inst.operands[1].reg << 3;
11581 Rd = inst.operands[0].reg;
11582 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11584 reject_bad_reg (Rd);
11585 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11586 reject_bad_reg (Rn);
11588 inst.instruction |= Rd << 8;
11589 inst.instruction |= Rn << 16;
11591 if (!inst.operands[2].isreg)
11593 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11594 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11600 Rm = inst.operands[2].reg;
11601 reject_bad_reg (Rm);
11603 constraint (inst.operands[2].shifted
11604 && inst.operands[2].immisreg,
11605 _("shift must be constant"));
11606 encode_thumb32_shifted_operand (2);
11613 unsigned Rd, Rn, Rm;
11615 Rd = inst.operands[0].reg;
11616 Rn = inst.operands[1].reg;
11617 Rm = inst.operands[2].reg;
11619 reject_bad_reg (Rd);
11620 reject_bad_reg (Rn);
11621 reject_bad_reg (Rm);
11623 inst.instruction |= Rd << 8;
11624 inst.instruction |= Rn << 16;
11625 inst.instruction |= Rm;
11626 if (inst.operands[3].present)
11628 unsigned int val = inst.reloc.exp.X_add_number;
11629 constraint (inst.reloc.exp.X_op != O_constant,
11630 _("expression too complex"));
11631 inst.instruction |= (val & 0x1c) << 10;
11632 inst.instruction |= (val & 0x03) << 6;
11639 if (!inst.operands[3].present)
11643 inst.instruction &= ~0x00000020;
11645 /* PR 10168. Swap the Rm and Rn registers. */
11646 Rtmp = inst.operands[1].reg;
11647 inst.operands[1].reg = inst.operands[2].reg;
11648 inst.operands[2].reg = Rtmp;
11656 if (inst.operands[0].immisreg)
11657 reject_bad_reg (inst.operands[0].imm);
11659 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11663 do_t_push_pop (void)
11667 constraint (inst.operands[0].writeback,
11668 _("push/pop do not support {reglist}^"));
11669 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11670 _("expression too complex"));
11672 mask = inst.operands[0].imm;
11673 if ((mask & ~0xff) == 0)
11674 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11675 else if ((inst.instruction == T_MNEM_push
11676 && (mask & ~0xff) == 1 << REG_LR)
11677 || (inst.instruction == T_MNEM_pop
11678 && (mask & ~0xff) == 1 << REG_PC))
11680 inst.instruction = THUMB_OP16 (inst.instruction);
11681 inst.instruction |= THUMB_PP_PC_LR;
11682 inst.instruction |= mask & 0xff;
11684 else if (unified_syntax)
11686 inst.instruction = THUMB_OP32 (inst.instruction);
11687 encode_thumb2_ldmstm (13, mask, TRUE);
11691 inst.error = _("invalid register list to push/pop instruction");
11701 Rd = inst.operands[0].reg;
11702 Rm = inst.operands[1].reg;
11704 reject_bad_reg (Rd);
11705 reject_bad_reg (Rm);
11707 inst.instruction |= Rd << 8;
11708 inst.instruction |= Rm << 16;
11709 inst.instruction |= Rm;
11717 Rd = inst.operands[0].reg;
11718 Rm = inst.operands[1].reg;
11720 reject_bad_reg (Rd);
11721 reject_bad_reg (Rm);
11723 if (Rd <= 7 && Rm <= 7
11724 && inst.size_req != 4)
11726 inst.instruction = THUMB_OP16 (inst.instruction);
11727 inst.instruction |= Rd;
11728 inst.instruction |= Rm << 3;
11730 else if (unified_syntax)
11732 inst.instruction = THUMB_OP32 (inst.instruction);
11733 inst.instruction |= Rd << 8;
11734 inst.instruction |= Rm << 16;
11735 inst.instruction |= Rm;
11738 inst.error = BAD_HIREG;
11746 Rd = inst.operands[0].reg;
11747 Rm = inst.operands[1].reg;
11749 reject_bad_reg (Rd);
11750 reject_bad_reg (Rm);
11752 inst.instruction |= Rd << 8;
11753 inst.instruction |= Rm;
11761 Rd = inst.operands[0].reg;
11762 Rs = (inst.operands[1].present
11763 ? inst.operands[1].reg /* Rd, Rs, foo */
11764 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11766 reject_bad_reg (Rd);
11767 reject_bad_reg (Rs);
11768 if (inst.operands[2].isreg)
11769 reject_bad_reg (inst.operands[2].reg);
11771 inst.instruction |= Rd << 8;
11772 inst.instruction |= Rs << 16;
11773 if (!inst.operands[2].isreg)
11775 bfd_boolean narrow;
11777 if ((inst.instruction & 0x00100000) != 0)
11778 narrow = !in_it_block ();
11780 narrow = in_it_block ();
11782 if (Rd > 7 || Rs > 7)
11785 if (inst.size_req == 4 || !unified_syntax)
11788 if (inst.reloc.exp.X_op != O_constant
11789 || inst.reloc.exp.X_add_number != 0)
11792 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11793 relaxation, but it doesn't seem worth the hassle. */
11796 inst.reloc.type = BFD_RELOC_UNUSED;
11797 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11798 inst.instruction |= Rs << 3;
11799 inst.instruction |= Rd;
11803 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11804 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11808 encode_thumb32_shifted_operand (2);
11814 if (warn_on_deprecated
11815 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11816 as_warn (_("setend use is deprecated for ARMv8"));
11818 set_it_insn_type (OUTSIDE_IT_INSN);
11819 if (inst.operands[0].imm)
11820 inst.instruction |= 0x8;
11826 if (!inst.operands[1].present)
11827 inst.operands[1].reg = inst.operands[0].reg;
11829 if (unified_syntax)
11831 bfd_boolean narrow;
11834 switch (inst.instruction)
11837 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11839 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11841 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11843 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11847 if (THUMB_SETS_FLAGS (inst.instruction))
11848 narrow = !in_it_block ();
11850 narrow = in_it_block ();
11851 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11853 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11855 if (inst.operands[2].isreg
11856 && (inst.operands[1].reg != inst.operands[0].reg
11857 || inst.operands[2].reg > 7))
11859 if (inst.size_req == 4)
11862 reject_bad_reg (inst.operands[0].reg);
11863 reject_bad_reg (inst.operands[1].reg);
11867 if (inst.operands[2].isreg)
11869 reject_bad_reg (inst.operands[2].reg);
11870 inst.instruction = THUMB_OP32 (inst.instruction);
11871 inst.instruction |= inst.operands[0].reg << 8;
11872 inst.instruction |= inst.operands[1].reg << 16;
11873 inst.instruction |= inst.operands[2].reg;
11875 /* PR 12854: Error on extraneous shifts. */
11876 constraint (inst.operands[2].shifted,
11877 _("extraneous shift as part of operand to shift insn"));
11881 inst.operands[1].shifted = 1;
11882 inst.operands[1].shift_kind = shift_kind;
11883 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11884 ? T_MNEM_movs : T_MNEM_mov);
11885 inst.instruction |= inst.operands[0].reg << 8;
11886 encode_thumb32_shifted_operand (1);
11887 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11888 inst.reloc.type = BFD_RELOC_UNUSED;
11893 if (inst.operands[2].isreg)
11895 switch (shift_kind)
11897 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11898 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11899 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11900 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11904 inst.instruction |= inst.operands[0].reg;
11905 inst.instruction |= inst.operands[2].reg << 3;
11907 /* PR 12854: Error on extraneous shifts. */
11908 constraint (inst.operands[2].shifted,
11909 _("extraneous shift as part of operand to shift insn"));
11913 switch (shift_kind)
11915 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11916 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11917 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11920 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11921 inst.instruction |= inst.operands[0].reg;
11922 inst.instruction |= inst.operands[1].reg << 3;
11928 constraint (inst.operands[0].reg > 7
11929 || inst.operands[1].reg > 7, BAD_HIREG);
11930 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11932 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11934 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11935 constraint (inst.operands[0].reg != inst.operands[1].reg,
11936 _("source1 and dest must be same register"));
11938 switch (inst.instruction)
11940 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11941 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11942 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11943 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11947 inst.instruction |= inst.operands[0].reg;
11948 inst.instruction |= inst.operands[2].reg << 3;
11950 /* PR 12854: Error on extraneous shifts. */
11951 constraint (inst.operands[2].shifted,
11952 _("extraneous shift as part of operand to shift insn"));
11956 switch (inst.instruction)
11958 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11959 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11960 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11961 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11964 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11965 inst.instruction |= inst.operands[0].reg;
11966 inst.instruction |= inst.operands[1].reg << 3;
11974 unsigned Rd, Rn, Rm;
11976 Rd = inst.operands[0].reg;
11977 Rn = inst.operands[1].reg;
11978 Rm = inst.operands[2].reg;
11980 reject_bad_reg (Rd);
11981 reject_bad_reg (Rn);
11982 reject_bad_reg (Rm);
11984 inst.instruction |= Rd << 8;
11985 inst.instruction |= Rn << 16;
11986 inst.instruction |= Rm;
11992 unsigned Rd, Rn, Rm;
11994 Rd = inst.operands[0].reg;
11995 Rm = inst.operands[1].reg;
11996 Rn = inst.operands[2].reg;
11998 reject_bad_reg (Rd);
11999 reject_bad_reg (Rn);
12000 reject_bad_reg (Rm);
12002 inst.instruction |= Rd << 8;
12003 inst.instruction |= Rn << 16;
12004 inst.instruction |= Rm;
12010 unsigned int value = inst.reloc.exp.X_add_number;
12011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12012 _("SMC is not permitted on this architecture"));
12013 constraint (inst.reloc.exp.X_op != O_constant,
12014 _("expression too complex"));
12015 inst.reloc.type = BFD_RELOC_UNUSED;
12016 inst.instruction |= (value & 0xf000) >> 12;
12017 inst.instruction |= (value & 0x0ff0);
12018 inst.instruction |= (value & 0x000f) << 16;
12019 /* PR gas/15623: SMC instructions must be last in an IT block. */
12020 set_it_insn_type_last ();
12026 unsigned int value = inst.reloc.exp.X_add_number;
12028 inst.reloc.type = BFD_RELOC_UNUSED;
12029 inst.instruction |= (value & 0x0fff);
12030 inst.instruction |= (value & 0xf000) << 4;
12034 do_t_ssat_usat (int bias)
12038 Rd = inst.operands[0].reg;
12039 Rn = inst.operands[2].reg;
12041 reject_bad_reg (Rd);
12042 reject_bad_reg (Rn);
12044 inst.instruction |= Rd << 8;
12045 inst.instruction |= inst.operands[1].imm - bias;
12046 inst.instruction |= Rn << 16;
12048 if (inst.operands[3].present)
12050 offsetT shift_amount = inst.reloc.exp.X_add_number;
12052 inst.reloc.type = BFD_RELOC_UNUSED;
12054 constraint (inst.reloc.exp.X_op != O_constant,
12055 _("expression too complex"));
12057 if (shift_amount != 0)
12059 constraint (shift_amount > 31,
12060 _("shift expression is too large"));
12062 if (inst.operands[3].shift_kind == SHIFT_ASR)
12063 inst.instruction |= 0x00200000; /* sh bit. */
12065 inst.instruction |= (shift_amount & 0x1c) << 10;
12066 inst.instruction |= (shift_amount & 0x03) << 6;
12074 do_t_ssat_usat (1);
12082 Rd = inst.operands[0].reg;
12083 Rn = inst.operands[2].reg;
12085 reject_bad_reg (Rd);
12086 reject_bad_reg (Rn);
12088 inst.instruction |= Rd << 8;
12089 inst.instruction |= inst.operands[1].imm - 1;
12090 inst.instruction |= Rn << 16;
12096 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12097 || inst.operands[2].postind || inst.operands[2].writeback
12098 || inst.operands[2].immisreg || inst.operands[2].shifted
12099 || inst.operands[2].negative,
12102 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12104 inst.instruction |= inst.operands[0].reg << 8;
12105 inst.instruction |= inst.operands[1].reg << 12;
12106 inst.instruction |= inst.operands[2].reg << 16;
12107 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12113 if (!inst.operands[2].present)
12114 inst.operands[2].reg = inst.operands[1].reg + 1;
12116 constraint (inst.operands[0].reg == inst.operands[1].reg
12117 || inst.operands[0].reg == inst.operands[2].reg
12118 || inst.operands[0].reg == inst.operands[3].reg,
12121 inst.instruction |= inst.operands[0].reg;
12122 inst.instruction |= inst.operands[1].reg << 12;
12123 inst.instruction |= inst.operands[2].reg << 8;
12124 inst.instruction |= inst.operands[3].reg << 16;
12130 unsigned Rd, Rn, Rm;
12132 Rd = inst.operands[0].reg;
12133 Rn = inst.operands[1].reg;
12134 Rm = inst.operands[2].reg;
12136 reject_bad_reg (Rd);
12137 reject_bad_reg (Rn);
12138 reject_bad_reg (Rm);
12140 inst.instruction |= Rd << 8;
12141 inst.instruction |= Rn << 16;
12142 inst.instruction |= Rm;
12143 inst.instruction |= inst.operands[3].imm << 4;
12151 Rd = inst.operands[0].reg;
12152 Rm = inst.operands[1].reg;
12154 reject_bad_reg (Rd);
12155 reject_bad_reg (Rm);
12157 if (inst.instruction <= 0xffff
12158 && inst.size_req != 4
12159 && Rd <= 7 && Rm <= 7
12160 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12162 inst.instruction = THUMB_OP16 (inst.instruction);
12163 inst.instruction |= Rd;
12164 inst.instruction |= Rm << 3;
12166 else if (unified_syntax)
12168 if (inst.instruction <= 0xffff)
12169 inst.instruction = THUMB_OP32 (inst.instruction);
12170 inst.instruction |= Rd << 8;
12171 inst.instruction |= Rm;
12172 inst.instruction |= inst.operands[2].imm << 4;
12176 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12177 _("Thumb encoding does not support rotation"));
12178 constraint (1, BAD_HIREG);
12185 /* We have to do the following check manually as ARM_EXT_OS only applies
12187 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12189 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12190 /* This only applies to the v6m howver, not later architectures. */
12191 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12192 as_bad (_("SVC is not permitted on this architecture"));
12193 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12196 inst.reloc.type = BFD_RELOC_ARM_SWI;
12205 half = (inst.instruction & 0x10) != 0;
12206 set_it_insn_type_last ();
12207 constraint (inst.operands[0].immisreg,
12208 _("instruction requires register index"));
12210 Rn = inst.operands[0].reg;
12211 Rm = inst.operands[0].imm;
12213 constraint (Rn == REG_SP, BAD_SP);
12214 reject_bad_reg (Rm);
12216 constraint (!half && inst.operands[0].shifted,
12217 _("instruction does not allow shifted index"));
12218 inst.instruction |= (Rn << 16) | Rm;
12224 do_t_ssat_usat (0);
12232 Rd = inst.operands[0].reg;
12233 Rn = inst.operands[2].reg;
12235 reject_bad_reg (Rd);
12236 reject_bad_reg (Rn);
12238 inst.instruction |= Rd << 8;
12239 inst.instruction |= inst.operands[1].imm;
12240 inst.instruction |= Rn << 16;
12243 /* Neon instruction encoder helpers. */
12245 /* Encodings for the different types for various Neon opcodes. */
12247 /* An "invalid" code for the following tables. */
12250 struct neon_tab_entry
12253 unsigned float_or_poly;
12254 unsigned scalar_or_imm;
12257 /* Map overloaded Neon opcodes to their respective encodings. */
12258 #define NEON_ENC_TAB \
12259 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12260 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12261 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12262 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12263 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12264 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12265 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12266 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12267 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12268 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12269 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12270 /* Register variants of the following two instructions are encoded as
12271 vcge / vcgt with the operands reversed. */ \
12272 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12273 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12274 X(vfma, N_INV, 0x0000c10, N_INV), \
12275 X(vfms, N_INV, 0x0200c10, N_INV), \
12276 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12277 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12278 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12279 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12280 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12281 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12282 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12283 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12284 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12285 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12286 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12287 X(vshl, 0x0000400, N_INV, 0x0800510), \
12288 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12289 X(vand, 0x0000110, N_INV, 0x0800030), \
12290 X(vbic, 0x0100110, N_INV, 0x0800030), \
12291 X(veor, 0x1000110, N_INV, N_INV), \
12292 X(vorn, 0x0300110, N_INV, 0x0800010), \
12293 X(vorr, 0x0200110, N_INV, 0x0800010), \
12294 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12295 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12296 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12297 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12298 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12299 X(vst1, 0x0000000, 0x0800000, N_INV), \
12300 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12301 X(vst2, 0x0000100, 0x0800100, N_INV), \
12302 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12303 X(vst3, 0x0000200, 0x0800200, N_INV), \
12304 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12305 X(vst4, 0x0000300, 0x0800300, N_INV), \
12306 X(vmovn, 0x1b20200, N_INV, N_INV), \
12307 X(vtrn, 0x1b20080, N_INV, N_INV), \
12308 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12309 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12310 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12311 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12312 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12313 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12314 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12315 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12316 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12317 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12318 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12319 X(vseleq, 0xe000a00, N_INV, N_INV), \
12320 X(vselvs, 0xe100a00, N_INV, N_INV), \
12321 X(vselge, 0xe200a00, N_INV, N_INV), \
12322 X(vselgt, 0xe300a00, N_INV, N_INV), \
12323 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12324 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12325 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12326 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12327 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12328 X(aes, 0x3b00300, N_INV, N_INV), \
12329 X(sha3op, 0x2000c00, N_INV, N_INV), \
12330 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12331 X(sha2op, 0x3ba0380, N_INV, N_INV)
12335 #define X(OPC,I,F,S) N_MNEM_##OPC
12340 static const struct neon_tab_entry neon_enc_tab[] =
12342 #define X(OPC,I,F,S) { (I), (F), (S) }
12347 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12348 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12349 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12350 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12351 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12352 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12353 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12354 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12355 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12356 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12357 #define NEON_ENC_SINGLE_(X) \
12358 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12359 #define NEON_ENC_DOUBLE_(X) \
12360 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12361 #define NEON_ENC_FPV8_(X) \
12362 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12364 #define NEON_ENCODE(type, inst) \
12367 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12368 inst.is_neon = 1; \
12372 #define check_neon_suffixes \
12375 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12377 as_bad (_("invalid neon suffix for non neon instruction")); \
12383 /* Define shapes for instruction operands. The following mnemonic characters
12384 are used in this table:
12386 F - VFP S<n> register
12387 D - Neon D<n> register
12388 Q - Neon Q<n> register
12392 L - D<n> register list
12394 This table is used to generate various data:
12395 - enumerations of the form NS_DDR to be used as arguments to
12397 - a table classifying shapes into single, double, quad, mixed.
12398 - a table used to drive neon_select_shape. */
12400 #define NEON_SHAPE_DEF \
12401 X(3, (D, D, D), DOUBLE), \
12402 X(3, (Q, Q, Q), QUAD), \
12403 X(3, (D, D, I), DOUBLE), \
12404 X(3, (Q, Q, I), QUAD), \
12405 X(3, (D, D, S), DOUBLE), \
12406 X(3, (Q, Q, S), QUAD), \
12407 X(2, (D, D), DOUBLE), \
12408 X(2, (Q, Q), QUAD), \
12409 X(2, (D, S), DOUBLE), \
12410 X(2, (Q, S), QUAD), \
12411 X(2, (D, R), DOUBLE), \
12412 X(2, (Q, R), QUAD), \
12413 X(2, (D, I), DOUBLE), \
12414 X(2, (Q, I), QUAD), \
12415 X(3, (D, L, D), DOUBLE), \
12416 X(2, (D, Q), MIXED), \
12417 X(2, (Q, D), MIXED), \
12418 X(3, (D, Q, I), MIXED), \
12419 X(3, (Q, D, I), MIXED), \
12420 X(3, (Q, D, D), MIXED), \
12421 X(3, (D, Q, Q), MIXED), \
12422 X(3, (Q, Q, D), MIXED), \
12423 X(3, (Q, D, S), MIXED), \
12424 X(3, (D, Q, S), MIXED), \
12425 X(4, (D, D, D, I), DOUBLE), \
12426 X(4, (Q, Q, Q, I), QUAD), \
12427 X(2, (F, F), SINGLE), \
12428 X(3, (F, F, F), SINGLE), \
12429 X(2, (F, I), SINGLE), \
12430 X(2, (F, D), MIXED), \
12431 X(2, (D, F), MIXED), \
12432 X(3, (F, F, I), MIXED), \
12433 X(4, (R, R, F, F), SINGLE), \
12434 X(4, (F, F, R, R), SINGLE), \
12435 X(3, (D, R, R), DOUBLE), \
12436 X(3, (R, R, D), DOUBLE), \
12437 X(2, (S, R), SINGLE), \
12438 X(2, (R, S), SINGLE), \
12439 X(2, (F, R), SINGLE), \
12440 X(2, (R, F), SINGLE)
12442 #define S2(A,B) NS_##A##B
12443 #define S3(A,B,C) NS_##A##B##C
12444 #define S4(A,B,C,D) NS_##A##B##C##D
12446 #define X(N, L, C) S##N L
12459 enum neon_shape_class
12467 #define X(N, L, C) SC_##C
12469 static enum neon_shape_class neon_shape_class[] =
12487 /* Register widths of above. */
12488 static unsigned neon_shape_el_size[] =
12499 struct neon_shape_info
12502 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12505 #define S2(A,B) { SE_##A, SE_##B }
12506 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12507 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12509 #define X(N, L, C) { N, S##N L }
12511 static struct neon_shape_info neon_shape_tab[] =
12521 /* Bit masks used in type checking given instructions.
12522 'N_EQK' means the type must be the same as (or based on in some way) the key
12523 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12524 set, various other bits can be set as well in order to modify the meaning of
12525 the type constraint. */
12527 enum neon_type_mask
12551 N_KEY = 0x1000000, /* Key element (main type specifier). */
12552 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12553 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12554 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12555 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12556 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12557 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12558 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12559 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12560 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12561 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12563 N_MAX_NONSPECIAL = N_P64
12566 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12568 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12569 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12570 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12571 #define N_SUF_32 (N_SU_32 | N_F32)
12572 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12573 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12575 /* Pass this as the first type argument to neon_check_type to ignore types
12577 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12579 /* Select a "shape" for the current instruction (describing register types or
12580 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12581 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12582 function of operand parsing, so this function doesn't need to be called.
12583 Shapes should be listed in order of decreasing length. */
12585 static enum neon_shape
12586 neon_select_shape (enum neon_shape shape, ...)
12589 enum neon_shape first_shape = shape;
12591 /* Fix missing optional operands. FIXME: we don't know at this point how
12592 many arguments we should have, so this makes the assumption that we have
12593 > 1. This is true of all current Neon opcodes, I think, but may not be
12594 true in the future. */
12595 if (!inst.operands[1].present)
12596 inst.operands[1] = inst.operands[0];
12598 va_start (ap, shape);
12600 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12605 for (j = 0; j < neon_shape_tab[shape].els; j++)
12607 if (!inst.operands[j].present)
12613 switch (neon_shape_tab[shape].el[j])
12616 if (!(inst.operands[j].isreg
12617 && inst.operands[j].isvec
12618 && inst.operands[j].issingle
12619 && !inst.operands[j].isquad))
12624 if (!(inst.operands[j].isreg
12625 && inst.operands[j].isvec
12626 && !inst.operands[j].isquad
12627 && !inst.operands[j].issingle))
12632 if (!(inst.operands[j].isreg
12633 && !inst.operands[j].isvec))
12638 if (!(inst.operands[j].isreg
12639 && inst.operands[j].isvec
12640 && inst.operands[j].isquad
12641 && !inst.operands[j].issingle))
12646 if (!(!inst.operands[j].isreg
12647 && !inst.operands[j].isscalar))
12652 if (!(!inst.operands[j].isreg
12653 && inst.operands[j].isscalar))
12663 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12664 /* We've matched all the entries in the shape table, and we don't
12665 have any left over operands which have not been matched. */
12671 if (shape == NS_NULL && first_shape != NS_NULL)
12672 first_error (_("invalid instruction shape"));
12677 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12678 means the Q bit should be set). */
12681 neon_quad (enum neon_shape shape)
12683 return neon_shape_class[shape] == SC_QUAD;
12687 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12690 /* Allow modification to be made to types which are constrained to be
12691 based on the key element, based on bits set alongside N_EQK. */
12692 if ((typebits & N_EQK) != 0)
12694 if ((typebits & N_HLF) != 0)
12696 else if ((typebits & N_DBL) != 0)
12698 if ((typebits & N_SGN) != 0)
12699 *g_type = NT_signed;
12700 else if ((typebits & N_UNS) != 0)
12701 *g_type = NT_unsigned;
12702 else if ((typebits & N_INT) != 0)
12703 *g_type = NT_integer;
12704 else if ((typebits & N_FLT) != 0)
12705 *g_type = NT_float;
12706 else if ((typebits & N_SIZ) != 0)
12707 *g_type = NT_untyped;
12711 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12712 operand type, i.e. the single type specified in a Neon instruction when it
12713 is the only one given. */
12715 static struct neon_type_el
12716 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12718 struct neon_type_el dest = *key;
12720 gas_assert ((thisarg & N_EQK) != 0);
12722 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12727 /* Convert Neon type and size into compact bitmask representation. */
12729 static enum neon_type_mask
12730 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12737 case 8: return N_8;
12738 case 16: return N_16;
12739 case 32: return N_32;
12740 case 64: return N_64;
12748 case 8: return N_I8;
12749 case 16: return N_I16;
12750 case 32: return N_I32;
12751 case 64: return N_I64;
12759 case 16: return N_F16;
12760 case 32: return N_F32;
12761 case 64: return N_F64;
12769 case 8: return N_P8;
12770 case 16: return N_P16;
12771 case 64: return N_P64;
12779 case 8: return N_S8;
12780 case 16: return N_S16;
12781 case 32: return N_S32;
12782 case 64: return N_S64;
12790 case 8: return N_U8;
12791 case 16: return N_U16;
12792 case 32: return N_U32;
12793 case 64: return N_U64;
12804 /* Convert compact Neon bitmask type representation to a type and size. Only
12805 handles the case where a single bit is set in the mask. */
12808 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12809 enum neon_type_mask mask)
12811 if ((mask & N_EQK) != 0)
12814 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12816 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12818 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12820 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12825 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12827 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12828 *type = NT_unsigned;
12829 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12830 *type = NT_integer;
12831 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12832 *type = NT_untyped;
12833 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12835 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12843 /* Modify a bitmask of allowed types. This is only needed for type
12847 modify_types_allowed (unsigned allowed, unsigned mods)
12850 enum neon_el_type type;
12856 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12858 if (el_type_of_type_chk (&type, &size,
12859 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12861 neon_modify_type_size (mods, &type, &size);
12862 destmask |= type_chk_of_el_type (type, size);
12869 /* Check type and return type classification.
12870 The manual states (paraphrase): If one datatype is given, it indicates the
12872 - the second operand, if there is one
12873 - the operand, if there is no second operand
12874 - the result, if there are no operands.
12875 This isn't quite good enough though, so we use a concept of a "key" datatype
12876 which is set on a per-instruction basis, which is the one which matters when
12877 only one data type is written.
12878 Note: this function has side-effects (e.g. filling in missing operands). All
12879 Neon instructions should call it before performing bit encoding. */
12881 static struct neon_type_el
12882 neon_check_type (unsigned els, enum neon_shape ns, ...)
12885 unsigned i, pass, key_el = 0;
12886 unsigned types[NEON_MAX_TYPE_ELS];
12887 enum neon_el_type k_type = NT_invtype;
12888 unsigned k_size = -1u;
12889 struct neon_type_el badtype = {NT_invtype, -1};
12890 unsigned key_allowed = 0;
12892 /* Optional registers in Neon instructions are always (not) in operand 1.
12893 Fill in the missing operand here, if it was omitted. */
12894 if (els > 1 && !inst.operands[1].present)
12895 inst.operands[1] = inst.operands[0];
12897 /* Suck up all the varargs. */
12899 for (i = 0; i < els; i++)
12901 unsigned thisarg = va_arg (ap, unsigned);
12902 if (thisarg == N_IGNORE_TYPE)
12907 types[i] = thisarg;
12908 if ((thisarg & N_KEY) != 0)
12913 if (inst.vectype.elems > 0)
12914 for (i = 0; i < els; i++)
12915 if (inst.operands[i].vectype.type != NT_invtype)
12917 first_error (_("types specified in both the mnemonic and operands"));
12921 /* Duplicate inst.vectype elements here as necessary.
12922 FIXME: No idea if this is exactly the same as the ARM assembler,
12923 particularly when an insn takes one register and one non-register
12925 if (inst.vectype.elems == 1 && els > 1)
12928 inst.vectype.elems = els;
12929 inst.vectype.el[key_el] = inst.vectype.el[0];
12930 for (j = 0; j < els; j++)
12932 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12935 else if (inst.vectype.elems == 0 && els > 0)
12938 /* No types were given after the mnemonic, so look for types specified
12939 after each operand. We allow some flexibility here; as long as the
12940 "key" operand has a type, we can infer the others. */
12941 for (j = 0; j < els; j++)
12942 if (inst.operands[j].vectype.type != NT_invtype)
12943 inst.vectype.el[j] = inst.operands[j].vectype;
12945 if (inst.operands[key_el].vectype.type != NT_invtype)
12947 for (j = 0; j < els; j++)
12948 if (inst.operands[j].vectype.type == NT_invtype)
12949 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12954 first_error (_("operand types can't be inferred"));
12958 else if (inst.vectype.elems != els)
12960 first_error (_("type specifier has the wrong number of parts"));
12964 for (pass = 0; pass < 2; pass++)
12966 for (i = 0; i < els; i++)
12968 unsigned thisarg = types[i];
12969 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12970 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12971 enum neon_el_type g_type = inst.vectype.el[i].type;
12972 unsigned g_size = inst.vectype.el[i].size;
12974 /* Decay more-specific signed & unsigned types to sign-insensitive
12975 integer types if sign-specific variants are unavailable. */
12976 if ((g_type == NT_signed || g_type == NT_unsigned)
12977 && (types_allowed & N_SU_ALL) == 0)
12978 g_type = NT_integer;
12980 /* If only untyped args are allowed, decay any more specific types to
12981 them. Some instructions only care about signs for some element
12982 sizes, so handle that properly. */
12983 if (((types_allowed & N_UNT) == 0)
12984 && ((g_size == 8 && (types_allowed & N_8) != 0)
12985 || (g_size == 16 && (types_allowed & N_16) != 0)
12986 || (g_size == 32 && (types_allowed & N_32) != 0)
12987 || (g_size == 64 && (types_allowed & N_64) != 0)))
12988 g_type = NT_untyped;
12992 if ((thisarg & N_KEY) != 0)
12996 key_allowed = thisarg & ~N_KEY;
13001 if ((thisarg & N_VFP) != 0)
13003 enum neon_shape_el regshape;
13004 unsigned regwidth, match;
13006 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13009 first_error (_("invalid instruction shape"));
13012 regshape = neon_shape_tab[ns].el[i];
13013 regwidth = neon_shape_el_size[regshape];
13015 /* In VFP mode, operands must match register widths. If we
13016 have a key operand, use its width, else use the width of
13017 the current operand. */
13023 if (regwidth != match)
13025 first_error (_("operand size must match register width"));
13030 if ((thisarg & N_EQK) == 0)
13032 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13034 if ((given_type & types_allowed) == 0)
13036 first_error (_("bad type in Neon instruction"));
13042 enum neon_el_type mod_k_type = k_type;
13043 unsigned mod_k_size = k_size;
13044 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13045 if (g_type != mod_k_type || g_size != mod_k_size)
13047 first_error (_("inconsistent types in Neon instruction"));
13055 return inst.vectype.el[key_el];
13058 /* Neon-style VFP instruction forwarding. */
13060 /* Thumb VFP instructions have 0xE in the condition field. */
13063 do_vfp_cond_or_thumb (void)
13068 inst.instruction |= 0xe0000000;
13070 inst.instruction |= inst.cond << 28;
13073 /* Look up and encode a simple mnemonic, for use as a helper function for the
13074 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13075 etc. It is assumed that operand parsing has already been done, and that the
13076 operands are in the form expected by the given opcode (this isn't necessarily
13077 the same as the form in which they were parsed, hence some massaging must
13078 take place before this function is called).
13079 Checks current arch version against that in the looked-up opcode. */
13082 do_vfp_nsyn_opcode (const char *opname)
13084 const struct asm_opcode *opcode;
13086 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13092 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13099 inst.instruction = opcode->tvalue;
13100 opcode->tencode ();
13104 inst.instruction = (inst.cond << 28) | opcode->avalue;
13105 opcode->aencode ();
13110 do_vfp_nsyn_add_sub (enum neon_shape rs)
13112 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13117 do_vfp_nsyn_opcode ("fadds");
13119 do_vfp_nsyn_opcode ("fsubs");
13124 do_vfp_nsyn_opcode ("faddd");
13126 do_vfp_nsyn_opcode ("fsubd");
13130 /* Check operand types to see if this is a VFP instruction, and if so call
13134 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13136 enum neon_shape rs;
13137 struct neon_type_el et;
13142 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13143 et = neon_check_type (2, rs,
13144 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13148 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13149 et = neon_check_type (3, rs,
13150 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13157 if (et.type != NT_invtype)
13168 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13170 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13175 do_vfp_nsyn_opcode ("fmacs");
13177 do_vfp_nsyn_opcode ("fnmacs");
13182 do_vfp_nsyn_opcode ("fmacd");
13184 do_vfp_nsyn_opcode ("fnmacd");
13189 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13191 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13196 do_vfp_nsyn_opcode ("ffmas");
13198 do_vfp_nsyn_opcode ("ffnmas");
13203 do_vfp_nsyn_opcode ("ffmad");
13205 do_vfp_nsyn_opcode ("ffnmad");
13210 do_vfp_nsyn_mul (enum neon_shape rs)
13213 do_vfp_nsyn_opcode ("fmuls");
13215 do_vfp_nsyn_opcode ("fmuld");
13219 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13221 int is_neg = (inst.instruction & 0x80) != 0;
13222 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13227 do_vfp_nsyn_opcode ("fnegs");
13229 do_vfp_nsyn_opcode ("fabss");
13234 do_vfp_nsyn_opcode ("fnegd");
13236 do_vfp_nsyn_opcode ("fabsd");
13240 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13241 insns belong to Neon, and are handled elsewhere. */
13244 do_vfp_nsyn_ldm_stm (int is_dbmode)
13246 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13250 do_vfp_nsyn_opcode ("fldmdbs");
13252 do_vfp_nsyn_opcode ("fldmias");
13257 do_vfp_nsyn_opcode ("fstmdbs");
13259 do_vfp_nsyn_opcode ("fstmias");
13264 do_vfp_nsyn_sqrt (void)
13266 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13267 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13270 do_vfp_nsyn_opcode ("fsqrts");
13272 do_vfp_nsyn_opcode ("fsqrtd");
13276 do_vfp_nsyn_div (void)
13278 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13279 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13280 N_F32 | N_F64 | N_KEY | N_VFP);
13283 do_vfp_nsyn_opcode ("fdivs");
13285 do_vfp_nsyn_opcode ("fdivd");
13289 do_vfp_nsyn_nmul (void)
13291 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13292 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13293 N_F32 | N_F64 | N_KEY | N_VFP);
13297 NEON_ENCODE (SINGLE, inst);
13298 do_vfp_sp_dyadic ();
13302 NEON_ENCODE (DOUBLE, inst);
13303 do_vfp_dp_rd_rn_rm ();
13305 do_vfp_cond_or_thumb ();
13309 do_vfp_nsyn_cmp (void)
13311 if (inst.operands[1].isreg)
13313 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13314 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13318 NEON_ENCODE (SINGLE, inst);
13319 do_vfp_sp_monadic ();
13323 NEON_ENCODE (DOUBLE, inst);
13324 do_vfp_dp_rd_rm ();
13329 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13330 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13332 switch (inst.instruction & 0x0fffffff)
13335 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13338 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13346 NEON_ENCODE (SINGLE, inst);
13347 do_vfp_sp_compare_z ();
13351 NEON_ENCODE (DOUBLE, inst);
13355 do_vfp_cond_or_thumb ();
13359 nsyn_insert_sp (void)
13361 inst.operands[1] = inst.operands[0];
13362 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13363 inst.operands[0].reg = REG_SP;
13364 inst.operands[0].isreg = 1;
13365 inst.operands[0].writeback = 1;
13366 inst.operands[0].present = 1;
13370 do_vfp_nsyn_push (void)
13373 if (inst.operands[1].issingle)
13374 do_vfp_nsyn_opcode ("fstmdbs");
13376 do_vfp_nsyn_opcode ("fstmdbd");
13380 do_vfp_nsyn_pop (void)
13383 if (inst.operands[1].issingle)
13384 do_vfp_nsyn_opcode ("fldmias");
13386 do_vfp_nsyn_opcode ("fldmiad");
13389 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13390 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13393 neon_dp_fixup (struct arm_it* insn)
13395 unsigned int i = insn->instruction;
13400 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13411 insn->instruction = i;
13414 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13418 neon_logbits (unsigned x)
13420 return ffs (x) - 4;
13423 #define LOW4(R) ((R) & 0xf)
13424 #define HI1(R) (((R) >> 4) & 1)
13426 /* Encode insns with bit pattern:
13428 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13429 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13431 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13432 different meaning for some instruction. */
13435 neon_three_same (int isquad, int ubit, int size)
13437 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13438 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13439 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13440 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13441 inst.instruction |= LOW4 (inst.operands[2].reg);
13442 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13443 inst.instruction |= (isquad != 0) << 6;
13444 inst.instruction |= (ubit != 0) << 24;
13446 inst.instruction |= neon_logbits (size) << 20;
13448 neon_dp_fixup (&inst);
13451 /* Encode instructions of the form:
13453 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13454 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13456 Don't write size if SIZE == -1. */
13459 neon_two_same (int qbit, int ubit, int size)
13461 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13462 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13463 inst.instruction |= LOW4 (inst.operands[1].reg);
13464 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13465 inst.instruction |= (qbit != 0) << 6;
13466 inst.instruction |= (ubit != 0) << 24;
13469 inst.instruction |= neon_logbits (size) << 18;
13471 neon_dp_fixup (&inst);
13474 /* Neon instruction encoders, in approximate order of appearance. */
13477 do_neon_dyadic_i_su (void)
13479 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13480 struct neon_type_el et = neon_check_type (3, rs,
13481 N_EQK, N_EQK, N_SU_32 | N_KEY);
13482 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13486 do_neon_dyadic_i64_su (void)
13488 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13489 struct neon_type_el et = neon_check_type (3, rs,
13490 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13491 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13495 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13498 unsigned size = et.size >> 3;
13499 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13500 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13501 inst.instruction |= LOW4 (inst.operands[1].reg);
13502 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13503 inst.instruction |= (isquad != 0) << 6;
13504 inst.instruction |= immbits << 16;
13505 inst.instruction |= (size >> 3) << 7;
13506 inst.instruction |= (size & 0x7) << 19;
13508 inst.instruction |= (uval != 0) << 24;
13510 neon_dp_fixup (&inst);
13514 do_neon_shl_imm (void)
13516 if (!inst.operands[2].isreg)
13518 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13519 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13520 NEON_ENCODE (IMMED, inst);
13521 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13525 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13526 struct neon_type_el et = neon_check_type (3, rs,
13527 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13530 /* VSHL/VQSHL 3-register variants have syntax such as:
13532 whereas other 3-register operations encoded by neon_three_same have
13535 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13537 tmp = inst.operands[2].reg;
13538 inst.operands[2].reg = inst.operands[1].reg;
13539 inst.operands[1].reg = tmp;
13540 NEON_ENCODE (INTEGER, inst);
13541 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13546 do_neon_qshl_imm (void)
13548 if (!inst.operands[2].isreg)
13550 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13551 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13553 NEON_ENCODE (IMMED, inst);
13554 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13555 inst.operands[2].imm);
13559 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13560 struct neon_type_el et = neon_check_type (3, rs,
13561 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13564 /* See note in do_neon_shl_imm. */
13565 tmp = inst.operands[2].reg;
13566 inst.operands[2].reg = inst.operands[1].reg;
13567 inst.operands[1].reg = tmp;
13568 NEON_ENCODE (INTEGER, inst);
13569 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13574 do_neon_rshl (void)
13576 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13577 struct neon_type_el et = neon_check_type (3, rs,
13578 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13581 tmp = inst.operands[2].reg;
13582 inst.operands[2].reg = inst.operands[1].reg;
13583 inst.operands[1].reg = tmp;
13584 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13588 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13590 /* Handle .I8 pseudo-instructions. */
13593 /* Unfortunately, this will make everything apart from zero out-of-range.
13594 FIXME is this the intended semantics? There doesn't seem much point in
13595 accepting .I8 if so. */
13596 immediate |= immediate << 8;
13602 if (immediate == (immediate & 0x000000ff))
13604 *immbits = immediate;
13607 else if (immediate == (immediate & 0x0000ff00))
13609 *immbits = immediate >> 8;
13612 else if (immediate == (immediate & 0x00ff0000))
13614 *immbits = immediate >> 16;
13617 else if (immediate == (immediate & 0xff000000))
13619 *immbits = immediate >> 24;
13622 if ((immediate & 0xffff) != (immediate >> 16))
13623 goto bad_immediate;
13624 immediate &= 0xffff;
13627 if (immediate == (immediate & 0x000000ff))
13629 *immbits = immediate;
13632 else if (immediate == (immediate & 0x0000ff00))
13634 *immbits = immediate >> 8;
13639 first_error (_("immediate value out of range"));
13643 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13647 neon_bits_same_in_bytes (unsigned imm)
13649 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13650 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13651 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13652 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13655 /* For immediate of above form, return 0bABCD. */
13658 neon_squash_bits (unsigned imm)
13660 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13661 | ((imm & 0x01000000) >> 21);
13664 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13667 neon_qfloat_bits (unsigned imm)
13669 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13672 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13673 the instruction. *OP is passed as the initial value of the op field, and
13674 may be set to a different value depending on the constant (i.e.
13675 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13676 MVN). If the immediate looks like a repeated pattern then also
13677 try smaller element sizes. */
13680 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13681 unsigned *immbits, int *op, int size,
13682 enum neon_el_type type)
13684 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13686 if (type == NT_float && !float_p)
13689 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13691 if (size != 32 || *op == 1)
13693 *immbits = neon_qfloat_bits (immlo);
13699 if (neon_bits_same_in_bytes (immhi)
13700 && neon_bits_same_in_bytes (immlo))
13704 *immbits = (neon_squash_bits (immhi) << 4)
13705 | neon_squash_bits (immlo);
13710 if (immhi != immlo)
13716 if (immlo == (immlo & 0x000000ff))
13721 else if (immlo == (immlo & 0x0000ff00))
13723 *immbits = immlo >> 8;
13726 else if (immlo == (immlo & 0x00ff0000))
13728 *immbits = immlo >> 16;
13731 else if (immlo == (immlo & 0xff000000))
13733 *immbits = immlo >> 24;
13736 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13738 *immbits = (immlo >> 8) & 0xff;
13741 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13743 *immbits = (immlo >> 16) & 0xff;
13747 if ((immlo & 0xffff) != (immlo >> 16))
13754 if (immlo == (immlo & 0x000000ff))
13759 else if (immlo == (immlo & 0x0000ff00))
13761 *immbits = immlo >> 8;
13765 if ((immlo & 0xff) != (immlo >> 8))
13770 if (immlo == (immlo & 0x000000ff))
13772 /* Don't allow MVN with 8-bit immediate. */
13782 /* Write immediate bits [7:0] to the following locations:
13784 |28/24|23 19|18 16|15 4|3 0|
13785 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13787 This function is used by VMOV/VMVN/VORR/VBIC. */
13790 neon_write_immbits (unsigned immbits)
13792 inst.instruction |= immbits & 0xf;
13793 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13794 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13797 /* Invert low-order SIZE bits of XHI:XLO. */
13800 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13802 unsigned immlo = xlo ? *xlo : 0;
13803 unsigned immhi = xhi ? *xhi : 0;
13808 immlo = (~immlo) & 0xff;
13812 immlo = (~immlo) & 0xffff;
13816 immhi = (~immhi) & 0xffffffff;
13817 /* fall through. */
13820 immlo = (~immlo) & 0xffffffff;
13835 do_neon_logic (void)
13837 if (inst.operands[2].present && inst.operands[2].isreg)
13839 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13840 neon_check_type (3, rs, N_IGNORE_TYPE);
13841 /* U bit and size field were set as part of the bitmask. */
13842 NEON_ENCODE (INTEGER, inst);
13843 neon_three_same (neon_quad (rs), 0, -1);
13847 const int three_ops_form = (inst.operands[2].present
13848 && !inst.operands[2].isreg);
13849 const int immoperand = (three_ops_form ? 2 : 1);
13850 enum neon_shape rs = (three_ops_form
13851 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13852 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13853 struct neon_type_el et = neon_check_type (2, rs,
13854 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13855 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13859 if (et.type == NT_invtype)
13862 if (three_ops_form)
13863 constraint (inst.operands[0].reg != inst.operands[1].reg,
13864 _("first and second operands shall be the same register"));
13866 NEON_ENCODE (IMMED, inst);
13868 immbits = inst.operands[immoperand].imm;
13871 /* .i64 is a pseudo-op, so the immediate must be a repeating
13873 if (immbits != (inst.operands[immoperand].regisimm ?
13874 inst.operands[immoperand].reg : 0))
13876 /* Set immbits to an invalid constant. */
13877 immbits = 0xdeadbeef;
13884 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13888 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13892 /* Pseudo-instruction for VBIC. */
13893 neon_invert_size (&immbits, 0, et.size);
13894 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13898 /* Pseudo-instruction for VORR. */
13899 neon_invert_size (&immbits, 0, et.size);
13900 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13910 inst.instruction |= neon_quad (rs) << 6;
13911 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13912 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13913 inst.instruction |= cmode << 8;
13914 neon_write_immbits (immbits);
13916 neon_dp_fixup (&inst);
13921 do_neon_bitfield (void)
13923 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13924 neon_check_type (3, rs, N_IGNORE_TYPE);
13925 neon_three_same (neon_quad (rs), 0, -1);
13929 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13932 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13933 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13935 if (et.type == NT_float)
13937 NEON_ENCODE (FLOAT, inst);
13938 neon_three_same (neon_quad (rs), 0, -1);
13942 NEON_ENCODE (INTEGER, inst);
13943 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13948 do_neon_dyadic_if_su (void)
13950 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13954 do_neon_dyadic_if_su_d (void)
13956 /* This version only allow D registers, but that constraint is enforced during
13957 operand parsing so we don't need to do anything extra here. */
13958 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13962 do_neon_dyadic_if_i_d (void)
13964 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13965 affected if we specify unsigned args. */
13966 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13969 enum vfp_or_neon_is_neon_bits
13972 NEON_CHECK_ARCH = 2,
13973 NEON_CHECK_ARCH8 = 4
13976 /* Call this function if an instruction which may have belonged to the VFP or
13977 Neon instruction sets, but turned out to be a Neon instruction (due to the
13978 operand types involved, etc.). We have to check and/or fix-up a couple of
13981 - Make sure the user hasn't attempted to make a Neon instruction
13983 - Alter the value in the condition code field if necessary.
13984 - Make sure that the arch supports Neon instructions.
13986 Which of these operations take place depends on bits from enum
13987 vfp_or_neon_is_neon_bits.
13989 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13990 current instruction's condition is COND_ALWAYS, the condition field is
13991 changed to inst.uncond_value. This is necessary because instructions shared
13992 between VFP and Neon may be conditional for the VFP variants only, and the
13993 unconditional Neon version must have, e.g., 0xF in the condition field. */
13996 vfp_or_neon_is_neon (unsigned check)
13998 /* Conditions are always legal in Thumb mode (IT blocks). */
13999 if (!thumb_mode && (check & NEON_CHECK_CC))
14001 if (inst.cond != COND_ALWAYS)
14003 first_error (_(BAD_COND));
14006 if (inst.uncond_value != -1)
14007 inst.instruction |= inst.uncond_value << 28;
14010 if ((check & NEON_CHECK_ARCH)
14011 && !mark_feature_used (&fpu_neon_ext_v1))
14013 first_error (_(BAD_FPU));
14017 if ((check & NEON_CHECK_ARCH8)
14018 && !mark_feature_used (&fpu_neon_ext_armv8))
14020 first_error (_(BAD_FPU));
14028 do_neon_addsub_if_i (void)
14030 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14033 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14036 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14037 affected if we specify unsigned args. */
14038 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14041 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14043 V<op> A,B (A is operand 0, B is operand 2)
14048 so handle that case specially. */
14051 neon_exchange_operands (void)
14053 void *scratch = alloca (sizeof (inst.operands[0]));
14054 if (inst.operands[1].present)
14056 /* Swap operands[1] and operands[2]. */
14057 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14058 inst.operands[1] = inst.operands[2];
14059 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14063 inst.operands[1] = inst.operands[2];
14064 inst.operands[2] = inst.operands[0];
14069 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14071 if (inst.operands[2].isreg)
14074 neon_exchange_operands ();
14075 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14079 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14080 struct neon_type_el et = neon_check_type (2, rs,
14081 N_EQK | N_SIZ, immtypes | N_KEY);
14083 NEON_ENCODE (IMMED, inst);
14084 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14085 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14086 inst.instruction |= LOW4 (inst.operands[1].reg);
14087 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14088 inst.instruction |= neon_quad (rs) << 6;
14089 inst.instruction |= (et.type == NT_float) << 10;
14090 inst.instruction |= neon_logbits (et.size) << 18;
14092 neon_dp_fixup (&inst);
14099 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14103 do_neon_cmp_inv (void)
14105 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14111 neon_compare (N_IF_32, N_IF_32, FALSE);
14114 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14115 scalars, which are encoded in 5 bits, M : Rm.
14116 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14117 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14121 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14123 unsigned regno = NEON_SCALAR_REG (scalar);
14124 unsigned elno = NEON_SCALAR_INDEX (scalar);
14129 if (regno > 7 || elno > 3)
14131 return regno | (elno << 3);
14134 if (regno > 15 || elno > 1)
14136 return regno | (elno << 4);
14140 first_error (_("scalar out of range for multiply instruction"));
14146 /* Encode multiply / multiply-accumulate scalar instructions. */
14149 neon_mul_mac (struct neon_type_el et, int ubit)
14153 /* Give a more helpful error message if we have an invalid type. */
14154 if (et.type == NT_invtype)
14157 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14158 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14159 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14160 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14161 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14162 inst.instruction |= LOW4 (scalar);
14163 inst.instruction |= HI1 (scalar) << 5;
14164 inst.instruction |= (et.type == NT_float) << 8;
14165 inst.instruction |= neon_logbits (et.size) << 20;
14166 inst.instruction |= (ubit != 0) << 24;
14168 neon_dp_fixup (&inst);
14172 do_neon_mac_maybe_scalar (void)
14174 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14177 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14180 if (inst.operands[2].isscalar)
14182 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14183 struct neon_type_el et = neon_check_type (3, rs,
14184 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14185 NEON_ENCODE (SCALAR, inst);
14186 neon_mul_mac (et, neon_quad (rs));
14190 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14191 affected if we specify unsigned args. */
14192 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14197 do_neon_fmac (void)
14199 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14202 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14205 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14211 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14212 struct neon_type_el et = neon_check_type (3, rs,
14213 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14214 neon_three_same (neon_quad (rs), 0, et.size);
14217 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14218 same types as the MAC equivalents. The polynomial type for this instruction
14219 is encoded the same as the integer type. */
14224 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14227 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14230 if (inst.operands[2].isscalar)
14231 do_neon_mac_maybe_scalar ();
14233 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14237 do_neon_qdmulh (void)
14239 if (inst.operands[2].isscalar)
14241 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14242 struct neon_type_el et = neon_check_type (3, rs,
14243 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14244 NEON_ENCODE (SCALAR, inst);
14245 neon_mul_mac (et, neon_quad (rs));
14249 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14250 struct neon_type_el et = neon_check_type (3, rs,
14251 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14252 NEON_ENCODE (INTEGER, inst);
14253 /* The U bit (rounding) comes from bit mask. */
14254 neon_three_same (neon_quad (rs), 0, et.size);
14259 do_neon_fcmp_absolute (void)
14261 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14262 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14263 /* Size field comes from bit mask. */
14264 neon_three_same (neon_quad (rs), 1, -1);
14268 do_neon_fcmp_absolute_inv (void)
14270 neon_exchange_operands ();
14271 do_neon_fcmp_absolute ();
14275 do_neon_step (void)
14277 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14278 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14279 neon_three_same (neon_quad (rs), 0, -1);
14283 do_neon_abs_neg (void)
14285 enum neon_shape rs;
14286 struct neon_type_el et;
14288 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14291 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14294 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14295 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14297 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14298 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14299 inst.instruction |= LOW4 (inst.operands[1].reg);
14300 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14301 inst.instruction |= neon_quad (rs) << 6;
14302 inst.instruction |= (et.type == NT_float) << 10;
14303 inst.instruction |= neon_logbits (et.size) << 18;
14305 neon_dp_fixup (&inst);
14311 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14312 struct neon_type_el et = neon_check_type (2, rs,
14313 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14314 int imm = inst.operands[2].imm;
14315 constraint (imm < 0 || (unsigned)imm >= et.size,
14316 _("immediate out of range for insert"));
14317 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14323 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14324 struct neon_type_el et = neon_check_type (2, rs,
14325 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14326 int imm = inst.operands[2].imm;
14327 constraint (imm < 1 || (unsigned)imm > et.size,
14328 _("immediate out of range for insert"));
14329 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14333 do_neon_qshlu_imm (void)
14335 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14336 struct neon_type_el et = neon_check_type (2, rs,
14337 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14338 int imm = inst.operands[2].imm;
14339 constraint (imm < 0 || (unsigned)imm >= et.size,
14340 _("immediate out of range for shift"));
14341 /* Only encodes the 'U present' variant of the instruction.
14342 In this case, signed types have OP (bit 8) set to 0.
14343 Unsigned types have OP set to 1. */
14344 inst.instruction |= (et.type == NT_unsigned) << 8;
14345 /* The rest of the bits are the same as other immediate shifts. */
14346 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14350 do_neon_qmovn (void)
14352 struct neon_type_el et = neon_check_type (2, NS_DQ,
14353 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14354 /* Saturating move where operands can be signed or unsigned, and the
14355 destination has the same signedness. */
14356 NEON_ENCODE (INTEGER, inst);
14357 if (et.type == NT_unsigned)
14358 inst.instruction |= 0xc0;
14360 inst.instruction |= 0x80;
14361 neon_two_same (0, 1, et.size / 2);
14365 do_neon_qmovun (void)
14367 struct neon_type_el et = neon_check_type (2, NS_DQ,
14368 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14369 /* Saturating move with unsigned results. Operands must be signed. */
14370 NEON_ENCODE (INTEGER, inst);
14371 neon_two_same (0, 1, et.size / 2);
14375 do_neon_rshift_sat_narrow (void)
14377 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14378 or unsigned. If operands are unsigned, results must also be unsigned. */
14379 struct neon_type_el et = neon_check_type (2, NS_DQI,
14380 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14381 int imm = inst.operands[2].imm;
14382 /* This gets the bounds check, size encoding and immediate bits calculation
14386 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14387 VQMOVN.I<size> <Dd>, <Qm>. */
14390 inst.operands[2].present = 0;
14391 inst.instruction = N_MNEM_vqmovn;
14396 constraint (imm < 1 || (unsigned)imm > et.size,
14397 _("immediate out of range"));
14398 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14402 do_neon_rshift_sat_narrow_u (void)
14404 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14405 or unsigned. If operands are unsigned, results must also be unsigned. */
14406 struct neon_type_el et = neon_check_type (2, NS_DQI,
14407 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14408 int imm = inst.operands[2].imm;
14409 /* This gets the bounds check, size encoding and immediate bits calculation
14413 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14414 VQMOVUN.I<size> <Dd>, <Qm>. */
14417 inst.operands[2].present = 0;
14418 inst.instruction = N_MNEM_vqmovun;
14423 constraint (imm < 1 || (unsigned)imm > et.size,
14424 _("immediate out of range"));
14425 /* FIXME: The manual is kind of unclear about what value U should have in
14426 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14428 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14432 do_neon_movn (void)
14434 struct neon_type_el et = neon_check_type (2, NS_DQ,
14435 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14436 NEON_ENCODE (INTEGER, inst);
14437 neon_two_same (0, 1, et.size / 2);
14441 do_neon_rshift_narrow (void)
14443 struct neon_type_el et = neon_check_type (2, NS_DQI,
14444 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14445 int imm = inst.operands[2].imm;
14446 /* This gets the bounds check, size encoding and immediate bits calculation
14450 /* If immediate is zero then we are a pseudo-instruction for
14451 VMOVN.I<size> <Dd>, <Qm> */
14454 inst.operands[2].present = 0;
14455 inst.instruction = N_MNEM_vmovn;
14460 constraint (imm < 1 || (unsigned)imm > et.size,
14461 _("immediate out of range for narrowing operation"));
14462 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14466 do_neon_shll (void)
14468 /* FIXME: Type checking when lengthening. */
14469 struct neon_type_el et = neon_check_type (2, NS_QDI,
14470 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14471 unsigned imm = inst.operands[2].imm;
14473 if (imm == et.size)
14475 /* Maximum shift variant. */
14476 NEON_ENCODE (INTEGER, inst);
14477 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14478 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14479 inst.instruction |= LOW4 (inst.operands[1].reg);
14480 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14481 inst.instruction |= neon_logbits (et.size) << 18;
14483 neon_dp_fixup (&inst);
14487 /* A more-specific type check for non-max versions. */
14488 et = neon_check_type (2, NS_QDI,
14489 N_EQK | N_DBL, N_SU_32 | N_KEY);
14490 NEON_ENCODE (IMMED, inst);
14491 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14495 /* Check the various types for the VCVT instruction, and return which version
14496 the current instruction is. */
14498 #define CVT_FLAVOUR_VAR \
14499 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14500 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14501 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14502 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14503 /* Half-precision conversions. */ \
14504 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14505 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14506 /* VFP instructions. */ \
14507 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14508 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14509 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14510 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14511 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14512 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14513 /* VFP instructions with bitshift. */ \
14514 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14515 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14516 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14517 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14518 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14519 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14520 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14521 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14523 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14524 neon_cvt_flavour_##C,
14526 /* The different types of conversions we can do. */
14527 enum neon_cvt_flavour
14530 neon_cvt_flavour_invalid,
14531 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14536 static enum neon_cvt_flavour
14537 get_neon_cvt_flavour (enum neon_shape rs)
14539 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14540 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14541 if (et.type != NT_invtype) \
14543 inst.error = NULL; \
14544 return (neon_cvt_flavour_##C); \
14547 struct neon_type_el et;
14548 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14549 || rs == NS_FF) ? N_VFP : 0;
14550 /* The instruction versions which take an immediate take one register
14551 argument, which is extended to the width of the full register. Thus the
14552 "source" and "destination" registers must have the same width. Hack that
14553 here by making the size equal to the key (wider, in this case) operand. */
14554 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14558 return neon_cvt_flavour_invalid;
14573 /* Neon-syntax VFP conversions. */
14576 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14578 const char *opname = 0;
14580 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14582 /* Conversions with immediate bitshift. */
14583 const char *enc[] =
14585 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14591 if (flavour < (int) ARRAY_SIZE (enc))
14593 opname = enc[flavour];
14594 constraint (inst.operands[0].reg != inst.operands[1].reg,
14595 _("operands 0 and 1 must be the same register"));
14596 inst.operands[1] = inst.operands[2];
14597 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14602 /* Conversions without bitshift. */
14603 const char *enc[] =
14605 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14611 if (flavour < (int) ARRAY_SIZE (enc))
14612 opname = enc[flavour];
14616 do_vfp_nsyn_opcode (opname);
14620 do_vfp_nsyn_cvtz (void)
14622 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14623 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14624 const char *enc[] =
14626 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14632 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14633 do_vfp_nsyn_opcode (enc[flavour]);
14637 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14638 enum neon_cvt_mode mode)
14643 set_it_insn_type (OUTSIDE_IT_INSN);
14647 case neon_cvt_flavour_s32_f64:
14651 case neon_cvt_flavour_s32_f32:
14655 case neon_cvt_flavour_u32_f64:
14659 case neon_cvt_flavour_u32_f32:
14664 first_error (_("invalid instruction shape"));
14670 case neon_cvt_mode_a: rm = 0; break;
14671 case neon_cvt_mode_n: rm = 1; break;
14672 case neon_cvt_mode_p: rm = 2; break;
14673 case neon_cvt_mode_m: rm = 3; break;
14674 default: first_error (_("invalid rounding mode")); return;
14677 NEON_ENCODE (FPV8, inst);
14678 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14679 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14680 inst.instruction |= sz << 8;
14681 inst.instruction |= op << 7;
14682 inst.instruction |= rm << 16;
14683 inst.instruction |= 0xf0000000;
14684 inst.is_neon = TRUE;
14688 do_neon_cvt_1 (enum neon_cvt_mode mode)
14690 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14691 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14692 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14694 /* PR11109: Handle round-to-zero for VCVT conversions. */
14695 if (mode == neon_cvt_mode_z
14696 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14697 && (flavour == neon_cvt_flavour_s32_f32
14698 || flavour == neon_cvt_flavour_u32_f32
14699 || flavour == neon_cvt_flavour_s32_f64
14700 || flavour == neon_cvt_flavour_u32_f64)
14701 && (rs == NS_FD || rs == NS_FF))
14703 do_vfp_nsyn_cvtz ();
14707 /* VFP rather than Neon conversions. */
14708 if (flavour >= neon_cvt_flavour_first_fp)
14710 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14711 do_vfp_nsyn_cvt (rs, flavour);
14713 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14724 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14726 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14729 /* Fixed-point conversion with #0 immediate is encoded as an
14730 integer conversion. */
14731 if (inst.operands[2].present && inst.operands[2].imm == 0)
14733 immbits = 32 - inst.operands[2].imm;
14734 NEON_ENCODE (IMMED, inst);
14735 if (flavour != neon_cvt_flavour_invalid)
14736 inst.instruction |= enctab[flavour];
14737 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14738 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14739 inst.instruction |= LOW4 (inst.operands[1].reg);
14740 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14741 inst.instruction |= neon_quad (rs) << 6;
14742 inst.instruction |= 1 << 21;
14743 inst.instruction |= immbits << 16;
14745 neon_dp_fixup (&inst);
14751 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14753 NEON_ENCODE (FLOAT, inst);
14754 set_it_insn_type (OUTSIDE_IT_INSN);
14756 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14759 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14760 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14761 inst.instruction |= LOW4 (inst.operands[1].reg);
14762 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14763 inst.instruction |= neon_quad (rs) << 6;
14764 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14765 inst.instruction |= mode << 8;
14767 inst.instruction |= 0xfc000000;
14769 inst.instruction |= 0xf0000000;
14775 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14777 NEON_ENCODE (INTEGER, inst);
14779 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14782 if (flavour != neon_cvt_flavour_invalid)
14783 inst.instruction |= enctab[flavour];
14785 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14786 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14787 inst.instruction |= LOW4 (inst.operands[1].reg);
14788 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14789 inst.instruction |= neon_quad (rs) << 6;
14790 inst.instruction |= 2 << 18;
14792 neon_dp_fixup (&inst);
14797 /* Half-precision conversions for Advanced SIMD -- neon. */
14802 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14804 as_bad (_("operand size must match register width"));
14809 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14811 as_bad (_("operand size must match register width"));
14816 inst.instruction = 0x3b60600;
14818 inst.instruction = 0x3b60700;
14820 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14821 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14822 inst.instruction |= LOW4 (inst.operands[1].reg);
14823 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14824 neon_dp_fixup (&inst);
14828 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14829 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14830 do_vfp_nsyn_cvt (rs, flavour);
14832 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14837 do_neon_cvtr (void)
14839 do_neon_cvt_1 (neon_cvt_mode_x);
14845 do_neon_cvt_1 (neon_cvt_mode_z);
14849 do_neon_cvta (void)
14851 do_neon_cvt_1 (neon_cvt_mode_a);
14855 do_neon_cvtn (void)
14857 do_neon_cvt_1 (neon_cvt_mode_n);
14861 do_neon_cvtp (void)
14863 do_neon_cvt_1 (neon_cvt_mode_p);
14867 do_neon_cvtm (void)
14869 do_neon_cvt_1 (neon_cvt_mode_m);
14873 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14876 mark_feature_used (&fpu_vfp_ext_armv8);
14878 encode_arm_vfp_reg (inst.operands[0].reg,
14879 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14880 encode_arm_vfp_reg (inst.operands[1].reg,
14881 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14882 inst.instruction |= to ? 0x10000 : 0;
14883 inst.instruction |= t ? 0x80 : 0;
14884 inst.instruction |= is_double ? 0x100 : 0;
14885 do_vfp_cond_or_thumb ();
14889 do_neon_cvttb_1 (bfd_boolean t)
14891 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14895 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14898 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14900 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14903 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14905 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14908 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14910 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14913 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14920 do_neon_cvtb (void)
14922 do_neon_cvttb_1 (FALSE);
14927 do_neon_cvtt (void)
14929 do_neon_cvttb_1 (TRUE);
14933 neon_move_immediate (void)
14935 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14936 struct neon_type_el et = neon_check_type (2, rs,
14937 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14938 unsigned immlo, immhi = 0, immbits;
14939 int op, cmode, float_p;
14941 constraint (et.type == NT_invtype,
14942 _("operand size must be specified for immediate VMOV"));
14944 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14945 op = (inst.instruction & (1 << 5)) != 0;
14947 immlo = inst.operands[1].imm;
14948 if (inst.operands[1].regisimm)
14949 immhi = inst.operands[1].reg;
14951 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14952 _("immediate has bits set outside the operand size"));
14954 float_p = inst.operands[1].immisfloat;
14956 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14957 et.size, et.type)) == FAIL)
14959 /* Invert relevant bits only. */
14960 neon_invert_size (&immlo, &immhi, et.size);
14961 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14962 with one or the other; those cases are caught by
14963 neon_cmode_for_move_imm. */
14965 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14966 &op, et.size, et.type)) == FAIL)
14968 first_error (_("immediate out of range"));
14973 inst.instruction &= ~(1 << 5);
14974 inst.instruction |= op << 5;
14976 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14977 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14978 inst.instruction |= neon_quad (rs) << 6;
14979 inst.instruction |= cmode << 8;
14981 neon_write_immbits (immbits);
14987 if (inst.operands[1].isreg)
14989 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14991 NEON_ENCODE (INTEGER, inst);
14992 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14993 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14994 inst.instruction |= LOW4 (inst.operands[1].reg);
14995 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14996 inst.instruction |= neon_quad (rs) << 6;
15000 NEON_ENCODE (IMMED, inst);
15001 neon_move_immediate ();
15004 neon_dp_fixup (&inst);
15007 /* Encode instructions of form:
15009 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15010 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15013 neon_mixed_length (struct neon_type_el et, unsigned size)
15015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15016 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15017 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15018 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15019 inst.instruction |= LOW4 (inst.operands[2].reg);
15020 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15021 inst.instruction |= (et.type == NT_unsigned) << 24;
15022 inst.instruction |= neon_logbits (size) << 20;
15024 neon_dp_fixup (&inst);
15028 do_neon_dyadic_long (void)
15030 /* FIXME: Type checking for lengthening op. */
15031 struct neon_type_el et = neon_check_type (3, NS_QDD,
15032 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15033 neon_mixed_length (et, et.size);
15037 do_neon_abal (void)
15039 struct neon_type_el et = neon_check_type (3, NS_QDD,
15040 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15041 neon_mixed_length (et, et.size);
15045 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15047 if (inst.operands[2].isscalar)
15049 struct neon_type_el et = neon_check_type (3, NS_QDS,
15050 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15051 NEON_ENCODE (SCALAR, inst);
15052 neon_mul_mac (et, et.type == NT_unsigned);
15056 struct neon_type_el et = neon_check_type (3, NS_QDD,
15057 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15058 NEON_ENCODE (INTEGER, inst);
15059 neon_mixed_length (et, et.size);
15064 do_neon_mac_maybe_scalar_long (void)
15066 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15070 do_neon_dyadic_wide (void)
15072 struct neon_type_el et = neon_check_type (3, NS_QQD,
15073 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15074 neon_mixed_length (et, et.size);
15078 do_neon_dyadic_narrow (void)
15080 struct neon_type_el et = neon_check_type (3, NS_QDD,
15081 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15082 /* Operand sign is unimportant, and the U bit is part of the opcode,
15083 so force the operand type to integer. */
15084 et.type = NT_integer;
15085 neon_mixed_length (et, et.size / 2);
15089 do_neon_mul_sat_scalar_long (void)
15091 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15095 do_neon_vmull (void)
15097 if (inst.operands[2].isscalar)
15098 do_neon_mac_maybe_scalar_long ();
15101 struct neon_type_el et = neon_check_type (3, NS_QDD,
15102 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15104 if (et.type == NT_poly)
15105 NEON_ENCODE (POLY, inst);
15107 NEON_ENCODE (INTEGER, inst);
15109 /* For polynomial encoding the U bit must be zero, and the size must
15110 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15111 obviously, as 0b10). */
15114 /* Check we're on the correct architecture. */
15115 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15117 _("Instruction form not available on this architecture.");
15122 neon_mixed_length (et, et.size);
15129 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15130 struct neon_type_el et = neon_check_type (3, rs,
15131 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15132 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15134 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15135 _("shift out of range"));
15136 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15137 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15138 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15139 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15140 inst.instruction |= LOW4 (inst.operands[2].reg);
15141 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15142 inst.instruction |= neon_quad (rs) << 6;
15143 inst.instruction |= imm << 8;
15145 neon_dp_fixup (&inst);
15151 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15152 struct neon_type_el et = neon_check_type (2, rs,
15153 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15154 unsigned op = (inst.instruction >> 7) & 3;
15155 /* N (width of reversed regions) is encoded as part of the bitmask. We
15156 extract it here to check the elements to be reversed are smaller.
15157 Otherwise we'd get a reserved instruction. */
15158 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15159 gas_assert (elsize != 0);
15160 constraint (et.size >= elsize,
15161 _("elements must be smaller than reversal region"));
15162 neon_two_same (neon_quad (rs), 1, et.size);
15168 if (inst.operands[1].isscalar)
15170 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15171 struct neon_type_el et = neon_check_type (2, rs,
15172 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15173 unsigned sizebits = et.size >> 3;
15174 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15175 int logsize = neon_logbits (et.size);
15176 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15178 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15181 NEON_ENCODE (SCALAR, inst);
15182 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15183 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15184 inst.instruction |= LOW4 (dm);
15185 inst.instruction |= HI1 (dm) << 5;
15186 inst.instruction |= neon_quad (rs) << 6;
15187 inst.instruction |= x << 17;
15188 inst.instruction |= sizebits << 16;
15190 neon_dp_fixup (&inst);
15194 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15195 struct neon_type_el et = neon_check_type (2, rs,
15196 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15197 /* Duplicate ARM register to lanes of vector. */
15198 NEON_ENCODE (ARMREG, inst);
15201 case 8: inst.instruction |= 0x400000; break;
15202 case 16: inst.instruction |= 0x000020; break;
15203 case 32: inst.instruction |= 0x000000; break;
15206 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15207 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15208 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15209 inst.instruction |= neon_quad (rs) << 21;
15210 /* The encoding for this instruction is identical for the ARM and Thumb
15211 variants, except for the condition field. */
15212 do_vfp_cond_or_thumb ();
15216 /* VMOV has particularly many variations. It can be one of:
15217 0. VMOV<c><q> <Qd>, <Qm>
15218 1. VMOV<c><q> <Dd>, <Dm>
15219 (Register operations, which are VORR with Rm = Rn.)
15220 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15221 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15223 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15224 (ARM register to scalar.)
15225 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15226 (Two ARM registers to vector.)
15227 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15228 (Scalar to ARM register.)
15229 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15230 (Vector to two ARM registers.)
15231 8. VMOV.F32 <Sd>, <Sm>
15232 9. VMOV.F64 <Dd>, <Dm>
15233 (VFP register moves.)
15234 10. VMOV.F32 <Sd>, #imm
15235 11. VMOV.F64 <Dd>, #imm
15236 (VFP float immediate load.)
15237 12. VMOV <Rd>, <Sm>
15238 (VFP single to ARM reg.)
15239 13. VMOV <Sd>, <Rm>
15240 (ARM reg to VFP single.)
15241 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15242 (Two ARM regs to two VFP singles.)
15243 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15244 (Two VFP singles to two ARM regs.)
15246 These cases can be disambiguated using neon_select_shape, except cases 1/9
15247 and 3/11 which depend on the operand type too.
15249 All the encoded bits are hardcoded by this function.
15251 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15252 Cases 5, 7 may be used with VFPv2 and above.
15254 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15255 can specify a type where it doesn't make sense to, and is ignored). */
15260 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15261 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15263 struct neon_type_el et;
15264 const char *ldconst = 0;
15268 case NS_DD: /* case 1/9. */
15269 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15270 /* It is not an error here if no type is given. */
15272 if (et.type == NT_float && et.size == 64)
15274 do_vfp_nsyn_opcode ("fcpyd");
15277 /* fall through. */
15279 case NS_QQ: /* case 0/1. */
15281 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15283 /* The architecture manual I have doesn't explicitly state which
15284 value the U bit should have for register->register moves, but
15285 the equivalent VORR instruction has U = 0, so do that. */
15286 inst.instruction = 0x0200110;
15287 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15288 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15289 inst.instruction |= LOW4 (inst.operands[1].reg);
15290 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15291 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15292 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15293 inst.instruction |= neon_quad (rs) << 6;
15295 neon_dp_fixup (&inst);
15299 case NS_DI: /* case 3/11. */
15300 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15302 if (et.type == NT_float && et.size == 64)
15304 /* case 11 (fconstd). */
15305 ldconst = "fconstd";
15306 goto encode_fconstd;
15308 /* fall through. */
15310 case NS_QI: /* case 2/3. */
15311 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15313 inst.instruction = 0x0800010;
15314 neon_move_immediate ();
15315 neon_dp_fixup (&inst);
15318 case NS_SR: /* case 4. */
15320 unsigned bcdebits = 0;
15322 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15323 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15325 /* .<size> is optional here, defaulting to .32. */
15326 if (inst.vectype.elems == 0
15327 && inst.operands[0].vectype.type == NT_invtype
15328 && inst.operands[1].vectype.type == NT_invtype)
15330 inst.vectype.el[0].type = NT_untyped;
15331 inst.vectype.el[0].size = 32;
15332 inst.vectype.elems = 1;
15335 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15336 logsize = neon_logbits (et.size);
15338 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15340 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15341 && et.size != 32, _(BAD_FPU));
15342 constraint (et.type == NT_invtype, _("bad type for scalar"));
15343 constraint (x >= 64 / et.size, _("scalar index out of range"));
15347 case 8: bcdebits = 0x8; break;
15348 case 16: bcdebits = 0x1; break;
15349 case 32: bcdebits = 0x0; break;
15353 bcdebits |= x << logsize;
15355 inst.instruction = 0xe000b10;
15356 do_vfp_cond_or_thumb ();
15357 inst.instruction |= LOW4 (dn) << 16;
15358 inst.instruction |= HI1 (dn) << 7;
15359 inst.instruction |= inst.operands[1].reg << 12;
15360 inst.instruction |= (bcdebits & 3) << 5;
15361 inst.instruction |= (bcdebits >> 2) << 21;
15365 case NS_DRR: /* case 5 (fmdrr). */
15366 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15369 inst.instruction = 0xc400b10;
15370 do_vfp_cond_or_thumb ();
15371 inst.instruction |= LOW4 (inst.operands[0].reg);
15372 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15373 inst.instruction |= inst.operands[1].reg << 12;
15374 inst.instruction |= inst.operands[2].reg << 16;
15377 case NS_RS: /* case 6. */
15380 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15381 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15382 unsigned abcdebits = 0;
15384 /* .<dt> is optional here, defaulting to .32. */
15385 if (inst.vectype.elems == 0
15386 && inst.operands[0].vectype.type == NT_invtype
15387 && inst.operands[1].vectype.type == NT_invtype)
15389 inst.vectype.el[0].type = NT_untyped;
15390 inst.vectype.el[0].size = 32;
15391 inst.vectype.elems = 1;
15394 et = neon_check_type (2, NS_NULL,
15395 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15396 logsize = neon_logbits (et.size);
15398 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15401 && et.size != 32, _(BAD_FPU));
15402 constraint (et.type == NT_invtype, _("bad type for scalar"));
15403 constraint (x >= 64 / et.size, _("scalar index out of range"));
15407 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15408 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15409 case 32: abcdebits = 0x00; break;
15413 abcdebits |= x << logsize;
15414 inst.instruction = 0xe100b10;
15415 do_vfp_cond_or_thumb ();
15416 inst.instruction |= LOW4 (dn) << 16;
15417 inst.instruction |= HI1 (dn) << 7;
15418 inst.instruction |= inst.operands[0].reg << 12;
15419 inst.instruction |= (abcdebits & 3) << 5;
15420 inst.instruction |= (abcdebits >> 2) << 21;
15424 case NS_RRD: /* case 7 (fmrrd). */
15425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15428 inst.instruction = 0xc500b10;
15429 do_vfp_cond_or_thumb ();
15430 inst.instruction |= inst.operands[0].reg << 12;
15431 inst.instruction |= inst.operands[1].reg << 16;
15432 inst.instruction |= LOW4 (inst.operands[2].reg);
15433 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15436 case NS_FF: /* case 8 (fcpys). */
15437 do_vfp_nsyn_opcode ("fcpys");
15440 case NS_FI: /* case 10 (fconsts). */
15441 ldconst = "fconsts";
15443 if (is_quarter_float (inst.operands[1].imm))
15445 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15446 do_vfp_nsyn_opcode (ldconst);
15449 first_error (_("immediate out of range"));
15452 case NS_RF: /* case 12 (fmrs). */
15453 do_vfp_nsyn_opcode ("fmrs");
15456 case NS_FR: /* case 13 (fmsr). */
15457 do_vfp_nsyn_opcode ("fmsr");
15460 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15461 (one of which is a list), but we have parsed four. Do some fiddling to
15462 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15464 case NS_RRFF: /* case 14 (fmrrs). */
15465 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15466 _("VFP registers must be adjacent"));
15467 inst.operands[2].imm = 2;
15468 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15469 do_vfp_nsyn_opcode ("fmrrs");
15472 case NS_FFRR: /* case 15 (fmsrr). */
15473 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15474 _("VFP registers must be adjacent"));
15475 inst.operands[1] = inst.operands[2];
15476 inst.operands[2] = inst.operands[3];
15477 inst.operands[0].imm = 2;
15478 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15479 do_vfp_nsyn_opcode ("fmsrr");
15483 /* neon_select_shape has determined that the instruction
15484 shape is wrong and has already set the error message. */
15493 do_neon_rshift_round_imm (void)
15495 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15496 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15497 int imm = inst.operands[2].imm;
15499 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15502 inst.operands[2].present = 0;
15507 constraint (imm < 1 || (unsigned)imm > et.size,
15508 _("immediate out of range for shift"));
15509 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15514 do_neon_movl (void)
15516 struct neon_type_el et = neon_check_type (2, NS_QD,
15517 N_EQK | N_DBL, N_SU_32 | N_KEY);
15518 unsigned sizebits = et.size >> 3;
15519 inst.instruction |= sizebits << 19;
15520 neon_two_same (0, et.type == NT_unsigned, -1);
15526 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15527 struct neon_type_el et = neon_check_type (2, rs,
15528 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15529 NEON_ENCODE (INTEGER, inst);
15530 neon_two_same (neon_quad (rs), 1, et.size);
15534 do_neon_zip_uzp (void)
15536 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15537 struct neon_type_el et = neon_check_type (2, rs,
15538 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15539 if (rs == NS_DD && et.size == 32)
15541 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15542 inst.instruction = N_MNEM_vtrn;
15546 neon_two_same (neon_quad (rs), 1, et.size);
15550 do_neon_sat_abs_neg (void)
15552 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15553 struct neon_type_el et = neon_check_type (2, rs,
15554 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15555 neon_two_same (neon_quad (rs), 1, et.size);
15559 do_neon_pair_long (void)
15561 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15562 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15563 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15564 inst.instruction |= (et.type == NT_unsigned) << 7;
15565 neon_two_same (neon_quad (rs), 1, et.size);
15569 do_neon_recip_est (void)
15571 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15572 struct neon_type_el et = neon_check_type (2, rs,
15573 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15574 inst.instruction |= (et.type == NT_float) << 8;
15575 neon_two_same (neon_quad (rs), 1, et.size);
15581 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15582 struct neon_type_el et = neon_check_type (2, rs,
15583 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15584 neon_two_same (neon_quad (rs), 1, et.size);
15590 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15591 struct neon_type_el et = neon_check_type (2, rs,
15592 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15593 neon_two_same (neon_quad (rs), 1, et.size);
15599 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15600 struct neon_type_el et = neon_check_type (2, rs,
15601 N_EQK | N_INT, N_8 | N_KEY);
15602 neon_two_same (neon_quad (rs), 1, et.size);
15608 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15609 neon_two_same (neon_quad (rs), 1, -1);
15613 do_neon_tbl_tbx (void)
15615 unsigned listlenbits;
15616 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15618 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15620 first_error (_("bad list length for table lookup"));
15624 listlenbits = inst.operands[1].imm - 1;
15625 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15626 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15627 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15628 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15629 inst.instruction |= LOW4 (inst.operands[2].reg);
15630 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15631 inst.instruction |= listlenbits << 8;
15633 neon_dp_fixup (&inst);
15637 do_neon_ldm_stm (void)
15639 /* P, U and L bits are part of bitmask. */
15640 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15641 unsigned offsetbits = inst.operands[1].imm * 2;
15643 if (inst.operands[1].issingle)
15645 do_vfp_nsyn_ldm_stm (is_dbmode);
15649 constraint (is_dbmode && !inst.operands[0].writeback,
15650 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15652 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15653 _("register list must contain at least 1 and at most 16 "
15656 inst.instruction |= inst.operands[0].reg << 16;
15657 inst.instruction |= inst.operands[0].writeback << 21;
15658 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15659 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15661 inst.instruction |= offsetbits;
15663 do_vfp_cond_or_thumb ();
15667 do_neon_ldr_str (void)
15669 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15671 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15672 And is UNPREDICTABLE in thumb mode. */
15674 && inst.operands[1].reg == REG_PC
15675 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15678 inst.error = _("Use of PC here is UNPREDICTABLE");
15679 else if (warn_on_deprecated)
15680 as_warn (_("Use of PC here is deprecated"));
15683 if (inst.operands[0].issingle)
15686 do_vfp_nsyn_opcode ("flds");
15688 do_vfp_nsyn_opcode ("fsts");
15693 do_vfp_nsyn_opcode ("fldd");
15695 do_vfp_nsyn_opcode ("fstd");
15699 /* "interleave" version also handles non-interleaving register VLD1/VST1
15703 do_neon_ld_st_interleave (void)
15705 struct neon_type_el et = neon_check_type (1, NS_NULL,
15706 N_8 | N_16 | N_32 | N_64);
15707 unsigned alignbits = 0;
15709 /* The bits in this table go:
15710 0: register stride of one (0) or two (1)
15711 1,2: register list length, minus one (1, 2, 3, 4).
15712 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15713 We use -1 for invalid entries. */
15714 const int typetable[] =
15716 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15717 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15718 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15719 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15723 if (et.type == NT_invtype)
15726 if (inst.operands[1].immisalign)
15727 switch (inst.operands[1].imm >> 8)
15729 case 64: alignbits = 1; break;
15731 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15732 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15733 goto bad_alignment;
15737 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15738 goto bad_alignment;
15743 first_error (_("bad alignment"));
15747 inst.instruction |= alignbits << 4;
15748 inst.instruction |= neon_logbits (et.size) << 6;
15750 /* Bits [4:6] of the immediate in a list specifier encode register stride
15751 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15752 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15753 up the right value for "type" in a table based on this value and the given
15754 list style, then stick it back. */
15755 idx = ((inst.operands[0].imm >> 4) & 7)
15756 | (((inst.instruction >> 8) & 3) << 3);
15758 typebits = typetable[idx];
15760 constraint (typebits == -1, _("bad list type for instruction"));
15762 inst.instruction &= ~0xf00;
15763 inst.instruction |= typebits << 8;
15766 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15767 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15768 otherwise. The variable arguments are a list of pairs of legal (size, align)
15769 values, terminated with -1. */
15772 neon_alignment_bit (int size, int align, int *do_align, ...)
15775 int result = FAIL, thissize, thisalign;
15777 if (!inst.operands[1].immisalign)
15783 va_start (ap, do_align);
15787 thissize = va_arg (ap, int);
15788 if (thissize == -1)
15790 thisalign = va_arg (ap, int);
15792 if (size == thissize && align == thisalign)
15795 while (result != SUCCESS);
15799 if (result == SUCCESS)
15802 first_error (_("unsupported alignment for instruction"));
15808 do_neon_ld_st_lane (void)
15810 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15811 int align_good, do_align = 0;
15812 int logsize = neon_logbits (et.size);
15813 int align = inst.operands[1].imm >> 8;
15814 int n = (inst.instruction >> 8) & 3;
15815 int max_el = 64 / et.size;
15817 if (et.type == NT_invtype)
15820 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15821 _("bad list length"));
15822 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15823 _("scalar index out of range"));
15824 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15826 _("stride of 2 unavailable when element size is 8"));
15830 case 0: /* VLD1 / VST1. */
15831 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15833 if (align_good == FAIL)
15837 unsigned alignbits = 0;
15840 case 16: alignbits = 0x1; break;
15841 case 32: alignbits = 0x3; break;
15844 inst.instruction |= alignbits << 4;
15848 case 1: /* VLD2 / VST2. */
15849 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15851 if (align_good == FAIL)
15854 inst.instruction |= 1 << 4;
15857 case 2: /* VLD3 / VST3. */
15858 constraint (inst.operands[1].immisalign,
15859 _("can't use alignment with this instruction"));
15862 case 3: /* VLD4 / VST4. */
15863 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15864 16, 64, 32, 64, 32, 128, -1);
15865 if (align_good == FAIL)
15869 unsigned alignbits = 0;
15872 case 8: alignbits = 0x1; break;
15873 case 16: alignbits = 0x1; break;
15874 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15877 inst.instruction |= alignbits << 4;
15884 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15885 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15886 inst.instruction |= 1 << (4 + logsize);
15888 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15889 inst.instruction |= logsize << 10;
15892 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15895 do_neon_ld_dup (void)
15897 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15898 int align_good, do_align = 0;
15900 if (et.type == NT_invtype)
15903 switch ((inst.instruction >> 8) & 3)
15905 case 0: /* VLD1. */
15906 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15907 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15908 &do_align, 16, 16, 32, 32, -1);
15909 if (align_good == FAIL)
15911 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15914 case 2: inst.instruction |= 1 << 5; break;
15915 default: first_error (_("bad list length")); return;
15917 inst.instruction |= neon_logbits (et.size) << 6;
15920 case 1: /* VLD2. */
15921 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15922 &do_align, 8, 16, 16, 32, 32, 64, -1);
15923 if (align_good == FAIL)
15925 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15926 _("bad list length"));
15927 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15928 inst.instruction |= 1 << 5;
15929 inst.instruction |= neon_logbits (et.size) << 6;
15932 case 2: /* VLD3. */
15933 constraint (inst.operands[1].immisalign,
15934 _("can't use alignment with this instruction"));
15935 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15936 _("bad list length"));
15937 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15938 inst.instruction |= 1 << 5;
15939 inst.instruction |= neon_logbits (et.size) << 6;
15942 case 3: /* VLD4. */
15944 int align = inst.operands[1].imm >> 8;
15945 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15946 16, 64, 32, 64, 32, 128, -1);
15947 if (align_good == FAIL)
15949 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15950 _("bad list length"));
15951 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15952 inst.instruction |= 1 << 5;
15953 if (et.size == 32 && align == 128)
15954 inst.instruction |= 0x3 << 6;
15956 inst.instruction |= neon_logbits (et.size) << 6;
15963 inst.instruction |= do_align << 4;
15966 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15967 apart from bits [11:4]. */
15970 do_neon_ldx_stx (void)
15972 if (inst.operands[1].isreg)
15973 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15975 switch (NEON_LANE (inst.operands[0].imm))
15977 case NEON_INTERLEAVE_LANES:
15978 NEON_ENCODE (INTERLV, inst);
15979 do_neon_ld_st_interleave ();
15982 case NEON_ALL_LANES:
15983 NEON_ENCODE (DUP, inst);
15984 if (inst.instruction == N_INV)
15986 first_error ("only loads support such operands");
15993 NEON_ENCODE (LANE, inst);
15994 do_neon_ld_st_lane ();
15997 /* L bit comes from bit mask. */
15998 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15999 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16000 inst.instruction |= inst.operands[1].reg << 16;
16002 if (inst.operands[1].postind)
16004 int postreg = inst.operands[1].imm & 0xf;
16005 constraint (!inst.operands[1].immisreg,
16006 _("post-index must be a register"));
16007 constraint (postreg == 0xd || postreg == 0xf,
16008 _("bad register for post-index"));
16009 inst.instruction |= postreg;
16013 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16014 constraint (inst.reloc.exp.X_op != O_constant
16015 || inst.reloc.exp.X_add_number != 0,
16018 if (inst.operands[1].writeback)
16020 inst.instruction |= 0xd;
16023 inst.instruction |= 0xf;
16027 inst.instruction |= 0xf9000000;
16029 inst.instruction |= 0xf4000000;
16034 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16036 NEON_ENCODE (FPV8, inst);
16039 do_vfp_sp_dyadic ();
16041 do_vfp_dp_rd_rn_rm ();
16044 inst.instruction |= 0x100;
16046 inst.instruction |= 0xf0000000;
16052 set_it_insn_type (OUTSIDE_IT_INSN);
16054 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16055 first_error (_("invalid instruction shape"));
16061 set_it_insn_type (OUTSIDE_IT_INSN);
16063 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16066 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16069 neon_dyadic_misc (NT_untyped, N_F32, 0);
16073 do_vrint_1 (enum neon_cvt_mode mode)
16075 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16076 struct neon_type_el et;
16081 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16082 if (et.type != NT_invtype)
16084 /* VFP encodings. */
16085 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16086 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16087 set_it_insn_type (OUTSIDE_IT_INSN);
16089 NEON_ENCODE (FPV8, inst);
16091 do_vfp_sp_monadic ();
16093 do_vfp_dp_rd_rm ();
16097 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16098 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16099 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16100 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16101 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16102 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16103 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16107 inst.instruction |= (rs == NS_DD) << 8;
16108 do_vfp_cond_or_thumb ();
16112 /* Neon encodings (or something broken...). */
16114 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16116 if (et.type == NT_invtype)
16119 set_it_insn_type (OUTSIDE_IT_INSN);
16120 NEON_ENCODE (FLOAT, inst);
16122 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16125 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16126 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16127 inst.instruction |= LOW4 (inst.operands[1].reg);
16128 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16129 inst.instruction |= neon_quad (rs) << 6;
16132 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16133 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16134 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16135 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16136 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16137 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16138 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16143 inst.instruction |= 0xfc000000;
16145 inst.instruction |= 0xf0000000;
16152 do_vrint_1 (neon_cvt_mode_x);
16158 do_vrint_1 (neon_cvt_mode_z);
16164 do_vrint_1 (neon_cvt_mode_r);
16170 do_vrint_1 (neon_cvt_mode_a);
16176 do_vrint_1 (neon_cvt_mode_n);
16182 do_vrint_1 (neon_cvt_mode_p);
16188 do_vrint_1 (neon_cvt_mode_m);
16191 /* Crypto v1 instructions. */
16193 do_crypto_2op_1 (unsigned elttype, int op)
16195 set_it_insn_type (OUTSIDE_IT_INSN);
16197 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16203 NEON_ENCODE (INTEGER, inst);
16204 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16205 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16206 inst.instruction |= LOW4 (inst.operands[1].reg);
16207 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16209 inst.instruction |= op << 6;
16212 inst.instruction |= 0xfc000000;
16214 inst.instruction |= 0xf0000000;
16218 do_crypto_3op_1 (int u, int op)
16220 set_it_insn_type (OUTSIDE_IT_INSN);
16222 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16223 N_32 | N_UNT | N_KEY).type == NT_invtype)
16228 NEON_ENCODE (INTEGER, inst);
16229 neon_three_same (1, u, 8 << op);
16235 do_crypto_2op_1 (N_8, 0);
16241 do_crypto_2op_1 (N_8, 1);
16247 do_crypto_2op_1 (N_8, 2);
16253 do_crypto_2op_1 (N_8, 3);
16259 do_crypto_3op_1 (0, 0);
16265 do_crypto_3op_1 (0, 1);
16271 do_crypto_3op_1 (0, 2);
16277 do_crypto_3op_1 (0, 3);
16283 do_crypto_3op_1 (1, 0);
16289 do_crypto_3op_1 (1, 1);
16293 do_sha256su1 (void)
16295 do_crypto_3op_1 (1, 2);
16301 do_crypto_2op_1 (N_32, -1);
16307 do_crypto_2op_1 (N_32, 0);
16311 do_sha256su0 (void)
16313 do_crypto_2op_1 (N_32, 1);
16317 do_crc32_1 (unsigned int poly, unsigned int sz)
16319 unsigned int Rd = inst.operands[0].reg;
16320 unsigned int Rn = inst.operands[1].reg;
16321 unsigned int Rm = inst.operands[2].reg;
16323 set_it_insn_type (OUTSIDE_IT_INSN);
16324 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16325 inst.instruction |= LOW4 (Rn) << 16;
16326 inst.instruction |= LOW4 (Rm);
16327 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16328 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16330 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16331 as_warn (UNPRED_REG ("r15"));
16332 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16333 as_warn (UNPRED_REG ("r13"));
16373 /* Overall per-instruction processing. */
16375 /* We need to be able to fix up arbitrary expressions in some statements.
16376 This is so that we can handle symbols that are an arbitrary distance from
16377 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16378 which returns part of an address in a form which will be valid for
16379 a data instruction. We do this by pushing the expression into a symbol
16380 in the expr_section, and creating a fix for that. */
16383 fix_new_arm (fragS * frag,
16397 /* Create an absolute valued symbol, so we have something to
16398 refer to in the object file. Unfortunately for us, gas's
16399 generic expression parsing will already have folded out
16400 any use of .set foo/.type foo %function that may have
16401 been used to set type information of the target location,
16402 that's being specified symbolically. We have to presume
16403 the user knows what they are doing. */
16407 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16409 symbol = symbol_find_or_make (name);
16410 S_SET_SEGMENT (symbol, absolute_section);
16411 symbol_set_frag (symbol, &zero_address_frag);
16412 S_SET_VALUE (symbol, exp->X_add_number);
16413 exp->X_op = O_symbol;
16414 exp->X_add_symbol = symbol;
16415 exp->X_add_number = 0;
16421 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16422 (enum bfd_reloc_code_real) reloc);
16426 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16427 pc_rel, (enum bfd_reloc_code_real) reloc);
16431 /* Mark whether the fix is to a THUMB instruction, or an ARM
16433 new_fix->tc_fix_data = thumb_mode;
16436 /* Create a frg for an instruction requiring relaxation. */
16438 output_relax_insn (void)
16444 /* The size of the instruction is unknown, so tie the debug info to the
16445 start of the instruction. */
16446 dwarf2_emit_insn (0);
16448 switch (inst.reloc.exp.X_op)
16451 sym = inst.reloc.exp.X_add_symbol;
16452 offset = inst.reloc.exp.X_add_number;
16456 offset = inst.reloc.exp.X_add_number;
16459 sym = make_expr_symbol (&inst.reloc.exp);
16463 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16464 inst.relax, sym, offset, NULL/*offset, opcode*/);
16465 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16468 /* Write a 32-bit thumb instruction to buf. */
16470 put_thumb32_insn (char * buf, unsigned long insn)
16472 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16473 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16477 output_inst (const char * str)
16483 as_bad ("%s -- `%s'", inst.error, str);
16488 output_relax_insn ();
16491 if (inst.size == 0)
16494 to = frag_more (inst.size);
16495 /* PR 9814: Record the thumb mode into the current frag so that we know
16496 what type of NOP padding to use, if necessary. We override any previous
16497 setting so that if the mode has changed then the NOPS that we use will
16498 match the encoding of the last instruction in the frag. */
16499 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16501 if (thumb_mode && (inst.size > THUMB_SIZE))
16503 gas_assert (inst.size == (2 * THUMB_SIZE));
16504 put_thumb32_insn (to, inst.instruction);
16506 else if (inst.size > INSN_SIZE)
16508 gas_assert (inst.size == (2 * INSN_SIZE));
16509 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16510 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16513 md_number_to_chars (to, inst.instruction, inst.size);
16515 if (inst.reloc.type != BFD_RELOC_UNUSED)
16516 fix_new_arm (frag_now, to - frag_now->fr_literal,
16517 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16520 dwarf2_emit_insn (inst.size);
16524 output_it_inst (int cond, int mask, char * to)
16526 unsigned long instruction = 0xbf00;
16529 instruction |= mask;
16530 instruction |= cond << 4;
16534 to = frag_more (2);
16536 dwarf2_emit_insn (2);
16540 md_number_to_chars (to, instruction, 2);
16545 /* Tag values used in struct asm_opcode's tag field. */
16548 OT_unconditional, /* Instruction cannot be conditionalized.
16549 The ARM condition field is still 0xE. */
16550 OT_unconditionalF, /* Instruction cannot be conditionalized
16551 and carries 0xF in its ARM condition field. */
16552 OT_csuffix, /* Instruction takes a conditional suffix. */
16553 OT_csuffixF, /* Some forms of the instruction take a conditional
16554 suffix, others place 0xF where the condition field
16556 OT_cinfix3, /* Instruction takes a conditional infix,
16557 beginning at character index 3. (In
16558 unified mode, it becomes a suffix.) */
16559 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16560 tsts, cmps, cmns, and teqs. */
16561 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16562 character index 3, even in unified mode. Used for
16563 legacy instructions where suffix and infix forms
16564 may be ambiguous. */
16565 OT_csuf_or_in3, /* Instruction takes either a conditional
16566 suffix or an infix at character index 3. */
16567 OT_odd_infix_unc, /* This is the unconditional variant of an
16568 instruction that takes a conditional infix
16569 at an unusual position. In unified mode,
16570 this variant will accept a suffix. */
16571 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16572 are the conditional variants of instructions that
16573 take conditional infixes in unusual positions.
16574 The infix appears at character index
16575 (tag - OT_odd_infix_0). These are not accepted
16576 in unified mode. */
16579 /* Subroutine of md_assemble, responsible for looking up the primary
16580 opcode from the mnemonic the user wrote. STR points to the
16581 beginning of the mnemonic.
16583 This is not simply a hash table lookup, because of conditional
16584 variants. Most instructions have conditional variants, which are
16585 expressed with a _conditional affix_ to the mnemonic. If we were
16586 to encode each conditional variant as a literal string in the opcode
16587 table, it would have approximately 20,000 entries.
16589 Most mnemonics take this affix as a suffix, and in unified syntax,
16590 'most' is upgraded to 'all'. However, in the divided syntax, some
16591 instructions take the affix as an infix, notably the s-variants of
16592 the arithmetic instructions. Of those instructions, all but six
16593 have the infix appear after the third character of the mnemonic.
16595 Accordingly, the algorithm for looking up primary opcodes given
16598 1. Look up the identifier in the opcode table.
16599 If we find a match, go to step U.
16601 2. Look up the last two characters of the identifier in the
16602 conditions table. If we find a match, look up the first N-2
16603 characters of the identifier in the opcode table. If we
16604 find a match, go to step CE.
16606 3. Look up the fourth and fifth characters of the identifier in
16607 the conditions table. If we find a match, extract those
16608 characters from the identifier, and look up the remaining
16609 characters in the opcode table. If we find a match, go
16614 U. Examine the tag field of the opcode structure, in case this is
16615 one of the six instructions with its conditional infix in an
16616 unusual place. If it is, the tag tells us where to find the
16617 infix; look it up in the conditions table and set inst.cond
16618 accordingly. Otherwise, this is an unconditional instruction.
16619 Again set inst.cond accordingly. Return the opcode structure.
16621 CE. Examine the tag field to make sure this is an instruction that
16622 should receive a conditional suffix. If it is not, fail.
16623 Otherwise, set inst.cond from the suffix we already looked up,
16624 and return the opcode structure.
16626 CM. Examine the tag field to make sure this is an instruction that
16627 should receive a conditional infix after the third character.
16628 If it is not, fail. Otherwise, undo the edits to the current
16629 line of input and proceed as for case CE. */
16631 static const struct asm_opcode *
16632 opcode_lookup (char **str)
16636 const struct asm_opcode *opcode;
16637 const struct asm_cond *cond;
16640 /* Scan up to the end of the mnemonic, which must end in white space,
16641 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16642 for (base = end = *str; *end != '\0'; end++)
16643 if (*end == ' ' || *end == '.')
16649 /* Handle a possible width suffix and/or Neon type suffix. */
16654 /* The .w and .n suffixes are only valid if the unified syntax is in
16656 if (unified_syntax && end[1] == 'w')
16658 else if (unified_syntax && end[1] == 'n')
16663 inst.vectype.elems = 0;
16665 *str = end + offset;
16667 if (end[offset] == '.')
16669 /* See if we have a Neon type suffix (possible in either unified or
16670 non-unified ARM syntax mode). */
16671 if (parse_neon_type (&inst.vectype, str) == FAIL)
16674 else if (end[offset] != '\0' && end[offset] != ' ')
16680 /* Look for unaffixed or special-case affixed mnemonic. */
16681 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16686 if (opcode->tag < OT_odd_infix_0)
16688 inst.cond = COND_ALWAYS;
16692 if (warn_on_deprecated && unified_syntax)
16693 as_warn (_("conditional infixes are deprecated in unified syntax"));
16694 affix = base + (opcode->tag - OT_odd_infix_0);
16695 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16698 inst.cond = cond->value;
16702 /* Cannot have a conditional suffix on a mnemonic of less than two
16704 if (end - base < 3)
16707 /* Look for suffixed mnemonic. */
16709 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16710 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16712 if (opcode && cond)
16715 switch (opcode->tag)
16717 case OT_cinfix3_legacy:
16718 /* Ignore conditional suffixes matched on infix only mnemonics. */
16722 case OT_cinfix3_deprecated:
16723 case OT_odd_infix_unc:
16724 if (!unified_syntax)
16726 /* else fall through */
16730 case OT_csuf_or_in3:
16731 inst.cond = cond->value;
16734 case OT_unconditional:
16735 case OT_unconditionalF:
16737 inst.cond = cond->value;
16740 /* Delayed diagnostic. */
16741 inst.error = BAD_COND;
16742 inst.cond = COND_ALWAYS;
16751 /* Cannot have a usual-position infix on a mnemonic of less than
16752 six characters (five would be a suffix). */
16753 if (end - base < 6)
16756 /* Look for infixed mnemonic in the usual position. */
16758 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16762 memcpy (save, affix, 2);
16763 memmove (affix, affix + 2, (end - affix) - 2);
16764 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16766 memmove (affix + 2, affix, (end - affix) - 2);
16767 memcpy (affix, save, 2);
16770 && (opcode->tag == OT_cinfix3
16771 || opcode->tag == OT_cinfix3_deprecated
16772 || opcode->tag == OT_csuf_or_in3
16773 || opcode->tag == OT_cinfix3_legacy))
16776 if (warn_on_deprecated && unified_syntax
16777 && (opcode->tag == OT_cinfix3
16778 || opcode->tag == OT_cinfix3_deprecated))
16779 as_warn (_("conditional infixes are deprecated in unified syntax"));
16781 inst.cond = cond->value;
16788 /* This function generates an initial IT instruction, leaving its block
16789 virtually open for the new instructions. Eventually,
16790 the mask will be updated by now_it_add_mask () each time
16791 a new instruction needs to be included in the IT block.
16792 Finally, the block is closed with close_automatic_it_block ().
16793 The block closure can be requested either from md_assemble (),
16794 a tencode (), or due to a label hook. */
16797 new_automatic_it_block (int cond)
16799 now_it.state = AUTOMATIC_IT_BLOCK;
16800 now_it.mask = 0x18;
16802 now_it.block_length = 1;
16803 mapping_state (MAP_THUMB);
16804 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16805 now_it.warn_deprecated = FALSE;
16806 now_it.insn_cond = TRUE;
16809 /* Close an automatic IT block.
16810 See comments in new_automatic_it_block (). */
16813 close_automatic_it_block (void)
16815 now_it.mask = 0x10;
16816 now_it.block_length = 0;
16819 /* Update the mask of the current automatically-generated IT
16820 instruction. See comments in new_automatic_it_block (). */
16823 now_it_add_mask (int cond)
16825 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16826 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16827 | ((bitvalue) << (nbit)))
16828 const int resulting_bit = (cond & 1);
16830 now_it.mask &= 0xf;
16831 now_it.mask = SET_BIT_VALUE (now_it.mask,
16833 (5 - now_it.block_length));
16834 now_it.mask = SET_BIT_VALUE (now_it.mask,
16836 ((5 - now_it.block_length) - 1) );
16837 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16840 #undef SET_BIT_VALUE
16843 /* The IT blocks handling machinery is accessed through the these functions:
16844 it_fsm_pre_encode () from md_assemble ()
16845 set_it_insn_type () optional, from the tencode functions
16846 set_it_insn_type_last () ditto
16847 in_it_block () ditto
16848 it_fsm_post_encode () from md_assemble ()
16849 force_automatic_it_block_close () from label habdling functions
16852 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16853 initializing the IT insn type with a generic initial value depending
16854 on the inst.condition.
16855 2) During the tencode function, two things may happen:
16856 a) The tencode function overrides the IT insn type by
16857 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16858 b) The tencode function queries the IT block state by
16859 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16861 Both set_it_insn_type and in_it_block run the internal FSM state
16862 handling function (handle_it_state), because: a) setting the IT insn
16863 type may incur in an invalid state (exiting the function),
16864 and b) querying the state requires the FSM to be updated.
16865 Specifically we want to avoid creating an IT block for conditional
16866 branches, so it_fsm_pre_encode is actually a guess and we can't
16867 determine whether an IT block is required until the tencode () routine
16868 has decided what type of instruction this actually it.
16869 Because of this, if set_it_insn_type and in_it_block have to be used,
16870 set_it_insn_type has to be called first.
16872 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16873 determines the insn IT type depending on the inst.cond code.
16874 When a tencode () routine encodes an instruction that can be
16875 either outside an IT block, or, in the case of being inside, has to be
16876 the last one, set_it_insn_type_last () will determine the proper
16877 IT instruction type based on the inst.cond code. Otherwise,
16878 set_it_insn_type can be called for overriding that logic or
16879 for covering other cases.
16881 Calling handle_it_state () may not transition the IT block state to
16882 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16883 still queried. Instead, if the FSM determines that the state should
16884 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16885 after the tencode () function: that's what it_fsm_post_encode () does.
16887 Since in_it_block () calls the state handling function to get an
16888 updated state, an error may occur (due to invalid insns combination).
16889 In that case, inst.error is set.
16890 Therefore, inst.error has to be checked after the execution of
16891 the tencode () routine.
16893 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16894 any pending state change (if any) that didn't take place in
16895 handle_it_state () as explained above. */
16898 it_fsm_pre_encode (void)
16900 if (inst.cond != COND_ALWAYS)
16901 inst.it_insn_type = INSIDE_IT_INSN;
16903 inst.it_insn_type = OUTSIDE_IT_INSN;
16905 now_it.state_handled = 0;
16908 /* IT state FSM handling function. */
16911 handle_it_state (void)
16913 now_it.state_handled = 1;
16914 now_it.insn_cond = FALSE;
16916 switch (now_it.state)
16918 case OUTSIDE_IT_BLOCK:
16919 switch (inst.it_insn_type)
16921 case OUTSIDE_IT_INSN:
16924 case INSIDE_IT_INSN:
16925 case INSIDE_IT_LAST_INSN:
16926 if (thumb_mode == 0)
16929 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16930 as_tsktsk (_("Warning: conditional outside an IT block"\
16935 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16936 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16938 /* Automatically generate the IT instruction. */
16939 new_automatic_it_block (inst.cond);
16940 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16941 close_automatic_it_block ();
16945 inst.error = BAD_OUT_IT;
16951 case IF_INSIDE_IT_LAST_INSN:
16952 case NEUTRAL_IT_INSN:
16956 now_it.state = MANUAL_IT_BLOCK;
16957 now_it.block_length = 0;
16962 case AUTOMATIC_IT_BLOCK:
16963 /* Three things may happen now:
16964 a) We should increment current it block size;
16965 b) We should close current it block (closing insn or 4 insns);
16966 c) We should close current it block and start a new one (due
16967 to incompatible conditions or
16968 4 insns-length block reached). */
16970 switch (inst.it_insn_type)
16972 case OUTSIDE_IT_INSN:
16973 /* The closure of the block shall happen immediatelly,
16974 so any in_it_block () call reports the block as closed. */
16975 force_automatic_it_block_close ();
16978 case INSIDE_IT_INSN:
16979 case INSIDE_IT_LAST_INSN:
16980 case IF_INSIDE_IT_LAST_INSN:
16981 now_it.block_length++;
16983 if (now_it.block_length > 4
16984 || !now_it_compatible (inst.cond))
16986 force_automatic_it_block_close ();
16987 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16988 new_automatic_it_block (inst.cond);
16992 now_it.insn_cond = TRUE;
16993 now_it_add_mask (inst.cond);
16996 if (now_it.state == AUTOMATIC_IT_BLOCK
16997 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16998 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16999 close_automatic_it_block ();
17002 case NEUTRAL_IT_INSN:
17003 now_it.block_length++;
17004 now_it.insn_cond = TRUE;
17006 if (now_it.block_length > 4)
17007 force_automatic_it_block_close ();
17009 now_it_add_mask (now_it.cc & 1);
17013 close_automatic_it_block ();
17014 now_it.state = MANUAL_IT_BLOCK;
17019 case MANUAL_IT_BLOCK:
17021 /* Check conditional suffixes. */
17022 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17025 now_it.mask &= 0x1f;
17026 is_last = (now_it.mask == 0x10);
17027 now_it.insn_cond = TRUE;
17029 switch (inst.it_insn_type)
17031 case OUTSIDE_IT_INSN:
17032 inst.error = BAD_NOT_IT;
17035 case INSIDE_IT_INSN:
17036 if (cond != inst.cond)
17038 inst.error = BAD_IT_COND;
17043 case INSIDE_IT_LAST_INSN:
17044 case IF_INSIDE_IT_LAST_INSN:
17045 if (cond != inst.cond)
17047 inst.error = BAD_IT_COND;
17052 inst.error = BAD_BRANCH;
17057 case NEUTRAL_IT_INSN:
17058 /* The BKPT instruction is unconditional even in an IT block. */
17062 inst.error = BAD_IT_IT;
17072 struct depr_insn_mask
17074 unsigned long pattern;
17075 unsigned long mask;
17076 const char* description;
17079 /* List of 16-bit instruction patterns deprecated in an IT block in
17081 static const struct depr_insn_mask depr_it_insns[] = {
17082 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17083 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17084 { 0xa000, 0xb800, N_("ADR") },
17085 { 0x4800, 0xf800, N_("Literal loads") },
17086 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17087 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17092 it_fsm_post_encode (void)
17096 if (!now_it.state_handled)
17097 handle_it_state ();
17099 if (now_it.insn_cond
17100 && !now_it.warn_deprecated
17101 && warn_on_deprecated
17102 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17104 if (inst.instruction >= 0x10000)
17106 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17107 "deprecated in ARMv8"));
17108 now_it.warn_deprecated = TRUE;
17112 const struct depr_insn_mask *p = depr_it_insns;
17114 while (p->mask != 0)
17116 if ((inst.instruction & p->mask) == p->pattern)
17118 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17119 "of the following class are deprecated in ARMv8: "
17120 "%s"), p->description);
17121 now_it.warn_deprecated = TRUE;
17129 if (now_it.block_length > 1)
17131 as_warn (_("IT blocks containing more than one conditional "
17132 "instruction are deprecated in ARMv8"));
17133 now_it.warn_deprecated = TRUE;
17137 is_last = (now_it.mask == 0x10);
17140 now_it.state = OUTSIDE_IT_BLOCK;
17146 force_automatic_it_block_close (void)
17148 if (now_it.state == AUTOMATIC_IT_BLOCK)
17150 close_automatic_it_block ();
17151 now_it.state = OUTSIDE_IT_BLOCK;
17159 if (!now_it.state_handled)
17160 handle_it_state ();
17162 return now_it.state != OUTSIDE_IT_BLOCK;
17166 md_assemble (char *str)
17169 const struct asm_opcode * opcode;
17171 /* Align the previous label if needed. */
17172 if (last_label_seen != NULL)
17174 symbol_set_frag (last_label_seen, frag_now);
17175 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17176 S_SET_SEGMENT (last_label_seen, now_seg);
17179 memset (&inst, '\0', sizeof (inst));
17180 inst.reloc.type = BFD_RELOC_UNUSED;
17182 opcode = opcode_lookup (&p);
17185 /* It wasn't an instruction, but it might be a register alias of
17186 the form alias .req reg, or a Neon .dn/.qn directive. */
17187 if (! create_register_alias (str, p)
17188 && ! create_neon_reg_alias (str, p))
17189 as_bad (_("bad instruction `%s'"), str);
17194 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17195 as_warn (_("s suffix on comparison instruction is deprecated"));
17197 /* The value which unconditional instructions should have in place of the
17198 condition field. */
17199 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17203 arm_feature_set variant;
17205 variant = cpu_variant;
17206 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17207 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17208 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17209 /* Check that this instruction is supported for this CPU. */
17210 if (!opcode->tvariant
17211 || (thumb_mode == 1
17212 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17214 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17217 if (inst.cond != COND_ALWAYS && !unified_syntax
17218 && opcode->tencode != do_t_branch)
17220 as_bad (_("Thumb does not support conditional execution"));
17224 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17226 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17227 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17228 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17230 /* Two things are addressed here.
17231 1) Implicit require narrow instructions on Thumb-1.
17232 This avoids relaxation accidentally introducing Thumb-2
17234 2) Reject wide instructions in non Thumb-2 cores. */
17235 if (inst.size_req == 0)
17237 else if (inst.size_req == 4)
17239 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17245 inst.instruction = opcode->tvalue;
17247 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17249 /* Prepare the it_insn_type for those encodings that don't set
17251 it_fsm_pre_encode ();
17253 opcode->tencode ();
17255 it_fsm_post_encode ();
17258 if (!(inst.error || inst.relax))
17260 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17261 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17262 if (inst.size_req && inst.size_req != inst.size)
17264 as_bad (_("cannot honor width suffix -- `%s'"), str);
17269 /* Something has gone badly wrong if we try to relax a fixed size
17271 gas_assert (inst.size_req == 0 || !inst.relax);
17273 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17274 *opcode->tvariant);
17275 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17276 set those bits when Thumb-2 32-bit instructions are seen. ie.
17277 anything other than bl/blx and v6-M instructions.
17278 This is overly pessimistic for relaxable instructions. */
17279 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17281 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17282 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17283 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17286 check_neon_suffixes;
17290 mapping_state (MAP_THUMB);
17293 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17297 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17298 is_bx = (opcode->aencode == do_bx);
17300 /* Check that this instruction is supported for this CPU. */
17301 if (!(is_bx && fix_v4bx)
17302 && !(opcode->avariant &&
17303 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17305 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17310 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17314 inst.instruction = opcode->avalue;
17315 if (opcode->tag == OT_unconditionalF)
17316 inst.instruction |= 0xF << 28;
17318 inst.instruction |= inst.cond << 28;
17319 inst.size = INSN_SIZE;
17320 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17322 it_fsm_pre_encode ();
17323 opcode->aencode ();
17324 it_fsm_post_encode ();
17326 /* Arm mode bx is marked as both v4T and v5 because it's still required
17327 on a hypothetical non-thumb v5 core. */
17329 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17331 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17332 *opcode->avariant);
17334 check_neon_suffixes;
17338 mapping_state (MAP_ARM);
17343 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17351 check_it_blocks_finished (void)
17356 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17357 if (seg_info (sect)->tc_segment_info_data.current_it.state
17358 == MANUAL_IT_BLOCK)
17360 as_warn (_("section '%s' finished with an open IT block."),
17364 if (now_it.state == MANUAL_IT_BLOCK)
17365 as_warn (_("file finished with an open IT block."));
17369 /* Various frobbings of labels and their addresses. */
17372 arm_start_line_hook (void)
17374 last_label_seen = NULL;
17378 arm_frob_label (symbolS * sym)
17380 last_label_seen = sym;
17382 ARM_SET_THUMB (sym, thumb_mode);
17384 #if defined OBJ_COFF || defined OBJ_ELF
17385 ARM_SET_INTERWORK (sym, support_interwork);
17388 force_automatic_it_block_close ();
17390 /* Note - do not allow local symbols (.Lxxx) to be labelled
17391 as Thumb functions. This is because these labels, whilst
17392 they exist inside Thumb code, are not the entry points for
17393 possible ARM->Thumb calls. Also, these labels can be used
17394 as part of a computed goto or switch statement. eg gcc
17395 can generate code that looks like this:
17397 ldr r2, [pc, .Laaa]
17407 The first instruction loads the address of the jump table.
17408 The second instruction converts a table index into a byte offset.
17409 The third instruction gets the jump address out of the table.
17410 The fourth instruction performs the jump.
17412 If the address stored at .Laaa is that of a symbol which has the
17413 Thumb_Func bit set, then the linker will arrange for this address
17414 to have the bottom bit set, which in turn would mean that the
17415 address computation performed by the third instruction would end
17416 up with the bottom bit set. Since the ARM is capable of unaligned
17417 word loads, the instruction would then load the incorrect address
17418 out of the jump table, and chaos would ensue. */
17419 if (label_is_thumb_function_name
17420 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17421 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17423 /* When the address of a Thumb function is taken the bottom
17424 bit of that address should be set. This will allow
17425 interworking between Arm and Thumb functions to work
17428 THUMB_SET_FUNC (sym, 1);
17430 label_is_thumb_function_name = FALSE;
17433 dwarf2_emit_label (sym);
17437 arm_data_in_code (void)
17439 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17441 *input_line_pointer = '/';
17442 input_line_pointer += 5;
17443 *input_line_pointer = 0;
17451 arm_canonicalize_symbol_name (char * name)
17455 if (thumb_mode && (len = strlen (name)) > 5
17456 && streq (name + len - 5, "/data"))
17457 *(name + len - 5) = 0;
17462 /* Table of all register names defined by default. The user can
17463 define additional names with .req. Note that all register names
17464 should appear in both upper and lowercase variants. Some registers
17465 also have mixed-case names. */
17467 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17468 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17469 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17470 #define REGSET(p,t) \
17471 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17472 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17473 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17474 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17475 #define REGSETH(p,t) \
17476 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17477 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17478 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17479 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17480 #define REGSET2(p,t) \
17481 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17482 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17483 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17484 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17485 #define SPLRBANK(base,bank,t) \
17486 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17487 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17488 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17489 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17490 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17491 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17493 static const struct reg_entry reg_names[] =
17495 /* ARM integer registers. */
17496 REGSET(r, RN), REGSET(R, RN),
17498 /* ATPCS synonyms. */
17499 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17500 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17501 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17503 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17504 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17505 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17507 /* Well-known aliases. */
17508 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17509 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17511 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17512 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17514 /* Coprocessor numbers. */
17515 REGSET(p, CP), REGSET(P, CP),
17517 /* Coprocessor register numbers. The "cr" variants are for backward
17519 REGSET(c, CN), REGSET(C, CN),
17520 REGSET(cr, CN), REGSET(CR, CN),
17522 /* ARM banked registers. */
17523 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17524 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17525 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17526 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17527 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17528 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17529 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17531 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17532 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17533 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17534 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17535 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17536 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17537 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17538 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17540 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17541 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17542 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17543 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17544 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17545 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17546 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17547 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17548 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17550 /* FPA registers. */
17551 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17552 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17554 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17555 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17557 /* VFP SP registers. */
17558 REGSET(s,VFS), REGSET(S,VFS),
17559 REGSETH(s,VFS), REGSETH(S,VFS),
17561 /* VFP DP Registers. */
17562 REGSET(d,VFD), REGSET(D,VFD),
17563 /* Extra Neon DP registers. */
17564 REGSETH(d,VFD), REGSETH(D,VFD),
17566 /* Neon QP registers. */
17567 REGSET2(q,NQ), REGSET2(Q,NQ),
17569 /* VFP control registers. */
17570 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17571 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17572 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17573 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17574 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17575 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17577 /* Maverick DSP coprocessor registers. */
17578 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17579 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17581 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17582 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17583 REGDEF(dspsc,0,DSPSC),
17585 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17586 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17587 REGDEF(DSPSC,0,DSPSC),
17589 /* iWMMXt data registers - p0, c0-15. */
17590 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17592 /* iWMMXt control registers - p1, c0-3. */
17593 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17594 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17595 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17596 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17598 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17599 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17600 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17601 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17602 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17604 /* XScale accumulator registers. */
17605 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17611 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17612 within psr_required_here. */
17613 static const struct asm_psr psrs[] =
17615 /* Backward compatibility notation. Note that "all" is no longer
17616 truly all possible PSR bits. */
17617 {"all", PSR_c | PSR_f},
17621 /* Individual flags. */
17627 /* Combinations of flags. */
17628 {"fs", PSR_f | PSR_s},
17629 {"fx", PSR_f | PSR_x},
17630 {"fc", PSR_f | PSR_c},
17631 {"sf", PSR_s | PSR_f},
17632 {"sx", PSR_s | PSR_x},
17633 {"sc", PSR_s | PSR_c},
17634 {"xf", PSR_x | PSR_f},
17635 {"xs", PSR_x | PSR_s},
17636 {"xc", PSR_x | PSR_c},
17637 {"cf", PSR_c | PSR_f},
17638 {"cs", PSR_c | PSR_s},
17639 {"cx", PSR_c | PSR_x},
17640 {"fsx", PSR_f | PSR_s | PSR_x},
17641 {"fsc", PSR_f | PSR_s | PSR_c},
17642 {"fxs", PSR_f | PSR_x | PSR_s},
17643 {"fxc", PSR_f | PSR_x | PSR_c},
17644 {"fcs", PSR_f | PSR_c | PSR_s},
17645 {"fcx", PSR_f | PSR_c | PSR_x},
17646 {"sfx", PSR_s | PSR_f | PSR_x},
17647 {"sfc", PSR_s | PSR_f | PSR_c},
17648 {"sxf", PSR_s | PSR_x | PSR_f},
17649 {"sxc", PSR_s | PSR_x | PSR_c},
17650 {"scf", PSR_s | PSR_c | PSR_f},
17651 {"scx", PSR_s | PSR_c | PSR_x},
17652 {"xfs", PSR_x | PSR_f | PSR_s},
17653 {"xfc", PSR_x | PSR_f | PSR_c},
17654 {"xsf", PSR_x | PSR_s | PSR_f},
17655 {"xsc", PSR_x | PSR_s | PSR_c},
17656 {"xcf", PSR_x | PSR_c | PSR_f},
17657 {"xcs", PSR_x | PSR_c | PSR_s},
17658 {"cfs", PSR_c | PSR_f | PSR_s},
17659 {"cfx", PSR_c | PSR_f | PSR_x},
17660 {"csf", PSR_c | PSR_s | PSR_f},
17661 {"csx", PSR_c | PSR_s | PSR_x},
17662 {"cxf", PSR_c | PSR_x | PSR_f},
17663 {"cxs", PSR_c | PSR_x | PSR_s},
17664 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17665 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17666 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17667 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17668 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17669 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17670 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17671 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17672 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17673 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17674 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17675 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17676 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17677 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17678 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17679 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17680 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17681 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17682 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17683 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17684 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17685 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17686 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17687 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17690 /* Table of V7M psr names. */
17691 static const struct asm_psr v7m_psrs[] =
17693 {"apsr", 0 }, {"APSR", 0 },
17694 {"iapsr", 1 }, {"IAPSR", 1 },
17695 {"eapsr", 2 }, {"EAPSR", 2 },
17696 {"psr", 3 }, {"PSR", 3 },
17697 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17698 {"ipsr", 5 }, {"IPSR", 5 },
17699 {"epsr", 6 }, {"EPSR", 6 },
17700 {"iepsr", 7 }, {"IEPSR", 7 },
17701 {"msp", 8 }, {"MSP", 8 },
17702 {"psp", 9 }, {"PSP", 9 },
17703 {"primask", 16}, {"PRIMASK", 16},
17704 {"basepri", 17}, {"BASEPRI", 17},
17705 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17706 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17707 {"faultmask", 19}, {"FAULTMASK", 19},
17708 {"control", 20}, {"CONTROL", 20}
17711 /* Table of all shift-in-operand names. */
17712 static const struct asm_shift_name shift_names [] =
17714 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17715 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17716 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17717 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17718 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17719 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17722 /* Table of all explicit relocation names. */
17724 static struct reloc_entry reloc_names[] =
17726 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17727 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17728 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17729 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17730 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17731 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17732 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17733 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17734 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17735 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17736 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17737 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17738 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17739 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17740 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17741 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17742 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17743 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17747 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17748 static const struct asm_cond conds[] =
17752 {"cs", 0x2}, {"hs", 0x2},
17753 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17767 #define UL_BARRIER(L,U,CODE,FEAT) \
17768 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17769 { U, CODE, ARM_FEATURE (FEAT, 0) }
17771 static struct asm_barrier_opt barrier_opt_names[] =
17773 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17774 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17775 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17776 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17777 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17778 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17779 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17780 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17781 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17782 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17783 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17784 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17785 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17786 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17787 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17788 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17793 /* Table of ARM-format instructions. */
17795 /* Macros for gluing together operand strings. N.B. In all cases
17796 other than OPS0, the trailing OP_stop comes from default
17797 zero-initialization of the unspecified elements of the array. */
17798 #define OPS0() { OP_stop, }
17799 #define OPS1(a) { OP_##a, }
17800 #define OPS2(a,b) { OP_##a,OP_##b, }
17801 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17802 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17803 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17804 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17806 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17807 This is useful when mixing operands for ARM and THUMB, i.e. using the
17808 MIX_ARM_THUMB_OPERANDS macro.
17809 In order to use these macros, prefix the number of operands with _
17811 #define OPS_1(a) { a, }
17812 #define OPS_2(a,b) { a,b, }
17813 #define OPS_3(a,b,c) { a,b,c, }
17814 #define OPS_4(a,b,c,d) { a,b,c,d, }
17815 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17816 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17818 /* These macros abstract out the exact format of the mnemonic table and
17819 save some repeated characters. */
17821 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17822 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17823 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17824 THUMB_VARIANT, do_##ae, do_##te }
17826 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17827 a T_MNEM_xyz enumerator. */
17828 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17829 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17830 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17831 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17833 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17834 infix after the third character. */
17835 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17836 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17837 THUMB_VARIANT, do_##ae, do_##te }
17838 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17839 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17840 THUMB_VARIANT, do_##ae, do_##te }
17841 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17842 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17843 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17844 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17845 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17846 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17847 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17848 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17850 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17851 field is still 0xE. Many of the Thumb variants can be executed
17852 conditionally, so this is checked separately. */
17853 #define TUE(mnem, op, top, nops, ops, ae, te) \
17854 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17855 THUMB_VARIANT, do_##ae, do_##te }
17857 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17858 Used by mnemonics that have very minimal differences in the encoding for
17859 ARM and Thumb variants and can be handled in a common function. */
17860 #define TUEc(mnem, op, top, nops, ops, en) \
17861 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17862 THUMB_VARIANT, do_##en, do_##en }
17864 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17865 condition code field. */
17866 #define TUF(mnem, op, top, nops, ops, ae, te) \
17867 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17868 THUMB_VARIANT, do_##ae, do_##te }
17870 /* ARM-only variants of all the above. */
17871 #define CE(mnem, op, nops, ops, ae) \
17872 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17874 #define C3(mnem, op, nops, ops, ae) \
17875 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17877 /* Legacy mnemonics that always have conditional infix after the third
17879 #define CL(mnem, op, nops, ops, ae) \
17880 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17881 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17883 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17884 #define cCE(mnem, op, nops, ops, ae) \
17885 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17887 /* Legacy coprocessor instructions where conditional infix and conditional
17888 suffix are ambiguous. For consistency this includes all FPA instructions,
17889 not just the potentially ambiguous ones. */
17890 #define cCL(mnem, op, nops, ops, ae) \
17891 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17892 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17894 /* Coprocessor, takes either a suffix or a position-3 infix
17895 (for an FPA corner case). */
17896 #define C3E(mnem, op, nops, ops, ae) \
17897 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17898 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17900 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17901 { m1 #m2 m3, OPS##nops ops, \
17902 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17903 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17905 #define CM(m1, m2, op, nops, ops, ae) \
17906 xCM_ (m1, , m2, op, nops, ops, ae), \
17907 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17908 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17909 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17910 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17911 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17912 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17913 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17914 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17915 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17916 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17917 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17918 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17919 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17920 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17921 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17922 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17923 xCM_ (m1, le, m2, op, nops, ops, ae), \
17924 xCM_ (m1, al, m2, op, nops, ops, ae)
17926 #define UE(mnem, op, nops, ops, ae) \
17927 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17929 #define UF(mnem, op, nops, ops, ae) \
17930 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17932 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17933 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17934 use the same encoding function for each. */
17935 #define NUF(mnem, op, nops, ops, enc) \
17936 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17937 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17939 /* Neon data processing, version which indirects through neon_enc_tab for
17940 the various overloaded versions of opcodes. */
17941 #define nUF(mnem, op, nops, ops, enc) \
17942 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17943 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17945 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17947 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17948 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17949 THUMB_VARIANT, do_##enc, do_##enc }
17951 #define NCE(mnem, op, nops, ops, enc) \
17952 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17954 #define NCEF(mnem, op, nops, ops, enc) \
17955 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17957 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17958 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17959 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17960 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17962 #define nCE(mnem, op, nops, ops, enc) \
17963 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17965 #define nCEF(mnem, op, nops, ops, enc) \
17966 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17970 static const struct asm_opcode insns[] =
17972 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17973 #define THUMB_VARIANT &arm_ext_v4t
17974 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17975 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17976 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17977 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17978 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17979 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17980 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17981 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17982 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17983 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17984 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17985 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17986 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17987 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17988 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17989 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17991 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17992 for setting PSR flag bits. They are obsolete in V6 and do not
17993 have Thumb equivalents. */
17994 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17995 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17996 CL("tstp", 110f000, 2, (RR, SH), cmp),
17997 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17998 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17999 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18000 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18001 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18002 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18004 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18005 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18006 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18007 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18009 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18010 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18011 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18013 OP_ADDRGLDR),ldst, t_ldst),
18014 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18016 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18017 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18018 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18019 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18020 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18021 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18023 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18024 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18025 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18026 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18029 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18030 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18031 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18033 /* Thumb-compatibility pseudo ops. */
18034 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18035 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18036 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18037 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18038 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18039 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18040 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18041 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18042 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18043 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18044 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18045 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18047 /* These may simplify to neg. */
18048 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18049 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18051 #undef THUMB_VARIANT
18052 #define THUMB_VARIANT & arm_ext_v6
18054 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18056 /* V1 instructions with no Thumb analogue prior to V6T2. */
18057 #undef THUMB_VARIANT
18058 #define THUMB_VARIANT & arm_ext_v6t2
18060 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18061 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18062 CL("teqp", 130f000, 2, (RR, SH), cmp),
18064 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18065 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18066 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18067 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18069 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18070 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18072 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18073 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18075 /* V1 instructions with no Thumb analogue at all. */
18076 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18077 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18079 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18080 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18081 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18082 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18083 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18084 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18085 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18086 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18089 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18090 #undef THUMB_VARIANT
18091 #define THUMB_VARIANT & arm_ext_v4t
18093 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18094 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18096 #undef THUMB_VARIANT
18097 #define THUMB_VARIANT & arm_ext_v6t2
18099 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18100 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18102 /* Generic coprocessor instructions. */
18103 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18104 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18105 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18106 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18107 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18108 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18109 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18112 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18114 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18115 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18118 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18119 #undef THUMB_VARIANT
18120 #define THUMB_VARIANT & arm_ext_msr
18122 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18123 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18126 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18127 #undef THUMB_VARIANT
18128 #define THUMB_VARIANT & arm_ext_v6t2
18130 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18131 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18132 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18133 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18134 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18135 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18136 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18137 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18140 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18141 #undef THUMB_VARIANT
18142 #define THUMB_VARIANT & arm_ext_v4t
18144 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18145 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18146 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18147 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18148 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18149 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18152 #define ARM_VARIANT & arm_ext_v4t_5
18154 /* ARM Architecture 4T. */
18155 /* Note: bx (and blx) are required on V5, even if the processor does
18156 not support Thumb. */
18157 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18160 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18161 #undef THUMB_VARIANT
18162 #define THUMB_VARIANT & arm_ext_v5t
18164 /* Note: blx has 2 variants; the .value coded here is for
18165 BLX(2). Only this variant has conditional execution. */
18166 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18167 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18169 #undef THUMB_VARIANT
18170 #define THUMB_VARIANT & arm_ext_v6t2
18172 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18173 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18174 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18175 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18176 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18177 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18178 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18179 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18182 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18183 #undef THUMB_VARIANT
18184 #define THUMB_VARIANT &arm_ext_v5exp
18186 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18187 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18188 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18189 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18191 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18192 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18194 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18195 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18196 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18197 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18199 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18200 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18201 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18202 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18204 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18205 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18207 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18208 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18209 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18210 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18213 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18214 #undef THUMB_VARIANT
18215 #define THUMB_VARIANT &arm_ext_v6t2
18217 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18218 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18220 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18221 ADDRGLDRS), ldrd, t_ldstd),
18223 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18224 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18227 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18229 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18232 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18233 #undef THUMB_VARIANT
18234 #define THUMB_VARIANT & arm_ext_v6
18236 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18237 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18238 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18239 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18240 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18241 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18242 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18243 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18244 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18245 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18247 #undef THUMB_VARIANT
18248 #define THUMB_VARIANT & arm_ext_v6t2
18250 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18251 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18253 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18254 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18256 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18257 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18259 /* ARM V6 not included in V7M. */
18260 #undef THUMB_VARIANT
18261 #define THUMB_VARIANT & arm_ext_v6_notm
18262 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18263 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18264 UF(rfeib, 9900a00, 1, (RRw), rfe),
18265 UF(rfeda, 8100a00, 1, (RRw), rfe),
18266 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18267 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18268 UF(rfefa, 8100a00, 1, (RRw), rfe),
18269 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18270 UF(rfeed, 9900a00, 1, (RRw), rfe),
18271 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18272 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18273 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18274 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18275 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18276 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18277 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18278 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18279 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18281 /* ARM V6 not included in V7M (eg. integer SIMD). */
18282 #undef THUMB_VARIANT
18283 #define THUMB_VARIANT & arm_ext_v6_dsp
18284 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18285 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18286 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18287 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18288 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18289 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18290 /* Old name for QASX. */
18291 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18292 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18293 /* Old name for QSAX. */
18294 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18295 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18296 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18297 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18298 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18299 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18300 /* Old name for SASX. */
18301 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18302 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18303 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18304 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18305 /* Old name for SHASX. */
18306 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18307 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18308 /* Old name for SHSAX. */
18309 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18310 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18311 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18312 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18313 /* Old name for SSAX. */
18314 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18315 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18316 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18317 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18318 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18320 /* Old name for UASX. */
18321 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18324 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 /* Old name for UHASX. */
18326 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18327 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18328 /* Old name for UHSAX. */
18329 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18330 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18331 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18333 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18335 /* Old name for UQASX. */
18336 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18337 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18338 /* Old name for UQSAX. */
18339 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18340 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18341 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18342 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18343 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18344 /* Old name for USAX. */
18345 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18346 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18347 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18348 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18349 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18350 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18351 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18352 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18353 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18354 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18355 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18356 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18357 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18358 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18359 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18360 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18361 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18362 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18363 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18364 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18365 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18366 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18367 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18368 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18369 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18370 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18371 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18372 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18373 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18374 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18375 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18376 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18377 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18378 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18381 #define ARM_VARIANT & arm_ext_v6k
18382 #undef THUMB_VARIANT
18383 #define THUMB_VARIANT & arm_ext_v6k
18385 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18386 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18387 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18388 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18390 #undef THUMB_VARIANT
18391 #define THUMB_VARIANT & arm_ext_v6_notm
18392 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18394 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18395 RRnpcb), strexd, t_strexd),
18397 #undef THUMB_VARIANT
18398 #define THUMB_VARIANT & arm_ext_v6t2
18399 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18401 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18403 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18405 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18407 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18410 #define ARM_VARIANT & arm_ext_sec
18411 #undef THUMB_VARIANT
18412 #define THUMB_VARIANT & arm_ext_sec
18414 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18417 #define ARM_VARIANT & arm_ext_virt
18418 #undef THUMB_VARIANT
18419 #define THUMB_VARIANT & arm_ext_virt
18421 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18422 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18425 #define ARM_VARIANT & arm_ext_v6t2
18426 #undef THUMB_VARIANT
18427 #define THUMB_VARIANT & arm_ext_v6t2
18429 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18430 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18431 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18432 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18434 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18435 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18436 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18437 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18439 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18440 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18441 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18442 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18444 /* Thumb-only instructions. */
18446 #define ARM_VARIANT NULL
18447 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18448 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18450 /* ARM does not really have an IT instruction, so always allow it.
18451 The opcode is copied from Thumb in order to allow warnings in
18452 -mimplicit-it=[never | arm] modes. */
18454 #define ARM_VARIANT & arm_ext_v1
18456 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18457 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18458 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18459 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18460 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18461 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18462 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18463 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18464 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18465 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18466 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18467 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18468 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18469 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18470 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18471 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18472 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18473 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18475 /* Thumb2 only instructions. */
18477 #define ARM_VARIANT NULL
18479 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18480 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18481 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18482 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18483 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18484 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18486 /* Hardware division instructions. */
18488 #define ARM_VARIANT & arm_ext_adiv
18489 #undef THUMB_VARIANT
18490 #define THUMB_VARIANT & arm_ext_div
18492 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18493 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18495 /* ARM V6M/V7 instructions. */
18497 #define ARM_VARIANT & arm_ext_barrier
18498 #undef THUMB_VARIANT
18499 #define THUMB_VARIANT & arm_ext_barrier
18501 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18502 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18503 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
18505 /* ARM V7 instructions. */
18507 #define ARM_VARIANT & arm_ext_v7
18508 #undef THUMB_VARIANT
18509 #define THUMB_VARIANT & arm_ext_v7
18511 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18512 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18515 #define ARM_VARIANT & arm_ext_mp
18516 #undef THUMB_VARIANT
18517 #define THUMB_VARIANT & arm_ext_mp
18519 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18521 /* AArchv8 instructions. */
18523 #define ARM_VARIANT & arm_ext_v8
18524 #undef THUMB_VARIANT
18525 #define THUMB_VARIANT & arm_ext_v8
18527 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18528 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18529 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18530 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18532 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18533 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18534 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18536 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18538 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18540 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18542 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18543 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18544 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18545 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18546 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18547 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18549 /* ARMv8 T32 only. */
18551 #define ARM_VARIANT NULL
18552 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18553 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18554 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18556 /* FP for ARMv8. */
18558 #define ARM_VARIANT & fpu_vfp_ext_armv8
18559 #undef THUMB_VARIANT
18560 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18562 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18563 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18564 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18565 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18566 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18567 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18568 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18569 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18570 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18571 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18572 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18573 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18574 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18575 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18576 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18577 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18578 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18580 /* Crypto v1 extensions. */
18582 #define ARM_VARIANT & fpu_crypto_ext_armv8
18583 #undef THUMB_VARIANT
18584 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18586 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18587 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18588 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18589 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18590 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18591 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18592 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18593 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18594 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18595 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18596 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18597 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18598 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18599 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18602 #define ARM_VARIANT & crc_ext_armv8
18603 #undef THUMB_VARIANT
18604 #define THUMB_VARIANT & crc_ext_armv8
18605 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18606 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18607 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18608 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18609 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18610 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18613 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18614 #undef THUMB_VARIANT
18615 #define THUMB_VARIANT NULL
18617 cCE("wfs", e200110, 1, (RR), rd),
18618 cCE("rfs", e300110, 1, (RR), rd),
18619 cCE("wfc", e400110, 1, (RR), rd),
18620 cCE("rfc", e500110, 1, (RR), rd),
18622 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18623 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18624 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18625 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18627 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18628 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18629 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18630 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18632 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18633 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18634 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18635 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18636 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18637 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18638 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18639 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18640 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18641 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18642 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18643 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18645 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18646 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18647 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18648 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18649 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18650 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18651 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18652 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18653 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18654 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18655 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18656 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18658 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18659 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18660 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18661 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18662 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18663 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18664 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18665 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18666 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18667 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18668 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18669 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18671 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18672 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18673 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18674 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18675 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18676 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18677 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18678 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18679 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18680 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18681 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18682 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18684 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18685 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18686 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18687 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18688 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18689 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18690 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18691 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18692 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18693 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18694 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18695 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18697 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18698 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18699 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18700 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18701 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18702 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18703 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18704 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18705 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18706 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18707 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18708 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18710 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18711 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18712 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18713 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18714 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18715 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18716 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18717 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18718 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18719 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18720 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18721 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18723 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18724 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18725 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18726 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18727 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18728 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18729 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18730 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18731 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18732 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18733 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18734 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18736 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18737 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18738 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18739 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18740 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18741 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18742 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18743 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18744 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18745 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18746 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18747 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18749 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18750 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18751 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18752 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18753 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18754 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18755 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18756 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18757 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18758 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18759 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18760 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18762 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18763 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18764 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18765 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18766 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18767 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18768 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18769 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18770 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18771 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18772 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18773 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18775 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18776 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18777 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18778 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18779 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18780 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18781 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18782 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18783 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18784 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18785 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18786 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18788 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18789 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18790 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18791 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18792 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18793 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18794 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18795 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18796 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18797 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18798 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18799 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18801 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18802 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18803 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18804 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18805 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18806 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18807 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18808 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18809 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18810 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18811 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18812 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18814 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18815 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18816 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18817 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18818 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18819 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18820 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18821 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18822 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18823 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18824 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18825 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18827 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18828 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18829 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18830 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18831 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18832 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18833 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18834 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18835 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18836 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18837 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18838 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18840 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18841 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18842 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18843 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18844 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18845 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18846 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18847 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18848 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18849 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18850 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18851 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18857 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18858 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18859 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18863 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18864 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18941 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18954 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18967 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18980 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18993 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18999 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19000 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19001 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19002 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19003 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19004 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19005 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19006 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19007 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19009 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19010 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19011 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19012 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19014 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19015 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19016 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19017 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19018 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19019 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19020 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19021 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19022 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19023 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19024 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19025 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19027 /* The implementation of the FIX instruction is broken on some
19028 assemblers, in that it accepts a precision specifier as well as a
19029 rounding specifier, despite the fact that this is meaningless.
19030 To be more compatible, we accept it as well, though of course it
19031 does not set any bits. */
19032 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19033 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19034 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19035 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19036 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19037 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19038 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19039 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19040 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19041 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19042 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19043 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19044 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19046 /* Instructions that were new with the real FPA, call them V2. */
19048 #define ARM_VARIANT & fpu_fpa_ext_v2
19050 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19051 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19052 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19053 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19054 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19055 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19058 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19060 /* Moves and type conversions. */
19061 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19062 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19063 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19064 cCE("fmstat", ef1fa10, 0, (), noargs),
19065 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19066 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19067 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19068 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19069 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19070 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19071 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19072 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19073 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19074 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19076 /* Memory operations. */
19077 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19078 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19079 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19080 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19081 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19082 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19083 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19084 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19085 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19086 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19087 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19088 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19089 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19090 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19091 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19092 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19093 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19094 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19096 /* Monadic operations. */
19097 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19098 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19099 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19101 /* Dyadic operations. */
19102 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19103 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19104 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19105 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19106 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19107 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19108 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19109 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19110 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19113 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19114 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19115 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19116 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19118 /* Double precision load/store are still present on single precision
19119 implementations. */
19120 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19121 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19122 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19123 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19124 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19125 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19126 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19127 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19128 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19129 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19132 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19134 /* Moves and type conversions. */
19135 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19136 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19137 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19138 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19139 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19140 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19141 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19142 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19143 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19144 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19145 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19146 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19147 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19149 /* Monadic operations. */
19150 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19151 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19152 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19154 /* Dyadic operations. */
19155 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19156 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19157 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19158 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19159 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19160 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19161 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19162 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19163 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19166 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19167 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19168 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19169 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19172 #define ARM_VARIANT & fpu_vfp_ext_v2
19174 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19175 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19176 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19177 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19179 /* Instructions which may belong to either the Neon or VFP instruction sets.
19180 Individual encoder functions perform additional architecture checks. */
19182 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19183 #undef THUMB_VARIANT
19184 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19186 /* These mnemonics are unique to VFP. */
19187 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19188 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19189 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19190 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19191 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19192 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19193 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19194 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19195 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19196 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19198 /* Mnemonics shared by Neon and VFP. */
19199 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19200 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19201 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19203 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19204 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19206 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19207 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19209 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19210 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19211 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19212 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19213 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19214 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19215 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19216 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19218 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19219 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19220 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19221 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19224 /* NOTE: All VMOV encoding is special-cased! */
19225 NCE(vmov, 0, 1, (VMOV), neon_mov),
19226 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19228 #undef THUMB_VARIANT
19229 #define THUMB_VARIANT & fpu_neon_ext_v1
19231 #define ARM_VARIANT & fpu_neon_ext_v1
19233 /* Data processing with three registers of the same length. */
19234 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19235 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19236 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19237 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19238 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19239 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19240 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19241 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19242 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19243 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19244 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19245 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19246 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19247 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19248 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19249 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19250 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19251 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19252 /* If not immediate, fall back to neon_dyadic_i64_su.
19253 shl_imm should accept I8 I16 I32 I64,
19254 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19255 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19256 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19257 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19258 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19259 /* Logic ops, types optional & ignored. */
19260 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19261 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19262 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19263 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19264 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19265 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19266 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19267 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19268 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19269 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19270 /* Bitfield ops, untyped. */
19271 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19272 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19273 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19274 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19275 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19276 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19277 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19278 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19279 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19280 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19281 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19282 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19283 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19284 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19285 back to neon_dyadic_if_su. */
19286 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19287 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19288 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19289 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19290 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19291 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19292 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19293 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19294 /* Comparison. Type I8 I16 I32 F32. */
19295 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19296 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19297 /* As above, D registers only. */
19298 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19299 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19300 /* Int and float variants, signedness unimportant. */
19301 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19302 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19303 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19304 /* Add/sub take types I8 I16 I32 I64 F32. */
19305 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19306 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19307 /* vtst takes sizes 8, 16, 32. */
19308 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19309 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19310 /* VMUL takes I8 I16 I32 F32 P8. */
19311 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19312 /* VQD{R}MULH takes S16 S32. */
19313 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19314 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19315 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19316 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19317 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19318 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19319 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19320 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19321 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19322 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19323 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19324 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19325 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19326 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19327 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19328 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19330 /* Two address, int/float. Types S8 S16 S32 F32. */
19331 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19332 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19334 /* Data processing with two registers and a shift amount. */
19335 /* Right shifts, and variants with rounding.
19336 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19337 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19338 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19339 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19340 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19341 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19342 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19343 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19344 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19345 /* Shift and insert. Sizes accepted 8 16 32 64. */
19346 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19347 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19348 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19349 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19350 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19351 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19352 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19353 /* Right shift immediate, saturating & narrowing, with rounding variants.
19354 Types accepted S16 S32 S64 U16 U32 U64. */
19355 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19356 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19357 /* As above, unsigned. Types accepted S16 S32 S64. */
19358 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19359 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19360 /* Right shift narrowing. Types accepted I16 I32 I64. */
19361 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19362 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19363 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19364 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19365 /* CVT with optional immediate for fixed-point variant. */
19366 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19368 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19369 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19371 /* Data processing, three registers of different lengths. */
19372 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19373 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19374 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19375 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19376 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19377 /* If not scalar, fall back to neon_dyadic_long.
19378 Vector types as above, scalar types S16 S32 U16 U32. */
19379 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19380 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19381 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19382 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19383 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19384 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19385 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19386 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19387 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19388 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19389 /* Saturating doubling multiplies. Types S16 S32. */
19390 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19391 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19392 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19393 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19394 S16 S32 U16 U32. */
19395 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19397 /* Extract. Size 8. */
19398 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19399 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19401 /* Two registers, miscellaneous. */
19402 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19403 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19404 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19405 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19406 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19407 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19408 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19409 /* Vector replicate. Sizes 8 16 32. */
19410 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19411 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19412 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19413 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19414 /* VMOVN. Types I16 I32 I64. */
19415 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19416 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19417 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19418 /* VQMOVUN. Types S16 S32 S64. */
19419 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19420 /* VZIP / VUZP. Sizes 8 16 32. */
19421 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19422 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19423 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19424 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19425 /* VQABS / VQNEG. Types S8 S16 S32. */
19426 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19427 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19428 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19429 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19430 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19431 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19432 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19433 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19434 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19435 /* Reciprocal estimates. Types U32 F32. */
19436 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19437 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19438 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19439 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19440 /* VCLS. Types S8 S16 S32. */
19441 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19442 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19443 /* VCLZ. Types I8 I16 I32. */
19444 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19445 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19446 /* VCNT. Size 8. */
19447 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19448 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19449 /* Two address, untyped. */
19450 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19451 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19452 /* VTRN. Sizes 8 16 32. */
19453 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19454 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19456 /* Table lookup. Size 8. */
19457 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19458 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19460 #undef THUMB_VARIANT
19461 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19463 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19465 /* Neon element/structure load/store. */
19466 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19467 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19468 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19469 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19470 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19471 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19472 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19473 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19475 #undef THUMB_VARIANT
19476 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19478 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19479 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19480 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19481 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19482 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19483 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19484 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19485 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19486 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19487 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19489 #undef THUMB_VARIANT
19490 #define THUMB_VARIANT & fpu_vfp_ext_v3
19492 #define ARM_VARIANT & fpu_vfp_ext_v3
19494 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19495 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19496 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19497 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19498 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19499 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19500 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19501 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19502 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19505 #define ARM_VARIANT &fpu_vfp_ext_fma
19506 #undef THUMB_VARIANT
19507 #define THUMB_VARIANT &fpu_vfp_ext_fma
19508 /* Mnemonics shared by Neon and VFP. These are included in the
19509 VFP FMA variant; NEON and VFP FMA always includes the NEON
19510 FMA instructions. */
19511 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19512 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19513 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19514 the v form should always be used. */
19515 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19516 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19517 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19518 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19519 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19520 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19522 #undef THUMB_VARIANT
19524 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19526 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19527 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19528 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19529 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19530 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19531 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19532 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19533 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19536 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19538 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19539 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19540 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19541 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19542 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19543 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19544 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19545 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19546 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19547 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19548 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19549 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19550 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19551 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19552 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19553 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19554 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19555 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19556 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19557 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19558 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19559 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19560 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19561 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19562 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19563 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19564 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19565 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19566 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19567 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19568 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19569 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19570 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19571 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19572 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19573 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19574 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19575 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19576 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19577 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19578 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19579 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19580 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19581 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19582 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19583 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19584 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19585 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19586 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19587 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19588 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19589 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19590 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19591 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19592 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19593 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19597 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19598 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19599 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19600 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19601 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19602 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19605 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19606 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19607 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19608 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19611 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19627 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19639 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19640 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19641 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19642 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19643 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19644 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19649 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19650 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19651 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19652 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19653 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19654 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19655 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19656 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19657 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19658 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19659 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19660 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19661 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19662 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19663 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19664 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19665 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19666 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19667 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19668 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19669 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19670 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19671 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19675 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19676 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19677 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19678 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19679 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19680 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19681 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19682 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19683 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19684 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19685 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19686 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19687 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19688 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19689 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19690 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19691 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19692 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19693 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19694 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19695 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19696 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19697 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19698 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19699 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19702 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19704 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19705 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19706 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19707 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19708 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19709 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19710 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19711 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19712 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19713 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19714 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19715 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19716 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19717 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19718 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19719 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19720 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19721 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19722 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19723 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19725 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19727 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19728 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19729 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19730 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19731 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19732 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19733 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19734 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19735 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19736 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19737 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19738 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19739 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19740 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19746 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19747 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19751 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19753 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19754 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19755 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19756 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19757 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19758 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19759 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19760 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19763 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19765 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19766 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19767 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19768 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19769 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19770 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19771 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19772 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19773 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19774 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19775 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19776 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19777 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19778 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19779 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19780 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19781 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19782 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19783 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19784 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19785 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19786 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19787 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19788 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19789 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19790 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19791 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19792 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19793 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19794 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19795 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19796 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19797 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19798 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19799 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19800 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19801 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19802 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19803 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19804 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19805 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19806 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19807 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19808 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19809 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19810 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19811 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19812 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19813 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19814 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19815 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19816 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19817 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19818 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19819 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19820 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19821 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19822 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19823 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19824 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19825 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19826 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19827 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19828 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19829 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19830 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19831 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19832 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19833 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19834 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19835 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19836 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19837 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19838 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19839 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19840 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19843 #undef THUMB_VARIANT
19869 /* MD interface: bits in the object file. */
19871 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19872 for use in the a.out file, and stores them in the array pointed to by buf.
19873 This knows about the endian-ness of the target machine and does
19874 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19875 2 (short) and 4 (long) Floating numbers are put out as a series of
19876 LITTLENUMS (shorts, here at least). */
19879 md_number_to_chars (char * buf, valueT val, int n)
19881 if (target_big_endian)
19882 number_to_chars_bigendian (buf, val, n);
19884 number_to_chars_littleendian (buf, val, n);
19888 md_chars_to_number (char * buf, int n)
19891 unsigned char * where = (unsigned char *) buf;
19893 if (target_big_endian)
19898 result |= (*where++ & 255);
19906 result |= (where[n] & 255);
19913 /* MD interface: Sections. */
19915 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19916 that an rs_machine_dependent frag may reach. */
19919 arm_frag_max_var (fragS *fragp)
19921 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19922 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19924 Note that we generate relaxable instructions even for cases that don't
19925 really need it, like an immediate that's a trivial constant. So we're
19926 overestimating the instruction size for some of those cases. Rather
19927 than putting more intelligence here, it would probably be better to
19928 avoid generating a relaxation frag in the first place when it can be
19929 determined up front that a short instruction will suffice. */
19931 gas_assert (fragp->fr_type == rs_machine_dependent);
19935 /* Estimate the size of a frag before relaxing. Assume everything fits in
19939 md_estimate_size_before_relax (fragS * fragp,
19940 segT segtype ATTRIBUTE_UNUSED)
19946 /* Convert a machine dependent frag. */
19949 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19951 unsigned long insn;
19952 unsigned long old_op;
19960 buf = fragp->fr_literal + fragp->fr_fix;
19962 old_op = bfd_get_16(abfd, buf);
19963 if (fragp->fr_symbol)
19965 exp.X_op = O_symbol;
19966 exp.X_add_symbol = fragp->fr_symbol;
19970 exp.X_op = O_constant;
19972 exp.X_add_number = fragp->fr_offset;
19973 opcode = fragp->fr_subtype;
19976 case T_MNEM_ldr_pc:
19977 case T_MNEM_ldr_pc2:
19978 case T_MNEM_ldr_sp:
19979 case T_MNEM_str_sp:
19986 if (fragp->fr_var == 4)
19988 insn = THUMB_OP32 (opcode);
19989 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19991 insn |= (old_op & 0x700) << 4;
19995 insn |= (old_op & 7) << 12;
19996 insn |= (old_op & 0x38) << 13;
19998 insn |= 0x00000c00;
19999 put_thumb32_insn (buf, insn);
20000 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20004 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20006 pc_rel = (opcode == T_MNEM_ldr_pc2);
20009 if (fragp->fr_var == 4)
20011 insn = THUMB_OP32 (opcode);
20012 insn |= (old_op & 0xf0) << 4;
20013 put_thumb32_insn (buf, insn);
20014 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20018 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20019 exp.X_add_number -= 4;
20027 if (fragp->fr_var == 4)
20029 int r0off = (opcode == T_MNEM_mov
20030 || opcode == T_MNEM_movs) ? 0 : 8;
20031 insn = THUMB_OP32 (opcode);
20032 insn = (insn & 0xe1ffffff) | 0x10000000;
20033 insn |= (old_op & 0x700) << r0off;
20034 put_thumb32_insn (buf, insn);
20035 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20039 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20044 if (fragp->fr_var == 4)
20046 insn = THUMB_OP32(opcode);
20047 put_thumb32_insn (buf, insn);
20048 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20051 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20055 if (fragp->fr_var == 4)
20057 insn = THUMB_OP32(opcode);
20058 insn |= (old_op & 0xf00) << 14;
20059 put_thumb32_insn (buf, insn);
20060 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20063 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20066 case T_MNEM_add_sp:
20067 case T_MNEM_add_pc:
20068 case T_MNEM_inc_sp:
20069 case T_MNEM_dec_sp:
20070 if (fragp->fr_var == 4)
20072 /* ??? Choose between add and addw. */
20073 insn = THUMB_OP32 (opcode);
20074 insn |= (old_op & 0xf0) << 4;
20075 put_thumb32_insn (buf, insn);
20076 if (opcode == T_MNEM_add_pc)
20077 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20079 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20082 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20090 if (fragp->fr_var == 4)
20092 insn = THUMB_OP32 (opcode);
20093 insn |= (old_op & 0xf0) << 4;
20094 insn |= (old_op & 0xf) << 16;
20095 put_thumb32_insn (buf, insn);
20096 if (insn & (1 << 20))
20097 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20099 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20102 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20108 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20109 (enum bfd_reloc_code_real) reloc_type);
20110 fixp->fx_file = fragp->fr_file;
20111 fixp->fx_line = fragp->fr_line;
20112 fragp->fr_fix += fragp->fr_var;
20115 /* Return the size of a relaxable immediate operand instruction.
20116 SHIFT and SIZE specify the form of the allowable immediate. */
20118 relax_immediate (fragS *fragp, int size, int shift)
20124 /* ??? Should be able to do better than this. */
20125 if (fragp->fr_symbol)
20128 low = (1 << shift) - 1;
20129 mask = (1 << (shift + size)) - (1 << shift);
20130 offset = fragp->fr_offset;
20131 /* Force misaligned offsets to 32-bit variant. */
20134 if (offset & ~mask)
20139 /* Get the address of a symbol during relaxation. */
20141 relaxed_symbol_addr (fragS *fragp, long stretch)
20147 sym = fragp->fr_symbol;
20148 sym_frag = symbol_get_frag (sym);
20149 know (S_GET_SEGMENT (sym) != absolute_section
20150 || sym_frag == &zero_address_frag);
20151 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20153 /* If frag has yet to be reached on this pass, assume it will
20154 move by STRETCH just as we did. If this is not so, it will
20155 be because some frag between grows, and that will force
20159 && sym_frag->relax_marker != fragp->relax_marker)
20163 /* Adjust stretch for any alignment frag. Note that if have
20164 been expanding the earlier code, the symbol may be
20165 defined in what appears to be an earlier frag. FIXME:
20166 This doesn't handle the fr_subtype field, which specifies
20167 a maximum number of bytes to skip when doing an
20169 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20171 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20174 stretch = - ((- stretch)
20175 & ~ ((1 << (int) f->fr_offset) - 1));
20177 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20189 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20192 relax_adr (fragS *fragp, asection *sec, long stretch)
20197 /* Assume worst case for symbols not known to be in the same section. */
20198 if (fragp->fr_symbol == NULL
20199 || !S_IS_DEFINED (fragp->fr_symbol)
20200 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20201 || S_IS_WEAK (fragp->fr_symbol))
20204 val = relaxed_symbol_addr (fragp, stretch);
20205 addr = fragp->fr_address + fragp->fr_fix;
20206 addr = (addr + 4) & ~3;
20207 /* Force misaligned targets to 32-bit variant. */
20211 if (val < 0 || val > 1020)
20216 /* Return the size of a relaxable add/sub immediate instruction. */
20218 relax_addsub (fragS *fragp, asection *sec)
20223 buf = fragp->fr_literal + fragp->fr_fix;
20224 op = bfd_get_16(sec->owner, buf);
20225 if ((op & 0xf) == ((op >> 4) & 0xf))
20226 return relax_immediate (fragp, 8, 0);
20228 return relax_immediate (fragp, 3, 0);
20231 /* Return TRUE iff the definition of symbol S could be pre-empted
20232 (overridden) at link or load time. */
20234 symbol_preemptible (symbolS *s)
20236 /* Weak symbols can always be pre-empted. */
20240 /* Non-global symbols cannot be pre-empted. */
20241 if (! S_IS_EXTERNAL (s))
20245 /* In ELF, a global symbol can be marked protected, or private. In that
20246 case it can't be pre-empted (other definitions in the same link unit
20247 would violate the ODR). */
20248 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20252 /* Other global symbols might be pre-empted. */
20256 /* Return the size of a relaxable branch instruction. BITS is the
20257 size of the offset field in the narrow instruction. */
20260 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20266 /* Assume worst case for symbols not known to be in the same section. */
20267 if (!S_IS_DEFINED (fragp->fr_symbol)
20268 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20269 || S_IS_WEAK (fragp->fr_symbol))
20273 /* A branch to a function in ARM state will require interworking. */
20274 if (S_IS_DEFINED (fragp->fr_symbol)
20275 && ARM_IS_FUNC (fragp->fr_symbol))
20279 if (symbol_preemptible (fragp->fr_symbol))
20282 val = relaxed_symbol_addr (fragp, stretch);
20283 addr = fragp->fr_address + fragp->fr_fix + 4;
20286 /* Offset is a signed value *2 */
20288 if (val >= limit || val < -limit)
20294 /* Relax a machine dependent frag. This returns the amount by which
20295 the current size of the frag should change. */
20298 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20303 oldsize = fragp->fr_var;
20304 switch (fragp->fr_subtype)
20306 case T_MNEM_ldr_pc2:
20307 newsize = relax_adr (fragp, sec, stretch);
20309 case T_MNEM_ldr_pc:
20310 case T_MNEM_ldr_sp:
20311 case T_MNEM_str_sp:
20312 newsize = relax_immediate (fragp, 8, 2);
20316 newsize = relax_immediate (fragp, 5, 2);
20320 newsize = relax_immediate (fragp, 5, 1);
20324 newsize = relax_immediate (fragp, 5, 0);
20327 newsize = relax_adr (fragp, sec, stretch);
20333 newsize = relax_immediate (fragp, 8, 0);
20336 newsize = relax_branch (fragp, sec, 11, stretch);
20339 newsize = relax_branch (fragp, sec, 8, stretch);
20341 case T_MNEM_add_sp:
20342 case T_MNEM_add_pc:
20343 newsize = relax_immediate (fragp, 8, 2);
20345 case T_MNEM_inc_sp:
20346 case T_MNEM_dec_sp:
20347 newsize = relax_immediate (fragp, 7, 2);
20353 newsize = relax_addsub (fragp, sec);
20359 fragp->fr_var = newsize;
20360 /* Freeze wide instructions that are at or before the same location as
20361 in the previous pass. This avoids infinite loops.
20362 Don't freeze them unconditionally because targets may be artificially
20363 misaligned by the expansion of preceding frags. */
20364 if (stretch <= 0 && newsize > 2)
20366 md_convert_frag (sec->owner, sec, fragp);
20370 return newsize - oldsize;
20373 /* Round up a section size to the appropriate boundary. */
20376 md_section_align (segT segment ATTRIBUTE_UNUSED,
20379 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20380 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20382 /* For a.out, force the section size to be aligned. If we don't do
20383 this, BFD will align it for us, but it will not write out the
20384 final bytes of the section. This may be a bug in BFD, but it is
20385 easier to fix it here since that is how the other a.out targets
20389 align = bfd_get_section_alignment (stdoutput, segment);
20390 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20397 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20398 of an rs_align_code fragment. */
20401 arm_handle_align (fragS * fragP)
20403 static char const arm_noop[2][2][4] =
20406 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20407 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20410 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20411 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20414 static char const thumb_noop[2][2][2] =
20417 {0xc0, 0x46}, /* LE */
20418 {0x46, 0xc0}, /* BE */
20421 {0x00, 0xbf}, /* LE */
20422 {0xbf, 0x00} /* BE */
20425 static char const wide_thumb_noop[2][4] =
20426 { /* Wide Thumb-2 */
20427 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20428 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20431 unsigned bytes, fix, noop_size;
20434 const char *narrow_noop = NULL;
20439 if (fragP->fr_type != rs_align_code)
20442 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20443 p = fragP->fr_literal + fragP->fr_fix;
20446 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20447 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20449 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20451 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20453 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20455 narrow_noop = thumb_noop[1][target_big_endian];
20456 noop = wide_thumb_noop[target_big_endian];
20459 noop = thumb_noop[0][target_big_endian];
20467 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20468 [target_big_endian];
20475 fragP->fr_var = noop_size;
20477 if (bytes & (noop_size - 1))
20479 fix = bytes & (noop_size - 1);
20481 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20483 memset (p, 0, fix);
20490 if (bytes & noop_size)
20492 /* Insert a narrow noop. */
20493 memcpy (p, narrow_noop, noop_size);
20495 bytes -= noop_size;
20499 /* Use wide noops for the remainder */
20503 while (bytes >= noop_size)
20505 memcpy (p, noop, noop_size);
20507 bytes -= noop_size;
20511 fragP->fr_fix += fix;
20514 /* Called from md_do_align. Used to create an alignment
20515 frag in a code section. */
20518 arm_frag_align_code (int n, int max)
20522 /* We assume that there will never be a requirement
20523 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20524 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20529 _("alignments greater than %d bytes not supported in .text sections."),
20530 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20531 as_fatal ("%s", err_msg);
20534 p = frag_var (rs_align_code,
20535 MAX_MEM_FOR_RS_ALIGN_CODE,
20537 (relax_substateT) max,
20544 /* Perform target specific initialisation of a frag.
20545 Note - despite the name this initialisation is not done when the frag
20546 is created, but only when its type is assigned. A frag can be created
20547 and used a long time before its type is set, so beware of assuming that
20548 this initialisationis performed first. */
20552 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20554 /* Record whether this frag is in an ARM or a THUMB area. */
20555 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20558 #else /* OBJ_ELF is defined. */
20560 arm_init_frag (fragS * fragP, int max_chars)
20562 /* If the current ARM vs THUMB mode has not already
20563 been recorded into this frag then do so now. */
20564 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20566 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20568 /* Record a mapping symbol for alignment frags. We will delete this
20569 later if the alignment ends up empty. */
20570 switch (fragP->fr_type)
20573 case rs_align_test:
20575 mapping_state_2 (MAP_DATA, max_chars);
20577 case rs_align_code:
20578 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20586 /* When we change sections we need to issue a new mapping symbol. */
20589 arm_elf_change_section (void)
20591 /* Link an unlinked unwind index table section to the .text section. */
20592 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20593 && elf_linked_to_section (now_seg) == NULL)
20594 elf_linked_to_section (now_seg) = text_section;
20598 arm_elf_section_type (const char * str, size_t len)
20600 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20601 return SHT_ARM_EXIDX;
20606 /* Code to deal with unwinding tables. */
20608 static void add_unwind_adjustsp (offsetT);
20610 /* Generate any deferred unwind frame offset. */
20613 flush_pending_unwind (void)
20617 offset = unwind.pending_offset;
20618 unwind.pending_offset = 0;
20620 add_unwind_adjustsp (offset);
20623 /* Add an opcode to this list for this function. Two-byte opcodes should
20624 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20628 add_unwind_opcode (valueT op, int length)
20630 /* Add any deferred stack adjustment. */
20631 if (unwind.pending_offset)
20632 flush_pending_unwind ();
20634 unwind.sp_restored = 0;
20636 if (unwind.opcode_count + length > unwind.opcode_alloc)
20638 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20639 if (unwind.opcodes)
20640 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20641 unwind.opcode_alloc);
20643 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20648 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20650 unwind.opcode_count++;
20654 /* Add unwind opcodes to adjust the stack pointer. */
20657 add_unwind_adjustsp (offsetT offset)
20661 if (offset > 0x200)
20663 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20668 /* Long form: 0xb2, uleb128. */
20669 /* This might not fit in a word so add the individual bytes,
20670 remembering the list is built in reverse order. */
20671 o = (valueT) ((offset - 0x204) >> 2);
20673 add_unwind_opcode (0, 1);
20675 /* Calculate the uleb128 encoding of the offset. */
20679 bytes[n] = o & 0x7f;
20685 /* Add the insn. */
20687 add_unwind_opcode (bytes[n - 1], 1);
20688 add_unwind_opcode (0xb2, 1);
20690 else if (offset > 0x100)
20692 /* Two short opcodes. */
20693 add_unwind_opcode (0x3f, 1);
20694 op = (offset - 0x104) >> 2;
20695 add_unwind_opcode (op, 1);
20697 else if (offset > 0)
20699 /* Short opcode. */
20700 op = (offset - 4) >> 2;
20701 add_unwind_opcode (op, 1);
20703 else if (offset < 0)
20706 while (offset > 0x100)
20708 add_unwind_opcode (0x7f, 1);
20711 op = ((offset - 4) >> 2) | 0x40;
20712 add_unwind_opcode (op, 1);
20716 /* Finish the list of unwind opcodes for this function. */
20718 finish_unwind_opcodes (void)
20722 if (unwind.fp_used)
20724 /* Adjust sp as necessary. */
20725 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20726 flush_pending_unwind ();
20728 /* After restoring sp from the frame pointer. */
20729 op = 0x90 | unwind.fp_reg;
20730 add_unwind_opcode (op, 1);
20733 flush_pending_unwind ();
20737 /* Start an exception table entry. If idx is nonzero this is an index table
20741 start_unwind_section (const segT text_seg, int idx)
20743 const char * text_name;
20744 const char * prefix;
20745 const char * prefix_once;
20746 const char * group_name;
20750 size_t sec_name_len;
20757 prefix = ELF_STRING_ARM_unwind;
20758 prefix_once = ELF_STRING_ARM_unwind_once;
20759 type = SHT_ARM_EXIDX;
20763 prefix = ELF_STRING_ARM_unwind_info;
20764 prefix_once = ELF_STRING_ARM_unwind_info_once;
20765 type = SHT_PROGBITS;
20768 text_name = segment_name (text_seg);
20769 if (streq (text_name, ".text"))
20772 if (strncmp (text_name, ".gnu.linkonce.t.",
20773 strlen (".gnu.linkonce.t.")) == 0)
20775 prefix = prefix_once;
20776 text_name += strlen (".gnu.linkonce.t.");
20779 prefix_len = strlen (prefix);
20780 text_len = strlen (text_name);
20781 sec_name_len = prefix_len + text_len;
20782 sec_name = (char *) xmalloc (sec_name_len + 1);
20783 memcpy (sec_name, prefix, prefix_len);
20784 memcpy (sec_name + prefix_len, text_name, text_len);
20785 sec_name[prefix_len + text_len] = '\0';
20791 /* Handle COMDAT group. */
20792 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20794 group_name = elf_group_name (text_seg);
20795 if (group_name == NULL)
20797 as_bad (_("Group section `%s' has no group signature"),
20798 segment_name (text_seg));
20799 ignore_rest_of_line ();
20802 flags |= SHF_GROUP;
20806 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20808 /* Set the section link for index tables. */
20810 elf_linked_to_section (now_seg) = text_seg;
20814 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20815 personality routine data. Returns zero, or the index table value for
20816 and inline entry. */
20819 create_unwind_entry (int have_data)
20824 /* The current word of data. */
20826 /* The number of bytes left in this word. */
20829 finish_unwind_opcodes ();
20831 /* Remember the current text section. */
20832 unwind.saved_seg = now_seg;
20833 unwind.saved_subseg = now_subseg;
20835 start_unwind_section (now_seg, 0);
20837 if (unwind.personality_routine == NULL)
20839 if (unwind.personality_index == -2)
20842 as_bad (_("handlerdata in cantunwind frame"));
20843 return 1; /* EXIDX_CANTUNWIND. */
20846 /* Use a default personality routine if none is specified. */
20847 if (unwind.personality_index == -1)
20849 if (unwind.opcode_count > 3)
20850 unwind.personality_index = 1;
20852 unwind.personality_index = 0;
20855 /* Space for the personality routine entry. */
20856 if (unwind.personality_index == 0)
20858 if (unwind.opcode_count > 3)
20859 as_bad (_("too many unwind opcodes for personality routine 0"));
20863 /* All the data is inline in the index table. */
20866 while (unwind.opcode_count > 0)
20868 unwind.opcode_count--;
20869 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20873 /* Pad with "finish" opcodes. */
20875 data = (data << 8) | 0xb0;
20882 /* We get two opcodes "free" in the first word. */
20883 size = unwind.opcode_count - 2;
20887 gas_assert (unwind.personality_index == -1);
20889 /* An extra byte is required for the opcode count. */
20890 size = unwind.opcode_count + 1;
20893 size = (size + 3) >> 2;
20895 as_bad (_("too many unwind opcodes"));
20897 frag_align (2, 0, 0);
20898 record_alignment (now_seg, 2);
20899 unwind.table_entry = expr_build_dot ();
20901 /* Allocate the table entry. */
20902 ptr = frag_more ((size << 2) + 4);
20903 /* PR 13449: Zero the table entries in case some of them are not used. */
20904 memset (ptr, 0, (size << 2) + 4);
20905 where = frag_now_fix () - ((size << 2) + 4);
20907 switch (unwind.personality_index)
20910 /* ??? Should this be a PLT generating relocation? */
20911 /* Custom personality routine. */
20912 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20913 BFD_RELOC_ARM_PREL31);
20918 /* Set the first byte to the number of additional words. */
20919 data = size > 0 ? size - 1 : 0;
20923 /* ABI defined personality routines. */
20925 /* Three opcodes bytes are packed into the first word. */
20932 /* The size and first two opcode bytes go in the first word. */
20933 data = ((0x80 + unwind.personality_index) << 8) | size;
20938 /* Should never happen. */
20942 /* Pack the opcodes into words (MSB first), reversing the list at the same
20944 while (unwind.opcode_count > 0)
20948 md_number_to_chars (ptr, data, 4);
20953 unwind.opcode_count--;
20955 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20958 /* Finish off the last word. */
20961 /* Pad with "finish" opcodes. */
20963 data = (data << 8) | 0xb0;
20965 md_number_to_chars (ptr, data, 4);
20970 /* Add an empty descriptor if there is no user-specified data. */
20971 ptr = frag_more (4);
20972 md_number_to_chars (ptr, 0, 4);
20979 /* Initialize the DWARF-2 unwind information for this procedure. */
20982 tc_arm_frame_initial_instructions (void)
20984 cfi_add_CFA_def_cfa (REG_SP, 0);
20986 #endif /* OBJ_ELF */
20988 /* Convert REGNAME to a DWARF-2 register number. */
20991 tc_arm_regname_to_dw2regnum (char *regname)
20993 int reg = arm_reg_parse (®name, REG_TYPE_RN);
21003 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
21007 exp.X_op = O_secrel;
21008 exp.X_add_symbol = symbol;
21009 exp.X_add_number = 0;
21010 emit_expr (&exp, size);
21014 /* MD interface: Symbol and relocation handling. */
21016 /* Return the address within the segment that a PC-relative fixup is
21017 relative to. For ARM, PC-relative fixups applied to instructions
21018 are generally relative to the location of the fixup plus 8 bytes.
21019 Thumb branches are offset by 4, and Thumb loads relative to PC
21020 require special handling. */
21023 md_pcrel_from_section (fixS * fixP, segT seg)
21025 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21027 /* If this is pc-relative and we are going to emit a relocation
21028 then we just want to put out any pipeline compensation that the linker
21029 will need. Otherwise we want to use the calculated base.
21030 For WinCE we skip the bias for externals as well, since this
21031 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21033 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21034 || (arm_force_relocation (fixP)
21036 && !S_IS_EXTERNAL (fixP->fx_addsy)
21042 switch (fixP->fx_r_type)
21044 /* PC relative addressing on the Thumb is slightly odd as the
21045 bottom two bits of the PC are forced to zero for the
21046 calculation. This happens *after* application of the
21047 pipeline offset. However, Thumb adrl already adjusts for
21048 this, so we need not do it again. */
21049 case BFD_RELOC_ARM_THUMB_ADD:
21052 case BFD_RELOC_ARM_THUMB_OFFSET:
21053 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21054 case BFD_RELOC_ARM_T32_ADD_PC12:
21055 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21056 return (base + 4) & ~3;
21058 /* Thumb branches are simply offset by +4. */
21059 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21060 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21061 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21062 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21063 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21066 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21068 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21069 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21070 && ARM_IS_FUNC (fixP->fx_addsy)
21071 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21072 base = fixP->fx_where + fixP->fx_frag->fr_address;
21075 /* BLX is like branches above, but forces the low two bits of PC to
21077 case BFD_RELOC_THUMB_PCREL_BLX:
21079 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21080 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21081 && THUMB_IS_FUNC (fixP->fx_addsy)
21082 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21083 base = fixP->fx_where + fixP->fx_frag->fr_address;
21084 return (base + 4) & ~3;
21086 /* ARM mode branches are offset by +8. However, the Windows CE
21087 loader expects the relocation not to take this into account. */
21088 case BFD_RELOC_ARM_PCREL_BLX:
21090 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21091 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21092 && ARM_IS_FUNC (fixP->fx_addsy)
21093 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21094 base = fixP->fx_where + fixP->fx_frag->fr_address;
21097 case BFD_RELOC_ARM_PCREL_CALL:
21099 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21100 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21101 && THUMB_IS_FUNC (fixP->fx_addsy)
21102 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21103 base = fixP->fx_where + fixP->fx_frag->fr_address;
21106 case BFD_RELOC_ARM_PCREL_BRANCH:
21107 case BFD_RELOC_ARM_PCREL_JUMP:
21108 case BFD_RELOC_ARM_PLT32:
21110 /* When handling fixups immediately, because we have already
21111 discovered the value of a symbol, or the address of the frag involved
21112 we must account for the offset by +8, as the OS loader will never see the reloc.
21113 see fixup_segment() in write.c
21114 The S_IS_EXTERNAL test handles the case of global symbols.
21115 Those need the calculated base, not just the pipe compensation the linker will need. */
21117 && fixP->fx_addsy != NULL
21118 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21119 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21127 /* ARM mode loads relative to PC are also offset by +8. Unlike
21128 branches, the Windows CE loader *does* expect the relocation
21129 to take this into account. */
21130 case BFD_RELOC_ARM_OFFSET_IMM:
21131 case BFD_RELOC_ARM_OFFSET_IMM8:
21132 case BFD_RELOC_ARM_HWLITERAL:
21133 case BFD_RELOC_ARM_LITERAL:
21134 case BFD_RELOC_ARM_CP_OFF_IMM:
21138 /* Other PC-relative relocations are un-offset. */
21144 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21145 Otherwise we have no need to default values of symbols. */
21148 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21151 if (name[0] == '_' && name[1] == 'G'
21152 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21156 if (symbol_find (name))
21157 as_bad (_("GOT already in the symbol table"));
21159 GOT_symbol = symbol_new (name, undefined_section,
21160 (valueT) 0, & zero_address_frag);
21170 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21171 computed as two separate immediate values, added together. We
21172 already know that this value cannot be computed by just one ARM
21175 static unsigned int
21176 validate_immediate_twopart (unsigned int val,
21177 unsigned int * highpart)
21182 for (i = 0; i < 32; i += 2)
21183 if (((a = rotate_left (val, i)) & 0xff) != 0)
21189 * highpart = (a >> 8) | ((i + 24) << 7);
21191 else if (a & 0xff0000)
21193 if (a & 0xff000000)
21195 * highpart = (a >> 16) | ((i + 16) << 7);
21199 gas_assert (a & 0xff000000);
21200 * highpart = (a >> 24) | ((i + 8) << 7);
21203 return (a & 0xff) | (i << 7);
21210 validate_offset_imm (unsigned int val, int hwse)
21212 if ((hwse && val > 255) || val > 4095)
21217 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21218 negative immediate constant by altering the instruction. A bit of
21223 by inverting the second operand, and
21226 by negating the second operand. */
21229 negate_data_op (unsigned long * instruction,
21230 unsigned long value)
21233 unsigned long negated, inverted;
21235 negated = encode_arm_immediate (-value);
21236 inverted = encode_arm_immediate (~value);
21238 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21241 /* First negates. */
21242 case OPCODE_SUB: /* ADD <-> SUB */
21243 new_inst = OPCODE_ADD;
21248 new_inst = OPCODE_SUB;
21252 case OPCODE_CMP: /* CMP <-> CMN */
21253 new_inst = OPCODE_CMN;
21258 new_inst = OPCODE_CMP;
21262 /* Now Inverted ops. */
21263 case OPCODE_MOV: /* MOV <-> MVN */
21264 new_inst = OPCODE_MVN;
21269 new_inst = OPCODE_MOV;
21273 case OPCODE_AND: /* AND <-> BIC */
21274 new_inst = OPCODE_BIC;
21279 new_inst = OPCODE_AND;
21283 case OPCODE_ADC: /* ADC <-> SBC */
21284 new_inst = OPCODE_SBC;
21289 new_inst = OPCODE_ADC;
21293 /* We cannot do anything. */
21298 if (value == (unsigned) FAIL)
21301 *instruction &= OPCODE_MASK;
21302 *instruction |= new_inst << DATA_OP_SHIFT;
21306 /* Like negate_data_op, but for Thumb-2. */
21308 static unsigned int
21309 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21313 unsigned int negated, inverted;
21315 negated = encode_thumb32_immediate (-value);
21316 inverted = encode_thumb32_immediate (~value);
21318 rd = (*instruction >> 8) & 0xf;
21319 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21322 /* ADD <-> SUB. Includes CMP <-> CMN. */
21323 case T2_OPCODE_SUB:
21324 new_inst = T2_OPCODE_ADD;
21328 case T2_OPCODE_ADD:
21329 new_inst = T2_OPCODE_SUB;
21333 /* ORR <-> ORN. Includes MOV <-> MVN. */
21334 case T2_OPCODE_ORR:
21335 new_inst = T2_OPCODE_ORN;
21339 case T2_OPCODE_ORN:
21340 new_inst = T2_OPCODE_ORR;
21344 /* AND <-> BIC. TST has no inverted equivalent. */
21345 case T2_OPCODE_AND:
21346 new_inst = T2_OPCODE_BIC;
21353 case T2_OPCODE_BIC:
21354 new_inst = T2_OPCODE_AND;
21359 case T2_OPCODE_ADC:
21360 new_inst = T2_OPCODE_SBC;
21364 case T2_OPCODE_SBC:
21365 new_inst = T2_OPCODE_ADC;
21369 /* We cannot do anything. */
21374 if (value == (unsigned int)FAIL)
21377 *instruction &= T2_OPCODE_MASK;
21378 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21382 /* Read a 32-bit thumb instruction from buf. */
21383 static unsigned long
21384 get_thumb32_insn (char * buf)
21386 unsigned long insn;
21387 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21388 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21394 /* We usually want to set the low bit on the address of thumb function
21395 symbols. In particular .word foo - . should have the low bit set.
21396 Generic code tries to fold the difference of two symbols to
21397 a constant. Prevent this and force a relocation when the first symbols
21398 is a thumb function. */
21401 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21403 if (op == O_subtract
21404 && l->X_op == O_symbol
21405 && r->X_op == O_symbol
21406 && THUMB_IS_FUNC (l->X_add_symbol))
21408 l->X_op = O_subtract;
21409 l->X_op_symbol = r->X_add_symbol;
21410 l->X_add_number -= r->X_add_number;
21414 /* Process as normal. */
21418 /* Encode Thumb2 unconditional branches and calls. The encoding
21419 for the 2 are identical for the immediate values. */
21422 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21424 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21427 addressT S, I1, I2, lo, hi;
21429 S = (value >> 24) & 0x01;
21430 I1 = (value >> 23) & 0x01;
21431 I2 = (value >> 22) & 0x01;
21432 hi = (value >> 12) & 0x3ff;
21433 lo = (value >> 1) & 0x7ff;
21434 newval = md_chars_to_number (buf, THUMB_SIZE);
21435 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21436 newval |= (S << 10) | hi;
21437 newval2 &= ~T2I1I2MASK;
21438 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21439 md_number_to_chars (buf, newval, THUMB_SIZE);
21440 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21444 md_apply_fix (fixS * fixP,
21448 offsetT value = * valP;
21450 unsigned int newimm;
21451 unsigned long temp;
21453 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21455 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21457 /* Note whether this will delete the relocation. */
21459 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21462 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21463 consistency with the behaviour on 32-bit hosts. Remember value
21465 value &= 0xffffffff;
21466 value ^= 0x80000000;
21467 value -= 0x80000000;
21470 fixP->fx_addnumber = value;
21472 /* Same treatment for fixP->fx_offset. */
21473 fixP->fx_offset &= 0xffffffff;
21474 fixP->fx_offset ^= 0x80000000;
21475 fixP->fx_offset -= 0x80000000;
21477 switch (fixP->fx_r_type)
21479 case BFD_RELOC_NONE:
21480 /* This will need to go in the object file. */
21484 case BFD_RELOC_ARM_IMMEDIATE:
21485 /* We claim that this fixup has been processed here,
21486 even if in fact we generate an error because we do
21487 not have a reloc for it, so tc_gen_reloc will reject it. */
21490 if (fixP->fx_addsy)
21492 const char *msg = 0;
21494 if (! S_IS_DEFINED (fixP->fx_addsy))
21495 msg = _("undefined symbol %s used as an immediate value");
21496 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21497 msg = _("symbol %s is in a different section");
21498 else if (S_IS_WEAK (fixP->fx_addsy))
21499 msg = _("symbol %s is weak and may be overridden later");
21503 as_bad_where (fixP->fx_file, fixP->fx_line,
21504 msg, S_GET_NAME (fixP->fx_addsy));
21509 temp = md_chars_to_number (buf, INSN_SIZE);
21511 /* If the offset is negative, we should use encoding A2 for ADR. */
21512 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21513 newimm = negate_data_op (&temp, value);
21516 newimm = encode_arm_immediate (value);
21518 /* If the instruction will fail, see if we can fix things up by
21519 changing the opcode. */
21520 if (newimm == (unsigned int) FAIL)
21521 newimm = negate_data_op (&temp, value);
21524 if (newimm == (unsigned int) FAIL)
21526 as_bad_where (fixP->fx_file, fixP->fx_line,
21527 _("invalid constant (%lx) after fixup"),
21528 (unsigned long) value);
21532 newimm |= (temp & 0xfffff000);
21533 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21536 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21538 unsigned int highpart = 0;
21539 unsigned int newinsn = 0xe1a00000; /* nop. */
21541 if (fixP->fx_addsy)
21543 const char *msg = 0;
21545 if (! S_IS_DEFINED (fixP->fx_addsy))
21546 msg = _("undefined symbol %s used as an immediate value");
21547 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21548 msg = _("symbol %s is in a different section");
21549 else if (S_IS_WEAK (fixP->fx_addsy))
21550 msg = _("symbol %s is weak and may be overridden later");
21554 as_bad_where (fixP->fx_file, fixP->fx_line,
21555 msg, S_GET_NAME (fixP->fx_addsy));
21560 newimm = encode_arm_immediate (value);
21561 temp = md_chars_to_number (buf, INSN_SIZE);
21563 /* If the instruction will fail, see if we can fix things up by
21564 changing the opcode. */
21565 if (newimm == (unsigned int) FAIL
21566 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21568 /* No ? OK - try using two ADD instructions to generate
21570 newimm = validate_immediate_twopart (value, & highpart);
21572 /* Yes - then make sure that the second instruction is
21574 if (newimm != (unsigned int) FAIL)
21576 /* Still No ? Try using a negated value. */
21577 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21578 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21579 /* Otherwise - give up. */
21582 as_bad_where (fixP->fx_file, fixP->fx_line,
21583 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21588 /* Replace the first operand in the 2nd instruction (which
21589 is the PC) with the destination register. We have
21590 already added in the PC in the first instruction and we
21591 do not want to do it again. */
21592 newinsn &= ~ 0xf0000;
21593 newinsn |= ((newinsn & 0x0f000) << 4);
21596 newimm |= (temp & 0xfffff000);
21597 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21599 highpart |= (newinsn & 0xfffff000);
21600 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21604 case BFD_RELOC_ARM_OFFSET_IMM:
21605 if (!fixP->fx_done && seg->use_rela_p)
21608 case BFD_RELOC_ARM_LITERAL:
21614 if (validate_offset_imm (value, 0) == FAIL)
21616 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21617 as_bad_where (fixP->fx_file, fixP->fx_line,
21618 _("invalid literal constant: pool needs to be closer"));
21620 as_bad_where (fixP->fx_file, fixP->fx_line,
21621 _("bad immediate value for offset (%ld)"),
21626 newval = md_chars_to_number (buf, INSN_SIZE);
21628 newval &= 0xfffff000;
21631 newval &= 0xff7ff000;
21632 newval |= value | (sign ? INDEX_UP : 0);
21634 md_number_to_chars (buf, newval, INSN_SIZE);
21637 case BFD_RELOC_ARM_OFFSET_IMM8:
21638 case BFD_RELOC_ARM_HWLITERAL:
21644 if (validate_offset_imm (value, 1) == FAIL)
21646 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21647 as_bad_where (fixP->fx_file, fixP->fx_line,
21648 _("invalid literal constant: pool needs to be closer"));
21650 as_bad_where (fixP->fx_file, fixP->fx_line,
21651 _("bad immediate value for 8-bit offset (%ld)"),
21656 newval = md_chars_to_number (buf, INSN_SIZE);
21658 newval &= 0xfffff0f0;
21661 newval &= 0xff7ff0f0;
21662 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21664 md_number_to_chars (buf, newval, INSN_SIZE);
21667 case BFD_RELOC_ARM_T32_OFFSET_U8:
21668 if (value < 0 || value > 1020 || value % 4 != 0)
21669 as_bad_where (fixP->fx_file, fixP->fx_line,
21670 _("bad immediate value for offset (%ld)"), (long) value);
21673 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21675 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21678 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21679 /* This is a complicated relocation used for all varieties of Thumb32
21680 load/store instruction with immediate offset:
21682 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21683 *4, optional writeback(W)
21684 (doubleword load/store)
21686 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21687 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21688 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21689 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21690 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21692 Uppercase letters indicate bits that are already encoded at
21693 this point. Lowercase letters are our problem. For the
21694 second block of instructions, the secondary opcode nybble
21695 (bits 8..11) is present, and bit 23 is zero, even if this is
21696 a PC-relative operation. */
21697 newval = md_chars_to_number (buf, THUMB_SIZE);
21699 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21701 if ((newval & 0xf0000000) == 0xe0000000)
21703 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21705 newval |= (1 << 23);
21708 if (value % 4 != 0)
21710 as_bad_where (fixP->fx_file, fixP->fx_line,
21711 _("offset not a multiple of 4"));
21717 as_bad_where (fixP->fx_file, fixP->fx_line,
21718 _("offset out of range"));
21723 else if ((newval & 0x000f0000) == 0x000f0000)
21725 /* PC-relative, 12-bit offset. */
21727 newval |= (1 << 23);
21732 as_bad_where (fixP->fx_file, fixP->fx_line,
21733 _("offset out of range"));
21738 else if ((newval & 0x00000100) == 0x00000100)
21740 /* Writeback: 8-bit, +/- offset. */
21742 newval |= (1 << 9);
21747 as_bad_where (fixP->fx_file, fixP->fx_line,
21748 _("offset out of range"));
21753 else if ((newval & 0x00000f00) == 0x00000e00)
21755 /* T-instruction: positive 8-bit offset. */
21756 if (value < 0 || value > 0xff)
21758 as_bad_where (fixP->fx_file, fixP->fx_line,
21759 _("offset out of range"));
21767 /* Positive 12-bit or negative 8-bit offset. */
21771 newval |= (1 << 23);
21781 as_bad_where (fixP->fx_file, fixP->fx_line,
21782 _("offset out of range"));
21789 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21790 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21793 case BFD_RELOC_ARM_SHIFT_IMM:
21794 newval = md_chars_to_number (buf, INSN_SIZE);
21795 if (((unsigned long) value) > 32
21797 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21799 as_bad_where (fixP->fx_file, fixP->fx_line,
21800 _("shift expression is too large"));
21805 /* Shifts of zero must be done as lsl. */
21807 else if (value == 32)
21809 newval &= 0xfffff07f;
21810 newval |= (value & 0x1f) << 7;
21811 md_number_to_chars (buf, newval, INSN_SIZE);
21814 case BFD_RELOC_ARM_T32_IMMEDIATE:
21815 case BFD_RELOC_ARM_T32_ADD_IMM:
21816 case BFD_RELOC_ARM_T32_IMM12:
21817 case BFD_RELOC_ARM_T32_ADD_PC12:
21818 /* We claim that this fixup has been processed here,
21819 even if in fact we generate an error because we do
21820 not have a reloc for it, so tc_gen_reloc will reject it. */
21824 && ! S_IS_DEFINED (fixP->fx_addsy))
21826 as_bad_where (fixP->fx_file, fixP->fx_line,
21827 _("undefined symbol %s used as an immediate value"),
21828 S_GET_NAME (fixP->fx_addsy));
21832 newval = md_chars_to_number (buf, THUMB_SIZE);
21834 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21837 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21838 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21840 newimm = encode_thumb32_immediate (value);
21841 if (newimm == (unsigned int) FAIL)
21842 newimm = thumb32_negate_data_op (&newval, value);
21844 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21845 && newimm == (unsigned int) FAIL)
21847 /* Turn add/sum into addw/subw. */
21848 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21849 newval = (newval & 0xfeffffff) | 0x02000000;
21850 /* No flat 12-bit imm encoding for addsw/subsw. */
21851 if ((newval & 0x00100000) == 0)
21853 /* 12 bit immediate for addw/subw. */
21857 newval ^= 0x00a00000;
21860 newimm = (unsigned int) FAIL;
21866 if (newimm == (unsigned int)FAIL)
21868 as_bad_where (fixP->fx_file, fixP->fx_line,
21869 _("invalid constant (%lx) after fixup"),
21870 (unsigned long) value);
21874 newval |= (newimm & 0x800) << 15;
21875 newval |= (newimm & 0x700) << 4;
21876 newval |= (newimm & 0x0ff);
21878 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21879 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21882 case BFD_RELOC_ARM_SMC:
21883 if (((unsigned long) value) > 0xffff)
21884 as_bad_where (fixP->fx_file, fixP->fx_line,
21885 _("invalid smc expression"));
21886 newval = md_chars_to_number (buf, INSN_SIZE);
21887 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21888 md_number_to_chars (buf, newval, INSN_SIZE);
21891 case BFD_RELOC_ARM_HVC:
21892 if (((unsigned long) value) > 0xffff)
21893 as_bad_where (fixP->fx_file, fixP->fx_line,
21894 _("invalid hvc expression"));
21895 newval = md_chars_to_number (buf, INSN_SIZE);
21896 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21897 md_number_to_chars (buf, newval, INSN_SIZE);
21900 case BFD_RELOC_ARM_SWI:
21901 if (fixP->tc_fix_data != 0)
21903 if (((unsigned long) value) > 0xff)
21904 as_bad_where (fixP->fx_file, fixP->fx_line,
21905 _("invalid swi expression"));
21906 newval = md_chars_to_number (buf, THUMB_SIZE);
21908 md_number_to_chars (buf, newval, THUMB_SIZE);
21912 if (((unsigned long) value) > 0x00ffffff)
21913 as_bad_where (fixP->fx_file, fixP->fx_line,
21914 _("invalid swi expression"));
21915 newval = md_chars_to_number (buf, INSN_SIZE);
21917 md_number_to_chars (buf, newval, INSN_SIZE);
21921 case BFD_RELOC_ARM_MULTI:
21922 if (((unsigned long) value) > 0xffff)
21923 as_bad_where (fixP->fx_file, fixP->fx_line,
21924 _("invalid expression in load/store multiple"));
21925 newval = value | md_chars_to_number (buf, INSN_SIZE);
21926 md_number_to_chars (buf, newval, INSN_SIZE);
21930 case BFD_RELOC_ARM_PCREL_CALL:
21932 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21934 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21935 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21936 && THUMB_IS_FUNC (fixP->fx_addsy))
21937 /* Flip the bl to blx. This is a simple flip
21938 bit here because we generate PCREL_CALL for
21939 unconditional bls. */
21941 newval = md_chars_to_number (buf, INSN_SIZE);
21942 newval = newval | 0x10000000;
21943 md_number_to_chars (buf, newval, INSN_SIZE);
21949 goto arm_branch_common;
21951 case BFD_RELOC_ARM_PCREL_JUMP:
21952 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21954 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21955 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21956 && THUMB_IS_FUNC (fixP->fx_addsy))
21958 /* This would map to a bl<cond>, b<cond>,
21959 b<always> to a Thumb function. We
21960 need to force a relocation for this particular
21962 newval = md_chars_to_number (buf, INSN_SIZE);
21966 case BFD_RELOC_ARM_PLT32:
21968 case BFD_RELOC_ARM_PCREL_BRANCH:
21970 goto arm_branch_common;
21972 case BFD_RELOC_ARM_PCREL_BLX:
21975 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21977 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21978 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21979 && ARM_IS_FUNC (fixP->fx_addsy))
21981 /* Flip the blx to a bl and warn. */
21982 const char *name = S_GET_NAME (fixP->fx_addsy);
21983 newval = 0xeb000000;
21984 as_warn_where (fixP->fx_file, fixP->fx_line,
21985 _("blx to '%s' an ARM ISA state function changed to bl"),
21987 md_number_to_chars (buf, newval, INSN_SIZE);
21993 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21994 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21998 /* We are going to store value (shifted right by two) in the
21999 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22000 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22001 also be be clear. */
22003 as_bad_where (fixP->fx_file, fixP->fx_line,
22004 _("misaligned branch destination"));
22005 if ((value & (offsetT)0xfe000000) != (offsetT)0
22006 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
22007 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22009 if (fixP->fx_done || !seg->use_rela_p)
22011 newval = md_chars_to_number (buf, INSN_SIZE);
22012 newval |= (value >> 2) & 0x00ffffff;
22013 /* Set the H bit on BLX instructions. */
22017 newval |= 0x01000000;
22019 newval &= ~0x01000000;
22021 md_number_to_chars (buf, newval, INSN_SIZE);
22025 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22026 /* CBZ can only branch forward. */
22028 /* Attempts to use CBZ to branch to the next instruction
22029 (which, strictly speaking, are prohibited) will be turned into
22032 FIXME: It may be better to remove the instruction completely and
22033 perform relaxation. */
22036 newval = md_chars_to_number (buf, THUMB_SIZE);
22037 newval = 0xbf00; /* NOP encoding T1 */
22038 md_number_to_chars (buf, newval, THUMB_SIZE);
22043 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22045 if (fixP->fx_done || !seg->use_rela_p)
22047 newval = md_chars_to_number (buf, THUMB_SIZE);
22048 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22049 md_number_to_chars (buf, newval, THUMB_SIZE);
22054 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22055 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22056 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22058 if (fixP->fx_done || !seg->use_rela_p)
22060 newval = md_chars_to_number (buf, THUMB_SIZE);
22061 newval |= (value & 0x1ff) >> 1;
22062 md_number_to_chars (buf, newval, THUMB_SIZE);
22066 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22067 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22068 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22070 if (fixP->fx_done || !seg->use_rela_p)
22072 newval = md_chars_to_number (buf, THUMB_SIZE);
22073 newval |= (value & 0xfff) >> 1;
22074 md_number_to_chars (buf, newval, THUMB_SIZE);
22078 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22080 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22081 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22082 && ARM_IS_FUNC (fixP->fx_addsy)
22083 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22085 /* Force a relocation for a branch 20 bits wide. */
22088 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22089 as_bad_where (fixP->fx_file, fixP->fx_line,
22090 _("conditional branch out of range"));
22092 if (fixP->fx_done || !seg->use_rela_p)
22095 addressT S, J1, J2, lo, hi;
22097 S = (value & 0x00100000) >> 20;
22098 J2 = (value & 0x00080000) >> 19;
22099 J1 = (value & 0x00040000) >> 18;
22100 hi = (value & 0x0003f000) >> 12;
22101 lo = (value & 0x00000ffe) >> 1;
22103 newval = md_chars_to_number (buf, THUMB_SIZE);
22104 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22105 newval |= (S << 10) | hi;
22106 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22107 md_number_to_chars (buf, newval, THUMB_SIZE);
22108 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22112 case BFD_RELOC_THUMB_PCREL_BLX:
22113 /* If there is a blx from a thumb state function to
22114 another thumb function flip this to a bl and warn
22118 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22119 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22120 && THUMB_IS_FUNC (fixP->fx_addsy))
22122 const char *name = S_GET_NAME (fixP->fx_addsy);
22123 as_warn_where (fixP->fx_file, fixP->fx_line,
22124 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22126 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22127 newval = newval | 0x1000;
22128 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22129 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22134 goto thumb_bl_common;
22136 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22137 /* A bl from Thumb state ISA to an internal ARM state function
22138 is converted to a blx. */
22140 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22141 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22142 && ARM_IS_FUNC (fixP->fx_addsy)
22143 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22145 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22146 newval = newval & ~0x1000;
22147 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22148 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22154 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22155 /* For a BLX instruction, make sure that the relocation is rounded up
22156 to a word boundary. This follows the semantics of the instruction
22157 which specifies that bit 1 of the target address will come from bit
22158 1 of the base address. */
22159 value = (value + 3) & ~ 3;
22162 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22163 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22164 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22167 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22169 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22170 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22171 else if ((value & ~0x1ffffff)
22172 && ((value & ~0x1ffffff) != ~0x1ffffff))
22173 as_bad_where (fixP->fx_file, fixP->fx_line,
22174 _("Thumb2 branch out of range"));
22177 if (fixP->fx_done || !seg->use_rela_p)
22178 encode_thumb2_b_bl_offset (buf, value);
22182 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22183 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22184 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22186 if (fixP->fx_done || !seg->use_rela_p)
22187 encode_thumb2_b_bl_offset (buf, value);
22192 if (fixP->fx_done || !seg->use_rela_p)
22193 md_number_to_chars (buf, value, 1);
22197 if (fixP->fx_done || !seg->use_rela_p)
22198 md_number_to_chars (buf, value, 2);
22202 case BFD_RELOC_ARM_TLS_CALL:
22203 case BFD_RELOC_ARM_THM_TLS_CALL:
22204 case BFD_RELOC_ARM_TLS_DESCSEQ:
22205 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22206 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22209 case BFD_RELOC_ARM_TLS_GOTDESC:
22210 case BFD_RELOC_ARM_TLS_GD32:
22211 case BFD_RELOC_ARM_TLS_LE32:
22212 case BFD_RELOC_ARM_TLS_IE32:
22213 case BFD_RELOC_ARM_TLS_LDM32:
22214 case BFD_RELOC_ARM_TLS_LDO32:
22215 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22218 case BFD_RELOC_ARM_GOT32:
22219 case BFD_RELOC_ARM_GOTOFF:
22220 if (fixP->fx_done || !seg->use_rela_p)
22221 md_number_to_chars (buf, 0, 4);
22224 case BFD_RELOC_ARM_GOT_PREL:
22225 if (fixP->fx_done || !seg->use_rela_p)
22226 md_number_to_chars (buf, value, 4);
22229 case BFD_RELOC_ARM_TARGET2:
22230 /* TARGET2 is not partial-inplace, so we need to write the
22231 addend here for REL targets, because it won't be written out
22232 during reloc processing later. */
22233 if (fixP->fx_done || !seg->use_rela_p)
22234 md_number_to_chars (buf, fixP->fx_offset, 4);
22238 case BFD_RELOC_RVA:
22240 case BFD_RELOC_ARM_TARGET1:
22241 case BFD_RELOC_ARM_ROSEGREL32:
22242 case BFD_RELOC_ARM_SBREL32:
22243 case BFD_RELOC_32_PCREL:
22245 case BFD_RELOC_32_SECREL:
22247 if (fixP->fx_done || !seg->use_rela_p)
22249 /* For WinCE we only do this for pcrel fixups. */
22250 if (fixP->fx_done || fixP->fx_pcrel)
22252 md_number_to_chars (buf, value, 4);
22256 case BFD_RELOC_ARM_PREL31:
22257 if (fixP->fx_done || !seg->use_rela_p)
22259 newval = md_chars_to_number (buf, 4) & 0x80000000;
22260 if ((value ^ (value >> 1)) & 0x40000000)
22262 as_bad_where (fixP->fx_file, fixP->fx_line,
22263 _("rel31 relocation overflow"));
22265 newval |= value & 0x7fffffff;
22266 md_number_to_chars (buf, newval, 4);
22271 case BFD_RELOC_ARM_CP_OFF_IMM:
22272 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22273 if (value < -1023 || value > 1023 || (value & 3))
22274 as_bad_where (fixP->fx_file, fixP->fx_line,
22275 _("co-processor offset out of range"));
22280 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22281 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22282 newval = md_chars_to_number (buf, INSN_SIZE);
22284 newval = get_thumb32_insn (buf);
22286 newval &= 0xffffff00;
22289 newval &= 0xff7fff00;
22290 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22292 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22293 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22294 md_number_to_chars (buf, newval, INSN_SIZE);
22296 put_thumb32_insn (buf, newval);
22299 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22300 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22301 if (value < -255 || value > 255)
22302 as_bad_where (fixP->fx_file, fixP->fx_line,
22303 _("co-processor offset out of range"));
22305 goto cp_off_common;
22307 case BFD_RELOC_ARM_THUMB_OFFSET:
22308 newval = md_chars_to_number (buf, THUMB_SIZE);
22309 /* Exactly what ranges, and where the offset is inserted depends
22310 on the type of instruction, we can establish this from the
22312 switch (newval >> 12)
22314 case 4: /* PC load. */
22315 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22316 forced to zero for these loads; md_pcrel_from has already
22317 compensated for this. */
22319 as_bad_where (fixP->fx_file, fixP->fx_line,
22320 _("invalid offset, target not word aligned (0x%08lX)"),
22321 (((unsigned long) fixP->fx_frag->fr_address
22322 + (unsigned long) fixP->fx_where) & ~3)
22323 + (unsigned long) value);
22325 if (value & ~0x3fc)
22326 as_bad_where (fixP->fx_file, fixP->fx_line,
22327 _("invalid offset, value too big (0x%08lX)"),
22330 newval |= value >> 2;
22333 case 9: /* SP load/store. */
22334 if (value & ~0x3fc)
22335 as_bad_where (fixP->fx_file, fixP->fx_line,
22336 _("invalid offset, value too big (0x%08lX)"),
22338 newval |= value >> 2;
22341 case 6: /* Word load/store. */
22343 as_bad_where (fixP->fx_file, fixP->fx_line,
22344 _("invalid offset, value too big (0x%08lX)"),
22346 newval |= value << 4; /* 6 - 2. */
22349 case 7: /* Byte load/store. */
22351 as_bad_where (fixP->fx_file, fixP->fx_line,
22352 _("invalid offset, value too big (0x%08lX)"),
22354 newval |= value << 6;
22357 case 8: /* Halfword load/store. */
22359 as_bad_where (fixP->fx_file, fixP->fx_line,
22360 _("invalid offset, value too big (0x%08lX)"),
22362 newval |= value << 5; /* 6 - 1. */
22366 as_bad_where (fixP->fx_file, fixP->fx_line,
22367 "Unable to process relocation for thumb opcode: %lx",
22368 (unsigned long) newval);
22371 md_number_to_chars (buf, newval, THUMB_SIZE);
22374 case BFD_RELOC_ARM_THUMB_ADD:
22375 /* This is a complicated relocation, since we use it for all of
22376 the following immediate relocations:
22380 9bit ADD/SUB SP word-aligned
22381 10bit ADD PC/SP word-aligned
22383 The type of instruction being processed is encoded in the
22390 newval = md_chars_to_number (buf, THUMB_SIZE);
22392 int rd = (newval >> 4) & 0xf;
22393 int rs = newval & 0xf;
22394 int subtract = !!(newval & 0x8000);
22396 /* Check for HI regs, only very restricted cases allowed:
22397 Adjusting SP, and using PC or SP to get an address. */
22398 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22399 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22400 as_bad_where (fixP->fx_file, fixP->fx_line,
22401 _("invalid Hi register with immediate"));
22403 /* If value is negative, choose the opposite instruction. */
22407 subtract = !subtract;
22409 as_bad_where (fixP->fx_file, fixP->fx_line,
22410 _("immediate value out of range"));
22415 if (value & ~0x1fc)
22416 as_bad_where (fixP->fx_file, fixP->fx_line,
22417 _("invalid immediate for stack address calculation"));
22418 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22419 newval |= value >> 2;
22421 else if (rs == REG_PC || rs == REG_SP)
22423 if (subtract || value & ~0x3fc)
22424 as_bad_where (fixP->fx_file, fixP->fx_line,
22425 _("invalid immediate for address calculation (value = 0x%08lX)"),
22426 (unsigned long) value);
22427 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22429 newval |= value >> 2;
22434 as_bad_where (fixP->fx_file, fixP->fx_line,
22435 _("immediate value out of range"));
22436 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22437 newval |= (rd << 8) | value;
22442 as_bad_where (fixP->fx_file, fixP->fx_line,
22443 _("immediate value out of range"));
22444 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22445 newval |= rd | (rs << 3) | (value << 6);
22448 md_number_to_chars (buf, newval, THUMB_SIZE);
22451 case BFD_RELOC_ARM_THUMB_IMM:
22452 newval = md_chars_to_number (buf, THUMB_SIZE);
22453 if (value < 0 || value > 255)
22454 as_bad_where (fixP->fx_file, fixP->fx_line,
22455 _("invalid immediate: %ld is out of range"),
22458 md_number_to_chars (buf, newval, THUMB_SIZE);
22461 case BFD_RELOC_ARM_THUMB_SHIFT:
22462 /* 5bit shift value (0..32). LSL cannot take 32. */
22463 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22464 temp = newval & 0xf800;
22465 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22466 as_bad_where (fixP->fx_file, fixP->fx_line,
22467 _("invalid shift value: %ld"), (long) value);
22468 /* Shifts of zero must be encoded as LSL. */
22470 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22471 /* Shifts of 32 are encoded as zero. */
22472 else if (value == 32)
22474 newval |= value << 6;
22475 md_number_to_chars (buf, newval, THUMB_SIZE);
22478 case BFD_RELOC_VTABLE_INHERIT:
22479 case BFD_RELOC_VTABLE_ENTRY:
22483 case BFD_RELOC_ARM_MOVW:
22484 case BFD_RELOC_ARM_MOVT:
22485 case BFD_RELOC_ARM_THUMB_MOVW:
22486 case BFD_RELOC_ARM_THUMB_MOVT:
22487 if (fixP->fx_done || !seg->use_rela_p)
22489 /* REL format relocations are limited to a 16-bit addend. */
22490 if (!fixP->fx_done)
22492 if (value < -0x8000 || value > 0x7fff)
22493 as_bad_where (fixP->fx_file, fixP->fx_line,
22494 _("offset out of range"));
22496 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22497 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22502 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22503 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22505 newval = get_thumb32_insn (buf);
22506 newval &= 0xfbf08f00;
22507 newval |= (value & 0xf000) << 4;
22508 newval |= (value & 0x0800) << 15;
22509 newval |= (value & 0x0700) << 4;
22510 newval |= (value & 0x00ff);
22511 put_thumb32_insn (buf, newval);
22515 newval = md_chars_to_number (buf, 4);
22516 newval &= 0xfff0f000;
22517 newval |= value & 0x0fff;
22518 newval |= (value & 0xf000) << 4;
22519 md_number_to_chars (buf, newval, 4);
22524 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22525 case BFD_RELOC_ARM_ALU_PC_G0:
22526 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22527 case BFD_RELOC_ARM_ALU_PC_G1:
22528 case BFD_RELOC_ARM_ALU_PC_G2:
22529 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22530 case BFD_RELOC_ARM_ALU_SB_G0:
22531 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22532 case BFD_RELOC_ARM_ALU_SB_G1:
22533 case BFD_RELOC_ARM_ALU_SB_G2:
22534 gas_assert (!fixP->fx_done);
22535 if (!seg->use_rela_p)
22538 bfd_vma encoded_addend;
22539 bfd_vma addend_abs = abs (value);
22541 /* Check that the absolute value of the addend can be
22542 expressed as an 8-bit constant plus a rotation. */
22543 encoded_addend = encode_arm_immediate (addend_abs);
22544 if (encoded_addend == (unsigned int) FAIL)
22545 as_bad_where (fixP->fx_file, fixP->fx_line,
22546 _("the offset 0x%08lX is not representable"),
22547 (unsigned long) addend_abs);
22549 /* Extract the instruction. */
22550 insn = md_chars_to_number (buf, INSN_SIZE);
22552 /* If the addend is positive, use an ADD instruction.
22553 Otherwise use a SUB. Take care not to destroy the S bit. */
22554 insn &= 0xff1fffff;
22560 /* Place the encoded addend into the first 12 bits of the
22562 insn &= 0xfffff000;
22563 insn |= encoded_addend;
22565 /* Update the instruction. */
22566 md_number_to_chars (buf, insn, INSN_SIZE);
22570 case BFD_RELOC_ARM_LDR_PC_G0:
22571 case BFD_RELOC_ARM_LDR_PC_G1:
22572 case BFD_RELOC_ARM_LDR_PC_G2:
22573 case BFD_RELOC_ARM_LDR_SB_G0:
22574 case BFD_RELOC_ARM_LDR_SB_G1:
22575 case BFD_RELOC_ARM_LDR_SB_G2:
22576 gas_assert (!fixP->fx_done);
22577 if (!seg->use_rela_p)
22580 bfd_vma addend_abs = abs (value);
22582 /* Check that the absolute value of the addend can be
22583 encoded in 12 bits. */
22584 if (addend_abs >= 0x1000)
22585 as_bad_where (fixP->fx_file, fixP->fx_line,
22586 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22587 (unsigned long) addend_abs);
22589 /* Extract the instruction. */
22590 insn = md_chars_to_number (buf, INSN_SIZE);
22592 /* If the addend is negative, clear bit 23 of the instruction.
22593 Otherwise set it. */
22595 insn &= ~(1 << 23);
22599 /* Place the absolute value of the addend into the first 12 bits
22600 of the instruction. */
22601 insn &= 0xfffff000;
22602 insn |= addend_abs;
22604 /* Update the instruction. */
22605 md_number_to_chars (buf, insn, INSN_SIZE);
22609 case BFD_RELOC_ARM_LDRS_PC_G0:
22610 case BFD_RELOC_ARM_LDRS_PC_G1:
22611 case BFD_RELOC_ARM_LDRS_PC_G2:
22612 case BFD_RELOC_ARM_LDRS_SB_G0:
22613 case BFD_RELOC_ARM_LDRS_SB_G1:
22614 case BFD_RELOC_ARM_LDRS_SB_G2:
22615 gas_assert (!fixP->fx_done);
22616 if (!seg->use_rela_p)
22619 bfd_vma addend_abs = abs (value);
22621 /* Check that the absolute value of the addend can be
22622 encoded in 8 bits. */
22623 if (addend_abs >= 0x100)
22624 as_bad_where (fixP->fx_file, fixP->fx_line,
22625 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22626 (unsigned long) addend_abs);
22628 /* Extract the instruction. */
22629 insn = md_chars_to_number (buf, INSN_SIZE);
22631 /* If the addend is negative, clear bit 23 of the instruction.
22632 Otherwise set it. */
22634 insn &= ~(1 << 23);
22638 /* Place the first four bits of the absolute value of the addend
22639 into the first 4 bits of the instruction, and the remaining
22640 four into bits 8 .. 11. */
22641 insn &= 0xfffff0f0;
22642 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22644 /* Update the instruction. */
22645 md_number_to_chars (buf, insn, INSN_SIZE);
22649 case BFD_RELOC_ARM_LDC_PC_G0:
22650 case BFD_RELOC_ARM_LDC_PC_G1:
22651 case BFD_RELOC_ARM_LDC_PC_G2:
22652 case BFD_RELOC_ARM_LDC_SB_G0:
22653 case BFD_RELOC_ARM_LDC_SB_G1:
22654 case BFD_RELOC_ARM_LDC_SB_G2:
22655 gas_assert (!fixP->fx_done);
22656 if (!seg->use_rela_p)
22659 bfd_vma addend_abs = abs (value);
22661 /* Check that the absolute value of the addend is a multiple of
22662 four and, when divided by four, fits in 8 bits. */
22663 if (addend_abs & 0x3)
22664 as_bad_where (fixP->fx_file, fixP->fx_line,
22665 _("bad offset 0x%08lX (must be word-aligned)"),
22666 (unsigned long) addend_abs);
22668 if ((addend_abs >> 2) > 0xff)
22669 as_bad_where (fixP->fx_file, fixP->fx_line,
22670 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22671 (unsigned long) addend_abs);
22673 /* Extract the instruction. */
22674 insn = md_chars_to_number (buf, INSN_SIZE);
22676 /* If the addend is negative, clear bit 23 of the instruction.
22677 Otherwise set it. */
22679 insn &= ~(1 << 23);
22683 /* Place the addend (divided by four) into the first eight
22684 bits of the instruction. */
22685 insn &= 0xfffffff0;
22686 insn |= addend_abs >> 2;
22688 /* Update the instruction. */
22689 md_number_to_chars (buf, insn, INSN_SIZE);
22693 case BFD_RELOC_ARM_V4BX:
22694 /* This will need to go in the object file. */
22698 case BFD_RELOC_UNUSED:
22700 as_bad_where (fixP->fx_file, fixP->fx_line,
22701 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22705 /* Translate internal representation of relocation info to BFD target
22709 tc_gen_reloc (asection *section, fixS *fixp)
22712 bfd_reloc_code_real_type code;
22714 reloc = (arelent *) xmalloc (sizeof (arelent));
22716 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22717 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22718 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22720 if (fixp->fx_pcrel)
22722 if (section->use_rela_p)
22723 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22725 fixp->fx_offset = reloc->address;
22727 reloc->addend = fixp->fx_offset;
22729 switch (fixp->fx_r_type)
22732 if (fixp->fx_pcrel)
22734 code = BFD_RELOC_8_PCREL;
22739 if (fixp->fx_pcrel)
22741 code = BFD_RELOC_16_PCREL;
22746 if (fixp->fx_pcrel)
22748 code = BFD_RELOC_32_PCREL;
22752 case BFD_RELOC_ARM_MOVW:
22753 if (fixp->fx_pcrel)
22755 code = BFD_RELOC_ARM_MOVW_PCREL;
22759 case BFD_RELOC_ARM_MOVT:
22760 if (fixp->fx_pcrel)
22762 code = BFD_RELOC_ARM_MOVT_PCREL;
22766 case BFD_RELOC_ARM_THUMB_MOVW:
22767 if (fixp->fx_pcrel)
22769 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22773 case BFD_RELOC_ARM_THUMB_MOVT:
22774 if (fixp->fx_pcrel)
22776 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22780 case BFD_RELOC_NONE:
22781 case BFD_RELOC_ARM_PCREL_BRANCH:
22782 case BFD_RELOC_ARM_PCREL_BLX:
22783 case BFD_RELOC_RVA:
22784 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22785 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22786 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22787 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22788 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22789 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22790 case BFD_RELOC_VTABLE_ENTRY:
22791 case BFD_RELOC_VTABLE_INHERIT:
22793 case BFD_RELOC_32_SECREL:
22795 code = fixp->fx_r_type;
22798 case BFD_RELOC_THUMB_PCREL_BLX:
22800 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22801 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22804 code = BFD_RELOC_THUMB_PCREL_BLX;
22807 case BFD_RELOC_ARM_LITERAL:
22808 case BFD_RELOC_ARM_HWLITERAL:
22809 /* If this is called then the a literal has
22810 been referenced across a section boundary. */
22811 as_bad_where (fixp->fx_file, fixp->fx_line,
22812 _("literal referenced across section boundary"));
22816 case BFD_RELOC_ARM_TLS_CALL:
22817 case BFD_RELOC_ARM_THM_TLS_CALL:
22818 case BFD_RELOC_ARM_TLS_DESCSEQ:
22819 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22820 case BFD_RELOC_ARM_GOT32:
22821 case BFD_RELOC_ARM_GOTOFF:
22822 case BFD_RELOC_ARM_GOT_PREL:
22823 case BFD_RELOC_ARM_PLT32:
22824 case BFD_RELOC_ARM_TARGET1:
22825 case BFD_RELOC_ARM_ROSEGREL32:
22826 case BFD_RELOC_ARM_SBREL32:
22827 case BFD_RELOC_ARM_PREL31:
22828 case BFD_RELOC_ARM_TARGET2:
22829 case BFD_RELOC_ARM_TLS_LE32:
22830 case BFD_RELOC_ARM_TLS_LDO32:
22831 case BFD_RELOC_ARM_PCREL_CALL:
22832 case BFD_RELOC_ARM_PCREL_JUMP:
22833 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22834 case BFD_RELOC_ARM_ALU_PC_G0:
22835 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22836 case BFD_RELOC_ARM_ALU_PC_G1:
22837 case BFD_RELOC_ARM_ALU_PC_G2:
22838 case BFD_RELOC_ARM_LDR_PC_G0:
22839 case BFD_RELOC_ARM_LDR_PC_G1:
22840 case BFD_RELOC_ARM_LDR_PC_G2:
22841 case BFD_RELOC_ARM_LDRS_PC_G0:
22842 case BFD_RELOC_ARM_LDRS_PC_G1:
22843 case BFD_RELOC_ARM_LDRS_PC_G2:
22844 case BFD_RELOC_ARM_LDC_PC_G0:
22845 case BFD_RELOC_ARM_LDC_PC_G1:
22846 case BFD_RELOC_ARM_LDC_PC_G2:
22847 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22848 case BFD_RELOC_ARM_ALU_SB_G0:
22849 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22850 case BFD_RELOC_ARM_ALU_SB_G1:
22851 case BFD_RELOC_ARM_ALU_SB_G2:
22852 case BFD_RELOC_ARM_LDR_SB_G0:
22853 case BFD_RELOC_ARM_LDR_SB_G1:
22854 case BFD_RELOC_ARM_LDR_SB_G2:
22855 case BFD_RELOC_ARM_LDRS_SB_G0:
22856 case BFD_RELOC_ARM_LDRS_SB_G1:
22857 case BFD_RELOC_ARM_LDRS_SB_G2:
22858 case BFD_RELOC_ARM_LDC_SB_G0:
22859 case BFD_RELOC_ARM_LDC_SB_G1:
22860 case BFD_RELOC_ARM_LDC_SB_G2:
22861 case BFD_RELOC_ARM_V4BX:
22862 code = fixp->fx_r_type;
22865 case BFD_RELOC_ARM_TLS_GOTDESC:
22866 case BFD_RELOC_ARM_TLS_GD32:
22867 case BFD_RELOC_ARM_TLS_IE32:
22868 case BFD_RELOC_ARM_TLS_LDM32:
22869 /* BFD will include the symbol's address in the addend.
22870 But we don't want that, so subtract it out again here. */
22871 if (!S_IS_COMMON (fixp->fx_addsy))
22872 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22873 code = fixp->fx_r_type;
22877 case BFD_RELOC_ARM_IMMEDIATE:
22878 as_bad_where (fixp->fx_file, fixp->fx_line,
22879 _("internal relocation (type: IMMEDIATE) not fixed up"));
22882 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22883 as_bad_where (fixp->fx_file, fixp->fx_line,
22884 _("ADRL used for a symbol not defined in the same file"));
22887 case BFD_RELOC_ARM_OFFSET_IMM:
22888 if (section->use_rela_p)
22890 code = fixp->fx_r_type;
22894 if (fixp->fx_addsy != NULL
22895 && !S_IS_DEFINED (fixp->fx_addsy)
22896 && S_IS_LOCAL (fixp->fx_addsy))
22898 as_bad_where (fixp->fx_file, fixp->fx_line,
22899 _("undefined local label `%s'"),
22900 S_GET_NAME (fixp->fx_addsy));
22904 as_bad_where (fixp->fx_file, fixp->fx_line,
22905 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22912 switch (fixp->fx_r_type)
22914 case BFD_RELOC_NONE: type = "NONE"; break;
22915 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22916 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22917 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22918 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22919 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22920 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22921 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22922 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22923 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22924 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22925 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22926 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22927 default: type = _("<unknown>"); break;
22929 as_bad_where (fixp->fx_file, fixp->fx_line,
22930 _("cannot represent %s relocation in this object file format"),
22937 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22939 && fixp->fx_addsy == GOT_symbol)
22941 code = BFD_RELOC_ARM_GOTPC;
22942 reloc->addend = fixp->fx_offset = reloc->address;
22946 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22948 if (reloc->howto == NULL)
22950 as_bad_where (fixp->fx_file, fixp->fx_line,
22951 _("cannot represent %s relocation in this object file format"),
22952 bfd_get_reloc_code_name (code));
22956 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22957 vtable entry to be used in the relocation's section offset. */
22958 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22959 reloc->address = fixp->fx_offset;
22964 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22967 cons_fix_new_arm (fragS * frag,
22972 bfd_reloc_code_real_type type;
22976 FIXME: @@ Should look at CPU word size. */
22980 type = BFD_RELOC_8;
22983 type = BFD_RELOC_16;
22987 type = BFD_RELOC_32;
22990 type = BFD_RELOC_64;
22995 if (exp->X_op == O_secrel)
22997 exp->X_op = O_symbol;
22998 type = BFD_RELOC_32_SECREL;
23002 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
23005 #if defined (OBJ_COFF)
23007 arm_validate_fix (fixS * fixP)
23009 /* If the destination of the branch is a defined symbol which does not have
23010 the THUMB_FUNC attribute, then we must be calling a function which has
23011 the (interfacearm) attribute. We look for the Thumb entry point to that
23012 function and change the branch to refer to that function instead. */
23013 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23014 && fixP->fx_addsy != NULL
23015 && S_IS_DEFINED (fixP->fx_addsy)
23016 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23018 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23025 arm_force_relocation (struct fix * fixp)
23027 #if defined (OBJ_COFF) && defined (TE_PE)
23028 if (fixp->fx_r_type == BFD_RELOC_RVA)
23032 /* In case we have a call or a branch to a function in ARM ISA mode from
23033 a thumb function or vice-versa force the relocation. These relocations
23034 are cleared off for some cores that might have blx and simple transformations
23038 switch (fixp->fx_r_type)
23040 case BFD_RELOC_ARM_PCREL_JUMP:
23041 case BFD_RELOC_ARM_PCREL_CALL:
23042 case BFD_RELOC_THUMB_PCREL_BLX:
23043 if (THUMB_IS_FUNC (fixp->fx_addsy))
23047 case BFD_RELOC_ARM_PCREL_BLX:
23048 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23049 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23050 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23051 if (ARM_IS_FUNC (fixp->fx_addsy))
23060 /* Resolve these relocations even if the symbol is extern or weak.
23061 Technically this is probably wrong due to symbol preemption.
23062 In practice these relocations do not have enough range to be useful
23063 at dynamic link time, and some code (e.g. in the Linux kernel)
23064 expects these references to be resolved. */
23065 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23066 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23067 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23068 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23069 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23070 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23071 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23072 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23073 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23074 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23075 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23076 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23077 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23078 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23081 /* Always leave these relocations for the linker. */
23082 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23083 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23084 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23087 /* Always generate relocations against function symbols. */
23088 if (fixp->fx_r_type == BFD_RELOC_32
23090 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23093 return generic_force_reloc (fixp);
23096 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23097 /* Relocations against function names must be left unadjusted,
23098 so that the linker can use this information to generate interworking
23099 stubs. The MIPS version of this function
23100 also prevents relocations that are mips-16 specific, but I do not
23101 know why it does this.
23104 There is one other problem that ought to be addressed here, but
23105 which currently is not: Taking the address of a label (rather
23106 than a function) and then later jumping to that address. Such
23107 addresses also ought to have their bottom bit set (assuming that
23108 they reside in Thumb code), but at the moment they will not. */
23111 arm_fix_adjustable (fixS * fixP)
23113 if (fixP->fx_addsy == NULL)
23116 /* Preserve relocations against symbols with function type. */
23117 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23120 if (THUMB_IS_FUNC (fixP->fx_addsy)
23121 && fixP->fx_subsy == NULL)
23124 /* We need the symbol name for the VTABLE entries. */
23125 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23126 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23129 /* Don't allow symbols to be discarded on GOT related relocs. */
23130 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23131 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23132 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23133 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23134 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23135 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23136 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23137 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23138 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23139 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23140 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23141 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23142 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23143 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23146 /* Similarly for group relocations. */
23147 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23148 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23149 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23152 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23153 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23154 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23155 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23156 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23157 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23158 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23159 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23160 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23165 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23170 elf32_arm_target_format (void)
23173 return (target_big_endian
23174 ? "elf32-bigarm-symbian"
23175 : "elf32-littlearm-symbian");
23176 #elif defined (TE_VXWORKS)
23177 return (target_big_endian
23178 ? "elf32-bigarm-vxworks"
23179 : "elf32-littlearm-vxworks");
23180 #elif defined (TE_NACL)
23181 return (target_big_endian
23182 ? "elf32-bigarm-nacl"
23183 : "elf32-littlearm-nacl");
23185 if (target_big_endian)
23186 return "elf32-bigarm";
23188 return "elf32-littlearm";
23193 armelf_frob_symbol (symbolS * symp,
23196 elf_frob_symbol (symp, puntp);
23200 /* MD interface: Finalization. */
23205 literal_pool * pool;
23207 /* Ensure that all the IT blocks are properly closed. */
23208 check_it_blocks_finished ();
23210 for (pool = list_of_pools; pool; pool = pool->next)
23212 /* Put it at the end of the relevant section. */
23213 subseg_set (pool->section, pool->sub_section);
23215 arm_elf_change_section ();
23222 /* Remove any excess mapping symbols generated for alignment frags in
23223 SEC. We may have created a mapping symbol before a zero byte
23224 alignment; remove it if there's a mapping symbol after the
23227 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23228 void *dummy ATTRIBUTE_UNUSED)
23230 segment_info_type *seginfo = seg_info (sec);
23233 if (seginfo == NULL || seginfo->frchainP == NULL)
23236 for (fragp = seginfo->frchainP->frch_root;
23238 fragp = fragp->fr_next)
23240 symbolS *sym = fragp->tc_frag_data.last_map;
23241 fragS *next = fragp->fr_next;
23243 /* Variable-sized frags have been converted to fixed size by
23244 this point. But if this was variable-sized to start with,
23245 there will be a fixed-size frag after it. So don't handle
23247 if (sym == NULL || next == NULL)
23250 if (S_GET_VALUE (sym) < next->fr_address)
23251 /* Not at the end of this frag. */
23253 know (S_GET_VALUE (sym) == next->fr_address);
23257 if (next->tc_frag_data.first_map != NULL)
23259 /* Next frag starts with a mapping symbol. Discard this
23261 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23265 if (next->fr_next == NULL)
23267 /* This mapping symbol is at the end of the section. Discard
23269 know (next->fr_fix == 0 && next->fr_var == 0);
23270 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23274 /* As long as we have empty frags without any mapping symbols,
23276 /* If the next frag is non-empty and does not start with a
23277 mapping symbol, then this mapping symbol is required. */
23278 if (next->fr_address != next->fr_next->fr_address)
23281 next = next->fr_next;
23283 while (next != NULL);
23288 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23292 arm_adjust_symtab (void)
23297 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23299 if (ARM_IS_THUMB (sym))
23301 if (THUMB_IS_FUNC (sym))
23303 /* Mark the symbol as a Thumb function. */
23304 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23305 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23306 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23308 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23309 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23311 as_bad (_("%s: unexpected function type: %d"),
23312 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23314 else switch (S_GET_STORAGE_CLASS (sym))
23317 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23320 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23323 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23331 if (ARM_IS_INTERWORK (sym))
23332 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23339 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23341 if (ARM_IS_THUMB (sym))
23343 elf_symbol_type * elf_sym;
23345 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23346 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23348 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23349 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23351 /* If it's a .thumb_func, declare it as so,
23352 otherwise tag label as .code 16. */
23353 if (THUMB_IS_FUNC (sym))
23354 elf_sym->internal_elf_sym.st_target_internal
23355 = ST_BRANCH_TO_THUMB;
23356 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23357 elf_sym->internal_elf_sym.st_info =
23358 ELF_ST_INFO (bind, STT_ARM_16BIT);
23363 /* Remove any overlapping mapping symbols generated by alignment frags. */
23364 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23365 /* Now do generic ELF adjustments. */
23366 elf_adjust_symtab ();
23370 /* MD interface: Initialization. */
23373 set_constant_flonums (void)
23377 for (i = 0; i < NUM_FLOAT_VALS; i++)
23378 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23382 /* Auto-select Thumb mode if it's the only available instruction set for the
23383 given architecture. */
23386 autoselect_thumb_from_cpu_variant (void)
23388 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23389 opcode_select (16);
23398 if ( (arm_ops_hsh = hash_new ()) == NULL
23399 || (arm_cond_hsh = hash_new ()) == NULL
23400 || (arm_shift_hsh = hash_new ()) == NULL
23401 || (arm_psr_hsh = hash_new ()) == NULL
23402 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23403 || (arm_reg_hsh = hash_new ()) == NULL
23404 || (arm_reloc_hsh = hash_new ()) == NULL
23405 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23406 as_fatal (_("virtual memory exhausted"));
23408 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23409 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23410 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23411 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23412 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23413 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23414 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23415 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23416 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23417 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23418 (void *) (v7m_psrs + i));
23419 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23420 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23422 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23424 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23425 (void *) (barrier_opt_names + i));
23427 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23429 struct reloc_entry * entry = reloc_names + i;
23431 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23432 /* This makes encode_branch() use the EABI versions of this relocation. */
23433 entry->reloc = BFD_RELOC_UNUSED;
23435 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23439 set_constant_flonums ();
23441 /* Set the cpu variant based on the command-line options. We prefer
23442 -mcpu= over -march= if both are set (as for GCC); and we prefer
23443 -mfpu= over any other way of setting the floating point unit.
23444 Use of legacy options with new options are faulted. */
23447 if (mcpu_cpu_opt || march_cpu_opt)
23448 as_bad (_("use of old and new-style options to set CPU type"));
23450 mcpu_cpu_opt = legacy_cpu;
23452 else if (!mcpu_cpu_opt)
23453 mcpu_cpu_opt = march_cpu_opt;
23458 as_bad (_("use of old and new-style options to set FPU type"));
23460 mfpu_opt = legacy_fpu;
23462 else if (!mfpu_opt)
23464 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23465 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23466 /* Some environments specify a default FPU. If they don't, infer it
23467 from the processor. */
23469 mfpu_opt = mcpu_fpu_opt;
23471 mfpu_opt = march_fpu_opt;
23473 mfpu_opt = &fpu_default;
23479 if (mcpu_cpu_opt != NULL)
23480 mfpu_opt = &fpu_default;
23481 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23482 mfpu_opt = &fpu_arch_vfp_v2;
23484 mfpu_opt = &fpu_arch_fpa;
23490 mcpu_cpu_opt = &cpu_default;
23491 selected_cpu = cpu_default;
23495 selected_cpu = *mcpu_cpu_opt;
23497 mcpu_cpu_opt = &arm_arch_any;
23500 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23502 autoselect_thumb_from_cpu_variant ();
23504 arm_arch_used = thumb_arch_used = arm_arch_none;
23506 #if defined OBJ_COFF || defined OBJ_ELF
23508 unsigned int flags = 0;
23510 #if defined OBJ_ELF
23511 flags = meabi_flags;
23513 switch (meabi_flags)
23515 case EF_ARM_EABI_UNKNOWN:
23517 /* Set the flags in the private structure. */
23518 if (uses_apcs_26) flags |= F_APCS26;
23519 if (support_interwork) flags |= F_INTERWORK;
23520 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23521 if (pic_code) flags |= F_PIC;
23522 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23523 flags |= F_SOFT_FLOAT;
23525 switch (mfloat_abi_opt)
23527 case ARM_FLOAT_ABI_SOFT:
23528 case ARM_FLOAT_ABI_SOFTFP:
23529 flags |= F_SOFT_FLOAT;
23532 case ARM_FLOAT_ABI_HARD:
23533 if (flags & F_SOFT_FLOAT)
23534 as_bad (_("hard-float conflicts with specified fpu"));
23538 /* Using pure-endian doubles (even if soft-float). */
23539 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23540 flags |= F_VFP_FLOAT;
23542 #if defined OBJ_ELF
23543 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23544 flags |= EF_ARM_MAVERICK_FLOAT;
23547 case EF_ARM_EABI_VER4:
23548 case EF_ARM_EABI_VER5:
23549 /* No additional flags to set. */
23556 bfd_set_private_flags (stdoutput, flags);
23558 /* We have run out flags in the COFF header to encode the
23559 status of ATPCS support, so instead we create a dummy,
23560 empty, debug section called .arm.atpcs. */
23565 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23569 bfd_set_section_flags
23570 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23571 bfd_set_section_size (stdoutput, sec, 0);
23572 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23578 /* Record the CPU type as well. */
23579 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23580 mach = bfd_mach_arm_iWMMXt2;
23581 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23582 mach = bfd_mach_arm_iWMMXt;
23583 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23584 mach = bfd_mach_arm_XScale;
23585 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23586 mach = bfd_mach_arm_ep9312;
23587 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23588 mach = bfd_mach_arm_5TE;
23589 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23591 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23592 mach = bfd_mach_arm_5T;
23594 mach = bfd_mach_arm_5;
23596 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23598 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23599 mach = bfd_mach_arm_4T;
23601 mach = bfd_mach_arm_4;
23603 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23604 mach = bfd_mach_arm_3M;
23605 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23606 mach = bfd_mach_arm_3;
23607 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23608 mach = bfd_mach_arm_2a;
23609 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23610 mach = bfd_mach_arm_2;
23612 mach = bfd_mach_arm_unknown;
23614 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23617 /* Command line processing. */
23620 Invocation line includes a switch not recognized by the base assembler.
23621 See if it's a processor-specific option.
23623 This routine is somewhat complicated by the need for backwards
23624 compatibility (since older releases of gcc can't be changed).
23625 The new options try to make the interface as compatible as
23628 New options (supported) are:
23630 -mcpu=<cpu name> Assemble for selected processor
23631 -march=<architecture name> Assemble for selected architecture
23632 -mfpu=<fpu architecture> Assemble for selected FPU.
23633 -EB/-mbig-endian Big-endian
23634 -EL/-mlittle-endian Little-endian
23635 -k Generate PIC code
23636 -mthumb Start in Thumb mode
23637 -mthumb-interwork Code supports ARM/Thumb interworking
23639 -m[no-]warn-deprecated Warn about deprecated features
23641 For now we will also provide support for:
23643 -mapcs-32 32-bit Program counter
23644 -mapcs-26 26-bit Program counter
23645 -macps-float Floats passed in FP registers
23646 -mapcs-reentrant Reentrant code
23648 (sometime these will probably be replaced with -mapcs=<list of options>
23649 and -matpcs=<list of options>)
23651 The remaining options are only supported for back-wards compatibility.
23652 Cpu variants, the arm part is optional:
23653 -m[arm]1 Currently not supported.
23654 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23655 -m[arm]3 Arm 3 processor
23656 -m[arm]6[xx], Arm 6 processors
23657 -m[arm]7[xx][t][[d]m] Arm 7 processors
23658 -m[arm]8[10] Arm 8 processors
23659 -m[arm]9[20][tdmi] Arm 9 processors
23660 -mstrongarm[110[0]] StrongARM processors
23661 -mxscale XScale processors
23662 -m[arm]v[2345[t[e]]] Arm architectures
23663 -mall All (except the ARM1)
23665 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23666 -mfpe-old (No float load/store multiples)
23667 -mvfpxd VFP Single precision
23669 -mno-fpu Disable all floating point instructions
23671 The following CPU names are recognized:
23672 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23673 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23674 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23675 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23676 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23677 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23678 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23682 const char * md_shortopts = "m:k";
23684 #ifdef ARM_BI_ENDIAN
23685 #define OPTION_EB (OPTION_MD_BASE + 0)
23686 #define OPTION_EL (OPTION_MD_BASE + 1)
23688 #if TARGET_BYTES_BIG_ENDIAN
23689 #define OPTION_EB (OPTION_MD_BASE + 0)
23691 #define OPTION_EL (OPTION_MD_BASE + 1)
23694 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23696 struct option md_longopts[] =
23699 {"EB", no_argument, NULL, OPTION_EB},
23702 {"EL", no_argument, NULL, OPTION_EL},
23704 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23705 {NULL, no_argument, NULL, 0}
23708 size_t md_longopts_size = sizeof (md_longopts);
23710 struct arm_option_table
23712 char *option; /* Option name to match. */
23713 char *help; /* Help information. */
23714 int *var; /* Variable to change. */
23715 int value; /* What to change it to. */
23716 char *deprecated; /* If non-null, print this message. */
23719 struct arm_option_table arm_opts[] =
23721 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23722 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23723 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23724 &support_interwork, 1, NULL},
23725 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23726 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23727 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23729 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23730 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23731 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23732 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23735 /* These are recognized by the assembler, but have no affect on code. */
23736 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23737 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23739 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23740 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23741 &warn_on_deprecated, 0, NULL},
23742 {NULL, NULL, NULL, 0, NULL}
23745 struct arm_legacy_option_table
23747 char *option; /* Option name to match. */
23748 const arm_feature_set **var; /* Variable to change. */
23749 const arm_feature_set value; /* What to change it to. */
23750 char *deprecated; /* If non-null, print this message. */
23753 const struct arm_legacy_option_table arm_legacy_opts[] =
23755 /* DON'T add any new processors to this list -- we want the whole list
23756 to go away... Add them to the processors table instead. */
23757 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23758 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23759 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23760 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23761 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23762 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23763 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23764 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23765 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23766 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23767 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23768 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23769 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23770 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23771 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23772 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23773 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23774 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23775 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23776 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23777 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23778 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23779 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23780 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23781 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23782 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23783 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23784 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23785 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23786 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23787 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23788 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23789 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23790 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23791 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23792 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23793 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23794 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23795 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23796 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23797 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23798 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23799 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23800 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23801 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23802 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23803 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23804 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23805 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23806 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23807 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23808 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23809 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23810 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23811 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23812 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23813 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23814 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23815 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23816 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23817 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23818 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23819 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23820 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23821 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23822 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23823 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23824 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23825 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23826 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23827 N_("use -mcpu=strongarm110")},
23828 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23829 N_("use -mcpu=strongarm1100")},
23830 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23831 N_("use -mcpu=strongarm1110")},
23832 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23833 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23834 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23836 /* Architecture variants -- don't add any more to this list either. */
23837 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23838 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23839 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23840 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23841 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23842 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23843 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23844 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23845 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23846 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23847 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23848 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23849 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23850 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23851 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23852 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23853 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23854 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23856 /* Floating point variants -- don't add any more to this list either. */
23857 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23858 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23859 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23860 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23861 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23863 {NULL, NULL, ARM_ARCH_NONE, NULL}
23866 struct arm_cpu_option_table
23870 const arm_feature_set value;
23871 /* For some CPUs we assume an FPU unless the user explicitly sets
23873 const arm_feature_set default_fpu;
23874 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23876 const char *canonical_name;
23879 /* This list should, at a minimum, contain all the cpu names
23880 recognized by GCC. */
23881 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23882 static const struct arm_cpu_option_table arm_cpus[] =
23884 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23885 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23886 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23887 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23888 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23889 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23890 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23891 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23892 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23893 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23894 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23895 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23896 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23897 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23898 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23899 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23900 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23901 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23902 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23903 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23904 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23905 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23906 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23907 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23908 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23909 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23910 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23911 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23912 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23913 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23914 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23915 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23916 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23917 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23918 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23919 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23920 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23921 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23922 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23923 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23924 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23925 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23926 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23927 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23928 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23929 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23930 /* For V5 or later processors we default to using VFP; but the user
23931 should really set the FPU type explicitly. */
23932 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23933 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23934 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23935 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23936 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23937 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23938 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23939 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23940 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23941 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23942 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23943 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23944 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23945 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23946 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23947 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23948 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23949 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23950 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23951 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23953 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23954 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23955 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23956 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23957 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23958 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23959 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23960 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23961 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23963 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23964 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23965 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23966 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23967 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23968 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23969 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23970 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23971 FPU_NONE, "Cortex-A5"),
23972 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23973 FPU_ARCH_NEON_VFP_V4,
23975 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23976 ARM_FEATURE (0, FPU_VFP_V3
23977 | FPU_NEON_EXT_V1),
23979 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23980 ARM_FEATURE (0, FPU_VFP_V3
23981 | FPU_NEON_EXT_V1),
23983 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23984 FPU_ARCH_NEON_VFP_V4,
23986 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23987 FPU_ARCH_NEON_VFP_V4,
23989 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23991 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23993 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23994 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23996 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23997 FPU_NONE, "Cortex-R5"),
23998 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
23999 FPU_ARCH_VFP_V3D16,
24001 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24002 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24003 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24004 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
24005 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
24006 /* ??? XSCALE is really an architecture. */
24007 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24008 /* ??? iwmmxt is not a processor. */
24009 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24010 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24011 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24013 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24014 FPU_ARCH_MAVERICK, "ARM920T"),
24015 /* Marvell processors. */
24016 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
24017 FPU_ARCH_VFP_V3D16, NULL),
24019 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24023 struct arm_arch_option_table
24027 const arm_feature_set value;
24028 const arm_feature_set default_fpu;
24031 /* This list should, at a minimum, contain all the architecture names
24032 recognized by GCC. */
24033 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24034 static const struct arm_arch_option_table arm_archs[] =
24036 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24037 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24038 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24039 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24040 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24041 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24042 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24043 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24044 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24045 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24046 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24047 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24048 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24049 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24050 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24051 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24052 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24053 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24054 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24055 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24056 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24057 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24058 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24059 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24060 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24061 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24062 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24063 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24064 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24065 /* The official spelling of the ARMv7 profile variants is the dashed form.
24066 Accept the non-dashed form for compatibility with old toolchains. */
24067 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24068 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24069 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24070 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24071 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24072 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24073 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24074 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24075 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24076 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24077 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24078 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24080 #undef ARM_ARCH_OPT
24082 /* ISA extensions in the co-processor and main instruction set space. */
24083 struct arm_option_extension_value_table
24087 const arm_feature_set value;
24088 const arm_feature_set allowed_archs;
24091 /* The following table must be in alphabetical order with a NULL last entry.
24093 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24094 static const struct arm_option_extension_value_table arm_extensions[] =
24096 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24097 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24098 ARM_FEATURE (ARM_EXT_V8, 0)),
24099 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24100 ARM_FEATURE (ARM_EXT_V8, 0)),
24101 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24102 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24103 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24104 ARM_EXT_OPT ("iwmmxt2",
24105 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24106 ARM_EXT_OPT ("maverick",
24107 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24108 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24109 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24110 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24111 ARM_FEATURE (ARM_EXT_V8, 0)),
24112 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24113 ARM_FEATURE (ARM_EXT_V6M, 0)),
24114 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24115 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24116 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24118 ARM_FEATURE (ARM_EXT_V7A, 0)),
24119 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24120 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24124 /* ISA floating-point and Advanced SIMD extensions. */
24125 struct arm_option_fpu_value_table
24128 const arm_feature_set value;
24131 /* This list should, at a minimum, contain all the fpu names
24132 recognized by GCC. */
24133 static const struct arm_option_fpu_value_table arm_fpus[] =
24135 {"softfpa", FPU_NONE},
24136 {"fpe", FPU_ARCH_FPE},
24137 {"fpe2", FPU_ARCH_FPE},
24138 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24139 {"fpa", FPU_ARCH_FPA},
24140 {"fpa10", FPU_ARCH_FPA},
24141 {"fpa11", FPU_ARCH_FPA},
24142 {"arm7500fe", FPU_ARCH_FPA},
24143 {"softvfp", FPU_ARCH_VFP},
24144 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24145 {"vfp", FPU_ARCH_VFP_V2},
24146 {"vfp9", FPU_ARCH_VFP_V2},
24147 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24148 {"vfp10", FPU_ARCH_VFP_V2},
24149 {"vfp10-r0", FPU_ARCH_VFP_V1},
24150 {"vfpxd", FPU_ARCH_VFP_V1xD},
24151 {"vfpv2", FPU_ARCH_VFP_V2},
24152 {"vfpv3", FPU_ARCH_VFP_V3},
24153 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24154 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24155 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24156 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24157 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24158 {"arm1020t", FPU_ARCH_VFP_V1},
24159 {"arm1020e", FPU_ARCH_VFP_V2},
24160 {"arm1136jfs", FPU_ARCH_VFP_V2},
24161 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24162 {"maverick", FPU_ARCH_MAVERICK},
24163 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24164 {"neon-fp16", FPU_ARCH_NEON_FP16},
24165 {"vfpv4", FPU_ARCH_VFP_V4},
24166 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24167 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24168 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24169 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24170 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24171 {"crypto-neon-fp-armv8",
24172 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24173 {NULL, ARM_ARCH_NONE}
24176 struct arm_option_value_table
24182 static const struct arm_option_value_table arm_float_abis[] =
24184 {"hard", ARM_FLOAT_ABI_HARD},
24185 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24186 {"soft", ARM_FLOAT_ABI_SOFT},
24191 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24192 static const struct arm_option_value_table arm_eabis[] =
24194 {"gnu", EF_ARM_EABI_UNKNOWN},
24195 {"4", EF_ARM_EABI_VER4},
24196 {"5", EF_ARM_EABI_VER5},
24201 struct arm_long_option_table
24203 char * option; /* Substring to match. */
24204 char * help; /* Help information. */
24205 int (* func) (char * subopt); /* Function to decode sub-option. */
24206 char * deprecated; /* If non-null, print this message. */
24210 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24212 arm_feature_set *ext_set = (arm_feature_set *)
24213 xmalloc (sizeof (arm_feature_set));
24215 /* We insist on extensions being specified in alphabetical order, and with
24216 extensions being added before being removed. We achieve this by having
24217 the global ARM_EXTENSIONS table in alphabetical order, and using the
24218 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24219 or removing it (0) and only allowing it to change in the order
24221 const struct arm_option_extension_value_table * opt = NULL;
24222 int adding_value = -1;
24224 /* Copy the feature set, so that we can modify it. */
24225 *ext_set = **opt_p;
24228 while (str != NULL && *str != 0)
24235 as_bad (_("invalid architectural extension"));
24240 ext = strchr (str, '+');
24245 len = strlen (str);
24247 if (len >= 2 && strncmp (str, "no", 2) == 0)
24249 if (adding_value != 0)
24252 opt = arm_extensions;
24260 if (adding_value == -1)
24263 opt = arm_extensions;
24265 else if (adding_value != 1)
24267 as_bad (_("must specify extensions to add before specifying "
24268 "those to remove"));
24275 as_bad (_("missing architectural extension"));
24279 gas_assert (adding_value != -1);
24280 gas_assert (opt != NULL);
24282 /* Scan over the options table trying to find an exact match. */
24283 for (; opt->name != NULL; opt++)
24284 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24286 /* Check we can apply the extension to this architecture. */
24287 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24289 as_bad (_("extension does not apply to the base architecture"));
24293 /* Add or remove the extension. */
24295 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24297 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24302 if (opt->name == NULL)
24304 /* Did we fail to find an extension because it wasn't specified in
24305 alphabetical order, or because it does not exist? */
24307 for (opt = arm_extensions; opt->name != NULL; opt++)
24308 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24311 if (opt->name == NULL)
24312 as_bad (_("unknown architectural extension `%s'"), str);
24314 as_bad (_("architectural extensions must be specified in "
24315 "alphabetical order"));
24321 /* We should skip the extension we've just matched the next time
24333 arm_parse_cpu (char *str)
24335 const struct arm_cpu_option_table *opt;
24336 char *ext = strchr (str, '+');
24342 len = strlen (str);
24346 as_bad (_("missing cpu name `%s'"), str);
24350 for (opt = arm_cpus; opt->name != NULL; opt++)
24351 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24353 mcpu_cpu_opt = &opt->value;
24354 mcpu_fpu_opt = &opt->default_fpu;
24355 if (opt->canonical_name)
24356 strcpy (selected_cpu_name, opt->canonical_name);
24361 for (i = 0; i < len; i++)
24362 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24363 selected_cpu_name[i] = 0;
24367 return arm_parse_extension (ext, &mcpu_cpu_opt);
24372 as_bad (_("unknown cpu `%s'"), str);
24377 arm_parse_arch (char *str)
24379 const struct arm_arch_option_table *opt;
24380 char *ext = strchr (str, '+');
24386 len = strlen (str);
24390 as_bad (_("missing architecture name `%s'"), str);
24394 for (opt = arm_archs; opt->name != NULL; opt++)
24395 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24397 march_cpu_opt = &opt->value;
24398 march_fpu_opt = &opt->default_fpu;
24399 strcpy (selected_cpu_name, opt->name);
24402 return arm_parse_extension (ext, &march_cpu_opt);
24407 as_bad (_("unknown architecture `%s'\n"), str);
24412 arm_parse_fpu (char * str)
24414 const struct arm_option_fpu_value_table * opt;
24416 for (opt = arm_fpus; opt->name != NULL; opt++)
24417 if (streq (opt->name, str))
24419 mfpu_opt = &opt->value;
24423 as_bad (_("unknown floating point format `%s'\n"), str);
24428 arm_parse_float_abi (char * str)
24430 const struct arm_option_value_table * opt;
24432 for (opt = arm_float_abis; opt->name != NULL; opt++)
24433 if (streq (opt->name, str))
24435 mfloat_abi_opt = opt->value;
24439 as_bad (_("unknown floating point abi `%s'\n"), str);
24445 arm_parse_eabi (char * str)
24447 const struct arm_option_value_table *opt;
24449 for (opt = arm_eabis; opt->name != NULL; opt++)
24450 if (streq (opt->name, str))
24452 meabi_flags = opt->value;
24455 as_bad (_("unknown EABI `%s'\n"), str);
24461 arm_parse_it_mode (char * str)
24463 bfd_boolean ret = TRUE;
24465 if (streq ("arm", str))
24466 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24467 else if (streq ("thumb", str))
24468 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24469 else if (streq ("always", str))
24470 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24471 else if (streq ("never", str))
24472 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24475 as_bad (_("unknown implicit IT mode `%s', should be "\
24476 "arm, thumb, always, or never."), str);
24483 struct arm_long_option_table arm_long_opts[] =
24485 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24486 arm_parse_cpu, NULL},
24487 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24488 arm_parse_arch, NULL},
24489 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24490 arm_parse_fpu, NULL},
24491 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24492 arm_parse_float_abi, NULL},
24494 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24495 arm_parse_eabi, NULL},
24497 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24498 arm_parse_it_mode, NULL},
24499 {NULL, NULL, 0, NULL}
24503 md_parse_option (int c, char * arg)
24505 struct arm_option_table *opt;
24506 const struct arm_legacy_option_table *fopt;
24507 struct arm_long_option_table *lopt;
24513 target_big_endian = 1;
24519 target_big_endian = 0;
24523 case OPTION_FIX_V4BX:
24528 /* Listing option. Just ignore these, we don't support additional
24533 for (opt = arm_opts; opt->option != NULL; opt++)
24535 if (c == opt->option[0]
24536 && ((arg == NULL && opt->option[1] == 0)
24537 || streq (arg, opt->option + 1)))
24539 /* If the option is deprecated, tell the user. */
24540 if (warn_on_deprecated && opt->deprecated != NULL)
24541 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24542 arg ? arg : "", _(opt->deprecated));
24544 if (opt->var != NULL)
24545 *opt->var = opt->value;
24551 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24553 if (c == fopt->option[0]
24554 && ((arg == NULL && fopt->option[1] == 0)
24555 || streq (arg, fopt->option + 1)))
24557 /* If the option is deprecated, tell the user. */
24558 if (warn_on_deprecated && fopt->deprecated != NULL)
24559 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24560 arg ? arg : "", _(fopt->deprecated));
24562 if (fopt->var != NULL)
24563 *fopt->var = &fopt->value;
24569 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24571 /* These options are expected to have an argument. */
24572 if (c == lopt->option[0]
24574 && strncmp (arg, lopt->option + 1,
24575 strlen (lopt->option + 1)) == 0)
24577 /* If the option is deprecated, tell the user. */
24578 if (warn_on_deprecated && lopt->deprecated != NULL)
24579 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24580 _(lopt->deprecated));
24582 /* Call the sup-option parser. */
24583 return lopt->func (arg + strlen (lopt->option) - 1);
24594 md_show_usage (FILE * fp)
24596 struct arm_option_table *opt;
24597 struct arm_long_option_table *lopt;
24599 fprintf (fp, _(" ARM-specific assembler options:\n"));
24601 for (opt = arm_opts; opt->option != NULL; opt++)
24602 if (opt->help != NULL)
24603 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24605 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24606 if (lopt->help != NULL)
24607 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24611 -EB assemble code for a big-endian cpu\n"));
24616 -EL assemble code for a little-endian cpu\n"));
24620 --fix-v4bx Allow BX in ARMv4 code\n"));
24628 arm_feature_set flags;
24629 } cpu_arch_ver_table;
24631 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24632 least features first. */
24633 static const cpu_arch_ver_table cpu_arch_ver[] =
24639 {4, ARM_ARCH_V5TE},
24640 {5, ARM_ARCH_V5TEJ},
24644 {11, ARM_ARCH_V6M},
24645 {12, ARM_ARCH_V6SM},
24646 {8, ARM_ARCH_V6T2},
24647 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24648 {10, ARM_ARCH_V7R},
24649 {10, ARM_ARCH_V7M},
24650 {14, ARM_ARCH_V8A},
24654 /* Set an attribute if it has not already been set by the user. */
24656 aeabi_set_attribute_int (int tag, int value)
24659 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24660 || !attributes_set_explicitly[tag])
24661 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24665 aeabi_set_attribute_string (int tag, const char *value)
24668 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24669 || !attributes_set_explicitly[tag])
24670 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24673 /* Set the public EABI object attributes. */
24675 aeabi_set_public_attributes (void)
24680 int fp16_optional = 0;
24681 arm_feature_set flags;
24682 arm_feature_set tmp;
24683 const cpu_arch_ver_table *p;
24685 /* Choose the architecture based on the capabilities of the requested cpu
24686 (if any) and/or the instructions actually used. */
24687 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24688 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24689 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24691 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24692 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24694 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24695 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24697 /* Allow the user to override the reported architecture. */
24700 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24701 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24704 /* We need to make sure that the attributes do not identify us as v6S-M
24705 when the only v6S-M feature in use is the Operating System Extensions. */
24706 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24707 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24708 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24712 for (p = cpu_arch_ver; p->val; p++)
24714 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24717 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24721 /* The table lookup above finds the last architecture to contribute
24722 a new feature. Unfortunately, Tag13 is a subset of the union of
24723 v6T2 and v7-M, so it is never seen as contributing a new feature.
24724 We can not search for the last entry which is entirely used,
24725 because if no CPU is specified we build up only those flags
24726 actually used. Perhaps we should separate out the specified
24727 and implicit cases. Avoid taking this path for -march=all by
24728 checking for contradictory v7-A / v7-M features. */
24730 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24731 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24732 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24735 /* Tag_CPU_name. */
24736 if (selected_cpu_name[0])
24740 q = selected_cpu_name;
24741 if (strncmp (q, "armv", 4) == 0)
24746 for (i = 0; q[i]; i++)
24747 q[i] = TOUPPER (q[i]);
24749 aeabi_set_attribute_string (Tag_CPU_name, q);
24752 /* Tag_CPU_arch. */
24753 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24755 /* Tag_CPU_arch_profile. */
24756 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24758 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24760 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24765 if (profile != '\0')
24766 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24768 /* Tag_ARM_ISA_use. */
24769 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24771 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24773 /* Tag_THUMB_ISA_use. */
24774 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24776 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24777 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24779 /* Tag_VFP_arch. */
24780 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24781 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24782 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24783 aeabi_set_attribute_int (Tag_VFP_arch,
24784 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24786 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24789 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24791 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24793 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24796 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24797 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24798 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24799 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24800 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24802 /* Tag_ABI_HardFP_use. */
24803 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24804 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24805 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24807 /* Tag_WMMX_arch. */
24808 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24809 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24810 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24811 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24813 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24814 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24815 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24816 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24818 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24820 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24824 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24829 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24830 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24831 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24835 We set Tag_DIV_use to two when integer divide instructions have been used
24836 in ARM state, or when Thumb integer divide instructions have been used,
24837 but we have no architecture profile set, nor have we any ARM instructions.
24839 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24842 For new architectures we will have to check these tests. */
24843 gas_assert (arch <= TAG_CPU_ARCH_V8);
24844 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24845 aeabi_set_attribute_int (Tag_DIV_use, 0);
24846 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24847 || (profile == '\0'
24848 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24849 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24850 aeabi_set_attribute_int (Tag_DIV_use, 2);
24852 /* Tag_MP_extension_use. */
24853 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24854 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24856 /* Tag Virtualization_use. */
24857 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24859 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24862 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24865 /* Add the default contents for the .ARM.attributes section. */
24869 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24872 aeabi_set_public_attributes ();
24874 #endif /* OBJ_ELF */
24877 /* Parse a .cpu directive. */
24880 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24882 const struct arm_cpu_option_table *opt;
24886 name = input_line_pointer;
24887 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24888 input_line_pointer++;
24889 saved_char = *input_line_pointer;
24890 *input_line_pointer = 0;
24892 /* Skip the first "all" entry. */
24893 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24894 if (streq (opt->name, name))
24896 mcpu_cpu_opt = &opt->value;
24897 selected_cpu = opt->value;
24898 if (opt->canonical_name)
24899 strcpy (selected_cpu_name, opt->canonical_name);
24903 for (i = 0; opt->name[i]; i++)
24904 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24906 selected_cpu_name[i] = 0;
24908 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24909 *input_line_pointer = saved_char;
24910 demand_empty_rest_of_line ();
24913 as_bad (_("unknown cpu `%s'"), name);
24914 *input_line_pointer = saved_char;
24915 ignore_rest_of_line ();
24919 /* Parse a .arch directive. */
24922 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24924 const struct arm_arch_option_table *opt;
24928 name = input_line_pointer;
24929 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24930 input_line_pointer++;
24931 saved_char = *input_line_pointer;
24932 *input_line_pointer = 0;
24934 /* Skip the first "all" entry. */
24935 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24936 if (streq (opt->name, name))
24938 mcpu_cpu_opt = &opt->value;
24939 selected_cpu = opt->value;
24940 strcpy (selected_cpu_name, opt->name);
24941 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24942 *input_line_pointer = saved_char;
24943 demand_empty_rest_of_line ();
24947 as_bad (_("unknown architecture `%s'\n"), name);
24948 *input_line_pointer = saved_char;
24949 ignore_rest_of_line ();
24953 /* Parse a .object_arch directive. */
24956 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24958 const struct arm_arch_option_table *opt;
24962 name = input_line_pointer;
24963 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24964 input_line_pointer++;
24965 saved_char = *input_line_pointer;
24966 *input_line_pointer = 0;
24968 /* Skip the first "all" entry. */
24969 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24970 if (streq (opt->name, name))
24972 object_arch = &opt->value;
24973 *input_line_pointer = saved_char;
24974 demand_empty_rest_of_line ();
24978 as_bad (_("unknown architecture `%s'\n"), name);
24979 *input_line_pointer = saved_char;
24980 ignore_rest_of_line ();
24983 /* Parse a .arch_extension directive. */
24986 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24988 const struct arm_option_extension_value_table *opt;
24991 int adding_value = 1;
24993 name = input_line_pointer;
24994 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24995 input_line_pointer++;
24996 saved_char = *input_line_pointer;
24997 *input_line_pointer = 0;
24999 if (strlen (name) >= 2
25000 && strncmp (name, "no", 2) == 0)
25006 for (opt = arm_extensions; opt->name != NULL; opt++)
25007 if (streq (opt->name, name))
25009 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25011 as_bad (_("architectural extension `%s' is not allowed for the "
25012 "current base architecture"), name);
25017 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25019 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25021 mcpu_cpu_opt = &selected_cpu;
25022 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25023 *input_line_pointer = saved_char;
25024 demand_empty_rest_of_line ();
25028 if (opt->name == NULL)
25029 as_bad (_("unknown architecture extension `%s'\n"), name);
25031 *input_line_pointer = saved_char;
25032 ignore_rest_of_line ();
25035 /* Parse a .fpu directive. */
25038 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25040 const struct arm_option_fpu_value_table *opt;
25044 name = input_line_pointer;
25045 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25046 input_line_pointer++;
25047 saved_char = *input_line_pointer;
25048 *input_line_pointer = 0;
25050 for (opt = arm_fpus; opt->name != NULL; opt++)
25051 if (streq (opt->name, name))
25053 mfpu_opt = &opt->value;
25054 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25055 *input_line_pointer = saved_char;
25056 demand_empty_rest_of_line ();
25060 as_bad (_("unknown floating point format `%s'\n"), name);
25061 *input_line_pointer = saved_char;
25062 ignore_rest_of_line ();
25065 /* Copy symbol information. */
25068 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25070 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25074 /* Given a symbolic attribute NAME, return the proper integer value.
25075 Returns -1 if the attribute is not known. */
25078 arm_convert_symbolic_attribute (const char *name)
25080 static const struct
25085 attribute_table[] =
25087 /* When you modify this table you should
25088 also modify the list in doc/c-arm.texi. */
25089 #define T(tag) {#tag, tag}
25090 T (Tag_CPU_raw_name),
25093 T (Tag_CPU_arch_profile),
25094 T (Tag_ARM_ISA_use),
25095 T (Tag_THUMB_ISA_use),
25099 T (Tag_Advanced_SIMD_arch),
25100 T (Tag_PCS_config),
25101 T (Tag_ABI_PCS_R9_use),
25102 T (Tag_ABI_PCS_RW_data),
25103 T (Tag_ABI_PCS_RO_data),
25104 T (Tag_ABI_PCS_GOT_use),
25105 T (Tag_ABI_PCS_wchar_t),
25106 T (Tag_ABI_FP_rounding),
25107 T (Tag_ABI_FP_denormal),
25108 T (Tag_ABI_FP_exceptions),
25109 T (Tag_ABI_FP_user_exceptions),
25110 T (Tag_ABI_FP_number_model),
25111 T (Tag_ABI_align_needed),
25112 T (Tag_ABI_align8_needed),
25113 T (Tag_ABI_align_preserved),
25114 T (Tag_ABI_align8_preserved),
25115 T (Tag_ABI_enum_size),
25116 T (Tag_ABI_HardFP_use),
25117 T (Tag_ABI_VFP_args),
25118 T (Tag_ABI_WMMX_args),
25119 T (Tag_ABI_optimization_goals),
25120 T (Tag_ABI_FP_optimization_goals),
25121 T (Tag_compatibility),
25122 T (Tag_CPU_unaligned_access),
25123 T (Tag_FP_HP_extension),
25124 T (Tag_VFP_HP_extension),
25125 T (Tag_ABI_FP_16bit_format),
25126 T (Tag_MPextension_use),
25128 T (Tag_nodefaults),
25129 T (Tag_also_compatible_with),
25130 T (Tag_conformance),
25132 T (Tag_Virtualization_use),
25133 /* We deliberately do not include Tag_MPextension_use_legacy. */
25141 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25142 if (streq (name, attribute_table[i].name))
25143 return attribute_table[i].tag;
25149 /* Apply sym value for relocations only in the case that
25150 they are for local symbols and you have the respective
25151 architectural feature for blx and simple switches. */
25153 arm_apply_sym_value (struct fix * fixP)
25156 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25157 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25159 switch (fixP->fx_r_type)
25161 case BFD_RELOC_ARM_PCREL_BLX:
25162 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25163 if (ARM_IS_FUNC (fixP->fx_addsy))
25167 case BFD_RELOC_ARM_PCREL_CALL:
25168 case BFD_RELOC_THUMB_PCREL_BLX:
25169 if (THUMB_IS_FUNC (fixP->fx_addsy))
25180 #endif /* OBJ_ELF */