1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
56 /* Architectures are the sum of the base and extensions */
57 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
58 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
59 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
60 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62 /* Some useful combinations: */
63 #define ARM_ANY 0x00ffffff
64 #define ARM_2UP (ARM_ANY - ARM_1)
65 #define ARM_ALL ARM_2UP /* Not arm1 only */
66 #define ARM_3UP 0x00fffffc
67 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
69 #define FPU_CORE 0x80000000
70 #define FPU_FPA10 0x40000000
71 #define FPU_FPA11 0x40000000
74 /* Some useful combinations */
75 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
76 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
83 #define CPU_DEFAULT ARM_ALL
88 #define FPU_DEFAULT FPU_ALL
91 #define streq(a,b) (strcmp (a, b) == 0)
93 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
94 static int target_oabi = 0;
96 #if defined OBJ_COFF || defined OBJ_ELF
97 /* Flags stored in private area of BFD structure */
98 static boolean uses_apcs_26 = false;
99 static boolean support_interwork = false;
100 static boolean uses_apcs_float = false;
101 static boolean pic_code = false;
104 /* This array holds the chars that always start a comment. If the
105 pre-processor is disabled, these aren't very useful */
106 CONST char comment_chars[] = "@";
108 /* This array holds the chars that only start a comment at the beginning of
109 a line. If the line seems to have the form '# 123 filename'
110 .line and .file directives will appear in the pre-processed output */
111 /* Note that input_file.c hand checks for '#' at the beginning of the
112 first line of the input file. This is because the compiler outputs
113 #NO_APP at the beginning of its output. */
114 /* Also note that comments like this one will always work. */
115 CONST char line_comment_chars[] = "#";
118 CONST char line_separator_chars[] = ";";
120 CONST char line_separator_chars[] = "";
123 /* Chars that can be used to separate mant from exp in floating point nums */
124 CONST char EXP_CHARS[] = "eE";
126 /* Chars that mean this number is a floating point constant */
130 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
132 /* Prefix characters that indicate the start of an immediate
134 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
137 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
140 CONST int md_reloc_size = 8; /* Size of relocation record */
142 static int thumb_mode = 0; /* non-zero if assembling thumb instructions */
144 typedef struct arm_fix
152 unsigned long instruction;
157 bfd_reloc_code_real_type type;
167 CONST char * template;
171 static CONST struct asm_shift shift[] =
187 #define NO_SHIFT_RESTRICT 1
188 #define SHIFT_RESTRICT 0
190 #define NUM_FLOAT_VALS 8
192 CONST char * fp_const[] =
194 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
197 /* Number of littlenums required to hold an extended precision number */
198 #define MAX_LITTLENUMS 6
200 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
210 #define CP_T_X 0x00008000
211 #define CP_T_Y 0x00400000
212 #define CP_T_Pre 0x01000000
213 #define CP_T_UD 0x00800000
214 #define CP_T_WB 0x00200000
216 #define CONDS_BIT (0x00100000)
217 #define LOAD_BIT (0x00100000)
218 #define TRANS_BIT (0x00200000)
222 CONST char * template;
226 /* This is to save a hash look-up in the common case */
227 #define COND_ALWAYS 0xe0000000
229 static CONST struct asm_cond conds[] =
233 {"cs", 0x20000000}, {"hs", 0x20000000},
234 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
249 /* Warning: If the top bit of the set_bits is set, then the standard
250 instruction bitmask is ignored, and the new bitmask is taken from
254 CONST char * template; /* Basic flag string */
255 unsigned long set_bits; /* Bits to set */
258 static CONST struct asm_flg s_flag[] =
264 static CONST struct asm_flg ldr_flags[] =
268 {"bt", 0x00400000 | TRANS_BIT},
275 static CONST struct asm_flg str_flags[] =
279 {"bt", 0x00400000 | TRANS_BIT},
284 static CONST struct asm_flg byte_flag[] =
290 static CONST struct asm_flg cmp_flags[] =
297 static CONST struct asm_flg ldm_flags[] =
310 static CONST struct asm_flg stm_flags[] =
323 static CONST struct asm_flg lfm_flags[] =
330 static CONST struct asm_flg sfm_flags[] =
337 static CONST struct asm_flg round_flags[] =
345 /* The implementation of the FIX instruction is broken on some assemblers,
346 in that it accepts a precision specifier as well as a rounding specifier,
347 despite the fact that this is meaningless. To be more compatible, we
348 accept it as well, though of course it does not set any bits. */
349 static CONST struct asm_flg fix_flags[] =
366 static CONST struct asm_flg except_flag[] =
372 static CONST struct asm_flg cplong_flag[] =
380 CONST char * template;
381 unsigned long number;
384 #define PSR_FIELD_MASK 0x000f0000
386 #define PSR_FLAGS 0x00080000
387 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
388 #define PSR_ALL 0x00090000
397 static CONST struct asm_psr psrs[] =
401 {"cpsr_all", CPSR_ALL},
403 {"spsr_all", SPSR_ALL},
406 {"cpsr_flg", CPSR_FLG},
407 {"spsr_flg", SPSR_FLG},
410 {"cpsr_c", CPSR_CTL},
411 {"cpsr_ctl", CPSR_CTL},
412 {"spsr_c", SPSR_CTL},
413 {"spsr_ctl", SPSR_CTL}
416 /* Functions called by parser */
417 /* ARM instructions */
418 static void do_arit PARAMS ((char *operands, unsigned long flags));
419 static void do_cmp PARAMS ((char *operands, unsigned long flags));
420 static void do_mov PARAMS ((char *operands, unsigned long flags));
421 static void do_ldst PARAMS ((char *operands, unsigned long flags));
422 static void do_ldmstm PARAMS ((char *operands, unsigned long flags));
423 static void do_branch PARAMS ((char *operands, unsigned long flags));
424 static void do_swi PARAMS ((char *operands, unsigned long flags));
425 /* Pseudo Op codes */
426 static void do_adr PARAMS ((char *operands, unsigned long flags));
427 static void do_adrl PARAMS ((char * operands, unsigned long flags));
428 static void do_nop PARAMS ((char *operands, unsigned long flags));
430 static void do_mul PARAMS ((char *operands, unsigned long flags));
431 static void do_mla PARAMS ((char *operands, unsigned long flags));
433 static void do_swap PARAMS ((char *operands, unsigned long flags));
435 static void do_msr PARAMS ((char *operands, unsigned long flags));
436 static void do_mrs PARAMS ((char *operands, unsigned long flags));
438 static void do_mull PARAMS ((char *operands, unsigned long flags));
440 static void do_bx PARAMS ((char *operands, unsigned long flags));
442 /* Coprocessor Instructions */
443 static void do_cdp PARAMS ((char *operands, unsigned long flags));
444 static void do_lstc PARAMS ((char *operands, unsigned long flags));
445 static void do_co_reg PARAMS ((char *operands, unsigned long flags));
446 static void do_fp_ctrl PARAMS ((char *operands, unsigned long flags));
447 static void do_fp_ldst PARAMS ((char *operands, unsigned long flags));
448 static void do_fp_ldmstm PARAMS ((char *operands, unsigned long flags));
449 static void do_fp_dyadic PARAMS ((char *operands, unsigned long flags));
450 static void do_fp_monadic PARAMS ((char *operands, unsigned long flags));
451 static void do_fp_cmp PARAMS ((char *operands, unsigned long flags));
452 static void do_fp_from_reg PARAMS ((char *operands, unsigned long flags));
453 static void do_fp_to_reg PARAMS ((char *operands, unsigned long flags));
455 static void fix_new_arm PARAMS ((fragS *frag, int where,
456 short int size, expressionS *exp,
457 int pc_rel, int reloc));
458 static int arm_reg_parse PARAMS ((char **ccp));
459 static int arm_psr_parse PARAMS ((char **ccp));
460 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT,
462 static int add_to_lit_pool PARAMS ((void));
463 static unsigned validate_immediate PARAMS ((unsigned));
464 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
465 static int validate_offset_imm PARAMS ((int, int));
466 static void opcode_select PARAMS ((int));
467 static void end_of_line PARAMS ((char *));
468 static int reg_required_here PARAMS ((char **, int));
469 static int psr_required_here PARAMS ((char **, int, int));
470 static int co_proc_number PARAMS ((char **));
471 static int cp_opc_expr PARAMS ((char **, int, int));
472 static int cp_reg_required_here PARAMS ((char **, int));
473 static int fp_reg_required_here PARAMS ((char **, int));
474 static int cp_address_offset PARAMS ((char **));
475 static int cp_address_required_here PARAMS ((char **));
476 static int my_get_float_expression PARAMS ((char **));
477 static int skip_past_comma PARAMS ((char **));
478 static int walk_no_bignums PARAMS ((symbolS *));
479 static int negate_data_op PARAMS ((unsigned long *,
481 static int data_op2 PARAMS ((char **));
482 static int fp_op2 PARAMS ((char **));
483 static long reg_list PARAMS ((char **));
484 static void thumb_load_store PARAMS ((char *, int, int));
485 static int decode_shift PARAMS ((char **, int));
486 static int ldst_extend PARAMS ((char **, int));
487 static void thumb_add_sub PARAMS ((char *, int));
488 static void insert_reg PARAMS ((int));
489 static void thumb_shift PARAMS ((char *, int));
490 static void thumb_mov_compare PARAMS ((char *, int));
491 static void set_constant_flonums PARAMS ((void));
492 static valueT md_chars_to_number PARAMS ((char *, int));
493 static void insert_reg_alias PARAMS ((char *, int));
494 static void output_inst PARAMS ((void));
496 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
499 /* ARM instructions take 4bytes in the object file, Thumb instructions
503 /* LONGEST_INST is the longest basic instruction name without conditions or
505 * ARM7M has 4 of length 5
508 #define LONGEST_INST 5
512 CONST char * template; /* Basic string to match */
513 unsigned long value; /* Basic instruction code */
514 CONST char * comp_suffix; /* Compulsory suffix that must follow conds */
515 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
516 unsigned long variants; /* Which CPU variants this exists for */
517 /* Function to call to parse args */
518 void (* parms) PARAMS ((char *, unsigned long));
521 static CONST struct asm_opcode insns[] =
523 /* ARM Instructions */
524 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
525 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
526 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
527 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
528 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
529 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
530 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
531 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
532 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
533 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
534 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
535 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
536 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
537 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
538 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
539 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
540 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
541 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
542 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
543 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
544 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
545 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
546 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
549 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
550 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
551 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
553 /* ARM 2 multiplies */
554 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
555 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
557 /* ARM 3 - swp instructions */
558 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
560 /* ARM 6 Coprocessor instructions */
561 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
562 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
563 /* ScottB: our code uses 0x0128f000 for msr.
564 NickC: but this is wrong because the bits 16 and 19 are handled
565 by the PSR_xxx defines above. */
567 /* ARM 7M long multiplies - need signed/unsigned flags! */
568 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
569 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
570 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
571 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
573 /* ARM THUMB interworking */
574 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
576 /* Floating point instructions */
577 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
578 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
579 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
580 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
581 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
582 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
583 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
584 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
585 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
586 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
587 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
588 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
589 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
590 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
591 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
592 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
593 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
594 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
595 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
596 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
597 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
598 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
599 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
600 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
602 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
603 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
604 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
605 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
606 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
607 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
608 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
609 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
610 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
611 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
612 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
613 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
614 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
615 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
616 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
617 be an optional suffix, but part of the instruction. To be compatible,
619 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
620 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
621 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
622 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
624 /* Generic copressor instructions */
625 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
626 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
627 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
628 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
629 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
632 /* defines for various bits that we will want to toggle */
634 #define INST_IMMEDIATE 0x02000000
635 #define OFFSET_REG 0x02000000
636 #define HWOFFSET_IMM 0x00400000
637 #define SHIFT_BY_REG 0x00000010
638 #define PRE_INDEX 0x01000000
639 #define INDEX_UP 0x00800000
640 #define WRITE_BACK 0x00200000
641 #define MULTI_SET_PSR 0x00400000
643 #define LITERAL_MASK 0xf000f000
644 #define COND_MASK 0xf0000000
645 #define OPCODE_MASK 0xfe1fffff
646 #define DATA_OP_SHIFT 21
648 /* Codes to distinguish the arithmetic instructions */
660 #define OPCODE_CMP 10
661 #define OPCODE_CMN 11
662 #define OPCODE_ORR 12
663 #define OPCODE_MOV 13
664 #define OPCODE_BIC 14
665 #define OPCODE_MVN 15
667 static void do_t_nop PARAMS ((char *operands));
668 static void do_t_arit PARAMS ((char *operands));
669 static void do_t_add PARAMS ((char *operands));
670 static void do_t_asr PARAMS ((char *operands));
671 static void do_t_branch9 PARAMS ((char *operands));
672 static void do_t_branch12 PARAMS ((char *operands));
673 static void do_t_branch23 PARAMS ((char *operands));
674 static void do_t_bx PARAMS ((char *operands));
675 static void do_t_compare PARAMS ((char *operands));
676 static void do_t_ldmstm PARAMS ((char *operands));
677 static void do_t_ldr PARAMS ((char *operands));
678 static void do_t_ldrb PARAMS ((char *operands));
679 static void do_t_ldrh PARAMS ((char *operands));
680 static void do_t_lds PARAMS ((char *operands));
681 static void do_t_lsl PARAMS ((char *operands));
682 static void do_t_lsr PARAMS ((char *operands));
683 static void do_t_mov PARAMS ((char *operands));
684 static void do_t_push_pop PARAMS ((char *operands));
685 static void do_t_str PARAMS ((char *operands));
686 static void do_t_strb PARAMS ((char *operands));
687 static void do_t_strh PARAMS ((char *operands));
688 static void do_t_sub PARAMS ((char *operands));
689 static void do_t_swi PARAMS ((char *operands));
690 static void do_t_adr PARAMS ((char *operands));
692 #define T_OPCODE_MUL 0x4340
693 #define T_OPCODE_TST 0x4200
694 #define T_OPCODE_CMN 0x42c0
695 #define T_OPCODE_NEG 0x4240
696 #define T_OPCODE_MVN 0x43c0
698 #define T_OPCODE_ADD_R3 0x1800
699 #define T_OPCODE_SUB_R3 0x1a00
700 #define T_OPCODE_ADD_HI 0x4400
701 #define T_OPCODE_ADD_ST 0xb000
702 #define T_OPCODE_SUB_ST 0xb080
703 #define T_OPCODE_ADD_SP 0xa800
704 #define T_OPCODE_ADD_PC 0xa000
705 #define T_OPCODE_ADD_I8 0x3000
706 #define T_OPCODE_SUB_I8 0x3800
707 #define T_OPCODE_ADD_I3 0x1c00
708 #define T_OPCODE_SUB_I3 0x1e00
710 #define T_OPCODE_ASR_R 0x4100
711 #define T_OPCODE_LSL_R 0x4080
712 #define T_OPCODE_LSR_R 0x40c0
713 #define T_OPCODE_ASR_I 0x1000
714 #define T_OPCODE_LSL_I 0x0000
715 #define T_OPCODE_LSR_I 0x0800
717 #define T_OPCODE_MOV_I8 0x2000
718 #define T_OPCODE_CMP_I8 0x2800
719 #define T_OPCODE_CMP_LR 0x4280
720 #define T_OPCODE_MOV_HR 0x4600
721 #define T_OPCODE_CMP_HR 0x4500
723 #define T_OPCODE_LDR_PC 0x4800
724 #define T_OPCODE_LDR_SP 0x9800
725 #define T_OPCODE_STR_SP 0x9000
726 #define T_OPCODE_LDR_IW 0x6800
727 #define T_OPCODE_STR_IW 0x6000
728 #define T_OPCODE_LDR_IH 0x8800
729 #define T_OPCODE_STR_IH 0x8000
730 #define T_OPCODE_LDR_IB 0x7800
731 #define T_OPCODE_STR_IB 0x7000
732 #define T_OPCODE_LDR_RW 0x5800
733 #define T_OPCODE_STR_RW 0x5000
734 #define T_OPCODE_LDR_RH 0x5a00
735 #define T_OPCODE_STR_RH 0x5200
736 #define T_OPCODE_LDR_RB 0x5c00
737 #define T_OPCODE_STR_RB 0x5400
739 #define T_OPCODE_PUSH 0xb400
740 #define T_OPCODE_POP 0xbc00
742 #define T_OPCODE_BRANCH 0xe7fe
744 static int thumb_reg PARAMS ((char ** str, int hi_lo));
746 #define THUMB_SIZE 2 /* Size of thumb instruction */
747 #define THUMB_REG_LO 0x1
748 #define THUMB_REG_HI 0x2
749 #define THUMB_REG_ANY 0x3
751 #define THUMB_H1 0x0080
752 #define THUMB_H2 0x0040
759 #define THUMB_COMPARE 1
762 #define THUMB_STORE 1
764 #define THUMB_PP_PC_LR 0x0100
766 /* These three are used for immediate shifts, do not alter */
768 #define THUMB_HALFWORD 1
773 CONST char * template; /* Basic string to match */
774 unsigned long value; /* Basic instruction code */
776 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
779 static CONST struct thumb_opcode tinsns[] =
781 {"adc", 0x4140, 2, do_t_arit},
782 {"add", 0x0000, 2, do_t_add},
783 {"and", 0x4000, 2, do_t_arit},
784 {"asr", 0x0000, 2, do_t_asr},
785 {"b", T_OPCODE_BRANCH, 2, do_t_branch12},
786 {"beq", 0xd0fe, 2, do_t_branch9},
787 {"bne", 0xd1fe, 2, do_t_branch9},
788 {"bcs", 0xd2fe, 2, do_t_branch9},
789 {"bhs", 0xd2fe, 2, do_t_branch9},
790 {"bcc", 0xd3fe, 2, do_t_branch9},
791 {"bul", 0xd3fe, 2, do_t_branch9},
792 {"blo", 0xd3fe, 2, do_t_branch9},
793 {"bmi", 0xd4fe, 2, do_t_branch9},
794 {"bpl", 0xd5fe, 2, do_t_branch9},
795 {"bvs", 0xd6fe, 2, do_t_branch9},
796 {"bvc", 0xd7fe, 2, do_t_branch9},
797 {"bhi", 0xd8fe, 2, do_t_branch9},
798 {"bls", 0xd9fe, 2, do_t_branch9},
799 {"bge", 0xdafe, 2, do_t_branch9},
800 {"blt", 0xdbfe, 2, do_t_branch9},
801 {"bgt", 0xdcfe, 2, do_t_branch9},
802 {"ble", 0xddfe, 2, do_t_branch9},
803 {"bic", 0x4380, 2, do_t_arit},
804 {"bl", 0xf7fffffe, 4, do_t_branch23},
805 {"bx", 0x4700, 2, do_t_bx},
806 {"cmn", T_OPCODE_CMN, 2, do_t_arit},
807 {"cmp", 0x0000, 2, do_t_compare},
808 {"eor", 0x4040, 2, do_t_arit},
809 {"ldmia", 0xc800, 2, do_t_ldmstm},
810 {"ldr", 0x0000, 2, do_t_ldr},
811 {"ldrb", 0x0000, 2, do_t_ldrb},
812 {"ldrh", 0x0000, 2, do_t_ldrh},
813 {"ldrsb", 0x5600, 2, do_t_lds},
814 {"ldrsh", 0x5e00, 2, do_t_lds},
815 {"ldsb", 0x5600, 2, do_t_lds},
816 {"ldsh", 0x5e00, 2, do_t_lds},
817 {"lsl", 0x0000, 2, do_t_lsl},
818 {"lsr", 0x0000, 2, do_t_lsr},
819 {"mov", 0x0000, 2, do_t_mov},
820 {"mul", T_OPCODE_MUL, 2, do_t_arit},
821 {"mvn", T_OPCODE_MVN, 2, do_t_arit},
822 {"neg", T_OPCODE_NEG, 2, do_t_arit},
823 {"orr", 0x4300, 2, do_t_arit},
824 {"pop", 0xbc00, 2, do_t_push_pop},
825 {"push", 0xb400, 2, do_t_push_pop},
826 {"ror", 0x41c0, 2, do_t_arit},
827 {"sbc", 0x4180, 2, do_t_arit},
828 {"stmia", 0xc000, 2, do_t_ldmstm},
829 {"str", 0x0000, 2, do_t_str},
830 {"strb", 0x0000, 2, do_t_strb},
831 {"strh", 0x0000, 2, do_t_strh},
832 {"swi", 0xdf00, 2, do_t_swi},
833 {"sub", 0x0000, 2, do_t_sub},
834 {"tst", T_OPCODE_TST, 2, do_t_arit},
836 {"adr", 0x0000, 2, do_t_adr},
837 {"nop", 0x46C0, 2, do_t_nop}, /* mov r8,r8 */
846 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
847 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
848 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
854 /* These are the standard names; Users can add aliases with .req */
855 static CONST struct reg_entry reg_table[] =
857 /* Processor Register Numbers */
858 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
859 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
860 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
861 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
862 /* APCS conventions */
863 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
864 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
865 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
866 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
868 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
869 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
870 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
871 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
872 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
873 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
874 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
875 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
876 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
877 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
881 #define bad_args _("Bad arguments to instruction");
882 #define bad_pc _("r15 not allowed here");
884 static struct hash_control * arm_ops_hsh = NULL;
885 static struct hash_control * arm_tops_hsh = NULL;
886 static struct hash_control * arm_cond_hsh = NULL;
887 static struct hash_control * arm_shift_hsh = NULL;
888 static struct hash_control * arm_reg_hsh = NULL;
889 static struct hash_control * arm_psr_hsh = NULL;
891 /* This table describes all the machine specific pseudo-ops the assembler
892 has to support. The fields are:
893 pseudo-op name without dot
894 function to call to execute this pseudo-op
895 Integer arg to pass to the function
898 static void s_req PARAMS ((int));
899 static void s_align PARAMS ((int));
900 static void s_bss PARAMS ((int));
901 static void s_even PARAMS ((int));
902 static void s_ltorg PARAMS ((int));
903 static void s_arm PARAMS ((int));
904 static void s_thumb PARAMS ((int));
905 static void s_code PARAMS ((int));
906 static void s_force_thumb PARAMS ((int));
907 static void s_thumb_func PARAMS ((int));
908 static void s_thumb_set PARAMS ((int));
909 static void arm_s_text PARAMS ((int));
910 static void arm_s_data PARAMS ((int));
912 static void arm_s_section PARAMS ((int));
913 static void s_arm_elf_cons PARAMS ((int));
916 static int my_get_expression PARAMS ((expressionS *, char **));
918 CONST pseudo_typeS md_pseudo_table[] =
920 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
922 { "align", s_align, 0 },
924 { "thumb", s_thumb, 0 },
925 { "code", s_code, 0 },
926 { "force_thumb", s_force_thumb, 0 },
927 { "thumb_func", s_thumb_func, 0 },
928 { "thumb_set", s_thumb_set, 0 },
929 { "even", s_even, 0 },
930 { "ltorg", s_ltorg, 0 },
931 { "pool", s_ltorg, 0 },
932 /* Allow for the effect of section changes. */
933 { "text", arm_s_text, 0 },
934 { "data", arm_s_data, 0 },
936 { "section", arm_s_section, 0 },
937 { "section.s", arm_s_section, 0 },
938 { "sect", arm_s_section, 0 },
939 { "sect.s", arm_s_section, 0 },
940 { "word", s_arm_elf_cons, 4 },
941 { "long", s_arm_elf_cons, 4 },
945 { "extend", float_cons, 'x' },
946 { "ldouble", float_cons, 'x' },
947 { "packed", float_cons, 'p' },
951 /* Stuff needed to resolve the label ambiguity
961 symbolS * last_label_seen;
962 static int label_is_thumb_function_name = false;
966 #define MAX_LITERAL_POOL_SIZE 1024
968 typedef struct literalS
970 struct expressionS exp;
971 struct arm_it * inst;
974 literalT literals[MAX_LITERAL_POOL_SIZE];
975 int next_literal_pool_place = 0; /* Next free entry in the pool */
976 int lit_pool_num = 1; /* Next literal pool number */
977 symbolS * current_poolP = NULL;
984 if (current_poolP == NULL)
985 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
986 (valueT) 0, &zero_address_frag);
988 /* Check if this literal value is already in the pool: */
989 while (lit_count < next_literal_pool_place)
991 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
992 && inst.reloc.exp.X_op == O_constant
993 && literals[lit_count].exp.X_add_number == inst.reloc.exp.X_add_number
994 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
999 if (lit_count == next_literal_pool_place) /* new entry */
1001 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1003 inst.error = _("Literal Pool Overflow");
1007 literals[next_literal_pool_place].exp = inst.reloc.exp;
1008 lit_count = next_literal_pool_place++;
1011 inst.reloc.exp.X_op = O_symbol;
1012 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1013 inst.reloc.exp.X_add_symbol = current_poolP;
1018 /* Can't use symbol_new here, so have to create a symbol and then at
1019 a later date assign it a value. Thats what these functions do. */
1021 symbol_locate (symbolP, name, segment, valu, frag)
1023 CONST char * name; /* It is copied, the caller can modify */
1024 segT segment; /* Segment identifier (SEG_<something>) */
1025 valueT valu; /* Symbol value */
1026 fragS * frag; /* Associated fragment */
1028 unsigned int name_length;
1029 char * preserved_copy_of_name;
1031 name_length = strlen (name) + 1; /* +1 for \0 */
1032 obstack_grow (¬es, name, name_length);
1033 preserved_copy_of_name = obstack_finish (¬es);
1034 #ifdef STRIP_UNDERSCORE
1035 if (preserved_copy_of_name[0] == '_')
1036 preserved_copy_of_name++;
1039 #ifdef tc_canonicalize_symbol_name
1040 preserved_copy_of_name =
1041 tc_canonicalize_symbol_name (preserved_copy_of_name);
1044 S_SET_NAME (symbolP, preserved_copy_of_name);
1046 S_SET_SEGMENT (symbolP, segment);
1047 S_SET_VALUE (symbolP, valu);
1048 symbol_clear_list_pointers(symbolP);
1050 symbol_set_frag (symbolP, frag);
1052 /* Link to end of symbol chain. */
1054 extern int symbol_table_frozen;
1055 if (symbol_table_frozen)
1059 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1061 obj_symbol_new_hook (symbolP);
1063 #ifdef tc_symbol_new_hook
1064 tc_symbol_new_hook (symbolP);
1068 verify_symbol_chain (symbol_rootP, symbol_lastP);
1069 #endif /* DEBUG_SYMS */
1072 /* Check that an immediate is valid, and if so, convert it to the right format. */
1075 validate_immediate (val)
1081 #define rotate_left(v, n) (v << n | v >> (32 - n))
1083 for (i = 0; i < 32; i += 2)
1084 if ((a = rotate_left (val, i)) <= 0xff)
1085 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1090 /* Check to see if an immediate can be computed as two seperate immediate
1091 values, added together. We already know that this value cannot be
1092 computed by just one ARM instruction. */
1095 validate_immediate_twopart (val, highpart)
1097 unsigned int * highpart;
1102 for (i = 0; i < 32; i += 2)
1103 if (((a = rotate_left (val, i)) & 0xff) != 0)
1109 * highpart = (a >> 8) | ((i + 24) << 7);
1111 else if (a & 0xff0000)
1116 * highpart = (a >> 16) | ((i + 16) << 7);
1120 assert (a & 0xff000000);
1122 * highpart = (a >> 24) | ((i + 8) << 7);
1125 return (a & 0xff) | (i << 7);
1132 validate_offset_imm (val, hwse)
1136 if ((hwse && (val < -255 || val > 255))
1137 || (val < -4095 || val > 4095))
1147 as_bad (_("Invalid syntax for .req directive."));
1154 /* We don't support putting frags in the BSS segment, we fake it by
1155 marking in_bss, then looking at s_skip for clues?.. */
1156 subseg_set (bss_section, 0);
1157 demand_empty_rest_of_line ();
1164 if (!need_pass_2) /* Never make frag if expect extra pass. */
1165 frag_align (1, 0, 0);
1167 record_alignment (now_seg, 1);
1169 demand_empty_rest_of_line ();
1179 if (current_poolP == NULL)
1182 /* Align pool as you have word accesses */
1183 /* Only make a frag if we have to ... */
1185 frag_align (2, 0, 0);
1187 record_alignment (now_seg, 2);
1189 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1191 symbol_locate (current_poolP, sym_name, now_seg,
1192 (valueT) frag_now_fix (), frag_now);
1193 symbol_table_insert (current_poolP);
1195 ARM_SET_THUMB (current_poolP, thumb_mode);
1197 #if defined OBJ_COFF || defined OBJ_ELF
1198 ARM_SET_INTERWORK (current_poolP, support_interwork);
1201 while (lit_count < next_literal_pool_place)
1202 /* First output the expression in the instruction to the pool */
1203 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1205 next_literal_pool_place = 0;
1206 current_poolP = NULL;
1210 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1214 register long temp_fill;
1215 long max_alignment = 15;
1217 temp = get_absolute_expression ();
1218 if (temp > max_alignment)
1219 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1222 as_bad (_("Alignment negative. 0 assumed."));
1226 if (*input_line_pointer == ',')
1228 input_line_pointer++;
1229 temp_fill = get_absolute_expression ();
1237 /* Only make a frag if we HAVE to. . . */
1238 if (temp && !need_pass_2)
1239 frag_align (temp, (int) temp_fill, 0);
1240 demand_empty_rest_of_line ();
1242 record_alignment (now_seg, temp);
1246 s_force_thumb (ignore)
1249 /* If we are not already in thumb mode go into it, EVEN if
1250 the target processor does not support thumb instructions.
1251 This is used by gcc/config/arm/lib1funcs.asm for example
1252 to compile interworking support functions even if the
1253 target processor should not support interworking. */
1259 record_alignment (now_seg, 1);
1262 demand_empty_rest_of_line ();
1266 s_thumb_func (ignore)
1269 /* The following label is the name/address of the start of a Thumb function.
1270 We need to know this for the interworking support. */
1272 label_is_thumb_function_name = true;
1274 demand_empty_rest_of_line ();
1277 /* Perform a .set directive, but also mark the alias as
1278 being a thumb function. */
1284 /* XXX the following is a duplicate of the code for s_set() in read.c
1285 We cannot just call that code as we need to get at the symbol that
1287 register char * name;
1288 register char delim;
1289 register char * end_name;
1290 register symbolS * symbolP;
1293 * Especial apologies for the random logic:
1294 * this just grew, and could be parsed much more simply!
1297 name = input_line_pointer;
1298 delim = get_symbol_end ();
1299 end_name = input_line_pointer;
1304 if (*input_line_pointer != ',')
1307 as_bad (_("Expected comma after name \"%s\""), name);
1309 ignore_rest_of_line ();
1313 input_line_pointer++;
1316 if (name[0] == '.' && name[1] == '\0')
1318 /* XXX - this should not happen to .thumb_set */
1322 if ((symbolP = symbol_find (name)) == NULL
1323 && (symbolP = md_undefined_symbol (name)) == NULL)
1326 /* When doing symbol listings, play games with dummy fragments living
1327 outside the normal fragment chain to record the file and line info
1329 if (listing & LISTING_SYMBOLS)
1331 extern struct list_info_struct * listing_tail;
1332 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1333 memset (dummy_frag, 0, sizeof(fragS));
1334 dummy_frag->fr_type = rs_fill;
1335 dummy_frag->line = listing_tail;
1336 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1337 dummy_frag->fr_symbol = symbolP;
1341 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1344 /* "set" symbols are local unless otherwise specified. */
1345 SF_SET_LOCAL (symbolP);
1346 #endif /* OBJ_COFF */
1347 } /* make a new symbol */
1349 symbol_table_insert (symbolP);
1354 && S_IS_DEFINED (symbolP)
1355 && S_GET_SEGMENT (symbolP) != reg_section)
1356 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1358 pseudo_set (symbolP);
1360 demand_empty_rest_of_line ();
1362 /* XXX now we come to the Thumb specific bit of code. */
1364 THUMB_SET_FUNC (symbolP, 1);
1365 ARM_SET_THUMB (symbolP, 1);
1366 ARM_SET_INTERWORK (symbolP, support_interwork);
1369 /* If we change section we must dump the literal pool first. */
1374 if (now_seg != text_section)
1384 if (flag_readonly_data_in_text)
1386 if (now_seg != text_section)
1389 else if (now_seg != data_section)
1397 arm_s_section (ignore)
1402 obj_elf_section (ignore);
1407 opcode_select (width)
1415 if (! (cpu_variant & ARM_THUMB))
1416 as_bad (_("selected processor does not support THUMB opcodes"));
1418 /* No need to force the alignment, since we will have been
1419 coming from ARM mode, which is word-aligned. */
1420 record_alignment (now_seg, 1);
1427 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1428 as_bad (_("selected processor does not support ARM opcodes"));
1431 frag_align (2, 0, 0);
1432 record_alignment (now_seg, 1);
1437 as_bad (_("invalid instruction size selected (%d)"), width);
1446 demand_empty_rest_of_line ();
1454 demand_empty_rest_of_line ();
1463 temp = get_absolute_expression ();
1468 opcode_select (temp);
1472 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1484 inst.error = _("Garbage following instruction");
1488 skip_past_comma (str)
1494 while ((c = *p) == ' ' || c == ',')
1497 if (c == ',' && comma++)
1505 return comma ? SUCCESS : FAIL;
1508 /* A standard register must be given at this point. Shift is the place to
1509 put it in the instruction. */
1512 reg_required_here (str, shift)
1516 static char buff [128]; /* XXX */
1518 char * start = *str;
1520 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1523 inst.instruction |= reg << shift;
1527 /* Restore the start point, we may have got a reg of the wrong class. */
1530 /* In the few cases where we might be able to accept something else
1531 this error can be overridden */
1532 sprintf (buff, _("Register expected, not '%.100s'"), start);
1539 psr_required_here (str, cpsr, spsr)
1545 char * start = *str;
1546 psr = arm_psr_parse (str);
1548 if (psr == cpsr || psr == spsr)
1551 inst.instruction |= 1 << 22;
1556 /* In the few cases where we might be able to accept something else
1557 this error can be overridden */
1558 inst.error = _("<psr(f)> expected");
1560 /* Restore the start point. */
1566 co_proc_number (str)
1569 int processor, pchar;
1571 while (**str == ' ')
1574 /* The data sheet seems to imply that just a number on its own is valid
1575 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1577 if (**str == 'p' || **str == 'P')
1581 if (pchar >= '0' && pchar <= '9')
1583 processor = pchar - '0';
1584 if (**str >= '0' && **str <= '9')
1586 processor = processor * 10 + *(*str)++ - '0';
1589 inst.error = _("Illegal co-processor number");
1596 inst.error = _("Bad or missing co-processor number");
1600 inst.instruction |= processor << 8;
1605 cp_opc_expr (str, where, length)
1612 while (**str == ' ')
1615 memset (&expr, '\0', sizeof (expr));
1617 if (my_get_expression (&expr, str))
1619 if (expr.X_op != O_constant)
1621 inst.error = _("bad or missing expression");
1625 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1627 inst.error = _("immediate co-processor expression too large");
1631 inst.instruction |= expr.X_add_number << where;
1636 cp_reg_required_here (str, where)
1641 char * start = *str;
1643 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1646 inst.instruction |= reg << where;
1650 /* In the few cases where we might be able to accept something else
1651 this error can be overridden */
1652 inst.error = _("Co-processor register expected");
1654 /* Restore the start point */
1660 fp_reg_required_here (str, where)
1665 char * start = *str;
1667 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1670 inst.instruction |= reg << where;
1674 /* In the few cases where we might be able to accept something else
1675 this error can be overridden */
1676 inst.error = _("Floating point register expected");
1678 /* Restore the start point */
1684 cp_address_offset (str)
1689 while (**str == ' ')
1692 if (! is_immediate_prefix (**str))
1694 inst.error = _("immediate expression expected");
1700 if (my_get_expression (& inst.reloc.exp, str))
1703 if (inst.reloc.exp.X_op == O_constant)
1705 offset = inst.reloc.exp.X_add_number;
1709 inst.error = _("co-processor address must be word aligned");
1713 if (offset > 1023 || offset < -1023)
1715 inst.error = _("offset too large");
1720 inst.instruction |= INDEX_UP;
1724 inst.instruction |= offset >> 2;
1727 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1733 cp_address_required_here (str)
1748 if ((reg = reg_required_here (& p, 16)) == FAIL)
1758 if (skip_past_comma (& p) == SUCCESS)
1761 write_back = WRITE_BACK;
1765 inst.error = _("pc may not be used in post-increment");
1769 if (cp_address_offset (& p) == FAIL)
1773 pre_inc = PRE_INDEX | INDEX_UP;
1777 /* '['Rn, #expr']'[!] */
1779 if (skip_past_comma (& p) == FAIL)
1781 inst.error = _("pre-indexed expression expected");
1785 pre_inc = PRE_INDEX;
1787 if (cp_address_offset (& p) == FAIL)
1795 inst.error = _("missing ]");
1806 inst.error = _("pc may not be used with write-back");
1811 write_back = WRITE_BACK;
1817 if (my_get_expression (&inst.reloc.exp, &p))
1820 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1821 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1822 inst.reloc.pc_rel = 1;
1823 inst.instruction |= (REG_PC << 16);
1824 pre_inc = PRE_INDEX;
1827 inst.instruction |= write_back | pre_inc;
1835 unsigned long flags;
1837 /* Do nothing really */
1838 inst.instruction |= flags; /* This is pointless */
1846 unsigned long flags;
1848 /* Only one syntax */
1852 if (reg_required_here (&str, 12) == FAIL)
1854 inst.error = bad_args;
1858 if (skip_past_comma (&str) == FAIL
1859 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1861 inst.error = _("<psr> expected");
1865 inst.instruction |= flags;
1870 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
1874 unsigned long flags;
1881 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1883 inst.instruction |= PSR_ALL;
1885 /* Sytax should be "<psr>, Rm" */
1886 if (skip_past_comma (&str) == FAIL
1887 || (reg = reg_required_here (&str, 0)) == FAIL)
1889 inst.error = bad_args;
1895 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1896 inst.instruction |= PSR_FLAGS;
1897 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1898 inst.instruction |= PSR_CONTROL;
1901 inst.error = bad_args;
1905 if (skip_past_comma (&str) == FAIL)
1907 inst.error = bad_args;
1911 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1913 if ((reg = reg_required_here (& str, 0)) != FAIL)
1915 /* Immediate expression */
1916 else if (is_immediate_prefix (* str))
1921 if (my_get_expression (& inst.reloc.exp, & str))
1923 inst.error = _("Register or shift expression expected");
1927 if (inst.reloc.exp.X_add_symbol)
1929 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1930 inst.reloc.pc_rel = 0;
1934 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1937 inst.error = _("Invalid constant");
1941 inst.instruction |= value;
1944 flags |= INST_IMMEDIATE;
1948 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1954 inst.instruction |= flags;
1959 /* Long Multiply Parser
1960 UMULL RdLo, RdHi, Rm, Rs
1961 SMULL RdLo, RdHi, Rm, Rs
1962 UMLAL RdLo, RdHi, Rm, Rs
1963 SMLAL RdLo, RdHi, Rm, Rs
1966 do_mull (str, flags)
1968 unsigned long flags;
1970 int rdlo, rdhi, rm, rs;
1972 /* only one format "rdlo, rdhi, rm, rs" */
1976 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1978 inst.error = bad_args;
1982 if (skip_past_comma (&str) == FAIL
1983 || (rdhi = reg_required_here (&str, 16)) == FAIL)
1985 inst.error = bad_args;
1989 if (skip_past_comma (&str) == FAIL
1990 || (rm = reg_required_here (&str, 0)) == FAIL)
1992 inst.error = bad_args;
1996 /* rdhi, rdlo and rm must all be different */
1997 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
1998 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2000 if (skip_past_comma (&str) == FAIL
2001 || (rs = reg_required_here (&str, 8)) == FAIL)
2003 inst.error = bad_args;
2007 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2009 inst.error = bad_pc;
2013 inst.instruction |= flags;
2021 unsigned long flags;
2025 /* only one format "rd, rm, rs" */
2029 if ((rd = reg_required_here (&str, 16)) == FAIL)
2031 inst.error = bad_args;
2037 inst.error = bad_pc;
2041 if (skip_past_comma (&str) == FAIL
2042 || (rm = reg_required_here (&str, 0)) == FAIL)
2044 inst.error = bad_args;
2050 inst.error = bad_pc;
2055 as_tsktsk (_("rd and rm should be different in mul"));
2057 if (skip_past_comma (&str) == FAIL
2058 || (rm = reg_required_here (&str, 8)) == FAIL)
2060 inst.error = bad_args;
2066 inst.error = bad_pc;
2070 inst.instruction |= flags;
2078 unsigned long flags;
2082 /* only one format "rd, rm, rs, rn" */
2086 if ((rd = reg_required_here (&str, 16)) == FAIL)
2088 inst.error = bad_args;
2094 inst.error = bad_pc;
2098 if (skip_past_comma (&str) == FAIL
2099 || (rm = reg_required_here (&str, 0)) == FAIL)
2101 inst.error = bad_args;
2107 inst.error = bad_pc;
2112 as_tsktsk (_("rd and rm should be different in mla"));
2114 if (skip_past_comma (&str) == FAIL
2115 || (rd = reg_required_here (&str, 8)) == FAIL
2116 || skip_past_comma (&str) == FAIL
2117 || (rm = reg_required_here (&str, 12)) == FAIL)
2119 inst.error = bad_args;
2123 if (rd == REG_PC || rm == REG_PC)
2125 inst.error = bad_pc;
2129 inst.instruction |= flags;
2134 /* Returns the index into fp_values of a floating point number, or -1 if
2135 not in the table. */
2137 my_get_float_expression (str)
2140 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2146 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2147 /* Look for a raw floating point number */
2148 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2149 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
2151 for (i = 0; i < NUM_FLOAT_VALS; i++)
2153 for (j = 0; j < MAX_LITTLENUMS; j++)
2155 if (words[j] != fp_values[i][j])
2159 if (j == MAX_LITTLENUMS)
2167 /* Try and parse a more complex expression, this will probably fail
2168 unless the code uses a floating point prefix (eg "0f") */
2169 save_in = input_line_pointer;
2170 input_line_pointer = *str;
2171 if (expression (&exp) == absolute_section
2172 && exp.X_op == O_big
2173 && exp.X_add_number < 0)
2175 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2177 if (gen_to_words (words, 5, (long)15) == 0)
2179 for (i = 0; i < NUM_FLOAT_VALS; i++)
2181 for (j = 0; j < MAX_LITTLENUMS; j++)
2183 if (words[j] != fp_values[i][j])
2187 if (j == MAX_LITTLENUMS)
2189 *str = input_line_pointer;
2190 input_line_pointer = save_in;
2197 *str = input_line_pointer;
2198 input_line_pointer = save_in;
2202 /* Return true if anything in the expression is a bignum */
2204 walk_no_bignums (sp)
2207 if (symbol_get_value_expression (sp)->X_op == O_big)
2210 if (symbol_get_value_expression (sp)->X_add_symbol)
2212 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2213 || (symbol_get_value_expression (sp)->X_op_symbol
2214 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2221 my_get_expression (ep, str)
2228 save_in = input_line_pointer;
2229 input_line_pointer = *str;
2230 seg = expression (ep);
2233 if (seg != absolute_section
2234 && seg != text_section
2235 && seg != data_section
2236 && seg != bss_section
2237 && seg != undefined_section)
2239 inst.error = _("bad_segment");
2240 *str = input_line_pointer;
2241 input_line_pointer = save_in;
2246 /* Get rid of any bignums now, so that we don't generate an error for which
2247 we can't establish a line number later on. Big numbers are never valid
2248 in instructions, which is where this routine is always called. */
2249 if (ep->X_op == O_big
2250 || (ep->X_add_symbol
2251 && (walk_no_bignums (ep->X_add_symbol)
2253 && walk_no_bignums (ep->X_op_symbol)))))
2255 inst.error = _("Invalid constant");
2256 *str = input_line_pointer;
2257 input_line_pointer = save_in;
2261 *str = input_line_pointer;
2262 input_line_pointer = save_in;
2266 /* unrestrict should be one if <shift> <register> is permitted for this
2270 decode_shift (str, unrestrict)
2274 struct asm_shift * shft;
2278 while (**str == ' ')
2281 for (p = *str; isalpha (*p); p++)
2286 inst.error = _("Shift expression expected");
2292 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2296 if (!strncmp (*str, "rrx", 3)
2297 || !strncmp (*str, "RRX", 3))
2300 inst.instruction |= shft->value;
2307 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2309 inst.instruction |= shft->value | SHIFT_BY_REG;
2313 else if (is_immediate_prefix (* p))
2317 if (my_get_expression (&inst.reloc.exp, &p))
2320 /* Validate some simple #expressions */
2321 if (inst.reloc.exp.X_op == O_constant)
2323 unsigned num = inst.reloc.exp.X_add_number;
2325 /* Reject operations greater than 32, or lsl #32 */
2326 if (num > 32 || (num == 32 && shft->value == 0))
2328 inst.error = _("Invalid immediate shift");
2332 /* Shifts of zero should be converted to lsl (which is zero)*/
2339 /* Shifts of 32 are encoded as 0, for those shifts that
2344 inst.instruction |= (num << 7) | shft->value;
2349 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2350 inst.reloc.pc_rel = 0;
2351 inst.instruction |= shft->value;
2357 inst.error = unrestrict ? _("shift requires register or #expression")
2358 : _("shift requires #expression");
2364 inst.error = _("Shift expression expected");
2368 /* Do those data_ops which can take a negative immediate constant */
2369 /* by altering the instuction. A bit of a hack really */
2373 by inverting the second operand, and
2376 by negating the second operand.
2379 negate_data_op (instruction, value)
2380 unsigned long * instruction;
2381 unsigned long value;
2384 unsigned long negated, inverted;
2386 negated = validate_immediate (-value);
2387 inverted = validate_immediate (~value);
2389 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2393 case OPCODE_SUB: /* ADD <-> SUB */
2394 new_inst = OPCODE_ADD;
2399 new_inst = OPCODE_SUB;
2403 case OPCODE_CMP: /* CMP <-> CMN */
2404 new_inst = OPCODE_CMN;
2409 new_inst = OPCODE_CMP;
2413 /* Now Inverted ops */
2414 case OPCODE_MOV: /* MOV <-> MVN */
2415 new_inst = OPCODE_MVN;
2420 new_inst = OPCODE_MOV;
2424 case OPCODE_AND: /* AND <-> BIC */
2425 new_inst = OPCODE_BIC;
2430 new_inst = OPCODE_AND;
2434 case OPCODE_ADC: /* ADC <-> SBC */
2435 new_inst = OPCODE_SBC;
2440 new_inst = OPCODE_ADC;
2444 /* We cannot do anything */
2452 *instruction &= OPCODE_MASK;
2453 *instruction |= new_inst << DATA_OP_SHIFT;
2464 while (**str == ' ')
2467 if (reg_required_here (str, 0) != FAIL)
2469 if (skip_past_comma (str) == SUCCESS)
2471 /* Shift operation on register */
2472 return decode_shift (str, NO_SHIFT_RESTRICT);
2478 /* Immediate expression */
2479 if (is_immediate_prefix (**str))
2483 if (my_get_expression (&inst.reloc.exp, str))
2486 if (inst.reloc.exp.X_add_symbol)
2488 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2489 inst.reloc.pc_rel = 0;
2493 if (skip_past_comma (str) == SUCCESS)
2495 /* #x, y -- ie explicit rotation by Y */
2496 if (my_get_expression (&expr, str))
2499 if (expr.X_op != O_constant)
2501 inst.error = _("Constant expression expected");
2505 /* Rotate must be a multiple of 2 */
2506 if (((unsigned) expr.X_add_number) > 30
2507 || (expr.X_add_number & 1) != 0
2508 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2510 inst.error = _("Invalid constant");
2513 inst.instruction |= INST_IMMEDIATE;
2514 inst.instruction |= inst.reloc.exp.X_add_number;
2515 inst.instruction |= expr.X_add_number << 7;
2519 /* Implicit rotation, select a suitable one */
2520 value = validate_immediate (inst.reloc.exp.X_add_number);
2524 /* Can't be done, perhaps the code reads something like
2525 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2526 if ((value = negate_data_op (&inst.instruction,
2527 inst.reloc.exp.X_add_number))
2530 inst.error = _("Invalid constant");
2535 inst.instruction |= value;
2538 inst.instruction |= INST_IMMEDIATE;
2543 inst.error = _("Register or shift expression expected");
2552 while (**str == ' ')
2555 if (fp_reg_required_here (str, 0) != FAIL)
2559 /* Immediate expression */
2560 if (*((*str)++) == '#')
2565 while (**str == ' ')
2568 /* First try and match exact strings, this is to guarantee that
2569 some formats will work even for cross assembly */
2571 for (i = 0; fp_const[i]; i++)
2573 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2577 *str += strlen (fp_const[i]);
2578 if (is_end_of_line[(int)**str] || **str == '\0')
2580 inst.instruction |= i + 8;
2587 /* Just because we didn't get a match doesn't mean that the
2588 constant isn't valid, just that it is in a format that we
2589 don't automatically recognize. Try parsing it with
2590 the standard expression routines. */
2591 if ((i = my_get_float_expression (str)) >= 0)
2593 inst.instruction |= i + 8;
2597 inst.error = _("Invalid floating point immediate expression");
2600 inst.error = _("Floating point register or immediate expression expected");
2606 do_arit (str, flags)
2608 unsigned long flags;
2613 if (reg_required_here (&str, 12) == FAIL
2614 || skip_past_comma (&str) == FAIL
2615 || reg_required_here (&str, 16) == FAIL
2616 || skip_past_comma (&str) == FAIL
2617 || data_op2 (&str) == FAIL)
2620 inst.error = bad_args;
2624 inst.instruction |= flags;
2632 unsigned long flags;
2634 /* This is a pseudo-op of the form "adr rd, label" to be converted
2635 into a relative address of the form "add rd, pc, #label-.-8" */
2640 if (reg_required_here (&str, 12) == FAIL
2641 || skip_past_comma (&str) == FAIL
2642 || my_get_expression (&inst.reloc.exp, &str))
2645 inst.error = bad_args;
2648 /* Frag hacking will turn this into a sub instruction if the offset turns
2649 out to be negative. */
2650 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2651 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2652 inst.reloc.pc_rel = 1;
2653 inst.instruction |= flags;
2659 do_adrl (str, flags)
2661 unsigned long flags;
2663 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2664 into a relative address of the form:
2665 add rd, pc, #low(label-.-8)"
2666 add rd, rd, #high(label-.-8)" */
2668 while (* str == ' ')
2671 if (reg_required_here (& str, 12) == FAIL
2672 || skip_past_comma (& str) == FAIL
2673 || my_get_expression (& inst.reloc.exp, & str))
2676 inst.error = bad_args;
2682 /* Frag hacking will turn this into a sub instruction if the offset turns
2683 out to be negative. */
2684 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2685 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2686 inst.reloc.pc_rel = 1;
2687 inst.instruction |= flags;
2688 inst.size = INSN_SIZE * 2;
2696 unsigned long flags;
2701 if (reg_required_here (&str, 16) == FAIL)
2704 inst.error = bad_args;
2708 if (skip_past_comma (&str) == FAIL
2709 || data_op2 (&str) == FAIL)
2712 inst.error = bad_args;
2716 inst.instruction |= flags;
2717 if ((flags & 0x0000f000) == 0)
2718 inst.instruction |= CONDS_BIT;
2727 unsigned long flags;
2732 if (reg_required_here (&str, 12) == FAIL)
2735 inst.error = bad_args;
2739 if (skip_past_comma (&str) == FAIL
2740 || data_op2 (&str) == FAIL)
2743 inst.error = bad_args;
2747 inst.instruction |= flags;
2753 ldst_extend (str, hwse)
2764 if (my_get_expression (& inst.reloc.exp, str))
2767 if (inst.reloc.exp.X_op == O_constant)
2769 int value = inst.reloc.exp.X_add_number;
2771 if ((hwse && (value < -255 || value > 255))
2772 || (value < -4095 || value > 4095))
2774 inst.error = _("address offset too large");
2784 /* Halfword and signextension instructions have the
2785 immediate value split across bits 11..8 and bits 3..0 */
2787 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2789 inst.instruction |= add | value;
2795 inst.instruction |= HWOFFSET_IMM;
2796 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2799 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2800 inst.reloc.pc_rel = 0;
2805 add = 0; /* and fall through */
2807 (*str)++; /* and fall through */
2809 if (reg_required_here (str, 0) == FAIL)
2813 inst.instruction |= add;
2816 inst.instruction |= add | OFFSET_REG;
2817 if (skip_past_comma (str) == SUCCESS)
2818 return decode_shift (str, SHIFT_RESTRICT);
2826 do_ldst (str, flags)
2828 unsigned long flags;
2835 /* This is not ideal, but it is the simplest way of dealing with the
2836 ARM7T halfword instructions (since they use a different
2837 encoding, but the same mnemonic): */
2838 halfword = (flags & 0x80000000) != 0;
2841 /* This is actually a load/store of a halfword, or a
2842 signed-extension load */
2843 if ((cpu_variant & ARM_HALFWORD) == 0)
2846 = _("Processor does not support halfwords or signed bytes");
2850 inst.instruction = (inst.instruction & COND_MASK)
2851 | (flags & ~COND_MASK);
2859 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2862 inst.error = bad_args;
2866 if (skip_past_comma (& str) == FAIL)
2868 inst.error = _("Address expected");
2880 if ((reg = reg_required_here (&str, 16)) == FAIL)
2883 conflict_reg = (((conflict_reg == reg)
2884 && (inst.instruction & LOAD_BIT))
2893 if (skip_past_comma (&str) == SUCCESS)
2895 /* [Rn],... (post inc) */
2896 if (ldst_extend (&str, halfword) == FAIL)
2899 as_warn (_("destination register same as write-back base\n"));
2905 inst.instruction |= HWOFFSET_IMM;
2913 as_warn (_("destination register same as write-back base\n"));
2915 inst.instruction |= WRITE_BACK;
2919 if (! (flags & TRANS_BIT))
2926 if (skip_past_comma (&str) == FAIL)
2928 inst.error = _("pre-indexed expression expected");
2933 if (ldst_extend (&str, halfword) == FAIL)
2941 inst.error = _("missing ]");
2951 as_tsktsk (_("destination register same as write-back base\n"));
2953 inst.instruction |= WRITE_BACK;
2957 else if (*str == '=')
2959 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2965 if (my_get_expression (&inst.reloc.exp, &str))
2968 if (inst.reloc.exp.X_op != O_constant
2969 && inst.reloc.exp.X_op != O_symbol)
2971 inst.error = _("Constant expression expected");
2975 if (inst.reloc.exp.X_op == O_constant
2976 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2978 /* This can be done with a mov instruction */
2979 inst.instruction &= LITERAL_MASK;
2980 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2981 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2987 /* Insert into literal pool */
2988 if (add_to_lit_pool () == FAIL)
2991 inst.error = _("literal pool insertion failed");
2995 /* Change the instruction exp to point to the pool */
2998 inst.instruction |= HWOFFSET_IMM;
2999 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3002 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3003 inst.reloc.pc_rel = 1;
3004 inst.instruction |= (REG_PC << 16);
3010 if (my_get_expression (&inst.reloc.exp, &str))
3015 inst.instruction |= HWOFFSET_IMM;
3016 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3019 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3020 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3021 inst.reloc.pc_rel = 1;
3022 inst.instruction |= (REG_PC << 16);
3026 if (pre_inc && (flags & TRANS_BIT))
3027 inst.error = _("Pre-increment instruction with translate");
3029 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3042 /* We come back here if we get ranges concatenated by '+' or '|' */
3060 if ((reg = reg_required_here (& str, -1)) == FAIL)
3069 inst.error = _("Bad range in register list");
3073 for (i = cur_reg + 1; i < reg; i++)
3075 if (range & (1 << i))
3077 (_("Warning: Duplicated register (r%d) in register list"),
3085 if (range & (1 << reg))
3086 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3088 else if (reg <= cur_reg)
3089 as_tsktsk (_("Warning: Register range not in ascending order"));
3093 } while (skip_past_comma (&str) != FAIL
3094 || (in_range = 1, *str++ == '-'));
3101 inst.error = _("Missing `}'");
3109 if (my_get_expression (&expr, &str))
3112 if (expr.X_op == O_constant)
3114 if (expr.X_add_number
3115 != (expr.X_add_number & 0x0000ffff))
3117 inst.error = _("invalid register mask");
3121 if ((range & expr.X_add_number) != 0)
3123 int regno = range & expr.X_add_number;
3126 regno = (1 << regno) - 1;
3128 (_("Warning: Duplicated register (r%d) in register list"),
3132 range |= expr.X_add_number;
3136 if (inst.reloc.type != 0)
3138 inst.error = _("expression too complex");
3142 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3143 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3144 inst.reloc.pc_rel = 0;
3151 if (*str == '|' || *str == '+')
3156 } while (another_range);
3163 do_ldmstm (str, flags)
3165 unsigned long flags;
3173 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3176 if (base_reg == REG_PC)
3178 inst.error = _("r15 not allowed as base register");
3186 flags |= WRITE_BACK;
3190 if (skip_past_comma (&str) == FAIL
3191 || (range = reg_list (&str)) == FAIL)
3194 inst.error = bad_args;
3201 flags |= MULTI_SET_PSR;
3204 inst.instruction |= flags | range;
3212 unsigned long flags;
3217 /* Allow optional leading '#'. */
3218 if (is_immediate_prefix (*str))
3221 if (my_get_expression (& inst.reloc.exp, & str))
3224 inst.reloc.type = BFD_RELOC_ARM_SWI;
3225 inst.reloc.pc_rel = 0;
3226 inst.instruction |= flags;
3234 do_swap (str, flags)
3236 unsigned long flags;
3243 if ((reg = reg_required_here (&str, 12)) == FAIL)
3248 inst.error = _("r15 not allowed in swap");
3252 if (skip_past_comma (&str) == FAIL
3253 || (reg = reg_required_here (&str, 0)) == FAIL)
3256 inst.error = bad_args;
3262 inst.error = _("r15 not allowed in swap");
3266 if (skip_past_comma (&str) == FAIL
3269 inst.error = bad_args;
3276 if ((reg = reg_required_here (&str, 16)) == FAIL)
3281 inst.error = bad_pc;
3290 inst.error = _("missing ]");
3294 inst.instruction |= flags;
3300 do_branch (str, flags)
3302 unsigned long flags;
3304 if (my_get_expression (&inst.reloc.exp, &str))
3311 /* ScottB: February 5, 1998 */
3312 /* Check to see of PLT32 reloc required for the instruction. */
3314 /* arm_parse_reloc() works on input_line_pointer.
3315 We actually want to parse the operands to the branch instruction
3316 passed in 'str'. Save the input pointer and restore it later. */
3317 save_in = input_line_pointer;
3318 input_line_pointer = str;
3319 if (inst.reloc.exp.X_op == O_symbol
3321 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3323 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3324 inst.reloc.pc_rel = 0;
3325 /* Modify str to point to after parsed operands, otherwise
3326 end_of_line() will complain about the (PLT) left in str. */
3327 str = input_line_pointer;
3331 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3332 inst.reloc.pc_rel = 1;
3334 input_line_pointer = save_in;
3337 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3338 inst.reloc.pc_rel = 1;
3339 #endif /* OBJ_ELF */
3348 unsigned long flags;
3355 if ((reg = reg_required_here (&str, 0)) == FAIL)
3359 as_tsktsk (_("Use of r15 in bx has undefined behaviour"));
3368 unsigned long flags;
3370 /* Co-processor data operation.
3371 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3375 if (co_proc_number (&str) == FAIL)
3378 inst.error = bad_args;
3382 if (skip_past_comma (&str) == FAIL
3383 || cp_opc_expr (&str, 20,4) == FAIL)
3386 inst.error = bad_args;
3390 if (skip_past_comma (&str) == FAIL
3391 || cp_reg_required_here (&str, 12) == FAIL)
3394 inst.error = bad_args;
3398 if (skip_past_comma (&str) == FAIL
3399 || cp_reg_required_here (&str, 16) == FAIL)
3402 inst.error = bad_args;
3406 if (skip_past_comma (&str) == FAIL
3407 || cp_reg_required_here (&str, 0) == FAIL)
3410 inst.error = bad_args;
3414 if (skip_past_comma (&str) == SUCCESS)
3416 if (cp_opc_expr (&str, 5, 3) == FAIL)
3419 inst.error = bad_args;
3429 do_lstc (str, flags)
3431 unsigned long flags;
3433 /* Co-processor register load/store.
3434 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3439 if (co_proc_number (&str) == FAIL)
3442 inst.error = bad_args;
3446 if (skip_past_comma (&str) == FAIL
3447 || cp_reg_required_here (&str, 12) == FAIL)
3450 inst.error = bad_args;
3454 if (skip_past_comma (&str) == FAIL
3455 || cp_address_required_here (&str) == FAIL)
3458 inst.error = bad_args;
3462 inst.instruction |= flags;
3468 do_co_reg (str, flags)
3470 unsigned long flags;
3472 /* Co-processor register transfer.
3473 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3478 if (co_proc_number (&str) == FAIL)
3481 inst.error = bad_args;
3485 if (skip_past_comma (&str) == FAIL
3486 || cp_opc_expr (&str, 21, 3) == FAIL)
3489 inst.error = bad_args;
3493 if (skip_past_comma (&str) == FAIL
3494 || reg_required_here (&str, 12) == FAIL)
3497 inst.error = bad_args;
3501 if (skip_past_comma (&str) == FAIL
3502 || cp_reg_required_here (&str, 16) == FAIL)
3505 inst.error = bad_args;
3509 if (skip_past_comma (&str) == FAIL
3510 || cp_reg_required_here (&str, 0) == FAIL)
3513 inst.error = bad_args;
3517 if (skip_past_comma (&str) == SUCCESS)
3519 if (cp_opc_expr (&str, 5, 3) == FAIL)
3522 inst.error = bad_args;
3532 do_fp_ctrl (str, flags)
3534 unsigned long flags;
3536 /* FP control registers.
3537 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3542 if (reg_required_here (&str, 12) == FAIL)
3545 inst.error = bad_args;
3554 do_fp_ldst (str, flags)
3556 unsigned long flags;
3561 switch (inst.suffix)
3566 inst.instruction |= CP_T_X;
3569 inst.instruction |= CP_T_Y;
3572 inst.instruction |= CP_T_X | CP_T_Y;
3578 if (fp_reg_required_here (&str, 12) == FAIL)
3581 inst.error = bad_args;
3585 if (skip_past_comma (&str) == FAIL
3586 || cp_address_required_here (&str) == FAIL)
3589 inst.error = bad_args;
3597 do_fp_ldmstm (str, flags)
3599 unsigned long flags;
3606 if (fp_reg_required_here (&str, 12) == FAIL)
3609 inst.error = bad_args;
3613 /* Get Number of registers to transfer */
3614 if (skip_past_comma (&str) == FAIL
3615 || my_get_expression (&inst.reloc.exp, &str))
3618 inst.error = _("constant expression expected");
3622 if (inst.reloc.exp.X_op != O_constant)
3624 inst.error = _("Constant value required for number of registers");
3628 num_regs = inst.reloc.exp.X_add_number;
3630 if (num_regs < 1 || num_regs > 4)
3632 inst.error = _("number of registers must be in the range [1:4]");
3639 inst.instruction |= CP_T_X;
3642 inst.instruction |= CP_T_Y;
3645 inst.instruction |= CP_T_Y | CP_T_X;
3659 /* The instruction specified "ea" or "fd", so we can only accept
3660 [Rn]{!}. The instruction does not really support stacking or
3661 unstacking, so we have to emulate these by setting appropriate
3662 bits and offsets. */
3663 if (skip_past_comma (&str) == FAIL
3667 inst.error = bad_args;
3675 if ((reg = reg_required_here (&str, 16)) == FAIL)
3683 inst.error = bad_args;
3694 inst.error = _("R15 not allowed as base register with write-back");
3701 if (flags & CP_T_Pre)
3704 offset = 3 * num_regs;
3710 /* Post-increment */
3714 offset = 3 * num_regs;
3718 /* No write-back, so convert this into a standard pre-increment
3719 instruction -- aesthetically more pleasing. */
3720 flags = CP_T_Pre | CP_T_UD;
3725 inst.instruction |= flags | offset;
3727 else if (skip_past_comma (&str) == FAIL
3728 || cp_address_required_here (&str) == FAIL)
3731 inst.error = bad_args;
3739 do_fp_dyadic (str, flags)
3741 unsigned long flags;
3746 switch (inst.suffix)
3751 inst.instruction |= 0x00000080;
3754 inst.instruction |= 0x00080000;
3760 if (fp_reg_required_here (&str, 12) == FAIL)
3763 inst.error = bad_args;
3767 if (skip_past_comma (&str) == FAIL
3768 || fp_reg_required_here (&str, 16) == FAIL)
3771 inst.error = bad_args;
3775 if (skip_past_comma (&str) == FAIL
3776 || fp_op2 (&str) == FAIL)
3779 inst.error = bad_args;
3783 inst.instruction |= flags;
3789 do_fp_monadic (str, flags)
3791 unsigned long flags;
3796 switch (inst.suffix)
3801 inst.instruction |= 0x00000080;
3804 inst.instruction |= 0x00080000;
3810 if (fp_reg_required_here (&str, 12) == FAIL)
3813 inst.error = bad_args;
3817 if (skip_past_comma (&str) == FAIL
3818 || fp_op2 (&str) == FAIL)
3821 inst.error = bad_args;
3825 inst.instruction |= flags;
3831 do_fp_cmp (str, flags)
3833 unsigned long flags;
3838 if (fp_reg_required_here (&str, 16) == FAIL)
3841 inst.error = bad_args;
3845 if (skip_past_comma (&str) == FAIL
3846 || fp_op2 (&str) == FAIL)
3849 inst.error = bad_args;
3853 inst.instruction |= flags;
3859 do_fp_from_reg (str, flags)
3861 unsigned long flags;
3866 switch (inst.suffix)
3871 inst.instruction |= 0x00000080;
3874 inst.instruction |= 0x00080000;
3880 if (fp_reg_required_here (&str, 16) == FAIL)
3883 inst.error = bad_args;
3887 if (skip_past_comma (&str) == FAIL
3888 || reg_required_here (&str, 12) == FAIL)
3891 inst.error = bad_args;
3895 inst.instruction |= flags;
3901 do_fp_to_reg (str, flags)
3903 unsigned long flags;
3908 if (reg_required_here (&str, 12) == FAIL)
3911 if (skip_past_comma (&str) == FAIL
3912 || fp_reg_required_here (&str, 0) == FAIL)
3915 inst.error = bad_args;
3919 inst.instruction |= flags;
3924 /* Thumb specific routines */
3926 /* Parse and validate that a register is of the right form, this saves
3927 repeated checking of this information in many similar cases.
3928 Unlike the 32-bit case we do not insert the register into the opcode
3929 here, since the position is often unknown until the full instruction
3932 thumb_reg (strp, hi_lo)
3938 if ((reg = reg_required_here (strp, -1)) == FAIL)
3946 inst.error = _("lo register required");
3954 inst.error = _("hi register required");
3966 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3969 thumb_add_sub (str, subtract)
3973 int Rd, Rs, Rn = FAIL;
3978 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3979 || skip_past_comma (&str) == FAIL)
3982 inst.error = bad_args;
3986 if (is_immediate_prefix (*str))
3990 if (my_get_expression (&inst.reloc.exp, &str))
3995 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3998 if (skip_past_comma (&str) == FAIL)
4000 /* Two operand format, shuffle the registers and pretend there
4005 else if (is_immediate_prefix (*str))
4008 if (my_get_expression (&inst.reloc.exp, &str))
4011 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4015 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4016 for the latter case, EXPR contains the immediate that was found. */
4019 /* All register format. */
4020 if (Rd > 7 || Rs > 7 || Rn > 7)
4024 inst.error = _("dest and source1 must be the same register");
4028 /* Can't do this for SUB */
4031 inst.error = _("subtract valid only on lo regs");
4035 inst.instruction = (T_OPCODE_ADD_HI
4036 | (Rd > 7 ? THUMB_H1 : 0)
4037 | (Rn > 7 ? THUMB_H2 : 0));
4038 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4042 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4043 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4048 /* Immediate expression, now things start to get nasty. */
4050 /* First deal with HI regs, only very restricted cases allowed:
4051 Adjusting SP, and using PC or SP to get an address. */
4052 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4053 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4055 inst.error = _("invalid Hi register with immediate");
4059 if (inst.reloc.exp.X_op != O_constant)
4061 /* Value isn't known yet, all we can do is store all the fragments
4062 we know about in the instruction and let the reloc hacking
4064 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4065 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4069 int offset = inst.reloc.exp.X_add_number;
4079 /* Quick check, in case offset is MIN_INT */
4082 inst.error = _("immediate value out of range");
4091 if (offset & ~0x1fc)
4093 inst.error = _("invalid immediate value for stack adjust");
4096 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4097 inst.instruction |= offset >> 2;
4099 else if (Rs == REG_PC || Rs == REG_SP)
4102 || (offset & ~0x3fc))
4104 inst.error = _("invalid immediate for address calculation");
4107 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4109 inst.instruction |= (Rd << 8) | (offset >> 2);
4115 inst.error = _("immediate value out of range");
4118 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4119 inst.instruction |= (Rd << 8) | offset;
4125 inst.error = _("immediate value out of range");
4128 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4129 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4137 thumb_shift (str, shift)
4141 int Rd, Rs, Rn = FAIL;
4146 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4147 || skip_past_comma (&str) == FAIL)
4150 inst.error = bad_args;
4154 if (is_immediate_prefix (*str))
4156 /* Two operand immediate format, set Rs to Rd. */
4159 if (my_get_expression (&inst.reloc.exp, &str))
4164 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4167 if (skip_past_comma (&str) == FAIL)
4169 /* Two operand format, shuffle the registers and pretend there
4174 else if (is_immediate_prefix (*str))
4177 if (my_get_expression (&inst.reloc.exp, &str))
4180 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4184 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4185 for the latter case, EXPR contains the immediate that was found. */
4191 inst.error = _("source1 and dest must be same register");
4197 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4198 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4199 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4202 inst.instruction |= Rd | (Rn << 3);
4208 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4209 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4210 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4213 if (inst.reloc.exp.X_op != O_constant)
4215 /* Value isn't known yet, create a dummy reloc and let reloc
4216 hacking fix it up */
4218 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4222 unsigned shift_value = inst.reloc.exp.X_add_number;
4224 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4226 inst.error = _("Invalid immediate for shift");
4230 /* Shifts of zero are handled by converting to LSL */
4231 if (shift_value == 0)
4232 inst.instruction = T_OPCODE_LSL_I;
4234 /* Shifts of 32 are encoded as a shift of zero */
4235 if (shift_value == 32)
4238 inst.instruction |= shift_value << 6;
4241 inst.instruction |= Rd | (Rs << 3);
4247 thumb_mov_compare (str, move)
4256 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4257 || skip_past_comma (&str) == FAIL)
4260 inst.error = bad_args;
4264 if (is_immediate_prefix (*str))
4267 if (my_get_expression (&inst.reloc.exp, &str))
4270 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4275 if (Rs < 8 && Rd < 8)
4277 if (move == THUMB_MOVE)
4278 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4279 since a MOV instruction produces unpredictable results */
4280 inst.instruction = T_OPCODE_ADD_I3;
4282 inst.instruction = T_OPCODE_CMP_LR;
4283 inst.instruction |= Rd | (Rs << 3);
4287 if (move == THUMB_MOVE)
4288 inst.instruction = T_OPCODE_MOV_HR;
4290 inst.instruction = T_OPCODE_CMP_HR;
4293 inst.instruction |= THUMB_H1;
4296 inst.instruction |= THUMB_H2;
4298 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4305 inst.error = _("only lo regs allowed with immediate");
4309 if (move == THUMB_MOVE)
4310 inst.instruction = T_OPCODE_MOV_I8;
4312 inst.instruction = T_OPCODE_CMP_I8;
4314 inst.instruction |= Rd << 8;
4316 if (inst.reloc.exp.X_op != O_constant)
4317 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4320 unsigned value = inst.reloc.exp.X_add_number;
4324 inst.error = _("invalid immediate");
4328 inst.instruction |= value;
4336 thumb_load_store (str, load_store, size)
4341 int Rd, Rb, Ro = FAIL;
4346 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4347 || skip_past_comma (&str) == FAIL)
4350 inst.error = bad_args;
4357 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4360 if (skip_past_comma (&str) != FAIL)
4362 if (is_immediate_prefix (*str))
4365 if (my_get_expression (&inst.reloc.exp, &str))
4368 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4373 inst.reloc.exp.X_op = O_constant;
4374 inst.reloc.exp.X_add_number = 0;
4379 inst.error = _("expected ']'");
4384 else if (*str == '=')
4386 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4392 if (my_get_expression (& inst.reloc.exp, & str))
4397 if ( inst.reloc.exp.X_op != O_constant
4398 && inst.reloc.exp.X_op != O_symbol)
4400 inst.error = "Constant expression expected";
4404 if (inst.reloc.exp.X_op == O_constant
4405 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4407 /* This can be done with a mov instruction */
4409 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4410 inst.instruction |= inst.reloc.exp.X_add_number;
4414 /* Insert into literal pool */
4415 if (add_to_lit_pool () == FAIL)
4418 inst.error = "literal pool insertion failed";
4422 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4423 inst.reloc.pc_rel = 1;
4424 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4425 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4431 if (my_get_expression (&inst.reloc.exp, &str))
4434 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4435 inst.reloc.pc_rel = 1;
4436 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4437 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4442 if (Rb == REG_PC || Rb == REG_SP)
4444 if (size != THUMB_WORD)
4446 inst.error = _("byte or halfword not valid for base register");
4449 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4451 inst.error = _("R15 based store not allowed");
4454 else if (Ro != FAIL)
4456 inst.error = _("Invalid base register for register offset");
4461 inst.instruction = T_OPCODE_LDR_PC;
4462 else if (load_store == THUMB_LOAD)
4463 inst.instruction = T_OPCODE_LDR_SP;
4465 inst.instruction = T_OPCODE_STR_SP;
4467 inst.instruction |= Rd << 8;
4468 if (inst.reloc.exp.X_op == O_constant)
4470 unsigned offset = inst.reloc.exp.X_add_number;
4472 if (offset & ~0x3fc)
4474 inst.error = _("invalid offset");
4478 inst.instruction |= offset >> 2;
4481 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4485 inst.error = _("invalid base register in load/store");
4488 else if (Ro == FAIL)
4490 /* Immediate offset */
4491 if (size == THUMB_WORD)
4492 inst.instruction = (load_store == THUMB_LOAD
4493 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4494 else if (size == THUMB_HALFWORD)
4495 inst.instruction = (load_store == THUMB_LOAD
4496 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4498 inst.instruction = (load_store == THUMB_LOAD
4499 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4501 inst.instruction |= Rd | (Rb << 3);
4503 if (inst.reloc.exp.X_op == O_constant)
4505 unsigned offset = inst.reloc.exp.X_add_number;
4507 if (offset & ~(0x1f << size))
4509 inst.error = _("Invalid offset");
4512 inst.instruction |= (offset >> size) << 6;
4515 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4519 /* Register offset */
4520 if (size == THUMB_WORD)
4521 inst.instruction = (load_store == THUMB_LOAD
4522 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4523 else if (size == THUMB_HALFWORD)
4524 inst.instruction = (load_store == THUMB_LOAD
4525 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4527 inst.instruction = (load_store == THUMB_LOAD
4528 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4530 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4545 /* Handle the Format 4 instructions that do not have equivalents in other
4546 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4557 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4560 if (skip_past_comma (&str) == FAIL
4561 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4564 inst.error = bad_args;
4568 if (skip_past_comma (&str) != FAIL)
4570 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4571 (It isn't allowed for CMP either, but that isn't handled by this
4573 if (inst.instruction == T_OPCODE_TST
4574 || inst.instruction == T_OPCODE_CMN
4575 || inst.instruction == T_OPCODE_NEG
4576 || inst.instruction == T_OPCODE_MVN)
4578 inst.error = bad_args;
4582 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4587 inst.error = _("dest and source1 one must be the same register");
4593 if (inst.instruction == T_OPCODE_MUL
4595 as_tsktsk (_("Rs and Rd must be different in MUL"));
4597 inst.instruction |= Rd | (Rs << 3);
4605 thumb_add_sub (str, 0);
4612 thumb_shift (str, THUMB_ASR);
4619 if (my_get_expression (&inst.reloc.exp, &str))
4621 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4622 inst.reloc.pc_rel = 1;
4630 if (my_get_expression (&inst.reloc.exp, &str))
4632 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4633 inst.reloc.pc_rel = 1;
4637 /* Find the real, Thumb encoded start of a Thumb function. */
4640 find_real_start (symbolP)
4644 const char * name = S_GET_NAME (symbolP);
4645 symbolS * new_target;
4647 /* This definitonmust agree with the one in gcc/config/arm/thumb.c */
4648 #define STUB_NAME ".real_start_of"
4653 /* Names that start with '.' are local labels, not function entry points.
4654 The compiler may generate BL instructions to these labels because it
4655 needs to perform a branch to a far away location. */
4659 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4660 sprintf (real_start, "%s%s", STUB_NAME, name);
4662 new_target = symbol_find (real_start);
4664 if (new_target == NULL)
4666 as_warn ("Failed to find real start of function: %s\n", name);
4667 new_target = symbolP;
4680 if (my_get_expression (&inst.reloc.exp, &str))
4682 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4683 inst.reloc.pc_rel = 1;
4686 /* If the destination of the branch is a defined symbol which does not have
4687 the THUMB_FUNC attribute, then we must be calling a function which has
4688 the (interfacearm) attribute. We look for the Thumb entry point to that
4689 function and change the branch to refer to that function instead. */
4690 if ( inst.reloc.exp.X_op == O_symbol
4691 && inst.reloc.exp.X_add_symbol != NULL
4692 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4693 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4694 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4706 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4709 /* This sets THUMB_H2 from the top bit of reg. */
4710 inst.instruction |= reg << 3;
4712 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4713 should cause the alignment to be checked once it is known. This is
4714 because BX PC only works if the instruction is word aligned. */
4723 thumb_mov_compare (str, THUMB_COMPARE);
4736 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4740 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4744 if (skip_past_comma (&str) == FAIL
4745 || (range = reg_list (&str)) == FAIL)
4748 inst.error = bad_args;
4752 if (inst.reloc.type != BFD_RELOC_NONE)
4754 /* This really doesn't seem worth it. */
4755 inst.reloc.type = BFD_RELOC_NONE;
4756 inst.error = _("Expression too complex");
4762 inst.error = _("only lo-regs valid in load/store multiple");
4766 inst.instruction |= (Rb << 8) | range;
4774 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4781 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4788 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4800 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4801 || skip_past_comma (&str) == FAIL
4803 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4804 || skip_past_comma (&str) == FAIL
4805 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4809 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4813 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4821 thumb_shift (str, THUMB_LSL);
4828 thumb_shift (str, THUMB_LSR);
4835 thumb_mov_compare (str, THUMB_MOVE);
4847 if ((range = reg_list (&str)) == FAIL)
4850 inst.error = bad_args;
4854 if (inst.reloc.type != BFD_RELOC_NONE)
4856 /* This really doesn't seem worth it. */
4857 inst.reloc.type = BFD_RELOC_NONE;
4858 inst.error = _("Expression too complex");
4864 if ((inst.instruction == T_OPCODE_PUSH
4865 && (range & ~0xff) == 1 << REG_LR)
4866 || (inst.instruction == T_OPCODE_POP
4867 && (range & ~0xff) == 1 << REG_PC))
4869 inst.instruction |= THUMB_PP_PC_LR;
4874 inst.error = _("invalid register list to push/pop instruction");
4879 inst.instruction |= range;
4887 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4894 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4901 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4908 thumb_add_sub (str, 1);
4918 if (my_get_expression (&inst.reloc.exp, &str))
4921 inst.reloc.type = BFD_RELOC_ARM_SWI;
4930 /* This is a pseudo-op of the form "adr rd, label" to be converted
4931 into a relative address of the form "add rd, pc, #label-.-4" */
4935 if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
4936 || skip_past_comma (&str) == FAIL
4937 || my_get_expression (&inst.reloc.exp, &str))
4940 inst.error = bad_args;
4944 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4945 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust */
4946 inst.reloc.pc_rel = 1;
4947 inst.instruction |= REG_PC; /* Rd is already placed into the instruction */
4955 int len = strlen (reg_table[entry].name) + 2;
4956 char * buf = (char *) xmalloc (len);
4957 char * buf2 = (char *) xmalloc (len);
4960 #ifdef REGISTER_PREFIX
4961 buf[i++] = REGISTER_PREFIX;
4964 strcpy (buf + i, reg_table[entry].name);
4966 for (i = 0; buf[i]; i++)
4967 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4971 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4972 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4976 insert_reg_alias (str, regnum)
4980 struct reg_entry *new =
4981 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4982 char *name = xmalloc (strlen (str) + 1);
4986 new->number = regnum;
4988 hash_insert (arm_reg_hsh, name, (PTR) new);
4992 set_constant_flonums ()
4996 for (i = 0; i < NUM_FLOAT_VALS; i++)
4997 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
5006 if ( (arm_ops_hsh = hash_new ()) == NULL
5007 || (arm_tops_hsh = hash_new ()) == NULL
5008 || (arm_cond_hsh = hash_new ()) == NULL
5009 || (arm_shift_hsh = hash_new ()) == NULL
5010 || (arm_reg_hsh = hash_new ()) == NULL
5011 || (arm_psr_hsh = hash_new ()) == NULL)
5012 as_fatal (_("Virtual memory exhausted"));
5014 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5015 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5016 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5017 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5018 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5019 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5020 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5021 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5022 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5023 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5025 for (i = 0; reg_table[i].name; i++)
5028 set_constant_flonums ();
5030 #if defined OBJ_COFF || defined OBJ_ELF
5032 unsigned int flags = 0;
5034 /* Set the flags in the private structure */
5035 if (uses_apcs_26) flags |= F_APCS26;
5036 if (support_interwork) flags |= F_INTERWORK;
5037 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5038 if (pic_code) flags |= F_PIC;
5040 bfd_set_private_flags (stdoutput, flags);
5047 /* Record the CPU type as well */
5048 switch (cpu_variant & ARM_CPU_MASK)
5051 mach = bfd_mach_arm_2;
5054 case ARM_3: /* also ARM_250 */
5055 mach = bfd_mach_arm_2a;
5059 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined */
5060 mach = bfd_mach_arm_4;
5063 case ARM_7: /* also ARM_6 */
5064 mach = bfd_mach_arm_3;
5068 /* Catch special cases */
5069 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5071 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5072 mach = bfd_mach_arm_5T;
5073 else if (cpu_variant & ARM_EXT_V5)
5074 mach = bfd_mach_arm_5;
5075 else if (cpu_variant & ARM_THUMB)
5076 mach = bfd_mach_arm_4T;
5077 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5078 mach = bfd_mach_arm_4;
5079 else if (cpu_variant & ARM_LONGMUL)
5080 mach = bfd_mach_arm_3M;
5083 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5087 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5088 for use in the a.out file, and stores them in the array pointed to by buf.
5089 This knows about the endian-ness of the target machine and does
5090 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5091 2 (short) and 4 (long) Floating numbers are put out as a series of
5092 LITTLENUMS (shorts, here at least)
5095 md_number_to_chars (buf, val, n)
5100 if (target_big_endian)
5101 number_to_chars_bigendian (buf, val, n);
5103 number_to_chars_littleendian (buf, val, n);
5107 md_chars_to_number (buf, n)
5112 unsigned char * where = (unsigned char *) buf;
5114 if (target_big_endian)
5119 result |= (*where++ & 255);
5127 result |= (where[n] & 255);
5134 /* Turn a string in input_line_pointer into a floating point constant
5135 of type TYPE, and store the appropriate bytes in *litP. The number
5136 of LITTLENUMS emitted is stored in *sizeP . An error message is
5137 returned, or NULL on OK.
5139 Note that fp constants aren't represent in the normal way on the ARM.
5140 In big endian mode, things are as expected. However, in little endian
5141 mode fp constants are big-endian word-wise, and little-endian byte-wise
5142 within the words. For example, (double) 1.1 in big endian mode is
5143 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5144 the byte sequence 99 99 f1 3f 9a 99 99 99.
5146 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5149 md_atof (type, litP, sizeP)
5155 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5187 return _("Bad call to MD_ATOF()");
5190 t = atof_ieee (input_line_pointer, type, words);
5192 input_line_pointer = t;
5195 if (target_big_endian)
5197 for (i = 0; i < prec; i++)
5199 md_number_to_chars (litP, (valueT) words[i], 2);
5205 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5206 8 byte float the order is 1 0 3 2. */
5207 for (i = 0; i < prec; i += 2)
5209 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5210 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5218 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5220 md_pcrel_from (fixP)
5224 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5225 && fixP->fx_subsy == NULL)
5228 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5230 /* PC relative addressing on the Thumb is slightly odd
5231 as the bottom two bits of the PC are forced to zero
5232 for the calculation */
5233 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5236 return fixP->fx_where + fixP->fx_frag->fr_address;
5239 /* Round up a section size to the appropriate boundary. */
5241 md_section_align (segment, size)
5246 /* Don't align the dwarf2 debug sections */
5247 if (!strncmp (segment->name, ".debug", 5))
5250 /* Round all sects to multiple of 4 */
5251 return (size + 3) & ~3;
5254 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5255 we have no need to default values of symbols. */
5259 md_undefined_symbol (name)
5263 if (name[0] == '_' && name[1] == 'G'
5264 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5268 if (symbol_find (name))
5269 as_bad ("GOT already in the symbol table");
5271 GOT_symbol = symbol_new (name, undefined_section,
5272 (valueT)0, & zero_address_frag);
5282 /* arm_reg_parse () := if it looks like a register, return its token and
5283 advance the pointer. */
5287 register char ** ccp;
5289 char * start = * ccp;
5292 struct reg_entry * reg;
5294 #ifdef REGISTER_PREFIX
5295 if (*start != REGISTER_PREFIX)
5300 #ifdef OPTIONAL_REGISTER_PREFIX
5301 if (*p == OPTIONAL_REGISTER_PREFIX)
5305 if (!isalpha (*p) || !is_name_beginner (*p))
5309 while (isalpha (c) || isdigit (c) || c == '_')
5313 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5327 register char ** ccp;
5329 char * start = * ccp;
5332 CONST struct asm_psr * psr;
5336 while (isalpha (c) || c == '_')
5340 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5353 md_apply_fix3 (fixP, val, seg)
5358 offsetT value = * val;
5360 unsigned int newimm;
5363 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5364 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5366 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5368 /* Note whether this will delete the relocation. */
5369 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5370 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5373 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5377 /* If this symbol is in a different section then we need to leave it for
5378 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5379 so we have to undo it's effects here. */
5382 if (fixP->fx_addsy != NULL
5383 && S_IS_DEFINED (fixP->fx_addsy)
5384 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5387 && fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
5390 value += md_pcrel_from (fixP);
5394 fixP->fx_addnumber = value; /* Remember value for emit_reloc */
5396 switch (fixP->fx_r_type)
5398 case BFD_RELOC_ARM_IMMEDIATE:
5399 newimm = validate_immediate (value);
5400 temp = md_chars_to_number (buf, INSN_SIZE);
5402 /* If the instruction will fail, see if we can fix things up by
5403 changing the opcode. */
5404 if (newimm == (unsigned int) FAIL
5405 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5407 as_bad_where (fixP->fx_file, fixP->fx_line,
5408 _("invalid constant (%lx) after fixup\n"),
5409 (unsigned long) value);
5413 newimm |= (temp & 0xfffff000);
5414 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5417 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5419 unsigned int highpart = 0;
5420 unsigned int newinsn = 0xe1a00000; /* nop */
5421 newimm = validate_immediate (value);
5422 temp = md_chars_to_number (buf, INSN_SIZE);
5424 /* If the instruction will fail, see if we can fix things up by
5425 changing the opcode. */
5426 if (newimm == (unsigned int) FAIL
5427 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5429 /* No ? OK - try using two ADD instructions to generate the value. */
5430 newimm = validate_immediate_twopart (value, & highpart);
5432 /* Yes - then make sure that the second instruction is also an add. */
5433 if (newimm != (unsigned int) FAIL)
5435 /* Still No ? Try using a negated value. */
5436 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5437 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5438 /* Otherwise - give up. */
5441 as_bad_where (fixP->fx_file, fixP->fx_line,
5442 _("Unable to compute ADRL instructions for PC offset of 0x%x\n"), value);
5446 /* Replace the first operand in the 2nd instruction (which is the PC)
5447 with the destination register. We have already added in the PC in the
5448 first instruction and we do not want to do it again. */
5449 newinsn &= ~ 0xf0000;
5450 newinsn |= ((newinsn & 0x0f000) << 4);
5453 newimm |= (temp & 0xfffff000);
5454 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5456 highpart |= (newinsn & 0xfffff000);
5457 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5461 case BFD_RELOC_ARM_OFFSET_IMM:
5463 if ((value = validate_offset_imm (value, 0)) == FAIL)
5465 as_bad (_("bad immediate value for offset (%ld)"), (long) value);
5471 newval = md_chars_to_number (buf, INSN_SIZE);
5472 newval &= 0xff7ff000;
5473 newval |= value | (sign ? INDEX_UP : 0);
5474 md_number_to_chars (buf, newval, INSN_SIZE);
5477 case BFD_RELOC_ARM_OFFSET_IMM8:
5478 case BFD_RELOC_ARM_HWLITERAL:
5480 if ((value = validate_offset_imm (value, 1)) == FAIL)
5482 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5483 as_bad_where (fixP->fx_file, fixP->fx_line,
5484 _("invalid literal constant: pool needs to be closer\n"));
5486 as_bad (_("bad immediate value for offset (%ld)"), (long) value);
5493 newval = md_chars_to_number (buf, INSN_SIZE);
5494 newval &= 0xff7ff0f0;
5495 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5496 md_number_to_chars (buf, newval, INSN_SIZE);
5499 case BFD_RELOC_ARM_LITERAL:
5504 if ((value = validate_offset_imm (value, 0)) == FAIL)
5506 as_bad_where (fixP->fx_file, fixP->fx_line,
5507 _("invalid literal constant: pool needs to be closer\n"));
5511 newval = md_chars_to_number (buf, INSN_SIZE);
5512 newval &= 0xff7ff000;
5513 newval |= value | (sign ? INDEX_UP : 0);
5514 md_number_to_chars (buf, newval, INSN_SIZE);
5517 case BFD_RELOC_ARM_SHIFT_IMM:
5518 newval = md_chars_to_number (buf, INSN_SIZE);
5519 if (((unsigned long) value) > 32
5521 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5523 as_bad_where (fixP->fx_file, fixP->fx_line,
5524 _("shift expression is too large"));
5529 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5530 else if (value == 32)
5532 newval &= 0xfffff07f;
5533 newval |= (value & 0x1f) << 7;
5534 md_number_to_chars (buf, newval , INSN_SIZE);
5537 case BFD_RELOC_ARM_SWI:
5538 if (arm_data->thumb_mode)
5540 if (((unsigned long) value) > 0xff)
5541 as_bad_where (fixP->fx_file, fixP->fx_line,
5542 _("Invalid swi expression"));
5543 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5545 md_number_to_chars (buf, newval, THUMB_SIZE);
5549 if (((unsigned long) value) > 0x00ffffff)
5550 as_bad_where (fixP->fx_file, fixP->fx_line,
5551 _("Invalid swi expression"));
5552 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5554 md_number_to_chars (buf, newval , INSN_SIZE);
5558 case BFD_RELOC_ARM_MULTI:
5559 if (((unsigned long) value) > 0xffff)
5560 as_bad_where (fixP->fx_file, fixP->fx_line,
5561 _("Invalid expression in load/store multiple"));
5562 newval = value | md_chars_to_number (buf, INSN_SIZE);
5563 md_number_to_chars (buf, newval, INSN_SIZE);
5566 case BFD_RELOC_ARM_PCREL_BRANCH:
5567 newval = md_chars_to_number (buf, INSN_SIZE);
5571 value = fixP->fx_offset;
5573 value = (value >> 2) & 0x00ffffff;
5574 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5575 newval = value | (newval & 0xff000000);
5576 md_number_to_chars (buf, newval, INSN_SIZE);
5579 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5580 newval = md_chars_to_number (buf, THUMB_SIZE);
5582 addressT diff = (newval & 0xff) << 1;
5587 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5588 as_bad_where (fixP->fx_file, fixP->fx_line,
5589 _("Branch out of range"));
5590 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5592 md_number_to_chars (buf, newval, THUMB_SIZE);
5595 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5596 newval = md_chars_to_number (buf, THUMB_SIZE);
5598 addressT diff = (newval & 0x7ff) << 1;
5603 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5604 as_bad_where (fixP->fx_file, fixP->fx_line,
5605 _("Branch out of range"));
5606 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5608 md_number_to_chars (buf, newval, THUMB_SIZE);
5611 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5616 newval = md_chars_to_number (buf, THUMB_SIZE);
5617 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5618 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5619 if (diff & 0x400000)
5622 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5623 as_bad_where (fixP->fx_file, fixP->fx_line,
5624 _("Branch with link out of range"));
5626 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5627 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5628 md_number_to_chars (buf, newval, THUMB_SIZE);
5629 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5634 if (fixP->fx_done || fixP->fx_pcrel)
5635 md_number_to_chars (buf, value, 1);
5637 else if (!target_oabi)
5639 value = fixP->fx_offset;
5640 md_number_to_chars (buf, value, 1);
5646 if (fixP->fx_done || fixP->fx_pcrel)
5647 md_number_to_chars (buf, value, 2);
5649 else if (!target_oabi)
5651 value = fixP->fx_offset;
5652 md_number_to_chars (buf, value, 2);
5658 case BFD_RELOC_ARM_GOT32:
5659 case BFD_RELOC_ARM_GOTOFF:
5660 md_number_to_chars (buf, 0, 4);
5666 if (fixP->fx_done || fixP->fx_pcrel)
5667 md_number_to_chars (buf, value, 4);
5669 else if (!target_oabi)
5671 value = fixP->fx_offset;
5672 md_number_to_chars (buf, value, 4);
5678 case BFD_RELOC_ARM_PLT32:
5679 /* It appears the instruction is fully prepared at this point. */
5683 case BFD_RELOC_ARM_GOTPC:
5684 md_number_to_chars (buf, value, 4);
5687 case BFD_RELOC_ARM_CP_OFF_IMM:
5689 if (value < -1023 || value > 1023 || (value & 3))
5690 as_bad_where (fixP->fx_file, fixP->fx_line,
5691 _("Illegal value for co-processor offset"));
5694 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5695 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5696 md_number_to_chars (buf, newval , INSN_SIZE);
5699 case BFD_RELOC_ARM_THUMB_OFFSET:
5700 newval = md_chars_to_number (buf, THUMB_SIZE);
5701 /* Exactly what ranges, and where the offset is inserted depends on
5702 the type of instruction, we can establish this from the top 4 bits */
5703 switch (newval >> 12)
5705 case 4: /* PC load */
5706 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5707 forced to zero for these loads, so we will need to round
5708 up the offset if the instruction address is not word
5709 aligned (since the final address produced must be, and
5710 we can only describe word-aligned immediate offsets). */
5712 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5713 as_bad_where (fixP->fx_file, fixP->fx_line,
5714 _("Invalid offset, target not word aligned (0x%08X)"),
5715 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5717 if ((value + 2) & ~0x3fe)
5718 as_bad_where (fixP->fx_file, fixP->fx_line,
5719 _("Invalid offset"));
5721 /* Round up, since pc will be rounded down. */
5722 newval |= (value + 2) >> 2;
5725 case 9: /* SP load/store */
5727 as_bad_where (fixP->fx_file, fixP->fx_line,
5728 _("Invalid offset"));
5729 newval |= value >> 2;
5732 case 6: /* Word load/store */
5734 as_bad_where (fixP->fx_file, fixP->fx_line,
5735 _("Invalid offset"));
5736 newval |= value << 4; /* 6 - 2 */
5739 case 7: /* Byte load/store */
5741 as_bad_where (fixP->fx_file, fixP->fx_line,
5742 _("Invalid offset"));
5743 newval |= value << 6;
5746 case 8: /* Halfword load/store */
5748 as_bad_where (fixP->fx_file, fixP->fx_line,
5749 _("Invalid offset"));
5750 newval |= value << 5; /* 6 - 1 */
5754 as_bad_where (fixP->fx_file, fixP->fx_line,
5755 "Unable to process relocation for thumb opcode: %lx",
5756 (unsigned long) newval);
5759 md_number_to_chars (buf, newval, THUMB_SIZE);
5762 case BFD_RELOC_ARM_THUMB_ADD:
5763 /* This is a complicated relocation, since we use it for all of
5764 the following immediate relocations:
5767 9bit ADD/SUB SP word-aligned
5768 10bit ADD PC/SP word-aligned
5770 The type of instruction being processed is encoded in the
5776 newval = md_chars_to_number (buf, THUMB_SIZE);
5778 int rd = (newval >> 4) & 0xf;
5779 int rs = newval & 0xf;
5780 int subtract = newval & 0x8000;
5785 as_bad_where (fixP->fx_file, fixP->fx_line,
5786 _("Invalid immediate for stack address calculation"));
5787 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5788 newval |= value >> 2;
5790 else if (rs == REG_PC || rs == REG_SP)
5794 as_bad_where (fixP->fx_file, fixP->fx_line,
5795 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5796 (unsigned long) value);
5797 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5799 newval |= value >> 2;
5804 as_bad_where (fixP->fx_file, fixP->fx_line,
5805 _("Invalid 8bit immediate"));
5806 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5807 newval |= (rd << 8) | value;
5812 as_bad_where (fixP->fx_file, fixP->fx_line,
5813 _("Invalid 3bit immediate"));
5814 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5815 newval |= rd | (rs << 3) | (value << 6);
5818 md_number_to_chars (buf, newval , THUMB_SIZE);
5821 case BFD_RELOC_ARM_THUMB_IMM:
5822 newval = md_chars_to_number (buf, THUMB_SIZE);
5823 switch (newval >> 11)
5825 case 0x04: /* 8bit immediate MOV */
5826 case 0x05: /* 8bit immediate CMP */
5827 if (value < 0 || value > 255)
5828 as_bad_where (fixP->fx_file, fixP->fx_line,
5829 _("Invalid immediate: %ld is too large"),
5837 md_number_to_chars (buf, newval , THUMB_SIZE);
5840 case BFD_RELOC_ARM_THUMB_SHIFT:
5841 /* 5bit shift value (0..31) */
5842 if (value < 0 || value > 31)
5843 as_bad_where (fixP->fx_file, fixP->fx_line,
5844 _("Illegal Thumb shift value: %ld"), (long) value);
5845 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5846 newval |= value << 6;
5847 md_number_to_chars (buf, newval , THUMB_SIZE);
5850 case BFD_RELOC_VTABLE_INHERIT:
5851 case BFD_RELOC_VTABLE_ENTRY:
5855 case BFD_RELOC_NONE:
5857 as_bad_where (fixP->fx_file, fixP->fx_line,
5858 _("Bad relocation fixup type (%d)\n"), fixP->fx_r_type);
5864 /* Translate internal representation of relocation info to BFD target
5867 tc_gen_reloc (section, fixp)
5872 bfd_reloc_code_real_type code;
5874 reloc = (arelent *) xmalloc (sizeof (arelent));
5876 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5877 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5878 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5880 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5882 if (fixp->fx_pcrel == 0)
5883 reloc->addend = fixp->fx_offset;
5885 reloc->addend = fixp->fx_offset = reloc->address;
5887 reloc->addend = fixp->fx_offset;
5890 switch (fixp->fx_r_type)
5895 code = BFD_RELOC_8_PCREL;
5902 code = BFD_RELOC_16_PCREL;
5909 code = BFD_RELOC_32_PCREL;
5913 case BFD_RELOC_ARM_PCREL_BRANCH:
5915 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5916 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5917 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5918 case BFD_RELOC_VTABLE_ENTRY:
5919 case BFD_RELOC_VTABLE_INHERIT:
5920 code = fixp->fx_r_type;
5923 case BFD_RELOC_ARM_LITERAL:
5924 case BFD_RELOC_ARM_HWLITERAL:
5925 /* If this is called then the a literal has been referenced across
5926 a section boundry - possibly due to an implicit dump */
5927 as_bad_where (fixp->fx_file, fixp->fx_line,
5928 _("Literal referenced across section boundry (Implicit dump?)"));
5931 case BFD_RELOC_ARM_GOTPC:
5932 assert (fixp->fx_pcrel != 0);
5933 code = fixp->fx_r_type;
5934 code = BFD_RELOC_32_PCREL;
5938 case BFD_RELOC_ARM_GOT32:
5939 case BFD_RELOC_ARM_GOTOFF:
5940 case BFD_RELOC_ARM_PLT32:
5941 code = fixp->fx_r_type;
5945 case BFD_RELOC_ARM_IMMEDIATE:
5946 as_bad_where (fixp->fx_file, fixp->fx_line,
5947 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5951 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5952 as_bad_where (fixp->fx_file, fixp->fx_line,
5953 _("ADRL used for a symbol not defined in the same file"),
5957 case BFD_RELOC_ARM_OFFSET_IMM:
5958 as_bad_where (fixp->fx_file, fixp->fx_line,
5959 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
5966 switch (fixp->fx_r_type)
5968 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
5969 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
5970 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
5971 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
5972 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
5973 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
5974 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
5975 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
5976 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
5977 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
5978 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
5979 default: type = "<unknown>"; break;
5981 as_bad_where (fixp->fx_file, fixp->fx_line,
5982 _("Can not represent %s relocation in this object file format (%d)"),
5983 type, fixp->fx_pcrel);
5989 if (code == BFD_RELOC_32_PCREL
5991 && fixp->fx_addsy == GOT_symbol)
5993 code = BFD_RELOC_ARM_GOTPC;
5994 reloc->addend = fixp->fx_offset = reloc->address;
5998 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6000 if (reloc->howto == NULL)
6002 as_bad_where (fixp->fx_file, fixp->fx_line,
6003 _("Can not represent %s relocation in this object file format"),
6004 bfd_get_reloc_code_name (code));
6012 md_estimate_size_before_relax (fragP, segtype)
6016 as_fatal (_("md_estimate_size_before_relax\n"));
6021 output_inst PARAMS ((void))
6027 as_bad (inst.error);
6031 to = frag_more (inst.size);
6032 if (thumb_mode && (inst.size > THUMB_SIZE))
6034 assert (inst.size == (2 * THUMB_SIZE));
6035 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6036 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6038 else if (inst.size > INSN_SIZE)
6040 assert (inst.size == (2 * INSN_SIZE));
6041 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6042 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6045 md_number_to_chars (to, inst.instruction, inst.size);
6047 if (inst.reloc.type != BFD_RELOC_NONE)
6048 fix_new_arm (frag_now, to - frag_now->fr_literal,
6049 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6064 /* Align the instruction.
6065 This may not be the right thing to do but ... */
6066 /* arm_align (2, 0); */
6067 listing_prev_line (); /* Defined in listing.h */
6069 /* Align the previous label if needed. */
6070 if (last_label_seen != NULL)
6072 symbol_set_frag (last_label_seen, frag_now);
6073 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6074 S_SET_SEGMENT (last_label_seen, now_seg);
6077 memset (&inst, '\0', sizeof (inst));
6078 inst.reloc.type = BFD_RELOC_NONE;
6081 str++; /* Skip leading white space */
6083 /* Scan up to the end of the op-code, which must end in white space or
6085 for (start = p = str; *p != '\0'; p++)
6091 as_bad (_("No operator -- statement `%s'\n"), str);
6097 CONST struct thumb_opcode * opcode;
6101 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6106 inst.instruction = opcode->value;
6107 inst.size = opcode->size;
6108 (*opcode->parms)(p);
6115 CONST struct asm_opcode * opcode;
6117 inst.size = INSN_SIZE;
6118 /* p now points to the end of the opcode, probably white space, but we
6119 have to break the opcode up in case it contains condionals and flags;
6120 keep trying with progressively smaller basic instructions until one
6121 matches, or we run out of opcode. */
6122 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6123 for (; q != str; q--)
6127 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6130 if (opcode && opcode->template)
6132 unsigned long flag_bits = 0;
6135 /* Check that this instruction is supported for this CPU */
6136 if ((opcode->variants & cpu_variant) == 0)
6139 inst.instruction = opcode->value;
6140 if (q == p) /* Just a simple opcode */
6142 if (opcode->comp_suffix != 0)
6143 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6144 opcode->comp_suffix);
6147 inst.instruction |= COND_ALWAYS;
6148 (*opcode->parms)(q, 0);
6154 /* Now check for a conditional */
6158 CONST struct asm_cond *cond;
6162 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6166 if (cond->value == 0xf0000000)
6168 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6170 inst.instruction |= cond->value;
6174 inst.instruction |= COND_ALWAYS;
6177 inst.instruction |= COND_ALWAYS;
6179 /* if there is a compulsory suffix, it should come here, before
6180 any optional flags. */
6181 if (opcode->comp_suffix)
6183 CONST char *s = opcode->comp_suffix;
6195 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6196 opcode->comp_suffix);
6203 /* The remainder, if any should now be flags for the instruction;
6204 Scan these checking each one found with the opcode. */
6208 CONST struct asm_flg *flag = opcode->flags;
6217 for (flagno = 0; flag[flagno].template; flagno++)
6219 if (streq (r, flag[flagno].template))
6221 flag_bits |= flag[flagno].set_bits;
6227 if (! flag[flagno].template)
6234 (*opcode->parms) (p, flag_bits);
6244 /* It wasn't an instruction, but it might be a register alias of the form
6254 if (*q && !strncmp (q, ".req ", 4))
6257 char * copy_of_str = str;
6264 for (r = q; *r != '\0'; r++)
6274 regnum = arm_reg_parse (& q);
6277 reg = arm_reg_parse (& str);
6283 insert_reg_alias (str, regnum);
6287 as_warn (_("register '%s' does not exist\n"), q);
6290 else if (regnum != FAIL)
6293 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str );
6295 /* Do not warn abpout redefinitions to the same alias. */
6298 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6302 as_warn (_("ignoring incomplete .req pseuso op"));
6309 as_bad (_("bad instruction `%s'"), start);
6314 * Invocation line includes a switch not recognized by the base assembler.
6315 * See if it's a processor-specific option. These are:
6316 * Cpu variants, the arm part is optional:
6317 * -m[arm]1 Currently not supported.
6318 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6319 * -m[arm]3 Arm 3 processor
6320 * -m[arm]6[xx], Arm 6 processors
6321 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6322 * -m[arm]8[10] Arm 8 processors
6323 * -m[arm]9[20][tdmi] Arm 9 processors
6324 * -mstrongarm[110[0]] StrongARM processors
6325 * -m[arm]v[2345] Arm architecures
6326 * -mall All (except the ARM1)
6328 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6329 * -mfpe-old (No float load/store multiples)
6330 * -mno-fpu Disable all floating point instructions
6331 * Run-time endian selection:
6332 * -EB big endian cpu
6333 * -EL little endian cpu
6334 * ARM Procedure Calling Standard:
6335 * -mapcs-32 32 bit APCS
6336 * -mapcs-26 26 bit APCS
6337 * -mapcs-float Pass floats in float regs
6338 * -mapcs-reentrant Position independent code
6339 * -mthumb-interwork Code supports Arm/Thumb interworking
6340 * -moabi Old ELF ABI
6343 CONST char * md_shortopts = "m:k";
6344 struct option md_longopts[] =
6346 #ifdef ARM_BI_ENDIAN
6347 #define OPTION_EB (OPTION_MD_BASE + 0)
6348 {"EB", no_argument, NULL, OPTION_EB},
6349 #define OPTION_EL (OPTION_MD_BASE + 1)
6350 {"EL", no_argument, NULL, OPTION_EL},
6352 #define OPTION_OABI (OPTION_MD_BASE +2)
6353 {"oabi", no_argument, NULL, OPTION_OABI},
6356 {NULL, no_argument, NULL, 0}
6358 size_t md_longopts_size = sizeof (md_longopts);
6361 md_parse_option (c, arg)
6369 #ifdef ARM_BI_ENDIAN
6371 target_big_endian = 1;
6374 target_big_endian = 0;
6382 if (streq (str, "fpa10"))
6383 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6384 else if (streq (str, "fpa11"))
6385 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6386 else if (streq (str, "fpe-old"))
6387 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6393 if (streq (str, "no-fpu"))
6394 cpu_variant &= ~FPU_ALL;
6399 if (streq (str, "oabi"))
6405 /* Limit assembler to generating only Thumb instructions: */
6406 if (streq (str, "thumb"))
6408 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6409 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6412 else if (streq (str, "thumb-interwork"))
6414 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCH_V4;
6415 #if defined OBJ_COFF || defined OBJ_ELF
6416 support_interwork = true;
6424 if (streq (str, "all"))
6426 cpu_variant = ARM_ALL | FPU_ALL;
6429 #if defined OBJ_COFF || defined OBJ_ELF
6430 if (! strncmp (str, "apcs-", 5))
6432 /* GCC passes on all command line options starting "-mapcs-..."
6433 to us, so we must parse them here. */
6437 if (streq (str, "32"))
6439 uses_apcs_26 = false;
6442 else if (streq (str, "26"))
6444 uses_apcs_26 = true;
6447 else if (streq (str, "frame"))
6449 /* Stack frames are being generated - does not affect
6453 else if (streq (str, "stack-check"))
6455 /* Stack checking is being performed - does not affect
6456 linkage, but does require that the functions
6457 __rt_stkovf_split_small and __rt_stkovf_split_big be
6458 present in the final link. */
6462 else if (streq (str, "float"))
6464 /* Floating point arguments are being passed in the floating
6465 point registers. This does affect linking, since this
6466 version of the APCS is incompatible with the version that
6467 passes floating points in the integer registers. */
6469 uses_apcs_float = true;
6472 else if (streq (str, "reentrant"))
6474 /* Reentrant code has been generated. This does affect
6475 linking, since there is no point in linking reentrant/
6476 position independent code with absolute position code. */
6481 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6485 /* Strip off optional "arm" */
6486 if (! strncmp (str, "arm", 3))
6492 if (streq (str, "1"))
6493 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6499 if (streq (str, "2"))
6500 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6501 else if (streq (str, "250"))
6502 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6508 if (streq (str, "3"))
6509 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6515 switch (strtol (str, NULL, 10))
6522 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6530 switch (strtol (str, & str, 10)) /* Eat the processor name */
6542 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6548 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6552 cpu_variant |= ARM_LONGMUL;
6555 case 'f': /* fe => fp enabled cpu. */
6561 case 'c': /* Left over from 710c processor name. */
6562 case 'd': /* Debug */
6563 case 'i': /* Embedded ICE */
6564 /* Included for completeness in ARM processor naming. */
6574 if (streq (str, "8") || streq (str, "810"))
6575 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6581 if (streq (str, "9"))
6582 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6583 else if (streq (str, "920"))
6584 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6585 else if (streq (str, "920t"))
6586 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6587 else if (streq (str, "9tdmi"))
6588 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6594 if (streq (str, "strongarm")
6595 || streq (str, "strongarm110")
6596 || streq (str, "strongarm1100"))
6597 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6603 /* Select variant based on architecture rather than processor */
6609 case 'a': cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; break;
6610 case 0: cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; break;
6611 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6616 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6620 case 'm': cpu_variant |= ARM_LONGMUL; break;
6622 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6627 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6631 case 't': cpu_variant |= ARM_THUMB; break;
6633 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6638 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6642 case 't': cpu_variant |= ARM_THUMB; break;
6644 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6649 as_bad (_("Invalid architecture variant -m%s"), arg);
6656 as_bad (_("Invalid processor variant -m%s"), arg);
6679 ARM Specific Assembler Options:\n\
6680 -m[arm][<processor name>] select processor variant\n\
6681 -m[arm]v[2|2a|3|3m|4|4t|5]select architecture variant\n\
6682 -mthumb only allow Thumb instructions\n\
6683 -mthumb-interwork mark the assembled code as supporting interworking\n\
6684 -mall allow any instruction\n\
6685 -mfpa10, -mfpa11 select floating point architecture\n\
6686 -mfpe-old don't allow floating-point multiple instructions\n\
6687 -mno-fpu don't allow any floating-point instructions.\n"));
6690 -k generate PIC code.\n"));
6691 #if defined OBJ_COFF || defined OBJ_ELF
6694 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n"));
6697 -mapcs-float floating point args are passed in FP regs\n"));
6700 -mapcs-reentrant the code is position independent/reentrant\n"));
6705 -moabi support the old ELF ABI\n"));
6707 #ifdef ARM_BI_ENDIAN
6710 -EB assemble code for a big endian cpu\n\
6711 -EL assemble code for a little endian cpu\n"));
6715 /* We need to be able to fix up arbitrary expressions in some statements.
6716 This is so that we can handle symbols that are an arbitrary distance from
6717 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6718 which returns part of an address in a form which will be valid for
6719 a data instruction. We do this by pushing the expression into a symbol
6720 in the expr_section, and creating a fix for that. */
6723 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6732 arm_fix_data * arm_data;
6740 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6744 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6749 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6750 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6751 new_fix->tc_fix_data = (PTR) arm_data;
6752 arm_data->thumb_mode = thumb_mode;
6759 * This fix_new is called by cons via TC_CONS_FIX_NEW
6761 * We check the expression to see if it is of the form
6762 * __GLOBAL_OFFSET_TABLE + ???
6763 * If it is then this is a PC relative reference to the GOT.
6770 * .word __GLOBAL_OFFSET_TABLE + (. - (L2 + 4))
6772 * In this case use a reloc type BFD_RELOC_ARM_GOTPC instead of the
6773 * normal BFD_RELOC_{16,32,64}
6777 cons_fix_new_arm (frag, where, size, exp)
6783 bfd_reloc_code_real_type type;
6788 * @@ Should look at CPU word size.
6793 type = BFD_RELOC_16;
6797 type = BFD_RELOC_32;
6800 type = BFD_RELOC_64;
6804 /* Look for possible GOTPC reloc */
6807 * Look for pic assembler and 'undef symbol + expr symbol' expression
6808 * and a 32 bit size.
6811 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6814 /* A good place to do this, although this was probably not intended
6815 * for this kind of use. We need to dump the literal pool before
6816 * references are made to a null symbol pointer. */
6820 if (current_poolP != NULL)
6822 subseg_set (text_section, 0); /* Put it at the end of text section */
6824 listing_prev_line ();
6829 arm_start_line_hook ()
6831 last_label_seen = NULL;
6835 arm_frob_label (sym)
6838 last_label_seen = sym;
6840 ARM_SET_THUMB (sym, thumb_mode);
6842 #if defined OBJ_COFF || defined OBJ_ELF
6843 ARM_SET_INTERWORK (sym, support_interwork);
6846 if (label_is_thumb_function_name)
6848 /* When the address of a Thumb function is taken the bottom
6849 bit of that address should be set. This will allow
6850 interworking between Arm and Thumb functions to work
6853 THUMB_SET_FUNC (sym, 1);
6855 label_is_thumb_function_name = false;
6859 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6863 arm_adjust_symtab ()
6868 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6870 if (ARM_IS_THUMB (sym))
6872 if (THUMB_IS_FUNC (sym))
6874 /* Mark the symbol as a Thumb function. */
6875 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6876 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6877 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6879 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6880 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6882 as_bad (_("%s: unexpected function type: %d"),
6883 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6885 else switch (S_GET_STORAGE_CLASS (sym))
6888 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6891 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6894 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6896 default: /* do nothing */
6901 if (ARM_IS_INTERWORK (sym))
6902 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
6907 elf_symbol_type * elf_sym;
6910 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6912 if (ARM_IS_THUMB (sym))
6914 if (THUMB_IS_FUNC (sym))
6916 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
6917 bind = ELF_ST_BIND (elf_sym);
6918 elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_TFUNC);
6928 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6930 *input_line_pointer = '/';
6931 input_line_pointer += 5;
6932 *input_line_pointer = 0;
6940 arm_canonicalize_symbol_name (name)
6945 if (thumb_mode && (len = strlen (name)) > 5
6946 && streq (name + len - 5, "/data"))
6948 *(name + len - 5) = 0;
6955 arm_validate_fix (fixP)
6958 /* If the destination of the branch is a defined symbol which does not have
6959 the THUMB_FUNC attribute, then we must be calling a function which has
6960 the (interfacearm) attribute. We look for the Thumb entry point to that
6961 function and change the branch to refer to that function instead. */
6962 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
6963 && fixP->fx_addsy != NULL
6964 && S_IS_DEFINED (fixP->fx_addsy)
6965 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6967 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6975 /* Relocations against Thumb function names must be left unadjusted,
6976 so that the linker can use this information to correctly set the
6977 bottom bit of their addresses. The MIPS version of this function
6978 also prevents relocations that are mips-16 specific, but I do not
6979 know why it does this.
6982 There is one other problem that ought to be addressed here, but
6983 which currently is not: Taking the address of a label (rather
6984 than a function) and then later jumping to that address. Such
6985 addresses also ought to have their bottom bit set (assuming that
6986 they reside in Thumb code), but at the moment they will not. */
6989 arm_fix_adjustable (fixP)
6993 if (fixP->fx_addsy == NULL)
6996 /* Prevent all adjustments to global symbols. */
6997 if (S_IS_EXTERN (fixP->fx_addsy))
7000 if (S_IS_WEAK (fixP->fx_addsy))
7003 if (THUMB_IS_FUNC (fixP->fx_addsy)
7004 && fixP->fx_subsy == NULL)
7007 /* We need the symbol name for the VTABLE entries */
7008 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7009 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7016 elf32_arm_target_format ()
7018 if (target_big_endian)
7020 return "elf32-bigarm-oabi";
7022 return "elf32-bigarm";
7025 return "elf32-littlearm-oabi";
7027 return "elf32-littlearm";
7031 armelf_frob_symbol (symp, puntp)
7035 elf_frob_symbol (symp, puntp);
7039 arm_force_relocation (fixp)
7042 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7043 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7044 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
7050 static bfd_reloc_code_real_type
7060 bfd_reloc_code_real_type reloc;
7064 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7065 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7066 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7067 /* ScottB: Jan 30, 1998 */
7068 /* Added support for parsing "var(PLT)" branch instructions */
7069 /* generated by GCC for PLT relocs */
7070 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7071 NULL, 0, BFD_RELOC_UNUSED
7075 for (i = 0, ip = input_line_pointer;
7076 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7078 id[i] = tolower (*ip);
7080 for (i = 0; reloc_map[i].str; i++)
7081 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7084 input_line_pointer += reloc_map[i].len;
7086 return reloc_map[i].reloc;
7090 s_arm_elf_cons (nbytes)
7095 #ifdef md_flush_pending_output
7096 md_flush_pending_output ();
7099 if (is_it_end_of_statement ())
7101 demand_empty_rest_of_line ();
7105 #ifdef md_cons_align
7106 md_cons_align (nbytes);
7111 bfd_reloc_code_real_type reloc;
7115 if (exp.X_op == O_symbol
7116 && * input_line_pointer == '('
7117 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7119 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7120 int size = bfd_get_reloc_size (howto);
7123 as_bad ("%s relocations do not fit in %d bytes", howto->name, nbytes);
7126 register char * p = frag_more ((int) nbytes);
7127 int offset = nbytes - size;
7129 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7134 emit_expr (& exp, (unsigned int) nbytes);
7136 while (*input_line_pointer++ == ',');
7138 input_line_pointer--; /* Put terminator back into stream. */
7139 demand_empty_rest_of_line ();
7142 #endif /* OBJ_ELF */